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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__AND3_FUNCTIONAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_BLACKBOX_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O31AI_FUNCTIONAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_4_V
`define SKY130_FD_SC_HD__NAND2_4_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_SYMBOL_V
`define SKY130_FD_SC_LP__A21O_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_SYMBOL_V
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={8} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP1} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.072, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.024, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.023, PCW_UIPARAM_DDR_BOARD_DELAY0=0.294, PCW_UIPARAM_DDR_BOARD_DELAY1=0.298, PCW_UIPARAM_DDR_BOARD_DELAY2=0.338, PCW_UIPARAM_DDR_BOARD_DELAY3=0.334, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=50.05, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=50.43, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=50.10, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=50.01, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=49.59, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=51.74, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=50.32, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=48.55, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=39.7, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=39.7, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=54.14, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=54.14, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666666, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=111.111115, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=111.111115, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=111.111115, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=100, PCW_FPGA2_PERIPHERAL_FREQMHZ=33.333333, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=1, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=100, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 46, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 50, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=EMIO, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 7, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=1, PCW_I2C1_I2C1_IO=EMIO, PCW_I2C1_GRP_INT_ENABLE=1, PCW_I2C1_GRP_INT_IO=EMIO, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// File name : UniversalCounter.v
// Written by : Jianjian Song
// 4-bit universal bidirectional counter
`timescale 1ns / 1ps
module PosClockedOneShot(InputPulse, OneShot, Reset, CLOCK) ;
input InputPulse, Reset, CLOCK;
output reg OneShot;
parameter State0=0, State1=1, State2=2, State3=3;
reg [1:0] State;
always@(State)
if(State==State1) OneShot<=1;
else OneShot<=0;
always @ (posedge CLOCK)
if(Reset==1) State <= 0; else
case (State)
0: if (InputPulse==0) State<=State0; else State<=State1;
1: if (InputPulse==0) State<=State0; else State<=State3;
2: State<=State0;
3: if (InputPulse==0) State<=State0; else State<=State3;
endcase
endmodule
module NegClockedOneShot(InputPulse, OneShot, Reset, CLOCK) ;
input InputPulse, Reset, CLOCK;
output reg OneShot;
parameter State0=0, State1=1, State2=2, State3=3;
reg [1:0] State;
always@(State)
if(State==State1) OneShot<=0;
else OneShot<=1;
always @ (posedge CLOCK)
if(Reset==1) State <= 0; else
case (State)
0: if (InputPulse==1) State<=State0; else State<=State1;
1: if (InputPulse==1) State<=State0; else State<=State3;
2: State<=State0;
3: if (InputPulse==1) State<=State0; else State<=State3;
endcase
endmodule
|
(** * Prop_J: 命題と根拠 *)
(* $Date: 2011-06-27 09:22:51 -0400 (Mon, 27 Jun 2011) $ *)
(** "アルゴリズムは計算可能な証明である。"(Robert Harper) *)
Require Export Poly_J.
(* ##################################################### *)
(* ##################################################### *)
(** * 命題によるプログラミング *)
(* _Note to readers_: Some of the concepts in this chapter may
seem quite abstract on a first encounter. We've included a _lot_
of exercises, most of which should be quite approachable even if
you're still working on understanding the details of the text.
Try to work as many of them as you can, especially the one-starred
exercises. *)
(** 読者への注意: この章で紹介するコンセプトは、初めて見た時には抽象的すぎるように感じられるかもしれません。
たくさんの練習問題を用意しておいたので、テキストの詳細を理解する途中であっても大部分は解けるはずです。
できるかぎり多くの問題、特に★の問題には重点的に挑戦するようにしてください。 *)
(* So far, the only statements we have been able to state and
prove have been in the form of _equalities_. However, the
language of mathematical statements and proofs is much richer than
this! In this chapter we will take a much closer and more
fundamental look at the sorts of mathematical statements
(_propositions_) we can make in Coq, and how we go about proving
them by providing logical _evidence_. *)
(** これまで宣言したり証明した文は等式の形をしたものだけでした。
しかし、数学で用いられる文や証明にはもっと豊かな表現力があります。
この章では Coq で作れる数学的な文（命題; _proposition_ ）の種類と、その証明を「根拠（ _evidence_ ）を与えること」でどのように進めていくか、もう少し詳しく、基本的な部分から見ていきましょう。
*)
(* A _proposition_ is a statement expressing a factual claim,
like "two plus two equals four." In Coq, propositions are written
as expressions of type [Prop]. Although we haven't mentioned it
explicitly, we have already seen numerous examples. *)
(** 命題（ _proposition_ ）は、"2足す2は4と等しい"のような事実に基づく主張を表現するための文です。
Coq において命題は [Prop] 型の式として書かれます。
これまであまりそれについて明示的に触れてはきませんでしたが、皆さんはすでに多くの例を見てきています。 *)
Check (2 + 2 = 4).
(* ===> 2 + 2 = 4 : Prop *)
Check (ble_nat 3 2 = false).
(* ===> ble_nat 3 2 = false : Prop *)
(* Both provable and unprovable claims are perfectly good
propositions. Simply _being_ a proposition is one thing; being
_provable_ is something else! *)
(** 証明可能な主張も証明不能な主張も、どちらも完全な命題であると言えます。
しかし単に命題であるということと、証明可能であるということは別ものです！ *)
Check (2 + 2 = 5).
(* ===> 2 + 2 = 5 : Prop *)
(** [2 + 2 = 4] も [2 + 2 = 5] も [Prop] の型をもった妥当な式です。 *)
(* We've seen one way that propositions can be used in Coq: in
[Theorem] (and [Lemma] and [Example]) declarations. *)
(** これまで Coq の中で命題を使う方法は1つしか見ていません。 [Theorem]（あるいは [Lemma]、[Example]）の宣言の中でだけです。 *)
Theorem plus_2_2_is_4 :
2 + 2 = 4.
Proof. reflexivity. Qed.
(* But they can be used in many other ways. For example, we
can give a name to a proposition using a [Definition], just as we
have given names to expressions of other sorts (numbers,
functions, types, type functions, ...). *)
(** しかし命題にはもっといろいろな使い方があります。
例えば、他の種類の式（数字、関数、型、型関数など）と同様に、[Definition] を使うことで命題に名前を与えることができます。 *)
Definition plus_fact : Prop := 2 + 2 = 4.
Check plus_fact.
(* ===> plus_fact : Prop *)
(* Now we can use this name in any situation where a proposition is
expected -- for example, as the claim in a [Theorem]
declaration. *)
(** こうすることで、命題が使える場所ならどこでも、例えば、[Theorem] 宣言内の主張などとして使うことができます。 *)
Theorem plus_fact_is_true :
plus_fact.
Proof. reflexivity. Qed.
(* So far, all the propositions we have seen are equality
propositions. We can also form new propositions out of old
ones. For example, given propositions [P] and [Q], we can form
the proposition "[P] implies [Q]." *)
(** ここまでに登場したすべての命題は等式の形をした命題でした。
それ以外にも新しい命題の形を作ることができます。
例えば、命題 [P] と [Q] が与えられば、" [P] ならば [Q] "という命題を作れます。
*)
Definition strange_prop1 : Prop :=
(2 + 2 = 5) -> (99 + 26 = 42).
(* Also, given a proposition [P] with a free variable [n], we can
form the proposition [forall n, P]. *)
(** また、自由変数[n]を含む命題 [P] が与えられれば、[forall n, P] という形の命題を作れます。 *)
Definition strange_prop2 :=
forall n, (ble_nat n 17 = true) -> (ble_nat n 99 = true).
(* Finally, we can define _parameterized propositions_. For
example, what does it mean to claim that "a number n is even"? We
have written a function that tests evenness, so one possible
definition of what it means to be even is "[n] is even iff [evenb
n = true]." *)
(** 最後に、パラメータ化された命題（_parameterized proposition_ ）の定義を紹介します。
例えば、"数nが偶数である"という主張はどのようになるでしょうか？
偶数を判定する関数は書いてあるので、偶数であるという定義は" [n] が偶数であることと [evenb n = true] は同値である"が考えられます。 *)
Definition even (n:nat) : Prop :=
evenb n = true.
(* This defines [even] as a _function_ that, when applied to a number
[n], _yields a proposition_ asserting that [n] is even. *)
(** これは [even] を関数として定義します。
この関数は数 [n] を適用されると、[n] が偶数であることを示す命題を返します。 *)
Check even.
(* ===> even : nat -> Prop *)
Check (even 4).
(* ===> even 4 : Prop *)
Check (even 3).
(* ===> even 3 : Prop *)
Check strange_prop2.
(* The type of [even], [nat->Prop], can be pronounced in three
ways: (1) "[even] is a _function_ from numbers to
propositions," (2) "[even] is a _family_ of propositions, indexed
by a number [n]," or (3) "[even] is a _property_ of numbers." *)
(** [even]の型 [nat -> Prop]は3つの意味を持っています。
(1) "[even]は数から命題への関数である。"
(2) "[even]は数[n]でインデックスされた命題の集りである"。 <= コロン:の右側をインデックスという理由
(3) "[even]は数の性質(_property_)である。" *)
(* Propositions -- including parameterized propositions -- are
first-class citizens in Coq. We can use them in other
definitions: *)
(** 命題（パラメータ化された命題も含む）はCoqにおける第一級（_first-class_）市民です。
このため、ほかの定義の中でこれらの命題を使うことができます。 *)
Definition even_n__even_SSn (n:nat) : Prop :=
(even n) -> (even (S (S n))).
Check even_n__even_SSn.
Check (even_n__even_SSn 4).
(* We can define them to take multiple arguments... *)
(** 複数の引数を受け取るように定義することや.. *)
Definition between (n m o: nat) : Prop :=
andb (ble_nat n o) (ble_nat o m) = true.
Check between.
Check (between 2 4 4).
(* ... and then partially apply them: *)
(** ...部分適用もできます。 *)
Definition teen : nat->Prop := between 13 19.
(* We can even pass propositions -- including parameterized
propositions -- as arguments to functions: *)
(** 他の関数に、引数として命題（パラーメータ化された命題も含む）を渡すことすらできます。 *)
Definition true_for_zero (P:nat->Prop) : Prop :=
P 0.
Definition true_for_n__true_for_Sn (P:nat->Prop) (n:nat) : Prop :=
P n -> P (S n).
(* (Names of the form [x__y], with two underscores in a row, can be
read "[x] implies [y].") *)
(** 2つのアンダースコアを続けた [x__y] という形式の名前は、" [x] ならば [y] である"と読みます。 *)
(* Here are two more examples of passing parameterized
propositions as arguments to a function. The first makes the
claim that a whenever a proposition [P] is true for some natural
number [n'], it is also true by the successor of [n']: *)
(** パラメータ化された命題を引数として渡す関数をさらに2つ紹介します。
1つ目の関数は、ある自然数 [n'] について [P] が真ならば常に [n'] の次の数でも [P] が真であることを述べています。
*)
Definition preserved_by_S (P:nat->Prop) : Prop :=
forall n', P n' -> P (S n').
(* P n' のとき成り立つ性質が P (S n') においても保存されている *)
(* And this one simply claims that a proposition is true for
all natural numbers: *)
(** そして次の関数は、すべての自然数について与えられた命題が真であることを述べています。 *)
Definition true_for_all_numbers (P:nat->Prop) : Prop :=
forall n, P n.
(* We can put these pieces together to manually restate the
principle of induction for natural numbers. Given a parameterized
proposition [P], if [P] is true for [0], and [P (S n')] is true
whenever [P n'] is, then [P] is true for all natural numbers. *)
(** これらを一つにまとめることで、自然数に関する帰納法の原理を自分で再宣言できます。
パラメータ化された命題 [P] が与えられた場合、[0] について [P] が真であり、[P n'] が真のとき [P (S n')] が真であるならば、すべての自然数について [P] は真である。
*)
Definition our_nat_induction (P:nat->Prop) : Prop :=
(true_for_zero P) ->
(preserved_by_S P) ->
(true_for_all_numbers P).
(* (yuga) このように定義したからといって帰納法を証明したことにはならない。
Coqは帰納法を公理として認めているシステム。
でも正則帰納法を自分で定義して使ったりできる。
*)
(* * Evidence *)
(** * 根拠 *)
(* We've seen that well-formed expressions of type [Prop] can
embody both provable and unprovable propositions. Naturally,
we're particularly interested in the provable ones. When [P] is a
proposition and [e] is a proof of [P] -- i.e., [e] is evidence
that [P] is true -- we'll write "[e : P]." This overloading of
the "has type" or "inhabits" notation is not accidental: we'll see
that there is a fundamental and fruitful analogy between data
values inhabiting types and evidence "inhabiting" propositions. *)
(** [Prop]型として妥当な式には証明可能な命題と証明不能な命題の両方があることは既にお話ししました。
当然、証明可能なものの方に興味が向かいます。
[P] が命題であり [e] が [P] の証明である場合、すなわち [e] が「 [P] が真である」ということの根拠となっている場合、それを" [e : P] "と書くことができます。
"型を持っている"や"属している"を表わす記法と同じなのは決して偶然ではありません。
型に属する値と命題に"属する"根拠の間には根本的で有益な類似性があるのです。 *)
(* The next question is "what are proofs?" -- i.e., what sorts of
things would we be willing to accept as evidence that particular
propositions are true? *)
(** 次の疑問は"証明とはなにか？"です。
すなわち、ある命題が真であるという根拠として使えるものは、どのようなものでしょうか？ *)
(* ##################################################### *)
(* ** Inductively Defined Propositions *)
(** ** 帰納的に定義された命題 *)
(* The answer, of course, depends on the form of the
proposition -- evidence for implication propositions ([P->Q]) is
different from evidence for conjunctions ([P/\Q]), etc. In this
chapter and the next, we'll address a number of specific cases.
To begin with, consider _atomic_ propositions -- ones that aren't
built into the logic we're using, but are rather introduced to
model useful concepts in a particular domain. For example, having
defined a type [day] as we did in Basics.v, we might have some
concept in our minds about certain days, say the fact that
[saturday] and [sunday] are "good" ones. If we want to use Coq to
state and prove theorems involving good days, we need to begin by
telling it what we mean by "good" -- that is, we need to specify
what counts as as evidence that some day [d] is good (namely, that
[d] is either [saturday] or [sunday]. The following declaration
achieves this: *)
(** もちろん、その答は命題の形に依存します。
例えば、含意の命題 [P->Q] に対する根拠と連言の命題 [P/\Q] に対する根拠は異なります。
この章では以後、たくさんの具体的な例を示します。
まずは、不可分（ _atomic_ ）な命題を考えましょう。
それは私達が使っている論理にあらかじめ組み込まれているものはなく、特定のドメイン（領域）に有用な概念を導入するものです。
例えば、Basic_J.v で [day] 型を定義したので、[saturday] と [sunday] は"良い"日であるといったような、特定の日に対して何らかの概念を考えてみましょう。
良い日に関する定理を宣言し証明したい場合はまず、"良い"とはどういう意味かをCoqに教えなければなりません。
ある日 [d] が良い（すなわち [d] が [saturday] か [sunday] である）とする根拠として何を使うかを決める必要があります。
このためには次のように宣言します。 *)
Inductive good_day : day -> Prop :=
| gd_sat : good_day saturday
| gd_sun : good_day sunday.
(* (yuga) 値 saturday と sunday が型に持ち上がっている *)
(* The [Inductive] keyword means exactly the same thing whether
we are using it to define sets of data values (in the [Type]
world) or sets of evidence (in the [Prop] world). Consider the
parts of the definition above:
- The first line declares that [good_day] is a proposition indexed
by a day.
- The second line declares that the constructor [gd_sat] can be
taken as evidence for the assertion [good_day saturday].
- The third line declares that the constructor [gd_sun] can be
taken as evidence for the assertion [good_day sunday]. *)
(** [Inductive] キーワードは、「データ値の集合を定義する場合( [Type] の世界)」であっても「根拠の集合を定義する場合( [Prop] の世界)」であってもまったく同じ意味で使われます。
上記の定義の意味はそれぞれ次のようになっています:
- 最初の行は「 [good_day] は日によってインデックスされた命題であること」を宣言しています。
- 二行目は [gd_sat] コンストラクタを宣言しています。このコンストラクタは [good_day saturday] という主張の根拠として使えます。
- 三行目は [gd_sun] コンストラクタを宣言しています。このコンストラクタは [good_day sunday] という主張の根拠として使えます。
*)
(* (yuga) 新たに公理を作成したことになる *)
(* That is, we're _defining_ what we mean by days being good by
saying "Saturday is good, sunday is good, and that's all." Then
someone can _prove_ that Sunday is good simply by observing that
we said it was when we defined what [good_day] meant. *)
(** 言い換えると、ある日が良いということを"土曜日は良い、日曜日は良い、それだけだ"と言うことで定義しています。
これによって、日曜日が良いということを証明したいときは、[good_day] の意味を定義したときにそう言っていたかを調べるだけで済みます。 *)
Theorem gds : good_day sunday.
Proof. apply gd_sun. Qed.
Check gd_sun.
Check (good_day sunday).
(* The constructor [gd_sun] is "primitive evidence" -- an _axiom_ --
justifying the claim that Sunday is good. *)
(** コンストラクタ [gd_sun] は、日曜日が良いという主張を正当化する"原始的（primitive）な根拠"、つまり公理です。*)
(* Similarly, we can define a proposition [day_before]
parameterized by _two_ days, together with axioms stating that
Monday comes before Tuesday, Tuesday before Wednesday, and so
on. *)
(** 同様に、月曜日は火曜日の前に来て、火曜日は水曜日の前に来て、...、ということを宣言する公理を、2つの日をパラメータとして取る命題 [day_before] として定義できます。*)
Inductive day_before : day -> day -> Prop :=
| db_tue : day_before tuesday monday
| db_wed : day_before wednesday tuesday
| db_thu : day_before thursday wednesday
| db_fri : day_before friday thursday
| db_sat : day_before saturday friday
| db_sun : day_before sunday saturday
| db_mon : day_before monday sunday.
(* The axioms that we introduce along with an inductively
defined proposition can also involve universal quantifiers. For
example, it is well known that every day is a fine day forsinging a song: *)
(** 帰納的な定義による命題で導入される公理では全称記号を使うこともできます。
例えば、「どの日だって歌いだしたくなるほど素敵な日だ」という事実については、
わざわざ説明する必要もないでしょう *)
Inductive fine_day_for_singing : day -> Prop :=
| fdfs_any : forall d:day, fine_day_for_singing d.
(* The line above declares that, if [d] is a day, then [fdfs_any d]
can be taken as evidence for [fine_day_for_singing d]. That is,
we can construct evidence that [d] is a [fine_day_for_singing]
by applying the constructor [fdfs_any] to [d].
In particular, Wednesday is a fine day for singing. *)
(** この行は、もし [d] が日ならば、[fdfs_any d] は [fine_day_for_singing d] の根拠として使えるということを宣言してます。
言い換えると、[d] が [fine_day_for_singing] であるという根拠を [fdfs_any] を [d] に適用することで作ることができます。
要するに、水曜日は「歌いだしたくなるほど素敵な日」だということです。
*)
Check day_before.
Check db_tue.
Check fine_day_for_singing.
Theorem fdfs_wed : fine_day_for_singing wednesday.
Proof. apply fdfs_any. Qed.
(* As always, the first line here can be read "I'm about to
show you some evidence for the proposition [fine_day_for_singing
wednesday], and I want to introduce the name [fdfs_wed] to refer
to that evidence later on." The second line then instructs Coq
how to assemble the evidence. *)
(** これも同じように、最初の行は"私は命題 [fine_day_for_singing wednesday] に対する根拠を示し、その根拠をあとで参照するために [fdfs_wed] という名前を導入しようと思っている"と解釈できます。
二行目は、Coqにその根拠をどのように組み立てるかを示しています。 *)
(* 2014-02-01 #4 ここまで *)
(* 2014-03-xx #5 ここから *)
(* ##################################################### *)
(* ** Proof Objects *)
(** ** 証明オブジェクト *)
(* There's another -- more primitive -- way to accomplish the
same thing: we can use a [Definition] whose left-hand side is the
name we're introducing and whose right-hand side is the evidence
_itself_, rather than a script for how to build it. *)
(** 同じことができる、もっと原始的な方法もあります。
[Definiton] の左辺を導入しようとしている名前にし、右辺を根拠の構築方法ではなく、根拠そのものにすればいいのです。 *)
Definition fdfs_wed' : fine_day_for_singing wednesday :=
fdfs_any wednesday.
Check fdfs_wed.
Check fdfs_wed'.
(* The expression [fdfs_any wednesday] can be thought of as
instantiating the parameterized axiom [fdfs_any] with the specific
argument [wednesday]. Alternatively, we can think of [fdfs_any]
as a primitive "evidence constructor" that, when applied to a
particular day, stands as evidence that that day is a fine day for
singing; its type, [forall d:day, fine_day_for_singing d],
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] in the previous chapter expressed the fact
that the constructor [nil] can be thought of as a function from
types to empty lists with elements of that type. *)
(** 式 [fdfs_any wednesday] は、パラメータを受け取る公理 [fdfs_any]を 特定の引数 [wednesday] によって具体化したものととらえることができます。
別の見方をすれば、[fdfs_any] を原始的な"根拠コンストラクタ"として捉えることもできます。この根拠コンストラクタは、特定の日を適用されると、その日が「歌わずにはいられないほどよい日」である根拠を表します。
型 [forall d:day, fine_day_for_singing d] はこの機能を表しています。
これは、前章で登場した多相型 [forall X, list X] において [nil] コンストラクタが型からその型を持つ空リストを返す関数であったことと同様です。 *)
(* Let's take a slightly more interesting example. Let's say
that a day of the week is "ok" if either (1) it is a good day or
else (2) it falls the day before an ok day. *)
(** もうちょっと面白い例を見てみましょう。
"OK"な日とは(1)良い日であるか(2)OKな日の前日であるとしましょう。*)
Inductive ok_day : day -> Prop :=
| okd_gd : forall d,
good_day d ->
ok_day d
| okd_before : forall d1 d2,
ok_day d2 ->
day_before d2 d1 ->
ok_day d1.
(* The first constructor can be read "One way to show that [d]
is an ok day is to present evidence that [d] is good." The second
can be read, "Another way to show that a day [d1] is ok is to
present evidence that it is the day before some other day [d2]
together with evidence that [d2] is ok." *)
(** 最初のコンストラクタは"[d]がOKな日であることを示す一つ目の方法は、[d]が良い日であるという根拠を示すことである"と読めます。
二番目のは"[d1]がOKであることを示す別の方法は、その日が別の日 [d2] の前日であり、[d2]がOKであるという根拠を示すことである"と読めます。 *)
(* Now suppose that we want to prove that [wednesday] is ok.
There are two ways to do it. First, we have the primitive way,
where we simply write down an expression that has the right
type -- a big nested application of constructors: *)
(** ここで [wednesday] がOKであることを証明したいとしましょう。
証明するには2つの方法があります
1つめは原始的な方法であり、コンストラクタの適用を何度もネストすることで、
正しい型を持つ式を書き下します。 *)
Definition okdw : ok_day wednesday :=
okd_before wednesday thursday
(okd_before thursday friday
(okd_before friday saturday
(okd_gd saturday gd_sat)
db_sat)
db_fri)
db_thu.
(* Second, we have the machine-assisted way, where we go into [Proof]
mode and Coq guides us through a series of goals and subgoals
until it is finally satisfied: *)
(** 2つめの方法は、機械に支援してもらう方法です。証明モードに入り、最終的に満たされるまでゴールやサブゴールを通してCoqに案内してもらいます。 *)
Theorem okdw' : ok_day wednesday.
Proof.
(* wednesday is OK because it's the day before an OK day *)
apply okd_before with (d2:=thursday).
(* "subgoal: show that thursday is ok". *)
(* thursday is OK because it's the day before an OK day *)
apply okd_before with (d2:=friday).
(* "subgoal: show that friday is ok". *)
(* friday is OK because it's the day before an OK day *)
apply okd_before with (d2:=saturday).
(* "subgoal: show that saturday is ok". *)
(* saturday is OK because it's good! *)
apply okd_gd. apply gd_sat.
(* "subgoal: show that the day before saturday is friday". *)
apply db_sat.
(* "subgoal: show that the day before friday is thursday". *)
apply db_fri.
(* "subgoal: show that the day before thursday is wednesday". *)
apply db_thu. Qed.
(* Fundamentally, though, these two ways of making proofs are the
same, in the sense that what Coq is actually doing when it's
following the commands in a [Proof] script is _literally_
attempting to construct an expression with the desired type. *)
(** しかし、根本的なところでこの2つの証明方法は同じです。
証明スクリプト内のコマンドを実行するときにCoqが実際にやっていることは、目的の型を持つ式を構築することと全く同じです。
*)
Print okdw'.
(* ===> okdw' = okd_before wednesday thursday
(okd_before thursday friday
(okd_before friday saturday
(okd_gd saturday gd_sat) db_sat)
db_fri)
db_thu
: ok_day wednesday *)
(* These expressions are often called _proof objects_. *)
(** この式は一般的に証明オブジェクト（Proof object）と呼ばれます。 *)
(* Proof objects are the bedrock of Coq. Tactic proofs are
essentially _programs_ that instruct Coq how to construct proof
objects for us instead of our writing them out explicitly. Here,
of course, the proof object is actually shorter than the tactic
proof. But the proof objects for more interesting proofs can
become quite large and complex -- building them by hand would be
painful. Moreover, we'll see later on in the course that Coq has
a number of automation tactics that can construct quite complex
proof objects without our needing to specify every step. *)
(** 証明オジェクトはCoqの根本を支えています。
タクティックによる証明は、自分で証明オブジェクトを書く代わりに、証明オブジェクトを構築する方法をCoqに指示する基本的なプログラムです。
もちろん、この例では証明オブジェクトはタクティックによる証明よりも短くなっています。
しかし、もっと興味深い証明では証明オブジェクトを手で構築することが苦痛に思えるほど大きく複雑になります。
この後の章では、各ステップを書くことなく複雑な証明オブジェクトを構築できる自動化されたタクティックをたくさん紹介します。 *)
(* ##################################################### *)
(* ** The Curry-Howard Correspondence *)
(** ** カリー・ハワード対応 *)
(* The analogy
<<
propositions ~ sets / types
proofs ~ data values
>>
is called the _Curry-Howard correspondence_ (or _Curry-Howard
isomorphism_). Many wonderful things follow from it. *)
(** この
<<
命題 ~ 集合 / 型
証明 ~ 元、要素 / データ値
>>
という類似性は、カリー・ハワード対応（もしくはカリー・ハワード同型, Curry-Howard correspondence, Curry-Howard isomorphism）と呼ばれます。
これにより多くのおもしろい性質が導けます。
*)
(* Just as a set can be empty, a singleton, finite, or infinite -- it
can have zero, one, or many inhabitants -- a proposition may be
inhabited by zero, one, many, or infinitely many proofs. Each
inhabitant of a proposition [P] is a different way of giving
evidence for [P]. If there are none, then [P] is not provable.
If there are many, then [P] has many different proofs. *)
(** 集合に空集合、単集合、有限集合、無限集合があり、それぞれが0個、1個、多数の元を持っているように、命題も0個、1個、多数、無限の証明を持ちえます。
命題 [P] の各要素は、それぞれ異なる [P] の根拠です。
もし要素がないならば、[P] は証明不能です。
もしたくさんの要素があるならば、[P] には多数の異なった証明があります。 *)
(* ##################################################### *)
(* ** Implication *)
(** ** 含意 *)
(* We've seen that the [->] operator (implication) builds bigger
propositions from smaller ones. What constitutes evidence for
propositions built in this way? Consider this statement: *)
(** これまで [->] 演算子(含意)を小さい命題から大きな命題を作るために使ってきました。
このような命題に対する根拠はどのようになるでしょうか?
次の文を考えてみてください。 *)
Definition okd_before2 := forall d1 d2 d3,
ok_day d3 ->
day_before d2 d1 ->
day_before d3 d2 ->
ok_day d1.
(* In English: if we have three days, [d1] which is before [d2]
which is before [d3], and if we know [d3] is ok, then so is
[d1].
It should be easy to see how we'd construct a tactic proof of
[okd_before2]... *)
(** これを日本語で書くと、もし3つの日があるとして、[d1] が [d2] の前日であり、[d2] が [d3] の前日であり、かつ [d3] がOKであるということがわかっているならば、[d1] もOKである、という意味になります。
[okd_before2] をタクティッックを使って証明するのは簡単なはずです... *)
(* **** Exercise: 1 star, optional (okd_before2_valid) *)
(** **** 練習問題: ★, optional (okd_before2_valid) *)
Theorem okd_before2_valid : okd_before2.
Proof.
unfold okd_before2.
intros d1 d2 d3 H H0 H1.
(* d1がok_dayであるにはokな日の前日であることを示す *)
apply (okd_before d1 d2).
apply (okd_before d2 d3).
apply H.
apply H1.
apply H0.
Qed.
(** [] *)
(* But what should the corresponding proof object look like?
Answer: We've made a notational pun between [->] as implication
and [->] as the type of functions. If we take this pun seriously,
then what we're looking for is an expression with _type_ [forall
d1 d2 d3, ok_day d3 -> day_before d2 d1 -> day_before d3 d2 ->
ok_day d1], and so what we want is a _function_ that takes six
arguments (three days and three pieces of evidence) and returns a
piece of evidence! Here it is: *)
(** ところで、これに対応する証明オブジェクトはどんな感じでしょうか?
答: 含意としての [->] と、関数の型の [->] の記法はそっくりです。
これをそのまま解釈すると、[forall d1 d2 d3, ok_day d3 -> day_before d2 d1 -> day_before d3 d2 -> ok_day d1] という型をもった式を見付ける必要があります。
なので探すものは6個の引数(3個の日と、3個の根拠)を受け取り、1個の根拠を返す関数です!
それはこんな感じです。
*)
Definition okd_before2_valid' : okd_before2 :=
fun (d1 d2 d3 : day) =>
fun (H : ok_day d3) =>
fun (H0 : day_before d2 d1) =>
fun (H1 : day_before d3 d2) =>
okd_before d1 d2 (okd_before d2 d3 H H1) H0.
(* **** Exercise: 1 star, optional (okd_before2_valid_defn) *)
(** **** 練習問題: ★, optional (okd_before2_valid_defn) *)
(* Predict what Coq will print in response to this: *)
(** 下記の結果としてCoqが出力するものを予測しなさい。 *)
(*
Inductive ok_day : day -> Prop :=
| okd_gd : forall d,
good_day d ->
ok_day d
| okd_before : forall d1 d2,
ok_day d2 ->
day_before d2 d1 ->
ok_day d1.
Definition okd_before2_valid =
fun (d1 d2 d3 day) (H : ok_day d3) (H0 : day_before d2 d1) (H1 : day_before d3 d2) =>
okd_before d1 d2 (okd_before d2 d3) H H1 H0
*)
Print okd_before2_valid.
(* ##################################################### *)
(* パラメータとインデックス *)
Inductive Foo (X : Type) : Type -> Prop :=
(* ^ Parameter ^ Index *)
| Foo0 : Foo X nat.
Inductive T0 : Type -> Type -> Prop :=
(* ^ Index ^ Index *)
| D0 : T0 nat nat.
Inductive T1 (X : Type) : Type -> Prop :=
| D1 : T1 X nat.
(* | D1 : T1 X X. *)
(* | D1 : T1 nat nat. *)
Inductive T2 (X Y : Type) : Prop :=
| D2 : T2 X Y.
(*
T0_ind :
forall P : Type -> Type -> Prop,
P nat nat ->
forall T T1 : Type, T0 T T1 ->
P T T1.
T1_ind :
forall (X : Type) (P : Type -> Prop),
P nat ->
forall T : Type, T1 X T ->
P T.
T2_ind :
forall (X Y : Type) (P : Prop),
P ->
T2 X Y ->
P.
*)
Check T0_ind.
Check T1_ind.
Check T2_ind.
(* ##################################################### *)
(* ** Induction Principles for Inductively Defined Types *)
(** ** 帰納的に定義された型に対する帰納法の原理 *)
(* Every time we declare a new [Inductive] datatype, Coq
automatically generates an axiom that embodies an _induction
principle_ for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
(** [Inductive] でデータ型を新たに定義するたびに、Coqは帰納法の原理に対応する公理を自動生成します。
型[t]に対応する帰納法の原理は[t_ind]という名前になります。
ここでは自然数に対するものを示します。 *)
Check nat_ind.
(* ===> nat_ind : forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(* Note that this is exactly the [our_nat_induction] property from
above. *)
(** これは先ほど定義した [our_nat_induction] の性質とまったく同じであることに注意してください。 *)
(* The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
(** [induction] タクティックは、基本的には [apply t_ind] の単純なラッパーです。
もっとわかりやすくするために、[induction] タクティックのかわりに [apply nat_ind] を使っていくつかの証明をしてみる実験をしてみましょう。
例えば、[Basics_J] の章で見た定理の別の証明を見てみましょう。 *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
Case "O". reflexivity.
Case "S". simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(* This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** この証明は基本的には前述のものと同じですが、細かい点で特筆すべき違いがあります。
1つめは、帰納段階の証明（["S"] の場合）において、[induction] が自動でやってくれること（[intros]）を手作業で行なう必要があることです。
2つめは、[nat_ind] を適用する前にコンテキストに [n] を導入していないことです。
[nat_ind] の結論は限量子を含む式であり、[apply] で使うためにはこの結論と限量子を含んだゴールの形とぴったりと一致する必要があります。
[induction] タクティックはコンテキストにある変数にもゴール内の量子化された変数のどちらにでも使えます。
3つめは、[apply] タクティックは変数名（この場合はサブゴール内で使われる変数名）を自動で選びますが、[induction] は（[as ...] 節によって）使う名前を指定できることです。
実際には、この自動選択にはちょっと不都合な点があります。元の定理の [n] とは別の変数として [n] を再利用してしまいます。
これは [Case] 注釈がただの [S] だからです。
ほかの証明で使ってきたように省略しない形で書くと、これは [n = S n] という意味のなさない形になってしまいます。
このようなことがあるため、実際には [nat_ind] のような帰納法の原理を直接適用するよりも、素直に [induction] を使ったほうがよいでしょう。
しかし、ちょっとした例外を除けば実際にやりたいのは [nat_ind] の適用であるということを知っておくことは重要です。 *)
(* **** Exercise: 2 stars (plus_one_r') *)
(** **** 練習問題: ★★ (plus_one_r') *)
(* Complete this proof without using the [induction] tactic. *)
(** [induction] タクティックを使わずに、下記の証明を完成させなさい。 *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
(* induction n as [| S n]. *)
(* induction を使わずに名前を変える方法
intros n.
rename n into m.
generalize dependent m. *)
apply nat_ind.
Case "0".
simpl.
reflexivity.
Case "S".
intros n IHn.
simpl.
rewrite -> IHn.
reflexivity.
Qed.
(** [] *)
(* The induction principles that Coq generates for other
datatypes defined with [Inductive] follow a similar pattern. If we
define a type [t] with constructors [c1] ... [cn], Coq generates a
theorem with this shape:
[[
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
... ->
... case for cn ... ->
forall n : t, P n
]]
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
(** ほかの [Inductive] によって定義されたデータ型に対しても、Coqは似た形の帰納法の原理を生成します。
コンストラクタ [c1] ... [cn] を持った型 [t] を定義すると、Coqは次の形の定理を生成します。
[[
t_ind :
forall P : t -> Prop,
... c1の場合 ... ->
... c2の場合 ... ->
... ->
... cnの場合 ... ->
forall n : t, P n
]]
各場合分けの形は、対応するコンストラクタの引数の数によって決まります。
一般的な規則を紹介する前に、もっと例を見てみましょう。
最初は、コンストラクタが引数を取らない場合です。
*)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(* **** Exercise: 1 star (rgb) *)
(** **** 練習問題: ★ (rgb) *)
(* Write out the induction principle that Coq will generate for
the following datatype. Write down your answer on paper, and
then compare it with what Coq prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
紙に答えを書いたのち、Coqの出力と比較しなさい。 *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
(*
rgb_ind :
forall P : rgb -> Prop,
P red ->
P green ->
P blue ->
forall r : rgb, P r
*)
Check rgb_ind.
(** [] *)
(* Here's another example, this time with one of the constructors
taking some arguments. *)
(** 別の例を見てみましょう。引数を受け取るコンストラクタがある場合です。 *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little tidying)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(* **** Exercise: 1 star (natlist1) *)
(** **** 練習問題: ★ (natlist1) *)
(* Suppose we had written the above definition a little
differently: *)
(** 上記の定義をすこし変えたとしましょう。 *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(* Now what will the induction principle look like? *)
(** このとき、帰納法の原理はどのようになるでしょうか？ *)
(*
natlist1_ind :
forall P : natlist1 -> Prop,
P nnil1 ->
(forall (n : natlist), P n -> forall n0 : nat, P (nsnoc n n0)) ->
forall n : natlist1, P n
8.4pl2では変数名はn, n0, .. という名前になる。
forall (n : 再帰型), P n -> P nの1step後を作るコンストラクタ
*)
Check natlist1_ind.
(** [] *)
(* From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if
[P] holds for each of the [x]s of type [t], then [P]
holds for [c x1 ... xn]". *)
(** これらの例より、一般的な規則を導くことができます。
- 型宣言は複数のコンストラクタを持ち、各コンストラクタが帰納法の原理の各節に対応する。
- 各コンストラクタ [c] は引数 [a1]..[an] を取る。
- [ai] は [t]（定義しようとしているデータ型）、もしくは別の型 [s] かのどちらかである。
- 帰納法の原理において各節は以下のことを述べている。
- "型 [a1]...[an] のすべての値 [x1]...[xn] について、各 [x] について [P] が成り立つならば、[c x1 ... xn] についても [P] が成り立つ"
*)
(* **** Exercise: 1 star (ExSet) *)
(** **** 練習問題: ★ (ExSet) *)
(* Here is an induction principle for an inductively defined
set.
[[
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
]]
Give an [Inductive] definition of [ExSet]: *)
(** 帰納的に定義された集合に対する帰納法の原理が次のようなものだとします。
[[
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
]]
[ExSet] の帰納的な定義を示しなさい。 *)
Inductive ExSet : Type :=
| con1 : bool -> ExSet
| con2 : nat -> ExSet -> ExSet.
Check ExSet_ind.
(** [] *)
(* What about polymorphic datatypes?
The inductive definition of polymorphic lists
[[
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
]]
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
[[
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
]]
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** 多相的なデータ型ではどのようになるでしょうか？
多相的なリストの帰納的定義は [natlist] によく似ています。
[[
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
]]
ここでの主な違いは、定義全体が集合 [X] によってパラメータ化されていることです。
つまり、それぞれの [X] ごとに帰納型 [list X] を定義していることになります。
(定義本体で [list] が登場するときは、常にパラメータ [X] に適用されていることに
注意してください。)
帰納法の原理も同様に [X] によってパラメータ化されます。
[[
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
]]
この表現（と [list_ind] の全体的な形）に注目してください。帰納法の原理全体が
[X] によってパラメータ化されています。
別の見方をすると、[list_ind] は多相関数と考えることができます。この関数は、型
[X] が適用されると、[list X] に特化した帰納法の原理を返します。 *)
(* **** Exercise: 1 star (tree) *)
(** **** 練習問題: ★ (tree) *)
(* Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
答えが書けたら、それをCoqの出力と比較しなさい。 *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
(*
tree :
forall (X : Type) (P : tree X -> Prop),
(forall (x : X), P (leaf x) ->
(forall t1 : tree X, P t1 -> forall t2 : P t2 -> P (node X t1 t2)) ->
forall t : tree X, P t
*)
Check tree_ind.
(** [] *)
(* **** Exercise: 1 star (mytype) *)
(** **** 練習問題: ★ (mytype) *)
(* Find an inductive definition that gives rise to the
following induction principle:
[[
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
]]
*)
(** 以下の帰納法の原理を生成する帰納的定義を探しなさい。
[[
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
]]
*)
Inductive mytype (X : Type) : Type :=
| constr1 : X -> mytype X
| constr2 : nat -> mytype X
| constr3 : mytype X -> nat -> mytype X
.
Check mytype_ind.
(** [] *)
(* **** Exercise: 1 star, optional (foo) *)
(** **** 練習問題: ★, optional (foo) *)
(* Find an inductive definition that gives rise to the
following induction principle:
[[
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
]]
*)
(** 以下の帰納法の原理を生成する帰納的定義を探しなさい。
[[
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
]]
*)
Inductive foo (X Y : Type) : Type :=
| bar : X -> foo X Y
| baz : Y -> foo X Y
| quux : (nat -> foo X Y) -> foo X Y
.
Check foo_ind.
(** [] *)
(* **** Exercise: 1 star, optional (foo') *)
(** **** 練習問題: ★, optional (foo') *)
(* Consider the following inductive definition: *)
(** 次のような帰納的定義があるとします。 *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(* What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
[[
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
]]
*)
(** [foo'] に対してCoqはどのような帰納法の原理を生成するでしょうか?
空欄を埋め、Coqの結果と比較しなさい
[[
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
P f ->
P (C1 X l f)) ->
P (C2 X) ->
forall f : foo' X, P f
]]
*)
Check foo'_ind.
(** [] *)
(* ##################################################### *)
(* ** Induction Hypotheses *)
(** ** 帰納法の仮定 *)
(* Where does the phrase "induction hypothesis" fit into this
picture?
The induction principle for numbers
[[
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
]]
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
(** この概念において"帰納法の仮定"はどこにあてはまるでしょうか?
数に関する帰納法の原理
[[
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
]]
は、すべての命題 [P]（より正確には数値 n を引数にとる命題 [P] ）について成り立つ一般的な文です。
この原理を使うときはいつも、[nat->Prop] という型を持つ式を [P] として選びます。
この式に名前を与えることで、証明をもっと明確にできます。
例えば、[mult_0_r] を"[forall n, n * 0 = 0]"と宣言するかわりに、"[forall n, P_m0r n]"と宣言します。
なお、ここで [P_m0r] は次のように定義されています。
*)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(* ... or equivalently... *)
(** あるいは *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** でも同じ意味です。 *)
(* Now when we do the proof it is easier to see where [P_m0r]
appears. *)
(** これで、証明する際に [P_m0r] がどこに表われるかが分かりやすくなります。 *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
Case "n = O". reflexivity.
Case "n = S n'".
(* Note the proof state at this point! *)
unfold P_m0r. simpl. intros n' IHn'.
apply IHn'. Qed.
(* This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(** このように名前をつける手順は通常の証明では不要です。
しかし、1つ2つ試してみると、帰納法の仮定がどのようなものなのかが分かりやすくなります。
[forall n, P_m0r n] を [n] による帰納法（[induction] か [apply nat_ind] を使う）によって証明しようとすると、最初のサブゴールでは [P_m0r 0]（"[P] が0に対して成り立つ"）を証明しなければならず、2つめのサブゴールでは [forall n', P_m0r n' -> P_m0r (S n')]（"[P] が [n'] について成り立つならば、[P] が [S n'] についても成り立つ"あるいは" [P] が [S] によって保存される"）を証明しなければなりません。
帰納法の仮定は、2つめの推論の基礎になっています -- [P] が [n'] について成り立つことを仮定することにより、それによって [P] が [S n'] について成り立つことを示すことができます。
*)
(* ####################################################### *)
(* ** Evenness Again *)
(** ** 偶数について再び *)
(* Some of the examples in the opening discussion of
propositions involved the concept of _evenness_. We began with a
computation [evenb n] that _checks_ evenness, yielding a boolean.
From this, we built a proposition [even n] (defined in terms of
[evenb]) that _asserts_ that [n] is even. That is, we defined
"[n] is even" to mean "[evenb] returns [true] when applied to
[n]."
Another alternative is to define the concept of evenness directly.
Instead of going indirectly via the [evenb] function ("a number is
even if a certain computation yields [true]"), we can say directly
what the concept of evenness means in terms of evidence. *)
(** 最初の方で命題に関して議論してきた例のいくつかは、偶数の概念に結びついてきます。
これまでは偶数を判定するために [evenb n] を計算することから始め、真偽値を返していました。
つぎに、[n] が偶数であることを主張する命題 [even n] を( [evenb] を使うことで）作りました。
つまり、"[n] が偶数である"を" [evenb] が [n] を適用されたときに [true] を返す"と定義していました。
偶数性の概念をそのまま定義する別の方法があります。
[evenb] 関数（"ある計算が [true] を返すなら、その数は偶数である"）を使って間接的に定義するのではなく、「偶数とは何を意味するか」を根拠を使って直接定義することができるのです。
*)
Inductive ev : nat -> Prop :=
| ev_0 : ev O
| ev_SS : forall n:nat, ev n -> ev (S (S n)).
(*
ev_ind : forall P (nat -> Prop),
P 0 ->
(forall n : nat, ev n -> P n -> P (S (S n))) ->
forall n : nat, P n
*)
Check ev_ind.
(* This definition says that there are two ways to give
evidence that a number [m] is even. First, [0] is even, and
[ev_0] is evidence for this. Second, if [m = S (S n)] for some
[n] and we can give evidence [e] that [n] is even, then [m] is
also even, and [ev_SS n e] is the evidence. *)
(** この定義は、数 [m] が偶数であるという根拠を与える方法が2つあることを示しています。
第一に、[0] は偶数であり、[ev_0] がこれに対する根拠です。
次に、任意の [n] に対して [m = S (S n)] とし、[n] が偶数であるという根拠 [e] を与えることができるならば、[m] も偶数であると言え、[ev_SS n e] がその根拠となります。 *)
(* **** Exercise: 1 star, optional (four_ev) *)
(** **** 練習問題: ★, optional (four_ev) *)
(* Give a tactic proof and a proof object showing that four is even. *)
(** 4が偶数であることをタクティックによる証明と証明オブジェクトによる証明で示しなさい。 *)
Theorem four_ev' :
ev 4.
Proof.
apply ev_SS.
apply ev_SS.
apply ev_0.
Qed.
Check ev_SS.
Check ev_0.
Print four_ev'.
Definition four_ev : ev 4 :=
(* ev_SS _ (ev_SS _ ev_0) *)
ev_SS 2 (ev_SS 0 ev_0)
(* この辺の書き方は依存型がらみ *)
.
(** [] *)
(* **** Exercise: 2 stars (ev_plus4) *)
(** **** 練習問題: ★★ (ev_plus4) *)
(* Give a tactic proof and a proof object showing that, if [n] is
even, then so is [4+n]. *)
(** [n] が偶数ならば [4+n] も偶数であることをタクティックによる証明と証明オブジェクトによる証明で示しなさい。 *)
Definition ev_plus4 : forall n, ev n -> ev (4 + n) :=
(* FILL IN HERE *) admit.
Theorem ev_plus4' : forall n,
ev n -> ev (4 + n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars (double_even) *)
(** **** 練習問題: ★★ (double_even) *)
(* Construct a tactic proof of the following proposition. *)
(** 次の命題をタクティックによって証明しなさい。 *)
Theorem double_even : forall n,
ev (double n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 4 stars, optional (double_even_pfobj) *)
(** **** 練習問題: ★★★★, optional (double_even_pfobj) *)
(* Try to predict what proof object is constructed by the above
tactic proof. (Before checking your answer, you'll want to
strip out any uses of [Case], as these will make the proof
object look a bit cluttered.) *)
(** 上記のタクティックによる証明でどのような証明オブジェクトが構築されるかを予想しなさい。
(答を確かめる前に、[Case] を除去しましょう。 これがあると証明オブジェクトが少し見づらくなります。)
*)
(** [] *)
(* ####################################################### *)
(* ** Reasoning by Induction Over Evidence *)
(** ** 根拠に対する帰納法の推論 *)
(* The highly "orthogonal" organization of Coq's design might
suggest that, since we use the keyword [Induction] to define
primitive propositions together with their evidence, there must be
some sort of induction principles associated with these
definitions. Indeed there are, and in this section we'll take a
look at how they can be used. To get warmed up, let's look at how
the simpler [destruct] tactic works with inductively defined
evidence. *)
(** Coqの設計は非常に直交しているので、素朴な命題を根拠と共に定義するために [Inductive] キーワードを使った場合、その定義と関連する帰納法の原理が使えるはずです。
実際、関連する帰納法の原理は存在しており、この節ではそれをどう使うかについて見ていきます。
ウォーミングアップとして、単純な [destruct] が帰納的に定義された根拠に対してどのように働くかを見てみましょう。
*)
(* Besides _constructing_ evidence of evenness, we can also _reason
about_ evidence of evenness. The fact that we introduced [ev]
with an [Inductive] declaration tells us not only that the
constructors [ev_0] and [ev_SS] are ways to build evidence of
evenness, but also that these two constructors are the _only_ ways
that evidence of evenness can be built.
In other words, if someone gives us evidence [E] justifying the
assertion [ev n], then we know that [E] can only have one of two
forms: either [E] is [ev_0] (and [n] is [O]), or [E] is [ev_SS n'
E'] (and [n] is [S (S n')]) and [E'] is evidence that [n'] is
even.
Thus, it makes sense to use the tactics that we have already seen
for inductively defined _data_ to reason instead about inductively
defined _evidence_.
For example, here we use a [destruct] on evidence that [n] is even
in order to show that [ev n] implies [ev (n-2)]. *)
(** 偶数であるという根拠を作るだけでなく、偶数であるという根拠に対して推論を行います。
帰納的な宣言によって [ev] を導入したことにより、「 [ev_0] と [ev_SS] が、偶数であるという根拠を作る唯一の方法である」ということが分かるだけでなく、「この2つのコンストラクタによってのみ偶数であるという根拠が構築される」ということが分かります。
言い換えると、 [ev n] という根拠 [E] があった場合、 [E] は2つの形式のどちらか片方であることが分かります : 「[E] が [ev_0] (かつ [n] が [0] )である」か、「 [E] が [ev_SS n' E'](かつ [n] が [S (S n')]) かつ [E'] が [n'] が偶数であるということの根拠である」かのどちらかです。
なので、これまで見てきたように帰納的に定義されたデータに対してだけでなく、帰納的に定義された根拠に対しても、 [destruct] タクティックを使うことは有用です。
一例として、[ev n] ならば [ev (n-2)] を示すために、 [n] が偶数であるという根拠に対して [destruct] タクティックを使ってみましょう。
*)
Theorem ev_minus2: forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
destruct E as [| n' E'].
Case "E = ev_0". simpl. apply ev_0.
Case "E = ev_SS n' E'". simpl. apply E'. Qed.
(* **** Exercise: 1 star (ev_minus2_n) *)
(** **** 練習問題: ★ (ev_minus2_n) *)
(* What happens if we try to [destruct] on [n] instead of [E]? *)
(** [E] の代わりに [n] に対して [destruct] するとどうなるでしょうか? *)
Theorem ev_minus2_n: forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
destruct n as [| n'].
Case "n = 0".
simpl.
apply E.
Case "n = S n'".
simpl.
destruct n' as [| n''].
SCase "n' = 0".
simpl. apply ev_0.
SCase "n' = S n''".
simpl.
inversion E.
apply H0.
Qed.
(** [] *)
(* [] *)
(* We can also perform _induction_ on evidence that [n] is
even. Here we use it to show that the old [evenb] function
returns [true] on [n] when [n] is even according to [ev]. *)
(** [n] が偶数であるという根拠に対して [induction] を実行することもできます。
[ev] を満たす [n] に対して、先に定義した [evenb] 関数が [true] を返すことを示すために使ってみましょう。
*)
Theorem ev_even : forall n,
ev n -> even n.
Proof.
intros n E. induction E as [| n' E'].
Case "E = ev_0".
unfold even. reflexivity.
Case "E = ev_SS n' E'".
unfold even. apply IHE'. Qed.
(* (Of course, we'd expect that [even n -> ev n] also holds. We'll
see how to prove it in the next chapter.) *)
(** (もちろん、 [even n -> ev n] も成り立つはずです。 どのように証明するかは次の章で説明します。) *)
(* **** Exercise: 1 star (ev_even_n) *)
(** **** 練習問題: ★ (ev_even_n) *)
(** *)
(** この証明を [E] でなく [n] に対する帰納法として実施できますか? *)
(* Could this proof be carried out by induction on [n] instead
of [E]? *)
(** [] *)
(* [] *)
(* The induction principle for inductively defined propositions does
not follow quite the same form as that of inductively defined
sets. For now, you can take the intuitive view that induction on
evidence [ev n] is similar to induction on [n], but restricts our
attention to only those numbers for which evidence [ev n] could be
generated. We'll look at the induction principle of [ev] in more
depth below, to explain what's really going on. *)
(** 帰納的に定義された命題に対する帰納法の原理は、帰納的に定義された集合のそれとまったく同じ形をしているわけではありません。
今の段階では、根拠 [ev n] に対する帰納法は [n] に対する帰納法に似ているが、 [ev n] が成立する数についてのみ着目することができると直感的に理解しておいて問題ありません。
[ev] の帰納法の原理をもっと深く見て行き、実際に何を起こっているかを説明します。*)
(* **** Exercise: 1 star (l_fails) *)
(** **** 練習問題: ★ (l_fails) *)
(* The following proof attempt will not succeed.[[
Theorem l : forall n,
ev n.
Proof.
intros n. induction n.
Case "O". simpl. apply ev_0.
Case "S".
...
]]
Briefly explain why.
(* FILL IN HERE *)
*)
(** 次の証明はうまくいきません。 [[
Theorem l : forall n,
ev n.
Proof.
intros n. induction n.
Case "O". simpl. apply ev_0.
Case "S".
...
]]
理由を簡潔に説明しない。
(* FILL IN HERE *)
*)
(** [] *)
(* [] *)
(* **** Exercise: 2 stars (ev_sum) *)
(** **** 練習問題: ★★ (ev_sum) *)
(* Here's another exercise requiring induction. *)
(** 帰納法が必要な別の練習問題をやってみましょう。 *)
Theorem ev_sum : forall n m,
ev n -> ev m -> ev (n+m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Here's another situation where we want to analyze evidence for
evenness: proving that if [n+2] is even, then [n] is. Our first
idea might be to use [destruct] for this kind of case analysis: *)
(** 「[n+2] が偶数ならば [n] も偶数である」という偶数に関する根拠を分析したいとします。
この種の場合分けに [destruct] を使ってみたくなるかもしれません。 *)
Theorem SSev_ev_firsttry : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E.
destruct E as [| n' E'].
(* Stuck: [destruct] は証明できないサブゴールを提示してしまいます！ *)
Admitted.
(* But this doesn't work. For example, in the first sub-goal, we've
lost the information that [n] is [0]. The right thing to use
here, it turns out, is [inversion]: *)
(** しかし、これはうまくいきません。 例えば、最初のサブゴールにおいて、 [n] が [0] であるという情報が失われてしまいます。
ここで使うべきは、 [inversion] です。 *)
Theorem SSev_even : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E. inversion E as [| n' E']. apply E'. Qed.
(* Print SSev_even. *)
(* This use of [inversion] may seem a bit mysterious at first.
Until now, we've only used [inversion] on equality
propositions, to utilize injectivity of constructors or to
discriminate between different constructors. But we see here
that [inversion] can also be applied to analyzing evidence
for inductively defined propositions.
Here's how [inversion] works in general. Suppose the name
[I] refers to an assumption [P] in the current context, where
[P] has been defined by an [Inductive] declaration. Then,
for each of the constructors of [P], [inversion I] generates
a subgoal in which [I] has been replaced by the exact,
specific conditions under which this constructor could have
been used to prove [P]. Some of these subgoals will be
self-contradictory; [inversion] throws these away. The ones
that are left represent the cases that must be proved to
establish the original goal.
In this particular case, the [inversion] analyzed the construction
[ev (S (S n))], determined that this could only have been
constructed using [ev_SS], and generated a new subgoal with the
arguments of that constructor as new hypotheses. (It also
produced an auxiliary equality, which happens to be useless here.)
We'll begin exploring this more general behavior of inversion in
what follows. *)
(** このような [inversion] の使い方は最初はちょっと謎めいて思えるかもしれません。
これまでは、 [inversion] は等号に関する命題に対して使い、コンストラクタから元のデータを取り出すためか、別のコンストラクタを区別するためににしか使っていませんでした。
しかし、ここでは [inversion] が 帰納的に定義された命題に対する根拠を分析するためにも使えることを紹介しました。
ここで、[inversion] が一般にはどのように動作するかを説明します。
[I] が現在のコンテキストにおいて帰納的に宣言された仮定 [P] を参照しているとします。
ここで、[inversion I] は、[P]のコンストラクタごとにサブゴールを生成します。 各サブゴールにおいて、 コンストラクタが [P] を証明するのに必要な条件によって [I] が置き換えられます。
サブゴールのうちいくつかは矛盾が存在するので、 [inversion] はそれらを除外します。
残っているのは、元のゴールが成り立つことを示すのに必要なサブゴールです。
先ほどの例で、 [inversion] は [ev (S (S n))] の分析に用いられ、 これはコンストラクタ [ev_SS] を使って構築されていることを判定し、そのコンストラクタの引数を仮定に追加した新しいサブゴールを生成しました。(今回は使いませんでしたが、補助的な等式も生成しています。)
このあとの例では、inversion のより一般的な振る舞いについて調べていきましょう。
*)
(* **** Exercise: 1 star (inversion_practice) *)
(** **** 練習問題: ★ (inversion_practice) *)
Theorem SSSSev_even : forall n,
ev (S (S (S (S n)))) -> ev n.
Proof.
intros n E.
inversion E as [|n' E'].
inversion E' as [|n'' E''].
apply E''.
Qed.
(* [] *)
(* The [inversion] tactic can also be used to derive goals by showing
the absurdity of a hypothesis. *)
(** [inversion] タクティックは、仮定が矛盾していることを示し、ゴールを達成するためにも使えます。
*)
Theorem even5_nonsense :
ev 5 -> 2 + 2 = 9.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* We can generally use [inversion] instead of [destruct] on
inductive propositions. This illustrates that in general, we
get one case for each possible constructor. Again, we also
get some auxiliary equalities that are rewritten in the goal
but not in the other hypotheses. *)
(** 一般に、帰納的な命題には [destruct] の代わりに [inversion] を使えます。
このことは一般的に、コンストラクタごとに場合分けができることを示しています。
加えて、いくつかの補助的な等式も得ることができます。
なお、ゴールはその等式によって書き換えられていますが、その他の仮定は書き換えられていません。
*)
Theorem ev_minus2': forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E. inversion E as [| n' E'].
Case "E = ev_0". simpl. apply ev_0.
Case "E = ev_SS n' E'". simpl. apply E'. Qed.
(* **** Exercise: 3 stars (ev_ev_even) *)
(** **** 練習問題: ★★★ (ev_ev_even) *)
(* Finding the appropriate thing to do induction on is a
bit tricky here: *)
(** 何に対して帰納法を行えばいいかを探しなさい。(ちょっとトリッキーですが) *)
Theorem ev_ev_even : forall n m,
ev (n+m) -> ev n -> ev m.
Proof.
intros n m Enm En.
generalize dependent Enm.
generalize dependent m.
induction En.
simpl. intros m Em. apply Em.
simpl. intros m ESSnm. inversion ESSnm. apply (IHEn m H0).
Qed.
(** [] *)
(* **** Exercise: 3 stars, optional (ev_plus_plus) *)
(** **** 練習問題: ★★★, optional (ev_plus_plus) *)
(* Here's an exercise that just requires applying existing lemmas. No
induction or even case analysis is needed, but some of the rewriting
may be tedious. You'll want the [replace] tactic used for [plus_swap']
in Basics.v *)
(** 既存の補題を適用する必要のある練習問題です。
帰納法も場合分けも不要ですが、書き換えのうちいくつかはちょっと大変です。
Basics_J.v の [plus_swap'] で使った [replace] タクティックを使うとよいかもしれません。 *)
Theorem ev_plus_plus : forall n m p,
ev (n+m) -> ev (n+p) -> ev (m+p).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ##################################################### *)
(* ** Why Define Propositions Inductively? *)
(** ** なぜ命題を帰納的に定義するのか? *)
(* We have seen that the proposition "some number is even" can
be phrased in two different ways -- indirectly, via a testing
function [evenb], or directly, by inductively describing what
constitutes evidence for evenness. These two ways of
defining evenness are about equally easy to state and work
with. Which we choose is basically a question of taste.
However, for many other properties of interest, the direct
inductive definition is preferable, since writing a testing
function may be awkward or even impossible. For example, consider
the property [MyProp] defined as follows:
- the number [4] has property [MyProp]
- if [n] has property [MyProp], then so does [4+n]
- if [2+n] has property [MyProp], then so does [n]
- no other numbers have property [MyProp]
This is a perfectly sensible definition of a set of numbers, but
we cannot translate this definition directly as a Coq Fixpoint (or
translate it directly into a recursive function in any other
programming language). We might be able to find a clever way of
testing this property using a [Fixpoint] (indeed, it is not too
hard to find one in this case), but in general this could require
arbitrarily much thinking. In fact, if the property we are
interested in is uncomputable, then we cannot define it as a
[Fixpoint] no matter how hard we try, because Coq requires that
all [Fixpoint]s correspond to terminating computations.
On the other hand, writing an inductive definition of what it
means to give evidence for the property [MyProp] is
straightforward: *)
(** ここまで見てきたように "ある数が偶数である" というのは次の2通りの方法で解釈されます。
間接的には「テスト用の [evenb] 関数」によって、直接的には「偶数であることの根拠の構築方法を帰納的に記述すること」によってです。
これら2つの偶数の定義は、ほぼ同じくらい楽に宣言できますし、同じように動きます。
どちらを選ぶかは基本的に好みの問題です。
しかし、興味深いほかの性質、例えば「テスト用の関数を書くのが難しかったり不可能だったりする」ようなことがあることを考えると、直接的な帰納的な定義のほうが好ましいと言えます。
例えば以下のように定義される [MyProp] という性質について考えてみましょう。
- [4] は性質 [MyProp] を満たす
- [n] が性質 [MyProp] を満たすならば、 [4+n] も満たす
- もし[2+n]が性質 [MyProp] を満たすならば、 [n] も満たす
- その他の数は、性質 [MyProp] を満たさない
これは数の集合の定義としてはなんの問題もありませんが、この定義をそのままCoqのFixPointに変換することはできません。
(それだけでなく他の言語の再帰関数に変換することもできません。)
[Fixpoint] を用いてこの性質をテストするうまい方法を見つけられるかもしれません。(実際のところ、この場合はそれほど難しいことではありません)
しかし、一般的にこういうことをしようとすると、かなりあれこれ考える必要があるでしょう。
実際、Coqの [Fixpoint] は停止する計算しか定義できないので、
定義しようとする性質が計算不能なものだった場合、どれだけがんばっても [Fixpoint] では定義できません。
一方、性質 [MyProp] がどのようなものかの根拠を与える帰納的な定義を書くことは、非常に簡単です。
*)
Inductive MyProp : nat -> Prop :=
| MyProp1 : MyProp 4
| MyProp2 : forall n:nat, MyProp n -> MyProp (4 + n)
| MyProp3 : forall n:nat, MyProp (2 + n) -> MyProp n.
(* The first three clauses in the informal definition of [MyProp]
above are reflected in the first three clauses of the inductive
definition. The fourth clause is the precise force of the keyword
[Inductive]. *)
(** [MyProp] の非形式的な定義の最初の3つの節は、帰納的な定義の最初の3つの節に反映されています。
4つ目の節は、[Inductive] キーワードによって強制されます。
*)
(* As we did with evenness, we can now construct evidence that
certain numbers satisfy [MyProp]. *)
(** これで、偶数のときにやったように、ある数が [MyProp] を満たすことの根拠を作ることができます。 *)
Theorem MyProp_ten : MyProp 10.
Proof.
apply MyProp3. simpl.
assert (12 = 4 + 8) as H12.
Case "Proof of assertion". reflexivity.
rewrite -> H12.
apply MyProp2.
assert (8 = 4 + 4) as H8.
Case "Proof of assertion". reflexivity.
rewrite -> H8.
apply MyProp2.
apply MyProp1. Qed.
(* **** Exercise: 2 stars (MyProp) *)
(** **** 練習問題: ★★ (MyProp) *)
(* Here are two useful facts about MyProp. The proofs are left
to you. *)
(** MyPropに関する便利な2つの事実があります。
証明はあなたのために残してあります。 *)
Theorem MyProp_0 : MyProp 0.
Proof.
(* FILL IN HERE *) Admitted.
Theorem MyProp_plustwo : forall n:nat, MyProp n -> MyProp (S (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* With these, we can show that [MyProp] holds of all even numbers,
and vice versa. *)
(** これらを使って、 [MyProp] は全ての奇数について成り立つことと、その逆も成り立つをことを示せます。 *)
Theorem MyProp_ev : forall n:nat,
ev n -> MyProp n.
Proof.
intros n E.
induction E as [| n' E'].
Case "E = ev_0".
apply MyProp_0.
Case "E = ev_SS n' E'".
apply MyProp_plustwo. apply IHE'. Qed.
(* Here's an informal proof of this theorem:
_Theorem_: For any nat [n], if [ev n] then [MyProp n].
_Proof_: Suppose [n] is a [nat] and [E] is a derivation of [ev n].
We must exhibit a derivation of [MyProp n]. The proof is by
induction on [E]. There are two cases to consider:
- If the last step in [E] is a use of [ev_0], then [n] is [0].
Then we must show that [MyProp 0] holds; this is true by
lemma [MyProp_0].
- If the last step in [E] is a use of [ev_SS], then [n = S (S n')]
for some [n'], and there is a derivation of [ev n']. We must
show [MyProp (S (S n'))], with the induction hypothesis that
[MyProp n'] holds. But by lemma [MyProp_plustwo], it's enough
to show [MyProp n'], which is exactly the induction
hypothesis. [] *)
(** この定理の非形式的な証明は次のようになります。
_Theorem_ : 任意の自然数 [n] において、もし [ev n] ならば [MyProp n] が成り立つ。
_Proof_ : [n] を [nat] とし、[ev n] の導出を [E] とします。
[MyProp n] の導出を示さなければなりません。
[E] の帰納法について証明を行うので、以下の2つの場合について考えなければなりません。
- [E] の最後のステップが[ev_0]だった場合、 [n] は [0] となる。
その場合、[MyProp 0]が成り立つをことを示さなければならない;
補題 [MyProp_0] よりこれは真である。
- [E] の最後のステップが [ev_SS] だった場合、 [n = S (S n')] となる [n'] が存在し、 [ev n'] の導出が存在する。
[MyProp n'] が成り立つという帰納法の仮定を用いて、[MyProp (S (S n'))] を示さなければなりません。
しかし、補題 [MyProp_plustwo] により、[MyProp n'] を示せば十分であることがわかり、さらにそれは帰納法の仮定そのものです。
*)
(* **** Exercise: 3 stars (ev_MyProp) *)
(** **** 練習問題: ★★★ (ev_MyProp) *)
Theorem ev_MyProp : forall n:nat,
MyProp n -> ev n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 3 stars, optional (ev_MyProp_informal) *)
(** **** 練習問題: ★★★, optional (ev_MyProp_informal) *)
(* Write an informal proof corresponding to your
formal proof of [ev_MyProp]:
Theorem: For any nat [n], if [MyProp n] then [ev n].
Proof:
(* FILL IN HERE *)
[] *)
(** [ev_MyProp] の 形式的な証明に対応する非形式的な証明を書きなさい。
定理: すべての自然数 [n] に対して、 [MyProp n] ならば [ev n]。
証明: (ここを埋める)
[] *)
(* ##################################################### *)
(* * The Big Picture: Coq's Two Universes *)
(** * 全体像: Coqの2つの空間 *)
(* Now that we've touched on several of Coq's basic structures,
it may be useful to take a step back and talk a little about how
it all fits together. *)
(** これまで Coq の基本的な構造についていくつか触れてきたので、
ここでは一歩引いてそれらがどのように組み合わさっているか少しだけ見てみましょう。
*)
(* Expressions in Coq live in two distinct universes:
- [Type] is the universe of _computations_ and _data_.
- [Prop] is the universe of _logical assertions_ and _evidence_.
The two universes have some deep similarities -- in each, we can
talk about values, inductive definitions, quantification, etc. --
but they play quite different roles in defining and reasoning about
mathematical structures. *)
(** Coq の式は2つの異なる空間のどちらかに属しています。
- [Type] は計算とデータの空間です。
- [Prop] は論理的表明と根拠の空間です。
2つの空間には深い類似性がありますが（それぞれについて値、帰納的な定義、限量子などについて言及できます）、
数学的構造の定義や推論において、これらはまったく異なる役割を果たします。
*)
(* ** Values *)
(** ** 値 *)
(* Both universes start with an infinite set of _constructors_.
Constructors have no internal structure: they are just atomic
symbols. For example, [true], [false], [O], [S], [nil], [cons],
[ev_0], [ev_SS], ...
The simplest values are expressions consisting entirely of
constructor applications. Examples include:
- [true]
- [O]
- [S (S (S O))]
- [ev_0]
- [ev_SS (S (S O)) ev_0]
- [ev_SS (S (S (S (S O)))) (ev_SS (S (S O)) ev_0)]
Such expressions can be thought of as trees. Their leaves are
nullary constructors (applied to no arguments), and their internal
nodes are applications of constructors to one or more values. In
the universe [Type], we think of values as _data_. In [Prop], we
think of values as _evidence_. Values in [Prop] are sometimes
called _derivation trees_.
Functions are also values -- for example:
- [fun x => true]
- [fun b => negb b]
- [fun n => S (S (S n))]
- [fun n => fun (P : ev n) => ev_SS (S (S n)) P]
Functions that return values in the universe [Type] represent
_computations_: they take some input values and return an output
value computed from the inputs. Functions returning values in
[Prop] are _universally quantified evidence_: that is, they use
their inputs to build evidence for some proposition (whose
statement may also involve these inputs). *)
(** どちらのの空間もコンストラクタの無限集合をスタート地点とします。
コンストラクタは内部構造を全く持っておらず、ただのアトミックなシンボルです。
例えば、[true], [false], [O], [S], [nil], [cons],
[ev_0], [ev_SS], ... などです。
最も単純な値は、コンストラクタの適用だけによって構成されます。
例えば:
- [true]
- [O]
- [S (S (S O))]
- [ev_0]
- [ev_SS (S (S O)) ev_0]
- [ev_SS (S (S (S (S O)))) (ev_SS (S (S O)) ev_0)]
そのような式は木として考えることもできます。
葉は0引数のコンストラクタ（引数なしで適用された）であり、内部ノードは1個以上の値に対して適用されたコンストラクタです。
[Type] 空間において、値はデータとして捉えます。
[Prop] において、値を根拠として捉えます。
[Prop] における値は、導出木と呼ばれることもあります。
関数もまた値です。例えば、
- [fun x => true]
- [fun b => negb b]
- [fun n => S (S (S n))]
- [fun n => fun (P : ev n) => ev_SS (S (S n)) P]
[Type] 空間の値を返す関数は、計算を表します: 入力値を受け取り、入力から計算した出力値を返します。
[Prop] の値を返す関数は、全量子化された根拠と呼ばれます。 すなわち、ある命題に対する根拠を作るのに入力も用います。
（作られる命題も入力を使うかもしれません。）
*)
(* ** Inductive Definitions *)
(** ** 帰納的定義 *)
(* [Inductive] declarations give names to subsets of the set of all
values. For example, the declaration of the inductive type [nat]
defines a _set_ whose _elements_ are values representing natural
numbers. That is, it picks out a subset [nat] of the set of all
values that satisfies the following properties:
- the value [O] is in this set;
- the set is _closed_ under applications of [S] (i.e., if a
value [n] is in the set, then [S n] is too);
- it is the smallest set satisfying these conditions (i.e., the
only values in [nat] are the ones that _must_ be, according to
the previous two conditions; there is no other "junk").
Inductively defined sets can themselves appear as arguments to
constructors in compound values. Examples:
- [nat]
- [nil nat]
- [cons nat O (cons nat (S O) (nil nat))]
Also, we can write functions that take sets as arguments and
return sets as results. For example, [list] is a function that
takes a set [X] as argument and returns as result the set [list
X] (whose members are lists with elements drawn from [X]).
Similarly, the declaration of the inductive type [ev] defines a
_family of propositions_ whose _elements_ are values representing
evidence that numbers are even. That is, for each [n], the
definition picks out a subset [ev n] of the set of all values,
satisfying the following properties:
- the value [ev_0] is in the set [ev O];
- the sets are _closed_ under well-typed applications of
[ev_SS] -- i.e., if [e] is in the set [ev n], then
[ev_SS n e] is in the set [ev (S (S n))];
- it is the smallest family of sets satisfying these
conditions (i.e., the only values in any set [ev n] are the
ones that _must_ be, according to the previous two conditions;
there is no other junk). *)
(** 帰納的（[Inductive]）な定義をするということは、全ての値の集合の「特定の部分集合に名前を与える」ということです。
例えば、帰納的な型 [nat] の定義は、要素の全てが自然数を表しているような集合を表します。つまり、 帰納的な定義が「全ての値の集合」から以下のような属性を持つ要素だけを抜き出して部分集合 [nat] を作っていると考えられます。
- 値 [O] はこの集合の要素である。
- この集合は、 [S] の適用に対し閉じている（つまり、値 [n] がこの集合の要素なら [S n] もまたこの集合の要素である）。
- これらの条件を満たす最小の集合がこの集合である。（つまり集合 [nat] の要素だけが上の二つの条件を満たしていて、それ以外のものはこの集合に入っていない）。
帰納的に定義された集合は、それ自身が複合的な値のコンストラクタの引数となることもあります。例えば、以下のようなものです。
- [nat]
- [nil nat]
- [cons nat O (cons nat (S O) (nil nat))]
また、引数や戻り値が集合となっているような関数を書くこともできます。例えば、 [list] は集合 [X] を引数にとり、 [list X] の集合を返す関数です（この集合の要素は、集合 [X] の要素を持つリストです）。
同様に、帰納的な型 [ev] の定義は、その数字が偶数であるという根拠となる命題を集めたものの定義です。このことは、全ての [n] について、この定義が全ての値の集合から以下の条件を満たす値を全て集めて部分集合 [ev n] を抜き出してくるような定義、ということです。
- 値 [ev_0] は集合 [ev O] の要素である。
- この集合は [ev_SS] の型が正しい（well-typed な）適用に関して閉じている。
-- つまり、もし値 [e] が集合 [ev n] の要素なら、
値[ev_SS n e] は集合 [ev (S (S n))] の要素である。;
- これらの条件を満たす最小の集合がこの集合である。 (つまり集合 [ev n] の要素だけが上の二つの条件を満たしていて、それ以外のものはこの集合に入っていない）。 *)
(* ** Types and Kinds *)
(** ** 型とカインド *)
(* Informally, a _type_ in Coq is an expression that is used to
classify other expressions. For example, [bool], [nat], [list
bool], [list nat], [nat->nat], and so on are all types. The type
[bool] classifies [true] and [false]; the type [nat] classifies
[O], [S O], [S (S O)], etc.; the type [nat->nat] classifies
function values (like [fun n => S n]) that yield a number when
given a number as input.
[Type], [Prop], and compound expressions built from them (like
[Type->Type]) play a similar classifying role "one level up" --
that is, they can be thought of as the _types of type (and
proposition) expressions_. Technically, they are called _kinds_,
to avoid too many uses of the word "type." For example, the
expressions [nat], [nat->nat] and [list nat] all have kind [Type],
while [list] itself has kind [Type->Type] and [ev] has kind
[nat->Prop]. *)
(** ざっくり言うと、Coqにおける「型」は、「式の分類に使われる式」です。例えば、 [bool], [nat], [list bool], [list nat], [nat->nat] などは全て「型」です。[bool] という型は、 [true] や [false] を他の値と区別しますし、[nat] 型は [O], [S O], [S (S O)] など、[nat->nat] 型は [fun n => S n] のように数を引数にとって数を返す関数値を他の値と区別します。
[Type] や [Prop] 、そしてそれらの複合式（ [Type -> Type] など）には、「ひとつ上位の」分類 -- それは, 「型（もしくは命題）の型を表す式」のようなものと考えてもらっていいですが -- が可能です。それを、単なる「型」と混同しないために「カインド」と呼ぶことにします。例えば、[nat] や [nat->nat] 、[list nat] などは全て [Type] という「カインド」を持ち、 [list] は [Type -> Type]、 [ev] は [nat -> Prop] というカインドを持ちます。 *)
(** ** 命題 vs. ブール値 *)
(* Propositions and booleans are superficially similar, but they are
really quite different things!
- Booleans are _values_ in the _computational_ world. Every
expression of type [bool] (with no free variables) can be
simplified to either [true] or [false].
- Propositions are _types_ in the _logical_ world. They are
either _provable_ (i.e., there is some expression that has this
type) or not (there is no such expression). It doesn't make
sense to say that a proposition is "equivalent to [true]."
We sometimes use the words "true" and "false" informally when
referring to propositions. Strictly speaking, this is wrong: a
proposition is either provable or it is not. *)
(** 命題とブール値は、一見とてもよく似ているように見えます。しかしこの二つは根本的に違うものです！
- ブール値は、「計算の世界における値」です。 [bool] 型の式は全て、（自由変数を持っていない限り）必ず [true] か [false] のどちらかに簡約することができます。
- 命題は「論理の世界にいおける型」です。これらは「証明可能（この型の式を書くことができる）」か、「証明不能（そのような式は存在しない）」かのいずれかです。従って「命題が [true] である」というような言い方は意味を持ちません。
我々は時折、命題に対してそれが "true" か "false" というようなことを言ってしまいがちですが、厳格に言えばこれは間違っています。命題は「証明可能かそうでないか」のどちらかです。 *)
(* ** Functions vs. Quantifiers *)
(** ** 関数 vs. 限量子 *)
(* The types [A->B] and [forall x:A, B] both describe functions from
[A] to [B]. The only difference is that, in the second case, the
expression [B] -- the type of the result -- can mention the
argument [x] by name. For example:
- The function [fun x:nat => x + x] has type [nat->nat] --
that is, it maps each number [n] to a number.
- The function [fun X:Type => nil (list X)] has type [forall
X:Type, list (list X)] -- that is, it maps each set [X] to a
particular list of lists of [X]s. (Of course, [nil] is
usually written as [[]] instead of [nil X].)
In fact, the two ways of writing function types are really the
same: In Coq, [A->B] is actually just an abbreviation for [forall
x:A, B], where [x] is some variable name not occurring in [B]. For
example, the type of [fun x:nat => x + x] can be written, if we
like, as [forall x:nat, nat]. *)
(** [A->B] という型も [forall x:A, B] という型も、どちらも型 [A] から型 [B] への関数である、という点については同じです。この二つの唯一の違いは、後者の場合戻り値の型 [B] が引数 [x] を参照できるということです。たとえば、
- 関数 [fun x:nat => x + x] は型 [nat->nat] を持っていますが、このことは任意の数 [n] を別の数に対応させるもの、ということです。
- 対して、関数 [fun X : Type => nil (list X)] は [forall
X : Type, list (list X)] という型になります。これは、任意の集合 [X] を、 [X] 型のリストのリストに対応させるもの、ということになります。（もちろん、[nil] は通常 [nil X] と書く代わりに [[]] と書くのが普通ですが。）
実際、関数を記述するためのこれら二つの書き方はほぼ同じですが、 Coq では [A->B] の書き方は、[x] が[B] の定義の中に変数として現れない限り、[fun x:nat => x + x] のただの省略形と考えていいでしょう。例えば、好みならばこれを [forall x:nat, nat] と書いてもいいのです。 *)
(** ** 関数 vs. 含意 *)
(* In both [Type] and [Prop], we can write functions that transform
values into other values. Also, functions themselves are values;
this means we can
- write higher-order functions that take functions as arguments
or return functions as results, and
- apply constructors to functions to build complex values
containing functions.
A function of type [P->Q] in [Prop] is something that takes
evidence for [P] as an argument and yields evidence for [Q] as its
result. Such a function can be regarded as _evidence_ that [P]
implies [Q], since, whenever we have evidence that [P] is true, we
can apply the function and get back evidence that [Q] is true:
evidence for an implication is a function on evidence. This is why
we use the same notation for functions and logical implications in
Coq: they are exactly the same thing! *)
(** [Type] にしろ [Prop] にしろ、我々はその値を別の値に変換する関数を書くことができます。 また、関数はそれ自身が値です。
このことは、我々が、次のようなことが出来ることを意味しています。
- 関数を引数にしたり、関数を戻り値にしたりする高階関数を書くこと。
- 関数をコンストラクタに適用し、関数を保持したさらに複雑な値を作り出すこと。
[Prop] 型を扱う [P->Q] という型の関数は、 [P] の根拠を引数にとり、新たな [Q] の根拠を結果として生成するものです。このような関数はそれ自身が「[P] ならば [Q] である」ということの根拠であると見なせます。そのことから、[P] が真であるという根拠があるなら、それを関数に適用して [Q] が真であるという根拠を得ることができます。含意に根拠を与えるということは、根拠の関数を与えるということと同じです。このことが、我々が Coq で関数と論理学の「含意」に同じ表記を与えている理由です。これらは全く同じものなのです。 *)
(* ####################################################### *)
(* * Informal Proofs *)
(** * 非形式的な証明 *)
(* Q: What is the relation between a formal proof of a proposition
[P] and an informal proof of the same proposition [P]?
A: The latter should _teach_ the reader how to produce the
former.
Q: How much detail is needed?
A: There is no single right answer; rather, there is a range
of choices.
At one end of the spectrum, we can essentially give the
reader the whole formal proof (i.e., the informal proof
amounts to just transcribing the formal one into words).
This gives the reader the _ability_ to reproduce the formal
one for themselves, but it doesn't _teach_ them anything.
At the other end of the spectrum, we can say "The theorem
is true and you can figure out why for yourself if you
think about it hard enough." This is also not a good
teaching strategy, because usually writing the proof
requires some deep insights into the thing we're proving,
and most readers will give up before they rediscover all
the same insights as we did.
In the middle is the golden mean -- a proof that includes
all of the essential insights (saving the reader the hard
part of work that we went through to find the proof in the
first place) and clear high-level suggestions for the more
routine parts to save the reader from spending too much
time reconstructing these parts (e.g., what the IH says and
what must be shown in each case of an inductive proof), but
not so much detail that the main ideas are obscured.
Another key point: if we're talking about a formal proof of a
proposition P and an informal proof of P, the proposition P doesn't
change. That is, formal and informal proofs are _talking about the
same world_ and they must _play by the same rules_. *)
(** Q: 命題 [P] の形式的な証明と、同じ命題 [P] の非形式的な証明の間にはどのような関係があるのでしょうか？
A: 後者は、読む人に「どのように形式的な証明を導くか」を示すようなものとなっているべきです。
Q: どの程度細かく書く必要があるのですか？
A: この問いに唯一と言えるような解答はありません。回答には選択の幅があります。
その範囲の片方の端は、読み手にただ形式的な証明全体を与えればよいという考えです。つまり非形式的な証明は、形式的な証明をただ単に普通の言葉で書き換えただけ 、ということです。この方法は、読み手に形式的な証明を書かせるための能力を与えることはできますが、それについて何かも「教えてくれる」訳ではありません。
これに対しもう一方の端は、「その定理は真で、頑張ればできるはず」ような記述です。この方法も、「教える」ということに関してはあまりいいやり方とはいえません。なぜなら、証明を記述するときはいつも、今証明しようとしているものの奥深くにまで目を向け考えることが必要とされますが、細かく書きすぎると証明を読む側の人の多くは自分自身の力で同じ思考にたどり着くことなく、あきらめて証明の記述に頼ってしまうでしょう。
一番の答えはその中間にあります。全ての要点をかいつまんだ証明というのは、「かつてあなたが証明をしたときに非常に苦労した部分について、読む人が同じ苦労をしなくて済むようになっている」ようなものです。そしてまた、読み手が同じような苦労を何時間もかけてする必要がないよう、証明の中で使える部品などを高度に示唆するものでなければなりません（例えば、仮定 IH が何を言っているかや、帰納的な証明のどの部分に現れるかなど）。しかし、詳細が少なすぎると、証明の主要なアイデアがうまく伝わりません。
もう一つのキーポイント：もし我々が命題 P の形式的な証明と非形式的な証明について話しているならば、命題 P 自体は何も変わりません。このことは、形式的な証明も非形式的な証明も、同じ「世界」について話をしていて、同じルールに基づいていなければならない、と言うことを意味しています。
*)
(* ####################################################### *)
(* ** Informal Proofs by Induction *)
(** ** 帰納法による非形式的な証明 *)
(* Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief
and telegraphic. The ideal is somewhere in between, of course,
but while you are getting used to the style it is better to start
out at the pedantic end. Also, during the learning phase, it is
probably helpful to have a clear standard to compare against.
With this in mind, we offer two templates below -- one for proofs
by induction over _data_ (i.e., where the thing we're doing
induction on lives in [Type]) and one for proofs by induction over
_evidence_ (i.e., where the inductively defined thing lives in
[Prop]). In the rest of this course, please follow one of the two
for _all_ of your inductive proofs. *)
(** ここまで、我々は「帰納法を使った形式的な証明の舞台裏」を覗くことにずいぶん章を割いてきました。そろそろ「帰納法を使った非形式的な証明」に話を向けてみましょう。
現実世界の数学的な事柄をやりとりするた記述された証明を見てみると、極端に風呂敷が広く衒学的なものから、逆に短く簡潔すぎるものまで様々です。理想的なものはその間のとこかにあります。もちろん、じぶんなりのスタイルを見つけるまでは、衒学的なスタイルから始めてみるほうがいいでしょう。また、学習中には、標準的なテンプレートと比較してみることも、学習の一助になるでしょう。
このような考えから、我々は以下の二つのテンプレートを用意しました。一つは「データ」に対して（「型」に潜む帰納的な構造について）帰納法を適用したもの、もう一つは「命題」に対して（命題に潜む機能的な定義について）帰納法を適用したものです。このコースが終わるまでに、あなたが行った帰納的な証明の全てに、どちらかの方法を適用してみましょう。
*)
(* *** Induction Over an Inductively Defined Set *)
(** *** 帰納的に定義された集合についての帰納法 *)
(* _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if length [[] = n], then [index (S n) [] =
None].
This follows immediately from the definition of index.
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
[[
length l = length (x::l') = S (length l'),
]]
it suffices to show that
[[
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be length [l']. [] *)
(** _Template_:
- 定理: < "For all [n:S], [P(n)],"の形で全量子化された命題。ただし [S] は帰納的に定義された集合。>
証明: [n] についての帰納法で証明する。
<集合 [S] の各コンストラクタ [c] について...>
- [n = c a1 ... ak] と仮定して、<...もし必要なら [S] のそれぞれの要素 [a] についてIHであることをを示す。>ならば
<...ここで再び [P(c a1 ... ak)] を示す> である。
< [P(n)] を証明してこのケースを終わらせる...>
- <他のケースも同様に記述する...> []
_Example_:
- _Theorem_: 任意の集合 [X] 、リスト [l : list X]、 自然数 [n] について、
もし [length l = n] が成り立つなら、[index (S n) l = None] も成り立つ。
_Proof_: [l] についての帰納法で証明する。
- まず、[l = []] と仮定して、任意の [n] でこれが成り立つことを示す。もし length [[] = n] ならば [index (S n) [] = None] 。
これは index の定義から直接導かれる 。
- 次に、 [x] と [l'] において [l = x :: l'] と仮定して、任意の [n'] について
[length l' = n'] ならば [index (S n') l' = None] である時、任意の [n] について、
もし [length (x::l') = n] ならば [index (S n) (x::l') = None] を示す。
[n] を [length l = n] となるような数とすると、
[[
length l = length (x::l') = S (length l'),
]]
これは以下の十分条件である。
[[
index (S (length l')) l' = None.
]]
しかしこれは仮定法の仮定から直接導かれる。
[l'] の length となるような [n'] を選択すればよい。 [] *)
(* *** Induction Over an Inductively Defined Proposition *)
(** *** 帰納的に定義された命題についての帰納法 *)
(* Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
*)
(** 帰納的に定義された証明オブジェクトは、しばしば”導出木”と呼ばれるため、この形の証明は「導出による帰納法（ _induction on derivations_ ）」として知られています。
_Template_ :
- _Theorem_ : <"[Q -> P]," という形を持った命題。ただし [Q] は帰納的に定義された命題（さらに一般的には、"For all [x] [y] [z], [Q x y z -> P x y z]" という形の命題）>
_Proof_ : [Q] の導出による帰納法で証明する。 <もしくは、さらに一般化して、" [x], [y], [z]を仮定して、[Q x y z] ならば [P x y z] を示す。[Q x y z]の導出による帰納法によって"...>
<各コンストラクタ [c] による値 [Q] について...>
- [Q] が [c] であることを示した最後のルールを仮定して、
<...ここで [a] の全ての型をコンストラクタの定義にある等式と
共に示し、型 [Q] を持つ [a] がIHであることをそれぞれ示す。>
ならば <...ここで再び [P] を示す> である。
<がんばって [P] を証明し、このケースを閉じる...>
- <他のケースも同様に...> []
*)
(*
_Example_
- _Theorem_ : The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and the result is immediate.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= o]. [] *)
(**
_Example_
- _Theorem_ : [<=] という関係は推移的である -- すなわち、任意の
数値 [n], [m], [o] について、もし [n <= m] と [m <= o] が成り立つ
ならば [n <= o] である。
_Proof_ : [m <= o] についての帰納法で証明する。
- [m <= o] が [le_n] であることを示した最後のルールを仮定する。
それにより [m = o] であることとその結果が直接導かれる。
- [m <= o] が [le_S] であることを示した最後のルールを仮定する。
それにより [m <= o'] を満たす [o'] について [o = S o'] が成り立つ。
帰納法の仮定法より [n <= o'] である。
従って[le_S] より [n <= o] である。 [] *)
(* 2014-03-xx たぶんこのあたりまで *)
(* 2014-04-19 たぶんこのあたりから *)
(* ##################################################### *)
(* * Optional Material *)
(** * 選択課題 *)
(* This section offers some additional details on how induction works
in Coq. It can safely be skimmed on a first reading. (We
recommend skimming rather than skipping over it outright: it
answers some questions that occur to many Coq users at some point,
so it is useful to have a rough idea of what's here.) *)
(** この項では、Coq において帰納法がどのように機能しているか、もう少し詳しく示していきたいと思います。
最初にこの項を読むときは、全体を読み流す感じでもかまいません（完全に
読み飛ばすのではなく、概要だけでも眺めてください。ここに書いてあることは、
多くの Coq ユーザーにとって、概要だけでも頭に入れておくことで、いつか直面する問題に
対する回答となりえるものです。） *)
(* ##################################################### *)
(* ** More on the [induction] Tactic *)
(** ** [induction] タクティックについてもう少し *)
(* The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in the proof above that [plus] is associative...
*)
(** [induction] タクティックは、実はこれまで見てきたような、いささか
低レベルな作業をこなすだけのものではありません。
自然数に関する帰納的な公理の非形式的な記述を思い出してみてください。:
- もし [P n] が数値 n を意味する何かの命題だとして、命題 P が全ての数値 n に
ついて成り立つことを示したい場合は、このような推論を
することができます。:
- [P O] が成り立つことを示す
- もし [P n'] が成り立つなら, [P (S n')] が成り立つことを示す。
- 任意の n について [P n] が成り立つと結論する。
我々が証明を [intros n] で始め、次に [induction n] とすると、
これはCoqに「特定の」 [n] について（それを仮定取り込むことで）考えて
から、その後でそれを帰納法を使って任意の数値にまで推し進めるよう
示していることになります。
このようなときに Coq が内部的に行っていることは、帰納法を適用した変数を
「再一般化（ _re-generalize_ ）」することです。
例えば、[plus] の結合則を証明するケースでは、
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
(** ...最初に 3個の変数を全てコンテキストに導入しています。
これはつまり"任意の [n], [m], [p] について考える"という
意味になっています... *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
(** ...ここで、[induction] タクティックを使い [P n] （任意の [n] に
ついて [n + (m + p) = (n + m) + p]）を証明し、すぐに、
コンテキストにある特定の [n] についても証明します。 *)
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
(** [induction] が作成した（帰納法の手順とも言うべき）二つ目の
ゴールでは、 [P n'] ならば任意の [n'] で [P (S n')] が成り立つ
ことを証明する必要があります。 この時に [induction] タクティックは
[P (S n')] をゴールにしたまま、自動的に [n'] と [P n'] を
コンテキストに導入してくれます。
*)
simpl. rewrite -> IHn'. reflexivity. Qed.
(* It also works to apply [induction] to a variable that is
quantified in the goal. *)
(** [induction] をゴールにある量化された変数に適用してもかまいません。 *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
Case "n = O". intros m. rewrite -> plus_0_r. reflexivity.
Case "n = S n'". intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(* Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
(** [induction n] が [m] をゴールに残したままにしていることに注目してください。
つまり、今証明しようとしている帰納的な性質は、[forall m] で表されて
いるということです。
もし [induction] をゴールにおいて量化された変数に対して他の量化子の後に
適用すると、[induction] タクティックは自動的に変数をその量化子に基づいて
コンテキストに導入します。 *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
(** ここで [n] の代わりに [m] を induction しましょう。... *)
induction m as [| m'].
Case "m = O". simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** 練習問題: ★, optional (plus_explicit_prop) *)
(* Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(** [plus_assoc'] と [plus_comm'] を、その証明とともに上の [mult_0_r''] と
同じスタイルになるよう書き直しなさい。このことは、それぞれの定理が
帰納法で証明された命題に明確な定義を与え、この定義された命題から定理と
証明を示しています。 *)
Definition P_plus_assoc : nat -> nat -> nat -> Prop :=
fun n m p => n + (m + p) = (n + m) + p.
Theorem plus_assoc'' : forall n m p : nat,
P_plus_assoc n m p.
Proof.
unfold P_plus_assoc.
intros n m p.
induction n as [| n'].
Case "n = 0".
simpl.
reflexivity.
Case "n = S n'".
simpl.
rewrite -> IHn'.
reflexivity.
Qed.
Theorem plus_assoc''' : forall n m p : nat,
P_plus_assoc n m p.
Proof.
unfold P_plus_assoc.
intros n.
Print nat_ind.
apply nat_ind with (n:=n).
intros.
simpl.
reflexivity.
intros.
simpl.
Admitted.
(* FILL IN HERE *)
(** [] *)
(* ##################################################### *)
(* One more quick digression, for adventurous souls: if we can define
parameterized propositions using [Definition], then can we also
define them using [Fixpoint]? Of course we can! However, this
kind of "recursive parameterization" doesn't correspond to
anything very familiar from everyday mathematics. The following
exercise gives a slightly contrived example. *)
(** 冒険心を満足させるために、もう少し脱線してみましょう。
[Definition] でパラメータ化された命題を定義できるなら、 [Fixpoint] でも
定義できていいのではないでしょうか？もちろんできます！しかし、この種の
「再帰的なパラメータ化」は、日常的に使われる数学の分野と必ずしも調和するわけでは
ありません。そんなわけで次の練習問題は、例としてはいささか不自然かもしれません。
*)
(* **** Exercise: 4 stars, optional (true_upto_n__true_everywhere) *)
(** **** 練習問題: ★★★★, optional (true_upto_n__true_everywhere) *)
(* Define a recursive function
[true_upto_n__true_everywhere] that makes
[true_upto_n_example] work. *)
(** [true_upto_n_example] を満たすような再帰関数 [true_upto_n__true_everywhere]
を定義しなさい。
*)
Fixpoint true_upto_n__true_everywhere (n : nat) (f : nat -> Prop) :=
match n with
| 0 => forall m, f m
| S n' => f n -> true_upto_n__true_everywhere n' f
end.
Example true_upto_n_example :
(true_upto_n__true_everywhere 3 (fun n => even n))
= (even 3 -> even 2 -> even 1 -> forall m : nat, even m).
Proof. reflexivity. Qed.
(* ちゃんと復習する 2014-04-19 *)
(** [] *)
(* ##################################################### *)
(* ** Induction Principles in [Prop] *)
(** ** [Prop] における帰納法の原理 *)
(* Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction principles
for inductively defined _propositions_ like [ev] are a tiny bit
more complicated. As with all induction principles, we want to use
the induction principle on [ev] to prove things by inductively
considering the possible shapes that something in [ev] can have --
either it is evidence that [0] is even, or it is evidence that,
for some [n], [S (S n)] is even, and it includes evidence that [n]
itself is. Intuitively speaking, however, what we want to prove
are not statements about _evidence_ but statements about _numbers_.
So we want an induction principle that lets us prove properties of
numbers by induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [ev]...
[[
Inductive ev : nat -> Prop :=
| ev_0 : ev O
| ev_SS : forall n:nat, ev n -> ev (S (S n)).
]]
...to give rise to an induction principle that looks like this...
[[
ev_ind_max :
forall P : (forall n : nat, ev n -> Prop),
P O ev_0 ->
(forall (n : nat) (e : ev n),
P n e -> P (S (S n)) (ev_SS n e)) ->
forall (n : nat) (e : ev n), P n e
]]
... because:
- Since [ev] is indexed by a number [n] (every [ev] object
[e] is a piece of evidence that some particular number [n]
is even), the proposition [P] is parameterized by both [n]
and [e] -- that is, the induction principle can be used to
prove assertions involving both an even number and the
evidence that it is even.
- Since there are two ways of giving evidence of evenness
([ev] has two constructors), applying the induction
principle generates two subgoals:
- We must prove that [P] holds for [O] and [ev_0].
- We must prove that, whenever [n] is an even number and
[e] is evidence of its evenness, if [P] holds of [n]
and [e], then it also holds of [S (S n)] and [ev_SS n
e].
- If these subgoals can be proved, then the induction
principle tells us that [P] is true for _all_ even numbers
[n] and evidence [e] of their evenness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
evenness, while all we really care about is proving properties of
_numbers_ that are even -- we are interested in assertions about
numbers, not about evidence. It would therefore be more convenient
to have an induction principle for proving propositions [P] that
are parameterized just by [n] and whose conclusion establishes [P]
for all even numbers [n]:
[[
forall P : nat -> Prop,
... ->
forall n : nat, ev n -> P n
]]
For this reason, Coq actually generates the following simplified
induction principle for [ev]: *)
(** 最初のほうで、我々は帰納的に定義された「集合」に対して、Coqが生成する
帰納法の原理をつぶさに見てきました。[ev] のように、帰納的に定義された
「命題」の帰納法の原理は、やや複雑でした。これらに共通して言えることですが、
これらを [ev] の証明に使おうとする際、帰納的な発想のもとで [ev] が持ちうる
ものの中から使えそうな形になっているものを探します。それは [0] が偶数であることの
根拠であったり、ある [n] について [S (S n)] は偶数であるという根拠（もちろん、
これには [n] 自身が偶数であるということの根拠も含まれていなければ
なりませんが）だったりするでしょう。しかしながら直観的な言い方をすると、
我々が証明したいものは根拠についての事柄ではなく、数値についての事柄です。
つまり、我々は根拠をベースに数値の属性を証明できるような帰納法の原理を
必要としているわけです。
例えば、ずいぶん前にお話ししたように、[ev] の帰納的な定義は、
こんな感じで...
[[
Inductive ev : nat -> Prop :=
| ev_0 : ev O
| ev_SS : forall n:nat, ev n -> ev (S (S n)).
]]
... ここから生成される帰納法の原理はこんな風になります ...
[[
ev_ind_max :
forall P : (forall n : nat, ev n -> Prop),
P O ev_0 ->
(forall (n : nat) (e : ev n),
P n e -> P (S (S n)) (ev_SS n e)) ->
forall (n : nat) (e : ev n), P n e
]]
... なぜなら：
- [ev] は数値 [n] でインデックスされている（ [ev] に属するオブジェクト [e] は、いずれも特定の数 [n] が偶数であることの根拠となっている）ため、この命題 [P] は [n] と[e] の両方でパラメータ化されている。-- つまり、この帰納法の原理は一つの偶数と、それが偶数であることの根拠が揃っているような主張の証明に使われる。
- 偶数であることに根拠を与える方法は二つある（ [ev] のコンストラクタは二つある）ので、帰納法の原理を適用すると、二つのゴールが生成されます。:
- [P] が [O] と [ev_0] で成り立つことを証明する必要がある。
- [n] が偶数で [e] がその偶数性の根拠であるとき、もし [P] が [n] と [e] のもとで成り立つなら、[S (S n)] と [ev_SS n e] のもとで成り立つことを証明する必要がある。
- もしこれらのサブゴールが証明できれば、この帰納法の原理によって [P] が全ての偶数 [n] とその偶数性の根拠 [e] のもとで真であることが示される。
しかしこれは、私たちが求めたり必要としているものより少しだけ柔軟にできていて、偶数性の根拠の断片を属性として含むような論理的主張を証明する方法を与えてくれます。我々の興味の対象は「数値の属性が偶数である」ことの証明なのですから、その興味の対象も数値に関する主張であって、根拠に対するものではないはずです。これにより、単に [n] だけでパラメータ化されていて、[P] がすべての偶数 [n] で成り立つことを示せるような命題 [P] を証明する際に帰納法の原理を得ることがより楽になります。
[[
forall P : nat -> Prop,
... ->
forall n : nat, ev n -> P n
]]
このような理由で、Coqは実際には [ev] のために次のような帰納法の原理を生成します。: *)
Print ev.
Inductive ev' : nat -> Prop :=
| ev_0' : ev' 0
| ev_SS' : forall n : nat, ev' n -> ev' (S (S n)).
Check ev'_ind. (* _indが自動的にできることの確認 *)
Check ev_ind.
(* ===> ev_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, ev n -> P n -> P (S (S n))) ->
forall n : nat, ev n -> P n *)
(* In particular, Coq has dropped the evidence term [e] as a parameter
of the the proposition [P], and consequently has rewritten the
assumption [forall (n:nat) (e:ev n), ...] to be [forall (n:nat), ev
n -> ...]; i.e., we no longer require explicit evidence of the
provability of [ev n]. *)
(** Coqが根拠の式 [e] を、命題 [P] のパラメータから取り去っていることに注目してください。
その結果として、仮定 [forall (n:nat) (e:ev n), ...] を [forall (n:nat), ev
n -> ...] に書き換えています。すなわち、我々はすでに [ev n] から証明可能であることの
明白な根拠を求められていないのです。 *)
(* In English, [ev_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P
n] is a [Prop] for every [n]). To show that [P n] holds
whenever [n] is even, it suffices to show:
- [P] holds for [0]
- for any [n], if [n] is even and [P] holds for [n],
then [P] holds for [S (S n)]. *)
(** [ev_ind] を自然言語で書き直すと、
- [P] が自然数の属性である（つまり、[P] が全ての [n] についての命題である）と仮定し、[P n] が偶数の場合常に成り立つことを示す。これは、以下を示すのに十分である。:
- [P] が [0] において成り立つ。
- 全ての [n] において、もし [n] が偶数で [P] が [n] において成り立つなら、[P] は [S (S n)] においても成り立つ。 *)
(* We can apply [ev_ind] directly instead of using [induction],
following pretty much the same pattern as above. *)
(** [induction] とする代わりに [ev_ind] を直接 apply することもできます。
以下は、これと同じパターンです。 *)
Theorem ev_even' : forall n,
ev n -> even n.
Proof.
apply ev_ind.
Case "ev_0". unfold even. reflexivity.
Case "ev_SS". intros n' E' IHE'. unfold even. apply IHE'. Qed.
(* apply IHE'のところがよくわからない 2014-04-19 *)
(* **** Exercise: 3 stars, optional (prop_ind) *)
(** **** 練習問題: ★★★, optional (prop_ind) *)
(* Write out the induction principles that Coq will generate for the
inductive declarations [list] and [MyProp]. Compare your answers
against the results Coq prints for the following queries. *)
(** 帰納的に定義された [list] と [MyProp] に対し、Coq がどのような帰納法の原理を
生成するか、予想して書き出し、次の行を実行した結果と比較しなさい。 *)
Print list.
(*
forall (X : Type) (P : list -> Prop),
P [] -> (forall (x : X) (l : list X), P l -> P (x :: l)) -> forall (l : list X), P l
*)
Check list_ind.
Print MyProp.
(*
forall (n : nat) (P : nat -> Prop),
P 4 -> (forall (n : nat), MyProp n -> P n -> P (4 + n))
途中
*)
Check MyProp_ind.
(** [] *)
(* **** Exercise: 3 stars, optional (ev_MyProp') *)
(** **** 練習問題: ★★★, optional (ev_MyProp') *)
(* Prove [ev_MyProp] again, using [apply MyProp_ind] instead
of the [induction] tactic. *)
(** もう一度 [ev_MyProp] を証明しなさい。ただし、今度は [induction] タクティックの代わりに
[apply MyProp_ind] を使いなさい。 *)
Theorem ev_MyProp' : forall n:nat,
MyProp n -> ev n.
Proof.
apply MyProp_ind.
apply (ev_SS 2 (ev_SS 0 (ev_0))).
intros n M1 ev_n.
apply ev_SS.
apply ev_SS.
apply ev_n.
SearchAbout MyProp.
intros n M1 ev_2n.
apply ev_minus2 in ev_2n.
exact ev_2n.
Qed.
(** [] *)
(* **** Exercise: 4 stars, optional (MyProp_pfobj) *)
(** **** 練習問題: ★★★★, optional (MyProp_pfobj) *)
(* Prove [MyProp_ev] and [ev_MyProp] again by constructing
explicit proof objects by hand (as you did above in
[ev_plus4], for example). *)
(** もう一度 [MyProp_ev] と [ev_MyProp] を証明しなさい。ただし今度は、明確な
証明オブジェクトを手作業で構築（上の [ev_plus4] でやったように）することで
証明しなさい。 *)
Print MyProp_ev.
Print ev_MyProp.
(* FILL IN HERE *)
(** [] *)
Module P.
(* **** Exercise: 3 stars, optional (p_provability) *)
(** **** 練習問題: ★★★, optional (p_provability) *)
(* Consider the following inductively defined proposition: *)
(** 次の、帰納的に定義された命題について考えてみてください。： *)
Inductive p : (tree nat) -> nat -> Prop :=
| c1 : forall n, p (leaf _ n) 1
| c2 : forall t1 t2 n1 n2,
p t1 n1 -> p t2 n2 -> p (node _ t1 t2) (n1 + n2)
| c3 : forall t n, p t n -> p t (S n).
(* Describe, in English, the conditions under which the
proposition [p t n] is provable.
(* FILL IN HERE *)
*)
(** これについて、どのような時に [p t n] が証明可能であるか、その
条件をを自然言語で説明しなさい。
(* FILL IN HERE *)
*)
(** [] *)
Print tree.
Fixpoint leaves (t : tree nat) :=
match t with
| leaf _ => 1
| node t1 t2 => leaves t1 + leaves t2
end.
Theorem p_correct : forall (t : tree nat) (n : nat),
p t n -> ble_nat (leaves t) n = true.
Proof.
Admitted.
End P.
(* ####################################################### *)
(* * Additional Exercises *)
(** * 追加練習問題 *)
(* **** Exercise: 4 stars (palindromes) *)
(** **** 練習問題: ★★★★ (palindromes) *)
(* A palindrome is a sequence that reads the same backwards as
forwards.
- Define an inductive proposition [pal] on [list X] that
captures what it means to be a palindrome. (Hint: You'll need
three cases. Your definition should be based on the structure
of the list; just having a single constructor
[[
c : forall l, l = rev l -> pal l
]]
may seem obvious, but will not work very well.)
- Prove that
[[
forall l, pal (l ++ rev l).
]]
- Prove that
[[
forall l, pal l -> l = rev l.
]]
*)
(** palindrome（回文）は、最初から読んでも逆から読んでも同じになるような
シーケンスです。
- [list X] でパラメータ化され、それが palindrome であることを示すような帰納的
命題 [pal] を定義しなさい。（ヒント：これには三つのケースが必要です。この定義は、
リストの構造に基いたものとなるはずです。まず一つのコンストラクタ、
[[
c : forall l, l = rev l -> pal l
]]
は明らかですが、これはあまりうまくいきません。）
- 以下を証明しなさい。
[[
forall l, pal (l ++ rev l).
]]
- 以下を証明しなさい。
[[
forall l, pal l -> l = rev l.
]]
*)
Inductive pal { X : Type } : list X -> Prop :=
| pal0 : pal []
| pal1 : forall x:X, pal [x]
| pal2 : forall (x:X) (l : list X), pal l -> pal (x :: (snoc l x)).
(* | pal2 : forall (x:X) (l:list X), l = rev l -> pal (x :: (snoc l x)). *)
Theorem pal_l_app : forall (X:Type) (l:list X),
pal (l ++ rev l).
Proof.
Admitted.
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 5 stars, optional (palindrome_converse) *)
(** **** 練習問題: ★★★★★, optional (palindrome_converse) *)
(* Using your definition of [pal] from the previous exercise, prove
that
[[
forall l, l = rev l -> pal l.
]]
*)
(** 一つ前の練習問題で定義した [pal] を使って、これを証明しなさい。
[[
forall l, l = rev l -> pal l.
]]
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 4 stars (subsequence) *)
(** **** 練習問題: ★★★★ (subsequence) *)
(* A list is a _subsequence_ of another list if all of the elements
in the first list occur in the same order in the second list,
possibly with some extra elements in between. For example,
[[
[1,2,3]
]]
is a subsequence of each of the lists
[[
[1,2,3]
[1,1,1,2,2,3]
[1,2,7,3]
[5,6,1,9,9,2,7,3,8]
]]
but it is _not_ a subsequence of any of the lists
[[
[1,2]
[1,3]
[5,6,2,1,7,3,8]
]]
- Define an inductive proposition [subseq] on [list nat] that
captures what it means to be a subsequence. (Hint: You'll need
three cases.)
- Prove that subsequence is reflexive, that is, any list is a
subsequence of itself.
- Prove that for any lists [l1], [l2], and [l3], if [l1] is a
subsequence of [l2], then [l1] is also a subsequence of [l2 ++
l3].
- (Optional, harder) Prove that subsequence is transitive -- that
is, if [l1] is a subsequence of [l2] and [l2] is a subsequence
of [l3], then [l1] is a subsequence of [l3]. Hint: choose your
induction carefully!
*)
(** あるリストが、別のリストのサブシーケンス（ _subsequence_ ）であるとは、
最初のリストの要素が全て二つ目のリストに同じ順序で現れるということです。
ただし、その間に何か別の要素が入ってもかまいません。例えば、
[[
[1,2,3]
]]
は、次のいずれのリストのサブシーケンスでもあります。
[[
[1,2,3]
[1,1,1,2,2,3]
[1,2,7,3]
[5,6,1,9,9,2,7,3,8]
]]
しかし、次のいずれのリストのサブシーケンスでもありません。
[[
[1,2]
[1,3]
[5,6,2,1,7,3,8]
]]
- [list nat] 上に、そのリストがサブシーケンスであることを意味するような命題 [subseq] を定義しなさい。（ヒント：三つのケースが必要になります）
- サブシーケンスである、という関係が「反射的」であることを証明しなさい。つまり、どのようなリストも、それ自身のサブシーケンスであるということです。
- 任意のリスト [l1]、 [l2]、 [l3] について、もし [l1] が [l2] のサブシーケンスならば、 [l1] は [l2 ++ l3] のサブシーケンスでもある、ということを証明しなさい。.
- （これは少し難しいですので、任意とします）サブシーケンスという関係は推移的である、つまり、 [l1] が [l2] のサブシーケンスであり、 [l2] が [l3] のサブシーケンスであるなら、 [l1] は [l3] のサブシーケンスである、というような関係であることを証明しなさい。（ヒント：何について帰納法を適用するか、よくよく注意して下さい。）
*)
(*
Inductive subseq : list nat -> list nat -> Prop :=
| s1 : forall l, subseq [] l
| s2 : forall x l1 l2, subseq l1 l2 -> subseq l1 (x::l2)
| s3 : forall x l1 l2, subseq l1 l2 -> subseq (x::l1) (x::l2).
(* 反射律 *)
Theorem subseq_refl : forall l,
subseq l l.
Proof.
Admitted.
Theorem subseq_app : forall (X : Type) (l1 l2 l3 : list X),
subseq l1 l2 -> subseq l1 (l2 ++ l3).
Proof.
Admitted.
Theorem subseq_trans : forall (X : Type) (l1 l2 l3 : list X),
subseq l1 l2 -> subseq l2 l3 -> subseq l1 l3.
Proof.
intros X l1 l2 l3 H12 H23.
generalize dependent l2.
generalize dependent l1.
induction l3.
(* constructor. assumption. *)
Admitted.
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** **** 練習問題: ★★, optional (foo_ind_principle) *)
(* Suppose we make the following inductive definition:
[[
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
]]
Fill in the blanks to complete the induction principle that will be
generated by Coq.
[[
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
]]
*)
(** 次のような、帰納的な定義をしたとします：
[[
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
]]
次の空欄を埋め、この定義のために Coq が生成する帰納法の原理を完成させなさい。
[[
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
]]
*)
(*
foo_ind :
forall (X Y : Set) (P : foo X Y -> Prop), (* インデックスとしてSetが必要 *)
(forall x : X, P (foo1 X Y x)) -> (* foo1にパラメータX Yがつく *)
(forall y : Y, P (foo2 X Y y)) -> (* foo2にパラメータX Yがつく *)
(forall f1 : foo X Y, P f -> P (foo3 X Y f1)) -> (* foo3にパラメータX Yがつく *)
forall f2 : foo X Y, P f2 (* すべてのf : foo X YについてPが成立 *)
*)
Inductive foo'' (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo'' X Y
| foo2 : Y -> foo'' X Y
| foo3 : foo'' X Y -> foo'' X Y.
Check foo''_ind.
(** [] *)
(** **** 練習問題: ★★, optional (bar_ind_principle) *)
(* Consider the following induction principle:
[[
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
]]
Write out the corresponding inductive set definition.
[[
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
]]
*)
(** 次に挙げた帰納法の原理について考えてみましょう：
[[
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
]]
これに対応する帰納的な集合の定義を書きなさい。
[[
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
]]
*)
Inductive bar' : Set :=
| bar1 : nat -> bar'
| bar2 : bar' -> bar'
| bar3 : bool -> bar' -> bar'.
Check bar'_ind.
(** [] *)
(* **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** **** 練習問題: ★★, optional (no_longer_than_ind) *)
(* Given the following inductively defined proposition:
[[
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
]]
write the induction principle generated by Coq.
[[
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
]]
*)
(** 次のような、帰納的に定義された命題が与えられたとします：
[[
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
]]
この命題のために Coq が生成する帰納法の原理を完成させなさい。
[[
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
]]
*)
(*
no_longer_than_ind :
forall (X : Set) (P : list X -> nat -> Prop),
(* nlt_nil *) (forall n : nat, P [] n) ->
(* nlt_cons *) (forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> P l n -> P (x :: l) (S n)) ->
(* nlt_succ *) (forall (l : list X) (n : nat),
no_longer_than X l n -> P l n -> P l (S n)) ->
forall (l : list X) (n : nat), no_longer_than X l n -> P l n.
*)
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
Check no_longer_than_ind.
(** [] *)
(* **** Exercise: 2 stars, optional (R_provability) *)
(** **** 練習問題: ★★, optional (R_provability) *)
(* Suppose we give Coq the following definition:
[[
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
]]
Which of the following propositions are provable?
- [R 2 [1,0]]
- [R 1 [1,2,1,0]]
- [R 6 [3,2,1,0]]
*)
(** Coq に次のような定義を与えたとします：
[[
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
]]
次のうち、証明可能なのはどの命題でしょうか？
- [R 2 [1,0]]
- [R 1 [1,2,1,0]]
- [R 6 [3,2,1,0]]
*)
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
Lemma Q1_OK : R 2 [1,0].
Proof.
apply c2.
apply c2.
apply c1.
Qed.
Lemma Q2_OK : R 1 [1,2,1,0].
Proof.
apply c3.
apply c2.
apply c3.
apply c3.
apply c2.
apply c2.
apply c2.
apply c1.
Qed.
Lemma Q3_OK : R 6 [3,2,1,0].
Proof.
Admitted.
(** [] *)
|
`timescale 1ns / 1ps
module data_memory_controll
#(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter SDRAM_DATA_WIDTH = 32,
parameter SDRAM_ADDR_WIDTH = 20,
parameter SDRAM_DQM_WIDTH = 4,
parameter SDRAM_BA_WIDTH = 2,
parameter SDRAM_CLOCK = 25
)
(/*autoport*/
input clk,
input rst_n,
// input enable, //removed the clock gate
input data_rd_en,
input data_wr_en,
input [ADDR_WIDTH-1:0] data_addr,
output reg [DATA_WIDTH-1:0] data_out,
input [DATA_WIDTH-1:0] data_in,
output reg data_out_valid,
output reg bus_busy,
//SDRAM
input [SDRAM_DATA_WIDTH-1:0] dram_dq_in, // sdram data bus 16 bits
output [SDRAM_DATA_WIDTH-1:0] dram_dq_out, // sdram data bus 16 bits
output reg [SDRAM_ADDR_WIDTH-1:0] dram_addr, // sdram address bus 12 bits
output reg [SDRAM_DQM_WIDTH-1:0] dram_dqm, // sdram data mask
output reg dram_we_n, // sdram write enable
output reg dram_cas_n, // sdram column address strobe
output reg dram_ras_n, // sdram row address strobe
output reg dram_cs_n, // sdram chip select
output reg [SDRAM_BA_WIDTH-1:0] dram_ba, // sdram bank address
output dram_clk, // sdram clock
output reg dram_cke // sdram clock enable
);
//*******************************************************
//Internal
//*******************************************************
//Local Parameters
//SDRAM fixed configuration
localparam BURST_LENGH = 3'd0; //burst lenght
localparam BURST_TYPE = 2'd0; //burst type
localparam LATENCY_MODE = 3'b010; //latency mode
localparam OPERATION_MODE = 2'b00; //operation mode
localparam WRITE_OPERATION_MODE = 1'b1; //write operation mode
localparam CAS_LATENCY = 2;
localparam READ_LATENCY = 3;
localparam WRITE_LATENCY = 3;
localparam ACTIVATE_LATENCY = 2;
localparam PRECHARGE_LATENCY = 1;
localparam INIT_LATENCY = 16;
localparam NOP_CMD = 1,
READ_CMD = 2,
WRITE_CMD = 3,
PRECHARGE_CMD = 4,
ACTIVATE_CMD = 0,
INIT_CMD = 6,
AUTO_REFRESH_CMD = 5,
PRECHARGE_ALL_CMD = 7,
MODE_REGISTER_CMD = 8,
SELF_REFRESH_CMD = 9,
SELF_REFRESH_EXIT_CMD = 10,
READ_AUTO_CMD = 1,
WRITE_AUTO_CMD = 11;
localparam SDRAM_COMMAND_WIDTH = 4;
localparam STATE_WIDTH = 4;
localparam INITIALIZE_SDRAM = 0,
LOAD_MODE_REGISTER = 1,
IDLE = 2,
READ_DATA = 3,
WRITE_DATA = 4,
ACTIVATE_BANK = 5,
PRECHARGE = 6,
READ_DATA_ACT = 7,
WRITE_DATA_ACT = 8;
localparam COUNT_WIDTH = 5;
//Wires
wire [12:0] row_address;
wire [1:0] bank_address;
wire [9:0] col_address;
//Registers
reg [SDRAM_COMMAND_WIDTH-1:0] sdram_command;
reg [COUNT_WIDTH-1:0] count_state; // atualizar depois
//*******************************************************
//General Purpose Signals
//*******************************************************
reg [STATE_WIDTH-1:0] state,
next_state;
reg data_rd_en_reg;
reg data_wr_en_reg;
reg [ADDR_WIDTH-1:0] data_addr_reg;
reg [DATA_WIDTH-1:0] data_in_reg;
//IS4216320B
assign bank_address = data_addr_reg[13:12];
assign row_address = data_addr_reg[26:14];
assign col_address = data_addr_reg[11:2];
//MT48LC8M16A2
//assign bank_address = data_addr_reg[12:11]; //2
//assign row_address = data_addr_reg[24:13]; //12
//assign col_address = data_addr_reg[10:2]; //9
//assign bank_address = data_addr_reg[12:11];
//assign row_address = data_addr_reg[10:1];
//assign col_address = {1'b0, data_addr_reg[0]};
assign dram_dq_out = data_in_reg;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_addr_reg <= {ADDR_WIDTH{1'b0}};
data_in_reg <= {DATA_WIDTH{1'b0}};
end
else if ((state == IDLE) && (data_rd_en || data_wr_en)) begin
data_addr_reg <= data_addr;
data_in_reg <= data_in;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= INITIALIZE_SDRAM;
end
else begin
state <= next_state;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_rd_en_reg <= 1'b0;
data_wr_en_reg <= 1'b0;
end
else begin
if (state == IDLE) begin
data_rd_en_reg <= data_rd_en;
data_wr_en_reg <= data_wr_en;
end
else if ((state == PRECHARGE)&& (count_state == 0)) begin
data_rd_en_reg <= 1'b0;
data_wr_en_reg <= 1'b0;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_out_valid <= 1'b0;
data_out <= {DATA_WIDTH{1'b0}};
end
else begin
if ((state == READ_DATA ) && count_state == 1) begin
data_out_valid <= 1'b1;
data_out <= dram_dq_in;
end
else begin
data_out_valid <= 1'b0;
end
end
end
always @(*) begin
if (state == IDLE)
bus_busy = 1'b0;
else begin
bus_busy = 1'b1;
end
end
always @(*) begin
next_state = state;
sdram_command = NOP_CMD;
case (state)
INITIALIZE_SDRAM: begin
if (count_state == 0)
sdram_command = NOP_CMD;
else if (count_state == 5'd1)
sdram_command = PRECHARGE_ALL_CMD;
else if (count_state == 5'd2)
sdram_command = AUTO_REFRESH_CMD;
else if (count_state == 5'd3)
sdram_command = NOP_CMD;
else if (count_state == 5'd4)
sdram_command = AUTO_REFRESH_CMD;
else if (count_state == 5'd5)
sdram_command = NOP_CMD;
else if (count_state == 5'd6)
sdram_command = AUTO_REFRESH_CMD;
else if (count_state == 5'd7)
sdram_command = NOP_CMD;
else if (count_state == 5'd8)
sdram_command = AUTO_REFRESH_CMD;
else if (count_state == 5'd9)
sdram_command = NOP_CMD;
else if (count_state == 5'd10)
sdram_command = AUTO_REFRESH_CMD;
else if (count_state == 5'd11)
sdram_command = NOP_CMD;
else if (count_state == 5'd12)
sdram_command = AUTO_REFRESH_CMD;
else if (count_state == 5'd13)
sdram_command = NOP_CMD;
else if (count_state == 5'd14)
sdram_command = AUTO_REFRESH_CMD;
else if (count_state == 5'd15)
sdram_command = NOP_CMD;
else if (count_state == 5'd16) begin
sdram_command = AUTO_REFRESH_CMD;
next_state = LOAD_MODE_REGISTER;
end
end
LOAD_MODE_REGISTER: begin
sdram_command = MODE_REGISTER_CMD;
next_state = IDLE;
end
IDLE: begin
sdram_command = NOP_CMD;
if (data_rd_en || data_wr_en_reg) begin
next_state = ACTIVATE_BANK;
end
end
ACTIVATE_BANK: begin
if (count_state == 5'd0)
sdram_command = ACTIVATE_CMD;
else if (count_state == ACTIVATE_LATENCY) begin
if (data_rd_en_reg) begin
next_state = READ_DATA;
end
else begin
next_state = WRITE_DATA;
end
end
else
sdram_command = NOP_CMD;
end
WRITE_DATA: begin
if (count_state == 5'd0)
sdram_command = WRITE_CMD;
else if (count_state == WRITE_LATENCY) begin
next_state = PRECHARGE;
sdram_command = NOP_CMD;
end
else
sdram_command = NOP_CMD;
end
READ_DATA: begin
if (count_state == 5'd0)
sdram_command = READ_CMD;
else if (count_state == READ_LATENCY) begin
next_state = PRECHARGE;
sdram_command = NOP_CMD;
end
else
sdram_command = NOP_CMD;
end
PRECHARGE: begin
if (count_state == 5'd0)
sdram_command = PRECHARGE_CMD;
else if (count_state == PRECHARGE_LATENCY) begin
next_state = IDLE;
sdram_command = NOP_CMD;
end
else
sdram_command = NOP_CMD;
end
endcase
end
always @(*) begin
case (state)
READ_DATA: begin
if (sdram_command == READ_CMD)
dram_dqm = 4'b0000;
else begin
dram_dqm = 4'b1111;
end
end
WRITE_DATA: dram_dqm = 4'b0000;
default : dram_dqm = 4'b1111;
endcase
end
// cke, cs, cas, ras and we logic
always @(*) begin
case (sdram_command)
NOP_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b1;
dram_cas_n = 1'b1;
dram_we_n = 1'b1;
dram_ba = 2'b00; //dont care
dram_addr = {SDRAM_ADDR_WIDTH{1'b0}};//dont care
dram_cke = 1'b1;
end
READ_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b1;
dram_cas_n = 1'b0;
dram_we_n = 1'b1;
dram_ba = bank_address; //valid
dram_addr[12:11] = 0;//col_address; //valid
dram_addr[10] = 1'b0;
dram_addr[9:0] = col_address; //valid
dram_cke = 1'b1;
end
READ_AUTO_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b1;
dram_cas_n = 1'b0;
dram_we_n = 1'b1;
dram_ba = 2'b00; //valid
dram_addr[12:11] = 2'd0; //valid
dram_addr[10] = 1'b1;
dram_addr[9:0] = 10'd0; //valid
dram_cke = 1'b1;
end
WRITE_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b1;
dram_cas_n = 1'b0;
dram_we_n = 1'b0;
dram_ba = bank_address; //valid
dram_addr[12:11] = 0;//col_address; //valid
dram_addr[10] = 1'b0;
dram_addr[9:0] = col_address; //valid
dram_cke = 1'b1;
end
WRITE_AUTO_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b1;
dram_cas_n = 1'b0;
dram_we_n = 1'b0;
dram_ba = 2'b00; //valid
dram_addr[12:11] = 2'd0; //valid
dram_addr[10] = 1'b1;
dram_addr[9:0] = 10'd0; //valid
dram_cke = 1'b1;
end
//precharge all banks
PRECHARGE_ALL_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b0;
dram_cas_n = 1'b1;
dram_we_n = 1'b0;
dram_ba = 2'b00; //dont care
dram_addr[12:11] = 2'd0; //dont care
dram_addr[10] = 1'b1;
dram_addr[9:0] = 10'd0; //dont care
dram_cke = 1'b1;
end
//precharge selected bank
PRECHARGE_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b0;
dram_cas_n = 1'b1;
dram_we_n = 1'b0;
dram_ba = bank_address; //valid
dram_addr[12:11] = 2'd0; //dont care
dram_addr[10] = 1'b0;
dram_addr[9:0] = 10'd0; //dont care
dram_cke = 1'b1;
end
MODE_REGISTER_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b0;
dram_cas_n = 1'b0;
dram_we_n = 1'b0;
dram_ba = 2'b00; //dont care
dram_addr[2:0] = BURST_LENGH; //burst lenght
dram_addr[3] = BURST_TYPE; //burst type
dram_addr[6:4] = LATENCY_MODE; //latency mode
dram_addr[8:7] = OPERATION_MODE; //operation mode
dram_addr[9] = WRITE_OPERATION_MODE; //write operation mode
dram_addr[10] = 1'b0; //dont care
dram_cke = 1'b1;
end
ACTIVATE_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b0;
dram_cas_n = 1'b1;
dram_we_n = 1'b1;
dram_ba = bank_address; //valid
dram_addr[12:11] = col_address; //valid
dram_addr[10] = 1'b0;
dram_addr[12:0] = row_address; //valid
dram_cke = 1'b1;
end
AUTO_REFRESH_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b0;
dram_cas_n = 1'b0;
dram_we_n = 1'b1;
dram_ba = 2'b00; //valid
dram_addr = {SDRAM_ADDR_WIDTH {1'd0}}; // dont care
dram_cke = 1'b1;
end
SELF_REFRESH_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b0;
dram_cas_n = 1'b0;
dram_we_n = 1'b1;
dram_ba = 2'b00; //valid
dram_addr = {SDRAM_ADDR_WIDTH {1'd0}}; // dont care
dram_cke = 1'b0;
end
SELF_REFRESH_EXIT_CMD: begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b1;
dram_cas_n = 1'b1;
dram_we_n = 1'b1;
dram_ba = 2'b00; //valid
dram_addr = {SDRAM_ADDR_WIDTH {1'd0}}; // dont care
dram_cke = 1'b1;
end
default begin
dram_cs_n = 1'b0;
dram_ras_n = 1'b1;
dram_cas_n = 1'b1;
dram_we_n = 1'b1;
dram_ba = 2'b00; //dont care
dram_addr = {SDRAM_ADDR_WIDTH{1'b0}};//dont care
dram_cke = 1'b1;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count_state <= 5'd0;
end
else begin
case (state)
INITIALIZE_SDRAM: begin
if (count_state == INIT_LATENCY) begin
count_state <= 5'd0;
end
else begin
count_state <= count_state + 5'd1;
end
end
ACTIVATE_BANK: begin
if (count_state == ACTIVATE_LATENCY) begin
count_state <= 5'd0;
end
else begin
count_state <= count_state + 5'd1;
end
end
READ_DATA: begin
if (count_state == READ_LATENCY) begin
count_state <= 5'd0;
end
else begin
count_state <= count_state + 5'd1;
end
end
WRITE_DATA: begin
if (count_state == WRITE_LATENCY) begin
count_state <= 5'd0;
end
else begin
count_state <= count_state + 5'd1;
end
end
PRECHARGE: begin
if (count_state == PRECHARGE_LATENCY) begin
count_state <= 5'd0;
end
else begin
count_state <= count_state + 5'd1;
end
end
IDLE:
count_state <= 5'd0;
endcase
end
end
//*******************************************************
//Outputs
//*******************************************************
assign dram_clk = clk;
//*******************************************************
//Instantiations
//*******************************************************
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_SYMBOL_V
`define SKY130_FD_SC_HS__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_SYMBOL_V
|
/***************************************************************************************************
** fpga_nes/hw/src/ppu/ppu_spr.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Sprite PPU sub-block.
***************************************************************************************************/
`timescale 1ps / 1ps
module ppu_spr
(
input wire clk_in, // 100MHz system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable sprites
input wire ls_clip_in, // clip sprites in left 8 pixels
input wire spr_h_in, // select 8/16 pixel high sprites
input wire spr_pt_sel_in, // sprite palette table select
input wire [ 7:0] oam_a_in, // sprite ram address
input wire [ 7:0] oam_d_in, // sprite ram data in
input wire oam_wr_in, // sprite ram write enable
input wire [ 9:0] nes_x_in, // nes x coordinate
input wire [ 9:0] nes_y_in, // nes y coordinate
input wire [ 9:0] nes_y_next_in, // next line's nes y coordinate
input wire pix_pulse_in, // pulse signal one clock immediately before nes x changes
input wire [ 7:0] vram_d_in, // vram data in for pattern table reads
output wire [ 7:0] oam_d_out, // sprite ram data out
output wire overflow_out, // more than 8 sprites on one scanline in current frame
output wire [ 3:0] palette_idx_out, // final sprite palette index
output wire primary_out, // final sprite is the primary object (sprite 0)
output wire priority_out, // final sprite priority (foreground/background)
output reg [13:0] vram_a_out, // vram address bus for pattern table reads
output reg vram_req_out // indicates sprite block needs vram ownership
);
// OAM: Object Attribute Memory (256 entries, 4 bytes per entry)
//
// byte bits desc
// ---- ---- ----
// 0 7:0 scanline coordinate minus one of object's top pixel row.
// 1 7:0 tile index number. Bit 0 here controls pattern table selection when reg 0x2000[5]5 = 1.
// 2 0 palette select low bit
// 1 palette select high bit
// 5 object priority (> playfield's if 0; < playfield's if 1)
// 6 apply bit reversal to fetched object pattern table data
// 7 invert the 3/4-bit (8/16 scanlines/object mode) scanline address used to access an object
// tile
// 3 7:0 scanline pixel coordinate of most left-hand side of object.
reg [7:0] m_oam [255:0];
always @(posedge clk_in)
begin
if (oam_wr_in)
m_oam[oam_a_in] <= oam_d_in;
end
// STM: Sprite Temporary Memory
//
// bits desc
// ------- -----
// 24 primary object flag (is sprite 0?)
// 23 : 16 tile index
// 15 : 8 x coordinate
// 7 : 6 palette select bits
// 5 object priority
// 4 apply bit reversal to fetched object pattern table data (horizontal invert)
// 3 : 0 range comparison result (sprite row)
reg [24:0] m_stm [7:0];
reg [24:0] stm_din;
reg [ 2:0] stm_a;
reg stm_wr;
always @(posedge clk_in)
begin
if (stm_wr)
m_stm[stm_a] <= stm_din;
end
// SBM: Sprite Buffer Memory
//
// bits desc
// ------- -----
// 27 primary object flag (is sprite 0?)
// 26 priority
// 25 - 24 palette select (bit 3-2)
// 23 - 16 pattern data bit 1
// 15 - 8 pattern data bit 0
// 7 - 0 x-start
reg [27:0] m_sbm [7:0];
reg [27:0] sbm_din;
reg [ 2:0] sbm_a;
reg sbm_wr;
always @(posedge clk_in)
begin
if (sbm_wr)
m_sbm[sbm_a] <= sbm_din;
end
//
// In-range object evaluation (line N-1, fetch phases 1-128).
//
reg [3:0] q_in_rng_cnt, d_in_rng_cnt; // number of objects on the next scanline
reg q_spr_overflow, d_spr_overflow; // signals more than 8 objects on a scanline this frame
always @(posedge clk_in)
begin
if (rst_in)
begin
q_in_rng_cnt <= 4'h0;
q_spr_overflow <= 1'h0;
end
else
begin
q_in_rng_cnt <= d_in_rng_cnt;
q_spr_overflow <= d_spr_overflow;
end
end
wire [5:0] oam_rd_idx; // oam entry selector
wire [7:0] oam_rd_y; // cur oam entry y coordinate
wire [7:0] oam_rd_tile_idx; // cur oam entry tile index
wire oam_rd_v_inv; // cur oam entry vertical inversion state
wire oam_rd_h_inv; // cur oam entry horizontal inversion state
wire oam_rd_priority; // cur oam entry priority
wire [1:0] oam_rd_ps; // cur oam entry palette select
wire [7:0] oam_rd_x; // cur oam entry x coordinate
wire [8:0] rng_cmp_res; // 9-bit comparison result for in-range check
wire in_rng; // indicates whether current object is in-range
assign oam_rd_idx = nes_x_in[7:2];
assign oam_rd_y = m_oam[{ oam_rd_idx, 2'b00 }] + 8'h01;
assign oam_rd_tile_idx = m_oam[{ oam_rd_idx, 2'b01 }];
assign oam_rd_v_inv = m_oam[{ oam_rd_idx, 2'b10 }] >> 3'h7;
assign oam_rd_h_inv = m_oam[{ oam_rd_idx, 2'b10 }] >> 3'h6;
assign oam_rd_priority = m_oam[{ oam_rd_idx, 2'b10 }] >> 3'h5;
assign oam_rd_ps = m_oam[{ oam_rd_idx, 2'b10 }];
assign oam_rd_x = m_oam[{ oam_rd_idx, 2'b11 }];
assign rng_cmp_res = nes_y_next_in - oam_rd_y;
assign in_rng = (~|rng_cmp_res[8:4]) & (~rng_cmp_res[3] | spr_h_in);
always @*
begin
d_in_rng_cnt = q_in_rng_cnt;
// Reset the sprite overflow flag at the beginning of each frame. Otherwise, set the flag if
// any scanline in this frame has intersected more than 8 sprites.
if ((nes_y_next_in == 0) && (nes_x_in == 0))
d_spr_overflow = 1'b0;
else
d_spr_overflow = q_spr_overflow || q_in_rng_cnt[3];
stm_a = q_in_rng_cnt[2:0];
stm_wr = 1'b0;
stm_din[ 24] = ~|oam_rd_idx;
stm_din[23:16] = oam_rd_tile_idx;
stm_din[15: 8] = oam_rd_x;
stm_din[ 7: 6] = oam_rd_ps;
stm_din[ 5] = oam_rd_priority;
stm_din[ 4] = oam_rd_h_inv;
stm_din[ 3: 0] = (oam_rd_v_inv) ? ~rng_cmp_res[3:0] : rng_cmp_res[3:0];
if (en_in && pix_pulse_in && (nes_y_next_in < 239))
begin
if (nes_x_in == 320)
begin
// Reset the in-range count and sprite 0 in-rnage flag at the end of each scanline.
d_in_rng_cnt = 4'h0;
end
else if ((nes_x_in < 256) && (nes_x_in[1:0] == 2'h0) && in_rng && !q_in_rng_cnt[3])
begin
// Current object is in range, and there are less than 8 in-range objects found
// so far. Update the STM and increment the in-range counter.
stm_wr = 1'b1;
d_in_rng_cnt = q_in_rng_cnt + 4'h1;
end
end
end
//
// Object pattern fetch (fetch phases 129-160).
//
reg [7:0] q_pd0, d_pd0;
reg [7:0] q_pd1, d_pd1;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_pd1 <= 8'h00;
q_pd0 <= 8'h00;
end
else
begin
q_pd1 <= d_pd1;
q_pd0 <= d_pd0;
end
end
wire [2:0] stm_rd_idx;
wire stm_rd_primary;
wire [7:0] stm_rd_tile_idx;
wire [7:0] stm_rd_x;
wire [1:0] stm_rd_ps;
wire stm_rd_priority;
wire stm_rd_h_inv;
wire [3:0] stm_rd_obj_row;
assign stm_rd_idx = nes_x_in[5:3];
assign stm_rd_primary = m_stm[stm_rd_idx] >> 24;
assign stm_rd_tile_idx = m_stm[stm_rd_idx] >> 16;
assign stm_rd_x = m_stm[stm_rd_idx] >> 8;
assign stm_rd_ps = m_stm[stm_rd_idx] >> 6;
assign stm_rd_priority = m_stm[stm_rd_idx] >> 5;
assign stm_rd_h_inv = m_stm[stm_rd_idx] >> 4;
assign stm_rd_obj_row = m_stm[stm_rd_idx];
always @*
begin
d_pd1 = q_pd1;
d_pd0 = q_pd0;
sbm_a = stm_rd_idx;
sbm_wr = 1'b0;
sbm_din = 28'h000;
vram_req_out = 1'b0;
if (spr_h_in)
vram_a_out = { 1'b0,
stm_rd_tile_idx[0],
stm_rd_tile_idx[7:1],
stm_rd_obj_row[3],
nes_x_in[1],
stm_rd_obj_row[2:0] };
else
vram_a_out = { 1'b0,
spr_pt_sel_in,
stm_rd_tile_idx,
nes_x_in[1],
stm_rd_obj_row[2:0] };
if (en_in && (nes_y_next_in < 239) && (nes_x_in >= 256) && (nes_x_in < 320))
begin
if (stm_rd_idx < q_in_rng_cnt)
begin
case (nes_x_in[2:1])
2'h0:
begin
vram_req_out = 1'b1;
if (stm_rd_h_inv)
begin
d_pd0 = vram_d_in;
end
else
begin
d_pd0[0] = vram_d_in[7];
d_pd0[1] = vram_d_in[6];
d_pd0[2] = vram_d_in[5];
d_pd0[3] = vram_d_in[4];
d_pd0[4] = vram_d_in[3];
d_pd0[5] = vram_d_in[2];
d_pd0[6] = vram_d_in[1];
d_pd0[7] = vram_d_in[0];
end
end
2'h1:
begin
vram_req_out = 1'b1;
if (stm_rd_h_inv)
begin
d_pd1 = vram_d_in;
end
else
begin
d_pd1[0] = vram_d_in[7];
d_pd1[1] = vram_d_in[6];
d_pd1[2] = vram_d_in[5];
d_pd1[3] = vram_d_in[4];
d_pd1[4] = vram_d_in[3];
d_pd1[5] = vram_d_in[2];
d_pd1[6] = vram_d_in[1];
d_pd1[7] = vram_d_in[0];
end
end
2'h2:
begin
sbm_din = { stm_rd_primary, stm_rd_priority, stm_rd_ps, q_pd1, q_pd0, stm_rd_x };
sbm_wr = 1'b1;
end
endcase
end
else
begin
sbm_din = 28'h0000000;
sbm_wr = 1'b1;
end
end
end
//
// Object prioritization and output (line N, fetch phases 1-128).
//
reg [7:0] q_obj0_pd1_shift, d_obj0_pd1_shift;
reg [7:0] q_obj1_pd1_shift, d_obj1_pd1_shift;
reg [7:0] q_obj2_pd1_shift, d_obj2_pd1_shift;
reg [7:0] q_obj3_pd1_shift, d_obj3_pd1_shift;
reg [7:0] q_obj4_pd1_shift, d_obj4_pd1_shift;
reg [7:0] q_obj5_pd1_shift, d_obj5_pd1_shift;
reg [7:0] q_obj6_pd1_shift, d_obj6_pd1_shift;
reg [7:0] q_obj7_pd1_shift, d_obj7_pd1_shift;
reg [7:0] q_obj0_pd0_shift, d_obj0_pd0_shift;
reg [7:0] q_obj1_pd0_shift, d_obj1_pd0_shift;
reg [7:0] q_obj2_pd0_shift, d_obj2_pd0_shift;
reg [7:0] q_obj3_pd0_shift, d_obj3_pd0_shift;
reg [7:0] q_obj4_pd0_shift, d_obj4_pd0_shift;
reg [7:0] q_obj5_pd0_shift, d_obj5_pd0_shift;
reg [7:0] q_obj6_pd0_shift, d_obj6_pd0_shift;
reg [7:0] q_obj7_pd0_shift, d_obj7_pd0_shift;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_obj0_pd1_shift <= 8'h00;
q_obj1_pd1_shift <= 8'h00;
q_obj2_pd1_shift <= 8'h00;
q_obj3_pd1_shift <= 8'h00;
q_obj4_pd1_shift <= 8'h00;
q_obj5_pd1_shift <= 8'h00;
q_obj6_pd1_shift <= 8'h00;
q_obj7_pd1_shift <= 8'h00;
q_obj0_pd0_shift <= 8'h00;
q_obj1_pd0_shift <= 8'h00;
q_obj2_pd0_shift <= 8'h00;
q_obj3_pd0_shift <= 8'h00;
q_obj4_pd0_shift <= 8'h00;
q_obj5_pd0_shift <= 8'h00;
q_obj6_pd0_shift <= 8'h00;
q_obj7_pd0_shift <= 8'h00;
end
else
begin
q_obj0_pd1_shift <= d_obj0_pd1_shift;
q_obj1_pd1_shift <= d_obj1_pd1_shift;
q_obj2_pd1_shift <= d_obj2_pd1_shift;
q_obj3_pd1_shift <= d_obj3_pd1_shift;
q_obj4_pd1_shift <= d_obj4_pd1_shift;
q_obj5_pd1_shift <= d_obj5_pd1_shift;
q_obj6_pd1_shift <= d_obj6_pd1_shift;
q_obj7_pd1_shift <= d_obj7_pd1_shift;
q_obj0_pd0_shift <= d_obj0_pd0_shift;
q_obj1_pd0_shift <= d_obj1_pd0_shift;
q_obj2_pd0_shift <= d_obj2_pd0_shift;
q_obj3_pd0_shift <= d_obj3_pd0_shift;
q_obj4_pd0_shift <= d_obj4_pd0_shift;
q_obj5_pd0_shift <= d_obj5_pd0_shift;
q_obj6_pd0_shift <= d_obj6_pd0_shift;
q_obj7_pd0_shift <= d_obj7_pd0_shift;
end
end
wire sbm_rd_obj0_primary;
wire sbm_rd_obj0_priority;
wire [1:0] sbm_rd_obj0_ps;
wire [7:0] sbm_rd_obj0_pd1;
wire [7:0] sbm_rd_obj0_pd0;
wire [7:0] sbm_rd_obj0_x;
wire sbm_rd_obj1_primary;
wire sbm_rd_obj1_priority;
wire [1:0] sbm_rd_obj1_ps;
wire [7:0] sbm_rd_obj1_pd1;
wire [7:0] sbm_rd_obj1_pd0;
wire [7:0] sbm_rd_obj1_x;
wire sbm_rd_obj2_primary;
wire sbm_rd_obj2_priority;
wire [1:0] sbm_rd_obj2_ps;
wire [7:0] sbm_rd_obj2_pd1;
wire [7:0] sbm_rd_obj2_pd0;
wire [7:0] sbm_rd_obj2_x;
wire sbm_rd_obj3_primary;
wire sbm_rd_obj3_priority;
wire [1:0] sbm_rd_obj3_ps;
wire [7:0] sbm_rd_obj3_pd1;
wire [7:0] sbm_rd_obj3_pd0;
wire [7:0] sbm_rd_obj3_x;
wire sbm_rd_obj4_primary;
wire sbm_rd_obj4_priority;
wire [1:0] sbm_rd_obj4_ps;
wire [7:0] sbm_rd_obj4_pd1;
wire [7:0] sbm_rd_obj4_pd0;
wire [7:0] sbm_rd_obj4_x;
wire sbm_rd_obj5_primary;
wire sbm_rd_obj5_priority;
wire [1:0] sbm_rd_obj5_ps;
wire [7:0] sbm_rd_obj5_pd1;
wire [7:0] sbm_rd_obj5_pd0;
wire [7:0] sbm_rd_obj5_x;
wire sbm_rd_obj6_primary;
wire sbm_rd_obj6_priority;
wire [1:0] sbm_rd_obj6_ps;
wire [7:0] sbm_rd_obj6_pd1;
wire [7:0] sbm_rd_obj6_pd0;
wire [7:0] sbm_rd_obj6_x;
wire sbm_rd_obj7_primary;
wire sbm_rd_obj7_priority;
wire [1:0] sbm_rd_obj7_ps;
wire [7:0] sbm_rd_obj7_pd1;
wire [7:0] sbm_rd_obj7_pd0;
wire [7:0] sbm_rd_obj7_x;
assign sbm_rd_obj0_primary = m_sbm[0] >> 27;
assign sbm_rd_obj0_priority = m_sbm[0] >> 26;
assign sbm_rd_obj0_ps = m_sbm[0] >> 24;
assign sbm_rd_obj0_pd1 = m_sbm[0] >> 16;
assign sbm_rd_obj0_pd0 = m_sbm[0] >> 8;
assign sbm_rd_obj0_x = m_sbm[0];
assign sbm_rd_obj1_primary = m_sbm[1] >> 27;
assign sbm_rd_obj1_priority = m_sbm[1] >> 26;
assign sbm_rd_obj1_ps = m_sbm[1] >> 24;
assign sbm_rd_obj1_pd1 = m_sbm[1] >> 16;
assign sbm_rd_obj1_pd0 = m_sbm[1] >> 8;
assign sbm_rd_obj1_x = m_sbm[1];
assign sbm_rd_obj2_primary = m_sbm[2] >> 27;
assign sbm_rd_obj2_priority = m_sbm[2] >> 26;
assign sbm_rd_obj2_ps = m_sbm[2] >> 24;
assign sbm_rd_obj2_pd1 = m_sbm[2] >> 16;
assign sbm_rd_obj2_pd0 = m_sbm[2] >> 8;
assign sbm_rd_obj2_x = m_sbm[2];
assign sbm_rd_obj3_primary = m_sbm[3] >> 27;
assign sbm_rd_obj3_priority = m_sbm[3] >> 26;
assign sbm_rd_obj3_ps = m_sbm[3] >> 24;
assign sbm_rd_obj3_pd1 = m_sbm[3] >> 16;
assign sbm_rd_obj3_pd0 = m_sbm[3] >> 8;
assign sbm_rd_obj3_x = m_sbm[3];
assign sbm_rd_obj4_primary = m_sbm[4] >> 27;
assign sbm_rd_obj4_priority = m_sbm[4] >> 26;
assign sbm_rd_obj4_ps = m_sbm[4] >> 24;
assign sbm_rd_obj4_pd1 = m_sbm[4] >> 16;
assign sbm_rd_obj4_pd0 = m_sbm[4] >> 8;
assign sbm_rd_obj4_x = m_sbm[4];
assign sbm_rd_obj5_primary = m_sbm[5] >> 27;
assign sbm_rd_obj5_priority = m_sbm[5] >> 26;
assign sbm_rd_obj5_ps = m_sbm[5] >> 24;
assign sbm_rd_obj5_pd1 = m_sbm[5] >> 16;
assign sbm_rd_obj5_pd0 = m_sbm[5] >> 8;
assign sbm_rd_obj5_x = m_sbm[5];
assign sbm_rd_obj6_primary = m_sbm[6] >> 27;
assign sbm_rd_obj6_priority = m_sbm[6] >> 26;
assign sbm_rd_obj6_ps = m_sbm[6] >> 24;
assign sbm_rd_obj6_pd1 = m_sbm[6] >> 16;
assign sbm_rd_obj6_pd0 = m_sbm[6] >> 8;
assign sbm_rd_obj6_x = m_sbm[6];
assign sbm_rd_obj7_primary = m_sbm[7] >> 27;
assign sbm_rd_obj7_priority = m_sbm[7] >> 26;
assign sbm_rd_obj7_ps = m_sbm[7] >> 24;
assign sbm_rd_obj7_pd1 = m_sbm[7] >> 16;
assign sbm_rd_obj7_pd0 = m_sbm[7] >> 8;
assign sbm_rd_obj7_x = m_sbm[7];
always @*
begin
d_obj0_pd1_shift = q_obj0_pd1_shift;
d_obj1_pd1_shift = q_obj1_pd1_shift;
d_obj2_pd1_shift = q_obj2_pd1_shift;
d_obj3_pd1_shift = q_obj3_pd1_shift;
d_obj4_pd1_shift = q_obj4_pd1_shift;
d_obj5_pd1_shift = q_obj5_pd1_shift;
d_obj6_pd1_shift = q_obj6_pd1_shift;
d_obj7_pd1_shift = q_obj7_pd1_shift;
d_obj0_pd0_shift = q_obj0_pd0_shift;
d_obj1_pd0_shift = q_obj1_pd0_shift;
d_obj2_pd0_shift = q_obj2_pd0_shift;
d_obj3_pd0_shift = q_obj3_pd0_shift;
d_obj4_pd0_shift = q_obj4_pd0_shift;
d_obj5_pd0_shift = q_obj5_pd0_shift;
d_obj6_pd0_shift = q_obj6_pd0_shift;
d_obj7_pd0_shift = q_obj7_pd0_shift;
if (en_in && (nes_y_in < 239))
begin
if (pix_pulse_in)
begin
d_obj0_pd1_shift = { 1'b0, q_obj0_pd1_shift[7:1] };
d_obj0_pd0_shift = { 1'b0, q_obj0_pd0_shift[7:1] };
end
else if ((nes_x_in - sbm_rd_obj0_x) == 8'h00)
begin
d_obj0_pd1_shift = sbm_rd_obj0_pd1;
d_obj0_pd0_shift = sbm_rd_obj0_pd0;
end
if (pix_pulse_in)
begin
d_obj1_pd1_shift = { 1'b0, q_obj1_pd1_shift[7:1] };
d_obj1_pd0_shift = { 1'b0, q_obj1_pd0_shift[7:1] };
end
else if ((nes_x_in - sbm_rd_obj1_x) == 8'h00)
begin
d_obj1_pd1_shift = sbm_rd_obj1_pd1;
d_obj1_pd0_shift = sbm_rd_obj1_pd0;
end
if (pix_pulse_in)
begin
d_obj2_pd1_shift = { 1'b0, q_obj2_pd1_shift[7:1] };
d_obj2_pd0_shift = { 1'b0, q_obj2_pd0_shift[7:1] };
end
else if ((nes_x_in - sbm_rd_obj2_x) == 8'h00)
begin
d_obj2_pd1_shift = sbm_rd_obj2_pd1;
d_obj2_pd0_shift = sbm_rd_obj2_pd0;
end
if (pix_pulse_in)
begin
d_obj3_pd1_shift = { 1'b0, q_obj3_pd1_shift[7:1] };
d_obj3_pd0_shift = { 1'b0, q_obj3_pd0_shift[7:1] };
end
else if ((nes_x_in - sbm_rd_obj3_x) == 8'h00)
begin
d_obj3_pd1_shift = sbm_rd_obj3_pd1;
d_obj3_pd0_shift = sbm_rd_obj3_pd0;
end
if (pix_pulse_in)
begin
d_obj4_pd1_shift = { 1'b0, q_obj4_pd1_shift[7:1] };
d_obj4_pd0_shift = { 1'b0, q_obj4_pd0_shift[7:1] };
end
else if ((nes_x_in - sbm_rd_obj4_x) == 8'h00)
begin
d_obj4_pd1_shift = sbm_rd_obj4_pd1;
d_obj4_pd0_shift = sbm_rd_obj4_pd0;
end
if (pix_pulse_in)
begin
d_obj5_pd1_shift = { 1'b0, q_obj5_pd1_shift[7:1] };
d_obj5_pd0_shift = { 1'b0, q_obj5_pd0_shift[7:1] };
end
else if ((nes_x_in - sbm_rd_obj5_x) == 8'h00)
begin
d_obj5_pd1_shift = sbm_rd_obj5_pd1;
d_obj5_pd0_shift = sbm_rd_obj5_pd0;
end
if (pix_pulse_in)
begin
d_obj6_pd1_shift = { 1'b0, q_obj6_pd1_shift[7:1] };
d_obj6_pd0_shift = { 1'b0, q_obj6_pd0_shift[7:1] };
end
else if ((nes_x_in - sbm_rd_obj6_x) == 8'h00)
begin
d_obj6_pd1_shift = sbm_rd_obj6_pd1;
d_obj6_pd0_shift = sbm_rd_obj6_pd0;
end
if (pix_pulse_in)
begin
d_obj7_pd1_shift = { 1'b0, q_obj7_pd1_shift[7:1] };
d_obj7_pd0_shift = { 1'b0, q_obj7_pd0_shift[7:1] };
end
else if ((nes_x_in - sbm_rd_obj7_x) == 8'h00)
begin
d_obj7_pd1_shift = sbm_rd_obj7_pd1;
d_obj7_pd0_shift = sbm_rd_obj7_pd0;
end
end
end
assign { primary_out, priority_out, palette_idx_out } =
(!en_in || (ls_clip_in && (nes_x_in >= 10'h000) && (nes_x_in < 10'h008))) ?
6'h00 :
({ q_obj0_pd1_shift[0], q_obj0_pd0_shift[0] } != 0) ?
{ sbm_rd_obj0_primary, sbm_rd_obj0_priority, sbm_rd_obj0_ps, q_obj0_pd1_shift[0], q_obj0_pd0_shift[0] } :
({ q_obj1_pd1_shift[0], q_obj1_pd0_shift[0] } != 0) ?
{ sbm_rd_obj1_primary, sbm_rd_obj1_priority, sbm_rd_obj1_ps, q_obj1_pd1_shift[0], q_obj1_pd0_shift[0] } :
({ q_obj2_pd1_shift[0], q_obj2_pd0_shift[0] } != 0) ?
{ sbm_rd_obj2_primary, sbm_rd_obj2_priority, sbm_rd_obj2_ps, q_obj2_pd1_shift[0], q_obj2_pd0_shift[0] } :
({ q_obj3_pd1_shift[0], q_obj3_pd0_shift[0] } != 0) ?
{ sbm_rd_obj3_primary, sbm_rd_obj3_priority, sbm_rd_obj3_ps, q_obj3_pd1_shift[0], q_obj3_pd0_shift[0] } :
({ q_obj4_pd1_shift[0], q_obj4_pd0_shift[0] } != 0) ?
{ sbm_rd_obj4_primary, sbm_rd_obj4_priority, sbm_rd_obj4_ps, q_obj4_pd1_shift[0], q_obj4_pd0_shift[0] } :
({ q_obj5_pd1_shift[0], q_obj5_pd0_shift[0] } != 0) ?
{ sbm_rd_obj5_primary, sbm_rd_obj5_priority, sbm_rd_obj5_ps, q_obj5_pd1_shift[0], q_obj5_pd0_shift[0] } :
({ q_obj6_pd1_shift[0], q_obj6_pd0_shift[0] } != 0) ?
{ sbm_rd_obj6_primary, sbm_rd_obj6_priority, sbm_rd_obj6_ps, q_obj6_pd1_shift[0], q_obj6_pd0_shift[0] } :
({ q_obj7_pd1_shift[0], q_obj7_pd0_shift[0] } != 0) ?
{ sbm_rd_obj7_primary, sbm_rd_obj7_priority, sbm_rd_obj7_ps, q_obj7_pd1_shift[0], q_obj7_pd0_shift[0] } : 6'b0000;
assign oam_d_out = m_oam[oam_a_in];
assign overflow_out = q_spr_overflow;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_4_V
`define SKY130_FD_SC_HDLL__O221AI_4_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_4_V
|
// Note: This code is written to support monitor display resolutions of 1280 x 1024 at 60 fps
// (DETAILS OF THE MODULES)
// VGAInterface.v is the top most level module and asserts the red/green/blue signals to draw to the computer screen
// VGAController.v is a submodule within the top module used to generate the vertical and horizontal synch signals as well as X and Y pixel positions
// VGAFrequency.v is a submodule within the top module used to generate a 108Mhz pixel clock frequency from a 50Mhz pixel clock frequency using the PLL
// (USER/CODER Notes)
// Note: User should modify/write code in the VGAInterface.v file and not modify any code written in VGAController.v or VGAFrequency.v
module VGAInterface(
//////////// CLOCK //////////
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
//////////// LED //////////
LEDG,
LEDR,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SEG7 //////////
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
//////////// VGA //////////
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
//////////// LED //////////
output [8:0] LEDG;
output [17:0] LEDR;
//////////// KEY //////////
input [3:0] KEY;
//////////// SW //////////
input [17:0] SW;
//////////// SEG7 //////////
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
//////////// VGA //////////
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg aresetPll = 0; // asynchrous reset for pll
wire pixelClock;
wire [10:0] XPixelPosition;
wire [10:0] YPixelPosition;
reg [7:0] redValue;
reg [7:0] greenValue;
reg [7:0] blueValue;
reg [1:0] movement = 0;
parameter r = 15;
// slow clock counter variables
reg [20:0] slowClockCounter = 0;
wire slowClock;
// fast clock counter variables
reg [20:0] fastClockCounter = 0;
wire fastClock;
// variables for the dot
reg [10:0] XDotPosition = 500;
reg [10:0] YDotPosition = 500;
// variables for paddle 1
reg [10:0] P1x = 225;
reg [10:0] P1y = 500;
// variables for paddle 2
reg [10:0] P2x = 1030;
reg [10:0] P2y = 500;
// variables for player scores
reg [3:0] P1Score = 0;
reg [3:0] P2Score = 0;
reg flag =1'b0;
//=======================================================
// Structural coding
//=======================================================
// output assignments
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b1;
assign VGA_CLK = pixelClock;
// display the X or Y position of the dot on LEDS (Binary format)
// MSB is LEDR[10], LSB is LEDR[0]
assign LEDR[10:0] = SW[1] ? YDotPosition : XDotPosition;
assign slowClock = slowClockCounter[16]; // take MSB from counter to use as a slow clock
always@ (posedge CLOCK_50) // generates a slow clock by selecting the MSB from a large counter
begin
slowClockCounter <= slowClockCounter + 1;
end
assign fastClock = fastClockCounter[17]; // take Middle Bit from counter to use as a slow clock
always@ (posedge CLOCK_50) // generates a fast clock by selecting the Middle Bit from a large counter
begin
fastClockCounter <= fastClockCounter + 1;
end
always@(posedge fastClock) // process moves the y position of player1 paddle
begin
if (SW[0] == 1'b0)
begin
if (KEY[2] == 1'b0 && KEY[3] == 1'b0)
P1y <= P1y;
else if (KEY[2] == 1'b0) begin
if (P1y+125 >896)
P1y <= 771;
else
P1y <= P1y + 1;
end
else if (KEY[3] == 1'b0) begin
if(P1y < 128)
P1y <= 128;
else
P1y <= P1y - 1;
end
end
else if (SW[0] == 1'b1 || flag==1)
P1y <= 500;
//flag =1'b0;
end
always@(posedge fastClock) // process moves the y position of player2 paddle
begin
if (SW[0] == 1'b0)
begin
if (KEY[0] == 1'b0 && KEY[1] == 1'b0)
P2y <= P2y;
else if (KEY[0] == 1'b0) begin
if(P2y+125 > 896)
P2y <= 771;
else
P2y <= P2y + 1;
end
else if (KEY[1] == 1'b0) begin
if(P2y < 128)
P2y <= 128;
else
P2y <= P2y - 1;
end
end
else if (SW[0] == 1'b1 || flag ==1)
P2y <= 500;
end
always@(posedge slowClock) // Moves Ball
begin
if (SW[0] == 1'b0)
begin
case(movement)
0: begin //Ball moves in NE direction
XDotPosition <= XDotPosition + 1;
YDotPosition <= YDotPosition - 1;
end
1: begin //Ball moves in SE direction
XDotPosition <= XDotPosition + 1;
YDotPosition <= YDotPosition + 1;
end
2: begin //Ball moves in SW direction
XDotPosition <= XDotPosition - 1;
YDotPosition <= YDotPosition + 1;
end
3: begin //Ball moves in NW direction
XDotPosition <= XDotPosition - 1;
YDotPosition <= YDotPosition - 1;
end
endcase
if(YDotPosition - r <= 128 && movement == 0) //bounce top wall from NE
movement = 1;
else if (YDotPosition - r <= 128 && movement == 3)// bounce top wall from NW
movement = 2;
else if (YDotPosition + r >= 896 && movement == 1) // bounce bottom wall from SE
movement = 0;
else if (YDotPosition + r >= 896 && movement == 2) // bounce bottom wall from Sw
movement = 3;
else if (XDotPosition -r <= P1x+25 && YDotPosition > P1y && YDotPosition < P1y+125 && movement == 2)//bounce left paddle from SW
movement = 1;
else if (XDotPosition -r<= P1x+25 && YDotPosition > P1y && YDotPosition < P1y+125 && movement == 3)//bounce left paddle from NW
movement = 0;
else if (XDotPosition + r >= P2x && YDotPosition > P2y && YDotPosition < P2y+125 && movement == 1)//bounce right paddle from SE
movement = 2;
else if (XDotPosition + r >= P2x && YDotPosition > P2y && YDotPosition < P2y+125 && movement == 0)//bounce right paddle from NE
movement = 3;
else if (XDotPosition - r <= 160) begin
P2Score = P2Score + 1;
//reset ball
XDotPosition <= 640;
YDotPosition <= 512;
end
else if (XDotPosition + r >= 1120)begin
P1Score = P1Score + 1;
//reset ball
XDotPosition <= 640;
YDotPosition <= 512;
end
/***if(flag==1) begin
flag<=0;
end***/
if(P1Score == 10 || P2Score ==10) begin
P1Score<=0;
P2Score<=0;
flag <=1;
end
end
else //reset ball and score
begin
XDotPosition <= 500;
YDotPosition <= 500;
P1Score <= 0;
P2Score <= 0;
end
end
/*always@(posedge slowClock) // process moves the X position of the dot
begin
if (KEY[0] == 1'b0)
XDotPosition <= XDotPosition + 1;
else if (KEY[1] == 1'b0)
XDotPosition <= XDotPosition - 1;
end
always@(posedge slowClock) // process moves the Y position of the dot
begin
if (KEY[2] == 1'b0)
YDotPosition <= YDotPosition + 1;
else if (KEY[3] == 1'b0)
YDotPosition <= YDotPosition - 1;
end
*/
// PLL Module (Phase Locked Loop) used to convert a 50Mhz clock signal to a 108 MHz clock signal for the pixel clock
VGAFrequency VGAFreq (aresetPll, CLOCK_50, pixelClock);
// VGA Controller Module used to generate the vertial and horizontal synch signals for the monitor and the X and Y Pixel position of the monitor display
VGAController VGAControl (pixelClock, redValue, greenValue, blueValue, VGA_R, VGA_G, VGA_B, VGA_VS, VGA_HS, XPixelPosition, YPixelPosition);
// COLOR ASSIGNMENT PROCESS (USER WRITES CODE HERE TO DRAW TO SCREEN)
always@ (posedge pixelClock)
begin
begin
if (XPixelPosition < 160) //set left green border
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b11111111;
end
else if (XPixelPosition > 1120) // set right green border
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b11111111;
end
else if (YPixelPosition < 128 && XPixelPosition > 160 && XPixelPosition < 1120) //set top magenta border
begin
redValue <= 8'b11111111;
blueValue <= 8'b11111111;
greenValue <= 8'b00000000;
end
else if (XPixelPosition < 1120 && XPixelPosition > 160 && YPixelPosition > 896) // set bottom magenta border
begin
redValue <= 8'b11111111;
blueValue <= 8'b11111111;
greenValue <= 8'b00000000;
end
else if (XPixelPosition > P1x && XPixelPosition < P1x+25 && YPixelPosition > P1y && YPixelPosition < P1y+125) // draw player 1 paddle
begin
redValue <= 8'b00000000;
blueValue <= 8'b111111111;
greenValue <= 8'b11111111;
end
else if (XPixelPosition > P2x && XPixelPosition < P2x+25 && YPixelPosition > P2y && YPixelPosition < P2y+125) // draw player 2 paddle
begin
redValue <= 8'b00000000;
blueValue <= 8'b11111111;
greenValue <= 8'b11111111;
end
//draw ball using (x-a)^2 + (y-b)^2 = r^2 where (a,b) is the center of the circle and r = 15
//a = XDotPosition, b = YDotPosition
else if (((XPixelPosition-XDotPosition)**2
+ (YPixelPosition-YDotPosition)**2) < 15**2)
begin
redValue <= 8'b11111111;
blueValue <= 8'b00000000;
greenValue <= 8'b00000000;
end
else // default background is black
begin
redValue <= 8'b00000000;
blueValue <= 8'b00000000;
greenValue <= 8'b00000000;
end
end
end
ScoreDecoder p1(P1Score, HEX7, HEX6);
ScoreDecoder p2(P2Score, HEX5, HEX4);
endmodule
|
/**
* Displays the binary content of a 16 bit register on the screen.
*/
module register_display(
input clk, // the system clock
input [15:0] data_in, // the value of the register to show
input [10:0] vga_h, // the current vertical pixel count being displayed
input [10:0] vga_v, // the current horizontal pixel count being displayed
input [2:0] bg, // the colour of the background pixel
output [2:0] pixel_out, // The requested pixel value at vga_h x vga_v
output display_on // whether the screen should be displaying this
);
parameter START_H = 10; // horizontal pixel where this should appear on the screen
parameter START_V = 380; // vertical pixel where this should appear on the screen
reg [2:0] out = 0;
assign pixel_out = out;
reg on = 0;
assign display_on = on;
always @ (posedge clk) begin
if (vga_v >= START_V && vga_v < START_V + 11'd6
&& vga_h >= START_H && vga_h < START_H + 11'd161) begin
on <= 1'b1;
// 5 x 5 squares that light if the corresponding bit in the data is set.
case (vga_h - START_H)
11'd0, 11'd1, 11'd2, 11'd3, 11'd4: out <= data_in[15] ? 3'b100 : 3'b000;
11'd10, 11'd11, 11'd12, 11'd13, 11'd14: out <= data_in[14] ? 3'b100 : 3'b000;
11'd20, 11'd21, 11'd22, 11'd23, 11'd24: out <= data_in[13] ? 3'b100 : 3'b000;
11'd30, 11'd31, 11'd32, 11'd33, 11'd34: out <= data_in[12] ? 3'b100 : 3'b000;
11'd40, 11'd41, 11'd42, 11'd43, 11'd44: out <= data_in[11] ? 3'b100 : 3'b000;
11'd50, 11'd51, 11'd52, 11'd53, 11'd54: out <= data_in[10] ? 3'b100 : 3'b000;
11'd60, 11'd61, 11'd62, 11'd63, 11'd64: out <= data_in[9] ? 3'b100 : 3'b000;
11'd70, 11'd71, 11'd72, 11'd73, 11'd74: out <= data_in[8] ? 3'b100 : 3'b000;
11'd80, 11'd81, 11'd82, 11'd83, 11'd84: out <= data_in[7] ? 3'b100 : 3'b000;
11'd90, 11'd91, 11'd92, 11'd93, 11'd94: out <= data_in[6] ? 3'b100 : 3'b000;
11'd100,11'd101,11'd102,11'd103,11'd104: out <= data_in[5] ? 3'b100 : 3'b000;
11'd110,11'd111,11'd112,11'd113,11'd114: out <= data_in[4] ? 3'b100 : 3'b000;
11'd120,11'd121,11'd122,11'd123,11'd124: out <= data_in[3] ? 3'b100 : 3'b000;
11'd130,11'd131,11'd132,11'd133,11'd134: out <= data_in[2] ? 3'b100 : 3'b000;
11'd140,11'd141,11'd142,11'd143,11'd144: out <= data_in[1] ? 3'b100 : 3'b000;
11'd150,11'd151,11'd152,11'd153,11'd154: out <= data_in[0] ? 3'b100 : 3'b000;
default: out <= bg;
endcase
end else begin
out <= bg;
on <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_1_V
`define SKY130_FD_SC_LP__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.4 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.3 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_2048x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bist artisan_ssp(
`else
art_hssp_2048x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x32_bist vs_ssp(
`else
vs_hdsp_2048x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[9:8]),
.EN(ce),
.WE(we),
.DO(doq[9:8])
);
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[11:10]),
.EN(ce),
.WE(we),
.DO(doq[11:10])
);
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[13:12]),
.EN(ce),
.WE(we),
.DO(doq[13:12])
);
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:14]),
.EN(ce),
.WE(we),
.DO(doq[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[17:16]),
.EN(ce),
.WE(we),
.DO(doq[17:16])
);
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[19:18]),
.EN(ce),
.WE(we),
.DO(doq[19:18])
);
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[21:20]),
.EN(ce),
.WE(we),
.DO(doq[21:20])
);
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[23:22]),
.EN(ce),
.WE(we),
.DO(doq[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[25:24]),
.EN(ce),
.WE(we),
.DO(doq[25:24])
);
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[27:26]),
.EN(ce),
.WE(we),
.DO(doq[27:26])
);
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[29:28]),
.EN(ce),
.WE(we),
.DO(doq[29:28])
);
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[31:30]),
.EN(ce),
.WE(we),
.DO(doq[31:30])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[7:0]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[7:0]),
.DOP()
);
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[15:8]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[15:8]),
.DOP()
);
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[23:16]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[23:16]),
.DOP()
);
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[31:24]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[31:24]),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
//lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_top.v
// /___/ /\ Date Last Modified: $Date: 2009/01/15 14:22:14 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// System level module. This level contains just the memory controller.
// This level will be intiantated when the user wants to remove the
// synthesizable test bench, IDELAY control block and the clock
// generation modules.
//Reference:
//Revision History:
// Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_top #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter BANK_WIDTH = 2, // # of memory bank addr bits
parameter CKE_WIDTH = 1, // # of memory clock enable outputs
parameter CLK_WIDTH = 1, // # of clock outputs
parameter COL_WIDTH = 10, // # of memory column bits
parameter CS_NUM = 1, // # of separate memory chip selects
parameter CS_BITS = 0, // set to log2(CS_NUM) (rounded up)
parameter CS_WIDTH = 1, // # of total memory chip selects
parameter USE_DM_PORT = 1, // enable Data Mask (=1 enable)
parameter DM_WIDTH = 9, // # of data mask bits
parameter DQ_WIDTH = 72, // # of data width
parameter DQ_BITS = 7, // set to log2(DQS_WIDTH*DQ_PER_DQS)
parameter DQ_PER_DQS = 8, // # of DQ data bits per strobe
parameter DQS_WIDTH = 9, // # of DQS strobes
parameter DQS_BITS = 4, // set to log2(DQS_WIDTH)
parameter HIGH_PERFORMANCE_MODE = "TRUE", // IODELAY Performance Mode
parameter IODELAY_GRP = "IODELAY_MIG", // IODELAY Group Name
parameter ODT_WIDTH = 1, // # of memory on-die term enables
parameter ROW_WIDTH = 14, // # of memory row & # of addr bits
parameter APPDATA_WIDTH = 144, // # of usr read/write data bus bits
parameter ADDITIVE_LAT = 0, // additive write latency
parameter BURST_LEN = 4, // burst length (in double words)
parameter BURST_TYPE = 0, // burst type (=0 seq; =1 interlved)
parameter CAS_LAT = 5, // CAS latency
parameter ECC_ENABLE = 0, // enable ECC (=1 enable)
parameter ODT_TYPE = 1, // ODT (=0(none),=1(75),=2(150),=3(50))
parameter MULTI_BANK_EN = 1, // enable bank management
parameter TWO_T_TIME_EN = 0, // 2t timing for unbuffered dimms
parameter REDUCE_DRV = 0, // reduced strength mem I/O (=1 yes)
parameter REG_ENABLE = 1, // registered addr/ctrl (=1 yes)
parameter TREFI_NS = 7800, // auto refresh interval (ns)
parameter TRAS = 40000, // active->precharge delay
parameter TRCD = 15000, // active->read/write delay
parameter TRFC = 105000, // ref->ref, ref->active delay
parameter TRP = 15000, // precharge->command delay
parameter TRTP = 7500, // read->precharge delay
parameter TWR = 15000, // used to determine wr->prech
parameter TWTR = 10000, // write->read delay
parameter CLK_PERIOD = 3000, // Core/Mem clk period (in ps)
parameter SIM_ONLY = 0, // = 1 to skip power up delay
parameter DEBUG_EN = 0, // Enable debug signals/controls
parameter FPGA_SPEED_GRADE = 2 // FPGA Speed Grade
)
(
input clk0,
input usr_clk, // jb
input clk90,
input clkdiv0,
input rst0,
input rst90,
input rstdiv0,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output app_af_afull,
output app_wdf_afull,
output rd_data_valid,
output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
output [1:0] rd_ecc_error,
output phy_init_done,
output [CLK_WIDTH-1:0] ddr2_ck,
output [CLK_WIDTH-1:0] ddr2_ck_n,
output [ROW_WIDTH-1:0] ddr2_a,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CS_WIDTH-1:0] ddr2_cs_n,
output [CKE_WIDTH-1:0] ddr2_cke,
output [ODT_WIDTH-1:0] ddr2_odt,
output [DM_WIDTH-1:0] ddr2_dm,
inout [DQS_WIDTH-1:0] ddr2_dqs,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
inout [DQ_WIDTH-1:0] ddr2_dq,
// Debug signals (optional use)
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_dq,
input dbg_idel_down_dq,
input dbg_idel_up_dqs,
input dbg_idel_down_dqs,
input dbg_idel_up_gate,
input dbg_idel_down_gate,
input [DQ_BITS-1:0] dbg_sel_idel_dq,
input dbg_sel_all_idel_dq,
input [DQS_BITS:0] dbg_sel_idel_dqs,
input dbg_sel_all_idel_dqs,
input [DQS_BITS:0] dbg_sel_idel_gate,
input dbg_sel_all_idel_gate,
output [3:0] dbg_calib_done,
output [3:0] dbg_calib_err,
output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
);
// memory initialization/control logic
ddr2_mem_if_top #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.USE_DM_PORT (USE_DM_PORT),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.MULTI_BANK_EN (MULTI_BANK_EN),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.ODT_TYPE (ODT_TYPE),
.DDR_TYPE (1),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.CLK_PERIOD (CLK_PERIOD),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
)
u_mem_if_top
(
.clk0 (clk0),
.usr_clk (usr_clk), // jb
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.app_af_afull (app_af_afull),
.app_wdf_afull (app_wdf_afull),
.rd_data_valid (rd_data_valid),
.rd_data_fifo_out (rd_data_fifo_out),
.rd_ecc_error (rd_ecc_error),
.phy_init_done (phy_init_done),
.ddr_ck (ddr2_ck),
.ddr_ck_n (ddr2_ck_n),
.ddr_addr (ddr2_a),
.ddr_ba (ddr2_ba),
.ddr_ras_n (ddr2_ras_n),
.ddr_cas_n (ddr2_cas_n),
.ddr_we_n (ddr2_we_n),
.ddr_cs_n (ddr2_cs_n),
.ddr_cke (ddr2_cke),
.ddr_odt (ddr2_odt),
.ddr_dm (ddr2_dm),
.ddr_dqs (ddr2_dqs),
.ddr_dqs_n (ddr2_dqs_n),
.ddr_dq (ddr2_dq),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Graphics mode CRT Cycle
// File : sm_graphic_crt.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This state machine is active when crt_cycle is active in graphics mode
// and crtfifo is writable. This state machine generates an svga_req to the
// memory module and waits for the acknowledge. transfers the data after
// the acknowledge is confirmed.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module sm_graphic_crt
(
input sync_c_crt_line_end,
input hreset_n,
input ff_writeable_crt,
input crt_gnt,
input svga_ack,
input mem_clk,
input graphic_mode,
input data_complete,
input [7:0] c_hde,
input color_256_mode,
output gra_crt_svga_req,
output enrd_gra_addr,
output gra_cnt_inc,
output [30:0] probe
);
//
// Define variables
//
reg [2:0] current_state;
reg [2:0] next_state;
reg [3:0] gra_cnt_qout;
reg gra_s1;
reg gra_s1x, gra_s2;
reg gra_s2x, gra_s3;
reg [4:0] char_count;
wire gra_cnt_0;
wire cnt_inc;
wire char_done;
assign probe = {data_complete, char_done, cnt_inc, ff_writeable_crt,
crt_gnt, svga_ack, graphic_mode, color_256_mode,
gra_crt_svga_req, enrd_gra_addr, gra_cnt_inc,
char_count, c_hde, current_state, gra_cnt_qout};
//
// Define state machine variables
//
parameter gra_crt_state0 = 3'b000,
gra_crt_state1x = 3'b001,
gra_crt_state2 = 3'b011,
gra_crt_state1 = 3'b111,
gra_crt_state2x = 3'b110,
gra_crt_state3 = 3'b010;
// In standard graphics modes we always increment by 1 character per piece
// of data read
always @ (posedge mem_clk or negedge hreset_n)
if (!hreset_n) char_count <= 5'b0;
else if (sync_c_crt_line_end) char_count <= 5'b0;
else if (data_complete) char_count <= char_count + 1;
// Need to add in extra characters for panning (can pan up to 3)
assign char_done = {char_count, 4'b0} >= (c_hde + 4);
always @ (posedge mem_clk or negedge hreset_n) begin
if (~hreset_n) current_state <= gra_crt_state0;
else if (sync_c_crt_line_end) current_state <= gra_crt_state0;
else current_state <= next_state;
end
always @* begin
gra_s1 = 1'b0;
gra_s1x = 1'b0;
gra_s2 = 1'b0;
gra_s2x = 1'b0;
gra_s3 = 1'b0;
case (current_state) // synopsys parallel_case
gra_crt_state0: begin
if (crt_gnt && ff_writeable_crt & graphic_mode && ~char_done)
next_state = gra_crt_state1x;
else
next_state = gra_crt_state0;
end
gra_crt_state1x: begin
gra_s1x = 1'b1;
if (svga_ack)
next_state = gra_crt_state2;
else
next_state = gra_crt_state1x;
end
gra_crt_state2: begin
gra_s2 = 1'b1;
if (~gra_cnt_0 )
next_state = gra_crt_state1;
else if (gra_cnt_0 )
next_state = gra_crt_state2x;
else
next_state = gra_crt_state2;
end
gra_crt_state1: begin
gra_s1 = 1'b1;
if (svga_ack)
next_state = gra_crt_state2;
else
next_state = gra_crt_state1;
end
gra_crt_state2x: begin
gra_s2x = 1'b1;
next_state = gra_crt_state3;
end
gra_crt_state3: begin
gra_s3 = 1'b1;
if (data_complete)
next_state = gra_crt_state0;
else
next_state = gra_crt_state3;
end
endcase
end
assign enrd_gra_addr = (gra_s2 );
assign gra_crt_svga_req = gra_s1x | ((gra_s1 | gra_s2) & ~gra_cnt_0);
assign gra_cnt_inc = (svga_ack & (gra_s2 | gra_s1)) | gra_s2x;
assign cnt_inc = svga_ack & (gra_s1x | gra_s2 | gra_s1);
assign gra_cnt_0 = (~gra_cnt_qout[3] & ~gra_cnt_qout[2] & ~gra_cnt_qout[1] & ~gra_cnt_qout[0] ) ;
always @ (posedge mem_clk or negedge hreset_n) begin
if (~hreset_n) gra_cnt_qout <= 4'b0;
else if (sync_c_crt_line_end) gra_cnt_qout <= 4'b0;
else if (cnt_inc) gra_cnt_qout <= gra_cnt_qout + 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_TB_V
`define SKY130_FD_SC_MS__CLKBUF_TB_V
/**
* clkbuf: Clock tree buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_TB_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:26:00 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top zqynq_lab_1_design_auto_pc_2 -prefix
// zqynq_lab_1_design_auto_pc_2_ zqynq_lab_1_design_auto_pc_1_sim_netlist.v
// Design : zqynq_lab_1_design_auto_pc_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "1" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.UNCONN_OUT({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
s_axi_bid,
s_axi_bresp,
UNCONN_OUT,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_arready,
s_axi_rready,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
s_axi_bready,
m_axi_awready,
s_axi_awvalid,
m_axi_bvalid,
m_axi_rvalid,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [35:0]UNCONN_OUT;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_arready;
input s_axi_rready;
input aclk;
input [33:0]in;
input [0:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [0:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input s_axi_bready;
input m_axi_awready;
input s_axi_awvalid;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_arvalid;
input aresetn;
wire [11:4]C;
wire [22:0]Q;
wire \RD.ar_channel_0_n_27 ;
wire \RD.ar_channel_0_n_28 ;
wire \RD.ar_channel_0_n_29 ;
wire \RD.ar_channel_0_n_30 ;
wire \RD.ar_channel_0_n_6 ;
wire \RD.ar_channel_0_n_7 ;
wire \RD.ar_channel_0_n_8 ;
wire \RD.ar_channel_0_n_9 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_1 ;
wire SI_REG_n_10;
wire SI_REG_n_11;
wire SI_REG_n_112;
wire SI_REG_n_113;
wire SI_REG_n_114;
wire SI_REG_n_115;
wire SI_REG_n_116;
wire SI_REG_n_117;
wire SI_REG_n_118;
wire SI_REG_n_119;
wire SI_REG_n_12;
wire SI_REG_n_120;
wire SI_REG_n_121;
wire SI_REG_n_122;
wire SI_REG_n_123;
wire SI_REG_n_124;
wire SI_REG_n_125;
wire SI_REG_n_126;
wire SI_REG_n_127;
wire SI_REG_n_128;
wire SI_REG_n_129;
wire SI_REG_n_132;
wire SI_REG_n_133;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_149;
wire SI_REG_n_150;
wire SI_REG_n_151;
wire SI_REG_n_152;
wire SI_REG_n_153;
wire SI_REG_n_154;
wire SI_REG_n_155;
wire SI_REG_n_156;
wire SI_REG_n_157;
wire SI_REG_n_158;
wire SI_REG_n_159;
wire SI_REG_n_160;
wire SI_REG_n_161;
wire SI_REG_n_162;
wire SI_REG_n_163;
wire SI_REG_n_164;
wire SI_REG_n_18;
wire SI_REG_n_57;
wire SI_REG_n_58;
wire SI_REG_n_59;
wire SI_REG_n_60;
wire SI_REG_n_66;
wire SI_REG_n_9;
wire [35:0]UNCONN_OUT;
wire \WR.aw_channel_0_n_14 ;
wire \WR.aw_channel_0_n_34 ;
wire \WR.aw_channel_0_n_35 ;
wire \WR.aw_channel_0_n_36 ;
wire \WR.aw_channel_0_n_37 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire \ar_pipe/p_1_in ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire \aw_pipe/p_1_in ;
wire b_awid;
wire [7:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3 ;
wire \cmd_translator_0/incr_cmd_0/sel_first ;
wire \cmd_translator_0/incr_cmd_0/sel_first_2 ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire s_arid;
wire s_arid_r;
wire s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_ar_channel \RD.ar_channel_0
(.CO(SI_REG_n_125),
.D({SI_REG_n_155,SI_REG_n_156,SI_REG_n_157,SI_REG_n_158,SI_REG_n_159,SI_REG_n_160,SI_REG_n_161}),
.E(\ar_pipe/p_1_in ),
.O({SI_REG_n_126,SI_REG_n_127,SI_REG_n_128,SI_REG_n_129}),
.Q({s_arid,SI_REG_n_57,SI_REG_n_58,SI_REG_n_59,SI_REG_n_60,si_rs_arlen,si_rs_arburst,SI_REG_n_66,si_rs_arsize,si_rs_araddr}),
.S({\RD.ar_channel_0_n_27 ,\RD.ar_channel_0_n_28 ,\RD.ar_channel_0_n_29 ,\RD.ar_channel_0_n_30 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\cnt_read_reg[2] (\RD.r_channel_0_n_1 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_8 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_9 ),
.\m_payload_i_reg[11] ({SI_REG_n_121,SI_REG_n_122,SI_REG_n_123,SI_REG_n_124}),
.\m_payload_i_reg[35] (SI_REG_n_139),
.\m_payload_i_reg[35]_0 (SI_REG_n_141),
.\m_payload_i_reg[38] (SI_REG_n_164),
.\m_payload_i_reg[3] (SI_REG_n_162),
.\m_payload_i_reg[3]_0 ({SI_REG_n_117,SI_REG_n_118,SI_REG_n_119,SI_REG_n_120}),
.\m_payload_i_reg[46] (\cmd_translator_0/wrap_cmd_0/axaddr_offset ),
.\m_payload_i_reg[47] (SI_REG_n_142),
.\m_payload_i_reg[47]_0 (SI_REG_n_140),
.\m_payload_i_reg[48] (SI_REG_n_143),
.\m_payload_i_reg[6] (SI_REG_n_154),
.r_push_r_reg(\RD.ar_channel_0_n_7 ),
.r_rlast(r_rlast),
.s_arid_r(s_arid_r),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_6 ));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_r_channel \RD.r_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_0 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_arid_r(s_arid_r),
.s_ready_i_reg(SI_REG_n_144),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[35] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_1 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_7 ));
zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axi_register_slice SI_REG
(.CO(SI_REG_n_112),
.D(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_113,SI_REG_n_114,SI_REG_n_115,SI_REG_n_116}),
.Q({s_awid,SI_REG_n_9,SI_REG_n_10,SI_REG_n_11,SI_REG_n_12,si_rs_awlen,si_rs_awburst,SI_REG_n_18,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_34 ,\WR.aw_channel_0_n_35 ,\WR.aw_channel_0_n_36 ,\WR.aw_channel_0_n_37 }),
.UNCONN_OUT(UNCONN_OUT),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr_reg(\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3 ),
.\axaddr_incr_reg[11] (C),
.\axaddr_incr_reg[11]_0 ({SI_REG_n_121,SI_REG_n_122,SI_REG_n_123,SI_REG_n_124}),
.\axaddr_incr_reg[3] ({SI_REG_n_126,SI_REG_n_127,SI_REG_n_128,SI_REG_n_129}),
.\axaddr_incr_reg[3]_0 (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.\axaddr_incr_reg[7] ({SI_REG_n_117,SI_REG_n_118,SI_REG_n_119,SI_REG_n_120}),
.\axaddr_incr_reg[7]_0 (SI_REG_n_125),
.\axaddr_offset_r_reg[0] (SI_REG_n_153),
.\axaddr_offset_r_reg[0]_0 (SI_REG_n_162),
.\axaddr_offset_r_reg[1] (SI_REG_n_132),
.\axaddr_offset_r_reg[1]_0 (SI_REG_n_139),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset ),
.\axaddr_offset_r_reg[2]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1 ),
.\axaddr_offset_r_reg[2]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axaddr_offset_r_reg[3] (SI_REG_n_145),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_154),
.\axlen_cnt_reg[3] (SI_REG_n_134),
.\axlen_cnt_reg[3]_0 (SI_REG_n_142),
.b_push(b_push),
.\cnt_read_reg[0] (SI_REG_n_144),
.\cnt_read_reg[4] (\RD.r_channel_0_n_0 ),
.\cnt_read_reg[4]_0 ({si_rs_rresp,si_rs_rdata}),
.\m_axi_araddr[10] (SI_REG_n_164),
.\m_axi_awaddr[10] (SI_REG_n_163),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_27 ,\RD.ar_channel_0_n_28 ,\RD.ar_channel_0_n_29 ,\RD.ar_channel_0_n_30 }),
.m_valid_i_reg(\ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_135),
.next_pending_r_reg_0(SI_REG_n_136),
.next_pending_r_reg_1(SI_REG_n_140),
.next_pending_r_reg_2(SI_REG_n_143),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[0] ({s_arid,SI_REG_n_57,SI_REG_n_58,SI_REG_n_59,SI_REG_n_60,si_rs_arlen,si_rs_arburst,SI_REG_n_66,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_2 ),
.sel_first_0(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\RD.ar_channel_0_n_9 ),
.\state_reg[1] (\WR.aw_channel_0_n_14 ),
.\state_reg[1]_0 (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\RD.ar_channel_0_n_6 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_8 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151,SI_REG_n_152}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_155,SI_REG_n_156,SI_REG_n_157,SI_REG_n_158,SI_REG_n_159,SI_REG_n_160,SI_REG_n_161}),
.\wrap_second_len_r_reg[3] (SI_REG_n_133),
.\wrap_second_len_r_reg[3]_0 (SI_REG_n_141));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_aw_channel \WR.aw_channel_0
(.CO(SI_REG_n_112),
.D(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_113,SI_REG_n_114,SI_REG_n_115,SI_REG_n_116}),
.Q({s_awid,SI_REG_n_9,SI_REG_n_10,SI_REG_n_11,SI_REG_n_12,si_rs_awlen,si_rs_awburst,SI_REG_n_18,si_rs_awsize,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_34 ,\WR.aw_channel_0_n_35 ,\WR.aw_channel_0_n_36 ,\WR.aw_channel_0_n_37 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3 ),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[11] (C),
.\m_payload_i_reg[35] (SI_REG_n_132),
.\m_payload_i_reg[35]_0 (SI_REG_n_133),
.\m_payload_i_reg[38] (SI_REG_n_163),
.\m_payload_i_reg[3] (SI_REG_n_153),
.\m_payload_i_reg[46] (SI_REG_n_136),
.\m_payload_i_reg[47] (SI_REG_n_134),
.\m_payload_i_reg[48] (SI_REG_n_135),
.\m_payload_i_reg[6] (SI_REG_n_145),
.\m_payload_i_reg[6]_0 ({SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151,SI_REG_n_152}),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_2 ),
.sel_first_reg(\aw_cmd_fsm_0/state ),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_14 ));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_ar_channel
(s_arid_r,
\axaddr_incr_reg[3] ,
sel_first,
\wrap_boundary_axaddr_r_reg[11] ,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\axaddr_offset_r_reg[2] ,
m_axi_arvalid,
r_rlast,
E,
m_axi_araddr,
S,
aclk,
Q,
O,
\m_payload_i_reg[47] ,
si_rs_arvalid,
m_axi_arready,
CO,
\cnt_read_reg[2] ,
\m_payload_i_reg[46] ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[47]_0 ,
areset_d1,
\m_payload_i_reg[48] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[3]_0 ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
D);
output s_arid_r;
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output \wrap_boundary_axaddr_r_reg[11] ;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [1:0]\axaddr_offset_r_reg[2] ;
output m_axi_arvalid;
output r_rlast;
output [0:0]E;
output [11:0]m_axi_araddr;
output [3:0]S;
input aclk;
input [24:0]Q;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_arvalid;
input m_axi_arready;
input [0:0]CO;
input \cnt_read_reg[2] ;
input [1:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[35] ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[47]_0 ;
input areset_d1;
input \m_payload_i_reg[48] ;
input \m_payload_i_reg[6] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [6:0]D;
wire [0:0]CO;
wire [6:0]D;
wire [0:0]E;
wire [3:0]O;
wire [24:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_11;
wire ar_cmd_fsm_0_n_12;
wire ar_cmd_fsm_0_n_13;
wire ar_cmd_fsm_0_n_14;
wire ar_cmd_fsm_0_n_22;
wire ar_cmd_fsm_0_n_23;
wire ar_cmd_fsm_0_n_26;
wire ar_cmd_fsm_0_n_27;
wire ar_cmd_fsm_0_n_6;
wire ar_cmd_fsm_0_n_7;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [3:0]\axaddr_incr_reg[3] ;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_14;
wire cmd_translator_0_n_15;
wire cmd_translator_0_n_6;
wire cmd_translator_0_n_7;
wire cmd_translator_0_n_8;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[2] ;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[3] ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire [1:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[48] ;
wire \m_payload_i_reg[6] ;
wire r_push_r_reg;
wire r_rlast;
wire s_arid_r;
wire sel_first;
wire sel_first_i;
wire si_rs_arvalid;
wire [1:0]state;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [3:0]\wrap_cmd_0/axaddr_offset ;
wire [3:0]\wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\wrap_cmd_0/wrap_second_len ;
wire [3:0]\wrap_cmd_0/wrap_second_len_r ;
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D({ar_cmd_fsm_0_n_6,ar_cmd_fsm_0_n_7,ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(state),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (ar_cmd_fsm_0_n_23),
.axaddr_offset({\wrap_cmd_0/axaddr_offset [3],\wrap_cmd_0/axaddr_offset [0]}),
.\axaddr_offset_r_reg[3] ({\wrap_cmd_0/axaddr_offset_r [3],\wrap_cmd_0/axaddr_offset_r [0]}),
.\axaddr_wrap_reg[11] (ar_cmd_fsm_0_n_22),
.\axlen_cnt_reg[3] (cmd_translator_0_n_11),
.\axlen_cnt_reg[4] (cmd_translator_0_n_15),
.\axlen_cnt_reg[5] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[6] ({cmd_translator_0_n_7,cmd_translator_0_n_8,cmd_translator_0_n_9,cmd_translator_0_n_10}),
.\axlen_cnt_reg[7] (cmd_translator_0_n_12),
.\cnt_read_reg[2] (\cnt_read_reg[2] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[35]_0 (\m_payload_i_reg[35]_0 ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] [1]),
.\m_payload_i_reg[50] ({Q[22:21],Q[19],Q[17:16]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq1_reg(cmd_translator_0_n_14),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_26),
.sel_first_reg_0(ar_cmd_fsm_0_n_27),
.sel_first_reg_1(cmd_translator_0_n_0),
.sel_first_reg_2(sel_first),
.sel_first_reg_3(cmd_translator_0_n_6),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_cnt_r_reg[0] (ar_cmd_fsm_0_n_14),
.\wrap_cnt_r_reg[3] ({ar_cmd_fsm_0_n_11,ar_cmd_fsm_0_n_12,ar_cmd_fsm_0_n_13}),
.\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len_r ));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 cmd_translator_0
(.CO(CO),
.D({ar_cmd_fsm_0_n_6,ar_cmd_fsm_0_n_7,ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_7,cmd_translator_0_n_8,cmd_translator_0_n_9,cmd_translator_0_n_10}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] ({\wrap_cmd_0/axaddr_offset_r [3],\axaddr_offset_r_reg[2] ,\wrap_cmd_0/axaddr_offset_r [0]}),
.\axaddr_offset_r_reg[3]_0 (ar_cmd_fsm_0_n_14),
.\axaddr_offset_r_reg[3]_1 ({\wrap_cmd_0/axaddr_offset [3],\m_payload_i_reg[46] ,\wrap_cmd_0/axaddr_offset [0]}),
.\axlen_cnt_reg[5] (cmd_translator_0_n_15),
.\axlen_cnt_reg[7] (cmd_translator_0_n_11),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3]_0 ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[51] ({Q[23],Q[20:0]}),
.\m_payload_i_reg[6] (D),
.m_valid_i_reg(ar_cmd_fsm_0_n_22),
.next_pending_r_reg(cmd_translator_0_n_12),
.r_rlast(r_rlast),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_0),
.sel_first_reg_1(cmd_translator_0_n_6),
.sel_first_reg_2(ar_cmd_fsm_0_n_23),
.sel_first_reg_3(ar_cmd_fsm_0_n_26),
.sel_first_reg_4(ar_cmd_fsm_0_n_27),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0] (ar_cmd_fsm_0_n_0),
.\state_reg[0]_rep (cmd_translator_0_n_14),
.\state_reg[1] (state),
.\state_reg[1]_rep (r_push_r_reg),
.\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_1 ({ar_cmd_fsm_0_n_11,ar_cmd_fsm_0_n_12,ar_cmd_fsm_0_n_13}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(s_arid_r),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_aw_channel
(in,
\axaddr_incr_reg[3] ,
sel_first,
\wrap_boundary_axaddr_r_reg[11] ,
sel_first_reg,
\axaddr_offset_r_reg[2] ,
E,
b_push,
m_axi_awvalid,
m_axi_awaddr,
S,
aclk,
Q,
O,
\m_payload_i_reg[47] ,
CO,
si_rs_awvalid,
D,
\m_payload_i_reg[35] ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[48] ,
areset_d1,
\m_payload_i_reg[46] ,
\m_payload_i_reg[6] ,
\cnt_read_reg[0]_rep ,
\cnt_read_reg[1]_rep__0 ,
m_axi_awready,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\m_payload_i_reg[6]_0 );
output [8:0]in;
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]sel_first_reg;
output [1:0]\axaddr_offset_r_reg[2] ;
output [0:0]E;
output b_push;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [3:0]S;
input aclk;
input [24:0]Q;
input [3:0]O;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input si_rs_awvalid;
input [1:0]D;
input \m_payload_i_reg[35] ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[48] ;
input areset_d1;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[6] ;
input \cnt_read_reg[0]_rep ;
input \cnt_read_reg[1]_rep__0 ;
input m_axi_awready;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [24:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_14;
wire aw_cmd_fsm_0_n_18;
wire aw_cmd_fsm_0_n_20;
wire aw_cmd_fsm_0_n_24;
wire aw_cmd_fsm_0_n_25;
wire aw_cmd_fsm_0_n_5;
wire [3:0]\axaddr_incr_reg[3] ;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[0]_rep ;
wire \cnt_read_reg[1]_rep__0 ;
wire [8:0]in;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[3] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[48] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire next;
wire [0:0]p_1_in;
wire sel_first;
wire sel_first__0;
wire sel_first_i;
wire [1:0]sel_first_reg;
wire si_rs_awvalid;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [3:0]\wrap_cmd_0/axaddr_offset ;
wire [3:0]\wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\wrap_cmd_0/wrap_second_len ;
wire [3:0]\wrap_cmd_0/wrap_second_len_r ;
wire [3:0]wrap_cnt;
wire wrap_next_pending;
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D({wrap_cnt[3:2],wrap_cnt[0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(sel_first_reg),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset({\wrap_cmd_0/axaddr_offset [3],\wrap_cmd_0/axaddr_offset [0]}),
.\axaddr_offset_r_reg[3] ({\wrap_cmd_0/axaddr_offset_r [3],\wrap_cmd_0/axaddr_offset_r [0]}),
.\axaddr_wrap_reg[0] (aw_cmd_fsm_0_n_20),
.\axlen_cnt_reg[0] (p_1_in),
.\axlen_cnt_reg[0]_0 (cmd_translator_0_n_9),
.\axlen_cnt_reg[2] (cmd_translator_0_n_12),
.\axlen_cnt_reg[4] (cmd_translator_0_n_10),
.b_push(b_push),
.\cnt_read_reg[0]_rep (\cnt_read_reg[0]_rep ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[35]_0 (\m_payload_i_reg[35]_0 ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[46] (D[1]),
.\m_payload_i_reg[46]_0 (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] ({Q[19],Q[16:15]}),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_14),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_18),
.s_axburst_eq1_reg_0(cmd_translator_0_n_11),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_24),
.sel_first_reg_0(aw_cmd_fsm_0_n_25),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_cnt_r_reg[0] (aw_cmd_fsm_0_n_5),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len_r ));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_cmd_translator cmd_translator_0
(.CO(CO),
.D(p_1_in),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q(Q[23:0]),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] ({\wrap_cmd_0/axaddr_offset_r [3],\axaddr_offset_r_reg[2] ,\wrap_cmd_0/axaddr_offset_r [0]}),
.\axaddr_offset_r_reg[3]_0 (aw_cmd_fsm_0_n_5),
.\axaddr_offset_r_reg[3]_1 ({\wrap_cmd_0/axaddr_offset [3],D,\wrap_cmd_0/axaddr_offset [0]}),
.\axlen_cnt_reg[3] (cmd_translator_0_n_9),
.\axlen_cnt_reg[3]_0 (cmd_translator_0_n_10),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_14),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_18),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_12),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_24),
.sel_first_reg_2(aw_cmd_fsm_0_n_25),
.\state_reg[0] (aw_cmd_fsm_0_n_20),
.\state_reg[1] (cmd_translator_0_n_11),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3]_0 ({wrap_cnt[3:2],wrap_cnt[0]}),
.\wrap_second_len_r_reg[3]_1 (\wrap_cmd_0/wrap_second_len ));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[19]),
.Q(in[3]),
.R(1'b0));
FDRE \s_awlen_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awlen_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awlen_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awlen_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(in[7]),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep ,
\cnt_read_reg[1]_rep__0 ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bresp,
m_axi_bvalid,
in);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep ;
output \cnt_read_reg[1]_rep__0 ;
output m_axi_bready;
output [0:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
input [8:0]in;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_4;
wire bid_fifo_0_n_5;
wire \bresp_cnt[7]_i_3_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep ;
wire \cnt_read_reg[1]_rep__0 ;
wire [8:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [0:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_4),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bresp_push(bresp_push),
.bvalid_i_reg(bid_fifo_0_n_5),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_rep_0 (\cnt_read_reg[0]_rep ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_3
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_3_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_4),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.bresp_push(bresp_push),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.s_bresp_acc(s_bresp_acc),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_5),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT5 #(
.INIT(32'h000000E2))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(s_bresp_acc),
.I2(m_axi_bresp[0]),
.I3(bresp_push),
.I4(areset_d1),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\s_bresp_acc[1]_i_1
(.I0(\s_bresp_acc_reg_n_0_[1] ),
.I1(s_bresp_acc),
.I2(m_axi_bresp[1]),
.I3(bresp_push),
.I4(areset_d1),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first__0,
\axlen_cnt_reg[3] ,
\axlen_cnt_reg[3]_0 ,
\state_reg[1] ,
next_pending_r_reg_1,
m_axi_awaddr,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
O,
sel_first_reg_1,
sel_first_reg_2,
E,
Q,
\m_payload_i_reg[47] ,
CO,
D,
next,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
\state_reg[0] ,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first__0;
output [0:0]\axlen_cnt_reg[3] ;
output \axlen_cnt_reg[3]_0 ;
output \state_reg[1] ;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input [3:0]O;
input sel_first_reg_1;
input sel_first_reg_2;
input [0:0]E;
input [23:0]Q;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]D;
input next;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input \axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]\state_reg[0] ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [3:0]O;
wire [23:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire [0:0]\axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire incr_cmd_0_n_16;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire [0:0]\state_reg[0] ;
wire \state_reg[1] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_incr_cmd incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(\axlen_cnt_reg[3] ),
.S(S),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3]_0 ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[1] (incr_cmd_0_n_16),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({Q[23:20],Q[18:17],Q[14:12],Q[3:0]}),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.\state_reg[0] (\state_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(Q[15]),
.I2(s_axburst_eq0),
.O(\state_reg[1] ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_wrap_cmd wrap_cmd_0
(.E(E),
.Q({Q[19:15],Q[13:0]}),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3:2],\axaddr_incr_reg[3] [0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first__0),
.sel_first_reg_1(sel_first_reg_2),
.sel_first_reg_2(incr_cmd_0_n_16),
.\state_reg[0] (\state_reg[0] ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_1 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_0 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_cmd_translator" *)
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
(sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first_reg_1,
Q,
\axlen_cnt_reg[7] ,
next_pending_r_reg,
r_rlast,
\state_reg[0]_rep ,
\axlen_cnt_reg[5] ,
m_axi_araddr,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
S,
aclk,
sel_first_i,
sel_first_reg_2,
O,
sel_first_reg_3,
sel_first_reg_4,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
\state_reg[1] ,
si_rs_arvalid,
CO,
\m_payload_i_reg[47]_0 ,
\state_reg[1]_rep ,
\m_payload_i_reg[48] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
m_valid_i_reg,
D,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
m_axi_arready);
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first_reg_1;
output [3:0]Q;
output \axlen_cnt_reg[7] ;
output next_pending_r_reg;
output r_rlast;
output \state_reg[0]_rep ;
output \axlen_cnt_reg[5] ;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input aclk;
input sel_first_i;
input sel_first_reg_2;
input [3:0]O;
input sel_first_reg_3;
input sel_first_reg_4;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [21:0]\m_payload_i_reg[51] ;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input [0:0]CO;
input \m_payload_i_reg[47]_0 ;
input \state_reg[1]_rep ;
input \m_payload_i_reg[48] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input \axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]m_valid_i_reg;
input [3:0]D;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input m_axi_arready;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[5] ;
wire \axlen_cnt_reg[7] ;
wire incr_cmd_0_n_20;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[48] ;
wire [21:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire wrap_cmd_0_n_1;
wire wrap_cmd_0_n_2;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11]_0 ({axaddr_incr_reg[11:7],axaddr_incr_reg[5:4]}),
.\axaddr_incr_reg[11]_1 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.\axlen_cnt_reg[5]_0 (\axlen_cnt_reg[5] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[6] (incr_cmd_0_n_20),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [21:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [6],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_3),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_1),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_2),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 wrap_cmd_0
(.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({axaddr_incr_reg[11:7],axaddr_incr_reg[5:4]}),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.s_axburst_eq0_reg(wrap_cmd_0_n_1),
.s_axburst_eq1_reg(wrap_cmd_0_n_2),
.sel_first_i(sel_first_i),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_4),
.sel_first_reg_2(incr_cmd_0_n_20),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
axaddr_incr_reg,
\axaddr_incr_reg[11]_0 ,
Q,
\axlen_cnt_reg[3]_0 ,
\m_axi_awaddr[1] ,
S,
incr_next_pending,
aclk,
O,
sel_first_reg_0,
\m_payload_i_reg[47] ,
E,
CO,
\m_payload_i_reg[51] ,
next,
\m_payload_i_reg[11] ,
\state_reg[0] ,
D);
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [7:0]axaddr_incr_reg;
output \axaddr_incr_reg[11]_0 ;
output [0:0]Q;
output \axlen_cnt_reg[3]_0 ;
output \m_axi_awaddr[1] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input [3:0]O;
input sel_first_reg_0;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [0:0]CO;
input [12:0]\m_payload_i_reg[51] ;
input next;
input [7:0]\m_payload_i_reg[11] ;
input [0:0]\state_reg[0] ;
input [0:0]D;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [3:0]O;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[0]_i_1_n_0 ;
wire \axaddr_incr[4]_i_2_n_0 ;
wire \axaddr_incr[4]_i_3_n_0 ;
wire \axaddr_incr[4]_i_4_n_0 ;
wire \axaddr_incr[4]_i_5_n_0 ;
wire \axaddr_incr[8]_i_2_n_0 ;
wire \axaddr_incr[8]_i_3_n_0 ;
wire \axaddr_incr[8]_i_4_n_0 ;
wire \axaddr_incr[8]_i_5_n_0 ;
wire [7:0]axaddr_incr_reg;
wire \axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1_n_0 ;
wire \axaddr_incr_reg[4]_i_1_n_1 ;
wire \axaddr_incr_reg[4]_i_1_n_2 ;
wire \axaddr_incr_reg[4]_i_1_n_3 ;
wire \axaddr_incr_reg[4]_i_1_n_4 ;
wire \axaddr_incr_reg[4]_i_1_n_5 ;
wire \axaddr_incr_reg[4]_i_1_n_6 ;
wire \axaddr_incr_reg[4]_i_1_n_7 ;
wire \axaddr_incr_reg[8]_i_1_n_1 ;
wire \axaddr_incr_reg[8]_i_1_n_2 ;
wire \axaddr_incr_reg[8]_i_1_n_3 ;
wire \axaddr_incr_reg[8]_i_1_n_4 ;
wire \axaddr_incr_reg[8]_i_1_n_5 ;
wire \axaddr_incr_reg[8]_i_1_n_6 ;
wire \axaddr_incr_reg[8]_i_1_n_7 ;
wire \axlen_cnt[3]_i_1__0_n_0 ;
wire \axlen_cnt[4]_i_2_n_0 ;
wire \axlen_cnt[4]_i_3_n_0 ;
wire \axlen_cnt[4]_i_4_n_0 ;
wire \axlen_cnt[5]_i_2_n_0 ;
wire \axlen_cnt[7]_i_3_n_0 ;
wire \axlen_cnt_reg[3]_0 ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[1] ;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[47] ;
wire [12:0]\m_payload_i_reg[51] ;
wire next;
wire next_pending_r_i_5_n_0;
wire next_pending_r_reg_0;
wire [7:1]p_1_in;
wire sel_first_reg_0;
wire [0:0]\state_reg[0] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'hE))
\axaddr_incr[0]_i_1
(.I0(\axaddr_incr_reg[11]_0 ),
.I1(next),
.O(\axaddr_incr[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(next),
.I2(\m_payload_i_reg[51] [5]),
.I3(\m_payload_i_reg[51] [4]),
.O(S[3]));
LUT4 #(
.INIT(16'h0A6A))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(next),
.I2(\m_payload_i_reg[51] [5]),
.I3(\m_payload_i_reg[51] [4]),
.O(S[2]));
LUT4 #(
.INIT(16'h006A))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(next),
.I2(\m_payload_i_reg[51] [4]),
.I3(\m_payload_i_reg[51] [5]),
.O(S[1]));
LUT4 #(
.INIT(16'h0006))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(next),
.I2(\m_payload_i_reg[51] [5]),
.I3(\m_payload_i_reg[51] [4]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[3]),
.O(\axaddr_incr[4]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[2]),
.O(\axaddr_incr[4]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[1]),
.O(\axaddr_incr[4]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[0]),
.O(\axaddr_incr[4]_i_5_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2
(.I0(\m_payload_i_reg[11] [7]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[7]),
.O(\axaddr_incr[8]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3
(.I0(\m_payload_i_reg[11] [6]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[6]),
.O(\axaddr_incr[8]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4
(.I0(\m_payload_i_reg[11] [5]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[5]),
.O(\axaddr_incr[8]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5
(.I0(\m_payload_i_reg[11] [4]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[4]),
.O(\axaddr_incr[8]_i_5_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[8]_i_1_n_5 ),
.Q(axaddr_incr_reg[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[8]_i_1_n_4 ),
.Q(axaddr_incr_reg[7]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[4]_i_1_n_7 ),
.Q(axaddr_incr_reg[0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1_n_0 ,\axaddr_incr_reg[4]_i_1_n_1 ,\axaddr_incr_reg[4]_i_1_n_2 ,\axaddr_incr_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1_n_4 ,\axaddr_incr_reg[4]_i_1_n_5 ,\axaddr_incr_reg[4]_i_1_n_6 ,\axaddr_incr_reg[4]_i_1_n_7 }),
.S({\axaddr_incr[4]_i_2_n_0 ,\axaddr_incr[4]_i_3_n_0 ,\axaddr_incr[4]_i_4_n_0 ,\axaddr_incr[4]_i_5_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[4]_i_1_n_6 ),
.Q(axaddr_incr_reg[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[4]_i_1_n_5 ),
.Q(axaddr_incr_reg[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[4]_i_1_n_4 ),
.Q(axaddr_incr_reg[3]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[8]_i_1_n_7 ),
.Q(axaddr_incr_reg[4]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1
(.CI(\axaddr_incr_reg[4]_i_1_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1_n_1 ,\axaddr_incr_reg[8]_i_1_n_2 ,\axaddr_incr_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1_n_4 ,\axaddr_incr_reg[8]_i_1_n_5 ,\axaddr_incr_reg[8]_i_1_n_6 ,\axaddr_incr_reg[8]_i_1_n_7 }),
.S({\axaddr_incr[8]_i_2_n_0 ,\axaddr_incr[8]_i_3_n_0 ,\axaddr_incr[8]_i_4_n_0 ,\axaddr_incr[8]_i_5_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[8]_i_1_n_6 ),
.Q(axaddr_incr_reg[5]),
.R(1'b0));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[51] [7]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg[3]_0 ),
.O(p_1_in[1]));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[51] [8]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg[3]_0 ),
.O(p_1_in[2]));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg[3]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h8B88888B))
\axlen_cnt[4]_i_1
(.I0(\m_payload_i_reg[51] [9]),
.I1(E),
.I2(\axlen_cnt[4]_i_2_n_0 ),
.I3(\axlen_cnt[4]_i_3_n_0 ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.O(p_1_in[4]));
LUT6 #(
.INIT(64'h0000000000000001))
\axlen_cnt[4]_i_2
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.I4(\axlen_cnt_reg_n_0_[6] ),
.I5(\axlen_cnt[4]_i_4_n_0 ),
.O(\axlen_cnt[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_3
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'hE))
\axlen_cnt[4]_i_4
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_4_n_0 ));
LUT5 #(
.INIT(32'h8FF88888))
\axlen_cnt[5]_i_1
(.I0(E),
.I1(\m_payload_i_reg[51] [10]),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt[5]_i_2_n_0 ),
.I4(\axlen_cnt_reg[3]_0 ),
.O(p_1_in[5]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[5]_i_2
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFF282828))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg[3]_0 ),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt[7]_i_3_n_0 ),
.I3(E),
.I4(\m_payload_i_reg[51] [11]),
.O(p_1_in[6]));
LUT6 #(
.INIT(64'hFFFF828882888288))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg[3]_0 ),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt[7]_i_3_n_0 ),
.I4(E),
.I5(\m_payload_i_reg[51] [12]),
.O(p_1_in[7]));
LUT6 #(
.INIT(64'h0000000000000001))
\axlen_cnt[7]_i_3
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(\axlen_cnt_reg_n_0_[5] ),
.O(\axlen_cnt[7]_i_3_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(D),
.Q(Q),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(p_1_in[1]),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(p_1_in[2]),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(p_1_in[4]),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(p_1_in[5]),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(p_1_in[6]),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(p_1_in[7]),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[1]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_0 ),
.I1(\axaddr_incr_reg[3]_0 [1]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\m_payload_i_reg[51] [1]),
.O(\m_axi_awaddr[1] ));
LUT5 #(
.INIT(32'h55555554))
next_pending_r_i_3__1
(.I0(E),
.I1(next_pending_r_i_5_n_0),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[5] ),
.O(\axlen_cnt_reg[3]_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_5
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_5_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[11]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_incr_cmd" *)
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
(incr_next_pending,
\axaddr_incr_reg[3]_0 ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[11]_1 ,
Q,
\axlen_cnt_reg[7]_0 ,
next_pending_r_reg_0,
\axlen_cnt_reg[5]_0 ,
\m_axi_araddr[6] ,
S,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[48] ,
\m_payload_i_reg[47]_0 ,
\state_reg[1]_rep ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
m_axi_arready);
output incr_next_pending;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [6:0]\axaddr_incr_reg[11]_0 ;
output \axaddr_incr_reg[11]_1 ;
output [3:0]Q;
output \axlen_cnt_reg[7]_0 ;
output next_pending_r_reg_0;
output \axlen_cnt_reg[5]_0 ;
output \m_axi_araddr[6] ;
output [3:0]S;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [10:0]\m_payload_i_reg[51] ;
input \m_payload_i_reg[48] ;
input \m_payload_i_reg[47]_0 ;
input \state_reg[1]_rep ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [3:0]D;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2__0_n_0 ;
wire \axaddr_incr[4]_i_3__0_n_0 ;
wire \axaddr_incr[4]_i_4__0_n_0 ;
wire \axaddr_incr[4]_i_5__0_n_0 ;
wire \axaddr_incr[8]_i_2__0_n_0 ;
wire \axaddr_incr[8]_i_3__0_n_0 ;
wire \axaddr_incr[8]_i_4__0_n_0 ;
wire \axaddr_incr[8]_i_5__0_n_0 ;
wire [6:6]axaddr_incr_reg;
wire [6:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_1 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_1 ;
wire \axaddr_incr_reg[4]_i_1__0_n_2 ;
wire \axaddr_incr_reg[4]_i_1__0_n_3 ;
wire \axaddr_incr_reg[4]_i_1__0_n_4 ;
wire \axaddr_incr_reg[4]_i_1__0_n_5 ;
wire \axaddr_incr_reg[4]_i_1__0_n_6 ;
wire \axaddr_incr_reg[4]_i_1__0_n_7 ;
wire \axaddr_incr_reg[8]_i_1__0_n_1 ;
wire \axaddr_incr_reg[8]_i_1__0_n_2 ;
wire \axaddr_incr_reg[8]_i_1__0_n_3 ;
wire \axaddr_incr_reg[8]_i_1__0_n_4 ;
wire \axaddr_incr_reg[8]_i_1__0_n_5 ;
wire \axaddr_incr_reg[8]_i_1__0_n_6 ;
wire \axaddr_incr_reg[8]_i_1__0_n_7 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[4]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt_reg[5]_0 ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[6] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[48] ;
wire [10:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_5__0_n_0;
wire next_pending_r_reg_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[1]));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [2]),
.O(\axaddr_incr[4]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(axaddr_incr_reg),
.O(\axaddr_incr[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [1]),
.O(\axaddr_incr[4]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [0]),
.O(\axaddr_incr[4]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2__0
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [6]),
.O(\axaddr_incr[8]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3__0
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [5]),
.O(\axaddr_incr[8]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4__0
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [4]),
.O(\axaddr_incr[8]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5__0
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [3]),
.O(\axaddr_incr[8]_i_5__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1__0
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1__0_n_0 ,\axaddr_incr_reg[4]_i_1__0_n_1 ,\axaddr_incr_reg[4]_i_1__0_n_2 ,\axaddr_incr_reg[4]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1__0_n_4 ,\axaddr_incr_reg[4]_i_1__0_n_5 ,\axaddr_incr_reg[4]_i_1__0_n_6 ,\axaddr_incr_reg[4]_i_1__0_n_7 }),
.S({\axaddr_incr[4]_i_2__0_n_0 ,\axaddr_incr[4]_i_3__0_n_0 ,\axaddr_incr[4]_i_4__0_n_0 ,\axaddr_incr[4]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_6 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_5 ),
.Q(axaddr_incr_reg),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1__0
(.CI(\axaddr_incr_reg[4]_i_1__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1__0_n_1 ,\axaddr_incr_reg[8]_i_1__0_n_2 ,\axaddr_incr_reg[8]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1__0_n_4 ,\axaddr_incr_reg[8]_i_1__0_n_5 ,\axaddr_incr_reg[8]_i_1__0_n_6 ,\axaddr_incr_reg[8]_i_1__0_n_7 }),
.S({\axaddr_incr[8]_i_2__0_n_0 ,\axaddr_incr[8]_i_3__0_n_0 ,\axaddr_incr[8]_i_4__0_n_0 ,\axaddr_incr[8]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_6 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[51] [8]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt[4]_i_2__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [9]),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[1]),
.I3(Q[0]),
.O(\axlen_cnt[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[5]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(Q[0]),
.I2(Q[1]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt_reg[5]_0 ));
LUT6 #(
.INIT(64'hF88888F8F888F888))
\axlen_cnt[7]_i_2__0
(.I0(E),
.I1(\m_payload_i_reg[51] [10]),
.I2(\state_reg[0] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.I4(Q[3]),
.I5(\axlen_cnt_reg[7]_0 ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\axlen_cnt[7]_i_4
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(Q[2]),
.O(\axlen_cnt_reg[7]_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[6]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(axaddr_incr_reg),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [4]),
.O(\m_axi_araddr[6] ));
LUT6 #(
.INIT(64'hDDDDCCFCFFDDFFFC))
next_pending_r_i_1__2
(.I0(\m_payload_i_reg[48] ),
.I1(\m_payload_i_reg[47]_0 ),
.I2(next_pending_r_reg_n_0),
.I3(\state_reg[1]_rep ),
.I4(E),
.I5(next_pending_r_reg_0),
.O(incr_next_pending));
LUT4 #(
.INIT(16'h0002))
next_pending_r_i_4__0
(.I0(next_pending_r_i_5__0_n_0),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(Q[3]),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(next_pending_r_reg_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_5__0
(.I0(Q[1]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(Q[2]),
.O(next_pending_r_i_5__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_1 ),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_r_channel
(m_valid_i_reg,
\state_reg[1]_rep ,
m_axi_rready,
out,
\skid_buffer_reg[35] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_arid_r,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output m_axi_rready;
output [33:0]out;
output [1:0]\skid_buffer_reg[35] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_arid_r;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_3;
wire rd_data_fifo_0_n_5;
wire s_arid_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [1:0]\skid_buffer_reg[35] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [1:0]trans_in;
wire transaction_fifo_0_n_2;
wire wr_en0;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(s_arid_r),
.Q(trans_in[1]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[3]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_0 (m_valid_i_reg),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_3),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.s_ready_i_reg_0(transaction_fifo_0_n_2),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_5),
.wr_en0(wr_en0));
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__2 (rd_data_fifo_0_n_5),
.\cnt_read_reg[0]_rep__2_0 (rd_data_fifo_0_n_3),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (transaction_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[35] (\skid_buffer_reg[35] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wr_en0(wr_en0));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
(\axlen_cnt_reg[5] ,
Q,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
D,
E,
\wrap_cnt_r_reg[3] ,
\wrap_cnt_r_reg[0] ,
axaddr_offset,
\wrap_second_len_r_reg[3] ,
sel_first_i,
\axaddr_wrap_reg[11] ,
\axaddr_incr_reg[11] ,
m_axi_arvalid,
\m_payload_i_reg[0]_1 ,
sel_first_reg,
sel_first_reg_0,
si_rs_arvalid,
\axlen_cnt_reg[7] ,
m_axi_arready,
s_axburst_eq1_reg,
\cnt_read_reg[2] ,
\axlen_cnt_reg[6] ,
\axlen_cnt_reg[4] ,
\m_payload_i_reg[50] ,
\axlen_cnt_reg[3] ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[46] ,
\axaddr_offset_r_reg[3] ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
areset_d1,
sel_first_reg_1,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first_reg_3,
aclk);
output \axlen_cnt_reg[5] ;
output [1:0]Q;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [3:0]D;
output [0:0]E;
output [2:0]\wrap_cnt_r_reg[3] ;
output \wrap_cnt_r_reg[0] ;
output [1:0]axaddr_offset;
output [3:0]\wrap_second_len_r_reg[3] ;
output sel_first_i;
output [0:0]\axaddr_wrap_reg[11] ;
output \axaddr_incr_reg[11] ;
output m_axi_arvalid;
output [0:0]\m_payload_i_reg[0]_1 ;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_arvalid;
input \axlen_cnt_reg[7] ;
input m_axi_arready;
input s_axburst_eq1_reg;
input \cnt_read_reg[2] ;
input [3:0]\axlen_cnt_reg[6] ;
input \axlen_cnt_reg[4] ;
input [4:0]\m_payload_i_reg[50] ;
input \axlen_cnt_reg[3] ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]\m_payload_i_reg[46] ;
input [1:0]\axaddr_offset_r_reg[3] ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input areset_d1;
input sel_first_reg_1;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first_reg_3;
input aclk;
wire [3:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [1:0]axaddr_offset;
wire [1:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[5] ;
wire [3:0]\axlen_cnt_reg[6] ;
wire \axlen_cnt_reg[7] ;
wire \cnt_read_reg[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [0:0]\m_payload_i_reg[46] ;
wire [4:0]\m_payload_i_reg[50] ;
wire \m_payload_i_reg[6] ;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq1_reg;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire \wrap_cnt_r[3]_i_2__0_n_0 ;
wire \wrap_cnt_r_reg[0] ;
wire [2:0]\wrap_cnt_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[0]_i_1__0
(.I0(sel_first_reg_2),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAC0AAAA))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [0]),
.I1(\m_payload_i_reg[3] ),
.I2(\m_payload_i_reg[50] [0]),
.I3(Q[0]),
.I4(si_rs_arvalid),
.I5(Q[1]),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [1]),
.I1(\m_payload_i_reg[50] [2]),
.I2(\m_payload_i_reg[0]_0 ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[6] ),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__1
(.I0(Q[1]),
.I1(si_rs_arvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[50] [0]),
.I4(\axlen_cnt_reg[6] [0]),
.I5(\axlen_cnt_reg[5] ),
.O(D[0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[50] [1]),
.I2(\axlen_cnt_reg[6] [1]),
.I3(\axlen_cnt_reg[6] [0]),
.I4(\axlen_cnt_reg[5] ),
.O(D[1]));
LUT5 #(
.INIT(32'hFF282828))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg[5] ),
.I1(\axlen_cnt_reg[6] [2]),
.I2(\axlen_cnt_reg[4] ),
.I3(E),
.I4(\m_payload_i_reg[50] [3]),
.O(D[2]));
LUT5 #(
.INIT(32'hFF282828))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg[5] ),
.I1(\axlen_cnt_reg[6] [3]),
.I2(\axlen_cnt_reg[3] ),
.I3(E),
.I4(\m_payload_i_reg[50] [4]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[7]_i_1__0
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_wrap_reg[11] ));
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_3__0
(.I0(Q[0]),
.I1(si_rs_arvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[7] ),
.O(\axlen_cnt_reg[5] ));
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(m_axi_arready),
.O(r_push_r_reg));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__0
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\m_payload_i_reg[0]_0 ),
.I4(m_axi_arready),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__4
(.I0(m_axi_arready),
.I1(sel_first_reg_3),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg),
.I5(\cnt_read_reg[2] ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1__0
(.I0(\cnt_read_reg[2] ),
.I1(s_axburst_eq1_reg),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(\m_payload_i_reg[0] ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(axaddr_offset[0]),
.O(\wrap_cnt_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(E),
.I3(\wrap_cnt_r_reg[0] ),
.I4(axaddr_offset[0]),
.I5(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [1]));
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [3]),
.I1(\wrap_second_len_r_reg[3] [1]),
.I2(\wrap_cnt_r[3]_i_2__0_n_0 ),
.I3(\wrap_second_len_r_reg[3] [2]),
.O(\wrap_cnt_r_reg[3] [2]));
LUT6 #(
.INIT(64'hD1D1D1D1D1D1DFD1))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(axaddr_offset[0]),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[46] ),
.I5(axaddr_offset[1]),
.O(\wrap_cnt_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(axaddr_offset[0]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'h0000000004000404))
\wrap_second_len_r[0]_i_2__0
(.I0(axaddr_offset[0]),
.I1(\m_payload_i_reg[35] ),
.I2(\m_payload_i_reg[46] ),
.I3(E),
.I4(\axaddr_offset_r_reg[3] [1]),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_cnt_r_reg[0] ));
LUT6 #(
.INIT(64'h0FE0FFFF0FE00000))
\wrap_second_len_r[1]_i_1__0
(.I0(axaddr_offset[1]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[35] ),
.I3(axaddr_offset[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hCC2CFFFFCC2C0000))
\wrap_second_len_r[2]_i_1__0
(.I0(axaddr_offset[1]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[35] ),
.I3(axaddr_offset[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hFFFFF4FF44444444))
\wrap_second_len_r[3]_i_1__0
(.I0(E),
.I1(\wrap_second_len_r_reg[3]_0 [3]),
.I2(axaddr_offset[0]),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[46] ),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_second_len_r_reg[3] [3]));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_simple_fifo
(\cnt_read_reg[0]_rep_0 ,
\cnt_read_reg[1]_rep__0_0 ,
SR,
bresp_push,
D,
bvalid_i_reg,
out,
shandshake_r,
b_push,
areset_d1,
Q,
\bresp_cnt_reg[7] ,
mhandshake_r,
bvalid_i_reg_0,
si_rs_bready,
in,
aclk);
output \cnt_read_reg[0]_rep_0 ;
output \cnt_read_reg[1]_rep__0_0 ;
output [0:0]SR;
output bresp_push;
output [0:0]D;
output bvalid_i_reg;
output [0:0]out;
input shandshake_r;
input b_push;
input areset_d1;
input [1:0]Q;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input bvalid_i_reg_0;
input si_rs_bready;
input [8:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire [7:0]\bresp_cnt_reg[7] ;
wire bresp_push;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_rep_0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [8:0]in;
wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_i_4_n_0 ;
wire \memory_reg[3][0]_srl4_i_5_n_0 ;
wire \memory_reg[3][0]_srl4_i_6_n_0 ;
wire \memory_reg[3][0]_srl4_i_7_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire \memory_reg[3][4]_srl4_n_0 ;
wire \memory_reg[3][5]_srl4_n_0 ;
wire \memory_reg[3][6]_srl4_n_0 ;
wire \memory_reg[3][7]_srl4_n_0 ;
wire mhandshake_r;
wire [0:0]out;
wire shandshake_r;
wire si_rs_bready;
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT2 #(
.INIT(4'hE))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(bresp_push),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT4 #(
.INIT(16'h002A))
bvalid_i_i_1
(.I0(bvalid_i_i_2_n_0),
.I1(bvalid_i_reg_0),
.I2(si_rs_bready),
.I3(areset_d1),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[0]_rep_0 ),
.I1(\cnt_read_reg[1]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1
(.I0(\cnt_read_reg[0]_rep_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(bresp_push),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT4 #(
.INIT(16'hDB24))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep_0 ),
.I1(shandshake_r),
.I2(b_push),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1_n_0 ),
.Q(\cnt_read_reg[0]_rep_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
LUT4 #(
.INIT(16'h0002))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
.I1(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I2(\memory_reg[3][0]_srl4_i_4_n_0 ),
.I3(\memory_reg[3][0]_srl4_i_5_n_0 ),
.O(bresp_push));
LUT6 #(
.INIT(64'h9009000000009009))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\bresp_cnt_reg[7] [7]),
.I1(\memory_reg[3][7]_srl4_n_0 ),
.I2(\memory_reg[3][1]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [1]),
.I4(\memory_reg[3][0]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [0]),
.O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hFFFF22F2))
\memory_reg[3][0]_srl4_i_3
(.I0(\bresp_cnt_reg[7] [3]),
.I1(\memory_reg[3][3]_srl4_n_0 ),
.I2(\memory_reg[3][6]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [6]),
.I4(\memory_reg[3][0]_srl4_i_6_n_0 ),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF4F4FFF4F))
\memory_reg[3][0]_srl4_i_4
(.I0(\memory_reg[3][6]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [6]),
.I2(mhandshake_r),
.I3(\memory_reg[3][3]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][0]_srl4_i_7_n_0 ),
.O(\memory_reg[3][0]_srl4_i_4_n_0 ));
LUT6 #(
.INIT(64'h66F666F6FFFF66F6))
\memory_reg[3][0]_srl4_i_5
(.I0(\bresp_cnt_reg[7] [2]),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [4]),
.I3(\memory_reg[3][4]_srl4_n_0 ),
.I4(\memory_reg[3][5]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [5]),
.O(\memory_reg[3][0]_srl4_i_5_n_0 ));
LUT4 #(
.INIT(16'h4F44))
\memory_reg[3][0]_srl4_i_6
(.I0(\memory_reg[3][5]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [5]),
.I2(\bresp_cnt_reg[7] [4]),
.I3(\memory_reg[3][4]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_6_n_0 ));
LUT2 #(
.INIT(4'h8))
\memory_reg[3][0]_srl4_i_7
(.I0(\cnt_read_reg[0]_rep_0 ),
.I1(\cnt_read_reg[1]_rep__0_0 ),
.O(\memory_reg[3][0]_srl4_i_7_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][4]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(\memory_reg[3][4]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][5]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(\memory_reg[3][5]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][6]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(\memory_reg[3][6]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][7]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(\memory_reg[3][7]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0
(s_bresp_acc,
mhandshake,
Q,
m_axi_bready,
\skid_buffer_reg[1] ,
in,
m_axi_bresp,
m_axi_bvalid,
mhandshake_r,
shandshake_r,
bresp_push,
aclk,
areset_d1,
D);
output s_bresp_acc;
output mhandshake;
output [1:0]Q;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input [1:0]in;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
input mhandshake_r;
input shandshake_r;
input bresp_push;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire bresp_push;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire s_bresp_acc;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(shandshake_r),
.I3(bresp_push),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(bresp_push),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(bresp_push),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
LUT5 #(
.INIT(32'h2020A220))
\s_bresp_acc[1]_i_2
(.I0(mhandshake),
.I1(in[1]),
.I2(m_axi_bresp[1]),
.I3(m_axi_bresp[0]),
.I4(in[0]),
.O(s_bresp_acc));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1
(\cnt_read_reg[3]_rep__2_0 ,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
s_ready_i_reg_0,
si_rs_rready,
\cnt_read_reg[4]_0 ,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[3]_rep__2_0 ;
output wr_en0;
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input s_ready_i_reg_0;
input si_rs_rready;
input \cnt_read_reg[4]_0 ;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(wr_en0),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(wr_en0),
.I2(s_ready_i_reg),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAA6AA9AA))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(wr_en0),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(wr_en0),
.I5(s_ready_i_reg),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAA55AAA6A6AAA6AA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read[4]_i_3_n_0 ),
.I3(s_ready_i_reg_0),
.I4(\cnt_read_reg[4]_rep__2_1 ),
.I5(\cnt_read_reg[3]_rep__2_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(\cnt_read_reg[4]_0 ),
.I3(wr_en0),
.O(\cnt_read[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_1 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hAA2A2AAA2A2A2AAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[3]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2
(m_valid_i_reg,
\state_reg[1]_rep ,
\cnt_read_reg[4]_rep__2 ,
\skid_buffer_reg[35] ,
s_ready_i_reg,
r_push_r,
si_rs_rready,
\cnt_read_reg[0]_rep__2 ,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[0]_rep__2_0 ,
in,
aclk,
areset_d1);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output \cnt_read_reg[4]_rep__2 ;
output [1:0]\skid_buffer_reg[35] ;
input s_ready_i_reg;
input r_push_r;
input si_rs_rready;
input \cnt_read_reg[0]_rep__2 ;
input wr_en0;
input \cnt_read_reg[4]_rep__2_0 ;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[0]_rep__2_0 ;
input [1:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read[4]_i_4__0_n_0 ;
wire \cnt_read[4]_i_5__0_n_0 ;
wire \cnt_read_reg[0]_rep__2 ;
wire \cnt_read_reg[0]_rep__2_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire [1:0]in;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [1:0]\skid_buffer_reg[35] ;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(cnt_read[0]),
.I1(s_ready_i_reg),
.I2(r_push_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h9AA6))
\cnt_read[1]_i_1__2
(.I0(cnt_read[1]),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(cnt_read[0]),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hAAA96AAA))
\cnt_read[2]_i_1__0
(.I0(cnt_read[2]),
.I1(cnt_read[1]),
.I2(cnt_read[0]),
.I3(r_push_r),
.I4(s_ready_i_reg),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1__0
(.I0(cnt_read[3]),
.I1(cnt_read[0]),
.I2(cnt_read[1]),
.I3(cnt_read[2]),
.I4(r_push_r),
.I5(s_ready_i_reg),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAA55AAA6A6AAA6AA))
\cnt_read[4]_i_1__0
(.I0(cnt_read[4]),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read[4]_i_4__0_n_0 ),
.I4(\cnt_read[4]_i_5__0_n_0 ),
.I5(cnt_read[3]),
.O(\cnt_read[4]_i_1__0_n_0 ));
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_2__0
(.I0(cnt_read[1]),
.I1(cnt_read[2]),
.O(\cnt_read[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_3__0
(.I0(cnt_read[0]),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(r_push_r),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.I2(wr_en0),
.O(\cnt_read_reg[4]_rep__2 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4__0
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.I2(r_push_r),
.O(\cnt_read[4]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5__0
(.I0(cnt_read[2]),
.I1(cnt_read[1]),
.I2(cnt_read[0]),
.O(\cnt_read[4]_i_5__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
LUT6 #(
.INIT(64'hFF80808080808080))
m_valid_i_i_2
(.I0(cnt_read[4]),
.I1(cnt_read[3]),
.I2(\cnt_read[4]_i_5__0_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2 ),
.I5(\cnt_read_reg[0]_rep__2_0 ),
.O(m_valid_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[35] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[35] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBEFEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__2 ),
.I1(cnt_read[2]),
.I2(cnt_read[1]),
.I3(cnt_read[0]),
.I4(cnt_read[3]),
.I5(cnt_read[4]),
.O(\state_reg[1]_rep ));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
(Q,
D,
\wrap_cnt_r_reg[0] ,
axaddr_offset,
\wrap_second_len_r_reg[3] ,
E,
\axlen_cnt_reg[0] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
next,
\axaddr_wrap_reg[0] ,
\m_payload_i_reg[0] ,
b_push,
m_axi_awvalid,
sel_first_reg,
sel_first_reg_0,
si_rs_awvalid,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[46] ,
\axaddr_offset_r_reg[3] ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[47] ,
\axlen_cnt_reg[0]_0 ,
\axlen_cnt_reg[4] ,
\m_payload_i_reg[48] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\m_payload_i_reg[46]_0 ,
\axlen_cnt_reg[2] ,
next_pending_r_reg_0,
\m_payload_i_reg[6] ,
\cnt_read_reg[0]_rep ,
\cnt_read_reg[1]_rep__0 ,
m_axi_awready,
s_axburst_eq1_reg_0,
sel_first_reg_2,
sel_first__0,
aclk);
output [1:0]Q;
output [2:0]D;
output \wrap_cnt_r_reg[0] ;
output [1:0]axaddr_offset;
output [3:0]\wrap_second_len_r_reg[3] ;
output [0:0]E;
output [0:0]\axlen_cnt_reg[0] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output next;
output [0:0]\axaddr_wrap_reg[0] ;
output [0:0]\m_payload_i_reg[0] ;
output b_push;
output m_axi_awvalid;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_awvalid;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]\m_payload_i_reg[46] ;
input [1:0]\axaddr_offset_r_reg[3] ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input [2:0]\m_payload_i_reg[47] ;
input [0:0]\axlen_cnt_reg[0]_0 ;
input \axlen_cnt_reg[4] ;
input \m_payload_i_reg[48] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input \m_payload_i_reg[46]_0 ;
input \axlen_cnt_reg[2] ;
input next_pending_r_reg_0;
input \m_payload_i_reg[6] ;
input \cnt_read_reg[0]_rep ;
input \cnt_read_reg[1]_rep__0 ;
input m_axi_awready;
input s_axburst_eq1_reg_0;
input sel_first_reg_2;
input sel_first__0;
input aclk;
wire [2:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [1:0]axaddr_offset;
wire [1:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_wrap_reg[0] ;
wire [0:0]\axlen_cnt_reg[0] ;
wire [0:0]\axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg[2] ;
wire \axlen_cnt_reg[4] ;
wire b_push;
wire \cnt_read_reg[0]_rep ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]\m_payload_i_reg[0] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [0:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[46]_0 ;
wire [2:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[48] ;
wire \m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [1:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire \state[0]_i_2_n_0 ;
wire \wrap_cnt_r[3]_i_2_n_0 ;
wire \wrap_cnt_r_reg[0] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
LUT6 #(
.INIT(64'hAAAAAAAAAAC0AAAA))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r_reg[3] [0]),
.I1(\m_payload_i_reg[3] ),
.I2(\m_payload_i_reg[47] [1]),
.I3(Q[0]),
.I4(si_rs_awvalid),
.I5(Q[1]),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r_reg[3] [1]),
.I1(\m_payload_i_reg[47] [2]),
.I2(Q[0]),
.I3(si_rs_awvalid),
.I4(Q[1]),
.I5(\m_payload_i_reg[6] ),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__0
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[47] [1]),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT4 #(
.INIT(16'hFF04))
\axlen_cnt[7]_i_1
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(next),
.O(\axaddr_wrap_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(Q[0]),
.I1(Q[1]),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(b_push),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0] ));
LUT6 #(
.INIT(64'hAA20AA200000AA20))
\memory_reg[3][0]_srl4_i_1
(.I0(Q[0]),
.I1(s_axburst_eq1_reg_0),
.I2(m_axi_awready),
.I3(Q[1]),
.I4(\cnt_read_reg[1]_rep__0 ),
.I5(\cnt_read_reg[0]_rep ),
.O(b_push));
LUT5 #(
.INIT(32'hB8BBB888))
next_pending_r_i_1
(.I0(\m_payload_i_reg[48] ),
.I1(E),
.I2(\axlen_cnt_reg[4] ),
.I3(next),
.I4(next_pending_r_reg),
.O(incr_next_pending));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46]_0 ),
.I1(E),
.I2(\axlen_cnt_reg[2] ),
.I3(next),
.I4(next_pending_r_reg_0),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hBBBBFFFF00B00000))
next_pending_r_i_4
(.I0(\cnt_read_reg[0]_rep ),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(m_axi_awready),
.I3(s_axburst_eq1_reg_0),
.I4(Q[0]),
.I5(Q[1]),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFF04FFFFFF04FF04))
sel_first_i_1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(areset_d1),
.I4(next),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1__1
(.I0(next),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1__2
(.I0(next),
.I1(sel_first__0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'hBBBA))
\state[0]_i_1
(.I0(\state[0]_i_2_n_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.O(next_state[0]));
LUT6 #(
.INIT(64'h00F000F055750000))
\state[0]_i_2
(.I0(m_axi_awready),
.I1(s_axburst_eq1_reg_0),
.I2(\cnt_read_reg[1]_rep__0 ),
.I3(\cnt_read_reg[0]_rep ),
.I4(Q[0]),
.I5(Q[1]),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h08000800FC000800))
\state[1]_i_1
(.I0(s_axburst_eq1_reg_0),
.I1(m_axi_awready),
.I2(Q[1]),
.I3(Q[0]),
.I4(\cnt_read_reg[1]_rep__0 ),
.I5(\cnt_read_reg[0]_rep ),
.O(next_state[1]));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(axaddr_offset[0]),
.O(D[0]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(E),
.I3(\wrap_cnt_r_reg[0] ),
.I4(axaddr_offset[0]),
.I5(\wrap_second_len_r_reg[3] [1]),
.O(D[1]));
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [3]),
.I1(\wrap_second_len_r_reg[3] [1]),
.I2(\wrap_cnt_r[3]_i_2_n_0 ),
.I3(\wrap_second_len_r_reg[3] [2]),
.O(D[2]));
LUT6 #(
.INIT(64'hD1D1D1D1D1D1DFD1))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(axaddr_offset[0]),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[46] ),
.I5(axaddr_offset[1]),
.O(\wrap_cnt_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(axaddr_offset[0]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'h0000000004000404))
\wrap_second_len_r[0]_i_2
(.I0(axaddr_offset[0]),
.I1(\m_payload_i_reg[35] ),
.I2(\m_payload_i_reg[46] ),
.I3(E),
.I4(\axaddr_offset_r_reg[3] [1]),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_cnt_r_reg[0] ));
LUT6 #(
.INIT(64'h0FE0FFFF0FE00000))
\wrap_second_len_r[1]_i_1
(.I0(axaddr_offset[1]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[35] ),
.I3(axaddr_offset[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hCC2CFFFFCC2C0000))
\wrap_second_len_r[2]_i_1
(.I0(axaddr_offset[1]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[35] ),
.I3(axaddr_offset[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hFFFFF4FF44444444))
\wrap_second_len_r[3]_i_1
(.I0(E),
.I1(\wrap_second_len_r_reg[3]_0 [3]),
.I2(axaddr_offset[0]),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[46] ),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_second_len_r_reg[3] [3]));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
Q,
next,
axaddr_incr_reg,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_1 ,
\m_payload_i_reg[35] ,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[0] ,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]Q;
input next;
input [7:0]axaddr_incr_reg;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input \axaddr_offset_r_reg[3]_1 ;
input \m_payload_i_reg[35] ;
input [3:0]\axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire [18:0]Q;
wire aclk;
wire [7:0]axaddr_incr_reg;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire [3:0]\axaddr_offset_r_reg[3]_2 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[11]_i_5_n_0 ;
wire \axaddr_wrap[11]_i_6_n_0 ;
wire \axaddr_wrap[11]_i_7_n_0 ;
wire \axaddr_wrap[11]_i_8_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_3_n_0 ;
wire \axaddr_wrap[7]_i_4_n_0 ;
wire \axaddr_wrap[7]_i_5_n_0 ;
wire \axaddr_wrap[7]_i_6_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1_n_0 ;
wire \axlen_cnt[1]_i_1_n_0 ;
wire \axlen_cnt[2]_i_1_n_0 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire [0:0]\state_reg[0] ;
wire [11:0]wrap_boundary_axaddr_r;
wire [1:1]wrap_cnt;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(Q[0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(Q[10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(Q[11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(wrap_cnt_r[2]),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(wrap_cnt_r[1]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5
(.I0(axaddr_wrap[11]),
.O(\axaddr_wrap[11]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6
(.I0(axaddr_wrap[10]),
.O(\axaddr_wrap[11]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7
(.I0(axaddr_wrap[9]),
.O(\axaddr_wrap[11]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8
(.I0(axaddr_wrap[8]),
.O(\axaddr_wrap[11]_i_8_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(Q[1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(Q[2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(Q[3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(Q[4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(Q[5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(Q[6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(Q[7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3
(.I0(axaddr_wrap[7]),
.O(\axaddr_wrap[7]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4
(.I0(axaddr_wrap[6]),
.O(\axaddr_wrap[7]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5
(.I0(axaddr_wrap[5]),
.O(\axaddr_wrap[7]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6
(.I0(axaddr_wrap[4]),
.O(\axaddr_wrap[7]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(Q[8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(Q[9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S({\axaddr_wrap[11]_i_5_n_0 ,\axaddr_wrap[11]_i_6_n_0 ,\axaddr_wrap[11]_i_7_n_0 ,\axaddr_wrap[11]_i_8_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S({\axaddr_wrap[7]_i_3_n_0 ,\axaddr_wrap[7]_i_4_n_0 ,\axaddr_wrap[7]_i_5_n_0 ,\axaddr_wrap[7]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1
(.I0(Q[15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(Q[16]),
.O(\axlen_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(Q[17]),
.O(\axlen_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(Q[18]),
.O(\axlen_cnt[3]_i_1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(Q[14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(Q[14]),
.I3(axaddr_incr_reg[6]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[10]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(Q[14]),
.I3(axaddr_incr_reg[7]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[11]),
.O(m_axi_awaddr[11]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[1]_INST_0
(.I0(Q[1]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[1]),
.I3(Q[14]),
.I4(sel_first_reg_2),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(Q[14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(Q[14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(Q[14]),
.I3(axaddr_incr_reg[0]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[4]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(Q[14]),
.I3(axaddr_incr_reg[1]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[5]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(Q[14]),
.I3(axaddr_incr_reg[2]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[6]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(Q[14]),
.I3(axaddr_incr_reg[3]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[7]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(Q[14]),
.I3(axaddr_incr_reg[4]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[8]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(Q[14]),
.I3(axaddr_incr_reg[5]),
.I4(\m_payload_i_reg[38] ),
.I5(Q[9]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'h01))
next_pending_r_i_3
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(Q[10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(Q[11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(Q[7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(Q[8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(Q[9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h313D020E))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_1 ),
.I3(\m_payload_i_reg[35] ),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(wrap_cnt));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(wrap_cnt),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wrap_cmd" *)
module zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
(sel_first_reg_0,
s_axburst_eq0_reg,
s_axburst_eq1_reg,
m_axi_araddr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_arvalid,
sel_first_i,
incr_next_pending,
\m_payload_i_reg[47]_0 ,
\state_reg[1]_rep ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_1 ,
\m_payload_i_reg[35] ,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output sel_first_reg_0;
output s_axburst_eq0_reg;
output s_axburst_eq1_reg;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input sel_first_i;
input incr_next_pending;
input \m_payload_i_reg[47]_0 ;
input \state_reg[1]_rep ;
input [6:0]\axaddr_incr_reg[11] ;
input \m_payload_i_reg[38] ;
input [3:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input \axaddr_offset_r_reg[3]_1 ;
input \m_payload_i_reg[35] ;
input [3:0]\axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [6:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire [3:0]\axaddr_offset_r_reg[3]_2 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[11]_i_5__0_n_0 ;
wire \axaddr_wrap[11]_i_6__0_n_0 ;
wire \axaddr_wrap[11]_i_7__0_n_0 ;
wire \axaddr_wrap[11]_i_8__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_3__0_n_0 ;
wire \axaddr_wrap[7]_i_4__0_n_0 ;
wire \axaddr_wrap[7]_i_5__0_n_0 ;
wire \axaddr_wrap[7]_i_6__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire [18:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__2_n_0;
wire next_pending_r_reg_n_0;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r[1]_i_1__0_n_0 ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\wrap_cnt_r_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\wrap_cnt_r_reg_n_0_[1] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[11] ),
.O(\axaddr_wrap[11]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[10] ),
.O(\axaddr_wrap[11]_i_6__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7__0
(.I0(\axaddr_wrap_reg_n_0_[9] ),
.O(\axaddr_wrap[11]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8__0
(.I0(\axaddr_wrap_reg_n_0_[8] ),
.O(\axaddr_wrap[11]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3__0
(.I0(\axaddr_wrap_reg_n_0_[7] ),
.O(\axaddr_wrap[7]_i_3__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4__0
(.I0(\axaddr_wrap_reg_n_0_[6] ),
.O(\axaddr_wrap[7]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[5] ),
.O(\axaddr_wrap[7]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[4] ),
.O(\axaddr_wrap[7]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap[11]_i_5__0_n_0 ,\axaddr_wrap[11]_i_6__0_n_0 ,\axaddr_wrap[11]_i_7__0_n_0 ,\axaddr_wrap[11]_i_8__0_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap[7]_i_3__0_n_0 ,\axaddr_wrap[7]_i_4__0_n_0 ,\axaddr_wrap[7]_i_5__0_n_0 ,\axaddr_wrap[7]_i_6__0_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__2
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [1]),
.O(m_axi_araddr[1]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[2] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [2]),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_araddr[4]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[5] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [5]),
.O(m_axi_araddr[5]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[6]_INST_0
(.I0(\m_payload_i_reg[47] [6]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[6] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFEAAFEAE))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[47]_0 ),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(next_pending_r_i_2__2_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__2
(.I0(\state_reg[1] [0]),
.I1(si_rs_arvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_2__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h313D020E))
\wrap_cnt_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_1 ),
.I3(\m_payload_i_reg[35] ),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_cnt_r[1]_i_1__0_n_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_cnt_r[1]_i_1__0_n_0 ),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
Q,
\s_arid_r_reg[0] ,
\axaddr_incr_reg[11] ,
CO,
O,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
D,
\axaddr_offset_r_reg[1] ,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[2] ,
\axaddr_offset_r_reg[1]_0 ,
next_pending_r_reg_1,
\wrap_second_len_r_reg[3]_0 ,
\axlen_cnt_reg[3]_0 ,
next_pending_r_reg_2,
\cnt_read_reg[0] ,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\axaddr_offset_r_reg[0]_0 ,
\m_axi_awaddr[10] ,
\m_axi_araddr[10] ,
s_axi_bid,
s_axi_bresp,
UNCONN_OUT,
aclk,
aresetn,
\cnt_read_reg[4] ,
s_axi_rready,
S,
\m_payload_i_reg[3] ,
\state_reg[1] ,
\axaddr_offset_r_reg[2]_0 ,
\state_reg[1]_0 ,
s_axi_awvalid,
b_push,
\state_reg[1]_rep ,
\axaddr_offset_r_reg[2]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
sel_first,
sel_first_0,
out,
\s_bresp_acc_reg[1] ,
si_rs_bvalid,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
r_push_r_reg,
\cnt_read_reg[4]_0 ,
axaddr_incr_reg,
\axaddr_incr_reg[3]_0 ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [47:0]Q;
output [47:0]\s_arid_r_reg[0] ;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11]_0 ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [1:0]D;
output \axaddr_offset_r_reg[1] ;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output [1:0]\axaddr_offset_r_reg[2] ;
output \axaddr_offset_r_reg[1]_0 ;
output next_pending_r_reg_1;
output \wrap_second_len_r_reg[3]_0 ;
output \axlen_cnt_reg[3]_0 ;
output next_pending_r_reg_2;
output \cnt_read_reg[0] ;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[3]_0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output \axaddr_offset_r_reg[0]_0 ;
output \m_axi_awaddr[10] ;
output \m_axi_araddr[10] ;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [35:0]UNCONN_OUT;
input aclk;
input aresetn;
input \cnt_read_reg[4] ;
input s_axi_rready;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input \state_reg[1] ;
input [1:0]\axaddr_offset_r_reg[2]_0 ;
input [1:0]\state_reg[1]_0 ;
input s_axi_awvalid;
input b_push;
input \state_reg[1]_rep ;
input [1:0]\axaddr_offset_r_reg[2]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input sel_first;
input sel_first_0;
input [0:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input si_rs_bvalid;
input s_axi_bready;
input s_axi_arvalid;
input [0:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [0:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [1:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4]_0 ;
input [3:0]axaddr_incr_reg;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [47:0]Q;
wire [3:0]S;
wire [35:0]UNCONN_OUT;
wire aclk;
wire ar_pipe_n_2;
wire aresetn;
wire aw_pipe_n_1;
wire aw_pipe_n_81;
wire [3:0]axaddr_incr_reg;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[0]_0 ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[1]_0 ;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire [1:0]\axaddr_offset_r_reg[2]_0 ;
wire [1:0]\axaddr_offset_r_reg[2]_1 ;
wire \axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[0] ;
wire \cnt_read_reg[4] ;
wire [33:0]\cnt_read_reg[4]_0 ;
wire \m_axi_araddr[10] ;
wire \m_axi_awaddr[10] ;
wire [3:0]\m_payload_i_reg[3] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire [0:0]out;
wire [1:0]r_push_r_reg;
wire [47:0]\s_arid_r_reg[0] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire sel_first;
wire sel_first_0;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_second_len_r_reg[3] ;
wire \wrap_second_len_r_reg[3]_0 ;
zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axic_register_slice ar_pipe
(.Q(\s_arid_r_reg[0] ),
.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[0]_0 (aw_pipe_n_81),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11]_0 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3]_0 ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.\axaddr_incr_reg[7]_0 (\axaddr_incr_reg[7]_0 ),
.\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0]_0 ),
.\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1]_0 ),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_1 ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_axi_araddr[10] (\m_axi_araddr[10] ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i_reg_0(ar_pipe_n_2),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_1),
.next_pending_r_reg_0(next_pending_r_reg_2),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.sel_first_0(sel_first_0),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ));
zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axic_register_slice_0 aw_pipe
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (aw_pipe_n_81),
.\aresetn_d_reg[1]_inv_0 (ar_pipe_n_2),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ),
.\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0] ),
.\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1] ),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2]_0 ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.\m_axi_awaddr[10] (\m_axi_awaddr[10] ),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.next_pending_r_reg_0(next_pending_r_reg_0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(aw_pipe_n_1),
.sel_first(sel_first),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_0 (\state_reg[1]_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ));
zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.m_valid_i_reg_0(si_rs_bready),
.out(out),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid));
zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.UNCONN_OUT(UNCONN_OUT),
.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.\cnt_read_reg[0] (\cnt_read_reg[0] ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_0 (\cnt_read_reg[4]_0 ),
.r_push_r_reg(r_push_r_reg),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11] ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
\axaddr_offset_r_reg[2] ,
\axaddr_offset_r_reg[1] ,
next_pending_r_reg,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\m_axi_araddr[10] ,
\aresetn_d_reg[0] ,
aclk,
\aresetn_d_reg[0]_0 ,
\m_payload_i_reg[3]_0 ,
\state_reg[1]_rep ,
\axaddr_offset_r_reg[2]_0 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
sel_first_0,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
\axaddr_incr_reg[3]_0 ,
m_valid_i_reg_1);
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [47:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11] ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [1:0]\axaddr_offset_r_reg[2] ;
output \axaddr_offset_r_reg[1] ;
output next_pending_r_reg;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output \m_axi_araddr[10] ;
input \aresetn_d_reg[0] ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [3:0]\m_payload_i_reg[3]_0 ;
input \state_reg[1]_rep ;
input [1:0]\axaddr_offset_r_reg[2]_0 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input sel_first_0;
input s_axi_arvalid;
input [0:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]m_valid_i_reg_1;
wire [47:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[0]_i_10__0_n_0 ;
wire \axaddr_incr[0]_i_12__0_n_0 ;
wire \axaddr_incr[0]_i_13__0_n_0 ;
wire \axaddr_incr[0]_i_14__0_n_0 ;
wire \axaddr_incr[0]_i_3__0_n_0 ;
wire \axaddr_incr[0]_i_4__0_n_0 ;
wire \axaddr_incr[0]_i_5__0_n_0 ;
wire \axaddr_incr[0]_i_6__0_n_0 ;
wire \axaddr_incr[0]_i_7__0_n_0 ;
wire \axaddr_incr[0]_i_8__0_n_0 ;
wire \axaddr_incr[0]_i_9__0_n_0 ;
wire \axaddr_incr[4]_i_10__0_n_0 ;
wire \axaddr_incr[4]_i_7__0_n_0 ;
wire \axaddr_incr[4]_i_8__0_n_0 ;
wire \axaddr_incr[4]_i_9__0_n_0 ;
wire \axaddr_incr[8]_i_10__0_n_0 ;
wire \axaddr_incr[8]_i_7__0_n_0 ;
wire \axaddr_incr[8]_i_8__0_n_0 ;
wire \axaddr_incr[8]_i_9__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_1 ;
wire \axaddr_incr_reg[0]_i_11__0_n_2 ;
wire \axaddr_incr_reg[0]_i_11__0_n_3 ;
wire \axaddr_incr_reg[0]_i_11__0_n_4 ;
wire \axaddr_incr_reg[0]_i_11__0_n_5 ;
wire \axaddr_incr_reg[0]_i_11__0_n_6 ;
wire \axaddr_incr_reg[0]_i_11__0_n_7 ;
wire \axaddr_incr_reg[0]_i_2__0_n_1 ;
wire \axaddr_incr_reg[0]_i_2__0_n_2 ;
wire \axaddr_incr_reg[0]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_1 ;
wire \axaddr_incr_reg[4]_i_6__0_n_2 ;
wire \axaddr_incr_reg[4]_i_6__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire \axaddr_incr_reg[8]_i_6__0_n_1 ;
wire \axaddr_incr_reg[8]_i_6__0_n_2 ;
wire \axaddr_incr_reg[8]_i_6__0_n_3 ;
wire \axaddr_offset_r[1]_i_3__0_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire [1:0]\axaddr_offset_r_reg[2]_0 ;
wire \axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[3] ;
wire \m_axi_araddr[10] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__0_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__0_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[48]_i_1__0_n_0 ;
wire \m_payload_i[49]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first_0;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [0]),
.I3(sel_first_0),
.I4(\axaddr_incr_reg[0]_i_11__0_n_7 ),
.O(\axaddr_incr[0]_i_10__0_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14__0_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_0),
.O(\axaddr_incr[0]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_0),
.O(\axaddr_incr[0]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first_0),
.O(\axaddr_incr[0]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_0),
.O(\axaddr_incr[0]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [3]),
.I3(sel_first_0),
.I4(\axaddr_incr_reg[0]_i_11__0_n_4 ),
.O(\axaddr_incr[0]_i_7__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [2]),
.I3(sel_first_0),
.I4(\axaddr_incr_reg[0]_i_11__0_n_5 ),
.O(\axaddr_incr[0]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(\axaddr_incr_reg[3]_0 [1]),
.I3(sel_first_0),
.I4(\axaddr_incr_reg[0]_i_11__0_n_6 ),
.O(\axaddr_incr[0]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10__0
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7__0
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8__0
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9__0
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10__0
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7__0
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8__0
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9__0
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9__0_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11__0_n_0 ,\axaddr_incr_reg[0]_i_11__0_n_1 ,\axaddr_incr_reg[0]_i_11__0_n_2 ,\axaddr_incr_reg[0]_i_11__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12__0_n_0 ,\axaddr_incr[0]_i_13__0_n_0 ,\axaddr_incr[0]_i_14__0_n_0 }),
.O({\axaddr_incr_reg[0]_i_11__0_n_4 ,\axaddr_incr_reg[0]_i_11__0_n_5 ,\axaddr_incr_reg[0]_i_11__0_n_6 ,\axaddr_incr_reg[0]_i_11__0_n_7 }),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[0]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[7]_0 ,\axaddr_incr_reg[0]_i_2__0_n_1 ,\axaddr_incr_reg[0]_i_2__0_n_2 ,\axaddr_incr_reg[0]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3__0_n_0 ,\axaddr_incr[0]_i_4__0_n_0 ,\axaddr_incr[0]_i_5__0_n_0 ,\axaddr_incr[0]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S({\axaddr_incr[0]_i_7__0_n_0 ,\axaddr_incr[0]_i_8__0_n_0 ,\axaddr_incr[0]_i_9__0_n_0 ,\axaddr_incr[0]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6__0
(.CI(\axaddr_incr_reg[0]_i_11__0_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6__0_n_0 ,\axaddr_incr_reg[4]_i_6__0_n_1 ,\axaddr_incr_reg[4]_i_6__0_n_2 ,\axaddr_incr_reg[4]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S({\axaddr_incr[4]_i_7__0_n_0 ,\axaddr_incr[4]_i_8__0_n_0 ,\axaddr_incr[4]_i_9__0_n_0 ,\axaddr_incr[4]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6__0
(.CI(\axaddr_incr_reg[4]_i_6__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6__0_n_1 ,\axaddr_incr_reg[8]_i_6__0_n_2 ,\axaddr_incr_reg[8]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] ),
.S({\axaddr_incr[8]_i_7__0_n_0 ,\axaddr_incr[8]_i_8__0_n_0 ,\axaddr_incr[8]_i_9__0_n_0 ,\axaddr_incr[8]_i_10__0_n_0 }));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r_reg[0] ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.O(\axaddr_offset_r_reg[2] [0]));
LUT6 #(
.INIT(64'h4F7F00004F7FFFFF))
\axaddr_offset_r[1]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[40]),
.I3(\axaddr_offset_r[1]_i_3__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[2]_0 [0]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_3__0
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hC808FFFFC8080000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[41]),
.I2(Q[35]),
.I3(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[2]_0 [1]),
.O(\axaddr_offset_r_reg[2] [1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2__0
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_araddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first_0),
.O(\m_axi_araddr[10] ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1__0
(.I0(s_axi_arlen[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(\m_payload_i[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1__0
(.I0(s_axi_arlen[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(\m_payload_i[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arlen[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arlen[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__0_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__0_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[48]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[49]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
LUT5 #(
.INIT(32'hBFFFBBBB))
m_valid_i_i_1__1
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_2__1
(.I0(Q[43]),
.I1(Q[45]),
.I2(Q[44]),
.I3(Q[46]),
.O(next_pending_r_reg_0));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_3__0
(.I0(\state_reg[1]_rep ),
.I1(Q[42]),
.I2(Q[40]),
.I3(Q[39]),
.I4(Q[41]),
.O(next_pending_r_reg));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'h8888028AAAAA028A))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[41]),
.I3(Q[40]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002A222A882AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[41]),
.I5(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r_reg[3] ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[11] ,
CO,
O,
D,
\axaddr_offset_r_reg[1] ,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\m_axi_awaddr[10] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
S,
\state_reg[1] ,
\axaddr_offset_r_reg[2] ,
\state_reg[1]_0 ,
s_axi_awvalid,
b_push,
sel_first,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
axaddr_incr_reg,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [47:0]Q;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [1:0]D;
output \axaddr_offset_r_reg[1] ;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output \m_axi_awaddr[10] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input [3:0]S;
input \state_reg[1] ;
input [1:0]\axaddr_offset_r_reg[2] ;
input [1:0]\state_reg[1]_0 ;
input s_axi_awvalid;
input b_push;
input sel_first;
input [0:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [3:0]axaddr_incr_reg;
input [0:0]E;
wire [3:0]C;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [47:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire \axaddr_incr[0]_i_10_n_0 ;
wire \axaddr_incr[0]_i_12_n_0 ;
wire \axaddr_incr[0]_i_13_n_0 ;
wire \axaddr_incr[0]_i_14_n_0 ;
wire \axaddr_incr[0]_i_3_n_0 ;
wire \axaddr_incr[0]_i_4_n_0 ;
wire \axaddr_incr[0]_i_5_n_0 ;
wire \axaddr_incr[0]_i_6_n_0 ;
wire \axaddr_incr[0]_i_7_n_0 ;
wire \axaddr_incr[0]_i_8_n_0 ;
wire \axaddr_incr[0]_i_9_n_0 ;
wire \axaddr_incr[4]_i_10_n_0 ;
wire \axaddr_incr[4]_i_7_n_0 ;
wire \axaddr_incr[4]_i_8_n_0 ;
wire \axaddr_incr[4]_i_9_n_0 ;
wire \axaddr_incr[8]_i_10_n_0 ;
wire \axaddr_incr[8]_i_7_n_0 ;
wire \axaddr_incr[8]_i_8_n_0 ;
wire \axaddr_incr[8]_i_9_n_0 ;
wire [3:0]axaddr_incr_reg;
wire \axaddr_incr_reg[0]_i_11_n_0 ;
wire \axaddr_incr_reg[0]_i_11_n_1 ;
wire \axaddr_incr_reg[0]_i_11_n_2 ;
wire \axaddr_incr_reg[0]_i_11_n_3 ;
wire \axaddr_incr_reg[0]_i_2_n_1 ;
wire \axaddr_incr_reg[0]_i_2_n_2 ;
wire \axaddr_incr_reg[0]_i_2_n_3 ;
wire [7:0]\axaddr_incr_reg[11] ;
wire \axaddr_incr_reg[4]_i_6_n_0 ;
wire \axaddr_incr_reg[4]_i_6_n_1 ;
wire \axaddr_incr_reg[4]_i_6_n_2 ;
wire \axaddr_incr_reg[4]_i_6_n_3 ;
wire \axaddr_incr_reg[8]_i_6_n_1 ;
wire \axaddr_incr_reg[8]_i_6_n_2 ;
wire \axaddr_incr_reg[8]_i_6_n_3 ;
wire \axaddr_offset_r[1]_i_3_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire \m_axi_awaddr[10] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first;
wire [53:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[0]),
.I3(sel_first),
.I4(C[0]),
.O(\axaddr_incr[0]_i_10_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_4_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[3]),
.I3(sel_first),
.I4(C[3]),
.O(\axaddr_incr[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[2]),
.I3(sel_first),
.I4(C[2]),
.O(\axaddr_incr[0]_i_8_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9
(.I0(Q[35]),
.I1(Q[36]),
.I2(axaddr_incr_reg[1]),
.I3(sel_first),
.I4(C[1]),
.O(\axaddr_incr[0]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11_n_0 ,\axaddr_incr_reg[0]_i_11_n_1 ,\axaddr_incr_reg[0]_i_11_n_2 ,\axaddr_incr_reg[0]_i_11_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12_n_0 ,\axaddr_incr[0]_i_13_n_0 ,\axaddr_incr[0]_i_14_n_0 }),
.O(C),
.S(S));
CARRY4 \axaddr_incr_reg[0]_i_2
(.CI(1'b0),
.CO({CO,\axaddr_incr_reg[0]_i_2_n_1 ,\axaddr_incr_reg[0]_i_2_n_2 ,\axaddr_incr_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3_n_0 ,\axaddr_incr[0]_i_4_n_0 ,\axaddr_incr[0]_i_5_n_0 ,\axaddr_incr[0]_i_6_n_0 }),
.O(O),
.S({\axaddr_incr[0]_i_7_n_0 ,\axaddr_incr[0]_i_8_n_0 ,\axaddr_incr[0]_i_9_n_0 ,\axaddr_incr[0]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6
(.CI(\axaddr_incr_reg[0]_i_11_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6_n_0 ,\axaddr_incr_reg[4]_i_6_n_1 ,\axaddr_incr_reg[4]_i_6_n_2 ,\axaddr_incr_reg[4]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [3:0]),
.S({\axaddr_incr[4]_i_7_n_0 ,\axaddr_incr[4]_i_8_n_0 ,\axaddr_incr[4]_i_9_n_0 ,\axaddr_incr[4]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6
(.CI(\axaddr_incr_reg[4]_i_6_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6_n_1 ,\axaddr_incr_reg[8]_i_6_n_2 ,\axaddr_incr_reg[8]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [7:4]),
.S({\axaddr_incr[8]_i_7_n_0 ,\axaddr_incr[8]_i_8_n_0 ,\axaddr_incr[8]_i_9_n_0 ,\axaddr_incr[8]_i_10_n_0 }));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r_reg[0] ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.O(D[0]));
LUT6 #(
.INIT(64'h4F7F00004F7FFFFF))
\axaddr_offset_r[1]_i_2
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(Q[35]),
.I2(Q[40]),
.I3(\axaddr_offset_r[1]_i_3_n_0 ),
.I4(\state_reg[1] ),
.I5(\axaddr_offset_r_reg[2] [0]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_3
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hC808FFFFC8080000))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(Q[41]),
.I2(Q[35]),
.I3(\axaddr_offset_r[2]_i_3_n_0 ),
.I4(\state_reg[1] ),
.I5(\axaddr_offset_r_reg[2] [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2
(.I0(Q[42]),
.I1(\state_reg[1]_0 [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_0 [1]),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first),
.O(\m_axi_awaddr[10] ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1
(.I0(s_axi_awlen[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(skid_buffer[48]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1
(.I0(s_axi_awlen[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(skid_buffer[49]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awlen[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awlen[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(E),
.D(skid_buffer[48]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(E),
.D(skid_buffer[49]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
next_pending_r_i_2
(.I0(next_pending_r_reg_0),
.I1(Q[43]),
.I2(Q[44]),
.I3(Q[46]),
.I4(Q[45]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2__0
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_awready),
.I2(b_push),
.I3(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'h8888028AAAAA028A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[41]),
.I3(Q[40]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A222A882AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[41]),
.I5(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_3_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r_reg[3] ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(s_axi_bvalid,
m_valid_i_reg_0,
s_axi_bid,
s_axi_bresp,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
out,
\s_bresp_acc_reg[1] ,
si_rs_bvalid,
s_axi_bready);
output s_axi_bvalid;
output m_valid_i_reg_0;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input [0:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input si_rs_bvalid;
input s_axi_bready;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1_n_0 ;
wire \m_payload_i[1]_i_1_n_0 ;
wire \m_payload_i[2]_i_1_n_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]out;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire [2:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hB8FFB8B8B800B8B8))
\m_payload_i[0]_i_1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[0] ),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.I5(s_axi_bresp[0]),
.O(\m_payload_i[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB8B8B800B8B8))
\m_payload_i[1]_i_1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[1] ),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.I5(s_axi_bresp[1]),
.O(\m_payload_i[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB8B8B800B8B8))
\m_payload_i[2]_i_1
(.I0(out),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[2] ),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.I5(s_axi_bid),
.O(\m_payload_i[2]_i_1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i[0]_i_1_n_0 ),
.Q(s_axi_bresp[0]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i[1]_i_1_n_0 ),
.Q(s_axi_bresp[1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i[2]_i_1_n_0 ),
.Q(s_axi_bid),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__0
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(m_valid_i_reg_0),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(m_valid_i_reg_0),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\skid_buffer[0]_i_1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\skid_buffer[1]_i_1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\skid_buffer[2]_i_1
(.I0(out),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zqynq_lab_1_design_auto_pc_2_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[0] ,
UNCONN_OUT,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[4] ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4]_0 );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[0] ;
output [35:0]UNCONN_OUT;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[4] ;
input s_axi_rready;
input [1:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4]_0 ;
wire [35:0]UNCONN_OUT;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[0] ;
wire \cnt_read_reg[4] ;
wire [33:0]\cnt_read_reg[4]_0 ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_2_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [1:0]r_push_r_reg;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[3]_i_2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4] ),
.O(\cnt_read_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\cnt_read_reg[4]_0 [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(\cnt_read_reg[4]_0 [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(\cnt_read_reg[4]_0 [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(\cnt_read_reg[4]_0 [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(\cnt_read_reg[4]_0 [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4]_0 [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4]_0 [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4]_0 [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4]_0 [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4]_0 [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4]_0 [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\cnt_read_reg[4]_0 [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4]_0 [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4]_0 [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4]_0 [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4]_0 [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4]_0 [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4]_0 [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4]_0 [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4]_0 [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4]_0 [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4]_0 [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(\cnt_read_reg[4]_0 [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4]_0 [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4]_0 [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4]_0 [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4]_0 [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[35]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_2
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(\cnt_read_reg[4]_0 [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(\cnt_read_reg[4]_0 [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(\cnt_read_reg[4]_0 [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(\cnt_read_reg[4]_0 [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(\cnt_read_reg[4]_0 [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(\cnt_read_reg[4]_0 [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(\cnt_read_reg[4]_0 [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(UNCONN_OUT[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(UNCONN_OUT[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(UNCONN_OUT[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(UNCONN_OUT[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(UNCONN_OUT[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(UNCONN_OUT[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(UNCONN_OUT[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(UNCONN_OUT[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(UNCONN_OUT[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(UNCONN_OUT[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(UNCONN_OUT[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(UNCONN_OUT[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(UNCONN_OUT[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(UNCONN_OUT[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(UNCONN_OUT[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(UNCONN_OUT[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(UNCONN_OUT[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(UNCONN_OUT[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(UNCONN_OUT[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(UNCONN_OUT[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(UNCONN_OUT[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(UNCONN_OUT[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(UNCONN_OUT[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(UNCONN_OUT[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(UNCONN_OUT[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(UNCONN_OUT[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(UNCONN_OUT[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(UNCONN_OUT[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_2_n_0 ),
.Q(UNCONN_OUT[35]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(UNCONN_OUT[3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(UNCONN_OUT[4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(UNCONN_OUT[5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(UNCONN_OUT[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(UNCONN_OUT[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(UNCONN_OUT[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(UNCONN_OUT[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\cnt_read_reg[4] ),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\cnt_read_reg[4] ),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4]_0 [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_auto_pc_2
(aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "1" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
zqynq_lab_1_design_auto_pc_2_axi_protocol_converter_v2_1_13_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(1'b0),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(1'b0),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(1'b0),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for fpga_core
*/
module test_fpga_core;
// Parameters
parameter TARGET = "SIM";
// Inputs
reg clk = 0;
reg clk90 = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg btnu = 0;
reg btnl = 0;
reg btnd = 0;
reg btnr = 0;
reg btnc = 0;
reg [7:0] sw = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
reg phy_rx_clk = 0;
reg [3:0] phy_rxd = 0;
reg phy_rx_ctl = 0;
reg phy_int_n = 1;
reg phy_pme_n = 1;
reg uart_rxd = 1;
// Outputs
wire [7:0] led;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
wire phy_tx_clk;
wire [3:0] phy_txd;
wire phy_tx_ctl;
wire phy_reset_n;
wire uart_txd;
initial begin
// myhdl integration
$from_myhdl(
clk,
clk90,
rst,
current_test,
btnu,
btnl,
btnd,
btnr,
btnc,
sw,
i2c_scl_i,
i2c_sda_i,
phy_rx_clk,
phy_rxd,
phy_rx_ctl,
phy_int_n,
phy_pme_n,
uart_rxd
);
$to_myhdl(
led,
i2c_scl_o,
i2c_scl_t,
i2c_sda_o,
i2c_sda_t,
phy_tx_clk,
phy_txd,
phy_tx_ctl,
phy_reset_n,
uart_txd
);
// dump file
$dumpfile("test_fpga_core.lxt");
$dumpvars(0, test_fpga_core);
end
fpga_core #(
.TARGET(TARGET)
)
UUT (
.clk(clk),
.clk90(clk90),
.rst(rst),
.btnu(btnu),
.btnl(btnl),
.btnd(btnd),
.btnr(btnr),
.btnc(btnc),
.sw(sw),
.led(led),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_ctl(phy_rx_ctl),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_ctl(phy_tx_ctl),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
.phy_pme_n(phy_pme_n),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_protocol_converter_v2_1_9_axi_protocol_converter,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "dma_loopback_auto_pc_0,axi_protocol_converter_v2_1_9_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "dma_loopback_auto_pc_0,axi_protocol_converter_v2_1_9_axi_protocol_converter,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUS\
ER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, CrYCb to RGB conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// R = (+408.583/256)*Cr + (+298.082/256)*Y + ( 000.000/256)*Cb + (-222.921);
// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
module cf_csc_CrYCb2RGB (
// Cr-Y-Cb inputs
clk,
CrYCb_vs,
CrYCb_hs,
CrYCb_de,
CrYCb_data,
// R-G-B outputs
RGB_vs,
RGB_hs,
RGB_de,
RGB_data);
// Cr-Y-Cb inputs
input clk;
input CrYCb_vs;
input CrYCb_hs;
input CrYCb_de;
input [23:0] CrYCb_data;
// R-G-B outputs
output RGB_vs;
output RGB_hs;
output RGB_de;
output [23:0] RGB_data;
reg RGB_vs = 'd0;
reg RGB_hs = 'd0;
reg RGB_de = 'd0;
reg [23:0] RGB_data = 'd0;
wire R_vs_s;
wire R_hs_s;
wire R_de_s;
wire [ 7:0] R_data_s;
wire G_vs_s;
wire G_hs_s;
wire G_de_s;
wire [ 7:0] G_data_s;
wire B_vs_s;
wire B_hs_s;
wire B_de_s;
wire [ 7:0] B_data_s;
// output registers (the control signals are gated together)
always @(posedge clk) begin
RGB_vs <= R_vs_s & G_vs_s & B_vs_s;
RGB_hs <= R_hs_s & G_hs_s & B_hs_s;
RGB_de <= R_de_s & G_de_s & B_de_s;
RGB_data <= {R_data_s, G_data_s, B_data_s};
end
// red
cf_csc_1 i_csc_R (
.clk (clk),
.vs (CrYCb_vs),
.hs (CrYCb_hs),
.de (CrYCb_de),
.data (CrYCb_data),
.C1 (17'h01989),
.C2 (17'h012a1),
.C3 (17'h00000),
.C4 (25'h10deebc),
.csc_vs (R_vs_s),
.csc_hs (R_hs_s),
.csc_de (R_de_s),
.csc_data_1 (R_data_s));
// green
cf_csc_1 i_csc_G (
.clk (clk),
.vs (CrYCb_vs),
.hs (CrYCb_hs),
.de (CrYCb_de),
.data (CrYCb_data),
.C1 (17'h10d01),
.C2 (17'h012a1),
.C3 (17'h10644),
.C4 (25'h0087937),
.csc_vs (G_vs_s),
.csc_hs (G_hs_s),
.csc_de (G_de_s),
.csc_data_1 (G_data_s));
// blue
cf_csc_1 i_csc_B (
.clk (clk),
.vs (CrYCb_vs),
.hs (CrYCb_hs),
.de (CrYCb_de),
.data (CrYCb_data),
.C1 (17'h00000),
.C2 (17'h012a1),
.C3 (17'h02046),
.C4 (25'h1114d60),
.csc_vs (B_vs_s),
.csc_hs (B_hs_s),
.csc_de (B_de_s),
.csc_data_1 (B_data_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: debounce_clk.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module debounce_clk (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 3125,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=debounce_clk",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.016000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.01600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "debounce_clk.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3125"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL debounce_clk.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL debounce_clk.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL debounce_clk.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL debounce_clk.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL debounce_clk.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL debounce_clk_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL debounce_clk_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
(** * Maps: Total and Partial Maps *)
(** _Maps_ (or _dictionaries_) are ubiquitous data structures both
generally and in the theory of programming languages in
particular; we're going to need them in many places in the coming
chapters. They also make a nice case study using ideas we've seen
in previous chapters, including building data structures out of
higher-order functions (from [Basics] and [Poly]) and the use of
reflection to streamline proofs (from [IndProp]).
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ################################################################# *)
(** * The Coq Standard Library *)
(** One small digression before we begin...
Unlike the chapters we have seen so far, this one does not
[Require Import] the chapter before it (and, transitively, all the
earlier chapters). Instead, in this chapter and from now, on
we're going to import the definitions and theorems we need
directly from Coq's standard library stuff. You should not notice
much difference, though, because we've been careful to name our
own definitions and theorems the same as their counterparts in the
standard library, wherever they overlap. *)
From Coq Require Import Arith.Arith.
From Coq Require Import Bool.Bool.
Require Export Coq.Strings.String.
From Coq Require Import Logic.FunctionalExtensionality.
From Coq Require Import Lists.List.
Import ListNotations.
(** Documentation for the standard library can be found at
https://coq.inria.fr/library/.
The [Search] command is a good way to look for theorems involving
objects of specific types. See [Lists] for a reminder of how
to use it. *)
(** If you want to find out how or where a notation is defined, the
[Locate] command is useful. For example, where is the natural
addition operation defined in the standard library? *)
Locate "+".
(** There are several uses for that notation, but only one for
naturals. *)
Print Init.Nat.add.
(* ################################################################# *)
(** * Identifiers *)
(** First, we need a type for the keys that we use to index into our
maps. In [Lists.v] we introduced a fresh type [id] for a similar
purpose; here and for the rest of _Software Foundations_ we will
use the [string] type from Coq's standard library. *)
(** To compare strings, we define the function [eqb_string], which
internally uses the function [string_dec] from Coq's string
library. *)
Definition eqb_string (x y : string) : bool :=
if string_dec x y then true else false.
(** (The function [string_dec] comes from Coq's string library.
If you check the result type of [string_dec], you'll see that it
does not actually return a [bool], but rather a type that looks
like [{x = y} + {x <> y}], called a [sumbool], which can be
thought of as an "evidence-carrying boolean." Formally, an
element of [{x = y} + {x <> y}] is either a proof that [x] and [y] are equal
or a proof that they are unequal, together with a tag indicating
which. But for present purposes you can think of it as just a
fancy [bool].) *)
(** Now we need a few basic properties of string equality... *)
Theorem eqb_string_refl : forall s : string, true = eqb_string s s.
Proof.
intros s. unfold eqb_string.
destruct (string_dec s s) as [Hs_eq | Hs_not_eq].
- reflexivity.
- destruct Hs_not_eq. reflexivity.
Qed.
(** Two strings are equal according to [eqb_string] iff they
are equal according to [=]. So [=] is reflected in [eqb_string],
in the sense of "reflection" as discussed in [IndProp]. *)
Theorem eqb_string_true_iff : forall x y : string,
eqb_string x y = true <-> x = y.
Proof.
intros x y.
unfold eqb_string.
destruct (string_dec x y) as [Hs_eq | Hs_not_eq].
- rewrite Hs_eq. split. reflexivity. reflexivity.
- split.
+ intros contra. discriminate contra.
+ intros H. exfalso. apply Hs_not_eq. apply H.
Qed.
(** Similarly: *)
Theorem eqb_string_false_iff : forall x y : string,
eqb_string x y = false <-> x <> y.
Proof.
intros x y. rewrite <- eqb_string_true_iff.
rewrite not_true_iff_false. reflexivity. Qed.
(** This corollary follows just by rewriting: *)
Theorem false_eqb_string : forall x y : string,
x <> y -> eqb_string x y = false.
Proof.
intros x y. rewrite eqb_string_false_iff.
intros H. apply H. Qed.
(* ################################################################# *)
(** * Total Maps *)
(** Our main job in this chapter will be to build a definition of
partial maps that is similar in behavior to the one we saw in the
[Lists] chapter, plus accompanying lemmas about its behavior.
This time around, though, we're going to use _functions_, rather
than lists of key-value pairs, to build maps. The advantage of
this representation is that it offers a more _extensional_ view of
maps, where two maps that respond to queries in the same way will
be represented as literally the same thing (the very same function),
rather than just "equivalent" data structures. This, in turn,
simplifies proofs that use maps. *)
(** We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A : Type) := string -> A.
(** Intuitively, a total map over an element type [A] is just a
function that can be used to look up [string]s, yielding [A]s. *)
(** The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any string. *)
Definition t_empty {A : Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A : Type} (m : total_map A)
(x : string) (v : A) :=
fun x' => if eqb_string x x' then v else m x'.
(** This definition is a nice example of higher-order programming:
[t_update] takes a _function_ [m] and yields a new function
[fun x' => ...] that behaves like the desired map. *)
(** For example, we can build a map taking [string]s to [bool]s, where
["foo"] and ["bar"] are mapped to [true] and every other key is
mapped to [false], like this: *)
Definition examplemap :=
t_update (t_update (t_empty false) "foo" true)
"bar" true.
(** Next, let's introduce some new notations to facilitate working
with maps. *)
(** First, we will use the following notation to create an empty
total map with a default value. *)
Notation "'_' '!->' v" := (t_empty v)
(at level 100, right associativity).
Example example_empty := (_ !-> false).
(** We then introduce a convenient notation for extending an existing
map with some bindings. *)
Notation "x '!->' v ';' m" := (t_update m x v)
(at level 100, v at next level, right associativity).
(** The [examplemap] above can now be defined as follows: *)
Definition examplemap' :=
( "bar" !-> true;
"foo" !-> true;
_ !-> false
).
(** This completes the definition of total maps. Note that we
don't need to define a [find] operation because it is just
function application! *)
Example update_example1 : examplemap' "baz" = false.
Proof. reflexivity. Qed.
Example update_example2 : examplemap' "foo" = true.
Proof. reflexivity. Qed.
Example update_example3 : examplemap' "quux" = false.
Proof. reflexivity. Qed.
Example update_example4 : examplemap' "bar" = true.
Proof. reflexivity. Qed.
(** To use maps in later chapters, we'll need several fundamental
facts about how they behave. *)
(** Even if you don't work the following exercises, make sure
you thoroughly understand the statements of the lemmas! *)
(** (Some of the proofs require the functional extensionality axiom,
which is discussed in the [Logic] chapter.) *)
(** **** Exercise: 1 star, standard, optional (t_apply_empty)
First, the empty map returns its default element for all keys: *)
Lemma t_apply_empty : forall (A : Type) (x : string) (v : A),
(_ !-> v) x = v.
Proof.
intros. unfold t_empty. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (t_update_eq)
Next, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall (A : Type) (m : total_map A) x v,
(x !-> v ; m) x = v.
Proof.
intros. unfold t_update.
rewrite <- eqb_string_refl.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (t_update_neq)
On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (A : Type) (m : total_map A) x1 x2 v,
x1 <> x2 ->
(x1 !-> v ; m) x2 = m x2.
Proof.
intros. unfold t_update.
rewrite <- eqb_string_false_iff in H. rewrite H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (t_update_shadow)
If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall (A : Type) (m : total_map A) x v1 v2,
(x !-> v2 ; x !-> v1 ; m) = (x !-> v2 ; m).
Proof.
intros.
unfold t_update.
apply functional_extensionality. intro.
destruct (string_dec x x0).
- (* x = x0 *)
apply eqb_string_true_iff in e.
rewrite e.
reflexivity.
- (* x <> x0 *)
apply eqb_string_false_iff in n.
rewrite n.
reflexivity.
Qed.
(** [] *)
(** For the final two lemmas about total maps, it's convenient to use
the reflection idioms introduced in chapter [IndProp]. We begin
by proving a fundamental _reflection lemma_ relating the equality
proposition on strings with the boolean function [eqb_string]. *)
(** **** Exercise: 2 stars, standard, optional (eqb_stringP)
Use the proof of [eqbP] in chapter [IndProp] as a template to
prove the following: *)
Lemma eqb_stringP : forall x y : string,
reflect (x = y) (eqb_string x y).
Proof.
intros.
apply iff_reflect. split.
- (* -> *)
intro. subst. symmetry. apply eqb_string_refl.
- (* <- *)
intros. apply eqb_string_true_iff in H.
apply H.
Qed.
(** [] *)
(** Now, given [string]s [x1] and [x2], we can use the tactic
[destruct (eqb_stringP x1 x2)] to simultaneously perform case
analysis on the result of [eqb_string x1 x2] and generate
hypotheses about the equality (in the sense of [=]) of [x1]
and [x2]. *)
(** **** Exercise: 2 stars, standard (t_update_same)
With the example in chapter [IndProp] as a template, use
[eqb_stringP] to prove the following theorem, which states that
if we update a map to assign key [x] the same value as it already
has in [m], then the result is equal to [m]: *)
Theorem t_update_same : forall (A : Type) (m : total_map A) x,
(x !-> m x ; m) = m.
Proof.
intros.
apply functional_extensionality. intro.
destruct (eqb_stringP x x0).
- (* x = x0 *)
subst. apply t_update_eq.
- (* x <> x0 *)
apply t_update_neq. apply n.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, especially useful (t_update_permute)
Use [eqb_stringP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (A : Type) (m : total_map A)
v1 v2 x1 x2,
x2 <> x1 ->
(x1 !-> v1 ; x2 !-> v2 ; m)
=
(x2 !-> v2 ; x1 !-> v1 ; m).
Proof.
intros.
apply functional_extensionality.
intro.
destruct (eqb_stringP x x1); destruct (eqb_stringP x x2).
- (* x = x1; x = x2 contradiction *)
subst. exfalso. apply H. reflexivity.
- (* x = x1; x <> x2 *)
subst.
rewrite t_update_eq.
rewrite t_update_neq; try rewrite t_update_eq.
+ reflexivity.
+ apply H.
- (* x <> x1; x = x2 *)
subst.
rewrite t_update_eq.
rewrite t_update_neq; try rewrite t_update_eq.
+ reflexivity.
+ intro. subst. apply H. reflexivity.
- (* x <> x1; x <> x2 *)
repeat rewrite t_update_neq.
reflexivity.
(* simple inequality cases that can all be found in assumption.
can be solved by tactics. I'll skip them with auto.
*)
auto. auto. auto. auto.
Qed.
(** [] *)
(* ################################################################# *)
(** * Partial maps *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A : Type) := total_map (option A).
Definition empty {A : Type} : partial_map A :=
t_empty None.
Definition update {A : Type} (m : partial_map A)
(x : string) (v : A) :=
(x !-> Some v ; m).
(** We introduce a similar notation for partial maps: *)
Notation "x '|->' v ';' m" := (update m x v)
(at level 100, v at next level, right associativity).
(** We can also hide the last case when it is empty. *)
Notation "x '|->' v" := (update empty x v)
(at level 100).
Example examplepmap :=
("Church" |-> true ; "Turing" |-> false).
(** We now straightforwardly lift all of the basic lemmas about total
maps to partial maps. *)
Lemma apply_empty : forall (A : Type) (x : string),
@empty A x = None.
Proof.
intros. unfold empty. rewrite t_apply_empty.
reflexivity.
Qed.
Lemma update_eq : forall (A : Type) (m : partial_map A) x v,
(x |-> v ; m) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (A : Type) (m : partial_map A) x1 x2 v,
x2 <> x1 ->
(x2 |-> v ; m) x1 = m x1.
Proof.
intros A m x1 x2 v H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall (A : Type) (m : partial_map A) x v1 v2,
(x |-> v2 ; x |-> v1 ; m) = (x |-> v2 ; m).
Proof.
intros A m x v1 v2. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall (A : Type) (m : partial_map A) x v,
m x = Some v ->
(x |-> v ; m) = m.
Proof.
intros A m x v H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (A : Type) (m : partial_map A)
x1 x2 v1 v2,
x2 <> x1 ->
(x1 |-> v1 ; x2 |-> v2 ; m) = (x2 |-> v2 ; x1 |-> v1 ; m).
Proof.
intros A m x1 x2 v1 v2. unfold update.
apply t_update_permute.
Qed.
(** Finally, for partial maps we introduce a notion of map inclusion,
stating that one map includes another: *)
Definition inclusion {A : Type} (m m' : partial_map A) :=
forall x v, m x = Some v -> m' x = Some v.
(** We show that map update preserves map inclusion, that is: *)
Lemma inclusion_update : forall (A : Type) (m m': partial_map A)
x vx,
inclusion m m' ->
inclusion (x |-> vx ; m) (x |-> vx ; m').
Proof.
unfold inclusion.
intros A m m' x vx H.
intros y vy.
destruct (eqb_stringP x y) as [Hxy | Hxy].
- rewrite Hxy.
rewrite update_eq. rewrite update_eq. intro H1. apply H1.
- rewrite update_neq. rewrite update_neq.
+ apply H.
+ apply Hxy.
+ apply Hxy.
Qed.
(** This property is useful for reasoning about the lambda-calculus,
where maps are used to keep track of which program variables are
defined at a given point. *)
(* 2020-09-09 20:51 *)
|
module tb;
import "DPI-C" context task c_main();
export "DPI-C" task read;
`include "parameter.v"
// System Signals
reg ACLK;
reg ARESETN;
// Slave Interface Write Address Ports
reg [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR;
reg [8-1 : 0] S_AXI_AWLEN;
reg [3-1 : 0] S_AXI_AWSIZE;
reg [2-1 : 0] S_AXI_AWBURST;
// input S_AXI_AWLOCK [2-1 : 0];
reg [1 : 0] S_AXI_AWLOCK;
reg [4-1 : 0] S_AXI_AWCACHE;
reg [3-1 : 0] S_AXI_AWPROT;
reg [4-1 : 0] S_AXI_AWQOS;
reg [C_S_AXI_AWUSER_WIDTH-1 :0] S_AXI_AWUSER;
reg S_AXI_AWVALID;
wire S_AXI_AWREADY;
// Slave Interface Write Data Ports
reg [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA;
reg [C_S_AXI_DATA_WIDTH/8-1 : 0]S_AXI_WSTRB;
reg S_AXI_WLAST;
reg [C_S_AXI_WUSER_WIDTH-1 : 0] S_AXI_WUSER;
reg S_AXI_WVALID;
wire S_AXI_WREADY;
// Slave Interface Write Response Ports
wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID;
wire [2-1 : 0] S_AXI_BRESP;
wire [C_S_AXI_BUSER_WIDTH-1 : 0] S_AXI_BUSER;
wire S_AXI_BVALID;
reg S_AXI_BREADY;
// Slave Interface Read Address Ports
reg [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR;
reg [8-1 : 0] S_AXI_ARLEN;
reg [3-1 : 0] S_AXI_ARSIZE;
reg [2-1 : 0] S_AXI_ARBURST;
reg [2-1 : 0] S_AXI_ARLOCK;
reg [4-1 : 0] S_AXI_ARCACHE;
reg [3-1 : 0] S_AXI_ARPROT;
reg [4-1 : 0] S_AXI_ARQOS;
reg [C_S_AXI_ARUSER_WIDTH-1 : 0]S_AXI_ARUSER;
reg S_AXI_ARVALID;
wire S_AXI_ARREADY;
// Slave Interface Read Data Ports
wire [C_S_AXI_ID_WIDTH-1: 0] S_AXI_RID;
wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA;
wire [2-1 : 0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_S_AXI_RUSER_WIDTH-1 : 0] S_AXI_RUSER;
wire S_AXI_RVALID;
reg S_AXI_RREADY;
axi_slave_bfm U1 (
.ACLK(ACLK),
.ARESETN(ARESETN),
.S_AXI_AWID(S_AXI_AWID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWLEN(S_AXI_AWLEN),
.S_AXI_AWSIZE(S_AXI_AWSIZE),
.S_AXI_AWBURST(S_AXI_AWBURST),
.S_AXI_AWLOCK(S_AXI_AWLOCK),
.S_AXI_AWCACHE(S_AXI_AWCACHE),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWQOS(S_AXI_AWQOS),
.S_AXI_AWUSER(S_AXI_AWUSER),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WLAST(S_AXI_WLAST),
.S_AXI_WUSER(S_AXI_WUSER),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BID(S_AXI_BID),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BUSER(S_AXI_BUSER),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARID(S_AXI_ARID),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARSIZE(S_AXI_ARSIZE),
.S_AXI_ARBURST(S_AXI_ARBURST),
.S_AXI_ARLOCK(S_AXI_ARLOCK),
.S_AXI_ARCACHE(S_AXI_ARCACHE),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARQOS(S_AXI_ARQOS),
.S_AXI_ARUSER(S_AXI_ARUSER),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RID(S_AXI_RID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RUSER(S_AXI_RUSER),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY)
);
`include "init.v"
task read(
input int t_s_axi_arid,
input int t_s_axi_araddr,
input int t_s_axi_arlen,
input int t_s_axi_arsize,
input int t_s_axi_arburst,
input int t_s_axi_arlock,
input int t_s_axi_arcache,
input int t_s_axi_arprot,
input int t_s_axi_arqos,
input int t_s_axi_aruser,
input int t_s_axi_arvalid);
begin
S_AXI_ARID = t_s_axi_arid;
S_AXI_ARADDR = t_s_axi_araddr;
S_AXI_ARLEN = t_s_axi_arlen;
S_AXI_ARSIZE = t_s_axi_arsize;
S_AXI_ARBURST = t_s_axi_arburst;
S_AXI_ARLOCK = t_s_axi_arlock;
S_AXI_ARCACHE = t_s_axi_arcache;
S_AXI_ARPROT = t_s_axi_arprot;
S_AXI_ARQOS = t_s_axi_arqos;
S_AXI_ARUSER = t_s_axi_aruser;
S_AXI_ARVALID = t_s_axi_arvalid;
S_AXI_RREADY = 0;
while(S_AXI_ARREADY === 1'b1) begin
@(posedge ACLK);
end
@ (posedge ACLK);
S_AXI_RREADY = 1;
S_AXI_ARID = 0;
S_AXI_ARADDR = 0;
S_AXI_ARLEN = 0;
S_AXI_ARSIZE = 0;
S_AXI_ARBURST = 0;
S_AXI_ARLOCK = 0;
S_AXI_ARCACHE = 0;
S_AXI_ARPROT = 0;
S_AXI_ARQOS = 0;
S_AXI_ARUSER = 0;
S_AXI_ARVALID = 0;
while(S_AXI_RLAST !== 1'b1) begin
@ (posedge ACLK);
end
@ (posedge ACLK);
end
endtask
`include "init.v"
initial begin
ACLK = 0;
forever begin
#1 ACLK = ~ACLK;
end
end
initial begin
@(posedge ACLK);
#10;
ARESETN = 0;
@(posedge ACLK);
ARESETN = 1;
repeat(10) @(posedge ACLK);
c_main;
$finish;
end
endmodule
// vim: set ts=4 autoindent shiftwidth=4 expandtab number:
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__einvp (
A ,
TE ,
Z ,
VPWR,
VGND
);
// Module ports
input A ;
input TE ;
output Z ;
input VPWR;
input VGND;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_BEHAVIORAL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pcie_bram_7x.v
// Version : 1.3
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ?
"WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
/******************************************************************************/
/* FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
/***** Comparator *****/
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** Sorter cell emitting multiple values at once *****/
/**************************************************************************************************/
module SCELL #(parameter SORTW = 32,
parameter M_LOG = 2)
(input wire CLK,
input wire RST,
input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [(SORTW<<M_LOG)-1:0] din1,
input wire [(SORTW<<M_LOG)-1:0] din2,
input wire full,
output wire [(SORTW<<M_LOG)-1:0] dout,
output wire enq);
function [(SORTW<<M_LOG)-1:0] mux;
input [(SORTW<<M_LOG)-1:0] a;
input [(SORTW<<M_LOG)-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire cmp = (din1[SORTW-1:0] < din2[SORTW-1:0]);
wire [(SORTW<<M_LOG)-1:0] cmp_dout = mux(din2, din1, cmp);
wire F_enq;
wire F_deq;
wire F_emp;
wire F_full;
wire [(SORTW<<M_LOG)-1:0] F_dot;
MRE2 #(1,(SORTW<<M_LOG)) F(.CLK(CLK), .RST(RST), .enq(F_enq), .deq(F_deq),
.din(cmp_dout), .dot(F_dot), .emp(F_emp), .full(F_full));
assign F_enq = &{~F_full,valid1,valid2}; // assign F_enq = (!F_full && valid1 && valid2);
assign F_deq = ~|{full,F_emp}; // assign F_deq = !full && !F_emp;
reg [(SORTW<<M_LOG)-1:0] fbdata;
reg [(SORTW<<M_LOG)-1:0] fbdata_a; // duplicated register
reg [(SORTW<<M_LOG)-1:0] fbdata_b; // duplicated register
reg fbinvoke;
assign enq = (F_deq && fbinvoke);
assign deq1 = (F_enq && cmp);
assign deq2 = (F_enq && !cmp);
localparam P_DATAWIDTH = 32;
wire [P_DATAWIDTH-1:0] a, b, c, d, e, f, g, h;
wire [P_DATAWIDTH-1:0] e_a, f_a, g_a, h_a; // for duplicated register
wire [P_DATAWIDTH-1:0] e_b, f_b, g_b, h_b; // for duplicated register
assign a = F_dot[ 31: 0];
assign b = F_dot[ 63:32];
assign c = F_dot[ 95:64];
assign d = F_dot[127:96];
assign e = fbdata[ 31: 0];
assign f = fbdata[ 63:32];
assign g = fbdata[ 95:64];
assign h = fbdata[127:96];
assign e_a = fbdata_a[ 31: 0];
assign f_a = fbdata_a[ 63:32];
assign g_a = fbdata_a[ 95:64];
assign h_a = fbdata_a[127:96];
assign e_b = fbdata_b[ 31: 0];
assign f_b = fbdata_b[ 63:32];
assign g_b = fbdata_b[ 95:64];
assign h_b = fbdata_b[127:96];
wire t0_c0 = (a < h);
wire t0_c1 = (b < g);
wire t0_c2 = (c < f);
wire t0_c3 = (d < e);
wire t0_x0 = t0_c0 ^ t0_c1;
wire t0_x1 = t0_c2 ^ t0_c3;
wire t0 = t0_x0 ^ t0_x1;
wire s2_c0 = (b < e);
wire s2_c1 = (a < f);
wire s3_c0 = (c < h);
wire s3_c1 = (d < g);
wire s4_c0 = (a < g);
wire s4_c1 = (b < f);
wire s4_c2 = (c < e);
wire s5_c0 = (d < f);
wire s5_c1 = (c < g);
wire s5_c2 = (b < h);
wire s0 = (a < e);
wire s1 = (d < h);
wire [1:0] s2 = {s0, (s2_c0 ^ s2_c1)};
wire [1:0] s3 = {s1, (s3_c0 ^ s3_c1)};
wire [2:0] s4 = {s2, (s4_c0 ^ s4_c1 ^ s4_c2)};
wire [2:0] s5 = {s3, (s5_c0 ^ s5_c1 ^ s5_c2)};
wire [3:0] s6 = {s4, t0};
wire [3:0] s7 = {s5, t0};
wire [P_DATAWIDTH-1:0] m0, m1, m2, m3, m4, m5, m6, m7;
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [32-1:0] mux4in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [1:0] sel;
begin
case (sel)
2'b00: mux4in32 = a;
2'b01: mux4in32 = b;
2'b10: mux4in32 = c;
2'b11: mux4in32 = d;
endcase
end
endfunction
function [32-1:0] mux6in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [2:0] sel;
begin
casex (sel)
3'b000: mux6in32 = a;
3'b001: mux6in32 = b;
3'b100: mux6in32 = c;
3'b101: mux6in32 = d;
3'bx10: mux6in32 = e;
3'bx11: mux6in32 = f;
endcase
end
endfunction
function [32-1:0] mux12in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [32-1:0] g;
input [32-1:0] h;
input [32-1:0] i;
input [32-1:0] j;
input [32-1:0] k;
input [32-1:0] l;
input [3:0] sel;
begin
casex (sel)
4'b0000: mux12in32 = a;
4'b0001: mux12in32 = b;
4'b0010: mux12in32 = c;
4'b0011: mux12in32 = d;
4'b1000: mux12in32 = e;
4'b1001: mux12in32 = f;
4'b1010: mux12in32 = g;
4'b1011: mux12in32 = h;
4'bx100: mux12in32 = i;
4'bx101: mux12in32 = j;
4'bx110: mux12in32 = k;
4'bx111: mux12in32 = l;
endcase
end
endfunction
assign m0 = mux32(e, a, s0);
assign m1 = mux32(d, h, s1);
assign m2 = mux4in32(f, a, b, e, s2);
assign m3 = mux4in32(c, h, g, d, s3);
assign m4 = mux6in32(g, a, e, c, b, f, s4);
assign m5 = mux6in32(b, h, d, f, g, c, s5);
// using duplicated registers
assign m6 = mux12in32(h_a, a, b, g_a, f_a, c, d, e_a, f_a, c, b, g_a, s6);
assign m7 = mux12in32(a, h_b, g_b, b, c, f_b, e_b, d, c, f_b, g_b, b, s7);
// output and feedback
//////////////////////////////////////////////////////////
assign dout = {m6,m4,m2,m0}; // output
always @(posedge CLK) begin // feedback
if (RST) begin
fbdata <= 0;
fbdata_a <= 0;
fbdata_b <= 0;
fbinvoke <= 0;
end else begin
if (F_deq) begin
fbdata <= {m1,m3,m5,m7};
fbdata_a <= {m1,m3,m5,m7};
fbdata_b <= {m1,m3,m5,m7};
fbinvoke <= 1;
end
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire rx_wait,
output wire [`MERGW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg [1:0] im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
(* mark_debug = "true" *) wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den;
wire im_deq = (req && !im_emp);
assign rx_wait = im_cnt[`IB_SIZE-1];
always @(posedge CLK) im_req <= (im_cnt==0) ? 3 : (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/ // todo
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`MERGW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [1:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`MERGW-1:0] mux;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[`MERGW-1:0], dot[`MERGW-1:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==3)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==2)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {`MERGW'b0, dot_t[`DRAMW-1:`MERGW]};
2'b11: dot_t <= {`MERGW'b0, dot[`DRAMW-1:`MERGW]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`MERGW-1:0] din, // data in
output wire [`MERGW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`MERGW-1:0] mux128;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux128 = a;
1'b1: mux128 = b;
endcase
end
endfunction
/*****************************************/
wire [`MERGW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`MERGW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux128(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 4;
if (ecnt==4 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`MERGW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`MERGW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07;
assign {d00, d01, d02, d03, d04, d05, d06, d07} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [`MERGW-1:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [`MERGW-1:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [`MERGW-1:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [`MERGW-1:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [`MERGW-1:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [`MERGW-1:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [`MERGW-1:0] F07_din, F07_dot; wire [1:0] F07_cnt;
wire F08_enq, F08_deq, F08_emp, F08_full; wire [`MERGW-1:0] F08_din, F08_dot; wire [1:0] F08_cnt;
wire F09_enq, F09_deq, F09_emp, F09_full; wire [`MERGW-1:0] F09_din, F09_dot; wire [1:0] F09_cnt;
wire F10_enq, F10_deq, F10_emp, F10_full; wire [`MERGW-1:0] F10_din, F10_dot; wire [1:0] F10_cnt;
wire F11_enq, F11_deq, F11_emp, F11_full; wire [`MERGW-1:0] F11_din, F11_dot; wire [1:0] F11_cnt;
wire F12_enq, F12_deq, F12_emp, F12_full; wire [`MERGW-1:0] F12_din, F12_dot; wire [1:0] F12_cnt;
wire F13_enq, F13_deq, F13_emp, F13_full; wire [`MERGW-1:0] F13_din, F13_dot; wire [1:0] F13_cnt;
wire F14_enq, F14_deq, F14_emp, F14_full; wire [`MERGW-1:0] F14_din, F14_dot; wire [1:0] F14_cnt;
wire F15_enq, F15_deq, F15_emp, F15_full; wire [`MERGW-1:0] F15_din, F15_dot; wire [1:0] F15_cnt;
INBUF IN08(CLK, RST, full[0], F08_full, F08_enq, d00, F08_din, enq[0], phase, irst);
INBUF IN09(CLK, RST, full[1], F09_full, F09_enq, d01, F09_din, enq[1], phase, irst);
INBUF IN10(CLK, RST, full[2], F10_full, F10_enq, d02, F10_din, enq[2], phase, irst);
INBUF IN11(CLK, RST, full[3], F11_full, F11_enq, d03, F11_din, enq[3], phase, irst);
INBUF IN12(CLK, RST, full[4], F12_full, F12_enq, d04, F12_din, enq[4], phase, irst);
INBUF IN13(CLK, RST, full[5], F13_full, F13_enq, d05, F13_din, enq[5], phase, irst);
INBUF IN14(CLK, RST, full[6], F14_full, F14_enq, d06, F14_din, enq[6], phase, irst);
INBUF IN15(CLK, RST, full[7], F15_full, F15_enq, d07, F15_din, enq[7], phase, irst);
MRE2 #(1, `MERGW) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1, `MERGW) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1, `MERGW) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1, `MERGW) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1, `MERGW) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1, `MERGW) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1, `MERGW) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
MRE2 #(1, `MERGW) F08(CLK, frst, F08_enq, F08_deq, F08_din, F08_dot, F08_emp, F08_full, F08_cnt);
MRE2 #(1, `MERGW) F09(CLK, frst, F09_enq, F09_deq, F09_din, F09_dot, F09_emp, F09_full, F09_cnt);
MRE2 #(1, `MERGW) F10(CLK, frst, F10_enq, F10_deq, F10_din, F10_dot, F10_emp, F10_full, F10_cnt);
MRE2 #(1, `MERGW) F11(CLK, frst, F11_enq, F11_deq, F11_din, F11_dot, F11_emp, F11_full, F11_cnt);
MRE2 #(1, `MERGW) F12(CLK, frst, F12_enq, F12_deq, F12_din, F12_dot, F12_emp, F12_full, F12_cnt);
MRE2 #(1, `MERGW) F13(CLK, frst, F13_enq, F13_deq, F13_din, F13_dot, F13_emp, F13_full, F13_cnt);
MRE2 #(1, `MERGW) F14(CLK, frst, F14_enq, F14_deq, F14_din, F14_dot, F14_emp, F14_full, F14_cnt);
MRE2 #(1, `MERGW) F15(CLK, frst, F15_enq, F15_deq, F15_din, F15_dot, F15_emp, F15_full, F15_cnt);
SCELL #(`SORTW, `M_LOG) S01(CLK, frst, !F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL #(`SORTW, `M_LOG) S02(CLK, frst, !F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL #(`SORTW, `M_LOG) S03(CLK, frst, !F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
SCELL #(`SORTW, `M_LOG) S04(CLK, frst, !F08_emp, !F09_emp, F08_deq, F09_deq, F08_dot, F09_dot, F04_full, F04_din, F04_enq);
SCELL #(`SORTW, `M_LOG) S05(CLK, frst, !F10_emp, !F11_emp, F10_deq, F11_deq, F10_dot, F11_dot, F05_full, F05_din, F05_enq);
SCELL #(`SORTW, `M_LOG) S06(CLK, frst, !F12_emp, !F13_emp, F12_deq, F13_deq, F12_dot, F13_dot, F06_full, F06_din, F06_enq);
SCELL #(`SORTW, `M_LOG) S07(CLK, frst, !F14_emp, !F15_emp, F14_deq, F15_deq, F14_dot, F15_dot, F07_full, F07_din, F07_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** compressor *****/
/**************************************************************************************************/
module COMPRESSOR(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] DIN,
input wire DIN_EN,
input wire P_Z,
input wire BUF_FULL,
output wire [`DRAMW-1:0] DOUT,
output wire DOUT_VALID);
function [`DRAMW-1:0] mux;
input [`DRAMW-1:0] a;
input [`DRAMW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
reg din_en;
always @(posedge CLK) din_en <= DIN_EN;
reg [31:0] block_cnt;
always @(posedge CLK) begin
if (RST) begin
block_cnt <= 0;
end else begin
case ({(block_cnt == ((`SORT_ELM>>4)>>(`P_LOG+`WAY_LOG))), din_en})
2'b10: block_cnt <= 0;
2'b01: block_cnt <= block_cnt + 1;
endcase
end
end
// Base+Delta Compressor /////////////////////////////////////////////////
wire [`SORTW-1:0] base = DIN[31 : 0];
wire [`SORTW-1:0] delta_a = DIN[63 : 32] - DIN[31 : 0];
wire [`SORTW-1:0] delta_b = DIN[95 : 64] - DIN[63 : 32];
wire [`SORTW-1:0] delta_c = DIN[127: 96] - DIN[95 : 64];
wire [`SORTW-1:0] delta_d = DIN[159:128] - DIN[127: 96];
wire [`SORTW-1:0] delta_e = DIN[191:160] - DIN[159:128];
wire [`SORTW-1:0] delta_f = DIN[223:192] - DIN[191:160];
wire [`SORTW-1:0] delta_g = DIN[255:224] - DIN[223:192];
wire [`SORTW-1:0] delta_h = DIN[287:256] - DIN[255:224];
wire [`SORTW-1:0] delta_i = DIN[319:288] - DIN[287:256];
wire [`SORTW-1:0] delta_j = DIN[351:320] - DIN[319:288];
wire [`SORTW-1:0] delta_k = DIN[383:352] - DIN[351:320];
wire [`SORTW-1:0] delta_l = DIN[415:384] - DIN[383:352];
wire [`SORTW-1:0] delta_m = DIN[447:416] - DIN[415:384];
wire [`SORTW-1:0] delta_n = DIN[479:448] - DIN[447:416];
wire [`SORTW-1:0] delta_o = DIN[511:480] - DIN[479:448];
reg c_cnt;
reg c_cflag;
always @(posedge CLK) c_cflag <= (delta_a<=13'h1fff) && (delta_b<=13'h1fff) && (delta_c<=13'h1fff) && (delta_d<=13'h1fff) &&
(delta_e<=13'h1fff) && (delta_f<=13'h1fff) && (delta_g<=13'h1fff) && (delta_h<=13'h1fff) &&
(delta_i<=13'h1fff) && (delta_j<=13'h1fff) && (delta_k<=13'h1fff) && (delta_l<=13'h1fff) &&
(delta_m<=13'h1fff) && (delta_n<=13'h1fff) && (delta_o<=13'h1fff) && !P_Z;
wire c_enable = (din_en && c_cflag);
wire c_cntrst;
reg [226:0] c_data;
always @(posedge CLK) c_data <= {delta_o[12:0], delta_n[12:0], delta_m[12:0], delta_l[12:0], delta_k[12:0], delta_j[12:0], delta_i[12:0],
delta_h[12:0], delta_g[12:0], delta_f[12:0], delta_e[12:0], delta_d[12:0], delta_c[12:0], delta_b[12:0],
delta_a[12:0], base};
always @(posedge CLK) begin
if (RST) begin
c_cnt <= 0;
end else begin
case ({c_enable, c_cntrst})
2'b10: c_cnt <= ~c_cnt;
2'b01: c_cnt <= 0;
endcase
end
end
// Data Packer ///////////////////////////////////////////////////////////
reg [226:0] data_buf;
always @(posedge CLK) if (c_enable) data_buf <= c_data;
reg p_valid; // packed data is valid
reg [`DRAMW-1:0] packed_data;
always @(posedge CLK) p_valid <= c_enable && c_cnt;
always @(posedge CLK) packed_data <= {{32'b0, 1'b1}, 25'b0, c_data, data_buf};
// temp FIFO /////////////////////////////////////////////////////////////
reg deq_req;
wire tmp_emp;
wire tmp_rst = RST || p_valid;
wire tmp_enq = DIN_EN;
wire tmp_deq = !BUF_FULL && deq_req && !tmp_emp;
wire [`DRAMW-1:0] tmp_dout;
wire tmp_full;
MRE2 #(1, `DRAMW) tmp(.CLK(CLK), .RST(tmp_rst), .enq(tmp_enq), .deq(tmp_deq),
.din(DIN), .dot(tmp_dout), .emp(tmp_emp), .full(tmp_full));
assign c_cntrst = tmp_deq;
always @(posedge CLK) begin
if (RST) begin
deq_req <= 0;
end else begin
if ((din_en && !c_cflag) ||
(din_en && (block_cnt==((`SORT_ELM>>4)>>(`P_LOG+`WAY_LOG))-1) && !c_cnt)) deq_req <= 1;
else if (tmp_emp) deq_req <= 0;
end
end
// Output ////////////////////////////////////////////////////////////////
assign DOUT = mux(tmp_dout, packed_data, p_valid);
assign DOUT_VALID = p_valid || tmp_deq;
endmodule
/***** decompressor *****/
/**************************************************************************************************/
module DECOMPRESSOR #(parameter SIZE = 7,
parameter BLOCKS = 8)
(input wire CLK,
input wire RST,
input wire [`SRTP_WAY+`DRAMW-1:0] DIN,
input wire DIN_EN,
output reg [`DRAMW-1:0] DOUT,
output reg [`SRTP_WAY:0] COUT,
output reg DATA_REQ);
function [227-1:0] mux227;
input [227-1:0] a;
input [227-1:0] b;
input sel;
begin
case (sel)
1'b0: mux227 = a;
1'b1: mux227 = b;
endcase
end
endfunction
function [512-1:0] mux512;
input [512-1:0] a;
input [512-1:0] b;
input sel;
begin
case (sel)
1'b0: mux512 = a;
1'b1: mux512 = b;
endcase
end
endfunction
// FIFO (Block RAM) //////////////////////////////////////////////////////
wire dmft_full;
wire dmf_emp;
wire dmf_enq = DIN_EN;
wire dmf_deq = !dmf_emp && !dmft_full;
wire [`SRTP_WAY+`DRAMW-1:0] dmf_din = DIN;
wire dmf_full;
wire [`SRTP_WAY+`DRAMW-1:0] dmf_dout;
wire [SIZE:0] dmf_cnt;
BFIFO #(SIZE, `SRTP_WAY+`DRAMW) dmf(CLK, RST, dmf_enq, dmf_deq, dmf_din, dmf_dout, dmf_emp, dmf_full, dmf_cnt);
reg dmf_dataen;
always @(posedge CLK) dmf_dataen <= dmf_deq;
always @(posedge CLK) DATA_REQ <= (dmf_cnt <= (1<<SIZE)-BLOCKS);
// FIFO (two entries) ///////////////////////////////////////////////////
wire dmft_enq = dmf_dataen;
wire [`SRTP_WAY+`DRAMW-1:0] dmft_din = dmf_dout;
wire [`SRTP_WAY+`DRAMW-1:0] dmft_dout;
wire dmft_emp;
wire c_valid = (dmft_dout[`DRAMW-1:`DRAMW-33]=={32'b0,1'b1}); // check whether the data is compressed or not
reg c_sel;
wire dmft_deq = c_sel || (!c_valid && !dmft_emp);
MRE2 #(1, `SRTP_WAY+`DRAMW) dmft(.CLK(CLK), .RST(RST), .enq(dmft_enq), .deq(dmft_deq),
.din(dmft_din), .dot(dmft_dout), .emp(dmft_emp), .full(dmft_full));
// Base+Delta Decompressor ///////////////////////////////////////////////
always @(posedge CLK) begin
if (RST) begin
c_sel <= 0;
end else begin
if (c_valid && !dmft_emp) c_sel <= ~c_sel;
end
end
wire [226:0] c_data = mux227(dmft_dout[226:0], dmft_dout[453:227], c_sel);
// Stage A
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] a00 = c_data[31 : 0];
wire [`SORTW-1:0] a01 = {19'b0, c_data[44 : 32]};
wire [`SORTW-1:0] a02 = {19'b0, c_data[57 : 45]};
wire [`SORTW-1:0] a03 = {19'b0, c_data[70 : 58]};
wire [`SORTW-1:0] a04 = {19'b0, c_data[83 : 71]};
wire [`SORTW-1:0] a05 = {19'b0, c_data[96 : 84]};
wire [`SORTW-1:0] a06 = {19'b0, c_data[109: 97]};
wire [`SORTW-1:0] a07 = {19'b0, c_data[122:110]};
wire [`SORTW-1:0] a08 = {19'b0, c_data[135:123]};
wire [`SORTW-1:0] a09 = {19'b0, c_data[148:136]};
wire [`SORTW-1:0] a10 = {19'b0, c_data[161:149]};
wire [`SORTW-1:0] a11 = {19'b0, c_data[174:162]};
wire [`SORTW-1:0] a12 = {19'b0, c_data[187:175]};
wire [`SORTW-1:0] a13 = {19'b0, c_data[200:188]};
wire [`SORTW-1:0] a14 = {19'b0, c_data[213:201]};
wire [`SORTW-1:0] a15 = {19'b0, c_data[226:214]};
reg [511:0] pdA; // pipeline regester A for data
always @(posedge CLK) pdA <= {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,(a03+a02+a01+a00),(a02+a01+a00),(a01+a00),a00};
reg [`DRAMW-1:0] dmft_dout_A;
always @(posedge CLK) dmft_dout_A <= dmft_dout[`DRAMW-1:0];
reg [(`SRTP_WAY+1+1)-1:0] pcA; // pipeline regester A for control
always @(posedge CLK) pcA <= {dmft_dout[`SRTP_WAY+`DRAMW-1:`DRAMW], (!dmft_emp), c_valid};
// Stage B
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
reg [511:0] pdB; // pipeline regester B for data
always @(posedge CLK) pdB <= {b15,b14,b13,b12,b11,b10,b09,b08,b07,(b06+b05+b04+b03),(b05+b04+b03),(b04+b03),b03,b02,b01,b00};
reg [`DRAMW-1:0] dmft_dout_B;
always @(posedge CLK) dmft_dout_B <= dmft_dout_A;
reg [(`SRTP_WAY+1+1)-1:0] pcB; // pipeline regester B for control
always @(posedge CLK) pcB <= pcA;
// Stage C
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
reg [511:0] pdC; // pipeline regester C for data
always @(posedge CLK) pdC <= {c15,c14,c13,c12,c11,c10,(c09+c08+c07+c06),(c08+c07+c06),(c07+c06),c06,c05,c04,c03,c02,c01,c00};
reg [`DRAMW-1:0] dmft_dout_C;
always @(posedge CLK) dmft_dout_C <= dmft_dout_B;
reg [(`SRTP_WAY+1+1)-1:0] pcC; // pipeline regester C for control
always @(posedge CLK) pcC <= pcB;
// Stage D
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
reg [511:0] pdD; // pipeline regester D for data
always @(posedge CLK) pdD <= {d15,d14,d13,(d12+d11+d10+d09),(d11+d10+d09),(d10+d09),d09,d08,d07,d06,d05,d04,d03,d02,d01,d00};
reg [`DRAMW-1:0] dmft_dout_D;
always @(posedge CLK) dmft_dout_D <= dmft_dout_C;
reg [(`SRTP_WAY+1+1)-1:0] pcD; // pipeline regester D for control
always @(posedge CLK) pcD <= pcC;
// Stage E
//////////////////////////////////////////////////////////////////////////////
wire [`SORTW-1:0] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
reg [511:0] pdE; // pipeline regester E for data
always @(posedge CLK) pdE <= {(e15+e14+e13+e12),(e14+e13+e12),(e13+e12),e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00};
reg [`DRAMW-1:0] dmft_dout_E;
always @(posedge CLK) dmft_dout_E <= dmft_dout_D;
reg [(`SRTP_WAY+1+1)-1:0] pcE; // pipeline regester E for control
always @(posedge CLK) pcE <= pcD;
// Decompression Result
//////////////////////////////////////////////////////////////////////////////
wire [`DRAMW-1:0] dc_data = pdE;
wire [`DRAMW-1:0] dmft_dot = dmft_dout_E;
wire c_vld = pcE[0];
wire dataen = pcE[1];
// Output ////////////////////////////////////////////////////////////////
always @(posedge CLK) if (dataen) DOUT <= mux512(dmft_dot, dc_data, c_vld);
always @(posedge CLK) COUT <= pcE[(`SRTP_WAY+1+1)-1:1];
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire d_busy,
input wire [31:0] w_block,
input wire p_z, // phase zero
input wire F01_deq,
input wire [`MERGW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire buf_t_ful,
output reg OB_req);
function [1-1:0] mux1;
input [1-1:0] a;
input [1-1:0] b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
reg [1:0] buf_t_cnt; // counter for temporary register
reg buf_t_en;
reg [`DRAMW-1:0] buf_t;
wire buf_t_emp;
wire [`DRAMW-1:0] c_din;
wire c_dinen;
wire [`DRAMW-1:0] c_dout;
wire c_douten;
wire [`DRAMW-1:0] OB_din = c_dout;
wire OB_enq = c_douten;
wire OB_full;
wire [`OB_SIZE:0] OB_cnt;
// 512-bit shift register ////////////////////////////////////////////////
always @(posedge CLK) begin
if (F01_deq) buf_t <= {F01_dot, buf_t[`DRAMW-1:`MERGW]};
end
always @(posedge CLK) begin
if (RST) begin
buf_t_cnt <= 0;
end else begin
if (F01_deq) buf_t_cnt <= buf_t_cnt + 1;
end
end
always @(posedge CLK) buf_t_en <= (F01_deq && buf_t_cnt == 3);
MRE2 #(1, `DRAMW) tmp(.CLK(CLK), .RST(RST), .enq(buf_t_en), .deq(c_dinen),
.din(buf_t), .dot(c_din), .emp(buf_t_emp), .full(buf_t_ful));
// Compressor ////////////////////////////////////////////////////////////
assign c_dinen = (~|{buf_t_emp,OB_full});
COMPRESSOR compressor(CLK, RST, c_din, c_dinen, p_z, OB_full, c_dout, c_douten);
// Output Buffer /////////////////////////////////////////////////////////
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
always @(posedge CLK) OB_req <= ((OB_cnt>=w_block) && !d_busy);
endmodule
/***** Sorting Network *****/
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester B for data
reg pcB; // pipeline regester B for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester C for data
reg pcC; // pipeline regester C for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester D for data
reg pcD; // pipeline regester D for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester E for data
reg pcE; // pipeline regester E for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester F for data
reg pcF; // pipeline regester F for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester G for data
reg pcG; // pipeline regester G for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester H for data
reg pcH; // pipeline regester H for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester I for data
reg pcI; // pipeline regester I for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** An SRL-based FIFO *****/
/******************************************************************************/
module SRL_FIFO #(parameter FIFO_SIZE = 4, // size in log scale, 4 for 16 entry
parameter FIFO_WIDTH = 64) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule
/***** request counter manager *****/
/**************************************************************************************************/
module REQCNTMG(input wire CLK,
input wire RST,
input wire DRIVE,
input wire [`SORT_WAY-1:0] req,
input wire [`SORT_WAY-1:0] im_enq,
input wire [`SORT_WAY-1:0] im_emp,
output reg reqcnt_a,
output reg reqcnt_b, // note!!! bit width
output reg reqcnt_c, // note!!! bit width
output reg reqcnt_d, // note!!! bit width
output reg reqcnt_e, // note!!! bit width
output reg reqcnt_f, // note!!! bit width
output reg reqcnt_g, // note!!! bit width
output reg reqcnt_h); // note!!! bit width
reg reqcnt_rsta;
reg reqcnt_rstb;
reg reqcnt_rstc;
reg reqcnt_rstd;
reg reqcnt_rste;
reg reqcnt_rstf;
reg reqcnt_rstg;
reg reqcnt_rsth;
// request counter manager
always @(posedge CLK) begin
if (RST) begin
{reqcnt_a, reqcnt_b, reqcnt_c, reqcnt_d, reqcnt_e, reqcnt_f, reqcnt_g, reqcnt_h} <= 0;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstc, reqcnt_rstd, reqcnt_rste, reqcnt_rstf, reqcnt_rstg, reqcnt_rsth} <= 0;
end else begin
if (DRIVE) begin
case (req)
8'h01: reqcnt_a <= 1;
8'h02: reqcnt_b <= 1;
8'h04: reqcnt_c <= 1;
8'h08: reqcnt_d <= 1;
8'h10: reqcnt_e <= 1;
8'h20: reqcnt_f <= 1;
8'h40: reqcnt_g <= 1;
8'h80: reqcnt_h <= 1;
endcase
end
if (|im_enq) begin
case (im_enq)
8'h01: begin
reqcnt_rsta <= 1;
{reqcnt_rstb, reqcnt_rstc, reqcnt_rstd, reqcnt_rste, reqcnt_rstf, reqcnt_rstg, reqcnt_rsth} <= 0;
end
8'h02: begin
reqcnt_rstb <= 1;
{reqcnt_rsta, reqcnt_rstc, reqcnt_rstd, reqcnt_rste, reqcnt_rstf, reqcnt_rstg, reqcnt_rsth} <= 0;
end
8'h04: begin
reqcnt_rstc <= 1;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstd, reqcnt_rste, reqcnt_rstf, reqcnt_rstg, reqcnt_rsth} <= 0;
end
8'h08: begin
reqcnt_rstd <= 1;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstc, reqcnt_rste, reqcnt_rstf, reqcnt_rstg, reqcnt_rsth} <= 0;
end
8'h10: begin
reqcnt_rste <= 1;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstc, reqcnt_rstd, reqcnt_rstf, reqcnt_rstg, reqcnt_rsth} <= 0;
end
8'h20: begin
reqcnt_rstf <= 1;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstc, reqcnt_rstd, reqcnt_rste, reqcnt_rstg, reqcnt_rsth} <= 0;
end
8'h40: begin
reqcnt_rstg <= 1;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstc, reqcnt_rstd, reqcnt_rste, reqcnt_rstf, reqcnt_rsth} <= 0;
end
8'h80: begin
reqcnt_rsth <= 1;
{reqcnt_rsta, reqcnt_rstb, reqcnt_rstc, reqcnt_rstd, reqcnt_rste, reqcnt_rstf, reqcnt_rstg} <= 0;
end
endcase
end else begin
if (reqcnt_rsta && im_emp[0]) reqcnt_rsta <= 0;
if (reqcnt_rstb && im_emp[1]) reqcnt_rstb <= 0;
if (reqcnt_rstc && im_emp[2]) reqcnt_rstc <= 0;
if (reqcnt_rstd && im_emp[3]) reqcnt_rstd <= 0;
if (reqcnt_rste && im_emp[4]) reqcnt_rste <= 0;
if (reqcnt_rstf && im_emp[5]) reqcnt_rstf <= 0;
if (reqcnt_rstg && im_emp[6]) reqcnt_rstg <= 0;
if (reqcnt_rsth && im_emp[7]) reqcnt_rsth <= 0;
end
if (reqcnt_rsta && ((|im_enq[`SORT_WAY-1:1]) || im_emp[0])) reqcnt_a <= 0;
if (reqcnt_rstb && ((|{im_enq[`SORT_WAY-1:2], im_enq[0]}) || im_emp[1])) reqcnt_b <= 0;
if (reqcnt_rstc && ((|{im_enq[`SORT_WAY-1:3], im_enq[1:0]}) || im_emp[2])) reqcnt_c <= 0;
if (reqcnt_rstd && ((|{im_enq[`SORT_WAY-1:4], im_enq[2:0]}) || im_emp[3])) reqcnt_d <= 0;
if (reqcnt_rste && ((|{im_enq[`SORT_WAY-1:5], im_enq[3:0]}) || im_emp[4])) reqcnt_e <= 0;
if (reqcnt_rstf && ((|{im_enq[`SORT_WAY-1:6], im_enq[4:0]}) || im_emp[5])) reqcnt_f <= 0;
if (reqcnt_rstg && ((|{im_enq[`SORT_WAY-1], im_enq[5:0]}) || im_emp[6])) reqcnt_g <= 0;
if (reqcnt_rsth && ((|im_enq[6:0]) || im_emp[7])) reqcnt_h <= 0;
end
end
endmodule
/***** write manager *****/
/**************************************************************************************************/
module WRITEMG #(parameter SORTELM_WAY = (`SORT_ELM>>`WAY_LOG))
(input wire CLK,
input wire RST,
input wire pchange,
input wire p_last,
input wire mgdrive,
input wire [31:0] elem,
input wire [31:0] elem_way,
input wire [31:0] elem_plast,
input wire [31:0] w_addr,
output reg [31:0] w_block,
output reg [31:0] r_endadr_a,
output reg [31:0] r_endadr_b,
output reg [31:0] r_endadr_c,
output reg [31:0] r_endadr_d,
output reg [31:0] r_endadr_e,
output reg [31:0] r_endadr_f,
output reg [31:0] r_endadr_g,
output reg [31:0] r_endadr_h);
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
reg [31:0] adr_a, adr_b, adr_c, adr_d, adr_e, adr_f, adr_g, adr_h;
reg reduce_flag;
always @(posedge CLK) begin
if (RST || pchange) begin
if (RST) {adr_a, adr_b, adr_c, adr_d, adr_e, adr_f, adr_g, adr_h} <= 0;
w_block <= `DRAM_WBLOCKS;
reduce_flag <= 0;
r_endadr_a <= adr_a;
r_endadr_b <= adr_b;
r_endadr_c <= adr_c;
r_endadr_d <= adr_d;
r_endadr_e <= adr_e;
r_endadr_f <= adr_f;
r_endadr_g <= adr_g;
r_endadr_h <= adr_h;
end else begin
case (p_last)
1'b0: begin
if (elem_way >= SORTELM_WAY-(`DRAM_WBLOCKS<<7)) reduce_flag <= 1;
if (mgdrive && reduce_flag) w_block <= mux32((w_block>>1), 1, (w_block==1));
case (elem)
SORTELM_WAY*1: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_a <= w_addr; end
end
SORTELM_WAY*2: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_b <= w_addr; end
end
SORTELM_WAY*3: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_c <= w_addr; end
end
SORTELM_WAY*4: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_d <= w_addr; end
end
SORTELM_WAY*5: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_e <= w_addr; end
end
SORTELM_WAY*6: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_f <= w_addr; end
end
SORTELM_WAY*7: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_g <= w_addr; end
end
SORTELM_WAY*8: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_h <= w_addr; end
end
endcase
end
1'b1: begin
if (elem_plast >= (SORTELM_WAY*2)-(`DRAM_WBLOCKS<<7)) reduce_flag <= 1;
if (mgdrive && reduce_flag) w_block <= mux32((w_block>>1), 1, (w_block==1));
case (elem)
SORTELM_WAY*2: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_b <= w_addr; end
end
SORTELM_WAY*4: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_d <= w_addr; end
end
SORTELM_WAY*6: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_f <= w_addr; end
end
SORTELM_WAY*8: begin
w_block <= `DRAM_WBLOCKS; reduce_flag <= 0; if (reduce_flag) begin adr_h <= w_addr; end
end
endcase
end
endcase
end
end
endmodule
/***** read manager *****/
/**************************************************************************************************/
module READMG(input wire CLK,
input wire RST,
input wire mgdrive,
input wire [`SORT_WAY-1:0] req,
input wire phase_lsb,
input wire [31:0] radr_a,
input wire [31:0] radr_b,
input wire [31:0] radr_c,
input wire [31:0] radr_d,
input wire [31:0] radr_e,
input wire [31:0] radr_f,
input wire [31:0] radr_g,
input wire [31:0] radr_h,
input wire [31:0] r_endadr_a,
input wire [31:0] r_endadr_b,
input wire [31:0] r_endadr_c,
input wire [31:0] r_endadr_d,
input wire [31:0] r_endadr_e,
input wire [31:0] r_endadr_f,
input wire [31:0] r_endadr_g,
input wire [31:0] r_endadr_h,
output reg [31:0] r_block_a,
output reg [31:0] r_block_b,
output reg [31:0] r_block_c,
output reg [31:0] r_block_d,
output reg [31:0] r_block_e,
output reg [31:0] r_block_f,
output reg [31:0] r_block_g,
output reg [31:0] r_block_h,
output reg readend_a,
output reg readend_b,
output reg readend_c,
output reg readend_d,
output reg readend_e,
output reg readend_f,
output reg readend_g,
output reg readend_h);
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
wire [31:0] way0_radr = mux32(radr_a, (radr_a + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way1_radr = mux32(radr_b, (radr_b + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way2_radr = mux32(radr_c, (radr_c + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way3_radr = mux32(radr_d, (radr_d + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way4_radr = mux32(radr_e, (radr_e + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way5_radr = mux32(radr_f, (radr_f + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way6_radr = mux32(radr_g, (radr_g + (`SORT_ELM>>1)), phase_lsb);
wire [31:0] way7_radr = mux32(radr_h, (radr_h + (`SORT_ELM>>1)), phase_lsb);
reg reduce_flag_a, reduce_flag_b, reduce_flag_c, reduce_flag_d, reduce_flag_e, reduce_flag_f, reduce_flag_g, reduce_flag_h;
always @(posedge CLK) begin
if (RST) begin
r_block_a <= `DRAM_RBLOCKS;
r_block_b <= `DRAM_RBLOCKS;
r_block_c <= `DRAM_RBLOCKS;
r_block_d <= `DRAM_RBLOCKS;
r_block_e <= `DRAM_RBLOCKS;
r_block_f <= `DRAM_RBLOCKS;
r_block_g <= `DRAM_RBLOCKS;
r_block_h <= `DRAM_RBLOCKS;
{readend_a,readend_b,readend_c,readend_d,readend_e,readend_f,readend_g,readend_h} <= 0;
{reduce_flag_a,reduce_flag_b,reduce_flag_c,reduce_flag_d,reduce_flag_e,reduce_flag_f,reduce_flag_g,reduce_flag_h} <= 0;
end else begin
readend_a <= (r_endadr_a == way0_radr);
readend_b <= (r_endadr_b == way1_radr);
readend_c <= (r_endadr_c == way2_radr);
readend_d <= (r_endadr_d == way3_radr);
readend_e <= (r_endadr_e == way4_radr);
readend_f <= (r_endadr_f == way5_radr);
readend_g <= (r_endadr_g == way6_radr);
readend_h <= (r_endadr_h == way7_radr);
if (r_endadr_a-((`D_RS)<<2) <= way0_radr) reduce_flag_a <= 1;
if (r_endadr_b-((`D_RS)<<2) <= way1_radr) reduce_flag_b <= 1;
if (r_endadr_c-((`D_RS)<<2) <= way2_radr) reduce_flag_c <= 1;
if (r_endadr_d-((`D_RS)<<2) <= way3_radr) reduce_flag_d <= 1;
if (r_endadr_e-((`D_RS)<<2) <= way4_radr) reduce_flag_e <= 1;
if (r_endadr_f-((`D_RS)<<2) <= way5_radr) reduce_flag_f <= 1;
if (r_endadr_g-((`D_RS)<<2) <= way6_radr) reduce_flag_g <= 1;
if (r_endadr_h-((`D_RS)<<2) <= way7_radr) reduce_flag_h <= 1;
if (mgdrive) begin
case (req)
8'h01: if (reduce_flag_a) r_block_a <= mux32((r_block_a>>1), 1, (r_block_a==1));
8'h02: if (reduce_flag_b) r_block_b <= mux32((r_block_b>>1), 1, (r_block_b==1));
8'h04: if (reduce_flag_c) r_block_c <= mux32((r_block_c>>1), 1, (r_block_c==1));
8'h08: if (reduce_flag_d) r_block_d <= mux32((r_block_d>>1), 1, (r_block_d==1));
8'h10: if (reduce_flag_e) r_block_e <= mux32((r_block_e>>1), 1, (r_block_e==1));
8'h20: if (reduce_flag_f) r_block_f <= mux32((r_block_f>>1), 1, (r_block_f==1));
8'h40: if (reduce_flag_g) r_block_g <= mux32((r_block_g>>1), 1, (r_block_g==1));
8'h80: if (reduce_flag_h) r_block_h <= mux32((r_block_h>>1), 1, (r_block_h==1));
endcase
end
end
end
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
input wire [`DRAMW-1:0] rx_data,
input wire rx_data_valid,
output wire rx_wait,
input wire chnl_tx_data_ren,
input wire chnl_tx_data_valid,
output wire [`MERGW-1:0] rslt,
output wire rslt_ready);
function [1-1:0] mux1;
input [1-1:0] a;
input [1-1:0] b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORT_WAY-1:0] mux_sortway;
input [`SORT_WAY-1:0] a;
input [`SORT_WAY-1:0] b;
input sel;
begin
case (sel)
1'b0: mux_sortway = a;
1'b1: mux_sortway = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [512-1:0] mux512;
input [512-1:0] a;
input [512-1:0] b;
input sel;
begin
case (sel)
1'b0: mux512 = a;
1'b1: mux512 = b;
endcase
end
endfunction
/**********************************************************************************************/
wire [`DRAMW-1:0] OB_dot_a, OB_dot_b;
wire OB_req_a, OB_req_b;
wire OB_full_a, OB_full_b;
reg OB_granted_a, OB_granted_b;
wire OB_deq_a = d_w && OB_granted_a;
wire OB_deq_b = d_w && OB_granted_b;
reg OB_doten_a, OB_doten_b;
assign d_din = mux512(OB_dot_b, OB_dot_a, OB_granted_a);
reg [`DRAMW-1:0] dout_ta;
reg [`DRAMW-1:0] dout_tb;
reg [`DRAMW-1:0] dout_tc;
reg [`DRAMW-1:0] dout_td;
reg [`DRAMW-1:0] dout_te;
reg [`DRAMW-1:0] dout_tf;
reg doen_ta;
reg doen_tb; //
reg doen_tc; //
reg doen_td; //
reg doen_te; //
reg doen_tf; //
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
reg [`SORT_WAY-1:0] req_a, req_b;
reg [`SORT_WAY-1:0] req_ta;
reg [`SORT_WAY-1:0] req_tb;
reg [`SORT_WAY-1:0] req_taa; //
reg [`SORT_WAY-1:0] req_tab; //
reg [`SORT_WAY-1:0] req_tba; //
reg [`SORT_WAY-1:0] req_tbb; //
reg [`SRTP_WAY-1:0] req_pzero;
wire [`SORT_WAY-1:0] im_req_a;
wire [`SORT_WAY-1:0] im_req_b;
wire [`SRTP_WAY-1:0] rxw;
reg [31:0] elem_a, elem_b; // sorted elements in a phase
reg [31:0] elem_way_a, elem_way_b; // sorted elements in a phase
reg [31:0] elem_plast_a, elem_plast_b; // sorted elements in a phase
reg elem_en_a, elem_en_b;
reg [`PHASE_W] phase_a, phase_b; //
reg pchange_a, pchange_b; // phase_change to reset some registers
reg iter_done_a, iter_done_b; //
reg [31:0] ecnt_a, ecnt_b; // sorted elements in an iteration
reg irst_a, irst_b; // INBUF reset
reg frst_a, frst_b; // sort-tree FIFO reset
reg plast_a, plast_b;
reg phase_zero;
reg last_phase;
reg RSTa, RSTb;
always @(posedge CLK) RSTa <= RST_IN;
always @(posedge CLK) RSTb <= RST_IN;
/**********************************************************************************************/
wire [`MERGW-1:0] d00_a, d01_a, d02_a, d03_a, d04_a, d05_a, d06_a, d07_a;
wire [1:0] ib00_req_a, ib01_req_a, ib02_req_a, ib03_req_a, ib04_req_a, ib05_req_a, ib06_req_a, ib07_req_a;
wire [`MERGW-1:0] d00_b, d01_b, d02_b, d03_b, d04_b, d05_b, d06_b, d07_b;
wire [1:0] ib00_req_b, ib01_req_b, ib02_req_b, ib03_req_b, ib04_req_b, ib05_req_b, ib06_req_b, ib07_req_b;
(* mark_debug = "true" *) wire rsltbuf_enq;
(* mark_debug = "true" *) wire rsltbuf_deq;
wire rsltbuf_emp;
wire rsltbuf_ful;
(* mark_debug = "true" *) wire [4:0] rsltbuf_cnt;
wire F01_emp_a, F01_emp_b;
wire F01_deq_a = mux1((~|{F01_emp_a,OB_full_a}), (~|{F01_emp_a,rsltbuf_ful}), last_phase);
wire F01_deq_b = (~|{F01_emp_b,OB_full_b});
wire [`MERGW-1:0] F01_dot_a, F01_dot_b;
wire [`MERGW*`SORT_WAY-1:0] s_din_a = {d00_a, d01_a, d02_a, d03_a, d04_a, d05_a, d06_a, d07_a};
wire [`MERGW*`SORT_WAY-1:0] s_din_b = {d00_b, d01_b, d02_b, d03_b, d04_b, d05_b, d06_b, d07_b};
wire [`SORT_WAY-1:0] enq_a, enq_b;
wire [`SORT_WAY-1:0] s_ful_a, s_ful_b;
wire [`SRTP_WAY+`DRAMW-1:0] dc_din = {req_tb,req_ta,d_dout};
wire dc_dinen = d_douten;
wire [`DRAMW-1:0] dc_dout; // for data
wire [`SRTP_WAY:0] dc_cout; // for control
wire dc_req;
DECOMPRESSOR #(`IB_SIZE, `DRAM_RBLOCKS)
decompressor(CLK, RSTa, dc_din, dc_dinen, dc_dout, dc_cout, dc_req);
wire [`DRAMW-1:0] stnet_dout;
wire stnet_douten;
SORTINGNETWORK sortingnetwork(CLK, RSTa, rx_data_valid, rx_data, stnet_dout, stnet_douten);
always @(posedge CLK) begin
if (RSTa) req_pzero <= 1;
else if (doen_tc) req_pzero <= {req_pzero[`SRTP_WAY-2:0],req_pzero[`SRTP_WAY-1]};
end
assign im_req_a = mux_sortway(req_tab, req_pzero[`SORT_WAY-1:0], phase_zero);
assign im_req_b = mux_sortway(req_tbb, req_pzero[`SRTP_WAY-1:`SORT_WAY], phase_zero);
wire im00_enq_a = doen_tc & im_req_a[0];
wire im01_enq_a = doen_tc & im_req_a[1];
wire im02_enq_a = doen_td & im_req_a[2];
wire im03_enq_a = doen_td & im_req_a[3];
wire im04_enq_a = doen_te & im_req_a[4];
wire im05_enq_a = doen_te & im_req_a[5];
wire im06_enq_a = doen_tf & im_req_a[6];
wire im07_enq_a = doen_tf & im_req_a[7];
wire im00_enq_b = doen_tc & im_req_b[0];
wire im01_enq_b = doen_tc & im_req_b[1];
wire im02_enq_b = doen_td & im_req_b[2];
wire im03_enq_b = doen_td & im_req_b[3];
wire im04_enq_b = doen_te & im_req_b[4];
wire im05_enq_b = doen_te & im_req_b[5];
wire im06_enq_b = doen_tf & im_req_b[6];
wire im07_enq_b = doen_tf & im_req_b[7];
INMOD2 im00_a(CLK, RSTa, dout_tc, im00_enq_a, s_ful_a[0], rxw[0], d00_a, enq_a[0], ib00_req_a);
INMOD2 im01_a(CLK, RSTa, dout_tc, im01_enq_a, s_ful_a[1], rxw[1], d01_a, enq_a[1], ib01_req_a);
INMOD2 im02_a(CLK, RSTa, dout_td, im02_enq_a, s_ful_a[2], rxw[2], d02_a, enq_a[2], ib02_req_a);
INMOD2 im03_a(CLK, RSTa, dout_td, im03_enq_a, s_ful_a[3], rxw[3], d03_a, enq_a[3], ib03_req_a);
INMOD2 im04_a(CLK, RSTa, dout_te, im04_enq_a, s_ful_a[4], rxw[4], d04_a, enq_a[4], ib04_req_a);
INMOD2 im05_a(CLK, RSTa, dout_te, im05_enq_a, s_ful_a[5], rxw[5], d05_a, enq_a[5], ib05_req_a);
INMOD2 im06_a(CLK, RSTa, dout_tf, im06_enq_a, s_ful_a[6], rxw[6], d06_a, enq_a[6], ib06_req_a);
INMOD2 im07_a(CLK, RSTa, dout_tf, im07_enq_a, s_ful_a[7], rxw[7], d07_a, enq_a[7], ib07_req_a);
INMOD2 im00_b(CLK, RSTb, dout_tc, im00_enq_b, s_ful_b[0], rxw[8], d00_b, enq_b[0], ib00_req_b);
INMOD2 im01_b(CLK, RSTb, dout_tc, im01_enq_b, s_ful_b[1], rxw[9], d01_b, enq_b[1], ib01_req_b);
INMOD2 im02_b(CLK, RSTb, dout_td, im02_enq_b, s_ful_b[2], rxw[10], d02_b, enq_b[2], ib02_req_b);
INMOD2 im03_b(CLK, RSTb, dout_td, im03_enq_b, s_ful_b[3], rxw[11], d03_b, enq_b[3], ib03_req_b);
INMOD2 im04_b(CLK, RSTb, dout_te, im04_enq_b, s_ful_b[4], rxw[12], d04_b, enq_b[4], ib04_req_b);
INMOD2 im05_b(CLK, RSTb, dout_te, im05_enq_b, s_ful_b[5], rxw[13], d05_b, enq_b[5], ib05_req_b);
INMOD2 im06_b(CLK, RSTb, dout_tf, im06_enq_b, s_ful_b[6], rxw[14], d06_b, enq_b[6], ib06_req_b);
INMOD2 im07_b(CLK, RSTb, dout_tf, im07_enq_b, s_ful_b[7], rxw[15], d07_b, enq_b[7], ib07_req_b);
assign rx_wait = |rxw;
STREE stree_a(CLK, RSTa, irst_a, frst_a, phase_a, s_din_a, enq_a, s_ful_a, F01_deq_a, F01_dot_a, F01_emp_a);
STREE stree_b(CLK, RSTb, irst_b, frst_b, phase_b, s_din_b, enq_b, s_ful_b, F01_deq_b, F01_dot_b, F01_emp_b);
// ----- for dram READ/WRITE controller -----
reg [31:0] w_addr; //
reg [31:0] w_addr_pzero; //
reg [31:0] w_addr_a, w_addr_b;
reg [3:0] state; // state
reg [31:0] radr_a, radr_b, radr_c, radr_d, radr_e, radr_f, radr_g, radr_h;
reg [31:0] radr_a_a, radr_b_a, radr_c_a, radr_d_a, radr_e_a, radr_f_a, radr_g_a, radr_h_a;
reg [31:0] radr_a_b, radr_b_b, radr_c_b, radr_d_b, radr_e_b, radr_f_b, radr_g_b, radr_h_b;
reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h;
reg [27:0] cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a, cnt_e_a, cnt_f_a, cnt_g_a, cnt_h_a;
reg [27:0] cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b, cnt_e_b, cnt_f_b, cnt_g_b, cnt_h_b;
reg c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h; // counter is full ?
reg c_a_a, c_b_a, c_c_a, c_d_a, c_e_a, c_f_a, c_g_a, c_h_a;
reg c_a_b, c_b_b, c_c_b, c_d_b, c_e_b, c_f_b, c_g_b, c_h_b;
// ----- request counter manager -----
// input
wire mgdrive = (state==3 && d_req!=0);
wire mgdrive_a = (state==6 && d_req!=0 && (|req_ta));
wire mgdrive_b = (state==6 && d_req!=0 && (|req_tb));
wire [`SORT_WAY-1:0] im_enq_a = {im07_enq_a,im06_enq_a,im05_enq_a,im04_enq_a,im03_enq_a,im02_enq_a,im01_enq_a,im00_enq_a};
wire [`SORT_WAY-1:0] im_enq_b = {im07_enq_b,im06_enq_b,im05_enq_b,im04_enq_b,im03_enq_b,im02_enq_b,im01_enq_b,im00_enq_b};
wire [`SORT_WAY-1:0] im_emp_a = {ib07_req_a[1],ib06_req_a[1],ib05_req_a[1],ib04_req_a[1],ib03_req_a[1],ib02_req_a[1],ib01_req_a[1],ib00_req_a[1]};
wire [`SORT_WAY-1:0] im_emp_b = {ib07_req_b[1],ib06_req_b[1],ib05_req_b[1],ib04_req_b[1],ib03_req_b[1],ib02_req_b[1],ib01_req_b[1],ib00_req_b[1]};
// output
wire reqcnt_a, reqcnt_b, reqcnt_c, reqcnt_d, reqcnt_e, reqcnt_f, reqcnt_g, reqcnt_h;
wire reqcnt_a_a, reqcnt_b_a, reqcnt_c_a, reqcnt_d_a, reqcnt_e_a, reqcnt_f_a, reqcnt_g_a, reqcnt_h_a;
wire reqcnt_a_b, reqcnt_b_b, reqcnt_c_b, reqcnt_d_b, reqcnt_e_b, reqcnt_f_b, reqcnt_g_b, reqcnt_h_b;
REQCNTMG reqcntmg(CLK, RSTa, mgdrive, req_ta, im_enq_a, im_emp_a, reqcnt_a, reqcnt_b, reqcnt_c, reqcnt_d, reqcnt_e, reqcnt_f, reqcnt_g, reqcnt_h);
REQCNTMG reqcntmg_a(CLK, RSTa, mgdrive_a, req_ta, im_enq_a, im_emp_a, reqcnt_a_a, reqcnt_b_a, reqcnt_c_a, reqcnt_d_a, reqcnt_e_a, reqcnt_f_a, reqcnt_g_a, reqcnt_h_a);
REQCNTMG reqcntmg_b(CLK, RSTb, mgdrive_b, req_tb, im_enq_b, im_emp_b, reqcnt_a_b, reqcnt_b_b, reqcnt_c_b, reqcnt_d_b, reqcnt_e_b, reqcnt_f_b, reqcnt_g_b, reqcnt_h_b);
// ----- write manager -----
// output
wire [31:0] w_block_a;
wire [31:0] w_block_b;
wire [31:0] r_endadr_a_a, r_endadr_b_a, r_endadr_c_a, r_endadr_d_a, r_endadr_e_a, r_endadr_f_a, r_endadr_g_a, r_endadr_h_a;
wire [31:0] r_endadr_a_b, r_endadr_b_b, r_endadr_c_b, r_endadr_d_b, r_endadr_e_b, r_endadr_f_b, r_endadr_g_b, r_endadr_h_b;
WRITEMG #((`SORT_ELM>>(`P_LOG+`WAY_LOG)))
writemg_a(CLK, RSTa, pchange_a, plast_a, (state==7 && d_req!=0), elem_a, elem_way_a, elem_plast_a, w_addr_a,
w_block_a, r_endadr_a_a, r_endadr_b_a, r_endadr_c_a, r_endadr_d_a, r_endadr_e_a, r_endadr_f_a, r_endadr_g_a, r_endadr_h_a);
WRITEMG #((`SORT_ELM>>(`P_LOG+`WAY_LOG)))
writemg_b(CLK, RSTb, pchange_b, plast_b, (state==8 && d_req!=0), elem_b, elem_way_b, elem_plast_b, w_addr_b,
w_block_b, r_endadr_a_b, r_endadr_b_b, r_endadr_c_b, r_endadr_d_b, r_endadr_e_b, r_endadr_f_b, r_endadr_g_b, r_endadr_h_b);
// ----- read manager -----
// output
wire [31:0] r_block_a, r_block_b, r_block_c, r_block_d, r_block_e, r_block_f, r_block_g, r_block_h;
wire [31:0] r_block_a_a, r_block_b_a, r_block_c_a, r_block_d_a, r_block_e_a, r_block_f_a, r_block_g_a, r_block_h_a;
wire [31:0] r_block_a_b, r_block_b_b, r_block_c_b, r_block_d_b, r_block_e_b, r_block_f_b, r_block_g_b, r_block_h_b;
wire readend_a, readend_b, readend_c, readend_d, readend_e, readend_f, readend_g, readend_h;
wire readend_a_a, readend_b_a, readend_c_a, readend_d_a, readend_e_a, readend_f_a, readend_g_a, readend_h_a;
wire readend_a_b, readend_b_b, readend_c_b, readend_d_b, readend_e_b, readend_f_b, readend_g_b, readend_h_b;
READMG readmg(CLK, !last_phase, (state==3 && d_req!=0), req_ta, phase_a[0],
radr_a, radr_b, radr_c, radr_d, radr_e, radr_f, radr_g, radr_h,
r_endadr_b_a, r_endadr_d_a, r_endadr_f_a, r_endadr_h_a, r_endadr_b_b, r_endadr_d_b, r_endadr_f_b, r_endadr_h_b,
r_block_a, r_block_b, r_block_c, r_block_d, r_block_e, r_block_f, r_block_g, r_block_h,
readend_a, readend_b, readend_c, readend_d, readend_e, readend_f, readend_g, readend_h);
READMG readmg_a(CLK, (RSTa || pchange_a), (state==6 && d_req!=0 && (|req_ta)), req_ta, phase_a[0],
radr_a_a, radr_b_a, radr_c_a, radr_d_a, radr_e_a, radr_f_a, radr_g_a, radr_h_a,
r_endadr_a_a, r_endadr_b_a, r_endadr_c_a, r_endadr_d_a, r_endadr_e_a, r_endadr_f_a, r_endadr_g_a, r_endadr_h_a,
r_block_a_a, r_block_b_a, r_block_c_a, r_block_d_a, r_block_e_a, r_block_f_a, r_block_g_a, r_block_h_a,
readend_a_a, readend_b_a, readend_c_a, readend_d_a, readend_e_a, readend_f_a, readend_g_a, readend_h_a);
READMG readmg_b(CLK, (RSTb || pchange_b), (state==6 && d_req!=0 && (|req_tb)), req_tb, phase_b[0],
radr_a_b, radr_b_b, radr_c_b, radr_d_b, radr_e_b, radr_f_b, radr_g_b, radr_h_b,
r_endadr_a_b, r_endadr_b_b, r_endadr_c_b, r_endadr_d_b, r_endadr_e_b, r_endadr_f_b, r_endadr_g_b, r_endadr_h_b,
r_block_a_b, r_block_b_b, r_block_c_b, r_block_d_b, r_block_e_b, r_block_f_b, r_block_g_b, r_block_h_b,
readend_a_b, readend_b_b, readend_c_b, readend_d_b, readend_e_b, readend_f_b, readend_g_b, readend_h_b);
// ----- output buffer -----
reg OB_stopreq_a, OB_stopreq_b;
always @(posedge CLK) OB_stopreq_a <= (d_busy || OB_doten_a || elem_en_a || (elem_way_a==(`SORT_ELM>>(`P_LOG+`WAY_LOG))));
always @(posedge CLK) OB_stopreq_b <= (d_busy || OB_doten_b || elem_en_b || (elem_way_b==(`SORT_ELM>>(`P_LOG+`WAY_LOG))));
always @(posedge CLK) OB_doten_a <= OB_deq_a;
always @(posedge CLK) OB_doten_b <= OB_deq_b;
OTMOD ob_a(CLK, RSTa, OB_stopreq_a, w_block_a, phase_zero, (!last_phase && F01_deq_a), F01_dot_a, OB_deq_a, OB_dot_a, OB_full_a, OB_req_a);
OTMOD ob_b(CLK, RSTb, OB_stopreq_b, w_block_b, phase_zero, F01_deq_b, F01_dot_b, OB_deq_b, OB_dot_b, OB_full_b, OB_req_b);
assign rsltbuf_enq = last_phase && F01_deq_a;
assign rsltbuf_deq = chnl_tx_data_ren && chnl_tx_data_valid;
SRL_FIFO #(4, `MERGW) rsltbuf(CLK, RSTa, rsltbuf_enq, rsltbuf_deq, F01_dot_a,
rslt, rsltbuf_emp, rsltbuf_ful, rsltbuf_cnt);
assign rslt_ready = !rsltbuf_emp;
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
wire reqhalt_a_a = mux1((readend_a_a || (phase_a==`LAST_PHASE)), c_a_a, (phase_a==1));
wire reqhalt_b_a = mux1((readend_b_a || (phase_a==`LAST_PHASE)), c_b_a, (phase_a==1));
wire reqhalt_c_a = mux1((readend_c_a || (phase_a==`LAST_PHASE)), c_c_a, (phase_a==1));
wire reqhalt_d_a = mux1((readend_d_a || (phase_a==`LAST_PHASE)), c_d_a, (phase_a==1));
wire reqhalt_e_a = mux1((readend_e_a || (phase_a==`LAST_PHASE)), c_e_a, (phase_a==1));
wire reqhalt_f_a = mux1((readend_f_a || (phase_a==`LAST_PHASE)), c_f_a, (phase_a==1));
wire reqhalt_g_a = mux1((readend_g_a || (phase_a==`LAST_PHASE)), c_g_a, (phase_a==1));
wire reqhalt_h_a = mux1((readend_h_a || (phase_a==`LAST_PHASE)), c_h_a, (phase_a==1));
wire reqhalt_a_b = mux1((readend_a_b || (phase_b==`LAST_PHASE)), c_a_b, (phase_b==1));
wire reqhalt_b_b = mux1((readend_b_b || (phase_b==`LAST_PHASE)), c_b_b, (phase_b==1));
wire reqhalt_c_b = mux1((readend_c_b || (phase_b==`LAST_PHASE)), c_c_b, (phase_b==1));
wire reqhalt_d_b = mux1((readend_d_b || (phase_b==`LAST_PHASE)), c_d_b, (phase_b==1));
wire reqhalt_e_b = mux1((readend_e_b || (phase_b==`LAST_PHASE)), c_e_b, (phase_b==1));
wire reqhalt_f_b = mux1((readend_f_b || (phase_b==`LAST_PHASE)), c_f_b, (phase_b==1));
wire reqhalt_g_b = mux1((readend_g_b || (phase_b==`LAST_PHASE)), c_g_b, (phase_b==1));
wire reqhalt_h_b = mux1((readend_h_b || (phase_b==`LAST_PHASE)), c_h_b, (phase_b==1));
always @(posedge CLK) begin
if (RSTa || pchange_a || pchange_b) begin
if (RSTa) state <= 0;
if (RSTa) {d_req, d_initadr, d_blocks} <= 0;
if (RSTa) w_addr_pzero <= (`SORT_ELM>>1);
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
radr_e <= ((`SELM_PER_WAY>>3)*4);
radr_f <= ((`SELM_PER_WAY>>3)*5);
radr_g <= ((`SELM_PER_WAY>>3)*6);
radr_h <= ((`SELM_PER_WAY>>3)*7);
{cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h} <= 0;
{c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h} <= 0;
if ((RSTa || pchange_a) && !plast_a) begin
req_a <= 0;
w_addr_a <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*0);
radr_b_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*1);
radr_c_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*2);
radr_d_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*3);
radr_e_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*4);
radr_f_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*5);
radr_g_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*6);
radr_h_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*7);
{cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a, cnt_e_a, cnt_f_a, cnt_g_a, cnt_h_a} <= 0;
{c_a_a, c_b_a, c_c_a, c_d_a, c_e_a, c_f_a, c_g_a, c_h_a} <= 0;
OB_granted_a <= 0;
end
if ((RSTa || pchange_b) && !plast_b) begin
req_b <= 0;
w_addr_b <= mux32(((`SORT_ELM>>2) | (`SORT_ELM>>1)), (`SORT_ELM>>2), phase_b[0]);
radr_a_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*0) | (`SORT_ELM>>2);
radr_b_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2);
radr_c_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2);
radr_d_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2);
radr_e_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*4) | (`SORT_ELM>>2);
radr_f_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*5) | (`SORT_ELM>>2);
radr_g_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*6) | (`SORT_ELM>>2);
radr_h_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*7) | (`SORT_ELM>>2);
{cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b, cnt_e_b, cnt_f_b, cnt_g_b, cnt_h_b} <= 0;
{c_a_b, c_b_b, c_c_b, c_d_b, c_e_b, c_f_b, c_g_b, c_h_b} <= 0;
OB_granted_b <= 0;
end
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
if (!phase_zero) state <= 4;
if (d_req != 0) d_req <= 0;
else if (!d_busy) begin
if (OB_req_a || OB_req_b) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr_pzero; //
w_addr_pzero <= w_addr_pzero + (`D_WS); // address for the next write
if (OB_req_a) begin OB_granted_a <= 1; OB_granted_b <= 0; end
else if (OB_req_b) begin OB_granted_a <= 0; OB_granted_b <= 1; end
end
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy && dc_req) begin
if (ib00_req_a[1] && !readend_a && ~reqcnt_a) begin req<=8'h01; state<=3; end // first priority
else if (ib01_req_a[1] && !readend_b && ~reqcnt_b) begin req<=8'h02; state<=3; end //
else if (ib02_req_a[1] && !readend_c && ~reqcnt_c) begin req<=8'h04; state<=3; end //
else if (ib03_req_a[1] && !readend_d && ~reqcnt_d) begin req<=8'h08; state<=3; end //
else if (ib04_req_a[1] && !readend_e && ~reqcnt_e) begin req<=8'h10; state<=3; end //
else if (ib05_req_a[1] && !readend_f && ~reqcnt_f) begin req<=8'h20; state<=3; end //
else if (ib06_req_a[1] && !readend_g && ~reqcnt_g) begin req<=8'h40; state<=3; end //
else if (ib07_req_a[1] && !readend_h && ~reqcnt_h) begin req<=8'h80; state<=3; end //
else state<=2;
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy && dc_req) begin // can be removed
if (ib00_req_a[0] && !readend_a && ~reqcnt_a) begin req<=8'h01; state<=3; end // second priority
else if (ib01_req_a[0] && !readend_b && ~reqcnt_b) begin req<=8'h02; state<=3; end //
else if (ib02_req_a[0] && !readend_c && ~reqcnt_c) begin req<=8'h04; state<=3; end //
else if (ib03_req_a[0] && !readend_d && ~reqcnt_d) begin req<=8'h08; state<=3; end //
else if (ib04_req_a[0] && !readend_e && ~reqcnt_e) begin req<=8'h10; state<=3; end //
else if (ib05_req_a[0] && !readend_f && ~reqcnt_f) begin req<=8'h20; state<=3; end //
else if (ib06_req_a[0] && !readend_g && ~reqcnt_g) begin req<=8'h40; state<=3; end //
else if (ib07_req_a[0] && !readend_h && ~reqcnt_h) begin req<=8'h80; state<=3; end //
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
case (req)
8'h01: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a <= radr_a+(r_block_a<<3);
d_blocks <= r_block_a;
end
8'h02: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), phase_a[0]);
radr_b <= radr_b+(r_block_b<<3);
d_blocks <= r_block_b;
end
8'h04: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), phase_a[0]);
radr_c <= radr_c+(r_block_c<<3);
d_blocks <= r_block_c;
end
8'h08: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), phase_a[0]);
radr_d <= radr_d+(r_block_d<<3);
d_blocks <= r_block_d;
end
8'h10: begin
d_initadr <= mux32(radr_e, (radr_e | (`SORT_ELM>>1)), phase_a[0]);
radr_e <= radr_e+(r_block_e<<3);
d_blocks <= r_block_e;
end
8'h20: begin
d_initadr <= mux32(radr_f, (radr_f | (`SORT_ELM>>1)), phase_a[0]);
radr_f <= radr_f+(r_block_f<<3);
d_blocks <= r_block_f;
end
8'h40: begin
d_initadr <= mux32(radr_g, (radr_g | (`SORT_ELM>>1)), phase_a[0]);
radr_g <= radr_g+(r_block_g<<3);
d_blocks <= r_block_g;
end
8'h80: begin
d_initadr <= mux32(radr_h, (radr_h | (`SORT_ELM>>1)), phase_a[0]);
radr_h <= radr_h+(r_block_h<<3);
d_blocks <= r_block_h;
end
endcase
d_req <= `DRAM_REQ_READ;
req_ta <= req;
req_tb <= 0;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin
if (!d_busy && dc_req) begin
///////////////// can be parameterized
if (ib00_req_a[1] && !reqhalt_a_a && ~reqcnt_a_a) begin req_a<=8'h01; req_b<=0; state<=6; end // 1st priority
else if (ib01_req_a[1] && !reqhalt_b_a && ~reqcnt_b_a) begin req_a<=8'h02; req_b<=0; state<=6; end //
else if (ib02_req_a[1] && !reqhalt_c_a && ~reqcnt_c_a) begin req_a<=8'h04; req_b<=0; state<=6; end //
else if (ib03_req_a[1] && !reqhalt_d_a && ~reqcnt_d_a) begin req_a<=8'h08; req_b<=0; state<=6; end //
else if (ib04_req_a[1] && !reqhalt_e_a && ~reqcnt_e_a) begin req_a<=8'h10; req_b<=0; state<=6; end //
else if (ib05_req_a[1] && !reqhalt_f_a && ~reqcnt_f_a) begin req_a<=8'h20; req_b<=0; state<=6; end //
else if (ib06_req_a[1] && !reqhalt_g_a && ~reqcnt_g_a) begin req_a<=8'h40; req_b<=0; state<=6; end //
else if (ib07_req_a[1] && !reqhalt_h_a && ~reqcnt_h_a) begin req_a<=8'h80; req_b<=0; state<=6; end //
else if (ib00_req_b[1] && !reqhalt_a_b && ~reqcnt_a_b) begin req_b<=8'h01; req_a<=0; state<=6; end //
else if (ib01_req_b[1] && !reqhalt_b_b && ~reqcnt_b_b) begin req_b<=8'h02; req_a<=0; state<=6; end //
else if (ib02_req_b[1] && !reqhalt_c_b && ~reqcnt_c_b) begin req_b<=8'h04; req_a<=0; state<=6; end //
else if (ib03_req_b[1] && !reqhalt_d_b && ~reqcnt_d_b) begin req_b<=8'h08; req_a<=0; state<=6; end //
else if (ib04_req_b[1] && !reqhalt_e_b && ~reqcnt_e_b) begin req_b<=8'h10; req_a<=0; state<=6; end //
else if (ib05_req_b[1] && !reqhalt_f_b && ~reqcnt_f_b) begin req_b<=8'h20; req_a<=0; state<=6; end //
else if (ib06_req_b[1] && !reqhalt_g_b && ~reqcnt_g_b) begin req_b<=8'h40; req_a<=0; state<=6; end //
else if (ib07_req_b[1] && !reqhalt_h_b && ~reqcnt_h_b) begin req_b<=8'h80; req_a<=0; state<=6; end //
else state<=5;
end
end
5: begin
case (plast_a)
0: begin
case (elem_a)
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*1: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*1), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*2), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*3: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*3), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*4: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*4) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*4), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*5: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*5) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*5), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*6: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*6) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*6), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*7: w_addr_a <= mux32(((`SELM_PER_WAY>>(`P_LOG+3))*7) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>(`P_LOG+3))*7), phase_a[0]);
endcase
end
1: begin
case (elem_a)
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2: w_addr_a <= mux32(((`SELM_PER_WAY>>3)*1) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>3)*1), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*4: w_addr_a <= mux32(((`SELM_PER_WAY>>3)*2) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>3)*2), phase_a[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*6: w_addr_a <= mux32(((`SELM_PER_WAY>>3)*3) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>3)*3), phase_a[0]);
endcase
end
endcase
case (plast_b)
0: begin
case (elem_b)
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*1: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2)), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2)), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*3: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2)), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*4: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*4) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*4) | (`SORT_ELM>>2)), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*5: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*5) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*5) | (`SORT_ELM>>2)), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*6: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*6) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*6) | (`SORT_ELM>>2)), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*7: w_addr_b <= mux32((((`SELM_PER_WAY>>(`P_LOG+3))*7) | (`SORT_ELM>>2)) | (`SORT_ELM>>1), (((`SELM_PER_WAY>>(`P_LOG+3))*7) | (`SORT_ELM>>2)), phase_b[0]);
endcase
end
1: begin
case (elem_b)
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2: w_addr_b <= mux32(((`SELM_PER_WAY>>3)*5) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>3)*5), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*4: w_addr_b <= mux32(((`SELM_PER_WAY>>3)*6) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>3)*6), phase_b[0]);
(`SORT_ELM>>(`P_LOG+`WAY_LOG))*6: w_addr_b <= mux32(((`SELM_PER_WAY>>3)*7) | (`SORT_ELM>>1), ((`SELM_PER_WAY>>3)*7), phase_b[0]);
endcase
end
endcase
///////////////// can be parameterized
if (ib00_req_a[0] && !reqhalt_a_a && ~reqcnt_a_a) begin req_a<=8'h01; req_b<=0; state<=6; end // 2nd priority
else if (ib01_req_a[0] && !reqhalt_b_a && ~reqcnt_b_a) begin req_a<=8'h02; req_b<=0; state<=6; end //
else if (ib02_req_a[0] && !reqhalt_c_a && ~reqcnt_c_a) begin req_a<=8'h04; req_b<=0; state<=6; end //
else if (ib03_req_a[0] && !reqhalt_d_a && ~reqcnt_d_a) begin req_a<=8'h08; req_b<=0; state<=6; end //
else if (ib04_req_a[0] && !reqhalt_e_a && ~reqcnt_e_a) begin req_a<=8'h10; req_b<=0; state<=6; end //
else if (ib05_req_a[0] && !reqhalt_f_a && ~reqcnt_f_a) begin req_a<=8'h20; req_b<=0; state<=6; end //
else if (ib06_req_a[0] && !reqhalt_g_a && ~reqcnt_g_a) begin req_a<=8'h40; req_b<=0; state<=6; end //
else if (ib07_req_a[0] && !reqhalt_h_a && ~reqcnt_h_a) begin req_a<=8'h80; req_b<=0; state<=6; end //
else if (ib00_req_b[0] && !reqhalt_a_b && ~reqcnt_a_b) begin req_b<=8'h01; req_a<=0; state<=6; end //
else if (ib01_req_b[0] && !reqhalt_b_b && ~reqcnt_b_b) begin req_b<=8'h02; req_a<=0; state<=6; end //
else if (ib02_req_b[0] && !reqhalt_c_b && ~reqcnt_c_b) begin req_b<=8'h04; req_a<=0; state<=6; end //
else if (ib03_req_b[0] && !reqhalt_d_b && ~reqcnt_d_b) begin req_b<=8'h08; req_a<=0; state<=6; end //
else if (ib04_req_b[0] && !reqhalt_e_b && ~reqcnt_e_b) begin req_b<=8'h10; req_a<=0; state<=6; end //
else if (ib05_req_b[0] && !reqhalt_f_b && ~reqcnt_f_b) begin req_b<=8'h20; req_a<=0; state<=6; end //
else if (ib06_req_b[0] && !reqhalt_g_b && ~reqcnt_g_b) begin req_b<=8'h40; req_a<=0; state<=6; end //
else if (ib07_req_b[0] && !reqhalt_h_b && ~reqcnt_h_b) begin req_b<=8'h80; req_a<=0; state<=6; end //
else if (OB_req_a) begin OB_granted_a <= 1; OB_granted_b <= 0; state<=7; end
else if (OB_req_b) begin OB_granted_a <= 0; OB_granted_b <= 1; state<=8; end
else if (last_phase) state<=1;
end
////////////////////////////////////////////////////////////////////////////////////////
6: begin
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
case ({req_b,req_a})
16'h0001: begin
d_initadr <= mux32(radr_a_a, (radr_a_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a_a <= mux32((radr_a_a+(r_block_a_a<<3)), radr_a_a+(`D_RS), (phase_a==1));
cnt_a_a <= cnt_a_a+1;
c_a_a <= (cnt_a_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_a_a, `DRAM_RBLOCKS, (phase_a==1));
end
16'h0002: begin
d_initadr <= mux32(radr_b_a, (radr_b_a | (`SORT_ELM>>1)), phase_a[0]);
radr_b_a <= mux32((radr_b_a+(r_block_b_a<<3)), radr_b_a+(`D_RS), (phase_a==1));
cnt_b_a <= cnt_b_a+1;
c_b_a <= (cnt_b_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_b_a, `DRAM_RBLOCKS, (phase_a==1));
end
16'h0004: begin
d_initadr <= mux32(radr_c_a, (radr_c_a | (`SORT_ELM>>1)), phase_a[0]);
radr_c_a <= mux32((radr_c_a+(r_block_c_a<<3)), radr_c_a+(`D_RS), (phase_a==1));
cnt_c_a <= cnt_c_a+1;
c_c_a <= (cnt_c_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_c_a, `DRAM_RBLOCKS, (phase_a==1));
end
16'h0008: begin
d_initadr <= mux32(radr_d_a, (radr_d_a | (`SORT_ELM>>1)), phase_a[0]);
radr_d_a <= mux32((radr_d_a+(r_block_d_a<<3)), radr_d_a+(`D_RS), (phase_a==1));
cnt_d_a <= cnt_d_a+1;
c_d_a <= (cnt_d_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_d_a, `DRAM_RBLOCKS, (phase_a==1));
end
16'h0010: begin
d_initadr <= mux32(radr_e_a, (radr_e_a | (`SORT_ELM>>1)), phase_a[0]);
radr_e_a <= mux32((radr_e_a+(r_block_e_a<<3)), radr_e_a+(`D_RS), (phase_a==1));
cnt_e_a <= cnt_e_a+1;
c_e_a <= (cnt_e_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_e_a, `DRAM_RBLOCKS, (phase_a==1));
end
16'h0020: begin
d_initadr <= mux32(radr_f_a, (radr_f_a | (`SORT_ELM>>1)), phase_a[0]);
radr_f_a <= mux32((radr_f_a+(r_block_f_a<<3)), radr_f_a+(`D_RS), (phase_a==1));
cnt_f_a <= cnt_f_a+1;
c_f_a <= (cnt_f_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_f_a, `DRAM_RBLOCKS, (phase_a==1));
end
16'h0040: begin
d_initadr <= mux32(radr_g_a, (radr_g_a | (`SORT_ELM>>1)), phase_a[0]);
radr_g_a <= mux32((radr_g_a+(r_block_g_a<<3)), radr_g_a+(`D_RS), (phase_a==1));
cnt_g_a <= cnt_g_a+1;
c_g_a <= (cnt_g_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_g_a, `DRAM_RBLOCKS, (phase_a==1));
end
16'h0080: begin
d_initadr <= mux32(radr_h_a, (radr_h_a | (`SORT_ELM>>1)), phase_a[0]);
radr_h_a <= mux32((radr_h_a+(r_block_h_a<<3)), radr_h_a+(`D_RS), (phase_a==1));
cnt_h_a <= cnt_h_a+1;
c_h_a <= (cnt_h_a>=`WAYP_CN_);
d_blocks <= mux32(r_block_h_a, `DRAM_RBLOCKS, (phase_a==1));
end
16'h0100: begin
d_initadr <= mux32(radr_a_b, (radr_a_b | (`SORT_ELM>>1)), phase_b[0]);
radr_a_b <= mux32((radr_a_b+(r_block_a_b<<3)), radr_a_b+(`D_RS), (phase_b==1));
cnt_a_b <= cnt_a_b+1;
c_a_b <= (cnt_a_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_a_b, `DRAM_RBLOCKS, (phase_b==1));
end
16'h0200: begin
d_initadr <= mux32(radr_b_b, (radr_b_b | (`SORT_ELM>>1)), phase_b[0]);
radr_b_b <= mux32((radr_b_b+(r_block_b_b<<3)), radr_b_b+(`D_RS), (phase_b==1));
cnt_b_b <= cnt_b_b+1;
c_b_b <= (cnt_b_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_b_b, `DRAM_RBLOCKS, (phase_b==1));
end
16'h0400: begin
d_initadr <= mux32(radr_c_b, (radr_c_b | (`SORT_ELM>>1)), phase_b[0]);
radr_c_b <= mux32((radr_c_b+(r_block_c_b<<3)), radr_c_b+(`D_RS), (phase_b==1));
cnt_c_b <= cnt_c_b+1;
c_c_b <= (cnt_c_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_c_b, `DRAM_RBLOCKS, (phase_b==1));
end
16'h0800: begin
d_initadr <= mux32(radr_d_b, (radr_d_b | (`SORT_ELM>>1)), phase_b[0]);
radr_d_b <= mux32((radr_d_b+(r_block_d_b<<3)), radr_d_b+(`D_RS), (phase_b==1));
cnt_d_b <= cnt_d_b+1;
c_d_b <= (cnt_d_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_d_b, `DRAM_RBLOCKS, (phase_b==1));
end
16'h1000: begin
d_initadr <= mux32(radr_e_b, (radr_e_b | (`SORT_ELM>>1)), phase_b[0]);
radr_e_b <= mux32((radr_e_b+(r_block_e_b<<3)), radr_e_b+(`D_RS), (phase_b==1));
cnt_e_b <= cnt_e_b+1;
c_e_b <= (cnt_e_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_e_b, `DRAM_RBLOCKS, (phase_b==1));
end
16'h2000: begin
d_initadr <= mux32(radr_f_b, (radr_f_b | (`SORT_ELM>>1)), phase_b[0]);
radr_f_b <= mux32((radr_f_b+(r_block_f_b<<3)), radr_f_b+(`D_RS), (phase_b==1));
cnt_f_b <= cnt_f_b+1;
c_f_b <= (cnt_f_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_f_b, `DRAM_RBLOCKS, (phase_b==1));
end
16'h4000: begin
d_initadr <= mux32(radr_g_b, (radr_g_b | (`SORT_ELM>>1)), phase_b[0]);
radr_g_b <= mux32((radr_g_b+(r_block_g_b<<3)), radr_g_b+(`D_RS), (phase_b==1));
cnt_g_b <= cnt_g_b+1;
c_g_b <= (cnt_g_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_g_b, `DRAM_RBLOCKS, (phase_b==1));
end
16'h8000: begin
d_initadr <= mux32(radr_h_b, (radr_h_b | (`SORT_ELM>>1)), phase_b[0]);
radr_h_b <= mux32((radr_h_b+(r_block_h_b<<3)), radr_h_b+(`D_RS), (phase_b==1));
cnt_h_b <= cnt_h_b+1;
c_h_b <= (cnt_h_b>=`WAYP_CN_);
d_blocks <= mux32(r_block_h_b, `DRAM_RBLOCKS, (phase_b==1));
end
endcase
d_req <= `DRAM_REQ_READ;
req_ta <= req_a;
req_tb <= req_b;
end
end
7: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= w_block_a; //
d_initadr <= w_addr_a; //
w_addr_a <= w_addr_a + (w_block_a<<3); // address for the next write
end
end
8: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= w_block_b; //
d_initadr <= w_addr_b; //
w_addr_b <= w_addr_b + (w_block_b<<3); // address for the next write
end
end
////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
/**********************************************************************************************/
always @(posedge CLK) begin
// Stage 0
////////////////////////////////////
dout_ta <= mux512(dc_dout, stnet_dout, phase_zero);
dout_tb <= mux512(dc_dout, stnet_dout, phase_zero);
doen_ta <= mux1(dc_cout[0], stnet_douten, phase_zero);
doen_tb <= mux1(dc_cout[0], stnet_douten, phase_zero);
req_taa <= dc_cout[`SORT_WAY:1];
req_tba <= dc_cout[`SORT_WAY*2:`SORT_WAY+1];
// Stage 1
////////////////////////////////////
dout_tc <= dout_ta;
dout_td <= dout_ta;
dout_te <= dout_tb;
dout_tf <= dout_tb;
doen_tc <= doen_ta;
doen_td <= doen_ta;
doen_te <= doen_tb;
doen_tf <= doen_tb;
req_tab <= req_taa;
req_tbb <= req_tba;
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
phase_a <= 0;
end else begin
if (elem_a==`SRTP_ELM) phase_a <= phase_a+1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
phase_b <= 0;
end else begin
if (elem_b==`SRTP_ELM) phase_b <= phase_b+1;
end
end
// for plast
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
plast_a <= 0;
end else begin
if (phase_a==`LAST_PHASE-1) plast_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
plast_b <= 0;
end else begin
if (phase_b==`LAST_PHASE-1) plast_b <= 1;
end
end
// for elem
// ###########################################################################
reg c_valid_a; // check whether the data is compressed or not
always @(posedge CLK) c_valid_a <= (OB_dot_a[`DRAMW-1:`DRAMW-33] == {32'b0,1'b1});
always @(posedge CLK) elem_en_a <= OB_doten_a;
always @(posedge CLK) begin
if (RSTa) begin
elem_a <= 0;
end else begin
case ({elem_en_a, (elem_a==`SRTP_ELM)})
2'b01: elem_a <= 0;
2'b10: elem_a <= mux32(elem_a+16, elem_a+32, c_valid_a);
endcase
end
end
always @(posedge CLK) begin
if (RSTa) begin
elem_way_a <= 0;
end else begin
case ({elem_en_a, (elem_way_a==(`SORT_ELM>>(`P_LOG+`WAY_LOG)))})
2'b01: elem_way_a <= 0;
2'b10: elem_way_a <= mux32(elem_way_a+16, elem_way_a+32, c_valid_a);
endcase
end
end
always @(posedge CLK) begin
if (RSTa) begin
elem_plast_a <= 0;
end else begin
case ({elem_en_a, (elem_plast_a==(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2)})
2'b01: elem_plast_a <= 0;
2'b10: elem_plast_a <= mux32(elem_plast_a+16, elem_plast_a+32, c_valid_a);
endcase
end
end
reg c_valid_b; // check whether the data is compressed or not
always @(posedge CLK) c_valid_b <= (OB_dot_b[`DRAMW-1:`DRAMW-33] == {32'b0,1'b1});
always @(posedge CLK) elem_en_b <= OB_doten_b;
always @(posedge CLK) begin
if (RSTb) begin
elem_b <= 0;
end else begin
case ({elem_en_b, (elem_b==`SRTP_ELM)})
2'b01: elem_b <= 0;
2'b10: elem_b <= mux32(elem_b+16, elem_b+32, c_valid_b);
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_way_b <= 0;
end else begin
case ({elem_en_b, (elem_way_b==(`SORT_ELM>>(`P_LOG+`WAY_LOG)))})
2'b01: elem_way_b <= 0;
2'b10: elem_way_b <= mux32(elem_way_b+16, elem_way_b+32, c_valid_b);
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_plast_b <= 0;
end else begin
case ({elem_en_b, (elem_plast_b==(`SORT_ELM>>(`P_LOG+`WAY_LOG))*2)})
2'b01: elem_plast_b <= 0;
2'b10: elem_plast_b <= mux32(elem_plast_b+16, elem_plast_b+32, c_valid_b);
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done_a <= (ecnt_a==8);
always @(posedge CLK) iter_done_b <= (ecnt_b==8);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange_a <= (elem_a==`SRTP_ELM);
always @(posedge CLK) pchange_b <= (elem_b==`SRTP_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst_a <= (ecnt_a==8) || pchange_a;
always @(posedge CLK) irst_b <= (ecnt_b==8) || pchange_b;
// for frst
// ###########################################################################
always @(posedge CLK) frst_a <= RSTa || (ecnt_a==8) || (elem_a==`SRTP_ELM);
always @(posedge CLK) frst_b <= RSTb || (ecnt_b==8) || (elem_b==`SRTP_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RSTa || iter_done_a || pchange_a) begin
ecnt_a <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_a * `WAY_LOG));
end else begin
if (ecnt_a!=0 && F01_deq_a) ecnt_a <= ecnt_a - 4;
end
end
always @(posedge CLK) begin
if (RSTb || iter_done_b || pchange_b) begin
ecnt_b <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_b * `WAY_LOG));
end else begin
if (ecnt_b!=0 && F01_deq_b) ecnt_b <= ecnt_b - 4;
end
end
// for phase zero
// ###########################################################################
always @(posedge CLK) phase_zero <= ((phase_a == 0) || (phase_b == 0));
// for last phase
// ###########################################################################
always @(posedge CLK) last_phase <= ((phase_a == `LAST_PHASE) && (phase_b == `LAST_PHASE));
// for debug
// ###########################################################################
// (* mark_debug = "true" *) reg [31:0] dcnt;
// always @(posedge CLK) begin
// if (RST) begin
// dcnt <= 0;
// end else begin
// case ({F01_deq, (dcnt==`SORT_ELM)})
// 2'b01: dcnt <= 0;
// 2'b10: dcnt <= dcnt + 4;
// endcase
// end
// end
endmodule // CORE
/**************************************************************************************************/
`default_nettype wire
|
/* HW4, Problem 24a */
module jerk_ct(output reg [7:0] count, input clk, reset);
reg [3:0] state; // 0 to 13 needed.
always @(posedge clk) begin
if (reset == 1) begin
state = 13;
end
case(state)
0: begin count <= 8'b00000010; state <= 1; end
1: begin count <= 8'b00000001; state <= 2; end
2: begin count <= 8'b00000100; state <= 3; end
3: begin count <= 8'b00000001; state <= 4; end
4: begin count <= 8'b00001000; state <= 5; end
5: begin count <= 8'b00000001; state <= 6; end
6: begin count <= 8'b00010000; state <= 7; end
7: begin count <= 8'b00000001; state <= 8; end
8: begin count <= 8'b00100000; state <= 9; end
9: begin count <= 8'b00000001; state <= 10;end
10:begin count <= 8'b01000000; state <= 11;end
11:begin count <= 8'b00000001; state <= 12;end
12:begin count <= 8'b10000000; state <= 13;end
13,14,15:
begin count <= 8'b00000001; state <= 0; end
endcase
end
endmodule
module p24_tb();
reg clk, reset;
wire [7:0] count;
jerk_ct device(count, clk, reset);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset = 0;
reset = 1;
#10 reset = 0;
$dumpfile("p24a.vcd");
$dumpvars(0, device);
fork
#201 reset = 1;
#205 reset = 0;
#300 reset = 1;
#320 reset = 0;
#500 $finish;
join
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: altera_primitive_sync_fifo_8in_8out_16depth.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 216 11/23/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_primitive_sync_fifo_8in_8out_16depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [7:0] data;
input rdreq;
input sclr;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [7:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [7:0] q = sub_wire3[7:0];
wire almost_empty = sub_wire4;
wire almost_full = sub_wire5;
scfifo scfifo_component (
.clock (clock),
.sclr (sclr),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (sub_wire4),
.almost_full (sub_wire5));
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_empty_value = 2,
scfifo_component.almost_full_value = 14,
scfifo_component.intended_device_family = "Cyclone IV GX",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "2"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "14"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "2"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "14"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL "almost_empty"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_8in_8out_16depth.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_8in_8out_16depth.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_8in_8out_16depth.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_8in_8out_16depth.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_8in_8out_16depth_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_8in_8out_16depth_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Tue Dec 22 18:42:27 2015
// Host : jon-GA-MA770T-ES3 running 64-bit Linux Mint 17.2 Rafaela
// Command : write_verilog -force ./cpu_impl_netlist.v -mode timesim -sdf_anno true
// Design : BSP
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
module BRAM
(DOBDO,
ETH_CLK_OBUF,
ADDRBWRADDR,
pwropt);
output [3:0]DOBDO;
input ETH_CLK_OBUF;
input [12:0]ADDRBWRADDR;
input pwropt;
wire [12:0]ADDRBWRADDR;
wire [3:0]DOBDO;
wire ETH_CLK_OBUF;
wire pwropt;
wire NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_MEMORY_reg_0_DBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED;
wire NLW_MEMORY_reg_0_REGCEB_UNCONNECTED;
wire NLW_MEMORY_reg_0_SBITERR_UNCONNECTED;
wire [31:0]NLW_MEMORY_reg_0_DOADO_UNCONNECTED;
wire [31:4]NLW_MEMORY_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED;
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENBWREN=NEW" *)
(* RTL_RAM_BITS = "60000" *)
(* RTL_RAM_NAME = "MEMORY" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.IS_ENBWREN_INVERTED(1'b1),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
MEMORY_reg_0
(.ADDRARDADDR({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(ETH_CLK_OBUF),
.DBITERR(NLW_MEMORY_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_MEMORY_reg_0_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_MEMORY_reg_0_DOBDO_UNCONNECTED[31:4],DOBDO}),
.DOPADOP(NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(1'b1),
.ENBWREN(pwropt),
.INJECTDBITERR(NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_MEMORY_reg_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_MEMORY_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ECO_CHECKSUM = "741e86af" *) (* POWER_OPT_BRAM_CDC = "0" *) (* POWER_OPT_BRAM_SR_ADDR = "0" *)
(* POWER_OPT_LOOPED_NET_PERCENTAGE = "0" *)
(* NotValidForBitStream *)
module BSP
(CLK_IN,
RST,
ETH_CLK,
PHY_RESET_N,
RXDV,
RXER,
RXD,
TXD,
TXEN,
JC,
SDA,
SCL,
KD,
KC,
AUDIO,
AUDIO_EN,
VGA_R,
VGA_G,
VGA_B,
HSYNCH,
VSYNCH,
GPIO_LEDS,
GPIO_SWITCHES,
GPIO_BUTTONS,
LED_R_PWM,
LED_G_PWM,
LED_B_PWM,
SEVEN_SEGMENT_CATHODE,
SEVEN_SEGMENT_ANNODE,
RS232_RX,
RS232_TX);
input CLK_IN;
input RST;
output ETH_CLK;
output PHY_RESET_N;
input RXDV;
input RXER;
input [1:0]RXD;
output [1:0]TXD;
output TXEN;
inout [7:0]JC;
inout SDA;
inout SCL;
input KD;
input KC;
output AUDIO;
output AUDIO_EN;
output [3:0]VGA_R;
output [3:0]VGA_G;
output [3:0]VGA_B;
output HSYNCH;
output VSYNCH;
output [15:0]GPIO_LEDS;
input [15:0]GPIO_SWITCHES;
input [4:0]GPIO_BUTTONS;
output LED_R_PWM;
output LED_G_PWM;
output LED_B_PWM;
output [6:0]SEVEN_SEGMENT_CATHODE;
output [7:0]SEVEN_SEGMENT_ANNODE;
input RS232_RX;
output RS232_TX;
wire AUDIO;
wire AUDIO_EN;
wire CLKFB;
wire CLKIN;
(* IBUF_LOW_PWR *) wire CLK_IN;
wire [7:0]DATA;
wire DATA_STB;
wire ETH_CLK;
wire ETH_CLK_OBUF;
wire \GPIO_BUTTONS[0] ;
wire \GPIO_BUTTONS[0]_IBUF ;
wire \GPIO_BUTTONS[1] ;
wire \GPIO_BUTTONS[1]_IBUF ;
wire \GPIO_BUTTONS[2] ;
wire \GPIO_BUTTONS[2]_IBUF ;
wire \GPIO_BUTTONS[3] ;
wire \GPIO_BUTTONS[3]_IBUF ;
wire \GPIO_BUTTONS[4] ;
wire \GPIO_BUTTONS[4]_IBUF ;
wire [15:0]GPIO_LEDS;
wire \GPIO_SWITCHES[0] ;
wire \GPIO_SWITCHES[0]_IBUF ;
wire \GPIO_SWITCHES[10] ;
wire \GPIO_SWITCHES[10]_IBUF ;
wire \GPIO_SWITCHES[11] ;
wire \GPIO_SWITCHES[11]_IBUF ;
wire \GPIO_SWITCHES[12] ;
wire \GPIO_SWITCHES[12]_IBUF ;
wire \GPIO_SWITCHES[13] ;
wire \GPIO_SWITCHES[13]_IBUF ;
wire \GPIO_SWITCHES[14] ;
wire \GPIO_SWITCHES[14]_IBUF ;
wire \GPIO_SWITCHES[15] ;
wire \GPIO_SWITCHES[15]_IBUF ;
wire \GPIO_SWITCHES[1] ;
wire \GPIO_SWITCHES[1]_IBUF ;
wire \GPIO_SWITCHES[2] ;
wire \GPIO_SWITCHES[2]_IBUF ;
wire \GPIO_SWITCHES[3] ;
wire \GPIO_SWITCHES[3]_IBUF ;
wire \GPIO_SWITCHES[4] ;
wire \GPIO_SWITCHES[4]_IBUF ;
wire \GPIO_SWITCHES[5] ;
wire \GPIO_SWITCHES[5]_IBUF ;
wire \GPIO_SWITCHES[6] ;
wire \GPIO_SWITCHES[6]_IBUF ;
wire \GPIO_SWITCHES[7] ;
wire \GPIO_SWITCHES[7]_IBUF ;
wire \GPIO_SWITCHES[8] ;
wire \GPIO_SWITCHES[8]_IBUF ;
wire \GPIO_SWITCHES[9] ;
wire \GPIO_SWITCHES[9]_IBUF ;
wire HSYNCH;
wire HSYNCH_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg_n_0;
wire [7:0]JC;
wire [1:1]JC_IBUF;
wire KC;
wire KC_IBUF;
wire KD;
wire KD_IBUF;
wire LED_B_PWM;
wire LED_B_PWM_OBUF;
wire LED_G_PWM;
wire LED_G_PWM_OBUF;
wire LED_R_PWM;
wire LED_R_PWM_OBUF;
wire NOT_LOCKED;
wire NOT_LOCKED_i_1_n_0;
wire [7:0]OUT1;
wire OUT1_ACK;
wire OUT1_STB;
wire PHY_RESET_N;
wire PHY_RESET_N_OBUF;
wire RS232_RX;
wire RS232_RX_IBUF;
wire RS232_TX;
wire RS232_TX_OBUF;
wire RST;
wire RST_IBUF;
wire RXDV;
wire RXDV_IBUF;
wire \RXD[0] ;
wire \RXD[0]_IBUF ;
wire \RXD[1] ;
wire \RXD[1]_IBUF ;
wire RXER;
wire RXER_IBUF;
(* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "SLOW" *) wire SCL;
wire SCL_IBUF;
wire SCL_TRI;
wire SDA;
wire SDA_IBUF;
wire SDA_TRI;
wire [7:0]SEVEN_SEGMENT_ANNODE;
wire [6:0]SEVEN_SEGMENT_CATHODE;
wire [1:0]TXD;
wire [1:0]TXD_OBUF;
wire TXEN;
wire TXEN_OBUF;
wire USER_DESIGN_INST_1_n_0;
wire USER_DESIGN_INST_1_n_10;
wire USER_DESIGN_INST_1_n_11;
wire USER_DESIGN_INST_1_n_2;
wire USER_DESIGN_INST_1_n_20;
wire USER_DESIGN_INST_1_n_21;
wire USER_DESIGN_INST_1_n_22;
wire USER_DESIGN_INST_1_n_23;
wire USER_DESIGN_INST_1_n_24;
wire USER_DESIGN_INST_1_n_25;
wire USER_DESIGN_INST_1_n_26;
wire USER_DESIGN_INST_1_n_27;
wire USER_DESIGN_INST_1_n_28;
wire USER_DESIGN_INST_1_n_29;
wire USER_DESIGN_INST_1_n_30;
wire USER_DESIGN_INST_1_n_31;
wire USER_DESIGN_INST_1_n_32;
wire USER_DESIGN_INST_1_n_33;
wire USER_DESIGN_INST_1_n_34;
wire USER_DESIGN_INST_1_n_35;
wire USER_DESIGN_INST_1_n_4;
wire USER_DESIGN_INST_1_n_5;
wire USER_DESIGN_INST_1_n_6;
wire USER_DESIGN_INST_1_n_7;
wire USER_DESIGN_INST_1_n_8;
wire USER_DESIGN_INST_1_n_9;
wire [3:0]VGA_B;
wire [0:0]VGA_B_OBUF;
wire [3:0]VGA_G;
wire [3:0]VGA_R;
wire VSYNCH;
wire VSYNCH_OBUF;
wire clk0;
wire clkdv;
wire locked_internal;
wire NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED;
wire NLW_dcm_sp_inst_DRDY_UNCONNECTED;
wire NLW_dcm_sp_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_dcm_sp_inst_DO_UNCONNECTED;
wire NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED;
wire NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED;
wire [1:0]NLW_ethernet_inst_1_D_UNCONNECTED;
PULLUP pullup_KC
(.O(KC));
PULLUP pullup_KD
(.O(KD));
initial begin
$sdf_annotate("cpu_impl_netlist.sdf",,,,"tool_control");
end
assign \GPIO_BUTTONS[0] = GPIO_BUTTONS[0];
assign \GPIO_BUTTONS[1] = GPIO_BUTTONS[1];
assign \GPIO_BUTTONS[2] = GPIO_BUTTONS[2];
assign \GPIO_BUTTONS[3] = GPIO_BUTTONS[3];
assign \GPIO_BUTTONS[4] = GPIO_BUTTONS[4];
assign \GPIO_SWITCHES[0] = GPIO_SWITCHES[0];
assign \GPIO_SWITCHES[10] = GPIO_SWITCHES[10];
assign \GPIO_SWITCHES[11] = GPIO_SWITCHES[11];
assign \GPIO_SWITCHES[12] = GPIO_SWITCHES[12];
assign \GPIO_SWITCHES[13] = GPIO_SWITCHES[13];
assign \GPIO_SWITCHES[14] = GPIO_SWITCHES[14];
assign \GPIO_SWITCHES[15] = GPIO_SWITCHES[15];
assign \GPIO_SWITCHES[1] = GPIO_SWITCHES[1];
assign \GPIO_SWITCHES[2] = GPIO_SWITCHES[2];
assign \GPIO_SWITCHES[3] = GPIO_SWITCHES[3];
assign \GPIO_SWITCHES[4] = GPIO_SWITCHES[4];
assign \GPIO_SWITCHES[5] = GPIO_SWITCHES[5];
assign \GPIO_SWITCHES[6] = GPIO_SWITCHES[6];
assign \GPIO_SWITCHES[7] = GPIO_SWITCHES[7];
assign \GPIO_SWITCHES[8] = GPIO_SWITCHES[8];
assign \GPIO_SWITCHES[9] = GPIO_SWITCHES[9];
assign \RXD[0] = RXD[0];
assign \RXD[1] = RXD[1];
OBUF AUDIO_EN_OBUF_inst
(.I(1'b1),
.O(AUDIO_EN));
OBUF AUDIO_OBUF_inst
(.I(1'b0),
.O(AUDIO));
(* box_type = "PRIMITIVE" *)
BUFG BUFG_INST1
(.I(clkdv),
.O(ETH_CLK_OBUF));
(* box_type = "PRIMITIVE" *)
BUFG BUFG_INST2
(.I(clk0),
.O(CLKFB));
CHARSVGA CHARSVGA_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.HSYNCH(HSYNCH_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.VGA_B_OBUF(VGA_B_OBUF),
.VSYNCH(VSYNCH_OBUF));
OBUF ETH_CLK_OBUF_inst
(.I(ETH_CLK_OBUF),
.O(ETH_CLK));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[0]_IBUF_inst
(.I(\GPIO_BUTTONS[0] ),
.O(\GPIO_BUTTONS[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[1]_IBUF_inst
(.I(\GPIO_BUTTONS[1] ),
.O(\GPIO_BUTTONS[1]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[2]_IBUF_inst
(.I(\GPIO_BUTTONS[2] ),
.O(\GPIO_BUTTONS[2]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[3]_IBUF_inst
(.I(\GPIO_BUTTONS[3] ),
.O(\GPIO_BUTTONS[3]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[4]_IBUF_inst
(.I(\GPIO_BUTTONS[4] ),
.O(\GPIO_BUTTONS[4]_IBUF ));
OBUF \GPIO_LEDS_OBUF[0]_inst
(.I(1'b0),
.O(GPIO_LEDS[0]));
OBUF \GPIO_LEDS_OBUF[10]_inst
(.I(1'b0),
.O(GPIO_LEDS[10]));
OBUF \GPIO_LEDS_OBUF[11]_inst
(.I(1'b0),
.O(GPIO_LEDS[11]));
OBUF \GPIO_LEDS_OBUF[12]_inst
(.I(1'b0),
.O(GPIO_LEDS[12]));
OBUF \GPIO_LEDS_OBUF[13]_inst
(.I(1'b0),
.O(GPIO_LEDS[13]));
OBUF \GPIO_LEDS_OBUF[14]_inst
(.I(1'b0),
.O(GPIO_LEDS[14]));
OBUF \GPIO_LEDS_OBUF[15]_inst
(.I(1'b0),
.O(GPIO_LEDS[15]));
OBUF \GPIO_LEDS_OBUF[1]_inst
(.I(1'b0),
.O(GPIO_LEDS[1]));
OBUF \GPIO_LEDS_OBUF[2]_inst
(.I(1'b0),
.O(GPIO_LEDS[2]));
OBUF \GPIO_LEDS_OBUF[3]_inst
(.I(1'b0),
.O(GPIO_LEDS[3]));
OBUF \GPIO_LEDS_OBUF[4]_inst
(.I(1'b0),
.O(GPIO_LEDS[4]));
OBUF \GPIO_LEDS_OBUF[5]_inst
(.I(1'b0),
.O(GPIO_LEDS[5]));
OBUF \GPIO_LEDS_OBUF[6]_inst
(.I(1'b0),
.O(GPIO_LEDS[6]));
OBUF \GPIO_LEDS_OBUF[7]_inst
(.I(1'b0),
.O(GPIO_LEDS[7]));
OBUF \GPIO_LEDS_OBUF[8]_inst
(.I(1'b0),
.O(GPIO_LEDS[8]));
OBUF \GPIO_LEDS_OBUF[9]_inst
(.I(1'b0),
.O(GPIO_LEDS[9]));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[0]_IBUF_inst
(.I(\GPIO_SWITCHES[0] ),
.O(\GPIO_SWITCHES[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[10]_IBUF_inst
(.I(\GPIO_SWITCHES[10] ),
.O(\GPIO_SWITCHES[10]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[11]_IBUF_inst
(.I(\GPIO_SWITCHES[11] ),
.O(\GPIO_SWITCHES[11]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[12]_IBUF_inst
(.I(\GPIO_SWITCHES[12] ),
.O(\GPIO_SWITCHES[12]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[13]_IBUF_inst
(.I(\GPIO_SWITCHES[13] ),
.O(\GPIO_SWITCHES[13]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[14]_IBUF_inst
(.I(\GPIO_SWITCHES[14] ),
.O(\GPIO_SWITCHES[14]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[15]_IBUF_inst
(.I(\GPIO_SWITCHES[15] ),
.O(\GPIO_SWITCHES[15]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[1]_IBUF_inst
(.I(\GPIO_SWITCHES[1] ),
.O(\GPIO_SWITCHES[1]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[2]_IBUF_inst
(.I(\GPIO_SWITCHES[2] ),
.O(\GPIO_SWITCHES[2]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[3]_IBUF_inst
(.I(\GPIO_SWITCHES[3] ),
.O(\GPIO_SWITCHES[3]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[4]_IBUF_inst
(.I(\GPIO_SWITCHES[4] ),
.O(\GPIO_SWITCHES[4]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[5]_IBUF_inst
(.I(\GPIO_SWITCHES[5] ),
.O(\GPIO_SWITCHES[5]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[6]_IBUF_inst
(.I(\GPIO_SWITCHES[6] ),
.O(\GPIO_SWITCHES[6]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[7]_IBUF_inst
(.I(\GPIO_SWITCHES[7] ),
.O(\GPIO_SWITCHES[7]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[8]_IBUF_inst
(.I(\GPIO_SWITCHES[8] ),
.O(\GPIO_SWITCHES[8]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[9]_IBUF_inst
(.I(\GPIO_SWITCHES[9] ),
.O(\GPIO_SWITCHES[9]_IBUF ));
OBUF HSYNCH_OBUF_inst
(.I(HSYNCH_OBUF),
.O(HSYNCH));
I2C I2C_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.SCL_IBUF(SCL_IBUF),
.SCL_TRI(SCL_TRI),
.SDA_IBUF(SDA_IBUF),
.SDA_TRI(SDA_TRI));
FDRE INTERNAL_RST_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(NOT_LOCKED),
.Q(INTERNAL_RST_reg_n_0),
.R(1'b0));
OBUF \JC_OBUF[0]_inst
(.I(1'b1),
.O(JC[0]));
OBUF \JC_OBUF[1]_inst
(.I(JC_IBUF),
.O(JC[1]));
(* OPT_INSERTED *)
IBUF KC_IBUF_inst
(.I(KC),
.O(KC_IBUF));
(* OPT_INSERTED *)
IBUF KD_IBUF_inst
(.I(KD),
.O(KD_IBUF));
OBUF LED_B_PWM_OBUF_inst
(.I(LED_B_PWM_OBUF),
.O(LED_B_PWM));
OBUF LED_G_PWM_OBUF_inst
(.I(LED_G_PWM_OBUF),
.O(LED_G_PWM));
OBUF LED_R_PWM_OBUF_inst
(.I(LED_R_PWM_OBUF),
.O(LED_R_PWM));
LUT1 #(
.INIT(2'h1))
NOT_LOCKED_i_1
(.I0(locked_internal),
.O(NOT_LOCKED_i_1_n_0));
FDRE NOT_LOCKED_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(NOT_LOCKED_i_1_n_0),
.Q(NOT_LOCKED),
.R(1'b0));
OBUF PHY_RESET_N_OBUF_inst
(.I(PHY_RESET_N_OBUF),
.O(PHY_RESET_N));
LUT1 #(
.INIT(2'h1))
PHY_RESET_N_OBUF_inst_i_1
(.I0(INTERNAL_RST_reg_n_0),
.O(PHY_RESET_N_OBUF));
PWM PWM_INST_1
(.E(USER_DESIGN_INST_1_n_2),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_R_PWM_OBUF(LED_R_PWM_OBUF),
.Q({USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8,USER_DESIGN_INST_1_n_9,USER_DESIGN_INST_1_n_10,USER_DESIGN_INST_1_n_11}));
PWM_0 PWM_INST_2
(.E(DATA_STB),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_G_PWM_OBUF(LED_G_PWM_OBUF),
.Q(DATA));
PWM_1 PWM_INST_3
(.E(USER_DESIGN_INST_1_n_0),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_B_PWM_OBUF(LED_B_PWM_OBUF),
.Q({USER_DESIGN_INST_1_n_20,USER_DESIGN_INST_1_n_21,USER_DESIGN_INST_1_n_22,USER_DESIGN_INST_1_n_23,USER_DESIGN_INST_1_n_24,USER_DESIGN_INST_1_n_25,USER_DESIGN_INST_1_n_26,USER_DESIGN_INST_1_n_27}));
IBUF RS232_RX_IBUF_inst
(.I(RS232_RX),
.O(RS232_RX_IBUF));
OBUF RS232_TX_OBUF_inst
(.I(RS232_TX_OBUF),
.O(RS232_TX));
IBUF RST_IBUF_inst
(.I(RST),
.O(RST_IBUF));
(* OPT_INSERTED *)
IBUF RXDV_IBUF_inst
(.I(RXDV),
.O(RXDV_IBUF));
(* OPT_INSERTED *)
IBUF \RXD[0]_IBUF_inst
(.I(\RXD[0] ),
.O(\RXD[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \RXD[1]_IBUF_inst
(.I(\RXD[1] ),
.O(\RXD[1]_IBUF ));
(* OPT_INSERTED *)
IBUF RXER_IBUF_inst
(.I(RXER),
.O(RXER_IBUF));
IOBUF_HD3 SCL_IOBUF_inst
(.I(1'b0),
.IO(SCL),
.O(SCL_IBUF),
.T(SCL_TRI));
IOBUF_UNIQ_BASE_ SDA_IOBUF_inst
(.I(1'b0),
.IO(SDA),
.O(SDA_IBUF),
.T(SDA_TRI));
SERIAL_INPUT SERIAL_INPUT_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.OUT1(OUT1),
.OUT1_ACK(OUT1_ACK),
.OUT1_STB(OUT1_STB),
.RX(RS232_RX_IBUF));
serial_output SERIAL_OUTPUT_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.Q({USER_DESIGN_INST_1_n_28,USER_DESIGN_INST_1_n_29,USER_DESIGN_INST_1_n_30,USER_DESIGN_INST_1_n_31,USER_DESIGN_INST_1_n_32,USER_DESIGN_INST_1_n_33,USER_DESIGN_INST_1_n_34,USER_DESIGN_INST_1_n_35}),
.RS232_TX_OBUF(RS232_TX_OBUF));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[0]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[0]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[1]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[1]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[2]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[2]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[3]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[3]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[4]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[4]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[5]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[5]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[6]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[6]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[7]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[7]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[0]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[0]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[1]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[1]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[2]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[2]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[3]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[3]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[4]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[4]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[5]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[5]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[6]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[6]));
OBUF \TXD_OBUF[0]_inst
(.I(TXD_OBUF[0]),
.O(TXD[0]));
OBUF \TXD_OBUF[1]_inst
(.I(TXD_OBUF[1]),
.O(TXD[1]));
OBUF TXEN_OBUF_inst
(.I(TXEN_OBUF),
.O(TXEN));
user_design USER_DESIGN_INST_1
(.E(USER_DESIGN_INST_1_n_0),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.OUT1(OUT1),
.OUT1_ACK(OUT1_ACK),
.OUT1_STB(OUT1_STB),
.\PWM_VAL_reg[7] (DATA_STB),
.\PWM_VAL_reg[7]_0 (USER_DESIGN_INST_1_n_2),
.output_led_b({USER_DESIGN_INST_1_n_20,USER_DESIGN_INST_1_n_21,USER_DESIGN_INST_1_n_22,USER_DESIGN_INST_1_n_23,USER_DESIGN_INST_1_n_24,USER_DESIGN_INST_1_n_25,USER_DESIGN_INST_1_n_26,USER_DESIGN_INST_1_n_27}),
.output_led_g(DATA),
.output_led_r({USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8,USER_DESIGN_INST_1_n_9,USER_DESIGN_INST_1_n_10,USER_DESIGN_INST_1_n_11}),
.output_rs232_tx({USER_DESIGN_INST_1_n_28,USER_DESIGN_INST_1_n_29,USER_DESIGN_INST_1_n_30,USER_DESIGN_INST_1_n_31,USER_DESIGN_INST_1_n_32,USER_DESIGN_INST_1_n_33,USER_DESIGN_INST_1_n_34,USER_DESIGN_INST_1_n_35}));
OBUF \VGA_B_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[0]));
OBUF \VGA_B_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[1]));
OBUF \VGA_B_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[2]));
OBUF \VGA_B_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[3]));
OBUF \VGA_G_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[0]));
OBUF \VGA_G_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[1]));
OBUF \VGA_G_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[2]));
OBUF \VGA_G_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[3]));
OBUF \VGA_R_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[0]));
OBUF \VGA_R_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[1]));
OBUF \VGA_R_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[2]));
OBUF \VGA_R_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[3]));
OBUF VSYNCH_OBUF_inst
(.I(VSYNCH_OBUF),
.O(VSYNCH));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* XILINX_LEGACY_PRIM = "IBUFG" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_buf
(.I(CLK_IN),
.O(CLKIN));
(* XILINX_LEGACY_PRIM = "DCM_SP" *)
(* XILINX_TRANSFORM_PINMAP = "STATUS[7]:DO[7] STATUS[6]:DO[6] STATUS[5]:DO[5] STATUS[4]:DO[4] STATUS[3]:DO[3] STATUS[2]:DO[2] STATUS[1]:DO[1] STATUS[0]:DO[0] CLKIN:CLKIN1 CLKFX:CLKOUT0 CLKFX180:CLKOUT0B CLK2X:CLKOUT1 CLK2X180:CLKOUT1B CLK90:CLKOUT2 CLK270:CLKOUT2B CLKDV:CLKOUT4 CLK0:CLKFBOUT CLK180:CLKFBOUTB CLKFB:CLKFBIN" *)
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(8.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(2.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(4),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(8),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(90.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(8),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(16),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_PSINCDEC_INVERTED(1'b1),
.IS_RST_INVERTED(1'b1),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
dcm_sp_inst
(.CLKFBIN(CLKFB),
.CLKFBOUT(clk0),
.CLKFBOUTB(NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(CLKIN),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED),
.CLKOUT0B(NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(clkdv),
.CLKOUT5(NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_dcm_sp_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_dcm_sp_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked_internal),
.PSCLK(1'b0),
.PSDONE(NLW_dcm_sp_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(RST_IBUF));
rmii_ethernet ethernet_inst_1
(.D(NLW_ethernet_inst_1_D_UNCONNECTED[1:0]),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.RXDV_IBUF(NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED),
.RXER_IBUF(NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED),
.TXD_OBUF(TXD_OBUF),
.TXEN_OBUF(TXEN_OBUF));
pwm_audio pwm_audio_inst_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.JC_IBUF(JC_IBUF));
endmodule
module CHARSVGA
(HSYNCH,
VSYNCH,
VGA_B_OBUF,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output HSYNCH;
output VSYNCH;
output [0:0]VGA_B_OBUF;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire [12:1]AOUT;
wire BLANK;
wire BLANK_DEL;
wire BLANK_DEL_DEL;
wire [3:0]DOUT;
wire ETH_CLK_OBUF;
wire HSYNCH;
wire HSYNCH_DEL;
wire INTERNAL_RST_reg;
wire [2:0]PIXCOL_DEL;
wire \PIXCOL_DEL_DEL_reg_n_0_[0] ;
wire \PIXCOL_DEL_DEL_reg_n_0_[1] ;
wire \PIXCOL_DEL_DEL_reg_n_0_[2] ;
wire [7:0]PIXELS_reg__0;
wire TIMEING1_n_0;
wire TIMEING1_n_1;
wire TIMEING1_n_15;
wire TIMEING1_n_16;
wire TIMEING1_n_17;
wire TIMEING1_n_18;
wire TIMEING1_n_19;
wire TIMEING1_n_2;
wire TIMEING1_n_20;
wire [0:0]VGA_B_OBUF;
wire \VGA_R_OBUF[3]_inst_i_2_n_0 ;
wire \VGA_R_OBUF[3]_inst_i_3_n_0 ;
wire VSYNCH;
wire VSYNCH_DEL;
wire [2:0]sel;
wire NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED;
wire NLW_PIXELS_reg_REGCEB_UNCONNECTED;
wire [15:8]NLW_PIXELS_reg_DOADO_UNCONNECTED;
wire [15:0]NLW_PIXELS_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_PIXELS_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_PIXELS_reg_DOPBDOP_UNCONNECTED;
FDRE BLANK_DEL_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BLANK_DEL),
.Q(BLANK_DEL_DEL),
.R(1'b0));
FDRE BLANK_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BLANK),
.Q(BLANK_DEL),
.R(1'b0));
BRAM BRAM_INST_1
(.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
.DOBDO(DOUT),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.pwropt(BLANK));
FDRE HSYNCH_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_19),
.Q(HSYNCH_DEL),
.R(1'b0));
FDRE HSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HSYNCH_DEL),
.Q(HSYNCH),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[0]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[1]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[2]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_0),
.Q(PIXCOL_DEL[0]),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_1),
.Q(PIXCOL_DEL[1]),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_2),
.Q(PIXCOL_DEL[2]),
.R(1'b0));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "16384" *)
(* RTL_RAM_NAME = "PIXELS" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
.INIT_09(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
.INIT_0A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
.INIT_0B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
.INIT_0C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
.INIT_0D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
.INIT_0E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
.INIT_0F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
.INIT_10(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
.INIT_11(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
.INIT_12(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
.INIT_13(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
.INIT_14(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
.INIT_15(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
.INIT_16(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
.INIT_17(256'h00FF000000000000000000000022140800181010101010180000402010080402),
.INIT_18(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
.INIT_19(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
.INIT_1A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
.INIT_1B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
.INIT_1C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
.INIT_1D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
.INIT_1E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
.INIT_1F(256'h000000000000000000000060920C000000040808100808040008080808080808),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
.INIT_29(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
.INIT_2A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
.INIT_2B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
.INIT_2C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
.INIT_2D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
.INIT_2E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
.INIT_2F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
.INIT_30(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
.INIT_31(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
.INIT_32(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
.INIT_33(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
.INIT_34(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
.INIT_35(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
.INIT_36(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
.INIT_37(256'h00FF000000000000000000000022140800181010101010180000402010080402),
.INIT_38(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
.INIT_39(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
.INIT_3A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
.INIT_3B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
.INIT_3C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
.INIT_3D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
.INIT_3E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
.INIT_3F(256'h000000000000000000000060920C000000040808100808040008080808080808),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.IS_ENARDEN_INVERTED(1'b1),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(0))
PIXELS_reg
(.ADDRARDADDR({DOUT,DOUT,sel,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO({NLW_PIXELS_reg_DOADO_UNCONNECTED[15:8],PIXELS_reg__0}),
.DOBDO(NLW_PIXELS_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_PIXELS_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_PIXELS_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(BLANK_DEL),
.ENBWREN(1'b0),
.REGCEAREGCE(NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_PIXELS_reg_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
FDRE \PIXROW_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_16),
.Q(sel[0]),
.R(1'b0));
FDRE \PIXROW_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_17),
.Q(sel[1]),
.R(1'b0));
FDRE \PIXROW_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_18),
.Q(sel[2]),
.R(1'b0));
VIDEO_TIME_GEN TIMEING1
(.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
.BLANK(BLANK),
.D(TIMEING1_n_18),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.HSYNCH_DEL_reg(TIMEING1_n_19),
.INTERNAL_RST_reg(INTERNAL_RST_reg),
.\PIXCOL_DEL_reg[0] (TIMEING1_n_0),
.\PIXCOL_DEL_reg[1] (TIMEING1_n_1),
.\PIXCOL_DEL_reg[2] (TIMEING1_n_2),
.\PIXROW_DEL_reg[0] (TIMEING1_n_16),
.\PIXROW_DEL_reg[1] (TIMEING1_n_17),
.VSYNCH_DEL_reg(TIMEING1_n_20));
LUT4 #(
.INIT(16'h00E2))
\VGA_R_OBUF[3]_inst_i_1
(.I0(\VGA_R_OBUF[3]_inst_i_2_n_0 ),
.I1(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
.I2(\VGA_R_OBUF[3]_inst_i_3_n_0 ),
.I3(BLANK_DEL_DEL),
.O(VGA_B_OBUF));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\VGA_R_OBUF[3]_inst_i_2
(.I0(PIXELS_reg__0[3]),
.I1(PIXELS_reg__0[2]),
.I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.I3(PIXELS_reg__0[1]),
.I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.I5(PIXELS_reg__0[0]),
.O(\VGA_R_OBUF[3]_inst_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\VGA_R_OBUF[3]_inst_i_3
(.I0(PIXELS_reg__0[7]),
.I1(PIXELS_reg__0[6]),
.I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.I3(PIXELS_reg__0[5]),
.I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.I5(PIXELS_reg__0[4]),
.O(\VGA_R_OBUF[3]_inst_i_3_n_0 ));
FDRE VSYNCH_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_20),
.Q(VSYNCH_DEL),
.R(1'b0));
FDRE VSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VSYNCH_DEL),
.Q(VSYNCH),
.R(1'b0));
endmodule
module I2C
(SDA_TRI,
SCL_TRI,
ETH_CLK_OBUF,
SCL_IBUF,
INTERNAL_RST_reg,
SDA_IBUF);
output SDA_TRI;
output SCL_TRI;
input ETH_CLK_OBUF;
input SCL_IBUF;
input INTERNAL_RST_reg;
input SDA_IBUF;
wire BIT_i_1_n_0;
wire BIT_i_2_n_0;
wire BIT_i_3_n_0;
wire BIT_reg_n_0;
wire [2:0]COUNT;
wire \COUNT[0]_i_1__0_n_0 ;
wire \COUNT[1]_i_1__0_n_0 ;
wire \COUNT[2]_i_1_n_0 ;
wire \COUNT[2]_i_2_n_0 ;
wire ETH_CLK_OBUF;
wire [3:0]GET_BIT_RETURN;
wire \GET_BIT_RETURN[0]_i_1_n_0 ;
wire \GET_BIT_RETURN[3]_i_1_n_0 ;
wire INTERNAL_RST_reg;
wire SCL_IBUF;
wire SCL_I_D;
wire SCL_I_SYNCH;
wire SCL_O_i_1_n_0;
wire SCL_O_i_2_n_0;
wire SCL_O_i_3_n_0;
wire SCL_O_i_4_n_0;
wire SCL_TRI;
wire SDA_IBUF;
wire SDA_I_D;
wire SDA_I_SYNCH;
wire SDA_O_i_1_n_0;
wire SDA_O_i_2_n_0;
wire SDA_TRI;
wire [3:0]SEND_BIT_RETURN;
wire \SEND_BIT_RETURN[0]_i_1_n_0 ;
wire \SEND_BIT_RETURN[3]_i_1_n_0 ;
wire STARTED;
wire STARTED_i_1_n_0;
wire STARTED_i_2_n_0;
wire \STATE[0]_i_2_n_0 ;
wire \STATE[0]_i_3_n_0 ;
wire \STATE[1]_i_1_n_0 ;
wire \STATE[1]_i_2_n_0 ;
wire \STATE[1]_i_3_n_0 ;
wire \STATE[1]_i_4_n_0 ;
wire \STATE[2]_i_1_n_0 ;
wire \STATE[3]_i_2_n_0 ;
wire \STATE[3]_i_3_n_0 ;
wire \STATE[4]_i_1_n_0 ;
wire \STATE[4]_i_2_n_0 ;
wire \STATE[4]_i_3_n_0 ;
wire \STATE[4]_i_4_n_0 ;
wire \STATE[4]_i_5_n_0 ;
wire \STATE[4]_i_6_n_0 ;
wire \STATE_reg[0]_i_1_n_0 ;
wire \STATE_reg[3]_i_1_n_0 ;
wire \STATE_reg_n_0_[0] ;
wire \STATE_reg_n_0_[1] ;
wire \STATE_reg_n_0_[2] ;
wire \STATE_reg_n_0_[3] ;
wire \STATE_reg_n_0_[4] ;
wire S_I2C_IN_ACK_i_1_n_0;
wire S_I2C_IN_ACK_reg_n_0;
wire S_I2C_OUT_STB_i_1_n_0;
wire S_I2C_OUT_STB_reg_n_0;
wire \TIMER[0]_i_1_n_0 ;
wire \TIMER[0]_i_2_n_0 ;
wire \TIMER[0]_i_3_n_0 ;
wire \TIMER[10]_i_1_n_0 ;
wire \TIMER[10]_i_2_n_0 ;
wire \TIMER[10]_i_3_n_0 ;
wire \TIMER[10]_i_5_n_0 ;
wire \TIMER[10]_i_6_n_0 ;
wire \TIMER[10]_i_7_n_0 ;
wire \TIMER[11]_i_1_n_0 ;
wire \TIMER[1]_i_1__2_n_0 ;
wire \TIMER[2]_i_1_n_0 ;
wire \TIMER[3]_i_1__2_n_0 ;
wire \TIMER[4]_i_1__2_n_0 ;
wire \TIMER[4]_i_3_n_0 ;
wire \TIMER[4]_i_4_n_0 ;
wire \TIMER[4]_i_5_n_0 ;
wire \TIMER[4]_i_6_n_0 ;
wire \TIMER[5]_i_1__2_n_0 ;
wire \TIMER[5]_i_3_n_0 ;
wire \TIMER[5]_i_4_n_0 ;
wire \TIMER[5]_i_5_n_0 ;
wire \TIMER[5]_i_6_n_0 ;
wire \TIMER[6]_i_1_n_0 ;
wire \TIMER[7]_i_1_n_0 ;
wire \TIMER[8]_i_1_n_0 ;
wire \TIMER[9]_i_1__2_n_0 ;
wire \TIMER_reg[10]_i_4_n_5 ;
wire \TIMER_reg[10]_i_4_n_6 ;
wire \TIMER_reg[10]_i_4_n_7 ;
wire \TIMER_reg[4]_i_2_n_0 ;
wire \TIMER_reg[4]_i_2_n_4 ;
wire \TIMER_reg[4]_i_2_n_5 ;
wire \TIMER_reg[4]_i_2_n_6 ;
wire \TIMER_reg[4]_i_2_n_7 ;
wire \TIMER_reg[5]_i_2_n_0 ;
wire \TIMER_reg[5]_i_2_n_4 ;
wire \TIMER_reg[5]_i_2_n_5 ;
wire \TIMER_reg[5]_i_2_n_6 ;
wire \TIMER_reg[5]_i_2_n_7 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[10] ;
wire \TIMER_reg_n_0_[11] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire g0_b0_n_0;
wire [3:0]\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hFFF0FA3300000A00))
BIT_i_1
(.I0(SDA_I_SYNCH),
.I1(BIT_i_2_n_0),
.I2(BIT_i_3_n_0),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(BIT_reg_n_0),
.O(BIT_i_1_n_0));
LUT3 #(
.INIT(8'h40))
BIT_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[3] ),
.O(BIT_i_2_n_0));
LUT3 #(
.INIT(8'hEF))
BIT_i_3
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[1] ),
.O(BIT_i_3_n_0));
FDRE BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BIT_i_1_n_0),
.Q(BIT_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h1FF0))
\COUNT[0]_i_1__0
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\COUNT[2]_i_2_n_0 ),
.I3(COUNT[0]),
.O(\COUNT[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hF1FF1F00))
\COUNT[1]_i_1__0
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(COUNT[0]),
.I3(\COUNT[2]_i_2_n_0 ),
.I4(COUNT[1]),
.O(\COUNT[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFF1FFFF111F0000))
\COUNT[2]_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(COUNT[0]),
.I3(COUNT[1]),
.I4(\COUNT[2]_i_2_n_0 ),
.I5(COUNT[2]),
.O(\COUNT[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00100401))
\COUNT[2]_i_2
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.O(\COUNT[2]_i_2_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[0]_i_1__0_n_0 ),
.Q(COUNT[0]),
.R(1'b0));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[1]_i_1__0_n_0 ),
.Q(COUNT[1]),
.R(1'b0));
FDRE \COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[2]_i_1_n_0 ),
.Q(COUNT[2]),
.R(1'b0));
LUT6 #(
.INIT(64'hFBFFFFFF00000010))
\GET_BIT_RETURN[0]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(GET_BIT_RETURN[0]),
.O(\GET_BIT_RETURN[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF04000000))
\GET_BIT_RETURN[3]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(GET_BIT_RETURN[3]),
.O(\GET_BIT_RETURN[3]_i_1_n_0 ));
FDRE \GET_BIT_RETURN_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\GET_BIT_RETURN[0]_i_1_n_0 ),
.Q(GET_BIT_RETURN[0]),
.R(1'b0));
FDRE \GET_BIT_RETURN_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\GET_BIT_RETURN[3]_i_1_n_0 ),
.Q(GET_BIT_RETURN[3]),
.R(1'b0));
FDRE SCL_I_D_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_IBUF),
.Q(SCL_I_D),
.R(1'b0));
FDRE SCL_I_SYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_I_D),
.Q(SCL_I_SYNCH),
.R(1'b0));
LUT6 #(
.INIT(64'h403FFFFF403F0000))
SCL_O_i_1
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(SCL_O_i_2_n_0),
.I5(SCL_TRI),
.O(SCL_O_i_1_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF01000000))
SCL_O_i_2
(.I0(\TIMER[0]_i_2_n_0 ),
.I1(SCL_O_i_3_n_0),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(SCL_O_i_4_n_0),
.O(SCL_O_i_2_n_0));
LUT2 #(
.INIT(4'h1))
SCL_O_i_3
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.O(SCL_O_i_3_n_0));
LUT6 #(
.INIT(64'h3C0C0C2C3C000000))
SCL_O_i_4
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\STATE_reg_n_0_[3] ),
.I5(\STATE_reg_n_0_[4] ),
.O(SCL_O_i_4_n_0));
FDSE SCL_O_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_O_i_1_n_0),
.Q(SCL_TRI),
.S(INTERNAL_RST_reg));
FDRE SDA_I_D_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_IBUF),
.Q(SDA_I_D),
.R(1'b0));
FDRE SDA_I_SYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_I_D),
.Q(SDA_I_SYNCH),
.R(1'b0));
LUT6 #(
.INIT(64'hADA5FFFFADA50000))
SDA_O_i_1
(.I0(\STATE_reg_n_0_[3] ),
.I1(BIT_reg_n_0),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(SDA_O_i_2_n_0),
.I5(SDA_TRI),
.O(SDA_O_i_1_n_0));
LUT6 #(
.INIT(64'h9098803080988030))
SDA_O_i_2
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[4] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[3] ),
.I5(\TIMER[10]_i_3_n_0 ),
.O(SDA_O_i_2_n_0));
FDSE SDA_O_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_O_i_1_n_0),
.Q(SDA_TRI),
.S(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFBF01000000))
\SEND_BIT_RETURN[0]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SEND_BIT_RETURN[0]),
.O(\SEND_BIT_RETURN[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEFFFFFF00000040))
\SEND_BIT_RETURN[3]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SEND_BIT_RETURN[3]),
.O(\SEND_BIT_RETURN[3]_i_1_n_0 ));
FDRE \SEND_BIT_RETURN_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\SEND_BIT_RETURN[0]_i_1_n_0 ),
.Q(SEND_BIT_RETURN[0]),
.R(1'b0));
FDRE \SEND_BIT_RETURN_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\SEND_BIT_RETURN[3]_i_1_n_0 ),
.Q(SEND_BIT_RETURN[3]),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFDFFFD08000000))
STARTED_i_1
(.I0(STARTED_i_2_n_0),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\TIMER[10]_i_3_n_0 ),
.I5(STARTED),
.O(STARTED_i_1_n_0));
LUT4 #(
.INIT(16'hEAAB))
STARTED_i_2
(.I0(\STATE_reg_n_0_[3] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[0] ),
.O(STARTED_i_2_n_0));
FDRE STARTED_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(STARTED_i_1_n_0),
.Q(STARTED),
.R(1'b0));
LUT5 #(
.INIT(32'hB0FC3CCF))
\STATE[0]_i_2
(.I0(SEND_BIT_RETURN[0]),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[2] ),
.O(\STATE[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h040004005F5F5A5F))
\STATE[0]_i_3
(.I0(\STATE_reg_n_0_[3] ),
.I1(STARTED),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(GET_BIT_RETURN[0]),
.I5(\STATE_reg_n_0_[0] ),
.O(\STATE[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h2))
\STATE[1]_i_1
(.I0(\STATE[1]_i_2_n_0 ),
.I1(\STATE[1]_i_3_n_0 ),
.O(\STATE[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h12781258FFFFFFFF))
\STATE[1]_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(STARTED),
.I5(\STATE_reg_n_0_[4] ),
.O(\STATE[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0005010555155055))
\STATE[1]_i_3
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE[1]_i_4_n_0 ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[1] ),
.I5(\STATE_reg_n_0_[2] ),
.O(\STATE[1]_i_3_n_0 ));
LUT3 #(
.INIT(8'h01))
\STATE[1]_i_4
(.I0(COUNT[2]),
.I1(COUNT[1]),
.I2(COUNT[0]),
.O(\STATE[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h406EB828406E3828))
\STATE[2]_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.I5(SEND_BIT_RETURN[0]),
.O(\STATE[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8F00F5F0))
\STATE[3]_i_2
(.I0(\STATE_reg_n_0_[2] ),
.I1(SEND_BIT_RETURN[3]),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[0] ),
.O(\STATE[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0F0F0200))
\STATE[3]_i_3
(.I0(GET_BIT_RETURN[3]),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[3] ),
.O(\STATE[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF4F4F0FF))
\STATE[4]_i_1
(.I0(\STATE[4]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE[4]_i_4_n_0 ),
.I3(\STATE[4]_i_5_n_0 ),
.I4(\STATE_reg_n_0_[1] ),
.I5(\STATE[4]_i_6_n_0 ),
.O(\STATE[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h1301FD80))
\STATE[4]_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[2] ),
.O(\STATE[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hEEEEEE0FEE00EE0F))
\STATE[4]_i_3
(.I0(\TIMER_reg_n_0_[0] ),
.I1(\TIMER[0]_i_2_n_0 ),
.I2(S_I2C_OUT_STB_reg_n_0),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.I5(\STATE_reg_n_0_[2] ),
.O(\STATE[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'h80AA8000))
\STATE[4]_i_4
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[4] ),
.O(\STATE[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFC0C0CDCFCFCDCDC))
\STATE[4]_i_5
(.I0(S_I2C_IN_ACK_reg_n_0),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SCL_I_SYNCH),
.O(\STATE[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h004075BB))
\STATE[4]_i_6
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(SCL_I_SYNCH),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.O(\STATE[4]_i_6_n_0 ));
FDRE \STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE_reg[0]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
MUXF7 \STATE_reg[0]_i_1
(.I0(\STATE[0]_i_2_n_0 ),
.I1(\STATE[0]_i_3_n_0 ),
.O(\STATE_reg[0]_i_1_n_0 ),
.S(\STATE_reg_n_0_[4] ));
FDRE \STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[1]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[2]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE_reg[3]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
MUXF7 \STATE_reg[3]_i_1
(.I0(\STATE[3]_i_2_n_0 ),
.I1(\STATE[3]_i_3_n_0 ),
.O(\STATE_reg[3]_i_1_n_0 ),
.S(\STATE_reg_n_0_[4] ));
FDRE \STATE_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[4]_i_2_n_0 ),
.Q(\STATE_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFEFFFF00010000))
S_I2C_IN_ACK_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(S_I2C_IN_ACK_reg_n_0),
.O(S_I2C_IN_ACK_i_1_n_0));
FDRE S_I2C_IN_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_I2C_IN_ACK_i_1_n_0),
.Q(S_I2C_IN_ACK_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFDFFFF00020000))
S_I2C_OUT_STB_i_1
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(S_I2C_OUT_STB_reg_n_0),
.O(S_I2C_OUT_STB_i_1_n_0));
FDRE S_I2C_OUT_STB_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_I2C_OUT_STB_i_1_n_0),
.Q(S_I2C_OUT_STB_reg_n_0),
.R(INTERNAL_RST_reg));
LUT5 #(
.INIT(32'h00FFA800))
\TIMER[0]_i_1
(.I0(\TIMER[0]_i_2_n_0 ),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(g0_b0_n_0),
.I4(\TIMER_reg_n_0_[0] ),
.O(\TIMER[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\TIMER[0]_i_2
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[11] ),
.I2(\TIMER_reg_n_0_[7] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[1] ),
.I5(\TIMER[0]_i_3_n_0 ),
.O(\TIMER[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\TIMER[0]_i_3
(.I0(\TIMER_reg_n_0_[6] ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[9] ),
.I3(\TIMER_reg_n_0_[10] ),
.I4(\TIMER_reg_n_0_[5] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(\TIMER[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\TIMER[10]_i_1
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(g0_b0_n_0),
.O(\TIMER[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[10]_i_2
(.I0(\TIMER_reg[10]_i_4_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[10]_i_2_n_0 ));
LUT2 #(
.INIT(4'h1))
\TIMER[10]_i_3
(.I0(\TIMER_reg_n_0_[0] ),
.I1(\TIMER[0]_i_2_n_0 ),
.O(\TIMER[10]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_5
(.I0(\TIMER_reg_n_0_[11] ),
.O(\TIMER[10]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_6
(.I0(\TIMER_reg_n_0_[10] ),
.O(\TIMER[10]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_7
(.I0(\TIMER_reg_n_0_[9] ),
.O(\TIMER[10]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[11]_i_1
(.I0(\TIMER_reg[10]_i_4_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[1]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[2]_i_1
(.I0(\TIMER_reg[4]_i_2_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[3]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[4]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_4 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[4]_i_1__2_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_3
(.I0(\TIMER_reg_n_0_[4] ),
.O(\TIMER[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_4
(.I0(\TIMER_reg_n_0_[3] ),
.O(\TIMER[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_5
(.I0(\TIMER_reg_n_0_[2] ),
.O(\TIMER[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_6
(.I0(\TIMER_reg_n_0_[1] ),
.O(\TIMER[4]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[5]_i_1__2
(.I0(\TIMER_reg[5]_i_2_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[5]_i_1__2_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_3
(.I0(\TIMER_reg_n_0_[8] ),
.O(\TIMER[5]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_4
(.I0(\TIMER_reg_n_0_[7] ),
.O(\TIMER[5]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_5
(.I0(\TIMER_reg_n_0_[6] ),
.O(\TIMER[5]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_6
(.I0(\TIMER_reg_n_0_[5] ),
.O(\TIMER[5]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[6]_i_1
(.I0(\TIMER_reg[5]_i_2_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAB))
\TIMER[7]_i_1
(.I0(\TIMER_reg[5]_i_2_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[8]_i_1
(.I0(\TIMER_reg[5]_i_2_n_4 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[9]_i_1__2
(.I0(\TIMER_reg[10]_i_4_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[9]_i_1__2_n_0 ));
FDRE \TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TIMER[0]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE \TIMER_reg[10]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[10]_i_2_n_0 ),
.Q(\TIMER_reg_n_0_[10] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[10]_i_4
(.CI(\TIMER_reg[5]_i_2_n_0 ),
.CO(\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\TIMER_reg_n_0_[10] ,\TIMER_reg_n_0_[9] }),
.O({\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED [3],\TIMER_reg[10]_i_4_n_5 ,\TIMER_reg[10]_i_4_n_6 ,\TIMER_reg[10]_i_4_n_7 }),
.S({1'b0,\TIMER[10]_i_5_n_0 ,\TIMER[10]_i_6_n_0 ,\TIMER[10]_i_7_n_0 }));
FDSE \TIMER_reg[11]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[11]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[11] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[1]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[1] ),
.R(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[2]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[2] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[3]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[3] ),
.R(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[4]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[4] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[4]_i_2
(.CI(1'b0),
.CO({\TIMER_reg[4]_i_2_n_0 ,\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\TIMER_reg_n_0_[0] ),
.DI({\TIMER_reg_n_0_[4] ,\TIMER_reg_n_0_[3] ,\TIMER_reg_n_0_[2] ,\TIMER_reg_n_0_[1] }),
.O({\TIMER_reg[4]_i_2_n_4 ,\TIMER_reg[4]_i_2_n_5 ,\TIMER_reg[4]_i_2_n_6 ,\TIMER_reg[4]_i_2_n_7 }),
.S({\TIMER[4]_i_3_n_0 ,\TIMER[4]_i_4_n_0 ,\TIMER[4]_i_5_n_0 ,\TIMER[4]_i_6_n_0 }));
FDRE \TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[5]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[5] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[5]_i_2
(.CI(\TIMER_reg[4]_i_2_n_0 ),
.CO({\TIMER_reg[5]_i_2_n_0 ,\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\TIMER_reg_n_0_[8] ,\TIMER_reg_n_0_[7] ,\TIMER_reg_n_0_[6] ,\TIMER_reg_n_0_[5] }),
.O({\TIMER_reg[5]_i_2_n_4 ,\TIMER_reg[5]_i_2_n_5 ,\TIMER_reg[5]_i_2_n_6 ,\TIMER_reg[5]_i_2_n_7 }),
.S({\TIMER[5]_i_3_n_0 ,\TIMER[5]_i_4_n_0 ,\TIMER[5]_i_5_n_0 ,\TIMER[5]_i_6_n_0 }));
FDSE \TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[6]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[6] ),
.S(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[7]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[7] ),
.S(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[8]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[8] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[9]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[9] ),
.R(\TIMER[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'h1DD5A001))
g0_b0
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.O(g0_b0_n_0));
endmodule
module IOBUF_UNIQ_BASE_
(IO,
O,
I,
T);
inout IO;
output O;
input I;
input T;
wire I;
wire IO;
wire O;
wire T;
IBUF IBUF
(.I(IO),
.O(O));
OBUFT OBUFT
(.I(I),
.O(IO),
.T(T));
endmodule
(* ORIG_REF_NAME = "IOBUF" *)
module IOBUF_HD3
(IO,
O,
I,
T);
inout IO;
output O;
input I;
input T;
wire I;
wire IO;
wire O;
wire T;
IBUF #(
.IOSTANDARD("DEFAULT"))
IBUF
(.I(IO),
.O(O));
OBUFT #(
.IOSTANDARD("DEFAULT"))
OBUFT
(.I(I),
.O(IO),
.T(T));
endmodule
module PWM
(LED_R_PWM_OBUF,
E,
Q,
ETH_CLK_OBUF);
output LED_R_PWM_OBUF;
input [0:0]E;
input [7:0]Q;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__1_n_0 ;
wire \COUNT[1]_i_1__1_n_0 ;
wire \COUNT[1]_i_2_n_0 ;
wire \COUNT[2]_i_1__0_n_0 ;
wire \COUNT[3]_i_1_n_0 ;
wire \COUNT[3]_i_2_n_0 ;
wire \COUNT[4]_i_1_n_0 ;
wire \COUNT[5]_i_1_n_0 ;
wire \COUNT[6]_i_1_n_0 ;
wire \COUNT[7]_i_1_n_0 ;
wire \COUNT[7]_i_2_n_0 ;
wire \COUNT[7]_i_3_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire [0:0]E;
wire ETH_CLK_OBUF;
wire LED_R_PWM_OBUF;
wire OUT_BIT_i_10_n_0;
wire OUT_BIT_i_1_n_0;
wire OUT_BIT_i_3_n_0;
wire OUT_BIT_i_4_n_0;
wire OUT_BIT_i_5_n_0;
wire OUT_BIT_i_6_n_0;
wire OUT_BIT_i_7_n_0;
wire OUT_BIT_i_8_n_0;
wire OUT_BIT_i_9_n_0;
wire [7:0]PWM_VAL;
wire [7:0]Q;
wire [9:0]TIMER;
wire \TIMER[4]_i_2_n_0 ;
wire \TIMER[9]_i_2_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__1
(.I0(\COUNT[7]_i_3_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__1
(.I0(\COUNT[1]_i_2_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__1_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2_n_0 ),
.O(\COUNT[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2_n_0 ),
.O(\COUNT[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1
(.I0(\COUNT[7]_i_3_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2_n_0 ),
.O(\COUNT[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[0]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[1]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[2]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[3]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[4]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[5]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[6]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[7]_i_2_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1
(.I0(p_0_in),
.O(OUT_BIT_i_1_n_0));
LUT4 #(
.INIT(16'h9009))
OUT_BIT_i_10
(.I0(PWM_VAL[1]),
.I1(\COUNT_reg_n_0_[1] ),
.I2(PWM_VAL[0]),
.I3(\COUNT_reg_n_0_[0] ),
.O(OUT_BIT_i_10_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_3
(.I0(\COUNT_reg_n_0_[7] ),
.I1(PWM_VAL[6]),
.I2(\COUNT_reg_n_0_[6] ),
.I3(PWM_VAL[7]),
.O(OUT_BIT_i_3_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_4
(.I0(\COUNT_reg_n_0_[5] ),
.I1(PWM_VAL[4]),
.I2(\COUNT_reg_n_0_[4] ),
.I3(PWM_VAL[5]),
.O(OUT_BIT_i_4_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_5
(.I0(\COUNT_reg_n_0_[3] ),
.I1(PWM_VAL[2]),
.I2(\COUNT_reg_n_0_[2] ),
.I3(PWM_VAL[3]),
.O(OUT_BIT_i_5_n_0));
LUT4 #(
.INIT(16'h22B2))
OUT_BIT_i_6
(.I0(\COUNT_reg_n_0_[1] ),
.I1(PWM_VAL[1]),
.I2(\COUNT_reg_n_0_[0] ),
.I3(PWM_VAL[0]),
.O(OUT_BIT_i_6_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_7
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(PWM_VAL[6]),
.I3(PWM_VAL[7]),
.O(OUT_BIT_i_7_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_8
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(PWM_VAL[4]),
.I3(PWM_VAL[5]),
.O(OUT_BIT_i_8_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_9
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(PWM_VAL[2]),
.I3(PWM_VAL[3]),
.O(OUT_BIT_i_9_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1_n_0),
.Q(LED_R_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3_n_0,OUT_BIT_i_4_n_0,OUT_BIT_i_5_n_0,OUT_BIT_i_6_n_0}),
.O(NLW_OUT_BIT_reg_i_2_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7_n_0,OUT_BIT_i_8_n_0,OUT_BIT_i_9_n_0,OUT_BIT_i_10_n_0}));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[0]),
.Q(PWM_VAL[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[1]),
.Q(PWM_VAL[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[2]),
.Q(PWM_VAL[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[3]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[3]),
.Q(PWM_VAL[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[4]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[4]),
.Q(PWM_VAL[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[5]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[5]),
.Q(PWM_VAL[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[6]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[6]),
.Q(PWM_VAL[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[7]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[7]),
.Q(PWM_VAL[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__0
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__0
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1
(.I0(\TIMER[4]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "PWM" *)
module PWM_0
(LED_G_PWM_OBUF,
E,
Q,
ETH_CLK_OBUF);
output LED_G_PWM_OBUF;
input [0:0]E;
input [7:0]Q;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__2_n_0 ;
wire \COUNT[1]_i_1__2_n_0 ;
wire \COUNT[1]_i_2__0_n_0 ;
wire \COUNT[2]_i_1__1_n_0 ;
wire \COUNT[3]_i_1__0_n_0 ;
wire \COUNT[3]_i_2__0_n_0 ;
wire \COUNT[4]_i_1__0_n_0 ;
wire \COUNT[5]_i_1__0_n_0 ;
wire \COUNT[6]_i_1__0_n_0 ;
wire \COUNT[7]_i_1__0_n_0 ;
wire \COUNT[7]_i_2__0_n_0 ;
wire \COUNT[7]_i_3__0_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire [0:0]E;
wire ETH_CLK_OBUF;
wire LED_G_PWM_OBUF;
wire OUT_BIT_i_10__0_n_0;
wire OUT_BIT_i_1__0_n_0;
wire OUT_BIT_i_3__0_n_0;
wire OUT_BIT_i_4__0_n_0;
wire OUT_BIT_i_5__0_n_0;
wire OUT_BIT_i_6__0_n_0;
wire OUT_BIT_i_7__0_n_0;
wire OUT_BIT_i_8__0_n_0;
wire OUT_BIT_i_9__0_n_0;
wire [7:0]PWM_VAL;
wire [7:0]Q;
wire [9:0]TIMER;
wire \TIMER[4]_i_2__0_n_0 ;
wire \TIMER[9]_i_2__0_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__2
(.I0(\COUNT[7]_i_3__0_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__2
(.I0(\COUNT[1]_i_2__0_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__2_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2__0
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2__0_n_0 ),
.O(\COUNT[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2__0_n_0 ),
.O(\COUNT[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3__0_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1__0
(.I0(\COUNT[7]_i_3__0_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3__0_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1__0
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2__0_n_0 ),
.O(\COUNT[7]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3__0_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[0]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[1]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[2]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[3]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[4]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[5]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[6]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[7]_i_2__0_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'h9009))
OUT_BIT_i_10__0
(.I0(PWM_VAL[1]),
.I1(\COUNT_reg_n_0_[1] ),
.I2(PWM_VAL[0]),
.I3(\COUNT_reg_n_0_[0] ),
.O(OUT_BIT_i_10__0_n_0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1__0
(.I0(p_0_in),
.O(OUT_BIT_i_1__0_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_3__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(PWM_VAL[6]),
.I2(\COUNT_reg_n_0_[6] ),
.I3(PWM_VAL[7]),
.O(OUT_BIT_i_3__0_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_4__0
(.I0(\COUNT_reg_n_0_[5] ),
.I1(PWM_VAL[4]),
.I2(\COUNT_reg_n_0_[4] ),
.I3(PWM_VAL[5]),
.O(OUT_BIT_i_4__0_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_5__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(PWM_VAL[2]),
.I2(\COUNT_reg_n_0_[2] ),
.I3(PWM_VAL[3]),
.O(OUT_BIT_i_5__0_n_0));
LUT4 #(
.INIT(16'h22B2))
OUT_BIT_i_6__0
(.I0(\COUNT_reg_n_0_[1] ),
.I1(PWM_VAL[1]),
.I2(\COUNT_reg_n_0_[0] ),
.I3(PWM_VAL[0]),
.O(OUT_BIT_i_6__0_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_7__0
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(PWM_VAL[6]),
.I3(PWM_VAL[7]),
.O(OUT_BIT_i_7__0_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_8__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(PWM_VAL[4]),
.I3(PWM_VAL[5]),
.O(OUT_BIT_i_8__0_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_9__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(PWM_VAL[2]),
.I3(PWM_VAL[3]),
.O(OUT_BIT_i_9__0_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1__0_n_0),
.Q(LED_G_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2__0
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3__0_n_0,OUT_BIT_i_4__0_n_0,OUT_BIT_i_5__0_n_0,OUT_BIT_i_6__0_n_0}),
.O(NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7__0_n_0,OUT_BIT_i_8__0_n_0,OUT_BIT_i_9__0_n_0,OUT_BIT_i_10__0_n_0}));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[0]),
.Q(PWM_VAL[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[1]),
.Q(PWM_VAL[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[2]),
.Q(PWM_VAL[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[3]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[3]),
.Q(PWM_VAL[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[4]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[4]),
.Q(PWM_VAL[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[5]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[5]),
.Q(PWM_VAL[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[6]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[6]),
.Q(PWM_VAL[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[7]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[7]),
.Q(PWM_VAL[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__1
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1__0
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__1
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1__0
(.I0(\TIMER[4]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1__0
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2__0_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2__0
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1__0
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1__0
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2__0
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "PWM" *)
module PWM_1
(LED_B_PWM_OBUF,
E,
Q,
ETH_CLK_OBUF);
output LED_B_PWM_OBUF;
input [0:0]E;
input [7:0]Q;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__3_n_0 ;
wire \COUNT[1]_i_1__3_n_0 ;
wire \COUNT[1]_i_2__1_n_0 ;
wire \COUNT[2]_i_1__2_n_0 ;
wire \COUNT[3]_i_1__1_n_0 ;
wire \COUNT[3]_i_2__1_n_0 ;
wire \COUNT[4]_i_1__1_n_0 ;
wire \COUNT[5]_i_1__1_n_0 ;
wire \COUNT[6]_i_1__1_n_0 ;
wire \COUNT[7]_i_1__1_n_0 ;
wire \COUNT[7]_i_2__1_n_0 ;
wire \COUNT[7]_i_3__1_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire [0:0]E;
wire ETH_CLK_OBUF;
wire LED_B_PWM_OBUF;
wire OUT_BIT_i_10__1_n_0;
wire OUT_BIT_i_1__1_n_0;
wire OUT_BIT_i_3__1_n_0;
wire OUT_BIT_i_4__1_n_0;
wire OUT_BIT_i_5__1_n_0;
wire OUT_BIT_i_6__1_n_0;
wire OUT_BIT_i_7__1_n_0;
wire OUT_BIT_i_8__1_n_0;
wire OUT_BIT_i_9__1_n_0;
wire [7:0]PWM_VAL;
wire [7:0]Q;
wire [9:0]TIMER;
wire \TIMER[4]_i_2__1_n_0 ;
wire \TIMER[9]_i_2__1_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__3
(.I0(\COUNT[7]_i_3__1_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__3_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__3
(.I0(\COUNT[1]_i_2__1_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__3_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2__1
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__2
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2__1_n_0 ),
.O(\COUNT[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2__1_n_0 ),
.O(\COUNT[3]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3__1_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1__1
(.I0(\COUNT[7]_i_3__1_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3__1_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1__1
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2__1_n_0 ),
.O(\COUNT[7]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3__1_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2__1_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3__1_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[0]_i_1__3_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[1]_i_1__3_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[2]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[3]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[4]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[5]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[6]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[7]_i_2__1_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'h9009))
OUT_BIT_i_10__1
(.I0(PWM_VAL[1]),
.I1(\COUNT_reg_n_0_[1] ),
.I2(PWM_VAL[0]),
.I3(\COUNT_reg_n_0_[0] ),
.O(OUT_BIT_i_10__1_n_0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1__1
(.I0(p_0_in),
.O(OUT_BIT_i_1__1_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_3__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(PWM_VAL[6]),
.I2(\COUNT_reg_n_0_[6] ),
.I3(PWM_VAL[7]),
.O(OUT_BIT_i_3__1_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_4__1
(.I0(\COUNT_reg_n_0_[5] ),
.I1(PWM_VAL[4]),
.I2(\COUNT_reg_n_0_[4] ),
.I3(PWM_VAL[5]),
.O(OUT_BIT_i_4__1_n_0));
LUT4 #(
.INIT(16'h20BA))
OUT_BIT_i_5__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(PWM_VAL[2]),
.I2(\COUNT_reg_n_0_[2] ),
.I3(PWM_VAL[3]),
.O(OUT_BIT_i_5__1_n_0));
LUT4 #(
.INIT(16'h22B2))
OUT_BIT_i_6__1
(.I0(\COUNT_reg_n_0_[1] ),
.I1(PWM_VAL[1]),
.I2(\COUNT_reg_n_0_[0] ),
.I3(PWM_VAL[0]),
.O(OUT_BIT_i_6__1_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_7__1
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(PWM_VAL[6]),
.I3(PWM_VAL[7]),
.O(OUT_BIT_i_7__1_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_8__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(PWM_VAL[4]),
.I3(PWM_VAL[5]),
.O(OUT_BIT_i_8__1_n_0));
LUT4 #(
.INIT(16'h8421))
OUT_BIT_i_9__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(PWM_VAL[2]),
.I3(PWM_VAL[3]),
.O(OUT_BIT_i_9__1_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1__1_n_0),
.Q(LED_B_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2__1
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3__1_n_0,OUT_BIT_i_4__1_n_0,OUT_BIT_i_5__1_n_0,OUT_BIT_i_6__1_n_0}),
.O(NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7__1_n_0,OUT_BIT_i_8__1_n_0,OUT_BIT_i_9__1_n_0,OUT_BIT_i_10__1_n_0}));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[0]),
.Q(PWM_VAL[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[1]),
.Q(PWM_VAL[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[2]),
.Q(PWM_VAL[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[3]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[3]),
.Q(PWM_VAL[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[4]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[4]),
.Q(PWM_VAL[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[5]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[5]),
.Q(PWM_VAL[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[6]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[6]),
.Q(PWM_VAL[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\PWM_VAL_reg[7]
(.C(ETH_CLK_OBUF),
.CE(E),
.D(Q[7]),
.Q(PWM_VAL[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__2
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1__1
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__2
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1__1
(.I0(\TIMER[4]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1__1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2__1_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2__1
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1__1
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1__1
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2__1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2__1_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
module RAM32M_UNIQ_BASE_
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD10
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD11
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD12
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD13
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD14
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD4
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD5
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD6
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD7
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD8
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "RAM32M" *)
module RAM32M_HD9
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
module SERIAL_INPUT
(OUT1,
OUT1_STB,
INTERNAL_RST_reg,
ETH_CLK_OBUF,
OUT1_ACK,
RX);
output [7:0]OUT1;
output OUT1_STB;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
input OUT1_ACK;
input RX;
wire [11:0]BAUD_COUNT;
wire \BAUD_COUNT[11]_i_2_n_0 ;
wire \BAUD_COUNT[11]_i_3_n_0 ;
wire \BAUD_COUNT[11]_i_5_n_0 ;
wire \BAUD_COUNT_reg[4]_i_2__0_n_0 ;
wire \BAUD_COUNT_reg[8]_i_2__0_n_0 ;
wire \BAUD_COUNT_reg_n_0_[0] ;
wire \BAUD_COUNT_reg_n_0_[10] ;
wire \BAUD_COUNT_reg_n_0_[11] ;
wire \BAUD_COUNT_reg_n_0_[1] ;
wire \BAUD_COUNT_reg_n_0_[2] ;
wire \BAUD_COUNT_reg_n_0_[3] ;
wire \BAUD_COUNT_reg_n_0_[4] ;
wire \BAUD_COUNT_reg_n_0_[5] ;
wire \BAUD_COUNT_reg_n_0_[6] ;
wire \BAUD_COUNT_reg_n_0_[7] ;
wire \BAUD_COUNT_reg_n_0_[8] ;
wire \BAUD_COUNT_reg_n_0_[9] ;
wire \BIT_SPACING[0]_i_1_n_0 ;
wire \BIT_SPACING[0]_i_2_n_0 ;
wire \BIT_SPACING[1]_i_1_n_0 ;
wire \BIT_SPACING[2]_i_1_n_0 ;
wire \BIT_SPACING[2]_i_2_n_0 ;
wire \BIT_SPACING[2]_i_3_n_0 ;
wire \BIT_SPACING[3]_i_1_n_0 ;
wire \BIT_SPACING[3]_i_2_n_0 ;
wire \BIT_SPACING[3]_i_3_n_0 ;
wire \BIT_SPACING[3]_i_4_n_0 ;
wire \BIT_SPACING[3]_i_5_n_0 ;
wire \BIT_SPACING_reg_n_0_[0] ;
wire \BIT_SPACING_reg_n_0_[1] ;
wire \BIT_SPACING_reg_n_0_[2] ;
wire \BIT_SPACING_reg_n_0_[3] ;
wire \COUNT[0]_i_1_n_0 ;
wire \COUNT[1]_i_1_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire ETH_CLK_OBUF;
wire \FSM_sequential_STATE[0]_i_1__0_n_0 ;
wire \FSM_sequential_STATE[1]_i_1__0_n_0 ;
wire \FSM_sequential_STATE[2]_i_1__0_n_0 ;
wire \FSM_sequential_STATE[3]_i_1__0_n_0 ;
wire \FSM_sequential_STATE[3]_i_2__0_n_0 ;
wire \FSM_sequential_STATE[3]_i_3__0_n_0 ;
wire \FSM_sequential_STATE[3]_i_4_n_0 ;
wire \FSM_sequential_STATE[3]_i_5_n_0 ;
wire \FSM_sequential_STATE[3]_i_6_n_0 ;
wire \FSM_sequential_STATE[3]_i_7_n_0 ;
wire INTERNAL_RST_reg;
wire INT_SERIAL_i_1_n_0;
wire INT_SERIAL_reg_n_0;
wire [7:0]OUT1;
wire \OUT1[0]_i_1_n_0 ;
wire \OUT1[1]_i_1_n_0 ;
wire \OUT1[2]_i_1_n_0 ;
wire \OUT1[3]_i_1_n_0 ;
wire \OUT1[3]_i_2_n_0 ;
wire \OUT1[4]_i_1_n_0 ;
wire \OUT1[4]_i_2_n_0 ;
wire \OUT1[5]_i_1_n_0 ;
wire \OUT1[5]_i_2_n_0 ;
wire \OUT1[6]_i_1_n_0 ;
wire \OUT1[7]_i_1_n_0 ;
wire OUT1_ACK;
wire OUT1_STB;
wire OUT1_STB_i_1_n_0;
wire OUT1_STB_i_2_n_0;
wire RX;
(* RTL_KEEP = "yes" *) wire [3:0]STATE;
wire X16CLK_EN7_out;
wire X16CLK_EN_reg_n_0;
wire [11:1]data0;
wire p_0_in;
wire p_0_in3_in;
wire [1:1]p_0_in__0;
wire [3:0]\NLW_BAUD_COUNT_reg[11]_i_4__0_CO_UNCONNECTED ;
wire [3:3]\NLW_BAUD_COUNT_reg[11]_i_4__0_O_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[4]_i_2__0_CO_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[8]_i_2__0_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h0E))
\BAUD_COUNT[0]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(\BAUD_COUNT_reg_n_0_[0] ),
.O(BAUD_COUNT[0]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[10]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[10]),
.O(BAUD_COUNT[10]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[11]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[11]),
.O(BAUD_COUNT[11]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\BAUD_COUNT[11]_i_2
(.I0(\BAUD_COUNT_reg_n_0_[10] ),
.I1(\BAUD_COUNT_reg_n_0_[11] ),
.I2(\BAUD_COUNT_reg_n_0_[9] ),
.I3(\BAUD_COUNT_reg_n_0_[8] ),
.I4(\BAUD_COUNT_reg_n_0_[7] ),
.O(\BAUD_COUNT[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF0707FF07))
\BAUD_COUNT[11]_i_3
(.I0(\BAUD_COUNT_reg_n_0_[4] ),
.I1(\BAUD_COUNT_reg_n_0_[3] ),
.I2(\BAUD_COUNT_reg_n_0_[5] ),
.I3(\BAUD_COUNT_reg_n_0_[6] ),
.I4(\BAUD_COUNT_reg_n_0_[7] ),
.I5(\BAUD_COUNT[11]_i_5_n_0 ),
.O(\BAUD_COUNT[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFDFFFFFFFFFFFF))
\BAUD_COUNT[11]_i_5
(.I0(\BAUD_COUNT_reg_n_0_[4] ),
.I1(\BAUD_COUNT_reg_n_0_[8] ),
.I2(\BAUD_COUNT_reg_n_0_[5] ),
.I3(\BAUD_COUNT_reg_n_0_[2] ),
.I4(\BAUD_COUNT_reg_n_0_[0] ),
.I5(\BAUD_COUNT_reg_n_0_[1] ),
.O(\BAUD_COUNT[11]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[1]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[1]),
.O(BAUD_COUNT[1]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[2]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[2]),
.O(BAUD_COUNT[2]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[3]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[3]),
.O(BAUD_COUNT[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[4]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[4]),
.O(BAUD_COUNT[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[5]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[5]),
.O(BAUD_COUNT[5]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[6]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[6]),
.O(BAUD_COUNT[6]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[7]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[7]),
.O(BAUD_COUNT[7]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[8]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[8]),
.O(BAUD_COUNT[8]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[9]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[9]),
.O(BAUD_COUNT[9]));
FDRE \BAUD_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[0]),
.Q(\BAUD_COUNT_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[10]),
.Q(\BAUD_COUNT_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[11]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[11]),
.Q(\BAUD_COUNT_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[11]_i_4__0
(.CI(\BAUD_COUNT_reg[8]_i_2__0_n_0 ),
.CO(\NLW_BAUD_COUNT_reg[11]_i_4__0_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_BAUD_COUNT_reg[11]_i_4__0_O_UNCONNECTED [3],data0[11:9]}),
.S({1'b0,\BAUD_COUNT_reg_n_0_[11] ,\BAUD_COUNT_reg_n_0_[10] ,\BAUD_COUNT_reg_n_0_[9] }));
FDRE \BAUD_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[1]),
.Q(\BAUD_COUNT_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[2]),
.Q(\BAUD_COUNT_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[3]),
.Q(\BAUD_COUNT_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[4]),
.Q(\BAUD_COUNT_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[4]_i_2__0
(.CI(1'b0),
.CO({\BAUD_COUNT_reg[4]_i_2__0_n_0 ,\NLW_BAUD_COUNT_reg[4]_i_2__0_CO_UNCONNECTED [2:0]}),
.CYINIT(\BAUD_COUNT_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[4:1]),
.S({\BAUD_COUNT_reg_n_0_[4] ,\BAUD_COUNT_reg_n_0_[3] ,\BAUD_COUNT_reg_n_0_[2] ,\BAUD_COUNT_reg_n_0_[1] }));
FDRE \BAUD_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[5]),
.Q(\BAUD_COUNT_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[6]),
.Q(\BAUD_COUNT_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[7]),
.Q(\BAUD_COUNT_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[8]),
.Q(\BAUD_COUNT_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[8]_i_2__0
(.CI(\BAUD_COUNT_reg[4]_i_2__0_n_0 ),
.CO({\BAUD_COUNT_reg[8]_i_2__0_n_0 ,\NLW_BAUD_COUNT_reg[8]_i_2__0_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[8:5]),
.S({\BAUD_COUNT_reg_n_0_[8] ,\BAUD_COUNT_reg_n_0_[7] ,\BAUD_COUNT_reg_n_0_[6] ,\BAUD_COUNT_reg_n_0_[5] }));
FDRE \BAUD_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[9]),
.Q(\BAUD_COUNT_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h3222332232223222))
\BIT_SPACING[0]_i_1
(.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I1(\BIT_SPACING_reg_n_0_[0] ),
.I2(\BIT_SPACING[3]_i_4_n_0 ),
.I3(\BIT_SPACING[0]_i_2_n_0 ),
.I4(p_0_in),
.I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
.O(\BIT_SPACING[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\BIT_SPACING[0]_i_2
(.I0(\BIT_SPACING_reg_n_0_[3] ),
.I1(\BIT_SPACING_reg_n_0_[2] ),
.I2(\BIT_SPACING_reg_n_0_[0] ),
.I3(\BIT_SPACING_reg_n_0_[1] ),
.O(\BIT_SPACING[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6660666666606660))
\BIT_SPACING[1]_i_1
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(\BIT_SPACING_reg_n_0_[0] ),
.I2(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I3(\BIT_SPACING[3]_i_4_n_0 ),
.I4(p_0_in),
.I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
.O(\BIT_SPACING[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF888FF88F888F888))
\BIT_SPACING[2]_i_1
(.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I1(\BIT_SPACING[2]_i_2_n_0 ),
.I2(\BIT_SPACING[3]_i_4_n_0 ),
.I3(\BIT_SPACING[2]_i_3_n_0 ),
.I4(p_0_in),
.I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
.O(\BIT_SPACING[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6C))
\BIT_SPACING[2]_i_2
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(\BIT_SPACING_reg_n_0_[2] ),
.I2(\BIT_SPACING_reg_n_0_[0] ),
.O(\BIT_SPACING[2]_i_2_n_0 ));
LUT3 #(
.INIT(8'h78))
\BIT_SPACING[2]_i_3
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(\BIT_SPACING_reg_n_0_[0] ),
.I2(\BIT_SPACING_reg_n_0_[2] ),
.O(\BIT_SPACING[2]_i_3_n_0 ));
LUT5 #(
.INIT(32'h55FF0001))
\BIT_SPACING[3]_i_1
(.I0(STATE[3]),
.I1(STATE[0]),
.I2(STATE[1]),
.I3(STATE[2]),
.I4(X16CLK_EN_reg_n_0),
.O(\BIT_SPACING[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF888FF88F888F888))
\BIT_SPACING[3]_i_2
(.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I1(\BIT_SPACING[3]_i_3_n_0 ),
.I2(\BIT_SPACING[3]_i_4_n_0 ),
.I3(\BIT_SPACING[3]_i_5_n_0 ),
.I4(p_0_in),
.I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
.O(\BIT_SPACING[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h52F0F0F0))
\BIT_SPACING[3]_i_3
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(X16CLK_EN_reg_n_0),
.I2(\BIT_SPACING_reg_n_0_[3] ),
.I3(\BIT_SPACING_reg_n_0_[2] ),
.I4(\BIT_SPACING_reg_n_0_[0] ),
.O(\BIT_SPACING[3]_i_3_n_0 ));
LUT4 #(
.INIT(16'h4000))
\BIT_SPACING[3]_i_4
(.I0(STATE[2]),
.I1(STATE[3]),
.I2(STATE[1]),
.I3(STATE[0]),
.O(\BIT_SPACING[3]_i_4_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\BIT_SPACING[3]_i_5
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(\BIT_SPACING_reg_n_0_[0] ),
.I2(\BIT_SPACING_reg_n_0_[2] ),
.I3(\BIT_SPACING_reg_n_0_[3] ),
.O(\BIT_SPACING[3]_i_5_n_0 ));
LUT5 #(
.INIT(32'h80000000))
\BIT_SPACING[3]_i_6
(.I0(\BIT_SPACING_reg_n_0_[3] ),
.I1(\BIT_SPACING_reg_n_0_[1] ),
.I2(\BIT_SPACING_reg_n_0_[0] ),
.I3(\BIT_SPACING_reg_n_0_[2] ),
.I4(X16CLK_EN_reg_n_0),
.O(p_0_in));
FDRE \BIT_SPACING_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\BIT_SPACING[3]_i_1_n_0 ),
.D(\BIT_SPACING[0]_i_1_n_0 ),
.Q(\BIT_SPACING_reg_n_0_[0] ),
.R(1'b0));
FDRE \BIT_SPACING_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\BIT_SPACING[3]_i_1_n_0 ),
.D(\BIT_SPACING[1]_i_1_n_0 ),
.Q(\BIT_SPACING_reg_n_0_[1] ),
.R(1'b0));
FDRE \BIT_SPACING_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\BIT_SPACING[3]_i_1_n_0 ),
.D(\BIT_SPACING[2]_i_1_n_0 ),
.Q(\BIT_SPACING_reg_n_0_[2] ),
.R(1'b0));
FDRE \BIT_SPACING_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\BIT_SPACING[3]_i_1_n_0 ),
.D(\BIT_SPACING[3]_i_2_n_0 ),
.Q(\BIT_SPACING_reg_n_0_[3] ),
.R(1'b0));
LUT4 #(
.INIT(16'h8FE0))
\COUNT[0]_i_1
(.I0(p_0_in3_in),
.I1(\COUNT_reg_n_0_[1] ),
.I2(X16CLK_EN_reg_n_0),
.I3(\COUNT_reg_n_0_[0] ),
.O(\COUNT[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'hECC4))
\COUNT[1]_i_1
(.I0(X16CLK_EN_reg_n_0),
.I1(\COUNT_reg_n_0_[1] ),
.I2(p_0_in3_in),
.I3(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[0]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[1]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
LUT3 #(
.INIT(8'h07))
\FSM_sequential_STATE[0]_i_1__0
(.I0(STATE[2]),
.I1(STATE[3]),
.I2(STATE[0]),
.O(\FSM_sequential_STATE[0]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h152A))
\FSM_sequential_STATE[1]_i_1__0
(.I0(STATE[1]),
.I1(STATE[2]),
.I2(STATE[3]),
.I3(STATE[0]),
.O(\FSM_sequential_STATE[1]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h006A))
\FSM_sequential_STATE[2]_i_1__0
(.I0(STATE[2]),
.I1(STATE[1]),
.I2(STATE[0]),
.I3(STATE[3]),
.O(\FSM_sequential_STATE[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFA8FF20))
\FSM_sequential_STATE[3]_i_1__0
(.I0(\FSM_sequential_STATE[3]_i_3__0_n_0 ),
.I1(\BIT_SPACING_reg_n_0_[3] ),
.I2(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I3(\FSM_sequential_STATE[3]_i_5_n_0 ),
.I4(\FSM_sequential_STATE[3]_i_6_n_0 ),
.I5(\FSM_sequential_STATE[3]_i_7_n_0 ),
.O(\FSM_sequential_STATE[3]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h1580))
\FSM_sequential_STATE[3]_i_2__0
(.I0(STATE[2]),
.I1(STATE[1]),
.I2(STATE[0]),
.I3(STATE[3]),
.O(\FSM_sequential_STATE[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h8000))
\FSM_sequential_STATE[3]_i_3__0
(.I0(X16CLK_EN_reg_n_0),
.I1(\BIT_SPACING_reg_n_0_[2] ),
.I2(\BIT_SPACING_reg_n_0_[0] ),
.I3(\BIT_SPACING_reg_n_0_[1] ),
.O(\FSM_sequential_STATE[3]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h0004))
\FSM_sequential_STATE[3]_i_4
(.I0(STATE[3]),
.I1(STATE[0]),
.I2(STATE[2]),
.I3(STATE[1]),
.O(\FSM_sequential_STATE[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\FSM_sequential_STATE[3]_i_5
(.I0(STATE[1]),
.I1(STATE[2]),
.I2(X16CLK_EN_reg_n_0),
.I3(INT_SERIAL_reg_n_0),
.I4(STATE[3]),
.I5(STATE[0]),
.O(\FSM_sequential_STATE[3]_i_5_n_0 ));
LUT4 #(
.INIT(16'h337C))
\FSM_sequential_STATE[3]_i_6
(.I0(STATE[0]),
.I1(STATE[3]),
.I2(STATE[1]),
.I3(STATE[2]),
.O(\FSM_sequential_STATE[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'h00800000))
\FSM_sequential_STATE[3]_i_7
(.I0(STATE[0]),
.I1(STATE[1]),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(OUT1_ACK),
.O(\FSM_sequential_STATE[3]_i_7_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
.D(\FSM_sequential_STATE[0]_i_1__0_n_0 ),
.Q(STATE[0]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
.D(\FSM_sequential_STATE[1]_i_1__0_n_0 ),
.Q(STATE[1]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
.D(\FSM_sequential_STATE[2]_i_1__0_n_0 ),
.Q(STATE[2]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
.D(\FSM_sequential_STATE[3]_i_2__0_n_0 ),
.Q(STATE[3]),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'hEAAAA8AA))
INT_SERIAL_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(X16CLK_EN_reg_n_0),
.I4(p_0_in3_in),
.O(INT_SERIAL_i_1_n_0));
FDRE INT_SERIAL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INT_SERIAL_i_1_n_0),
.Q(INT_SERIAL_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\OUT1[0]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(p_0_in),
.I2(STATE[1]),
.I3(STATE[2]),
.I4(\OUT1[4]_i_2_n_0 ),
.I5(OUT1[0]),
.O(\OUT1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF8FFFFFF08000000))
\OUT1[1]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(\OUT1[3]_i_2_n_0 ),
.I2(STATE[2]),
.I3(p_0_in),
.I4(\OUT1[5]_i_2_n_0 ),
.I5(OUT1[1]),
.O(\OUT1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\OUT1[2]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[2]),
.I2(\OUT1[4]_i_2_n_0 ),
.I3(STATE[1]),
.I4(p_0_in),
.I5(OUT1[2]),
.O(\OUT1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\OUT1[3]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[2]),
.I2(\OUT1[3]_i_2_n_0 ),
.I3(STATE[1]),
.I4(p_0_in),
.I5(OUT1[3]),
.O(\OUT1[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\OUT1[3]_i_2
(.I0(STATE[0]),
.I1(STATE[3]),
.O(\OUT1[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFF80000000))
\OUT1[4]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(p_0_in),
.I2(STATE[1]),
.I3(STATE[2]),
.I4(\OUT1[4]_i_2_n_0 ),
.I5(OUT1[4]),
.O(\OUT1[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\OUT1[4]_i_2
(.I0(STATE[0]),
.I1(STATE[3]),
.O(\OUT1[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hBFFF8000))
\OUT1[5]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[2]),
.I2(p_0_in),
.I3(\OUT1[5]_i_2_n_0 ),
.I4(OUT1[5]),
.O(\OUT1[5]_i_1_n_0 ));
LUT3 #(
.INIT(8'h08))
\OUT1[5]_i_2
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[3]),
.O(\OUT1[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\OUT1[6]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[0]),
.I2(STATE[3]),
.I3(STATE[1]),
.I4(p_0_in),
.I5(OUT1[6]),
.O(\OUT1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\OUT1[7]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[3]),
.I2(STATE[0]),
.I3(STATE[1]),
.I4(p_0_in),
.I5(OUT1[7]),
.O(\OUT1[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h10FF1000))
OUT1_STB_i_1
(.I0(STATE[2]),
.I1(STATE[0]),
.I2(p_0_in),
.I3(OUT1_STB_i_2_n_0),
.I4(OUT1_STB),
.O(OUT1_STB_i_1_n_0));
LUT6 #(
.INIT(64'h080C000008000000))
OUT1_STB_i_2
(.I0(OUT1_ACK),
.I1(STATE[3]),
.I2(STATE[2]),
.I3(STATE[0]),
.I4(STATE[1]),
.I5(p_0_in),
.O(OUT1_STB_i_2_n_0));
FDRE OUT1_STB_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT1_STB_i_1_n_0),
.Q(OUT1_STB),
.R(INTERNAL_RST_reg));
FDRE \OUT1_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[0]_i_1_n_0 ),
.Q(OUT1[0]),
.R(1'b0));
FDRE \OUT1_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[1]_i_1_n_0 ),
.Q(OUT1[1]),
.R(1'b0));
FDRE \OUT1_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[2]_i_1_n_0 ),
.Q(OUT1[2]),
.R(1'b0));
FDRE \OUT1_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[3]_i_1_n_0 ),
.Q(OUT1[3]),
.R(1'b0));
FDRE \OUT1_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[4]_i_1_n_0 ),
.Q(OUT1[4]),
.R(1'b0));
FDRE \OUT1_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[5]_i_1_n_0 ),
.Q(OUT1[5]),
.R(1'b0));
FDRE \OUT1_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[6]_i_1_n_0 ),
.Q(OUT1[6]),
.R(1'b0));
FDRE \OUT1_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[7]_i_1_n_0 ),
.Q(OUT1[7]),
.R(1'b0));
FDSE \SERIAL_DEGLITCH_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(RX),
.Q(p_0_in__0),
.S(INTERNAL_RST_reg));
FDSE \SERIAL_DEGLITCH_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(p_0_in__0),
.Q(p_0_in3_in),
.S(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h01))
X16CLK_EN_i_1
(.I0(INTERNAL_RST_reg),
.I1(\BAUD_COUNT[11]_i_2_n_0 ),
.I2(\BAUD_COUNT[11]_i_3_n_0 ),
.O(X16CLK_EN7_out));
FDRE X16CLK_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(X16CLK_EN7_out),
.Q(X16CLK_EN_reg_n_0),
.R(1'b0));
endmodule
module VIDEO_TIME_GEN
(\PIXCOL_DEL_reg[0] ,
\PIXCOL_DEL_reg[1] ,
\PIXCOL_DEL_reg[2] ,
ADDRBWRADDR,
\PIXROW_DEL_reg[0] ,
\PIXROW_DEL_reg[1] ,
D,
HSYNCH_DEL_reg,
VSYNCH_DEL_reg,
BLANK,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output \PIXCOL_DEL_reg[0] ;
output \PIXCOL_DEL_reg[1] ;
output \PIXCOL_DEL_reg[2] ;
output [12:0]ADDRBWRADDR;
output \PIXROW_DEL_reg[0] ;
output \PIXROW_DEL_reg[1] ;
output [0:0]D;
output HSYNCH_DEL_reg;
output VSYNCH_DEL_reg;
output BLANK;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire [12:0]ADDRBWRADDR;
wire BLANK;
wire \COL_ADDRESS[0]_i_1_n_0 ;
wire \COL_ADDRESS[1]_i_1_n_0 ;
wire \COL_ADDRESS[2]_i_1_n_0 ;
wire \COL_ADDRESS[3]_i_1_n_0 ;
wire \COL_ADDRESS[4]_i_1_n_0 ;
wire \COL_ADDRESS[5]_i_1_n_0 ;
wire \COL_ADDRESS[6]_i_1_n_0 ;
wire \COL_ADDRESS[6]_i_2_n_0 ;
wire \COL_ADDRESS[6]_i_3_n_0 ;
wire \COL_ADDRESS_reg_n_0_[1] ;
wire \COL_ADDRESS_reg_n_0_[2] ;
wire \COL_ADDRESS_reg_n_0_[3] ;
wire \COL_ADDRESS_reg_n_0_[4] ;
wire \COL_ADDRESS_reg_n_0_[5] ;
wire \COL_ADDRESS_reg_n_0_[6] ;
wire [0:0]D;
wire ETH_CLK_OBUF;
wire HBLANK_i_1_n_0;
wire HBLANK_i_2_n_0;
wire HBLANK_i_3_n_0;
wire HBLANK_i_4_n_0;
wire HBLANK_i_5_n_0;
wire HBLANK_i_6_n_0;
wire HBLANK_reg_n_0;
wire HSYNCH_DEL_reg;
wire [10:0]HTIMER;
wire \HTIMER[0]_i_2_n_0 ;
wire \HTIMER[0]_i_3_n_0 ;
wire \HTIMER[10]_i_2_n_0 ;
wire \HTIMER[10]_i_3_n_0 ;
wire \HTIMER[10]_i_4_n_0 ;
wire \HTIMER[2]_i_1_n_0 ;
wire \HTIMER[4]_i_2_n_0 ;
wire \HTIMER[5]_i_1_n_0 ;
wire \HTIMER[6]_i_1_n_0 ;
wire \HTIMER[9]_i_2_n_0 ;
wire INTERNAL_RST_reg;
wire INTHSYNCH_i_1_n_0;
wire INTVSYNCH2_out;
wire INTVSYNCH_i_1_n_0;
wire INTVSYNCH_i_3_n_0;
wire MEMORY_reg_0_i_11_n_0;
wire MEMORY_reg_0_i_12_n_0;
wire MEMORY_reg_0_i_13_n_0;
wire MEMORY_reg_0_i_14_n_0;
wire MEMORY_reg_0_i_15_n_0;
wire MEMORY_reg_0_i_16_n_0;
wire MEMORY_reg_0_i_2_n_0;
wire MEMORY_reg_0_i_3_n_0;
wire \PIXCOL_DEL_reg[0] ;
wire \PIXCOL_DEL_reg[1] ;
wire \PIXCOL_DEL_reg[2] ;
wire \PIXROW_DEL_reg[0] ;
wire \PIXROW_DEL_reg[1] ;
wire \PIX_COL_ADDRESS[0]_i_1_n_0 ;
wire \PIX_COL_ADDRESS[1]_i_1_n_0 ;
wire \PIX_COL_ADDRESS[2]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[0]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[1]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_2_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_3_n_0 ;
wire [12:1]ROW_ADDRESS;
wire \ROW_ADDRESS[12]_i_1_n_0 ;
wire \ROW_ADDRESS[12]_i_3_n_0 ;
wire \ROW_ADDRESS[12]_i_4_n_0 ;
wire \ROW_ADDRESS[4]_i_5_n_0 ;
wire \ROW_ADDRESS[8]_i_5_n_0 ;
wire \ROW_ADDRESS[8]_i_6_n_0 ;
wire [12:1]ROW_ADDRESS_0;
wire \ROW_ADDRESS_reg[12]_i_5_n_4 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_5 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_6 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_7 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_0 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_4 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_5 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_6 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_7 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_0 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_4 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_5 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_6 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_7 ;
wire VBLANK_i_1_n_0;
wire VBLANK_i_2_n_0;
wire VBLANK_i_3_n_0;
wire VBLANK_i_4_n_0;
wire VBLANK_i_5_n_0;
wire VBLANK_i_6_n_0;
wire VBLANK_i_7_n_0;
wire VBLANK_reg_n_0;
wire VSYNCH_DEL_reg;
wire [9:0]VTIMER;
wire \VTIMER[0]_i_1_n_0 ;
wire \VTIMER[2]_i_2_n_0 ;
wire \VTIMER[2]_i_3_n_0 ;
wire \VTIMER[5]_i_1_n_0 ;
wire \VTIMER[9]_i_2_n_0 ;
wire \VTIMER[9]_i_3_n_0 ;
wire \VTIMER[9]_i_4_n_0 ;
wire \VTIMER[9]_i_5_n_0 ;
wire [9:1]VTIMER_1;
wire VTIMER_EN;
wire VTIMER_EN_i_1_n_0;
wire [10:0]sel0;
wire [3:0]NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED;
wire [2:0]NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED;
wire [2:0]NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED;
wire [0:0]NLW_MEMORY_reg_0_i_3_O_UNCONNECTED;
wire [3:0]\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED ;
wire [2:0]\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'hE))
BLANK_DEL_i_1
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.O(BLANK));
LUT1 #(
.INIT(2'h1))
\COL_ADDRESS[0]_i_1
(.I0(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\COL_ADDRESS[1]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[1] ),
.I1(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF00000000EFFF))
\COL_ADDRESS[2]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[4] ),
.I1(\COL_ADDRESS_reg_n_0_[3] ),
.I2(\COL_ADDRESS_reg_n_0_[6] ),
.I3(\COL_ADDRESS_reg_n_0_[5] ),
.I4(\COL_ADDRESS[6]_i_3_n_0 ),
.I5(\COL_ADDRESS_reg_n_0_[2] ),
.O(\COL_ADDRESS[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6AAA))
\COL_ADDRESS[3]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[3] ),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.I2(ADDRBWRADDR[0]),
.I3(\COL_ADDRESS_reg_n_0_[2] ),
.O(\COL_ADDRESS[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\COL_ADDRESS[4]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[4] ),
.I1(\COL_ADDRESS_reg_n_0_[2] ),
.I2(ADDRBWRADDR[0]),
.I3(\COL_ADDRESS_reg_n_0_[1] ),
.I4(\COL_ADDRESS_reg_n_0_[3] ),
.O(\COL_ADDRESS[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFD00C00000))
\COL_ADDRESS[5]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[6] ),
.I1(\COL_ADDRESS_reg_n_0_[4] ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS[6]_i_3_n_0 ),
.I4(\COL_ADDRESS_reg_n_0_[3] ),
.I5(\COL_ADDRESS_reg_n_0_[5] ),
.O(\COL_ADDRESS[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\COL_ADDRESS[6]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(\PIXCOL_DEL_reg[1] ),
.I2(\PIXCOL_DEL_reg[2] ),
.I3(HBLANK_reg_n_0),
.I4(VBLANK_reg_n_0),
.O(\COL_ADDRESS[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFEFFFF20000000))
\COL_ADDRESS[6]_i_2
(.I0(\COL_ADDRESS_reg_n_0_[3] ),
.I1(\COL_ADDRESS[6]_i_3_n_0 ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS_reg_n_0_[4] ),
.I4(\COL_ADDRESS_reg_n_0_[5] ),
.I5(\COL_ADDRESS_reg_n_0_[6] ),
.O(\COL_ADDRESS[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'h7))
\COL_ADDRESS[6]_i_3
(.I0(\COL_ADDRESS_reg_n_0_[1] ),
.I1(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[6]_i_3_n_0 ));
FDRE \COL_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[0]_i_1_n_0 ),
.Q(ADDRBWRADDR[0]),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[1]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[2]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[3]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[4]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[5]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[6]_i_2_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFFFFFF70000))
HBLANK_i_1
(.I0(HBLANK_i_2_n_0),
.I1(sel0[7]),
.I2(sel0[8]),
.I3(sel0[6]),
.I4(HBLANK_reg_n_0),
.I5(HBLANK_i_3_n_0),
.O(HBLANK_i_1_n_0));
LUT6 #(
.INIT(64'h0000000010000000))
HBLANK_i_2
(.I0(sel0[9]),
.I1(sel0[10]),
.I2(sel0[5]),
.I3(sel0[4]),
.I4(sel0[3]),
.I5(HBLANK_i_4_n_0),
.O(HBLANK_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAABAAAAAAAAAA))
HBLANK_i_3
(.I0(INTERNAL_RST_reg),
.I1(HBLANK_i_5_n_0),
.I2(sel0[0]),
.I3(sel0[3]),
.I4(HBLANK_i_6_n_0),
.I5(\HTIMER[0]_i_3_n_0 ),
.O(HBLANK_i_3_n_0));
LUT3 #(
.INIT(8'hFE))
HBLANK_i_4
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[0]),
.O(HBLANK_i_4_n_0));
LUT3 #(
.INIT(8'hBF))
HBLANK_i_5
(.I0(sel0[10]),
.I1(sel0[8]),
.I2(sel0[9]),
.O(HBLANK_i_5_n_0));
LUT2 #(
.INIT(4'h7))
HBLANK_i_6
(.I0(sel0[7]),
.I1(sel0[6]),
.O(HBLANK_i_6_n_0));
FDRE HBLANK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HBLANK_i_1_n_0),
.Q(HBLANK_reg_n_0),
.R(1'b0));
LUT5 #(
.INIT(32'h0000FDFF))
\HTIMER[0]_i_1
(.I0(\HTIMER[0]_i_2_n_0 ),
.I1(sel0[6]),
.I2(sel0[3]),
.I3(\HTIMER[0]_i_3_n_0 ),
.I4(sel0[0]),
.O(HTIMER[0]));
LUT4 #(
.INIT(16'h0010))
\HTIMER[0]_i_2
(.I0(sel0[8]),
.I1(sel0[7]),
.I2(sel0[10]),
.I3(sel0[9]),
.O(\HTIMER[0]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0010))
\HTIMER[0]_i_3
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[4]),
.I3(sel0[5]),
.O(\HTIMER[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'h3AAAAAAA))
\HTIMER[10]_i_1
(.I0(\HTIMER[10]_i_2_n_0 ),
.I1(sel0[10]),
.I2(sel0[8]),
.I3(sel0[9]),
.I4(\HTIMER[10]_i_3_n_0 ),
.O(HTIMER[10]));
LUT6 #(
.INIT(64'hAAAAAAA8AAAAAAAA))
\HTIMER[10]_i_2
(.I0(sel0[10]),
.I1(sel0[8]),
.I2(sel0[6]),
.I3(sel0[9]),
.I4(sel0[7]),
.I5(\HTIMER[10]_i_4_n_0 ),
.O(\HTIMER[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'h40))
\HTIMER[10]_i_3
(.I0(\HTIMER[9]_i_2_n_0 ),
.I1(sel0[6]),
.I2(sel0[7]),
.O(\HTIMER[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\HTIMER[10]_i_4
(.I0(sel0[5]),
.I1(sel0[3]),
.I2(sel0[4]),
.I3(sel0[2]),
.I4(sel0[1]),
.I5(sel0[0]),
.O(\HTIMER[10]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\HTIMER[1]_i_1
(.I0(sel0[0]),
.I1(sel0[1]),
.O(HTIMER[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h6A))
\HTIMER[2]_i_1
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[0]),
.O(\HTIMER[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h6AAA))
\HTIMER[3]_i_1
(.I0(sel0[3]),
.I1(sel0[1]),
.I2(sel0[0]),
.I3(sel0[2]),
.O(HTIMER[3]));
LUT6 #(
.INIT(64'h1555555540000000))
\HTIMER[4]_i_1
(.I0(\HTIMER[4]_i_2_n_0 ),
.I1(sel0[2]),
.I2(sel0[0]),
.I3(sel0[1]),
.I4(sel0[3]),
.I5(sel0[4]),
.O(HTIMER[4]));
LUT6 #(
.INIT(64'h0000000000000200))
\HTIMER[4]_i_2
(.I0(\HTIMER[10]_i_4_n_0 ),
.I1(sel0[8]),
.I2(sel0[7]),
.I3(sel0[10]),
.I4(sel0[9]),
.I5(sel0[6]),
.O(\HTIMER[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\HTIMER[5]_i_1
(.I0(sel0[5]),
.I1(sel0[4]),
.I2(sel0[3]),
.I3(sel0[1]),
.I4(sel0[0]),
.I5(sel0[2]),
.O(\HTIMER[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h9))
\HTIMER[6]_i_1
(.I0(sel0[6]),
.I1(\HTIMER[9]_i_2_n_0 ),
.O(\HTIMER[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'h9A))
\HTIMER[7]_i_1
(.I0(sel0[7]),
.I1(\HTIMER[9]_i_2_n_0 ),
.I2(sel0[6]),
.O(HTIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hAA6A))
\HTIMER[8]_i_1
(.I0(sel0[8]),
.I1(sel0[7]),
.I2(sel0[6]),
.I3(\HTIMER[9]_i_2_n_0 ),
.O(HTIMER[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h9AAAAAAA))
\HTIMER[9]_i_1
(.I0(sel0[9]),
.I1(\HTIMER[9]_i_2_n_0 ),
.I2(sel0[6]),
.I3(sel0[7]),
.I4(sel0[8]),
.O(HTIMER[9]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\HTIMER[9]_i_2
(.I0(sel0[4]),
.I1(sel0[3]),
.I2(sel0[1]),
.I3(sel0[0]),
.I4(sel0[2]),
.I5(sel0[5]),
.O(\HTIMER[9]_i_2_n_0 ));
FDRE \HTIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[0]),
.Q(sel0[0]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[10]),
.Q(sel0[10]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[1]),
.Q(sel0[1]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[2]_i_1_n_0 ),
.Q(sel0[2]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[3]),
.Q(sel0[3]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[4]),
.Q(sel0[4]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[5]_i_1_n_0 ),
.Q(sel0[5]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[6]_i_1_n_0 ),
.Q(sel0[6]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[7]),
.Q(sel0[7]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[8]),
.Q(sel0[8]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[9]),
.Q(sel0[9]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h00000000AAAEAAAA))
INTHSYNCH_i_1
(.I0(HSYNCH_DEL_reg),
.I1(HBLANK_i_2_n_0),
.I2(sel0[7]),
.I3(sel0[8]),
.I4(sel0[6]),
.I5(VTIMER_EN_i_1_n_0),
.O(INTHSYNCH_i_1_n_0));
FDRE INTHSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INTHSYNCH_i_1_n_0),
.Q(HSYNCH_DEL_reg),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000EEEE0EEE))
INTVSYNCH_i_1
(.I0(VSYNCH_DEL_reg),
.I1(INTVSYNCH2_out),
.I2(\VTIMER[2]_i_2_n_0 ),
.I3(VTIMER_EN),
.I4(VTIMER[0]),
.I5(INTERNAL_RST_reg),
.O(INTVSYNCH_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
INTVSYNCH_i_2
(.I0(VBLANK_i_2_n_0),
.I1(VTIMER[0]),
.I2(INTVSYNCH_i_3_n_0),
.I3(VTIMER[3]),
.I4(VTIMER[5]),
.I5(VTIMER[4]),
.O(INTVSYNCH2_out));
LUT2 #(
.INIT(4'h7))
INTVSYNCH_i_3
(.I0(VTIMER[1]),
.I1(VTIMER[2]),
.O(INTVSYNCH_i_3_n_0));
FDRE INTVSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INTVSYNCH_i_1_n_0),
.Q(VSYNCH_DEL_reg),
.R(1'b0));
CARRY4 MEMORY_reg_0_i_1
(.CI(MEMORY_reg_0_i_2_n_0),
.CO(NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(ADDRBWRADDR[12:9]),
.S(ROW_ADDRESS[12:9]));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_11
(.I0(ROW_ADDRESS[6]),
.I1(\COL_ADDRESS_reg_n_0_[6] ),
.O(MEMORY_reg_0_i_11_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_12
(.I0(ROW_ADDRESS[5]),
.I1(\COL_ADDRESS_reg_n_0_[5] ),
.O(MEMORY_reg_0_i_12_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_13
(.I0(ROW_ADDRESS[4]),
.I1(\COL_ADDRESS_reg_n_0_[4] ),
.O(MEMORY_reg_0_i_13_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_14
(.I0(ROW_ADDRESS[3]),
.I1(\COL_ADDRESS_reg_n_0_[3] ),
.O(MEMORY_reg_0_i_14_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_15
(.I0(ROW_ADDRESS[2]),
.I1(\COL_ADDRESS_reg_n_0_[2] ),
.O(MEMORY_reg_0_i_15_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_16
(.I0(ROW_ADDRESS[1]),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.O(MEMORY_reg_0_i_16_n_0));
CARRY4 MEMORY_reg_0_i_2
(.CI(MEMORY_reg_0_i_3_n_0),
.CO({MEMORY_reg_0_i_2_n_0,NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
.O(ADDRBWRADDR[8:5]),
.S({ROW_ADDRESS[8:7],MEMORY_reg_0_i_11_n_0,MEMORY_reg_0_i_12_n_0}));
CARRY4 MEMORY_reg_0_i_3
(.CI(1'b0),
.CO({MEMORY_reg_0_i_3_n_0,NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(ROW_ADDRESS[4:1]),
.O({ADDRBWRADDR[4:2],NLW_MEMORY_reg_0_i_3_O_UNCONNECTED[0]}),
.S({MEMORY_reg_0_i_13_n_0,MEMORY_reg_0_i_14_n_0,MEMORY_reg_0_i_15_n_0,MEMORY_reg_0_i_16_n_0}));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_4
(.I0(ROW_ADDRESS[1]),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.O(ADDRBWRADDR[1]));
LUT3 #(
.INIT(8'hE1))
\PIX_COL_ADDRESS[0]_i_1
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.I2(\PIXCOL_DEL_reg[0] ),
.O(\PIX_COL_ADDRESS[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFD02))
\PIX_COL_ADDRESS[1]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(HBLANK_reg_n_0),
.I2(VBLANK_reg_n_0),
.I3(\PIXCOL_DEL_reg[1] ),
.O(\PIX_COL_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFF70008))
\PIX_COL_ADDRESS[2]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(\PIXCOL_DEL_reg[1] ),
.I2(HBLANK_reg_n_0),
.I3(VBLANK_reg_n_0),
.I4(\PIXCOL_DEL_reg[2] ),
.O(\PIX_COL_ADDRESS[2]_i_1_n_0 ));
FDRE \PIX_COL_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[0]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[0] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_COL_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[1]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[1] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_COL_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[2]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[2] ),
.R(INTERNAL_RST_reg));
LUT2 #(
.INIT(4'h6))
\PIX_ROW_ADDRESS[0]_i_1
(.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I1(\PIXROW_DEL_reg[0] ),
.O(\PIX_ROW_ADDRESS[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\PIX_ROW_ADDRESS[1]_i_1
(.I0(\PIXROW_DEL_reg[0] ),
.I1(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I2(\PIXROW_DEL_reg[1] ),
.O(\PIX_ROW_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\PIX_ROW_ADDRESS[2]_i_1
(.I0(\PIXROW_DEL_reg[0] ),
.I1(\PIXROW_DEL_reg[1] ),
.I2(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I3(D),
.O(\PIX_ROW_ADDRESS[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000010000000))
\PIX_ROW_ADDRESS[2]_i_2
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.I2(\PIXCOL_DEL_reg[2] ),
.I3(\PIXCOL_DEL_reg[1] ),
.I4(\PIXCOL_DEL_reg[0] ),
.I5(\PIX_ROW_ADDRESS[2]_i_3_n_0 ),
.O(\PIX_ROW_ADDRESS[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF7))
\PIX_ROW_ADDRESS[2]_i_3
(.I0(\COL_ADDRESS_reg_n_0_[5] ),
.I1(\COL_ADDRESS_reg_n_0_[6] ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS_reg_n_0_[3] ),
.I4(\COL_ADDRESS_reg_n_0_[4] ),
.I5(\COL_ADDRESS[6]_i_3_n_0 ),
.O(\PIX_ROW_ADDRESS[2]_i_3_n_0 ));
FDRE \PIX_ROW_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[0]_i_1_n_0 ),
.Q(\PIXROW_DEL_reg[0] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_ROW_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[1]_i_1_n_0 ),
.Q(\PIXROW_DEL_reg[1] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_ROW_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[2]_i_1_n_0 ),
.Q(D),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[10]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_6 ),
.O(ROW_ADDRESS_0[10]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[11]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_5 ),
.O(ROW_ADDRESS_0[11]));
LUT4 #(
.INIT(16'h8000))
\ROW_ADDRESS[12]_i_1
(.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I1(D),
.I2(\PIXROW_DEL_reg[0] ),
.I3(\PIXROW_DEL_reg[1] ),
.O(\ROW_ADDRESS[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[12]_i_2
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_4 ),
.O(ROW_ADDRESS_0[12]));
LUT6 #(
.INIT(64'h0040000000000000))
\ROW_ADDRESS[12]_i_3
(.I0(ROW_ADDRESS[9]),
.I1(ROW_ADDRESS[10]),
.I2(ROW_ADDRESS[7]),
.I3(ROW_ADDRESS[8]),
.I4(ROW_ADDRESS[11]),
.I5(ROW_ADDRESS[12]),
.O(\ROW_ADDRESS[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\ROW_ADDRESS[12]_i_4
(.I0(ROW_ADDRESS[6]),
.I1(ROW_ADDRESS[5]),
.I2(ROW_ADDRESS[3]),
.I3(ROW_ADDRESS[4]),
.I4(ROW_ADDRESS[1]),
.I5(ROW_ADDRESS[2]),
.O(\ROW_ADDRESS[12]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[1]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_7 ),
.O(ROW_ADDRESS_0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[2]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_6 ),
.O(ROW_ADDRESS_0[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[3]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_5 ),
.O(ROW_ADDRESS_0[3]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[4]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_4 ),
.O(ROW_ADDRESS_0[4]));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[4]_i_5
(.I0(ROW_ADDRESS[2]),
.O(\ROW_ADDRESS[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[5]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_7 ),
.O(ROW_ADDRESS_0[5]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[6]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_6 ),
.O(ROW_ADDRESS_0[6]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[7]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_5 ),
.O(ROW_ADDRESS_0[7]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[8]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_4 ),
.O(ROW_ADDRESS_0[8]));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[8]_i_5
(.I0(ROW_ADDRESS[6]),
.O(\ROW_ADDRESS[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[8]_i_6
(.I0(ROW_ADDRESS[5]),
.O(\ROW_ADDRESS[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[9]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_7 ),
.O(ROW_ADDRESS_0[9]));
FDRE \ROW_ADDRESS_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[10]),
.Q(ROW_ADDRESS[10]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[11]),
.Q(ROW_ADDRESS[11]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[12]),
.Q(ROW_ADDRESS[12]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[12]_i_5
(.CI(\ROW_ADDRESS_reg[8]_i_2_n_0 ),
.CO(\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\ROW_ADDRESS_reg[12]_i_5_n_4 ,\ROW_ADDRESS_reg[12]_i_5_n_5 ,\ROW_ADDRESS_reg[12]_i_5_n_6 ,\ROW_ADDRESS_reg[12]_i_5_n_7 }),
.S(ROW_ADDRESS[12:9]));
FDRE \ROW_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[1]),
.Q(ROW_ADDRESS[1]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[2]),
.Q(ROW_ADDRESS[2]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[3]),
.Q(ROW_ADDRESS[3]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[4]),
.Q(ROW_ADDRESS[4]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[4]_i_2
(.CI(1'b0),
.CO({\ROW_ADDRESS_reg[4]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[2],1'b0}),
.O({\ROW_ADDRESS_reg[4]_i_2_n_4 ,\ROW_ADDRESS_reg[4]_i_2_n_5 ,\ROW_ADDRESS_reg[4]_i_2_n_6 ,\ROW_ADDRESS_reg[4]_i_2_n_7 }),
.S({ROW_ADDRESS[4:3],\ROW_ADDRESS[4]_i_5_n_0 ,ROW_ADDRESS[1]}));
FDRE \ROW_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[5]),
.Q(ROW_ADDRESS[5]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[6]),
.Q(ROW_ADDRESS[6]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[7]),
.Q(ROW_ADDRESS[7]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[8]),
.Q(ROW_ADDRESS[8]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[8]_i_2
(.CI(\ROW_ADDRESS_reg[4]_i_2_n_0 ),
.CO({\ROW_ADDRESS_reg[8]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
.O({\ROW_ADDRESS_reg[8]_i_2_n_4 ,\ROW_ADDRESS_reg[8]_i_2_n_5 ,\ROW_ADDRESS_reg[8]_i_2_n_6 ,\ROW_ADDRESS_reg[8]_i_2_n_7 }),
.S({ROW_ADDRESS[8:7],\ROW_ADDRESS[8]_i_5_n_0 ,\ROW_ADDRESS[8]_i_6_n_0 }));
FDRE \ROW_ADDRESS_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[9]),
.Q(ROW_ADDRESS[9]),
.R(INTERNAL_RST_reg));
LUT4 #(
.INIT(16'hFFD0))
VBLANK_i_1
(.I0(VBLANK_i_2_n_0),
.I1(VBLANK_i_3_n_0),
.I2(VBLANK_reg_n_0),
.I3(VBLANK_i_4_n_0),
.O(VBLANK_i_1_n_0));
LUT5 #(
.INIT(32'h00000004))
VBLANK_i_2
(.I0(VTIMER[7]),
.I1(VTIMER_EN),
.I2(VTIMER[8]),
.I3(VTIMER[9]),
.I4(VTIMER[6]),
.O(VBLANK_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFBFFFFFFFFFF))
VBLANK_i_3
(.I0(VTIMER[2]),
.I1(VTIMER[0]),
.I2(VTIMER[1]),
.I3(VTIMER[5]),
.I4(VTIMER[4]),
.I5(VTIMER[3]),
.O(VBLANK_i_3_n_0));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAABA))
VBLANK_i_4
(.I0(INTERNAL_RST_reg),
.I1(VBLANK_i_5_n_0),
.I2(VTIMER_EN),
.I3(VBLANK_i_6_n_0),
.I4(VTIMER[6]),
.I5(VBLANK_i_7_n_0),
.O(VBLANK_i_4_n_0));
LUT3 #(
.INIT(8'hFE))
VBLANK_i_5
(.I0(VTIMER[3]),
.I1(VTIMER[5]),
.I2(VTIMER[4]),
.O(VBLANK_i_5_n_0));
LUT3 #(
.INIT(8'hFB))
VBLANK_i_6
(.I0(VTIMER[1]),
.I1(VTIMER[0]),
.I2(VTIMER[2]),
.O(VBLANK_i_6_n_0));
LUT3 #(
.INIT(8'hDF))
VBLANK_i_7
(.I0(VTIMER[9]),
.I1(VTIMER[8]),
.I2(VTIMER[7]),
.O(VBLANK_i_7_n_0));
FDRE VBLANK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VBLANK_i_1_n_0),
.Q(VBLANK_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h1))
\VTIMER[0]_i_1
(.I0(VTIMER[0]),
.I1(\VTIMER[2]_i_2_n_0 ),
.O(\VTIMER[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h06))
\VTIMER[1]_i_1
(.I0(VTIMER[0]),
.I1(VTIMER[1]),
.I2(\VTIMER[2]_i_2_n_0 ),
.O(VTIMER_1[1]));
LUT4 #(
.INIT(16'h0078))
\VTIMER[2]_i_1
(.I0(VTIMER[1]),
.I1(VTIMER[0]),
.I2(VTIMER[2]),
.I3(\VTIMER[2]_i_2_n_0 ),
.O(VTIMER_1[2]));
LUT6 #(
.INIT(64'h0222000000000000))
\VTIMER[2]_i_2
(.I0(\VTIMER[2]_i_3_n_0 ),
.I1(VTIMER[5]),
.I2(VTIMER[3]),
.I3(VTIMER[4]),
.I4(VTIMER[1]),
.I5(VTIMER[2]),
.O(\VTIMER[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000400000))
\VTIMER[2]_i_3
(.I0(VTIMER[8]),
.I1(VTIMER[9]),
.I2(VTIMER[4]),
.I3(VTIMER[5]),
.I4(VTIMER[7]),
.I5(VTIMER[6]),
.O(\VTIMER[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\VTIMER[3]_i_1
(.I0(VTIMER[3]),
.I1(VTIMER[2]),
.I2(VTIMER[1]),
.I3(VTIMER[0]),
.O(VTIMER_1[3]));
LUT6 #(
.INIT(64'h000000007FFF8000))
\VTIMER[4]_i_1
(.I0(VTIMER[0]),
.I1(VTIMER[1]),
.I2(VTIMER[2]),
.I3(VTIMER[3]),
.I4(VTIMER[4]),
.I5(\VTIMER[9]_i_3_n_0 ),
.O(VTIMER_1[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\VTIMER[5]_i_1
(.I0(VTIMER[5]),
.I1(VTIMER[4]),
.I2(VTIMER[0]),
.I3(VTIMER[1]),
.I4(VTIMER[2]),
.I5(VTIMER[3]),
.O(\VTIMER[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\VTIMER[6]_i_1
(.I0(VTIMER[6]),
.I1(\VTIMER[9]_i_2_n_0 ),
.O(VTIMER_1[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h1540))
\VTIMER[7]_i_1
(.I0(\VTIMER[9]_i_3_n_0 ),
.I1(\VTIMER[9]_i_2_n_0 ),
.I2(VTIMER[6]),
.I3(VTIMER[7]),
.O(VTIMER_1[7]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6AAA))
\VTIMER[8]_i_1
(.I0(VTIMER[8]),
.I1(VTIMER[7]),
.I2(VTIMER[6]),
.I3(\VTIMER[9]_i_2_n_0 ),
.O(VTIMER_1[8]));
LUT6 #(
.INIT(64'h000000006AAAAAAA))
\VTIMER[9]_i_1
(.I0(VTIMER[9]),
.I1(\VTIMER[9]_i_2_n_0 ),
.I2(VTIMER[6]),
.I3(VTIMER[7]),
.I4(VTIMER[8]),
.I5(\VTIMER[9]_i_3_n_0 ),
.O(VTIMER_1[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\VTIMER[9]_i_2
(.I0(VTIMER[5]),
.I1(VTIMER[4]),
.I2(VTIMER[0]),
.I3(VTIMER[1]),
.I4(VTIMER[2]),
.I5(VTIMER[3]),
.O(\VTIMER[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000020))
\VTIMER[9]_i_3
(.I0(VTIMER[7]),
.I1(\VTIMER[9]_i_4_n_0 ),
.I2(VTIMER[9]),
.I3(VTIMER[8]),
.I4(\VTIMER[9]_i_5_n_0 ),
.O(\VTIMER[9]_i_3_n_0 ));
LUT4 #(
.INIT(16'hF8FF))
\VTIMER[9]_i_4
(.I0(VTIMER[6]),
.I1(VTIMER[7]),
.I2(VTIMER[5]),
.I3(VTIMER[4]),
.O(\VTIMER[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF7F7F7))
\VTIMER[9]_i_5
(.I0(VTIMER[1]),
.I1(VTIMER[2]),
.I2(VTIMER[0]),
.I3(VTIMER[4]),
.I4(VTIMER[3]),
.I5(VTIMER[5]),
.O(\VTIMER[9]_i_5_n_0 ));
LUT2 #(
.INIT(4'hE))
VTIMER_EN_i_1
(.I0(INTERNAL_RST_reg),
.I1(\HTIMER[4]_i_2_n_0 ),
.O(VTIMER_EN_i_1_n_0));
FDRE VTIMER_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VTIMER_EN_i_1_n_0),
.Q(VTIMER_EN),
.R(1'b0));
FDRE \VTIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(\VTIMER[0]_i_1_n_0 ),
.Q(VTIMER[0]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[1]),
.Q(VTIMER[1]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[2]),
.Q(VTIMER[2]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[3]),
.Q(VTIMER[3]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[4]),
.Q(VTIMER[4]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(\VTIMER[5]_i_1_n_0 ),
.Q(VTIMER[5]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[6]),
.Q(VTIMER[6]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[7]),
.Q(VTIMER[7]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[8]),
.Q(VTIMER[8]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[9]),
.Q(VTIMER[9]),
.R(INTERNAL_RST_reg));
endmodule
module main_0
(IN1_STB,
E,
\PWM_VAL_reg[7] ,
\PWM_VAL_reg[7]_0 ,
\s_output_rs232_tx_reg[7]_0 ,
OUT1_ACK,
output_led_r,
output_led_g,
output_led_b,
output_rs232_tx,
ETH_CLK_OBUF,
INTERNAL_RST_reg,
S_IN1_ACK_reg,
OUT1,
OUT1_STB,
IN1_ACK);
output IN1_STB;
output [0:0]E;
output [0:0]\PWM_VAL_reg[7] ;
output [0:0]\PWM_VAL_reg[7]_0 ;
output [0:0]\s_output_rs232_tx_reg[7]_0 ;
output OUT1_ACK;
output [7:0]output_led_r;
output [7:0]output_led_g;
output [7:0]output_led_b;
output [7:0]output_rs232_tx;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
input S_IN1_ACK_reg;
input [7:0]OUT1;
input OUT1_STB;
input IN1_ACK;
wire [0:0]E;
wire ETH_CLK_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]OUT1;
wire OUT1_ACK;
wire OUT1_STB;
wire [0:0]\PWM_VAL_reg[7] ;
wire [0:0]\PWM_VAL_reg[7]_0 ;
wire S_IN1_ACK_reg;
wire [3:0]address_a;
wire [3:0]address_a_2;
wire [3:0]address_b_2;
wire [3:0]address_z;
wire [3:0]address_z_2;
wire [3:0]address_z_3;
wire \address_z_3[3]_i_1_n_0 ;
wire [16:1]data2;
wire data4;
wire data6;
wire [31:0]data7;
wire data8;
wire instruction0;
wire [15:4]literal_2;
wire [31:0]load_data;
wire memory_reg_0_i_2_n_0;
wire memory_reg_1_ENARDEN_cooolgate_en_sig_1;
wire memory_reg_2_ENARDEN_cooolgate_en_sig_2;
wire memory_reg_3_ENARDEN_cooolgate_en_sig_3;
wire memory_reg_4_ENARDEN_cooolgate_en_sig_4;
wire memory_reg_5_ENARDEN_cooolgate_en_sig_5;
wire memory_reg_6_ENARDEN_cooolgate_en_sig_6;
wire memory_reg_7_ENARDEN_cooolgate_en_sig_7;
wire [4:0]opcode;
wire [4:0]opcode_2;
wire opcode_20;
wire operand_a1;
wire operand_b1;
wire out0;
wire [7:0]output_led_b;
wire [7:0]output_led_g;
wire [7:0]output_led_r;
wire [7:0]output_rs232_tx;
wire p_0_in;
wire \program_counter[0]_i_2_n_0 ;
wire \program_counter[0]_i_3_n_0 ;
wire \program_counter[10]_i_2_n_0 ;
wire \program_counter[10]_i_3_n_0 ;
wire \program_counter[11]_i_2_n_0 ;
wire \program_counter[11]_i_3_n_0 ;
wire \program_counter[12]_i_2_n_0 ;
wire \program_counter[12]_i_4_n_0 ;
wire \program_counter[13]_i_2_n_0 ;
wire \program_counter[13]_i_3_n_0 ;
wire \program_counter[14]_i_2_n_0 ;
wire \program_counter[14]_i_3_n_0 ;
wire \program_counter[15]_i_12_n_0 ;
wire \program_counter[15]_i_13_n_0 ;
wire \program_counter[15]_i_14_n_0 ;
wire \program_counter[15]_i_15_n_0 ;
wire \program_counter[15]_i_16_n_0 ;
wire \program_counter[15]_i_17_n_0 ;
wire \program_counter[15]_i_3_n_0 ;
wire \program_counter[15]_i_4_n_0 ;
wire \program_counter[15]_i_6_n_0 ;
wire \program_counter[15]_i_7_n_0 ;
wire \program_counter[15]_i_8_n_0 ;
wire \program_counter[1]_i_2_n_0 ;
wire \program_counter[1]_i_3_n_0 ;
wire \program_counter[1]_i_4_n_0 ;
wire \program_counter[2]_i_2_n_0 ;
wire \program_counter[2]_i_3_n_0 ;
wire \program_counter[3]_i_2_n_0 ;
wire \program_counter[3]_i_3_n_0 ;
wire \program_counter[4]_i_2_n_0 ;
wire \program_counter[4]_i_4_n_0 ;
wire \program_counter[5]_i_2_n_0 ;
wire \program_counter[5]_i_3_n_0 ;
wire \program_counter[6]_i_2_n_0 ;
wire \program_counter[6]_i_3_n_0 ;
wire \program_counter[6]_i_4_n_0 ;
wire \program_counter[7]_i_2_n_0 ;
wire \program_counter[7]_i_3_n_0 ;
wire \program_counter[8]_i_2_n_0 ;
wire \program_counter[8]_i_4_n_0 ;
wire \program_counter[8]_i_5_n_0 ;
wire \program_counter[8]_i_6_n_0 ;
wire \program_counter[8]_i_7_n_0 ;
wire \program_counter[9]_i_2_n_0 ;
wire \program_counter[9]_i_3_n_0 ;
wire [15:0]program_counter_1;
wire [15:0]program_counter_2;
wire \program_counter_reg[12]_i_3_n_0 ;
wire \program_counter_reg[12]_i_3_n_4 ;
wire \program_counter_reg[12]_i_3_n_5 ;
wire \program_counter_reg[12]_i_3_n_6 ;
wire \program_counter_reg[12]_i_3_n_7 ;
wire \program_counter_reg[15]_i_5_n_5 ;
wire \program_counter_reg[15]_i_5_n_6 ;
wire \program_counter_reg[15]_i_5_n_7 ;
wire \program_counter_reg[4]_i_3_n_0 ;
wire \program_counter_reg[4]_i_3_n_4 ;
wire \program_counter_reg[4]_i_3_n_5 ;
wire \program_counter_reg[4]_i_3_n_6 ;
wire \program_counter_reg[4]_i_3_n_7 ;
wire \program_counter_reg[8]_i_3_n_0 ;
wire \program_counter_reg[8]_i_3_n_4 ;
wire \program_counter_reg[8]_i_3_n_5 ;
wire \program_counter_reg[8]_i_3_n_6 ;
wire \program_counter_reg[8]_i_3_n_7 ;
wire \program_counter_reg_n_0_[0] ;
wire \program_counter_reg_n_0_[10] ;
wire \program_counter_reg_n_0_[11] ;
wire \program_counter_reg_n_0_[12] ;
wire \program_counter_reg_n_0_[13] ;
wire \program_counter_reg_n_0_[14] ;
wire \program_counter_reg_n_0_[15] ;
wire \program_counter_reg_n_0_[1] ;
wire \program_counter_reg_n_0_[2] ;
wire \program_counter_reg_n_0_[3] ;
wire \program_counter_reg_n_0_[4] ;
wire \program_counter_reg_n_0_[5] ;
wire \program_counter_reg_n_0_[6] ;
wire \program_counter_reg_n_0_[7] ;
wire \program_counter_reg_n_0_[8] ;
wire \program_counter_reg_n_0_[9] ;
wire program_counter_reg_rep_0_i_10_n_0;
wire program_counter_reg_rep_0_i_11_n_0;
wire program_counter_reg_rep_0_i_12_n_0;
wire program_counter_reg_rep_0_i_13_n_0;
wire program_counter_reg_rep_0_i_14_n_0;
wire program_counter_reg_rep_0_i_15_n_0;
wire program_counter_reg_rep_0_i_16_n_0;
wire program_counter_reg_rep_0_i_17_n_0;
wire program_counter_reg_rep_0_i_1_n_0;
wire program_counter_reg_rep_0_i_2_n_0;
wire program_counter_reg_rep_0_i_3_n_0;
wire program_counter_reg_rep_0_i_4_n_0;
wire program_counter_reg_rep_0_i_5_n_0;
wire program_counter_reg_rep_0_i_6_n_0;
wire program_counter_reg_rep_0_i_7_n_0;
wire program_counter_reg_rep_0_i_8_n_0;
wire program_counter_reg_rep_0_i_9_n_0;
wire program_counter_reg_rep_0_n_20;
wire program_counter_reg_rep_0_n_21;
wire program_counter_reg_rep_0_n_22;
wire program_counter_reg_rep_0_n_23;
wire program_counter_reg_rep_0_n_24;
wire program_counter_reg_rep_0_n_25;
wire program_counter_reg_rep_0_n_26;
wire program_counter_reg_rep_0_n_27;
wire program_counter_reg_rep_0_n_28;
wire program_counter_reg_rep_0_n_29;
wire program_counter_reg_rep_0_n_30;
wire program_counter_reg_rep_0_n_31;
wire program_counter_reg_rep_0_n_32;
wire program_counter_reg_rep_0_n_33;
wire program_counter_reg_rep_0_n_34;
wire program_counter_reg_rep_0_n_35;
wire program_counter_reg_rep_1_REGCEAREGCE_cooolgate_en_sig_11;
wire [31:0]read_input;
wire \read_input[0]_i_1_n_0 ;
wire \read_input[10]_i_1_n_0 ;
wire \read_input[11]_i_1_n_0 ;
wire \read_input[12]_i_1_n_0 ;
wire \read_input[13]_i_1_n_0 ;
wire \read_input[14]_i_1_n_0 ;
wire \read_input[15]_i_1_n_0 ;
wire \read_input[16]_i_1_n_0 ;
wire \read_input[17]_i_1_n_0 ;
wire \read_input[18]_i_1_n_0 ;
wire \read_input[19]_i_1_n_0 ;
wire \read_input[1]_i_1_n_0 ;
wire \read_input[20]_i_1_n_0 ;
wire \read_input[21]_i_1_n_0 ;
wire \read_input[22]_i_1_n_0 ;
wire \read_input[23]_i_1_n_0 ;
wire \read_input[24]_i_1_n_0 ;
wire \read_input[25]_i_1_n_0 ;
wire \read_input[26]_i_1_n_0 ;
wire \read_input[27]_i_1_n_0 ;
wire \read_input[28]_i_1_n_0 ;
wire \read_input[29]_i_1_n_0 ;
wire \read_input[2]_i_1_n_0 ;
wire \read_input[30]_i_1_n_0 ;
wire \read_input[31]_i_1_n_0 ;
wire \read_input[31]_i_2_n_0 ;
wire \read_input[31]_i_3_n_0 ;
wire \read_input[31]_i_4_n_0 ;
wire \read_input[31]_i_5_n_0 ;
wire \read_input[3]_i_1_n_0 ;
wire \read_input[4]_i_1_n_0 ;
wire \read_input[5]_i_1_n_0 ;
wire \read_input[6]_i_1_n_0 ;
wire \read_input[7]_i_1_n_0 ;
wire \read_input[8]_i_1_n_0 ;
wire \read_input[9]_i_1_n_0 ;
wire [31:0]register_a;
wire [31:0]register_b;
wire [31:0]result;
wire \result[0]_i_100_n_0 ;
wire \result[0]_i_101_n_0 ;
wire \result[0]_i_102_n_0 ;
wire \result[0]_i_103_n_0 ;
wire \result[0]_i_104_n_0 ;
wire \result[0]_i_105_n_0 ;
wire \result[0]_i_106_n_0 ;
wire \result[0]_i_107_n_0 ;
wire \result[0]_i_108_n_0 ;
wire \result[0]_i_109_n_0 ;
wire \result[0]_i_110_n_0 ;
wire \result[0]_i_111_n_0 ;
wire \result[0]_i_11_n_0 ;
wire \result[0]_i_13_n_0 ;
wire \result[0]_i_16_n_0 ;
wire \result[0]_i_17_n_0 ;
wire \result[0]_i_18_n_0 ;
wire \result[0]_i_19_n_0 ;
wire \result[0]_i_1_n_0 ;
wire \result[0]_i_20_n_0 ;
wire \result[0]_i_21_n_0 ;
wire \result[0]_i_22_n_0 ;
wire \result[0]_i_23_n_0 ;
wire \result[0]_i_25_n_0 ;
wire \result[0]_i_26_n_0 ;
wire \result[0]_i_27_n_0 ;
wire \result[0]_i_28_n_0 ;
wire \result[0]_i_29_n_0 ;
wire \result[0]_i_2_n_0 ;
wire \result[0]_i_31_n_0 ;
wire \result[0]_i_32_n_0 ;
wire \result[0]_i_33_n_0 ;
wire \result[0]_i_35_n_0 ;
wire \result[0]_i_36_n_0 ;
wire \result[0]_i_37_n_0 ;
wire \result[0]_i_38_n_0 ;
wire \result[0]_i_39_n_0 ;
wire \result[0]_i_3_n_0 ;
wire \result[0]_i_40_n_0 ;
wire \result[0]_i_41_n_0 ;
wire \result[0]_i_42_n_0 ;
wire \result[0]_i_43_n_0 ;
wire \result[0]_i_44_n_0 ;
wire \result[0]_i_45_n_0 ;
wire \result[0]_i_46_n_0 ;
wire \result[0]_i_47_n_0 ;
wire \result[0]_i_48_n_0 ;
wire \result[0]_i_49_n_0 ;
wire \result[0]_i_4_n_0 ;
wire \result[0]_i_50_n_0 ;
wire \result[0]_i_51_n_0 ;
wire \result[0]_i_53_n_0 ;
wire \result[0]_i_54_n_0 ;
wire \result[0]_i_55_n_0 ;
wire \result[0]_i_56_n_0 ;
wire \result[0]_i_58_n_0 ;
wire \result[0]_i_59_n_0 ;
wire \result[0]_i_5_n_0 ;
wire \result[0]_i_60_n_0 ;
wire \result[0]_i_61_n_0 ;
wire \result[0]_i_62_n_0 ;
wire \result[0]_i_63_n_0 ;
wire \result[0]_i_65_n_0 ;
wire \result[0]_i_66_n_0 ;
wire \result[0]_i_67_n_0 ;
wire \result[0]_i_68_n_0 ;
wire \result[0]_i_69_n_0 ;
wire \result[0]_i_6_n_0 ;
wire \result[0]_i_70_n_0 ;
wire \result[0]_i_71_n_0 ;
wire \result[0]_i_72_n_0 ;
wire \result[0]_i_73_n_0 ;
wire \result[0]_i_74_n_0 ;
wire \result[0]_i_75_n_0 ;
wire \result[0]_i_76_n_0 ;
wire \result[0]_i_77_n_0 ;
wire \result[0]_i_78_n_0 ;
wire \result[0]_i_79_n_0 ;
wire \result[0]_i_7_n_0 ;
wire \result[0]_i_81_n_0 ;
wire \result[0]_i_82_n_0 ;
wire \result[0]_i_83_n_0 ;
wire \result[0]_i_84_n_0 ;
wire \result[0]_i_85_n_0 ;
wire \result[0]_i_86_n_0 ;
wire \result[0]_i_87_n_0 ;
wire \result[0]_i_88_n_0 ;
wire \result[0]_i_89_n_0 ;
wire \result[0]_i_8_n_0 ;
wire \result[0]_i_90_n_0 ;
wire \result[0]_i_91_n_0 ;
wire \result[0]_i_92_n_0 ;
wire \result[0]_i_93_n_0 ;
wire \result[0]_i_94_n_0 ;
wire \result[0]_i_95_n_0 ;
wire \result[0]_i_96_n_0 ;
wire \result[0]_i_97_n_0 ;
wire \result[0]_i_98_n_0 ;
wire \result[0]_i_99_n_0 ;
wire \result[0]_i_9_n_0 ;
wire \result[10]_i_10_n_0 ;
wire \result[10]_i_11_n_0 ;
wire \result[10]_i_1_n_0 ;
wire \result[10]_i_2_n_0 ;
wire \result[10]_i_3_n_0 ;
wire \result[10]_i_4_n_0 ;
wire \result[10]_i_5_n_0 ;
wire \result[10]_i_6_n_0 ;
wire \result[10]_i_7_n_0 ;
wire \result[10]_i_8_n_0 ;
wire \result[10]_i_9_n_0 ;
wire \result[11]_i_12_n_0 ;
wire \result[11]_i_14_n_0 ;
wire \result[11]_i_15_n_0 ;
wire \result[11]_i_16_n_0 ;
wire \result[11]_i_17_n_0 ;
wire \result[11]_i_18_n_0 ;
wire \result[11]_i_19_n_0 ;
wire \result[11]_i_1_n_0 ;
wire \result[11]_i_20_n_0 ;
wire \result[11]_i_21_n_0 ;
wire \result[11]_i_22_n_0 ;
wire \result[11]_i_23_n_0 ;
wire \result[11]_i_24_n_0 ;
wire \result[11]_i_25_n_0 ;
wire \result[11]_i_26_n_0 ;
wire \result[11]_i_2_n_0 ;
wire \result[11]_i_3_n_0 ;
wire \result[11]_i_4_n_0 ;
wire \result[11]_i_5_n_0 ;
wire \result[11]_i_6_n_0 ;
wire \result[11]_i_7_n_0 ;
wire \result[11]_i_8_n_0 ;
wire \result[11]_i_9_n_0 ;
wire \result[12]_i_11_n_0 ;
wire \result[12]_i_12_n_0 ;
wire \result[12]_i_1_n_0 ;
wire \result[12]_i_2_n_0 ;
wire \result[12]_i_3_n_0 ;
wire \result[12]_i_4_n_0 ;
wire \result[12]_i_5_n_0 ;
wire \result[12]_i_6_n_0 ;
wire \result[12]_i_7_n_0 ;
wire \result[12]_i_8_n_0 ;
wire \result[12]_i_9_n_0 ;
wire \result[13]_i_10_n_0 ;
wire \result[13]_i_11_n_0 ;
wire \result[13]_i_1_n_0 ;
wire \result[13]_i_2_n_0 ;
wire \result[13]_i_3_n_0 ;
wire \result[13]_i_4_n_0 ;
wire \result[13]_i_5_n_0 ;
wire \result[13]_i_6_n_0 ;
wire \result[13]_i_7_n_0 ;
wire \result[13]_i_8_n_0 ;
wire \result[13]_i_9_n_0 ;
wire \result[14]_i_1_n_0 ;
wire \result[14]_i_2_n_0 ;
wire \result[14]_i_3_n_0 ;
wire \result[14]_i_4_n_0 ;
wire \result[14]_i_5_n_0 ;
wire \result[14]_i_6_n_0 ;
wire \result[14]_i_7_n_0 ;
wire \result[14]_i_8_n_0 ;
wire \result[14]_i_9_n_0 ;
wire \result[15]_i_10_n_0 ;
wire \result[15]_i_11_n_0 ;
wire \result[15]_i_12_n_0 ;
wire \result[15]_i_13_n_0 ;
wire \result[15]_i_14_n_0 ;
wire \result[15]_i_15_n_0 ;
wire \result[15]_i_16_n_0 ;
wire \result[15]_i_17_n_0 ;
wire \result[15]_i_18_n_0 ;
wire \result[15]_i_19_n_0 ;
wire \result[15]_i_1_n_0 ;
wire \result[15]_i_2_n_0 ;
wire \result[15]_i_3_n_0 ;
wire \result[15]_i_4_n_0 ;
wire \result[15]_i_5_n_0 ;
wire \result[15]_i_6_n_0 ;
wire \result[15]_i_8_n_0 ;
wire \result[16]_i_10_n_0 ;
wire \result[16]_i_12_n_0 ;
wire \result[16]_i_13_n_0 ;
wire \result[16]_i_14_n_0 ;
wire \result[16]_i_15_n_0 ;
wire \result[16]_i_16_n_0 ;
wire \result[16]_i_17_n_0 ;
wire \result[16]_i_18_n_0 ;
wire \result[16]_i_19_n_0 ;
wire \result[16]_i_1_n_0 ;
wire \result[16]_i_2_n_0 ;
wire \result[16]_i_3_n_0 ;
wire \result[16]_i_4_n_0 ;
wire \result[16]_i_5_n_0 ;
wire \result[16]_i_6_n_0 ;
wire \result[16]_i_7_n_0 ;
wire \result[16]_i_8_n_0 ;
wire \result[17]_i_10_n_0 ;
wire \result[17]_i_11_n_0 ;
wire \result[17]_i_12_n_0 ;
wire \result[17]_i_1_n_0 ;
wire \result[17]_i_2_n_0 ;
wire \result[17]_i_3_n_0 ;
wire \result[17]_i_4_n_0 ;
wire \result[17]_i_5_n_0 ;
wire \result[17]_i_6_n_0 ;
wire \result[17]_i_7_n_0 ;
wire \result[17]_i_8_n_0 ;
wire \result[17]_i_9_n_0 ;
wire \result[18]_i_10_n_0 ;
wire \result[18]_i_11_n_0 ;
wire \result[18]_i_12_n_0 ;
wire \result[18]_i_1_n_0 ;
wire \result[18]_i_2_n_0 ;
wire \result[18]_i_3_n_0 ;
wire \result[18]_i_4_n_0 ;
wire \result[18]_i_5_n_0 ;
wire \result[18]_i_6_n_0 ;
wire \result[18]_i_7_n_0 ;
wire \result[18]_i_8_n_0 ;
wire \result[18]_i_9_n_0 ;
wire \result[19]_i_10_n_0 ;
wire \result[19]_i_13_n_0 ;
wire \result[19]_i_14_n_0 ;
wire \result[19]_i_15_n_0 ;
wire \result[19]_i_16_n_0 ;
wire \result[19]_i_17_n_0 ;
wire \result[19]_i_18_n_0 ;
wire \result[19]_i_19_n_0 ;
wire \result[19]_i_1_n_0 ;
wire \result[19]_i_20_n_0 ;
wire \result[19]_i_21_n_0 ;
wire \result[19]_i_22_n_0 ;
wire \result[19]_i_23_n_0 ;
wire \result[19]_i_24_n_0 ;
wire \result[19]_i_25_n_0 ;
wire \result[19]_i_26_n_0 ;
wire \result[19]_i_27_n_0 ;
wire \result[19]_i_2_n_0 ;
wire \result[19]_i_3_n_0 ;
wire \result[19]_i_4_n_0 ;
wire \result[19]_i_5_n_0 ;
wire \result[19]_i_6_n_0 ;
wire \result[19]_i_8_n_0 ;
wire \result[19]_i_9_n_0 ;
wire \result[1]_i_1_n_0 ;
wire \result[1]_i_2_n_0 ;
wire \result[1]_i_3_n_0 ;
wire \result[1]_i_4_n_0 ;
wire \result[1]_i_5_n_0 ;
wire \result[1]_i_6_n_0 ;
wire \result[1]_i_7_n_0 ;
wire \result[1]_i_8_n_0 ;
wire \result[1]_i_9_n_0 ;
wire \result[20]_i_10_n_0 ;
wire \result[20]_i_11_n_0 ;
wire \result[20]_i_1_n_0 ;
wire \result[20]_i_2_n_0 ;
wire \result[20]_i_3_n_0 ;
wire \result[20]_i_4_n_0 ;
wire \result[20]_i_5_n_0 ;
wire \result[20]_i_6_n_0 ;
wire \result[20]_i_7_n_0 ;
wire \result[20]_i_8_n_0 ;
wire \result[20]_i_9_n_0 ;
wire \result[21]_i_10_n_0 ;
wire \result[21]_i_11_n_0 ;
wire \result[21]_i_1_n_0 ;
wire \result[21]_i_2_n_0 ;
wire \result[21]_i_3_n_0 ;
wire \result[21]_i_4_n_0 ;
wire \result[21]_i_5_n_0 ;
wire \result[21]_i_6_n_0 ;
wire \result[21]_i_7_n_0 ;
wire \result[21]_i_8_n_0 ;
wire \result[21]_i_9_n_0 ;
wire \result[22]_i_10_n_0 ;
wire \result[22]_i_11_n_0 ;
wire \result[22]_i_1_n_0 ;
wire \result[22]_i_2_n_0 ;
wire \result[22]_i_3_n_0 ;
wire \result[22]_i_4_n_0 ;
wire \result[22]_i_5_n_0 ;
wire \result[22]_i_6_n_0 ;
wire \result[22]_i_7_n_0 ;
wire \result[22]_i_8_n_0 ;
wire \result[22]_i_9_n_0 ;
wire \result[23]_i_10_n_0 ;
wire \result[23]_i_12_n_0 ;
wire \result[23]_i_13_n_0 ;
wire \result[23]_i_14_n_0 ;
wire \result[23]_i_15_n_0 ;
wire \result[23]_i_16_n_0 ;
wire \result[23]_i_17_n_0 ;
wire \result[23]_i_18_n_0 ;
wire \result[23]_i_19_n_0 ;
wire \result[23]_i_1_n_0 ;
wire \result[23]_i_20_n_0 ;
wire \result[23]_i_21_n_0 ;
wire \result[23]_i_2_n_0 ;
wire \result[23]_i_3_n_0 ;
wire \result[23]_i_4_n_0 ;
wire \result[23]_i_5_n_0 ;
wire \result[23]_i_6_n_0 ;
wire \result[23]_i_8_n_0 ;
wire \result[23]_i_9_n_0 ;
wire \result[24]_i_10_n_0 ;
wire \result[24]_i_11_n_0 ;
wire \result[24]_i_1_n_0 ;
wire \result[24]_i_2_n_0 ;
wire \result[24]_i_3_n_0 ;
wire \result[24]_i_4_n_0 ;
wire \result[24]_i_5_n_0 ;
wire \result[24]_i_6_n_0 ;
wire \result[24]_i_7_n_0 ;
wire \result[24]_i_8_n_0 ;
wire \result[24]_i_9_n_0 ;
wire \result[25]_i_10_n_0 ;
wire \result[25]_i_11_n_0 ;
wire \result[25]_i_1_n_0 ;
wire \result[25]_i_2_n_0 ;
wire \result[25]_i_3_n_0 ;
wire \result[25]_i_4_n_0 ;
wire \result[25]_i_5_n_0 ;
wire \result[25]_i_6_n_0 ;
wire \result[25]_i_7_n_0 ;
wire \result[25]_i_8_n_0 ;
wire \result[25]_i_9_n_0 ;
wire \result[26]_i_10_n_0 ;
wire \result[26]_i_11_n_0 ;
wire \result[26]_i_1_n_0 ;
wire \result[26]_i_2_n_0 ;
wire \result[26]_i_3_n_0 ;
wire \result[26]_i_4_n_0 ;
wire \result[26]_i_5_n_0 ;
wire \result[26]_i_6_n_0 ;
wire \result[26]_i_7_n_0 ;
wire \result[26]_i_8_n_0 ;
wire \result[26]_i_9_n_0 ;
wire \result[27]_i_11_n_0 ;
wire \result[27]_i_12_n_0 ;
wire \result[27]_i_13_n_0 ;
wire \result[27]_i_14_n_0 ;
wire \result[27]_i_15_n_0 ;
wire \result[27]_i_16_n_0 ;
wire \result[27]_i_17_n_0 ;
wire \result[27]_i_19_n_0 ;
wire \result[27]_i_1_n_0 ;
wire \result[27]_i_20_n_0 ;
wire \result[27]_i_21_n_0 ;
wire \result[27]_i_22_n_0 ;
wire \result[27]_i_24_n_0 ;
wire \result[27]_i_25_n_0 ;
wire \result[27]_i_26_n_0 ;
wire \result[27]_i_27_n_0 ;
wire \result[27]_i_28_n_0 ;
wire \result[27]_i_29_n_0 ;
wire \result[27]_i_2_n_0 ;
wire \result[27]_i_30_n_0 ;
wire \result[27]_i_31_n_0 ;
wire \result[27]_i_3_n_0 ;
wire \result[27]_i_4_n_0 ;
wire \result[27]_i_5_n_0 ;
wire \result[27]_i_6_n_0 ;
wire \result[27]_i_8_n_0 ;
wire \result[27]_i_9_n_0 ;
wire \result[28]_i_10_n_0 ;
wire \result[28]_i_1_n_0 ;
wire \result[28]_i_2_n_0 ;
wire \result[28]_i_3_n_0 ;
wire \result[28]_i_4_n_0 ;
wire \result[28]_i_5_n_0 ;
wire \result[28]_i_6_n_0 ;
wire \result[28]_i_7_n_0 ;
wire \result[28]_i_8_n_0 ;
wire \result[28]_i_9_n_0 ;
wire \result[29]_i_10_n_0 ;
wire \result[29]_i_1_n_0 ;
wire \result[29]_i_2_n_0 ;
wire \result[29]_i_3_n_0 ;
wire \result[29]_i_4_n_0 ;
wire \result[29]_i_5_n_0 ;
wire \result[29]_i_6_n_0 ;
wire \result[29]_i_7_n_0 ;
wire \result[29]_i_8_n_0 ;
wire \result[29]_i_9_n_0 ;
wire \result[2]_i_1_n_0 ;
wire \result[2]_i_2_n_0 ;
wire \result[2]_i_3_n_0 ;
wire \result[2]_i_4_n_0 ;
wire \result[2]_i_5_n_0 ;
wire \result[2]_i_6_n_0 ;
wire \result[2]_i_7_n_0 ;
wire \result[2]_i_8_n_0 ;
wire \result[2]_i_9_n_0 ;
wire \result[30]_i_10_n_0 ;
wire \result[30]_i_1_n_0 ;
wire \result[30]_i_2_n_0 ;
wire \result[30]_i_3_n_0 ;
wire \result[30]_i_4_n_0 ;
wire \result[30]_i_5_n_0 ;
wire \result[30]_i_6_n_0 ;
wire \result[30]_i_7_n_0 ;
wire \result[30]_i_8_n_0 ;
wire \result[30]_i_9_n_0 ;
wire \result[31]_i_11_n_0 ;
wire \result[31]_i_12_n_0 ;
wire \result[31]_i_13_n_0 ;
wire \result[31]_i_14_n_0 ;
wire \result[31]_i_16_n_0 ;
wire \result[31]_i_17_n_0 ;
wire \result[31]_i_18_n_0 ;
wire \result[31]_i_19_n_0 ;
wire \result[31]_i_1_n_0 ;
wire \result[31]_i_20_n_0 ;
wire \result[31]_i_21_n_0 ;
wire \result[31]_i_22_n_0 ;
wire \result[31]_i_23_n_0 ;
wire \result[31]_i_24_n_0 ;
wire \result[31]_i_25_n_0 ;
wire \result[31]_i_26_n_0 ;
wire \result[31]_i_27_n_0 ;
wire \result[31]_i_28_n_0 ;
wire \result[31]_i_29_n_0 ;
wire \result[31]_i_2_n_0 ;
wire \result[31]_i_30_n_0 ;
wire \result[31]_i_31_n_0 ;
wire \result[31]_i_32_n_0 ;
wire \result[31]_i_33_n_0 ;
wire \result[31]_i_34_n_0 ;
wire \result[31]_i_35_n_0 ;
wire \result[31]_i_36_n_0 ;
wire \result[31]_i_37_n_0 ;
wire \result[31]_i_38_n_0 ;
wire \result[31]_i_39_n_0 ;
wire \result[31]_i_3_n_0 ;
wire \result[31]_i_41_n_0 ;
wire \result[31]_i_42_n_0 ;
wire \result[31]_i_43_n_0 ;
wire \result[31]_i_44_n_0 ;
wire \result[31]_i_4_n_0 ;
wire \result[31]_i_5_n_0 ;
wire \result[31]_i_6_n_0 ;
wire \result[31]_i_7_n_0 ;
wire \result[31]_i_8_n_0 ;
wire \result[31]_i_9_n_0 ;
wire \result[3]_i_12_n_0 ;
wire \result[3]_i_13_n_0 ;
wire \result[3]_i_14_n_0 ;
wire \result[3]_i_15_n_0 ;
wire \result[3]_i_16_n_0 ;
wire \result[3]_i_17_n_0 ;
wire \result[3]_i_18_n_0 ;
wire \result[3]_i_19_n_0 ;
wire \result[3]_i_1_n_0 ;
wire \result[3]_i_20_n_0 ;
wire \result[3]_i_21_n_0 ;
wire \result[3]_i_22_n_0 ;
wire \result[3]_i_23_n_0 ;
wire \result[3]_i_24_n_0 ;
wire \result[3]_i_2_n_0 ;
wire \result[3]_i_3_n_0 ;
wire \result[3]_i_4_n_0 ;
wire \result[3]_i_5_n_0 ;
wire \result[3]_i_6_n_0 ;
wire \result[3]_i_7_n_0 ;
wire \result[3]_i_8_n_0 ;
wire \result[4]_i_10_n_0 ;
wire \result[4]_i_1_n_0 ;
wire \result[4]_i_2_n_0 ;
wire \result[4]_i_3_n_0 ;
wire \result[4]_i_4_n_0 ;
wire \result[4]_i_5_n_0 ;
wire \result[4]_i_6_n_0 ;
wire \result[4]_i_7_n_0 ;
wire \result[4]_i_8_n_0 ;
wire \result[5]_i_1_n_0 ;
wire \result[5]_i_2_n_0 ;
wire \result[5]_i_3_n_0 ;
wire \result[5]_i_4_n_0 ;
wire \result[5]_i_5_n_0 ;
wire \result[5]_i_6_n_0 ;
wire \result[5]_i_7_n_0 ;
wire \result[5]_i_8_n_0 ;
wire \result[5]_i_9_n_0 ;
wire \result[6]_i_1_n_0 ;
wire \result[6]_i_2_n_0 ;
wire \result[6]_i_3_n_0 ;
wire \result[6]_i_4_n_0 ;
wire \result[6]_i_5_n_0 ;
wire \result[6]_i_6_n_0 ;
wire \result[6]_i_7_n_0 ;
wire \result[6]_i_8_n_0 ;
wire \result[6]_i_9_n_0 ;
wire \result[7]_i_12_n_0 ;
wire \result[7]_i_14_n_0 ;
wire \result[7]_i_15_n_0 ;
wire \result[7]_i_16_n_0 ;
wire \result[7]_i_17_n_0 ;
wire \result[7]_i_18_n_0 ;
wire \result[7]_i_19_n_0 ;
wire \result[7]_i_1_n_0 ;
wire \result[7]_i_20_n_0 ;
wire \result[7]_i_21_n_0 ;
wire \result[7]_i_22_n_0 ;
wire \result[7]_i_23_n_0 ;
wire \result[7]_i_24_n_0 ;
wire \result[7]_i_25_n_0 ;
wire \result[7]_i_26_n_0 ;
wire \result[7]_i_2_n_0 ;
wire \result[7]_i_3_n_0 ;
wire \result[7]_i_4_n_0 ;
wire \result[7]_i_5_n_0 ;
wire \result[7]_i_6_n_0 ;
wire \result[7]_i_7_n_0 ;
wire \result[7]_i_8_n_0 ;
wire \result[7]_i_9_n_0 ;
wire \result[8]_i_11_n_0 ;
wire \result[8]_i_12_n_0 ;
wire \result[8]_i_1_n_0 ;
wire \result[8]_i_2_n_0 ;
wire \result[8]_i_3_n_0 ;
wire \result[8]_i_4_n_0 ;
wire \result[8]_i_5_n_0 ;
wire \result[8]_i_6_n_0 ;
wire \result[8]_i_7_n_0 ;
wire \result[8]_i_8_n_0 ;
wire \result[8]_i_9_n_0 ;
wire \result[9]_i_10_n_0 ;
wire \result[9]_i_11_n_0 ;
wire \result[9]_i_1_n_0 ;
wire \result[9]_i_2_n_0 ;
wire \result[9]_i_3_n_0 ;
wire \result[9]_i_4_n_0 ;
wire \result[9]_i_5_n_0 ;
wire \result[9]_i_6_n_0 ;
wire \result[9]_i_7_n_0 ;
wire \result[9]_i_8_n_0 ;
wire \result[9]_i_9_n_0 ;
wire \result_reg[0]_i_15_n_0 ;
wire \result_reg[0]_i_24_n_0 ;
wire \result_reg[0]_i_30_n_0 ;
wire \result_reg[0]_i_34_n_0 ;
wire \result_reg[0]_i_52_n_0 ;
wire \result_reg[0]_i_57_n_0 ;
wire \result_reg[0]_i_64_n_0 ;
wire \result_reg[0]_i_80_n_0 ;
wire \result_reg[11]_i_10_n_0 ;
wire \result_reg[11]_i_11_n_0 ;
wire \result_reg[11]_i_11_n_4 ;
wire \result_reg[11]_i_11_n_5 ;
wire \result_reg[11]_i_11_n_6 ;
wire \result_reg[11]_i_11_n_7 ;
wire \result_reg[11]_i_13_n_0 ;
wire \result_reg[11]_i_13_n_4 ;
wire \result_reg[11]_i_13_n_5 ;
wire \result_reg[11]_i_13_n_6 ;
wire \result_reg[11]_i_13_n_7 ;
wire \result_reg[12]_i_10_n_0 ;
wire \result_reg[15]_i_7_n_0 ;
wire \result_reg[15]_i_9_n_0 ;
wire \result_reg[15]_i_9_n_4 ;
wire \result_reg[15]_i_9_n_5 ;
wire \result_reg[15]_i_9_n_6 ;
wire \result_reg[15]_i_9_n_7 ;
wire \result_reg[16]_i_9_n_0 ;
wire \result_reg[19]_i_11_n_0 ;
wire \result_reg[19]_i_11_n_4 ;
wire \result_reg[19]_i_11_n_5 ;
wire \result_reg[19]_i_11_n_6 ;
wire \result_reg[19]_i_11_n_7 ;
wire \result_reg[19]_i_12_n_0 ;
wire \result_reg[19]_i_12_n_4 ;
wire \result_reg[19]_i_12_n_5 ;
wire \result_reg[19]_i_12_n_6 ;
wire \result_reg[19]_i_12_n_7 ;
wire \result_reg[19]_i_7_n_0 ;
wire \result_reg[19]_i_7_n_4 ;
wire \result_reg[19]_i_7_n_5 ;
wire \result_reg[19]_i_7_n_6 ;
wire \result_reg[19]_i_7_n_7 ;
wire \result_reg[23]_i_11_n_0 ;
wire \result_reg[23]_i_11_n_4 ;
wire \result_reg[23]_i_11_n_5 ;
wire \result_reg[23]_i_11_n_6 ;
wire \result_reg[23]_i_11_n_7 ;
wire \result_reg[23]_i_7_n_0 ;
wire \result_reg[23]_i_7_n_4 ;
wire \result_reg[23]_i_7_n_5 ;
wire \result_reg[23]_i_7_n_6 ;
wire \result_reg[23]_i_7_n_7 ;
wire \result_reg[27]_i_10_n_0 ;
wire \result_reg[27]_i_18_n_0 ;
wire \result_reg[27]_i_23_n_0 ;
wire \result_reg[27]_i_23_n_4 ;
wire \result_reg[27]_i_23_n_5 ;
wire \result_reg[27]_i_23_n_6 ;
wire \result_reg[27]_i_23_n_7 ;
wire \result_reg[27]_i_7_n_0 ;
wire \result_reg[27]_i_7_n_4 ;
wire \result_reg[27]_i_7_n_5 ;
wire \result_reg[27]_i_7_n_6 ;
wire \result_reg[27]_i_7_n_7 ;
wire \result_reg[31]_i_10_n_4 ;
wire \result_reg[31]_i_10_n_5 ;
wire \result_reg[31]_i_10_n_6 ;
wire \result_reg[31]_i_10_n_7 ;
wire \result_reg[31]_i_40_n_4 ;
wire \result_reg[31]_i_40_n_5 ;
wire \result_reg[31]_i_40_n_6 ;
wire \result_reg[31]_i_40_n_7 ;
wire \result_reg[3]_i_10_n_0 ;
wire \result_reg[3]_i_10_n_4 ;
wire \result_reg[3]_i_10_n_5 ;
wire \result_reg[3]_i_10_n_6 ;
wire \result_reg[3]_i_10_n_7 ;
wire \result_reg[3]_i_11_n_0 ;
wire \result_reg[3]_i_11_n_4 ;
wire \result_reg[3]_i_11_n_5 ;
wire \result_reg[3]_i_11_n_6 ;
wire \result_reg[3]_i_11_n_7 ;
wire \result_reg[3]_i_9_n_0 ;
wire \result_reg[4]_i_9_n_0 ;
wire \result_reg[7]_i_10_n_0 ;
wire \result_reg[7]_i_11_n_0 ;
wire \result_reg[7]_i_11_n_4 ;
wire \result_reg[7]_i_11_n_5 ;
wire \result_reg[7]_i_11_n_6 ;
wire \result_reg[7]_i_11_n_7 ;
wire \result_reg[7]_i_13_n_0 ;
wire \result_reg[7]_i_13_n_4 ;
wire \result_reg[7]_i_13_n_5 ;
wire \result_reg[7]_i_13_n_6 ;
wire \result_reg[7]_i_13_n_7 ;
wire \result_reg[8]_i_10_n_0 ;
wire \s_input_rs232_rx_ack[0]_i_1_n_0 ;
wire \s_input_rs232_rx_ack[0]_i_2_n_0 ;
wire \s_input_rs232_rx_ack[0]_i_3_n_0 ;
wire \s_input_rs232_rx_ack[0]_i_4_n_0 ;
wire \s_input_rs232_rx_ack[0]_i_5_n_0 ;
wire \s_input_rs232_rx_ack[0]_i_6_n_0 ;
wire \s_input_rs232_rx_ack[0]_i_7_n_0 ;
wire \s_input_rs232_rx_ack[0]_i_8_n_0 ;
wire \s_output_led_b[7]_i_1_n_0 ;
wire \s_output_led_b[7]_i_2_n_0 ;
wire \s_output_led_b_stb[0]_i_1_n_0 ;
wire \s_output_led_g[7]_i_1_n_0 ;
wire \s_output_led_g_stb[0]_i_1_n_0 ;
wire \s_output_led_r[7]_i_1_n_0 ;
wire \s_output_led_r[7]_i_2_n_0 ;
wire \s_output_led_r_stb[0]_i_1_n_0 ;
wire \s_output_rs232_tx[7]_i_2_n_0 ;
wire \s_output_rs232_tx[7]_i_3_n_0 ;
wire \s_output_rs232_tx[7]_i_4_n_0 ;
wire \s_output_rs232_tx[7]_i_5_n_0 ;
wire \s_output_rs232_tx[7]_i_6_n_0 ;
wire \s_output_rs232_tx[7]_i_7_n_0 ;
wire [0:0]\s_output_rs232_tx_reg[7]_0 ;
wire [15:0]sel;
wire \state[0]_i_1_n_0 ;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[2]_i_1_n_0 ;
wire \state[2]_i_2_n_0 ;
wire \state[2]_i_3_n_0 ;
wire \state[2]_i_4_n_0 ;
wire \state[2]_i_5_n_0 ;
wire \state[2]_i_6_n_0 ;
wire \state_reg_n_0_[0] ;
wire \state_reg_n_0_[1] ;
wire \state_reg_n_0_[2] ;
wire [31:0]store_data;
wire write_enable_reg_n_0;
wire [31:0]write_output;
wire [7:0]write_value;
wire \write_value[7]_i_2_n_0 ;
wire \write_value[7]_i_3_n_0 ;
wire NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_0_DBITERR_UNCONNECTED;
wire NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_0_REGCEB_UNCONNECTED;
wire NLW_memory_reg_0_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_0_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_0_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_1_DBITERR_UNCONNECTED;
wire NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_1_REGCEB_UNCONNECTED;
wire NLW_memory_reg_1_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_1_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_1_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_1_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_1_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_1_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_1_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_2_DBITERR_UNCONNECTED;
wire NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_2_REGCEB_UNCONNECTED;
wire NLW_memory_reg_2_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_2_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_2_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_2_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_2_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_2_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_2_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_3_DBITERR_UNCONNECTED;
wire NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_3_REGCEB_UNCONNECTED;
wire NLW_memory_reg_3_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_3_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_3_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_3_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_3_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_3_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_3_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_4_DBITERR_UNCONNECTED;
wire NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_4_REGCEB_UNCONNECTED;
wire NLW_memory_reg_4_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_4_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_4_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_4_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_4_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_4_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_4_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_5_DBITERR_UNCONNECTED;
wire NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_5_REGCEB_UNCONNECTED;
wire NLW_memory_reg_5_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_5_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_5_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_5_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_5_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_5_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_5_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_6_DBITERR_UNCONNECTED;
wire NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_6_REGCEB_UNCONNECTED;
wire NLW_memory_reg_6_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_6_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_6_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_6_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_6_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_6_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_6_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_7_DBITERR_UNCONNECTED;
wire NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_7_REGCEB_UNCONNECTED;
wire NLW_memory_reg_7_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_7_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_7_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_7_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_7_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_7_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_7_RDADDRECC_UNCONNECTED;
wire [2:0]\NLW_program_counter_reg[12]_i_3_CO_UNCONNECTED ;
wire [3:0]\NLW_program_counter_reg[15]_i_5_CO_UNCONNECTED ;
wire [3:3]\NLW_program_counter_reg[15]_i_5_O_UNCONNECTED ;
wire [2:0]\NLW_program_counter_reg[4]_i_3_CO_UNCONNECTED ;
wire [2:0]\NLW_program_counter_reg[8]_i_3_CO_UNCONNECTED ;
wire NLW_program_counter_reg_rep_0_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_SBITERR_UNCONNECTED;
wire [31:16]NLW_program_counter_reg_rep_0_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_0_DOBDO_UNCONNECTED;
wire [3:2]NLW_program_counter_reg_rep_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_0_RDADDRECC_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_SBITERR_UNCONNECTED;
wire [31:11]NLW_program_counter_reg_rep_1_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_1_DOBDO_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_1_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_1_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_1_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_1_RDADDRECC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED;
wire [2:0]\NLW_result_reg[0]_i_10_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_10_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_12_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_12_O_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_14_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_14_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_15_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_15_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_24_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_24_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_30_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_30_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_34_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_34_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_52_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_52_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_57_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_57_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_64_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_64_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_80_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_80_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[11]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[11]_i_11_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[11]_i_13_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[12]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_7_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_9_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[16]_i_11_CO_UNCONNECTED ;
wire [3:3]\NLW_result_reg[16]_i_11_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[16]_i_9_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_11_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_12_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_7_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_11_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_7_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_18_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_23_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_7_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_10_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_15_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_40_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_11_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_9_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[4]_i_9_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_11_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_13_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[8]_i_10_CO_UNCONNECTED ;
FDRE \address_a_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[0]),
.Q(address_a_2[0]),
.R(1'b0));
FDRE \address_a_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[1]),
.Q(address_a_2[1]),
.R(1'b0));
FDRE \address_a_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[2]),
.Q(address_a_2[2]),
.R(1'b0));
FDRE \address_a_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[3]),
.Q(address_a_2[3]),
.R(1'b0));
FDRE \address_b_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_35),
.Q(address_b_2[0]),
.R(1'b0));
FDRE \address_b_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_34),
.Q(address_b_2[1]),
.R(1'b0));
FDRE \address_b_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_33),
.Q(address_b_2[2]),
.R(1'b0));
FDRE \address_b_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_32),
.Q(address_b_2[3]),
.R(1'b0));
FDRE \address_z_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[0]),
.Q(address_z_2[0]),
.R(1'b0));
FDRE \address_z_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[1]),
.Q(address_z_2[1]),
.R(1'b0));
FDRE \address_z_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[2]),
.Q(address_z_2[2]),
.R(1'b0));
FDRE \address_z_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[3]),
.Q(address_z_2[3]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\address_z_3[3]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.O(\address_z_3[3]_i_1_n_0 ));
FDRE \address_z_3_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[0]),
.Q(address_z_3[0]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[1]),
.Q(address_z_3[1]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[2]),
.Q(address_z_3[2]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[3]),
.Q(address_z_3[3]),
.R(INTERNAL_RST_reg));
LUT2 #(
.INIT(4'h2))
\literal_2[15]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.O(opcode_20));
FDRE \literal_2_reg[10]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_25),
.Q(literal_2[10]),
.R(1'b0));
FDRE \literal_2_reg[11]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_24),
.Q(literal_2[11]),
.R(1'b0));
FDRE \literal_2_reg[12]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_23),
.Q(literal_2[12]),
.R(1'b0));
FDRE \literal_2_reg[13]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_22),
.Q(literal_2[13]),
.R(1'b0));
FDRE \literal_2_reg[14]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_21),
.Q(literal_2[14]),
.R(1'b0));
FDRE \literal_2_reg[15]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_20),
.Q(literal_2[15]),
.R(1'b0));
FDRE \literal_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_31),
.Q(literal_2[4]),
.R(1'b0));
FDRE \literal_2_reg[5]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_30),
.Q(literal_2[5]),
.R(1'b0));
FDRE \literal_2_reg[6]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_29),
.Q(literal_2[6]),
.R(1'b0));
FDRE \literal_2_reg[7]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_28),
.Q(literal_2[7]),
.R(1'b0));
FDRE \literal_2_reg[8]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_27),
.Q(literal_2[8]),
.R(1'b0));
FDRE \literal_2_reg[9]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_26),
.Q(literal_2[9]),
.R(1'b0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_0
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[3:0]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_0_DOADO_UNCONNECTED[31:4],load_data[3:0]}),
.DOBDO(NLW_memory_reg_0_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000000002000))
memory_reg_0_i_1
(.I0(opcode_2[1]),
.I1(opcode_2[2]),
.I2(opcode_20),
.I3(\state_reg_n_0_[0] ),
.I4(memory_reg_0_i_2_n_0),
.I5(opcode_2[4]),
.O(p_0_in));
LUT2 #(
.INIT(4'hE))
memory_reg_0_i_2
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.O(memory_reg_0_i_2_n_0));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "4" *)
(* bram_slice_end = "7" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_1
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_1_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[7:4]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_1_DOADO_UNCONNECTED[31:4],load_data[7:4]}),
.DOBDO(NLW_memory_reg_1_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_1_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_1_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_1_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_1_ENARDEN_cooolgate_en_sig_1),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_1_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_1_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_1_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_1_ENARDEN_cooolgate_en_gate_1
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_1_ENARDEN_cooolgate_en_sig_1));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "8" *)
(* bram_slice_end = "11" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_2
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_2_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[11:8]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_2_DOADO_UNCONNECTED[31:4],load_data[11:8]}),
.DOBDO(NLW_memory_reg_2_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_2_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_2_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_2_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_2_ENARDEN_cooolgate_en_sig_2),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_2_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_2_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_2_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_2_ENARDEN_cooolgate_en_gate_3
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_2_ENARDEN_cooolgate_en_sig_2));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_2_i_1
(.I0(result[11]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[11]),
.O(store_data[11]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_2_i_2
(.I0(result[10]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[10]),
.O(store_data[10]));
LUT3 #(
.INIT(8'hB8))
memory_reg_2_i_3
(.I0(result[9]),
.I1(operand_b1),
.I2(register_b[9]),
.O(store_data[9]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_2_i_4
(.I0(result[8]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[8]),
.O(store_data[8]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "12" *)
(* bram_slice_end = "15" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_3
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_3_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[15:12]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_3_DOADO_UNCONNECTED[31:4],load_data[15:12]}),
.DOBDO(NLW_memory_reg_3_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_3_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_3_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_3_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_3_ENARDEN_cooolgate_en_sig_3),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_3_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_3_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_3_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_3_ENARDEN_cooolgate_en_gate_5
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_3_ENARDEN_cooolgate_en_sig_3));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_3_i_1
(.I0(result[15]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[15]),
.O(store_data[15]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_3_i_2
(.I0(result[14]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[14]),
.O(store_data[14]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_3_i_3
(.I0(result[13]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[13]),
.O(store_data[13]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_3_i_4
(.I0(result[12]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[12]),
.O(store_data[12]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "16" *)
(* bram_slice_end = "19" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_4
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_4_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[19:16]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_4_DOADO_UNCONNECTED[31:4],load_data[19:16]}),
.DOBDO(NLW_memory_reg_4_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_4_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_4_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_4_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_4_ENARDEN_cooolgate_en_sig_4),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_4_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_4_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_4_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_4_ENARDEN_cooolgate_en_gate_7
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_4_ENARDEN_cooolgate_en_sig_4));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_4_i_1
(.I0(result[19]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[19]),
.O(store_data[19]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_4_i_2
(.I0(result[18]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[18]),
.O(store_data[18]));
LUT3 #(
.INIT(8'hB8))
memory_reg_4_i_3
(.I0(result[17]),
.I1(operand_b1),
.I2(register_b[17]),
.O(store_data[17]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_4_i_4
(.I0(result[16]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[16]),
.O(store_data[16]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "20" *)
(* bram_slice_end = "23" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_5
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_5_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[23:20]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_5_DOADO_UNCONNECTED[31:4],load_data[23:20]}),
.DOBDO(NLW_memory_reg_5_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_5_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_5_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_5_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_5_ENARDEN_cooolgate_en_sig_5),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_5_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_5_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_5_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_5_ENARDEN_cooolgate_en_gate_9
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_5_ENARDEN_cooolgate_en_sig_5));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_5_i_1
(.I0(result[23]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[23]),
.O(store_data[23]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_5_i_2
(.I0(result[22]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[22]),
.O(store_data[22]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_5_i_3
(.I0(result[21]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[21]),
.O(store_data[21]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_5_i_4
(.I0(result[20]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[20]),
.O(store_data[20]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "24" *)
(* bram_slice_end = "27" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_6
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_6_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[27:24]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_6_DOADO_UNCONNECTED[31:4],load_data[27:24]}),
.DOBDO(NLW_memory_reg_6_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_6_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_6_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_6_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_6_ENARDEN_cooolgate_en_sig_6),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_6_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_6_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_6_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_6_ENARDEN_cooolgate_en_gate_11
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_6_ENARDEN_cooolgate_en_sig_6));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_6_i_1
(.I0(result[27]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[27]),
.O(store_data[27]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_6_i_2
(.I0(result[26]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[26]),
.O(store_data[26]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_6_i_3
(.I0(result[25]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[25]),
.O(store_data[25]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_6_i_4
(.I0(result[24]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[24]),
.O(store_data[24]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "28" *)
(* bram_slice_end = "31" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_7
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_7_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[31:28]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_7_DOADO_UNCONNECTED[31:4],load_data[31:28]}),
.DOBDO(NLW_memory_reg_7_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_7_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_7_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_7_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_7_ENARDEN_cooolgate_en_sig_7),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_7_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_7_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_7_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,p_0_in}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_7_ENARDEN_cooolgate_en_gate_13
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(p_0_in),
.O(memory_reg_7_ENARDEN_cooolgate_en_sig_7));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_7_i_1
(.I0(result[31]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[31]),
.O(store_data[31]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_7_i_2
(.I0(result[30]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[30]),
.O(store_data[30]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_7_i_3
(.I0(result[29]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[29]),
.O(store_data[29]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_7_i_4
(.I0(result[28]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[28]),
.O(store_data[28]));
FDRE \opcode_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[0]),
.Q(opcode_2[0]),
.R(1'b0));
FDRE \opcode_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[1]),
.Q(opcode_2[1]),
.R(1'b0));
FDRE \opcode_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[2]),
.Q(opcode_2[2]),
.R(1'b0));
FDRE \opcode_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[3]),
.Q(opcode_2[3]),
.R(1'b0));
FDRE \opcode_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[4]),
.Q(opcode_2[4]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBB8B88))
\program_counter[0]_i_1
(.I0(\program_counter[0]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg_n_0_[0] ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(address_b_2[0]),
.O(sel[0]));
LUT5 #(
.INIT(32'h0000FF74))
\program_counter[0]_i_2
(.I0(\program_counter_reg_n_0_[0] ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(address_b_2[0]),
.I3(opcode_2[1]),
.I4(\program_counter[0]_i_3_n_0 ),
.O(\program_counter[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[0]_i_3
(.I0(result[0]),
.I1(operand_a1),
.I2(register_a[0]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(address_b_2[0]),
.O(\program_counter[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[10]_i_1
(.I0(\program_counter[10]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[12]_i_3_n_6 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[10]),
.O(sel[10]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[10]_i_2
(.I0(\program_counter_reg[12]_i_3_n_6 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[10]),
.I3(opcode_2[1]),
.I4(\program_counter[10]_i_3_n_0 ),
.O(\program_counter[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[10]_i_3
(.I0(result[10]),
.I1(operand_a1),
.I2(register_a[10]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[10]),
.O(\program_counter[10]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[11]_i_1
(.I0(\program_counter[11]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[12]_i_3_n_5 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[11]),
.O(sel[11]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[11]_i_2
(.I0(\program_counter_reg[12]_i_3_n_5 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[11]),
.I3(opcode_2[1]),
.I4(\program_counter[11]_i_3_n_0 ),
.O(\program_counter[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[11]_i_3
(.I0(result[11]),
.I1(operand_a1),
.I2(register_a[11]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[11]),
.O(\program_counter[11]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[12]_i_1
(.I0(\program_counter[12]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[12]_i_3_n_4 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[12]),
.O(sel[12]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[12]_i_2
(.I0(\program_counter_reg[12]_i_3_n_4 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[12]),
.I3(opcode_2[1]),
.I4(\program_counter[12]_i_4_n_0 ),
.O(\program_counter[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[12]_i_4
(.I0(result[12]),
.I1(operand_a1),
.I2(register_a[12]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[12]),
.O(\program_counter[12]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[13]_i_1
(.I0(\program_counter[13]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[15]_i_5_n_7 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[13]),
.O(sel[13]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[13]_i_2
(.I0(\program_counter_reg[15]_i_5_n_7 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[13]),
.I3(opcode_2[1]),
.I4(\program_counter[13]_i_3_n_0 ),
.O(\program_counter[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[13]_i_3
(.I0(result[13]),
.I1(operand_a1),
.I2(register_a[13]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[13]),
.O(\program_counter[13]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[14]_i_1
(.I0(\program_counter[14]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[15]_i_5_n_6 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[14]),
.O(sel[14]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[14]_i_2
(.I0(\program_counter_reg[15]_i_5_n_6 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[14]),
.I3(opcode_2[1]),
.I4(\program_counter[14]_i_3_n_0 ),
.O(\program_counter[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[14]_i_3
(.I0(result[14]),
.I1(operand_a1),
.I2(register_a[14]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[14]),
.O(\program_counter[14]_i_3_n_0 ));
LUT3 #(
.INIT(8'h32))
\program_counter[15]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[0] ),
.O(instruction0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[15]_i_12
(.I0(\read_input[3]_i_1_n_0 ),
.I1(\read_input[2]_i_1_n_0 ),
.I2(\read_input[6]_i_1_n_0 ),
.I3(\read_input[7]_i_1_n_0 ),
.I4(\read_input[4]_i_1_n_0 ),
.I5(\read_input[5]_i_1_n_0 ),
.O(\program_counter[15]_i_12_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\program_counter[15]_i_13
(.I0(register_a[0]),
.I1(result[0]),
.I2(register_a[1]),
.I3(operand_a1),
.I4(result[1]),
.O(\program_counter[15]_i_13_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[15]_i_14
(.I0(\read_input[21]_i_1_n_0 ),
.I1(\read_input[20]_i_1_n_0 ),
.I2(\read_input[24]_i_1_n_0 ),
.I3(\read_input[25]_i_1_n_0 ),
.I4(\read_input[22]_i_1_n_0 ),
.I5(\read_input[23]_i_1_n_0 ),
.O(\program_counter[15]_i_14_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[15]_i_15
(.I0(\read_input[27]_i_1_n_0 ),
.I1(\read_input[26]_i_1_n_0 ),
.I2(\read_input[30]_i_1_n_0 ),
.I3(\read_input[31]_i_2_n_0 ),
.I4(\read_input[28]_i_1_n_0 ),
.I5(\read_input[29]_i_1_n_0 ),
.O(\program_counter[15]_i_15_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[15]_i_16
(.I0(\read_input[9]_i_1_n_0 ),
.I1(\read_input[8]_i_1_n_0 ),
.I2(\read_input[12]_i_1_n_0 ),
.I3(\read_input[13]_i_1_n_0 ),
.I4(\read_input[10]_i_1_n_0 ),
.I5(\read_input[11]_i_1_n_0 ),
.O(\program_counter[15]_i_16_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[15]_i_17
(.I0(\read_input[15]_i_1_n_0 ),
.I1(\read_input[14]_i_1_n_0 ),
.I2(\read_input[18]_i_1_n_0 ),
.I3(\read_input[19]_i_1_n_0 ),
.I4(\read_input[16]_i_1_n_0 ),
.I5(\read_input[17]_i_1_n_0 ),
.O(\program_counter[15]_i_17_n_0 ));
LUT6 #(
.INIT(64'h2002000000002002))
\program_counter[15]_i_18
(.I0(write_enable_reg_n_0),
.I1(\read_input[31]_i_4_n_0 ),
.I2(address_a_2[0]),
.I3(address_z_3[0]),
.I4(address_a_2[3]),
.I5(address_z_3[3]),
.O(operand_a1));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[15]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[15]_i_5_n_5 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[15]),
.O(sel[15]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[15]_i_3
(.I0(\program_counter_reg[15]_i_5_n_5 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[15]),
.I3(opcode_2[1]),
.I4(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hB434000000000000))
\program_counter[15]_i_4
(.I0(opcode_2[2]),
.I1(opcode_2[3]),
.I2(opcode_2[1]),
.I3(\program_counter[15]_i_7_n_0 ),
.I4(\program_counter[8]_i_4_n_0 ),
.I5(\read_input[31]_i_3_n_0 ),
.O(\program_counter[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'hEFFFFFFFFFFFFFFF))
\program_counter[15]_i_6
(.I0(opcode_2[4]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(\state_reg_n_0_[1] ),
.I5(\state_reg_n_0_[0] ),
.O(\program_counter[15]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[15]_i_7
(.I0(\program_counter[15]_i_12_n_0 ),
.I1(\program_counter[15]_i_13_n_0 ),
.I2(\program_counter[15]_i_14_n_0 ),
.I3(\program_counter[15]_i_15_n_0 ),
.I4(\program_counter[15]_i_16_n_0 ),
.I5(\program_counter[15]_i_17_n_0 ),
.O(\program_counter[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[15]_i_8
(.I0(result[15]),
.I1(operand_a1),
.I2(register_a[15]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[15]),
.O(\program_counter[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'hF444FFFFF4444444))
\program_counter[1]_i_1
(.I0(\program_counter[1]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter[8]_i_6_n_0 ),
.I3(\program_counter[1]_i_3_n_0 ),
.I4(\program_counter[8]_i_4_n_0 ),
.I5(\program_counter_reg[4]_i_3_n_7 ),
.O(sel[1]));
LUT5 #(
.INIT(32'hFFFF0047))
\program_counter[1]_i_2
(.I0(\program_counter_reg[4]_i_3_n_7 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(address_b_2[1]),
.I3(opcode_2[1]),
.I4(\program_counter[1]_i_4_n_0 ),
.O(\program_counter[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAEAAAAAAA2A))
\program_counter[1]_i_3
(.I0(\program_counter_reg[4]_i_3_n_7 ),
.I1(opcode_2[1]),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(opcode_2[4]),
.I5(address_b_2[1]),
.O(\program_counter[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[1]_i_4
(.I0(result[1]),
.I1(operand_a1),
.I2(register_a[1]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(address_b_2[1]),
.O(\program_counter[1]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[2]_i_1
(.I0(\program_counter[2]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[4]_i_3_n_6 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(address_b_2[2]),
.O(sel[2]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[2]_i_2
(.I0(\program_counter_reg[4]_i_3_n_6 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(address_b_2[2]),
.I3(opcode_2[1]),
.I4(\program_counter[2]_i_3_n_0 ),
.O(\program_counter[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[2]_i_3
(.I0(result[2]),
.I1(operand_a1),
.I2(register_a[2]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(address_b_2[2]),
.O(\program_counter[2]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[3]_i_1
(.I0(\program_counter[3]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[4]_i_3_n_5 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(address_b_2[3]),
.O(sel[3]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[3]_i_2
(.I0(\program_counter_reg[4]_i_3_n_5 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(address_b_2[3]),
.I3(opcode_2[1]),
.I4(\program_counter[3]_i_3_n_0 ),
.O(\program_counter[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[3]_i_3
(.I0(result[3]),
.I1(operand_a1),
.I2(register_a[3]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(address_b_2[3]),
.O(\program_counter[3]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[4]_i_1
(.I0(\program_counter[4]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[4]_i_3_n_4 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[4]),
.O(sel[4]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[4]_i_2
(.I0(\program_counter_reg[4]_i_3_n_4 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[4]),
.I3(opcode_2[1]),
.I4(\program_counter[4]_i_4_n_0 ),
.O(\program_counter[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[4]_i_4
(.I0(result[4]),
.I1(operand_a1),
.I2(register_a[4]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[4]),
.O(\program_counter[4]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[5]_i_1
(.I0(\program_counter[5]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[8]_i_3_n_7 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[5]),
.O(sel[5]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[5]_i_2
(.I0(\program_counter_reg[8]_i_3_n_7 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[5]),
.I3(opcode_2[1]),
.I4(\program_counter[5]_i_3_n_0 ),
.O(\program_counter[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[5]_i_3
(.I0(result[5]),
.I1(operand_a1),
.I2(register_a[5]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[5]),
.O(\program_counter[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFF444F444F444F4))
\program_counter[6]_i_1
(.I0(\program_counter[6]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[8]_i_3_n_6 ),
.I3(\program_counter[8]_i_4_n_0 ),
.I4(\program_counter[6]_i_3_n_0 ),
.I5(\program_counter[8]_i_6_n_0 ),
.O(sel[6]));
LUT5 #(
.INIT(32'hFFFF0047))
\program_counter[6]_i_2
(.I0(\program_counter_reg[8]_i_3_n_6 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[6]),
.I3(opcode_2[1]),
.I4(\program_counter[6]_i_4_n_0 ),
.O(\program_counter[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAEAAAAAAA2A))
\program_counter[6]_i_3
(.I0(\program_counter_reg[8]_i_3_n_6 ),
.I1(opcode_2[1]),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(opcode_2[4]),
.I5(literal_2[6]),
.O(\program_counter[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[6]_i_4
(.I0(result[6]),
.I1(operand_a1),
.I2(register_a[6]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[6]),
.O(\program_counter[6]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[7]_i_1
(.I0(\program_counter[7]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[8]_i_3_n_5 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[7]),
.O(sel[7]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[7]_i_2
(.I0(\program_counter_reg[8]_i_3_n_5 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[7]),
.I3(opcode_2[1]),
.I4(\program_counter[7]_i_3_n_0 ),
.O(\program_counter[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[7]_i_3
(.I0(result[7]),
.I1(operand_a1),
.I2(register_a[7]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[7]),
.O(\program_counter[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFF444F444F444F4))
\program_counter[8]_i_1
(.I0(\program_counter[8]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[8]_i_3_n_4 ),
.I3(\program_counter[8]_i_4_n_0 ),
.I4(\program_counter[8]_i_5_n_0 ),
.I5(\program_counter[8]_i_6_n_0 ),
.O(sel[8]));
LUT5 #(
.INIT(32'hFFFF0047))
\program_counter[8]_i_2
(.I0(\program_counter_reg[8]_i_3_n_4 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[8]),
.I3(opcode_2[1]),
.I4(\program_counter[8]_i_7_n_0 ),
.O(\program_counter[8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\program_counter[8]_i_4
(.I0(\state_reg_n_0_[0] ),
.I1(\state_reg_n_0_[1] ),
.O(\program_counter[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAEAAAAAAA2A))
\program_counter[8]_i_5
(.I0(\program_counter_reg[8]_i_3_n_4 ),
.I1(opcode_2[1]),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(opcode_2[4]),
.I5(literal_2[8]),
.O(\program_counter[8]_i_5_n_0 ));
LUT6 #(
.INIT(64'hBFBBFBFFFFBBFBFF))
\program_counter[8]_i_6
(.I0(opcode_2[4]),
.I1(opcode_2[0]),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(opcode_2[1]),
.I5(\program_counter[15]_i_7_n_0 ),
.O(\program_counter[8]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[8]_i_7
(.I0(result[8]),
.I1(operand_a1),
.I2(register_a[8]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[8]),
.O(\program_counter[8]_i_7_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\program_counter[9]_i_1
(.I0(\program_counter[9]_i_2_n_0 ),
.I1(\program_counter[15]_i_4_n_0 ),
.I2(\program_counter_reg[12]_i_3_n_7 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(literal_2[9]),
.O(sel[9]));
LUT5 #(
.INIT(32'h0000FFB8))
\program_counter[9]_i_2
(.I0(\program_counter_reg[12]_i_3_n_7 ),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(literal_2[9]),
.I3(opcode_2[1]),
.I4(\program_counter[9]_i_3_n_0 ),
.O(\program_counter[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00470000FF4700FF))
\program_counter[9]_i_3
(.I0(result[9]),
.I1(operand_a1),
.I2(register_a[9]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(literal_2[9]),
.O(\program_counter[9]_i_3_n_0 ));
FDRE \program_counter_1_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[0] ),
.Q(program_counter_1[0]),
.R(1'b0));
FDRE \program_counter_1_reg[10]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[10] ),
.Q(program_counter_1[10]),
.R(1'b0));
FDRE \program_counter_1_reg[11]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[11] ),
.Q(program_counter_1[11]),
.R(1'b0));
FDRE \program_counter_1_reg[12]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[12] ),
.Q(program_counter_1[12]),
.R(1'b0));
FDRE \program_counter_1_reg[13]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[13] ),
.Q(program_counter_1[13]),
.R(1'b0));
FDRE \program_counter_1_reg[14]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[14] ),
.Q(program_counter_1[14]),
.R(1'b0));
FDRE \program_counter_1_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[15] ),
.Q(program_counter_1[15]),
.R(1'b0));
FDRE \program_counter_1_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[1] ),
.Q(program_counter_1[1]),
.R(1'b0));
FDRE \program_counter_1_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[2] ),
.Q(program_counter_1[2]),
.R(1'b0));
FDRE \program_counter_1_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[3] ),
.Q(program_counter_1[3]),
.R(1'b0));
FDRE \program_counter_1_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[4] ),
.Q(program_counter_1[4]),
.R(1'b0));
FDRE \program_counter_1_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[5] ),
.Q(program_counter_1[5]),
.R(1'b0));
FDRE \program_counter_1_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[6] ),
.Q(program_counter_1[6]),
.R(1'b0));
FDRE \program_counter_1_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[7] ),
.Q(program_counter_1[7]),
.R(1'b0));
FDRE \program_counter_1_reg[8]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[8] ),
.Q(program_counter_1[8]),
.R(1'b0));
FDRE \program_counter_1_reg[9]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[9] ),
.Q(program_counter_1[9]),
.R(1'b0));
FDRE \program_counter_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[0]),
.Q(program_counter_2[0]),
.R(1'b0));
FDRE \program_counter_2_reg[10]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[10]),
.Q(program_counter_2[10]),
.R(1'b0));
FDRE \program_counter_2_reg[11]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[11]),
.Q(program_counter_2[11]),
.R(1'b0));
FDRE \program_counter_2_reg[12]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[12]),
.Q(program_counter_2[12]),
.R(1'b0));
FDRE \program_counter_2_reg[13]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[13]),
.Q(program_counter_2[13]),
.R(1'b0));
FDRE \program_counter_2_reg[14]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[14]),
.Q(program_counter_2[14]),
.R(1'b0));
FDRE \program_counter_2_reg[15]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[15]),
.Q(program_counter_2[15]),
.R(1'b0));
FDRE \program_counter_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[1]),
.Q(program_counter_2[1]),
.R(1'b0));
FDRE \program_counter_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[2]),
.Q(program_counter_2[2]),
.R(1'b0));
FDRE \program_counter_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[3]),
.Q(program_counter_2[3]),
.R(1'b0));
FDRE \program_counter_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[4]),
.Q(program_counter_2[4]),
.R(1'b0));
FDRE \program_counter_2_reg[5]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[5]),
.Q(program_counter_2[5]),
.R(1'b0));
FDRE \program_counter_2_reg[6]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[6]),
.Q(program_counter_2[6]),
.R(1'b0));
FDRE \program_counter_2_reg[7]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[7]),
.Q(program_counter_2[7]),
.R(1'b0));
FDRE \program_counter_2_reg[8]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[8]),
.Q(program_counter_2[8]),
.R(1'b0));
FDRE \program_counter_2_reg[9]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[9]),
.Q(program_counter_2[9]),
.R(1'b0));
FDRE \program_counter_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[0]),
.Q(\program_counter_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[10]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[10]),
.Q(\program_counter_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[11]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[11]),
.Q(\program_counter_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[12]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[12]),
.Q(\program_counter_reg_n_0_[12] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[12]_i_3
(.CI(\program_counter_reg[8]_i_3_n_0 ),
.CO({\program_counter_reg[12]_i_3_n_0 ,\NLW_program_counter_reg[12]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\program_counter_reg[12]_i_3_n_4 ,\program_counter_reg[12]_i_3_n_5 ,\program_counter_reg[12]_i_3_n_6 ,\program_counter_reg[12]_i_3_n_7 }),
.S({\program_counter_reg_n_0_[12] ,\program_counter_reg_n_0_[11] ,\program_counter_reg_n_0_[10] ,\program_counter_reg_n_0_[9] }));
FDRE \program_counter_reg[13]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[13]),
.Q(\program_counter_reg_n_0_[13] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[14]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[14]),
.Q(\program_counter_reg_n_0_[14] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[15]),
.Q(\program_counter_reg_n_0_[15] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[15]_i_5
(.CI(\program_counter_reg[12]_i_3_n_0 ),
.CO(\NLW_program_counter_reg[15]_i_5_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_program_counter_reg[15]_i_5_O_UNCONNECTED [3],\program_counter_reg[15]_i_5_n_5 ,\program_counter_reg[15]_i_5_n_6 ,\program_counter_reg[15]_i_5_n_7 }),
.S({1'b0,\program_counter_reg_n_0_[15] ,\program_counter_reg_n_0_[14] ,\program_counter_reg_n_0_[13] }));
FDRE \program_counter_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[1]),
.Q(\program_counter_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[2]),
.Q(\program_counter_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[3]),
.Q(\program_counter_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[4]),
.Q(\program_counter_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[4]_i_3
(.CI(1'b0),
.CO({\program_counter_reg[4]_i_3_n_0 ,\NLW_program_counter_reg[4]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(\program_counter_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\program_counter_reg[4]_i_3_n_4 ,\program_counter_reg[4]_i_3_n_5 ,\program_counter_reg[4]_i_3_n_6 ,\program_counter_reg[4]_i_3_n_7 }),
.S({\program_counter_reg_n_0_[4] ,\program_counter_reg_n_0_[3] ,\program_counter_reg_n_0_[2] ,\program_counter_reg_n_0_[1] }));
FDRE \program_counter_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[5]),
.Q(\program_counter_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[6]),
.Q(\program_counter_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[7]),
.Q(\program_counter_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[8]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[8]),
.Q(\program_counter_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[8]_i_3
(.CI(\program_counter_reg[4]_i_3_n_0 ),
.CO({\program_counter_reg[8]_i_3_n_0 ,\NLW_program_counter_reg[8]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\program_counter_reg[8]_i_3_n_4 ,\program_counter_reg[8]_i_3_n_5 ,\program_counter_reg[8]_i_3_n_6 ,\program_counter_reg[8]_i_3_n_7 }),
.S({\program_counter_reg_n_0_[8] ,\program_counter_reg_n_0_[7] ,\program_counter_reg_n_0_[6] ,\program_counter_reg_n_0_[5] }));
FDRE \program_counter_reg[9]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[9]),
.Q(\program_counter_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
(* RTL_RAM_BITS = "59392" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0820820820820820820820820820820820820820820820820820820820820830),
.INITP_01(256'h2082082082082082082082082082082082082082082082082082082082082082),
.INITP_02(256'h8208208208208208208208208208208208208208208208208208208208208208),
.INITP_03(256'h3FFFFCCF83FE23FF33FFFFCCF3FFFFCCF3FE208830C820820820820820820820),
.INITP_04(256'hFFFCCF83FE23FF33FFFFCCF3FFFFCCF3FFFFCCF83FE23FF33FFFFCCF3FFFFCCF),
.INITP_05(256'h3E0F3E0CF83E0F83E020F83E083B3FFCCF83E0FFEC3FFCCF83E0F83FFFFCCF3F),
.INITP_06(256'h0F3B22020F83E3FF33E0FF83E0F003E3FF33E0FFF20820EC88FFCCF83FFB00F8),
.INITP_07(256'hCF83CF03CF803E0F0B20F83C0F3E00F83CEC83CF803E0F03CF803E0F03CF803E),
.INITP_08(256'h82082082082082082082083B3FFCCF83E0FFEC80B20F3E0F3C0F3E00F83C2C83),
.INITP_09(256'hFFECCF83E0CF83E0CF83E0EC3E0F83CF833E0F83CF820F83C83E0F03CF820820),
.INITP_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_00(256'h000200080005000000080004002000080003000A000800000000009100000000),
.INIT_01(256'h000B00690008000A006800080009004300080008000400080007000000080006),
.INIT_02(256'h0008001000650008000F00440008000E00200008000D00730008000C00700008),
.INIT_03(256'h006900080015007200080014007400080013002000080012006F00080011006D),
.INIT_04(256'h001B006F0008001A006C00080019006F00080018006300080017002D00080016),
.INIT_05(256'h0008002000440008001F00450008001E004C0008001D00200008001C00720008),
.INIT_06(256'h007000080025006D000800240061000800230078000800220065000800210020),
.INIT_07(256'h002B00000008002A002000080029000A00080028006500080027006C00080026),
.INIT_08(256'h0008003100720008003000650008002F00740008002E006E0008002D00650008),
.INIT_09(256'h002000080036006500080035007500080034006C000800330062000800320020),
.INIT_0A(256'h003C006C0008003B00650008003A007600080039006500080038006C00080037),
.INIT_0B(256'h0008004100780008004000650008003F00680008003E00280008003D00200008),
.INIT_0C(256'h002900080046004600080045004600080044002D000800430030000800420020),
.INIT_0D(256'h004C000A0008004B00010008004A000000080049002000080048000A00080047),
.INIT_0E(256'h00080052007400080051006E0008005000650008004E00000008004D00200008),
.INIT_0F(256'h0065000800570072000800560067000800550020000800540072000800530065),
.INIT_10(256'h005D00650008005C006C0008005B00200008005A006E00080059006500080058),
.INIT_11(256'h00080062002800080061002000080060006C0008005F00650008005E00760008),
.INIT_12(256'h002D000800670030000800660020000800650078000800640065000800630068),
.INIT_13(256'h006D00200008006C000A0008006B00290008006A004600080069004600080068),
.INIT_14(256'h00080072006E0008007100650008007000000008006F00030008006E00000008),
.INIT_15(256'h0065000800770072000800760020000800750072000800740065000800730074),
.INIT_16(256'h007D00760008007C00650008007B006C0008007A002000080079006400080078),
.INIT_17(256'h0008008200680008008100280008008000200008007F006C0008007E00650008),
.INIT_18(256'h004600080087002D000800860030000800850020000800840078000800830065),
.INIT_19(256'h008D00000008008C00200008008B000A0008008A002900080089004600080088),
.INIT_1A(256'h006F0089000001AE000000000008009000000008008F00200008008E000A0008),
.INIT_1B(256'h0001000800090001000700010006000800000000000000080008000700000000),
.INIT_1C(256'h000100080071000100070001000600000000FFFF0000FFFFFFFF02AF00000000),
.INIT_1D(256'h030A00000000000100070001000600000000FFFF0000FFFFFFFF02AF00000000),
.INIT_1E(256'h000000000000000100070001000600080000000000020000FFFF0000FFFF0000),
.INIT_1F(256'h0003000100070001000600000000FFFF0000FFFFFFFF04370000000000010008),
.INIT_20(256'h0050000100070001000600000000FFFF0000FFFFFFFF02AF0000000000010008),
.INIT_21(256'h0000000100070001000600000000FFFF0000FFFFFFFF02AF0000000000010008),
.INIT_22(256'h0001000100070001000600080001000000020000FFFF0000FFFF0000030A0000),
.INIT_23(256'h00070001000600000000FFFF0000FFFFFFFF0437000000000001000800000000),
.INIT_24(256'h00070001000600000000FFFF0000FFFFFFFF02AF0000000000010008008E0001),
.INIT_25(256'h00070001000600000000FFFF0000FFFFFFFF02AF0000000000010008002D0001),
.INIT_26(256'h00070001000600080002000000020000FFFF0000FFFF0000030A000000000001),
.INIT_27(256'h000600000000FFFF0000FFFFFFFF043700000000000100080000000000020001),
.INIT_28(256'h000600000000FFFF0000FFFFFFFF02AF0000000000010008004C000100070001),
.INIT_29(256'h0000000000020001000800000000000100010008000000000000000100070001),
.INIT_2A(256'h000000000000000001C900000000FFFF0000FFFFFFFD04D30000000000010008),
.INIT_2B(256'h00000000000100080000000000070001000800000000FFFF0001000700010006),
.INIT_2C(256'h0000FFFE000800000000000100000000000000000000FFFF0000FFFFFFFE02CA),
.INIT_2D(256'h000800000000FFFF03050000000000020000FFFF000000000000000100080000),
.INIT_2E(256'h0000FFFF0000000000020000FFFF0000000000000001000800000000FFFE0001),
.INIT_2F(256'h000A0000FFFF0000000000000001000800010001000800000000000000000008),
.INIT_30(256'h00000001000700010006000000000000000002CE030703060000FFFF00080000),
.INIT_31(256'h000800020000004F0000FFFF0000FFFFFFFF0323000000000001000800000000),
.INIT_32(256'h00010008000000080001000000000000FFFF0008000000000002000000000000),
.INIT_33(256'hFFFF0000FFFFFFFF037A00000000000100080000000000010001000700010006),
.INIT_34(256'hFFFF000000000000000100080004034903720349000A0000FFFF000000010000),
.INIT_35(256'h03BB0000000000010008000000000001000100070001000600080000000A0000),
.INIT_36(256'h0000000A0000FFFF000000000000000100080000002C0000FFFF0000FFFFFFFF),
.INIT_37(256'h0000FFFF00010008004100000000000000000008004F00000000000003270008),
.INIT_38(256'h006103A2000A0000FFFF00460001000800000000FFFF038E000A0000FFFF0000),
.INIT_39(256'hFFFF00660001000800000000FFFF03A2000A0000FFFF00000000FFFF00010008),
.INIT_3A(256'h00000000FFFF03B6000A0000FFFF00000000FFFF00010008003003B6000A0000),
.INIT_3B(256'hFFFF000100080030000000000000000000080001000A0000FFFF003900010008),
.INIT_3C(256'h03DF000A0000FFFF00390001000800000000FFFF03CF000A0000FFFF00000000),
.INIT_3D(256'h006103DF0000000000000008002C000A0000FFFF00000000FFFF000100080030),
.INIT_3E(256'hFFFF00660001000800000000FFFF03F2000A0000FFFF00000000FFFF00010008),
.INIT_3F(256'hFFFF000A0000FFFF00000000FFFF00010008006100010008000A0408000A0000),
.INIT_40(256'h0000FFFF00000000FFFF00010008004104080000000000000008002C000A0000),
.INIT_41(256'h004100010008000A0431000A0000FFFF00460001000800000000FFFF041B000A),
.INIT_42(256'h0000000000000008002C000A0000FFFF000A0000FFFF00000000FFFF00010008),
.INIT_43(256'h000800000000FFFF000100070001000600000000000000000008002C000A0431),
.INIT_44(256'h000000000000FFFF0000FFFFFFFE045200000000000100080000000000070001),
.INIT_45(256'h0034000800030033000800020032000800010031000800000030001300000000),
.INIT_46(256'h0009003900080008003800080007003700080006003600080005003500080004),
.INIT_47(256'h0008000E00650008000D00640008000C00630008000B00620008000A00610008),
.INIT_48(256'hFFFF0008000100080000000000110008001100000008001000000008000F0066),
.INIT_49(256'h0008000400080012000A0000FFFF00000000FFFE00010008001C04D0000A0000),
.INIT_4A(256'h000800000001000800000000FFFF0008FFFE000A0000FFFF00000000FFFE0001),
.INIT_4B(256'h000000000011000000080000FFFF0000000000020000FFFF0000000000120001),
.INIT_4C(256'h04890000FFFF00080011000A0000FFFF00000000001100010008000100010008),
.INIT_4D(256'h000000080000FFFF00000000FFFD000100080000000000700000000000000000),
.INIT_4E(256'h0008000000000006000000080000FFFF00000000FFFE0001000800000000004B),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFF000000000000000000080000FFFF00000000FFFF0001),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_0
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b1,1'b1}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_0_DOADO_UNCONNECTED[31:16],program_counter_reg_rep_0_n_20,program_counter_reg_rep_0_n_21,program_counter_reg_rep_0_n_22,program_counter_reg_rep_0_n_23,program_counter_reg_rep_0_n_24,program_counter_reg_rep_0_n_25,program_counter_reg_rep_0_n_26,program_counter_reg_rep_0_n_27,program_counter_reg_rep_0_n_28,program_counter_reg_rep_0_n_29,program_counter_reg_rep_0_n_30,program_counter_reg_rep_0_n_31,program_counter_reg_rep_0_n_32,program_counter_reg_rep_0_n_33,program_counter_reg_rep_0_n_34,program_counter_reg_rep_0_n_35}),
.DOBDO(NLW_program_counter_reg_rep_0_DOBDO_UNCONNECTED[31:0]),
.DOPADOP({NLW_program_counter_reg_rep_0_DOPADOP_UNCONNECTED[3:2],address_a[1:0]}),
.DOPBDOP(NLW_program_counter_reg_rep_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(instruction0),
.REGCEB(NLW_program_counter_reg_rep_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_0_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hAFAE))
program_counter_reg_rep_0_i_1
(.I0(INTERNAL_RST_reg),
.I1(\state_reg_n_0_[0] ),
.I2(\state_reg_n_0_[2] ),
.I3(\state_reg_n_0_[1] ),
.O(program_counter_reg_rep_0_i_1_n_0));
LUT6 #(
.INIT(64'h00000000FFE200E2))
program_counter_reg_rep_0_i_10
(.I0(address_b_2[2]),
.I1(\program_counter[15]_i_6_n_0 ),
.I2(\program_counter_reg[4]_i_3_n_6 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[2]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_10_n_0));
LUT6 #(
.INIT(64'h00000000BABAFFBA))
program_counter_reg_rep_0_i_11
(.I0(program_counter_reg_rep_0_i_15_n_0),
.I1(program_counter_reg_rep_0_i_16_n_0),
.I2(\program_counter[8]_i_6_n_0 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[1]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_11_n_0));
LUT6 #(
.INIT(64'h00000000FF2E002E))
program_counter_reg_rep_0_i_12
(.I0(address_b_2[0]),
.I1(\program_counter[15]_i_6_n_0 ),
.I2(\program_counter_reg_n_0_[0] ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[0]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_12_n_0));
LUT6 #(
.INIT(64'h73C3FFFF00000000))
program_counter_reg_rep_0_i_13
(.I0(\program_counter[15]_i_7_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[8]_i_5_n_0 ),
.O(program_counter_reg_rep_0_i_13_n_0));
LUT6 #(
.INIT(64'h73C3FFFF00000000))
program_counter_reg_rep_0_i_14
(.I0(\program_counter[15]_i_7_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[6]_i_3_n_0 ),
.O(program_counter_reg_rep_0_i_14_n_0));
LUT3 #(
.INIT(8'h2A))
program_counter_reg_rep_0_i_15
(.I0(\program_counter_reg[4]_i_3_n_7 ),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.O(program_counter_reg_rep_0_i_15_n_0));
LUT5 #(
.INIT(32'h777FFF7F))
program_counter_reg_rep_0_i_16
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[0] ),
.I2(address_b_2[1]),
.I3(program_counter_reg_rep_0_i_17_n_0),
.I4(\program_counter_reg[4]_i_3_n_7 ),
.O(program_counter_reg_rep_0_i_16_n_0));
LUT4 #(
.INIT(16'hFFF7))
program_counter_reg_rep_0_i_17
(.I0(opcode_2[1]),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.I3(opcode_2[4]),
.O(program_counter_reg_rep_0_i_17_n_0));
LUT6 #(
.INIT(64'h00000000FFE200E2))
program_counter_reg_rep_0_i_2
(.I0(literal_2[10]),
.I1(\program_counter[15]_i_6_n_0 ),
.I2(\program_counter_reg[12]_i_3_n_6 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[10]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_2_n_0));
LUT6 #(
.INIT(64'h00000000FFE200E2))
program_counter_reg_rep_0_i_3
(.I0(literal_2[9]),
.I1(\program_counter[15]_i_6_n_0 ),
.I2(\program_counter_reg[12]_i_3_n_7 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[9]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_3_n_0));
LUT6 #(
.INIT(64'h00000000B8B8FFB8))
program_counter_reg_rep_0_i_4
(.I0(program_counter_reg_rep_0_i_13_n_0),
.I1(\program_counter[8]_i_4_n_0 ),
.I2(\program_counter_reg[8]_i_3_n_4 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[8]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_4_n_0));
LUT6 #(
.INIT(64'h00000000FFE200E2))
program_counter_reg_rep_0_i_5
(.I0(literal_2[7]),
.I1(\program_counter[15]_i_6_n_0 ),
.I2(\program_counter_reg[8]_i_3_n_5 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[7]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_5_n_0));
LUT6 #(
.INIT(64'h00000000B8B8FFB8))
program_counter_reg_rep_0_i_6
(.I0(program_counter_reg_rep_0_i_14_n_0),
.I1(\program_counter[8]_i_4_n_0 ),
.I2(\program_counter_reg[8]_i_3_n_6 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[6]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_6_n_0));
LUT6 #(
.INIT(64'h00000000FFE200E2))
program_counter_reg_rep_0_i_7
(.I0(literal_2[5]),
.I1(\program_counter[15]_i_6_n_0 ),
.I2(\program_counter_reg[8]_i_3_n_7 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[5]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_7_n_0));
LUT6 #(
.INIT(64'h00000000FFE200E2))
program_counter_reg_rep_0_i_8
(.I0(literal_2[4]),
.I1(\program_counter[15]_i_6_n_0 ),
.I2(\program_counter_reg[4]_i_3_n_4 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[4]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_8_n_0));
LUT6 #(
.INIT(64'h00000000FFE200E2))
program_counter_reg_rep_0_i_9
(.I0(address_b_2[3]),
.I1(\program_counter[15]_i_6_n_0 ),
.I2(\program_counter_reg[4]_i_3_n_5 ),
.I3(\program_counter[15]_i_4_n_0 ),
.I4(\program_counter[3]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_9_n_0));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* POWER_OPTED_CE = "REGCEAREGCE=AUG" *)
(* RTL_RAM_BITS = "59392" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "18" *)
(* bram_slice_end = "35" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'hFFC0000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INITP_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_00(256'h0020008000080020008000080020008000080020008000080020004C0010000C),
.INIT_01(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_02(256'h0080000800200080000800200080000800200080000800200080000800200080),
.INIT_03(256'h0020008000080020008000080020008000080020008000080020008000080020),
.INIT_04(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_05(256'h0080000800200080000800200080000800200080000800200080000800200080),
.INIT_06(256'h0020008000080020008000080020008000080020008000080020008000080020),
.INIT_07(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_08(256'h0080000800200080000800200080000800200080000800200080000800200080),
.INIT_09(256'h0020008000080020008000080020008000080020008000080020008000080020),
.INIT_0A(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_0B(256'h0080000800200080000800200080000800200080000800200080000800200080),
.INIT_0C(256'h0020008000080020008000080020008000080020008000080020008000080020),
.INIT_0D(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_0E(256'h0080000800200080000800200080000800200080000800200080000800200080),
.INIT_0F(256'h0020008000080020008000080020008000080020008000080020008000080020),
.INIT_10(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_11(256'h0080000800200080000800200080000800200080000800200080000800200080),
.INIT_12(256'h0020008000080020008000080020008000080020008000080020008000080020),
.INIT_13(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_14(256'h0080000800200080000800200080000800200080000800200080000800200080),
.INIT_15(256'h0020008000080020008000080020008000080020008000080020008000080020),
.INIT_16(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_17(256'h0080000800200080000800200080000800200080000800200080000800200080),
.INIT_18(256'h0020008000080020008000080020008000080020008000080020008000080020),
.INIT_19(256'h0008002000800008002000800008002000800008002000800008002000800008),
.INIT_1A(256'h0020004C010000D80050005D0080000800200080000800200080000800200080),
.INIT_1B(256'h004C00800020004C0080004C0080008000080160004A0020008000080160004A),
.INIT_1C(256'h004C00800020004C0080004C0080004C0158004C015C004C004C00D80050005D),
.INIT_1D(256'h00D80050005D004C0080004C0080004C0158004C015C004C004C00D80050005D),
.INIT_1E(256'h0160004A0061004C0080004C008000800049016000080158004C015C004C004C),
.INIT_1F(256'h0020004C0080004C0080004C0158004C015C004C004C00D80050005D004C0080),
.INIT_20(256'h0020004C0080004C0080004C0158004C015C004C004C00D80050005D004C0080),
.INIT_21(256'h005D004C0080004C0080004C0158004C015C004C004C00D80050005D004C0080),
.INIT_22(256'h0061004C0080004C008000800049016000080158004C015C004C004C00D80050),
.INIT_23(256'h0080004C0080004C0158004C015C004C004C00D80050005D004C00800160004A),
.INIT_24(256'h0080004C0080004C0158004C015C004C004C00D80050005D004C00800020004C),
.INIT_25(256'h0080004C0080004C0158004C015C004C004C00D80050005D004C00800020004C),
.INIT_26(256'h0080004C008000800049016000080158004C015C004C004C00D80050005D004C),
.INIT_27(256'h0080004C0158004C015C004C004C00D80050005D004C00800160004A0061004C),
.INIT_28(256'h0080004C0158004C015C004C004C00D80050005D004C00800020004C0080004C),
.INIT_29(256'h0160004A0061004C00800160004A0061004C00800160004A0061004C0080004C),
.INIT_2A(256'h004C01C10051004D0180004C0158004C015C004C004C00D80050005D004C0080),
.INIT_2B(256'h0050005D004C00800160004A0020004C00800160004A0061004C0080004C0080),
.INIT_2C(256'h004A0061008000490020004C01C10051004D004C0158004C015C004C004C00D8),
.INIT_2D(256'h00800160004A006102420160004A02220148004C0160004A0061004C00800160),
.INIT_2E(256'h0140004C0160004A02220148004C0160004A0061004C00800160004A0061004C),
.INIT_2F(256'h02220168004C0160004A0061004C00800020004C00800160004A0061004C0280),
.INIT_30(256'h0020004C0080004C0080004C01C10051004D0180018001800160004C00800049),
.INIT_31(256'h00800008016000080158004C015C004C004C00D80050005D004C00800160004A),
.INIT_32(256'h004C008000200080004902E20160004A0061008000490020004C01C10051004D),
.INIT_33(256'h004C015C004C004C00D80050005D004C00800160004A0061004C0080004C0080),
.INIT_34(256'h004C0160004A0061004C0080002001800180024203220168004C016000080158),
.INIT_35(256'h00D80050005D004C00800160004A0061004C0080004C00800080004903620168),
.INIT_36(256'h004902220168004C0160004A0061004C0080016000080158004C015C004C004C),
.INIT_37(256'h004A0061004C00800020004C01C10051004D008000080160004A006101800080),
.INIT_38(256'h002003C203A20168004C0020004C00800160004A0061024203A20168004C0160),
.INIT_39(256'h004C0020004C00800160004A0061024203A20168004C0160004A0061004C0080),
.INIT_3A(256'h0160004A0061024203A20168004C0160004A0061004C0080002003C203A20168),
.INIT_3B(256'h0061004C00800020004C01C10051004D0080000803A20168004C0020004C0080),
.INIT_3C(256'h024203A20168004C0020004C00800160004A0061024203A20168004C0160004A),
.INIT_3D(256'h0020018001C10051004D0080000804220168004C0160004A0061004C00800020),
.INIT_3E(256'h004C0020004C00800160004A0061024203A20168004C0160004A0061004C0080),
.INIT_3F(256'h004C04220168004C0160004A0061004C00800020004C00800020024203A20168),
.INIT_40(256'h0168004C0160004A0061004C00800020018001C10051004D0080000802220168),
.INIT_41(256'h0020004C00800020024203A20168004C0020004C00800160004A0061024203A2),
.INIT_42(256'h01C10051004D0080000802220168004C04220168004C0160004A0061004C0080),
.INIT_43(256'h00800160004A0061004C0080004C0080004C01C10051004D0080000800200180),
.INIT_44(256'h004D004C0158004C015C004C004C00D80050005D004C00800160004A0020004C),
.INIT_45(256'h0020008000490020008000490020008000490020008000490020004C01C10051),
.INIT_46(256'h0049002000800049002000800049002000800049002000800049002000800049),
.INIT_47(256'h0080004900200080004900200080004900200080004900200080004900200080),
.INIT_48(256'h004C0020004C00800160004A0061008000490020008000490020008000490020),
.INIT_49(256'h008000200080004904A20168004C0160004A0061004C00800020024204620168),
.INIT_4A(256'h00800061004C00800160004A00610080004903620168004C0160004A0061004C),
.INIT_4B(256'h0160004A0061004C02800140004C0160004A02220148004C0160004A0061004C),
.INIT_4C(256'h01800160004C0080004902220168004C0160004A0061004C00800020004C0080),
.INIT_4D(256'h004C02800140004C0160004A0061004C00800160004A0020004C01C10051004D),
.INIT_4E(256'h00800160004A0020004C02800140004C0160004A0061004C00800160004A0020),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFF01C10051004D004C02800140004C0160004A0061004C),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_1
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_1_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_1_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_1_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_1_DOADO_UNCONNECTED[31:11],opcode,address_z,address_a[3:2]}),
.DOBDO(NLW_program_counter_reg_rep_1_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_program_counter_reg_rep_1_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_program_counter_reg_rep_1_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_1_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_1_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_1_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_1_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(program_counter_reg_rep_1_REGCEAREGCE_cooolgate_en_sig_11),
.REGCEB(NLW_program_counter_reg_rep_1_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_1_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT3 #(
.INIT(8'h20))
program_counter_reg_rep_1_REGCEAREGCE_cooolgate_en_gate_21
(.I0(instruction0),
.I1(INTERNAL_RST_reg),
.I2(instruction0),
.O(program_counter_reg_rep_1_REGCEAREGCE_cooolgate_en_sig_11));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[0]_i_1
(.I0(result[0]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[0]),
.O(\read_input[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[10]_i_1
(.I0(result[10]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[10]),
.O(\read_input[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[11]_i_1
(.I0(result[11]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[11]),
.O(\read_input[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[12]_i_1
(.I0(result[12]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[12]),
.O(\read_input[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[13]_i_1
(.I0(result[13]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[13]),
.O(\read_input[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[14]_i_1
(.I0(result[14]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[14]),
.O(\read_input[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[15]_i_1
(.I0(result[15]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[15]),
.O(\read_input[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[16]_i_1
(.I0(result[16]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[16]),
.O(\read_input[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[17]_i_1
(.I0(result[17]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[17]),
.O(\read_input[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[18]_i_1
(.I0(result[18]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[18]),
.O(\read_input[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[19]_i_1
(.I0(result[19]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[19]),
.O(\read_input[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[1]_i_1
(.I0(result[1]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[1]),
.O(\read_input[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[20]_i_1
(.I0(result[20]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[20]),
.O(\read_input[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[21]_i_1
(.I0(result[21]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[21]),
.O(\read_input[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[22]_i_1
(.I0(result[22]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[22]),
.O(\read_input[22]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[23]_i_1
(.I0(result[23]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[23]),
.O(\read_input[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[24]_i_1
(.I0(result[24]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[24]),
.O(\read_input[24]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[25]_i_1
(.I0(result[25]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[25]),
.O(\read_input[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[26]_i_1
(.I0(result[26]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[26]),
.O(\read_input[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[27]_i_1
(.I0(result[27]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[27]),
.O(\read_input[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[28]_i_1
(.I0(result[28]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[28]),
.O(\read_input[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[29]_i_1
(.I0(result[29]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[29]),
.O(\read_input[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[2]_i_1
(.I0(result[2]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[2]),
.O(\read_input[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[30]_i_1
(.I0(result[30]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[30]),
.O(\read_input[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h2000000000000000))
\read_input[31]_i_1
(.I0(opcode_2[1]),
.I1(opcode_2[2]),
.I2(opcode_20),
.I3(\state_reg_n_0_[0] ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(opcode_2[3]),
.O(\read_input[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[31]_i_2
(.I0(result[31]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[31]),
.O(\read_input[31]_i_2_n_0 ));
LUT2 #(
.INIT(4'h2))
\read_input[31]_i_3
(.I0(opcode_2[0]),
.I1(opcode_2[4]),
.O(\read_input[31]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\read_input[31]_i_4
(.I0(address_a_2[2]),
.I1(address_z_3[2]),
.I2(address_a_2[1]),
.I3(address_z_3[1]),
.O(\read_input[31]_i_4_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\read_input[31]_i_5
(.I0(address_a_2[0]),
.I1(address_z_3[0]),
.I2(address_a_2[3]),
.I3(address_z_3[3]),
.O(\read_input[31]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[3]_i_1
(.I0(result[3]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[3]),
.O(\read_input[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[4]_i_1
(.I0(result[4]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[4]),
.O(\read_input[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[5]_i_1
(.I0(result[5]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[5]),
.O(\read_input[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[6]_i_1
(.I0(result[6]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[6]),
.O(\read_input[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[7]_i_1
(.I0(result[7]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[7]),
.O(\read_input[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[8]_i_1
(.I0(result[8]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[8]),
.O(\read_input[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[9]_i_1
(.I0(result[9]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[9]),
.O(\read_input[9]_i_1_n_0 ));
FDRE \read_input_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[0]_i_1_n_0 ),
.Q(read_input[0]),
.R(1'b0));
FDRE \read_input_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[10]_i_1_n_0 ),
.Q(read_input[10]),
.R(1'b0));
FDRE \read_input_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[11]_i_1_n_0 ),
.Q(read_input[11]),
.R(1'b0));
FDRE \read_input_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[12]_i_1_n_0 ),
.Q(read_input[12]),
.R(1'b0));
FDRE \read_input_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[13]_i_1_n_0 ),
.Q(read_input[13]),
.R(1'b0));
FDRE \read_input_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[14]_i_1_n_0 ),
.Q(read_input[14]),
.R(1'b0));
FDRE \read_input_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[15]_i_1_n_0 ),
.Q(read_input[15]),
.R(1'b0));
FDRE \read_input_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[16]_i_1_n_0 ),
.Q(read_input[16]),
.R(1'b0));
FDRE \read_input_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[17]_i_1_n_0 ),
.Q(read_input[17]),
.R(1'b0));
FDRE \read_input_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[18]_i_1_n_0 ),
.Q(read_input[18]),
.R(1'b0));
FDRE \read_input_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[19]_i_1_n_0 ),
.Q(read_input[19]),
.R(1'b0));
FDRE \read_input_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[1]_i_1_n_0 ),
.Q(read_input[1]),
.R(1'b0));
FDRE \read_input_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[20]_i_1_n_0 ),
.Q(read_input[20]),
.R(1'b0));
FDRE \read_input_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[21]_i_1_n_0 ),
.Q(read_input[21]),
.R(1'b0));
FDRE \read_input_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[22]_i_1_n_0 ),
.Q(read_input[22]),
.R(1'b0));
FDRE \read_input_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[23]_i_1_n_0 ),
.Q(read_input[23]),
.R(1'b0));
FDRE \read_input_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[24]_i_1_n_0 ),
.Q(read_input[24]),
.R(1'b0));
FDRE \read_input_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[25]_i_1_n_0 ),
.Q(read_input[25]),
.R(1'b0));
FDRE \read_input_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[26]_i_1_n_0 ),
.Q(read_input[26]),
.R(1'b0));
FDRE \read_input_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[27]_i_1_n_0 ),
.Q(read_input[27]),
.R(1'b0));
FDRE \read_input_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[28]_i_1_n_0 ),
.Q(read_input[28]),
.R(1'b0));
FDRE \read_input_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[29]_i_1_n_0 ),
.Q(read_input[29]),
.R(1'b0));
FDRE \read_input_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[2]_i_1_n_0 ),
.Q(read_input[2]),
.R(1'b0));
FDRE \read_input_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[30]_i_1_n_0 ),
.Q(read_input[30]),
.R(1'b0));
FDRE \read_input_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[31]_i_2_n_0 ),
.Q(read_input[31]),
.R(1'b0));
FDRE \read_input_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[3]_i_1_n_0 ),
.Q(read_input[3]),
.R(1'b0));
FDRE \read_input_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[4]_i_1_n_0 ),
.Q(read_input[4]),
.R(1'b0));
FDRE \read_input_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[5]_i_1_n_0 ),
.Q(read_input[5]),
.R(1'b0));
FDRE \read_input_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[6]_i_1_n_0 ),
.Q(read_input[6]),
.R(1'b0));
FDRE \read_input_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[7]_i_1_n_0 ),
.Q(read_input[7]),
.R(1'b0));
FDRE \read_input_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[8]_i_1_n_0 ),
.Q(read_input[8]),
.R(1'b0));
FDRE \read_input_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[9]_i_1_n_0 ),
.Q(read_input[9]),
.R(1'b0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_UNIQ_BASE_ registers_reg_r1_0_15_0_5
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[1:0]),
.DIB(result[3:2]),
.DIC(result[5:4]),
.DID({1'b0,1'b0}),
.DOA(register_b[1:0]),
.DOB(register_b[3:2]),
.DOC(register_b[5:4]),
.DOD(NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD5 registers_reg_r1_0_15_12_17
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[13:12]),
.DIB(result[15:14]),
.DIC(result[17:16]),
.DID({1'b0,1'b0}),
.DOA(register_b[13:12]),
.DOB(register_b[15:14]),
.DOC(register_b[17:16]),
.DOD(NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD6 registers_reg_r1_0_15_18_23
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[19:18]),
.DIB(result[21:20]),
.DIC(result[23:22]),
.DID({1'b0,1'b0}),
.DOA(register_b[19:18]),
.DOB(register_b[21:20]),
.DOC(register_b[23:22]),
.DOD(NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD7 registers_reg_r1_0_15_24_29
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[25:24]),
.DIB(result[27:26]),
.DIC(result[29:28]),
.DID({1'b0,1'b0}),
.DOA(register_b[25:24]),
.DOB(register_b[27:26]),
.DOC(register_b[29:28]),
.DOD(NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD8 registers_reg_r1_0_15_30_31
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[31:30]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(register_b[31:30]),
.DOB(NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED[1:0]),
.DOC(NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED[1:0]),
.DOD(NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD4 registers_reg_r1_0_15_6_11
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[7:6]),
.DIB(result[9:8]),
.DIC(result[11:10]),
.DID({1'b0,1'b0}),
.DOA(register_b[7:6]),
.DOB(register_b[9:8]),
.DOC(register_b[11:10]),
.DOD(NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD9 registers_reg_r2_0_15_0_5
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[1:0]),
.DIB(result[3:2]),
.DIC(result[5:4]),
.DID({1'b0,1'b0}),
.DOA(register_a[1:0]),
.DOB(register_a[3:2]),
.DOC(register_a[5:4]),
.DOD(NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD11 registers_reg_r2_0_15_12_17
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[13:12]),
.DIB(result[15:14]),
.DIC(result[17:16]),
.DID({1'b0,1'b0}),
.DOA(register_a[13:12]),
.DOB(register_a[15:14]),
.DOC(register_a[17:16]),
.DOD(NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD12 registers_reg_r2_0_15_18_23
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[19:18]),
.DIB(result[21:20]),
.DIC(result[23:22]),
.DID({1'b0,1'b0}),
.DOA(register_a[19:18]),
.DOB(register_a[21:20]),
.DOC(register_a[23:22]),
.DOD(NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD13 registers_reg_r2_0_15_24_29
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[25:24]),
.DIB(result[27:26]),
.DIC(result[29:28]),
.DID({1'b0,1'b0}),
.DOA(register_a[25:24]),
.DOB(register_a[27:26]),
.DOC(register_a[29:28]),
.DOD(NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD14 registers_reg_r2_0_15_30_31
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[31:30]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(register_a[31:30]),
.DOB(NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED[1:0]),
.DOC(NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED[1:0]),
.DOD(NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD10 registers_reg_r2_0_15_6_11
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[7:6]),
.DIB(result[9:8]),
.DIC(result[11:10]),
.DID({1'b0,1'b0}),
.DOA(register_a[7:6]),
.DOB(register_a[9:8]),
.DOC(register_a[11:10]),
.DOD(NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFF20000))
\result[0]_i_1
(.I0(\result[0]_i_2_n_0 ),
.I1(\result[0]_i_3_n_0 ),
.I2(\result[0]_i_4_n_0 ),
.I3(\result[0]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[0]_i_6_n_0 ),
.O(\result[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h9A95000000009A95))
\result[0]_i_100
(.I0(store_data[1]),
.I1(result[1]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_a[1]),
.I4(store_data[0]),
.I5(\read_input[0]_i_1_n_0 ),
.O(\result[0]_i_100_n_0 ));
LUT5 #(
.INIT(32'h000E2202))
\result[0]_i_101
(.I0(register_a[14]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[14]),
.I3(operand_b1),
.I4(result[14]),
.O(\result[0]_i_101_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_102
(.I0(register_a[11]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[11]),
.I3(operand_b1),
.I4(result[11]),
.O(\result[0]_i_102_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_103
(.I0(register_a[8]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[8]),
.I3(operand_b1),
.I4(result[8]),
.O(\result[0]_i_103_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_104
(.I0(\result[0]_i_109_n_0 ),
.I1(result[6]),
.I2(operand_b1),
.I3(register_b[6]),
.I4(\result[0]_i_43_n_0 ),
.I5(register_a[6]),
.O(\result[0]_i_104_n_0 ));
LUT5 #(
.INIT(32'h41444111))
\result[0]_i_105
(.I0(\result[0]_i_110_n_0 ),
.I1(store_data[4]),
.I2(result[4]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[4]),
.O(\result[0]_i_105_n_0 ));
LUT6 #(
.INIT(64'h9A95000000009A95))
\result[0]_i_106
(.I0(store_data[3]),
.I1(result[3]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_a[3]),
.I4(store_data[2]),
.I5(\read_input[2]_i_1_n_0 ),
.O(\result[0]_i_106_n_0 ));
LUT6 #(
.INIT(64'h9A95000000009A95))
\result[0]_i_107
(.I0(store_data[1]),
.I1(result[1]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_a[1]),
.I4(store_data[0]),
.I5(\read_input[0]_i_1_n_0 ),
.O(\result[0]_i_107_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_108
(.I0(\result[0]_i_102_n_0 ),
.I1(result[10]),
.I2(operand_b1),
.I3(register_b[10]),
.I4(\result[0]_i_43_n_0 ),
.I5(register_a[10]),
.O(\result[0]_i_108_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_109
(.I0(register_a[7]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[7]),
.I3(operand_b1),
.I4(result[7]),
.O(\result[0]_i_109_n_0 ));
LUT6 #(
.INIT(64'h0000000000000200))
\result[0]_i_11
(.I0(opcode_2[2]),
.I1(store_data[2]),
.I2(store_data[3]),
.I3(\read_input[0]_i_1_n_0 ),
.I4(store_data[4]),
.I5(store_data[1]),
.O(\result[0]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_110
(.I0(register_a[5]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[5]),
.I3(operand_b1),
.I4(result[5]),
.O(\result[0]_i_110_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[0]_i_111
(.I0(register_a[3]),
.I1(\result[0]_i_43_n_0 ),
.I2(result[3]),
.I3(store_data[3]),
.O(\result[0]_i_111_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[0]_i_13
(.I0(\read_input[24]_i_1_n_0 ),
.I1(\read_input[8]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[16]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[0]_i_1_n_0 ),
.O(\result[0]_i_13_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF02470200))
\result[0]_i_16
(.I0(result[31]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_a[31]),
.I3(operand_b1),
.I4(register_b[31]),
.I5(\result[0]_i_44_n_0 ),
.O(\result[0]_i_16_n_0 ));
LUT6 #(
.INIT(64'hEFFFEF4702470200))
\result[0]_i_17
(.I0(result[29]),
.I1(operand_b1),
.I2(register_b[29]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[29]),
.I5(\result[0]_i_45_n_0 ),
.O(\result[0]_i_17_n_0 ));
LUT6 #(
.INIT(64'hEFFFEF4702470200))
\result[0]_i_18
(.I0(result[27]),
.I1(operand_b1),
.I2(register_b[27]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[27]),
.I5(\result[0]_i_46_n_0 ),
.O(\result[0]_i_18_n_0 ));
LUT6 #(
.INIT(64'hEFFFEF4702470200))
\result[0]_i_19
(.I0(result[25]),
.I1(operand_b1),
.I2(register_b[25]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[25]),
.I5(\result[0]_i_47_n_0 ),
.O(\result[0]_i_19_n_0 ));
LUT2 #(
.INIT(4'h2))
\result[0]_i_2
(.I0(opcode_2[1]),
.I1(opcode_2[2]),
.O(\result[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_20
(.I0(\result[0]_i_48_n_0 ),
.I1(register_a[30]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[30]),
.I4(operand_b1),
.I5(result[30]),
.O(\result[0]_i_20_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_21
(.I0(\result[0]_i_49_n_0 ),
.I1(register_a[28]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[28]),
.I4(operand_b1),
.I5(result[28]),
.O(\result[0]_i_21_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_22
(.I0(\result[0]_i_50_n_0 ),
.I1(register_a[26]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[26]),
.I4(operand_b1),
.I5(result[26]),
.O(\result[0]_i_22_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_23
(.I0(register_a[24]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[24]),
.I3(operand_b1),
.I4(result[24]),
.I5(\result[0]_i_51_n_0 ),
.O(\result[0]_i_23_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF02470200))
\result[0]_i_25
(.I0(result[31]),
.I1(operand_b1),
.I2(register_b[31]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[31]),
.I5(\result[0]_i_44_n_0 ),
.O(\result[0]_i_25_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_26
(.I0(\result[0]_i_48_n_0 ),
.I1(register_a[30]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[30]),
.I4(operand_b1),
.I5(result[30]),
.O(\result[0]_i_26_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_27
(.I0(\result[0]_i_49_n_0 ),
.I1(register_a[28]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[28]),
.I4(operand_b1),
.I5(result[28]),
.O(\result[0]_i_27_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_28
(.I0(\result[0]_i_50_n_0 ),
.I1(register_a[26]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[26]),
.I4(operand_b1),
.I5(result[26]),
.O(\result[0]_i_28_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_29
(.I0(register_a[24]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[24]),
.I3(operand_b1),
.I4(result[24]),
.I5(\result[0]_i_51_n_0 ),
.O(\result[0]_i_29_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8BBBBBBB8BB))
\result[0]_i_3
(.I0(program_counter_2[0]),
.I1(opcode_2[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[0]_i_7_n_0 ),
.I4(store_data[0]),
.I5(\result[1]_i_8_n_0 ),
.O(\result[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_31
(.I0(\result[0]_i_48_n_0 ),
.I1(register_a[30]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[30]),
.I4(operand_b1),
.I5(result[30]),
.O(\result[0]_i_31_n_0 ));
LUT6 #(
.INIT(64'hA8A8A802A2A208A2))
\result[0]_i_32
(.I0(\result[0]_i_62_n_0 ),
.I1(register_a[27]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[27]),
.I4(operand_b1),
.I5(result[27]),
.O(\result[0]_i_32_n_0 ));
LUT6 #(
.INIT(64'hA8A8A802A2A208A2))
\result[0]_i_33
(.I0(\result[0]_i_63_n_0 ),
.I1(register_a[26]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[26]),
.I4(operand_b1),
.I5(result[26]),
.O(\result[0]_i_33_n_0 ));
LUT6 #(
.INIT(64'hEFFFEF4702470200))
\result[0]_i_35
(.I0(result[23]),
.I1(operand_b1),
.I2(register_b[23]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[23]),
.I5(\result[0]_i_73_n_0 ),
.O(\result[0]_i_35_n_0 ));
LUT6 #(
.INIT(64'hEFFFEF4702470200))
\result[0]_i_36
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[21]),
.I5(\result[0]_i_74_n_0 ),
.O(\result[0]_i_36_n_0 ));
LUT6 #(
.INIT(64'hEFFFEF4702470200))
\result[0]_i_37
(.I0(result[19]),
.I1(operand_b1),
.I2(register_b[19]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[19]),
.I5(\result[0]_i_75_n_0 ),
.O(\result[0]_i_37_n_0 ));
LUT6 #(
.INIT(64'h444444D4D4D444D4))
\result[0]_i_38
(.I0(store_data[17]),
.I1(\read_input[17]_i_1_n_0 ),
.I2(\read_input[16]_i_1_n_0 ),
.I3(register_b[16]),
.I4(operand_b1),
.I5(result[16]),
.O(\result[0]_i_38_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_39
(.I0(\result[0]_i_76_n_0 ),
.I1(register_a[22]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[22]),
.I4(operand_b1),
.I5(result[22]),
.O(\result[0]_i_39_n_0 ));
LUT5 #(
.INIT(32'hFCDDCCDD))
\result[0]_i_4
(.I0(\result[0]_i_8_n_0 ),
.I1(\result[0]_i_9_n_0 ),
.I2(data6),
.I3(opcode_2[1]),
.I4(opcode_2[2]),
.O(\result[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_40
(.I0(register_a[21]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[21]),
.I3(operand_b1),
.I4(result[21]),
.I5(\result[0]_i_77_n_0 ),
.O(\result[0]_i_40_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_41
(.I0(\result[0]_i_78_n_0 ),
.I1(register_a[18]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[18]),
.I4(operand_b1),
.I5(result[18]),
.O(\result[0]_i_41_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_42
(.I0(\result[0]_i_79_n_0 ),
.I1(register_a[16]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[16]),
.I4(operand_b1),
.I5(result[16]),
.O(\result[0]_i_42_n_0 ));
LUT6 #(
.INIT(64'h2002000000002002))
\result[0]_i_43
(.I0(write_enable_reg_n_0),
.I1(\read_input[31]_i_4_n_0 ),
.I2(address_a_2[0]),
.I3(address_z_3[0]),
.I4(address_a_2[3]),
.I5(address_z_3[3]),
.O(\result[0]_i_43_n_0 ));
LUT6 #(
.INIT(64'h0000000002470200))
\result[0]_i_44
(.I0(result[30]),
.I1(operand_b1),
.I2(register_b[30]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[30]),
.I5(\result[0]_i_48_n_0 ),
.O(\result[0]_i_44_n_0 ));
LUT5 #(
.INIT(32'h000E2202))
\result[0]_i_45
(.I0(register_a[28]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[28]),
.I3(operand_b1),
.I4(result[28]),
.O(\result[0]_i_45_n_0 ));
LUT5 #(
.INIT(32'h000E2202))
\result[0]_i_46
(.I0(register_a[26]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[26]),
.I3(operand_b1),
.I4(result[26]),
.O(\result[0]_i_46_n_0 ));
LUT5 #(
.INIT(32'h000E2202))
\result[0]_i_47
(.I0(register_a[24]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[24]),
.I3(operand_b1),
.I4(result[24]),
.O(\result[0]_i_47_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_48
(.I0(result[31]),
.I1(operand_b1),
.I2(register_b[31]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[31]),
.O(\result[0]_i_48_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_49
(.I0(result[29]),
.I1(operand_b1),
.I2(register_b[29]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[29]),
.O(\result[0]_i_49_n_0 ));
LUT6 #(
.INIT(64'hAAAA000800080008))
\result[0]_i_5
(.I0(opcode_2[0]),
.I1(\result[0]_i_11_n_0 ),
.I2(\result[31]_i_12_n_0 ),
.I3(store_data[0]),
.I4(opcode_2[4]),
.I5(data8),
.O(\result[0]_i_5_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_50
(.I0(result[27]),
.I1(operand_b1),
.I2(register_b[27]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[27]),
.O(\result[0]_i_50_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_51
(.I0(result[25]),
.I1(operand_b1),
.I2(register_b[25]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[25]),
.O(\result[0]_i_51_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_53
(.I0(\result[0]_i_76_n_0 ),
.I1(register_a[22]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[22]),
.I4(operand_b1),
.I5(result[22]),
.O(\result[0]_i_53_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_54
(.I0(register_a[21]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[21]),
.I3(operand_b1),
.I4(result[21]),
.I5(\result[0]_i_77_n_0 ),
.O(\result[0]_i_54_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_55
(.I0(\result[0]_i_78_n_0 ),
.I1(register_a[18]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[18]),
.I4(operand_b1),
.I5(result[18]),
.O(\result[0]_i_55_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_56
(.I0(\result[0]_i_79_n_0 ),
.I1(register_a[16]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[16]),
.I4(operand_b1),
.I5(result[16]),
.O(\result[0]_i_56_n_0 ));
LUT6 #(
.INIT(64'hEDB8ED4700000000))
\result[0]_i_58
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[21]),
.I5(\result[0]_i_89_n_0 ),
.O(\result[0]_i_58_n_0 ));
LUT6 #(
.INIT(64'h000000000000B847))
\result[0]_i_59
(.I0(result[18]),
.I1(operand_b1),
.I2(register_b[18]),
.I3(\read_input[18]_i_1_n_0 ),
.I4(\result[0]_i_78_n_0 ),
.I5(\result[0]_i_77_n_0 ),
.O(\result[0]_i_59_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[0]_i_6
(.I0(load_data[0]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[0]),
.I3(\state_reg_n_0_[2] ),
.O(\result[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'hEEE1DD2D00000000))
\result[0]_i_60
(.I0(register_a[15]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.I5(\result[0]_i_90_n_0 ),
.O(\result[0]_i_60_n_0 ));
LUT6 #(
.INIT(64'h000000000000A959))
\result[0]_i_61
(.I0(\read_input[12]_i_1_n_0 ),
.I1(register_b[12]),
.I2(operand_b1),
.I3(result[12]),
.I4(\result[0]_i_91_n_0 ),
.I5(\result[0]_i_92_n_0 ),
.O(\result[0]_i_61_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_62
(.I0(\result[0]_i_49_n_0 ),
.I1(register_a[28]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[28]),
.I4(operand_b1),
.I5(result[28]),
.O(\result[0]_i_62_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_63
(.I0(register_a[24]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[24]),
.I3(operand_b1),
.I4(result[24]),
.I5(\result[0]_i_51_n_0 ),
.O(\result[0]_i_63_n_0 ));
LUT6 #(
.INIT(64'hEEEFFF2F000E2202))
\result[0]_i_65
(.I0(register_a[15]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.I5(\result[0]_i_101_n_0 ),
.O(\result[0]_i_65_n_0 ));
LUT6 #(
.INIT(64'h222222B2B2B222B2))
\result[0]_i_66
(.I0(\read_input[13]_i_1_n_0 ),
.I1(store_data[13]),
.I2(\read_input[12]_i_1_n_0 ),
.I3(register_b[12]),
.I4(operand_b1),
.I5(result[12]),
.O(\result[0]_i_66_n_0 ));
LUT6 #(
.INIT(64'h222222B2B2B222B2))
\result[0]_i_67
(.I0(\read_input[11]_i_1_n_0 ),
.I1(store_data[11]),
.I2(\read_input[10]_i_1_n_0 ),
.I3(register_b[10]),
.I4(operand_b1),
.I5(result[10]),
.O(\result[0]_i_67_n_0 ));
LUT6 #(
.INIT(64'h222222B2B2B222B2))
\result[0]_i_68
(.I0(\read_input[9]_i_1_n_0 ),
.I1(store_data[9]),
.I2(\read_input[8]_i_1_n_0 ),
.I3(register_b[8]),
.I4(operand_b1),
.I5(result[8]),
.O(\result[0]_i_68_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_69
(.I0(result[15]),
.I1(operand_b1),
.I2(register_b[15]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[15]),
.I5(\result[0]_i_92_n_0 ),
.O(\result[0]_i_69_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[0]_i_7
(.I0(\result[6]_i_9_n_0 ),
.I1(\result[2]_i_9_n_0 ),
.I2(store_data[1]),
.I3(\result[4]_i_10_n_0 ),
.I4(store_data[2]),
.I5(\result[0]_i_13_n_0 ),
.O(\result[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_70
(.I0(\result[0]_i_91_n_0 ),
.I1(result[12]),
.I2(operand_b1),
.I3(register_b[12]),
.I4(\result[0]_i_43_n_0 ),
.I5(register_a[12]),
.O(\result[0]_i_70_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_71
(.I0(\result[0]_i_102_n_0 ),
.I1(result[10]),
.I2(operand_b1),
.I3(register_b[10]),
.I4(\result[0]_i_43_n_0 ),
.I5(register_a[10]),
.O(\result[0]_i_71_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_72
(.I0(result[9]),
.I1(operand_b1),
.I2(register_b[9]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[9]),
.I5(\result[0]_i_103_n_0 ),
.O(\result[0]_i_72_n_0 ));
LUT5 #(
.INIT(32'h000E2202))
\result[0]_i_73
(.I0(register_a[22]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[22]),
.I3(operand_b1),
.I4(result[22]),
.O(\result[0]_i_73_n_0 ));
LUT5 #(
.INIT(32'h000E2202))
\result[0]_i_74
(.I0(register_a[20]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[20]),
.I3(operand_b1),
.I4(result[20]),
.O(\result[0]_i_74_n_0 ));
LUT5 #(
.INIT(32'h000E2202))
\result[0]_i_75
(.I0(register_a[18]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[18]),
.I3(operand_b1),
.I4(result[18]),
.O(\result[0]_i_75_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_76
(.I0(result[23]),
.I1(operand_b1),
.I2(register_b[23]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[23]),
.O(\result[0]_i_76_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_77
(.I0(result[20]),
.I1(operand_b1),
.I2(register_b[20]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[20]),
.O(\result[0]_i_77_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_78
(.I0(result[19]),
.I1(operand_b1),
.I2(register_b[19]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[19]),
.O(\result[0]_i_78_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_79
(.I0(result[17]),
.I1(operand_b1),
.I2(register_b[17]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[17]),
.O(\result[0]_i_79_n_0 ));
LUT6 #(
.INIT(64'hCCCCCFFFC7F7C7F7))
\result[0]_i_8
(.I0(\result_reg[3]_i_10_n_7 ),
.I1(opcode_2[0]),
.I2(opcode_2[2]),
.I3(data4),
.I4(data7[0]),
.I5(opcode_2[4]),
.O(\result[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_81
(.I0(result[15]),
.I1(operand_b1),
.I2(register_b[15]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[15]),
.I5(\result[0]_i_92_n_0 ),
.O(\result[0]_i_81_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_82
(.I0(\result[0]_i_91_n_0 ),
.I1(result[12]),
.I2(operand_b1),
.I3(register_b[12]),
.I4(\result[0]_i_43_n_0 ),
.I5(register_a[12]),
.O(\result[0]_i_82_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_83
(.I0(\result[0]_i_102_n_0 ),
.I1(result[10]),
.I2(operand_b1),
.I3(register_b[10]),
.I4(\result[0]_i_43_n_0 ),
.I5(register_a[10]),
.O(\result[0]_i_83_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_84
(.I0(result[9]),
.I1(operand_b1),
.I2(register_b[9]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[9]),
.I5(\result[0]_i_103_n_0 ),
.O(\result[0]_i_84_n_0 ));
LUT6 #(
.INIT(64'hEEE1DD2D00000000))
\result[0]_i_85
(.I0(register_a[9]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[9]),
.I3(operand_b1),
.I4(result[9]),
.I5(\result[0]_i_108_n_0 ),
.O(\result[0]_i_85_n_0 ));
LUT6 #(
.INIT(64'h000000000000A959))
\result[0]_i_86
(.I0(\read_input[6]_i_1_n_0 ),
.I1(register_b[6]),
.I2(operand_b1),
.I3(result[6]),
.I4(\result[0]_i_109_n_0 ),
.I5(\result[0]_i_103_n_0 ),
.O(\result[0]_i_86_n_0 ));
LUT6 #(
.INIT(64'h0000000054040151))
\result[0]_i_87
(.I0(\result[0]_i_110_n_0 ),
.I1(register_a[4]),
.I2(\result[0]_i_43_n_0 ),
.I3(result[4]),
.I4(store_data[4]),
.I5(\result[0]_i_111_n_0 ),
.O(\result[0]_i_87_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\result[0]_i_88
(.I0(\read_input[0]_i_1_n_0 ),
.I1(store_data[0]),
.I2(\read_input[2]_i_1_n_0 ),
.I3(store_data[2]),
.I4(\read_input[1]_i_1_n_0 ),
.I5(store_data[1]),
.O(\result[0]_i_88_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_89
(.I0(\result[0]_i_76_n_0 ),
.I1(register_a[22]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[22]),
.I4(operand_b1),
.I5(result[22]),
.O(\result[0]_i_89_n_0 ));
LUT6 #(
.INIT(64'h4444000F44440000))
\result[0]_i_9
(.I0(opcode_2[2]),
.I1(\result_reg[3]_i_11_n_7 ),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.I5(address_b_2[0]),
.O(\result[0]_i_9_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_90
(.I0(\result[0]_i_79_n_0 ),
.I1(register_a[16]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_b[16]),
.I4(operand_b1),
.I5(result[16]),
.O(\result[0]_i_90_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_91
(.I0(register_a[13]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[13]),
.I3(operand_b1),
.I4(result[13]),
.O(\result[0]_i_91_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_92
(.I0(register_a[14]),
.I1(\result[0]_i_43_n_0 ),
.I2(register_b[14]),
.I3(operand_b1),
.I4(result[14]),
.O(\result[0]_i_92_n_0 ));
LUT6 #(
.INIT(64'h222222B2B2B222B2))
\result[0]_i_93
(.I0(\read_input[7]_i_1_n_0 ),
.I1(store_data[7]),
.I2(\read_input[6]_i_1_n_0 ),
.I3(register_b[6]),
.I4(operand_b1),
.I5(result[6]),
.O(\result[0]_i_93_n_0 ));
LUT6 #(
.INIT(64'h02A202A2ABFB02A2))
\result[0]_i_94
(.I0(\read_input[5]_i_1_n_0 ),
.I1(register_b[5]),
.I2(operand_b1),
.I3(result[5]),
.I4(\read_input[4]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[0]_i_94_n_0 ));
LUT6 #(
.INIT(64'h54040000FFFF5404))
\result[0]_i_95
(.I0(store_data[2]),
.I1(register_a[2]),
.I2(\result[0]_i_43_n_0 ),
.I3(result[2]),
.I4(\read_input[3]_i_1_n_0 ),
.I5(store_data[3]),
.O(\result[0]_i_95_n_0 ));
LUT6 #(
.INIT(64'h22222222BBB222B2))
\result[0]_i_96
(.I0(\read_input[1]_i_1_n_0 ),
.I1(store_data[1]),
.I2(register_a[0]),
.I3(\result[0]_i_43_n_0 ),
.I4(result[0]),
.I5(store_data[0]),
.O(\result[0]_i_96_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_97
(.I0(\result[0]_i_109_n_0 ),
.I1(result[6]),
.I2(operand_b1),
.I3(register_b[6]),
.I4(\result[0]_i_43_n_0 ),
.I5(register_a[6]),
.O(\result[0]_i_97_n_0 ));
LUT5 #(
.INIT(32'h41444111))
\result[0]_i_98
(.I0(\result[0]_i_110_n_0 ),
.I1(store_data[4]),
.I2(result[4]),
.I3(\result[0]_i_43_n_0 ),
.I4(register_a[4]),
.O(\result[0]_i_98_n_0 ));
LUT6 #(
.INIT(64'h9A95000000009A95))
\result[0]_i_99
(.I0(store_data[3]),
.I1(result[3]),
.I2(\result[0]_i_43_n_0 ),
.I3(register_a[3]),
.I4(store_data[2]),
.I5(\read_input[2]_i_1_n_0 ),
.O(\result[0]_i_99_n_0 ));
LUT6 #(
.INIT(64'hBABABABAAABAAAAA))
\result[10]_i_1
(.I0(\result[10]_i_2_n_0 ),
.I1(\result[10]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(opcode_2[0]),
.I4(\result[10]_i_4_n_0 ),
.I5(\result[10]_i_5_n_0 ),
.O(\result[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\result[10]_i_10
(.I0(\read_input[3]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[4]),
.I3(\read_input[7]_i_1_n_0 ),
.I4(store_data[3]),
.O(\result[10]_i_10_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[10]_i_11
(.I0(\read_input[18]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[26]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[10]_i_1_n_0 ),
.O(\result[10]_i_11_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[10]_i_2
(.I0(load_data[10]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000A2A2A0AA))
\result[10]_i_3
(.I0(\result[10]_i_6_n_0 ),
.I1(\result[10]_i_7_n_0 ),
.I2(\result[16]_i_7_n_0 ),
.I3(\result[11]_i_7_n_0 ),
.I4(store_data[0]),
.I5(\result[10]_i_8_n_0 ),
.O(\result[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[10]_i_4
(.I0(\result[10]_i_9_n_0 ),
.I1(store_data[0]),
.I2(\result[11]_i_9_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[10]),
.O(\result[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[10]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[10]),
.I3(opcode_2[1]),
.I4(\result_reg[11]_i_11_n_5 ),
.I5(opcode_2[0]),
.O(\result[10]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFCCD))
\result[10]_i_6
(.I0(literal_2[10]),
.I1(opcode_2[3]),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.O(\result[10]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[10]_i_7
(.I0(\result[10]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[12]_i_11_n_0 ),
.O(\result[10]_i_7_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[10]_i_8
(.I0(\result_reg[11]_i_13_n_5 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[10]_i_8_n_0 ));
LUT6 #(
.INIT(64'h5F50CFCF5F50C0C0))
\result[10]_i_9
(.I0(\result[16]_i_19_n_0 ),
.I1(\result[12]_i_12_n_0 ),
.I2(store_data[1]),
.I3(\result[14]_i_9_n_0 ),
.I4(store_data[2]),
.I5(\result[10]_i_11_n_0 ),
.O(\result[10]_i_9_n_0 ));
LUT6 #(
.INIT(64'hBABABABAAABAAAAA))
\result[11]_i_1
(.I0(\result[11]_i_2_n_0 ),
.I1(\result[11]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(opcode_2[0]),
.I4(\result[11]_i_4_n_0 ),
.I5(\result[11]_i_5_n_0 ),
.O(\result[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\result[11]_i_12
(.I0(\read_input[4]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[0]_i_1_n_0 ),
.I3(store_data[3]),
.I4(\read_input[8]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[11]_i_12_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[11]_i_14
(.I0(\read_input[19]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[27]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[11]_i_1_n_0 ),
.O(\result[11]_i_14_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[11]_i_15
(.I0(result[11]),
.I1(operand_b1),
.I2(register_b[11]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[11]),
.O(\result[11]_i_15_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[11]_i_16
(.I0(result[10]),
.I1(operand_b1),
.I2(register_b[10]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[10]),
.O(\result[11]_i_16_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[11]_i_17
(.I0(result[9]),
.I1(operand_b1),
.I2(register_b[9]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[9]),
.O(\result[11]_i_17_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[11]_i_18
(.I0(result[8]),
.I1(operand_b1),
.I2(register_b[8]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[8]),
.O(\result[11]_i_18_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_19
(.I0(register_a[11]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[11]),
.I3(literal_2[11]),
.O(\result[11]_i_19_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[11]_i_2
(.I0(load_data[11]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[11]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_20
(.I0(register_a[10]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[10]),
.I3(literal_2[10]),
.O(\result[11]_i_20_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_21
(.I0(register_a[9]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[9]),
.I3(literal_2[9]),
.O(\result[11]_i_21_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_22
(.I0(register_a[8]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[8]),
.I3(literal_2[8]),
.O(\result[11]_i_22_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_23
(.I0(register_a[11]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[11]),
.I3(operand_b1),
.I4(result[11]),
.O(\result[11]_i_23_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_24
(.I0(register_a[10]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[10]),
.I3(operand_b1),
.I4(result[10]),
.O(\result[11]_i_24_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_25
(.I0(register_a[9]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[9]),
.I3(operand_b1),
.I4(result[9]),
.O(\result[11]_i_25_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[11]_i_26
(.I0(register_a[8]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[8]),
.I3(operand_b1),
.I4(result[8]),
.O(\result[11]_i_26_n_0 ));
LUT6 #(
.INIT(64'h00000000A2A2A0AA))
\result[11]_i_3
(.I0(\result[11]_i_6_n_0 ),
.I1(\result[11]_i_7_n_0 ),
.I2(\result[16]_i_7_n_0 ),
.I3(\result[12]_i_7_n_0 ),
.I4(store_data[0]),
.I5(\result[11]_i_8_n_0 ),
.O(\result[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[11]_i_4
(.I0(\result[11]_i_9_n_0 ),
.I1(store_data[0]),
.I2(\result[12]_i_9_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[11]),
.O(\result[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[11]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[11]),
.I3(opcode_2[1]),
.I4(\result_reg[11]_i_11_n_4 ),
.I5(opcode_2[0]),
.O(\result[11]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFCCD))
\result[11]_i_6
(.I0(literal_2[11]),
.I1(opcode_2[3]),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.O(\result[11]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[11]_i_7
(.I0(\result[11]_i_12_n_0 ),
.I1(store_data[1]),
.I2(\result[13]_i_10_n_0 ),
.O(\result[11]_i_7_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[11]_i_8
(.I0(\result_reg[11]_i_13_n_4 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[11]_i_8_n_0 ));
LUT6 #(
.INIT(64'h5F50CFCF5F50C0C0))
\result[11]_i_9
(.I0(\result[17]_i_10_n_0 ),
.I1(\result[13]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[15]_i_15_n_0 ),
.I4(store_data[2]),
.I5(\result[11]_i_14_n_0 ),
.O(\result[11]_i_9_n_0 ));
LUT6 #(
.INIT(64'hBABABABAAABAAAAA))
\result[12]_i_1
(.I0(\result[12]_i_2_n_0 ),
.I1(\result[12]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(opcode_2[0]),
.I4(\result[12]_i_4_n_0 ),
.I5(\result[12]_i_5_n_0 ),
.O(\result[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\result[12]_i_11
(.I0(\read_input[5]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[1]_i_1_n_0 ),
.I3(store_data[3]),
.I4(\read_input[9]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[12]_i_11_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[12]_i_12
(.I0(\read_input[20]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[28]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[12]_i_1_n_0 ),
.O(\result[12]_i_12_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[12]_i_2
(.I0(load_data[12]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000A2A2A0AA))
\result[12]_i_3
(.I0(\result[12]_i_6_n_0 ),
.I1(\result[12]_i_7_n_0 ),
.I2(\result[16]_i_7_n_0 ),
.I3(\result[13]_i_7_n_0 ),
.I4(store_data[0]),
.I5(\result[12]_i_8_n_0 ),
.O(\result[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[12]_i_4
(.I0(\result[12]_i_9_n_0 ),
.I1(store_data[0]),
.I2(\result[13]_i_9_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[12]),
.O(\result[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[12]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[12]),
.I3(opcode_2[1]),
.I4(\result_reg[15]_i_9_n_7 ),
.I5(opcode_2[0]),
.O(\result[12]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFCCD))
\result[12]_i_6
(.I0(literal_2[12]),
.I1(opcode_2[3]),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.O(\result[12]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[12]_i_7
(.I0(\result[12]_i_11_n_0 ),
.I1(store_data[1]),
.I2(\result[14]_i_8_n_0 ),
.O(\result[12]_i_7_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[12]_i_8
(.I0(\result_reg[19]_i_12_n_7 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[12]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505FCFCF505FC0C0))
\result[12]_i_9
(.I0(\result[18]_i_11_n_0 ),
.I1(\result[14]_i_9_n_0 ),
.I2(store_data[1]),
.I3(\result[16]_i_19_n_0 ),
.I4(store_data[2]),
.I5(\result[12]_i_12_n_0 ),
.O(\result[12]_i_9_n_0 ));
LUT6 #(
.INIT(64'hBABABABAAABAAAAA))
\result[13]_i_1
(.I0(\result[13]_i_2_n_0 ),
.I1(\result[13]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(opcode_2[0]),
.I4(\result[13]_i_4_n_0 ),
.I5(\result[13]_i_5_n_0 ),
.O(\result[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\result[13]_i_10
(.I0(\read_input[6]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[2]_i_1_n_0 ),
.I3(store_data[3]),
.I4(\read_input[10]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[13]_i_10_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[13]_i_11
(.I0(\read_input[21]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[29]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[13]_i_1_n_0 ),
.O(\result[13]_i_11_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[13]_i_2
(.I0(load_data[13]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000A2A2A0AA))
\result[13]_i_3
(.I0(\result[13]_i_6_n_0 ),
.I1(\result[13]_i_7_n_0 ),
.I2(\result[16]_i_7_n_0 ),
.I3(\result[14]_i_6_n_0 ),
.I4(store_data[0]),
.I5(\result[13]_i_8_n_0 ),
.O(\result[13]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[13]_i_4
(.I0(\result[13]_i_9_n_0 ),
.I1(store_data[0]),
.I2(\result[14]_i_7_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[13]),
.O(\result[13]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[13]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[13]),
.I3(opcode_2[1]),
.I4(\result_reg[15]_i_9_n_6 ),
.I5(opcode_2[0]),
.O(\result[13]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFCCD))
\result[13]_i_6
(.I0(literal_2[13]),
.I1(opcode_2[3]),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.O(\result[13]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\result[13]_i_7
(.I0(\result[13]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[15]_i_10_n_0 ),
.I3(store_data[2]),
.I4(\result[19]_i_19_n_0 ),
.O(\result[13]_i_7_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[13]_i_8
(.I0(\result_reg[19]_i_12_n_6 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[13]_i_8_n_0 ));
LUT6 #(
.INIT(64'hA0AFCFCFA0AFC0C0))
\result[13]_i_9
(.I0(\result[19]_i_17_n_0 ),
.I1(\result[15]_i_15_n_0 ),
.I2(store_data[1]),
.I3(\result[17]_i_10_n_0 ),
.I4(store_data[2]),
.I5(\result[13]_i_11_n_0 ),
.O(\result[13]_i_9_n_0 ));
LUT6 #(
.INIT(64'h4F4F4F4F444F4444))
\result[14]_i_1
(.I0(\result[16]_i_2_n_0 ),
.I1(load_data[14]),
.I2(\result[14]_i_2_n_0 ),
.I3(opcode_2[0]),
.I4(\result[14]_i_3_n_0 ),
.I5(\result[14]_i_4_n_0 ),
.O(\result[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h51515055FFFFFFFF))
\result[14]_i_2
(.I0(\result[14]_i_5_n_0 ),
.I1(\result[14]_i_6_n_0 ),
.I2(\result[16]_i_7_n_0 ),
.I3(\result[15]_i_6_n_0 ),
.I4(store_data[0]),
.I5(\state_reg_n_0_[0] ),
.O(\result[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[14]_i_3
(.I0(\result[14]_i_7_n_0 ),
.I1(store_data[0]),
.I2(\result[15]_i_8_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[14]),
.O(\result[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[14]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[14]),
.I3(opcode_2[1]),
.I4(\result_reg[15]_i_9_n_5 ),
.I5(opcode_2[0]),
.O(\result[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h005E005EFF5E005E))
\result[14]_i_5
(.I0(opcode_2[4]),
.I1(literal_2[14]),
.I2(opcode_2[0]),
.I3(opcode_2[3]),
.I4(\result_reg[19]_i_12_n_5 ),
.I5(opcode_2[2]),
.O(\result[14]_i_5_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\result[14]_i_6
(.I0(\result[14]_i_8_n_0 ),
.I1(store_data[1]),
.I2(\result[16]_i_13_n_0 ),
.I3(store_data[2]),
.I4(\result[20]_i_11_n_0 ),
.O(\result[14]_i_6_n_0 ));
LUT6 #(
.INIT(64'h505F3F3F505F3030))
\result[14]_i_7
(.I0(\result[16]_i_18_n_0 ),
.I1(\result[16]_i_19_n_0 ),
.I2(store_data[1]),
.I3(\result[18]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[14]_i_9_n_0 ),
.O(\result[14]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\result[14]_i_8
(.I0(\read_input[7]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[3]_i_1_n_0 ),
.I3(store_data[3]),
.I4(\read_input[11]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[14]_i_8_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[14]_i_9
(.I0(\read_input[22]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[30]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[14]_i_1_n_0 ),
.O(\result[14]_i_9_n_0 ));
LUT6 #(
.INIT(64'h4F4F4F4F4444444F))
\result[15]_i_1
(.I0(\result[16]_i_2_n_0 ),
.I1(load_data[15]),
.I2(\result[15]_i_2_n_0 ),
.I3(\result[15]_i_3_n_0 ),
.I4(opcode_2[0]),
.I5(\result[15]_i_4_n_0 ),
.O(\result[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000000E2FFE200))
\result[15]_i_10
(.I0(register_a[0]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[0]),
.I3(store_data[3]),
.I4(\read_input[8]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[15]_i_10_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[15]_i_11
(.I0(result[15]),
.I1(operand_b1),
.I2(register_b[15]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[15]),
.O(\result[15]_i_11_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[15]_i_12
(.I0(result[14]),
.I1(operand_b1),
.I2(register_b[14]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[14]),
.O(\result[15]_i_12_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[15]_i_13
(.I0(result[13]),
.I1(operand_b1),
.I2(register_b[13]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[13]),
.O(\result[15]_i_13_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[15]_i_14
(.I0(result[12]),
.I1(operand_b1),
.I2(register_b[12]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[12]),
.O(\result[15]_i_14_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[15]_i_15
(.I0(\read_input[23]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[31]_i_2_n_0 ),
.I3(store_data[4]),
.I4(\read_input[15]_i_1_n_0 ),
.O(\result[15]_i_15_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_16
(.I0(register_a[15]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[15]),
.I3(literal_2[15]),
.O(\result[15]_i_16_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_17
(.I0(register_a[14]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[14]),
.I3(literal_2[14]),
.O(\result[15]_i_17_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_18
(.I0(register_a[13]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[13]),
.I3(literal_2[13]),
.O(\result[15]_i_18_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_19
(.I0(register_a[12]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[12]),
.I3(literal_2[12]),
.O(\result[15]_i_19_n_0 ));
LUT6 #(
.INIT(64'h51515055FFFFFFFF))
\result[15]_i_2
(.I0(\result[15]_i_5_n_0 ),
.I1(\result[15]_i_6_n_0 ),
.I2(\result[16]_i_7_n_0 ),
.I3(\result[16]_i_8_n_0 ),
.I4(store_data[0]),
.I5(\state_reg_n_0_[0] ),
.O(\result[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hD1DDD1D1D1DDDDDD))
\result[15]_i_3
(.I0(data7[15]),
.I1(opcode_2[1]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[16]_i_10_n_0 ),
.I4(store_data[0]),
.I5(\result[15]_i_8_n_0 ),
.O(\result[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[15]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[15]),
.I3(opcode_2[1]),
.I4(\result_reg[15]_i_9_n_4 ),
.I5(opcode_2[0]),
.O(\result[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'h003EFF3E003E003E))
\result[15]_i_5
(.I0(literal_2[15]),
.I1(opcode_2[0]),
.I2(opcode_2[4]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(\result_reg[19]_i_12_n_4 ),
.O(\result[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[15]_i_6
(.I0(\result[15]_i_10_n_0 ),
.I1(\result[19]_i_19_n_0 ),
.I2(store_data[1]),
.I3(\result[17]_i_12_n_0 ),
.I4(store_data[2]),
.I5(\result[21]_i_11_n_0 ),
.O(\result[15]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\result[15]_i_8
(.I0(\result[17]_i_11_n_0 ),
.I1(\result[17]_i_10_n_0 ),
.I2(store_data[1]),
.I3(\result[19]_i_17_n_0 ),
.I4(store_data[2]),
.I5(\result[15]_i_15_n_0 ),
.O(\result[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'h4F4F4F4F4444444F))
\result[16]_i_1
(.I0(\result[16]_i_2_n_0 ),
.I1(load_data[16]),
.I2(\result[16]_i_3_n_0 ),
.I3(\result[16]_i_4_n_0 ),
.I4(opcode_2[0]),
.I5(\result[16]_i_5_n_0 ),
.O(\result[16]_i_1_n_0 ));
LUT6 #(
.INIT(64'h303F303F50505F5F))
\result[16]_i_10
(.I0(\result[18]_i_11_n_0 ),
.I1(\result[18]_i_10_n_0 ),
.I2(store_data[1]),
.I3(\result[16]_i_18_n_0 ),
.I4(\result[16]_i_19_n_0 ),
.I5(store_data[2]),
.O(\result[16]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\result[16]_i_12
(.I0(store_data[10]),
.I1(store_data[29]),
.I2(store_data[24]),
.I3(store_data[27]),
.I4(store_data[14]),
.I5(store_data[19]),
.O(\result[16]_i_12_n_0 ));
LUT6 #(
.INIT(64'h00000000E2FFE200))
\result[16]_i_13
(.I0(register_a[1]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[1]),
.I3(store_data[3]),
.I4(\read_input[9]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[16]_i_13_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[16]_i_14
(.I0(register_a[19]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[19]),
.I3(operand_b1),
.I4(result[19]),
.O(\result[16]_i_14_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[16]_i_15
(.I0(register_a[18]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[18]),
.I3(operand_b1),
.I4(result[18]),
.O(\result[16]_i_15_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[16]_i_16
(.I0(register_a[17]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[17]),
.I3(operand_b1),
.I4(result[17]),
.O(\result[16]_i_16_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[16]_i_17
(.I0(register_a[16]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[16]),
.I3(operand_b1),
.I4(result[16]),
.O(\result[16]_i_17_n_0 ));
LUT6 #(
.INIT(64'hFFFF1D00FFFF1DFF))
\result[16]_i_18
(.I0(register_a[28]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[28]),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[20]_i_1_n_0 ),
.O(\result[16]_i_18_n_0 ));
LUT6 #(
.INIT(64'hFFFF1D00FFFF1DFF))
\result[16]_i_19
(.I0(register_a[24]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[24]),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[16]_i_1_n_0 ),
.O(\result[16]_i_19_n_0 ));
LUT2 #(
.INIT(4'hB))
\result[16]_i_2
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.O(\result[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'h45454455FFFFFFFF))
\result[16]_i_3
(.I0(\result[16]_i_6_n_0 ),
.I1(\result[16]_i_7_n_0 ),
.I2(\result[16]_i_8_n_0 ),
.I3(\result[17]_i_8_n_0 ),
.I4(store_data[0]),
.I5(\state_reg_n_0_[0] ),
.O(\result[16]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFF55C055FF55F355))
\result[16]_i_4
(.I0(data7[16]),
.I1(store_data[0]),
.I2(\result[17]_i_7_n_0 ),
.I3(opcode_2[1]),
.I4(\result[31]_i_12_n_0 ),
.I5(\result[16]_i_10_n_0 ),
.O(\result[16]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[16]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[16]),
.I3(opcode_2[1]),
.I4(\result_reg[19]_i_11_n_7 ),
.I5(opcode_2[0]),
.O(\result[16]_i_5_n_0 ));
LUT6 #(
.INIT(64'h444400FF4444FFF0))
\result[16]_i_6
(.I0(opcode_2[2]),
.I1(\result_reg[19]_i_7_n_7 ),
.I2(literal_2[15]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.I5(opcode_2[4]),
.O(\result[16]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEFFFFFFFF))
\result[16]_i_7
(.I0(\result[31]_i_27_n_0 ),
.I1(\result[16]_i_12_n_0 ),
.I2(\result[31]_i_24_n_0 ),
.I3(\result[31]_i_23_n_0 ),
.I4(\result[31]_i_22_n_0 ),
.I5(\result[7]_i_6_n_0 ),
.O(\result[16]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[16]_i_8
(.I0(\result[16]_i_13_n_0 ),
.I1(\result[20]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[18]_i_12_n_0 ),
.I4(store_data[2]),
.I5(\result[22]_i_11_n_0 ),
.O(\result[16]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFD5D0000))
\result[17]_i_1
(.I0(\result[17]_i_2_n_0 ),
.I1(\result[17]_i_3_n_0 ),
.I2(\result[17]_i_4_n_0 ),
.I3(\result[17]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[17]_i_6_n_0 ),
.O(\result[17]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF1D00FFFF1DFF))
\result[17]_i_10
(.I0(register_a[25]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[25]),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[17]_i_1_n_0 ),
.O(\result[17]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFF1D00FFFF1DFF))
\result[17]_i_11
(.I0(register_a[29]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[29]),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[21]_i_1_n_0 ),
.O(\result[17]_i_11_n_0 ));
LUT6 #(
.INIT(64'h00000000E2FFE200))
\result[17]_i_12
(.I0(register_a[2]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[2]),
.I3(store_data[3]),
.I4(\read_input[10]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[17]_i_12_n_0 ));
LUT3 #(
.INIT(8'hDF))
\result[17]_i_2
(.I0(\result_reg[19]_i_7_n_6 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[17]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[17]_i_3
(.I0(opcode_2[4]),
.I1(\result[18]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[17]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[17]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[17]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[18]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[17]_i_8_n_0 ),
.O(\result[17]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFAAAEAA))
\result[17]_i_5
(.I0(\result[17]_i_9_n_0 ),
.I1(\result_reg[19]_i_11_n_6 ),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.I4(opcode_2[2]),
.O(\result[17]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[17]_i_6
(.I0(load_data[17]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[17]_i_6_n_0 ));
LUT6 #(
.INIT(64'hCF5FCF50C05FC050))
\result[17]_i_7
(.I0(\result[19]_i_17_n_0 ),
.I1(\result[19]_i_18_n_0 ),
.I2(store_data[1]),
.I3(store_data[2]),
.I4(\result[17]_i_10_n_0 ),
.I5(\result[17]_i_11_n_0 ),
.O(\result[17]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[17]_i_8
(.I0(\result[17]_i_12_n_0 ),
.I1(\result[21]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[19]_i_19_n_0 ),
.I4(store_data[2]),
.I5(\result[23]_i_17_n_0 ),
.O(\result[17]_i_8_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\result[17]_i_9
(.I0(literal_2[15]),
.I1(opcode_2[4]),
.I2(data7[17]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.O(\result[17]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFD5D0000))
\result[18]_i_1
(.I0(\result[18]_i_2_n_0 ),
.I1(\result[18]_i_3_n_0 ),
.I2(\result[18]_i_4_n_0 ),
.I3(\result[18]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[18]_i_6_n_0 ),
.O(\result[18]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF1D00FFFF1DFF))
\result[18]_i_10
(.I0(register_a[30]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[30]),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[22]_i_1_n_0 ),
.O(\result[18]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFF1D00FFFF1DFF))
\result[18]_i_11
(.I0(register_a[26]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[26]),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[18]_i_1_n_0 ),
.O(\result[18]_i_11_n_0 ));
LUT6 #(
.INIT(64'h00000000E2FFE200))
\result[18]_i_12
(.I0(register_a[3]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[3]),
.I3(store_data[3]),
.I4(\read_input[11]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[18]_i_12_n_0 ));
LUT3 #(
.INIT(8'hDF))
\result[18]_i_2
(.I0(\result_reg[19]_i_7_n_5 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[18]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[18]_i_3
(.I0(opcode_2[4]),
.I1(\result[19]_i_8_n_0 ),
.I2(store_data[0]),
.I3(\result[18]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[18]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[18]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[19]_i_9_n_0 ),
.I4(opcode_2[3]),
.I5(\result[18]_i_8_n_0 ),
.O(\result[18]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFAAAEAA))
\result[18]_i_5
(.I0(\result[18]_i_9_n_0 ),
.I1(\result_reg[19]_i_11_n_5 ),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.I4(opcode_2[2]),
.O(\result[18]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[18]_i_6
(.I0(load_data[18]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[18]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8B8BB88))
\result[18]_i_7
(.I0(\result[20]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[18]_i_10_n_0 ),
.I3(\result[18]_i_11_n_0 ),
.I4(store_data[2]),
.O(\result[18]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[18]_i_8
(.I0(\result[18]_i_12_n_0 ),
.I1(\result[22]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[20]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[24]_i_11_n_0 ),
.O(\result[18]_i_8_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\result[18]_i_9
(.I0(literal_2[15]),
.I1(opcode_2[4]),
.I2(data7[18]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.O(\result[18]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFD5D0000))
\result[19]_i_1
(.I0(\result[19]_i_2_n_0 ),
.I1(\result[19]_i_3_n_0 ),
.I2(\result[19]_i_4_n_0 ),
.I3(\result[19]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[19]_i_6_n_0 ),
.O(\result[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\result[19]_i_10
(.I0(literal_2[15]),
.I1(opcode_2[4]),
.I2(data7[19]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.O(\result[19]_i_10_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[19]_i_13
(.I0(result[19]),
.I1(operand_b1),
.I2(register_b[19]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[19]),
.O(\result[19]_i_13_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[19]_i_14
(.I0(result[18]),
.I1(operand_b1),
.I2(register_b[18]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[18]),
.O(\result[19]_i_14_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[19]_i_15
(.I0(result[17]),
.I1(operand_b1),
.I2(register_b[17]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[17]),
.O(\result[19]_i_15_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[19]_i_16
(.I0(result[16]),
.I1(operand_b1),
.I2(register_b[16]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[16]),
.O(\result[19]_i_16_n_0 ));
LUT6 #(
.INIT(64'h00000000E2FFE200))
\result[19]_i_17
(.I0(register_a[27]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[27]),
.I3(store_data[3]),
.I4(\read_input[19]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[19]_i_17_n_0 ));
LUT6 #(
.INIT(64'hFFFF1D00FFFF1DFF))
\result[19]_i_18
(.I0(register_a[31]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[31]),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[23]_i_1_n_0 ),
.O(\result[19]_i_18_n_0 ));
LUT6 #(
.INIT(64'h00000000E2FFE200))
\result[19]_i_19
(.I0(register_a[4]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[4]),
.I3(store_data[3]),
.I4(\read_input[12]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[19]_i_19_n_0 ));
LUT3 #(
.INIT(8'hDF))
\result[19]_i_2
(.I0(\result_reg[19]_i_7_n_4 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[19]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_20
(.I0(result[19]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[19]),
.O(\result[19]_i_20_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_21
(.I0(result[18]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[18]),
.O(\result[19]_i_21_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_22
(.I0(result[17]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[17]),
.O(\result[19]_i_22_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_23
(.I0(result[16]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[16]),
.O(\result[19]_i_23_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_24
(.I0(register_a[15]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.O(\result[19]_i_24_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_25
(.I0(register_a[14]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[14]),
.I3(operand_b1),
.I4(result[14]),
.O(\result[19]_i_25_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_26
(.I0(register_a[13]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[13]),
.I3(operand_b1),
.I4(result[13]),
.O(\result[19]_i_26_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_27
(.I0(register_a[12]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[12]),
.I3(operand_b1),
.I4(result[12]),
.O(\result[19]_i_27_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[19]_i_3
(.I0(opcode_2[4]),
.I1(\result[20]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[19]_i_8_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[19]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[19]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[20]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[19]_i_9_n_0 ),
.O(\result[19]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFAAAEAA))
\result[19]_i_5
(.I0(\result[19]_i_10_n_0 ),
.I1(\result_reg[19]_i_11_n_4 ),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.I4(opcode_2[2]),
.O(\result[19]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[19]_i_6
(.I0(load_data[19]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[19]_i_6_n_0 ));
LUT5 #(
.INIT(32'hBB8B888B))
\result[19]_i_8
(.I0(\result[21]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[19]_i_17_n_0 ),
.I3(store_data[2]),
.I4(\result[19]_i_18_n_0 ),
.O(\result[19]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[19]_i_9
(.I0(\result[19]_i_19_n_0 ),
.I1(\result[23]_i_17_n_0 ),
.I2(store_data[1]),
.I3(\result[21]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[25]_i_11_n_0 ),
.O(\result[19]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44440400))
\result[1]_i_1
(.I0(\result[1]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(\result[1]_i_3_n_0 ),
.I4(\result[1]_i_4_n_0 ),
.I5(\result[1]_i_5_n_0 ),
.O(\result[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000000FFB8FFFF))
\result[1]_i_2
(.I0(\result[1]_i_6_n_0 ),
.I1(store_data[0]),
.I2(\result[2]_i_6_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(\result[7]_i_6_n_0 ),
.I5(\result[1]_i_7_n_0 ),
.O(\result[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[1]_i_3
(.I0(\result[1]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[2]_i_8_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[1]),
.O(\result[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[1]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[1]),
.I3(opcode_2[1]),
.I4(\result_reg[3]_i_10_n_6 ),
.I5(opcode_2[0]),
.O(\result[1]_i_4_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[1]_i_5
(.I0(load_data[1]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[1]),
.I3(\state_reg_n_0_[2] ),
.O(\result[1]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFEF))
\result[1]_i_6
(.I0(store_data[1]),
.I1(store_data[4]),
.I2(\read_input[0]_i_1_n_0 ),
.I3(store_data[3]),
.I4(store_data[2]),
.O(\result[1]_i_6_n_0 ));
LUT6 #(
.INIT(64'h005E005EFF5E005E))
\result[1]_i_7
(.I0(opcode_2[4]),
.I1(address_b_2[1]),
.I2(opcode_2[0]),
.I3(opcode_2[3]),
.I4(\result_reg[3]_i_11_n_6 ),
.I5(opcode_2[2]),
.O(\result[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[1]_i_8
(.I0(\result[7]_i_14_n_0 ),
.I1(\result[3]_i_12_n_0 ),
.I2(store_data[1]),
.I3(\result[5]_i_9_n_0 ),
.I4(store_data[2]),
.I5(\result[1]_i_9_n_0 ),
.O(\result[1]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[1]_i_9
(.I0(\read_input[25]_i_1_n_0 ),
.I1(\read_input[9]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[17]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[1]_i_1_n_0 ),
.O(\result[1]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFD5D0000))
\result[20]_i_1
(.I0(\result[20]_i_2_n_0 ),
.I1(\result[20]_i_3_n_0 ),
.I2(\result[20]_i_4_n_0 ),
.I3(\result[20]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[20]_i_6_n_0 ),
.O(\result[20]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFCF44FFFFCF77))
\result[20]_i_10
(.I0(\read_input[24]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[28]_i_1_n_0 ),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[20]_i_1_n_0 ),
.O(\result[20]_i_10_n_0 ));
LUT6 #(
.INIT(64'h00000000BBB888B8))
\result[20]_i_11
(.I0(\read_input[5]_i_1_n_0 ),
.I1(store_data[3]),
.I2(register_a[13]),
.I3(\result[31]_i_21_n_0 ),
.I4(result[13]),
.I5(store_data[4]),
.O(\result[20]_i_11_n_0 ));
LUT3 #(
.INIT(8'hDF))
\result[20]_i_2
(.I0(\result_reg[23]_i_7_n_7 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[20]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[20]_i_3
(.I0(opcode_2[4]),
.I1(\result[21]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[20]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[20]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[20]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[21]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[20]_i_8_n_0 ),
.O(\result[20]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFAAAEAA))
\result[20]_i_5
(.I0(\result[20]_i_9_n_0 ),
.I1(\result_reg[23]_i_11_n_7 ),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.I4(opcode_2[2]),
.O(\result[20]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[20]_i_6
(.I0(load_data[20]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[20]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[20]_i_7
(.I0(\result[22]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[20]_i_10_n_0 ),
.O(\result[20]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[20]_i_8
(.I0(\result[20]_i_11_n_0 ),
.I1(\result[24]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[22]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[26]_i_11_n_0 ),
.O(\result[20]_i_8_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\result[20]_i_9
(.I0(literal_2[15]),
.I1(opcode_2[4]),
.I2(data7[20]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.O(\result[20]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFD5D0000))
\result[21]_i_1
(.I0(\result[21]_i_2_n_0 ),
.I1(\result[21]_i_3_n_0 ),
.I2(\result[21]_i_4_n_0 ),
.I3(\result[21]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[21]_i_6_n_0 ),
.O(\result[21]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFCF44FFFFCF77))
\result[21]_i_10
(.I0(\read_input[25]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[29]_i_1_n_0 ),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[21]_i_1_n_0 ),
.O(\result[21]_i_10_n_0 ));
LUT6 #(
.INIT(64'h00000000BBB888B8))
\result[21]_i_11
(.I0(\read_input[6]_i_1_n_0 ),
.I1(store_data[3]),
.I2(register_a[14]),
.I3(\result[31]_i_21_n_0 ),
.I4(result[14]),
.I5(store_data[4]),
.O(\result[21]_i_11_n_0 ));
LUT3 #(
.INIT(8'hDF))
\result[21]_i_2
(.I0(\result_reg[23]_i_7_n_6 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[21]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[21]_i_3
(.I0(opcode_2[4]),
.I1(\result[22]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[21]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[21]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[21]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[22]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[21]_i_8_n_0 ),
.O(\result[21]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFAAAEAA))
\result[21]_i_5
(.I0(\result[21]_i_9_n_0 ),
.I1(\result_reg[23]_i_11_n_6 ),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.I4(opcode_2[2]),
.O(\result[21]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[21]_i_6
(.I0(load_data[21]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[21]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[21]_i_7
(.I0(\result[23]_i_16_n_0 ),
.I1(store_data[1]),
.I2(\result[21]_i_10_n_0 ),
.O(\result[21]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[21]_i_8
(.I0(\result[21]_i_11_n_0 ),
.I1(\result[25]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[23]_i_17_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_17_n_0 ),
.O(\result[21]_i_8_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\result[21]_i_9
(.I0(literal_2[15]),
.I1(opcode_2[4]),
.I2(data7[21]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.O(\result[21]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFD5D0000))
\result[22]_i_1
(.I0(\result[22]_i_2_n_0 ),
.I1(\result[22]_i_3_n_0 ),
.I2(\result[22]_i_4_n_0 ),
.I3(\result[22]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[22]_i_6_n_0 ),
.O(\result[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFCF44FFFFCF77))
\result[22]_i_10
(.I0(\read_input[26]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[30]_i_1_n_0 ),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[22]_i_1_n_0 ),
.O(\result[22]_i_10_n_0 ));
LUT6 #(
.INIT(64'h00000000BBB888B8))
\result[22]_i_11
(.I0(\read_input[7]_i_1_n_0 ),
.I1(store_data[3]),
.I2(register_a[15]),
.I3(\result[31]_i_21_n_0 ),
.I4(result[15]),
.I5(store_data[4]),
.O(\result[22]_i_11_n_0 ));
LUT3 #(
.INIT(8'hDF))
\result[22]_i_2
(.I0(\result_reg[23]_i_7_n_5 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[22]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[22]_i_3
(.I0(opcode_2[4]),
.I1(\result[23]_i_8_n_0 ),
.I2(store_data[0]),
.I3(\result[22]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[22]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[22]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[23]_i_9_n_0 ),
.I4(opcode_2[3]),
.I5(\result[22]_i_8_n_0 ),
.O(\result[22]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFAAAEAA))
\result[22]_i_5
(.I0(\result[22]_i_9_n_0 ),
.I1(\result_reg[23]_i_11_n_5 ),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.I4(opcode_2[2]),
.O(\result[22]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[22]_i_6
(.I0(load_data[22]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[22]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[22]_i_7
(.I0(\result[24]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[22]_i_10_n_0 ),
.O(\result[22]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[22]_i_8
(.I0(\result[22]_i_11_n_0 ),
.I1(\result[26]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[24]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[28]_i_10_n_0 ),
.O(\result[22]_i_8_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\result[22]_i_9
(.I0(literal_2[15]),
.I1(opcode_2[4]),
.I2(data7[22]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.O(\result[22]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFD5D0000))
\result[23]_i_1
(.I0(\result[23]_i_2_n_0 ),
.I1(\result[23]_i_3_n_0 ),
.I2(\result[23]_i_4_n_0 ),
.I3(\result[23]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[23]_i_6_n_0 ),
.O(\result[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\result[23]_i_10
(.I0(literal_2[15]),
.I1(opcode_2[4]),
.I2(data7[23]),
.I3(opcode_2[0]),
.I4(opcode_2[3]),
.O(\result[23]_i_10_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[23]_i_12
(.I0(result[23]),
.I1(operand_b1),
.I2(register_b[23]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[23]),
.O(\result[23]_i_12_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[23]_i_13
(.I0(result[22]),
.I1(operand_b1),
.I2(register_b[22]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[22]),
.O(\result[23]_i_13_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[23]_i_14
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[21]),
.O(\result[23]_i_14_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[23]_i_15
(.I0(result[20]),
.I1(operand_b1),
.I2(register_b[20]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[20]),
.O(\result[23]_i_15_n_0 ));
LUT6 #(
.INIT(64'hFFFFCF44FFFFCF77))
\result[23]_i_16
(.I0(\read_input[27]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[31]_i_2_n_0 ),
.I3(store_data[3]),
.I4(store_data[4]),
.I5(\read_input[23]_i_1_n_0 ),
.O(\result[23]_i_16_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[23]_i_17
(.I0(\read_input[8]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[0]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[16]_i_1_n_0 ),
.O(\result[23]_i_17_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_18
(.I0(result[23]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[23]),
.O(\result[23]_i_18_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_19
(.I0(result[22]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[22]),
.O(\result[23]_i_19_n_0 ));
LUT3 #(
.INIT(8'hDF))
\result[23]_i_2
(.I0(\result_reg[23]_i_7_n_4 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[23]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_20
(.I0(result[21]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[21]),
.O(\result[23]_i_20_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_21
(.I0(result[20]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[20]),
.O(\result[23]_i_21_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[23]_i_3
(.I0(opcode_2[4]),
.I1(\result[24]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[23]_i_8_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[23]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[24]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[23]_i_9_n_0 ),
.O(\result[23]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFAAAEAA))
\result[23]_i_5
(.I0(\result[23]_i_10_n_0 ),
.I1(\result_reg[23]_i_11_n_4 ),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.I4(opcode_2[2]),
.O(\result[23]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[23]_i_6
(.I0(load_data[23]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[23]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[23]_i_8
(.I0(\result[25]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[23]_i_16_n_0 ),
.O(\result[23]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[23]_i_9
(.I0(\result[23]_i_17_n_0 ),
.I1(\result[27]_i_17_n_0 ),
.I2(store_data[1]),
.I3(\result[25]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[29]_i_10_n_0 ),
.O(\result[23]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAE02A2))
\result[24]_i_1
(.I0(\result[24]_i_2_n_0 ),
.I1(\result[24]_i_3_n_0 ),
.I2(\result[24]_i_4_n_0 ),
.I3(\result[24]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[24]_i_6_n_0 ),
.O(\result[24]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFF4F7))
\result[24]_i_10
(.I0(\read_input[28]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[3]),
.I3(\read_input[24]_i_1_n_0 ),
.I4(store_data[4]),
.O(\result[24]_i_10_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[24]_i_11
(.I0(\read_input[9]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[1]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[17]_i_1_n_0 ),
.O(\result[24]_i_11_n_0 ));
LUT4 #(
.INIT(16'h0080))
\result[24]_i_2
(.I0(\result_reg[27]_i_7_n_7 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[24]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[24]_i_3
(.I0(opcode_2[4]),
.I1(\result[25]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[24]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[24]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[24]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[25]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[24]_i_8_n_0 ),
.O(\result[24]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF10111000))
\result[24]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.I2(data7[24]),
.I3(opcode_2[4]),
.I4(literal_2[15]),
.I5(\result[24]_i_9_n_0 ),
.O(\result[24]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[24]_i_6
(.I0(load_data[24]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[24]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[24]_i_7
(.I0(\result[26]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[24]_i_10_n_0 ),
.O(\result[24]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[24]_i_8
(.I0(\result[24]_i_11_n_0 ),
.I1(\result[28]_i_10_n_0 ),
.I2(store_data[1]),
.I3(\result[26]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[30]_i_10_n_0 ),
.O(\result[24]_i_8_n_0 ));
LUT4 #(
.INIT(16'hF400))
\result[24]_i_9
(.I0(opcode_2[4]),
.I1(\result_reg[27]_i_23_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[0]),
.O(\result[24]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAE02A2))
\result[25]_i_1
(.I0(\result[25]_i_2_n_0 ),
.I1(\result[25]_i_3_n_0 ),
.I2(\result[25]_i_4_n_0 ),
.I3(\result[25]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[25]_i_6_n_0 ),
.O(\result[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFF4F7))
\result[25]_i_10
(.I0(\read_input[29]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[3]),
.I3(\read_input[25]_i_1_n_0 ),
.I4(store_data[4]),
.O(\result[25]_i_10_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[25]_i_11
(.I0(\read_input[10]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[2]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[18]_i_1_n_0 ),
.O(\result[25]_i_11_n_0 ));
LUT4 #(
.INIT(16'h0080))
\result[25]_i_2
(.I0(\result_reg[27]_i_7_n_6 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[25]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[25]_i_3
(.I0(opcode_2[4]),
.I1(\result[26]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[25]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[25]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[25]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[26]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[25]_i_8_n_0 ),
.O(\result[25]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF10111000))
\result[25]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.I2(data7[25]),
.I3(opcode_2[4]),
.I4(literal_2[15]),
.I5(\result[25]_i_9_n_0 ),
.O(\result[25]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[25]_i_6
(.I0(load_data[25]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[25]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[25]_i_7
(.I0(\result[27]_i_16_n_0 ),
.I1(store_data[1]),
.I2(\result[25]_i_10_n_0 ),
.O(\result[25]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[25]_i_8
(.I0(\result[25]_i_11_n_0 ),
.I1(\result[29]_i_10_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_17_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_32_n_0 ),
.O(\result[25]_i_8_n_0 ));
LUT4 #(
.INIT(16'hF400))
\result[25]_i_9
(.I0(opcode_2[4]),
.I1(\result_reg[27]_i_23_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[0]),
.O(\result[25]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAE02A2))
\result[26]_i_1
(.I0(\result[26]_i_2_n_0 ),
.I1(\result[26]_i_3_n_0 ),
.I2(\result[26]_i_4_n_0 ),
.I3(\result[26]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[26]_i_6_n_0 ),
.O(\result[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFF4F7))
\result[26]_i_10
(.I0(\read_input[30]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[3]),
.I3(\read_input[26]_i_1_n_0 ),
.I4(store_data[4]),
.O(\result[26]_i_10_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[26]_i_11
(.I0(\read_input[11]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[3]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[19]_i_1_n_0 ),
.O(\result[26]_i_11_n_0 ));
LUT4 #(
.INIT(16'h0080))
\result[26]_i_2
(.I0(\result_reg[27]_i_7_n_5 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[26]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[26]_i_3
(.I0(opcode_2[4]),
.I1(\result[27]_i_8_n_0 ),
.I2(store_data[0]),
.I3(\result[26]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[26]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[26]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[27]_i_9_n_0 ),
.I4(opcode_2[3]),
.I5(\result[26]_i_8_n_0 ),
.O(\result[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF10111000))
\result[26]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.I2(data7[26]),
.I3(opcode_2[4]),
.I4(literal_2[15]),
.I5(\result[26]_i_9_n_0 ),
.O(\result[26]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[26]_i_6
(.I0(load_data[26]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[26]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFFFFEF0000))
\result[26]_i_7
(.I0(store_data[2]),
.I1(store_data[4]),
.I2(\read_input[28]_i_1_n_0 ),
.I3(store_data[3]),
.I4(store_data[1]),
.I5(\result[26]_i_10_n_0 ),
.O(\result[26]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[26]_i_8
(.I0(\result[26]_i_11_n_0 ),
.I1(\result[30]_i_10_n_0 ),
.I2(store_data[1]),
.I3(\result[28]_i_10_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_28_n_0 ),
.O(\result[26]_i_8_n_0 ));
LUT4 #(
.INIT(16'hF400))
\result[26]_i_9
(.I0(opcode_2[4]),
.I1(\result_reg[27]_i_23_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[0]),
.O(\result[26]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAE02A2))
\result[27]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(\result[27]_i_3_n_0 ),
.I2(\result[27]_i_4_n_0 ),
.I3(\result[27]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[27]_i_6_n_0 ),
.O(\result[27]_i_1_n_0 ));
LUT4 #(
.INIT(16'hF400))
\result[27]_i_11
(.I0(opcode_2[4]),
.I1(\result_reg[27]_i_23_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[0]),
.O(\result[27]_i_11_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[27]_i_12
(.I0(result[27]),
.I1(operand_b1),
.I2(register_b[27]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[27]),
.O(\result[27]_i_12_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[27]_i_13
(.I0(result[26]),
.I1(operand_b1),
.I2(register_b[26]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[26]),
.O(\result[27]_i_13_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[27]_i_14
(.I0(result[25]),
.I1(operand_b1),
.I2(register_b[25]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[25]),
.O(\result[27]_i_14_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[27]_i_15
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[24]),
.O(\result[27]_i_15_n_0 ));
LUT5 #(
.INIT(32'hFFF4FFF7))
\result[27]_i_16
(.I0(\read_input[31]_i_2_n_0 ),
.I1(store_data[2]),
.I2(store_data[3]),
.I3(store_data[4]),
.I4(\read_input[27]_i_1_n_0 ),
.O(\result[27]_i_16_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[27]_i_17
(.I0(\read_input[12]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[4]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[20]_i_1_n_0 ),
.O(\result[27]_i_17_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[27]_i_19
(.I0(register_a[27]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[27]),
.I3(operand_b1),
.I4(result[27]),
.O(\result[27]_i_19_n_0 ));
LUT4 #(
.INIT(16'h0080))
\result[27]_i_2
(.I0(\result_reg[27]_i_7_n_4 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[27]_i_2_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[27]_i_20
(.I0(register_a[26]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[26]),
.I3(operand_b1),
.I4(result[26]),
.O(\result[27]_i_20_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[27]_i_21
(.I0(register_a[25]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[25]),
.I3(operand_b1),
.I4(result[25]),
.O(\result[27]_i_21_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[27]_i_22
(.I0(register_a[24]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[24]),
.I3(operand_b1),
.I4(result[24]),
.O(\result[27]_i_22_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[27]_i_24
(.I0(register_a[23]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[23]),
.I3(operand_b1),
.I4(result[23]),
.O(\result[27]_i_24_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[27]_i_25
(.I0(register_a[22]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[22]),
.I3(operand_b1),
.I4(result[22]),
.O(\result[27]_i_25_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[27]_i_26
(.I0(register_a[21]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[21]),
.I3(operand_b1),
.I4(result[21]),
.O(\result[27]_i_26_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[27]_i_27
(.I0(register_a[20]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[20]),
.I3(operand_b1),
.I4(result[20]),
.O(\result[27]_i_27_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_28
(.I0(result[27]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[27]),
.O(\result[27]_i_28_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_29
(.I0(result[26]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[26]),
.O(\result[27]_i_29_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[27]_i_3
(.I0(opcode_2[4]),
.I1(\result[28]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[27]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_30
(.I0(result[25]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[25]),
.O(\result[27]_i_30_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[27]_i_31
(.I0(result[24]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[24]),
.O(\result[27]_i_31_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[27]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[28]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[27]_i_9_n_0 ),
.O(\result[27]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF10111000))
\result[27]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.I2(data7[27]),
.I3(opcode_2[4]),
.I4(literal_2[15]),
.I5(\result[27]_i_11_n_0 ),
.O(\result[27]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[27]_i_6
(.I0(load_data[27]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[27]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFFFFEF0000))
\result[27]_i_8
(.I0(store_data[2]),
.I1(store_data[4]),
.I2(\read_input[29]_i_1_n_0 ),
.I3(store_data[3]),
.I4(store_data[1]),
.I5(\result[27]_i_16_n_0 ),
.O(\result[27]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[27]_i_9
(.I0(\result[27]_i_17_n_0 ),
.I1(\result[31]_i_32_n_0 ),
.I2(store_data[1]),
.I3(\result[29]_i_10_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_34_n_0 ),
.O(\result[27]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAE02A2))
\result[28]_i_1
(.I0(\result[28]_i_2_n_0 ),
.I1(\result[28]_i_3_n_0 ),
.I2(\result[28]_i_4_n_0 ),
.I3(\result[28]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[28]_i_6_n_0 ),
.O(\result[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[28]_i_10
(.I0(\read_input[13]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[5]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[21]_i_1_n_0 ),
.O(\result[28]_i_10_n_0 ));
LUT4 #(
.INIT(16'h0080))
\result[28]_i_2
(.I0(\result_reg[31]_i_10_n_7 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[28]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000202A))
\result[28]_i_3
(.I0(opcode_2[4]),
.I1(\result[29]_i_7_n_0 ),
.I2(store_data[0]),
.I3(\result[28]_i_7_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.O(\result[28]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[28]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[29]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[28]_i_8_n_0 ),
.O(\result[28]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF10111000))
\result[28]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.I2(data7[28]),
.I3(opcode_2[4]),
.I4(literal_2[15]),
.I5(\result[28]_i_9_n_0 ),
.O(\result[28]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[28]_i_6
(.I0(load_data[28]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[28]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF4FFF7))
\result[28]_i_7
(.I0(\read_input[30]_i_1_n_0 ),
.I1(store_data[1]),
.I2(store_data[2]),
.I3(store_data[4]),
.I4(\read_input[28]_i_1_n_0 ),
.I5(store_data[3]),
.O(\result[28]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[28]_i_8
(.I0(\result[28]_i_10_n_0 ),
.I1(\result[31]_i_28_n_0 ),
.I2(store_data[1]),
.I3(\result[30]_i_10_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_30_n_0 ),
.O(\result[28]_i_8_n_0 ));
LUT4 #(
.INIT(16'hF400))
\result[28]_i_9
(.I0(opcode_2[4]),
.I1(\result_reg[31]_i_40_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[0]),
.O(\result[28]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAE02A2))
\result[29]_i_1
(.I0(\result[29]_i_2_n_0 ),
.I1(\result[29]_i_3_n_0 ),
.I2(\result[29]_i_4_n_0 ),
.I3(\result[29]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[29]_i_6_n_0 ),
.O(\result[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[29]_i_10
(.I0(\read_input[14]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[6]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[22]_i_1_n_0 ),
.O(\result[29]_i_10_n_0 ));
LUT4 #(
.INIT(16'h0080))
\result[29]_i_2
(.I0(\result_reg[31]_i_10_n_6 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000020002AA))
\result[29]_i_3
(.I0(opcode_2[4]),
.I1(store_data[1]),
.I2(\result[30]_i_7_n_0 ),
.I3(store_data[0]),
.I4(\result[29]_i_7_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[29]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[29]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[30]_i_8_n_0 ),
.I4(opcode_2[3]),
.I5(\result[29]_i_8_n_0 ),
.O(\result[29]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF10111000))
\result[29]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.I2(data7[29]),
.I3(opcode_2[4]),
.I4(literal_2[15]),
.I5(\result[29]_i_9_n_0 ),
.O(\result[29]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[29]_i_6
(.I0(load_data[29]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[29]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF4FFF7))
\result[29]_i_7
(.I0(\read_input[31]_i_2_n_0 ),
.I1(store_data[1]),
.I2(store_data[2]),
.I3(store_data[4]),
.I4(\read_input[29]_i_1_n_0 ),
.I5(store_data[3]),
.O(\result[29]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[29]_i_8
(.I0(\result[29]_i_10_n_0 ),
.I1(\result[31]_i_34_n_0 ),
.I2(store_data[1]),
.I3(\result[31]_i_32_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_33_n_0 ),
.O(\result[29]_i_8_n_0 ));
LUT4 #(
.INIT(16'hF400))
\result[29]_i_9
(.I0(opcode_2[4]),
.I1(\result_reg[31]_i_40_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[0]),
.O(\result[29]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44440400))
\result[2]_i_1
(.I0(\result[2]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(\result[2]_i_3_n_0 ),
.I4(\result[2]_i_4_n_0 ),
.I5(\result[2]_i_5_n_0 ),
.O(\result[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000000FFB8FFFF))
\result[2]_i_2
(.I0(\result[2]_i_6_n_0 ),
.I1(store_data[0]),
.I2(\result[3]_i_6_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(\result[7]_i_6_n_0 ),
.I5(\result[2]_i_7_n_0 ),
.O(\result[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[2]_i_3
(.I0(\result[2]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[3]_i_8_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[2]),
.O(\result[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[2]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[2]),
.I3(opcode_2[1]),
.I4(\result_reg[3]_i_10_n_5 ),
.I5(opcode_2[0]),
.O(\result[2]_i_4_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[2]_i_5
(.I0(load_data[2]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[2]),
.I3(\state_reg_n_0_[2] ),
.O(\result[2]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFEF))
\result[2]_i_6
(.I0(store_data[1]),
.I1(store_data[4]),
.I2(\read_input[1]_i_1_n_0 ),
.I3(store_data[3]),
.I4(store_data[2]),
.O(\result[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'h005E005EFF5E005E))
\result[2]_i_7
(.I0(opcode_2[4]),
.I1(address_b_2[2]),
.I2(opcode_2[0]),
.I3(opcode_2[3]),
.I4(\result_reg[3]_i_11_n_5 ),
.I5(opcode_2[2]),
.O(\result[2]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[2]_i_8
(.I0(\result[8]_i_12_n_0 ),
.I1(\result[4]_i_10_n_0 ),
.I2(store_data[1]),
.I3(\result[6]_i_9_n_0 ),
.I4(store_data[2]),
.I5(\result[2]_i_9_n_0 ),
.O(\result[2]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[2]_i_9
(.I0(\read_input[26]_i_1_n_0 ),
.I1(\read_input[10]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[18]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[2]_i_1_n_0 ),
.O(\result[2]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAE02A2))
\result[30]_i_1
(.I0(\result[30]_i_2_n_0 ),
.I1(\result[30]_i_3_n_0 ),
.I2(\result[30]_i_4_n_0 ),
.I3(\result[30]_i_5_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[30]_i_6_n_0 ),
.O(\result[30]_i_1_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[30]_i_10
(.I0(\read_input[15]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[7]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[23]_i_1_n_0 ),
.O(\result[30]_i_10_n_0 ));
LUT4 #(
.INIT(16'h0080))
\result[30]_i_2
(.I0(\result_reg[31]_i_10_n_5 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000000020002A))
\result[30]_i_3
(.I0(opcode_2[4]),
.I1(\result[31]_i_11_n_0 ),
.I2(store_data[0]),
.I3(store_data[1]),
.I4(\result[30]_i_7_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[30]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0504555501005555))
\result[30]_i_4
(.I0(opcode_2[1]),
.I1(store_data[0]),
.I2(\result[31]_i_12_n_0 ),
.I3(\result[31]_i_14_n_0 ),
.I4(opcode_2[3]),
.I5(\result[30]_i_8_n_0 ),
.O(\result[30]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF10111000))
\result[30]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.I2(data7[30]),
.I3(opcode_2[4]),
.I4(literal_2[15]),
.I5(\result[30]_i_9_n_0 ),
.O(\result[30]_i_5_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[30]_i_6
(.I0(load_data[30]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[30]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFEEEFFFEF))
\result[30]_i_7
(.I0(store_data[2]),
.I1(store_data[4]),
.I2(register_a[30]),
.I3(\result[31]_i_21_n_0 ),
.I4(result[30]),
.I5(store_data[3]),
.O(\result[30]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[30]_i_8
(.I0(\result[30]_i_10_n_0 ),
.I1(\result[31]_i_30_n_0 ),
.I2(store_data[1]),
.I3(\result[31]_i_28_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_29_n_0 ),
.O(\result[30]_i_8_n_0 ));
LUT4 #(
.INIT(16'hF400))
\result[30]_i_9
(.I0(opcode_2[4]),
.I1(\result_reg[31]_i_40_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[0]),
.O(\result[30]_i_9_n_0 ));
LUT5 #(
.INIT(32'h0300A0A0))
\result[31]_i_1
(.I0(\result[31]_i_3_n_0 ),
.I1(\result[31]_i_4_n_0 ),
.I2(\state_reg_n_0_[2] ),
.I3(\state_reg_n_0_[1] ),
.I4(\state_reg_n_0_[0] ),
.O(\result[31]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFEEEFFFEF))
\result[31]_i_11
(.I0(store_data[2]),
.I1(store_data[4]),
.I2(register_a[31]),
.I3(\result[31]_i_21_n_0 ),
.I4(result[31]),
.I5(store_data[3]),
.O(\result[31]_i_11_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\result[31]_i_12
(.I0(\result[31]_i_22_n_0 ),
.I1(\result[31]_i_23_n_0 ),
.I2(\result[31]_i_24_n_0 ),
.I3(\result[31]_i_25_n_0 ),
.I4(\result[31]_i_26_n_0 ),
.I5(\result[31]_i_27_n_0 ),
.O(\result[31]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_13
(.I0(\result[31]_i_28_n_0 ),
.I1(\result[31]_i_29_n_0 ),
.I2(store_data[1]),
.I3(\result[31]_i_30_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_31_n_0 ),
.O(\result[31]_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_14
(.I0(\result[31]_i_32_n_0 ),
.I1(\result[31]_i_33_n_0 ),
.I2(store_data[1]),
.I3(\result[31]_i_34_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_35_n_0 ),
.O(\result[31]_i_14_n_0 ));
LUT4 #(
.INIT(16'hF400))
\result[31]_i_16
(.I0(opcode_2[4]),
.I1(\result_reg[31]_i_40_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[0]),
.O(\result[31]_i_16_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[31]_i_17
(.I0(result[31]),
.I1(operand_b1),
.I2(register_b[31]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[31]),
.O(\result[31]_i_17_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[31]_i_18
(.I0(result[30]),
.I1(operand_b1),
.I2(register_b[30]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[30]),
.O(\result[31]_i_18_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[31]_i_19
(.I0(result[29]),
.I1(operand_b1),
.I2(register_b[29]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[29]),
.O(\result[31]_i_19_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAE02A2))
\result[31]_i_2
(.I0(\result[31]_i_5_n_0 ),
.I1(\result[31]_i_6_n_0 ),
.I2(\result[31]_i_7_n_0 ),
.I3(\result[31]_i_8_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[31]_i_9_n_0 ),
.O(\result[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[31]_i_20
(.I0(result[28]),
.I1(operand_b1),
.I2(register_b[28]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[28]),
.O(\result[31]_i_20_n_0 ));
LUT6 #(
.INIT(64'h2002000000002002))
\result[31]_i_21
(.I0(write_enable_reg_n_0),
.I1(\read_input[31]_i_4_n_0 ),
.I2(address_a_2[0]),
.I3(address_z_3[0]),
.I4(address_a_2[3]),
.I5(address_z_3[3]),
.O(\result[31]_i_21_n_0 ));
LUT6 #(
.INIT(64'hFFFCFFFFFFFCFAFA))
\result[31]_i_22
(.I0(register_b[9]),
.I1(result[9]),
.I2(store_data[15]),
.I3(result[17]),
.I4(operand_b1),
.I5(register_b[17]),
.O(\result[31]_i_22_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\result[31]_i_23
(.I0(store_data[11]),
.I1(store_data[30]),
.I2(store_data[18]),
.I3(store_data[20]),
.I4(store_data[12]),
.I5(store_data[13]),
.O(\result[31]_i_23_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\result[31]_i_24
(.I0(store_data[16]),
.I1(store_data[21]),
.I2(store_data[6]),
.I3(store_data[7]),
.I4(store_data[22]),
.I5(store_data[5]),
.O(\result[31]_i_24_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFEA))
\result[31]_i_25
(.I0(store_data[19]),
.I1(result[14]),
.I2(operand_b1),
.I3(register_b[14]),
.I4(store_data[27]),
.I5(store_data[24]),
.O(\result[31]_i_25_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\result[31]_i_26
(.I0(register_b[29]),
.I1(result[29]),
.I2(register_b[10]),
.I3(operand_b1),
.I4(result[10]),
.O(\result[31]_i_26_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\result[31]_i_27
(.I0(store_data[25]),
.I1(store_data[23]),
.I2(store_data[31]),
.I3(store_data[8]),
.I4(store_data[26]),
.I5(store_data[28]),
.O(\result[31]_i_27_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_28
(.I0(\read_input[1]_i_1_n_0 ),
.I1(\read_input[17]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[9]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[25]_i_1_n_0 ),
.O(\result[31]_i_28_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_29
(.I0(\read_input[5]_i_1_n_0 ),
.I1(\read_input[21]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[13]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[29]_i_1_n_0 ),
.O(\result[31]_i_29_n_0 ));
LUT4 #(
.INIT(16'h55D5))
\result[31]_i_3
(.I0(\state_reg_n_0_[1] ),
.I1(OUT1_ACK),
.I2(OUT1_STB),
.I3(\s_input_rs232_rx_ack[0]_i_2_n_0 ),
.O(\result[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_30
(.I0(\read_input[3]_i_1_n_0 ),
.I1(\read_input[19]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[11]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[27]_i_1_n_0 ),
.O(\result[31]_i_30_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_31
(.I0(\read_input[7]_i_1_n_0 ),
.I1(\read_input[23]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[15]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[31]_i_2_n_0 ),
.O(\result[31]_i_31_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_32
(.I0(\read_input[0]_i_1_n_0 ),
.I1(\read_input[16]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[8]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[24]_i_1_n_0 ),
.O(\result[31]_i_32_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_33
(.I0(\read_input[4]_i_1_n_0 ),
.I1(\read_input[20]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[12]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[28]_i_1_n_0 ),
.O(\result[31]_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_34
(.I0(\read_input[2]_i_1_n_0 ),
.I1(\read_input[18]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[10]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[26]_i_1_n_0 ),
.O(\result[31]_i_34_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_35
(.I0(\read_input[6]_i_1_n_0 ),
.I1(\read_input[22]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[14]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[30]_i_1_n_0 ),
.O(\result[31]_i_35_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[31]_i_36
(.I0(register_a[31]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[31]),
.I3(operand_b1),
.I4(result[31]),
.O(\result[31]_i_36_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[31]_i_37
(.I0(register_a[30]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[30]),
.I3(operand_b1),
.I4(result[30]),
.O(\result[31]_i_37_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[31]_i_38
(.I0(register_a[29]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[29]),
.I3(operand_b1),
.I4(result[29]),
.O(\result[31]_i_38_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[31]_i_39
(.I0(register_a[28]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[28]),
.I3(operand_b1),
.I4(result[28]),
.O(\result[31]_i_39_n_0 ));
LUT5 #(
.INIT(32'hFEE7EE64))
\result[31]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[2]),
.I2(opcode_2[0]),
.I3(opcode_2[4]),
.I4(opcode_2[1]),
.O(\result[31]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_41
(.I0(result[31]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[31]),
.O(\result[31]_i_41_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_42
(.I0(result[30]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[30]),
.O(\result[31]_i_42_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_43
(.I0(result[29]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[29]),
.O(\result[31]_i_43_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_44
(.I0(result[28]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[28]),
.O(\result[31]_i_44_n_0 ));
LUT4 #(
.INIT(16'h0080))
\result[31]_i_5
(.I0(\result_reg[31]_i_10_n_4 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[31]_i_5_n_0 ));
LUT5 #(
.INIT(32'h00000002))
\result[31]_i_6
(.I0(opcode_2[4]),
.I1(store_data[0]),
.I2(\result[31]_i_11_n_0 ),
.I3(store_data[1]),
.I4(\result[31]_i_12_n_0 ),
.O(\result[31]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000540455555555))
\result[31]_i_7
(.I0(opcode_2[1]),
.I1(\result[31]_i_13_n_0 ),
.I2(store_data[0]),
.I3(\result[31]_i_14_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.I5(opcode_2[3]),
.O(\result[31]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF10111000))
\result[31]_i_8
(.I0(opcode_2[3]),
.I1(opcode_2[0]),
.I2(data7[31]),
.I3(opcode_2[4]),
.I4(literal_2[15]),
.I5(\result[31]_i_16_n_0 ),
.O(\result[31]_i_8_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[31]_i_9
(.I0(load_data[31]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[31]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44440400))
\result[3]_i_1
(.I0(\result[3]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(\result[3]_i_3_n_0 ),
.I4(\result[3]_i_4_n_0 ),
.I5(\result[3]_i_5_n_0 ),
.O(\result[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[3]_i_12
(.I0(\read_input[27]_i_1_n_0 ),
.I1(\read_input[11]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[19]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[3]_i_1_n_0 ),
.O(\result[3]_i_12_n_0 ));
LUT4 #(
.INIT(16'h9A95))
\result[3]_i_13
(.I0(store_data[3]),
.I1(result[3]),
.I2(\result[31]_i_21_n_0 ),
.I3(register_a[3]),
.O(\result[3]_i_13_n_0 ));
LUT4 #(
.INIT(16'h9A95))
\result[3]_i_14
(.I0(store_data[2]),
.I1(result[2]),
.I2(\result[31]_i_21_n_0 ),
.I3(register_a[2]),
.O(\result[3]_i_14_n_0 ));
LUT4 #(
.INIT(16'h9A95))
\result[3]_i_15
(.I0(store_data[1]),
.I1(result[1]),
.I2(\result[31]_i_21_n_0 ),
.I3(register_a[1]),
.O(\result[3]_i_15_n_0 ));
LUT4 #(
.INIT(16'h9A95))
\result[3]_i_16
(.I0(store_data[0]),
.I1(result[0]),
.I2(\result[31]_i_21_n_0 ),
.I3(register_a[0]),
.O(\result[3]_i_16_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_17
(.I0(register_a[3]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[3]),
.I3(address_b_2[3]),
.O(\result[3]_i_17_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_18
(.I0(register_a[2]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[2]),
.I3(address_b_2[2]),
.O(\result[3]_i_18_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_19
(.I0(register_a[1]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[1]),
.I3(address_b_2[1]),
.O(\result[3]_i_19_n_0 ));
LUT6 #(
.INIT(64'h00000000FFB8FFFF))
\result[3]_i_2
(.I0(\result[3]_i_6_n_0 ),
.I1(store_data[0]),
.I2(\result[4]_i_6_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(\result[7]_i_6_n_0 ),
.I5(\result[3]_i_7_n_0 ),
.O(\result[3]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_20
(.I0(register_a[0]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[0]),
.I3(address_b_2[0]),
.O(\result[3]_i_20_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_21
(.I0(register_a[3]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[3]),
.I3(store_data[3]),
.O(\result[3]_i_21_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_22
(.I0(register_a[2]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[2]),
.I3(store_data[2]),
.O(\result[3]_i_22_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_23
(.I0(register_a[1]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[1]),
.I3(store_data[1]),
.O(\result[3]_i_23_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[3]_i_24
(.I0(register_a[0]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[0]),
.I3(store_data[0]),
.O(\result[3]_i_24_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[3]_i_3
(.I0(\result[3]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[4]_i_8_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[3]),
.O(\result[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[3]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[3]),
.I3(opcode_2[1]),
.I4(\result_reg[3]_i_10_n_4 ),
.I5(opcode_2[0]),
.O(\result[3]_i_4_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[3]_i_5
(.I0(load_data[3]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[3]),
.I3(\state_reg_n_0_[2] ),
.O(\result[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFF4F7))
\result[3]_i_6
(.I0(\read_input[0]_i_1_n_0 ),
.I1(store_data[1]),
.I2(store_data[3]),
.I3(\read_input[2]_i_1_n_0 ),
.I4(store_data[4]),
.I5(store_data[2]),
.O(\result[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h005E005EFF5E005E))
\result[3]_i_7
(.I0(opcode_2[4]),
.I1(address_b_2[3]),
.I2(opcode_2[0]),
.I3(opcode_2[3]),
.I4(\result_reg[3]_i_11_n_4 ),
.I5(opcode_2[2]),
.O(\result[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[3]_i_8
(.I0(\result[9]_i_11_n_0 ),
.I1(\result[5]_i_9_n_0 ),
.I2(store_data[1]),
.I3(\result[7]_i_14_n_0 ),
.I4(store_data[2]),
.I5(\result[3]_i_12_n_0 ),
.O(\result[3]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44440400))
\result[4]_i_1
(.I0(\result[4]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(\result[4]_i_3_n_0 ),
.I4(\result[4]_i_4_n_0 ),
.I5(\result[4]_i_5_n_0 ),
.O(\result[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[4]_i_10
(.I0(\read_input[28]_i_1_n_0 ),
.I1(\read_input[12]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[20]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[4]_i_1_n_0 ),
.O(\result[4]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFBFFF1F00000000))
\result[4]_i_2
(.I0(store_data[0]),
.I1(\result[5]_i_6_n_0 ),
.I2(\result[7]_i_6_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(\result[4]_i_6_n_0 ),
.I5(\result[4]_i_7_n_0 ),
.O(\result[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[4]_i_3
(.I0(\result[4]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[5]_i_8_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[4]),
.O(\result[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[4]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[4]),
.I3(opcode_2[1]),
.I4(\result_reg[7]_i_11_n_7 ),
.I5(opcode_2[0]),
.O(\result[4]_i_4_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[4]_i_5
(.I0(load_data[4]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[4]),
.I3(\state_reg_n_0_[2] ),
.O(\result[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFF4F7))
\result[4]_i_6
(.I0(\read_input[1]_i_1_n_0 ),
.I1(store_data[1]),
.I2(store_data[3]),
.I3(\read_input[3]_i_1_n_0 ),
.I4(store_data[4]),
.I5(store_data[2]),
.O(\result[4]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFF890089FF89FF89))
\result[4]_i_7
(.I0(opcode_2[0]),
.I1(opcode_2[4]),
.I2(literal_2[4]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(\result_reg[7]_i_13_n_7 ),
.O(\result[4]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[4]_i_8
(.I0(\result[10]_i_11_n_0 ),
.I1(\result[6]_i_9_n_0 ),
.I2(store_data[1]),
.I3(\result[8]_i_12_n_0 ),
.I4(store_data[2]),
.I5(\result[4]_i_10_n_0 ),
.O(\result[4]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44440400))
\result[5]_i_1
(.I0(\result[5]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(\result[5]_i_3_n_0 ),
.I4(\result[5]_i_4_n_0 ),
.I5(\result[5]_i_5_n_0 ),
.O(\result[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1FFFBF00000000))
\result[5]_i_2
(.I0(store_data[0]),
.I1(\result[6]_i_6_n_0 ),
.I2(\result[7]_i_6_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(\result[5]_i_6_n_0 ),
.I5(\result[5]_i_7_n_0 ),
.O(\result[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[5]_i_3
(.I0(\result[5]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[6]_i_8_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[5]),
.O(\result[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[5]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[5]),
.I3(opcode_2[1]),
.I4(\result_reg[7]_i_11_n_6 ),
.I5(opcode_2[0]),
.O(\result[5]_i_4_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[5]_i_5
(.I0(load_data[5]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[5]),
.I3(\state_reg_n_0_[2] ),
.O(\result[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0004FFFF00040000))
\result[5]_i_6
(.I0(store_data[3]),
.I1(\read_input[2]_i_1_n_0 ),
.I2(store_data[4]),
.I3(store_data[2]),
.I4(store_data[1]),
.I5(\result[7]_i_12_n_0 ),
.O(\result[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFF890089FF89FF89))
\result[5]_i_7
(.I0(opcode_2[0]),
.I1(opcode_2[4]),
.I2(literal_2[5]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(\result_reg[7]_i_13_n_6 ),
.O(\result[5]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[5]_i_8
(.I0(\result[11]_i_14_n_0 ),
.I1(\result[7]_i_14_n_0 ),
.I2(store_data[1]),
.I3(\result[9]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[5]_i_9_n_0 ),
.O(\result[5]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[5]_i_9
(.I0(\read_input[29]_i_1_n_0 ),
.I1(\read_input[13]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[21]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[5]_i_1_n_0 ),
.O(\result[5]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44440400))
\result[6]_i_1
(.I0(\result[6]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(\result[6]_i_3_n_0 ),
.I4(\result[6]_i_4_n_0 ),
.I5(\result[6]_i_5_n_0 ),
.O(\result[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1FFFBF00000000))
\result[6]_i_2
(.I0(store_data[0]),
.I1(\result[7]_i_7_n_0 ),
.I2(\result[7]_i_6_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(\result[6]_i_6_n_0 ),
.I5(\result[6]_i_7_n_0 ),
.O(\result[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[6]_i_3
(.I0(\result[6]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[7]_i_9_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[6]),
.O(\result[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[6]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[6]),
.I3(opcode_2[1]),
.I4(\result_reg[7]_i_11_n_5 ),
.I5(opcode_2[0]),
.O(\result[6]_i_4_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[6]_i_5
(.I0(load_data[6]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[6]),
.I3(\state_reg_n_0_[2] ),
.O(\result[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0004FFFF00040000))
\result[6]_i_6
(.I0(store_data[3]),
.I1(\read_input[3]_i_1_n_0 ),
.I2(store_data[4]),
.I3(store_data[2]),
.I4(store_data[1]),
.I5(\result[8]_i_11_n_0 ),
.O(\result[6]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFF890089FF89FF89))
\result[6]_i_7
(.I0(opcode_2[0]),
.I1(opcode_2[4]),
.I2(literal_2[6]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(\result_reg[7]_i_13_n_5 ),
.O(\result[6]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[6]_i_8
(.I0(\result[12]_i_12_n_0 ),
.I1(\result[8]_i_12_n_0 ),
.I2(store_data[1]),
.I3(\result[10]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[6]_i_9_n_0 ),
.O(\result[6]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[6]_i_9
(.I0(\read_input[30]_i_1_n_0 ),
.I1(\read_input[14]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[22]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[6]_i_1_n_0 ),
.O(\result[6]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44440400))
\result[7]_i_1
(.I0(\result[7]_i_2_n_0 ),
.I1(\state_reg_n_0_[0] ),
.I2(opcode_2[0]),
.I3(\result[7]_i_3_n_0 ),
.I4(\result[7]_i_4_n_0 ),
.I5(\result[7]_i_5_n_0 ),
.O(\result[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\result[7]_i_12
(.I0(\read_input[0]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[4]),
.I3(\read_input[4]_i_1_n_0 ),
.I4(store_data[3]),
.O(\result[7]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[7]_i_14
(.I0(\read_input[31]_i_2_n_0 ),
.I1(\read_input[15]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[23]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[7]_i_1_n_0 ),
.O(\result[7]_i_14_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[7]_i_15
(.I0(result[7]),
.I1(operand_b1),
.I2(register_b[7]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[7]),
.O(\result[7]_i_15_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[7]_i_16
(.I0(result[6]),
.I1(operand_b1),
.I2(register_b[6]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[6]),
.O(\result[7]_i_16_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[7]_i_17
(.I0(result[5]),
.I1(operand_b1),
.I2(register_b[5]),
.I3(\result[31]_i_21_n_0 ),
.I4(register_a[5]),
.O(\result[7]_i_17_n_0 ));
LUT4 #(
.INIT(16'h9A95))
\result[7]_i_18
(.I0(store_data[4]),
.I1(result[4]),
.I2(\result[31]_i_21_n_0 ),
.I3(register_a[4]),
.O(\result[7]_i_18_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_19
(.I0(register_a[7]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[7]),
.I3(literal_2[7]),
.O(\result[7]_i_19_n_0 ));
LUT6 #(
.INIT(64'hFF1FFFBF00000000))
\result[7]_i_2
(.I0(store_data[0]),
.I1(\result[8]_i_7_n_0 ),
.I2(\result[7]_i_6_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(\result[7]_i_7_n_0 ),
.I5(\result[7]_i_8_n_0 ),
.O(\result[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_20
(.I0(register_a[6]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[6]),
.I3(literal_2[6]),
.O(\result[7]_i_20_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_21
(.I0(register_a[5]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[5]),
.I3(literal_2[5]),
.O(\result[7]_i_21_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_22
(.I0(register_a[4]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[4]),
.I3(literal_2[4]),
.O(\result[7]_i_22_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_23
(.I0(register_a[7]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[7]),
.I3(operand_b1),
.I4(result[7]),
.O(\result[7]_i_23_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_24
(.I0(register_a[6]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[6]),
.I3(operand_b1),
.I4(result[6]),
.O(\result[7]_i_24_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[7]_i_25
(.I0(register_a[5]),
.I1(\result[31]_i_21_n_0 ),
.I2(register_b[5]),
.I3(operand_b1),
.I4(result[5]),
.O(\result[7]_i_25_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_26
(.I0(register_a[4]),
.I1(\result[31]_i_21_n_0 ),
.I2(result[4]),
.I3(store_data[4]),
.O(\result[7]_i_26_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[7]_i_3
(.I0(\result[7]_i_9_n_0 ),
.I1(store_data[0]),
.I2(\result[8]_i_9_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[7]),
.O(\result[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[7]_i_4
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[7]),
.I3(opcode_2[1]),
.I4(\result_reg[7]_i_11_n_4 ),
.I5(opcode_2[0]),
.O(\result[7]_i_4_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[7]_i_5
(.I0(load_data[7]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[7]),
.I3(\state_reg_n_0_[2] ),
.O(\result[7]_i_5_n_0 ));
LUT2 #(
.INIT(4'h8))
\result[7]_i_6
(.I0(opcode_2[2]),
.I1(opcode_2[0]),
.O(\result[7]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[7]_i_7
(.I0(\result[7]_i_12_n_0 ),
.I1(store_data[1]),
.I2(\result[9]_i_10_n_0 ),
.O(\result[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFF890089FF89FF89))
\result[7]_i_8
(.I0(opcode_2[0]),
.I1(opcode_2[4]),
.I2(literal_2[7]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(\result_reg[7]_i_13_n_4 ),
.O(\result[7]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[7]_i_9
(.I0(\result[13]_i_11_n_0 ),
.I1(\result[9]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[11]_i_14_n_0 ),
.I4(store_data[2]),
.I5(\result[7]_i_14_n_0 ),
.O(\result[7]_i_9_n_0 ));
LUT6 #(
.INIT(64'hBABABABAAABAAAAA))
\result[8]_i_1
(.I0(\result[8]_i_2_n_0 ),
.I1(\result[8]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(opcode_2[0]),
.I4(\result[8]_i_4_n_0 ),
.I5(\result[8]_i_5_n_0 ),
.O(\result[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\result[8]_i_11
(.I0(\read_input[1]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[4]),
.I3(\read_input[5]_i_1_n_0 ),
.I4(store_data[3]),
.O(\result[8]_i_11_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[8]_i_12
(.I0(\read_input[16]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[24]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[8]_i_1_n_0 ),
.O(\result[8]_i_12_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[8]_i_2
(.I0(load_data[8]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000A2A2A0AA))
\result[8]_i_3
(.I0(\result[8]_i_6_n_0 ),
.I1(\result[8]_i_7_n_0 ),
.I2(\result[16]_i_7_n_0 ),
.I3(\result[9]_i_7_n_0 ),
.I4(store_data[0]),
.I5(\result[8]_i_8_n_0 ),
.O(\result[8]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[8]_i_4
(.I0(\result[8]_i_9_n_0 ),
.I1(store_data[0]),
.I2(\result[9]_i_9_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[8]),
.O(\result[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[8]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[8]),
.I3(opcode_2[1]),
.I4(\result_reg[11]_i_11_n_7 ),
.I5(opcode_2[0]),
.O(\result[8]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFCCD))
\result[8]_i_6
(.I0(literal_2[8]),
.I1(opcode_2[3]),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.O(\result[8]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[8]_i_7
(.I0(\result[8]_i_11_n_0 ),
.I1(store_data[1]),
.I2(\result[10]_i_10_n_0 ),
.O(\result[8]_i_7_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[8]_i_8
(.I0(\result_reg[11]_i_13_n_7 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[8]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[8]_i_9
(.I0(\result[14]_i_9_n_0 ),
.I1(\result[10]_i_11_n_0 ),
.I2(store_data[1]),
.I3(\result[12]_i_12_n_0 ),
.I4(store_data[2]),
.I5(\result[8]_i_12_n_0 ),
.O(\result[8]_i_9_n_0 ));
LUT6 #(
.INIT(64'hBABABABAAABAAAAA))
\result[9]_i_1
(.I0(\result[9]_i_2_n_0 ),
.I1(\result[9]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(opcode_2[0]),
.I4(\result[9]_i_4_n_0 ),
.I5(\result[9]_i_5_n_0 ),
.O(\result[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\result[9]_i_10
(.I0(\read_input[2]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[4]),
.I3(\read_input[6]_i_1_n_0 ),
.I4(store_data[3]),
.O(\result[9]_i_10_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[9]_i_11
(.I0(\read_input[17]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[25]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[9]_i_1_n_0 ),
.O(\result[9]_i_11_n_0 ));
LUT3 #(
.INIT(8'h08))
\result[9]_i_2
(.I0(load_data[9]),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[1] ),
.O(\result[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000A2A2A0AA))
\result[9]_i_3
(.I0(\result[9]_i_6_n_0 ),
.I1(\result[9]_i_7_n_0 ),
.I2(\result[16]_i_7_n_0 ),
.I3(\result[10]_i_7_n_0 ),
.I4(store_data[0]),
.I5(\result[9]_i_8_n_0 ),
.O(\result[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00E2FFFF00E20000))
\result[9]_i_4
(.I0(\result[9]_i_9_n_0 ),
.I1(store_data[0]),
.I2(\result[10]_i_9_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(opcode_2[1]),
.I5(data7[9]),
.O(\result[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFEFFFEEEBBBBBBBB))
\result[9]_i_5
(.I0(opcode_2[3]),
.I1(opcode_2[4]),
.I2(data2[9]),
.I3(opcode_2[1]),
.I4(\result_reg[11]_i_11_n_6 ),
.I5(opcode_2[0]),
.O(\result[9]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFCCD))
\result[9]_i_6
(.I0(literal_2[9]),
.I1(opcode_2[3]),
.I2(opcode_2[4]),
.I3(opcode_2[0]),
.O(\result[9]_i_6_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[9]_i_7
(.I0(\result[9]_i_10_n_0 ),
.I1(store_data[1]),
.I2(\result[11]_i_12_n_0 ),
.O(\result[9]_i_7_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[9]_i_8
(.I0(\result_reg[11]_i_13_n_6 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.O(\result[9]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[9]_i_9
(.I0(\result[15]_i_15_n_0 ),
.I1(\result[11]_i_14_n_0 ),
.I2(store_data[1]),
.I3(\result[13]_i_11_n_0 ),
.I4(store_data[2]),
.I5(\result[9]_i_11_n_0 ),
.O(\result[9]_i_9_n_0 ));
FDRE \result_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[0]_i_1_n_0 ),
.Q(result[0]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[0]_i_10
(.CI(\result_reg[0]_i_15_n_0 ),
.CO({data6,\NLW_result_reg[0]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_16_n_0 ,\result[0]_i_17_n_0 ,\result[0]_i_18_n_0 ,\result[0]_i_19_n_0 }),
.O(\NLW_result_reg[0]_i_10_O_UNCONNECTED [3:0]),
.S({\result[0]_i_20_n_0 ,\result[0]_i_21_n_0 ,\result[0]_i_22_n_0 ,\result[0]_i_23_n_0 }));
CARRY4 \result_reg[0]_i_12
(.CI(\result_reg[0]_i_24_n_0 ),
.CO({data8,\NLW_result_reg[0]_i_12_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_25_n_0 ,\result[0]_i_17_n_0 ,\result[0]_i_18_n_0 ,\result[0]_i_19_n_0 }),
.O(\NLW_result_reg[0]_i_12_O_UNCONNECTED [3:0]),
.S({\result[0]_i_26_n_0 ,\result[0]_i_27_n_0 ,\result[0]_i_28_n_0 ,\result[0]_i_29_n_0 }));
CARRY4 \result_reg[0]_i_14
(.CI(\result_reg[0]_i_30_n_0 ),
.CO({\NLW_result_reg[0]_i_14_CO_UNCONNECTED [3],data4,\NLW_result_reg[0]_i_14_CO_UNCONNECTED [1:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_result_reg[0]_i_14_O_UNCONNECTED [3:0]),
.S({1'b0,\result[0]_i_31_n_0 ,\result[0]_i_32_n_0 ,\result[0]_i_33_n_0 }));
CARRY4 \result_reg[0]_i_15
(.CI(\result_reg[0]_i_34_n_0 ),
.CO({\result_reg[0]_i_15_n_0 ,\NLW_result_reg[0]_i_15_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_35_n_0 ,\result[0]_i_36_n_0 ,\result[0]_i_37_n_0 ,\result[0]_i_38_n_0 }),
.O(\NLW_result_reg[0]_i_15_O_UNCONNECTED [3:0]),
.S({\result[0]_i_39_n_0 ,\result[0]_i_40_n_0 ,\result[0]_i_41_n_0 ,\result[0]_i_42_n_0 }));
CARRY4 \result_reg[0]_i_24
(.CI(\result_reg[0]_i_52_n_0 ),
.CO({\result_reg[0]_i_24_n_0 ,\NLW_result_reg[0]_i_24_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_35_n_0 ,\result[0]_i_36_n_0 ,\result[0]_i_37_n_0 ,\result[0]_i_38_n_0 }),
.O(\NLW_result_reg[0]_i_24_O_UNCONNECTED [3:0]),
.S({\result[0]_i_53_n_0 ,\result[0]_i_54_n_0 ,\result[0]_i_55_n_0 ,\result[0]_i_56_n_0 }));
CARRY4 \result_reg[0]_i_30
(.CI(\result_reg[0]_i_57_n_0 ),
.CO({\result_reg[0]_i_30_n_0 ,\NLW_result_reg[0]_i_30_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_result_reg[0]_i_30_O_UNCONNECTED [3:0]),
.S({\result[0]_i_58_n_0 ,\result[0]_i_59_n_0 ,\result[0]_i_60_n_0 ,\result[0]_i_61_n_0 }));
CARRY4 \result_reg[0]_i_34
(.CI(\result_reg[0]_i_64_n_0 ),
.CO({\result_reg[0]_i_34_n_0 ,\NLW_result_reg[0]_i_34_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_65_n_0 ,\result[0]_i_66_n_0 ,\result[0]_i_67_n_0 ,\result[0]_i_68_n_0 }),
.O(\NLW_result_reg[0]_i_34_O_UNCONNECTED [3:0]),
.S({\result[0]_i_69_n_0 ,\result[0]_i_70_n_0 ,\result[0]_i_71_n_0 ,\result[0]_i_72_n_0 }));
CARRY4 \result_reg[0]_i_52
(.CI(\result_reg[0]_i_80_n_0 ),
.CO({\result_reg[0]_i_52_n_0 ,\NLW_result_reg[0]_i_52_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_65_n_0 ,\result[0]_i_66_n_0 ,\result[0]_i_67_n_0 ,\result[0]_i_68_n_0 }),
.O(\NLW_result_reg[0]_i_52_O_UNCONNECTED [3:0]),
.S({\result[0]_i_81_n_0 ,\result[0]_i_82_n_0 ,\result[0]_i_83_n_0 ,\result[0]_i_84_n_0 }));
CARRY4 \result_reg[0]_i_57
(.CI(1'b0),
.CO({\result_reg[0]_i_57_n_0 ,\NLW_result_reg[0]_i_57_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_result_reg[0]_i_57_O_UNCONNECTED [3:0]),
.S({\result[0]_i_85_n_0 ,\result[0]_i_86_n_0 ,\result[0]_i_87_n_0 ,\result[0]_i_88_n_0 }));
CARRY4 \result_reg[0]_i_64
(.CI(1'b0),
.CO({\result_reg[0]_i_64_n_0 ,\NLW_result_reg[0]_i_64_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\result[0]_i_93_n_0 ,\result[0]_i_94_n_0 ,\result[0]_i_95_n_0 ,\result[0]_i_96_n_0 }),
.O(\NLW_result_reg[0]_i_64_O_UNCONNECTED [3:0]),
.S({\result[0]_i_97_n_0 ,\result[0]_i_98_n_0 ,\result[0]_i_99_n_0 ,\result[0]_i_100_n_0 }));
CARRY4 \result_reg[0]_i_80
(.CI(1'b0),
.CO({\result_reg[0]_i_80_n_0 ,\NLW_result_reg[0]_i_80_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_93_n_0 ,\result[0]_i_94_n_0 ,\result[0]_i_95_n_0 ,\result[0]_i_96_n_0 }),
.O(\NLW_result_reg[0]_i_80_O_UNCONNECTED [3:0]),
.S({\result[0]_i_104_n_0 ,\result[0]_i_105_n_0 ,\result[0]_i_106_n_0 ,\result[0]_i_107_n_0 }));
FDRE \result_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[10]_i_1_n_0 ),
.Q(result[10]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[11]_i_1_n_0 ),
.Q(result[11]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[11]_i_10
(.CI(\result_reg[7]_i_10_n_0 ),
.CO({\result_reg[11]_i_10_n_0 ,\NLW_result_reg[11]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
.O(data7[11:8]),
.S({\result[11]_i_15_n_0 ,\result[11]_i_16_n_0 ,\result[11]_i_17_n_0 ,\result[11]_i_18_n_0 }));
CARRY4 \result_reg[11]_i_11
(.CI(\result_reg[7]_i_11_n_0 ),
.CO({\result_reg[11]_i_11_n_0 ,\NLW_result_reg[11]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
.O({\result_reg[11]_i_11_n_4 ,\result_reg[11]_i_11_n_5 ,\result_reg[11]_i_11_n_6 ,\result_reg[11]_i_11_n_7 }),
.S({\result[11]_i_19_n_0 ,\result[11]_i_20_n_0 ,\result[11]_i_21_n_0 ,\result[11]_i_22_n_0 }));
CARRY4 \result_reg[11]_i_13
(.CI(\result_reg[7]_i_13_n_0 ),
.CO({\result_reg[11]_i_13_n_0 ,\NLW_result_reg[11]_i_13_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
.O({\result_reg[11]_i_13_n_4 ,\result_reg[11]_i_13_n_5 ,\result_reg[11]_i_13_n_6 ,\result_reg[11]_i_13_n_7 }),
.S({\result[11]_i_23_n_0 ,\result[11]_i_24_n_0 ,\result[11]_i_25_n_0 ,\result[11]_i_26_n_0 }));
FDRE \result_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[12]_i_1_n_0 ),
.Q(result[12]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[12]_i_10
(.CI(\result_reg[8]_i_10_n_0 ),
.CO({\result_reg[12]_i_10_n_0 ,\NLW_result_reg[12]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[12:9]),
.S(program_counter_2[12:9]));
FDRE \result_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[13]_i_1_n_0 ),
.Q(result[13]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[14]_i_1_n_0 ),
.Q(result[14]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[15]_i_1_n_0 ),
.Q(result[15]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[15]_i_7
(.CI(\result_reg[11]_i_10_n_0 ),
.CO({\result_reg[15]_i_7_n_0 ,\NLW_result_reg[15]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
.O(data7[15:12]),
.S({\result[15]_i_11_n_0 ,\result[15]_i_12_n_0 ,\result[15]_i_13_n_0 ,\result[15]_i_14_n_0 }));
CARRY4 \result_reg[15]_i_9
(.CI(\result_reg[11]_i_11_n_0 ),
.CO({\result_reg[15]_i_9_n_0 ,\NLW_result_reg[15]_i_9_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
.O({\result_reg[15]_i_9_n_4 ,\result_reg[15]_i_9_n_5 ,\result_reg[15]_i_9_n_6 ,\result_reg[15]_i_9_n_7 }),
.S({\result[15]_i_16_n_0 ,\result[15]_i_17_n_0 ,\result[15]_i_18_n_0 ,\result[15]_i_19_n_0 }));
FDRE \result_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[16]_i_1_n_0 ),
.Q(result[16]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[16]_i_11
(.CI(\result_reg[12]_i_10_n_0 ),
.CO({data2[16],\NLW_result_reg[16]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_result_reg[16]_i_11_O_UNCONNECTED [3],data2[15:13]}),
.S({1'b1,program_counter_2[15:13]}));
CARRY4 \result_reg[16]_i_9
(.CI(\result_reg[15]_i_7_n_0 ),
.CO({\result_reg[16]_i_9_n_0 ,\NLW_result_reg[16]_i_9_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[19]_i_1_n_0 ,\read_input[18]_i_1_n_0 ,\read_input[17]_i_1_n_0 ,\read_input[16]_i_1_n_0 }),
.O(data7[19:16]),
.S({\result[16]_i_14_n_0 ,\result[16]_i_15_n_0 ,\result[16]_i_16_n_0 ,\result[16]_i_17_n_0 }));
FDRE \result_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[17]_i_1_n_0 ),
.Q(result[17]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[18]_i_1_n_0 ),
.Q(result[18]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[19]_i_1_n_0 ),
.Q(result[19]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[19]_i_11
(.CI(\result_reg[15]_i_9_n_0 ),
.CO({\result_reg[19]_i_11_n_0 ,\NLW_result_reg[19]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[19]_i_11_n_4 ,\result_reg[19]_i_11_n_5 ,\result_reg[19]_i_11_n_6 ,\result_reg[19]_i_11_n_7 }),
.S({\result[19]_i_20_n_0 ,\result[19]_i_21_n_0 ,\result[19]_i_22_n_0 ,\result[19]_i_23_n_0 }));
CARRY4 \result_reg[19]_i_12
(.CI(\result_reg[11]_i_13_n_0 ),
.CO({\result_reg[19]_i_12_n_0 ,\NLW_result_reg[19]_i_12_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
.O({\result_reg[19]_i_12_n_4 ,\result_reg[19]_i_12_n_5 ,\result_reg[19]_i_12_n_6 ,\result_reg[19]_i_12_n_7 }),
.S({\result[19]_i_24_n_0 ,\result[19]_i_25_n_0 ,\result[19]_i_26_n_0 ,\result[19]_i_27_n_0 }));
CARRY4 \result_reg[19]_i_7
(.CI(\result_reg[19]_i_12_n_0 ),
.CO({\result_reg[19]_i_7_n_0 ,\NLW_result_reg[19]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[19]_i_1_n_0 ,\read_input[18]_i_1_n_0 ,\read_input[17]_i_1_n_0 ,\read_input[16]_i_1_n_0 }),
.O({\result_reg[19]_i_7_n_4 ,\result_reg[19]_i_7_n_5 ,\result_reg[19]_i_7_n_6 ,\result_reg[19]_i_7_n_7 }),
.S({\result[19]_i_13_n_0 ,\result[19]_i_14_n_0 ,\result[19]_i_15_n_0 ,\result[19]_i_16_n_0 }));
FDRE \result_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[1]_i_1_n_0 ),
.Q(result[1]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[20]_i_1_n_0 ),
.Q(result[20]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[21]_i_1_n_0 ),
.Q(result[21]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[22]_i_1_n_0 ),
.Q(result[22]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[23]_i_1_n_0 ),
.Q(result[23]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[23]_i_11
(.CI(\result_reg[19]_i_11_n_0 ),
.CO({\result_reg[23]_i_11_n_0 ,\NLW_result_reg[23]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[23]_i_11_n_4 ,\result_reg[23]_i_11_n_5 ,\result_reg[23]_i_11_n_6 ,\result_reg[23]_i_11_n_7 }),
.S({\result[23]_i_18_n_0 ,\result[23]_i_19_n_0 ,\result[23]_i_20_n_0 ,\result[23]_i_21_n_0 }));
CARRY4 \result_reg[23]_i_7
(.CI(\result_reg[19]_i_7_n_0 ),
.CO({\result_reg[23]_i_7_n_0 ,\NLW_result_reg[23]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[23]_i_1_n_0 ,\read_input[22]_i_1_n_0 ,\read_input[21]_i_1_n_0 ,\read_input[20]_i_1_n_0 }),
.O({\result_reg[23]_i_7_n_4 ,\result_reg[23]_i_7_n_5 ,\result_reg[23]_i_7_n_6 ,\result_reg[23]_i_7_n_7 }),
.S({\result[23]_i_12_n_0 ,\result[23]_i_13_n_0 ,\result[23]_i_14_n_0 ,\result[23]_i_15_n_0 }));
FDRE \result_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[24]_i_1_n_0 ),
.Q(result[24]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[25]_i_1_n_0 ),
.Q(result[25]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[26]_i_1_n_0 ),
.Q(result[26]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[27]_i_1_n_0 ),
.Q(result[27]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[27]_i_10
(.CI(\result_reg[27]_i_18_n_0 ),
.CO({\result_reg[27]_i_10_n_0 ,\NLW_result_reg[27]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[27]_i_1_n_0 ,\read_input[26]_i_1_n_0 ,\read_input[25]_i_1_n_0 ,\read_input[24]_i_1_n_0 }),
.O(data7[27:24]),
.S({\result[27]_i_19_n_0 ,\result[27]_i_20_n_0 ,\result[27]_i_21_n_0 ,\result[27]_i_22_n_0 }));
CARRY4 \result_reg[27]_i_18
(.CI(\result_reg[16]_i_9_n_0 ),
.CO({\result_reg[27]_i_18_n_0 ,\NLW_result_reg[27]_i_18_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[23]_i_1_n_0 ,\read_input[22]_i_1_n_0 ,\read_input[21]_i_1_n_0 ,\read_input[20]_i_1_n_0 }),
.O(data7[23:20]),
.S({\result[27]_i_24_n_0 ,\result[27]_i_25_n_0 ,\result[27]_i_26_n_0 ,\result[27]_i_27_n_0 }));
CARRY4 \result_reg[27]_i_23
(.CI(\result_reg[23]_i_11_n_0 ),
.CO({\result_reg[27]_i_23_n_0 ,\NLW_result_reg[27]_i_23_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[27]_i_23_n_4 ,\result_reg[27]_i_23_n_5 ,\result_reg[27]_i_23_n_6 ,\result_reg[27]_i_23_n_7 }),
.S({\result[27]_i_28_n_0 ,\result[27]_i_29_n_0 ,\result[27]_i_30_n_0 ,\result[27]_i_31_n_0 }));
CARRY4 \result_reg[27]_i_7
(.CI(\result_reg[23]_i_7_n_0 ),
.CO({\result_reg[27]_i_7_n_0 ,\NLW_result_reg[27]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[27]_i_1_n_0 ,\read_input[26]_i_1_n_0 ,\read_input[25]_i_1_n_0 ,\read_input[24]_i_1_n_0 }),
.O({\result_reg[27]_i_7_n_4 ,\result_reg[27]_i_7_n_5 ,\result_reg[27]_i_7_n_6 ,\result_reg[27]_i_7_n_7 }),
.S({\result[27]_i_12_n_0 ,\result[27]_i_13_n_0 ,\result[27]_i_14_n_0 ,\result[27]_i_15_n_0 }));
FDRE \result_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[28]_i_1_n_0 ),
.Q(result[28]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[29]_i_1_n_0 ),
.Q(result[29]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[2]_i_1_n_0 ),
.Q(result[2]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[30]_i_1_n_0 ),
.Q(result[30]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[31]_i_2_n_0 ),
.Q(result[31]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[31]_i_10
(.CI(\result_reg[27]_i_7_n_0 ),
.CO(\NLW_result_reg[31]_i_10_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,\read_input[30]_i_1_n_0 ,\read_input[29]_i_1_n_0 ,\read_input[28]_i_1_n_0 }),
.O({\result_reg[31]_i_10_n_4 ,\result_reg[31]_i_10_n_5 ,\result_reg[31]_i_10_n_6 ,\result_reg[31]_i_10_n_7 }),
.S({\result[31]_i_17_n_0 ,\result[31]_i_18_n_0 ,\result[31]_i_19_n_0 ,\result[31]_i_20_n_0 }));
CARRY4 \result_reg[31]_i_15
(.CI(\result_reg[27]_i_10_n_0 ),
.CO(\NLW_result_reg[31]_i_15_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,\read_input[30]_i_1_n_0 ,\read_input[29]_i_1_n_0 ,\read_input[28]_i_1_n_0 }),
.O(data7[31:28]),
.S({\result[31]_i_36_n_0 ,\result[31]_i_37_n_0 ,\result[31]_i_38_n_0 ,\result[31]_i_39_n_0 }));
CARRY4 \result_reg[31]_i_40
(.CI(\result_reg[27]_i_23_n_0 ),
.CO(\NLW_result_reg[31]_i_40_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[31]_i_40_n_4 ,\result_reg[31]_i_40_n_5 ,\result_reg[31]_i_40_n_6 ,\result_reg[31]_i_40_n_7 }),
.S({\result[31]_i_41_n_0 ,\result[31]_i_42_n_0 ,\result[31]_i_43_n_0 ,\result[31]_i_44_n_0 }));
FDRE \result_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[3]_i_1_n_0 ),
.Q(result[3]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[3]_i_10
(.CI(1'b0),
.CO({\result_reg[3]_i_10_n_0 ,\NLW_result_reg[3]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
.O({\result_reg[3]_i_10_n_4 ,\result_reg[3]_i_10_n_5 ,\result_reg[3]_i_10_n_6 ,\result_reg[3]_i_10_n_7 }),
.S({\result[3]_i_17_n_0 ,\result[3]_i_18_n_0 ,\result[3]_i_19_n_0 ,\result[3]_i_20_n_0 }));
CARRY4 \result_reg[3]_i_11
(.CI(1'b0),
.CO({\result_reg[3]_i_11_n_0 ,\NLW_result_reg[3]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
.O({\result_reg[3]_i_11_n_4 ,\result_reg[3]_i_11_n_5 ,\result_reg[3]_i_11_n_6 ,\result_reg[3]_i_11_n_7 }),
.S({\result[3]_i_21_n_0 ,\result[3]_i_22_n_0 ,\result[3]_i_23_n_0 ,\result[3]_i_24_n_0 }));
CARRY4 \result_reg[3]_i_9
(.CI(1'b0),
.CO({\result_reg[3]_i_9_n_0 ,\NLW_result_reg[3]_i_9_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
.O(data7[3:0]),
.S({\result[3]_i_13_n_0 ,\result[3]_i_14_n_0 ,\result[3]_i_15_n_0 ,\result[3]_i_16_n_0 }));
FDRE \result_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[4]_i_1_n_0 ),
.Q(result[4]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[4]_i_9
(.CI(1'b0),
.CO({\result_reg[4]_i_9_n_0 ,\NLW_result_reg[4]_i_9_CO_UNCONNECTED [2:0]}),
.CYINIT(program_counter_2[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[4:1]),
.S(program_counter_2[4:1]));
FDRE \result_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[5]_i_1_n_0 ),
.Q(result[5]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[6]_i_1_n_0 ),
.Q(result[6]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[7]_i_1_n_0 ),
.Q(result[7]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[7]_i_10
(.CI(\result_reg[3]_i_9_n_0 ),
.CO({\result_reg[7]_i_10_n_0 ,\NLW_result_reg[7]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
.O(data7[7:4]),
.S({\result[7]_i_15_n_0 ,\result[7]_i_16_n_0 ,\result[7]_i_17_n_0 ,\result[7]_i_18_n_0 }));
CARRY4 \result_reg[7]_i_11
(.CI(\result_reg[3]_i_10_n_0 ),
.CO({\result_reg[7]_i_11_n_0 ,\NLW_result_reg[7]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
.O({\result_reg[7]_i_11_n_4 ,\result_reg[7]_i_11_n_5 ,\result_reg[7]_i_11_n_6 ,\result_reg[7]_i_11_n_7 }),
.S({\result[7]_i_19_n_0 ,\result[7]_i_20_n_0 ,\result[7]_i_21_n_0 ,\result[7]_i_22_n_0 }));
CARRY4 \result_reg[7]_i_13
(.CI(\result_reg[3]_i_11_n_0 ),
.CO({\result_reg[7]_i_13_n_0 ,\NLW_result_reg[7]_i_13_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
.O({\result_reg[7]_i_13_n_4 ,\result_reg[7]_i_13_n_5 ,\result_reg[7]_i_13_n_6 ,\result_reg[7]_i_13_n_7 }),
.S({\result[7]_i_23_n_0 ,\result[7]_i_24_n_0 ,\result[7]_i_25_n_0 ,\result[7]_i_26_n_0 }));
FDRE \result_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[8]_i_1_n_0 ),
.Q(result[8]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[8]_i_10
(.CI(\result_reg[4]_i_9_n_0 ),
.CO({\result_reg[8]_i_10_n_0 ,\NLW_result_reg[8]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[8:5]),
.S(program_counter_2[8:5]));
FDRE \result_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[9]_i_1_n_0 ),
.Q(result[9]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFDFFF00003000))
\s_input_rs232_rx_ack[0]_i_1
(.I0(OUT1_STB),
.I1(\state_reg_n_0_[0] ),
.I2(\state_reg_n_0_[2] ),
.I3(\state_reg_n_0_[1] ),
.I4(\s_input_rs232_rx_ack[0]_i_2_n_0 ),
.I5(OUT1_ACK),
.O(\s_input_rs232_rx_ack[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_input_rs232_rx_ack[0]_i_2
(.I0(\s_input_rs232_rx_ack[0]_i_3_n_0 ),
.I1(\s_input_rs232_rx_ack[0]_i_4_n_0 ),
.I2(\s_input_rs232_rx_ack[0]_i_5_n_0 ),
.I3(\s_input_rs232_rx_ack[0]_i_6_n_0 ),
.I4(\s_input_rs232_rx_ack[0]_i_7_n_0 ),
.I5(\s_input_rs232_rx_ack[0]_i_8_n_0 ),
.O(\s_input_rs232_rx_ack[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFEFF))
\s_input_rs232_rx_ack[0]_i_3
(.I0(read_input[27]),
.I1(read_input[0]),
.I2(read_input[18]),
.I3(read_input[2]),
.I4(read_input[4]),
.I5(read_input[29]),
.O(\s_input_rs232_rx_ack[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\s_input_rs232_rx_ack[0]_i_4
(.I0(read_input[17]),
.I1(read_input[23]),
.O(\s_input_rs232_rx_ack[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_input_rs232_rx_ack[0]_i_5
(.I0(read_input[11]),
.I1(read_input[10]),
.I2(read_input[14]),
.I3(read_input[20]),
.I4(read_input[7]),
.I5(read_input[19]),
.O(\s_input_rs232_rx_ack[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_input_rs232_rx_ack[0]_i_6
(.I0(read_input[9]),
.I1(read_input[8]),
.I2(read_input[26]),
.I3(read_input[30]),
.I4(read_input[13]),
.I5(read_input[15]),
.O(\s_input_rs232_rx_ack[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_input_rs232_rx_ack[0]_i_7
(.I0(read_input[31]),
.I1(read_input[28]),
.I2(read_input[1]),
.I3(read_input[21]),
.I4(read_input[6]),
.I5(read_input[12]),
.O(\s_input_rs232_rx_ack[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_input_rs232_rx_ack[0]_i_8
(.I0(read_input[24]),
.I1(read_input[3]),
.I2(read_input[16]),
.I3(read_input[22]),
.I4(read_input[5]),
.I5(read_input[25]),
.O(\s_input_rs232_rx_ack[0]_i_8_n_0 ));
FDRE \s_input_rs232_rx_ack_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\s_input_rs232_rx_ack[0]_i_1_n_0 ),
.Q(OUT1_ACK),
.R(INTERNAL_RST_reg));
LUT5 #(
.INIT(32'h80000000))
\s_output_led_b[7]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(write_output[1]),
.I2(\state_reg_n_0_[0] ),
.I3(\state_reg_n_0_[1] ),
.I4(\s_output_led_b[7]_i_2_n_0 ),
.O(\s_output_led_b[7]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\s_output_led_b[7]_i_2
(.I0(write_output[0]),
.I1(\s_output_rs232_tx[7]_i_2_n_0 ),
.O(\s_output_led_b[7]_i_2_n_0 ));
FDRE \s_output_led_b_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_b[7]_i_1_n_0 ),
.D(write_value[0]),
.Q(output_led_b[0]),
.R(1'b0));
FDRE \s_output_led_b_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_b[7]_i_1_n_0 ),
.D(write_value[1]),
.Q(output_led_b[1]),
.R(1'b0));
FDRE \s_output_led_b_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_b[7]_i_1_n_0 ),
.D(write_value[2]),
.Q(output_led_b[2]),
.R(1'b0));
FDRE \s_output_led_b_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_b[7]_i_1_n_0 ),
.D(write_value[3]),
.Q(output_led_b[3]),
.R(1'b0));
FDRE \s_output_led_b_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_b[7]_i_1_n_0 ),
.D(write_value[4]),
.Q(output_led_b[4]),
.R(1'b0));
FDRE \s_output_led_b_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_b[7]_i_1_n_0 ),
.D(write_value[5]),
.Q(output_led_b[5]),
.R(1'b0));
FDRE \s_output_led_b_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_b[7]_i_1_n_0 ),
.D(write_value[6]),
.Q(output_led_b[6]),
.R(1'b0));
FDRE \s_output_led_b_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_b[7]_i_1_n_0 ),
.D(write_value[7]),
.Q(output_led_b[7]),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\s_output_led_b_stb[0]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(write_output[1]),
.I2(\state_reg_n_0_[0] ),
.I3(\state_reg_n_0_[1] ),
.I4(\s_output_led_b[7]_i_2_n_0 ),
.I5(E),
.O(\s_output_led_b_stb[0]_i_1_n_0 ));
FDRE \s_output_led_b_stb_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\s_output_led_b_stb[0]_i_1_n_0 ),
.Q(E),
.R(INTERNAL_RST_reg));
LUT4 #(
.INIT(16'h0800))
\s_output_led_g[7]_i_1
(.I0(\s_output_led_r[7]_i_2_n_0 ),
.I1(write_output[0]),
.I2(write_output[1]),
.I3(\state_reg_n_0_[1] ),
.O(\s_output_led_g[7]_i_1_n_0 ));
FDRE \s_output_led_g_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_g[7]_i_1_n_0 ),
.D(write_value[0]),
.Q(output_led_g[0]),
.R(1'b0));
FDRE \s_output_led_g_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_g[7]_i_1_n_0 ),
.D(write_value[1]),
.Q(output_led_g[1]),
.R(1'b0));
FDRE \s_output_led_g_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_g[7]_i_1_n_0 ),
.D(write_value[2]),
.Q(output_led_g[2]),
.R(1'b0));
FDRE \s_output_led_g_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_g[7]_i_1_n_0 ),
.D(write_value[3]),
.Q(output_led_g[3]),
.R(1'b0));
FDRE \s_output_led_g_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_g[7]_i_1_n_0 ),
.D(write_value[4]),
.Q(output_led_g[4]),
.R(1'b0));
FDRE \s_output_led_g_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_g[7]_i_1_n_0 ),
.D(write_value[5]),
.Q(output_led_g[5]),
.R(1'b0));
FDRE \s_output_led_g_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_g[7]_i_1_n_0 ),
.D(write_value[6]),
.Q(output_led_g[6]),
.R(1'b0));
FDRE \s_output_led_g_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_g[7]_i_1_n_0 ),
.D(write_value[7]),
.Q(output_led_g[7]),
.R(1'b0));
LUT5 #(
.INIT(32'hF7FF0800))
\s_output_led_g_stb[0]_i_1
(.I0(\s_output_led_r[7]_i_2_n_0 ),
.I1(write_output[0]),
.I2(write_output[1]),
.I3(\state_reg_n_0_[1] ),
.I4(\PWM_VAL_reg[7] ),
.O(\s_output_led_g_stb[0]_i_1_n_0 ));
FDRE \s_output_led_g_stb_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\s_output_led_g_stb[0]_i_1_n_0 ),
.Q(\PWM_VAL_reg[7] ),
.R(INTERNAL_RST_reg));
LUT4 #(
.INIT(16'h0020))
\s_output_led_r[7]_i_1
(.I0(\s_output_led_r[7]_i_2_n_0 ),
.I1(write_output[1]),
.I2(\state_reg_n_0_[1] ),
.I3(write_output[0]),
.O(\s_output_led_r[7]_i_1_n_0 ));
LUT3 #(
.INIT(8'h40))
\s_output_led_r[7]_i_2
(.I0(\s_output_rs232_tx[7]_i_2_n_0 ),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[0] ),
.O(\s_output_led_r[7]_i_2_n_0 ));
FDRE \s_output_led_r_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_r[7]_i_1_n_0 ),
.D(write_value[0]),
.Q(output_led_r[0]),
.R(1'b0));
FDRE \s_output_led_r_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_r[7]_i_1_n_0 ),
.D(write_value[1]),
.Q(output_led_r[1]),
.R(1'b0));
FDRE \s_output_led_r_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_r[7]_i_1_n_0 ),
.D(write_value[2]),
.Q(output_led_r[2]),
.R(1'b0));
FDRE \s_output_led_r_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_r[7]_i_1_n_0 ),
.D(write_value[3]),
.Q(output_led_r[3]),
.R(1'b0));
FDRE \s_output_led_r_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_r[7]_i_1_n_0 ),
.D(write_value[4]),
.Q(output_led_r[4]),
.R(1'b0));
FDRE \s_output_led_r_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_r[7]_i_1_n_0 ),
.D(write_value[5]),
.Q(output_led_r[5]),
.R(1'b0));
FDRE \s_output_led_r_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_r[7]_i_1_n_0 ),
.D(write_value[6]),
.Q(output_led_r[6]),
.R(1'b0));
FDRE \s_output_led_r_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\s_output_led_r[7]_i_1_n_0 ),
.D(write_value[7]),
.Q(output_led_r[7]),
.R(1'b0));
LUT5 #(
.INIT(32'hFFDF0020))
\s_output_led_r_stb[0]_i_1
(.I0(\s_output_led_r[7]_i_2_n_0 ),
.I1(write_output[1]),
.I2(\state_reg_n_0_[1] ),
.I3(write_output[0]),
.I4(\PWM_VAL_reg[7]_0 ),
.O(\s_output_led_r_stb[0]_i_1_n_0 ));
FDRE \s_output_led_r_stb_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\s_output_led_r_stb[0]_i_1_n_0 ),
.Q(\PWM_VAL_reg[7]_0 ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h2000000000000000))
\s_output_rs232_tx[7]_i_1
(.I0(write_output[0]),
.I1(\s_output_rs232_tx[7]_i_2_n_0 ),
.I2(\state_reg_n_0_[2] ),
.I3(write_output[1]),
.I4(\state_reg_n_0_[0] ),
.I5(\state_reg_n_0_[1] ),
.O(\s_output_rs232_tx_reg[7]_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\s_output_rs232_tx[7]_i_2
(.I0(\s_output_rs232_tx[7]_i_3_n_0 ),
.I1(\s_output_rs232_tx[7]_i_4_n_0 ),
.I2(\s_output_rs232_tx[7]_i_5_n_0 ),
.I3(\s_output_rs232_tx[7]_i_6_n_0 ),
.I4(\s_output_rs232_tx[7]_i_7_n_0 ),
.O(\s_output_rs232_tx[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_output_rs232_tx[7]_i_3
(.I0(write_output[9]),
.I1(write_output[11]),
.I2(write_output[15]),
.I3(write_output[26]),
.I4(write_output[12]),
.I5(write_output[18]),
.O(\s_output_rs232_tx[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_output_rs232_tx[7]_i_4
(.I0(write_output[22]),
.I1(write_output[25]),
.I2(write_output[8]),
.I3(write_output[3]),
.I4(write_output[27]),
.I5(write_output[31]),
.O(\s_output_rs232_tx[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_output_rs232_tx[7]_i_5
(.I0(write_output[23]),
.I1(write_output[24]),
.I2(write_output[13]),
.I3(write_output[5]),
.I4(write_output[10]),
.I5(write_output[20]),
.O(\s_output_rs232_tx[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_output_rs232_tx[7]_i_6
(.I0(write_output[2]),
.I1(write_output[7]),
.I2(write_output[16]),
.I3(write_output[6]),
.I4(write_output[4]),
.I5(write_output[19]),
.O(\s_output_rs232_tx[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_output_rs232_tx[7]_i_7
(.I0(write_output[28]),
.I1(write_output[30]),
.I2(write_output[14]),
.I3(write_output[21]),
.I4(write_output[29]),
.I5(write_output[17]),
.O(\s_output_rs232_tx[7]_i_7_n_0 ));
FDRE \s_output_rs232_tx_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx_reg[7]_0 ),
.D(write_value[0]),
.Q(output_rs232_tx[0]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx_reg[7]_0 ),
.D(write_value[1]),
.Q(output_rs232_tx[1]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx_reg[7]_0 ),
.D(write_value[2]),
.Q(output_rs232_tx[2]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx_reg[7]_0 ),
.D(write_value[3]),
.Q(output_rs232_tx[3]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx_reg[7]_0 ),
.D(write_value[4]),
.Q(output_rs232_tx[4]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx_reg[7]_0 ),
.D(write_value[5]),
.Q(output_rs232_tx[5]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx_reg[7]_0 ),
.D(write_value[6]),
.Q(output_rs232_tx[6]),
.R(1'b0));
FDRE \s_output_rs232_tx_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_tx_reg[7]_0 ),
.D(write_value[7]),
.Q(output_rs232_tx[7]),
.R(1'b0));
FDRE \s_output_rs232_tx_stb_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_IN1_ACK_reg),
.Q(IN1_STB),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFF5F5FF0F05CDC))
\state[0]_i_1
(.I0(\state[0]_i_2_n_0 ),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.I3(\state[2]_i_3_n_0 ),
.I4(\state_reg_n_0_[2] ),
.I5(\state[2]_i_4_n_0 ),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF7F5FDF7FFFFF7FF))
\state[0]_i_2
(.I0(\state_reg_n_0_[1] ),
.I1(opcode_2[0]),
.I2(opcode_2[4]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(opcode_2[1]),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFBFBFCCCCBCFC))
\state[1]_i_1
(.I0(\state[1]_i_2_n_0 ),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.I3(\state[2]_i_3_n_0 ),
.I4(\state_reg_n_0_[2] ),
.I5(\state[2]_i_4_n_0 ),
.O(\state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0400))
\state[1]_i_2
(.I0(opcode_2[2]),
.I1(opcode_2[3]),
.I2(opcode_2[4]),
.I3(opcode_2[1]),
.O(\state[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00008080FFFF8000))
\state[2]_i_1
(.I0(\state[2]_i_2_n_0 ),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.I3(\state[2]_i_3_n_0 ),
.I4(\state_reg_n_0_[2] ),
.I5(\state[2]_i_4_n_0 ),
.O(\state[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00240020))
\state[2]_i_2
(.I0(opcode_2[1]),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.I3(opcode_2[4]),
.I4(opcode_2[0]),
.O(\state[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000008FBA0FA0))
\state[2]_i_3
(.I0(opcode_2[1]),
.I1(\program_counter[15]_i_7_n_0 ),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.I4(opcode_2[0]),
.I5(opcode_2[4]),
.O(\state[2]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0888AA88))
\state[2]_i_4
(.I0(\state_reg_n_0_[2] ),
.I1(\result[31]_i_3_n_0 ),
.I2(\state_reg_n_0_[1] ),
.I3(\state_reg_n_0_[0] ),
.I4(\state[2]_i_5_n_0 ),
.O(\state[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF004747))
\state[2]_i_5
(.I0(E),
.I1(write_output[1]),
.I2(\PWM_VAL_reg[7]_0 ),
.I3(\state[2]_i_6_n_0 ),
.I4(write_output[0]),
.I5(\s_output_rs232_tx[7]_i_2_n_0 ),
.O(\state[2]_i_5_n_0 ));
LUT4 #(
.INIT(16'h707F))
\state[2]_i_6
(.I0(IN1_STB),
.I1(IN1_ACK),
.I2(write_output[1]),
.I3(\PWM_VAL_reg[7] ),
.O(\state[2]_i_6_n_0 ));
FDSE \state_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\state_reg_n_0_[0] ),
.S(INTERNAL_RST_reg));
FDRE \state_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(\state_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \state_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[2]_i_1_n_0 ),
.Q(\state_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE write_enable_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\result[31]_i_1_n_0 ),
.Q(write_enable_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000200000))
\write_output[31]_i_1
(.I0(opcode_2[1]),
.I1(opcode_2[2]),
.I2(\address_z_3[3]_i_1_n_0 ),
.I3(opcode_2[4]),
.I4(opcode_2[3]),
.I5(opcode_2[0]),
.O(out0));
FDRE \write_output_reg[0]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[0]_i_1_n_0 ),
.Q(write_output[0]),
.R(1'b0));
FDRE \write_output_reg[10]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[10]_i_1_n_0 ),
.Q(write_output[10]),
.R(1'b0));
FDRE \write_output_reg[11]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[11]_i_1_n_0 ),
.Q(write_output[11]),
.R(1'b0));
FDRE \write_output_reg[12]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[12]_i_1_n_0 ),
.Q(write_output[12]),
.R(1'b0));
FDRE \write_output_reg[13]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[13]_i_1_n_0 ),
.Q(write_output[13]),
.R(1'b0));
FDRE \write_output_reg[14]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[14]_i_1_n_0 ),
.Q(write_output[14]),
.R(1'b0));
FDRE \write_output_reg[15]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[15]_i_1_n_0 ),
.Q(write_output[15]),
.R(1'b0));
FDRE \write_output_reg[16]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[16]_i_1_n_0 ),
.Q(write_output[16]),
.R(1'b0));
FDRE \write_output_reg[17]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[17]_i_1_n_0 ),
.Q(write_output[17]),
.R(1'b0));
FDRE \write_output_reg[18]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[18]_i_1_n_0 ),
.Q(write_output[18]),
.R(1'b0));
FDRE \write_output_reg[19]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[19]_i_1_n_0 ),
.Q(write_output[19]),
.R(1'b0));
FDRE \write_output_reg[1]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[1]_i_1_n_0 ),
.Q(write_output[1]),
.R(1'b0));
FDRE \write_output_reg[20]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[20]_i_1_n_0 ),
.Q(write_output[20]),
.R(1'b0));
FDRE \write_output_reg[21]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[21]_i_1_n_0 ),
.Q(write_output[21]),
.R(1'b0));
FDRE \write_output_reg[22]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[22]_i_1_n_0 ),
.Q(write_output[22]),
.R(1'b0));
FDRE \write_output_reg[23]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[23]_i_1_n_0 ),
.Q(write_output[23]),
.R(1'b0));
FDRE \write_output_reg[24]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[24]_i_1_n_0 ),
.Q(write_output[24]),
.R(1'b0));
FDRE \write_output_reg[25]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[25]_i_1_n_0 ),
.Q(write_output[25]),
.R(1'b0));
FDRE \write_output_reg[26]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[26]_i_1_n_0 ),
.Q(write_output[26]),
.R(1'b0));
FDRE \write_output_reg[27]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[27]_i_1_n_0 ),
.Q(write_output[27]),
.R(1'b0));
FDRE \write_output_reg[28]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[28]_i_1_n_0 ),
.Q(write_output[28]),
.R(1'b0));
FDRE \write_output_reg[29]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[29]_i_1_n_0 ),
.Q(write_output[29]),
.R(1'b0));
FDRE \write_output_reg[2]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[2]_i_1_n_0 ),
.Q(write_output[2]),
.R(1'b0));
FDRE \write_output_reg[30]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[30]_i_1_n_0 ),
.Q(write_output[30]),
.R(1'b0));
FDRE \write_output_reg[31]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[31]_i_2_n_0 ),
.Q(write_output[31]),
.R(1'b0));
FDRE \write_output_reg[3]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[3]_i_1_n_0 ),
.Q(write_output[3]),
.R(1'b0));
FDRE \write_output_reg[4]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[4]_i_1_n_0 ),
.Q(write_output[4]),
.R(1'b0));
FDRE \write_output_reg[5]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[5]_i_1_n_0 ),
.Q(write_output[5]),
.R(1'b0));
FDRE \write_output_reg[6]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[6]_i_1_n_0 ),
.Q(write_output[6]),
.R(1'b0));
FDRE \write_output_reg[7]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[7]_i_1_n_0 ),
.Q(write_output[7]),
.R(1'b0));
FDRE \write_output_reg[8]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[8]_i_1_n_0 ),
.Q(write_output[8]),
.R(1'b0));
FDRE \write_output_reg[9]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[9]_i_1_n_0 ),
.Q(write_output[9]),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
\write_value[0]_i_1
(.I0(result[0]),
.I1(operand_b1),
.I2(register_b[0]),
.O(store_data[0]));
LUT3 #(
.INIT(8'hB8))
\write_value[1]_i_1
(.I0(result[1]),
.I1(operand_b1),
.I2(register_b[1]),
.O(store_data[1]));
LUT6 #(
.INIT(64'h2002000000002002))
\write_value[1]_i_2
(.I0(write_enable_reg_n_0),
.I1(\write_value[7]_i_2_n_0 ),
.I2(address_z_3[0]),
.I3(address_b_2[0]),
.I4(address_z_3[3]),
.I5(address_b_2[3]),
.O(operand_b1));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[2]_i_1
(.I0(result[2]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[2]),
.O(store_data[2]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[3]_i_1
(.I0(result[3]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[3]),
.O(store_data[3]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[4]_i_1
(.I0(result[4]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[4]),
.O(store_data[4]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[5]_i_1
(.I0(result[5]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[5]),
.O(store_data[5]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[6]_i_1
(.I0(result[6]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[6]),
.O(store_data[6]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[7]_i_1
(.I0(result[7]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[7]),
.O(store_data[7]));
LUT4 #(
.INIT(16'h6FF6))
\write_value[7]_i_2
(.I0(address_z_3[1]),
.I1(address_b_2[1]),
.I2(address_z_3[2]),
.I3(address_b_2[2]),
.O(\write_value[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\write_value[7]_i_3
(.I0(address_z_3[0]),
.I1(address_b_2[0]),
.I2(address_z_3[3]),
.I3(address_b_2[3]),
.O(\write_value[7]_i_3_n_0 ));
FDRE \write_value_reg[0]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[0]),
.Q(write_value[0]),
.R(1'b0));
FDRE \write_value_reg[1]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[1]),
.Q(write_value[1]),
.R(1'b0));
FDRE \write_value_reg[2]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[2]),
.Q(write_value[2]),
.R(1'b0));
FDRE \write_value_reg[3]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[3]),
.Q(write_value[3]),
.R(1'b0));
FDRE \write_value_reg[4]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[4]),
.Q(write_value[4]),
.R(1'b0));
FDRE \write_value_reg[5]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[5]),
.Q(write_value[5]),
.R(1'b0));
FDRE \write_value_reg[6]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[6]),
.Q(write_value[6]),
.R(1'b0));
FDRE \write_value_reg[7]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[7]),
.Q(write_value[7]),
.R(1'b0));
endmodule
module pwm_audio
(JC_IBUF,
INTERNAL_RST_reg,
ETH_CLK_OBUF);
output [0:0]JC_IBUF;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
wire \COUNT[10]_i_2_n_0 ;
wire \COUNT[10]_i_4_n_0 ;
wire \COUNT[10]_i_5_n_0 ;
wire \COUNT[10]_i_6_n_0 ;
wire \COUNT[9]_i_2_n_0 ;
wire [10:0]COUNT_reg__0;
wire ETH_CLK_OBUF;
wire INTERNAL_RST_reg;
wire [0:0]JC_IBUF;
wire STATE;
wire STATE_i_1_n_0;
wire STATE_reg_n_0;
wire S_DATA_IN_ACK_i_1_n_0;
wire [10:0]p_0_in;
(* SOFT_HLUTNM = "soft_lutpair201" *)
LUT1 #(
.INIT(2'h1))
\COUNT[0]_i_1__4
(.I0(COUNT_reg__0[0]),
.O(p_0_in[0]));
LUT2 #(
.INIT(4'h2))
\COUNT[10]_i_1
(.I0(JC_IBUF),
.I1(STATE_reg_n_0),
.O(STATE));
LUT2 #(
.INIT(4'h2))
\COUNT[10]_i_2
(.I0(STATE_reg_n_0),
.I1(\COUNT[10]_i_4_n_0 ),
.O(\COUNT[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'h6A))
\COUNT[10]_i_3
(.I0(COUNT_reg__0[10]),
.I1(\COUNT[10]_i_5_n_0 ),
.I2(COUNT_reg__0[9]),
.O(p_0_in[10]));
LUT6 #(
.INIT(64'h0000800000000000))
\COUNT[10]_i_4
(.I0(COUNT_reg__0[2]),
.I1(COUNT_reg__0[3]),
.I2(COUNT_reg__0[6]),
.I3(COUNT_reg__0[5]),
.I4(COUNT_reg__0[7]),
.I5(\COUNT[10]_i_6_n_0 ),
.O(\COUNT[10]_i_4_n_0 ));
LUT5 #(
.INIT(32'h80000000))
\COUNT[10]_i_5
(.I0(COUNT_reg__0[8]),
.I1(COUNT_reg__0[7]),
.I2(\COUNT[9]_i_2_n_0 ),
.I3(COUNT_reg__0[6]),
.I4(COUNT_reg__0[5]),
.O(\COUNT[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\COUNT[10]_i_6
(.I0(COUNT_reg__0[9]),
.I1(COUNT_reg__0[10]),
.I2(COUNT_reg__0[4]),
.I3(COUNT_reg__0[8]),
.I4(COUNT_reg__0[0]),
.I5(COUNT_reg__0[1]),
.O(\COUNT[10]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair201" *)
LUT2 #(
.INIT(4'h6))
\COUNT[1]_i_1__4
(.I0(COUNT_reg__0[0]),
.I1(COUNT_reg__0[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair200" *)
LUT3 #(
.INIT(8'h78))
\COUNT[2]_i_1__3
(.I0(COUNT_reg__0[0]),
.I1(COUNT_reg__0[1]),
.I2(COUNT_reg__0[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair200" *)
LUT4 #(
.INIT(16'h6AAA))
\COUNT[3]_i_1__2
(.I0(COUNT_reg__0[3]),
.I1(COUNT_reg__0[0]),
.I2(COUNT_reg__0[1]),
.I3(COUNT_reg__0[2]),
.O(p_0_in[3]));
LUT5 #(
.INIT(32'h7FFF8000))
\COUNT[4]_i_1__2
(.I0(COUNT_reg__0[1]),
.I1(COUNT_reg__0[0]),
.I2(COUNT_reg__0[3]),
.I3(COUNT_reg__0[2]),
.I4(COUNT_reg__0[4]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\COUNT[5]_i_1__2
(.I0(COUNT_reg__0[5]),
.I1(COUNT_reg__0[1]),
.I2(COUNT_reg__0[0]),
.I3(COUNT_reg__0[3]),
.I4(COUNT_reg__0[2]),
.I5(COUNT_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair199" *)
LUT3 #(
.INIT(8'h6A))
\COUNT[6]_i_1__2
(.I0(COUNT_reg__0[6]),
.I1(\COUNT[9]_i_2_n_0 ),
.I2(COUNT_reg__0[5]),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair199" *)
LUT4 #(
.INIT(16'h6AAA))
\COUNT[7]_i_1__2
(.I0(COUNT_reg__0[7]),
.I1(COUNT_reg__0[5]),
.I2(COUNT_reg__0[6]),
.I3(\COUNT[9]_i_2_n_0 ),
.O(p_0_in[7]));
LUT5 #(
.INIT(32'h6AAAAAAA))
\COUNT[8]_i_1
(.I0(COUNT_reg__0[8]),
.I1(COUNT_reg__0[7]),
.I2(\COUNT[9]_i_2_n_0 ),
.I3(COUNT_reg__0[6]),
.I4(COUNT_reg__0[5]),
.O(p_0_in[8]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\COUNT[9]_i_1
(.I0(COUNT_reg__0[9]),
.I1(COUNT_reg__0[5]),
.I2(COUNT_reg__0[6]),
.I3(\COUNT[9]_i_2_n_0 ),
.I4(COUNT_reg__0[7]),
.I5(COUNT_reg__0[8]),
.O(p_0_in[9]));
LUT5 #(
.INIT(32'h80000000))
\COUNT[9]_i_2
(.I0(COUNT_reg__0[4]),
.I1(COUNT_reg__0[2]),
.I2(COUNT_reg__0[3]),
.I3(COUNT_reg__0[0]),
.I4(COUNT_reg__0[1]),
.O(\COUNT[9]_i_2_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[0]),
.Q(COUNT_reg__0[0]),
.R(STATE));
FDRE \COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[10]),
.Q(COUNT_reg__0[10]),
.R(STATE));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[1]),
.Q(COUNT_reg__0[1]),
.R(STATE));
FDRE \COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[2]),
.Q(COUNT_reg__0[2]),
.R(STATE));
FDRE \COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[3]),
.Q(COUNT_reg__0[3]),
.R(STATE));
FDRE \COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[4]),
.Q(COUNT_reg__0[4]),
.R(STATE));
FDRE \COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[5]),
.Q(COUNT_reg__0[5]),
.R(STATE));
FDRE \COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[6]),
.Q(COUNT_reg__0[6]),
.R(STATE));
FDRE \COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[7]),
.Q(COUNT_reg__0[7]),
.R(STATE));
FDRE \COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[8]),
.Q(COUNT_reg__0[8]),
.R(STATE));
FDRE \COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[9]),
.Q(COUNT_reg__0[9]),
.R(STATE));
LUT3 #(
.INIT(8'h4E))
STATE_i_1
(.I0(STATE_reg_n_0),
.I1(JC_IBUF),
.I2(\COUNT[10]_i_4_n_0 ),
.O(STATE_i_1_n_0));
FDRE STATE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(STATE_i_1_n_0),
.Q(STATE_reg_n_0),
.R(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h09))
S_DATA_IN_ACK_i_1
(.I0(STATE_reg_n_0),
.I1(JC_IBUF),
.I2(INTERNAL_RST_reg),
.O(S_DATA_IN_ACK_i_1_n_0));
FDRE S_DATA_IN_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_DATA_IN_ACK_i_1_n_0),
.Q(JC_IBUF),
.R(1'b0));
endmodule
module rmii_ethernet
(TXEN_OBUF,
TXD_OBUF,
ETH_CLK_OBUF,
RXDV_IBUF,
RXER_IBUF,
INTERNAL_RST_reg,
D);
output TXEN_OBUF;
output [1:0]TXD_OBUF;
input ETH_CLK_OBUF;
input RXDV_IBUF;
input RXER_IBUF;
input INTERNAL_RST_reg;
input [1:0]D;
wire DONE;
wire DONE_DEL;
wire DONE_SYNC;
wire DONE_i_1_n_0;
wire ETH_CLK_OBUF;
wire GO;
wire GO_DEL;
wire GO_SYNC;
wire GO_i_1_n_0;
wire INTERNAL_RST_reg;
wire NEXTCRC32_D80177_out;
wire NEXTCRC32_D80181_out;
wire NEXTCRC32_D80189_out;
wire NEXTCRC32_D80195_out;
wire NEXTCRC32_D80203_out;
wire NEXTCRC32_D80217_out;
wire NEXTCRC32_D8070_out;
wire NEXTCRC32_D8074_out;
wire \PREAMBLE_COUNT[0]_i_1_n_0 ;
wire \PREAMBLE_COUNT[1]_i_1_n_0 ;
wire \PREAMBLE_COUNT[2]_i_1_n_0 ;
wire \PREAMBLE_COUNT[3]_i_1_n_0 ;
wire \PREAMBLE_COUNT[4]_i_1_n_0 ;
wire \PREAMBLE_COUNT[4]_i_2_n_0 ;
wire \PREAMBLE_COUNT[4]_i_3_n_0 ;
wire \PREAMBLE_COUNT[4]_i_4_n_0 ;
wire \PREAMBLE_COUNT_reg_n_0_[0] ;
wire \PREAMBLE_COUNT_reg_n_0_[1] ;
wire \PREAMBLE_COUNT_reg_n_0_[2] ;
wire \PREAMBLE_COUNT_reg_n_0_[3] ;
wire \PREAMBLE_COUNT_reg_n_0_[4] ;
wire S_TX_ACK_i_1_n_0;
wire S_TX_ACK_reg_n_0;
wire \TXD[0]_i_10_n_0 ;
wire \TXD[0]_i_11_n_0 ;
wire \TXD[0]_i_1_n_0 ;
wire \TXD[0]_i_2_n_0 ;
wire \TXD[0]_i_3_n_0 ;
wire \TXD[0]_i_6_n_0 ;
wire \TXD[0]_i_7_n_0 ;
wire \TXD[0]_i_8_n_0 ;
wire \TXD[0]_i_9_n_0 ;
wire \TXD[1]_i_10_n_0 ;
wire \TXD[1]_i_11_n_0 ;
wire \TXD[1]_i_12_n_0 ;
wire \TXD[1]_i_1_n_0 ;
wire \TXD[1]_i_2_n_0 ;
wire \TXD[1]_i_3_n_0 ;
wire \TXD[1]_i_4_n_0 ;
wire \TXD[1]_i_7_n_0 ;
wire \TXD[1]_i_8_n_0 ;
wire \TXD[1]_i_9_n_0 ;
wire [1:0]TXD_OBUF;
wire \TXD_reg[0]_i_4_n_0 ;
wire \TXD_reg[0]_i_5_n_0 ;
wire \TXD_reg[1]_i_5_n_0 ;
wire \TXD_reg[1]_i_6_n_0 ;
wire TXEN_OBUF;
wire TXEN_i_1_n_0;
wire \TX_CRC[0]_i_1_n_0 ;
wire \TX_CRC[0]_i_2_n_0 ;
wire \TX_CRC[10]_i_3_n_0 ;
wire \TX_CRC[10]_i_4_n_0 ;
wire \TX_CRC[10]_i_5_n_0 ;
wire \TX_CRC[11]_i_1_n_0 ;
wire \TX_CRC[11]_i_2_n_0 ;
wire \TX_CRC[11]_i_3_n_0 ;
wire \TX_CRC[11]_i_4_n_0 ;
wire \TX_CRC[12]_i_2_n_0 ;
wire \TX_CRC[12]_i_3_n_0 ;
wire \TX_CRC[12]_i_4_n_0 ;
wire \TX_CRC[12]_i_5_n_0 ;
wire \TX_CRC[12]_i_6_n_0 ;
wire \TX_CRC[12]_i_7_n_0 ;
wire \TX_CRC[12]_i_8_n_0 ;
wire \TX_CRC[13]_i_3_n_0 ;
wire \TX_CRC[13]_i_4_n_0 ;
wire \TX_CRC[14]_i_2_n_0 ;
wire \TX_CRC[14]_i_3_n_0 ;
wire \TX_CRC[14]_i_4_n_0 ;
wire \TX_CRC[14]_i_5_n_0 ;
wire \TX_CRC[15]_i_1_n_0 ;
wire \TX_CRC[15]_i_2_n_0 ;
wire \TX_CRC[15]_i_3_n_0 ;
wire \TX_CRC[15]_i_4_n_0 ;
wire \TX_CRC[15]_i_5_n_0 ;
wire \TX_CRC[16]_i_1_n_0 ;
wire \TX_CRC[16]_i_2_n_0 ;
wire \TX_CRC[16]_i_3_n_0 ;
wire \TX_CRC[17]_i_3_n_0 ;
wire \TX_CRC[17]_i_5_n_0 ;
wire \TX_CRC[18]_i_2_n_0 ;
wire \TX_CRC[18]_i_3_n_0 ;
wire \TX_CRC[18]_i_4_n_0 ;
wire \TX_CRC[19]_i_1_n_0 ;
wire \TX_CRC[19]_i_2_n_0 ;
wire \TX_CRC[1]_i_2_n_0 ;
wire \TX_CRC[20]_i_1_n_0 ;
wire \TX_CRC[21]_i_1_n_0 ;
wire \TX_CRC[22]_i_1_n_0 ;
wire \TX_CRC[23]_i_1_n_0 ;
wire \TX_CRC[23]_i_2_n_0 ;
wire \TX_CRC[23]_i_3_n_0 ;
wire \TX_CRC[24]_i_3_n_0 ;
wire \TX_CRC[24]_i_4_n_0 ;
wire \TX_CRC[25]_i_2_n_0 ;
wire \TX_CRC[25]_i_3_n_0 ;
wire \TX_CRC[26]_i_1_n_0 ;
wire \TX_CRC[26]_i_2_n_0 ;
wire \TX_CRC[26]_i_3_n_0 ;
wire \TX_CRC[26]_i_4_n_0 ;
wire \TX_CRC[27]_i_1_n_0 ;
wire \TX_CRC[27]_i_2_n_0 ;
wire \TX_CRC[27]_i_3_n_0 ;
wire \TX_CRC[27]_i_4_n_0 ;
wire \TX_CRC[28]_i_1_n_0 ;
wire \TX_CRC[28]_i_2_n_0 ;
wire \TX_CRC[28]_i_3_n_0 ;
wire \TX_CRC[29]_i_2_n_0 ;
wire \TX_CRC[29]_i_3_n_0 ;
wire \TX_CRC[29]_i_4_n_0 ;
wire \TX_CRC[29]_i_5_n_0 ;
wire \TX_CRC[2]_i_1_n_0 ;
wire \TX_CRC[2]_i_2_n_0 ;
wire \TX_CRC[2]_i_3_n_0 ;
wire \TX_CRC[2]_i_4_n_0 ;
wire \TX_CRC[30]_i_2_n_0 ;
wire \TX_CRC[30]_i_3_n_0 ;
wire \TX_CRC[31]_i_1_n_0 ;
wire \TX_CRC[31]_i_2_n_0 ;
wire \TX_CRC[31]_i_3_n_0 ;
wire \TX_CRC[3]_i_3_n_0 ;
wire \TX_CRC[3]_i_4_n_0 ;
wire \TX_CRC[4]_i_2_n_0 ;
wire \TX_CRC[4]_i_3_n_0 ;
wire \TX_CRC[4]_i_4_n_0 ;
wire \TX_CRC[4]_i_5_n_0 ;
wire \TX_CRC[5]_i_4_n_0 ;
wire \TX_CRC[5]_i_5_n_0 ;
wire \TX_CRC[5]_i_6_n_0 ;
wire \TX_CRC[5]_i_7_n_0 ;
wire \TX_CRC[5]_i_8_n_0 ;
wire \TX_CRC[5]_i_9_n_0 ;
wire \TX_CRC[6]_i_2_n_0 ;
wire \TX_CRC[6]_i_3_n_0 ;
wire \TX_CRC[6]_i_4_n_0 ;
wire \TX_CRC[6]_i_5_n_0 ;
wire \TX_CRC[6]_i_6_n_0 ;
wire \TX_CRC[7]_i_1_n_0 ;
wire \TX_CRC[7]_i_2_n_0 ;
wire \TX_CRC[7]_i_3_n_0 ;
wire \TX_CRC[7]_i_4_n_0 ;
wire \TX_CRC[8]_i_1_n_0 ;
wire \TX_CRC[9]_i_1_n_0 ;
wire \TX_CRC[9]_i_2_n_0 ;
wire \TX_CRC[9]_i_3_n_0 ;
wire \TX_CRC[9]_i_4_n_0 ;
wire \TX_CRC_reg[10]_i_1_n_0 ;
wire \TX_CRC_reg[12]_i_1_n_0 ;
wire \TX_CRC_reg[13]_i_1_n_0 ;
wire \TX_CRC_reg[14]_i_1_n_0 ;
wire \TX_CRC_reg[17]_i_1_n_0 ;
wire \TX_CRC_reg[18]_i_1_n_0 ;
wire \TX_CRC_reg[1]_i_1_n_0 ;
wire \TX_CRC_reg[24]_i_1_n_0 ;
wire \TX_CRC_reg[25]_i_1_n_0 ;
wire \TX_CRC_reg[29]_i_1_n_0 ;
wire \TX_CRC_reg[30]_i_1_n_0 ;
wire \TX_CRC_reg[3]_i_1_n_0 ;
wire \TX_CRC_reg[4]_i_1_n_0 ;
wire \TX_CRC_reg[5]_i_1_n_0 ;
wire \TX_CRC_reg[6]_i_1_n_0 ;
wire \TX_CRC_reg_n_0_[0] ;
wire \TX_CRC_reg_n_0_[10] ;
wire \TX_CRC_reg_n_0_[11] ;
wire \TX_CRC_reg_n_0_[12] ;
wire \TX_CRC_reg_n_0_[13] ;
wire \TX_CRC_reg_n_0_[14] ;
wire \TX_CRC_reg_n_0_[15] ;
wire \TX_CRC_reg_n_0_[16] ;
wire \TX_CRC_reg_n_0_[17] ;
wire \TX_CRC_reg_n_0_[18] ;
wire \TX_CRC_reg_n_0_[19] ;
wire \TX_CRC_reg_n_0_[20] ;
wire \TX_CRC_reg_n_0_[21] ;
wire \TX_CRC_reg_n_0_[22] ;
wire \TX_CRC_reg_n_0_[23] ;
wire \TX_CRC_reg_n_0_[8] ;
wire \TX_CRC_reg_n_0_[9] ;
wire [10:1]TX_IN_COUNT;
wire \TX_IN_COUNT[10]_i_1_n_0 ;
wire \TX_IN_COUNT[10]_i_2_n_0 ;
wire \TX_IN_COUNT[10]_i_3_n_0 ;
wire \TX_IN_COUNT[10]_i_4_n_0 ;
wire \TX_IN_COUNT[1]_i_1_n_0 ;
wire \TX_IN_COUNT[2]_i_1_n_0 ;
wire \TX_IN_COUNT[3]_i_1_n_0 ;
wire \TX_IN_COUNT[4]_i_1_n_0 ;
wire \TX_IN_COUNT[5]_i_1_n_0 ;
wire \TX_IN_COUNT[6]_i_1_n_0 ;
wire \TX_IN_COUNT[7]_i_1_n_0 ;
wire \TX_IN_COUNT[8]_i_1_n_0 ;
wire \TX_IN_COUNT[9]_i_1_n_0 ;
wire TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9;
wire TX_MEMORY_reg_n_59;
wire TX_MEMORY_reg_n_67;
wire [0:0]TX_OUT_COUNT0_in;
wire \TX_OUT_COUNT[10]_i_1_n_0 ;
wire \TX_OUT_COUNT[10]_i_2_n_0 ;
wire \TX_OUT_COUNT[10]_i_3_n_0 ;
wire \TX_OUT_COUNT[10]_i_4_n_0 ;
wire \TX_OUT_COUNT[10]_i_5_n_0 ;
wire \TX_OUT_COUNT[10]_i_6_n_0 ;
wire \TX_OUT_COUNT[10]_i_7_n_0 ;
wire \TX_OUT_COUNT[10]_i_8_n_0 ;
wire \TX_OUT_COUNT[1]_i_1_n_0 ;
wire \TX_OUT_COUNT[2]_i_1_n_0 ;
wire \TX_OUT_COUNT[3]_i_1_n_0 ;
wire \TX_OUT_COUNT[4]_i_1_n_0 ;
wire \TX_OUT_COUNT[5]_i_1_n_0 ;
wire \TX_OUT_COUNT[6]_i_1_n_0 ;
wire \TX_OUT_COUNT[7]_i_1_n_0 ;
wire \TX_OUT_COUNT[8]_i_1_n_0 ;
wire \TX_OUT_COUNT[8]_i_2_n_0 ;
wire \TX_OUT_COUNT[9]_i_1_n_0 ;
wire \TX_OUT_COUNT_reg_n_0_[0] ;
wire \TX_OUT_COUNT_reg_n_0_[10] ;
wire \TX_OUT_COUNT_reg_n_0_[1] ;
wire \TX_OUT_COUNT_reg_n_0_[2] ;
wire \TX_OUT_COUNT_reg_n_0_[3] ;
wire \TX_OUT_COUNT_reg_n_0_[4] ;
wire \TX_OUT_COUNT_reg_n_0_[5] ;
wire \TX_OUT_COUNT_reg_n_0_[6] ;
wire \TX_OUT_COUNT_reg_n_0_[7] ;
wire \TX_OUT_COUNT_reg_n_0_[8] ;
wire \TX_OUT_COUNT_reg_n_0_[9] ;
wire \TX_PACKET_STATE[0]_i_1_n_0 ;
wire \TX_PACKET_STATE[1]_i_10_n_0 ;
wire \TX_PACKET_STATE[1]_i_11_n_0 ;
wire \TX_PACKET_STATE[1]_i_12_n_0 ;
wire \TX_PACKET_STATE[1]_i_13_n_0 ;
wire \TX_PACKET_STATE[1]_i_1_n_0 ;
wire \TX_PACKET_STATE[1]_i_4_n_0 ;
wire \TX_PACKET_STATE[1]_i_5_n_0 ;
wire \TX_PACKET_STATE[1]_i_6_n_0 ;
wire \TX_PACKET_STATE[1]_i_7_n_0 ;
wire \TX_PACKET_STATE[1]_i_8_n_0 ;
wire \TX_PACKET_STATE[1]_i_9_n_0 ;
wire \TX_PACKET_STATE_reg[1]_i_2_n_2 ;
wire \TX_PACKET_STATE_reg[1]_i_3_n_0 ;
wire \TX_PACKET_STATE_reg_n_0_[0] ;
wire \TX_PACKET_STATE_reg_n_0_[1] ;
wire \TX_PHY_STATE[0]_i_1_n_0 ;
wire \TX_PHY_STATE[1]_i_1_n_0 ;
wire \TX_PHY_STATE[2]_i_1_n_0 ;
wire \TX_PHY_STATE[2]_i_2_n_0 ;
wire \TX_PHY_STATE[2]_i_3_n_0 ;
wire \TX_PHY_STATE[2]_i_4_n_0 ;
wire \TX_PHY_STATE[3]_i_1_n_0 ;
wire \TX_PHY_STATE[3]_i_2_n_0 ;
wire \TX_PHY_STATE[3]_i_3_n_0 ;
wire \TX_PHY_STATE[3]_i_4_n_0 ;
wire \TX_PHY_STATE[3]_i_5_n_0 ;
wire \TX_PHY_STATE[4]_i_1_n_0 ;
wire \TX_PHY_STATE[4]_i_2_n_0 ;
wire \TX_PHY_STATE[4]_i_3_n_0 ;
wire \TX_PHY_STATE[4]_i_4_n_0 ;
wire \TX_PHY_STATE_reg_n_0_[0] ;
wire \TX_PHY_STATE_reg_n_0_[1] ;
wire \TX_PHY_STATE_reg_n_0_[2] ;
wire \TX_PHY_STATE_reg_n_0_[3] ;
wire \TX_PHY_STATE_reg_n_0_[4] ;
wire [10:0]TX_READ_ADDRESS;
wire [10:1]TX_READ_ADDRESS0;
wire \TX_READ_ADDRESS_rep[0]_i_1_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_1_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_2_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_4_n_0 ;
wire TX_WRITE;
wire [10:0]TX_WRITE_ADDRESS;
wire \TX_WRITE_ADDRESS[0]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_2_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_3_n_0 ;
wire \TX_WRITE_ADDRESS[1]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[2]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[3]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[4]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[5]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[5]_i_2_n_0 ;
wire \TX_WRITE_ADDRESS[6]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[7]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[8]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[9]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[9]_i_2_n_0 ;
wire [10:0]TX_WRITE_ADDRESS_DEL;
wire TX_WRITE_i_1_n_0;
wire p_0_in167_in;
wire p_0_in66_in;
wire [1:0]p_16_in;
wire [1:0]p_17_in;
wire [1:0]p_18_in;
wire p_1_in126_in;
wire p_1_in128_in;
wire p_1_in130_in;
wire p_1_in132_in;
wire p_1_in133_in;
wire p_1_in135_in;
wire p_1_in136_in;
wire p_202_in;
wire p_206_in;
wire [1:0]p_20_in;
wire p_214_in;
wire p_216_in;
wire [1:0]p_21_in;
wire [1:0]p_22_in;
wire [7:0]slv1_out;
wire NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED;
wire NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED;
wire NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED;
wire NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED;
wire NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED;
wire [31:0]NLW_TX_MEMORY_reg_DOADO_UNCONNECTED;
wire [31:16]NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED;
wire [3:0]NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED;
wire [3:0]NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED ;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED ;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED ;
FDRE DONE_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE),
.Q(DONE_DEL),
.R(1'b0));
FDRE DONE_SYNC_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE_DEL),
.Q(DONE_SYNC),
.R(1'b0));
LUT6 #(
.INIT(64'hBFFFFFFF80000000))
DONE_i_1
(.I0(GO_SYNC),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[1] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(DONE),
.O(DONE_i_1_n_0));
FDRE DONE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE_i_1_n_0),
.Q(DONE),
.R(INTERNAL_RST_reg));
FDRE GO_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO),
.Q(GO_DEL),
.R(1'b0));
FDRE GO_SYNC_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO_DEL),
.Q(GO_SYNC),
.R(1'b0));
LUT4 #(
.INIT(16'hF704))
GO_i_1
(.I0(DONE_SYNC),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(GO),
.O(GO_i_1_n_0));
FDRE GO_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO_i_1_n_0),
.Q(GO),
.R(INTERNAL_RST_reg));
LUT1 #(
.INIT(2'h1))
\PREAMBLE_COUNT[0]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
.O(\PREAMBLE_COUNT[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT2 #(
.INIT(4'h9))
\PREAMBLE_COUNT[1]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.O(\PREAMBLE_COUNT[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFDFDFDDD00000020))
\PREAMBLE_COUNT[2]_i_1
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I5(\PREAMBLE_COUNT_reg_n_0_[2] ),
.O(\PREAMBLE_COUNT[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT4 #(
.INIT(16'hFE01))
\PREAMBLE_COUNT[3]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[2] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[3] ),
.O(\PREAMBLE_COUNT[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\PREAMBLE_COUNT[4]_i_1
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\PREAMBLE_COUNT[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\PREAMBLE_COUNT[4]_i_2
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\PREAMBLE_COUNT[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0001))
\PREAMBLE_COUNT[4]_i_3
(.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[2] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[4] ),
.O(\PREAMBLE_COUNT[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000001110100))
\PREAMBLE_COUNT[4]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE[4]_i_4_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(GO_SYNC),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\PREAMBLE_COUNT[4]_i_4_n_0 ));
FDSE \PREAMBLE_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[0]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[0] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDSE \PREAMBLE_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[1]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[1] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDRE \PREAMBLE_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PREAMBLE_COUNT[2]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[2] ),
.R(1'b0));
FDSE \PREAMBLE_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[3]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[3] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDSE \PREAMBLE_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[4]_i_3_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[4] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'hAE55))
S_TX_ACK_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I3(S_TX_ACK_reg_n_0),
.O(S_TX_ACK_i_1_n_0));
FDRE S_TX_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_TX_ACK_i_1_n_0),
.Q(S_TX_ACK_reg_n_0),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair185" *)
LUT3 #(
.INIT(8'hB8))
\TXD[0]_i_1
(.I0(\TXD[0]_i_2_n_0 ),
.I1(\TXD[1]_i_3_n_0 ),
.I2(TXD_OBUF[0]),
.O(\TXD[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[0]_i_10
(.I0(p_18_in[0]),
.I1(TX_MEMORY_reg_n_67),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_20_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_21_in[0]),
.O(\TXD[0]_i_10_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\TXD[0]_i_11
(.I0(slv1_out[5]),
.I1(slv1_out[7]),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_16_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_17_in[0]),
.O(\TXD[0]_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[0]_i_2
(.I0(\TXD[0]_i_3_n_0 ),
.I1(\TXD_reg[0]_i_4_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TXD_reg[0]_i_5_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.I5(\TXD[0]_i_6_n_0 ),
.O(\TXD[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h47FF4700))
\TXD[0]_i_3
(.I0(p_1_in126_in),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_1_in130_in),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TXD[0]_i_7_n_0 ),
.O(\TXD[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'hDFD5FFFF))
\TXD[0]_i_6
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(p_22_in[0]),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(TX_MEMORY_reg_n_59),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TXD[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_7
(.I0(p_1_in133_in),
.I1(p_1_in136_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[9] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[11] ),
.O(\TXD[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_8
(.I0(\TX_CRC_reg_n_0_[21] ),
.I1(\TX_CRC_reg_n_0_[23] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(slv1_out[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(slv1_out[3]),
.O(\TXD[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_9
(.I0(\TX_CRC_reg_n_0_[13] ),
.I1(\TX_CRC_reg_n_0_[15] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[17] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[19] ),
.O(\TXD[0]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair185" *)
LUT3 #(
.INIT(8'hB8))
\TXD[1]_i_1
(.I0(\TXD[1]_i_2_n_0 ),
.I1(\TXD[1]_i_3_n_0 ),
.I2(TXD_OBUF[1]),
.O(\TXD[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_10
(.I0(\TX_CRC_reg_n_0_[12] ),
.I1(\TX_CRC_reg_n_0_[14] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[16] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[18] ),
.O(\TXD[1]_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[1]_i_11
(.I0(p_18_in[1]),
.I1(p_0_in66_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_20_in[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_21_in[1]),
.O(\TXD[1]_i_11_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\TXD[1]_i_12
(.I0(slv1_out[4]),
.I1(slv1_out[6]),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_16_in[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_17_in[1]),
.O(\TXD[1]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[1]_i_2
(.I0(\TXD[1]_i_4_n_0 ),
.I1(\TXD_reg[1]_i_5_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TXD_reg[1]_i_6_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.I5(\TXD[1]_i_7_n_0 ),
.O(\TXD[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hBFFFFFFE))
\TXD[1]_i_3
(.I0(\TX_PHY_STATE_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[1] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TXD[1]_i_3_n_0 ));
LUT5 #(
.INIT(32'h47FF4700))
\TXD[1]_i_4
(.I0(\TX_CRC_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_1_in128_in),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TXD[1]_i_8_n_0 ),
.O(\TXD[1]_i_4_n_0 ));
LUT5 #(
.INIT(32'hA8882808))
\TXD[1]_i_7
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_0_in167_in),
.I4(p_22_in[1]),
.O(\TXD[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_8
(.I0(p_1_in132_in),
.I1(p_1_in135_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[8] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[10] ),
.O(\TXD[1]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_9
(.I0(\TX_CRC_reg_n_0_[20] ),
.I1(\TX_CRC_reg_n_0_[22] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(slv1_out[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(slv1_out[2]),
.O(\TXD[1]_i_9_n_0 ));
FDRE \TXD_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TXD[0]_i_1_n_0 ),
.Q(TXD_OBUF[0]),
.R(INTERNAL_RST_reg));
MUXF7 \TXD_reg[0]_i_4
(.I0(\TXD[0]_i_8_n_0 ),
.I1(\TXD[0]_i_9_n_0 ),
.O(\TXD_reg[0]_i_4_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
MUXF7 \TXD_reg[0]_i_5
(.I0(\TXD[0]_i_10_n_0 ),
.I1(\TXD[0]_i_11_n_0 ),
.O(\TXD_reg[0]_i_5_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDRE \TXD_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TXD[1]_i_1_n_0 ),
.Q(TXD_OBUF[1]),
.R(INTERNAL_RST_reg));
MUXF7 \TXD_reg[1]_i_5
(.I0(\TXD[1]_i_9_n_0 ),
.I1(\TXD[1]_i_10_n_0 ),
.O(\TXD_reg[1]_i_5_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
MUXF7 \TXD_reg[1]_i_6
(.I0(\TXD[1]_i_11_n_0 ),
.I1(\TXD[1]_i_12_n_0 ),
.O(\TXD_reg[1]_i_6_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
LUT6 #(
.INIT(64'h7F7FFFFF00000100))
TXEN_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(TXEN_OBUF),
.O(TXEN_i_1_n_0));
FDRE TXEN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TXEN_i_1_n_0),
.Q(TXEN_OBUF),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h8BB8744774478BB8))
\TX_CRC[0]_i_1
(.I0(\TX_CRC[0]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_0_in167_in),
.I3(p_20_in[1]),
.I4(slv1_out[6]),
.I5(slv1_out[0]),
.O(\TX_CRC[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[0]_i_2
(.I0(p_16_in[1]),
.I1(p_0_in66_in),
.O(\TX_CRC[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_2
(.I0(p_21_in[1]),
.I1(p_20_in[1]),
.I2(\TX_CRC[10]_i_4_n_0 ),
.I3(p_21_in[0]),
.I4(p_22_in[0]),
.O(NEXTCRC32_D80189_out));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_3
(.I0(slv1_out[2]),
.I1(slv1_out[3]),
.I2(p_18_in[0]),
.I3(slv1_out[0]),
.I4(\TX_CRC[10]_i_5_n_0 ),
.O(\TX_CRC[10]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_4
(.I0(p_1_in128_in),
.I1(slv1_out[5]),
.I2(slv1_out[0]),
.I3(slv1_out[3]),
.I4(slv1_out[2]),
.O(\TX_CRC[10]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_5
(.I0(slv1_out[5]),
.I1(p_1_in128_in),
.I2(p_16_in[1]),
.I3(p_17_in[1]),
.I4(p_17_in[0]),
.O(\TX_CRC[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF0660F990F99F066))
\TX_CRC[11]_i_1
(.I0(p_22_in[1]),
.I1(\TX_CRC[11]_i_2_n_0 ),
.I2(\TX_CRC[11]_i_3_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(p_1_in130_in),
.I5(slv1_out[4]),
.O(\TX_CRC[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[11]_i_2
(.I0(p_20_in[0]),
.I1(p_20_in[1]),
.I2(slv1_out[1]),
.I3(slv1_out[0]),
.I4(slv1_out[3]),
.I5(p_21_in[0]),
.O(\TX_CRC[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[11]_i_3
(.I0(p_16_in[1]),
.I1(p_17_in[0]),
.I2(slv1_out[0]),
.I3(p_16_in[0]),
.I4(slv1_out[1]),
.I5(\TX_CRC[11]_i_4_n_0 ),
.O(\TX_CRC[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[11]_i_4
(.I0(slv1_out[3]),
.I1(p_18_in[1]),
.O(\TX_CRC[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[12]_i_2
(.I0(slv1_out[0]),
.I1(\TX_CRC[12]_i_4_n_0 ),
.I2(slv1_out[4]),
.I3(slv1_out[1]),
.I4(p_22_in[1]),
.I5(\TX_CRC[12]_i_5_n_0 ),
.O(\TX_CRC[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[12]_i_3
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(p_16_in[1]),
.I3(p_0_in66_in),
.I4(\TX_CRC[12]_i_6_n_0 ),
.O(\TX_CRC[12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_4
(.I0(slv1_out[6]),
.I1(slv1_out[2]),
.O(\TX_CRC[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[12]_i_5
(.I0(\TX_CRC[18]_i_4_n_0 ),
.I1(p_22_in[0]),
.I2(p_20_in[0]),
.I3(slv1_out[5]),
.I4(p_1_in132_in),
.I5(p_20_in[1]),
.O(\TX_CRC[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[12]_i_6
(.I0(p_17_in[1]),
.I1(p_1_in132_in),
.I2(slv1_out[5]),
.I3(p_18_in[1]),
.I4(\TX_CRC[12]_i_7_n_0 ),
.I5(\TX_CRC[12]_i_8_n_0 ),
.O(\TX_CRC[12]_i_6_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_7
(.I0(slv1_out[4]),
.I1(slv1_out[1]),
.O(\TX_CRC[12]_i_7_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[12]_i_8
(.I0(slv1_out[0]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.O(\TX_CRC[12]_i_8_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[13]_i_2
(.I0(p_22_in[0]),
.I1(p_21_in[0]),
.I2(TX_MEMORY_reg_n_59),
.I3(\TX_CRC[13]_i_4_n_0 ),
.I4(\TX_CRC[18]_i_4_n_0 ),
.I5(p_20_in[0]),
.O(NEXTCRC32_D80195_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[13]_i_3
(.I0(p_17_in[1]),
.I1(p_17_in[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(\TX_CRC[13]_i_4_n_0 ),
.I4(p_18_in[0]),
.I5(\TX_CRC[17]_i_5_n_0 ),
.O(\TX_CRC[13]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[13]_i_4
(.I0(p_1_in133_in),
.I1(slv1_out[6]),
.I2(slv1_out[1]),
.I3(slv1_out[5]),
.I4(\TX_CRC[3]_i_4_n_0 ),
.O(\TX_CRC[13]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_2
(.I0(p_21_in[1]),
.I1(p_0_in167_in),
.I2(p_21_in[0]),
.I3(\TX_CRC[14]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_59),
.I5(p_22_in[1]),
.O(\TX_CRC[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_3
(.I0(p_18_in[1]),
.I1(slv1_out[3]),
.I2(p_17_in[1]),
.I3(\TX_CRC[14]_i_5_n_0 ),
.I4(TX_MEMORY_reg_n_67),
.I5(p_0_in66_in),
.O(\TX_CRC[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_4
(.I0(p_1_in135_in),
.I1(slv1_out[7]),
.I2(slv1_out[4]),
.I3(slv1_out[3]),
.I4(slv1_out[6]),
.I5(slv1_out[2]),
.O(\TX_CRC[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_5
(.I0(p_17_in[0]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[4]),
.I4(slv1_out[7]),
.I5(p_1_in135_in),
.O(\TX_CRC[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9F90606F909F6F60))
\TX_CRC[15]_i_1
(.I0(\TX_CRC[15]_i_2_n_0 ),
.I1(\TX_CRC[15]_i_3_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_CRC[15]_i_4_n_0 ),
.I4(slv1_out[3]),
.I5(\TX_CRC[15]_i_5_n_0 ),
.O(\TX_CRC[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[15]_i_2
(.I0(p_18_in[1]),
.I1(slv1_out[4]),
.O(\TX_CRC[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[15]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(slv1_out[5]),
.I3(p_18_in[0]),
.I4(slv1_out[7]),
.I5(p_1_in136_in),
.O(\TX_CRC[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[15]_i_4
(.I0(slv1_out[4]),
.I1(p_22_in[1]),
.O(\TX_CRC[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[15]_i_5
(.I0(p_21_in[0]),
.I1(p_22_in[0]),
.I2(slv1_out[5]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[7]),
.I5(p_1_in136_in),
.O(\TX_CRC[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9F90606F909F6F60))
\TX_CRC[16]_i_1
(.I0(p_18_in[1]),
.I1(\TX_CRC[16]_i_2_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(slv1_out[4]),
.I4(slv1_out[0]),
.I5(\TX_CRC[16]_i_3_n_0 ),
.O(\TX_CRC[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[16]_i_2
(.I0(p_18_in[0]),
.I1(slv1_out[4]),
.I2(slv1_out[5]),
.I3(\TX_CRC_reg_n_0_[8] ),
.I4(p_16_in[1]),
.O(\TX_CRC[16]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[16]_i_3
(.I0(p_20_in[1]),
.I1(p_22_in[1]),
.I2(p_22_in[0]),
.I3(slv1_out[5]),
.I4(\TX_CRC_reg_n_0_[8] ),
.O(\TX_CRC[16]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[17]_i_2
(.I0(slv1_out[5]),
.I1(p_202_in),
.I2(p_20_in[0]),
.I3(slv1_out[1]),
.I4(p_22_in[0]),
.I5(p_0_in167_in),
.O(NEXTCRC32_D80203_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[17]_i_3
(.I0(slv1_out[5]),
.I1(\TX_CRC[17]_i_5_n_0 ),
.I2(\TX_CRC_reg_n_0_[9] ),
.I3(slv1_out[6]),
.I4(slv1_out[1]),
.I5(p_18_in[0]),
.O(\TX_CRC[17]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[17]_i_4
(.I0(slv1_out[6]),
.I1(\TX_CRC_reg_n_0_[9] ),
.O(p_202_in));
LUT2 #(
.INIT(4'h6))
\TX_CRC[17]_i_5
(.I0(p_0_in66_in),
.I1(p_16_in[0]),
.O(\TX_CRC[17]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[18]_i_2
(.I0(slv1_out[6]),
.I1(TX_MEMORY_reg_n_59),
.I2(\TX_CRC_reg_n_0_[10] ),
.I3(slv1_out[7]),
.I4(slv1_out[2]),
.I5(\TX_CRC[18]_i_4_n_0 ),
.O(\TX_CRC[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[18]_i_3
(.I0(slv1_out[6]),
.I1(\TX_CRC[29]_i_5_n_0 ),
.I2(\TX_CRC_reg_n_0_[10] ),
.I3(slv1_out[7]),
.I4(slv1_out[2]),
.I5(p_17_in[1]),
.O(\TX_CRC[18]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[18]_i_4
(.I0(p_0_in167_in),
.I1(p_21_in[1]),
.O(\TX_CRC[18]_i_4_n_0 ));
LUT6 #(
.INIT(64'h8778B44BB44B8778))
\TX_CRC[19]_i_1
(.I0(\TX_CRC[19]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(slv1_out[3]),
.I3(p_206_in),
.I4(TX_MEMORY_reg_n_59),
.I5(p_21_in[0]),
.O(\TX_CRC[19]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[19]_i_2
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.O(\TX_CRC[19]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[19]_i_3
(.I0(slv1_out[7]),
.I1(\TX_CRC_reg_n_0_[11] ),
.O(p_206_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[1]_i_2
(.I0(\TX_CRC[23]_i_3_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[7]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[0]),
.I5(slv1_out[6]),
.O(\TX_CRC[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[1]_i_3
(.I0(\TX_CRC[23]_i_2_n_0 ),
.I1(slv1_out[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(slv1_out[7]),
.I4(slv1_out[1]),
.O(NEXTCRC32_D8070_out));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[20]_i_1
(.I0(p_18_in[1]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[1]),
.I3(slv1_out[4]),
.I4(\TX_CRC_reg_n_0_[12] ),
.O(\TX_CRC[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[21]_i_1
(.I0(p_18_in[0]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[0]),
.I3(\TX_CRC_reg_n_0_[13] ),
.I4(slv1_out[5]),
.O(\TX_CRC[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[22]_i_1
(.I0(p_16_in[1]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_20_in[1]),
.I3(\TX_CRC_reg_n_0_[14] ),
.I4(slv1_out[0]),
.O(\TX_CRC[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h87B4784BB4874B78))
\TX_CRC[23]_i_1
(.I0(\TX_CRC[23]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(slv1_out[0]),
.I3(\TX_CRC[23]_i_3_n_0 ),
.I4(p_214_in),
.I5(slv1_out[6]),
.O(\TX_CRC[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[23]_i_2
(.I0(p_0_in66_in),
.I1(p_16_in[1]),
.I2(p_16_in[0]),
.I3(slv1_out[6]),
.O(\TX_CRC[23]_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[23]_i_3
(.I0(p_20_in[1]),
.I1(p_20_in[0]),
.I2(p_0_in167_in),
.O(\TX_CRC[23]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[23]_i_4
(.I0(slv1_out[1]),
.I1(\TX_CRC_reg_n_0_[15] ),
.O(p_214_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[24]_i_2
(.I0(\TX_CRC[24]_i_4_n_0 ),
.I1(TX_MEMORY_reg_n_59),
.I2(slv1_out[2]),
.I3(\TX_CRC_reg_n_0_[16] ),
.I4(p_20_in[0]),
.I5(p_21_in[1]),
.O(NEXTCRC32_D80217_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[24]_i_3
(.I0(slv1_out[7]),
.I1(p_16_in[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(p_216_in),
.I4(slv1_out[1]),
.I5(p_17_in[1]),
.O(\TX_CRC[24]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[24]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[1]),
.O(\TX_CRC[24]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[24]_i_5
(.I0(\TX_CRC_reg_n_0_[16] ),
.I1(slv1_out[2]),
.O(p_216_in));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[25]_i_2
(.I0(slv1_out[3]),
.I1(\TX_CRC_reg_n_0_[17] ),
.I2(slv1_out[2]),
.I3(p_21_in[1]),
.I4(p_21_in[0]),
.O(\TX_CRC[25]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[25]_i_3
(.I0(slv1_out[2]),
.I1(p_17_in[1]),
.I2(slv1_out[3]),
.I3(\TX_CRC_reg_n_0_[17] ),
.I4(p_17_in[0]),
.O(\TX_CRC[25]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996FFFF69960000))
\TX_CRC[26]_i_1
(.I0(p_16_in[1]),
.I1(\TX_CRC[26]_i_2_n_0 ),
.I2(p_0_in66_in),
.I3(p_17_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_CRC[26]_i_3_n_0 ),
.O(\TX_CRC[26]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[26]_i_2
(.I0(p_18_in[1]),
.I1(slv1_out[6]),
.I2(slv1_out[3]),
.I3(slv1_out[0]),
.I4(\TX_CRC_reg_n_0_[18] ),
.I5(slv1_out[4]),
.O(\TX_CRC[26]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[26]_i_3
(.I0(p_0_in167_in),
.I1(p_20_in[1]),
.I2(\TX_CRC[26]_i_4_n_0 ),
.I3(p_22_in[1]),
.O(\TX_CRC[26]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[26]_i_4
(.I0(p_21_in[0]),
.I1(slv1_out[6]),
.I2(slv1_out[3]),
.I3(slv1_out[0]),
.I4(\TX_CRC_reg_n_0_[18] ),
.I5(slv1_out[4]),
.O(\TX_CRC[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6F90906F609F9F60))
\TX_CRC[27]_i_1
(.I0(p_18_in[1]),
.I1(\TX_CRC[27]_i_2_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(slv1_out[4]),
.I4(slv1_out[7]),
.I5(\TX_CRC[27]_i_3_n_0 ),
.O(\TX_CRC[27]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[27]_i_2
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(slv1_out[1]),
.I3(slv1_out[5]),
.I4(\TX_CRC_reg_n_0_[19] ),
.I5(TX_MEMORY_reg_n_67),
.O(\TX_CRC[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[27]_i_3
(.I0(\TX_CRC[27]_i_4_n_0 ),
.I1(p_22_in[1]),
.I2(slv1_out[1]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[5]),
.I5(\TX_CRC_reg_n_0_[19] ),
.O(\TX_CRC[27]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[27]_i_4
(.I0(p_22_in[0]),
.I1(p_20_in[0]),
.O(\TX_CRC[27]_i_4_n_0 ));
LUT5 #(
.INIT(32'h906F9F60))
\TX_CRC[28]_i_1
(.I0(slv1_out[2]),
.I1(\TX_CRC[28]_i_2_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(slv1_out[5]),
.I4(\TX_CRC[28]_i_3_n_0 ),
.O(\TX_CRC[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[28]_i_2
(.I0(slv1_out[6]),
.I1(\TX_CRC_reg_n_0_[20] ),
.I2(p_0_in66_in),
.I3(p_17_in[1]),
.I4(p_18_in[0]),
.O(\TX_CRC[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[28]_i_3
(.I0(p_0_in167_in),
.I1(p_22_in[0]),
.I2(slv1_out[2]),
.I3(p_21_in[1]),
.I4(slv1_out[6]),
.I5(\TX_CRC_reg_n_0_[20] ),
.O(\TX_CRC[28]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[29]_i_2
(.I0(\TX_CRC[29]_i_4_n_0 ),
.I1(p_0_in167_in),
.I2(p_21_in[0]),
.I3(\TX_CRC_reg_n_0_[21] ),
.I4(slv1_out[7]),
.I5(TX_MEMORY_reg_n_59),
.O(\TX_CRC[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[29]_i_3
(.I0(slv1_out[3]),
.I1(p_17_in[0]),
.I2(\TX_CRC_reg_n_0_[21] ),
.I3(slv1_out[7]),
.I4(slv1_out[6]),
.I5(\TX_CRC[29]_i_5_n_0 ),
.O(\TX_CRC[29]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[29]_i_4
(.I0(slv1_out[3]),
.I1(slv1_out[6]),
.O(\TX_CRC[29]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[29]_i_5
(.I0(TX_MEMORY_reg_n_67),
.I1(p_0_in66_in),
.O(\TX_CRC[29]_i_5_n_0 ));
LUT5 #(
.INIT(32'hB4874B78))
\TX_CRC[2]_i_1
(.I0(\TX_CRC[2]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(slv1_out[0]),
.I3(\TX_CRC[2]_i_3_n_0 ),
.I4(\TX_CRC[2]_i_4_n_0 ),
.O(\TX_CRC[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[2]_i_2
(.I0(TX_MEMORY_reg_n_67),
.I1(p_0_in66_in),
.I2(p_16_in[0]),
.I3(p_17_in[1]),
.I4(p_16_in[1]),
.O(\TX_CRC[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[2]_i_3
(.I0(p_20_in[0]),
.I1(p_0_in167_in),
.I2(p_21_in[1]),
.I3(p_20_in[1]),
.I4(TX_MEMORY_reg_n_59),
.O(\TX_CRC[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[2]_i_4
(.I0(slv1_out[6]),
.I1(slv1_out[7]),
.I2(slv1_out[1]),
.I3(slv1_out[2]),
.O(\TX_CRC[2]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[30]_i_2
(.I0(p_22_in[1]),
.I1(slv1_out[4]),
.I2(TX_MEMORY_reg_n_59),
.I3(slv1_out[7]),
.I4(\TX_CRC_reg_n_0_[22] ),
.O(\TX_CRC[30]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[30]_i_3
(.I0(slv1_out[4]),
.I1(p_18_in[1]),
.I2(slv1_out[7]),
.I3(\TX_CRC_reg_n_0_[22] ),
.I4(TX_MEMORY_reg_n_67),
.O(\TX_CRC[30]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000008))
\TX_CRC[31]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_CRC[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'h10101000))
\TX_CRC[31]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[1] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_CRC[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[31]_i_3
(.I0(p_18_in[0]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[0]),
.I3(\TX_CRC_reg_n_0_[23] ),
.I4(slv1_out[5]),
.O(\TX_CRC[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[3]_i_2
(.I0(\TX_CRC[3]_i_4_n_0 ),
.I1(p_21_in[1]),
.I2(p_21_in[0]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[1]),
.I5(p_20_in[0]),
.O(NEXTCRC32_D80177_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[3]_i_3
(.I0(\TX_CRC[3]_i_4_n_0 ),
.I1(p_16_in[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(p_17_in[0]),
.I4(slv1_out[1]),
.I5(p_17_in[1]),
.O(\TX_CRC[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[3]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[2]),
.I2(slv1_out[3]),
.O(\TX_CRC[3]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[4]_i_2
(.I0(p_21_in[1]),
.I1(p_0_in167_in),
.I2(\TX_CRC[4]_i_4_n_0 ),
.I3(p_22_in[1]),
.I4(p_21_in[0]),
.O(\TX_CRC[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[4]_i_3
(.I0(slv1_out[4]),
.I1(slv1_out[3]),
.I2(slv1_out[0]),
.I3(p_18_in[1]),
.I4(\TX_CRC[4]_i_5_n_0 ),
.O(\TX_CRC[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[4]_i_4
(.I0(p_20_in[1]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[3]),
.I4(slv1_out[0]),
.I5(slv1_out[4]),
.O(\TX_CRC[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[4]_i_5
(.I0(p_17_in[1]),
.I1(slv1_out[6]),
.I2(slv1_out[2]),
.I3(p_17_in[0]),
.I4(p_16_in[1]),
.I5(p_0_in66_in),
.O(\TX_CRC[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_2
(.I0(\TX_CRC[5]_i_4_n_0 ),
.I1(p_20_in[1]),
.I2(p_0_in167_in),
.I3(TX_MEMORY_reg_n_59),
.I4(\TX_CRC[5]_i_5_n_0 ),
.I5(\TX_CRC[5]_i_6_n_0 ),
.O(NEXTCRC32_D80181_out));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[5]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(p_16_in[1]),
.I3(p_0_in66_in),
.I4(\TX_CRC[5]_i_7_n_0 ),
.O(NEXTCRC32_D8074_out));
LUT2 #(
.INIT(4'h6))
\TX_CRC[5]_i_4
(.I0(p_21_in[0]),
.I1(p_22_in[0]),
.O(\TX_CRC[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_5
(.I0(p_20_in[0]),
.I1(\TX_CRC[6]_i_6_n_0 ),
.I2(slv1_out[0]),
.I3(slv1_out[5]),
.I4(slv1_out[6]),
.I5(slv1_out[3]),
.O(\TX_CRC[5]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[5]_i_6
(.I0(p_22_in[1]),
.I1(slv1_out[1]),
.O(\TX_CRC[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_7
(.I0(\TX_CRC[5]_i_8_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[4]),
.I3(slv1_out[7]),
.I4(\TX_CRC[5]_i_9_n_0 ),
.I5(p_18_in[1]),
.O(\TX_CRC[5]_i_7_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[5]_i_8
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.O(\TX_CRC[5]_i_8_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[5]_i_9
(.I0(slv1_out[0]),
.I1(slv1_out[5]),
.I2(slv1_out[6]),
.I3(slv1_out[3]),
.O(\TX_CRC[5]_i_9_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_2
(.I0(\TX_CRC[18]_i_4_n_0 ),
.I1(p_22_in[1]),
.I2(slv1_out[1]),
.I3(\TX_CRC[6]_i_4_n_0 ),
.I4(p_22_in[0]),
.I5(p_20_in[0]),
.O(\TX_CRC[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_3
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(slv1_out[2]),
.I3(slv1_out[6]),
.I4(p_17_in[1]),
.I5(\TX_CRC[6]_i_5_n_0 ),
.O(\TX_CRC[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_4
(.I0(TX_MEMORY_reg_n_59),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[5]),
.I4(slv1_out[7]),
.I5(slv1_out[4]),
.O(\TX_CRC[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_5
(.I0(p_0_in66_in),
.I1(TX_MEMORY_reg_n_67),
.I2(\TX_CRC[6]_i_6_n_0 ),
.I3(slv1_out[5]),
.I4(slv1_out[1]),
.I5(p_18_in[1]),
.O(\TX_CRC[6]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[6]_i_6
(.I0(slv1_out[7]),
.I1(slv1_out[4]),
.O(\TX_CRC[6]_i_6_n_0 ));
LUT6 #(
.INIT(64'h690096FF69FF9600))
\TX_CRC[7]_i_1
(.I0(slv1_out[5]),
.I1(p_18_in[0]),
.I2(\TX_CRC[7]_i_2_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC[7]_i_3_n_0 ),
.I5(\TX_CRC[7]_i_4_n_0 ),
.O(\TX_CRC[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[7]_i_2
(.I0(TX_MEMORY_reg_n_67),
.I1(p_16_in[1]),
.I2(p_17_in[1]),
.I3(p_17_in[0]),
.O(\TX_CRC[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[7]_i_3
(.I0(slv1_out[3]),
.I1(slv1_out[2]),
.I2(slv1_out[7]),
.I3(slv1_out[0]),
.O(\TX_CRC[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[7]_i_4
(.I0(p_20_in[1]),
.I1(p_21_in[1]),
.I2(slv1_out[5]),
.I3(TX_MEMORY_reg_n_59),
.I4(p_21_in[0]),
.I5(p_22_in[0]),
.O(\TX_CRC[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF0660F990F99F066))
\TX_CRC[8]_i_1
(.I0(p_22_in[1]),
.I1(\TX_CRC[11]_i_2_n_0 ),
.I2(\TX_CRC[11]_i_3_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC_reg_n_0_[0] ),
.I5(slv1_out[4]),
.O(\TX_CRC[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996FFFF69960000))
\TX_CRC[9]_i_1
(.I0(slv1_out[4]),
.I1(slv1_out[1]),
.I2(p_18_in[1]),
.I3(\TX_CRC[9]_i_2_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_CRC[9]_i_3_n_0 ),
.O(\TX_CRC[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[9]_i_2
(.I0(slv1_out[2]),
.I1(p_17_in[1]),
.I2(slv1_out[5]),
.I3(p_1_in126_in),
.I4(p_18_in[0]),
.I5(p_16_in[0]),
.O(\TX_CRC[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[9]_i_3
(.I0(\TX_CRC[9]_i_4_n_0 ),
.I1(p_1_in126_in),
.I2(slv1_out[5]),
.I3(p_21_in[1]),
.I4(slv1_out[2]),
.I5(\TX_CRC[27]_i_4_n_0 ),
.O(\TX_CRC[9]_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[9]_i_4
(.I0(slv1_out[4]),
.I1(slv1_out[1]),
.I2(p_22_in[1]),
.O(\TX_CRC[9]_i_4_n_0 ));
FDSE \TX_CRC_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[0]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[0] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[10]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[10] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[10]_i_1
(.I0(NEXTCRC32_D80189_out),
.I1(\TX_CRC[10]_i_3_n_0 ),
.O(\TX_CRC_reg[10]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[11]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[11] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[12]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[12] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[12]_i_1
(.I0(\TX_CRC[12]_i_2_n_0 ),
.I1(\TX_CRC[12]_i_3_n_0 ),
.O(\TX_CRC_reg[12]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[13]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[13] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[13]_i_1
(.I0(NEXTCRC32_D80195_out),
.I1(\TX_CRC[13]_i_3_n_0 ),
.O(\TX_CRC_reg[13]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[14]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[14] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[14]_i_1
(.I0(\TX_CRC[14]_i_2_n_0 ),
.I1(\TX_CRC[14]_i_3_n_0 ),
.O(\TX_CRC_reg[14]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[15]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[15] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[16]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[16] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[17]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[17] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[17]_i_1
(.I0(NEXTCRC32_D80203_out),
.I1(\TX_CRC[17]_i_3_n_0 ),
.O(\TX_CRC_reg[17]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[18]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[18] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[18]_i_1
(.I0(\TX_CRC[18]_i_2_n_0 ),
.I1(\TX_CRC[18]_i_3_n_0 ),
.O(\TX_CRC_reg[18]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[19]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[19] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[1]_i_1_n_0 ),
.Q(p_1_in126_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[1]_i_1
(.I0(\TX_CRC[1]_i_2_n_0 ),
.I1(NEXTCRC32_D8070_out),
.O(\TX_CRC_reg[1]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[20]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[20] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[21]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[21] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[22]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[22] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[23]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[23] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[24]_i_1_n_0 ),
.Q(slv1_out[0]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[24]_i_1
(.I0(NEXTCRC32_D80217_out),
.I1(\TX_CRC[24]_i_3_n_0 ),
.O(\TX_CRC_reg[24]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[25]_i_1_n_0 ),
.Q(slv1_out[1]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[25]_i_1
(.I0(\TX_CRC[25]_i_2_n_0 ),
.I1(\TX_CRC[25]_i_3_n_0 ),
.O(\TX_CRC_reg[25]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[26]_i_1_n_0 ),
.Q(slv1_out[2]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[27]_i_1_n_0 ),
.Q(slv1_out[3]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[28]_i_1_n_0 ),
.Q(slv1_out[4]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[29]_i_1_n_0 ),
.Q(slv1_out[5]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[29]_i_1
(.I0(\TX_CRC[29]_i_2_n_0 ),
.I1(\TX_CRC[29]_i_3_n_0 ),
.O(\TX_CRC_reg[29]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[2]_i_1_n_0 ),
.Q(p_1_in128_in),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[30]_i_1_n_0 ),
.Q(slv1_out[6]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[30]_i_1
(.I0(\TX_CRC[30]_i_2_n_0 ),
.I1(\TX_CRC[30]_i_3_n_0 ),
.O(\TX_CRC_reg[30]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[31]_i_3_n_0 ),
.Q(slv1_out[7]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[3]_i_1_n_0 ),
.Q(p_1_in130_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[3]_i_1
(.I0(NEXTCRC32_D80177_out),
.I1(\TX_CRC[3]_i_3_n_0 ),
.O(\TX_CRC_reg[3]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[4]_i_1_n_0 ),
.Q(p_1_in132_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[4]_i_1
(.I0(\TX_CRC[4]_i_2_n_0 ),
.I1(\TX_CRC[4]_i_3_n_0 ),
.O(\TX_CRC_reg[4]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[5]_i_1_n_0 ),
.Q(p_1_in133_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[5]_i_1
(.I0(NEXTCRC32_D80181_out),
.I1(NEXTCRC32_D8074_out),
.O(\TX_CRC_reg[5]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[6]_i_1_n_0 ),
.Q(p_1_in135_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[6]_i_1
(.I0(\TX_CRC[6]_i_2_n_0 ),
.I1(\TX_CRC[6]_i_3_n_0 ),
.O(\TX_CRC_reg[6]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[7]_i_1_n_0 ),
.Q(p_1_in136_in),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[8]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[8] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[9]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[9] ),
.S(\TX_CRC[31]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\TX_IN_COUNT[10]_i_1
(.I0(S_TX_ACK_reg_n_0),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(\TX_IN_COUNT[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0444))
\TX_IN_COUNT[10]_i_2
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.O(\TX_IN_COUNT[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'hAAAA6AAA))
\TX_IN_COUNT[10]_i_3
(.I0(TX_IN_COUNT[10]),
.I1(TX_IN_COUNT[9]),
.I2(TX_IN_COUNT[8]),
.I3(TX_IN_COUNT[7]),
.I4(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\TX_IN_COUNT[10]_i_4
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[3]),
.I2(TX_IN_COUNT[1]),
.I3(TX_IN_COUNT[2]),
.I4(TX_IN_COUNT[4]),
.I5(TX_IN_COUNT[6]),
.O(\TX_IN_COUNT[10]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT5 #(
.INIT(32'hFFBF0444))
\TX_IN_COUNT[1]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I4(TX_IN_COUNT[1]),
.O(\TX_IN_COUNT[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFCFDFCF00002000))
\TX_IN_COUNT[2]_i_1
(.I0(TX_IN_COUNT[1]),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(S_TX_ACK_reg_n_0),
.I3(\TX_PACKET_STATE_reg_n_0_[0] ),
.I4(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I5(TX_IN_COUNT[2]),
.O(\TX_IN_COUNT[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\TX_IN_COUNT[3]_i_1
(.I0(TX_IN_COUNT[3]),
.I1(TX_IN_COUNT[2]),
.I2(TX_IN_COUNT[1]),
.O(\TX_IN_COUNT[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT4 #(
.INIT(16'h6AAA))
\TX_IN_COUNT[4]_i_1
(.I0(TX_IN_COUNT[4]),
.I1(TX_IN_COUNT[3]),
.I2(TX_IN_COUNT[1]),
.I3(TX_IN_COUNT[2]),
.O(\TX_IN_COUNT[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\TX_IN_COUNT[5]_i_1
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[4]),
.I2(TX_IN_COUNT[2]),
.I3(TX_IN_COUNT[1]),
.I4(TX_IN_COUNT[3]),
.O(\TX_IN_COUNT[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\TX_IN_COUNT[6]_i_1
(.I0(TX_IN_COUNT[6]),
.I1(TX_IN_COUNT[5]),
.I2(TX_IN_COUNT[3]),
.I3(TX_IN_COUNT[1]),
.I4(TX_IN_COUNT[2]),
.I5(TX_IN_COUNT[4]),
.O(\TX_IN_COUNT[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair187" *)
LUT2 #(
.INIT(4'h9))
\TX_IN_COUNT[7]_i_1
(.I0(TX_IN_COUNT[7]),
.I1(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair187" *)
LUT3 #(
.INIT(8'hA6))
\TX_IN_COUNT[8]_i_1
(.I0(TX_IN_COUNT[8]),
.I1(TX_IN_COUNT[7]),
.I2(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h9AAA))
\TX_IN_COUNT[9]_i_1
(.I0(TX_IN_COUNT[9]),
.I1(\TX_IN_COUNT[10]_i_4_n_0 ),
.I2(TX_IN_COUNT[7]),
.I3(TX_IN_COUNT[8]),
.O(\TX_IN_COUNT[9]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[10]_i_3_n_0 ),
.Q(TX_IN_COUNT[10]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_IN_COUNT[1]_i_1_n_0 ),
.Q(TX_IN_COUNT[1]),
.R(1'b0));
FDRE \TX_IN_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_IN_COUNT[2]_i_1_n_0 ),
.Q(TX_IN_COUNT[2]),
.R(1'b0));
FDRE \TX_IN_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[3]_i_1_n_0 ),
.Q(TX_IN_COUNT[3]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[4]_i_1_n_0 ),
.Q(TX_IN_COUNT[4]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[5]_i_1_n_0 ),
.Q(TX_IN_COUNT[5]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[6]_i_1_n_0 ),
.Q(TX_IN_COUNT[6]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[7]_i_1_n_0 ),
.Q(TX_IN_COUNT[7]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[8]_i_1_n_0 ),
.Q(TX_IN_COUNT[8]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[9]_i_1_n_0 ),
.Q(TX_IN_COUNT[9]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENBWREN=NEW" *)
(* RTL_RAM_BITS = "16400" *)
(* RTL_RAM_NAME = "TX_MEMORY" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
TX_MEMORY_reg
(.ADDRARDADDR({1'b1,TX_WRITE_ADDRESS_DEL,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,TX_READ_ADDRESS,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(ETH_CLK_OBUF),
.DBITERR(NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_TX_MEMORY_reg_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED[31:16],p_20_in,p_21_in,p_22_in,p_0_in167_in,TX_MEMORY_reg_n_59,p_16_in,p_17_in,p_18_in,p_0_in66_in,TX_MEMORY_reg_n_67}),
.DOPADOP(NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(TX_WRITE),
.ENBWREN(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9),
.INJECTDBITERR(NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff35))
TX_MEMORY_reg_ENBWREN_cooolgate_en_gate_17
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE[4]_i_2_n_0 ),
.I2(\TX_PHY_STATE[4]_i_1_n_0 ),
.I3(INTERNAL_RST_reg),
.O(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9));
(* SOFT_HLUTNM = "soft_lutpair180" *)
LUT2 #(
.INIT(4'h7))
\TX_OUT_COUNT[0]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.O(TX_OUT_COUNT0_in));
LUT6 #(
.INIT(64'h00000000AA100010))
\TX_OUT_COUNT[10]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[3] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT[10]_i_3_n_0 ),
.I5(\TX_OUT_COUNT[10]_i_4_n_0 ),
.O(\TX_OUT_COUNT[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair177" *)
LUT4 #(
.INIT(16'hE133))
\TX_OUT_COUNT[10]_i_2
(.I0(\TX_OUT_COUNT_reg_n_0_[9] ),
.I1(\TX_OUT_COUNT[10]_i_5_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[10] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFF7F))
\TX_OUT_COUNT[10]_i_3
(.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
.I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
.I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT_reg_n_0_[1] ),
.I5(\TX_OUT_COUNT_reg_n_0_[2] ),
.O(\TX_OUT_COUNT[10]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_OUT_COUNT[10]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\TX_OUT_COUNT[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEF0F0F0F0))
\TX_OUT_COUNT[10]_i_5
(.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[6] ),
.I4(\TX_OUT_COUNT_reg_n_0_[8] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[10]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\TX_OUT_COUNT[10]_i_6
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[4] ),
.I2(\TX_OUT_COUNT_reg_n_0_[5] ),
.O(\TX_OUT_COUNT[10]_i_6_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_OUT_COUNT[10]_i_7
(.I0(\TX_OUT_COUNT_reg_n_0_[10] ),
.I1(\TX_OUT_COUNT_reg_n_0_[9] ),
.O(\TX_OUT_COUNT[10]_i_7_n_0 ));
LUT3 #(
.INIT(8'h01))
\TX_OUT_COUNT[10]_i_8
(.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
.I1(\TX_OUT_COUNT_reg_n_0_[8] ),
.I2(\TX_OUT_COUNT_reg_n_0_[7] ),
.O(\TX_OUT_COUNT[10]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair180" *)
LUT3 #(
.INIT(8'h9F))
\TX_OUT_COUNT[1]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT4 #(
.INIT(16'hE1FF))
\TX_OUT_COUNT[2]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[1] ),
.I1(\TX_OUT_COUNT_reg_n_0_[0] ),
.I2(\TX_OUT_COUNT_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT5 #(
.INIT(32'hFE01FFFF))
\TX_OUT_COUNT[3]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[2] ),
.I1(\TX_OUT_COUNT_reg_n_0_[0] ),
.I2(\TX_OUT_COUNT_reg_n_0_[1] ),
.I3(\TX_OUT_COUNT_reg_n_0_[3] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFE0001FFFFFFFF))
\TX_OUT_COUNT[4]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_OUT_COUNT_reg_n_0_[0] ),
.I3(\TX_OUT_COUNT_reg_n_0_[2] ),
.I4(\TX_OUT_COUNT_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'h95))
\TX_OUT_COUNT[5]_i_1
(.I0(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'hE133))
\TX_OUT_COUNT[6]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[5] ),
.I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[6] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT5 #(
.INIT(32'hFE013333))
\TX_OUT_COUNT[7]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
.I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[5] ),
.I3(\TX_OUT_COUNT_reg_n_0_[7] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFE00010F0F0F0F))
\TX_OUT_COUNT[8]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[6] ),
.I4(\TX_OUT_COUNT_reg_n_0_[8] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFE00000000))
\TX_OUT_COUNT[8]_i_2
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_OUT_COUNT_reg_n_0_[0] ),
.I3(\TX_OUT_COUNT_reg_n_0_[2] ),
.I4(\TX_OUT_COUNT_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[8]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair177" *)
LUT3 #(
.INIT(8'h95))
\TX_OUT_COUNT[9]_i_1
(.I0(\TX_OUT_COUNT[10]_i_5_n_0 ),
.I1(\TX_OUT_COUNT_reg_n_0_[9] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[9]_i_1_n_0 ));
FDRE \TX_OUT_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(TX_OUT_COUNT0_in),
.Q(\TX_OUT_COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[10]_i_2_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[10] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[1]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[2]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[3]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[4]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[5]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[6]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[7]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[7] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[8]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[8] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[9]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT5 #(
.INIT(32'hFF007C7C))
\TX_PACKET_STATE[0]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(S_TX_ACK_reg_n_0),
.I3(DONE_SYNC),
.I4(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_PACKET_STATE[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT5 #(
.INIT(32'hFF338080))
\TX_PACKET_STATE[1]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(S_TX_ACK_reg_n_0),
.I3(DONE_SYNC),
.I4(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_PACKET_STATE[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_10
(.I0(TX_IN_COUNT[6]),
.I1(TX_IN_COUNT[7]),
.O(\TX_PACKET_STATE[1]_i_10_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_11
(.I0(TX_IN_COUNT[4]),
.I1(TX_IN_COUNT[5]),
.O(\TX_PACKET_STATE[1]_i_11_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_12
(.I0(TX_IN_COUNT[2]),
.I1(TX_IN_COUNT[3]),
.O(\TX_PACKET_STATE[1]_i_12_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_PACKET_STATE[1]_i_13
(.I0(TX_IN_COUNT[1]),
.O(\TX_PACKET_STATE[1]_i_13_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_4
(.I0(TX_IN_COUNT[9]),
.I1(TX_IN_COUNT[8]),
.O(\TX_PACKET_STATE[1]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_PACKET_STATE[1]_i_5
(.I0(TX_IN_COUNT[10]),
.O(\TX_PACKET_STATE[1]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_6
(.I0(TX_IN_COUNT[8]),
.I1(TX_IN_COUNT[9]),
.O(\TX_PACKET_STATE[1]_i_6_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_7
(.I0(TX_IN_COUNT[7]),
.I1(TX_IN_COUNT[6]),
.O(\TX_PACKET_STATE[1]_i_7_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_8
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[4]),
.O(\TX_PACKET_STATE[1]_i_8_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_9
(.I0(TX_IN_COUNT[3]),
.I1(TX_IN_COUNT[2]),
.O(\TX_PACKET_STATE[1]_i_9_n_0 ));
FDRE \TX_PACKET_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_PACKET_STATE[0]_i_1_n_0 ),
.Q(\TX_PACKET_STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PACKET_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_PACKET_STATE[1]_i_1_n_0 ),
.Q(\TX_PACKET_STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
CARRY4 \TX_PACKET_STATE_reg[1]_i_2
(.CI(\TX_PACKET_STATE_reg[1]_i_3_n_0 ),
.CO({\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [3:2],\TX_PACKET_STATE_reg[1]_i_2_n_2 ,\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,TX_IN_COUNT[10],\TX_PACKET_STATE[1]_i_4_n_0 }),
.O(\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED [3:0]),
.S({1'b0,1'b0,\TX_PACKET_STATE[1]_i_5_n_0 ,\TX_PACKET_STATE[1]_i_6_n_0 }));
CARRY4 \TX_PACKET_STATE_reg[1]_i_3
(.CI(1'b0),
.CO({\TX_PACKET_STATE_reg[1]_i_3_n_0 ,\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\TX_PACKET_STATE[1]_i_7_n_0 ,\TX_PACKET_STATE[1]_i_8_n_0 ,\TX_PACKET_STATE[1]_i_9_n_0 ,TX_IN_COUNT[1]}),
.O(\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED [3:0]),
.S({\TX_PACKET_STATE[1]_i_10_n_0 ,\TX_PACKET_STATE[1]_i_11_n_0 ,\TX_PACKET_STATE[1]_i_12_n_0 ,\TX_PACKET_STATE[1]_i_13_n_0 }));
LUT6 #(
.INIT(64'h80000000DFFFFFFF))
\TX_PHY_STATE[0]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.I4(\TX_PHY_STATE_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000FFFFDFFF0000))
\TX_PHY_STATE[1]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8ABABA8ABA8ABA8A))
\TX_PHY_STATE[2]_i_1
(.I0(\TX_PHY_STATE[2]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8BB88BBBB8888))
\TX_PHY_STATE[2]_i_2
(.I0(\TX_PHY_STATE[2]_i_3_n_0 ),
.I1(\TX_PHY_STATE[2]_i_4_n_0 ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0FF0F8F0))
\TX_PHY_STATE[2]_i_3
(.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_3_n_0 ));
LUT3 #(
.INIT(8'h5D))
\TX_PHY_STATE[2]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_PHY_STATE[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCFAAC0AAC0AAC0AA))
\TX_PHY_STATE[3]_i_1
(.I0(\TX_PHY_STATE[3]_i_2_n_0 ),
.I1(\TX_PHY_STATE[3]_i_3_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_PHY_STATE[3]_i_4_n_0 ),
.O(\TX_PHY_STATE[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h3CCC8CCC))
\TX_PHY_STATE[3]_i_2
(.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hBF))
\TX_PHY_STATE[3]_i_3
(.I0(GO_SYNC),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\TX_PHY_STATE[3]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\TX_PHY_STATE[3]_i_5
(.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
.I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
.I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT_reg_n_0_[1] ),
.I5(\TX_OUT_COUNT_reg_n_0_[2] ),
.O(\TX_PHY_STATE[3]_i_5_n_0 ));
LUT5 #(
.INIT(32'hAFBEAABE))
\TX_PHY_STATE[4]_i_1
(.I0(\TX_PHY_STATE[4]_i_3_n_0 ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE[4]_i_4_n_0 ),
.O(\TX_PHY_STATE[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF5FF8800FFFF0000))
\TX_PHY_STATE[4]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_PHY_STATE[4]_i_2_n_0 ));
LUT4 #(
.INIT(16'h7FFE))
\TX_PHY_STATE[4]_i_3
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\TX_PHY_STATE[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000001))
\TX_PHY_STATE[4]_i_4
(.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[4] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[2] ),
.O(\TX_PHY_STATE[4]_i_4_n_0 ));
FDRE \TX_PHY_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[0]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[1]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[2]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[3]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[4]_i_2_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \TX_READ_ADDRESS_reg_rep[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ),
.Q(TX_READ_ADDRESS[0]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[10]),
.Q(TX_READ_ADDRESS[10]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[1]),
.Q(TX_READ_ADDRESS[1]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[2]),
.Q(TX_READ_ADDRESS[2]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[3]),
.Q(TX_READ_ADDRESS[3]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[4]),
.Q(TX_READ_ADDRESS[4]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[5]),
.Q(TX_READ_ADDRESS[5]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[6]),
.Q(TX_READ_ADDRESS[6]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[7]),
.Q(TX_READ_ADDRESS[7]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[8]),
.Q(TX_READ_ADDRESS[8]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[9]),
.Q(TX_READ_ADDRESS[9]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_READ_ADDRESS_rep[0]_i_1
(.I0(TX_READ_ADDRESS[0]),
.O(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\TX_READ_ADDRESS_rep[10]_i_1
(.I0(TX_READ_ADDRESS[8]),
.I1(TX_READ_ADDRESS[6]),
.I2(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I3(TX_READ_ADDRESS[7]),
.I4(TX_READ_ADDRESS[9]),
.I5(TX_READ_ADDRESS[10]),
.O(TX_READ_ADDRESS0[10]));
(* SOFT_HLUTNM = "soft_lutpair178" *)
LUT2 #(
.INIT(4'h6))
\TX_READ_ADDRESS_rep[1]_i_1
(.I0(TX_READ_ADDRESS[0]),
.I1(TX_READ_ADDRESS[1]),
.O(TX_READ_ADDRESS0[1]));
(* SOFT_HLUTNM = "soft_lutpair178" *)
LUT3 #(
.INIT(8'h78))
\TX_READ_ADDRESS_rep[2]_i_1
(.I0(TX_READ_ADDRESS[0]),
.I1(TX_READ_ADDRESS[1]),
.I2(TX_READ_ADDRESS[2]),
.O(TX_READ_ADDRESS0[2]));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT4 #(
.INIT(16'h7F80))
\TX_READ_ADDRESS_rep[3]_i_1
(.I0(TX_READ_ADDRESS[1]),
.I1(TX_READ_ADDRESS[0]),
.I2(TX_READ_ADDRESS[2]),
.I3(TX_READ_ADDRESS[3]),
.O(TX_READ_ADDRESS0[3]));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TX_READ_ADDRESS_rep[4]_i_1
(.I0(TX_READ_ADDRESS[2]),
.I1(TX_READ_ADDRESS[0]),
.I2(TX_READ_ADDRESS[1]),
.I3(TX_READ_ADDRESS[3]),
.I4(TX_READ_ADDRESS[4]),
.O(TX_READ_ADDRESS0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\TX_READ_ADDRESS_rep[5]_i_1
(.I0(TX_READ_ADDRESS[3]),
.I1(TX_READ_ADDRESS[1]),
.I2(TX_READ_ADDRESS[0]),
.I3(TX_READ_ADDRESS[2]),
.I4(TX_READ_ADDRESS[4]),
.I5(TX_READ_ADDRESS[5]),
.O(TX_READ_ADDRESS0[5]));
(* SOFT_HLUTNM = "soft_lutpair181" *)
LUT2 #(
.INIT(4'h6))
\TX_READ_ADDRESS_rep[6]_i_1
(.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I1(TX_READ_ADDRESS[6]),
.O(TX_READ_ADDRESS0[6]));
(* SOFT_HLUTNM = "soft_lutpair181" *)
LUT3 #(
.INIT(8'h78))
\TX_READ_ADDRESS_rep[7]_i_1
(.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I1(TX_READ_ADDRESS[6]),
.I2(TX_READ_ADDRESS[7]),
.O(TX_READ_ADDRESS0[7]));
(* SOFT_HLUTNM = "soft_lutpair155" *)
LUT4 #(
.INIT(16'h7F80))
\TX_READ_ADDRESS_rep[8]_i_1
(.I0(TX_READ_ADDRESS[6]),
.I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I2(TX_READ_ADDRESS[7]),
.I3(TX_READ_ADDRESS[8]),
.O(TX_READ_ADDRESS0[8]));
LUT6 #(
.INIT(64'h0000000000000004))
\TX_READ_ADDRESS_rep[9]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0100010000010000))
\TX_READ_ADDRESS_rep[9]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.I4(GO_SYNC),
.I5(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair155" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TX_READ_ADDRESS_rep[9]_i_3
(.I0(TX_READ_ADDRESS[7]),
.I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I2(TX_READ_ADDRESS[6]),
.I3(TX_READ_ADDRESS[8]),
.I4(TX_READ_ADDRESS[9]),
.O(TX_READ_ADDRESS0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\TX_READ_ADDRESS_rep[9]_i_4
(.I0(TX_READ_ADDRESS[5]),
.I1(TX_READ_ADDRESS[3]),
.I2(TX_READ_ADDRESS[1]),
.I3(TX_READ_ADDRESS[0]),
.I4(TX_READ_ADDRESS[2]),
.I5(TX_READ_ADDRESS[4]),
.O(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair175" *)
LUT2 #(
.INIT(4'h1))
\TX_WRITE_ADDRESS[0]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[0]),
.O(\TX_WRITE_ADDRESS[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h04F0))
\TX_WRITE_ADDRESS[10]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[1] ),
.I3(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(\TX_WRITE_ADDRESS[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair175" *)
LUT4 #(
.INIT(16'h0078))
\TX_WRITE_ADDRESS[10]_i_2
(.I0(\TX_WRITE_ADDRESS[10]_i_3_n_0 ),
.I1(TX_WRITE_ADDRESS[9]),
.I2(TX_WRITE_ADDRESS[10]),
.I3(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_WRITE_ADDRESS[10]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0800))
\TX_WRITE_ADDRESS[10]_i_3
(.I0(TX_WRITE_ADDRESS[8]),
.I1(TX_WRITE_ADDRESS[7]),
.I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I3(TX_WRITE_ADDRESS[6]),
.O(\TX_WRITE_ADDRESS[10]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair182" *)
LUT3 #(
.INIT(8'h06))
\TX_WRITE_ADDRESS[1]_i_1
(.I0(TX_WRITE_ADDRESS[1]),
.I1(TX_WRITE_ADDRESS[0]),
.I2(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_WRITE_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT4 #(
.INIT(16'h1540))
\TX_WRITE_ADDRESS[2]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[0]),
.I2(TX_WRITE_ADDRESS[1]),
.I3(TX_WRITE_ADDRESS[2]),
.O(\TX_WRITE_ADDRESS[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT5 #(
.INIT(32'h15554000))
\TX_WRITE_ADDRESS[3]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[1]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[2]),
.I4(TX_WRITE_ADDRESS[3]),
.O(\TX_WRITE_ADDRESS[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1555555540000000))
\TX_WRITE_ADDRESS[4]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[2]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[1]),
.I4(TX_WRITE_ADDRESS[3]),
.I5(TX_WRITE_ADDRESS[4]),
.O(\TX_WRITE_ADDRESS[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair182" *)
LUT3 #(
.INIT(8'h41))
\TX_WRITE_ADDRESS[5]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[5]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[5]),
.O(\TX_WRITE_ADDRESS[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h7FFFFFFF))
\TX_WRITE_ADDRESS[5]_i_2
(.I0(TX_WRITE_ADDRESS[3]),
.I1(TX_WRITE_ADDRESS[1]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[2]),
.I4(TX_WRITE_ADDRESS[4]),
.O(\TX_WRITE_ADDRESS[5]_i_2_n_0 ));
LUT3 #(
.INIT(8'h41))
\TX_WRITE_ADDRESS[6]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[6]),
.O(\TX_WRITE_ADDRESS[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT4 #(
.INIT(16'h4510))
\TX_WRITE_ADDRESS[7]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[6]),
.I3(TX_WRITE_ADDRESS[7]),
.O(\TX_WRITE_ADDRESS[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h51550400))
\TX_WRITE_ADDRESS[8]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[6]),
.I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I3(TX_WRITE_ADDRESS[7]),
.I4(TX_WRITE_ADDRESS[8]),
.O(\TX_WRITE_ADDRESS[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h5515555500400000))
\TX_WRITE_ADDRESS[9]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[8]),
.I2(TX_WRITE_ADDRESS[7]),
.I3(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I4(TX_WRITE_ADDRESS[6]),
.I5(TX_WRITE_ADDRESS[9]),
.O(\TX_WRITE_ADDRESS[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\TX_WRITE_ADDRESS[9]_i_2
(.I0(TX_WRITE_ADDRESS[4]),
.I1(TX_WRITE_ADDRESS[2]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[1]),
.I4(TX_WRITE_ADDRESS[3]),
.I5(TX_WRITE_ADDRESS[5]),
.O(\TX_WRITE_ADDRESS[9]_i_2_n_0 ));
FDRE \TX_WRITE_ADDRESS_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[0]),
.Q(TX_WRITE_ADDRESS_DEL[0]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[10]),
.Q(TX_WRITE_ADDRESS_DEL[10]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[1]),
.Q(TX_WRITE_ADDRESS_DEL[1]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[2]),
.Q(TX_WRITE_ADDRESS_DEL[2]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[3]),
.Q(TX_WRITE_ADDRESS_DEL[3]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[4]),
.Q(TX_WRITE_ADDRESS_DEL[4]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[5]),
.Q(TX_WRITE_ADDRESS_DEL[5]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[6]),
.Q(TX_WRITE_ADDRESS_DEL[6]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[7]),
.Q(TX_WRITE_ADDRESS_DEL[7]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[8]),
.Q(TX_WRITE_ADDRESS_DEL[8]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[9]),
.Q(TX_WRITE_ADDRESS_DEL[9]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[0]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[0]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[10]_i_2_n_0 ),
.Q(TX_WRITE_ADDRESS[10]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[1]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[1]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[2]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[2]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[3]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[3]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[4]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[4]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[5]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[5]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[6]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[6]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[7]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[7]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[8]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[8]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[9]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[9]),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'h20))
TX_WRITE_i_1
(.I0(S_TX_ACK_reg_n_0),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(TX_WRITE_i_1_n_0));
FDRE TX_WRITE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_i_1_n_0),
.Q(TX_WRITE),
.R(1'b0));
endmodule
module serial_output
(IN1_ACK,
RS232_TX_OBUF,
INTERNAL_RST_reg,
ETH_CLK_OBUF,
IN1_STB,
Q);
output IN1_ACK;
output RS232_TX_OBUF;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
input IN1_STB;
input [7:0]Q;
wire [11:0]BAUD_COUNT;
wire \BAUD_COUNT[11]_i_2__0_n_0 ;
wire \BAUD_COUNT[11]_i_3__0_n_0 ;
wire \BAUD_COUNT_reg[4]_i_2_n_0 ;
wire \BAUD_COUNT_reg[8]_i_2_n_0 ;
wire \BAUD_COUNT_reg_n_0_[0] ;
wire \BAUD_COUNT_reg_n_0_[10] ;
wire \BAUD_COUNT_reg_n_0_[11] ;
wire \BAUD_COUNT_reg_n_0_[1] ;
wire \BAUD_COUNT_reg_n_0_[2] ;
wire \BAUD_COUNT_reg_n_0_[3] ;
wire \BAUD_COUNT_reg_n_0_[4] ;
wire \BAUD_COUNT_reg_n_0_[5] ;
wire \BAUD_COUNT_reg_n_0_[6] ;
wire \BAUD_COUNT_reg_n_0_[7] ;
wire \BAUD_COUNT_reg_n_0_[8] ;
wire \BAUD_COUNT_reg_n_0_[9] ;
wire \DATA[7]_i_1_n_0 ;
wire \DATA_reg_n_0_[0] ;
wire ETH_CLK_OBUF;
wire \FSM_sequential_STATE[0]_i_1_n_0 ;
wire \FSM_sequential_STATE[1]_i_1_n_0 ;
wire \FSM_sequential_STATE[2]_i_1_n_0 ;
wire \FSM_sequential_STATE[3]_i_1_n_0 ;
wire \FSM_sequential_STATE[3]_i_2_n_0 ;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]Q;
wire RS232_TX_OBUF;
(* RTL_KEEP = "yes" *) wire [3:0]STATE;
wire S_IN1_ACK1;
wire S_IN1_ACK_i_1_n_0;
wire TX_i_1_n_0;
wire TX_i_3_n_0;
wire TX_i_4_n_0;
wire TX_i_5_n_0;
wire TX_i_6_n_0;
wire TX_reg_i_2_n_0;
wire X16CLK_EN_i_1__0_n_0;
wire X16CLK_EN_reg_n_0;
wire [11:1]data0;
wire p_0_in;
wire p_1_in;
wire p_2_in;
wire p_3_in;
wire p_4_in;
wire p_5_in;
wire p_6_in;
wire [3:0]\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\BAUD_COUNT[0]_i_1
(.I0(\BAUD_COUNT_reg_n_0_[0] ),
.O(BAUD_COUNT[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[10]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[10]),
.O(BAUD_COUNT[10]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[11]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[11]),
.O(BAUD_COUNT[11]));
LUT6 #(
.INIT(64'hFFFFFEFFFFFFFFFF))
\BAUD_COUNT[11]_i_2__0
(.I0(\BAUD_COUNT_reg_n_0_[10] ),
.I1(\BAUD_COUNT_reg_n_0_[9] ),
.I2(\BAUD_COUNT_reg_n_0_[6] ),
.I3(\BAUD_COUNT_reg_n_0_[7] ),
.I4(\BAUD_COUNT_reg_n_0_[11] ),
.I5(\BAUD_COUNT_reg_n_0_[5] ),
.O(\BAUD_COUNT[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFDFFF))
\BAUD_COUNT[11]_i_3__0
(.I0(\BAUD_COUNT_reg_n_0_[8] ),
.I1(\BAUD_COUNT_reg_n_0_[1] ),
.I2(\BAUD_COUNT_reg_n_0_[4] ),
.I3(\BAUD_COUNT_reg_n_0_[0] ),
.I4(\BAUD_COUNT_reg_n_0_[2] ),
.I5(\BAUD_COUNT_reg_n_0_[3] ),
.O(\BAUD_COUNT[11]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[1]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[1]),
.O(BAUD_COUNT[1]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[2]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[2]),
.O(BAUD_COUNT[2]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[3]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[3]),
.O(BAUD_COUNT[3]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[4]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[4]),
.O(BAUD_COUNT[4]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[5]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[5]),
.O(BAUD_COUNT[5]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[6]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[6]),
.O(BAUD_COUNT[6]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[7]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[7]),
.O(BAUD_COUNT[7]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[8]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[8]),
.O(BAUD_COUNT[8]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[9]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[9]),
.O(BAUD_COUNT[9]));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[0]),
.Q(\BAUD_COUNT_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[10]),
.Q(\BAUD_COUNT_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[11]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[11]),
.Q(\BAUD_COUNT_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[11]_i_4
(.CI(\BAUD_COUNT_reg[8]_i_2_n_0 ),
.CO(\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),
.S({1'b0,\BAUD_COUNT_reg_n_0_[11] ,\BAUD_COUNT_reg_n_0_[10] ,\BAUD_COUNT_reg_n_0_[9] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[1]),
.Q(\BAUD_COUNT_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[2]),
.Q(\BAUD_COUNT_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[3]),
.Q(\BAUD_COUNT_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[4]),
.Q(\BAUD_COUNT_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[4]_i_2
(.CI(1'b0),
.CO({\BAUD_COUNT_reg[4]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\BAUD_COUNT_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[4:1]),
.S({\BAUD_COUNT_reg_n_0_[4] ,\BAUD_COUNT_reg_n_0_[3] ,\BAUD_COUNT_reg_n_0_[2] ,\BAUD_COUNT_reg_n_0_[1] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[5]),
.Q(\BAUD_COUNT_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[6]),
.Q(\BAUD_COUNT_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[7]),
.Q(\BAUD_COUNT_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[8]),
.Q(\BAUD_COUNT_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[8]_i_2
(.CI(\BAUD_COUNT_reg[4]_i_2_n_0 ),
.CO({\BAUD_COUNT_reg[8]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[8:5]),
.S({\BAUD_COUNT_reg_n_0_[8] ,\BAUD_COUNT_reg_n_0_[7] ,\BAUD_COUNT_reg_n_0_[6] ,\BAUD_COUNT_reg_n_0_[5] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[9]),
.Q(\BAUD_COUNT_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h0000000000001000))
\DATA[7]_i_1
(.I0(STATE[1]),
.I1(STATE[3]),
.I2(IN1_ACK),
.I3(IN1_STB),
.I4(STATE[2]),
.I5(STATE[0]),
.O(\DATA[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\DATA_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[0]),
.Q(\DATA_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[1]),
.Q(p_6_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[2]),
.Q(p_5_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[3]),
.Q(p_4_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[4]),
.Q(p_3_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[5]),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[6]),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[7]),
.Q(p_0_in),
.R(1'b0));
LUT3 #(
.INIT(8'h07))
\FSM_sequential_STATE[0]_i_1
(.I0(STATE[2]),
.I1(STATE[3]),
.I2(STATE[0]),
.O(\FSM_sequential_STATE[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h152A))
\FSM_sequential_STATE[1]_i_1
(.I0(STATE[0]),
.I1(STATE[2]),
.I2(STATE[3]),
.I3(STATE[1]),
.O(\FSM_sequential_STATE[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0078))
\FSM_sequential_STATE[2]_i_1
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[2]),
.I3(STATE[3]),
.O(\FSM_sequential_STATE[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0F00FF010F00FE00))
\FSM_sequential_STATE[3]_i_1
(.I0(STATE[0]),
.I1(STATE[1]),
.I2(STATE[2]),
.I3(X16CLK_EN_reg_n_0),
.I4(STATE[3]),
.I5(S_IN1_ACK1),
.O(\FSM_sequential_STATE[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0870))
\FSM_sequential_STATE[3]_i_2
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[3]),
.I3(STATE[2]),
.O(\FSM_sequential_STATE[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\FSM_sequential_STATE[3]_i_3
(.I0(IN1_ACK),
.I1(IN1_STB),
.O(S_IN1_ACK1));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[0]_i_1_n_0 ),
.Q(STATE[0]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[1]_i_1_n_0 ),
.Q(STATE[1]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[2]_i_1_n_0 ),
.Q(STATE[2]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[3]_i_2_n_0 ),
.Q(STATE[3]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFFD00000003))
S_IN1_ACK_i_1
(.I0(IN1_STB),
.I1(STATE[1]),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[0]),
.I5(IN1_ACK),
.O(S_IN1_ACK_i_1_n_0));
FDRE #(
.INIT(1'b0))
S_IN1_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_IN1_ACK_i_1_n_0),
.Q(IN1_ACK),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFAAAABA00AAAA8A))
TX_i_1
(.I0(TX_reg_i_2_n_0),
.I1(STATE[1]),
.I2(STATE[0]),
.I3(STATE[3]),
.I4(STATE[2]),
.I5(RS232_TX_OBUF),
.O(TX_i_1_n_0));
LUT6 #(
.INIT(64'h0AC0FFFF0AC00000))
TX_i_3
(.I0(p_4_in),
.I1(p_0_in),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[1]),
.I5(TX_i_5_n_0),
.O(TX_i_3_n_0));
LUT6 #(
.INIT(64'h0AFCFFFF0AFC0000))
TX_i_4
(.I0(p_3_in),
.I1(\DATA_reg_n_0_[0] ),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[1]),
.I5(TX_i_6_n_0),
.O(TX_i_4_n_0));
LUT4 #(
.INIT(16'h0ACF))
TX_i_5
(.I0(p_6_in),
.I1(p_2_in),
.I2(STATE[3]),
.I3(STATE[2]),
.O(TX_i_5_n_0));
LUT4 #(
.INIT(16'h30BB))
TX_i_6
(.I0(p_5_in),
.I1(STATE[2]),
.I2(p_1_in),
.I3(STATE[3]),
.O(TX_i_6_n_0));
FDSE #(
.INIT(1'b1))
TX_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_i_1_n_0),
.Q(RS232_TX_OBUF),
.S(INTERNAL_RST_reg));
MUXF7 TX_reg_i_2
(.I0(TX_i_3_n_0),
.I1(TX_i_4_n_0),
.O(TX_reg_i_2_n_0),
.S(STATE[0]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h1))
X16CLK_EN_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.O(X16CLK_EN_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
X16CLK_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(X16CLK_EN_i_1__0_n_0),
.Q(X16CLK_EN_reg_n_0),
.R(INTERNAL_RST_reg));
endmodule
module user_design
(E,
\PWM_VAL_reg[7] ,
\PWM_VAL_reg[7]_0 ,
OUT1_ACK,
output_led_r,
output_led_g,
output_led_b,
output_rs232_tx,
IN1_STB,
INTERNAL_RST_reg,
OUT1,
ETH_CLK_OBUF,
OUT1_STB,
IN1_ACK);
output [0:0]E;
output [0:0]\PWM_VAL_reg[7] ;
output [0:0]\PWM_VAL_reg[7]_0 ;
output OUT1_ACK;
output [7:0]output_led_r;
output [7:0]output_led_g;
output [7:0]output_led_b;
output [7:0]output_rs232_tx;
output IN1_STB;
input INTERNAL_RST_reg;
input [7:0]OUT1;
input ETH_CLK_OBUF;
input OUT1_STB;
input IN1_ACK;
wire [0:0]E;
wire ETH_CLK_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]OUT1;
wire OUT1_ACK;
wire OUT1_STB;
wire [0:0]\PWM_VAL_reg[7] ;
wire [0:0]\PWM_VAL_reg[7]_0 ;
wire main_0_139931285810784_n_4;
wire [7:0]output_led_b;
wire [7:0]output_led_g;
wire [7:0]output_led_r;
wire [7:0]output_rs232_tx;
wire \s_output_rs232_tx_stb[0]_i_1_n_0 ;
main_0 main_0_139931285810784
(.E(E),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg),
.OUT1(OUT1),
.OUT1_ACK(OUT1_ACK),
.OUT1_STB(OUT1_STB),
.\PWM_VAL_reg[7] (\PWM_VAL_reg[7] ),
.\PWM_VAL_reg[7]_0 (\PWM_VAL_reg[7]_0 ),
.S_IN1_ACK_reg(\s_output_rs232_tx_stb[0]_i_1_n_0 ),
.output_led_b(output_led_b),
.output_led_g(output_led_g),
.output_led_r(output_led_r),
.output_rs232_tx(output_rs232_tx),
.\s_output_rs232_tx_reg[7]_0 (main_0_139931285810784_n_4));
LUT3 #(
.INIT(8'h7C))
\s_output_rs232_tx_stb[0]_i_1
(.I0(IN1_ACK),
.I1(main_0_139931285810784_n_4),
.I2(IN1_STB),
.O(\s_output_rs232_tx_stb[0]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// File : ../RTL/hostController/sendpacketcheckpreamble.v
// Generated : 11/10/06 05:37:21
// From : ../RTL/hostController/sendpacketcheckpreamble.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// sendpacketcheckpreamble
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbConstants_h.v"
module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
input clk;
input preAmbleEnable;
input rst;
input [3:0] sendPacketCPPID;
input sendPacketCPWEn;
input sendPacketRdy;
output sendPacketCPReady;
output [3:0] sendPacketPID;
output sendPacketWEn;
wire clk;
wire preAmbleEnable;
wire rst;
wire [3:0] sendPacketCPPID;
reg sendPacketCPReady, next_sendPacketCPReady;
wire sendPacketCPWEn;
reg [3:0] sendPacketPID, next_sendPacketPID;
wire sendPacketRdy;
reg sendPacketWEn, next_sendPacketWEn;
// BINARY ENCODED state machine: sendPktCP
// State codes definitions:
`define SPC_WAIT_EN 4'b0000
`define START_SPC 4'b0001
`define CHK_PREAM 4'b0010
`define PREAM_PKT_SND_PREAM 4'b0011
`define PREAM_PKT_WAIT_RDY1 4'b0100
`define PREAM_PKT_PREAM_SENT 4'b0101
`define PREAM_PKT_SND_PID 4'b0110
`define PREAM_PKT_PID_SENT 4'b0111
`define REG_PKT_SEND_PID 4'b1000
`define REG_PKT_WAIT_RDY1 4'b1001
`define REG_PKT_WAIT_RDY 4'b1010
`define READY 4'b1011
`define PREAM_PKT_WAIT_RDY2 4'b1100
`define PREAM_PKT_WAIT_RDY3 4'b1101
reg [3:0] CurrState_sendPktCP;
reg [3:0] NextState_sendPktCP;
//--------------------------------------------------------------------
// Machine: sendPktCP
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
begin : sendPktCP_NextState
NextState_sendPktCP <= CurrState_sendPktCP;
// Set default values for outputs and signals
next_sendPacketCPReady <= sendPacketCPReady;
next_sendPacketWEn <= sendPacketWEn;
next_sendPacketPID <= sendPacketPID;
case (CurrState_sendPktCP)
`SPC_WAIT_EN:
if (sendPacketCPWEn == 1'b1)
begin
NextState_sendPktCP <= `CHK_PREAM;
next_sendPacketCPReady <= 1'b0;
end
`START_SPC:
NextState_sendPktCP <= `SPC_WAIT_EN;
`CHK_PREAM:
if (preAmbleEnable == 1'b1 && sendPacketCPPID != `SOF)
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
else
NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
`READY:
begin
next_sendPacketCPReady <= 1'b1;
NextState_sendPktCP <= `SPC_WAIT_EN;
end
`PREAM_PKT_SND_PREAM:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= `PREAMBLE;
NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
end
`PREAM_PKT_WAIT_RDY1:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
`PREAM_PKT_PREAM_SENT:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
end
`PREAM_PKT_SND_PID:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= sendPacketCPPID;
NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
end
`PREAM_PKT_PID_SENT:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
end
`PREAM_PKT_WAIT_RDY2:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `PREAM_PKT_SND_PID;
`PREAM_PKT_WAIT_RDY3:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `READY;
`REG_PKT_SEND_PID:
begin
next_sendPacketWEn <= 1'b1;
next_sendPacketPID <= sendPacketCPPID;
NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
end
`REG_PKT_WAIT_RDY1:
if (sendPacketRdy == 1'b1)
NextState_sendPktCP <= `REG_PKT_SEND_PID;
`REG_PKT_WAIT_RDY:
begin
next_sendPacketWEn <= 1'b0;
NextState_sendPktCP <= `READY;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sendPktCP_CurrentState
if (rst)
CurrState_sendPktCP <= `START_SPC;
else
CurrState_sendPktCP <= NextState_sendPktCP;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sendPktCP_RegOutput
if (rst)
begin
sendPacketWEn <= 1'b0;
sendPacketPID <= 4'b0;
sendPacketCPReady <= 1'b1;
end
else
begin
sendPacketWEn <= next_sendPacketWEn;
sendPacketPID <= next_sendPacketPID;
sendPacketCPReady <= next_sendPacketCPReady;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_MS__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:35:35 05/12/2015
// Design Name:
// Module Name: exin
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module exin(CCLK,rst,instr,IF
);
input CCLK,rst;
input [31:0] instr;
output reg [7:0] IF;
always @(*)
begin
if (rst)
IF=8'd0;
else
case(instr[31:26])
6'b000000:
begin
case(instr[5:0])
6'b100000:
begin
IF=(|instr[15:11])?8'd1:8'h0;//add 01
end
6'b100001:IF=8'd2;//addui 02
6'b100010:IF=8'd3;//sub 03
6'b100011:IF=8'd4;//subu 04
6'b100100:IF=8'd5;//and 05
6'b100101:IF=8'd6;//or 06
6'b100110:IF=8'd7;//xor 07
6'b100111:IF=8'd8;//nor 08
6'b101010:IF=8'd9;//slt 09
6'b101011:IF=8'd10;//sltu 0a
6'b000000:IF=8'd11;//sll 0b
6'b000010:IF=8'd12;//srl 0c
6'b000011:IF=8'd13;//sra 0d
6'b000100:IF=8'd14;//sllv 0e
6'b000110:IF=8'd15;//srlv 0f
6'b000111:IF=8'd16;//srav 10
6'b001000:IF=8'd17;//jr 11
endcase
end
6'b001000:IF=8'd18;//addi 12
6'b001001:IF=8'd19;//addui 13
6'b001100:IF=8'd20;//andi 14
6'b001101:IF=8'd20;//ori 15
6'b001110:IF=8'd22;//xori 16
6'b001111:IF=8'd23;//lui 17
6'b100011:IF=8'd24;//lw 18
6'b101011:IF=8'd25;//sw 19
6'b000100:IF=8'd26;//beq 1a
6'b000101:IF=8'd27;//bne 1b
6'b001010:IF=8'd28;//slti 1c
6'b001011:IF=8'd29;//sltiu 1d
6'b000010:IF=8'd30;//j 1e
6'b000011:IF=8'd31;//jal 1f
default:IF=8'd0;
endcase
end
endmodule
//module exin(CCLK,rst,instr,IF
// );
// input CCLK,rst;
// input [31:0] instr;
// output reg [7:0] IF;
// always @(*)
// begin
// if (rst)
// IF=8'd0;
// else
// case(instr[31:26])
// 6'b000000:
// begin
// case(instr[5:0])
// 6'b100000:
// begin
// IF=(|instr[15:11])?8'd1:8'd0;
// end
// 6'b100010:IF=8'd2;
// 6'b100100:IF=8'd3;
// 6'b100101:IF=8'd4;
// 6'b000000:IF=8'd5;
// 6'b000010:IF=8'd6;
// 6'b000011:IF=8'd7;
// endcase
// end
// 6'b001000:IF=8'd8;
// 6'b001100:IF=8'd9;
// 6'b001101:IF=8'd10;
// 6'b100011:IF=8'd11;
// 6'b101011:IF=8'd12;
// 6'b000100:IF=8'd13;
// 6'b000101:IF=8'd14;
// 6'b000010:IF=8'd15;
// default:IF=8'd0;
// endcase
// end
//endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKBUF_PP_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_PP_SYMBOL_V
|
/*
* Copyright (C) 2015 Xiongfei Guo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License, version 3
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program. If not, see
* <http://www.gnu.org/licenses/>.
*
*
* Send a pulse from one domain to another timing domain.
*
* NOTE: the pulse must be one cycle and cannot be set again when busy_o is
* high.
*/
module xdom_pulse_sender (
input grst_i,
input odom_clk_i,
input odom_pulse_i,
input xdom_clk_i,
output xdom_pulse_o,
output busy_o,
output err_o
);
/* signals in origin domain */
reg odom_pulse_delay_r;
reg odom_pulse_keeper_r;
reg [1:0] odom_feedback_double_flips_r ;
reg err_r;
reg odom_pulse_gen_r;
/* cross-domain signals */
wire xdom_pulse_en;
wire odom_pulse_safe_cancel;
/* signals in cross domain */
reg [1:0] xdom_double_flips_r ;
reg xdom_pulse_en_delay_r ;
reg xdom_pulse_gen_r ;
/* latch input pulse for one cycle */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_delay_r <= 1'b0;
else
odom_pulse_delay_r <= odom_pulse_i;
/* detect pos-edge of odm_pulse_i */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_gen_r <= 1'b0;
else if ((odom_pulse_i == 1'b1) && (odom_pulse_delay_r == 1'b0))
odom_pulse_gen_r <= 1'b1;
else
odom_pulse_gen_r <= 1'b0;
/* keep input pulse signal until feedback signal cancel it */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_keeper_r <= 1'b0;
else if (odom_pulse_keeper_r == 1'b0 && (odom_pulse_gen_r == 1'b1))
odom_pulse_keeper_r <= 1'b1;
else if (odom_pulse_keeper_r == 1'b1 && odom_pulse_safe_cancel == 1'b1)
odom_pulse_keeper_r <= 1'b0;
else
odom_pulse_keeper_r <= odom_pulse_keeper_r;
/* busy signal */
assign busy_o = odom_pulse_keeper_r | odom_pulse_i | odom_pulse_safe_cancel;
/* a new request must wait until last is finished */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
err_r <= 1'b0;
else
err_r <= (odom_pulse_keeper_r == 1'b1) && (odom_pulse_i == 1'b1);
assign err_o = err_r;
/* double flips in cross-domain */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_double_flips_r <= 2'b0;
else
xdom_double_flips_r <= {odom_pulse_keeper_r, xdom_double_flips_r[1]};
assign xdom_pulse_en = xdom_double_flips_r[0];
/* double flips in origin-domain */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_feedback_double_flips_r <= 2'b0;
else
odom_feedback_double_flips_r <= {xdom_pulse_en, odom_feedback_double_flips_r[1]};
assign odom_pulse_safe_cancel = odom_feedback_double_flips_r[0];
/* latch cross domain pulse enable signal for one cycle. */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_pulse_en_delay_r <= 1'b0;
else
xdom_pulse_en_delay_r <= xdom_pulse_en;
/* generate pulse in cross-domain */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_pulse_gen_r <= 1'b0;
else if (xdom_pulse_en == 1'b1 && xdom_pulse_en_delay_r == 1'b0)
xdom_pulse_gen_r <= 1'b1;
else
xdom_pulse_gen_r <= 1'b0;
assign xdom_pulse_o = xdom_pulse_gen_r;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream asynchronous FIFO (64 bit datapath)
*/
module axis_async_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
/*
* AXI input
*/
input wire input_clk,
input wire input_rst,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
input wire output_rst,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1;
reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray[ADDR_WIDTH] != rd_ptr_gray_sync2[ADDR_WIDTH]) &&
(wr_ptr_gray[ADDR_WIDTH-1] != rd_ptr_gray_sync2[ADDR_WIDTH-1]) &&
(wr_ptr_gray[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray == wr_ptr_gray_sync2;
wire write = input_axis_tvalid & ~full;
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_out_reg;
assign input_axis_tready = ~full;
assign output_axis_tvalid = output_axis_tvalid_reg;
// reset synchronization
always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
input_rst_sync1 <= 1;
input_rst_sync2 <= 1;
end else begin
input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1;
end
end
always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
output_rst_sync1 <= 1;
output_rst_sync2 <= 1;
end else begin
output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1;
end
end
// write
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
end else if (write) begin
mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_next = wr_ptr + 1;
wr_ptr <= wr_ptr_next;
wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0;
end else begin
rd_ptr_gray_sync1 <= rd_ptr_gray;
rd_ptr_gray_sync2 <= rd_ptr_gray_sync1;
end
end
// read
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;
rd_ptr <= rd_ptr_next;
rd_ptr_gray <= rd_ptr_next ^ (rd_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0;
end else begin
wr_ptr_gray_sync1 <= wr_ptr_gray;
wr_ptr_gray_sync2 <= wr_ptr_gray_sync1;
end
end
// source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_rq_tag.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Tag Queue
// Top level Module: jbi_min_rq_rhq_tag
// Where Instantiated: jbi_min_rq
//
// Description: This block tracks 16 entries of tag and wait info bits for a
// corresponding queue entry. If a tag is the oldest tag in jbi,
// the wait bit is cleared.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_rq_tag(/*AUTOARG*/
// Outputs
c_tag_byps_out,
// Inputs
clk, rst_l, cpu_clk, cpu_rst_l, cpu_rx_en, wrtrk_oldest_wri_tag,
raddr, tag_byps_in, tag_in, csn_wr, waddr
);
input clk;
input rst_l;
input cpu_clk;
input cpu_rst_l;
input cpu_rx_en;
//cpu_clk
input [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_oldest_wri_tag;
input [3:0] raddr;
//jbus clk
input tag_byps_in;
input [`JBI_WRI_TAG_WIDTH-1:0] tag_in;
input csn_wr;
input [3:0] waddr;
output c_tag_byps_out;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
reg c_tag_byps_out;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire tag0_byps_ff;
wire tag1_byps_ff;
wire tag2_byps_ff;
wire tag3_byps_ff;
wire tag4_byps_ff;
wire tag5_byps_ff;
wire tag6_byps_ff;
wire tag7_byps_ff;
wire tag8_byps_ff;
wire tag9_byps_ff;
wire tag10_byps_ff;
wire tag11_byps_ff;
wire tag12_byps_ff;
wire tag13_byps_ff;
wire tag14_byps_ff;
wire tag15_byps_ff;
wire tag0_cs_wr;
wire tag1_cs_wr;
wire tag2_cs_wr;
wire tag3_cs_wr;
wire tag4_cs_wr;
wire tag5_cs_wr;
wire tag6_cs_wr;
wire tag7_cs_wr;
wire tag8_cs_wr;
wire tag9_cs_wr;
wire tag10_cs_wr;
wire tag11_cs_wr;
wire tag12_cs_wr;
wire tag13_cs_wr;
wire tag14_cs_wr;
wire tag15_cs_wr;
wire tag_byps_in_ff;
wire [`JBI_WRI_TAG_WIDTH-1:0] tag_in_ff;
wire csn_wr_ff;
wire [3:0] waddr_ff;
wire c_tag_byps_in;
wire [`JBI_WRI_TAG_WIDTH-1:0] c_tag_in;
wire c_csn_wr;
wire [3:0] c_waddr;
//
// Code start here
//
//*******************************************************************************
// Write - CPU Clk
//*******************************************************************************
assign tag0_cs_wr = ~c_csn_wr & c_waddr == 4'd0;
assign tag1_cs_wr = ~c_csn_wr & c_waddr == 4'd1;
assign tag2_cs_wr = ~c_csn_wr & c_waddr == 4'd2;
assign tag3_cs_wr = ~c_csn_wr & c_waddr == 4'd3;
assign tag4_cs_wr = ~c_csn_wr & c_waddr == 4'd4;
assign tag5_cs_wr = ~c_csn_wr & c_waddr == 4'd5;
assign tag6_cs_wr = ~c_csn_wr & c_waddr == 4'd6;
assign tag7_cs_wr = ~c_csn_wr & c_waddr == 4'd7;
assign tag8_cs_wr = ~c_csn_wr & c_waddr == 4'd8;
assign tag9_cs_wr = ~c_csn_wr & c_waddr == 4'd9;
assign tag10_cs_wr = ~c_csn_wr & c_waddr == 4'd10;
assign tag11_cs_wr = ~c_csn_wr & c_waddr == 4'd11;
assign tag12_cs_wr = ~c_csn_wr & c_waddr == 4'd12;
assign tag13_cs_wr = ~c_csn_wr & c_waddr == 4'd13;
assign tag14_cs_wr = ~c_csn_wr & c_waddr == 4'd14;
assign tag15_cs_wr = ~c_csn_wr & c_waddr == 4'd15;
//*******************************************************************************
// Read - CPU clk
//*******************************************************************************
always @ ( /*AUTOSENSE*/raddr or tag0_byps_ff or tag10_byps_ff
or tag11_byps_ff or tag12_byps_ff or tag13_byps_ff
or tag14_byps_ff or tag15_byps_ff or tag1_byps_ff
or tag2_byps_ff or tag3_byps_ff or tag4_byps_ff
or tag5_byps_ff or tag6_byps_ff or tag7_byps_ff
or tag8_byps_ff or tag9_byps_ff) begin
case(raddr)
4'd0: c_tag_byps_out = tag0_byps_ff;
4'd1: c_tag_byps_out = tag1_byps_ff;
4'd2: c_tag_byps_out = tag2_byps_ff;
4'd3: c_tag_byps_out = tag3_byps_ff;
4'd4: c_tag_byps_out = tag4_byps_ff;
4'd5: c_tag_byps_out = tag5_byps_ff;
4'd6: c_tag_byps_out = tag6_byps_ff;
4'd7: c_tag_byps_out = tag7_byps_ff;
4'd8: c_tag_byps_out = tag8_byps_ff;
4'd9: c_tag_byps_out = tag9_byps_ff;
4'd10: c_tag_byps_out = tag10_byps_ff;
4'd11: c_tag_byps_out = tag11_byps_ff;
4'd12: c_tag_byps_out = tag12_byps_ff;
4'd13: c_tag_byps_out = tag13_byps_ff;
4'd14: c_tag_byps_out = tag14_byps_ff;
4'd15: c_tag_byps_out = tag15_byps_ff;
// CoverMeter line_off
default: c_tag_byps_out = 1'bx;
// CoverMeter line_on
endcase
end
//*******************************************************************************
// Tag Slice Instantiation
//*******************************************************************************
/* jbi_min_rq_tag_slice AUTO_TEMPLATE (
.tag_cs_wr (tag@_cs_wr),
.tag_byps_ff (tag@_byps_ff),
); */
jbi_min_rq_tag_slice u_rq_tag0 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag0_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag0_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag1 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag1_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag1_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag2 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag2_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag2_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag3 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag3_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag3_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag4 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag4_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag4_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag5 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag5_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag5_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag6 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag6_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag6_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag7 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag7_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag7_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag8 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag8_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag8_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag9 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag9_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag9_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag10 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag10_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag10_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag11 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag11_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag11_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag12 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag12_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag12_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag13 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag13_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag13_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag14 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag14_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag14_cs_wr)); // Templated
jbi_min_rq_tag_slice u_rq_tag15 (/*AUTOINST*/
// Outputs
.tag_byps_ff(tag15_byps_ff), // Templated
// Inputs
.cpu_clk(cpu_clk),
.cpu_rst_l(cpu_rst_l),
.wrtrk_oldest_wri_tag(wrtrk_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.c_tag_byps_in(c_tag_byps_in),
.c_tag_in(c_tag_in[`JBI_WRI_TAG_WIDTH-1:0]),
.tag_cs_wr(tag15_cs_wr)); // Templated
//*******************************************************************************
// Synchronization DFFRLEs
//*******************************************************************************
//----------------------
// JBUS -> CPU
//----------------------
// waddr
dffrl_ns #(4) u_dffrl_waddr_ff
(.din(waddr),
.clk(clk),
.rst_l(rst_l),
.q(waddr_ff)
);
dffrle_ns #(4) u_dffrle_c_waddr
(.din(waddr_ff),
.clk(cpu_clk),
.en(cpu_rx_en),
.rst_l(cpu_rst_l),
.q(c_waddr)
);
// csn_wr
dffrl_ns #(1) u_dffrl_csn_wr_ff
(.din(csn_wr),
.clk(clk),
.rst_l(rst_l),
.q(csn_wr_ff)
);
dffrle_ns #(1) u_dffrle_c_csn_wr
(.din(csn_wr_ff),
.clk(cpu_clk),
.en(cpu_rx_en),
.rst_l(cpu_rst_l),
.q(c_csn_wr)
);
// tag_in
dffrl_ns #(`JBI_WRI_TAG_WIDTH) u_dffrl_tag_in_ff
(.din(tag_in),
.clk(clk),
.rst_l(rst_l),
.q(tag_in_ff)
);
dffrle_ns #(`JBI_WRI_TAG_WIDTH) u_dffrle_c_tag_in
(.din(tag_in_ff),
.clk(cpu_clk),
.en(cpu_rx_en),
.rst_l(cpu_rst_l),
.q(c_tag_in)
);
// tag_byps_in
dffrl_ns #(1) u_dffrl_tag_byps_in_ff
(.din(tag_byps_in),
.clk(clk),
.rst_l(rst_l),
.q(tag_byps_in_ff)
);
dffrle_ns #(1) u_dffrle_c_tag_byps_in
(.din(tag_byps_in_ff),
.clk(cpu_clk),
.en(cpu_rx_en),
.rst_l(cpu_rst_l),
.q(c_tag_byps_in)
);
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_111x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_111x256 (
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input clock;
input [110:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [110:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire [110:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [7:0] usedw = sub_wire1[7:0];
wire empty = sub_wire2;
wire [110:0] q = sub_wire3[110:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 240,
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 111,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "240"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "111"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "111"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "240"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "111"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 111 0 INPUT NODEFVAL data[110..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 111 0 OUTPUT NODEFVAL q[110..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 111 0 data 0 0 111 0
// Retrieval info: CONNECT: q 0 0 111 0 @q 0 0 111 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_111x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_111x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_111x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_111x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_111x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_111x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_111x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_111x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2015 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 64-Deep 8-bit Read 1-bit Write Multi Port RAM
// /___/ /\ Filename : RAM64X8SW.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 11/09/15 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM64X8SW #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [63:0] INIT_E = 64'h0000000000000000,
parameter [63:0] INIT_F = 64'h0000000000000000,
parameter [63:0] INIT_G = 64'h0000000000000000,
parameter [63:0] INIT_H = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output [7:0] O,
input [5:0] A,
input D,
input WCLK,
input WE,
input [2:0] WSEL
);
// define constants
localparam MODULE_NAME = "RAM64X8SW";
`ifdef XIL_TIMING
wire [5:0] A_dly;
wire D_dly;
wire WCLK_dly;
wire WE_dly;
wire [2:0] WSEL_dly;
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
reg [63:0] mem_a, mem_b, mem_c, mem_d;
reg [63:0] mem_e, mem_f, mem_g, mem_h;
reg [7:0] O_out;
assign O = O_out;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
mem_e = INIT_E;
mem_f = INIT_F;
mem_g = INIT_G;
mem_h = INIT_H;
#100;
O_out = {mem_a[A], mem_b[A], mem_c[A], mem_d[A], mem_e[A], mem_f[A], mem_g[A], mem_h[A]};
end
generate if (IS_WCLK_INVERTED == 1'b0) begin : write_block
`ifdef XIL_TIMING
always @(posedge WCLK_dly)
if ((WE === 1'bz) || WE_dly) begin
case (WSEL_dly)
3'b111: begin
if (mem_a[A_dly] !== D_dly) mem_a[A_dly] <= D_dly;
end
3'b110: begin
if (mem_b[A_dly] !== D_dly) mem_b[A_dly] <= D_dly;
end
3'b101: begin
if (mem_c[A_dly] !== D_dly) mem_c[A_dly] <= D_dly;
end
3'b100: begin
if (mem_d[A_dly] !== D_dly) mem_d[A_dly] <= D_dly;
end
3'b011: begin
if (mem_e[A_dly] !== D_dly) mem_e[A_dly] <= D_dly;
end
3'b010: begin
if (mem_f[A_dly] !== D_dly) mem_f[A_dly] <= D_dly;
end
3'b001: begin
if (mem_g[A_dly] !== D_dly) mem_g[A_dly] <= D_dly;
end
3'b000: begin
if (mem_h[A_dly] !== D_dly) mem_h[A_dly] <= D_dly;
end
endcase
end
`else
always @(posedge WCLK)
if ((WE === 1'bz) || WE) begin
case (WSEL)
3'b111: begin
if (mem_a[A] !== D) mem_a[A] <= D;
end
3'b110: begin
if (mem_b[A] !== D) mem_b[A] <= D;
end
3'b101: begin
if (mem_c[A] !== D) mem_c[A] <= D;
end
3'b100: begin
if (mem_d[A] !== D) mem_d[A] <= D;
end
3'b011: begin
if (mem_e[A] !== D) mem_e[A] <= D;
end
3'b010: begin
if (mem_f[A] !== D) mem_f[A] <= D;
end
3'b001: begin
if (mem_g[A] !== D) mem_g[A] <= D;
end
3'b000: begin
if (mem_h[A] !== D) mem_h[A] <= D;
end
endcase
end
`endif
end else begin : write_block
`ifdef XIL_TIMING
always @(negedge WCLK_dly)
if ((WE === 1'bz) || WE_dly) begin
case (WSEL_dly)
3'b111: begin
if (mem_a[A_dly] !== D_dly) mem_a[A_dly] <= D_dly;
end
3'b110: begin
if (mem_b[A_dly] !== D_dly) mem_b[A_dly] <= D_dly;
end
3'b101: begin
if (mem_c[A_dly] !== D_dly) mem_c[A_dly] <= D_dly;
end
3'b100: begin
if (mem_d[A_dly] !== D_dly) mem_d[A_dly] <= D_dly;
end
3'b011: begin
if (mem_e[A_dly] !== D_dly) mem_e[A_dly] <= D_dly;
end
3'b010: begin
if (mem_f[A_dly] !== D_dly) mem_f[A_dly] <= D_dly;
end
3'b001: begin
if (mem_g[A_dly] !== D_dly) mem_g[A_dly] <= D_dly;
end
3'b000: begin
if (mem_h[A_dly] !== D_dly) mem_h[A_dly] <= D_dly;
end
endcase
end
`else
always @(negedge WCLK)
if ((WE === 1'bz) || WE) begin
case (WSEL)
3'b111: begin
if (mem_a[A] !== D) mem_a[A] <= D;
end
3'b110: begin
if (mem_b[A] !== D) mem_b[A] <= D;
end
3'b101: begin
if (mem_c[A] !== D) mem_c[A] <= D;
end
3'b100: begin
if (mem_d[A] !== D) mem_d[A] <= D;
end
3'b011: begin
if (mem_e[A] !== D) mem_e[A] <= D;
end
3'b010: begin
if (mem_f[A] !== D) mem_f[A] <= D;
end
3'b001: begin
if (mem_g[A] !== D) mem_g[A] <= D;
end
3'b000: begin
if (mem_h[A] !== D) mem_h[A] <= D;
end
endcase
end
`endif
end
endgenerate
`ifdef XIL_TIMING
always @ (mem_a[A_dly] or A_dly) begin
if (O_out[7] !== mem_a[A_dly]) O_out[7] = mem_a[A_dly];
end
always @ (mem_b[A_dly] or A_dly) begin
if (O_out[6] !== mem_b[A_dly]) O_out[6] = mem_b[A_dly];
end
always @ (mem_c[A_dly] or A_dly) begin
if (O_out[5] !== mem_c[A_dly]) O_out[5] = mem_c[A_dly];
end
always @ (mem_d[A_dly] or A_dly) begin
if (O_out[4] !== mem_d[A_dly]) O_out[4] = mem_d[A_dly];
end
always @ (mem_e[A_dly] or A_dly) begin
if (O_out[3] !== mem_e[A_dly]) O_out[3] = mem_e[A_dly];
end
always @ (mem_f[A_dly] or A_dly) begin
if (O_out[2] !== mem_f[A_dly]) O_out[2] = mem_f[A_dly];
end
always @ (mem_g[A_dly] or A_dly) begin
if (O_out[1] !== mem_g[A_dly]) O_out[1] = mem_g[A_dly];
end
always @ (mem_h[A_dly] or A_dly) begin
if (O_out[0] !== mem_h[A_dly]) O_out[0] = mem_h[A_dly];
end
`else
always @ (mem_a[A] or A) begin
if (O_out[7] !== mem_a[A]) O_out[7] = mem_a[A];
end
always @ (mem_b[A] or A) begin
if (O_out[6] !== mem_b[A]) O_out[6] = mem_b[A];
end
always @ (mem_c[A] or A) begin
if (O_out[5] !== mem_c[A]) O_out[5] = mem_c[A];
end
always @ (mem_d[A] or A) begin
if (O_out[4] !== mem_d[A]) O_out[4] = mem_d[A];
end
always @ (mem_e[A] or A) begin
if (O_out[3] !== mem_e[A]) O_out[3] = mem_e[A];
end
always @ (mem_f[A] or A) begin
if (O_out[2] !== mem_f[A]) O_out[2] = mem_f[A];
end
always @ (mem_g[A] or A) begin
if (O_out[1] !== mem_g[A]) O_out[1] = mem_g[A];
end
always @ (mem_h[A] or A) begin
if (O_out[0] !== mem_h[A]) O_out[0] = mem_h[A];
end
`endif
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[A_dly] <= 1'bx;
mem_b[A_dly] <= 1'bx;
mem_c[A_dly] <= 1'bx;
mem_d[A_dly] <= 1'bx;
mem_e[A_dly] <= 1'bx;
mem_f[A_dly] <= 1'bx;
mem_g[A_dly] <= 1'bx;
mem_h[A_dly] <= 1'bx;
end
`endif
// end behavioral model
`ifdef XIL_TIMING
wire sh_clk_en_p;
wire sh_clk_en_n;
assign sh_clk_en_p = ~IS_WCLK_INVERTED;
assign sh_clk_en_n = IS_WCLK_INVERTED;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign sh_we_clk_en_p = (WE || (WE === 1'bz)) && ~IS_WCLK_INVERTED;
assign sh_we_clk_en_n = (WE || (WE === 1'bz)) && IS_WCLK_INVERTED;
`endif
specify
(WCLK *> O) = (100:100:100, 100:100:100);
(A *> O) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WSEL[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[0]);
$setuphold (negedge WCLK, negedge WSEL[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[1]);
$setuphold (negedge WCLK, negedge WSEL[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[2]);
$setuphold (negedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge WSEL[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[0]);
$setuphold (negedge WCLK, posedge WSEL[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[1]);
$setuphold (negedge WCLK, posedge WSEL[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[2]);
$setuphold (posedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WSEL[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[0]);
$setuphold (posedge WCLK, negedge WSEL[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[1]);
$setuphold (posedge WCLK, negedge WSEL[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[2]);
$setuphold (posedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge WSEL[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[0]);
$setuphold (posedge WCLK, posedge WSEL[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[1]);
$setuphold (posedge WCLK, posedge WSEL[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,WSEL_dly[2]);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This simple write master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post writes until the length register
reaches zero. When the length register reaches zero the 'done' bit is asserted.
To use this master you must simply drive the control signals into this block,
and also write the data to the exposed write FIFO. To read from the exposed FIFO
use the 'user_write_buffer' signal to push data into the FIFO 'user_buffer_data'.
The signal 'user_buffer_full' is asserted whenever the exposed buffer is full.
You should not attempt to write data to the exposed FIFO if it is full.
*/
// altera message_off 10230
module write_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
// user logic inputs and outputs
user_write_buffer,
user_buffer_data,
user_buffer_full,
// master inputs and outputs
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location; // this only makes sense to enable when MAXBURSTCOUNT = 1
input [ADDRESSWIDTH-1:0] control_write_base;
input [ADDRESSWIDTH-1:0] control_write_length;
input control_go;
output wire control_done;
// user logic inputs and outputs
input user_write_buffer;
input [DATAWIDTH-1:0] user_buffer_data;
output wire user_buffer_full;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_write;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [DATAWIDTH-1:0] master_writedata;
// internal control signals
reg control_fixed_location_d1;
reg [ADDRESSWIDTH-1:0] address; // this increments for each word
reg [ADDRESSWIDTH-1:0] length;
wire increment_address; // this increments the 'address' register when write is asserted and waitrequest is de-asserted
wire read_fifo;
wire user_buffer_empty;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master word increment counter
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if (control_go == 1)
begin
address <= control_write_base;
end
else if ((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if (control_go == 1)
begin
length <= control_write_length;
end
else if (increment_address == 1)
begin
length <= length - BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign control_done = (length == 0);
assign master_write = (user_buffer_empty == 0) & (control_done == 0);
assign increment_address = (user_buffer_empty == 0) & (master_waitrequest == 0) & (control_done == 0);
assign read_fifo = increment_address;
// write data feed by user logic
scfifo the_user_to_master_fifo (
.aclr (reset),
.clock (clk),
.data (user_buffer_data),
.full (user_buffer_full),
.empty (user_buffer_empty),
.q (master_writedata),
.rdreq (read_fifo),
.wrreq (user_write_buffer)
);
defparam the_user_to_master_fifo.lpm_width = DATAWIDTH;
defparam the_user_to_master_fifo.lpm_widthu = FIFODEPTH_LOG2; //Deepak
defparam the_user_to_master_fifo.lpm_numwords = FIFODEPTH;
defparam the_user_to_master_fifo.lpm_showahead = "ON";
defparam the_user_to_master_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_user_to_master_fifo.add_ram_output_register = "OFF";
defparam the_user_to_master_fifo.underflow_checking = "OFF";
defparam the_user_to_master_fifo.overflow_checking = "OFF";
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O2BB2AI_BEHAVIORAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_1_V
`define SKY130_FD_SC_LP__DLRBP_1_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_1_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 13
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_auto_pc_2 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_13_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/* Generated by Yosys 0.5+ (git sha1 ba4cce9, gcc 4.8.4-2ubuntu1~14.04 -O2 -fstack-protector -fPIC -Os) */
module \$paramod\SERIAL_TO_PARALLEL\SIZE=32 (serial_in, enable_stp, SD_CLK, RESET_L, reception_complete, parallel_out);
wire [8:0] _000_;
wire [31:0] _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
input RESET_L;
input SD_CLK;
wire [8:0] contador;
input enable_stp;
output [31:0] parallel_out;
output reception_complete;
input serial_in;
NOT _238_ (
.A(RESET_L),
.Y(_003_)
);
NOT _239_ (
.A(enable_stp),
.Y(_004_)
);
NAND _240_ (
.A(_004_),
.B(reception_complete),
.Y(_005_)
);
NOR _241_ (
.A(contador[8]),
.B(contador[7]),
.Y(_006_)
);
NAND _242_ (
.A(_006_),
.B(contador[5]),
.Y(_007_)
);
NOR _243_ (
.A(contador[1]),
.B(contador[0]),
.Y(_008_)
);
NOT _244_ (
.A(contador[2]),
.Y(_009_)
);
NOT _245_ (
.A(contador[3]),
.Y(_010_)
);
NAND _246_ (
.A(_010_),
.B(_009_),
.Y(_011_)
);
NOT _247_ (
.A(contador[4]),
.Y(_012_)
);
NOT _248_ (
.A(contador[6]),
.Y(_013_)
);
NAND _249_ (
.A(_013_),
.B(_012_),
.Y(_014_)
);
NOR _250_ (
.A(_014_),
.B(_011_),
.Y(_015_)
);
NAND _251_ (
.A(_015_),
.B(_008_),
.Y(_016_)
);
NOR _252_ (
.A(_016_),
.B(_007_),
.Y(_017_)
);
NAND _253_ (
.A(_017_),
.B(enable_stp),
.Y(_018_)
);
NAND _254_ (
.A(_018_),
.B(_005_),
.Y(_002_)
);
NOT _255_ (
.A(parallel_out[1]),
.Y(_019_)
);
NOR _256_ (
.A(_017_),
.B(_019_),
.Y(_020_)
);
NOT _257_ (
.A(parallel_out[0]),
.Y(_022_)
);
NOT _258_ (
.A(_007_),
.Y(_024_)
);
NOT _259_ (
.A(_008_),
.Y(_026_)
);
NOR _260_ (
.A(contador[3]),
.B(contador[2]),
.Y(_028_)
);
NOR _261_ (
.A(contador[6]),
.B(contador[4]),
.Y(_030_)
);
NAND _262_ (
.A(_030_),
.B(_028_),
.Y(_032_)
);
NOR _263_ (
.A(_032_),
.B(_026_),
.Y(_034_)
);
NAND _264_ (
.A(_034_),
.B(_024_),
.Y(_036_)
);
NOR _265_ (
.A(_036_),
.B(_022_),
.Y(_038_)
);
NOR _266_ (
.A(_038_),
.B(_020_),
.Y(_040_)
);
NOR _267_ (
.A(_040_),
.B(_004_),
.Y(_001_[0])
);
NOT _268_ (
.A(parallel_out[2]),
.Y(_043_)
);
NOR _269_ (
.A(_017_),
.B(_043_),
.Y(_045_)
);
NOR _270_ (
.A(_036_),
.B(_019_),
.Y(_047_)
);
NOR _271_ (
.A(_047_),
.B(_045_),
.Y(_049_)
);
NOR _272_ (
.A(_049_),
.B(_004_),
.Y(_001_[1])
);
NOT _273_ (
.A(parallel_out[3]),
.Y(_052_)
);
NOR _274_ (
.A(_017_),
.B(_052_),
.Y(_054_)
);
NOR _275_ (
.A(_036_),
.B(_043_),
.Y(_056_)
);
NOR _276_ (
.A(_056_),
.B(_054_),
.Y(_058_)
);
NOR _277_ (
.A(_058_),
.B(_004_),
.Y(_001_[2])
);
NOT _278_ (
.A(parallel_out[4]),
.Y(_061_)
);
NOR _279_ (
.A(_017_),
.B(_061_),
.Y(_063_)
);
NOR _280_ (
.A(_036_),
.B(_052_),
.Y(_065_)
);
NOR _281_ (
.A(_065_),
.B(_063_),
.Y(_067_)
);
NOR _282_ (
.A(_067_),
.B(_004_),
.Y(_001_[3])
);
NOT _283_ (
.A(parallel_out[5]),
.Y(_070_)
);
NOR _284_ (
.A(_017_),
.B(_070_),
.Y(_072_)
);
NOR _285_ (
.A(_036_),
.B(_061_),
.Y(_074_)
);
NOR _286_ (
.A(_074_),
.B(_072_),
.Y(_076_)
);
NOR _287_ (
.A(_076_),
.B(_004_),
.Y(_001_[4])
);
NOT _288_ (
.A(parallel_out[6]),
.Y(_079_)
);
NOR _289_ (
.A(_017_),
.B(_079_),
.Y(_081_)
);
NOR _290_ (
.A(_036_),
.B(_070_),
.Y(_083_)
);
NOR _291_ (
.A(_083_),
.B(_081_),
.Y(_085_)
);
NOR _292_ (
.A(_085_),
.B(_004_),
.Y(_001_[5])
);
NOT _293_ (
.A(parallel_out[7]),
.Y(_088_)
);
NOR _294_ (
.A(_017_),
.B(_088_),
.Y(_090_)
);
NOR _295_ (
.A(_036_),
.B(_079_),
.Y(_092_)
);
NOR _296_ (
.A(_092_),
.B(_090_),
.Y(_094_)
);
NOR _297_ (
.A(_094_),
.B(_004_),
.Y(_001_[6])
);
NOT _298_ (
.A(parallel_out[8]),
.Y(_096_)
);
NOR _299_ (
.A(_017_),
.B(_096_),
.Y(_097_)
);
NOR _300_ (
.A(_036_),
.B(_088_),
.Y(_098_)
);
NOR _301_ (
.A(_098_),
.B(_097_),
.Y(_099_)
);
NOR _302_ (
.A(_099_),
.B(_004_),
.Y(_001_[7])
);
NOT _303_ (
.A(parallel_out[9]),
.Y(_100_)
);
NOR _304_ (
.A(_017_),
.B(_100_),
.Y(_101_)
);
NOR _305_ (
.A(_036_),
.B(_096_),
.Y(_102_)
);
NOR _306_ (
.A(_102_),
.B(_101_),
.Y(_103_)
);
NOR _307_ (
.A(_103_),
.B(_004_),
.Y(_001_[8])
);
NOT _308_ (
.A(parallel_out[10]),
.Y(_104_)
);
NOR _309_ (
.A(_017_),
.B(_104_),
.Y(_105_)
);
NOR _310_ (
.A(_036_),
.B(_100_),
.Y(_106_)
);
NOR _311_ (
.A(_106_),
.B(_105_),
.Y(_107_)
);
NOR _312_ (
.A(_107_),
.B(_004_),
.Y(_001_[9])
);
NOT _313_ (
.A(parallel_out[11]),
.Y(_108_)
);
NOR _314_ (
.A(_017_),
.B(_108_),
.Y(_109_)
);
NOR _315_ (
.A(_036_),
.B(_104_),
.Y(_110_)
);
NOR _316_ (
.A(_110_),
.B(_109_),
.Y(_111_)
);
NOR _317_ (
.A(_111_),
.B(_004_),
.Y(_001_[10])
);
NOT _318_ (
.A(parallel_out[12]),
.Y(_112_)
);
NOR _319_ (
.A(_017_),
.B(_112_),
.Y(_113_)
);
NOR _320_ (
.A(_036_),
.B(_108_),
.Y(_114_)
);
NOR _321_ (
.A(_114_),
.B(_113_),
.Y(_115_)
);
NOR _322_ (
.A(_115_),
.B(_004_),
.Y(_001_[11])
);
NOT _323_ (
.A(parallel_out[13]),
.Y(_116_)
);
NOR _324_ (
.A(_017_),
.B(_116_),
.Y(_117_)
);
NOR _325_ (
.A(_036_),
.B(_112_),
.Y(_118_)
);
NOR _326_ (
.A(_118_),
.B(_117_),
.Y(_119_)
);
NOR _327_ (
.A(_119_),
.B(_004_),
.Y(_001_[12])
);
NOT _328_ (
.A(parallel_out[14]),
.Y(_120_)
);
NOR _329_ (
.A(_017_),
.B(_120_),
.Y(_121_)
);
NOR _330_ (
.A(_036_),
.B(_116_),
.Y(_122_)
);
NOR _331_ (
.A(_122_),
.B(_121_),
.Y(_123_)
);
NOR _332_ (
.A(_123_),
.B(_004_),
.Y(_001_[13])
);
NOT _333_ (
.A(parallel_out[15]),
.Y(_124_)
);
NOR _334_ (
.A(_017_),
.B(_124_),
.Y(_125_)
);
NOR _335_ (
.A(_036_),
.B(_120_),
.Y(_126_)
);
NOR _336_ (
.A(_126_),
.B(_125_),
.Y(_127_)
);
NOR _337_ (
.A(_127_),
.B(_004_),
.Y(_001_[14])
);
NOT _338_ (
.A(parallel_out[16]),
.Y(_128_)
);
NOR _339_ (
.A(_017_),
.B(_128_),
.Y(_129_)
);
NOR _340_ (
.A(_036_),
.B(_124_),
.Y(_130_)
);
NOR _341_ (
.A(_130_),
.B(_129_),
.Y(_131_)
);
NOR _342_ (
.A(_131_),
.B(_004_),
.Y(_001_[15])
);
NOT _343_ (
.A(parallel_out[17]),
.Y(_132_)
);
NOR _344_ (
.A(_017_),
.B(_132_),
.Y(_133_)
);
NOR _345_ (
.A(_036_),
.B(_128_),
.Y(_134_)
);
NOR _346_ (
.A(_134_),
.B(_133_),
.Y(_135_)
);
NOR _347_ (
.A(_135_),
.B(_004_),
.Y(_001_[16])
);
NOT _348_ (
.A(parallel_out[18]),
.Y(_136_)
);
NOR _349_ (
.A(_017_),
.B(_136_),
.Y(_137_)
);
NOR _350_ (
.A(_036_),
.B(_132_),
.Y(_138_)
);
NOR _351_ (
.A(_138_),
.B(_137_),
.Y(_139_)
);
NOR _352_ (
.A(_139_),
.B(_004_),
.Y(_001_[17])
);
NOT _353_ (
.A(parallel_out[19]),
.Y(_140_)
);
NOR _354_ (
.A(_017_),
.B(_140_),
.Y(_141_)
);
NOR _355_ (
.A(_036_),
.B(_136_),
.Y(_142_)
);
NOR _356_ (
.A(_142_),
.B(_141_),
.Y(_143_)
);
NOR _357_ (
.A(_143_),
.B(_004_),
.Y(_001_[18])
);
NOT _358_ (
.A(parallel_out[20]),
.Y(_144_)
);
NOR _359_ (
.A(_017_),
.B(_144_),
.Y(_145_)
);
NOR _360_ (
.A(_036_),
.B(_140_),
.Y(_146_)
);
NOR _361_ (
.A(_146_),
.B(_145_),
.Y(_147_)
);
NOR _362_ (
.A(_147_),
.B(_004_),
.Y(_001_[19])
);
NOT _363_ (
.A(parallel_out[21]),
.Y(_148_)
);
NOR _364_ (
.A(_017_),
.B(_148_),
.Y(_149_)
);
NOR _365_ (
.A(_036_),
.B(_144_),
.Y(_150_)
);
NOR _366_ (
.A(_150_),
.B(_149_),
.Y(_151_)
);
NOR _367_ (
.A(_151_),
.B(_004_),
.Y(_001_[20])
);
NOT _368_ (
.A(parallel_out[22]),
.Y(_152_)
);
NOR _369_ (
.A(_017_),
.B(_152_),
.Y(_153_)
);
NOR _370_ (
.A(_036_),
.B(_148_),
.Y(_154_)
);
NOR _371_ (
.A(_154_),
.B(_153_),
.Y(_155_)
);
NOR _372_ (
.A(_155_),
.B(_004_),
.Y(_001_[21])
);
NOT _373_ (
.A(parallel_out[23]),
.Y(_156_)
);
NOR _374_ (
.A(_017_),
.B(_156_),
.Y(_157_)
);
NOR _375_ (
.A(_036_),
.B(_152_),
.Y(_158_)
);
NOR _376_ (
.A(_158_),
.B(_157_),
.Y(_159_)
);
NOR _377_ (
.A(_159_),
.B(_004_),
.Y(_001_[22])
);
NOT _378_ (
.A(parallel_out[24]),
.Y(_160_)
);
NOR _379_ (
.A(_017_),
.B(_160_),
.Y(_161_)
);
NOR _380_ (
.A(_036_),
.B(_156_),
.Y(_162_)
);
NOR _381_ (
.A(_162_),
.B(_161_),
.Y(_163_)
);
NOR _382_ (
.A(_163_),
.B(_004_),
.Y(_001_[23])
);
NOT _383_ (
.A(parallel_out[25]),
.Y(_164_)
);
NOR _384_ (
.A(_017_),
.B(_164_),
.Y(_165_)
);
NOR _385_ (
.A(_036_),
.B(_160_),
.Y(_166_)
);
NOR _386_ (
.A(_166_),
.B(_165_),
.Y(_167_)
);
NOR _387_ (
.A(_167_),
.B(_004_),
.Y(_001_[24])
);
NOT _388_ (
.A(parallel_out[26]),
.Y(_168_)
);
NOR _389_ (
.A(_017_),
.B(_168_),
.Y(_169_)
);
NOR _390_ (
.A(_036_),
.B(_164_),
.Y(_170_)
);
NOR _391_ (
.A(_170_),
.B(_169_),
.Y(_171_)
);
NOR _392_ (
.A(_171_),
.B(_004_),
.Y(_001_[25])
);
NOT _393_ (
.A(parallel_out[27]),
.Y(_172_)
);
NOR _394_ (
.A(_017_),
.B(_172_),
.Y(_173_)
);
NOR _395_ (
.A(_036_),
.B(_168_),
.Y(_174_)
);
NOR _396_ (
.A(_174_),
.B(_173_),
.Y(_175_)
);
NOR _397_ (
.A(_175_),
.B(_004_),
.Y(_001_[26])
);
NOT _398_ (
.A(parallel_out[28]),
.Y(_176_)
);
NOR _399_ (
.A(_017_),
.B(_176_),
.Y(_177_)
);
NOR _400_ (
.A(_036_),
.B(_172_),
.Y(_178_)
);
NOR _401_ (
.A(_178_),
.B(_177_),
.Y(_179_)
);
NOR _402_ (
.A(_179_),
.B(_004_),
.Y(_001_[27])
);
NOT _403_ (
.A(parallel_out[29]),
.Y(_180_)
);
NOR _404_ (
.A(_017_),
.B(_180_),
.Y(_181_)
);
NOR _405_ (
.A(_036_),
.B(_176_),
.Y(_182_)
);
NOR _406_ (
.A(_182_),
.B(_181_),
.Y(_183_)
);
NOR _407_ (
.A(_183_),
.B(_004_),
.Y(_001_[28])
);
NOT _408_ (
.A(parallel_out[30]),
.Y(_184_)
);
NOR _409_ (
.A(_017_),
.B(_184_),
.Y(_185_)
);
NOR _410_ (
.A(_036_),
.B(_180_),
.Y(_186_)
);
NOR _411_ (
.A(_186_),
.B(_185_),
.Y(_187_)
);
NOR _412_ (
.A(_187_),
.B(_004_),
.Y(_001_[29])
);
NOT _413_ (
.A(parallel_out[31]),
.Y(_188_)
);
NOR _414_ (
.A(_017_),
.B(_188_),
.Y(_189_)
);
NOR _415_ (
.A(_036_),
.B(_184_),
.Y(_190_)
);
NOR _416_ (
.A(_190_),
.B(_189_),
.Y(_191_)
);
NOR _417_ (
.A(_191_),
.B(_004_),
.Y(_001_[30])
);
NOT _418_ (
.A(serial_in),
.Y(_192_)
);
NOR _419_ (
.A(_017_),
.B(_192_),
.Y(_193_)
);
NOR _420_ (
.A(_036_),
.B(_188_),
.Y(_194_)
);
NOR _421_ (
.A(_194_),
.B(_193_),
.Y(_195_)
);
NOR _422_ (
.A(_195_),
.B(_004_),
.Y(_001_[31])
);
NAND _423_ (
.A(contador[0]),
.B(_004_),
.Y(_196_)
);
NOR _424_ (
.A(_017_),
.B(contador[0]),
.Y(_197_)
);
NAND _425_ (
.A(_197_),
.B(enable_stp),
.Y(_198_)
);
NAND _426_ (
.A(_198_),
.B(_196_),
.Y(_000_[0])
);
NOT _427_ (
.A(contador[0]),
.Y(_199_)
);
NOT _428_ (
.A(contador[1]),
.Y(_200_)
);
NOR _429_ (
.A(_200_),
.B(_199_),
.Y(_201_)
);
NOR _430_ (
.A(_201_),
.B(_008_),
.Y(_202_)
);
NOR _431_ (
.A(_202_),
.B(_004_),
.Y(_203_)
);
NOR _432_ (
.A(contador[1]),
.B(enable_stp),
.Y(_204_)
);
NOR _433_ (
.A(_204_),
.B(_203_),
.Y(_000_[1])
);
NAND _434_ (
.A(_201_),
.B(enable_stp),
.Y(_205_)
);
NOR _435_ (
.A(_205_),
.B(_009_),
.Y(_206_)
);
NAND _436_ (
.A(contador[1]),
.B(contador[0]),
.Y(_207_)
);
NOR _437_ (
.A(_207_),
.B(_004_),
.Y(_208_)
);
NOR _438_ (
.A(_208_),
.B(contador[2]),
.Y(_209_)
);
NOR _439_ (
.A(_209_),
.B(_206_),
.Y(_000_[2])
);
NOR _440_ (
.A(_206_),
.B(contador[3]),
.Y(_210_)
);
NAND _441_ (
.A(contador[3]),
.B(contador[2]),
.Y(_211_)
);
NOR _442_ (
.A(_211_),
.B(_205_),
.Y(_212_)
);
NOR _443_ (
.A(_212_),
.B(_210_),
.Y(_000_[3])
);
NOR _444_ (
.A(_212_),
.B(contador[4]),
.Y(_213_)
);
NOT _445_ (
.A(_211_),
.Y(_214_)
);
NAND _446_ (
.A(_214_),
.B(_208_),
.Y(_215_)
);
NOR _447_ (
.A(_215_),
.B(_012_),
.Y(_216_)
);
NOR _448_ (
.A(_216_),
.B(_213_),
.Y(_000_[4])
);
NOR _449_ (
.A(_216_),
.B(contador[5]),
.Y(_217_)
);
NAND _450_ (
.A(_216_),
.B(contador[5]),
.Y(_218_)
);
NAND _451_ (
.A(_218_),
.B(_018_),
.Y(_219_)
);
NOR _452_ (
.A(_219_),
.B(_217_),
.Y(_000_[5])
);
NAND _453_ (
.A(_218_),
.B(contador[6]),
.Y(_220_)
);
NOT _454_ (
.A(contador[5]),
.Y(_221_)
);
NAND _455_ (
.A(_212_),
.B(contador[4]),
.Y(_222_)
);
NOR _456_ (
.A(_222_),
.B(_221_),
.Y(_223_)
);
NAND _457_ (
.A(_223_),
.B(_013_),
.Y(_224_)
);
NAND _458_ (
.A(_224_),
.B(_220_),
.Y(_000_[6])
);
NOT _459_ (
.A(contador[7]),
.Y(_225_)
);
NOR _460_ (
.A(_211_),
.B(_207_),
.Y(_226_)
);
NAND _461_ (
.A(contador[6]),
.B(contador[4]),
.Y(_227_)
);
NAND _462_ (
.A(contador[5]),
.B(enable_stp),
.Y(_228_)
);
NOR _463_ (
.A(_228_),
.B(_227_),
.Y(_229_)
);
NAND _464_ (
.A(_229_),
.B(_226_),
.Y(_230_)
);
NOR _465_ (
.A(_230_),
.B(_225_),
.Y(_231_)
);
NOT _466_ (
.A(_230_),
.Y(_232_)
);
NOR _467_ (
.A(_232_),
.B(contador[7]),
.Y(_233_)
);
NOR _468_ (
.A(_233_),
.B(_231_),
.Y(_000_[7])
);
NOR _469_ (
.A(_231_),
.B(contador[8]),
.Y(_234_)
);
NOT _470_ (
.A(contador[8]),
.Y(_235_)
);
NOT _471_ (
.A(_231_),
.Y(_236_)
);
NOR _472_ (
.A(_236_),
.B(_235_),
.Y(_237_)
);
NOR _473_ (
.A(_237_),
.B(_234_),
.Y(_000_[8])
);
BUF _474_ (
.A(_003_),
.Y(_021_)
);
BUF _475_ (
.A(_003_),
.Y(_023_)
);
BUF _476_ (
.A(_003_),
.Y(_025_)
);
BUF _477_ (
.A(_003_),
.Y(_027_)
);
BUF _478_ (
.A(_003_),
.Y(_029_)
);
BUF _479_ (
.A(_003_),
.Y(_031_)
);
BUF _480_ (
.A(_003_),
.Y(_033_)
);
BUF _481_ (
.A(_003_),
.Y(_035_)
);
BUF _482_ (
.A(_003_),
.Y(_037_)
);
BUF _483_ (
.A(_003_),
.Y(_039_)
);
BUF _484_ (
.A(_003_),
.Y(_041_)
);
BUF _485_ (
.A(_003_),
.Y(_042_)
);
BUF _486_ (
.A(_003_),
.Y(_044_)
);
BUF _487_ (
.A(_003_),
.Y(_046_)
);
BUF _488_ (
.A(_003_),
.Y(_048_)
);
BUF _489_ (
.A(_003_),
.Y(_050_)
);
BUF _490_ (
.A(_003_),
.Y(_051_)
);
BUF _491_ (
.A(_003_),
.Y(_053_)
);
BUF _492_ (
.A(_003_),
.Y(_055_)
);
BUF _493_ (
.A(_003_),
.Y(_057_)
);
BUF _494_ (
.A(_003_),
.Y(_059_)
);
BUF _495_ (
.A(_003_),
.Y(_060_)
);
BUF _496_ (
.A(_003_),
.Y(_062_)
);
BUF _497_ (
.A(_003_),
.Y(_064_)
);
BUF _498_ (
.A(_003_),
.Y(_066_)
);
BUF _499_ (
.A(_003_),
.Y(_068_)
);
BUF _500_ (
.A(_003_),
.Y(_069_)
);
BUF _501_ (
.A(_003_),
.Y(_071_)
);
BUF _502_ (
.A(_003_),
.Y(_073_)
);
BUF _503_ (
.A(_003_),
.Y(_075_)
);
BUF _504_ (
.A(_003_),
.Y(_077_)
);
BUF _505_ (
.A(_003_),
.Y(_078_)
);
BUF _506_ (
.A(_003_),
.Y(_080_)
);
BUF _507_ (
.A(_003_),
.Y(_082_)
);
BUF _508_ (
.A(_003_),
.Y(_084_)
);
BUF _509_ (
.A(_003_),
.Y(_086_)
);
BUF _510_ (
.A(_003_),
.Y(_087_)
);
BUF _511_ (
.A(_003_),
.Y(_089_)
);
BUF _512_ (
.A(_003_),
.Y(_091_)
);
BUF _513_ (
.A(_003_),
.Y(_093_)
);
BUF _514_ (
.A(_003_),
.Y(_095_)
);
DFFSR _515_ (
.C(SD_CLK),
.D(_002_),
.Q(reception_complete),
.R(_021_),
.S(1'b0)
);
DFFSR _516_ (
.C(SD_CLK),
.D(_001_[0]),
.Q(parallel_out[0]),
.R(_023_),
.S(1'b0)
);
DFFSR _517_ (
.C(SD_CLK),
.D(_001_[1]),
.Q(parallel_out[1]),
.R(_025_),
.S(1'b0)
);
DFFSR _518_ (
.C(SD_CLK),
.D(_001_[2]),
.Q(parallel_out[2]),
.R(_027_),
.S(1'b0)
);
DFFSR _519_ (
.C(SD_CLK),
.D(_001_[3]),
.Q(parallel_out[3]),
.R(_029_),
.S(1'b0)
);
DFFSR _520_ (
.C(SD_CLK),
.D(_001_[4]),
.Q(parallel_out[4]),
.R(_031_),
.S(1'b0)
);
DFFSR _521_ (
.C(SD_CLK),
.D(_001_[5]),
.Q(parallel_out[5]),
.R(_033_),
.S(1'b0)
);
DFFSR _522_ (
.C(SD_CLK),
.D(_001_[6]),
.Q(parallel_out[6]),
.R(_035_),
.S(1'b0)
);
DFFSR _523_ (
.C(SD_CLK),
.D(_001_[7]),
.Q(parallel_out[7]),
.R(_037_),
.S(1'b0)
);
DFFSR _524_ (
.C(SD_CLK),
.D(_001_[8]),
.Q(parallel_out[8]),
.R(_039_),
.S(1'b0)
);
DFFSR _525_ (
.C(SD_CLK),
.D(_001_[9]),
.Q(parallel_out[9]),
.R(_041_),
.S(1'b0)
);
DFFSR _526_ (
.C(SD_CLK),
.D(_001_[10]),
.Q(parallel_out[10]),
.R(_042_),
.S(1'b0)
);
DFFSR _527_ (
.C(SD_CLK),
.D(_001_[11]),
.Q(parallel_out[11]),
.R(_044_),
.S(1'b0)
);
DFFSR _528_ (
.C(SD_CLK),
.D(_001_[12]),
.Q(parallel_out[12]),
.R(_046_),
.S(1'b0)
);
DFFSR _529_ (
.C(SD_CLK),
.D(_001_[13]),
.Q(parallel_out[13]),
.R(_048_),
.S(1'b0)
);
DFFSR _530_ (
.C(SD_CLK),
.D(_001_[14]),
.Q(parallel_out[14]),
.R(_050_),
.S(1'b0)
);
DFFSR _531_ (
.C(SD_CLK),
.D(_001_[15]),
.Q(parallel_out[15]),
.R(_051_),
.S(1'b0)
);
DFFSR _532_ (
.C(SD_CLK),
.D(_001_[16]),
.Q(parallel_out[16]),
.R(_053_),
.S(1'b0)
);
DFFSR _533_ (
.C(SD_CLK),
.D(_001_[17]),
.Q(parallel_out[17]),
.R(_055_),
.S(1'b0)
);
DFFSR _534_ (
.C(SD_CLK),
.D(_001_[18]),
.Q(parallel_out[18]),
.R(_057_),
.S(1'b0)
);
DFFSR _535_ (
.C(SD_CLK),
.D(_001_[19]),
.Q(parallel_out[19]),
.R(_059_),
.S(1'b0)
);
DFFSR _536_ (
.C(SD_CLK),
.D(_001_[20]),
.Q(parallel_out[20]),
.R(_060_),
.S(1'b0)
);
DFFSR _537_ (
.C(SD_CLK),
.D(_001_[21]),
.Q(parallel_out[21]),
.R(_062_),
.S(1'b0)
);
DFFSR _538_ (
.C(SD_CLK),
.D(_001_[22]),
.Q(parallel_out[22]),
.R(_064_),
.S(1'b0)
);
DFFSR _539_ (
.C(SD_CLK),
.D(_001_[23]),
.Q(parallel_out[23]),
.R(_066_),
.S(1'b0)
);
DFFSR _540_ (
.C(SD_CLK),
.D(_001_[24]),
.Q(parallel_out[24]),
.R(_068_),
.S(1'b0)
);
DFFSR _541_ (
.C(SD_CLK),
.D(_001_[25]),
.Q(parallel_out[25]),
.R(_069_),
.S(1'b0)
);
DFFSR _542_ (
.C(SD_CLK),
.D(_001_[26]),
.Q(parallel_out[26]),
.R(_071_),
.S(1'b0)
);
DFFSR _543_ (
.C(SD_CLK),
.D(_001_[27]),
.Q(parallel_out[27]),
.R(_073_),
.S(1'b0)
);
DFFSR _544_ (
.C(SD_CLK),
.D(_001_[28]),
.Q(parallel_out[28]),
.R(_075_),
.S(1'b0)
);
DFFSR _545_ (
.C(SD_CLK),
.D(_001_[29]),
.Q(parallel_out[29]),
.R(_077_),
.S(1'b0)
);
DFFSR _546_ (
.C(SD_CLK),
.D(_001_[30]),
.Q(parallel_out[30]),
.R(_078_),
.S(1'b0)
);
DFFSR _547_ (
.C(SD_CLK),
.D(_001_[31]),
.Q(parallel_out[31]),
.R(_080_),
.S(1'b0)
);
DFFSR _548_ (
.C(SD_CLK),
.D(_000_[0]),
.Q(contador[0]),
.R(_082_),
.S(1'b0)
);
DFFSR _549_ (
.C(SD_CLK),
.D(_000_[1]),
.Q(contador[1]),
.R(_084_),
.S(1'b0)
);
DFFSR _550_ (
.C(SD_CLK),
.D(_000_[2]),
.Q(contador[2]),
.R(_086_),
.S(1'b0)
);
DFFSR _551_ (
.C(SD_CLK),
.D(_000_[3]),
.Q(contador[3]),
.R(_087_),
.S(1'b0)
);
DFFSR _552_ (
.C(SD_CLK),
.D(_000_[4]),
.Q(contador[4]),
.R(_089_),
.S(1'b0)
);
DFFSR _553_ (
.C(SD_CLK),
.D(_000_[5]),
.Q(contador[5]),
.R(_091_),
.S(1'b0)
);
DFFSR _554_ (
.C(SD_CLK),
.D(_000_[6]),
.Q(contador[6]),
.R(_093_),
.S(1'b0)
);
DFFSR _555_ (
.C(SD_CLK),
.D(_000_[7]),
.Q(contador[7]),
.R(_095_),
.S(1'b0)
);
DFFSR _556_ (
.C(SD_CLK),
.D(_000_[8]),
.Q(contador[8]),
.R(_003_),
.S(1'b0)
);
endmodule
module BloqueDATA(CLK, SD_CLK, RESET_L, timeout_Reg_Regs_DATA, writeRead_Regs_DATA, blockCount_Regs_DATA, multipleData_Regs_DATA, timeout_enable_Regs_DATA, FIFO_OK_FIFO_DATA, dataFromFIFO_FIFO_Phy, New_DAT_DMA_DATA, DATA_PIN_IN, writeFIFO_enable_Phy_FIFO, readFIFO_enable_Phy_FIFO, dataReadToFIFO_Phy_FIFO, transfer_complete_DATA_DMA, IO_enable_Phy_SD_CARD, DATA_PIN_OUT, pad_state_Phy_PAD, pad_enable_Phy_PAD);
input CLK;
input DATA_PIN_IN;
output DATA_PIN_OUT;
input FIFO_OK_FIFO_DATA;
output IO_enable_Phy_SD_CARD;
input New_DAT_DMA_DATA;
input RESET_L;
input SD_CLK;
wire ack_IN_Phy_DATA;
wire ack_OUT_DATA_Phy;
input [3:0] blockCount_Regs_DATA;
wire [3:0] blocks_DATA_Phy;
wire complete_Phy_DATA;
input [31:0] dataFromFIFO_FIFO_Phy;
wire [31:0] dataParallel_Phy_PS;
output [31:0] dataReadToFIFO_Phy_FIFO;
wire [31:0] data_read_SP_Phy;
wire enable_pts_Wrapper_Phy_PS;
wire enable_stp_Wrapper_Phy_SP;
wire idle_out_DATA_Phy;
input multipleData_Regs_DATA;
wire multiple_DATA_Phy;
output pad_enable_Phy_PAD;
output pad_state_Phy_PAD;
output readFIFO_enable_Phy_FIFO;
wire reception_complete_SP_Phy;
wire reset_Wrapper_Phy_PS;
wire serial_Ready_Phy_DATA;
wire strobe_OUT_DATA_Phy;
wire timeout_Phy_DATA;
input [15:0] timeout_Reg_Regs_DATA;
input timeout_enable_Regs_DATA;
wire [15:0] timeout_value_DATA_Phy;
output transfer_complete_DATA_DMA;
wire transmission_complete_PS_Phy;
output writeFIFO_enable_Phy_FIFO;
wire writeReadPhysical_DATA_Phy;
input writeRead_Regs_DATA;
DATA_PHYSICAL CapaFisica (
.IO_enable_Phy_SD_CARD(IO_enable_Phy_SD_CARD),
.RESET_L(RESET_L),
.SD_CLK(SD_CLK),
.ack_IN_DATA_Phy(ack_OUT_DATA_Phy),
.ack_OUT_Phy_DATA(ack_IN_Phy_DATA),
.blocks_DATA_Phy(blocks_DATA_Phy),
.complete_Phy_DATA(complete_Phy_DATA),
.dataFromFIFO_FIFO_Phy(dataFromFIFO_FIFO_Phy),
.dataParallel_Phy_PS(dataParallel_Phy_PS),
.dataReadToFIFO_Phy_FIFO(dataReadToFIFO_Phy_FIFO),
.data_read_SP_Phy(data_read_SP_Phy),
.data_timeout_Phy_DATA(timeout_Phy_DATA),
.enable_pts_Wrapper_Phy_PS(enable_pts_Wrapper_Phy_PS),
.enable_stp_Wrapper_Phy_SP(enable_stp_Wrapper_Phy_SP),
.idle_in_DATA_Phy(idle_out_DATA_Phy),
.multiple_DATA_Phy(multiple_DATA_Phy),
.pad_enable_Phy_PAD(pad_enable_Phy_PAD),
.pad_state_Phy_PAD(pad_state_Phy_PAD),
.readFIFO_enable_Phy_FIFO(readFIFO_enable_Phy_FIFO),
.reception_complete_SP_Phy(reception_complete_SP_Phy),
.reset_Wrapper_Phy_PS(reset_Wrapper_Phy_PS),
.serial_Ready_Phy_DATA(serial_Ready_Phy_DATA),
.strobe_IN_DATA_Phy(strobe_OUT_DATA_Phy),
.timeout_Reg_DATA_Phy(timeout_value_DATA_Phy),
.transmission_complete_PS_Phy(transmission_complete_PS_Phy),
.writeFIFO_enable_Phy_FIFO(writeFIFO_enable_Phy_FIFO),
.writeRead_DATA_Phy(writeReadPhysical_DATA_Phy)
);
DATA ControlDatos (
.CLK(CLK),
.RESET_L(RESET_L),
.ack_IN_Phy_DATA(ack_IN_Phy_DATA),
.ack_OUT_DATA_Phy(ack_OUT_DATA_Phy),
.blockCount_Regs_DATA(blockCount_Regs_DATA),
.blocks_DATA_Phy(blocks_DATA_Phy),
.complete_Phy_DATA(complete_Phy_DATA),
.fifo_OK_FIFO_DATA(FIFO_OK_FIFO_DATA),
.idle_out_DATA_Phy(idle_out_DATA_Phy),
.multipleData_Regs_DATA(multipleData_Regs_DATA),
.multiple_DATA_Phy(multiple_DATA_Phy),
.new_DAT_DMA_DATA(New_DAT_DMA_DATA),
.serial_Ready_Phy_DATA(serial_Ready_Phy_DATA),
.strobe_OUT_DATA_Phy(strobe_OUT_DATA_Phy),
.timeout_Enable_Regs_DATA(timeout_enable_Regs_DATA),
.timeout_Phy_DATA(timeout_Phy_DATA),
.timeout_Reg_Regs_DATA(timeout_Reg_Regs_DATA),
.timeout_value_DATA_Phy(timeout_value_DATA_Phy),
.transfer_complete_DATA_DMA(transfer_complete_DATA_DMA),
.writeReadPhysical_DATA_Phy(writeReadPhysical_DATA_Phy),
.writeRead_Regs_DATA(writeRead_Regs_DATA)
);
PARALLEL_TO_SERIAL convert_paralelo_serial (
.SD_CLK(SD_CLK),
.enable_pts(enable_pts_Wrapper_Phy_PS),
.parallel_complete(transmission_complete_PS_Phy),
.reset_pts(reset_Wrapper_Phy_PS),
.signal_in(dataParallel_Phy_PS),
.signal_out(DATA_PIN_OUT)
);
\$paramod\SERIAL_TO_PARALLEL\SIZE=32 convert_serial_paralelo (
.RESET_L(RESET_L),
.SD_CLK(SD_CLK),
.enable_stp(enable_stp_Wrapper_Phy_SP),
.parallel_out(data_read_SP_Phy),
.reception_complete(reception_complete_SP_Phy),
.serial_in(DATA_PIN_IN)
);
endmodule
module CMD(clk_host, reset_host, new_command, cmd_argument, cmd_index, cmd_complete, cmd_index_error, response, CMD_PIN_OUT, IO_enable_pin, CMD_PIN_IN, clk_SD);
input CMD_PIN_IN;
output CMD_PIN_OUT;
output IO_enable_pin;
wire ack_control_to_physical;
wire ack_physic_to_control;
input clk_SD;
input clk_host;
input [31:0] cmd_argument;
output cmd_complete;
input [5:0] cmd_index;
output cmd_index_error;
wire [39:0] cmd_out_control_to_pts;
wire end_parallel;
wire end_serializer;
wire idle_control_to_physical;
input new_command;
wire [135:0] pad_response;
wire physic_enable_pts;
wire physic_enable_stp;
wire physic_reset_pts;
wire physic_reset_stp;
input reset_host;
output [127:0] response;
wire [135:0] response_to_cmd_in;
wire strobe_control_to_physical;
wire strobe_physic_to_control;
cmd_control cmd_control1 (
.ack_in(ack_physic_to_control),
.ack_out(ack_control_to_physical),
.clk_host(clk_host),
.cmd_argument(cmd_argument),
.cmd_complete(cmd_complete),
.cmd_in(response_to_cmd_in),
.cmd_index(cmd_index),
.cmd_index_error(cmd_index_error),
.cmd_out(cmd_out_control_to_pts),
.idle_out(idle_control_to_physical),
.new_command(new_command),
.reset_host(reset_host),
.response(response),
.strobe_in(strobe_physic_to_control),
.strobe_out(strobe_control_to_physical)
);
control_capa_fisica control_capa_fisica1 (
.ack_in(ack_control_to_physical),
.ack_out(ack_physic_to_control),
.clk_SD(clk_SD),
.enable_pts(physic_enable_pts),
.enable_stp(physic_enable_stp),
.idle_in(idle_control_to_physical),
.load_send(IO_enable_pin),
.pad_response(pad_response),
.reception_complete(end_serializer),
.reset_host(reset_host),
.reset_pts(physic_reset_pts),
.reset_stp(physic_reset_stp),
.response(response_to_cmd_in),
.strobe_in(strobe_control_to_physical),
.strobe_out(strobe_physic_to_control),
.transmission_complete(end_parallel)
);
parallel_to_serial parallel_to_serial1 (
.clk_SD(clk_SD),
.enable_pts(physic_enable_pts),
.parallel_complete(end_parallel),
.reset_pts(physic_reset_pts),
.signal_in(cmd_out_control_to_pts),
.signal_out(CMD_PIN_OUT)
);
serial_to_parallel serial_to_parallel1 (
.clk_SD(clk_SD),
.command(cmd_out_control_to_pts),
.enable_stp(physic_enable_stp),
.reset_stp(physic_reset_stp),
.serial_complete(end_serializer),
.signal_in(CMD_PIN_IN),
.signal_out(pad_response)
);
endmodule
module DATA(CLK, RESET_L, writeRead_Regs_DATA, blockCount_Regs_DATA, multipleData_Regs_DATA, timeout_Enable_Regs_DATA, timeout_Reg_Regs_DATA, new_DAT_DMA_DATA, serial_Ready_Phy_DATA, timeout_Phy_DATA, complete_Phy_DATA, ack_IN_Phy_DATA, fifo_OK_FIFO_DATA, transfer_complete_DATA_DMA, strobe_OUT_DATA_Phy, ack_OUT_DATA_Phy, blocks_DATA_Phy, timeout_value_DATA_Phy, writeReadPhysical_DATA_Phy, multiple_DATA_Phy, idle_out_DATA_Phy);
wire _0_;
input CLK;
input RESET_L;
wire STATE;
input ack_IN_Phy_DATA;
output ack_OUT_DATA_Phy;
input [3:0] blockCount_Regs_DATA;
output [3:0] blocks_DATA_Phy;
input complete_Phy_DATA;
input fifo_OK_FIFO_DATA;
output idle_out_DATA_Phy;
input multipleData_Regs_DATA;
output multiple_DATA_Phy;
input new_DAT_DMA_DATA;
input serial_Ready_Phy_DATA;
output strobe_OUT_DATA_Phy;
input timeout_Enable_Regs_DATA;
input timeout_Phy_DATA;
input [15:0] timeout_Reg_Regs_DATA;
output [15:0] timeout_value_DATA_Phy;
output transfer_complete_DATA_DMA;
output writeReadPhysical_DATA_Phy;
input writeRead_Regs_DATA;
NOT _1_ (
.A(RESET_L),
.Y(_0_)
);
NOT _2_ (
.A(STATE),
.Y(idle_out_DATA_Phy)
);
DFF _3_ (
.C(CLK),
.D(_0_),
.Q(STATE)
);
\$_DLATCH_P_ _4_ (
.D(1'b0),
.E(STATE),
.Q(timeout_value_DATA_Phy[7])
);
assign ack_OUT_DATA_Phy = timeout_value_DATA_Phy[7];
assign blocks_DATA_Phy = { timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7] };
assign multiple_DATA_Phy = timeout_value_DATA_Phy[7];
assign strobe_OUT_DATA_Phy = timeout_value_DATA_Phy[7];
assign { timeout_value_DATA_Phy[15:8], timeout_value_DATA_Phy[6:0] } = { timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7], timeout_value_DATA_Phy[7] };
assign transfer_complete_DATA_DMA = timeout_value_DATA_Phy[7];
assign writeReadPhysical_DATA_Phy = timeout_value_DATA_Phy[7];
endmodule
module DATA_PHYSICAL(SD_CLK, RESET_L, strobe_IN_DATA_Phy, ack_IN_DATA_Phy, timeout_Reg_DATA_Phy, blocks_DATA_Phy, writeRead_DATA_Phy, multiple_DATA_Phy, idle_in_DATA_Phy, transmission_complete_PS_Phy, reception_complete_SP_Phy, data_read_SP_Phy, dataFromFIFO_FIFO_Phy, serial_Ready_Phy_DATA, complete_Phy_DATA, ack_OUT_Phy_DATA, data_timeout_Phy_DATA, reset_Wrapper_Phy_PS, enable_pts_Wrapper_Phy_PS, enable_stp_Wrapper_Phy_SP, dataParallel_Phy_PS, pad_state_Phy_PAD, pad_enable_Phy_PAD, writeFIFO_enable_Phy_FIFO, readFIFO_enable_Phy_FIFO, dataReadToFIFO_Phy_FIFO, IO_enable_Phy_SD_CARD);
wire _0_;
wire _1_;
output IO_enable_Phy_SD_CARD;
input RESET_L;
input SD_CLK;
wire STATE;
input ack_IN_DATA_Phy;
output ack_OUT_Phy_DATA;
input [3:0] blocks_DATA_Phy;
output complete_Phy_DATA;
input [31:0] dataFromFIFO_FIFO_Phy;
output [31:0] dataParallel_Phy_PS;
output [31:0] dataReadToFIFO_Phy_FIFO;
input [31:0] data_read_SP_Phy;
output data_timeout_Phy_DATA;
output enable_pts_Wrapper_Phy_PS;
output enable_stp_Wrapper_Phy_SP;
input idle_in_DATA_Phy;
input multiple_DATA_Phy;
output pad_enable_Phy_PAD;
output pad_state_Phy_PAD;
output readFIFO_enable_Phy_FIFO;
input reception_complete_SP_Phy;
output reset_Wrapper_Phy_PS;
output serial_Ready_Phy_DATA;
input strobe_IN_DATA_Phy;
input [15:0] timeout_Reg_DATA_Phy;
input transmission_complete_PS_Phy;
output writeFIFO_enable_Phy_FIFO;
input writeRead_DATA_Phy;
NOT _2_ (
.A(RESET_L),
.Y(_0_)
);
NOT _3_ (
.A(STATE),
.Y(serial_Ready_Phy_DATA)
);
BUF _4_ (
.A(STATE),
.Y(_1_)
);
DFF _5_ (
.C(SD_CLK),
.D(_0_),
.Q(STATE)
);
\$_DLATCH_P_ _6_ (
.D(_1_),
.E(STATE),
.Q(reset_Wrapper_Phy_PS)
);
\$_DLATCH_P_ _7_ (
.D(1'b0),
.E(STATE),
.Q(dataParallel_Phy_PS[24])
);
assign IO_enable_Phy_SD_CARD = dataParallel_Phy_PS[24];
assign ack_OUT_Phy_DATA = dataParallel_Phy_PS[24];
assign complete_Phy_DATA = dataParallel_Phy_PS[24];
assign { dataParallel_Phy_PS[31:25], dataParallel_Phy_PS[23:0] } = { dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24] };
assign dataReadToFIFO_Phy_FIFO = { dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24], dataParallel_Phy_PS[24] };
assign data_timeout_Phy_DATA = dataParallel_Phy_PS[24];
assign enable_pts_Wrapper_Phy_PS = dataParallel_Phy_PS[24];
assign enable_stp_Wrapper_Phy_SP = dataParallel_Phy_PS[24];
assign pad_enable_Phy_PAD = dataParallel_Phy_PS[24];
assign pad_state_Phy_PAD = dataParallel_Phy_PS[24];
assign readFIFO_enable_Phy_FIFO = dataParallel_Phy_PS[24];
assign writeFIFO_enable_Phy_FIFO = dataParallel_Phy_PS[24];
endmodule
module PARALLEL_TO_SERIAL(enable_pts, reset_pts, SD_CLK, signal_in, signal_out, parallel_complete);
wire [8:0] _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
input SD_CLK;
wire [8:0] contador;
input enable_pts;
output parallel_complete;
input reset_pts;
input [31:0] signal_in;
output signal_out;
NOT _166_ (
.A(reset_pts),
.Y(_128_)
);
NOT _167_ (
.A(parallel_complete),
.Y(_129_)
);
NOR _168_ (
.A(enable_pts),
.B(_129_),
.Y(_130_)
);
NOT _169_ (
.A(enable_pts),
.Y(_131_)
);
NOR _170_ (
.A(contador[1]),
.B(contador[0]),
.Y(_132_)
);
NOT _171_ (
.A(_132_),
.Y(_133_)
);
NOR _172_ (
.A(_133_),
.B(contador[3]),
.Y(_134_)
);
NOT _173_ (
.A(contador[7]),
.Y(_135_)
);
NOR _174_ (
.A(contador[8]),
.B(contador[4]),
.Y(_136_)
);
NAND _175_ (
.A(_136_),
.B(_135_),
.Y(_137_)
);
NOT _176_ (
.A(contador[2]),
.Y(_138_)
);
NOT _177_ (
.A(contador[5]),
.Y(_139_)
);
NOR _178_ (
.A(_139_),
.B(contador[6]),
.Y(_140_)
);
NAND _179_ (
.A(_140_),
.B(_138_),
.Y(_141_)
);
NOR _180_ (
.A(_141_),
.B(_137_),
.Y(_142_)
);
NAND _181_ (
.A(_142_),
.B(_134_),
.Y(_143_)
);
NOR _182_ (
.A(_143_),
.B(_131_),
.Y(_144_)
);
NOR _183_ (
.A(_144_),
.B(_130_),
.Y(_145_)
);
NOR _184_ (
.A(_145_),
.B(_128_),
.Y(_001_)
);
NOR _185_ (
.A(_144_),
.B(_128_),
.Y(_146_)
);
NOT _186_ (
.A(_146_),
.Y(_147_)
);
NOT _187_ (
.A(contador[0]),
.Y(_148_)
);
NAND _188_ (
.A(_148_),
.B(_131_),
.Y(_149_)
);
NAND _189_ (
.A(contador[0]),
.B(enable_pts),
.Y(_150_)
);
NAND _190_ (
.A(_150_),
.B(_149_),
.Y(_151_)
);
NOR _191_ (
.A(_151_),
.B(_147_),
.Y(_000_[0])
);
NOT _192_ (
.A(contador[1]),
.Y(_152_)
);
NOR _193_ (
.A(_150_),
.B(_152_),
.Y(_153_)
);
NAND _194_ (
.A(_150_),
.B(_152_),
.Y(_154_)
);
NAND _195_ (
.A(_154_),
.B(reset_pts),
.Y(_155_)
);
NOR _196_ (
.A(_155_),
.B(_153_),
.Y(_000_[1])
);
NAND _197_ (
.A(_153_),
.B(contador[2]),
.Y(_156_)
);
NOT _198_ (
.A(_156_),
.Y(_157_)
);
NOT _199_ (
.A(_153_),
.Y(_158_)
);
NAND _200_ (
.A(_158_),
.B(_138_),
.Y(_159_)
);
NAND _201_ (
.A(_159_),
.B(reset_pts),
.Y(_160_)
);
NOR _202_ (
.A(_160_),
.B(_157_),
.Y(_000_[2])
);
NOT _203_ (
.A(contador[3]),
.Y(_161_)
);
NOR _204_ (
.A(_156_),
.B(_161_),
.Y(_162_)
);
NAND _205_ (
.A(_156_),
.B(_161_),
.Y(_163_)
);
NAND _206_ (
.A(_163_),
.B(reset_pts),
.Y(_164_)
);
NOR _207_ (
.A(_164_),
.B(_162_),
.Y(_000_[3])
);
NAND _208_ (
.A(_162_),
.B(contador[4]),
.Y(_165_)
);
NOT _209_ (
.A(_165_),
.Y(_003_)
);
NOT _210_ (
.A(contador[4]),
.Y(_004_)
);
NOT _211_ (
.A(_162_),
.Y(_005_)
);
NAND _212_ (
.A(_005_),
.B(_004_),
.Y(_006_)
);
NAND _213_ (
.A(_006_),
.B(reset_pts),
.Y(_007_)
);
NOR _214_ (
.A(_007_),
.B(_003_),
.Y(_000_[4])
);
NOR _215_ (
.A(_003_),
.B(contador[5]),
.Y(_008_)
);
NOR _216_ (
.A(_165_),
.B(_139_),
.Y(_009_)
);
NOT _217_ (
.A(_009_),
.Y(_010_)
);
NAND _218_ (
.A(_010_),
.B(_146_),
.Y(_011_)
);
NOR _219_ (
.A(_011_),
.B(_008_),
.Y(_000_[5])
);
NOR _220_ (
.A(_009_),
.B(contador[6]),
.Y(_012_)
);
NAND _221_ (
.A(_009_),
.B(contador[6]),
.Y(_013_)
);
NAND _222_ (
.A(_013_),
.B(reset_pts),
.Y(_014_)
);
NOR _223_ (
.A(_014_),
.B(_012_),
.Y(_000_[6])
);
NOR _224_ (
.A(_013_),
.B(_135_),
.Y(_015_)
);
NAND _225_ (
.A(_013_),
.B(_135_),
.Y(_016_)
);
NAND _226_ (
.A(_016_),
.B(reset_pts),
.Y(_017_)
);
NOR _227_ (
.A(_017_),
.B(_015_),
.Y(_000_[7])
);
NOT _228_ (
.A(contador[8]),
.Y(_018_)
);
NOR _229_ (
.A(_015_),
.B(_018_),
.Y(_019_)
);
NOT _230_ (
.A(_015_),
.Y(_020_)
);
NOR _231_ (
.A(_020_),
.B(contador[8]),
.Y(_021_)
);
NOR _232_ (
.A(_021_),
.B(_019_),
.Y(_022_)
);
NOR _233_ (
.A(_022_),
.B(_128_),
.Y(_000_[8])
);
NOT _234_ (
.A(signal_out),
.Y(_023_)
);
NOR _235_ (
.A(_143_),
.B(_023_),
.Y(_024_)
);
NOR _236_ (
.A(signal_in[0]),
.B(_004_),
.Y(_025_)
);
NOR _237_ (
.A(signal_in[16]),
.B(contador[4]),
.Y(_026_)
);
NOR _238_ (
.A(_026_),
.B(_025_),
.Y(_027_)
);
NOR _239_ (
.A(_027_),
.B(_161_),
.Y(_028_)
);
NOR _240_ (
.A(signal_in[24]),
.B(contador[4]),
.Y(_029_)
);
NOR _241_ (
.A(signal_in[8]),
.B(_004_),
.Y(_030_)
);
NOR _242_ (
.A(_030_),
.B(_029_),
.Y(_031_)
);
NOR _243_ (
.A(_031_),
.B(contador[3]),
.Y(_032_)
);
NOR _244_ (
.A(_032_),
.B(_028_),
.Y(_033_)
);
NOR _245_ (
.A(_033_),
.B(_152_),
.Y(_034_)
);
NAND _246_ (
.A(signal_in[26]),
.B(_004_),
.Y(_035_)
);
NAND _247_ (
.A(signal_in[10]),
.B(contador[4]),
.Y(_036_)
);
NAND _248_ (
.A(_036_),
.B(_035_),
.Y(_037_)
);
NOR _249_ (
.A(_037_),
.B(contador[3]),
.Y(_038_)
);
NOT _250_ (
.A(signal_in[2]),
.Y(_039_)
);
NOR _251_ (
.A(_039_),
.B(_004_),
.Y(_040_)
);
NAND _252_ (
.A(signal_in[18]),
.B(_004_),
.Y(_041_)
);
NAND _253_ (
.A(_041_),
.B(contador[3]),
.Y(_042_)
);
NOR _254_ (
.A(_042_),
.B(_040_),
.Y(_043_)
);
NOR _255_ (
.A(_043_),
.B(_038_),
.Y(_044_)
);
NOR _256_ (
.A(_044_),
.B(contador[1]),
.Y(_045_)
);
NOR _257_ (
.A(_045_),
.B(_034_),
.Y(_046_)
);
NOR _258_ (
.A(_046_),
.B(_138_),
.Y(_047_)
);
NOR _259_ (
.A(signal_in[4]),
.B(_004_),
.Y(_048_)
);
NOR _260_ (
.A(signal_in[20]),
.B(contador[4]),
.Y(_049_)
);
NOR _261_ (
.A(_049_),
.B(_048_),
.Y(_050_)
);
NOR _262_ (
.A(_050_),
.B(_161_),
.Y(_051_)
);
NOR _263_ (
.A(signal_in[28]),
.B(contador[4]),
.Y(_052_)
);
NOR _264_ (
.A(signal_in[12]),
.B(_004_),
.Y(_053_)
);
NOR _265_ (
.A(_053_),
.B(_052_),
.Y(_054_)
);
NOR _266_ (
.A(_054_),
.B(contador[3]),
.Y(_055_)
);
NOR _267_ (
.A(_055_),
.B(_051_),
.Y(_056_)
);
NOR _268_ (
.A(_056_),
.B(_152_),
.Y(_057_)
);
NAND _269_ (
.A(signal_in[30]),
.B(_004_),
.Y(_058_)
);
NAND _270_ (
.A(signal_in[14]),
.B(contador[4]),
.Y(_059_)
);
NAND _271_ (
.A(_059_),
.B(_058_),
.Y(_060_)
);
NOR _272_ (
.A(_060_),
.B(contador[3]),
.Y(_061_)
);
NOT _273_ (
.A(signal_in[6]),
.Y(_062_)
);
NOR _274_ (
.A(_062_),
.B(_004_),
.Y(_063_)
);
NAND _275_ (
.A(signal_in[22]),
.B(_004_),
.Y(_064_)
);
NAND _276_ (
.A(_064_),
.B(contador[3]),
.Y(_065_)
);
NOR _277_ (
.A(_065_),
.B(_063_),
.Y(_066_)
);
NOR _278_ (
.A(_066_),
.B(_061_),
.Y(_067_)
);
NOR _279_ (
.A(_067_),
.B(contador[1]),
.Y(_068_)
);
NOR _280_ (
.A(_068_),
.B(_057_),
.Y(_069_)
);
NOR _281_ (
.A(_069_),
.B(contador[2]),
.Y(_070_)
);
NOR _282_ (
.A(_070_),
.B(_047_),
.Y(_071_)
);
NOR _283_ (
.A(_071_),
.B(_148_),
.Y(_072_)
);
NAND _284_ (
.A(signal_in[25]),
.B(_004_),
.Y(_073_)
);
NOT _285_ (
.A(signal_in[9]),
.Y(_074_)
);
NOR _286_ (
.A(_074_),
.B(_004_),
.Y(_075_)
);
NOR _287_ (
.A(_075_),
.B(contador[3]),
.Y(_076_)
);
NAND _288_ (
.A(_076_),
.B(_073_),
.Y(_077_)
);
NAND _289_ (
.A(signal_in[1]),
.B(contador[4]),
.Y(_078_)
);
NOT _290_ (
.A(signal_in[17]),
.Y(_079_)
);
NOR _291_ (
.A(_079_),
.B(contador[4]),
.Y(_080_)
);
NOR _292_ (
.A(_080_),
.B(_161_),
.Y(_081_)
);
NAND _293_ (
.A(_081_),
.B(_078_),
.Y(_082_)
);
NAND _294_ (
.A(_082_),
.B(_077_),
.Y(_083_)
);
NOR _295_ (
.A(_083_),
.B(_138_),
.Y(_084_)
);
NAND _296_ (
.A(signal_in[29]),
.B(_004_),
.Y(_085_)
);
NAND _297_ (
.A(signal_in[13]),
.B(contador[4]),
.Y(_086_)
);
NAND _298_ (
.A(_086_),
.B(_085_),
.Y(_087_)
);
NOR _299_ (
.A(_087_),
.B(contador[3]),
.Y(_088_)
);
NOT _300_ (
.A(signal_in[5]),
.Y(_089_)
);
NOR _301_ (
.A(_089_),
.B(_004_),
.Y(_090_)
);
NAND _302_ (
.A(signal_in[21]),
.B(_004_),
.Y(_091_)
);
NAND _303_ (
.A(_091_),
.B(contador[3]),
.Y(_092_)
);
NOR _304_ (
.A(_092_),
.B(_090_),
.Y(_093_)
);
NOR _305_ (
.A(_093_),
.B(_088_),
.Y(_094_)
);
NAND _306_ (
.A(_094_),
.B(_138_),
.Y(_095_)
);
NAND _307_ (
.A(_095_),
.B(contador[1]),
.Y(_096_)
);
NOR _308_ (
.A(_096_),
.B(_084_),
.Y(_097_)
);
NAND _309_ (
.A(_097_),
.B(_148_),
.Y(_098_)
);
NOR _310_ (
.A(signal_in[3]),
.B(_004_),
.Y(_099_)
);
NOR _311_ (
.A(signal_in[19]),
.B(contador[4]),
.Y(_100_)
);
NOR _312_ (
.A(_100_),
.B(_099_),
.Y(_101_)
);
NOR _313_ (
.A(_101_),
.B(_161_),
.Y(_102_)
);
NOR _314_ (
.A(signal_in[27]),
.B(contador[4]),
.Y(_103_)
);
NOR _315_ (
.A(signal_in[11]),
.B(_004_),
.Y(_104_)
);
NOR _316_ (
.A(_104_),
.B(_103_),
.Y(_105_)
);
NOR _317_ (
.A(_105_),
.B(contador[3]),
.Y(_106_)
);
NOR _318_ (
.A(_106_),
.B(_102_),
.Y(_107_)
);
NOR _319_ (
.A(_107_),
.B(_138_),
.Y(_108_)
);
NOR _320_ (
.A(signal_in[7]),
.B(_004_),
.Y(_109_)
);
NOR _321_ (
.A(signal_in[23]),
.B(contador[4]),
.Y(_110_)
);
NOR _322_ (
.A(_110_),
.B(_109_),
.Y(_111_)
);
NOR _323_ (
.A(_111_),
.B(_161_),
.Y(_112_)
);
NOR _324_ (
.A(signal_in[31]),
.B(contador[4]),
.Y(_113_)
);
NOR _325_ (
.A(signal_in[15]),
.B(_004_),
.Y(_114_)
);
NOR _326_ (
.A(_114_),
.B(_113_),
.Y(_115_)
);
NOR _327_ (
.A(_115_),
.B(contador[3]),
.Y(_116_)
);
NOR _328_ (
.A(_116_),
.B(_112_),
.Y(_117_)
);
NOR _329_ (
.A(_117_),
.B(contador[2]),
.Y(_118_)
);
NOR _330_ (
.A(_118_),
.B(_108_),
.Y(_119_)
);
NOR _331_ (
.A(_119_),
.B(_133_),
.Y(_120_)
);
NOT _332_ (
.A(contador[6]),
.Y(_121_)
);
NAND _333_ (
.A(_139_),
.B(_121_),
.Y(_122_)
);
NOR _334_ (
.A(_122_),
.B(_120_),
.Y(_123_)
);
NAND _335_ (
.A(_123_),
.B(_098_),
.Y(_124_)
);
NOR _336_ (
.A(_124_),
.B(_072_),
.Y(_125_)
);
NOR _337_ (
.A(_125_),
.B(_024_),
.Y(_126_)
);
NAND _338_ (
.A(reset_pts),
.B(enable_pts),
.Y(_127_)
);
NOR _339_ (
.A(_127_),
.B(_126_),
.Y(_002_)
);
DFF _340_ (
.C(SD_CLK),
.D(_002_),
.Q(signal_out)
);
DFF _341_ (
.C(SD_CLK),
.D(_001_),
.Q(parallel_complete)
);
DFF _342_ (
.C(SD_CLK),
.D(_000_[0]),
.Q(contador[0])
);
DFF _343_ (
.C(SD_CLK),
.D(_000_[1]),
.Q(contador[1])
);
DFF _344_ (
.C(SD_CLK),
.D(_000_[2]),
.Q(contador[2])
);
DFF _345_ (
.C(SD_CLK),
.D(_000_[3]),
.Q(contador[3])
);
DFF _346_ (
.C(SD_CLK),
.D(_000_[4]),
.Q(contador[4])
);
DFF _347_ (
.C(SD_CLK),
.D(_000_[5]),
.Q(contador[5])
);
DFF _348_ (
.C(SD_CLK),
.D(_000_[6]),
.Q(contador[6])
);
DFF _349_ (
.C(SD_CLK),
.D(_000_[7]),
.Q(contador[7])
);
DFF _350_ (
.C(SD_CLK),
.D(_000_[8]),
.Q(contador[8])
);
endmodule
module SERIAL_TO_PARALLEL(serial_in, enable_stp, SD_CLK, RESET_L, reception_complete, parallel_out);
wire [8:0] _000_;
wire [31:0] _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
input RESET_L;
input SD_CLK;
wire [8:0] contador;
input enable_stp;
output [31:0] parallel_out;
output reception_complete;
input serial_in;
NOT _238_ (
.A(RESET_L),
.Y(_237_)
);
NOT _239_ (
.A(enable_stp),
.Y(_003_)
);
NAND _240_ (
.A(_003_),
.B(reception_complete),
.Y(_004_)
);
NOR _241_ (
.A(contador[8]),
.B(contador[7]),
.Y(_005_)
);
NAND _242_ (
.A(_005_),
.B(contador[5]),
.Y(_006_)
);
NOR _243_ (
.A(contador[1]),
.B(contador[0]),
.Y(_007_)
);
NOT _244_ (
.A(contador[2]),
.Y(_008_)
);
NOT _245_ (
.A(contador[3]),
.Y(_009_)
);
NAND _246_ (
.A(_009_),
.B(_008_),
.Y(_010_)
);
NOT _247_ (
.A(contador[4]),
.Y(_011_)
);
NOT _248_ (
.A(contador[6]),
.Y(_012_)
);
NAND _249_ (
.A(_012_),
.B(_011_),
.Y(_013_)
);
NOR _250_ (
.A(_013_),
.B(_010_),
.Y(_014_)
);
NAND _251_ (
.A(_014_),
.B(_007_),
.Y(_015_)
);
NOR _252_ (
.A(_015_),
.B(_006_),
.Y(_016_)
);
NAND _253_ (
.A(_016_),
.B(enable_stp),
.Y(_017_)
);
NAND _254_ (
.A(_017_),
.B(_004_),
.Y(_002_)
);
NOT _255_ (
.A(parallel_out[1]),
.Y(_018_)
);
NOR _256_ (
.A(_016_),
.B(_018_),
.Y(_019_)
);
NOT _257_ (
.A(parallel_out[0]),
.Y(_021_)
);
NOT _258_ (
.A(_006_),
.Y(_023_)
);
NOT _259_ (
.A(_007_),
.Y(_024_)
);
NOR _260_ (
.A(contador[3]),
.B(contador[2]),
.Y(_026_)
);
NOR _261_ (
.A(contador[6]),
.B(contador[4]),
.Y(_028_)
);
NAND _262_ (
.A(_028_),
.B(_026_),
.Y(_030_)
);
NOR _263_ (
.A(_030_),
.B(_024_),
.Y(_032_)
);
NAND _264_ (
.A(_032_),
.B(_023_),
.Y(_033_)
);
NOR _265_ (
.A(_033_),
.B(_021_),
.Y(_034_)
);
NOR _266_ (
.A(_034_),
.B(_019_),
.Y(_035_)
);
NOR _267_ (
.A(_035_),
.B(_003_),
.Y(_001_[0])
);
NOT _268_ (
.A(parallel_out[2]),
.Y(_038_)
);
NOR _269_ (
.A(_016_),
.B(_038_),
.Y(_040_)
);
NOR _270_ (
.A(_033_),
.B(_018_),
.Y(_042_)
);
NOR _271_ (
.A(_042_),
.B(_040_),
.Y(_043_)
);
NOR _272_ (
.A(_043_),
.B(_003_),
.Y(_001_[1])
);
NOT _273_ (
.A(parallel_out[3]),
.Y(_044_)
);
NOR _274_ (
.A(_016_),
.B(_044_),
.Y(_045_)
);
NOR _275_ (
.A(_033_),
.B(_038_),
.Y(_046_)
);
NOR _276_ (
.A(_046_),
.B(_045_),
.Y(_047_)
);
NOR _277_ (
.A(_047_),
.B(_003_),
.Y(_001_[2])
);
NOT _278_ (
.A(parallel_out[4]),
.Y(_048_)
);
NOR _279_ (
.A(_016_),
.B(_048_),
.Y(_049_)
);
NOR _280_ (
.A(_033_),
.B(_044_),
.Y(_050_)
);
NOR _281_ (
.A(_050_),
.B(_049_),
.Y(_051_)
);
NOR _282_ (
.A(_051_),
.B(_003_),
.Y(_001_[3])
);
NOT _283_ (
.A(parallel_out[5]),
.Y(_052_)
);
NOR _284_ (
.A(_016_),
.B(_052_),
.Y(_053_)
);
NOR _285_ (
.A(_033_),
.B(_048_),
.Y(_054_)
);
NOR _286_ (
.A(_054_),
.B(_053_),
.Y(_055_)
);
NOR _287_ (
.A(_055_),
.B(_003_),
.Y(_001_[4])
);
NOT _288_ (
.A(parallel_out[6]),
.Y(_056_)
);
NOR _289_ (
.A(_016_),
.B(_056_),
.Y(_057_)
);
NOR _290_ (
.A(_033_),
.B(_052_),
.Y(_058_)
);
NOR _291_ (
.A(_058_),
.B(_057_),
.Y(_059_)
);
NOR _292_ (
.A(_059_),
.B(_003_),
.Y(_001_[5])
);
NOT _293_ (
.A(parallel_out[7]),
.Y(_060_)
);
NOR _294_ (
.A(_016_),
.B(_060_),
.Y(_061_)
);
NOR _295_ (
.A(_033_),
.B(_056_),
.Y(_062_)
);
NOR _296_ (
.A(_062_),
.B(_061_),
.Y(_063_)
);
NOR _297_ (
.A(_063_),
.B(_003_),
.Y(_001_[6])
);
NOT _298_ (
.A(parallel_out[8]),
.Y(_064_)
);
NOR _299_ (
.A(_016_),
.B(_064_),
.Y(_065_)
);
NOR _300_ (
.A(_033_),
.B(_060_),
.Y(_066_)
);
NOR _301_ (
.A(_066_),
.B(_065_),
.Y(_067_)
);
NOR _302_ (
.A(_067_),
.B(_003_),
.Y(_001_[7])
);
NOT _303_ (
.A(parallel_out[9]),
.Y(_068_)
);
NOR _304_ (
.A(_016_),
.B(_068_),
.Y(_069_)
);
NOR _305_ (
.A(_033_),
.B(_064_),
.Y(_070_)
);
NOR _306_ (
.A(_070_),
.B(_069_),
.Y(_071_)
);
NOR _307_ (
.A(_071_),
.B(_003_),
.Y(_001_[8])
);
NOT _308_ (
.A(parallel_out[10]),
.Y(_072_)
);
NOR _309_ (
.A(_016_),
.B(_072_),
.Y(_073_)
);
NOR _310_ (
.A(_033_),
.B(_068_),
.Y(_074_)
);
NOR _311_ (
.A(_074_),
.B(_073_),
.Y(_075_)
);
NOR _312_ (
.A(_075_),
.B(_003_),
.Y(_001_[9])
);
NOT _313_ (
.A(parallel_out[11]),
.Y(_076_)
);
NOR _314_ (
.A(_016_),
.B(_076_),
.Y(_077_)
);
NOR _315_ (
.A(_033_),
.B(_072_),
.Y(_078_)
);
NOR _316_ (
.A(_078_),
.B(_077_),
.Y(_079_)
);
NOR _317_ (
.A(_079_),
.B(_003_),
.Y(_001_[10])
);
NOT _318_ (
.A(parallel_out[12]),
.Y(_080_)
);
NOR _319_ (
.A(_016_),
.B(_080_),
.Y(_081_)
);
NOR _320_ (
.A(_033_),
.B(_076_),
.Y(_082_)
);
NOR _321_ (
.A(_082_),
.B(_081_),
.Y(_083_)
);
NOR _322_ (
.A(_083_),
.B(_003_),
.Y(_001_[11])
);
NOT _323_ (
.A(parallel_out[13]),
.Y(_084_)
);
NOR _324_ (
.A(_016_),
.B(_084_),
.Y(_085_)
);
NOR _325_ (
.A(_033_),
.B(_080_),
.Y(_086_)
);
NOR _326_ (
.A(_086_),
.B(_085_),
.Y(_087_)
);
NOR _327_ (
.A(_087_),
.B(_003_),
.Y(_001_[12])
);
NOT _328_ (
.A(parallel_out[14]),
.Y(_088_)
);
NOR _329_ (
.A(_016_),
.B(_088_),
.Y(_089_)
);
NOR _330_ (
.A(_033_),
.B(_084_),
.Y(_090_)
);
NOR _331_ (
.A(_090_),
.B(_089_),
.Y(_091_)
);
NOR _332_ (
.A(_091_),
.B(_003_),
.Y(_001_[13])
);
NOT _333_ (
.A(parallel_out[15]),
.Y(_092_)
);
NOR _334_ (
.A(_016_),
.B(_092_),
.Y(_093_)
);
NOR _335_ (
.A(_033_),
.B(_088_),
.Y(_094_)
);
NOR _336_ (
.A(_094_),
.B(_093_),
.Y(_095_)
);
NOR _337_ (
.A(_095_),
.B(_003_),
.Y(_001_[14])
);
NOT _338_ (
.A(parallel_out[16]),
.Y(_096_)
);
NOR _339_ (
.A(_016_),
.B(_096_),
.Y(_097_)
);
NOR _340_ (
.A(_033_),
.B(_092_),
.Y(_098_)
);
NOR _341_ (
.A(_098_),
.B(_097_),
.Y(_099_)
);
NOR _342_ (
.A(_099_),
.B(_003_),
.Y(_001_[15])
);
NOT _343_ (
.A(parallel_out[17]),
.Y(_100_)
);
NOR _344_ (
.A(_016_),
.B(_100_),
.Y(_101_)
);
NOR _345_ (
.A(_033_),
.B(_096_),
.Y(_102_)
);
NOR _346_ (
.A(_102_),
.B(_101_),
.Y(_103_)
);
NOR _347_ (
.A(_103_),
.B(_003_),
.Y(_001_[16])
);
NOT _348_ (
.A(parallel_out[18]),
.Y(_104_)
);
NOR _349_ (
.A(_016_),
.B(_104_),
.Y(_105_)
);
NOR _350_ (
.A(_033_),
.B(_100_),
.Y(_106_)
);
NOR _351_ (
.A(_106_),
.B(_105_),
.Y(_107_)
);
NOR _352_ (
.A(_107_),
.B(_003_),
.Y(_001_[17])
);
NOT _353_ (
.A(parallel_out[19]),
.Y(_108_)
);
NOR _354_ (
.A(_016_),
.B(_108_),
.Y(_109_)
);
NOR _355_ (
.A(_033_),
.B(_104_),
.Y(_110_)
);
NOR _356_ (
.A(_110_),
.B(_109_),
.Y(_111_)
);
NOR _357_ (
.A(_111_),
.B(_003_),
.Y(_001_[18])
);
NOT _358_ (
.A(parallel_out[20]),
.Y(_112_)
);
NOR _359_ (
.A(_016_),
.B(_112_),
.Y(_113_)
);
NOR _360_ (
.A(_033_),
.B(_108_),
.Y(_114_)
);
NOR _361_ (
.A(_114_),
.B(_113_),
.Y(_115_)
);
NOR _362_ (
.A(_115_),
.B(_003_),
.Y(_001_[19])
);
NOT _363_ (
.A(parallel_out[21]),
.Y(_116_)
);
NOR _364_ (
.A(_016_),
.B(_116_),
.Y(_117_)
);
NOR _365_ (
.A(_033_),
.B(_112_),
.Y(_118_)
);
NOR _366_ (
.A(_118_),
.B(_117_),
.Y(_119_)
);
NOR _367_ (
.A(_119_),
.B(_003_),
.Y(_001_[20])
);
NOT _368_ (
.A(parallel_out[22]),
.Y(_120_)
);
NOR _369_ (
.A(_016_),
.B(_120_),
.Y(_121_)
);
NOR _370_ (
.A(_033_),
.B(_116_),
.Y(_122_)
);
NOR _371_ (
.A(_122_),
.B(_121_),
.Y(_123_)
);
NOR _372_ (
.A(_123_),
.B(_003_),
.Y(_001_[21])
);
NOT _373_ (
.A(parallel_out[23]),
.Y(_124_)
);
NOR _374_ (
.A(_016_),
.B(_124_),
.Y(_125_)
);
NOR _375_ (
.A(_033_),
.B(_120_),
.Y(_126_)
);
NOR _376_ (
.A(_126_),
.B(_125_),
.Y(_127_)
);
NOR _377_ (
.A(_127_),
.B(_003_),
.Y(_001_[22])
);
NOT _378_ (
.A(parallel_out[24]),
.Y(_128_)
);
NOR _379_ (
.A(_016_),
.B(_128_),
.Y(_129_)
);
NOR _380_ (
.A(_033_),
.B(_124_),
.Y(_130_)
);
NOR _381_ (
.A(_130_),
.B(_129_),
.Y(_131_)
);
NOR _382_ (
.A(_131_),
.B(_003_),
.Y(_001_[23])
);
NOT _383_ (
.A(parallel_out[25]),
.Y(_132_)
);
NOR _384_ (
.A(_016_),
.B(_132_),
.Y(_133_)
);
NOR _385_ (
.A(_033_),
.B(_128_),
.Y(_134_)
);
NOR _386_ (
.A(_134_),
.B(_133_),
.Y(_135_)
);
NOR _387_ (
.A(_135_),
.B(_003_),
.Y(_001_[24])
);
NOT _388_ (
.A(parallel_out[26]),
.Y(_136_)
);
NOR _389_ (
.A(_016_),
.B(_136_),
.Y(_137_)
);
NOR _390_ (
.A(_033_),
.B(_132_),
.Y(_138_)
);
NOR _391_ (
.A(_138_),
.B(_137_),
.Y(_139_)
);
NOR _392_ (
.A(_139_),
.B(_003_),
.Y(_001_[25])
);
NOT _393_ (
.A(parallel_out[27]),
.Y(_140_)
);
NOR _394_ (
.A(_016_),
.B(_140_),
.Y(_141_)
);
NOR _395_ (
.A(_033_),
.B(_136_),
.Y(_142_)
);
NOR _396_ (
.A(_142_),
.B(_141_),
.Y(_143_)
);
NOR _397_ (
.A(_143_),
.B(_003_),
.Y(_001_[26])
);
NOT _398_ (
.A(parallel_out[28]),
.Y(_144_)
);
NOR _399_ (
.A(_016_),
.B(_144_),
.Y(_145_)
);
NOR _400_ (
.A(_033_),
.B(_140_),
.Y(_146_)
);
NOR _401_ (
.A(_146_),
.B(_145_),
.Y(_147_)
);
NOR _402_ (
.A(_147_),
.B(_003_),
.Y(_001_[27])
);
NOT _403_ (
.A(parallel_out[29]),
.Y(_148_)
);
NOR _404_ (
.A(_016_),
.B(_148_),
.Y(_149_)
);
NOR _405_ (
.A(_033_),
.B(_144_),
.Y(_150_)
);
NOR _406_ (
.A(_150_),
.B(_149_),
.Y(_151_)
);
NOR _407_ (
.A(_151_),
.B(_003_),
.Y(_001_[28])
);
NOT _408_ (
.A(parallel_out[30]),
.Y(_152_)
);
NOR _409_ (
.A(_016_),
.B(_152_),
.Y(_153_)
);
NOR _410_ (
.A(_033_),
.B(_148_),
.Y(_154_)
);
NOR _411_ (
.A(_154_),
.B(_153_),
.Y(_155_)
);
NOR _412_ (
.A(_155_),
.B(_003_),
.Y(_001_[29])
);
NOT _413_ (
.A(parallel_out[31]),
.Y(_156_)
);
NOR _414_ (
.A(_016_),
.B(_156_),
.Y(_157_)
);
NOR _415_ (
.A(_033_),
.B(_152_),
.Y(_158_)
);
NOR _416_ (
.A(_158_),
.B(_157_),
.Y(_159_)
);
NOR _417_ (
.A(_159_),
.B(_003_),
.Y(_001_[30])
);
NOT _418_ (
.A(serial_in),
.Y(_160_)
);
NOR _419_ (
.A(_016_),
.B(_160_),
.Y(_161_)
);
NOR _420_ (
.A(_033_),
.B(_156_),
.Y(_162_)
);
NOR _421_ (
.A(_162_),
.B(_161_),
.Y(_163_)
);
NOR _422_ (
.A(_163_),
.B(_003_),
.Y(_001_[31])
);
NAND _423_ (
.A(contador[0]),
.B(_003_),
.Y(_164_)
);
NOR _424_ (
.A(_016_),
.B(contador[0]),
.Y(_165_)
);
NAND _425_ (
.A(_165_),
.B(enable_stp),
.Y(_166_)
);
NAND _426_ (
.A(_166_),
.B(_164_),
.Y(_000_[0])
);
NOT _427_ (
.A(contador[0]),
.Y(_167_)
);
NOT _428_ (
.A(contador[1]),
.Y(_168_)
);
NOR _429_ (
.A(_168_),
.B(_167_),
.Y(_169_)
);
NOR _430_ (
.A(_169_),
.B(_007_),
.Y(_170_)
);
NOR _431_ (
.A(_170_),
.B(_003_),
.Y(_171_)
);
NOR _432_ (
.A(contador[1]),
.B(enable_stp),
.Y(_172_)
);
NOR _433_ (
.A(_172_),
.B(_171_),
.Y(_000_[1])
);
NAND _434_ (
.A(_169_),
.B(enable_stp),
.Y(_173_)
);
NOR _435_ (
.A(_173_),
.B(_008_),
.Y(_174_)
);
NAND _436_ (
.A(contador[1]),
.B(contador[0]),
.Y(_175_)
);
NOR _437_ (
.A(_175_),
.B(_003_),
.Y(_176_)
);
NOR _438_ (
.A(_176_),
.B(contador[2]),
.Y(_177_)
);
NOR _439_ (
.A(_177_),
.B(_174_),
.Y(_000_[2])
);
NOR _440_ (
.A(_174_),
.B(contador[3]),
.Y(_178_)
);
NAND _441_ (
.A(contador[3]),
.B(contador[2]),
.Y(_179_)
);
NOR _442_ (
.A(_179_),
.B(_173_),
.Y(_180_)
);
NOR _443_ (
.A(_180_),
.B(_178_),
.Y(_000_[3])
);
NOR _444_ (
.A(_180_),
.B(contador[4]),
.Y(_181_)
);
NOT _445_ (
.A(_179_),
.Y(_182_)
);
NAND _446_ (
.A(_182_),
.B(_176_),
.Y(_183_)
);
NOR _447_ (
.A(_183_),
.B(_011_),
.Y(_184_)
);
NOR _448_ (
.A(_184_),
.B(_181_),
.Y(_000_[4])
);
NOR _449_ (
.A(_184_),
.B(contador[5]),
.Y(_185_)
);
NAND _450_ (
.A(_184_),
.B(contador[5]),
.Y(_186_)
);
NAND _451_ (
.A(_186_),
.B(_017_),
.Y(_187_)
);
NOR _452_ (
.A(_187_),
.B(_185_),
.Y(_000_[5])
);
NAND _453_ (
.A(_186_),
.B(contador[6]),
.Y(_188_)
);
NOT _454_ (
.A(contador[5]),
.Y(_189_)
);
NAND _455_ (
.A(_180_),
.B(contador[4]),
.Y(_190_)
);
NOR _456_ (
.A(_190_),
.B(_189_),
.Y(_191_)
);
NAND _457_ (
.A(_191_),
.B(_012_),
.Y(_192_)
);
NAND _458_ (
.A(_192_),
.B(_188_),
.Y(_000_[6])
);
NOT _459_ (
.A(contador[7]),
.Y(_193_)
);
NOR _460_ (
.A(_179_),
.B(_175_),
.Y(_194_)
);
NAND _461_ (
.A(contador[6]),
.B(contador[4]),
.Y(_195_)
);
NAND _462_ (
.A(contador[5]),
.B(enable_stp),
.Y(_196_)
);
NOR _463_ (
.A(_196_),
.B(_195_),
.Y(_197_)
);
NAND _464_ (
.A(_197_),
.B(_194_),
.Y(_198_)
);
NOR _465_ (
.A(_198_),
.B(_193_),
.Y(_199_)
);
NOT _466_ (
.A(_198_),
.Y(_200_)
);
NOR _467_ (
.A(_200_),
.B(contador[7]),
.Y(_201_)
);
NOR _468_ (
.A(_201_),
.B(_199_),
.Y(_000_[7])
);
NOR _469_ (
.A(_199_),
.B(contador[8]),
.Y(_202_)
);
NOT _470_ (
.A(contador[8]),
.Y(_203_)
);
NOT _471_ (
.A(_199_),
.Y(_204_)
);
NOR _472_ (
.A(_204_),
.B(_203_),
.Y(_205_)
);
NOR _473_ (
.A(_205_),
.B(_202_),
.Y(_000_[8])
);
BUF _474_ (
.A(_237_),
.Y(_020_)
);
BUF _475_ (
.A(_237_),
.Y(_022_)
);
BUF _476_ (
.A(_237_),
.Y(_206_)
);
BUF _477_ (
.A(_237_),
.Y(_025_)
);
BUF _478_ (
.A(_237_),
.Y(_027_)
);
BUF _479_ (
.A(_237_),
.Y(_029_)
);
BUF _480_ (
.A(_237_),
.Y(_031_)
);
BUF _481_ (
.A(_237_),
.Y(_207_)
);
BUF _482_ (
.A(_237_),
.Y(_208_)
);
BUF _483_ (
.A(_237_),
.Y(_209_)
);
BUF _484_ (
.A(_237_),
.Y(_036_)
);
BUF _485_ (
.A(_237_),
.Y(_037_)
);
BUF _486_ (
.A(_237_),
.Y(_039_)
);
BUF _487_ (
.A(_237_),
.Y(_041_)
);
BUF _488_ (
.A(_237_),
.Y(_210_)
);
BUF _489_ (
.A(_237_),
.Y(_211_)
);
BUF _490_ (
.A(_237_),
.Y(_212_)
);
BUF _491_ (
.A(_237_),
.Y(_213_)
);
BUF _492_ (
.A(_237_),
.Y(_214_)
);
BUF _493_ (
.A(_237_),
.Y(_215_)
);
BUF _494_ (
.A(_237_),
.Y(_216_)
);
BUF _495_ (
.A(_237_),
.Y(_217_)
);
BUF _496_ (
.A(_237_),
.Y(_218_)
);
BUF _497_ (
.A(_237_),
.Y(_219_)
);
BUF _498_ (
.A(_237_),
.Y(_220_)
);
BUF _499_ (
.A(_237_),
.Y(_221_)
);
BUF _500_ (
.A(_237_),
.Y(_222_)
);
BUF _501_ (
.A(_237_),
.Y(_223_)
);
BUF _502_ (
.A(_237_),
.Y(_224_)
);
BUF _503_ (
.A(_237_),
.Y(_225_)
);
BUF _504_ (
.A(_237_),
.Y(_226_)
);
BUF _505_ (
.A(_237_),
.Y(_227_)
);
BUF _506_ (
.A(_237_),
.Y(_228_)
);
BUF _507_ (
.A(_237_),
.Y(_229_)
);
BUF _508_ (
.A(_237_),
.Y(_230_)
);
BUF _509_ (
.A(_237_),
.Y(_231_)
);
BUF _510_ (
.A(_237_),
.Y(_232_)
);
BUF _511_ (
.A(_237_),
.Y(_233_)
);
BUF _512_ (
.A(_237_),
.Y(_234_)
);
BUF _513_ (
.A(_237_),
.Y(_235_)
);
BUF _514_ (
.A(_237_),
.Y(_236_)
);
DFFSR _515_ (
.C(SD_CLK),
.D(_002_),
.Q(reception_complete),
.R(_020_),
.S(1'b0)
);
DFFSR _516_ (
.C(SD_CLK),
.D(_001_[0]),
.Q(parallel_out[0]),
.R(_022_),
.S(1'b0)
);
DFFSR _517_ (
.C(SD_CLK),
.D(_001_[1]),
.Q(parallel_out[1]),
.R(_206_),
.S(1'b0)
);
DFFSR _518_ (
.C(SD_CLK),
.D(_001_[2]),
.Q(parallel_out[2]),
.R(_025_),
.S(1'b0)
);
DFFSR _519_ (
.C(SD_CLK),
.D(_001_[3]),
.Q(parallel_out[3]),
.R(_027_),
.S(1'b0)
);
DFFSR _520_ (
.C(SD_CLK),
.D(_001_[4]),
.Q(parallel_out[4]),
.R(_029_),
.S(1'b0)
);
DFFSR _521_ (
.C(SD_CLK),
.D(_001_[5]),
.Q(parallel_out[5]),
.R(_031_),
.S(1'b0)
);
DFFSR _522_ (
.C(SD_CLK),
.D(_001_[6]),
.Q(parallel_out[6]),
.R(_207_),
.S(1'b0)
);
DFFSR _523_ (
.C(SD_CLK),
.D(_001_[7]),
.Q(parallel_out[7]),
.R(_208_),
.S(1'b0)
);
DFFSR _524_ (
.C(SD_CLK),
.D(_001_[8]),
.Q(parallel_out[8]),
.R(_209_),
.S(1'b0)
);
DFFSR _525_ (
.C(SD_CLK),
.D(_001_[9]),
.Q(parallel_out[9]),
.R(_036_),
.S(1'b0)
);
DFFSR _526_ (
.C(SD_CLK),
.D(_001_[10]),
.Q(parallel_out[10]),
.R(_037_),
.S(1'b0)
);
DFFSR _527_ (
.C(SD_CLK),
.D(_001_[11]),
.Q(parallel_out[11]),
.R(_039_),
.S(1'b0)
);
DFFSR _528_ (
.C(SD_CLK),
.D(_001_[12]),
.Q(parallel_out[12]),
.R(_041_),
.S(1'b0)
);
DFFSR _529_ (
.C(SD_CLK),
.D(_001_[13]),
.Q(parallel_out[13]),
.R(_210_),
.S(1'b0)
);
DFFSR _530_ (
.C(SD_CLK),
.D(_001_[14]),
.Q(parallel_out[14]),
.R(_211_),
.S(1'b0)
);
DFFSR _531_ (
.C(SD_CLK),
.D(_001_[15]),
.Q(parallel_out[15]),
.R(_212_),
.S(1'b0)
);
DFFSR _532_ (
.C(SD_CLK),
.D(_001_[16]),
.Q(parallel_out[16]),
.R(_213_),
.S(1'b0)
);
DFFSR _533_ (
.C(SD_CLK),
.D(_001_[17]),
.Q(parallel_out[17]),
.R(_214_),
.S(1'b0)
);
DFFSR _534_ (
.C(SD_CLK),
.D(_001_[18]),
.Q(parallel_out[18]),
.R(_215_),
.S(1'b0)
);
DFFSR _535_ (
.C(SD_CLK),
.D(_001_[19]),
.Q(parallel_out[19]),
.R(_216_),
.S(1'b0)
);
DFFSR _536_ (
.C(SD_CLK),
.D(_001_[20]),
.Q(parallel_out[20]),
.R(_217_),
.S(1'b0)
);
DFFSR _537_ (
.C(SD_CLK),
.D(_001_[21]),
.Q(parallel_out[21]),
.R(_218_),
.S(1'b0)
);
DFFSR _538_ (
.C(SD_CLK),
.D(_001_[22]),
.Q(parallel_out[22]),
.R(_219_),
.S(1'b0)
);
DFFSR _539_ (
.C(SD_CLK),
.D(_001_[23]),
.Q(parallel_out[23]),
.R(_220_),
.S(1'b0)
);
DFFSR _540_ (
.C(SD_CLK),
.D(_001_[24]),
.Q(parallel_out[24]),
.R(_221_),
.S(1'b0)
);
DFFSR _541_ (
.C(SD_CLK),
.D(_001_[25]),
.Q(parallel_out[25]),
.R(_222_),
.S(1'b0)
);
DFFSR _542_ (
.C(SD_CLK),
.D(_001_[26]),
.Q(parallel_out[26]),
.R(_223_),
.S(1'b0)
);
DFFSR _543_ (
.C(SD_CLK),
.D(_001_[27]),
.Q(parallel_out[27]),
.R(_224_),
.S(1'b0)
);
DFFSR _544_ (
.C(SD_CLK),
.D(_001_[28]),
.Q(parallel_out[28]),
.R(_225_),
.S(1'b0)
);
DFFSR _545_ (
.C(SD_CLK),
.D(_001_[29]),
.Q(parallel_out[29]),
.R(_226_),
.S(1'b0)
);
DFFSR _546_ (
.C(SD_CLK),
.D(_001_[30]),
.Q(parallel_out[30]),
.R(_227_),
.S(1'b0)
);
DFFSR _547_ (
.C(SD_CLK),
.D(_001_[31]),
.Q(parallel_out[31]),
.R(_228_),
.S(1'b0)
);
DFFSR _548_ (
.C(SD_CLK),
.D(_000_[0]),
.Q(contador[0]),
.R(_229_),
.S(1'b0)
);
DFFSR _549_ (
.C(SD_CLK),
.D(_000_[1]),
.Q(contador[1]),
.R(_230_),
.S(1'b0)
);
DFFSR _550_ (
.C(SD_CLK),
.D(_000_[2]),
.Q(contador[2]),
.R(_231_),
.S(1'b0)
);
DFFSR _551_ (
.C(SD_CLK),
.D(_000_[3]),
.Q(contador[3]),
.R(_232_),
.S(1'b0)
);
DFFSR _552_ (
.C(SD_CLK),
.D(_000_[4]),
.Q(contador[4]),
.R(_233_),
.S(1'b0)
);
DFFSR _553_ (
.C(SD_CLK),
.D(_000_[5]),
.Q(contador[5]),
.R(_234_),
.S(1'b0)
);
DFFSR _554_ (
.C(SD_CLK),
.D(_000_[6]),
.Q(contador[6]),
.R(_235_),
.S(1'b0)
);
DFFSR _555_ (
.C(SD_CLK),
.D(_000_[7]),
.Q(contador[7]),
.R(_236_),
.S(1'b0)
);
DFFSR _556_ (
.C(SD_CLK),
.D(_000_[8]),
.Q(contador[8]),
.R(_237_),
.S(1'b0)
);
endmodule
module cmd_control(clk_host, reset_host, new_command, cmd_argument, cmd_index, ack_in, strobe_in, cmd_in, response, cmd_complete, cmd_index_error, strobe_out, ack_out, idle_out, cmd_out);
wire _0000_;
wire _0001_;
wire [39:0] _0002_;
wire _0003_;
wire [127:0] _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire [39:0] _0008_;
wire [1:0] _0009_;
wire _0010_;
wire [127:0] _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire [1:0] _0015_;
wire _0016_;
wire [127:0] _0017_;
wire _0018_;
wire [1:0] _0019_;
wire [1:0] _0020_;
wire [1:0] _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire [1:0] _0601_;
wire [1:0] _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire [39:0] _0609_;
wire [5:0] _0610_;
wire [1:0] _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
input ack_in;
output ack_out;
input clk_host;
input [31:0] cmd_argument;
output cmd_complete;
input [135:0] cmd_in;
input [5:0] cmd_index;
output cmd_index_error;
output [39:0] cmd_out;
wire [1:0] estado;
output idle_out;
input new_command;
input reset_host;
output [127:0] response;
input strobe_in;
output strobe_out;
NOT _0615_ (
.A(_0033_),
.Y(_0036_)
);
NOT _0616_ (
.A(_0550_),
.Y(_0037_)
);
NOR _0617_ (
.A(_0037_),
.B(_0036_),
.Y(_0038_)
);
NAND _0618_ (
.A(_0037_),
.B(_0549_),
.Y(_0039_)
);
NOR _0619_ (
.A(_0143_),
.B(_0033_),
.Y(_0040_)
);
NOR _0620_ (
.A(_0040_),
.B(_0039_),
.Y(_0041_)
);
NOR _0621_ (
.A(_0041_),
.B(_0038_),
.Y(_0022_)
);
NOT _0622_ (
.A(_0549_),
.Y(_0042_)
);
NOR _0623_ (
.A(_0037_),
.B(_0042_),
.Y(_0043_)
);
NOT _0624_ (
.A(_0064_),
.Y(_0044_)
);
NOT _0625_ (
.A(_0261_),
.Y(_0046_)
);
NOR _0626_ (
.A(_0046_),
.B(_0044_),
.Y(_0047_)
);
NOR _0627_ (
.A(_0047_),
.B(_0033_),
.Y(_0048_)
);
NAND _0628_ (
.A(_0048_),
.B(_0043_),
.Y(_0049_)
);
NAND _0629_ (
.A(_0143_),
.B(_0036_),
.Y(_0050_)
);
NOR _0630_ (
.A(_0050_),
.B(_0039_),
.Y(_0051_)
);
NAND _0631_ (
.A(_0550_),
.B(_0042_),
.Y(_0052_)
);
NOR _0632_ (
.A(_0052_),
.B(_0033_),
.Y(_0350_)
);
NOR _0633_ (
.A(_0350_),
.B(_0051_),
.Y(_0053_)
);
NAND _0634_ (
.A(_0053_),
.B(_0049_),
.Y(_0082_)
);
NOT _0635_ (
.A(_0349_),
.Y(_0054_)
);
NOR _0636_ (
.A(_0037_),
.B(_0549_),
.Y(_0055_)
);
NAND _0637_ (
.A(_0055_),
.B(_0036_),
.Y(_0056_)
);
NOR _0638_ (
.A(_0056_),
.B(_0054_),
.Y(_0263_)
);
NOT _0639_ (
.A(_0380_),
.Y(_0057_)
);
NOR _0640_ (
.A(_0056_),
.B(_0057_),
.Y(_0266_)
);
NOT _0641_ (
.A(_0411_),
.Y(_0058_)
);
NOR _0642_ (
.A(_0056_),
.B(_0058_),
.Y(_0268_)
);
NOT _0643_ (
.A(_0442_),
.Y(_0059_)
);
NOR _0644_ (
.A(_0056_),
.B(_0059_),
.Y(_0270_)
);
NOT _0645_ (
.A(_0473_),
.Y(_0060_)
);
NOR _0646_ (
.A(_0056_),
.B(_0060_),
.Y(_0272_)
);
NOT _0647_ (
.A(_0504_),
.Y(_0061_)
);
NOR _0648_ (
.A(_0056_),
.B(_0061_),
.Y(_0274_)
);
NOT _0649_ (
.A(_0533_),
.Y(_0062_)
);
NOR _0650_ (
.A(_0056_),
.B(_0062_),
.Y(_0276_)
);
NOT _0651_ (
.A(_0548_),
.Y(_0063_)
);
NOR _0652_ (
.A(_0056_),
.B(_0063_),
.Y(_0278_)
);
NOT _0653_ (
.A(_0551_),
.Y(_0065_)
);
NOR _0654_ (
.A(_0056_),
.B(_0065_),
.Y(_0280_)
);
NOT _0655_ (
.A(_0552_),
.Y(_0068_)
);
NOR _0656_ (
.A(_0056_),
.B(_0068_),
.Y(_0282_)
);
NOT _0657_ (
.A(_0553_),
.Y(_0071_)
);
NOR _0658_ (
.A(_0056_),
.B(_0071_),
.Y(_0284_)
);
NOT _0659_ (
.A(_0554_),
.Y(_0074_)
);
NOR _0660_ (
.A(_0056_),
.B(_0074_),
.Y(_0287_)
);
NOT _0661_ (
.A(_0555_),
.Y(_0077_)
);
NOR _0662_ (
.A(_0056_),
.B(_0077_),
.Y(_0289_)
);
NOT _0663_ (
.A(_0556_),
.Y(_0080_)
);
NOR _0664_ (
.A(_0056_),
.B(_0080_),
.Y(_0291_)
);
NOT _0665_ (
.A(_0557_),
.Y(_0084_)
);
NOR _0666_ (
.A(_0056_),
.B(_0084_),
.Y(_0293_)
);
NOT _0667_ (
.A(_0558_),
.Y(_0087_)
);
NOR _0668_ (
.A(_0056_),
.B(_0087_),
.Y(_0295_)
);
NOT _0669_ (
.A(_0559_),
.Y(_0090_)
);
NOR _0670_ (
.A(_0056_),
.B(_0090_),
.Y(_0297_)
);
NOT _0671_ (
.A(_0560_),
.Y(_0093_)
);
NOR _0672_ (
.A(_0056_),
.B(_0093_),
.Y(_0299_)
);
NOT _0673_ (
.A(_0561_),
.Y(_0096_)
);
NOR _0674_ (
.A(_0056_),
.B(_0096_),
.Y(_0301_)
);
NOT _0675_ (
.A(_0562_),
.Y(_0099_)
);
NOR _0676_ (
.A(_0056_),
.B(_0099_),
.Y(_0303_)
);
NOT _0677_ (
.A(_0023_),
.Y(_0102_)
);
NOR _0678_ (
.A(_0056_),
.B(_0102_),
.Y(_0305_)
);
NOT _0679_ (
.A(_0024_),
.Y(_0105_)
);
NOR _0680_ (
.A(_0056_),
.B(_0105_),
.Y(_0308_)
);
NOT _0681_ (
.A(_0025_),
.Y(_0108_)
);
NOR _0682_ (
.A(_0056_),
.B(_0108_),
.Y(_0310_)
);
NOT _0683_ (
.A(_0026_),
.Y(_0111_)
);
NOR _0684_ (
.A(_0056_),
.B(_0111_),
.Y(_0312_)
);
NOT _0685_ (
.A(_0027_),
.Y(_0114_)
);
NOR _0686_ (
.A(_0056_),
.B(_0114_),
.Y(_0314_)
);
NOT _0687_ (
.A(_0028_),
.Y(_0117_)
);
NOR _0688_ (
.A(_0056_),
.B(_0117_),
.Y(_0316_)
);
NOT _0689_ (
.A(_0029_),
.Y(_0120_)
);
NOR _0690_ (
.A(_0056_),
.B(_0120_),
.Y(_0318_)
);
NOT _0691_ (
.A(_0030_),
.Y(_0123_)
);
NOR _0692_ (
.A(_0056_),
.B(_0123_),
.Y(_0320_)
);
NOT _0693_ (
.A(_0031_),
.Y(_0126_)
);
NOR _0694_ (
.A(_0056_),
.B(_0126_),
.Y(_0322_)
);
NOT _0695_ (
.A(_0032_),
.Y(_0129_)
);
NOR _0696_ (
.A(_0056_),
.B(_0129_),
.Y(_0324_)
);
NOT _0697_ (
.A(_0034_),
.Y(_0132_)
);
NOR _0698_ (
.A(_0056_),
.B(_0132_),
.Y(_0326_)
);
NOT _0699_ (
.A(_0035_),
.Y(_0135_)
);
NOR _0700_ (
.A(_0056_),
.B(_0135_),
.Y(_0329_)
);
NOT _0701_ (
.A(_0205_),
.Y(_0138_)
);
NOR _0702_ (
.A(_0056_),
.B(_0138_),
.Y(_0331_)
);
NOT _0703_ (
.A(_0236_),
.Y(_0141_)
);
NOR _0704_ (
.A(_0056_),
.B(_0141_),
.Y(_0333_)
);
NOT _0705_ (
.A(_0265_),
.Y(_0145_)
);
NOR _0706_ (
.A(_0056_),
.B(_0145_),
.Y(_0335_)
);
NOT _0707_ (
.A(_0286_),
.Y(_0148_)
);
NOR _0708_ (
.A(_0056_),
.B(_0148_),
.Y(_0337_)
);
NOT _0709_ (
.A(_0307_),
.Y(_0151_)
);
NOR _0710_ (
.A(_0056_),
.B(_0151_),
.Y(_0339_)
);
NOT _0711_ (
.A(_0328_),
.Y(_0154_)
);
NOR _0712_ (
.A(_0056_),
.B(_0154_),
.Y(_0341_)
);
NOT _0713_ (
.A(_0040_),
.Y(_0158_)
);
NOR _0714_ (
.A(_0158_),
.B(_0039_),
.Y(_0345_)
);
NOR _0715_ (
.A(_0044_),
.B(_0033_),
.Y(_0161_)
);
NAND _0716_ (
.A(_0161_),
.B(_0043_),
.Y(_0163_)
);
NOT _0717_ (
.A(_0163_),
.Y(_0347_)
);
NOT _0718_ (
.A(_0544_),
.Y(_0166_)
);
NOR _0719_ (
.A(_0166_),
.B(_0045_),
.Y(_0168_)
);
NOR _0720_ (
.A(_0168_),
.B(_0163_),
.Y(_0351_)
);
NOT _0721_ (
.A(_0066_),
.Y(_0171_)
);
NOR _0722_ (
.A(_0163_),
.B(_0171_),
.Y(_0353_)
);
NOT _0723_ (
.A(_0067_),
.Y(_0174_)
);
NOR _0724_ (
.A(_0163_),
.B(_0174_),
.Y(_0354_)
);
NOT _0725_ (
.A(_0069_),
.Y(_0177_)
);
NOR _0726_ (
.A(_0163_),
.B(_0177_),
.Y(_0356_)
);
NOT _0727_ (
.A(_0070_),
.Y(_0180_)
);
NOR _0728_ (
.A(_0163_),
.B(_0180_),
.Y(_0357_)
);
NOT _0729_ (
.A(_0072_),
.Y(_0183_)
);
NOR _0730_ (
.A(_0163_),
.B(_0183_),
.Y(_0359_)
);
NOT _0731_ (
.A(_0073_),
.Y(_0186_)
);
NOR _0732_ (
.A(_0163_),
.B(_0186_),
.Y(_0360_)
);
NOT _0733_ (
.A(_0075_),
.Y(_0189_)
);
NOR _0734_ (
.A(_0163_),
.B(_0189_),
.Y(_0362_)
);
NOT _0735_ (
.A(_0076_),
.Y(_0192_)
);
NOR _0736_ (
.A(_0163_),
.B(_0192_),
.Y(_0363_)
);
NOT _0737_ (
.A(_0078_),
.Y(_0195_)
);
NOR _0738_ (
.A(_0163_),
.B(_0195_),
.Y(_0365_)
);
NOT _0739_ (
.A(_0079_),
.Y(_0198_)
);
NOR _0740_ (
.A(_0163_),
.B(_0198_),
.Y(_0366_)
);
NOT _0741_ (
.A(_0081_),
.Y(_0201_)
);
NOR _0742_ (
.A(_0163_),
.B(_0201_),
.Y(_0368_)
);
NOT _0743_ (
.A(_0083_),
.Y(_0204_)
);
NOR _0744_ (
.A(_0163_),
.B(_0204_),
.Y(_0369_)
);
NOT _0745_ (
.A(_0085_),
.Y(_0208_)
);
NOR _0746_ (
.A(_0163_),
.B(_0208_),
.Y(_0371_)
);
NOT _0747_ (
.A(_0086_),
.Y(_0211_)
);
NOR _0748_ (
.A(_0163_),
.B(_0211_),
.Y(_0372_)
);
NOT _0749_ (
.A(_0088_),
.Y(_0214_)
);
NOR _0750_ (
.A(_0163_),
.B(_0214_),
.Y(_0374_)
);
NOT _0751_ (
.A(_0089_),
.Y(_0217_)
);
NOR _0752_ (
.A(_0163_),
.B(_0217_),
.Y(_0375_)
);
NOT _0753_ (
.A(_0091_),
.Y(_0220_)
);
NOR _0754_ (
.A(_0163_),
.B(_0220_),
.Y(_0377_)
);
NOT _0755_ (
.A(_0092_),
.Y(_0223_)
);
NOR _0756_ (
.A(_0163_),
.B(_0223_),
.Y(_0378_)
);
NOT _0757_ (
.A(_0094_),
.Y(_0226_)
);
NOR _0758_ (
.A(_0163_),
.B(_0226_),
.Y(_0381_)
);
NOT _0759_ (
.A(_0095_),
.Y(_0229_)
);
NOR _0760_ (
.A(_0163_),
.B(_0229_),
.Y(_0382_)
);
NOT _0761_ (
.A(_0097_),
.Y(_0232_)
);
NOR _0762_ (
.A(_0163_),
.B(_0232_),
.Y(_0384_)
);
NOT _0763_ (
.A(_0098_),
.Y(_0235_)
);
NOR _0764_ (
.A(_0163_),
.B(_0235_),
.Y(_0385_)
);
NOT _0765_ (
.A(_0100_),
.Y(_0239_)
);
NOR _0766_ (
.A(_0163_),
.B(_0239_),
.Y(_0387_)
);
NOT _0767_ (
.A(_0101_),
.Y(_0242_)
);
NOR _0768_ (
.A(_0163_),
.B(_0242_),
.Y(_0388_)
);
NOT _0769_ (
.A(_0103_),
.Y(_0245_)
);
NOR _0770_ (
.A(_0163_),
.B(_0245_),
.Y(_0390_)
);
NOT _0771_ (
.A(_0104_),
.Y(_0248_)
);
NOR _0772_ (
.A(_0163_),
.B(_0248_),
.Y(_0391_)
);
NOT _0773_ (
.A(_0106_),
.Y(_0251_)
);
NOR _0774_ (
.A(_0163_),
.B(_0251_),
.Y(_0393_)
);
NOT _0775_ (
.A(_0107_),
.Y(_0254_)
);
NOR _0776_ (
.A(_0163_),
.B(_0254_),
.Y(_0394_)
);
NOT _0777_ (
.A(_0109_),
.Y(_0257_)
);
NOR _0778_ (
.A(_0163_),
.B(_0257_),
.Y(_0396_)
);
NOT _0779_ (
.A(_0110_),
.Y(_0260_)
);
NOR _0780_ (
.A(_0163_),
.B(_0260_),
.Y(_0397_)
);
NOT _0781_ (
.A(_0112_),
.Y(_0262_)
);
NOR _0782_ (
.A(_0163_),
.B(_0262_),
.Y(_0399_)
);
NOT _0783_ (
.A(_0113_),
.Y(_0264_)
);
NOR _0784_ (
.A(_0163_),
.B(_0264_),
.Y(_0400_)
);
NOT _0785_ (
.A(_0115_),
.Y(_0267_)
);
NOR _0786_ (
.A(_0163_),
.B(_0267_),
.Y(_0402_)
);
NOT _0787_ (
.A(_0116_),
.Y(_0269_)
);
NOR _0788_ (
.A(_0163_),
.B(_0269_),
.Y(_0403_)
);
NOT _0789_ (
.A(_0118_),
.Y(_0271_)
);
NOR _0790_ (
.A(_0163_),
.B(_0271_),
.Y(_0405_)
);
NOT _0791_ (
.A(_0119_),
.Y(_0273_)
);
NOR _0792_ (
.A(_0163_),
.B(_0273_),
.Y(_0406_)
);
NOT _0793_ (
.A(_0121_),
.Y(_0275_)
);
NOR _0794_ (
.A(_0163_),
.B(_0275_),
.Y(_0408_)
);
NOT _0795_ (
.A(_0122_),
.Y(_0277_)
);
NOR _0796_ (
.A(_0163_),
.B(_0277_),
.Y(_0409_)
);
NOT _0797_ (
.A(_0124_),
.Y(_0279_)
);
NOR _0798_ (
.A(_0163_),
.B(_0279_),
.Y(_0412_)
);
NOT _0799_ (
.A(_0125_),
.Y(_0281_)
);
NOR _0800_ (
.A(_0163_),
.B(_0281_),
.Y(_0413_)
);
NOT _0801_ (
.A(_0127_),
.Y(_0283_)
);
NOR _0802_ (
.A(_0163_),
.B(_0283_),
.Y(_0415_)
);
NOT _0803_ (
.A(_0128_),
.Y(_0285_)
);
NOR _0804_ (
.A(_0163_),
.B(_0285_),
.Y(_0416_)
);
NOT _0805_ (
.A(_0130_),
.Y(_0288_)
);
NOR _0806_ (
.A(_0163_),
.B(_0288_),
.Y(_0418_)
);
NOT _0807_ (
.A(_0131_),
.Y(_0290_)
);
NOR _0808_ (
.A(_0163_),
.B(_0290_),
.Y(_0419_)
);
NOT _0809_ (
.A(_0133_),
.Y(_0292_)
);
NOR _0810_ (
.A(_0163_),
.B(_0292_),
.Y(_0421_)
);
NOT _0811_ (
.A(_0134_),
.Y(_0294_)
);
NOR _0812_ (
.A(_0163_),
.B(_0294_),
.Y(_0422_)
);
NOT _0813_ (
.A(_0136_),
.Y(_0296_)
);
NOR _0814_ (
.A(_0163_),
.B(_0296_),
.Y(_0424_)
);
NOT _0815_ (
.A(_0137_),
.Y(_0298_)
);
NOR _0816_ (
.A(_0163_),
.B(_0298_),
.Y(_0425_)
);
NOT _0817_ (
.A(_0139_),
.Y(_0300_)
);
NOR _0818_ (
.A(_0163_),
.B(_0300_),
.Y(_0427_)
);
NOT _0819_ (
.A(_0140_),
.Y(_0302_)
);
NOR _0820_ (
.A(_0163_),
.B(_0302_),
.Y(_0428_)
);
NOT _0821_ (
.A(_0142_),
.Y(_0304_)
);
NOR _0822_ (
.A(_0163_),
.B(_0304_),
.Y(_0430_)
);
NOT _0823_ (
.A(_0144_),
.Y(_0306_)
);
NOR _0824_ (
.A(_0163_),
.B(_0306_),
.Y(_0431_)
);
NOT _0825_ (
.A(_0146_),
.Y(_0309_)
);
NOR _0826_ (
.A(_0163_),
.B(_0309_),
.Y(_0433_)
);
NOT _0827_ (
.A(_0147_),
.Y(_0311_)
);
NOR _0828_ (
.A(_0163_),
.B(_0311_),
.Y(_0434_)
);
NOT _0829_ (
.A(_0149_),
.Y(_0313_)
);
NOR _0830_ (
.A(_0163_),
.B(_0313_),
.Y(_0436_)
);
NOT _0831_ (
.A(_0150_),
.Y(_0315_)
);
NOR _0832_ (
.A(_0163_),
.B(_0315_),
.Y(_0437_)
);
NOT _0833_ (
.A(_0152_),
.Y(_0317_)
);
NOR _0834_ (
.A(_0163_),
.B(_0317_),
.Y(_0439_)
);
NOT _0835_ (
.A(_0153_),
.Y(_0319_)
);
NOR _0836_ (
.A(_0163_),
.B(_0319_),
.Y(_0440_)
);
NOT _0837_ (
.A(_0155_),
.Y(_0321_)
);
NOR _0838_ (
.A(_0163_),
.B(_0321_),
.Y(_0443_)
);
NOT _0839_ (
.A(_0156_),
.Y(_0323_)
);
NOR _0840_ (
.A(_0163_),
.B(_0323_),
.Y(_0444_)
);
NOT _0841_ (
.A(_0157_),
.Y(_0325_)
);
NOR _0842_ (
.A(_0163_),
.B(_0325_),
.Y(_0446_)
);
NOT _0843_ (
.A(_0159_),
.Y(_0327_)
);
NOR _0844_ (
.A(_0163_),
.B(_0327_),
.Y(_0447_)
);
NOT _0845_ (
.A(_0160_),
.Y(_0330_)
);
NOR _0846_ (
.A(_0163_),
.B(_0330_),
.Y(_0449_)
);
NOT _0847_ (
.A(_0162_),
.Y(_0332_)
);
NOR _0848_ (
.A(_0163_),
.B(_0332_),
.Y(_0450_)
);
NOT _0849_ (
.A(_0164_),
.Y(_0334_)
);
NOR _0850_ (
.A(_0163_),
.B(_0334_),
.Y(_0452_)
);
NOT _0851_ (
.A(_0165_),
.Y(_0336_)
);
NOR _0852_ (
.A(_0163_),
.B(_0336_),
.Y(_0453_)
);
NOT _0853_ (
.A(_0167_),
.Y(_0338_)
);
NOR _0854_ (
.A(_0163_),
.B(_0338_),
.Y(_0455_)
);
NOT _0855_ (
.A(_0169_),
.Y(_0340_)
);
NOR _0856_ (
.A(_0163_),
.B(_0340_),
.Y(_0456_)
);
NOT _0857_ (
.A(_0170_),
.Y(_0342_)
);
NOR _0858_ (
.A(_0163_),
.B(_0342_),
.Y(_0458_)
);
NOT _0859_ (
.A(_0172_),
.Y(_0344_)
);
NOR _0860_ (
.A(_0163_),
.B(_0344_),
.Y(_0459_)
);
NOT _0861_ (
.A(_0173_),
.Y(_0346_)
);
NOR _0862_ (
.A(_0163_),
.B(_0346_),
.Y(_0461_)
);
NOT _0863_ (
.A(_0175_),
.Y(_0348_)
);
NOR _0864_ (
.A(_0163_),
.B(_0348_),
.Y(_0462_)
);
NOT _0865_ (
.A(_0176_),
.Y(_0352_)
);
NOR _0866_ (
.A(_0163_),
.B(_0352_),
.Y(_0464_)
);
NOT _0867_ (
.A(_0178_),
.Y(_0355_)
);
NOR _0868_ (
.A(_0163_),
.B(_0355_),
.Y(_0465_)
);
NOT _0869_ (
.A(_0179_),
.Y(_0358_)
);
NOR _0870_ (
.A(_0163_),
.B(_0358_),
.Y(_0467_)
);
NOT _0871_ (
.A(_0181_),
.Y(_0361_)
);
NOR _0872_ (
.A(_0163_),
.B(_0361_),
.Y(_0468_)
);
NOT _0873_ (
.A(_0182_),
.Y(_0364_)
);
NOR _0874_ (
.A(_0163_),
.B(_0364_),
.Y(_0470_)
);
NOT _0875_ (
.A(_0184_),
.Y(_0367_)
);
NOR _0876_ (
.A(_0163_),
.B(_0367_),
.Y(_0471_)
);
NOT _0877_ (
.A(_0185_),
.Y(_0370_)
);
NOR _0878_ (
.A(_0163_),
.B(_0370_),
.Y(_0474_)
);
NOT _0879_ (
.A(_0187_),
.Y(_0373_)
);
NOR _0880_ (
.A(_0163_),
.B(_0373_),
.Y(_0475_)
);
NOT _0881_ (
.A(_0188_),
.Y(_0376_)
);
NOR _0882_ (
.A(_0163_),
.B(_0376_),
.Y(_0477_)
);
NOT _0883_ (
.A(_0190_),
.Y(_0379_)
);
NOR _0884_ (
.A(_0163_),
.B(_0379_),
.Y(_0478_)
);
NOT _0885_ (
.A(_0191_),
.Y(_0383_)
);
NOR _0886_ (
.A(_0163_),
.B(_0383_),
.Y(_0480_)
);
NOT _0887_ (
.A(_0193_),
.Y(_0386_)
);
NOR _0888_ (
.A(_0163_),
.B(_0386_),
.Y(_0481_)
);
NOT _0889_ (
.A(_0194_),
.Y(_0389_)
);
NOR _0890_ (
.A(_0163_),
.B(_0389_),
.Y(_0483_)
);
NOT _0891_ (
.A(_0196_),
.Y(_0392_)
);
NOR _0892_ (
.A(_0163_),
.B(_0392_),
.Y(_0484_)
);
NOT _0893_ (
.A(_0197_),
.Y(_0395_)
);
NOR _0894_ (
.A(_0163_),
.B(_0395_),
.Y(_0486_)
);
NOT _0895_ (
.A(_0199_),
.Y(_0398_)
);
NOR _0896_ (
.A(_0163_),
.B(_0398_),
.Y(_0487_)
);
NOT _0897_ (
.A(_0200_),
.Y(_0401_)
);
NOR _0898_ (
.A(_0163_),
.B(_0401_),
.Y(_0489_)
);
NOT _0899_ (
.A(_0202_),
.Y(_0404_)
);
NOR _0900_ (
.A(_0163_),
.B(_0404_),
.Y(_0490_)
);
NOT _0901_ (
.A(_0203_),
.Y(_0407_)
);
NOR _0902_ (
.A(_0163_),
.B(_0407_),
.Y(_0492_)
);
NOT _0903_ (
.A(_0206_),
.Y(_0410_)
);
NOR _0904_ (
.A(_0163_),
.B(_0410_),
.Y(_0493_)
);
NOT _0905_ (
.A(_0207_),
.Y(_0414_)
);
NOR _0906_ (
.A(_0163_),
.B(_0414_),
.Y(_0495_)
);
NOT _0907_ (
.A(_0209_),
.Y(_0417_)
);
NOR _0908_ (
.A(_0163_),
.B(_0417_),
.Y(_0496_)
);
NOT _0909_ (
.A(_0210_),
.Y(_0420_)
);
NOR _0910_ (
.A(_0163_),
.B(_0420_),
.Y(_0498_)
);
NOT _0911_ (
.A(_0212_),
.Y(_0423_)
);
NOR _0912_ (
.A(_0163_),
.B(_0423_),
.Y(_0499_)
);
NOT _0913_ (
.A(_0213_),
.Y(_0426_)
);
NOR _0914_ (
.A(_0163_),
.B(_0426_),
.Y(_0501_)
);
NOT _0915_ (
.A(_0215_),
.Y(_0429_)
);
NOR _0916_ (
.A(_0163_),
.B(_0429_),
.Y(_0502_)
);
NOT _0917_ (
.A(_0216_),
.Y(_0432_)
);
NOR _0918_ (
.A(_0163_),
.B(_0432_),
.Y(_0505_)
);
NOT _0919_ (
.A(_0218_),
.Y(_0435_)
);
NOR _0920_ (
.A(_0163_),
.B(_0435_),
.Y(_0506_)
);
NOT _0921_ (
.A(_0219_),
.Y(_0438_)
);
NOR _0922_ (
.A(_0163_),
.B(_0438_),
.Y(_0508_)
);
NOT _0923_ (
.A(_0221_),
.Y(_0441_)
);
NOR _0924_ (
.A(_0163_),
.B(_0441_),
.Y(_0509_)
);
NOT _0925_ (
.A(_0222_),
.Y(_0445_)
);
NOR _0926_ (
.A(_0163_),
.B(_0445_),
.Y(_0511_)
);
NOT _0927_ (
.A(_0224_),
.Y(_0448_)
);
NOR _0928_ (
.A(_0163_),
.B(_0448_),
.Y(_0512_)
);
NOT _0929_ (
.A(_0225_),
.Y(_0451_)
);
NOR _0930_ (
.A(_0163_),
.B(_0451_),
.Y(_0514_)
);
NOT _0931_ (
.A(_0227_),
.Y(_0454_)
);
NOR _0932_ (
.A(_0163_),
.B(_0454_),
.Y(_0515_)
);
NOT _0933_ (
.A(_0228_),
.Y(_0457_)
);
NOR _0934_ (
.A(_0163_),
.B(_0457_),
.Y(_0517_)
);
NOT _0935_ (
.A(_0230_),
.Y(_0460_)
);
NOR _0936_ (
.A(_0163_),
.B(_0460_),
.Y(_0518_)
);
NOT _0937_ (
.A(_0231_),
.Y(_0463_)
);
NOR _0938_ (
.A(_0163_),
.B(_0463_),
.Y(_0520_)
);
NOT _0939_ (
.A(_0233_),
.Y(_0466_)
);
NOR _0940_ (
.A(_0163_),
.B(_0466_),
.Y(_0521_)
);
NOT _0941_ (
.A(_0234_),
.Y(_0469_)
);
NOR _0942_ (
.A(_0163_),
.B(_0469_),
.Y(_0523_)
);
NOT _0943_ (
.A(_0237_),
.Y(_0472_)
);
NOR _0944_ (
.A(_0163_),
.B(_0472_),
.Y(_0524_)
);
NOT _0945_ (
.A(_0238_),
.Y(_0476_)
);
NOR _0946_ (
.A(_0163_),
.B(_0476_),
.Y(_0525_)
);
NOT _0947_ (
.A(_0240_),
.Y(_0479_)
);
NOR _0948_ (
.A(_0163_),
.B(_0479_),
.Y(_0526_)
);
NOT _0949_ (
.A(_0241_),
.Y(_0482_)
);
NOR _0950_ (
.A(_0163_),
.B(_0482_),
.Y(_0528_)
);
NOT _0951_ (
.A(_0243_),
.Y(_0485_)
);
NOR _0952_ (
.A(_0163_),
.B(_0485_),
.Y(_0530_)
);
NOT _0953_ (
.A(_0244_),
.Y(_0488_)
);
NOR _0954_ (
.A(_0163_),
.B(_0488_),
.Y(_0531_)
);
NOT _0955_ (
.A(_0246_),
.Y(_0491_)
);
NOR _0956_ (
.A(_0163_),
.B(_0491_),
.Y(_0532_)
);
NOT _0957_ (
.A(_0247_),
.Y(_0494_)
);
NOR _0958_ (
.A(_0163_),
.B(_0494_),
.Y(_0534_)
);
NOT _0959_ (
.A(_0249_),
.Y(_0497_)
);
NOR _0960_ (
.A(_0163_),
.B(_0497_),
.Y(_0535_)
);
NOT _0961_ (
.A(_0250_),
.Y(_0500_)
);
NOR _0962_ (
.A(_0163_),
.B(_0500_),
.Y(_0536_)
);
NOT _0963_ (
.A(_0252_),
.Y(_0503_)
);
NOR _0964_ (
.A(_0163_),
.B(_0503_),
.Y(_0537_)
);
NOT _0965_ (
.A(_0253_),
.Y(_0507_)
);
NOR _0966_ (
.A(_0163_),
.B(_0507_),
.Y(_0538_)
);
NOT _0967_ (
.A(_0255_),
.Y(_0510_)
);
NOR _0968_ (
.A(_0163_),
.B(_0510_),
.Y(_0539_)
);
NOT _0969_ (
.A(_0256_),
.Y(_0513_)
);
NOR _0970_ (
.A(_0163_),
.B(_0513_),
.Y(_0540_)
);
NOT _0971_ (
.A(_0258_),
.Y(_0516_)
);
NOR _0972_ (
.A(_0163_),
.B(_0516_),
.Y(_0541_)
);
NOT _0973_ (
.A(_0045_),
.Y(_0519_)
);
NOR _0974_ (
.A(_0163_),
.B(_0519_),
.Y(_0542_)
);
NOT _0975_ (
.A(_0259_),
.Y(_0522_)
);
NOR _0976_ (
.A(_0163_),
.B(_0522_),
.Y(_0543_)
);
NOR _0977_ (
.A(_0041_),
.B(_0550_),
.Y(_0545_)
);
NOR _0978_ (
.A(_0038_),
.B(_0549_),
.Y(_0546_)
);
NAND _0979_ (
.A(_0052_),
.B(_0039_),
.Y(_0527_)
);
NOR _0980_ (
.A(_0161_),
.B(_0042_),
.Y(_0529_)
);
NOR _0981_ (
.A(_0529_),
.B(_0527_),
.Y(_0547_)
);
\$_DLATCH_P_ _0982_ (
.D(_0002_[0]),
.E(_0565_),
.Q(cmd_out[0])
);
\$_DLATCH_P_ _0983_ (
.D(_0002_[1]),
.E(_0565_),
.Q(cmd_out[1])
);
\$_DLATCH_P_ _0984_ (
.D(_0002_[2]),
.E(_0565_),
.Q(cmd_out[2])
);
\$_DLATCH_P_ _0985_ (
.D(_0002_[3]),
.E(_0565_),
.Q(cmd_out[3])
);
\$_DLATCH_P_ _0986_ (
.D(_0002_[4]),
.E(_0565_),
.Q(cmd_out[4])
);
\$_DLATCH_P_ _0987_ (
.D(_0002_[5]),
.E(_0565_),
.Q(cmd_out[5])
);
\$_DLATCH_P_ _0988_ (
.D(_0002_[6]),
.E(_0565_),
.Q(cmd_out[6])
);
\$_DLATCH_P_ _0989_ (
.D(_0002_[7]),
.E(_0565_),
.Q(cmd_out[7])
);
\$_DLATCH_P_ _0990_ (
.D(_0002_[8]),
.E(_0565_),
.Q(cmd_out[8])
);
\$_DLATCH_P_ _0991_ (
.D(_0002_[9]),
.E(_0565_),
.Q(cmd_out[9])
);
\$_DLATCH_P_ _0992_ (
.D(_0002_[10]),
.E(_0565_),
.Q(cmd_out[10])
);
\$_DLATCH_P_ _0993_ (
.D(_0002_[11]),
.E(_0565_),
.Q(cmd_out[11])
);
\$_DLATCH_P_ _0994_ (
.D(_0002_[12]),
.E(_0565_),
.Q(cmd_out[12])
);
\$_DLATCH_P_ _0995_ (
.D(_0002_[13]),
.E(_0565_),
.Q(cmd_out[13])
);
\$_DLATCH_P_ _0996_ (
.D(_0002_[14]),
.E(_0565_),
.Q(cmd_out[14])
);
\$_DLATCH_P_ _0997_ (
.D(_0002_[15]),
.E(_0565_),
.Q(cmd_out[15])
);
\$_DLATCH_P_ _0998_ (
.D(_0002_[16]),
.E(_0565_),
.Q(cmd_out[16])
);
\$_DLATCH_P_ _0999_ (
.D(_0002_[17]),
.E(_0565_),
.Q(cmd_out[17])
);
\$_DLATCH_P_ _1000_ (
.D(_0002_[18]),
.E(_0565_),
.Q(cmd_out[18])
);
\$_DLATCH_P_ _1001_ (
.D(_0002_[19]),
.E(_0565_),
.Q(cmd_out[19])
);
\$_DLATCH_P_ _1002_ (
.D(_0002_[20]),
.E(_0565_),
.Q(cmd_out[20])
);
\$_DLATCH_P_ _1003_ (
.D(_0002_[21]),
.E(_0565_),
.Q(cmd_out[21])
);
\$_DLATCH_P_ _1004_ (
.D(_0002_[22]),
.E(_0565_),
.Q(cmd_out[22])
);
\$_DLATCH_P_ _1005_ (
.D(_0002_[23]),
.E(_0565_),
.Q(cmd_out[23])
);
\$_DLATCH_P_ _1006_ (
.D(_0002_[24]),
.E(_0565_),
.Q(cmd_out[24])
);
\$_DLATCH_P_ _1007_ (
.D(_0002_[25]),
.E(_0565_),
.Q(cmd_out[25])
);
\$_DLATCH_P_ _1008_ (
.D(_0002_[26]),
.E(_0565_),
.Q(cmd_out[26])
);
\$_DLATCH_P_ _1009_ (
.D(_0002_[27]),
.E(_0565_),
.Q(cmd_out[27])
);
\$_DLATCH_P_ _1010_ (
.D(_0002_[28]),
.E(_0565_),
.Q(cmd_out[28])
);
\$_DLATCH_P_ _1011_ (
.D(_0002_[29]),
.E(_0565_),
.Q(cmd_out[29])
);
\$_DLATCH_P_ _1012_ (
.D(_0002_[30]),
.E(_0565_),
.Q(cmd_out[30])
);
\$_DLATCH_P_ _1013_ (
.D(_0002_[31]),
.E(_0565_),
.Q(cmd_out[31])
);
\$_DLATCH_P_ _1014_ (
.D(_0002_[32]),
.E(_0565_),
.Q(cmd_out[32])
);
\$_DLATCH_P_ _1015_ (
.D(_0002_[33]),
.E(_0565_),
.Q(cmd_out[33])
);
\$_DLATCH_P_ _1016_ (
.D(_0002_[34]),
.E(_0565_),
.Q(cmd_out[34])
);
\$_DLATCH_P_ _1017_ (
.D(_0002_[35]),
.E(_0565_),
.Q(cmd_out[35])
);
\$_DLATCH_P_ _1018_ (
.D(_0002_[36]),
.E(_0565_),
.Q(cmd_out[36])
);
\$_DLATCH_P_ _1019_ (
.D(_0002_[37]),
.E(_0565_),
.Q(cmd_out[37])
);
\$_DLATCH_P_ _1020_ (
.D(_0005_),
.E(_0565_),
.Q(cmd_out[38])
);
\$_DLATCH_P_ _1021_ (
.D(_0002_[39]),
.E(_0565_),
.Q(cmd_out[39])
);
\$_DLATCH_P_ _1022_ (
.D(_0003_),
.E(_0566_),
.Q(idle_out)
);
\$_DLATCH_P_ _1023_ (
.D(_0000_),
.E(_0568_),
.Q(ack_out)
);
\$_DLATCH_P_ _1024_ (
.D(_0004_[0]),
.E(_0568_),
.Q(response[0])
);
\$_DLATCH_P_ _1025_ (
.D(_0004_[1]),
.E(_0568_),
.Q(response[1])
);
\$_DLATCH_P_ _1026_ (
.D(_0004_[2]),
.E(_0568_),
.Q(response[2])
);
\$_DLATCH_P_ _1027_ (
.D(_0004_[3]),
.E(_0568_),
.Q(response[3])
);
\$_DLATCH_P_ _1028_ (
.D(_0004_[4]),
.E(_0568_),
.Q(response[4])
);
\$_DLATCH_P_ _1029_ (
.D(_0004_[5]),
.E(_0568_),
.Q(response[5])
);
\$_DLATCH_P_ _1030_ (
.D(_0004_[6]),
.E(_0568_),
.Q(response[6])
);
\$_DLATCH_P_ _1031_ (
.D(_0004_[7]),
.E(_0568_),
.Q(response[7])
);
\$_DLATCH_P_ _1032_ (
.D(_0004_[8]),
.E(_0568_),
.Q(response[8])
);
\$_DLATCH_P_ _1033_ (
.D(_0004_[9]),
.E(_0568_),
.Q(response[9])
);
\$_DLATCH_P_ _1034_ (
.D(_0004_[10]),
.E(_0568_),
.Q(response[10])
);
\$_DLATCH_P_ _1035_ (
.D(_0004_[11]),
.E(_0568_),
.Q(response[11])
);
\$_DLATCH_P_ _1036_ (
.D(_0004_[12]),
.E(_0568_),
.Q(response[12])
);
\$_DLATCH_P_ _1037_ (
.D(_0004_[13]),
.E(_0568_),
.Q(response[13])
);
\$_DLATCH_P_ _1038_ (
.D(_0004_[14]),
.E(_0568_),
.Q(response[14])
);
\$_DLATCH_P_ _1039_ (
.D(_0004_[15]),
.E(_0568_),
.Q(response[15])
);
\$_DLATCH_P_ _1040_ (
.D(_0004_[16]),
.E(_0568_),
.Q(response[16])
);
\$_DLATCH_P_ _1041_ (
.D(_0004_[17]),
.E(_0568_),
.Q(response[17])
);
\$_DLATCH_P_ _1042_ (
.D(_0004_[18]),
.E(_0568_),
.Q(response[18])
);
\$_DLATCH_P_ _1043_ (
.D(_0004_[19]),
.E(_0568_),
.Q(response[19])
);
\$_DLATCH_P_ _1044_ (
.D(_0004_[20]),
.E(_0568_),
.Q(response[20])
);
\$_DLATCH_P_ _1045_ (
.D(_0004_[21]),
.E(_0568_),
.Q(response[21])
);
\$_DLATCH_P_ _1046_ (
.D(_0004_[22]),
.E(_0568_),
.Q(response[22])
);
\$_DLATCH_P_ _1047_ (
.D(_0004_[23]),
.E(_0568_),
.Q(response[23])
);
\$_DLATCH_P_ _1048_ (
.D(_0004_[24]),
.E(_0568_),
.Q(response[24])
);
\$_DLATCH_P_ _1049_ (
.D(_0004_[25]),
.E(_0568_),
.Q(response[25])
);
\$_DLATCH_P_ _1050_ (
.D(_0004_[26]),
.E(_0568_),
.Q(response[26])
);
\$_DLATCH_P_ _1051_ (
.D(_0004_[27]),
.E(_0568_),
.Q(response[27])
);
\$_DLATCH_P_ _1052_ (
.D(_0004_[28]),
.E(_0568_),
.Q(response[28])
);
\$_DLATCH_P_ _1053_ (
.D(_0004_[29]),
.E(_0568_),
.Q(response[29])
);
\$_DLATCH_P_ _1054_ (
.D(_0004_[30]),
.E(_0568_),
.Q(response[30])
);
\$_DLATCH_P_ _1055_ (
.D(_0004_[31]),
.E(_0568_),
.Q(response[31])
);
\$_DLATCH_P_ _1056_ (
.D(_0004_[32]),
.E(_0568_),
.Q(response[32])
);
\$_DLATCH_P_ _1057_ (
.D(_0004_[33]),
.E(_0568_),
.Q(response[33])
);
\$_DLATCH_P_ _1058_ (
.D(_0004_[34]),
.E(_0568_),
.Q(response[34])
);
\$_DLATCH_P_ _1059_ (
.D(_0004_[35]),
.E(_0568_),
.Q(response[35])
);
\$_DLATCH_P_ _1060_ (
.D(_0004_[36]),
.E(_0568_),
.Q(response[36])
);
\$_DLATCH_P_ _1061_ (
.D(_0004_[37]),
.E(_0568_),
.Q(response[37])
);
\$_DLATCH_P_ _1062_ (
.D(_0004_[38]),
.E(_0568_),
.Q(response[38])
);
\$_DLATCH_P_ _1063_ (
.D(_0004_[39]),
.E(_0568_),
.Q(response[39])
);
\$_DLATCH_P_ _1064_ (
.D(_0004_[40]),
.E(_0568_),
.Q(response[40])
);
\$_DLATCH_P_ _1065_ (
.D(_0004_[41]),
.E(_0568_),
.Q(response[41])
);
\$_DLATCH_P_ _1066_ (
.D(_0004_[42]),
.E(_0568_),
.Q(response[42])
);
\$_DLATCH_P_ _1067_ (
.D(_0004_[43]),
.E(_0568_),
.Q(response[43])
);
\$_DLATCH_P_ _1068_ (
.D(_0004_[44]),
.E(_0568_),
.Q(response[44])
);
\$_DLATCH_P_ _1069_ (
.D(_0004_[45]),
.E(_0568_),
.Q(response[45])
);
\$_DLATCH_P_ _1070_ (
.D(_0004_[46]),
.E(_0568_),
.Q(response[46])
);
\$_DLATCH_P_ _1071_ (
.D(_0004_[47]),
.E(_0568_),
.Q(response[47])
);
\$_DLATCH_P_ _1072_ (
.D(_0004_[48]),
.E(_0568_),
.Q(response[48])
);
\$_DLATCH_P_ _1073_ (
.D(_0004_[49]),
.E(_0568_),
.Q(response[49])
);
\$_DLATCH_P_ _1074_ (
.D(_0004_[50]),
.E(_0568_),
.Q(response[50])
);
\$_DLATCH_P_ _1075_ (
.D(_0004_[51]),
.E(_0568_),
.Q(response[51])
);
\$_DLATCH_P_ _1076_ (
.D(_0004_[52]),
.E(_0568_),
.Q(response[52])
);
\$_DLATCH_P_ _1077_ (
.D(_0004_[53]),
.E(_0568_),
.Q(response[53])
);
\$_DLATCH_P_ _1078_ (
.D(_0004_[54]),
.E(_0568_),
.Q(response[54])
);
\$_DLATCH_P_ _1079_ (
.D(_0004_[55]),
.E(_0568_),
.Q(response[55])
);
\$_DLATCH_P_ _1080_ (
.D(_0004_[56]),
.E(_0568_),
.Q(response[56])
);
\$_DLATCH_P_ _1081_ (
.D(_0004_[57]),
.E(_0568_),
.Q(response[57])
);
\$_DLATCH_P_ _1082_ (
.D(_0004_[58]),
.E(_0568_),
.Q(response[58])
);
\$_DLATCH_P_ _1083_ (
.D(_0004_[59]),
.E(_0568_),
.Q(response[59])
);
\$_DLATCH_P_ _1084_ (
.D(_0004_[60]),
.E(_0568_),
.Q(response[60])
);
\$_DLATCH_P_ _1085_ (
.D(_0004_[61]),
.E(_0568_),
.Q(response[61])
);
\$_DLATCH_P_ _1086_ (
.D(_0004_[62]),
.E(_0568_),
.Q(response[62])
);
\$_DLATCH_P_ _1087_ (
.D(_0004_[63]),
.E(_0568_),
.Q(response[63])
);
\$_DLATCH_P_ _1088_ (
.D(_0004_[64]),
.E(_0568_),
.Q(response[64])
);
\$_DLATCH_P_ _1089_ (
.D(_0004_[65]),
.E(_0568_),
.Q(response[65])
);
\$_DLATCH_P_ _1090_ (
.D(_0004_[66]),
.E(_0568_),
.Q(response[66])
);
\$_DLATCH_P_ _1091_ (
.D(_0004_[67]),
.E(_0568_),
.Q(response[67])
);
\$_DLATCH_P_ _1092_ (
.D(_0004_[68]),
.E(_0568_),
.Q(response[68])
);
\$_DLATCH_P_ _1093_ (
.D(_0004_[69]),
.E(_0568_),
.Q(response[69])
);
\$_DLATCH_P_ _1094_ (
.D(_0004_[70]),
.E(_0568_),
.Q(response[70])
);
\$_DLATCH_P_ _1095_ (
.D(_0004_[71]),
.E(_0568_),
.Q(response[71])
);
\$_DLATCH_P_ _1096_ (
.D(_0004_[72]),
.E(_0568_),
.Q(response[72])
);
\$_DLATCH_P_ _1097_ (
.D(_0004_[73]),
.E(_0568_),
.Q(response[73])
);
\$_DLATCH_P_ _1098_ (
.D(_0004_[74]),
.E(_0568_),
.Q(response[74])
);
\$_DLATCH_P_ _1099_ (
.D(_0004_[75]),
.E(_0568_),
.Q(response[75])
);
\$_DLATCH_P_ _1100_ (
.D(_0004_[76]),
.E(_0568_),
.Q(response[76])
);
\$_DLATCH_P_ _1101_ (
.D(_0004_[77]),
.E(_0568_),
.Q(response[77])
);
\$_DLATCH_P_ _1102_ (
.D(_0004_[78]),
.E(_0568_),
.Q(response[78])
);
\$_DLATCH_P_ _1103_ (
.D(_0004_[79]),
.E(_0568_),
.Q(response[79])
);
\$_DLATCH_P_ _1104_ (
.D(_0004_[80]),
.E(_0568_),
.Q(response[80])
);
\$_DLATCH_P_ _1105_ (
.D(_0004_[81]),
.E(_0568_),
.Q(response[81])
);
\$_DLATCH_P_ _1106_ (
.D(_0004_[82]),
.E(_0568_),
.Q(response[82])
);
\$_DLATCH_P_ _1107_ (
.D(_0004_[83]),
.E(_0568_),
.Q(response[83])
);
\$_DLATCH_P_ _1108_ (
.D(_0004_[84]),
.E(_0568_),
.Q(response[84])
);
\$_DLATCH_P_ _1109_ (
.D(_0004_[85]),
.E(_0568_),
.Q(response[85])
);
\$_DLATCH_P_ _1110_ (
.D(_0004_[86]),
.E(_0568_),
.Q(response[86])
);
\$_DLATCH_P_ _1111_ (
.D(_0004_[87]),
.E(_0568_),
.Q(response[87])
);
\$_DLATCH_P_ _1112_ (
.D(_0004_[88]),
.E(_0568_),
.Q(response[88])
);
\$_DLATCH_P_ _1113_ (
.D(_0004_[89]),
.E(_0568_),
.Q(response[89])
);
\$_DLATCH_P_ _1114_ (
.D(_0004_[90]),
.E(_0568_),
.Q(response[90])
);
\$_DLATCH_P_ _1115_ (
.D(_0004_[91]),
.E(_0568_),
.Q(response[91])
);
\$_DLATCH_P_ _1116_ (
.D(_0004_[92]),
.E(_0568_),
.Q(response[92])
);
\$_DLATCH_P_ _1117_ (
.D(_0004_[93]),
.E(_0568_),
.Q(response[93])
);
\$_DLATCH_P_ _1118_ (
.D(_0004_[94]),
.E(_0568_),
.Q(response[94])
);
\$_DLATCH_P_ _1119_ (
.D(_0004_[95]),
.E(_0568_),
.Q(response[95])
);
\$_DLATCH_P_ _1120_ (
.D(_0004_[96]),
.E(_0568_),
.Q(response[96])
);
\$_DLATCH_P_ _1121_ (
.D(_0004_[97]),
.E(_0568_),
.Q(response[97])
);
\$_DLATCH_P_ _1122_ (
.D(_0004_[98]),
.E(_0568_),
.Q(response[98])
);
\$_DLATCH_P_ _1123_ (
.D(_0004_[99]),
.E(_0568_),
.Q(response[99])
);
\$_DLATCH_P_ _1124_ (
.D(_0004_[100]),
.E(_0568_),
.Q(response[100])
);
\$_DLATCH_P_ _1125_ (
.D(_0004_[101]),
.E(_0568_),
.Q(response[101])
);
\$_DLATCH_P_ _1126_ (
.D(_0004_[102]),
.E(_0568_),
.Q(response[102])
);
\$_DLATCH_P_ _1127_ (
.D(_0004_[103]),
.E(_0568_),
.Q(response[103])
);
\$_DLATCH_P_ _1128_ (
.D(_0004_[104]),
.E(_0568_),
.Q(response[104])
);
\$_DLATCH_P_ _1129_ (
.D(_0004_[105]),
.E(_0568_),
.Q(response[105])
);
\$_DLATCH_P_ _1130_ (
.D(_0004_[106]),
.E(_0568_),
.Q(response[106])
);
\$_DLATCH_P_ _1131_ (
.D(_0004_[107]),
.E(_0568_),
.Q(response[107])
);
\$_DLATCH_P_ _1132_ (
.D(_0004_[108]),
.E(_0568_),
.Q(response[108])
);
\$_DLATCH_P_ _1133_ (
.D(_0004_[109]),
.E(_0568_),
.Q(response[109])
);
\$_DLATCH_P_ _1134_ (
.D(_0004_[110]),
.E(_0568_),
.Q(response[110])
);
\$_DLATCH_P_ _1135_ (
.D(_0004_[111]),
.E(_0568_),
.Q(response[111])
);
\$_DLATCH_P_ _1136_ (
.D(_0004_[112]),
.E(_0568_),
.Q(response[112])
);
\$_DLATCH_P_ _1137_ (
.D(_0004_[113]),
.E(_0568_),
.Q(response[113])
);
\$_DLATCH_P_ _1138_ (
.D(_0004_[114]),
.E(_0568_),
.Q(response[114])
);
\$_DLATCH_P_ _1139_ (
.D(_0004_[115]),
.E(_0568_),
.Q(response[115])
);
\$_DLATCH_P_ _1140_ (
.D(_0004_[116]),
.E(_0568_),
.Q(response[116])
);
\$_DLATCH_P_ _1141_ (
.D(_0004_[117]),
.E(_0568_),
.Q(response[117])
);
\$_DLATCH_P_ _1142_ (
.D(_0004_[118]),
.E(_0568_),
.Q(response[118])
);
\$_DLATCH_P_ _1143_ (
.D(_0004_[119]),
.E(_0568_),
.Q(response[119])
);
\$_DLATCH_P_ _1144_ (
.D(_0004_[120]),
.E(_0568_),
.Q(response[120])
);
\$_DLATCH_P_ _1145_ (
.D(_0004_[121]),
.E(_0568_),
.Q(response[121])
);
\$_DLATCH_P_ _1146_ (
.D(_0004_[122]),
.E(_0568_),
.Q(response[122])
);
\$_DLATCH_P_ _1147_ (
.D(_0004_[123]),
.E(_0568_),
.Q(response[123])
);
\$_DLATCH_P_ _1148_ (
.D(_0004_[124]),
.E(_0568_),
.Q(response[124])
);
\$_DLATCH_P_ _1149_ (
.D(_0004_[125]),
.E(_0568_),
.Q(response[125])
);
\$_DLATCH_P_ _1150_ (
.D(_0004_[126]),
.E(_0568_),
.Q(response[126])
);
\$_DLATCH_P_ _1151_ (
.D(_0004_[127]),
.E(_0568_),
.Q(response[127])
);
\$_DLATCH_P_ _1152_ (
.D(_0001_),
.E(_0568_),
.Q(cmd_index_error)
);
assign cmd_complete = ack_out;
assign strobe_out = cmd_out[38];
assign _0563_ = estado[0];
assign _0564_ = estado[1];
assign _0343_ = 1'b0;
assign estado[0] = _0022_;
assign estado[1] = _0082_;
assign _0033_ = reset_host;
assign _0045_ = cmd_in[134];
assign _0143_ = new_command;
assign _0205_ = cmd_index[0];
assign _0236_ = cmd_index[1];
assign _0265_ = cmd_index[2];
assign _0286_ = cmd_index[3];
assign _0307_ = cmd_index[4];
assign _0328_ = cmd_index[5];
assign _0349_ = cmd_argument[0];
assign _0380_ = cmd_argument[1];
assign _0411_ = cmd_argument[2];
assign _0442_ = cmd_argument[3];
assign _0473_ = cmd_argument[4];
assign _0504_ = cmd_argument[5];
assign _0533_ = cmd_argument[6];
assign _0548_ = cmd_argument[7];
assign _0551_ = cmd_argument[8];
assign _0552_ = cmd_argument[9];
assign _0553_ = cmd_argument[10];
assign _0554_ = cmd_argument[11];
assign _0555_ = cmd_argument[12];
assign _0556_ = cmd_argument[13];
assign _0557_ = cmd_argument[14];
assign _0558_ = cmd_argument[15];
assign _0559_ = cmd_argument[16];
assign _0560_ = cmd_argument[17];
assign _0561_ = cmd_argument[18];
assign _0562_ = cmd_argument[19];
assign _0023_ = cmd_argument[20];
assign _0024_ = cmd_argument[21];
assign _0025_ = cmd_argument[22];
assign _0026_ = cmd_argument[23];
assign _0027_ = cmd_argument[24];
assign _0028_ = cmd_argument[25];
assign _0029_ = cmd_argument[26];
assign _0030_ = cmd_argument[27];
assign _0031_ = cmd_argument[28];
assign _0032_ = cmd_argument[29];
assign _0034_ = cmd_argument[30];
assign _0035_ = cmd_argument[31];
assign _0064_ = strobe_in;
assign _0066_ = cmd_in[8];
assign _0067_ = cmd_in[9];
assign _0069_ = cmd_in[10];
assign _0070_ = cmd_in[11];
assign _0072_ = cmd_in[12];
assign _0073_ = cmd_in[13];
assign _0075_ = cmd_in[14];
assign _0076_ = cmd_in[15];
assign _0078_ = cmd_in[16];
assign _0079_ = cmd_in[17];
assign _0081_ = cmd_in[18];
assign _0083_ = cmd_in[19];
assign _0085_ = cmd_in[20];
assign _0086_ = cmd_in[21];
assign _0088_ = cmd_in[22];
assign _0089_ = cmd_in[23];
assign _0091_ = cmd_in[24];
assign _0092_ = cmd_in[25];
assign _0094_ = cmd_in[26];
assign _0095_ = cmd_in[27];
assign _0097_ = cmd_in[28];
assign _0098_ = cmd_in[29];
assign _0100_ = cmd_in[30];
assign _0101_ = cmd_in[31];
assign _0103_ = cmd_in[32];
assign _0104_ = cmd_in[33];
assign _0106_ = cmd_in[34];
assign _0107_ = cmd_in[35];
assign _0109_ = cmd_in[36];
assign _0110_ = cmd_in[37];
assign _0112_ = cmd_in[38];
assign _0113_ = cmd_in[39];
assign _0115_ = cmd_in[40];
assign _0116_ = cmd_in[41];
assign _0118_ = cmd_in[42];
assign _0119_ = cmd_in[43];
assign _0121_ = cmd_in[44];
assign _0122_ = cmd_in[45];
assign _0124_ = cmd_in[46];
assign _0125_ = cmd_in[47];
assign _0127_ = cmd_in[48];
assign _0128_ = cmd_in[49];
assign _0130_ = cmd_in[50];
assign _0131_ = cmd_in[51];
assign _0133_ = cmd_in[52];
assign _0134_ = cmd_in[53];
assign _0136_ = cmd_in[54];
assign _0137_ = cmd_in[55];
assign _0139_ = cmd_in[56];
assign _0140_ = cmd_in[57];
assign _0142_ = cmd_in[58];
assign _0144_ = cmd_in[59];
assign _0146_ = cmd_in[60];
assign _0147_ = cmd_in[61];
assign _0149_ = cmd_in[62];
assign _0150_ = cmd_in[63];
assign _0152_ = cmd_in[64];
assign _0153_ = cmd_in[65];
assign _0155_ = cmd_in[66];
assign _0156_ = cmd_in[67];
assign _0157_ = cmd_in[68];
assign _0159_ = cmd_in[69];
assign _0160_ = cmd_in[70];
assign _0162_ = cmd_in[71];
assign _0164_ = cmd_in[72];
assign _0165_ = cmd_in[73];
assign _0167_ = cmd_in[74];
assign _0169_ = cmd_in[75];
assign _0170_ = cmd_in[76];
assign _0172_ = cmd_in[77];
assign _0173_ = cmd_in[78];
assign _0175_ = cmd_in[79];
assign _0176_ = cmd_in[80];
assign _0178_ = cmd_in[81];
assign _0179_ = cmd_in[82];
assign _0181_ = cmd_in[83];
assign _0182_ = cmd_in[84];
assign _0184_ = cmd_in[85];
assign _0185_ = cmd_in[86];
assign _0187_ = cmd_in[87];
assign _0188_ = cmd_in[88];
assign _0190_ = cmd_in[89];
assign _0191_ = cmd_in[90];
assign _0193_ = cmd_in[91];
assign _0194_ = cmd_in[92];
assign _0196_ = cmd_in[93];
assign _0197_ = cmd_in[94];
assign _0199_ = cmd_in[95];
assign _0200_ = cmd_in[96];
assign _0202_ = cmd_in[97];
assign _0203_ = cmd_in[98];
assign _0206_ = cmd_in[99];
assign _0207_ = cmd_in[100];
assign _0209_ = cmd_in[101];
assign _0210_ = cmd_in[102];
assign _0212_ = cmd_in[103];
assign _0213_ = cmd_in[104];
assign _0215_ = cmd_in[105];
assign _0216_ = cmd_in[106];
assign _0218_ = cmd_in[107];
assign _0219_ = cmd_in[108];
assign _0221_ = cmd_in[109];
assign _0222_ = cmd_in[110];
assign _0224_ = cmd_in[111];
assign _0225_ = cmd_in[112];
assign _0227_ = cmd_in[113];
assign _0228_ = cmd_in[114];
assign _0230_ = cmd_in[115];
assign _0231_ = cmd_in[116];
assign _0233_ = cmd_in[117];
assign _0234_ = cmd_in[118];
assign _0237_ = cmd_in[119];
assign _0238_ = cmd_in[120];
assign _0240_ = cmd_in[121];
assign _0241_ = cmd_in[122];
assign _0243_ = cmd_in[123];
assign _0244_ = cmd_in[124];
assign _0246_ = cmd_in[125];
assign _0247_ = cmd_in[126];
assign _0249_ = cmd_in[127];
assign _0250_ = cmd_in[128];
assign _0252_ = cmd_in[129];
assign _0253_ = cmd_in[130];
assign _0255_ = cmd_in[131];
assign _0256_ = cmd_in[132];
assign _0258_ = cmd_in[133];
assign _0259_ = cmd_in[135];
assign _0261_ = ack_in;
assign _0002_[0] = _0263_;
assign _0002_[1] = _0266_;
assign _0002_[2] = _0268_;
assign _0002_[3] = _0270_;
assign _0002_[4] = _0272_;
assign _0002_[5] = _0274_;
assign _0002_[6] = _0276_;
assign _0002_[7] = _0278_;
assign _0002_[8] = _0280_;
assign _0002_[9] = _0282_;
assign _0002_[10] = _0284_;
assign _0002_[11] = _0287_;
assign _0002_[12] = _0289_;
assign _0002_[13] = _0291_;
assign _0002_[14] = _0293_;
assign _0002_[15] = _0295_;
assign _0002_[16] = _0297_;
assign _0002_[17] = _0299_;
assign _0002_[18] = _0301_;
assign _0002_[19] = _0303_;
assign _0002_[20] = _0305_;
assign _0002_[21] = _0308_;
assign _0002_[22] = _0310_;
assign _0002_[23] = _0312_;
assign _0002_[24] = _0314_;
assign _0002_[25] = _0316_;
assign _0002_[26] = _0318_;
assign _0002_[27] = _0320_;
assign _0002_[28] = _0322_;
assign _0002_[29] = _0324_;
assign _0002_[30] = _0326_;
assign _0002_[31] = _0329_;
assign _0002_[32] = _0331_;
assign _0002_[33] = _0333_;
assign _0002_[34] = _0335_;
assign _0002_[35] = _0337_;
assign _0002_[36] = _0339_;
assign _0002_[37] = _0341_;
assign _0002_[39] = _0343_;
assign _0003_ = _0345_;
assign _0000_ = _0347_;
assign _0005_ = _0350_;
assign _0001_ = _0351_;
assign _0004_[0] = _0353_;
assign _0004_[1] = _0354_;
assign _0004_[2] = _0356_;
assign _0004_[3] = _0357_;
assign _0004_[4] = _0359_;
assign _0004_[5] = _0360_;
assign _0004_[6] = _0362_;
assign _0004_[7] = _0363_;
assign _0004_[8] = _0365_;
assign _0004_[9] = _0366_;
assign _0004_[10] = _0368_;
assign _0004_[11] = _0369_;
assign _0004_[12] = _0371_;
assign _0004_[13] = _0372_;
assign _0004_[14] = _0374_;
assign _0004_[15] = _0375_;
assign _0004_[16] = _0377_;
assign _0004_[17] = _0378_;
assign _0004_[18] = _0381_;
assign _0004_[19] = _0382_;
assign _0004_[20] = _0384_;
assign _0004_[21] = _0385_;
assign _0004_[22] = _0387_;
assign _0004_[23] = _0388_;
assign _0004_[24] = _0390_;
assign _0004_[25] = _0391_;
assign _0004_[26] = _0393_;
assign _0004_[27] = _0394_;
assign _0004_[28] = _0396_;
assign _0004_[29] = _0397_;
assign _0004_[30] = _0399_;
assign _0004_[31] = _0400_;
assign _0004_[32] = _0402_;
assign _0004_[33] = _0403_;
assign _0004_[34] = _0405_;
assign _0004_[35] = _0406_;
assign _0004_[36] = _0408_;
assign _0004_[37] = _0409_;
assign _0004_[38] = _0412_;
assign _0004_[39] = _0413_;
assign _0004_[40] = _0415_;
assign _0004_[41] = _0416_;
assign _0004_[42] = _0418_;
assign _0004_[43] = _0419_;
assign _0004_[44] = _0421_;
assign _0004_[45] = _0422_;
assign _0004_[46] = _0424_;
assign _0004_[47] = _0425_;
assign _0004_[48] = _0427_;
assign _0004_[49] = _0428_;
assign _0004_[50] = _0430_;
assign _0004_[51] = _0431_;
assign _0004_[52] = _0433_;
assign _0004_[53] = _0434_;
assign _0004_[54] = _0436_;
assign _0004_[55] = _0437_;
assign _0004_[56] = _0439_;
assign _0004_[57] = _0440_;
assign _0004_[58] = _0443_;
assign _0004_[59] = _0444_;
assign _0004_[60] = _0446_;
assign _0004_[61] = _0447_;
assign _0004_[62] = _0449_;
assign _0004_[63] = _0450_;
assign _0004_[64] = _0452_;
assign _0004_[65] = _0453_;
assign _0004_[66] = _0455_;
assign _0004_[67] = _0456_;
assign _0004_[68] = _0458_;
assign _0004_[69] = _0459_;
assign _0004_[70] = _0461_;
assign _0004_[71] = _0462_;
assign _0004_[72] = _0464_;
assign _0004_[73] = _0465_;
assign _0004_[74] = _0467_;
assign _0004_[75] = _0468_;
assign _0004_[76] = _0470_;
assign _0004_[77] = _0471_;
assign _0004_[78] = _0474_;
assign _0004_[79] = _0475_;
assign _0004_[80] = _0477_;
assign _0004_[81] = _0478_;
assign _0004_[82] = _0480_;
assign _0004_[83] = _0481_;
assign _0004_[84] = _0483_;
assign _0004_[85] = _0484_;
assign _0004_[86] = _0486_;
assign _0004_[87] = _0487_;
assign _0004_[88] = _0489_;
assign _0004_[89] = _0490_;
assign _0004_[90] = _0492_;
assign _0004_[91] = _0493_;
assign _0004_[92] = _0495_;
assign _0004_[93] = _0496_;
assign _0004_[94] = _0498_;
assign _0004_[95] = _0499_;
assign _0004_[96] = _0501_;
assign _0004_[97] = _0502_;
assign _0004_[98] = _0505_;
assign _0004_[99] = _0506_;
assign _0004_[100] = _0508_;
assign _0004_[101] = _0509_;
assign _0004_[102] = _0511_;
assign _0004_[103] = _0512_;
assign _0004_[104] = _0514_;
assign _0004_[105] = _0515_;
assign _0004_[106] = _0517_;
assign _0004_[107] = _0518_;
assign _0004_[108] = _0520_;
assign _0004_[109] = _0521_;
assign _0004_[110] = _0523_;
assign _0004_[111] = _0524_;
assign _0004_[112] = _0525_;
assign _0004_[113] = _0526_;
assign _0004_[114] = _0528_;
assign _0004_[115] = _0530_;
assign _0004_[116] = _0531_;
assign _0004_[117] = _0532_;
assign _0004_[118] = _0534_;
assign _0004_[119] = _0535_;
assign _0004_[120] = _0536_;
assign _0004_[121] = _0537_;
assign _0004_[122] = _0538_;
assign _0004_[123] = _0539_;
assign _0004_[124] = _0540_;
assign _0004_[125] = _0541_;
assign _0004_[126] = _0542_;
assign _0004_[127] = _0543_;
assign _0544_ = cmd_out[0];
assign _0566_ = _0545_;
assign _0565_ = _0546_;
assign _0568_ = _0547_;
assign _0549_ = _0563_;
assign _0550_ = _0564_;
endmodule
module control_capa_fisica(strobe_in, ack_in, idle_in, pad_response, reception_complete, transmission_complete, ack_out, strobe_out, response, load_send, enable_stp, enable_pts, reset_stp, reset_pts, reset_host, clk_SD);
wire _0000_;
wire _0001_;
wire _0002_;
wire [135:0] _0003_;
wire _0004_;
wire [2:0] _0005_;
wire [2:0] _0006_;
wire [2:0] _0007_;
wire [2:0] _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire [2:0] _0013_;
wire _0014_;
wire [135:0] _0015_;
wire _0016_;
wire [2:0] _0017_;
wire _0018_;
wire [135:0] _0019_;
wire [2:0] _0020_;
wire _0021_;
wire [2:0] _0022_;
wire _0023_;
wire _0024_;
wire [2:0] _0025_;
wire [2:0] _0026_;
wire [2:0] _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire [2:0] _0598_;
wire _0599_;
wire [2:0] _0600_;
wire _0601_;
wire [2:0] _0602_;
wire _0603_;
wire [2:0] _0604_;
wire _0605_;
wire [2:0] _0606_;
wire _0607_;
wire [2:0] _0608_;
wire _0609_;
wire [1:0] _0610_;
wire _0611_;
wire [1:0] _0612_;
wire _0613_;
wire [1:0] _0614_;
wire _0615_;
wire [1:0] _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire [1:0] _0623_;
wire [1:0] _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire _0636_;
wire _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
wire _0654_;
wire _0655_;
wire _0656_;
wire _0657_;
wire _0658_;
wire _0659_;
wire _0660_;
wire _0661_;
wire _0662_;
wire _0663_;
wire _0664_;
wire _0665_;
wire _0666_;
wire _0667_;
wire _0668_;
wire _0669_;
wire _0670_;
wire _0671_;
wire _0672_;
wire _0673_;
wire _0674_;
wire _0675_;
wire _0676_;
wire _0677_;
wire _0678_;
wire _0679_;
wire _0680_;
wire _0681_;
wire _0682_;
wire _0683_;
wire _0684_;
wire _0685_;
wire _0686_;
wire _0687_;
wire _0688_;
wire _0689_;
wire _0690_;
wire _0691_;
wire _0692_;
wire _0693_;
wire _0694_;
wire _0695_;
wire _0696_;
wire _0697_;
wire _0698_;
wire _0699_;
wire _0700_;
wire _0701_;
wire _0702_;
wire _0703_;
wire _0704_;
wire _0705_;
wire _0706_;
wire _0707_;
wire _0708_;
wire _0709_;
wire _0710_;
wire _0711_;
wire _0712_;
wire _0713_;
wire _0714_;
wire _0715_;
wire _0716_;
wire _0717_;
wire _0718_;
wire _0719_;
wire _0720_;
wire _0721_;
wire _0722_;
wire _0723_;
wire _0724_;
wire _0725_;
wire _0726_;
wire _0727_;
wire _0728_;
wire _0729_;
wire _0730_;
wire _0731_;
wire _0732_;
wire _0733_;
wire _0734_;
wire _0735_;
wire _0736_;
wire _0737_;
wire _0738_;
wire _0739_;
wire _0740_;
wire _0741_;
wire _0742_;
wire _0743_;
wire _0744_;
wire _0745_;
wire _0746_;
wire _0747_;
wire _0748_;
wire _0749_;
wire _0750_;
wire _0751_;
wire _0752_;
wire _0753_;
wire _0754_;
wire _0755_;
wire _0756_;
wire _0757_;
wire _0758_;
wire _0759_;
wire _0760_;
wire _0761_;
wire _0762_;
wire _0763_;
wire _0764_;
wire _0765_;
wire _0766_;
wire [2:0] _0767_;
wire [2:0] _0768_;
wire [2:0] _0769_;
wire _0770_;
wire _0771_;
wire _0772_;
wire _0773_;
wire _0774_;
wire _0775_;
wire [2:0] _0776_;
wire _0777_;
wire _0778_;
wire _0779_;
wire _0780_;
wire _0781_;
wire _0782_;
wire [2:0] _0783_;
wire [407:0] _0784_;
wire [3:0] _0785_;
wire _0786_;
wire [2:0] _0787_;
wire [2:0] _0788_;
wire [14:0] _0789_;
wire [2:0] _0790_;
wire _0791_;
wire _0792_;
wire _0793_;
wire _0794_;
wire _0795_;
wire _0796_;
wire _0797_;
input ack_in;
output ack_out;
input clk_SD;
output enable_pts;
output enable_stp;
wire [2:0] estado;
input idle_in;
output load_send;
input [135:0] pad_response;
input reception_complete;
input reset_host;
output reset_pts;
output reset_stp;
output [135:0] response;
input strobe_in;
output strobe_out;
input transmission_complete;
NOT _0798_ (
.A(_0029_),
.Y(_0034_)
);
NOT _0799_ (
.A(_0031_),
.Y(_0035_)
);
NAND _0800_ (
.A(_0035_),
.B(_0030_),
.Y(_0036_)
);
NOR _0801_ (
.A(_0036_),
.B(_0034_),
.Y(_0037_)
);
NOT _0802_ (
.A(_0391_),
.Y(_0038_)
);
NOR _0803_ (
.A(_0038_),
.B(_0033_),
.Y(_0039_)
);
NOR _0804_ (
.A(_0039_),
.B(_0084_),
.Y(_0040_)
);
NAND _0805_ (
.A(_0040_),
.B(_0037_),
.Y(_0041_)
);
NOT _0806_ (
.A(_0084_),
.Y(_0042_)
);
NOT _0807_ (
.A(_0030_),
.Y(_0043_)
);
NAND _0808_ (
.A(_0035_),
.B(_0043_),
.Y(_0044_)
);
NOR _0809_ (
.A(_0044_),
.B(_0034_),
.Y(_0045_)
);
NAND _0810_ (
.A(_0045_),
.B(_0042_),
.Y(_0046_)
);
NAND _0811_ (
.A(_0046_),
.B(_0041_),
.Y(_0047_)
);
NAND _0812_ (
.A(_0031_),
.B(_0030_),
.Y(_0048_)
);
NOR _0813_ (
.A(_0048_),
.B(_0029_),
.Y(_0049_)
);
NOT _0814_ (
.A(_0119_),
.Y(_0050_)
);
NOR _0815_ (
.A(_0050_),
.B(_0033_),
.Y(_0051_)
);
NOR _0816_ (
.A(_0051_),
.B(_0084_),
.Y(_0052_)
);
NAND _0817_ (
.A(_0052_),
.B(_0049_),
.Y(_0053_)
);
NAND _0818_ (
.A(_0031_),
.B(_0043_),
.Y(_0054_)
);
NOR _0819_ (
.A(_0054_),
.B(_0029_),
.Y(_0055_)
);
NOR _0820_ (
.A(_0112_),
.B(_0033_),
.Y(_0056_)
);
NOR _0821_ (
.A(_0056_),
.B(_0084_),
.Y(_0057_)
);
NAND _0822_ (
.A(_0057_),
.B(_0055_),
.Y(_0058_)
);
NAND _0823_ (
.A(_0058_),
.B(_0053_),
.Y(_0059_)
);
NOR _0824_ (
.A(_0059_),
.B(_0047_),
.Y(_0060_)
);
NOR _0825_ (
.A(_0031_),
.B(_0034_),
.Y(_0061_)
);
NOR _0826_ (
.A(_0031_),
.B(_0030_),
.Y(_0062_)
);
NOR _0827_ (
.A(_0062_),
.B(_0029_),
.Y(_0063_)
);
NOR _0828_ (
.A(_0063_),
.B(_0061_),
.Y(_0064_)
);
NOR _0829_ (
.A(_0036_),
.B(_0029_),
.Y(_0065_)
);
NAND _0830_ (
.A(_0065_),
.B(_0042_),
.Y(_0066_)
);
NOR _0831_ (
.A(_0066_),
.B(_0108_),
.Y(_0067_)
);
NOR _0832_ (
.A(_0067_),
.B(_0064_),
.Y(_0068_)
);
NAND _0833_ (
.A(_0068_),
.B(_0060_),
.Y(_0028_)
);
NOT _0834_ (
.A(_0108_),
.Y(_0069_)
);
NOR _0835_ (
.A(_0066_),
.B(_0069_),
.Y(_0070_)
);
NOR _0836_ (
.A(_0030_),
.B(_0029_),
.Y(_0071_)
);
NAND _0837_ (
.A(_0071_),
.B(_0031_),
.Y(_0072_)
);
NOT _0838_ (
.A(_0033_),
.Y(_0073_)
);
NAND _0839_ (
.A(_0042_),
.B(_0073_),
.Y(_0074_)
);
NOR _0840_ (
.A(_0074_),
.B(_0072_),
.Y(_0393_)
);
NOR _0841_ (
.A(_0393_),
.B(_0070_),
.Y(_0075_)
);
NOR _0842_ (
.A(_0084_),
.B(_0033_),
.Y(_0076_)
);
NAND _0843_ (
.A(_0076_),
.B(_0049_),
.Y(_0077_)
);
NOR _0844_ (
.A(_0077_),
.B(_0119_),
.Y(_0078_)
);
NOR _0845_ (
.A(_0031_),
.B(_0043_),
.Y(_0079_)
);
NAND _0846_ (
.A(_0079_),
.B(_0029_),
.Y(_0080_)
);
NAND _0847_ (
.A(_0076_),
.B(_0391_),
.Y(_0081_)
);
NOR _0848_ (
.A(_0081_),
.B(_0080_),
.Y(_0082_)
);
NOR _0849_ (
.A(_0082_),
.B(_0078_),
.Y(_0083_)
);
NAND _0850_ (
.A(_0083_),
.B(_0075_),
.Y(_0214_)
);
NOR _0851_ (
.A(_0035_),
.B(_0043_),
.Y(_0085_)
);
NAND _0852_ (
.A(_0085_),
.B(_0034_),
.Y(_0086_)
);
NOR _0853_ (
.A(_0086_),
.B(_0050_),
.Y(_0087_)
);
NOR _0854_ (
.A(_0087_),
.B(_0061_),
.Y(_0088_)
);
NOR _0855_ (
.A(_0088_),
.B(_0074_),
.Y(_0032_)
);
NOT _0856_ (
.A(_0066_),
.Y(_0392_)
);
NOT _0857_ (
.A(_0077_),
.Y(_0394_)
);
NOT _0858_ (
.A(_0255_),
.Y(_0089_)
);
NAND _0859_ (
.A(_0076_),
.B(_0045_),
.Y(_0090_)
);
NOR _0860_ (
.A(_0090_),
.B(_0089_),
.Y(_0396_)
);
NOT _0861_ (
.A(_0256_),
.Y(_0091_)
);
NOR _0862_ (
.A(_0090_),
.B(_0091_),
.Y(_0397_)
);
NOT _0863_ (
.A(_0257_),
.Y(_0092_)
);
NOR _0864_ (
.A(_0090_),
.B(_0092_),
.Y(_0398_)
);
NOT _0865_ (
.A(_0258_),
.Y(_0093_)
);
NOR _0866_ (
.A(_0090_),
.B(_0093_),
.Y(_0399_)
);
NOT _0867_ (
.A(_0259_),
.Y(_0094_)
);
NOR _0868_ (
.A(_0090_),
.B(_0094_),
.Y(_0400_)
);
NOT _0869_ (
.A(_0260_),
.Y(_0095_)
);
NOR _0870_ (
.A(_0090_),
.B(_0095_),
.Y(_0401_)
);
NOT _0871_ (
.A(_0261_),
.Y(_0096_)
);
NOR _0872_ (
.A(_0090_),
.B(_0096_),
.Y(_0402_)
);
NOT _0873_ (
.A(_0262_),
.Y(_0097_)
);
NOR _0874_ (
.A(_0090_),
.B(_0097_),
.Y(_0403_)
);
NOT _0875_ (
.A(_0263_),
.Y(_0098_)
);
NOR _0876_ (
.A(_0090_),
.B(_0098_),
.Y(_0404_)
);
NOT _0877_ (
.A(_0264_),
.Y(_0099_)
);
NOR _0878_ (
.A(_0090_),
.B(_0099_),
.Y(_0405_)
);
NOT _0879_ (
.A(_0265_),
.Y(_0100_)
);
NOR _0880_ (
.A(_0090_),
.B(_0100_),
.Y(_0406_)
);
NOT _0881_ (
.A(_0266_),
.Y(_0101_)
);
NOR _0882_ (
.A(_0090_),
.B(_0101_),
.Y(_0407_)
);
NOT _0883_ (
.A(_0267_),
.Y(_0102_)
);
NOR _0884_ (
.A(_0090_),
.B(_0102_),
.Y(_0408_)
);
NOT _0885_ (
.A(_0268_),
.Y(_0103_)
);
NOR _0886_ (
.A(_0090_),
.B(_0103_),
.Y(_0409_)
);
NOT _0887_ (
.A(_0269_),
.Y(_0104_)
);
NOR _0888_ (
.A(_0090_),
.B(_0104_),
.Y(_0410_)
);
NOT _0889_ (
.A(_0270_),
.Y(_0105_)
);
NOR _0890_ (
.A(_0090_),
.B(_0105_),
.Y(_0411_)
);
NOT _0891_ (
.A(_0271_),
.Y(_0106_)
);
NOR _0892_ (
.A(_0090_),
.B(_0106_),
.Y(_0412_)
);
NOT _0893_ (
.A(_0272_),
.Y(_0107_)
);
NOR _0894_ (
.A(_0090_),
.B(_0107_),
.Y(_0413_)
);
NOT _0895_ (
.A(_0273_),
.Y(_0109_)
);
NOR _0896_ (
.A(_0090_),
.B(_0109_),
.Y(_0414_)
);
NOT _0897_ (
.A(_0274_),
.Y(_0110_)
);
NOR _0898_ (
.A(_0090_),
.B(_0110_),
.Y(_0415_)
);
NOT _0899_ (
.A(_0275_),
.Y(_0111_)
);
NOR _0900_ (
.A(_0090_),
.B(_0111_),
.Y(_0416_)
);
NOT _0901_ (
.A(_0276_),
.Y(_0113_)
);
NOR _0902_ (
.A(_0090_),
.B(_0113_),
.Y(_0417_)
);
NOT _0903_ (
.A(_0277_),
.Y(_0114_)
);
NOR _0904_ (
.A(_0090_),
.B(_0114_),
.Y(_0418_)
);
NOT _0905_ (
.A(_0278_),
.Y(_0115_)
);
NOR _0906_ (
.A(_0090_),
.B(_0115_),
.Y(_0419_)
);
NOT _0907_ (
.A(_0279_),
.Y(_0116_)
);
NOR _0908_ (
.A(_0090_),
.B(_0116_),
.Y(_0420_)
);
NOT _0909_ (
.A(_0280_),
.Y(_0117_)
);
NOR _0910_ (
.A(_0090_),
.B(_0117_),
.Y(_0421_)
);
NOT _0911_ (
.A(_0281_),
.Y(_0118_)
);
NOR _0912_ (
.A(_0090_),
.B(_0118_),
.Y(_0422_)
);
NOT _0913_ (
.A(_0282_),
.Y(_0120_)
);
NOR _0914_ (
.A(_0090_),
.B(_0120_),
.Y(_0423_)
);
NOT _0915_ (
.A(_0283_),
.Y(_0121_)
);
NOR _0916_ (
.A(_0090_),
.B(_0121_),
.Y(_0424_)
);
NOT _0917_ (
.A(_0284_),
.Y(_0122_)
);
NOR _0918_ (
.A(_0090_),
.B(_0122_),
.Y(_0425_)
);
NOT _0919_ (
.A(_0285_),
.Y(_0123_)
);
NOR _0920_ (
.A(_0090_),
.B(_0123_),
.Y(_0426_)
);
NOT _0921_ (
.A(_0286_),
.Y(_0124_)
);
NOR _0922_ (
.A(_0090_),
.B(_0124_),
.Y(_0427_)
);
NOT _0923_ (
.A(_0287_),
.Y(_0125_)
);
NOR _0924_ (
.A(_0090_),
.B(_0125_),
.Y(_0428_)
);
NOT _0925_ (
.A(_0288_),
.Y(_0126_)
);
NOR _0926_ (
.A(_0090_),
.B(_0126_),
.Y(_0429_)
);
NOT _0927_ (
.A(_0289_),
.Y(_0127_)
);
NOR _0928_ (
.A(_0090_),
.B(_0127_),
.Y(_0430_)
);
NOT _0929_ (
.A(_0290_),
.Y(_0128_)
);
NOR _0930_ (
.A(_0090_),
.B(_0128_),
.Y(_0431_)
);
NOT _0931_ (
.A(_0291_),
.Y(_0129_)
);
NOR _0932_ (
.A(_0090_),
.B(_0129_),
.Y(_0432_)
);
NOT _0933_ (
.A(_0292_),
.Y(_0130_)
);
NOR _0934_ (
.A(_0090_),
.B(_0130_),
.Y(_0433_)
);
NOT _0935_ (
.A(_0293_),
.Y(_0131_)
);
NOR _0936_ (
.A(_0090_),
.B(_0131_),
.Y(_0434_)
);
NOT _0937_ (
.A(_0294_),
.Y(_0132_)
);
NOR _0938_ (
.A(_0090_),
.B(_0132_),
.Y(_0435_)
);
NOT _0939_ (
.A(_0295_),
.Y(_0133_)
);
NOR _0940_ (
.A(_0090_),
.B(_0133_),
.Y(_0436_)
);
NOT _0941_ (
.A(_0296_),
.Y(_0134_)
);
NOR _0942_ (
.A(_0090_),
.B(_0134_),
.Y(_0437_)
);
NOT _0943_ (
.A(_0297_),
.Y(_0135_)
);
NOR _0944_ (
.A(_0090_),
.B(_0135_),
.Y(_0438_)
);
NOT _0945_ (
.A(_0298_),
.Y(_0136_)
);
NOR _0946_ (
.A(_0090_),
.B(_0136_),
.Y(_0439_)
);
NOT _0947_ (
.A(_0299_),
.Y(_0137_)
);
NOR _0948_ (
.A(_0090_),
.B(_0137_),
.Y(_0440_)
);
NOT _0949_ (
.A(_0300_),
.Y(_0138_)
);
NOR _0950_ (
.A(_0090_),
.B(_0138_),
.Y(_0441_)
);
NOT _0951_ (
.A(_0301_),
.Y(_0139_)
);
NOR _0952_ (
.A(_0090_),
.B(_0139_),
.Y(_0442_)
);
NOT _0953_ (
.A(_0302_),
.Y(_0140_)
);
NOR _0954_ (
.A(_0090_),
.B(_0140_),
.Y(_0443_)
);
NOT _0955_ (
.A(_0303_),
.Y(_0141_)
);
NOR _0956_ (
.A(_0090_),
.B(_0141_),
.Y(_0444_)
);
NOT _0957_ (
.A(_0304_),
.Y(_0142_)
);
NOR _0958_ (
.A(_0090_),
.B(_0142_),
.Y(_0445_)
);
NOT _0959_ (
.A(_0305_),
.Y(_0143_)
);
NOR _0960_ (
.A(_0090_),
.B(_0143_),
.Y(_0446_)
);
NOT _0961_ (
.A(_0306_),
.Y(_0144_)
);
NOR _0962_ (
.A(_0090_),
.B(_0144_),
.Y(_0447_)
);
NOT _0963_ (
.A(_0307_),
.Y(_0145_)
);
NOR _0964_ (
.A(_0090_),
.B(_0145_),
.Y(_0448_)
);
NOT _0965_ (
.A(_0308_),
.Y(_0146_)
);
NOR _0966_ (
.A(_0090_),
.B(_0146_),
.Y(_0449_)
);
NOT _0967_ (
.A(_0309_),
.Y(_0147_)
);
NOR _0968_ (
.A(_0090_),
.B(_0147_),
.Y(_0450_)
);
NOT _0969_ (
.A(_0310_),
.Y(_0148_)
);
NOR _0970_ (
.A(_0090_),
.B(_0148_),
.Y(_0451_)
);
NOT _0971_ (
.A(_0311_),
.Y(_0149_)
);
NOR _0972_ (
.A(_0090_),
.B(_0149_),
.Y(_0452_)
);
NOT _0973_ (
.A(_0312_),
.Y(_0150_)
);
NOR _0974_ (
.A(_0090_),
.B(_0150_),
.Y(_0453_)
);
NOT _0975_ (
.A(_0313_),
.Y(_0151_)
);
NOR _0976_ (
.A(_0090_),
.B(_0151_),
.Y(_0454_)
);
NOT _0977_ (
.A(_0314_),
.Y(_0152_)
);
NOR _0978_ (
.A(_0090_),
.B(_0152_),
.Y(_0455_)
);
NOT _0979_ (
.A(_0315_),
.Y(_0153_)
);
NOR _0980_ (
.A(_0090_),
.B(_0153_),
.Y(_0456_)
);
NOT _0981_ (
.A(_0316_),
.Y(_0154_)
);
NOR _0982_ (
.A(_0090_),
.B(_0154_),
.Y(_0457_)
);
NOT _0983_ (
.A(_0317_),
.Y(_0155_)
);
NOR _0984_ (
.A(_0090_),
.B(_0155_),
.Y(_0458_)
);
NOT _0985_ (
.A(_0318_),
.Y(_0156_)
);
NOR _0986_ (
.A(_0090_),
.B(_0156_),
.Y(_0459_)
);
NOT _0987_ (
.A(_0319_),
.Y(_0157_)
);
NOR _0988_ (
.A(_0090_),
.B(_0157_),
.Y(_0460_)
);
NOT _0989_ (
.A(_0320_),
.Y(_0158_)
);
NOR _0990_ (
.A(_0090_),
.B(_0158_),
.Y(_0461_)
);
NOT _0991_ (
.A(_0321_),
.Y(_0159_)
);
NOR _0992_ (
.A(_0090_),
.B(_0159_),
.Y(_0462_)
);
NOT _0993_ (
.A(_0322_),
.Y(_0160_)
);
NOR _0994_ (
.A(_0090_),
.B(_0160_),
.Y(_0463_)
);
NOT _0995_ (
.A(_0323_),
.Y(_0161_)
);
NOR _0996_ (
.A(_0090_),
.B(_0161_),
.Y(_0464_)
);
NOT _0997_ (
.A(_0324_),
.Y(_0162_)
);
NOR _0998_ (
.A(_0090_),
.B(_0162_),
.Y(_0465_)
);
NOT _0999_ (
.A(_0325_),
.Y(_0163_)
);
NOR _1000_ (
.A(_0090_),
.B(_0163_),
.Y(_0466_)
);
NOT _1001_ (
.A(_0326_),
.Y(_0164_)
);
NOR _1002_ (
.A(_0090_),
.B(_0164_),
.Y(_0467_)
);
NOT _1003_ (
.A(_0327_),
.Y(_0165_)
);
NOR _1004_ (
.A(_0090_),
.B(_0165_),
.Y(_0468_)
);
NOT _1005_ (
.A(_0328_),
.Y(_0166_)
);
NOR _1006_ (
.A(_0090_),
.B(_0166_),
.Y(_0469_)
);
NOT _1007_ (
.A(_0329_),
.Y(_0167_)
);
NOR _1008_ (
.A(_0090_),
.B(_0167_),
.Y(_0470_)
);
NOT _1009_ (
.A(_0330_),
.Y(_0168_)
);
NOR _1010_ (
.A(_0090_),
.B(_0168_),
.Y(_0471_)
);
NOT _1011_ (
.A(_0331_),
.Y(_0169_)
);
NOR _1012_ (
.A(_0090_),
.B(_0169_),
.Y(_0472_)
);
NOT _1013_ (
.A(_0332_),
.Y(_0170_)
);
NOR _1014_ (
.A(_0090_),
.B(_0170_),
.Y(_0473_)
);
NOT _1015_ (
.A(_0333_),
.Y(_0171_)
);
NOR _1016_ (
.A(_0090_),
.B(_0171_),
.Y(_0474_)
);
NOT _1017_ (
.A(_0334_),
.Y(_0172_)
);
NOR _1018_ (
.A(_0090_),
.B(_0172_),
.Y(_0475_)
);
NOT _1019_ (
.A(_0335_),
.Y(_0173_)
);
NOR _1020_ (
.A(_0090_),
.B(_0173_),
.Y(_0476_)
);
NOT _1021_ (
.A(_0336_),
.Y(_0174_)
);
NOR _1022_ (
.A(_0090_),
.B(_0174_),
.Y(_0477_)
);
NOT _1023_ (
.A(_0337_),
.Y(_0175_)
);
NOR _1024_ (
.A(_0090_),
.B(_0175_),
.Y(_0478_)
);
NOT _1025_ (
.A(_0338_),
.Y(_0176_)
);
NOR _1026_ (
.A(_0090_),
.B(_0176_),
.Y(_0479_)
);
NOT _1027_ (
.A(_0339_),
.Y(_0177_)
);
NOR _1028_ (
.A(_0090_),
.B(_0177_),
.Y(_0480_)
);
NOT _1029_ (
.A(_0340_),
.Y(_0178_)
);
NOR _1030_ (
.A(_0090_),
.B(_0178_),
.Y(_0481_)
);
NOT _1031_ (
.A(_0341_),
.Y(_0179_)
);
NOR _1032_ (
.A(_0090_),
.B(_0179_),
.Y(_0482_)
);
NOT _1033_ (
.A(_0342_),
.Y(_0180_)
);
NOR _1034_ (
.A(_0090_),
.B(_0180_),
.Y(_0483_)
);
NOT _1035_ (
.A(_0343_),
.Y(_0181_)
);
NOR _1036_ (
.A(_0090_),
.B(_0181_),
.Y(_0484_)
);
NOT _1037_ (
.A(_0344_),
.Y(_0182_)
);
NOR _1038_ (
.A(_0090_),
.B(_0182_),
.Y(_0485_)
);
NOT _1039_ (
.A(_0345_),
.Y(_0183_)
);
NOR _1040_ (
.A(_0090_),
.B(_0183_),
.Y(_0486_)
);
NOT _1041_ (
.A(_0346_),
.Y(_0184_)
);
NOR _1042_ (
.A(_0090_),
.B(_0184_),
.Y(_0487_)
);
NOT _1043_ (
.A(_0347_),
.Y(_0185_)
);
NOR _1044_ (
.A(_0090_),
.B(_0185_),
.Y(_0488_)
);
NOT _1045_ (
.A(_0348_),
.Y(_0186_)
);
NOR _1046_ (
.A(_0090_),
.B(_0186_),
.Y(_0489_)
);
NOT _1047_ (
.A(_0349_),
.Y(_0187_)
);
NOR _1048_ (
.A(_0090_),
.B(_0187_),
.Y(_0490_)
);
NOT _1049_ (
.A(_0350_),
.Y(_0188_)
);
NOR _1050_ (
.A(_0090_),
.B(_0188_),
.Y(_0491_)
);
NOT _1051_ (
.A(_0351_),
.Y(_0189_)
);
NOR _1052_ (
.A(_0090_),
.B(_0189_),
.Y(_0492_)
);
NOT _1053_ (
.A(_0352_),
.Y(_0190_)
);
NOR _1054_ (
.A(_0090_),
.B(_0190_),
.Y(_0493_)
);
NOT _1055_ (
.A(_0353_),
.Y(_0191_)
);
NOR _1056_ (
.A(_0090_),
.B(_0191_),
.Y(_0494_)
);
NOT _1057_ (
.A(_0354_),
.Y(_0192_)
);
NOR _1058_ (
.A(_0090_),
.B(_0192_),
.Y(_0495_)
);
NOT _1059_ (
.A(_0355_),
.Y(_0193_)
);
NOR _1060_ (
.A(_0090_),
.B(_0193_),
.Y(_0496_)
);
NOT _1061_ (
.A(_0356_),
.Y(_0194_)
);
NOR _1062_ (
.A(_0090_),
.B(_0194_),
.Y(_0497_)
);
NOT _1063_ (
.A(_0357_),
.Y(_0195_)
);
NOR _1064_ (
.A(_0090_),
.B(_0195_),
.Y(_0498_)
);
NOT _1065_ (
.A(_0358_),
.Y(_0196_)
);
NOR _1066_ (
.A(_0090_),
.B(_0196_),
.Y(_0499_)
);
NOT _1067_ (
.A(_0359_),
.Y(_0197_)
);
NOR _1068_ (
.A(_0090_),
.B(_0197_),
.Y(_0500_)
);
NOT _1069_ (
.A(_0360_),
.Y(_0198_)
);
NOR _1070_ (
.A(_0090_),
.B(_0198_),
.Y(_0501_)
);
NOT _1071_ (
.A(_0361_),
.Y(_0199_)
);
NOR _1072_ (
.A(_0090_),
.B(_0199_),
.Y(_0502_)
);
NOT _1073_ (
.A(_0362_),
.Y(_0200_)
);
NOR _1074_ (
.A(_0090_),
.B(_0200_),
.Y(_0503_)
);
NOT _1075_ (
.A(_0363_),
.Y(_0201_)
);
NOR _1076_ (
.A(_0090_),
.B(_0201_),
.Y(_0504_)
);
NOT _1077_ (
.A(_0364_),
.Y(_0202_)
);
NOR _1078_ (
.A(_0090_),
.B(_0202_),
.Y(_0505_)
);
NOT _1079_ (
.A(_0365_),
.Y(_0203_)
);
NOR _1080_ (
.A(_0090_),
.B(_0203_),
.Y(_0506_)
);
NOT _1081_ (
.A(_0366_),
.Y(_0204_)
);
NOR _1082_ (
.A(_0090_),
.B(_0204_),
.Y(_0507_)
);
NOT _1083_ (
.A(_0367_),
.Y(_0205_)
);
NOR _1084_ (
.A(_0090_),
.B(_0205_),
.Y(_0508_)
);
NOT _1085_ (
.A(_0368_),
.Y(_0206_)
);
NOR _1086_ (
.A(_0090_),
.B(_0206_),
.Y(_0509_)
);
NOT _1087_ (
.A(_0369_),
.Y(_0207_)
);
NOR _1088_ (
.A(_0090_),
.B(_0207_),
.Y(_0510_)
);
NOT _1089_ (
.A(_0370_),
.Y(_0208_)
);
NOR _1090_ (
.A(_0090_),
.B(_0208_),
.Y(_0511_)
);
NOT _1091_ (
.A(_0371_),
.Y(_0209_)
);
NOR _1092_ (
.A(_0090_),
.B(_0209_),
.Y(_0512_)
);
NOT _1093_ (
.A(_0372_),
.Y(_0210_)
);
NOR _1094_ (
.A(_0090_),
.B(_0210_),
.Y(_0513_)
);
NOT _1095_ (
.A(_0373_),
.Y(_0211_)
);
NOR _1096_ (
.A(_0090_),
.B(_0211_),
.Y(_0514_)
);
NOT _1097_ (
.A(_0374_),
.Y(_0212_)
);
NOR _1098_ (
.A(_0090_),
.B(_0212_),
.Y(_0515_)
);
NOT _1099_ (
.A(_0375_),
.Y(_0213_)
);
NOR _1100_ (
.A(_0090_),
.B(_0213_),
.Y(_0516_)
);
NOT _1101_ (
.A(_0376_),
.Y(_0215_)
);
NOR _1102_ (
.A(_0090_),
.B(_0215_),
.Y(_0517_)
);
NOT _1103_ (
.A(_0377_),
.Y(_0216_)
);
NOR _1104_ (
.A(_0090_),
.B(_0216_),
.Y(_0518_)
);
NOT _1105_ (
.A(_0378_),
.Y(_0217_)
);
NOR _1106_ (
.A(_0090_),
.B(_0217_),
.Y(_0519_)
);
NOT _1107_ (
.A(_0379_),
.Y(_0218_)
);
NOR _1108_ (
.A(_0090_),
.B(_0218_),
.Y(_0520_)
);
NOT _1109_ (
.A(_0380_),
.Y(_0219_)
);
NOR _1110_ (
.A(_0090_),
.B(_0219_),
.Y(_0521_)
);
NOT _1111_ (
.A(_0381_),
.Y(_0220_)
);
NOR _1112_ (
.A(_0090_),
.B(_0220_),
.Y(_0522_)
);
NOT _1113_ (
.A(_0382_),
.Y(_0221_)
);
NOR _1114_ (
.A(_0090_),
.B(_0221_),
.Y(_0523_)
);
NOT _1115_ (
.A(_0383_),
.Y(_0222_)
);
NOR _1116_ (
.A(_0090_),
.B(_0222_),
.Y(_0524_)
);
NOT _1117_ (
.A(_0384_),
.Y(_0223_)
);
NOR _1118_ (
.A(_0090_),
.B(_0223_),
.Y(_0525_)
);
NOT _1119_ (
.A(_0385_),
.Y(_0224_)
);
NOR _1120_ (
.A(_0090_),
.B(_0224_),
.Y(_0526_)
);
NOT _1121_ (
.A(_0386_),
.Y(_0225_)
);
NOR _1122_ (
.A(_0090_),
.B(_0225_),
.Y(_0527_)
);
NOT _1123_ (
.A(_0387_),
.Y(_0226_)
);
NOR _1124_ (
.A(_0090_),
.B(_0226_),
.Y(_0528_)
);
NOT _1125_ (
.A(_0388_),
.Y(_0227_)
);
NOR _1126_ (
.A(_0090_),
.B(_0227_),
.Y(_0529_)
);
NOT _1127_ (
.A(_0389_),
.Y(_0228_)
);
NOR _1128_ (
.A(_0090_),
.B(_0228_),
.Y(_0530_)
);
NOT _1129_ (
.A(_0390_),
.Y(_0229_)
);
NOR _1130_ (
.A(_0090_),
.B(_0229_),
.Y(_0531_)
);
NOT _1131_ (
.A(_0090_),
.Y(_0532_)
);
NOR _1132_ (
.A(_0054_),
.B(_0034_),
.Y(_0533_)
);
NOT _1133_ (
.A(_0045_),
.Y(_0230_)
);
NAND _1134_ (
.A(_0074_),
.B(_0055_),
.Y(_0231_)
);
NAND _1135_ (
.A(_0231_),
.B(_0230_),
.Y(_0232_)
);
NOR _1136_ (
.A(_0035_),
.B(_0034_),
.Y(_0233_)
);
NOR _1137_ (
.A(_0074_),
.B(_0391_),
.Y(_0234_)
);
NOR _1138_ (
.A(_0234_),
.B(_0080_),
.Y(_0235_)
);
NOR _1139_ (
.A(_0235_),
.B(_0233_),
.Y(_0236_)
);
NAND _1140_ (
.A(_0030_),
.B(_0034_),
.Y(_0237_)
);
NAND _1141_ (
.A(_0237_),
.B(_0236_),
.Y(_0238_)
);
NOR _1142_ (
.A(_0238_),
.B(_0232_),
.Y(_0534_)
);
NOT _1143_ (
.A(_0233_),
.Y(_0239_)
);
NAND _1144_ (
.A(_0076_),
.B(_0038_),
.Y(_0240_)
);
NAND _1145_ (
.A(_0240_),
.B(_0037_),
.Y(_0241_)
);
NAND _1146_ (
.A(_0241_),
.B(_0239_),
.Y(_0242_)
);
NOR _1147_ (
.A(_0063_),
.B(_0045_),
.Y(_0243_)
);
NOR _1148_ (
.A(_0036_),
.B(_0084_),
.Y(_0244_)
);
NOR _1149_ (
.A(_0244_),
.B(_0243_),
.Y(_0245_)
);
NOR _1150_ (
.A(_0245_),
.B(_0242_),
.Y(_0535_)
);
NAND _1151_ (
.A(_0230_),
.B(_0072_),
.Y(_0246_)
);
NOR _1152_ (
.A(_0076_),
.B(_0086_),
.Y(_0247_)
);
NOR _1153_ (
.A(_0247_),
.B(_0065_),
.Y(_0248_)
);
NAND _1154_ (
.A(_0248_),
.B(_0236_),
.Y(_0249_)
);
NOR _1155_ (
.A(_0249_),
.B(_0246_),
.Y(_0536_)
);
NOT _1156_ (
.A(_0063_),
.Y(_0250_)
);
NAND _1157_ (
.A(_0074_),
.B(_0045_),
.Y(_0251_)
);
NAND _1158_ (
.A(_0251_),
.B(_0250_),
.Y(_0252_)
);
NOR _1159_ (
.A(_0252_),
.B(_0242_),
.Y(_0537_)
);
NOT _1160_ (
.A(_0243_),
.Y(_0253_)
);
NAND _1161_ (
.A(_0241_),
.B(_0048_),
.Y(_0254_)
);
NOR _1162_ (
.A(_0254_),
.B(_0253_),
.Y(_0538_)
);
NOR _1163_ (
.A(_0249_),
.B(_0232_),
.Y(_0539_)
);
BUF _1164_ (
.A(_0393_),
.Y(_0395_)
);
\$_DLATCH_P_ _1165_ (
.D(_0001_),
.E(_0543_),
.Q(enable_pts)
);
\$_DLATCH_P_ _1166_ (
.D(_0010_),
.E(_0544_),
.Q(reset_pts)
);
\$_DLATCH_P_ _1167_ (
.D(_0009_),
.E(_0545_),
.Q(enable_stp)
);
\$_DLATCH_P_ _1168_ (
.D(_0004_),
.E(_0546_),
.Q(strobe_out)
);
\$_DLATCH_P_ _1169_ (
.D(_0000_),
.E(_0547_),
.Q(ack_out)
);
\$_DLATCH_P_ _1170_ (
.D(_0002_),
.E(_0548_),
.Q(load_send)
);
\$_DLATCH_P_ _1171_ (
.D(_0003_[0]),
.E(_0546_),
.Q(response[0])
);
\$_DLATCH_P_ _1172_ (
.D(_0003_[1]),
.E(_0546_),
.Q(response[1])
);
\$_DLATCH_P_ _1173_ (
.D(_0003_[2]),
.E(_0546_),
.Q(response[2])
);
\$_DLATCH_P_ _1174_ (
.D(_0003_[3]),
.E(_0546_),
.Q(response[3])
);
\$_DLATCH_P_ _1175_ (
.D(_0003_[4]),
.E(_0546_),
.Q(response[4])
);
\$_DLATCH_P_ _1176_ (
.D(_0003_[5]),
.E(_0546_),
.Q(response[5])
);
\$_DLATCH_P_ _1177_ (
.D(_0003_[6]),
.E(_0546_),
.Q(response[6])
);
\$_DLATCH_P_ _1178_ (
.D(_0003_[7]),
.E(_0546_),
.Q(response[7])
);
\$_DLATCH_P_ _1179_ (
.D(_0003_[8]),
.E(_0546_),
.Q(response[8])
);
\$_DLATCH_P_ _1180_ (
.D(_0003_[9]),
.E(_0546_),
.Q(response[9])
);
\$_DLATCH_P_ _1181_ (
.D(_0003_[10]),
.E(_0546_),
.Q(response[10])
);
\$_DLATCH_P_ _1182_ (
.D(_0003_[11]),
.E(_0546_),
.Q(response[11])
);
\$_DLATCH_P_ _1183_ (
.D(_0003_[12]),
.E(_0546_),
.Q(response[12])
);
\$_DLATCH_P_ _1184_ (
.D(_0003_[13]),
.E(_0546_),
.Q(response[13])
);
\$_DLATCH_P_ _1185_ (
.D(_0003_[14]),
.E(_0546_),
.Q(response[14])
);
\$_DLATCH_P_ _1186_ (
.D(_0003_[15]),
.E(_0546_),
.Q(response[15])
);
\$_DLATCH_P_ _1187_ (
.D(_0003_[16]),
.E(_0546_),
.Q(response[16])
);
\$_DLATCH_P_ _1188_ (
.D(_0003_[17]),
.E(_0546_),
.Q(response[17])
);
\$_DLATCH_P_ _1189_ (
.D(_0003_[18]),
.E(_0546_),
.Q(response[18])
);
\$_DLATCH_P_ _1190_ (
.D(_0003_[19]),
.E(_0546_),
.Q(response[19])
);
\$_DLATCH_P_ _1191_ (
.D(_0003_[20]),
.E(_0546_),
.Q(response[20])
);
\$_DLATCH_P_ _1192_ (
.D(_0003_[21]),
.E(_0546_),
.Q(response[21])
);
\$_DLATCH_P_ _1193_ (
.D(_0003_[22]),
.E(_0546_),
.Q(response[22])
);
\$_DLATCH_P_ _1194_ (
.D(_0003_[23]),
.E(_0546_),
.Q(response[23])
);
\$_DLATCH_P_ _1195_ (
.D(_0003_[24]),
.E(_0546_),
.Q(response[24])
);
\$_DLATCH_P_ _1196_ (
.D(_0003_[25]),
.E(_0546_),
.Q(response[25])
);
\$_DLATCH_P_ _1197_ (
.D(_0003_[26]),
.E(_0546_),
.Q(response[26])
);
\$_DLATCH_P_ _1198_ (
.D(_0003_[27]),
.E(_0546_),
.Q(response[27])
);
\$_DLATCH_P_ _1199_ (
.D(_0003_[28]),
.E(_0546_),
.Q(response[28])
);
\$_DLATCH_P_ _1200_ (
.D(_0003_[29]),
.E(_0546_),
.Q(response[29])
);
\$_DLATCH_P_ _1201_ (
.D(_0003_[30]),
.E(_0546_),
.Q(response[30])
);
\$_DLATCH_P_ _1202_ (
.D(_0003_[31]),
.E(_0546_),
.Q(response[31])
);
\$_DLATCH_P_ _1203_ (
.D(_0003_[32]),
.E(_0546_),
.Q(response[32])
);
\$_DLATCH_P_ _1204_ (
.D(_0003_[33]),
.E(_0546_),
.Q(response[33])
);
\$_DLATCH_P_ _1205_ (
.D(_0003_[34]),
.E(_0546_),
.Q(response[34])
);
\$_DLATCH_P_ _1206_ (
.D(_0003_[35]),
.E(_0546_),
.Q(response[35])
);
\$_DLATCH_P_ _1207_ (
.D(_0003_[36]),
.E(_0546_),
.Q(response[36])
);
\$_DLATCH_P_ _1208_ (
.D(_0003_[37]),
.E(_0546_),
.Q(response[37])
);
\$_DLATCH_P_ _1209_ (
.D(_0003_[38]),
.E(_0546_),
.Q(response[38])
);
\$_DLATCH_P_ _1210_ (
.D(_0003_[39]),
.E(_0546_),
.Q(response[39])
);
\$_DLATCH_P_ _1211_ (
.D(_0003_[40]),
.E(_0546_),
.Q(response[40])
);
\$_DLATCH_P_ _1212_ (
.D(_0003_[41]),
.E(_0546_),
.Q(response[41])
);
\$_DLATCH_P_ _1213_ (
.D(_0003_[42]),
.E(_0546_),
.Q(response[42])
);
\$_DLATCH_P_ _1214_ (
.D(_0003_[43]),
.E(_0546_),
.Q(response[43])
);
\$_DLATCH_P_ _1215_ (
.D(_0003_[44]),
.E(_0546_),
.Q(response[44])
);
\$_DLATCH_P_ _1216_ (
.D(_0003_[45]),
.E(_0546_),
.Q(response[45])
);
\$_DLATCH_P_ _1217_ (
.D(_0003_[46]),
.E(_0546_),
.Q(response[46])
);
\$_DLATCH_P_ _1218_ (
.D(_0003_[47]),
.E(_0546_),
.Q(response[47])
);
\$_DLATCH_P_ _1219_ (
.D(_0003_[48]),
.E(_0546_),
.Q(response[48])
);
\$_DLATCH_P_ _1220_ (
.D(_0003_[49]),
.E(_0546_),
.Q(response[49])
);
\$_DLATCH_P_ _1221_ (
.D(_0003_[50]),
.E(_0546_),
.Q(response[50])
);
\$_DLATCH_P_ _1222_ (
.D(_0003_[51]),
.E(_0546_),
.Q(response[51])
);
\$_DLATCH_P_ _1223_ (
.D(_0003_[52]),
.E(_0546_),
.Q(response[52])
);
\$_DLATCH_P_ _1224_ (
.D(_0003_[53]),
.E(_0546_),
.Q(response[53])
);
\$_DLATCH_P_ _1225_ (
.D(_0003_[54]),
.E(_0546_),
.Q(response[54])
);
\$_DLATCH_P_ _1226_ (
.D(_0003_[55]),
.E(_0546_),
.Q(response[55])
);
\$_DLATCH_P_ _1227_ (
.D(_0003_[56]),
.E(_0546_),
.Q(response[56])
);
\$_DLATCH_P_ _1228_ (
.D(_0003_[57]),
.E(_0546_),
.Q(response[57])
);
\$_DLATCH_P_ _1229_ (
.D(_0003_[58]),
.E(_0546_),
.Q(response[58])
);
\$_DLATCH_P_ _1230_ (
.D(_0003_[59]),
.E(_0546_),
.Q(response[59])
);
\$_DLATCH_P_ _1231_ (
.D(_0003_[60]),
.E(_0546_),
.Q(response[60])
);
\$_DLATCH_P_ _1232_ (
.D(_0003_[61]),
.E(_0546_),
.Q(response[61])
);
\$_DLATCH_P_ _1233_ (
.D(_0003_[62]),
.E(_0546_),
.Q(response[62])
);
\$_DLATCH_P_ _1234_ (
.D(_0003_[63]),
.E(_0546_),
.Q(response[63])
);
\$_DLATCH_P_ _1235_ (
.D(_0003_[64]),
.E(_0546_),
.Q(response[64])
);
\$_DLATCH_P_ _1236_ (
.D(_0003_[65]),
.E(_0546_),
.Q(response[65])
);
\$_DLATCH_P_ _1237_ (
.D(_0003_[66]),
.E(_0546_),
.Q(response[66])
);
\$_DLATCH_P_ _1238_ (
.D(_0003_[67]),
.E(_0546_),
.Q(response[67])
);
\$_DLATCH_P_ _1239_ (
.D(_0003_[68]),
.E(_0546_),
.Q(response[68])
);
\$_DLATCH_P_ _1240_ (
.D(_0003_[69]),
.E(_0546_),
.Q(response[69])
);
\$_DLATCH_P_ _1241_ (
.D(_0003_[70]),
.E(_0546_),
.Q(response[70])
);
\$_DLATCH_P_ _1242_ (
.D(_0003_[71]),
.E(_0546_),
.Q(response[71])
);
\$_DLATCH_P_ _1243_ (
.D(_0003_[72]),
.E(_0546_),
.Q(response[72])
);
\$_DLATCH_P_ _1244_ (
.D(_0003_[73]),
.E(_0546_),
.Q(response[73])
);
\$_DLATCH_P_ _1245_ (
.D(_0003_[74]),
.E(_0546_),
.Q(response[74])
);
\$_DLATCH_P_ _1246_ (
.D(_0003_[75]),
.E(_0546_),
.Q(response[75])
);
\$_DLATCH_P_ _1247_ (
.D(_0003_[76]),
.E(_0546_),
.Q(response[76])
);
\$_DLATCH_P_ _1248_ (
.D(_0003_[77]),
.E(_0546_),
.Q(response[77])
);
\$_DLATCH_P_ _1249_ (
.D(_0003_[78]),
.E(_0546_),
.Q(response[78])
);
\$_DLATCH_P_ _1250_ (
.D(_0003_[79]),
.E(_0546_),
.Q(response[79])
);
\$_DLATCH_P_ _1251_ (
.D(_0003_[80]),
.E(_0546_),
.Q(response[80])
);
\$_DLATCH_P_ _1252_ (
.D(_0003_[81]),
.E(_0546_),
.Q(response[81])
);
\$_DLATCH_P_ _1253_ (
.D(_0003_[82]),
.E(_0546_),
.Q(response[82])
);
\$_DLATCH_P_ _1254_ (
.D(_0003_[83]),
.E(_0546_),
.Q(response[83])
);
\$_DLATCH_P_ _1255_ (
.D(_0003_[84]),
.E(_0546_),
.Q(response[84])
);
\$_DLATCH_P_ _1256_ (
.D(_0003_[85]),
.E(_0546_),
.Q(response[85])
);
\$_DLATCH_P_ _1257_ (
.D(_0003_[86]),
.E(_0546_),
.Q(response[86])
);
\$_DLATCH_P_ _1258_ (
.D(_0003_[87]),
.E(_0546_),
.Q(response[87])
);
\$_DLATCH_P_ _1259_ (
.D(_0003_[88]),
.E(_0546_),
.Q(response[88])
);
\$_DLATCH_P_ _1260_ (
.D(_0003_[89]),
.E(_0546_),
.Q(response[89])
);
\$_DLATCH_P_ _1261_ (
.D(_0003_[90]),
.E(_0546_),
.Q(response[90])
);
\$_DLATCH_P_ _1262_ (
.D(_0003_[91]),
.E(_0546_),
.Q(response[91])
);
\$_DLATCH_P_ _1263_ (
.D(_0003_[92]),
.E(_0546_),
.Q(response[92])
);
\$_DLATCH_P_ _1264_ (
.D(_0003_[93]),
.E(_0546_),
.Q(response[93])
);
\$_DLATCH_P_ _1265_ (
.D(_0003_[94]),
.E(_0546_),
.Q(response[94])
);
\$_DLATCH_P_ _1266_ (
.D(_0003_[95]),
.E(_0546_),
.Q(response[95])
);
\$_DLATCH_P_ _1267_ (
.D(_0003_[96]),
.E(_0546_),
.Q(response[96])
);
\$_DLATCH_P_ _1268_ (
.D(_0003_[97]),
.E(_0546_),
.Q(response[97])
);
\$_DLATCH_P_ _1269_ (
.D(_0003_[98]),
.E(_0546_),
.Q(response[98])
);
\$_DLATCH_P_ _1270_ (
.D(_0003_[99]),
.E(_0546_),
.Q(response[99])
);
\$_DLATCH_P_ _1271_ (
.D(_0003_[100]),
.E(_0546_),
.Q(response[100])
);
\$_DLATCH_P_ _1272_ (
.D(_0003_[101]),
.E(_0546_),
.Q(response[101])
);
\$_DLATCH_P_ _1273_ (
.D(_0003_[102]),
.E(_0546_),
.Q(response[102])
);
\$_DLATCH_P_ _1274_ (
.D(_0003_[103]),
.E(_0546_),
.Q(response[103])
);
\$_DLATCH_P_ _1275_ (
.D(_0003_[104]),
.E(_0546_),
.Q(response[104])
);
\$_DLATCH_P_ _1276_ (
.D(_0003_[105]),
.E(_0546_),
.Q(response[105])
);
\$_DLATCH_P_ _1277_ (
.D(_0003_[106]),
.E(_0546_),
.Q(response[106])
);
\$_DLATCH_P_ _1278_ (
.D(_0003_[107]),
.E(_0546_),
.Q(response[107])
);
\$_DLATCH_P_ _1279_ (
.D(_0003_[108]),
.E(_0546_),
.Q(response[108])
);
\$_DLATCH_P_ _1280_ (
.D(_0003_[109]),
.E(_0546_),
.Q(response[109])
);
\$_DLATCH_P_ _1281_ (
.D(_0003_[110]),
.E(_0546_),
.Q(response[110])
);
\$_DLATCH_P_ _1282_ (
.D(_0003_[111]),
.E(_0546_),
.Q(response[111])
);
\$_DLATCH_P_ _1283_ (
.D(_0003_[112]),
.E(_0546_),
.Q(response[112])
);
\$_DLATCH_P_ _1284_ (
.D(_0003_[113]),
.E(_0546_),
.Q(response[113])
);
\$_DLATCH_P_ _1285_ (
.D(_0003_[114]),
.E(_0546_),
.Q(response[114])
);
\$_DLATCH_P_ _1286_ (
.D(_0003_[115]),
.E(_0546_),
.Q(response[115])
);
\$_DLATCH_P_ _1287_ (
.D(_0003_[116]),
.E(_0546_),
.Q(response[116])
);
\$_DLATCH_P_ _1288_ (
.D(_0003_[117]),
.E(_0546_),
.Q(response[117])
);
\$_DLATCH_P_ _1289_ (
.D(_0003_[118]),
.E(_0546_),
.Q(response[118])
);
\$_DLATCH_P_ _1290_ (
.D(_0003_[119]),
.E(_0546_),
.Q(response[119])
);
\$_DLATCH_P_ _1291_ (
.D(_0003_[120]),
.E(_0546_),
.Q(response[120])
);
\$_DLATCH_P_ _1292_ (
.D(_0003_[121]),
.E(_0546_),
.Q(response[121])
);
\$_DLATCH_P_ _1293_ (
.D(_0003_[122]),
.E(_0546_),
.Q(response[122])
);
\$_DLATCH_P_ _1294_ (
.D(_0003_[123]),
.E(_0546_),
.Q(response[123])
);
\$_DLATCH_P_ _1295_ (
.D(_0003_[124]),
.E(_0546_),
.Q(response[124])
);
\$_DLATCH_P_ _1296_ (
.D(_0003_[125]),
.E(_0546_),
.Q(response[125])
);
\$_DLATCH_P_ _1297_ (
.D(_0003_[126]),
.E(_0546_),
.Q(response[126])
);
\$_DLATCH_P_ _1298_ (
.D(_0003_[127]),
.E(_0546_),
.Q(response[127])
);
\$_DLATCH_P_ _1299_ (
.D(_0003_[128]),
.E(_0546_),
.Q(response[128])
);
\$_DLATCH_P_ _1300_ (
.D(_0003_[129]),
.E(_0546_),
.Q(response[129])
);
\$_DLATCH_P_ _1301_ (
.D(_0003_[130]),
.E(_0546_),
.Q(response[130])
);
\$_DLATCH_P_ _1302_ (
.D(_0003_[131]),
.E(_0546_),
.Q(response[131])
);
\$_DLATCH_P_ _1303_ (
.D(_0003_[132]),
.E(_0546_),
.Q(response[132])
);
\$_DLATCH_P_ _1304_ (
.D(_0003_[133]),
.E(_0546_),
.Q(response[133])
);
\$_DLATCH_P_ _1305_ (
.D(_0003_[134]),
.E(_0546_),
.Q(response[134])
);
\$_DLATCH_P_ _1306_ (
.D(_0003_[135]),
.E(_0546_),
.Q(response[135])
);
assign reset_stp = reset_pts;
assign _0540_ = estado[2];
assign _0541_ = estado[0];
assign _0542_ = estado[1];
assign estado[0] = _0028_;
assign estado[1] = _0214_;
assign estado[2] = _0032_;
assign _0033_ = idle_in;
assign _0084_ = reset_host;
assign _0108_ = strobe_in;
assign _0112_ = transmission_complete;
assign _0119_ = reception_complete;
assign _0255_ = pad_response[0];
assign _0256_ = pad_response[1];
assign _0257_ = pad_response[2];
assign _0258_ = pad_response[3];
assign _0259_ = pad_response[4];
assign _0260_ = pad_response[5];
assign _0261_ = pad_response[6];
assign _0262_ = pad_response[7];
assign _0263_ = pad_response[8];
assign _0264_ = pad_response[9];
assign _0265_ = pad_response[10];
assign _0266_ = pad_response[11];
assign _0267_ = pad_response[12];
assign _0268_ = pad_response[13];
assign _0269_ = pad_response[14];
assign _0270_ = pad_response[15];
assign _0271_ = pad_response[16];
assign _0272_ = pad_response[17];
assign _0273_ = pad_response[18];
assign _0274_ = pad_response[19];
assign _0275_ = pad_response[20];
assign _0276_ = pad_response[21];
assign _0277_ = pad_response[22];
assign _0278_ = pad_response[23];
assign _0279_ = pad_response[24];
assign _0280_ = pad_response[25];
assign _0281_ = pad_response[26];
assign _0282_ = pad_response[27];
assign _0283_ = pad_response[28];
assign _0284_ = pad_response[29];
assign _0285_ = pad_response[30];
assign _0286_ = pad_response[31];
assign _0287_ = pad_response[32];
assign _0288_ = pad_response[33];
assign _0289_ = pad_response[34];
assign _0290_ = pad_response[35];
assign _0291_ = pad_response[36];
assign _0292_ = pad_response[37];
assign _0293_ = pad_response[38];
assign _0294_ = pad_response[39];
assign _0295_ = pad_response[40];
assign _0296_ = pad_response[41];
assign _0297_ = pad_response[42];
assign _0298_ = pad_response[43];
assign _0299_ = pad_response[44];
assign _0300_ = pad_response[45];
assign _0301_ = pad_response[46];
assign _0302_ = pad_response[47];
assign _0303_ = pad_response[48];
assign _0304_ = pad_response[49];
assign _0305_ = pad_response[50];
assign _0306_ = pad_response[51];
assign _0307_ = pad_response[52];
assign _0308_ = pad_response[53];
assign _0309_ = pad_response[54];
assign _0310_ = pad_response[55];
assign _0311_ = pad_response[56];
assign _0312_ = pad_response[57];
assign _0313_ = pad_response[58];
assign _0314_ = pad_response[59];
assign _0315_ = pad_response[60];
assign _0316_ = pad_response[61];
assign _0317_ = pad_response[62];
assign _0318_ = pad_response[63];
assign _0319_ = pad_response[64];
assign _0320_ = pad_response[65];
assign _0321_ = pad_response[66];
assign _0322_ = pad_response[67];
assign _0323_ = pad_response[68];
assign _0324_ = pad_response[69];
assign _0325_ = pad_response[70];
assign _0326_ = pad_response[71];
assign _0327_ = pad_response[72];
assign _0328_ = pad_response[73];
assign _0329_ = pad_response[74];
assign _0330_ = pad_response[75];
assign _0331_ = pad_response[76];
assign _0332_ = pad_response[77];
assign _0333_ = pad_response[78];
assign _0334_ = pad_response[79];
assign _0335_ = pad_response[80];
assign _0336_ = pad_response[81];
assign _0337_ = pad_response[82];
assign _0338_ = pad_response[83];
assign _0339_ = pad_response[84];
assign _0340_ = pad_response[85];
assign _0341_ = pad_response[86];
assign _0342_ = pad_response[87];
assign _0343_ = pad_response[88];
assign _0344_ = pad_response[89];
assign _0345_ = pad_response[90];
assign _0346_ = pad_response[91];
assign _0347_ = pad_response[92];
assign _0348_ = pad_response[93];
assign _0349_ = pad_response[94];
assign _0350_ = pad_response[95];
assign _0351_ = pad_response[96];
assign _0352_ = pad_response[97];
assign _0353_ = pad_response[98];
assign _0354_ = pad_response[99];
assign _0355_ = pad_response[100];
assign _0356_ = pad_response[101];
assign _0357_ = pad_response[102];
assign _0358_ = pad_response[103];
assign _0359_ = pad_response[104];
assign _0360_ = pad_response[105];
assign _0361_ = pad_response[106];
assign _0362_ = pad_response[107];
assign _0363_ = pad_response[108];
assign _0364_ = pad_response[109];
assign _0365_ = pad_response[110];
assign _0366_ = pad_response[111];
assign _0367_ = pad_response[112];
assign _0368_ = pad_response[113];
assign _0369_ = pad_response[114];
assign _0370_ = pad_response[115];
assign _0371_ = pad_response[116];
assign _0372_ = pad_response[117];
assign _0373_ = pad_response[118];
assign _0374_ = pad_response[119];
assign _0375_ = pad_response[120];
assign _0376_ = pad_response[121];
assign _0377_ = pad_response[122];
assign _0378_ = pad_response[123];
assign _0379_ = pad_response[124];
assign _0380_ = pad_response[125];
assign _0381_ = pad_response[126];
assign _0382_ = pad_response[127];
assign _0383_ = pad_response[128];
assign _0384_ = pad_response[129];
assign _0385_ = pad_response[130];
assign _0386_ = pad_response[131];
assign _0387_ = pad_response[132];
assign _0388_ = pad_response[133];
assign _0389_ = pad_response[134];
assign _0390_ = pad_response[135];
assign _0391_ = ack_in;
assign _0010_ = _0392_;
assign _0001_ = _0393_;
assign _0009_ = _0394_;
assign _0002_ = _0395_;
assign _0003_[0] = _0396_;
assign _0003_[1] = _0397_;
assign _0003_[2] = _0398_;
assign _0003_[3] = _0399_;
assign _0003_[4] = _0400_;
assign _0003_[5] = _0401_;
assign _0003_[6] = _0402_;
assign _0003_[7] = _0403_;
assign _0003_[8] = _0404_;
assign _0003_[9] = _0405_;
assign _0003_[10] = _0406_;
assign _0003_[11] = _0407_;
assign _0003_[12] = _0408_;
assign _0003_[13] = _0409_;
assign _0003_[14] = _0410_;
assign _0003_[15] = _0411_;
assign _0003_[16] = _0412_;
assign _0003_[17] = _0413_;
assign _0003_[18] = _0414_;
assign _0003_[19] = _0415_;
assign _0003_[20] = _0416_;
assign _0003_[21] = _0417_;
assign _0003_[22] = _0418_;
assign _0003_[23] = _0419_;
assign _0003_[24] = _0420_;
assign _0003_[25] = _0421_;
assign _0003_[26] = _0422_;
assign _0003_[27] = _0423_;
assign _0003_[28] = _0424_;
assign _0003_[29] = _0425_;
assign _0003_[30] = _0426_;
assign _0003_[31] = _0427_;
assign _0003_[32] = _0428_;
assign _0003_[33] = _0429_;
assign _0003_[34] = _0430_;
assign _0003_[35] = _0431_;
assign _0003_[36] = _0432_;
assign _0003_[37] = _0433_;
assign _0003_[38] = _0434_;
assign _0003_[39] = _0435_;
assign _0003_[40] = _0436_;
assign _0003_[41] = _0437_;
assign _0003_[42] = _0438_;
assign _0003_[43] = _0439_;
assign _0003_[44] = _0440_;
assign _0003_[45] = _0441_;
assign _0003_[46] = _0442_;
assign _0003_[47] = _0443_;
assign _0003_[48] = _0444_;
assign _0003_[49] = _0445_;
assign _0003_[50] = _0446_;
assign _0003_[51] = _0447_;
assign _0003_[52] = _0448_;
assign _0003_[53] = _0449_;
assign _0003_[54] = _0450_;
assign _0003_[55] = _0451_;
assign _0003_[56] = _0452_;
assign _0003_[57] = _0453_;
assign _0003_[58] = _0454_;
assign _0003_[59] = _0455_;
assign _0003_[60] = _0456_;
assign _0003_[61] = _0457_;
assign _0003_[62] = _0458_;
assign _0003_[63] = _0459_;
assign _0003_[64] = _0460_;
assign _0003_[65] = _0461_;
assign _0003_[66] = _0462_;
assign _0003_[67] = _0463_;
assign _0003_[68] = _0464_;
assign _0003_[69] = _0465_;
assign _0003_[70] = _0466_;
assign _0003_[71] = _0467_;
assign _0003_[72] = _0468_;
assign _0003_[73] = _0469_;
assign _0003_[74] = _0470_;
assign _0003_[75] = _0471_;
assign _0003_[76] = _0472_;
assign _0003_[77] = _0473_;
assign _0003_[78] = _0474_;
assign _0003_[79] = _0475_;
assign _0003_[80] = _0476_;
assign _0003_[81] = _0477_;
assign _0003_[82] = _0478_;
assign _0003_[83] = _0479_;
assign _0003_[84] = _0480_;
assign _0003_[85] = _0481_;
assign _0003_[86] = _0482_;
assign _0003_[87] = _0483_;
assign _0003_[88] = _0484_;
assign _0003_[89] = _0485_;
assign _0003_[90] = _0486_;
assign _0003_[91] = _0487_;
assign _0003_[92] = _0488_;
assign _0003_[93] = _0489_;
assign _0003_[94] = _0490_;
assign _0003_[95] = _0491_;
assign _0003_[96] = _0492_;
assign _0003_[97] = _0493_;
assign _0003_[98] = _0494_;
assign _0003_[99] = _0495_;
assign _0003_[100] = _0496_;
assign _0003_[101] = _0497_;
assign _0003_[102] = _0498_;
assign _0003_[103] = _0499_;
assign _0003_[104] = _0500_;
assign _0003_[105] = _0501_;
assign _0003_[106] = _0502_;
assign _0003_[107] = _0503_;
assign _0003_[108] = _0504_;
assign _0003_[109] = _0505_;
assign _0003_[110] = _0506_;
assign _0003_[111] = _0507_;
assign _0003_[112] = _0508_;
assign _0003_[113] = _0509_;
assign _0003_[114] = _0510_;
assign _0003_[115] = _0511_;
assign _0003_[116] = _0512_;
assign _0003_[117] = _0513_;
assign _0003_[118] = _0514_;
assign _0003_[119] = _0515_;
assign _0003_[120] = _0516_;
assign _0003_[121] = _0517_;
assign _0003_[122] = _0518_;
assign _0003_[123] = _0519_;
assign _0003_[124] = _0520_;
assign _0003_[125] = _0521_;
assign _0003_[126] = _0522_;
assign _0003_[127] = _0523_;
assign _0003_[128] = _0524_;
assign _0003_[129] = _0525_;
assign _0003_[130] = _0526_;
assign _0003_[131] = _0527_;
assign _0003_[132] = _0528_;
assign _0003_[133] = _0529_;
assign _0003_[134] = _0530_;
assign _0003_[135] = _0531_;
assign _0004_ = _0532_;
assign _0000_ = _0533_;
assign _0543_ = _0534_;
assign _0544_ = _0535_;
assign _0545_ = _0536_;
assign _0546_ = _0537_;
assign _0547_ = _0538_;
assign _0548_ = _0539_;
assign _0029_ = _0540_;
assign _0030_ = _0541_;
assign _0031_ = _0542_;
endmodule
module parallel_to_serial(enable_pts, reset_pts, clk_SD, signal_in, signal_out, parallel_complete);
wire [8:0] _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire [31:0] _254_;
wire [3:0] _255_;
wire [1:0] _256_;
wire _257_;
wire [8:0] _258_;
wire _259_;
wire _260_;
wire _261_;
wire [8:0] _262_;
wire [8:0] _263_;
wire _264_;
wire [31:0] _265_;
wire [31:0] _266_;
wire [167:0] _267_;
wire [167:0] _268_;
wire [167:0] _269_;
wire [167:0] _270_;
wire [167:0] _271_;
wire [167:0] _272_;
wire [167:0] _273_;
wire [167:0] _274_;
wire [167:0] _275_;
wire [167:0] _276_;
wire [167:0] _277_;
wire [167:0] _278_;
wire [167:0] _279_;
wire [31:0] _280_;
wire [31:0] _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire [31:0] _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
input clk_SD;
wire [8:0] contador;
input enable_pts;
output parallel_complete;
input reset_pts;
input [39:0] signal_in;
output signal_out;
NOT _297_ (
.A(_084_),
.Y(_205_)
);
NOR _298_ (
.A(_095_),
.B(_205_),
.Y(_206_)
);
NOR _299_ (
.A(_190_),
.B(_189_),
.Y(_208_)
);
NAND _300_ (
.A(_208_),
.B(_192_),
.Y(_209_)
);
NOT _301_ (
.A(_191_),
.Y(_210_)
);
NOR _302_ (
.A(_210_),
.B(_188_),
.Y(_212_)
);
NOT _303_ (
.A(_212_),
.Y(_214_)
);
NOR _304_ (
.A(_200_),
.B(_005_),
.Y(_215_)
);
NOR _305_ (
.A(_045_),
.B(_211_),
.Y(_217_)
);
NAND _306_ (
.A(_217_),
.B(_215_),
.Y(_218_)
);
NOR _307_ (
.A(_218_),
.B(_214_),
.Y(_220_)
);
NOT _308_ (
.A(_220_),
.Y(_221_)
);
NOR _309_ (
.A(_221_),
.B(_209_),
.Y(_223_)
);
NAND _310_ (
.A(_223_),
.B(_095_),
.Y(_224_)
);
NOT _311_ (
.A(_224_),
.Y(_226_)
);
NOR _312_ (
.A(_226_),
.B(_206_),
.Y(_227_)
);
NOR _313_ (
.A(_227_),
.B(_126_),
.Y(_137_)
);
NOR _314_ (
.A(_226_),
.B(_126_),
.Y(_229_)
);
NOT _315_ (
.A(_229_),
.Y(_231_)
);
NOT _316_ (
.A(_095_),
.Y(_232_)
);
NOT _317_ (
.A(_189_),
.Y(_234_)
);
NAND _318_ (
.A(_234_),
.B(_232_),
.Y(_235_)
);
NAND _319_ (
.A(_189_),
.B(_095_),
.Y(_237_)
);
NAND _320_ (
.A(_237_),
.B(_235_),
.Y(_238_)
);
NOR _321_ (
.A(_238_),
.B(_231_),
.Y(_193_)
);
NOT _322_ (
.A(_190_),
.Y(_240_)
);
NOR _323_ (
.A(_237_),
.B(_240_),
.Y(_242_)
);
NOT _324_ (
.A(_126_),
.Y(_243_)
);
NAND _325_ (
.A(_237_),
.B(_240_),
.Y(_245_)
);
NAND _326_ (
.A(_245_),
.B(_243_),
.Y(_246_)
);
NOR _327_ (
.A(_246_),
.B(_242_),
.Y(_194_)
);
NOR _328_ (
.A(_242_),
.B(_005_),
.Y(_248_)
);
NAND _329_ (
.A(_190_),
.B(_189_),
.Y(_250_)
);
NAND _330_ (
.A(_095_),
.B(_005_),
.Y(_251_)
);
NOR _331_ (
.A(_251_),
.B(_250_),
.Y(_253_)
);
NOT _332_ (
.A(_253_),
.Y(_006_)
);
NAND _333_ (
.A(_006_),
.B(_243_),
.Y(_008_)
);
NOR _334_ (
.A(_008_),
.B(_248_),
.Y(_195_)
);
NAND _335_ (
.A(_006_),
.B(_210_),
.Y(_010_)
);
NOR _336_ (
.A(_006_),
.B(_210_),
.Y(_011_)
);
NOT _337_ (
.A(_011_),
.Y(_013_)
);
NAND _338_ (
.A(_013_),
.B(_010_),
.Y(_014_)
);
NOR _339_ (
.A(_014_),
.B(_231_),
.Y(_196_)
);
NOR _340_ (
.A(_011_),
.B(_188_),
.Y(_016_)
);
NOT _341_ (
.A(_188_),
.Y(_018_)
);
NOR _342_ (
.A(_210_),
.B(_018_),
.Y(_019_)
);
NAND _343_ (
.A(_019_),
.B(_253_),
.Y(_021_)
);
NAND _344_ (
.A(_021_),
.B(_243_),
.Y(_022_)
);
NOR _345_ (
.A(_022_),
.B(_016_),
.Y(_197_)
);
NOT _346_ (
.A(_192_),
.Y(_024_)
);
NAND _347_ (
.A(_021_),
.B(_024_),
.Y(_026_)
);
NOR _348_ (
.A(_021_),
.B(_024_),
.Y(_027_)
);
NOT _349_ (
.A(_027_),
.Y(_029_)
);
NAND _350_ (
.A(_029_),
.B(_026_),
.Y(_030_)
);
NOR _351_ (
.A(_030_),
.B(_231_),
.Y(_198_)
);
NAND _352_ (
.A(_027_),
.B(_200_),
.Y(_032_)
);
NOT _353_ (
.A(_200_),
.Y(_034_)
);
NAND _354_ (
.A(_029_),
.B(_034_),
.Y(_035_)
);
NAND _355_ (
.A(_035_),
.B(_032_),
.Y(_037_)
);
NOR _356_ (
.A(_037_),
.B(_126_),
.Y(_199_)
);
NOT _357_ (
.A(_211_),
.Y(_039_)
);
NOR _358_ (
.A(_032_),
.B(_039_),
.Y(_040_)
);
NAND _359_ (
.A(_032_),
.B(_039_),
.Y(_042_)
);
NAND _360_ (
.A(_042_),
.B(_243_),
.Y(_043_)
);
NOR _361_ (
.A(_043_),
.B(_040_),
.Y(_201_)
);
NOT _362_ (
.A(_045_),
.Y(_046_)
);
NOR _363_ (
.A(_040_),
.B(_046_),
.Y(_048_)
);
NOT _364_ (
.A(_040_),
.Y(_049_)
);
NOR _365_ (
.A(_049_),
.B(_045_),
.Y(_051_)
);
NOR _366_ (
.A(_051_),
.B(_048_),
.Y(_052_)
);
NOR _367_ (
.A(_052_),
.B(_126_),
.Y(_202_)
);
NOR _368_ (
.A(_191_),
.B(_188_),
.Y(_054_)
);
NOR _369_ (
.A(_054_),
.B(_024_),
.Y(_056_)
);
NAND _370_ (
.A(_054_),
.B(_024_),
.Y(_057_)
);
NOT _371_ (
.A(_057_),
.Y(_059_)
);
NOR _372_ (
.A(_059_),
.B(_056_),
.Y(_060_)
);
NAND _373_ (
.A(_054_),
.B(_213_),
.Y(_062_)
);
NOR _374_ (
.A(_191_),
.B(_018_),
.Y(_063_)
);
NAND _375_ (
.A(_063_),
.B(_009_),
.Y(_065_)
);
NAND _376_ (
.A(_065_),
.B(_062_),
.Y(_066_)
);
NAND _377_ (
.A(_212_),
.B(_031_),
.Y(_068_)
);
NAND _378_ (
.A(_019_),
.B(_236_),
.Y(_069_)
);
NAND _379_ (
.A(_069_),
.B(_068_),
.Y(_071_)
);
NOR _380_ (
.A(_071_),
.B(_066_),
.Y(_072_)
);
NAND _381_ (
.A(_072_),
.B(_060_),
.Y(_073_)
);
NOT _382_ (
.A(_005_),
.Y(_074_)
);
NOR _383_ (
.A(_060_),
.B(_053_),
.Y(_075_)
);
NOR _384_ (
.A(_075_),
.B(_074_),
.Y(_076_)
);
NAND _385_ (
.A(_076_),
.B(_073_),
.Y(_077_)
);
NOT _386_ (
.A(_056_),
.Y(_078_)
);
NAND _387_ (
.A(_057_),
.B(_078_),
.Y(_079_)
);
NAND _388_ (
.A(_019_),
.B(_247_),
.Y(_080_)
);
NAND _389_ (
.A(_063_),
.B(_020_),
.Y(_081_)
);
NAND _390_ (
.A(_081_),
.B(_080_),
.Y(_082_)
);
NAND _391_ (
.A(_212_),
.B(_041_),
.Y(_083_)
);
NAND _392_ (
.A(_054_),
.B(_225_),
.Y(_085_)
);
NAND _393_ (
.A(_085_),
.B(_083_),
.Y(_086_)
);
NOR _394_ (
.A(_086_),
.B(_082_),
.Y(_087_)
);
NOR _395_ (
.A(_087_),
.B(_079_),
.Y(_088_)
);
NOT _396_ (
.A(_064_),
.Y(_089_)
);
NOR _397_ (
.A(_060_),
.B(_089_),
.Y(_090_)
);
NOR _398_ (
.A(_090_),
.B(_088_),
.Y(_091_)
);
NOR _399_ (
.A(_091_),
.B(_005_),
.Y(_092_)
);
NOR _400_ (
.A(_092_),
.B(_240_),
.Y(_093_)
);
NAND _401_ (
.A(_093_),
.B(_077_),
.Y(_094_)
);
NAND _402_ (
.A(_039_),
.B(_034_),
.Y(_096_)
);
NOR _403_ (
.A(_056_),
.B(_096_),
.Y(_097_)
);
NAND _404_ (
.A(_097_),
.B(_094_),
.Y(_098_)
);
NAND _405_ (
.A(_019_),
.B(_241_),
.Y(_099_)
);
NAND _406_ (
.A(_054_),
.B(_219_),
.Y(_100_)
);
NAND _407_ (
.A(_100_),
.B(_099_),
.Y(_101_)
);
NAND _408_ (
.A(_212_),
.B(_036_),
.Y(_102_)
);
NAND _409_ (
.A(_063_),
.B(_015_),
.Y(_103_)
);
NAND _410_ (
.A(_103_),
.B(_102_),
.Y(_104_)
);
NOR _411_ (
.A(_104_),
.B(_101_),
.Y(_105_)
);
NAND _412_ (
.A(_105_),
.B(_060_),
.Y(_106_)
);
NOR _413_ (
.A(_060_),
.B(_058_),
.Y(_107_)
);
NOR _414_ (
.A(_107_),
.B(_074_),
.Y(_108_)
);
NAND _415_ (
.A(_108_),
.B(_106_),
.Y(_109_)
);
NAND _416_ (
.A(_019_),
.B(_252_),
.Y(_110_)
);
NAND _417_ (
.A(_054_),
.B(_230_),
.Y(_111_)
);
NAND _418_ (
.A(_111_),
.B(_110_),
.Y(_112_)
);
NAND _419_ (
.A(_212_),
.B(_047_),
.Y(_113_)
);
NAND _420_ (
.A(_063_),
.B(_025_),
.Y(_114_)
);
NAND _421_ (
.A(_114_),
.B(_113_),
.Y(_115_)
);
NOR _422_ (
.A(_115_),
.B(_112_),
.Y(_116_)
);
NAND _423_ (
.A(_116_),
.B(_060_),
.Y(_117_)
);
NOT _424_ (
.A(_070_),
.Y(_118_)
);
NAND _425_ (
.A(_079_),
.B(_118_),
.Y(_119_)
);
NAND _426_ (
.A(_119_),
.B(_117_),
.Y(_120_)
);
NOR _427_ (
.A(_120_),
.B(_005_),
.Y(_121_)
);
NOR _428_ (
.A(_121_),
.B(_190_),
.Y(_122_)
);
NAND _429_ (
.A(_122_),
.B(_109_),
.Y(_123_)
);
NAND _430_ (
.A(_123_),
.B(_234_),
.Y(_124_)
);
NOR _431_ (
.A(_124_),
.B(_098_),
.Y(_125_)
);
NAND _432_ (
.A(_212_),
.B(_038_),
.Y(_127_)
);
NAND _433_ (
.A(_063_),
.B(_017_),
.Y(_128_)
);
NAND _434_ (
.A(_054_),
.B(_222_),
.Y(_129_)
);
NAND _435_ (
.A(_129_),
.B(_128_),
.Y(_130_)
);
NAND _436_ (
.A(_019_),
.B(_244_),
.Y(_131_)
);
NAND _437_ (
.A(_131_),
.B(_074_),
.Y(_132_)
);
NOR _438_ (
.A(_132_),
.B(_130_),
.Y(_133_)
);
NAND _439_ (
.A(_133_),
.B(_127_),
.Y(_134_)
);
NAND _440_ (
.A(_063_),
.B(_007_),
.Y(_135_)
);
NAND _441_ (
.A(_135_),
.B(_005_),
.Y(_136_)
);
NAND _442_ (
.A(_019_),
.B(_233_),
.Y(_138_)
);
NOT _443_ (
.A(_028_),
.Y(_139_)
);
NOR _444_ (
.A(_214_),
.B(_139_),
.Y(_140_)
);
NOT _445_ (
.A(_207_),
.Y(_141_)
);
NOT _446_ (
.A(_054_),
.Y(_142_)
);
NOR _447_ (
.A(_142_),
.B(_141_),
.Y(_143_)
);
NOR _448_ (
.A(_143_),
.B(_140_),
.Y(_144_)
);
NAND _449_ (
.A(_144_),
.B(_138_),
.Y(_145_)
);
NOR _450_ (
.A(_145_),
.B(_136_),
.Y(_146_)
);
NOR _451_ (
.A(_146_),
.B(_240_),
.Y(_147_)
);
NAND _452_ (
.A(_147_),
.B(_134_),
.Y(_148_)
);
NAND _453_ (
.A(_063_),
.B(_012_),
.Y(_149_)
);
NAND _454_ (
.A(_054_),
.B(_216_),
.Y(_150_)
);
NAND _455_ (
.A(_150_),
.B(_149_),
.Y(_151_)
);
NAND _456_ (
.A(_019_),
.B(_239_),
.Y(_152_)
);
NAND _457_ (
.A(_212_),
.B(_033_),
.Y(_153_)
);
NAND _458_ (
.A(_153_),
.B(_152_),
.Y(_154_)
);
NOR _459_ (
.A(_154_),
.B(_151_),
.Y(_155_)
);
NOR _460_ (
.A(_155_),
.B(_074_),
.Y(_156_)
);
NAND _461_ (
.A(_054_),
.B(_228_),
.Y(_157_)
);
NAND _462_ (
.A(_019_),
.B(_249_),
.Y(_158_)
);
NAND _463_ (
.A(_158_),
.B(_157_),
.Y(_159_)
);
NAND _464_ (
.A(_212_),
.B(_044_),
.Y(_160_)
);
NAND _465_ (
.A(_063_),
.B(_023_),
.Y(_161_)
);
NAND _466_ (
.A(_161_),
.B(_160_),
.Y(_162_)
);
NOR _467_ (
.A(_162_),
.B(_159_),
.Y(_163_)
);
NOR _468_ (
.A(_163_),
.B(_005_),
.Y(_164_)
);
NOR _469_ (
.A(_164_),
.B(_156_),
.Y(_165_)
);
NOR _470_ (
.A(_165_),
.B(_190_),
.Y(_166_)
);
NOR _471_ (
.A(_166_),
.B(_079_),
.Y(_167_)
);
NAND _472_ (
.A(_167_),
.B(_148_),
.Y(_168_)
);
NOT _473_ (
.A(_067_),
.Y(_169_)
);
NOR _474_ (
.A(_169_),
.B(_005_),
.Y(_170_)
);
NOT _475_ (
.A(_055_),
.Y(_171_)
);
NOR _476_ (
.A(_171_),
.B(_074_),
.Y(_172_)
);
NOR _477_ (
.A(_172_),
.B(_170_),
.Y(_173_)
);
NOR _478_ (
.A(_173_),
.B(_190_),
.Y(_174_)
);
NAND _479_ (
.A(_061_),
.B(_074_),
.Y(_175_)
);
NAND _480_ (
.A(_050_),
.B(_005_),
.Y(_176_)
);
NAND _481_ (
.A(_176_),
.B(_175_),
.Y(_177_)
);
NAND _482_ (
.A(_177_),
.B(_190_),
.Y(_178_)
);
NAND _483_ (
.A(_178_),
.B(_059_),
.Y(_179_)
);
NOR _484_ (
.A(_179_),
.B(_174_),
.Y(_180_)
);
NAND _485_ (
.A(_097_),
.B(_189_),
.Y(_181_)
);
NOR _486_ (
.A(_181_),
.B(_180_),
.Y(_182_)
);
NAND _487_ (
.A(_182_),
.B(_168_),
.Y(_183_)
);
NAND _488_ (
.A(_223_),
.B(_204_),
.Y(_184_)
);
NAND _489_ (
.A(_184_),
.B(_183_),
.Y(_185_)
);
NOR _490_ (
.A(_185_),
.B(_125_),
.Y(_186_)
);
NAND _491_ (
.A(_243_),
.B(_095_),
.Y(_187_)
);
NOR _492_ (
.A(_187_),
.B(_186_),
.Y(_203_)
);
DFF _493_ (
.C(clk_SD),
.D(_002_),
.Q(signal_out)
);
DFF _494_ (
.C(clk_SD),
.D(_001_),
.Q(parallel_complete)
);
DFF _495_ (
.C(clk_SD),
.D(_000_[0]),
.Q(contador[0])
);
DFF _496_ (
.C(clk_SD),
.D(_000_[1]),
.Q(contador[1])
);
DFF _497_ (
.C(clk_SD),
.D(_000_[2]),
.Q(contador[2])
);
DFF _498_ (
.C(clk_SD),
.D(_000_[3]),
.Q(contador[3])
);
DFF _499_ (
.C(clk_SD),
.D(_000_[4]),
.Q(contador[4])
);
DFF _500_ (
.C(clk_SD),
.D(_000_[5]),
.Q(contador[5])
);
DFF _501_ (
.C(clk_SD),
.D(_000_[6]),
.Q(contador[6])
);
DFF _502_ (
.C(clk_SD),
.D(_000_[7]),
.Q(contador[7])
);
DFF _503_ (
.C(clk_SD),
.D(_000_[8]),
.Q(contador[8])
);
assign _005_ = contador[2];
assign _188_ = contador[4];
assign _200_ = contador[6];
assign _211_ = contador[7];
assign _045_ = contador[8];
assign _084_ = parallel_complete;
assign _095_ = enable_pts;
assign _126_ = reset_pts;
assign _001_ = _137_;
assign _189_ = contador[0];
assign _190_ = contador[1];
assign _191_ = contador[3];
assign _192_ = contador[5];
assign _000_[0] = _193_;
assign _000_[1] = _194_;
assign _000_[2] = _195_;
assign _000_[3] = _196_;
assign _000_[4] = _197_;
assign _000_[5] = _198_;
assign _000_[6] = _199_;
assign _000_[7] = _201_;
assign _000_[8] = _202_;
assign _002_ = _203_;
assign _204_ = signal_out;
assign _207_ = signal_in[0];
assign _213_ = signal_in[1];
assign _216_ = signal_in[2];
assign _219_ = signal_in[3];
assign _222_ = signal_in[4];
assign _225_ = signal_in[5];
assign _228_ = signal_in[6];
assign _230_ = signal_in[7];
assign _233_ = signal_in[8];
assign _236_ = signal_in[9];
assign _239_ = signal_in[10];
assign _241_ = signal_in[11];
assign _244_ = signal_in[12];
assign _247_ = signal_in[13];
assign _249_ = signal_in[14];
assign _252_ = signal_in[15];
assign _007_ = signal_in[16];
assign _009_ = signal_in[17];
assign _012_ = signal_in[18];
assign _015_ = signal_in[19];
assign _017_ = signal_in[20];
assign _020_ = signal_in[21];
assign _023_ = signal_in[22];
assign _025_ = signal_in[23];
assign _028_ = signal_in[24];
assign _031_ = signal_in[25];
assign _033_ = signal_in[26];
assign _036_ = signal_in[27];
assign _038_ = signal_in[28];
assign _041_ = signal_in[29];
assign _044_ = signal_in[30];
assign _047_ = signal_in[31];
assign _050_ = signal_in[32];
assign _053_ = signal_in[33];
assign _055_ = signal_in[34];
assign _058_ = signal_in[35];
assign _061_ = signal_in[36];
assign _064_ = signal_in[37];
assign _067_ = signal_in[38];
assign _070_ = signal_in[39];
endmodule
module serial_to_parallel(command, signal_in, enable_stp, reset_stp, clk_SD, signal_out, serial_complete);
wire [8:0] _0000_;
wire _0001_;
wire [135:0] _0002_;
wire _0003_;
wire _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire [31:0] _0497_;
wire [3:0] _0498_;
wire [1:0] _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire _0601_;
wire _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire _0609_;
wire _0610_;
wire _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
wire _0615_;
wire _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire _0623_;
wire _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire [8:0] _0636_;
wire [8:0] _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
wire _0654_;
wire _0655_;
wire _0656_;
wire _0657_;
wire _0658_;
wire _0659_;
wire _0660_;
wire _0661_;
wire _0662_;
wire _0663_;
wire _0664_;
wire _0665_;
wire _0666_;
wire _0667_;
wire [31:0] _0668_;
wire _0669_;
wire _0670_;
wire _0671_;
wire _0672_;
input clk_SD;
input [39:0] command;
wire [8:0] contador;
input enable_stp;
input reset_stp;
output serial_complete;
input signal_in;
output [135:0] signal_out;
NOT _0673_ (
.A(_0054_),
.Y(_0147_)
);
NOT _0674_ (
.A(_0076_),
.Y(_0148_)
);
NAND _0675_ (
.A(_0148_),
.B(_0061_),
.Y(_0150_)
);
NOR _0676_ (
.A(_0150_),
.B(_0147_),
.Y(_0083_)
);
NOT _0677_ (
.A(_0105_),
.Y(_0152_)
);
NOR _0678_ (
.A(_0150_),
.B(_0152_),
.Y(_0120_)
);
NOT _0679_ (
.A(_0091_),
.Y(_0157_)
);
NOR _0680_ (
.A(_0150_),
.B(_0157_),
.Y(_0127_)
);
NOT _0681_ (
.A(_0203_),
.Y(_0159_)
);
NOR _0682_ (
.A(_0150_),
.B(_0159_),
.Y(_0190_)
);
NOT _0683_ (
.A(_0154_),
.Y(_0161_)
);
NOR _0684_ (
.A(_0150_),
.B(_0161_),
.Y(_0216_)
);
NOT _0685_ (
.A(_0253_),
.Y(_0164_)
);
NOR _0686_ (
.A(_0150_),
.B(_0164_),
.Y(_0240_)
);
NOT _0687_ (
.A(_0291_),
.Y(_0166_)
);
NOR _0688_ (
.A(_0150_),
.B(_0166_),
.Y(_0278_)
);
NOT _0689_ (
.A(_0135_),
.Y(_0168_)
);
NOR _0690_ (
.A(_0150_),
.B(_0168_),
.Y(_0303_)
);
NOT _0691_ (
.A(_0314_),
.Y(_0171_)
);
NOR _0692_ (
.A(_0150_),
.B(_0171_),
.Y(_0327_)
);
NOT _0693_ (
.A(_0355_),
.Y(_0173_)
);
NOR _0694_ (
.A(_0150_),
.B(_0173_),
.Y(_0349_)
);
NOT _0695_ (
.A(_0361_),
.Y(_0175_)
);
NOR _0696_ (
.A(_0150_),
.B(_0175_),
.Y(_0383_)
);
NOT _0697_ (
.A(_0372_),
.Y(_0178_)
);
NOR _0698_ (
.A(_0150_),
.B(_0178_),
.Y(_0389_)
);
NOT _0699_ (
.A(_0437_),
.Y(_0180_)
);
NOR _0700_ (
.A(_0150_),
.B(_0180_),
.Y(_0400_)
);
NOT _0701_ (
.A(_0406_),
.Y(_0182_)
);
NOR _0702_ (
.A(_0150_),
.B(_0182_),
.Y(_0426_)
);
NOT _0703_ (
.A(_0464_),
.Y(_0185_)
);
NOR _0704_ (
.A(_0150_),
.B(_0185_),
.Y(_0454_)
);
NOT _0705_ (
.A(_0474_),
.Y(_0187_)
);
NOR _0706_ (
.A(_0150_),
.B(_0187_),
.Y(_0473_)
);
NOT _0707_ (
.A(_0478_),
.Y(_0189_)
);
NOR _0708_ (
.A(_0150_),
.B(_0189_),
.Y(_0477_)
);
NOT _0709_ (
.A(_0475_),
.Y(_0193_)
);
NOR _0710_ (
.A(_0150_),
.B(_0193_),
.Y(_0479_)
);
NOT _0711_ (
.A(_0481_),
.Y(_0195_)
);
NOR _0712_ (
.A(_0150_),
.B(_0195_),
.Y(_0480_)
);
NOT _0713_ (
.A(_0483_),
.Y(_0197_)
);
NOR _0714_ (
.A(_0150_),
.B(_0197_),
.Y(_0482_)
);
NOT _0715_ (
.A(_0484_),
.Y(_0200_)
);
NOR _0716_ (
.A(_0150_),
.B(_0200_),
.Y(_0485_)
);
NOT _0717_ (
.A(_0487_),
.Y(_0202_)
);
NOR _0718_ (
.A(_0150_),
.B(_0202_),
.Y(_0486_)
);
NOT _0719_ (
.A(_0489_),
.Y(_0205_)
);
NOR _0720_ (
.A(_0150_),
.B(_0205_),
.Y(_0488_)
);
NOT _0721_ (
.A(_0491_),
.Y(_0208_)
);
NOR _0722_ (
.A(_0150_),
.B(_0208_),
.Y(_0490_)
);
NOT _0723_ (
.A(_0493_),
.Y(_0210_)
);
NOR _0724_ (
.A(_0150_),
.B(_0210_),
.Y(_0492_)
);
NOT _0725_ (
.A(_0495_),
.Y(_0212_)
);
NOR _0726_ (
.A(_0150_),
.B(_0212_),
.Y(_0494_)
);
NOT _0727_ (
.A(_0008_),
.Y(_0215_)
);
NOR _0728_ (
.A(_0150_),
.B(_0215_),
.Y(_0496_)
);
NOT _0729_ (
.A(_0009_),
.Y(_0218_)
);
NOR _0730_ (
.A(_0150_),
.B(_0218_),
.Y(_0005_)
);
NOT _0731_ (
.A(_0014_),
.Y(_0220_)
);
NOR _0732_ (
.A(_0150_),
.B(_0220_),
.Y(_0007_)
);
NOT _0733_ (
.A(_0011_),
.Y(_0223_)
);
NOR _0734_ (
.A(_0150_),
.B(_0223_),
.Y(_0010_)
);
NOT _0735_ (
.A(_0013_),
.Y(_0225_)
);
NOR _0736_ (
.A(_0150_),
.B(_0225_),
.Y(_0012_)
);
NOT _0737_ (
.A(_0006_),
.Y(_0227_)
);
NOR _0738_ (
.A(_0150_),
.B(_0227_),
.Y(_0015_)
);
NOT _0739_ (
.A(_0019_),
.Y(_0230_)
);
NOR _0740_ (
.A(_0150_),
.B(_0230_),
.Y(_0016_)
);
NOT _0741_ (
.A(_0018_),
.Y(_0232_)
);
NOR _0742_ (
.A(_0150_),
.B(_0232_),
.Y(_0017_)
);
NOT _0743_ (
.A(_0027_),
.Y(_0234_)
);
NOR _0744_ (
.A(_0150_),
.B(_0234_),
.Y(_0021_)
);
NOT _0745_ (
.A(_0023_),
.Y(_0237_)
);
NOR _0746_ (
.A(_0150_),
.B(_0237_),
.Y(_0022_)
);
NOT _0747_ (
.A(_0026_),
.Y(_0239_)
);
NOR _0748_ (
.A(_0150_),
.B(_0239_),
.Y(_0024_)
);
NOT _0749_ (
.A(_0028_),
.Y(_0242_)
);
NOR _0750_ (
.A(_0150_),
.B(_0242_),
.Y(_0029_)
);
NOT _0751_ (
.A(_0020_),
.Y(_0245_)
);
NOR _0752_ (
.A(_0150_),
.B(_0245_),
.Y(_0030_)
);
NOT _0753_ (
.A(_0031_),
.Y(_0247_)
);
NOR _0754_ (
.A(_0150_),
.B(_0247_),
.Y(_0032_)
);
NOT _0755_ (
.A(_0033_),
.Y(_0249_)
);
NOR _0756_ (
.A(_0150_),
.B(_0249_),
.Y(_0034_)
);
NOT _0757_ (
.A(_0035_),
.Y(_0252_)
);
NOR _0758_ (
.A(_0150_),
.B(_0252_),
.Y(_0036_)
);
NOT _0759_ (
.A(_0037_),
.Y(_0255_)
);
NOR _0760_ (
.A(_0150_),
.B(_0255_),
.Y(_0038_)
);
NOT _0761_ (
.A(_0039_),
.Y(_0257_)
);
NOR _0762_ (
.A(_0150_),
.B(_0257_),
.Y(_0040_)
);
NOT _0763_ (
.A(_0041_),
.Y(_0260_)
);
NOR _0764_ (
.A(_0150_),
.B(_0260_),
.Y(_0042_)
);
NOT _0765_ (
.A(_0043_),
.Y(_0262_)
);
NOR _0766_ (
.A(_0150_),
.B(_0262_),
.Y(_0044_)
);
NOT _0767_ (
.A(_0045_),
.Y(_0264_)
);
NOR _0768_ (
.A(_0150_),
.B(_0264_),
.Y(_0046_)
);
NOT _0769_ (
.A(_0047_),
.Y(_0267_)
);
NOR _0770_ (
.A(_0150_),
.B(_0267_),
.Y(_0048_)
);
NOT _0771_ (
.A(_0049_),
.Y(_0269_)
);
NOR _0772_ (
.A(_0150_),
.B(_0269_),
.Y(_0050_)
);
NOT _0773_ (
.A(_0051_),
.Y(_0271_)
);
NOR _0774_ (
.A(_0150_),
.B(_0271_),
.Y(_0052_)
);
NOT _0775_ (
.A(_0053_),
.Y(_0274_)
);
NOR _0776_ (
.A(_0150_),
.B(_0274_),
.Y(_0055_)
);
NOT _0777_ (
.A(_0056_),
.Y(_0276_)
);
NOR _0778_ (
.A(_0150_),
.B(_0276_),
.Y(_0057_)
);
NOT _0779_ (
.A(_0058_),
.Y(_0280_)
);
NOR _0780_ (
.A(_0150_),
.B(_0280_),
.Y(_0059_)
);
NOT _0781_ (
.A(_0060_),
.Y(_0283_)
);
NOR _0782_ (
.A(_0150_),
.B(_0283_),
.Y(_0062_)
);
NOT _0783_ (
.A(_0063_),
.Y(_0285_)
);
NOR _0784_ (
.A(_0150_),
.B(_0285_),
.Y(_0064_)
);
NOT _0785_ (
.A(_0065_),
.Y(_0287_)
);
NOR _0786_ (
.A(_0150_),
.B(_0287_),
.Y(_0066_)
);
NOT _0787_ (
.A(_0067_),
.Y(_0290_)
);
NOR _0788_ (
.A(_0150_),
.B(_0290_),
.Y(_0068_)
);
NOT _0789_ (
.A(_0069_),
.Y(_0293_)
);
NOR _0790_ (
.A(_0150_),
.B(_0293_),
.Y(_0070_)
);
NOT _0791_ (
.A(_0071_),
.Y(_0295_)
);
NOR _0792_ (
.A(_0150_),
.B(_0295_),
.Y(_0072_)
);
NOT _0793_ (
.A(_0073_),
.Y(_0298_)
);
NOR _0794_ (
.A(_0150_),
.B(_0298_),
.Y(_0074_)
);
NOT _0795_ (
.A(_0075_),
.Y(_0300_)
);
NOR _0796_ (
.A(_0150_),
.B(_0300_),
.Y(_0077_)
);
NOT _0797_ (
.A(_0078_),
.Y(_0302_)
);
NOR _0798_ (
.A(_0150_),
.B(_0302_),
.Y(_0079_)
);
NOT _0799_ (
.A(_0080_),
.Y(_0306_)
);
NOR _0800_ (
.A(_0150_),
.B(_0306_),
.Y(_0081_)
);
NOT _0801_ (
.A(_0082_),
.Y(_0308_)
);
NOR _0802_ (
.A(_0150_),
.B(_0308_),
.Y(_0084_)
);
NOT _0803_ (
.A(_0085_),
.Y(_0310_)
);
NOR _0804_ (
.A(_0150_),
.B(_0310_),
.Y(_0086_)
);
NOT _0805_ (
.A(_0087_),
.Y(_0312_)
);
NOR _0806_ (
.A(_0150_),
.B(_0312_),
.Y(_0088_)
);
NOT _0807_ (
.A(_0089_),
.Y(_0313_)
);
NOR _0808_ (
.A(_0150_),
.B(_0313_),
.Y(_0090_)
);
NOT _0809_ (
.A(_0092_),
.Y(_0315_)
);
NOR _0810_ (
.A(_0150_),
.B(_0315_),
.Y(_0093_)
);
NOT _0811_ (
.A(_0094_),
.Y(_0316_)
);
NOR _0812_ (
.A(_0150_),
.B(_0316_),
.Y(_0095_)
);
NOT _0813_ (
.A(_0096_),
.Y(_0317_)
);
NOR _0814_ (
.A(_0150_),
.B(_0317_),
.Y(_0097_)
);
NOT _0815_ (
.A(_0098_),
.Y(_0318_)
);
NOR _0816_ (
.A(_0150_),
.B(_0318_),
.Y(_0099_)
);
NOT _0817_ (
.A(_0100_),
.Y(_0319_)
);
NOR _0818_ (
.A(_0150_),
.B(_0319_),
.Y(_0101_)
);
NOT _0819_ (
.A(_0102_),
.Y(_0320_)
);
NOR _0820_ (
.A(_0150_),
.B(_0320_),
.Y(_0103_)
);
NOT _0821_ (
.A(_0104_),
.Y(_0321_)
);
NOR _0822_ (
.A(_0150_),
.B(_0321_),
.Y(_0106_)
);
NOT _0823_ (
.A(_0107_),
.Y(_0323_)
);
NOR _0824_ (
.A(_0150_),
.B(_0323_),
.Y(_0108_)
);
NOT _0825_ (
.A(_0109_),
.Y(_0325_)
);
NOR _0826_ (
.A(_0150_),
.B(_0325_),
.Y(_0110_)
);
NOT _0827_ (
.A(_0111_),
.Y(_0326_)
);
NOR _0828_ (
.A(_0150_),
.B(_0326_),
.Y(_0112_)
);
NOT _0829_ (
.A(_0113_),
.Y(_0328_)
);
NOR _0830_ (
.A(_0150_),
.B(_0328_),
.Y(_0114_)
);
NOT _0831_ (
.A(_0115_),
.Y(_0329_)
);
NOR _0832_ (
.A(_0150_),
.B(_0329_),
.Y(_0116_)
);
NOT _0833_ (
.A(_0117_),
.Y(_0330_)
);
NOR _0834_ (
.A(_0150_),
.B(_0330_),
.Y(_0118_)
);
NOT _0835_ (
.A(_0119_),
.Y(_0333_)
);
NOR _0836_ (
.A(_0150_),
.B(_0333_),
.Y(_0121_)
);
NOT _0837_ (
.A(_0122_),
.Y(_0336_)
);
NOR _0838_ (
.A(_0150_),
.B(_0336_),
.Y(_0123_)
);
NOT _0839_ (
.A(_0124_),
.Y(_0339_)
);
NOR _0840_ (
.A(_0150_),
.B(_0339_),
.Y(_0125_)
);
NOT _0841_ (
.A(_0126_),
.Y(_0342_)
);
NOR _0842_ (
.A(_0150_),
.B(_0342_),
.Y(_0128_)
);
NOT _0843_ (
.A(_0129_),
.Y(_0345_)
);
NOR _0844_ (
.A(_0150_),
.B(_0345_),
.Y(_0130_)
);
NOT _0845_ (
.A(_0131_),
.Y(_0347_)
);
NOR _0846_ (
.A(_0150_),
.B(_0347_),
.Y(_0132_)
);
NOT _0847_ (
.A(_0133_),
.Y(_0348_)
);
NOR _0848_ (
.A(_0150_),
.B(_0348_),
.Y(_0134_)
);
NOT _0849_ (
.A(_0136_),
.Y(_0350_)
);
NOR _0850_ (
.A(_0150_),
.B(_0350_),
.Y(_0137_)
);
NOT _0851_ (
.A(_0138_),
.Y(_0351_)
);
NOR _0852_ (
.A(_0150_),
.B(_0351_),
.Y(_0139_)
);
NOT _0853_ (
.A(_0140_),
.Y(_0352_)
);
NOR _0854_ (
.A(_0150_),
.B(_0352_),
.Y(_0141_)
);
NOT _0855_ (
.A(_0142_),
.Y(_0353_)
);
NOR _0856_ (
.A(_0150_),
.B(_0353_),
.Y(_0143_)
);
NOT _0857_ (
.A(_0144_),
.Y(_0354_)
);
NOR _0858_ (
.A(_0150_),
.B(_0354_),
.Y(_0145_)
);
NOT _0859_ (
.A(_0146_),
.Y(_0356_)
);
NOR _0860_ (
.A(_0150_),
.B(_0356_),
.Y(_0149_)
);
NOT _0861_ (
.A(_0151_),
.Y(_0357_)
);
NOR _0862_ (
.A(_0150_),
.B(_0357_),
.Y(_0155_)
);
NOT _0863_ (
.A(_0156_),
.Y(_0358_)
);
NOR _0864_ (
.A(_0150_),
.B(_0358_),
.Y(_0158_)
);
NOT _0865_ (
.A(_0160_),
.Y(_0359_)
);
NOR _0866_ (
.A(_0150_),
.B(_0359_),
.Y(_0162_)
);
NOT _0867_ (
.A(_0163_),
.Y(_0360_)
);
NOR _0868_ (
.A(_0150_),
.B(_0360_),
.Y(_0165_)
);
NOT _0869_ (
.A(_0167_),
.Y(_0362_)
);
NOR _0870_ (
.A(_0150_),
.B(_0362_),
.Y(_0169_)
);
NOT _0871_ (
.A(_0170_),
.Y(_0363_)
);
NOR _0872_ (
.A(_0150_),
.B(_0363_),
.Y(_0172_)
);
NOT _0873_ (
.A(_0174_),
.Y(_0364_)
);
NOR _0874_ (
.A(_0150_),
.B(_0364_),
.Y(_0176_)
);
NOT _0875_ (
.A(_0177_),
.Y(_0365_)
);
NOR _0876_ (
.A(_0150_),
.B(_0365_),
.Y(_0179_)
);
NOT _0877_ (
.A(_0181_),
.Y(_0366_)
);
NOR _0878_ (
.A(_0150_),
.B(_0366_),
.Y(_0183_)
);
NOT _0879_ (
.A(_0184_),
.Y(_0367_)
);
NOR _0880_ (
.A(_0150_),
.B(_0367_),
.Y(_0186_)
);
NOT _0881_ (
.A(_0188_),
.Y(_0368_)
);
NOR _0882_ (
.A(_0150_),
.B(_0368_),
.Y(_0191_)
);
NOT _0883_ (
.A(_0192_),
.Y(_0369_)
);
NOR _0884_ (
.A(_0150_),
.B(_0369_),
.Y(_0194_)
);
NOT _0885_ (
.A(_0196_),
.Y(_0370_)
);
NOR _0886_ (
.A(_0150_),
.B(_0370_),
.Y(_0198_)
);
NOT _0887_ (
.A(_0199_),
.Y(_0371_)
);
NOR _0888_ (
.A(_0150_),
.B(_0371_),
.Y(_0201_)
);
NOT _0889_ (
.A(_0204_),
.Y(_0373_)
);
NOR _0890_ (
.A(_0150_),
.B(_0373_),
.Y(_0206_)
);
NOT _0891_ (
.A(_0207_),
.Y(_0374_)
);
NOR _0892_ (
.A(_0150_),
.B(_0374_),
.Y(_0209_)
);
NOT _0893_ (
.A(_0211_),
.Y(_0375_)
);
NOR _0894_ (
.A(_0150_),
.B(_0375_),
.Y(_0213_)
);
NOT _0895_ (
.A(_0214_),
.Y(_0376_)
);
NOR _0896_ (
.A(_0150_),
.B(_0376_),
.Y(_0217_)
);
NOT _0897_ (
.A(_0219_),
.Y(_0377_)
);
NOR _0898_ (
.A(_0150_),
.B(_0377_),
.Y(_0221_)
);
NOT _0899_ (
.A(_0222_),
.Y(_0378_)
);
NOR _0900_ (
.A(_0150_),
.B(_0378_),
.Y(_0224_)
);
NOT _0901_ (
.A(_0226_),
.Y(_0379_)
);
NOR _0902_ (
.A(_0150_),
.B(_0379_),
.Y(_0228_)
);
NOT _0903_ (
.A(_0229_),
.Y(_0380_)
);
NOR _0904_ (
.A(_0150_),
.B(_0380_),
.Y(_0231_)
);
NOT _0905_ (
.A(_0233_),
.Y(_0381_)
);
NOR _0906_ (
.A(_0150_),
.B(_0381_),
.Y(_0235_)
);
NOT _0907_ (
.A(_0236_),
.Y(_0382_)
);
NOR _0908_ (
.A(_0150_),
.B(_0382_),
.Y(_0238_)
);
NOT _0909_ (
.A(_0241_),
.Y(_0384_)
);
NOR _0910_ (
.A(_0150_),
.B(_0384_),
.Y(_0243_)
);
NOT _0911_ (
.A(_0244_),
.Y(_0385_)
);
NOR _0912_ (
.A(_0150_),
.B(_0385_),
.Y(_0246_)
);
NOT _0913_ (
.A(_0248_),
.Y(_0386_)
);
NOR _0914_ (
.A(_0150_),
.B(_0386_),
.Y(_0250_)
);
NOT _0915_ (
.A(_0251_),
.Y(_0387_)
);
NOR _0916_ (
.A(_0150_),
.B(_0387_),
.Y(_0254_)
);
NOT _0917_ (
.A(_0256_),
.Y(_0388_)
);
NOR _0918_ (
.A(_0150_),
.B(_0388_),
.Y(_0258_)
);
NOT _0919_ (
.A(_0259_),
.Y(_0390_)
);
NOR _0920_ (
.A(_0150_),
.B(_0390_),
.Y(_0261_)
);
NOT _0921_ (
.A(_0263_),
.Y(_0391_)
);
NOR _0922_ (
.A(_0150_),
.B(_0391_),
.Y(_0265_)
);
NOT _0923_ (
.A(_0266_),
.Y(_0392_)
);
NOR _0924_ (
.A(_0150_),
.B(_0392_),
.Y(_0268_)
);
NOT _0925_ (
.A(_0270_),
.Y(_0393_)
);
NOR _0926_ (
.A(_0150_),
.B(_0393_),
.Y(_0272_)
);
NOT _0927_ (
.A(_0273_),
.Y(_0394_)
);
NOR _0928_ (
.A(_0150_),
.B(_0394_),
.Y(_0275_)
);
NOT _0929_ (
.A(_0279_),
.Y(_0395_)
);
NOR _0930_ (
.A(_0150_),
.B(_0395_),
.Y(_0281_)
);
NOT _0931_ (
.A(_0282_),
.Y(_0396_)
);
NOR _0932_ (
.A(_0150_),
.B(_0396_),
.Y(_0284_)
);
NOT _0933_ (
.A(_0286_),
.Y(_0397_)
);
NOR _0934_ (
.A(_0150_),
.B(_0397_),
.Y(_0288_)
);
NOT _0935_ (
.A(_0289_),
.Y(_0398_)
);
NOR _0936_ (
.A(_0150_),
.B(_0398_),
.Y(_0292_)
);
NOT _0937_ (
.A(_0294_),
.Y(_0399_)
);
NOR _0938_ (
.A(_0150_),
.B(_0399_),
.Y(_0296_)
);
NOT _0939_ (
.A(_0297_),
.Y(_0401_)
);
NOR _0940_ (
.A(_0150_),
.B(_0401_),
.Y(_0299_)
);
NOT _0941_ (
.A(_0301_),
.Y(_0402_)
);
NOR _0942_ (
.A(_0150_),
.B(_0402_),
.Y(_0304_)
);
NOT _0943_ (
.A(_0305_),
.Y(_0403_)
);
NOR _0944_ (
.A(_0150_),
.B(_0403_),
.Y(_0307_)
);
NOT _0945_ (
.A(_0309_),
.Y(_0404_)
);
NOR _0946_ (
.A(_0150_),
.B(_0404_),
.Y(_0311_)
);
NOR _0947_ (
.A(_0324_),
.B(_0322_),
.Y(_0405_)
);
NOT _0948_ (
.A(_0061_),
.Y(_0407_)
);
NOR _0949_ (
.A(_0407_),
.B(_0025_),
.Y(_0408_)
);
NAND _0950_ (
.A(_0408_),
.B(_0405_),
.Y(_0409_)
);
NOT _0951_ (
.A(_0153_),
.Y(_0410_)
);
NOT _0952_ (
.A(_0277_),
.Y(_0411_)
);
NAND _0953_ (
.A(_0411_),
.B(_0410_),
.Y(_0412_)
);
NOT _0954_ (
.A(_0436_),
.Y(_0413_)
);
NOT _0955_ (
.A(_0476_),
.Y(_0414_)
);
NAND _0956_ (
.A(_0414_),
.B(_0413_),
.Y(_0415_)
);
NOR _0957_ (
.A(_0415_),
.B(_0412_),
.Y(_0416_)
);
NOR _0958_ (
.A(_0004_),
.B(_0003_),
.Y(_0417_)
);
NAND _0959_ (
.A(_0417_),
.B(_0416_),
.Y(_0418_)
);
NOR _0960_ (
.A(_0418_),
.B(_0409_),
.Y(_0419_)
);
NOT _0961_ (
.A(_0322_),
.Y(_0420_)
);
NAND _0962_ (
.A(_0420_),
.B(_0407_),
.Y(_0421_)
);
NOR _0963_ (
.A(_0420_),
.B(_0407_),
.Y(_0422_)
);
NOR _0964_ (
.A(_0422_),
.B(_0076_),
.Y(_0423_)
);
NAND _0965_ (
.A(_0423_),
.B(_0421_),
.Y(_0424_)
);
NOR _0966_ (
.A(_0424_),
.B(_0419_),
.Y(_0331_)
);
NAND _0967_ (
.A(_0324_),
.B(_0322_),
.Y(_0425_)
);
NOR _0968_ (
.A(_0425_),
.B(_0407_),
.Y(_0427_)
);
NOT _0969_ (
.A(_0324_),
.Y(_0428_)
);
NOT _0970_ (
.A(_0422_),
.Y(_0429_)
);
NAND _0971_ (
.A(_0429_),
.B(_0428_),
.Y(_0430_)
);
NAND _0972_ (
.A(_0430_),
.B(_0148_),
.Y(_0431_)
);
NOR _0973_ (
.A(_0431_),
.B(_0427_),
.Y(_0332_)
);
NOT _0974_ (
.A(_0003_),
.Y(_0432_)
);
NOT _0975_ (
.A(_0427_),
.Y(_0433_)
);
NOR _0976_ (
.A(_0433_),
.B(_0432_),
.Y(_0434_)
);
NAND _0977_ (
.A(_0433_),
.B(_0432_),
.Y(_0435_)
);
NAND _0978_ (
.A(_0435_),
.B(_0148_),
.Y(_0438_)
);
NOR _0979_ (
.A(_0438_),
.B(_0434_),
.Y(_0334_)
);
NOR _0980_ (
.A(_0434_),
.B(_0004_),
.Y(_0439_)
);
NOT _0981_ (
.A(_0004_),
.Y(_0440_)
);
NOR _0982_ (
.A(_0440_),
.B(_0432_),
.Y(_0441_)
);
NAND _0983_ (
.A(_0441_),
.B(_0427_),
.Y(_0442_)
);
NAND _0984_ (
.A(_0442_),
.B(_0148_),
.Y(_0443_)
);
NOR _0985_ (
.A(_0443_),
.B(_0439_),
.Y(_0335_)
);
NAND _0986_ (
.A(_0442_),
.B(_0410_),
.Y(_0444_)
);
NAND _0987_ (
.A(_0004_),
.B(_0003_),
.Y(_0445_)
);
NOR _0988_ (
.A(_0445_),
.B(_0410_),
.Y(_0446_)
);
NAND _0989_ (
.A(_0446_),
.B(_0427_),
.Y(_0447_)
);
NAND _0990_ (
.A(_0447_),
.B(_0444_),
.Y(_0448_)
);
NOR _0991_ (
.A(_0448_),
.B(_0076_),
.Y(_0337_)
);
NOR _0992_ (
.A(_0442_),
.B(_0410_),
.Y(_0449_)
);
NOR _0993_ (
.A(_0449_),
.B(_0277_),
.Y(_0450_)
);
NAND _0994_ (
.A(_0449_),
.B(_0277_),
.Y(_0451_)
);
NAND _0995_ (
.A(_0451_),
.B(_0148_),
.Y(_0452_)
);
NOR _0996_ (
.A(_0452_),
.B(_0450_),
.Y(_0338_)
);
NOR _0997_ (
.A(_0425_),
.B(_0411_),
.Y(_0453_)
);
NAND _0998_ (
.A(_0453_),
.B(_0446_),
.Y(_0455_)
);
NOR _0999_ (
.A(_0407_),
.B(_0413_),
.Y(_0456_)
);
NOT _1000_ (
.A(_0456_),
.Y(_0457_)
);
NOR _1001_ (
.A(_0457_),
.B(_0455_),
.Y(_0458_)
);
NAND _1002_ (
.A(_0451_),
.B(_0413_),
.Y(_0459_)
);
NAND _1003_ (
.A(_0459_),
.B(_0148_),
.Y(_0460_)
);
NOR _1004_ (
.A(_0460_),
.B(_0458_),
.Y(_0340_)
);
NOR _1005_ (
.A(_0458_),
.B(_0476_),
.Y(_0461_)
);
NAND _1006_ (
.A(_0456_),
.B(_0476_),
.Y(_0462_)
);
NOR _1007_ (
.A(_0462_),
.B(_0455_),
.Y(_0463_)
);
NOT _1008_ (
.A(_0463_),
.Y(_0465_)
);
NAND _1009_ (
.A(_0465_),
.B(_0148_),
.Y(_0466_)
);
NOR _1010_ (
.A(_0466_),
.B(_0461_),
.Y(_0341_)
);
NOR _1011_ (
.A(_0463_),
.B(_0025_),
.Y(_0467_)
);
NAND _1012_ (
.A(_0463_),
.B(_0025_),
.Y(_0468_)
);
NAND _1013_ (
.A(_0468_),
.B(_0148_),
.Y(_0469_)
);
NOR _1014_ (
.A(_0469_),
.B(_0467_),
.Y(_0343_)
);
NOT _1015_ (
.A(_0344_),
.Y(_0470_)
);
NOR _1016_ (
.A(_0470_),
.B(_0061_),
.Y(_0471_)
);
NOR _1017_ (
.A(_0471_),
.B(_0419_),
.Y(_0472_)
);
NOR _1018_ (
.A(_0472_),
.B(_0076_),
.Y(_0346_)
);
DFF _1019_ (
.C(clk_SD),
.D(_0640_),
.Q(signal_out[0])
);
DFF _1020_ (
.C(clk_SD),
.D(_0002_[1]),
.Q(signal_out[1])
);
DFF _1021_ (
.C(clk_SD),
.D(_0643_),
.Q(signal_out[2])
);
DFF _1022_ (
.C(clk_SD),
.D(_0002_[3]),
.Q(signal_out[3])
);
DFF _1023_ (
.C(clk_SD),
.D(_0002_[4]),
.Q(signal_out[4])
);
DFF _1024_ (
.C(clk_SD),
.D(_0647_),
.Q(signal_out[5])
);
DFF _1025_ (
.C(clk_SD),
.D(_0649_),
.Q(signal_out[6])
);
DFF _1026_ (
.C(clk_SD),
.D(_0651_),
.Q(signal_out[7])
);
DFF _1027_ (
.C(clk_SD),
.D(_0653_),
.Q(signal_out[8])
);
DFF _1028_ (
.C(clk_SD),
.D(_0655_),
.Q(signal_out[9])
);
DFF _1029_ (
.C(clk_SD),
.D(_0657_),
.Q(signal_out[10])
);
DFF _1030_ (
.C(clk_SD),
.D(_0659_),
.Q(signal_out[11])
);
DFF _1031_ (
.C(clk_SD),
.D(_0661_),
.Q(signal_out[12])
);
DFF _1032_ (
.C(clk_SD),
.D(_0663_),
.Q(signal_out[13])
);
DFF _1033_ (
.C(clk_SD),
.D(_0665_),
.Q(signal_out[14])
);
DFF _1034_ (
.C(clk_SD),
.D(_0667_),
.Q(signal_out[15])
);
DFF _1035_ (
.C(clk_SD),
.D(_0503_),
.Q(signal_out[16])
);
DFF _1036_ (
.C(clk_SD),
.D(_0505_),
.Q(signal_out[17])
);
DFF _1037_ (
.C(clk_SD),
.D(_0002_[18]),
.Q(signal_out[18])
);
DFF _1038_ (
.C(clk_SD),
.D(_0002_[19]),
.Q(signal_out[19])
);
DFF _1039_ (
.C(clk_SD),
.D(_0002_[20]),
.Q(signal_out[20])
);
DFF _1040_ (
.C(clk_SD),
.D(_0002_[21]),
.Q(signal_out[21])
);
DFF _1041_ (
.C(clk_SD),
.D(_0002_[22]),
.Q(signal_out[22])
);
DFF _1042_ (
.C(clk_SD),
.D(_0513_),
.Q(signal_out[23])
);
DFF _1043_ (
.C(clk_SD),
.D(_0002_[24]),
.Q(signal_out[24])
);
DFF _1044_ (
.C(clk_SD),
.D(_0002_[25]),
.Q(signal_out[25])
);
DFF _1045_ (
.C(clk_SD),
.D(_0002_[26]),
.Q(signal_out[26])
);
DFF _1046_ (
.C(clk_SD),
.D(_0002_[27]),
.Q(signal_out[27])
);
DFF _1047_ (
.C(clk_SD),
.D(_0002_[28]),
.Q(signal_out[28])
);
DFF _1048_ (
.C(clk_SD),
.D(_0520_),
.Q(signal_out[29])
);
DFF _1049_ (
.C(clk_SD),
.D(_0522_),
.Q(signal_out[30])
);
DFF _1050_ (
.C(clk_SD),
.D(_0524_),
.Q(signal_out[31])
);
DFF _1051_ (
.C(clk_SD),
.D(_0526_),
.Q(signal_out[32])
);
DFF _1052_ (
.C(clk_SD),
.D(_0528_),
.Q(signal_out[33])
);
DFF _1053_ (
.C(clk_SD),
.D(_0530_),
.Q(signal_out[34])
);
DFF _1054_ (
.C(clk_SD),
.D(_0532_),
.Q(signal_out[35])
);
DFF _1055_ (
.C(clk_SD),
.D(_0534_),
.Q(signal_out[36])
);
DFF _1056_ (
.C(clk_SD),
.D(_0536_),
.Q(signal_out[37])
);
DFF _1057_ (
.C(clk_SD),
.D(_0538_),
.Q(signal_out[38])
);
DFF _1058_ (
.C(clk_SD),
.D(_0002_[39]),
.Q(signal_out[39])
);
DFF _1059_ (
.C(clk_SD),
.D(_0002_[40]),
.Q(signal_out[40])
);
DFF _1060_ (
.C(clk_SD),
.D(_0002_[41]),
.Q(signal_out[41])
);
DFF _1061_ (
.C(clk_SD),
.D(_0002_[42]),
.Q(signal_out[42])
);
DFF _1062_ (
.C(clk_SD),
.D(_0002_[43]),
.Q(signal_out[43])
);
DFF _1063_ (
.C(clk_SD),
.D(_0002_[44]),
.Q(signal_out[44])
);
DFF _1064_ (
.C(clk_SD),
.D(_0002_[45]),
.Q(signal_out[45])
);
DFF _1065_ (
.C(clk_SD),
.D(_0002_[46]),
.Q(signal_out[46])
);
DFF _1066_ (
.C(clk_SD),
.D(_0002_[47]),
.Q(signal_out[47])
);
DFF _1067_ (
.C(clk_SD),
.D(_0002_[48]),
.Q(signal_out[48])
);
DFF _1068_ (
.C(clk_SD),
.D(_0002_[49]),
.Q(signal_out[49])
);
DFF _1069_ (
.C(clk_SD),
.D(_0002_[50]),
.Q(signal_out[50])
);
DFF _1070_ (
.C(clk_SD),
.D(_0002_[51]),
.Q(signal_out[51])
);
DFF _1071_ (
.C(clk_SD),
.D(_0002_[52]),
.Q(signal_out[52])
);
DFF _1072_ (
.C(clk_SD),
.D(_0002_[53]),
.Q(signal_out[53])
);
DFF _1073_ (
.C(clk_SD),
.D(_0002_[54]),
.Q(signal_out[54])
);
DFF _1074_ (
.C(clk_SD),
.D(_0002_[55]),
.Q(signal_out[55])
);
DFF _1075_ (
.C(clk_SD),
.D(_0002_[56]),
.Q(signal_out[56])
);
DFF _1076_ (
.C(clk_SD),
.D(_0002_[57]),
.Q(signal_out[57])
);
DFF _1077_ (
.C(clk_SD),
.D(_0002_[58]),
.Q(signal_out[58])
);
DFF _1078_ (
.C(clk_SD),
.D(_0002_[59]),
.Q(signal_out[59])
);
DFF _1079_ (
.C(clk_SD),
.D(_0002_[60]),
.Q(signal_out[60])
);
DFF _1080_ (
.C(clk_SD),
.D(_0002_[61]),
.Q(signal_out[61])
);
DFF _1081_ (
.C(clk_SD),
.D(_0002_[62]),
.Q(signal_out[62])
);
DFF _1082_ (
.C(clk_SD),
.D(_0002_[63]),
.Q(signal_out[63])
);
DFF _1083_ (
.C(clk_SD),
.D(_0002_[64]),
.Q(signal_out[64])
);
DFF _1084_ (
.C(clk_SD),
.D(_0002_[65]),
.Q(signal_out[65])
);
DFF _1085_ (
.C(clk_SD),
.D(_0002_[66]),
.Q(signal_out[66])
);
DFF _1086_ (
.C(clk_SD),
.D(_0002_[67]),
.Q(signal_out[67])
);
DFF _1087_ (
.C(clk_SD),
.D(_0002_[68]),
.Q(signal_out[68])
);
DFF _1088_ (
.C(clk_SD),
.D(_0002_[69]),
.Q(signal_out[69])
);
DFF _1089_ (
.C(clk_SD),
.D(_0002_[70]),
.Q(signal_out[70])
);
DFF _1090_ (
.C(clk_SD),
.D(_0002_[71]),
.Q(signal_out[71])
);
DFF _1091_ (
.C(clk_SD),
.D(_0002_[72]),
.Q(signal_out[72])
);
DFF _1092_ (
.C(clk_SD),
.D(_0002_[73]),
.Q(signal_out[73])
);
DFF _1093_ (
.C(clk_SD),
.D(_0002_[74]),
.Q(signal_out[74])
);
DFF _1094_ (
.C(clk_SD),
.D(_0002_[75]),
.Q(signal_out[75])
);
DFF _1095_ (
.C(clk_SD),
.D(_0002_[76]),
.Q(signal_out[76])
);
DFF _1096_ (
.C(clk_SD),
.D(_0002_[77]),
.Q(signal_out[77])
);
DFF _1097_ (
.C(clk_SD),
.D(_0002_[78]),
.Q(signal_out[78])
);
DFF _1098_ (
.C(clk_SD),
.D(_0002_[79]),
.Q(signal_out[79])
);
DFF _1099_ (
.C(clk_SD),
.D(_0002_[80]),
.Q(signal_out[80])
);
DFF _1100_ (
.C(clk_SD),
.D(_0002_[81]),
.Q(signal_out[81])
);
DFF _1101_ (
.C(clk_SD),
.D(_0002_[82]),
.Q(signal_out[82])
);
DFF _1102_ (
.C(clk_SD),
.D(_0002_[83]),
.Q(signal_out[83])
);
DFF _1103_ (
.C(clk_SD),
.D(_0002_[84]),
.Q(signal_out[84])
);
DFF _1104_ (
.C(clk_SD),
.D(_0002_[85]),
.Q(signal_out[85])
);
DFF _1105_ (
.C(clk_SD),
.D(_0002_[86]),
.Q(signal_out[86])
);
DFF _1106_ (
.C(clk_SD),
.D(_0002_[87]),
.Q(signal_out[87])
);
DFF _1107_ (
.C(clk_SD),
.D(_0002_[88]),
.Q(signal_out[88])
);
DFF _1108_ (
.C(clk_SD),
.D(_0002_[89]),
.Q(signal_out[89])
);
DFF _1109_ (
.C(clk_SD),
.D(_0002_[90]),
.Q(signal_out[90])
);
DFF _1110_ (
.C(clk_SD),
.D(_0002_[91]),
.Q(signal_out[91])
);
DFF _1111_ (
.C(clk_SD),
.D(_0002_[92]),
.Q(signal_out[92])
);
DFF _1112_ (
.C(clk_SD),
.D(_0002_[93]),
.Q(signal_out[93])
);
DFF _1113_ (
.C(clk_SD),
.D(_0002_[94]),
.Q(signal_out[94])
);
DFF _1114_ (
.C(clk_SD),
.D(_0002_[95]),
.Q(signal_out[95])
);
DFF _1115_ (
.C(clk_SD),
.D(_0002_[96]),
.Q(signal_out[96])
);
DFF _1116_ (
.C(clk_SD),
.D(_0002_[97]),
.Q(signal_out[97])
);
DFF _1117_ (
.C(clk_SD),
.D(_0002_[98]),
.Q(signal_out[98])
);
DFF _1118_ (
.C(clk_SD),
.D(_0002_[99]),
.Q(signal_out[99])
);
DFF _1119_ (
.C(clk_SD),
.D(_0002_[100]),
.Q(signal_out[100])
);
DFF _1120_ (
.C(clk_SD),
.D(_0002_[101]),
.Q(signal_out[101])
);
DFF _1121_ (
.C(clk_SD),
.D(_0002_[102]),
.Q(signal_out[102])
);
DFF _1122_ (
.C(clk_SD),
.D(_0002_[103]),
.Q(signal_out[103])
);
DFF _1123_ (
.C(clk_SD),
.D(_0002_[104]),
.Q(signal_out[104])
);
DFF _1124_ (
.C(clk_SD),
.D(_0002_[105]),
.Q(signal_out[105])
);
DFF _1125_ (
.C(clk_SD),
.D(_0002_[106]),
.Q(signal_out[106])
);
DFF _1126_ (
.C(clk_SD),
.D(_0002_[107]),
.Q(signal_out[107])
);
DFF _1127_ (
.C(clk_SD),
.D(_0002_[108]),
.Q(signal_out[108])
);
DFF _1128_ (
.C(clk_SD),
.D(_0002_[109]),
.Q(signal_out[109])
);
DFF _1129_ (
.C(clk_SD),
.D(_0002_[110]),
.Q(signal_out[110])
);
DFF _1130_ (
.C(clk_SD),
.D(_0002_[111]),
.Q(signal_out[111])
);
DFF _1131_ (
.C(clk_SD),
.D(_0002_[112]),
.Q(signal_out[112])
);
DFF _1132_ (
.C(clk_SD),
.D(_0002_[113]),
.Q(signal_out[113])
);
DFF _1133_ (
.C(clk_SD),
.D(_0002_[114]),
.Q(signal_out[114])
);
DFF _1134_ (
.C(clk_SD),
.D(_0002_[115]),
.Q(signal_out[115])
);
DFF _1135_ (
.C(clk_SD),
.D(_0002_[116]),
.Q(signal_out[116])
);
DFF _1136_ (
.C(clk_SD),
.D(_0002_[117]),
.Q(signal_out[117])
);
DFF _1137_ (
.C(clk_SD),
.D(_0002_[118]),
.Q(signal_out[118])
);
DFF _1138_ (
.C(clk_SD),
.D(_0002_[119]),
.Q(signal_out[119])
);
DFF _1139_ (
.C(clk_SD),
.D(_0002_[120]),
.Q(signal_out[120])
);
DFF _1140_ (
.C(clk_SD),
.D(_0002_[121]),
.Q(signal_out[121])
);
DFF _1141_ (
.C(clk_SD),
.D(_0002_[122]),
.Q(signal_out[122])
);
DFF _1142_ (
.C(clk_SD),
.D(_0002_[123]),
.Q(signal_out[123])
);
DFF _1143_ (
.C(clk_SD),
.D(_0002_[124]),
.Q(signal_out[124])
);
DFF _1144_ (
.C(clk_SD),
.D(_0002_[125]),
.Q(signal_out[125])
);
DFF _1145_ (
.C(clk_SD),
.D(_0002_[126]),
.Q(signal_out[126])
);
DFF _1146_ (
.C(clk_SD),
.D(_0002_[127]),
.Q(signal_out[127])
);
DFF _1147_ (
.C(clk_SD),
.D(_0002_[128]),
.Q(signal_out[128])
);
DFF _1148_ (
.C(clk_SD),
.D(_0002_[129]),
.Q(signal_out[129])
);
DFF _1149_ (
.C(clk_SD),
.D(_0002_[130]),
.Q(signal_out[130])
);
DFF _1150_ (
.C(clk_SD),
.D(_0002_[131]),
.Q(signal_out[131])
);
DFF _1151_ (
.C(clk_SD),
.D(_0002_[132]),
.Q(signal_out[132])
);
DFF _1152_ (
.C(clk_SD),
.D(_0002_[133]),
.Q(signal_out[133])
);
DFF _1153_ (
.C(clk_SD),
.D(_0002_[134]),
.Q(signal_out[134])
);
DFF _1154_ (
.C(clk_SD),
.D(_0002_[135]),
.Q(signal_out[135])
);
DFF _1155_ (
.C(clk_SD),
.D(_0000_[0]),
.Q(contador[0])
);
DFF _1156_ (
.C(clk_SD),
.D(_0000_[1]),
.Q(contador[1])
);
DFF _1157_ (
.C(clk_SD),
.D(_0000_[2]),
.Q(contador[2])
);
DFF _1158_ (
.C(clk_SD),
.D(_0000_[3]),
.Q(contador[3])
);
DFF _1159_ (
.C(clk_SD),
.D(_0000_[4]),
.Q(contador[4])
);
DFF _1160_ (
.C(clk_SD),
.D(_0000_[5]),
.Q(contador[5])
);
DFF _1161_ (
.C(clk_SD),
.D(_0000_[6]),
.Q(contador[6])
);
DFF _1162_ (
.C(clk_SD),
.D(_0000_[7]),
.Q(contador[7])
);
DFF _1163_ (
.C(clk_SD),
.D(_0000_[8]),
.Q(contador[8])
);
DFF _1164_ (
.C(clk_SD),
.D(_0001_),
.Q(serial_complete)
);
assign _0003_ = contador[2];
assign _0004_ = contador[3];
assign _0153_ = contador[4];
assign _0277_ = contador[5];
assign _0436_ = contador[6];
assign _0476_ = contador[7];
assign _0025_ = contador[8];
assign _0054_ = signal_out[5];
assign _0061_ = enable_stp;
assign _0076_ = reset_stp;
assign _0647_ = _0083_;
assign _0091_ = signal_out[23];
assign _0105_ = signal_out[33];
assign _0528_ = _0120_;
assign _0513_ = _0127_;
assign _0135_ = signal_out[7];
assign _0154_ = signal_out[37];
assign _0538_ = _0190_;
assign _0203_ = signal_out[38];
assign _0536_ = _0216_;
assign _0640_ = _0240_;
assign _0253_ = signal_out[0];
assign _0649_ = _0278_;
assign _0291_ = signal_out[6];
assign _0651_ = _0303_;
assign _0314_ = signal_out[11];
assign _0659_ = _0327_;
assign _0657_ = _0349_;
assign _0355_ = signal_out[10];
assign _0361_ = signal_out[34];
assign _0372_ = signal_out[35];
assign _0530_ = _0383_;
assign _0532_ = _0389_;
assign _0653_ = _0400_;
assign _0406_ = signal_out[36];
assign _0534_ = _0426_;
assign _0437_ = signal_out[8];
assign _0526_ = _0454_;
assign _0464_ = signal_out[32];
assign _0524_ = _0473_;
assign _0474_ = signal_out[31];
assign _0475_ = signal_out[17];
assign _0665_ = _0477_;
assign _0478_ = signal_out[14];
assign _0505_ = _0479_;
assign _0663_ = _0480_;
assign _0481_ = signal_out[13];
assign _0667_ = _0482_;
assign _0483_ = signal_out[15];
assign _0484_ = signal_out[12];
assign _0661_ = _0485_;
assign _0643_ = _0486_;
assign _0487_ = signal_out[2];
assign _0522_ = _0488_;
assign _0489_ = signal_out[30];
assign _0520_ = _0490_;
assign _0491_ = signal_out[29];
assign _0503_ = _0492_;
assign _0493_ = signal_out[16];
assign _0655_ = _0494_;
assign _0495_ = signal_out[9];
assign _0002_[1] = _0496_;
assign _0002_[28] = _0005_;
assign _0006_ = signal_out[3];
assign _0002_[4] = _0007_;
assign _0008_ = signal_out[1];
assign _0009_ = signal_out[28];
assign _0002_[27] = _0010_;
assign _0011_ = signal_out[27];
assign _0002_[26] = _0012_;
assign _0013_ = signal_out[26];
assign _0014_ = signal_out[4];
assign _0002_[3] = _0015_;
assign _0002_[22] = _0016_;
assign _0002_[21] = _0017_;
assign _0018_ = signal_out[21];
assign _0019_ = signal_out[22];
assign _0020_ = signal_out[19];
assign _0002_[18] = _0021_;
assign _0002_[25] = _0022_;
assign _0023_ = signal_out[25];
assign _0002_[24] = _0024_;
assign _0026_ = signal_out[24];
assign _0027_ = signal_out[18];
assign _0028_ = signal_out[20];
assign _0002_[20] = _0029_;
assign _0002_[19] = _0030_;
assign _0031_ = signal_out[39];
assign _0002_[39] = _0032_;
assign _0033_ = signal_out[40];
assign _0002_[40] = _0034_;
assign _0035_ = signal_out[41];
assign _0002_[41] = _0036_;
assign _0037_ = signal_out[42];
assign _0002_[42] = _0038_;
assign _0039_ = signal_out[43];
assign _0002_[43] = _0040_;
assign _0041_ = signal_out[44];
assign _0002_[44] = _0042_;
assign _0043_ = signal_out[45];
assign _0002_[45] = _0044_;
assign _0045_ = signal_out[46];
assign _0002_[46] = _0046_;
assign _0047_ = signal_out[47];
assign _0002_[47] = _0048_;
assign _0049_ = signal_out[48];
assign _0002_[48] = _0050_;
assign _0051_ = signal_out[49];
assign _0002_[49] = _0052_;
assign _0053_ = signal_out[50];
assign _0002_[50] = _0055_;
assign _0056_ = signal_out[51];
assign _0002_[51] = _0057_;
assign _0058_ = signal_out[52];
assign _0002_[52] = _0059_;
assign _0060_ = signal_out[53];
assign _0002_[53] = _0062_;
assign _0063_ = signal_out[54];
assign _0002_[54] = _0064_;
assign _0065_ = signal_out[55];
assign _0002_[55] = _0066_;
assign _0067_ = signal_out[56];
assign _0002_[56] = _0068_;
assign _0069_ = signal_out[57];
assign _0002_[57] = _0070_;
assign _0071_ = signal_out[58];
assign _0002_[58] = _0072_;
assign _0073_ = signal_out[59];
assign _0002_[59] = _0074_;
assign _0075_ = signal_out[60];
assign _0002_[60] = _0077_;
assign _0078_ = signal_out[61];
assign _0002_[61] = _0079_;
assign _0080_ = signal_out[62];
assign _0002_[62] = _0081_;
assign _0082_ = signal_out[63];
assign _0002_[63] = _0084_;
assign _0085_ = signal_out[64];
assign _0002_[64] = _0086_;
assign _0087_ = signal_out[65];
assign _0002_[65] = _0088_;
assign _0089_ = signal_out[66];
assign _0002_[66] = _0090_;
assign _0092_ = signal_out[67];
assign _0002_[67] = _0093_;
assign _0094_ = signal_out[68];
assign _0002_[68] = _0095_;
assign _0096_ = signal_out[69];
assign _0002_[69] = _0097_;
assign _0098_ = signal_out[70];
assign _0002_[70] = _0099_;
assign _0100_ = signal_out[71];
assign _0002_[71] = _0101_;
assign _0102_ = signal_out[72];
assign _0002_[72] = _0103_;
assign _0104_ = signal_out[73];
assign _0002_[73] = _0106_;
assign _0107_ = signal_out[74];
assign _0002_[74] = _0108_;
assign _0109_ = signal_out[75];
assign _0002_[75] = _0110_;
assign _0111_ = signal_out[76];
assign _0002_[76] = _0112_;
assign _0113_ = signal_out[77];
assign _0002_[77] = _0114_;
assign _0115_ = signal_out[78];
assign _0002_[78] = _0116_;
assign _0117_ = signal_out[79];
assign _0002_[79] = _0118_;
assign _0119_ = signal_out[80];
assign _0002_[80] = _0121_;
assign _0122_ = signal_out[81];
assign _0002_[81] = _0123_;
assign _0124_ = signal_out[82];
assign _0002_[82] = _0125_;
assign _0126_ = signal_out[83];
assign _0002_[83] = _0128_;
assign _0129_ = signal_out[84];
assign _0002_[84] = _0130_;
assign _0131_ = signal_out[85];
assign _0002_[85] = _0132_;
assign _0133_ = signal_out[86];
assign _0002_[86] = _0134_;
assign _0136_ = signal_out[87];
assign _0002_[87] = _0137_;
assign _0138_ = signal_out[88];
assign _0002_[88] = _0139_;
assign _0140_ = signal_out[89];
assign _0002_[89] = _0141_;
assign _0142_ = signal_out[90];
assign _0002_[90] = _0143_;
assign _0144_ = signal_out[91];
assign _0002_[91] = _0145_;
assign _0146_ = signal_out[92];
assign _0002_[92] = _0149_;
assign _0151_ = signal_out[93];
assign _0002_[93] = _0155_;
assign _0156_ = signal_out[94];
assign _0002_[94] = _0158_;
assign _0160_ = signal_out[95];
assign _0002_[95] = _0162_;
assign _0163_ = signal_out[96];
assign _0002_[96] = _0165_;
assign _0167_ = signal_out[97];
assign _0002_[97] = _0169_;
assign _0170_ = signal_out[98];
assign _0002_[98] = _0172_;
assign _0174_ = signal_out[99];
assign _0002_[99] = _0176_;
assign _0177_ = signal_out[100];
assign _0002_[100] = _0179_;
assign _0181_ = signal_out[101];
assign _0002_[101] = _0183_;
assign _0184_ = signal_out[102];
assign _0002_[102] = _0186_;
assign _0188_ = signal_out[103];
assign _0002_[103] = _0191_;
assign _0192_ = signal_out[104];
assign _0002_[104] = _0194_;
assign _0196_ = signal_out[105];
assign _0002_[105] = _0198_;
assign _0199_ = signal_out[106];
assign _0002_[106] = _0201_;
assign _0204_ = signal_out[107];
assign _0002_[107] = _0206_;
assign _0207_ = signal_out[108];
assign _0002_[108] = _0209_;
assign _0211_ = signal_out[109];
assign _0002_[109] = _0213_;
assign _0214_ = signal_out[110];
assign _0002_[110] = _0217_;
assign _0219_ = signal_out[111];
assign _0002_[111] = _0221_;
assign _0222_ = signal_out[112];
assign _0002_[112] = _0224_;
assign _0226_ = signal_out[113];
assign _0002_[113] = _0228_;
assign _0229_ = signal_out[114];
assign _0002_[114] = _0231_;
assign _0233_ = signal_out[115];
assign _0002_[115] = _0235_;
assign _0236_ = signal_out[116];
assign _0002_[116] = _0238_;
assign _0241_ = signal_out[117];
assign _0002_[117] = _0243_;
assign _0244_ = signal_out[118];
assign _0002_[118] = _0246_;
assign _0248_ = signal_out[119];
assign _0002_[119] = _0250_;
assign _0251_ = signal_out[120];
assign _0002_[120] = _0254_;
assign _0256_ = signal_out[121];
assign _0002_[121] = _0258_;
assign _0259_ = signal_out[122];
assign _0002_[122] = _0261_;
assign _0263_ = signal_out[123];
assign _0002_[123] = _0265_;
assign _0266_ = signal_out[124];
assign _0002_[124] = _0268_;
assign _0270_ = signal_out[125];
assign _0002_[125] = _0272_;
assign _0273_ = signal_out[126];
assign _0002_[126] = _0275_;
assign _0279_ = signal_out[127];
assign _0002_[127] = _0281_;
assign _0282_ = signal_out[128];
assign _0002_[128] = _0284_;
assign _0286_ = signal_out[129];
assign _0002_[129] = _0288_;
assign _0289_ = signal_out[130];
assign _0002_[130] = _0292_;
assign _0294_ = signal_out[131];
assign _0002_[131] = _0296_;
assign _0297_ = signal_out[132];
assign _0002_[132] = _0299_;
assign _0301_ = signal_out[133];
assign _0002_[133] = _0304_;
assign _0305_ = signal_out[134];
assign _0002_[134] = _0307_;
assign _0309_ = signal_out[135];
assign _0002_[135] = _0311_;
assign _0322_ = contador[0];
assign _0324_ = contador[1];
assign _0000_[0] = _0331_;
assign _0000_[1] = _0332_;
assign _0000_[2] = _0334_;
assign _0000_[3] = _0335_;
assign _0000_[4] = _0337_;
assign _0000_[5] = _0338_;
assign _0000_[6] = _0340_;
assign _0000_[7] = _0341_;
assign _0000_[8] = _0343_;
assign _0344_ = serial_complete;
assign _0001_ = _0346_;
endmodule
|
// Must be generated:
//
// ram4k_low_low 0 .. 2047
// ram4k_low_high 2048 .. 4095
// ram4k_high_low 4096 .. 6143
// ram4k_high_high 6144 .. 8191
module ram8k_low(input clk,
input [11:0] addr,
input [15:0] data_in,
output [15:0] data_out,
input we,
input re);
wire [15:0] data_out_low;
wire [15:0] data_out_high;
wire we_low;
wire re_low;
wire we_high;
wire re_high;
// Each block is 4048 words; each, in turn,
// made of two 2024 word block
ram4k_low_low r1(.clk(clk),
.addr(addr[10:0]),
.data_in(data_in),
.data_out(data_out_low),
.we(we_low),
.re(re_low));
ram4k_low_high r2(.clk(clk),
.addr(addr[10:0]),
.data_in(data_in),
.data_out(data_out_high),
.we(we_high),
.re(re_high));
reg on_high;
always @(posedge clk) on_high <= addr[11];
assign data_out = on_high?data_out_high:data_out_low;
assign we_high = addr[11]&we;
assign we_low = (~addr[11])&we;
assign re_low = 1;
assign re_high = 1;
endmodule // ram8k
module ram8k_high(input clk,
input [11:0] addr,
input [15:0] data_in,
output [15:0] data_out,
input we,
input re);
wire [15:0] data_out_low;
wire [15:0] data_out_high;
wire we_low;
wire re_low;
wire we_high;
wire re_high;
// Each block is 4048 words; each, in turn,
// made of two 2024 word block
ram4k_high_low r1(.clk(clk),
.addr(addr[10:0]),
.data_in(data_in),
.data_out(data_out_low),
.we(we_low),
.re(re_low));
ram4k_high_high r2(.clk(clk),
.addr(addr[10:0]),
.data_in(data_in),
.data_out(data_out_high),
.we(we_high),
.re(re_high));
reg on_high;
always @(posedge clk) on_high <= addr[11];
assign data_out = on_high?data_out_high:data_out_low;
assign we_high = addr[11]&we;
assign we_low = (~addr[11])&we;
assign re_low = 1;
assign re_high = 1;
endmodule // ram8k
// wrapper for 2 memory bundles on HX8k,
// will be only one on 1k
`ifndef ICESTICK
module ram16k(input clk,
input [12:0] addr,
input [15:0] data_in,
output [15:0] data_out,
input we,
input re);
wire [15:0] data_out_low;
wire [15:0] data_out_high;
wire we_low;
wire re_low;
wire we_high;
wire re_high;
// Each block is 4048 words; each, in turn,
// made of two 2024 word block
ram8k_low r1(.clk(clk),
.addr(addr[11:0]),
.data_in(data_in),
.data_out(data_out_low),
.we(we_low),
.re(re_low));
ram8k_high r2(.clk(clk),
.addr(addr[11:0]),
.data_in(data_in),
.data_out(data_out_high),
.we(we_high),
.re(re_high));
reg on_high;
always @(posedge clk) on_high <= addr[12];
assign data_out = on_high?data_out_high:data_out_low;
assign we_high = addr[12]&we;
assign we_low = (~addr[12])&we;
assign re_low = 1;
assign re_high = 1;
endmodule // ram16k
`else // !`ifndef ICESTICK
module ram16k(input clk,
input [12:0] addr,
input [15:0] data_in,
output [15:0] data_out,
input we,
input re);
// Only low half is available anyway
ram8k_low r1(.clk(clk),
.addr(addr[11:0]),
.data_in(data_in),
.data_out(data_out),
.we(we&(~addr[12])),
.re(re&(~addr[12])));
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:12 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_1_stub.v
// Design : bram_1024_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: VC709_Gen1x8If64_CLK.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx VC709 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module VC709_Gen1x8If64_CLK
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 12,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 6)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [7:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
wire riffa_5_clk;
wire riffa_10_clk;
wire riffa_25_clk;
wire riffa_50_clk;
wire riffa_75_clk;
wire riffa_100_clk;
wire riffa_125_clk;
wire riffa_150_clk;
wire riffa_175_clk;
wire riffa_200_clk;
wire riffa_225_clk;
wire riffa_250_clk;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
OBUF
#()
led_2_obuf
(.O(LED[2]),
.I(cfg_ltssm_state[2]));
OBUF
#()
led_3_obuf
(.O(LED[3]),
.I(cfg_ltssm_state[3]));
OBUF
#()
led_4_obuf
(.O(LED[4]),
.I(cfg_ltssm_state[4]));
OBUF
#()
led_5_obuf
(.O(LED[5]),
.I(cfg_ltssm_state[5]));
OBUF
#()
led_6_obuf
(.O(LED[6]),
.I(pcie_reset_n));
OBUF
#()
led_7_obuf
(.O(LED[7]),
.I(rst_out));
// Core Top Level Wrapper
PCIeGen1x8If64
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_vc709
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
clk_250MIn_1
clkgen
(.user_clk(user_clk),
.riffa_5_clk(riffa_5_clk),
.riffa_10_clk(riffa_10_clk),
.riffa_25_clk(riffa_25_clk),
.riffa_50_clk(riffa_50_clk),
.riffa_75_clk(riffa_75_clk),
.riffa_100_clk(riffa_100_clk));
clk_250MIn_2
clkgen_2
(.user_clk(user_clk),
.riffa_125_clk(riffa_125_clk),
.riffa_150_clk(riffa_150_clk),
.riffa_175_clk(riffa_175_clk),
.riffa_200_clk(riffa_200_clk),
.riffa_225_clk(riffa_225_clk),
.riffa_250_clk(riffa_250_clk));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_5mhz
(.CLK(riffa_5_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[0]),
.CHNL_RX(chnl_rx[0]),
.CHNL_RX_ACK(chnl_rx_ack[0]),
.CHNL_RX_LAST(chnl_rx_last[0]),
.CHNL_RX_LEN(chnl_rx_len[32*0 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*0 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[0]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[0]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[0]),
.CHNL_TX(chnl_tx[0]),
.CHNL_TX_ACK(chnl_tx_ack[0]),
.CHNL_TX_LAST(chnl_tx_last[0]),
.CHNL_TX_LEN(chnl_tx_len[32*0 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*0 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[0]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[0]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_10mhz
(.CLK(riffa_10_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[1]),
.CHNL_RX(chnl_rx[1]),
.CHNL_RX_ACK(chnl_rx_ack[1]),
.CHNL_RX_LAST(chnl_rx_last[1]),
.CHNL_RX_LEN(chnl_rx_len[32*1 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*1 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[1]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[1]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[1]),
.CHNL_TX(chnl_tx[1]),
.CHNL_TX_ACK(chnl_tx_ack[1]),
.CHNL_TX_LAST(chnl_tx_last[1]),
.CHNL_TX_LEN(chnl_tx_len[32*1 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*1 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[1]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[1]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_25mhz
(.CLK(riffa_25_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[2]),
.CHNL_RX(chnl_rx[2]),
.CHNL_RX_ACK(chnl_rx_ack[2]),
.CHNL_RX_LAST(chnl_rx_last[2]),
.CHNL_RX_LEN(chnl_rx_len[32*2 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*2 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[2]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[2]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[2]),
.CHNL_TX(chnl_tx[2]),
.CHNL_TX_ACK(chnl_tx_ack[2]),
.CHNL_TX_LAST(chnl_tx_last[2]),
.CHNL_TX_LEN(chnl_tx_len[32*2 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*2 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[2]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[2]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_50mhz
(.CLK(riffa_50_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[3]),
.CHNL_RX(chnl_rx[3]),
.CHNL_RX_ACK(chnl_rx_ack[3]),
.CHNL_RX_LAST(chnl_rx_last[3]),
.CHNL_RX_LEN(chnl_rx_len[32*3 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*3 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[3]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[3]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[3]),
.CHNL_TX(chnl_tx[3]),
.CHNL_TX_ACK(chnl_tx_ack[3]),
.CHNL_TX_LAST(chnl_tx_last[3]),
.CHNL_TX_LEN(chnl_tx_len[32*3 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*3 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[3]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[3]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_75mhz
(.CLK(riffa_75_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[4]),
.CHNL_RX(chnl_rx[4]),
.CHNL_RX_ACK(chnl_rx_ack[4]),
.CHNL_RX_LAST(chnl_rx_last[4]),
.CHNL_RX_LEN(chnl_rx_len[32*4 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*4 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[4]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[4]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[4]),
.CHNL_TX(chnl_tx[4]),
.CHNL_TX_ACK(chnl_tx_ack[4]),
.CHNL_TX_LAST(chnl_tx_last[4]),
.CHNL_TX_LEN(chnl_tx_len[32*4 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*4 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[4]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[4]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_100mhz
(.CLK(riffa_100_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[5]),
.CHNL_RX(chnl_rx[5]),
.CHNL_RX_ACK(chnl_rx_ack[5]),
.CHNL_RX_LAST(chnl_rx_last[5]),
.CHNL_RX_LEN(chnl_rx_len[32*5 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*5 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[5]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[5]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[5]),
.CHNL_TX(chnl_tx[5]),
.CHNL_TX_ACK(chnl_tx_ack[5]),
.CHNL_TX_LAST(chnl_tx_last[5]),
.CHNL_TX_LEN(chnl_tx_len[32*5 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*5 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[5]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[5]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_125mhz
(.CLK(riffa_125_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[6]),
.CHNL_RX(chnl_rx[6]),
.CHNL_RX_ACK(chnl_rx_ack[6]),
.CHNL_RX_LAST(chnl_rx_last[6]),
.CHNL_RX_LEN(chnl_rx_len[32*6 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*6 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[6]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[6]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[6]),
.CHNL_TX(chnl_tx[6]),
.CHNL_TX_ACK(chnl_tx_ack[6]),
.CHNL_TX_LAST(chnl_tx_last[6]),
.CHNL_TX_LEN(chnl_tx_len[32*6 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*6 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[6]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[6]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_150mhz
(.CLK(riffa_150_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[7]),
.CHNL_RX(chnl_rx[7]),
.CHNL_RX_ACK(chnl_rx_ack[7]),
.CHNL_RX_LAST(chnl_rx_last[7]),
.CHNL_RX_LEN(chnl_rx_len[32*7 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*7 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[7]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[7]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[7]),
.CHNL_TX(chnl_tx[7]),
.CHNL_TX_ACK(chnl_tx_ack[7]),
.CHNL_TX_LAST(chnl_tx_last[7]),
.CHNL_TX_LEN(chnl_tx_len[32*7 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*7 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[7]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[7]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_175mhz
(.CLK(riffa_175_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[8]),
.CHNL_RX(chnl_rx[8]),
.CHNL_RX_ACK(chnl_rx_ack[8]),
.CHNL_RX_LAST(chnl_rx_last[8]),
.CHNL_RX_LEN(chnl_rx_len[32*8 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*8 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[8]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[8]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[8]),
.CHNL_TX(chnl_tx[8]),
.CHNL_TX_ACK(chnl_tx_ack[8]),
.CHNL_TX_LAST(chnl_tx_last[8]),
.CHNL_TX_LEN(chnl_tx_len[32*8 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*8 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[8]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[8]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_200mhz
(.CLK(riffa_200_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[9]),
.CHNL_RX(chnl_rx[9]),
.CHNL_RX_ACK(chnl_rx_ack[9]),
.CHNL_RX_LAST(chnl_rx_last[9]),
.CHNL_RX_LEN(chnl_rx_len[32*9 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*9 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[9]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[9]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[9]),
.CHNL_TX(chnl_tx[9]),
.CHNL_TX_ACK(chnl_tx_ack[9]),
.CHNL_TX_LAST(chnl_tx_last[9]),
.CHNL_TX_LEN(chnl_tx_len[32*9 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*9 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[9]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[9]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_225mhz
(.CLK(riffa_225_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[10]),
.CHNL_RX(chnl_rx[10]),
.CHNL_RX_ACK(chnl_rx_ack[10]),
.CHNL_RX_LAST(chnl_rx_last[10]),
.CHNL_RX_LEN(chnl_rx_len[32*10 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*10 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[10]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[10]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[10]),
.CHNL_TX(chnl_tx[10]),
.CHNL_TX_ACK(chnl_tx_ack[10]),
.CHNL_TX_LAST(chnl_tx_last[10]),
.CHNL_TX_LEN(chnl_tx_len[32*10 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*10 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[10]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[10]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_250mhz
(.CLK(riffa_250_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[11]),
.CHNL_RX(chnl_rx[11]),
.CHNL_RX_ACK(chnl_rx_ack[11]),
.CHNL_RX_LAST(chnl_rx_last[11]),
.CHNL_RX_LEN(chnl_rx_len[32*11 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*11 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[11]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[11]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[11]),
.CHNL_TX(chnl_tx[11]),
.CHNL_TX_ACK(chnl_tx_ack[11]),
.CHNL_TX_LAST(chnl_tx_last[11]),
.CHNL_TX_LEN(chnl_tx_len[32*11 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*11 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[11]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[11]));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module seq_rec #(
parameter BASEADDR = 0,
parameter HIGHADDR = 0,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 2*1024,
parameter IN_BITS = 8
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire SEQ_CLK,
input wire [IN_BITS-1:0] SEQ_IN,
input wire SEQ_EXT_START
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
seq_rec_core #(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES),
.IN_BITS(IN_BITS)
) seq_rec_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SEQ_CLK(SEQ_CLK),
.SEQ_IN(SEQ_IN),
.SEQ_EXT_START(SEQ_EXT_START)
);
endmodule
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
module qa_contents
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output wire [WIDTH-1:0] out_data,
output reg out_nd,
output reg [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output reg error
);
reg [WIDTH-1:0] x;
reg counter;
reg active;
always @ (posedge clk)
begin
out_nd <= 1'b0;
if (~rst_n)
begin
active <= 1'b0;
counter <= 1'b0;
error <= 1'b0;
end
else if (in_nd)
begin
if (((~active)& (in_data != {WIDTH{1'b0}})) | (counter == 1'd0))
begin
active <= 1'b1;
x <= in_data;
counter <= 1'b1;
end
else if (counter == 1'b1)
begin
counter <= 1'b0;
out_nd <= 1'b1;
end
end
end
multiply_complex #(WIDTH) multiply_complex_0
(.clk(clk),
.rst_n(rst_n),
.x(x),
.y(in_data),
.z(out_data)
);
endmodule
|
//
// ram.v -- main memory, using SDRAM
//
module ram(clk, clk_ok, reset,
en, wr, size, addr,
data_in, data_out, wt,
sdram_cke, sdram_cs_n,
sdram_ras_n, sdram_cas_n,
sdram_we_n, sdram_ba, sdram_a,
sdram_udqm, sdram_ldqm, sdram_dq);
// internal interface signals
input clk;
input clk_ok;
input reset;
input en;
input wr;
input [1:0] size;
input [24:0] addr;
input [31:0] data_in;
output reg [31:0] data_out;
output reg wt;
// SDRAM interface signals
output sdram_cke;
output sdram_cs_n;
output sdram_ras_n;
output sdram_cas_n;
output sdram_we_n;
output [1:0] sdram_ba;
output [12:0] sdram_a;
output sdram_udqm;
output sdram_ldqm;
inout [15:0] sdram_dq;
reg [3:0] state;
reg a0;
reg cntl_read;
reg cntl_write;
wire cntl_done;
wire [23:0] cntl_addr;
reg [15:0] cntl_din;
wire [15:0] cntl_dout;
wire sd_out_en;
wire [15:0] sd_out;
//--------------------------------------------------------------
sdramCntl sdramCntl1(
// clock
.clk(clk),
.clk_ok(clk_ok),
// host side
.rd(cntl_read & ~cntl_done),
.wr(cntl_write & ~cntl_done),
.done(cntl_done),
.hAddr(cntl_addr),
.hDIn(cntl_din),
.hDOut(cntl_dout),
// SDRAM side
.cke(sdram_cke),
.ce_n(sdram_cs_n),
.ras_n(sdram_ras_n),
.cas_n(sdram_cas_n),
.we_n(sdram_we_n),
.ba(sdram_ba),
.sAddr(sdram_a),
.sDIn(sdram_dq),
.sDOut(sd_out),
.sDOutEn(sd_out_en),
.dqmh(sdram_udqm),
.dqml(sdram_ldqm)
);
assign sdram_dq = (sd_out_en == 1) ? sd_out : 16'hzzzz;
//--------------------------------------------------------------
// the SDRAM is organized in 16-bit halfwords
// address line 0 is controlled by the state machine
// (this is necessary for word accesses)
assign cntl_addr[23:1] = addr[24:2];
assign cntl_addr[0] = a0;
// state machine for SDRAM access
always @(posedge clk) begin
if (reset == 1) begin
state <= 4'b0000;
wt <= 1;
end else begin
case (state)
4'b0000:
// wait for access
begin
if (en == 1) begin
// access
if (wr == 1) begin
// write
if (size[1] == 1) begin
// write word
state <= 4'b0001;
end else begin
if (size[0] == 1) begin
// write halfword
state <= 4'b0101;
end else begin
// write byte
state <= 4'b0111;
end
end
end else begin
// read
if (size[1] == 1) begin
// read word
state <= 4'b0011;
end else begin
if (size[0] == 1) begin
// read halfword
state <= 4'b0110;
end else begin
// read byte
state <= 4'b1001;
end
end
end
end
end
4'b0001:
// write word, upper 16 bits
begin
if (cntl_done == 1) begin
state <= 4'b0010;
end
end
4'b0010:
// write word, lower 16 bits
begin
if (cntl_done == 1) begin
state <= 4'b1111;
wt <= 0;
end
end
4'b0011:
// read word, upper 16 bits
begin
if (cntl_done == 1) begin
state <= 4'b0100;
data_out[31:16] <= cntl_dout;
end
end
4'b0100:
// read word, lower 16 bits
begin
if (cntl_done == 1) begin
state <= 4'b1111;
data_out[15:0] <= cntl_dout;
wt <= 0;
end
end
4'b0101:
// write halfword
begin
if (cntl_done == 1) begin
state <= 4'b1111;
wt <= 0;
end
end
4'b0110:
// read halfword
begin
if (cntl_done == 1) begin
state <= 4'b1111;
data_out[31:16] <= 16'h0000;
data_out[15:0] <= cntl_dout;
wt <= 0;
end
end
4'b0111:
// write byte (read halfword cycle)
begin
if (cntl_done == 1) begin
state <= 4'b1000;
data_out[31:16] <= 16'h0000;
data_out[15:0] <= cntl_dout;
end
end
4'b1000:
// write byte (write halfword cycle)
begin
if (cntl_done == 1) begin
state <= 4'b1111;
wt <= 0;
end
end
4'b1001:
// read byte
begin
if (cntl_done == 1) begin
state <= 4'b1111;
data_out[31:8] <= 24'h000000;
if (addr[0] == 0) begin
data_out[7:0] <= cntl_dout[15:8];
end else begin
data_out[7:0] <= cntl_dout[7:0];
end
wt <= 0;
end
end
4'b1111:
// end of bus cycle
begin
state <= 4'b0000;
wt <= 1;
end
default:
// all other states: reset
begin
state <= 4'b0000;
wt <= 1;
end
endcase
end
end
// output of state machine
always @(*) begin
case (state)
4'b0000:
// wait for access
begin
a0 = 1'bx;
cntl_read = 0;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b0001:
// write word, upper 16 bits
begin
a0 = 1'b0;
cntl_read = 0;
cntl_write = 1;
cntl_din = data_in[31:16];
end
4'b0010:
// write word, lower 16 bits
begin
a0 = 1'b1;
cntl_read = 0;
cntl_write = 1;
cntl_din = data_in[15:0];
end
4'b0011:
// read word, upper 16 bits
begin
a0 = 1'b0;
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b0100:
// read word, lower 16 bits
begin
a0 = 1'b1;
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b0101:
// write halfword
begin
a0 = addr[1];
cntl_read = 0;
cntl_write = 1;
cntl_din = data_in[15:0];
end
4'b0110:
// read halfword
begin
a0 = addr[1];
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b0111:
// write byte (read halfword cycle)
begin
a0 = addr[1];
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b1000:
// write byte (write halfword cycle)
begin
a0 = addr[1];
cntl_read = 0;
cntl_write = 1;
if (addr[0] == 0) begin
cntl_din = { data_in[7:0], data_out[7:0] };
end else begin
cntl_din = { data_out[15:8], data_in[7:0] };
end
end
4'b1001:
// read byte
begin
a0 = addr[1];
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b1111:
// end of bus cycle
begin
a0 = 1'bx;
cntl_read = 0;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
default:
// all other states: reset
begin
a0 = 1'bx;
cntl_read = 0;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
endcase
end
endmodule
|
/*
* File: pippo_operandmuxes.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* Mux.A:
* input: rf_a, wb_fwd
* output: bus a (alu, mac, lsu)
* Mux.B:
* input: rf_b, imm, wb_fwd
* output: bus b (alu, mac, lsu, sprs(dat_i), except(datain))
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_operandmuxes(
rf_dataa, rf_datab, wb_fwd, imm,
sel_a, sel_b,
bus_a, bus_b
);
parameter width = `OPERAND_WIDTH;
//
// I/O
//
input [width-1:0] rf_dataa;
input [width-1:0] rf_datab;
input [width-1:0] wb_fwd;
input [width-1:0] imm;
input [`OPSEL_WIDTH-1:0] sel_a;
input [`OPSEL_WIDTH-1:0] sel_b;
output [width-1:0] bus_a;
output [width-1:0] bus_b;
//
// Internal wires and regs
//
reg [width-1:0] bus_a;
reg [width-1:0] bus_b;
//
// Multiplexer for operand bus A
// source: rf_dataa, wb_fwd
//
always @(wb_fwd or rf_dataa or sel_a) begin
`ifdef pippo_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_a) // synopsys parallel_case infer_mux
`else
casex (sel_a) // synopsys parallel_case
`endif
`OPSEL_WBFWD:
bus_a = wb_fwd;
`OPSEL_RF:
bus_a = rf_dataa;
default:
bus_a = rf_dataa;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("%t: WARNING: OperandMux enter default case %h", $time);
// synopsys translate_on
`endif
endcase
end
//
// Multiplexer for operand bus B
// source: imm, rf_datab, wb_fwd
//
always @(imm or wb_fwd or rf_datab or sel_b) begin
`ifdef pippo_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_b) // synopsys parallel_case infer_mux
`else
casex (sel_b) // synopsys parallel_case
`endif
`OPSEL_IMM:
bus_b = imm;
`OPSEL_WBFWD:
bus_b = wb_fwd;
`OPSEL_RF:
bus_b = rf_datab;
default:
bus_b = rf_datab;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("%t: WARNING: OperandMux enter default case %h", $time);
// synopsys translate_on
`endif
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__OR3_PP_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_LP_V
`define SKY130_FD_SC_LP__A31O_LP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_lp (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3B_4_V
`define SKY130_FD_SC_MS__OR3B_4_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3B_4_V
|
`timescale 1ns / 100ps
module VitaPolySimple(
input wire clk50M,
input wire key0,
input wire key1,
input wire sw0,
input wire sw1,
input wire sw2,
input wire sw3,
output snd_0,
output snd_1,
output snd_2,
output snd_3,
output snd_4,
output snd_5,
output snd_6,
output snd_7,
output pwm_out_0,
output pwm_out_1,
input wire MIDI_IN,
output led0,
output led1,
output [7:0] SEG
);
//генератор сброса
wire rst;
powerup_reset res_gen(.clk(clk50M), .key(~key0), .rst(rst));
//MIDI вход
wire [3:0] CH_MESSAGE;
wire [3:0] CHAN;
wire [6:0] NOTE;
wire [6:0] LSB;
wire [6:0] MSB;
midi_in midi_in_0(.clk(clk50M),
.rst(rst),
.midi_in(MIDI_IN),
.chan(CHAN),
.ch_message(CH_MESSAGE),
.lsb(LSB),
.msb(MSB),
.note(NOTE));
//ловим ноту на любом, кроме 10-го барабанного канала
wire NOTE_ON = ((CH_MESSAGE==4'b1001)&&(CHAN!=4'd9)); //строб признак появления сообщения note on
wire NOTE_OFF = ((CH_MESSAGE==4'b1000)&&(CHAN!=4'd9)); //строб признак появления сообщения note off
wire GATE; // сигнал GATE в единице между note on и note off
//reg_rs GATEreg(.clk(clk50M), .s(NOTE_ON), .r(NOTE_OFF), .data_out(GATE));
wire [6:0] LAST_NOTE; //последняя полученная нота
//reg7 NOTEreg(.clk(clk50M), .wr(NOTE_ON), .data(NOTE), .data_out(LAST_NOTE));
note_mono note_mono_0(.clk(clk50M),
.rst(rst),
.note_on(NOTE_ON),
.note_off(NOTE_OFF),
.note(NOTE),
.out_note(LAST_NOTE),
.out_gate(GATE));
//PITCH
wire ptch_strobe = (CH_MESSAGE==4'b1110)||rst; //сообщение PITCH
wire [13:0] pitch_value = (rst) ? 14'd08192 : {MSB,LSB};
wire [13:0] pitch; // значение PITCH
reg14w pitch_reg(.clk(clk50M), .wr(ptch_strobe), .data(pitch_value), .data_out(pitch));
/* wire [31:0] adder_val;
note_pitch2dds transl1(.clk(clk50M),
.note(LAST_NOTE),
.pitch(pitch_val),
.adder(adder_val)); */
/*
note2dds transl1(.clk(clk50M),
.note(LAST_NOTE),
.adder(adder_val));*/
//масштабирование
wire [31:0] add_value;
lin2exp_t exp(.data_in(MSB), .data_out(add_value));
//ADSR
//A1
wire [13:0] A1;
wire A1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd016))||rst; // control change & 16 control - LSB
wire [13:0] A1_value = (rst) ? 14'd07540 : add_value[13:0];
reg14w A1reg(clk50M, A1_lsb, A1_value, A1);
//D1
wire [13:0] D1;
wire D1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd017))||rst; // control change & 17 control - LSB
wire [13:0] D1_value = (rst) ? 14'd07540 : add_value[13:0];
reg14w D1reg(clk50M, D1_lsb, D1_value, D1);
//S1
wire [6:0] S1;
wire S1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd018))||rst; // control change & 18 control - LSB
wire [6:0] S1_value = (rst) ? 7'b1111111 : MSB;
reg7 S1reg(clk50M, S1_lsb, S1_value, S1);
//R1
wire [13:0] R1;
wire R1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd019))||rst; // control change & 19 control - LSB
wire [13:0] R1_value = (rst) ? 14'd07540 : add_value[13:0];
reg14w R1reg(clk50M, R1_lsb, R1_value, R1);
//WAVE FORM
wire [6:0] W_FORM;
wire W_FORM_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd048))||rst; // control change & 48 control - LSB
wire [6:0] W_FORM_value = (rst) ? 7'd0 : MSB;
reg7 W_FORM_reg(clk50M, W_FORM_lsb, W_FORM_value, W_FORM);
// LFO FORM
wire [6:0] LFO_FORM;
wire LFO_FORM_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd049))||rst; // control change & 49 control - LSB
wire [6:0] LFO_FORM_lsb_value = (rst) ? 7'd0 : MSB;
reg7 LFO_FORM_lsb_reg(clk50M, LFO_FORM_lsb, LFO_FORM_lsb_value, LFO_FORM);
// LFO RATE
wire [6:0] LFO_RATE;
wire LFO_RATE_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd050))||rst; // control change & 50 control - LSB
wire [6:0] LFO_RATE_value = (rst) ? 7'd0 : MSB;
reg7 LFO_RATE_reg(clk50M, LFO_RATE_lsb, LFO_RATE_value, LFO_RATE);
// LFO DEPTH
wire [6:0] LFO_DEPTH;
wire LFO_DEPTH_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd051))||rst; // control change & 51 control - LSB
wire [6:0] LFO_DEPTH_value = (rst) ? 7'd0 : MSB;
reg7 LFO_DEPTH_reg(clk50M, LFO_DEPTH_lsb, LFO_DEPTH_value, LFO_DEPTH);
// LFO DEPTH2
wire [6:0] LFO_DEPTH2;
wire LFO_DEPTH2_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd052))||rst; // control change & 52 control - LSB
wire [6:0] LFO_DEPTH2_value = (rst) ? 7'd0 : MSB;
reg7 LFO_DEPTH2_reg(clk50M, LFO_DEPTH2_lsb, LFO_DEPTH2_value, LFO_DEPTH2);
// LFO DEPTH3 (fine)
wire [6:0] LFO_DEPTH3;
wire LFO_DEPTH3_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd053))||rst; // control change & 53 control - LSB
wire [6:0] LFO_DEPTH3_value = (rst) ? 7'd0 : MSB;
reg7 LFO_DEPTH3_reg(clk50M, LFO_DEPTH3_lsb, LFO_DEPTH3_value, LFO_DEPTH3);
// VREF
wire [6:0] VREF;
wire VREF_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd054))||rst; // control change & 54 control - LSB
wire [6:0] VREF_value = (rst) ? 7'd024 : MSB;
reg7 VREF_reg(clk50M, VREF_lsb, VREF_value, VREF);
//вывод VREF
ds8dac1 dac_vref(.clk(clk50M), .in_data({VREF, 1'b0}), .sout(pwm_out_0)); //pwm8dac1, ds8dac1, rnd8dac1
wire [31:0] lfo1_out;
wire [31:0] lfo1_adder = LFO_RATE << 4;
dds #(.WIDTH(32)) lfo_osc1(.clk(clk50M), .adder(lfo1_adder), .signal_out(lfo1_out));
//SINE table
wire [7:0] lfo_sine_out;
sine sine_rom(.address(lfo1_out[31:31-7]),
.q(lfo_sine_out),
.clock(clk50M));
// wave_forms
parameter SAW = 3'b000;
parameter SQUARE = 3'b001; //with PWM
parameter TRIANGLE = 3'b010;
parameter SINE = 3'b011;
parameter RAMP = 3'b100;
parameter SAW_TRI = 3'b101;
parameter NOISE = 3'b110;
parameter UNDEF = 3'b111;
wire [7:0] saw_out = lfo1_out[31:31-7];
wire [7:0] square_out = (lfo1_out[31:31-7] > 127) ? 8'b11111111 : 1'b00000000;
wire [7:0] tri_out = (saw_out>8'd191) ? 7'd127 + ((saw_out << 1) - 9'd511) :
(saw_out>8'd063) ? 8'd255 - ((saw_out << 1) - 7'd127) : 7'd127 + (saw_out << 1);
wire [7:0] ramp_out = -saw_out;
wire [7:0] saw_tri_out = (saw_out > 7'd127) ? -saw_out : 8'd127 + saw_out;
//signal_out
wire [7:0] lfo_signal_out = (LFO_FORM == SAW) ? saw_out :
(LFO_FORM == SQUARE) ? square_out :
(LFO_FORM == TRIANGLE) ? tri_out :
(LFO_FORM == SINE) ? lfo_sine_out :
(LFO_FORM == RAMP) ? ramp_out :
(LFO_FORM == SAW_TRI) ? saw_tri_out : 8'd127;
wire [15:0] lfo_with_depth = lfo_signal_out * (LFO_DEPTH << 1);
wire [7:0] lfo_result = lfo_with_depth[15:8];
//ONE VOICE
wire [7:0] voice1_wave_form;
wire [7:0] ss1,ss2,ss3,ss4,ss5,ss6,ss7;
voice voice1(.clk(clk50M),
.gate(GATE),
.note(LAST_NOTE),
.pitch(pitch),
.lfo_sig(lfo_signal_out),
.lfo_depth(LFO_DEPTH2),
.lfo_depth_fine(LFO_DEPTH3),
.wave_form(W_FORM[2:0]),
.signal_out(voice1_wave_form));
//ADSR
wire [31:0] adsr1out;
adsr32 adsr1(clk50M, GATE, A1, D1, {S1,25'b0}, R1, adsr1out);
wire [7:0] adsr1_8bit = adsr1out[31:31-7];
wire [7:0] lfo_8bit = 8'd255 - lfo_result;
//digi VCA lfo
wire [7:0] voice1_with_digital_lfo;
svca #(.WIDTH(8)) digital_vca_1(.in(voice1_wave_form) , .cv(lfo_8bit), .signal_out(voice1_with_digital_lfo));
//digi VCA adsr
wire [7:0] voice1_with_digital_vca;
svca #(.WIDTH(8)) digital_vca_2(.in(voice1_with_digital_lfo) , .cv(adsr1_8bit), .signal_out(voice1_with_digital_vca));
assign led0 = ~MIDI_IN;
assign led1 = GATE;
assign SEG = (GATE) ? {MIDI_IN, S1} : 8'd0;
//вывод сигнала VCO масштабированным в цифровом виде
wire out1bit;
pwm8dac1 dac1(clk50M, voice1_with_digital_vca, out1bit); //pwm8dac1, ds8dac1, rnd8dac1
assign snd_0 = out1bit;
assign snd_1 = out1bit;
assign pwm_out_1 = out1bit;
endmodule
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import CpdtTactics.
Set Implicit Arguments.
(* end hide *)
(** %\part{Basic Programming and Proving}
\chapter{Introducing Inductive Types}% *)
(** The logical foundation of Coq is the Calculus of Inductive Constructions, or CIC. In a sense, CIC is built from just two relatively straightforward features: function types and inductive types. From this modest foundation, we can prove essentially all of the theorems of math and carry out effectively all program verifications, with enough effort expended. This chapter introduces induction and recursion for functional programming in Coq. Most of our examples reproduce functionality from the Coq standard library, and I have tried to copy the standard library's choices of identifiers, where possible, so many of the definitions here are already available in the default Coq environment.
The last chapter took a deep dive into some of the more advanced Coq features, to highlight the unusual approach that I advocate in this book. However, from this point on, we will rewind and go back to basics, presenting the relevant features of Coq in a more bottom-up manner. A useful first step is a discussion of the differences and relationships between proofs and programs in Coq. *)
(** * Proof Terms *)
(** Mainstream presentations of mathematics treat proofs as objects that exist outside of the universe of mathematical objects. However, for a variety of reasoning tasks, it is convenient to encode proofs, traditional mathematical objects, and programs within a single formal language. Validity checks on mathematical objects are useful in any setting, to catch typos and other uninteresting errors. The benefits of static typing for programs are widely recognized, and Coq brings those benefits to both mathematical objects and programs via a uniform mechanism. In fact, from this point on, we will not bother to distinguish between programs and mathematical objects. Many mathematical formalisms are most easily encoded in terms of programs.
Proofs are fundamentally different from programs, because any two proofs of a theorem are considered equivalent, from a formal standpoint if not from an engineering standpoint. However, we can use the same type-checking technology to check proofs as we use to validate our programs. This is the%\index{Curry-Howard correspondence}% _Curry-Howard correspondence_ %\cite{Curry,Howard}%, an approach for relating proofs and programs. We represent mathematical theorems as types, such that a theorem's proofs are exactly those programs that type-check at the corresponding type.
The last chapter's example already snuck in an instance of Curry-Howard. We used the token [->] to stand for both function types and logical implications. One reasonable conclusion upon seeing this might be that some fancy overloading of notations is at work. In fact, functions and implications are precisely identical according to Curry-Howard! That is, they are just two ways of describing the same computational phenomenon.
A short demonstration should explain how this can be. The identity function over the natural numbers is certainly not a controversial program. *)
Check (fun x : nat => x).
(** [: nat -> nat] *)
(** %\smallskip{}%Consider this alternate program, which is almost identical to the last one. *)
Check (fun x : True => x).
(** [: True -> True] *)
(** %\smallskip{}%The identity program is interpreted as a proof that %\index{Gallina terms!True}%[True], the always-true proposition, implies itself! What we see is that Curry-Howard interprets implications as functions, where an input is a proposition being assumed and an output is a proposition being deduced. This intuition is not too far from a common one for informal theorem proving, where we might already think of an implication proof as a process for transforming a hypothesis into a conclusion.
There are also more primitive proof forms available. For instance, the term %\index{Gallina terms!I}%[I] is the single proof of [True], applicable in any context. *)
Check I.
(** [: True] *)
(** %\smallskip{}%With [I], we can prove another simple propositional theorem. *)
Check (fun _ : False => I).
(** [: False -> True] *)
(** %\smallskip{}%No proofs of %\index{Gallina terms!False}%[False] exist in the top-level context, but the implication-as-function analogy gives us an easy way to, for example, show that [False] implies itself. *)
Check (fun x : False => x).
(** [: False -> False] *)
(** %\smallskip{}%Every one of these example programs whose type looks like a logical formula is a%\index{proof term}% _proof term_. We use that name for any Gallina term of a logical type, and we will elaborate shortly on what makes a type logical.
In the rest of this chapter, we will introduce different ways of defining types. Every example type can be interpreted alternatively as a type of programs or proofs.
One of the first types we introduce will be [bool], with constructors [true] and [false]. Newcomers to Coq often wonder about the distinction between [True] and [true] and the distinction between [False] and [false]. One glib answer is that [True] and [False] are types, but [true] and [false] are not. A more useful answer is that Coq's metatheory guarantees that any term of type [bool] _evaluates_ to either [true] or [false]. This means that we have an _algorithm_ for answering any question phrased as an expression of type [bool]. Conversely, most propositions do not evaluate to [True] or [False]; the language of inductively defined propositions is much richer than that. We ought to be glad that we have no algorithm for deciding our formalized version of mathematical truth, since otherwise it would be clear that we could not formalize undecidable properties, like almost any interesting property of general-purpose programs. *)
(** * Enumerations *)
(** Coq inductive types generalize the %\index{algebraic datatypes}%algebraic datatypes found in %\index{Haskell}%Haskell and %\index{ML}%ML. Confusingly enough, inductive types also generalize %\index{generalized algebraic datatypes}%generalized algebraic datatypes (GADTs), by adding the possibility for type dependency. Even so, it is worth backing up from the examples of the last chapter and going over basic, algebraic-datatype uses of inductive datatypes, because the chance to prove things about the values of these types adds new wrinkles beyond usual practice in Haskell and ML.
The singleton type [unit] is an inductive type:%\index{Gallina terms!unit}\index{Gallina terms!tt}% *)
Inductive unit : Set :=
| tt.
(** This vernacular command defines a new inductive type [unit] whose only value is [tt]. We can verify the types of the two identifiers we introduce: *)
Check unit.
(** [unit : Set] *)
Check tt.
(** [tt : unit] *)
(** %\smallskip{}%We can prove that [unit] is a genuine singleton type. *)
Theorem unit_singleton : forall x : unit, x = tt.
(** The important thing about an inductive type is, unsurprisingly, that you can do induction over its values, and induction is the key to proving this theorem. We ask to proceed by induction on the variable [x].%\index{tactics!induction}% *)
(* begin thide *)
induction x.
(** The goal changes to:
[[
tt = tt
]]
*)
(** %\noindent{}%...which we can discharge trivially. *)
reflexivity.
Qed.
(* end thide *)
(** It seems kind of odd to write a proof by induction with no inductive hypotheses. We could have arrived at the same result by beginning the proof with:%\index{tactics!destruct}% [[
destruct x.
]]
%\noindent%...which corresponds to "proof by case analysis" in classical math. For non-recursive inductive types, the two tactics will always have identical behavior. Often case analysis is sufficient, even in proofs about recursive types, and it is nice to avoid introducing unneeded induction hypotheses.
What exactly _is_ the %\index{induction principles}%induction principle for [unit]? We can ask Coq: *)
Check unit_ind.
(** [unit_ind : forall P : unit -> Prop, P tt -> forall u : unit, P u] *)
(** %\smallskip{}%Every [Inductive] command defining a type [T] also defines an induction principle named [T_ind]. Recall from the last section that our type, operations over it, and principles for reasoning about it all live in the same language and are described by the same type system. The key to telling what is a program and what is a proof lies in the distinction between the type %\index{Gallina terms!Prop}%[Prop], which appears in our induction principle; and the type %\index{Gallina terms!Set}%[Set], which we have seen a few times already.
The convention goes like this: [Set] is the type of normal types used in programming, and the values of such types are programs. [Prop] is the type of logical propositions, and the values of such types are proofs. Thus, an induction principle has a type that shows us that it is a function for building proofs.
Specifically, [unit_ind] quantifies over a predicate [P] over [unit] values. If we can present a proof that [P] holds of [tt], then we are rewarded with a proof that [P] holds for any value [u] of type [unit]. In our last proof, the predicate was [(fun u : unit => u = tt)].
The definition of [unit] places the type in [Set]. By replacing [Set] with [Prop], [unit] with [True], and [tt] with [I], we arrive at precisely the definition of [True] that the Coq standard library employs! The program type [unit] is the Curry-Howard equivalent of the proposition [True]. We might make the tongue-in-cheek claim that, while philosophers have expended much ink on the nature of truth, we have now determined that truth is the [unit] type of functional programming.
%\medskip%
We can define an inductive type even simpler than [unit]:%\index{Gallina terms!Empty\_set}% *)
Inductive Empty_set : Set := .
(** [Empty_set] has no elements. We can prove fun theorems about it: *)
Theorem the_sky_is_falling : forall x : Empty_set, 2 + 2 = 5.
(* begin thide *)
destruct 1.
Qed.
(* end thide *)
(** Because [Empty_set] has no elements, the fact of having an element of this type implies anything. We use [destruct 1] instead of [destruct x] in the proof because unused quantified variables are relegated to being referred to by number. (There is a good reason for this, related to the unity of quantifiers and implication. At least within Coq's logical foundation of %\index{constructive logic}%constructive logic, which we elaborate on more in the next chapter, an implication is just a quantification over a proof, where the quantified variable is never used. It generally makes more sense to refer to implication hypotheses by number than by name, and Coq treats our quantifier over an unused variable as an implication in determining the proper behavior.)
We can see the induction principle that made this proof so easy: *)
Check Empty_set_ind.
(** [Empty_set_ind : forall (P : Empty_set -> Prop) (e : Empty_set), P e] *)
(** %\smallskip{}%In other words, any predicate over values from the empty set holds vacuously of every such element. In the last proof, we chose the predicate [(fun _ : Empty_set => 2 + 2 = 5)].
We can also apply this get-out-of-jail-free card programmatically. Here is a lazy way of converting values of [Empty_set] to values of [unit]: *)
Definition e2u (e : Empty_set) : unit := match e with end.
(** We employ [match] pattern matching as in the last chapter. Since we match on a value whose type has no constructors, there is no need to provide any branches. It turns out that [Empty_set] is the Curry-Howard equivalent of [False]. As for why [Empty_set] starts with a capital letter and not a lowercase letter like [unit] does, we must refer the reader to the authors of the Coq standard library, to which we try to be faithful.
%\medskip%
Moving up the ladder of complexity, we can define the Booleans:%\index{Gallina terms!bool}\index{Gallina terms!true}\index{Gallina terms!false}% *)
Inductive bool : Set :=
| true
| false.
(** We can use less vacuous pattern matching to define Boolean negation.%\index{Gallina terms!negb}% *)
Definition negb (b : bool) : bool :=
match b with
| true => false
| false => true
end.
(** An alternative definition desugars to the above, thanks to an %\index{Gallina terms!if}%[if] notation overloaded to work with any inductive type that has exactly two constructors: *)
Definition negb' (b : bool) : bool :=
if b then false else true.
(** We might want to prove that [negb] is its own inverse operation. *)
Theorem negb_inverse : forall b : bool, negb (negb b) = b.
(* begin thide *)
destruct b.
(** After we case-analyze on [b], we are left with one subgoal for each constructor of [bool].
[[
2 subgoals
============================
negb (negb true) = true
subgoal 2 is
negb (negb false) = false
]]
The first subgoal follows by Coq's rules of computation, so we can dispatch it easily: *)
reflexivity.
(** Likewise for the second subgoal, so we can restart the proof and give a very compact justification.%\index{Vernacular commands!Restart}% *)
Restart.
destruct b; reflexivity.
Qed.
(* end thide *)
(** Another theorem about Booleans illustrates another useful tactic.%\index{tactics!discriminate}% *)
Theorem negb_ineq : forall b : bool, negb b <> b.
(* begin thide *)
destruct b; discriminate.
Qed.
(* end thide *)
(** The [discriminate] tactic is used to prove that two values of an inductive type are not equal, whenever the values are formed with different constructors. In this case, the different constructors are [true] and [false].
At this point, it is probably not hard to guess what the underlying induction principle for [bool] is. *)
Check bool_ind.
(** [bool_ind : forall P : bool -> Prop, P true -> P false -> forall b : bool, P b] *)
(** %\smallskip{}%That is, to prove that a property describes all [bool]s, prove that it describes both [true] and [false].
There is no interesting Curry-Howard analogue of [bool]. Of course, we can define such a type by replacing [Set] by [Prop] above, but the proposition we arrive at is not very useful. It is logically equivalent to [True], but it provides two indistinguishable primitive proofs, [true] and [false]. In the rest of the chapter, we will skip commenting on Curry-Howard versions of inductive definitions where such versions are not interesting. *)
(** * Simple Recursive Types *)
(** The natural numbers are the simplest common example of an inductive type that actually deserves the name.%\index{Gallina terms!nat}\index{Gallina terms!O}\index{Gallina terms!S}% *)
Inductive nat : Set :=
| O : nat
| S : nat -> nat.
(** The constructor [O] is zero, and [S] is the successor function, so that [0] is syntactic sugar for [O], [1] for [S O], [2] for [S (S O)], and so on.
Pattern matching works as we demonstrated in the last chapter:%\index{Gallina terms!pred}% *)
Definition isZero (n : nat) : bool :=
match n with
| O => true
| S _ => false
end.
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** We can prove theorems by case analysis with [destruct] as for simpler inductive types, but we can also now get into genuine inductive theorems. First, we will need a recursive function, to make things interesting.%\index{Gallina terms!plus}% *)
Fixpoint plus (n m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Recall that [Fixpoint] is Coq's mechanism for recursive function definitions. Some theorems about [plus] can be proved without induction. *)
Theorem O_plus_n : forall n : nat, plus O n = n.
(* begin thide *)
intro; reflexivity.
Qed.
(* end thide *)
(** Coq's computation rules automatically simplify the application of [plus], because unfolding the definition of [plus] gives us a [match] expression where the branch to be taken is obvious from syntax alone. If we just reverse the order of the arguments, though, this no longer works, and we need induction. *)
Theorem n_plus_O : forall n : nat, plus n O = n.
(* begin thide *)
induction n.
(** Our first subgoal is [plus O O = O], which _is_ trivial by computation. *)
reflexivity.
(** Our second subgoal requires more work and also demonstrates our first inductive hypothesis.
[[
n : nat
IHn : plus n O = n
============================
plus (S n) O = S n
]]
We can start out by using computation to simplify the goal as far as we can.%\index{tactics!simpl}% *)
simpl.
(** Now the conclusion is [S (plus n O) = S n]. Using our inductive hypothesis: *)
rewrite IHn.
(** %\noindent{}%...we get a trivial conclusion [S n = S n]. *)
reflexivity.
(** Not much really went on in this proof, so the [crush] tactic from the [CpdtTactics] module can prove this theorem automatically. *)
Restart.
induction n; crush.
Qed.
(* end thide *)
(** We can check out the induction principle at work here: *)
Check nat_ind.
(** %\vspace{-.15in}% [[
nat_ind : forall P : nat -> Prop,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
Each of the two cases of our last proof came from the type of one of the arguments to [nat_ind]. We chose [P] to be [(fun n : nat => plus n O = n)]. The first proof case corresponded to [P O] and the second case to [(forall n : nat, P n -> P (S n))]. The free variable [n] and inductive hypothesis [IHn] came from the argument types given here.
Since [nat] has a constructor that takes an argument, we may sometimes need to know that that constructor is injective.%\index{tactics!injection}\index{tactics!trivial}% *)
Theorem S_inj : forall n m : nat, S n = S m -> n = m.
(* begin thide *)
injection 1; trivial.
Qed.
(* end thide *)
(** The [injection] tactic refers to a premise by number, adding new equalities between the corresponding arguments of equated terms that are formed with the same constructor. We end up needing to prove [n = m -> n = m], so it is unsurprising that a tactic named [trivial] is able to finish the proof. This tactic attempts a variety of single proof steps, drawn from a user-specified database that we will later see how to extend.
There is also a very useful tactic called %\index{tactics!congruence}%[congruence] that can prove this theorem immediately. The [congruence] tactic generalizes [discriminate] and [injection], and it also adds reasoning about the general properties of equality, such as that a function returns equal results on equal arguments. That is, [congruence] is a%\index{theory of equality and uninterpreted functions}% _complete decision procedure for the theory of equality and uninterpreted functions_, plus some smarts about inductive types.
%\medskip%
We can define a type of lists of natural numbers. *)
Inductive nat_list : Set :=
| NNil : nat_list
| NCons : nat -> nat_list -> nat_list.
(** Recursive definitions over [nat_list] are straightforward extensions of what we have seen before. *)
Fixpoint nlength (ls : nat_list) : nat :=
match ls with
| NNil => O
| NCons _ ls' => S (nlength ls')
end.
Fixpoint napp (ls1 ls2 : nat_list) : nat_list :=
match ls1 with
| NNil => ls2
| NCons n ls1' => NCons n (napp ls1' ls2)
end.
(** Inductive theorem proving can again be automated quite effectively. *)
Theorem nlength_napp : forall ls1 ls2 : nat_list, nlength (napp ls1 ls2)
= plus (nlength ls1) (nlength ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
Check nat_list_ind.
(** %\vspace{-.15in}% [[
nat_list_ind
: forall P : nat_list -> Prop,
P NNil ->
(forall (n : nat) (n0 : nat_list), P n0 -> P (NCons n n0)) ->
forall n : nat_list, P n
]]
%\medskip%
In general, we can implement any "tree" type as an inductive type. For example, here are binary trees of naturals. *)
Inductive nat_btree : Set :=
| NLeaf : nat_btree
| NNode : nat_btree -> nat -> nat_btree -> nat_btree.
(** Here are two functions whose intuitive explanations are not so important. The first one computes the size of a tree, and the second performs some sort of splicing of one tree into the leftmost available leaf node of another. *)
Fixpoint nsize (tr : nat_btree) : nat :=
match tr with
| NLeaf => S O
| NNode tr1 _ tr2 => plus (nsize tr1) (nsize tr2)
end.
Fixpoint nsplice (tr1 tr2 : nat_btree) : nat_btree :=
match tr1 with
| NLeaf => NNode tr2 O NLeaf
| NNode tr1' n tr2' => NNode (nsplice tr1' tr2) n tr2'
end.
Theorem plus_assoc : forall n1 n2 n3 : nat, plus (plus n1 n2) n3 = plus n1 (plus n2 n3).
(* begin thide *)
induction n1; crush.
Qed.
(* end thide *)
Theorem nsize_nsplice : forall tr1 tr2 : nat_btree, nsize (nsplice tr1 tr2)
= plus (nsize tr2) (nsize tr1).
(* begin thide *)
Hint Rewrite n_plus_O plus_assoc.
induction tr1; crush.
Qed.
(* end thide *)
(** It is convenient that these proofs go through so easily, but it is still useful to look into the details of what happened, by checking the statement of the tree induction principle. *)
Check nat_btree_ind.
(** %\vspace{-.15in}% [[
nat_btree_ind
: forall P : nat_btree -> Prop,
P NLeaf ->
(forall n : nat_btree,
P n -> forall (n0 : nat) (n1 : nat_btree), P n1 -> P (NNode n n0 n1)) ->
forall n : nat_btree, P n
]]
We have the usual two cases, one for each constructor of [nat_btree]. *)
(** * Parameterized Types *)
(** We can also define %\index{polymorphism}%polymorphic inductive types, as with algebraic datatypes in Haskell and ML.%\index{Gallina terms!list}\index{Gallina terms!Nil}\index{Gallina terms!Cons}\index{Gallina terms!length}\index{Gallina terms!app}% *)
Inductive list (T : Set) : Set :=
| Nil : list T
| Cons : T -> list T -> list T.
Fixpoint length T (ls : list T) : nat :=
match ls with
| Nil => O
| Cons _ ls' => S (length ls')
end.
Fixpoint app T (ls1 ls2 : list T) : list T :=
match ls1 with
| Nil => ls2
| Cons x ls1' => Cons x (app ls1' ls2)
end.
Theorem length_app : forall T (ls1 ls2 : list T), length (app ls1 ls2)
= plus (length ls1) (length ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
(** There is a useful shorthand for writing many definitions that share the same parameter, based on Coq's%\index{sections}\index{Vernacular commands!Section}\index{Vernacular commands!Variable}% _section_ mechanism. The following block of code is equivalent to the above: *)
(* begin hide *)
Reset list.
(* end hide *)
Section list.
Variable T : Set.
Inductive list : Set :=
| Nil : list
| Cons : T -> list -> list.
Fixpoint length (ls : list) : nat :=
match ls with
| Nil => O
| Cons _ ls' => S (length ls')
end.
Fixpoint app (ls1 ls2 : list) : list :=
match ls1 with
| Nil => ls2
| Cons x ls1' => Cons x (app ls1' ls2)
end.
Theorem length_app : forall ls1 ls2 : list, length (app ls1 ls2)
= plus (length ls1) (length ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
End list.
Implicit Arguments Nil [T].
(** After we end the section, the [Variable]s we used are added as extra function parameters for each defined identifier, as needed. With an [Implicit Arguments]%~\index{Vernacular commands!Implicit Arguments}% command, we ask that [T] be inferred when we use [Nil]; Coq's heuristics already decided to apply a similar policy to [Cons], because of the [Set Implicit Arguments]%~\index{Vernacular commands!Set Implicit Arguments}% command elided at the beginning of this chapter. We verify that our definitions have been saved properly using the [Print] command, a cousin of [Check] which shows the definition of a symbol, rather than just its type. *)
Print list.
(** %\vspace{-.15in}% [[
Inductive list (T : Set) : Set :=
Nil : list T | Cons : T -> list T -> list T
]]
The final definition is the same as what we wrote manually before. The other elements of the section are altered similarly, turning out exactly as they were before, though we managed to write their definitions more succinctly. *)
Check length.
(** %\vspace{-.15in}% [[
length
: forall T : Set, list T -> nat
]]
The parameter [T] is treated as a new argument to the induction principle, too. *)
Check list_ind.
(** %\vspace{-.15in}% [[
list_ind
: forall (T : Set) (P : list T -> Prop),
P (Nil T) ->
(forall (t : T) (l : list T), P l -> P (Cons t l)) ->
forall l : list T, P l
]]
Thus, despite a very real sense in which the type [T] is an argument to the constructor [Cons], the inductive case in the type of [list_ind] (i.e., the third line of the type) includes no quantifier for [T], even though all of the other arguments are quantified explicitly. Parameters in other inductive definitions are treated similarly in stating induction principles. *)
(** * Mutually Inductive Types *)
(** We can define inductive types that refer to each other: *)
Inductive even_list : Set :=
| ENil : even_list
| ECons : nat -> odd_list -> even_list
with odd_list : Set :=
| OCons : nat -> even_list -> odd_list.
Fixpoint elength (el : even_list) : nat :=
match el with
| ENil => O
| ECons _ ol => S (olength ol)
end
with olength (ol : odd_list) : nat :=
match ol with
| OCons _ el => S (elength el)
end.
Fixpoint eapp (el1 el2 : even_list) : even_list :=
match el1 with
| ENil => el2
| ECons n ol => ECons n (oapp ol el2)
end
with oapp (ol : odd_list) (el : even_list) : odd_list :=
match ol with
| OCons n el' => OCons n (eapp el' el)
end.
(** Everything is going roughly the same as in past examples, until we try to prove a theorem similar to those that came before. *)
Theorem elength_eapp : forall el1 el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2).
(* begin thide *)
induction el1; crush.
(** One goal remains: [[
n : nat
o : odd_list
el2 : even_list
============================
S (olength (oapp o el2)) = S (plus (olength o) (elength el2))
]]
We have no induction hypothesis, so we cannot prove this goal without starting another induction, which would reach a similar point, sending us into a futile infinite chain of inductions. The problem is that Coq's generation of [T_ind] principles is incomplete. We only get non-mutual induction principles generated by default. *)
Abort.
Check even_list_ind.
(** %\vspace{-.15in}% [[
even_list_ind
: forall P : even_list -> Prop,
P ENil ->
(forall (n : nat) (o : odd_list), P (ECons n o)) ->
forall e : even_list, P e
]]
We see that no inductive hypotheses are included anywhere in the type. To get them, we must ask for mutual principles as we need them, using the %\index{Vernacular commands!Scheme}%[Scheme] command. *)
Scheme even_list_mut := Induction for even_list Sort Prop
with odd_list_mut := Induction for odd_list Sort Prop.
(** This invocation of [Scheme] asks for the creation of induction principles [even_list_mut] for the type [even_list] and [odd_list_mut] for the type [odd_list]. The [Induction] keyword says we want standard induction schemes, since [Scheme] supports more exotic choices. Finally, [Sort Prop] establishes that we really want induction schemes, not recursion schemes, which are the same according to Curry-Howard, save for the [Prop]/[Set] distinction. *)
Check even_list_mut.
(** %\vspace{-.15in}% [[
even_list_mut
: forall (P : even_list -> Prop) (P0 : odd_list -> Prop),
P ENil ->
(forall (n : nat) (o : odd_list), P0 o -> P (ECons n o)) ->
(forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) ->
forall e : even_list, P e
]]
This is the principle we wanted in the first place.
The [Scheme] command is for asking Coq to generate particular induction schemes that are mutual among a set of inductive types (possibly only one such type, in which case we get a normal induction principle). In a sense, it generalizes the induction scheme generation that goes on automatically for each inductive definition. Future Coq versions might make that automatic generation smarter, so that [Scheme] is needed in fewer places. In a few sections, we will see how induction principles are derived theorems in Coq, so that there is not actually any need to build in _any_ automatic scheme generation.
There is one more wrinkle left in using the [even_list_mut] induction principle: the [induction] tactic will not apply it for us automatically. It will be helpful to look at how to prove one of our past examples without using [induction], so that we can then generalize the technique to mutual inductive types.%\index{tactics!apply}% *)
Theorem n_plus_O' : forall n : nat, plus n O = n.
apply nat_ind.
(** Here we use [apply], which is one of the most essential basic tactics. When we are trying to prove fact [P], and when [thm] is a theorem whose conclusion can be made to match [P] by proper choice of quantified variable values, the invocation [apply thm] will replace the current goal with one new goal for each premise of [thm].
This use of [apply] may seem a bit _too_ magical. To better see what is going on, we use a variant where we partially apply the theorem [nat_ind] to give an explicit value for the predicate that gives our induction hypothesis. *)
Undo.
apply (nat_ind (fun n => plus n O = n)); crush.
Qed.
(** From this example, we can see that [induction] is not magic. It only does some bookkeeping for us to make it easy to apply a theorem, which we can do directly with the [apply] tactic.
This technique generalizes to our mutual example: *)
Theorem elength_eapp : forall el1 el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2).
apply (even_list_mut
(fun el1 : even_list => forall el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2))
(fun ol : odd_list => forall el : even_list,
olength (oapp ol el) = plus (olength ol) (elength el))); crush.
Qed.
(* end thide *)
(** We simply need to specify two predicates, one for each of the mutually inductive types. In general, it is not a good idea to assume that a proof assistant can infer extra predicates, so this way of applying mutual induction is about as straightforward as we may hope for. *)
(** * Reflexive Types *)
(** A kind of inductive type called a _reflexive type_ includes at least one constructor that takes as an argument _a function returning the same type we are defining_. One very useful class of examples is in modeling variable binders. Our example will be an encoding of the syntax of first-order logic. Since the idea of syntactic encodings of logic may require a bit of acclimation, let us first consider a simpler formula type for a subset of propositional logic. We are not yet using a reflexive type, but later we will extend the example reflexively. *)
Inductive pformula : Set :=
| Truth : pformula
| Falsehood : pformula
| Conjunction : pformula -> pformula -> pformula.
(* begin hide *)
(* begin thide *)
Definition prod' := prod.
(* end thide *)
(* end hide *)
(** A key distinction here is between, for instance, the _syntax_ [Truth] and its _semantics_ [True]. We can make the semantics explicit with a recursive function. This function uses the infix operator %\index{Gallina operators!/\textbackslash}%[/\], which desugars to instances of the type family %\index{Gallina terms!and}%[and] from the standard library. The family [and] implements conjunction, the [Prop] Curry-Howard analogue of the usual pair type from functional programming (which is the type family %\index{Gallina terms!prod}%[prod] in Coq's standard library). *)
Fixpoint pformulaDenote (f : pformula) : Prop :=
match f with
| Truth => True
| Falsehood => False
| Conjunction f1 f2 => pformulaDenote f1 /\ pformulaDenote f2
end.
(** This is just a warm-up that does not use reflexive types, the new feature we mean to introduce. When we set our sights on first-order logic instead, it becomes very handy to give constructors recursive arguments that are functions. *)
Inductive formula : Set :=
| Eq : nat -> nat -> formula
| And : formula -> formula -> formula
| Forall : (nat -> formula) -> formula.
(** Our kinds of formulas are equalities between naturals, conjunction, and universal quantification over natural numbers. We avoid needing to include a notion of "variables" in our type, by using Coq functions to encode the syntax of quantification. For instance, here is the encoding of [forall x : nat, x = x]:%\index{Vernacular commands!Example}% *)
Example forall_refl : formula := Forall (fun x => Eq x x).
(** We can write recursive functions over reflexive types quite naturally. Here is one translating our formulas into native Coq propositions. *)
Fixpoint formulaDenote (f : formula) : Prop :=
match f with
| Eq n1 n2 => n1 = n2
| And f1 f2 => formulaDenote f1 /\ formulaDenote f2
| Forall f' => forall n : nat, formulaDenote (f' n)
end.
(** We can also encode a trivial formula transformation that swaps the order of equality and conjunction operands. *)
Fixpoint swapper (f : formula) : formula :=
match f with
| Eq n1 n2 => Eq n2 n1
| And f1 f2 => And (swapper f2) (swapper f1)
| Forall f' => Forall (fun n => swapper (f' n))
end.
(** It is helpful to prove that this transformation does not make true formulas false. *)
Theorem swapper_preserves_truth : forall f, formulaDenote f -> formulaDenote (swapper f).
(* begin thide *)
induction f; crush.
Qed.
(* end thide *)
(** We can take a look at the induction principle behind this proof. *)
Check formula_ind.
(** %\vspace{-.15in}% [[
formula_ind
: forall P : formula -> Prop,
(forall n n0 : nat, P (Eq n n0)) ->
(forall f0 : formula,
P f0 -> forall f1 : formula, P f1 -> P (And f0 f1)) ->
(forall f1 : nat -> formula,
(forall n : nat, P (f1 n)) -> P (Forall f1)) ->
forall f2 : formula, P f2
]]
Focusing on the [Forall] case, which comes third, we see that we are allowed to assume that the theorem holds _for any application of the argument function [f1]_. That is, Coq induction principles do not follow a simple rule that the textual representations of induction variables must get shorter in appeals to induction hypotheses. Luckily for us, the people behind the metatheory of Coq have verified that this flexibility does not introduce unsoundness.
%\medskip%
Up to this point, we have seen how to encode in Coq more and more of what is possible with algebraic datatypes in %\index{Haskell}%Haskell and %\index{ML}%ML. This may have given the inaccurate impression that inductive types are a strict extension of algebraic datatypes. In fact, Coq must rule out some types allowed by Haskell and ML, for reasons of soundness. Reflexive types provide our first good example of such a case; only some of them are legal.
Given our last example of an inductive type, many readers are probably eager to try encoding the syntax of %\index{lambda calculus}%lambda calculus. Indeed, the function-based representation technique that we just used, called%\index{higher-order abstract syntax}\index{HOAS|see{higher-order abstract syntax}}% _higher-order abstract syntax_ (HOAS)%~\cite{HOAS}%, is the representation of choice for lambda calculi in %\index{Twelf}%Twelf and in many applications implemented in Haskell and ML. Let us try to import that choice to Coq: *)
(* begin hide *)
(* begin thide *)
Inductive term : Set := App | Abs.
Reset term.
Definition uhoh := O.
(* end thide *)
(* end hide *)
(** [[
Inductive term : Set :=
| App : term -> term -> term
| Abs : (term -> term) -> term.
]]
<<
Error: Non strictly positive occurrence of "term" in "(term -> term) -> term"
>>
We have run afoul of the%\index{strict positivity requirement}\index{positivity requirement}% _strict positivity requirement_ for inductive definitions, which says that the type being defined may not occur to the left of an arrow in the type of a constructor argument. It is important that the type of a constructor is viewed in terms of a series of arguments and a result, since obviously we need recursive occurrences to the lefts of the outermost arrows if we are to have recursive occurrences at all. Our candidate definition above violates the positivity requirement because it involves an argument of type [term -> term], where the type [term] that we are defining appears to the left of an arrow. The candidate type of [App] is fine, however, since every occurrence of [term] is either a constructor argument or the final result type.
Why must Coq enforce this restriction? Imagine that our last definition had been accepted, allowing us to write this function:
%\vspace{-.15in}%[[
Definition uhoh (t : term) : term :=
match t with
| Abs f => f t
| _ => t
end.
]]
Using an informal idea of Coq's semantics, it is easy to verify that the application [uhoh (Abs uhoh)] will run forever. This would be a mere curiosity in OCaml and Haskell, where non-termination is commonplace, though the fact that we have a non-terminating program without explicit recursive function definitions is unusual.
%\index{termination checking}%For Coq, however, this would be a disaster. The possibility of writing such a function would destroy all our confidence that proving a theorem means anything. Since Coq combines programs and proofs in one language, we would be able to prove every theorem with an infinite loop.
Nonetheless, the basic insight of HOAS is a very useful one, and there are ways to realize most benefits of HOAS in Coq. We will study a particular technique of this kind in the final chapter, on programming language syntax and semantics. *)
(** * An Interlude on Induction Principles *)
(** As we have emphasized a few times already, Coq proofs are actually programs, written in the same language we have been using in our examples all along. We can get a first sense of what this means by taking a look at the definitions of some of the %\index{induction principles}%induction principles we have used. A close look at the details here will help us construct induction principles manually, which we will see is necessary for some more advanced inductive definitions. *)
Print nat_ind.
(** %\vspace{-.15in}%[[
nat_ind =
fun P : nat -> Prop => nat_rect P
: forall P : nat -> Prop,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
We see that this induction principle is defined in terms of a more general principle, [nat_rect]. The <<rec>> stands for "recursion principle," and the <<t>> at the end stands for [Type]. *)
Check nat_rect.
(** %\vspace{-.15in}% [[
nat_rect
: forall P : nat -> Type,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
The principle [nat_rect] gives [P] type [nat -> Type] instead of [nat -> Prop]. This [Type] is another universe, like [Set] and [Prop]. In fact, it is a common supertype of both. Later on, we will discuss exactly what the significances of the different universes are. For now, it is just important that we can use [Type] as a sort of meta-universe that may turn out to be either [Set] or [Prop]. We can see the symmetry inherent in the subtyping relationship by printing the definition of another principle that was generated for [nat] automatically: *)
Print nat_rec.
(** %\vspace{-.15in}%[[
nat_rec =
fun P : nat -> Set => nat_rect P
: forall P : nat -> Set,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
This is identical to the definition for [nat_ind], except that we have substituted [Set] for [Prop]. For most inductive types [T], then, we get not just induction principles [T_ind], but also %\index{recursion principles}%recursion principles [T_rec]. We can use [T_rec] to write recursive definitions without explicit [Fixpoint] recursion. For instance, the following two definitions are equivalent: *)
Fixpoint plus_recursive (n : nat) : nat -> nat :=
match n with
| O => fun m => m
| S n' => fun m => S (plus_recursive n' m)
end.
Definition plus_rec : nat -> nat -> nat :=
nat_rec (fun _ : nat => nat -> nat) (fun m => m) (fun _ r m => S (r m)).
Theorem plus_equivalent : plus_recursive = plus_rec.
reflexivity.
Qed.
(** Going even further down the rabbit hole, [nat_rect] itself is not even a primitive. It is a functional program that we can write manually. *)
Print nat_rect.
(** %\vspace{-.15in}%[[
nat_rect =
fun (P : nat -> Type) (f : P O) (f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n as n0 return (P n0) with
| O => f
| S n0 => f0 n0 (F n0)
end
: forall P : nat -> Type,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
The only new wrinkles here are, first, an anonymous recursive function definition, using the %\index{Gallina terms!fix}%[fix] keyword of Gallina (which is like [fun] with recursion supported); and, second, the annotations on the [match] expression. This is a%\index{dependent pattern matching}% _dependently typed_ pattern match, because the _type_ of the expression depends on the _value_ being matched on. We will meet more involved examples later, especially in Part II of the book.
%\index{type inference}%Type inference for dependent pattern matching is undecidable, which can be proved by reduction from %\index{higher-order unification}%higher-order unification%~\cite{HOU}%. Thus, we often find ourselves needing to annotate our programs in a way that explains dependencies to the type checker. In the example of [nat_rect], we have an %\index{Gallina terms!as}%[as] clause, which binds a name for the discriminee; and a %\index{Gallina terms!return}%[return] clause, which gives a way to compute the [match] result type as a function of the discriminee.
To prove that [nat_rect] is nothing special, we can reimplement it manually. *)
Fixpoint nat_rect' (P : nat -> Type)
(HO : P O)
(HS : forall n, P n -> P (S n)) (n : nat) :=
match n return P n with
| O => HO
| S n' => HS n' (nat_rect' P HO HS n')
end.
(** We can understand the definition of [nat_rect] better by reimplementing [nat_ind] using sections. *)
Section nat_ind'.
(** First, we have the property of natural numbers that we aim to prove. *)
Variable P : nat -> Prop.
(** Then we require a proof of the [O] case, which we declare with the command %\index{Vernacular commands!Hypothesis}%[Hypothesis], which is a synonym for [Variable] that, by convention, is used for variables whose types are propositions. *)
Hypothesis O_case : P O.
(** Next is a proof of the [S] case, which may assume an inductive hypothesis. *)
Hypothesis S_case : forall n : nat, P n -> P (S n).
(** Finally, we define a recursive function to tie the pieces together. *)
Fixpoint nat_ind' (n : nat) : P n :=
match n with
| O => O_case
| S n' => S_case (nat_ind' n')
end.
End nat_ind'.
(** Closing the section adds the [Variable]s and [Hypothesis]es as new [fun]-bound arguments to [nat_ind'], and, modulo the use of [Prop] instead of [Type], we end up with the exact same definition that was generated automatically for [nat_rect].
%\medskip%
We can also examine the definition of [even_list_mut], which we generated with [Scheme] for a mutually recursive type. *)
Print even_list_mut.
(** %\vspace{-.15in}%[[
even_list_mut =
fun (P : even_list -> Prop) (P0 : odd_list -> Prop)
(f : P ENil) (f0 : forall (n : nat) (o : odd_list), P0 o -> P (ECons n o))
(f1 : forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) =>
fix F (e : even_list) : P e :=
match e as e0 return (P e0) with
| ENil => f
| ECons n o => f0 n o (F0 o)
end
with F0 (o : odd_list) : P0 o :=
match o as o0 return (P0 o0) with
| OCons n e => f1 n e (F e)
end
for F
: forall (P : even_list -> Prop) (P0 : odd_list -> Prop),
P ENil ->
(forall (n : nat) (o : odd_list), P0 o -> P (ECons n o)) ->
(forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) ->
forall e : even_list, P e
]]
We see a mutually recursive [fix], with the different functions separated by %\index{Gallina terms!with}%[with] in the same way that they would be separated by <<and>> in ML. A final %\index{Gallina terms!for}%[for] clause identifies which of the mutually recursive functions should be the final value of the [fix] expression. Using this definition as a template, we can reimplement [even_list_mut] directly. *)
Section even_list_mut'.
(** First, we need the properties that we are proving. *)
Variable Peven : even_list -> Prop.
Variable Podd : odd_list -> Prop.
(** Next, we need proofs of the three cases. *)
Hypothesis ENil_case : Peven ENil.
Hypothesis ECons_case : forall (n : nat) (o : odd_list), Podd o -> Peven (ECons n o).
Hypothesis OCons_case : forall (n : nat) (e : even_list), Peven e -> Podd (OCons n e).
(** Finally, we define the recursive functions. *)
Fixpoint even_list_mut' (e : even_list) : Peven e :=
match e with
| ENil => ENil_case
| ECons n o => ECons_case n (odd_list_mut' o)
end
with odd_list_mut' (o : odd_list) : Podd o :=
match o with
| OCons n e => OCons_case n (even_list_mut' e)
end.
End even_list_mut'.
(** Even induction principles for reflexive types are easy to implement directly. For our [formula] type, we can use a recursive definition much like those we wrote above. *)
Section formula_ind'.
Variable P : formula -> Prop.
Hypothesis Eq_case : forall n1 n2 : nat, P (Eq n1 n2).
Hypothesis And_case : forall f1 f2 : formula,
P f1 -> P f2 -> P (And f1 f2).
Hypothesis Forall_case : forall f : nat -> formula,
(forall n : nat, P (f n)) -> P (Forall f).
Fixpoint formula_ind' (f : formula) : P f :=
match f with
| Eq n1 n2 => Eq_case n1 n2
| And f1 f2 => And_case (formula_ind' f1) (formula_ind' f2)
| Forall f' => Forall_case f' (fun n => formula_ind' (f' n))
end.
End formula_ind'.
(** It is apparent that induction principle implementations involve some tedium but not terribly much creativity. *)
(** * Nested Inductive Types *)
(** Suppose we want to extend our earlier type of binary trees to trees with arbitrary finite branching. We can use lists to give a simple definition. *)
Inductive nat_tree : Set :=
| NNode' : nat -> list nat_tree -> nat_tree.
(** This is an example of a%\index{nested inductive type}% _nested_ inductive type definition, because we use the type we are defining as an argument to a parameterized type family. Coq will not allow all such definitions; it effectively pretends that we are defining [nat_tree] mutually with a version of [list] specialized to [nat_tree], checking that the resulting expanded definition satisfies the usual rules. For instance, if we replaced [list] with a type family that used its parameter as a function argument, then the definition would be rejected as violating the positivity restriction.
As we encountered with mutual inductive types, we find that the automatically generated induction principle for [nat_tree] is too weak. *)
(* begin hide *)
(* begin thide *)
Check Forall.
(* end thide *)
(* end hide *)
Check nat_tree_ind.
(** %\vspace{-.15in}% [[
nat_tree_ind
: forall P : nat_tree -> Prop,
(forall (n : nat) (l : list nat_tree), P (NNode' n l)) ->
forall n : nat_tree, P n
]]
There is no command like [Scheme] that will implement an improved principle for us. In general, it takes creativity to figure out _good_ ways to incorporate nested uses of different type families. Now that we know how to implement induction principles manually, we are in a position to apply just such creativity to this problem.
Many induction principles for types with nested used of [list] could benefit from a unified predicate capturing the idea that some property holds of every element in a list. By defining this generic predicate once, we facilitate reuse of library theorems about it. (Here, we are actually duplicating the standard library's [Forall] predicate, with a different implementation, for didactic purposes.) *)
Section All.
Variable T : Set.
Variable P : T -> Prop.
Fixpoint All (ls : list T) : Prop :=
match ls with
| Nil => True
| Cons h t => P h /\ All t
end.
End All.
(** It will be useful to review the definitions of [True] and [/\], since we will want to write manual proofs of them below. *)
Print True.
(** %\vspace{-.15in}%[[
Inductive True : Prop := I : True
]]
That is, [True] is a proposition with exactly one proof, [I], which we may always supply trivially.
Finding the definition of [/\] takes a little more work. Coq supports user registration of arbitrary parsing rules, and it is such a rule that is letting us write [/\] instead of an application of some inductive type family. We can find the underlying inductive type with the %\index{Vernacular commands!Locate}%[Locate] command, whose argument may be a parsing token.%\index{Gallina terms!and}% *)
Locate "/\".
(** %\vspace{-.15in}%[[
"A /\ B" := and A B : type_scope (default interpretation)
]]
*)
Print and.
(** %\vspace{-.15in}%[[
Inductive and (A : Prop) (B : Prop) : Prop := conj : A -> B -> A /\ B
]]
%\vspace{-.1in}%
<<
For conj: Arguments A, B are implicit
>>
In addition to the definition of [and] itself, we get information on %\index{implicit arguments}%implicit arguments (and some other information that we omit here). The implicit argument information tells us that we build a proof of a conjunction by calling the constructor [conj] on proofs of the conjuncts, with no need to include the types of those proofs as explicit arguments.
%\medskip%
Now we create a section for our induction principle, following the same basic plan as in the previous section of this chapter. *)
Section nat_tree_ind'.
Variable P : nat_tree -> Prop.
Hypothesis NNode'_case : forall (n : nat) (ls : list nat_tree),
All P ls -> P (NNode' n ls).
(* begin hide *)
(* begin thide *)
Definition list_nat_tree_ind := O.
(* end thide *)
(* end hide *)
(** A first attempt at writing the induction principle itself follows the intuition that nested inductive type definitions are expanded into mutual inductive definitions.
%\vspace{-.15in}%[[
Fixpoint nat_tree_ind' (tr : nat_tree) : P tr :=
match tr with
| NNode' n ls => NNode'_case n ls (list_nat_tree_ind ls)
end
with list_nat_tree_ind (ls : list nat_tree) : All P ls :=
match ls with
| Nil => I
| Cons tr rest => conj (nat_tree_ind' tr) (list_nat_tree_ind rest)
end.
]]
Coq rejects this definition, saying
<<
Recursive call to nat_tree_ind' has principal argument equal to "tr"
instead of rest.
>>
There is no deep theoretical reason why this program should be rejected; Coq applies incomplete termination-checking heuristics, and it is necessary to learn a few of the most important rules. The term "nested inductive type" hints at the solution to this particular problem. Just as mutually inductive types require mutually recursive induction principles, nested types require nested recursion. *)
Fixpoint nat_tree_ind' (tr : nat_tree) : P tr :=
match tr with
| NNode' n ls => NNode'_case n ls
((fix list_nat_tree_ind (ls : list nat_tree) : All P ls :=
match ls with
| Nil => I
| Cons tr' rest => conj (nat_tree_ind' tr') (list_nat_tree_ind rest)
end) ls)
end.
(** We include an anonymous [fix] version of [list_nat_tree_ind] that is literally _nested_ inside the definition of the recursive function corresponding to the inductive definition that had the nested use of [list]. *)
End nat_tree_ind'.
(** We can try our induction principle out by defining some recursive functions on [nat_tree] and proving a theorem about them. First, we define some helper functions that operate on lists. *)
Section map.
Variables T T' : Set.
Variable F : T -> T'.
Fixpoint map (ls : list T) : list T' :=
match ls with
| Nil => Nil
| Cons h t => Cons (F h) (map t)
end.
End map.
Fixpoint sum (ls : list nat) : nat :=
match ls with
| Nil => O
| Cons h t => plus h (sum t)
end.
(** Now we can define a size function over our trees. *)
Fixpoint ntsize (tr : nat_tree) : nat :=
match tr with
| NNode' _ trs => S (sum (map ntsize trs))
end.
(** Notice that Coq was smart enough to expand the definition of [map] to verify that we are using proper nested recursion, even through a use of a higher-order function. *)
Fixpoint ntsplice (tr1 tr2 : nat_tree) : nat_tree :=
match tr1 with
| NNode' n Nil => NNode' n (Cons tr2 Nil)
| NNode' n (Cons tr trs) => NNode' n (Cons (ntsplice tr tr2) trs)
end.
(** We have defined another arbitrary notion of tree splicing, similar to before, and we can prove an analogous theorem about its relationship with tree size. We start with a useful lemma about addition. *)
(* begin thide *)
Lemma plus_S : forall n1 n2 : nat,
plus n1 (S n2) = S (plus n1 n2).
induction n1; crush.
Qed.
(* end thide *)
(** Now we begin the proof of the theorem, adding the lemma [plus_S] as a hint. *)
Theorem ntsize_ntsplice : forall tr1 tr2 : nat_tree, ntsize (ntsplice tr1 tr2)
= plus (ntsize tr2) (ntsize tr1).
(* begin thide *)
Hint Rewrite plus_S.
(** We know that the standard induction principle is insufficient for the task, so we need to provide a %\index{tactics!using}%[using] clause for the [induction] tactic to specify our alternate principle. *)
induction tr1 using nat_tree_ind'; crush.
(** One subgoal remains: [[
n : nat
ls : list nat_tree
H : All
(fun tr1 : nat_tree =>
forall tr2 : nat_tree,
ntsize (ntsplice tr1 tr2) = plus (ntsize tr2) (ntsize tr1)) ls
tr2 : nat_tree
============================
ntsize
match ls with
| Nil => NNode' n (Cons tr2 Nil)
| Cons tr trs => NNode' n (Cons (ntsplice tr tr2) trs)
end = S (plus (ntsize tr2) (sum (map ntsize ls)))
]]
After a few moments of squinting at this goal, it becomes apparent that we need to do a case analysis on the structure of [ls]. The rest is routine. *)
destruct ls; crush.
(** We can go further in automating the proof by exploiting the hint mechanism.%\index{Vernacular commands!Hint Extern}% *)
Restart.
Hint Extern 1 (ntsize (match ?LS with Nil => _ | Cons _ _ => _ end) = _) =>
destruct LS; crush.
induction tr1 using nat_tree_ind'; crush.
Qed.
(* end thide *)
(** We will go into great detail on hints in a later chapter, but the only important thing to note here is that we register a pattern that describes a conclusion we expect to encounter during the proof. The pattern may contain unification variables, whose names are prefixed with question marks, and we may refer to those bound variables in a tactic that we ask to have run whenever the pattern matches.
The advantage of using the hint is not very clear here, because the original proof was so short. However, the hint has fundamentally improved the readability of our proof. Before, the proof referred to the local variable [ls], which has an automatically generated name. To a human reading the proof script without stepping through it interactively, it was not clear where [ls] came from. The hint explains to the reader the process for choosing which variables to case analyze, and the hint can continue working even if the rest of the proof structure changes significantly. *)
(** * Manual Proofs About Constructors *)
(** It can be useful to understand how tactics like %\index{tactics!discriminate}%[discriminate] and %\index{tactics!injection}%[injection] work, so it is worth stepping through a manual proof of each kind. We will start with a proof fit for [discriminate]. *)
Theorem true_neq_false : true <> false.
(* begin thide *)
(** We begin with the tactic %\index{tactics!red}%[red], which is short for "one step of reduction," to unfold the definition of logical negation. *)
red.
(** %\vspace{-.15in}%[[
============================
true = false -> False
]]
The negation is replaced with an implication of falsehood. We use the tactic %\index{tactics!intro}%[intro H] to change the assumption of the implication into a hypothesis named [H]. *)
intro H.
(** %\vspace{-.15in}%[[
H : true = false
============================
False
]]
This is the point in the proof where we apply some creativity. We define a function whose utility will become clear soon. *)
Definition toProp (b : bool) := if b then True else False.
(** It is worth recalling the difference between the lowercase and uppercase versions of truth and falsehood: [True] and [False] are logical propositions, while [true] and [false] are Boolean values that we can case-analyze. We have defined [toProp] such that our conclusion of [False] is computationally equivalent to [toProp false]. Thus, the %\index{tactics!change}%[change] tactic will let us change the conclusion to [toProp false]. The general form [change e] replaces the conclusion with [e], whenever Coq's built-in computation rules suffice to establish the equivalence of [e] with the original conclusion. *)
change (toProp false).
(** %\vspace{-.15in}%[[
H : true = false
============================
toProp false
]]
Now the righthand side of [H]'s equality appears in the conclusion, so we can rewrite, using the notation [<-] to request to replace the righthand side of the equality with the lefthand side.%\index{tactics!rewrite}% *)
rewrite <- H.
(** %\vspace{-.15in}%[[
H : true = false
============================
toProp true
]]
We are almost done. Just how close we are to done is revealed by computational simplification. *)
simpl.
(** %\vspace{-.15in}%[[
H : true = false
============================
True
]]
*)
trivial.
Qed.
(* end thide *)
(** I have no trivial automated version of this proof to suggest, beyond using [discriminate] or [congruence] in the first place.
%\medskip%
We can perform a similar manual proof of injectivity of the constructor [S]. I leave a walk-through of the details to curious readers who want to run the proof script interactively. *)
Theorem S_inj' : forall n m : nat, S n = S m -> n = m.
(* begin thide *)
intros n m H.
change (pred (S n) = pred (S m)).
rewrite H.
reflexivity.
Qed.
(* end thide *)
(** The key piece of creativity in this theorem comes in the use of the natural number predecessor function [pred]. Embodied in the implementation of [injection] is a generic recipe for writing such type-specific functions.
The examples in this section illustrate an important aspect of the design philosophy behind Coq. We could certainly design a Gallina replacement that built in rules for constructor discrimination and injectivity, but a simpler alternative is to include a few carefully chosen rules that enable the desired reasoning patterns and many others. A key benefit of this philosophy is that the complexity of proof checking is minimized, which bolsters our confidence that proved theorems are really true. *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_1_V
`define SKY130_FD_SC_MS__EINVN_1_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_1_V
|
`include "../../../rtl/verilog/gfx/gfx_wbm_read.v"
module wbm_r_bench();
// wishbone signals
reg clk_i; // master clock reg
reg rst_i; // synchronous active high reset
wire cyc_o; // cycle wire
wire stb_o; // strobe output
wire [ 2:0] cti_o; // cycle type id
wire [ 1:0] bte_o; // burst type extension
wire we_o; // write enable wire
wire [31:0] adr_o; // address wire
wire [ 3:0] sel_o; // byte select wires (only 32bits accesses are supported)
reg ack_i; // wishbone cycle acknowledge
reg err_i; // wishbone cycle error
reg [31:0] dat_i; // wishbone data in
wire sint_o; // non recoverable error, interrupt host
// Renderer stuff
reg read_request_i;
reg [31:2] texture_addr_i;
reg [3:0] texture_sel_i;
wire [31:0] texture_dat_o;
wire texture_data_ack;
initial begin
$dumpfile("wbm_r.vcd");
$dumpvars(0,wbm_r_bench);
// init values
ack_i = 0;
clk_i = 1;
rst_i = 1;
read_request_i = 0;
err_i = 0;
texture_sel_i = 4'hf;
dat_i = 0;
texture_addr_i = 0;
//timing
#4 rst_i =0;
#2 read_request_i = 1;
#2 read_request_i = 0;
// end sim
#100 $finish;
end
always begin
#1 ack_i = !ack_i & cyc_o;
end
always begin
#1 clk_i = ~clk_i;
end
gfx_wbm_read wbm_r(
// WB signals
.clk_i (clk_i),
.rst_i (rst_i),
.cyc_o (cyc_o),
.stb_o (stb_o),
.cti_o (cti_o),
.bte_o (bte_o),
.we_o (we_o),
.adr_o (adr_o),
.sel_o (sel_o),
.ack_i (ack_i),
.err_i (err_i),
.dat_i (dat_i),
.sint_o (sint_o),
// Control signals
.read_request_i (read_request_i),
.texture_addr_i (texture_addr_i),
.texture_sel_i (texture_sel_i),
.texture_dat_o (texture_dat_o),
.texture_data_ack (texture_data_ack)
);
endmodule
|
// soc_system_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2011-2012, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
//
// Ken Chapman - Xilinx Ltd.
//
// 30th April 2012 - Conversion from original VHDL version (30th April 2012).
// 30th July 2014 - Corrections to comment only.
//
// This reference design provides a simple UART communication example.
// Please see 'UART6_User_Guide_and_Reference_Designs_30Sept14.pdf' for more detailed
// descriptions.
//
// The code in this example is set to implement a 115200 baud rate when using a 50MHz
// clock. Whilst the design is presented as a working example for the XC6VLX240T-1FF1156
// device on the ML605 Evaluation Board (www.xilinx.com) it is a simple reference design
// that is easily adapted or incorporated into a design for use with any hardware platform.
//
//
//////////////////////////////////////////////////////////////////////////////////////////-
//
//
module uart6_ml605 ( input uart_rx,
input clk200_p,
input clk200_n,
output uart_tx );
//
///////////////////////////////////////////////////////////////////////////////////////////
// Signals
///////////////////////////////////////////////////////////////////////////////////////////
//
// Signals used to create 50MHz clock from 200MHz differential clock
//
wire clk200;
wire clk;
// Signals used to connect KCPSM6
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
reg [7:0] in_port;
wire [7:0] out_port;
wire [7:0] port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
wire interrupt_ack;
wire kcpsm6_sleep;
wire kcpsm6_reset;
wire rdl;
// Signals used to connect UART_TX6
wire [7:0] uart_tx_data_in;
wire write_to_uart_tx;
wire uart_tx_data_present;
wire uart_tx_half_full;
wire uart_tx_full;
reg uart_tx_reset;
// Signals used to connect UART_RX6
wire [7:0] uart_rx_data_out;
reg read_from_uart_rx;
wire uart_rx_data_present;
wire uart_rx_half_full;
wire uart_rx_full;
reg uart_rx_reset;
// Signals used to define baud rate
reg [4:0] baud_count;
reg en_16_x_baud;
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Start of circuit description
//
///////////////////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////////////////
// Create 50MHz clock from 200MHz differential clock
/////////////////////////////////////////////////////////////////////////////////////////
IBUFGDS diff_clk_buffer(
.I(clk200_p),
.IB(clk200_n),
.O(clk200));
// BUFR used to divide by 4 and create a regional clock
BUFR #(
.BUFR_DIVIDE("4"),
.SIM_DEVICE("VIRTEX6"))
clock_divide (
.I(clk200),
.O(clk),
.CE(1'b1),
.CLR(1'b0));
/////////////////////////////////////////////////////////////////////////////////////////
// Instantiate KCPSM6 and connect to program ROM
/////////////////////////////////////////////////////////////////////////////////////////
//
// The generics can be defined as required. In this case the 'hwbuild' value is used to
// define a version using the ASCII code for the desired letter.
//
kcpsm6 #(
.interrupt_vector (12'h7F0),
.scratch_pad_memory_size(64),
.hwbuild (8'h42)) // 42 hex is ASCII Character "B"
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
// Reset connected to JTAG Loader enabled Program Memory
assign kcpsm6_reset = rdl;
// Unused signals tied off until required.
assign kcpsm6_sleep = 1'b0;
assign interrupt = interrupt_ack;
// Development Program Memory
// JTAG Loader enabled for rapid code development.
uart_control #(
.C_FAMILY ("V6"),
.C_RAM_SIZE_KWORDS (2),
.C_JTAG_LOADER_ENABLE (1))
program_rom (
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Transmitter with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Write to buffer in UART Transmitter at port address 01 hex
//
uart_tx6 tx(
.data_in(uart_tx_data_in),
.en_16_x_baud(en_16_x_baud),
.serial_out(uart_tx),
.buffer_write(write_to_uart_tx),
.buffer_data_present(uart_tx_data_present),
.buffer_half_full(uart_tx_half_full ),
.buffer_full(uart_tx_full),
.buffer_reset(uart_tx_reset),
.clk(clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Receiver with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Read from buffer in UART Receiver at port address 01 hex.
//
// When KCPMS6 reads data from the receiver a pulse must be generated so that the
// FIFO buffer presents the next character to be read and updates the buffer flags.
//
uart_rx6 rx(
.serial_in(uart_rx),
.en_16_x_baud(en_16_x_baud ),
.data_out(uart_rx_data_out ),
.buffer_read(read_from_uart_rx ),
.buffer_data_present(uart_rx_data_present ),
.buffer_half_full(uart_rx_half_full ),
.buffer_full(uart_rx_full ),
.buffer_reset(uart_rx_reset ),
.clk(clk ));
//
/////////////////////////////////////////////////////////////////////////////////////////
// RS232 (UART) baud rate
/////////////////////////////////////////////////////////////////////////////////////////
//
// To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
// High at 1,843,200Hz which is every 27.13 cycles at 50MHz. In this implementation
// a pulse is generated every 27 cycles resulting is a baud rate of 115,741 baud which
// is only 0.5% high and well within limits.
//
always @ (posedge clk )
begin
if (baud_count == 5'b11010) begin // counts 27 states including zero
baud_count <= 5'b00000;
en_16_x_baud <= 1'b1; // single cycle enable pulse
end
else begin
baud_count <= baud_count + 5'b00001;
en_16_x_baud <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Input Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
// Two input ports are used with the UART macros. The first is used to monitor the flags
// on both the transmitter and receiver. The second is used to read the data from the
// receiver and generate the 'buffer_read' pulse.
//
always @ (posedge clk)
begin
case (port_id[0])
// Read UART status at port address 00 hex
1'b0 : in_port <= { 2'b00,
uart_rx_full,
uart_rx_half_full,
uart_rx_data_present,
uart_tx_full,
uart_tx_half_full,
uart_tx_data_present };
// Read UART_RX6 data at port address 01 hex
// (see 'buffer_read' pulse generation below)
1'b1 : in_port <= uart_rx_data_out;
default : in_port <= 8'bXXXXXXXX ;
endcase;
// Generate 'buffer_read' pulse following read from port address 01
if ((read_strobe == 1'b1) && (port_id[0] == 1'b1)) begin
read_from_uart_rx <= 1'b1;
end
else begin
read_from_uart_rx <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// In this simple example there is only one output port and that it involves writing
// directly to the FIFO buffer within 'uart_tx6'. As such the only requirements are to
// connect the 'out_port' to the transmitter macro and generate the write pulse.
//
assign uart_tx_data_in = out_port;
assign write_to_uart_tx = write_strobe & port_id[0];
//
/////////////////////////////////////////////////////////////////////////////////////////
// Constant-Optimised Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// One constant-optimised output port is used to facilitate resetting of the UART macros.
//
always @ (posedge clk)
begin
if (k_write_strobe == 1'b1) begin
if (port_id[0] == 1'b1) begin
uart_tx_reset <= out_port[0];
uart_rx_reset <= out_port[1];
end
end
end
/////////////////////////////////////////////////////////////////////////////////////////
endmodule
//
///////////////////////////////////////////////////////////////////////////////////////////
// END OF FILE uart6_ml605.v
///////////////////////////////////////////////////////////////////////////////////////////
//
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
// Date : Thu Jul 24 13:45:39 2014
// Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_stub.v
// Design : blk_mem_gen_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.1" *)
module blk_mem_gen_1(clka, wea, addra, dina, clkb, enb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[11:0],dina[7:0],clkb,enb,addrb[9:0],doutb[31:0]" */;
input clka;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
input clkb;
input enb;
input [9:0]addrb;
output [31:0]doutb;
endmodule
|
`include "defines.v"
module cpu(
input wire clk50,
input wire rst,
output wire[15:0] led_o,
output wire flash_flashByte_o,
output wire flash_flashVpen_o,
output wire flash_flashRP_o,
output wire flash_flashSTS_o,
output wire flash_flashEnable_o,
output wire flash_flashCE1_o,
output wire flash_flashCE2_o,
output wire flash_readEnable_o,
output wire flash_writeEnable_o,
output wire[22:0] flash_addr_o,
output wire[7:0] pc_output,
inout wire[15:0] flash_data_io,
output wire sram_sramEnable_o,
output wire sram_writeEnable_o,
output wire sram_readEnable_o,
output wire[21:0] sram_addr_o,
inout wire[31:0] sram_data_io,
input wire RxD,
output wire TxD
);
//reg
wire[31:0] reg_data1;
wire[31:0] reg_data2;
//hilo
wire[31:0] reg_dataHi;
wire[31:0] reg_dataLo;
//CP0
wire[31:0] cp0_data;
wire[31:0] cp0_Status;
wire[31:0] cp0_Index;
wire[31:0] cp0_EntryLo0;
wire[31:0] cp0_EntryLo1;
wire[31:0] cp0_EntryHi;
wire[31:0] cp0_Ebase;
wire[31:0] cp0_EPC;
wire cp0_timeInt;
//control
wire memcontrol_pauseRequest;
wire con_pauseControl = memcontrol_pauseRequest;
//sramcontrol
wire[21:0] sramcontrol_ramAddr;
wire sramcontrol_sramEnable;
wire sramcontrol_writeEnable;
wire sramcontrol_readEnable;
wire sramcontrol_busEnable;
wire[31:0] sramcontrol_writeData;
wire[31:0] sramcontrol_ramData;
//flashcontrol
wire flashcontrol_flashEnable;
wire flashcontrol_readEnable;
wire flashcontrol_writeEnable;
wire flashcontrol_busEnable;
wire[22:0] flashcontrol_ramAddr;
wire[15:0] flashcontrol_writeData;
wire flashcontrol_pauseRequest;
wire[31:0] flashcontrol_ramData;
//serialcontrol
wire[31:0] serialcontrol_ramData;
wire serialcontrol_serialInt;
//rom
wire[31:0] rom_ins;
//pc
wire[31:0] pc_insAddr;
//if_id
wire[31:0] if_id_insAddr;
wire[31:0] if_id_ins;
wire[3:0] if_id_exception;
wire[31:0] if_id_badVAddr;
wire if_id_insValid;
//id
wire[4:0] id_regReadAddr1;
wire[4:0] id_regReadAddr2;
wire id_regEnable1;
wire id_regEnable2;
wire id_CP0ReadEnable;
wire[4:0] id_CP0ReadAddr;
wire[31:0] id_operand1;
wire[31:0] id_operand2;
wire id_writeReg;
wire[4:0] id_writeRegAddr;
wire[4:0] id_aluOp;
wire id_writeRegHiLo;
wire id_branchEnable;
wire id_writeCP0;
wire[4:0] id_writeCP0Addr;
wire[31:0] id_branchAddr;
wire id_inDelaySlot;
wire id_nextInDelaySlot;
wire id_bubbleRequest;
wire[31:0] id_storeData;
wire[2:0] id_memOp;
wire[3:0] id_exception;
wire[31:0] id_insAddr;
wire[31:0] id_badVAddr;
//id_ex
wire[31:0] id_ex_operand1;
wire[31:0] id_ex_operand2;
wire id_ex_writeReg;
wire[4:0] id_ex_writeRegAddr;
wire[4:0] id_ex_aluOp;
wire id_ex_writeRegHiLo;
wire id_ex_writeCP0;
wire[4:0] id_ex_writeCP0Addr;
wire id_ex_inDelaySlot;
wire id_ex_nextInDelaySlot;
wire[31:0] id_ex_storeData;
wire[2:0] id_ex_memOp;
wire[31:0] id_ex_insAddr;
wire[3:0] id_ex_exception;
wire[31:0] id_ex_badVAddr;
wire id_ex_insValid;
//ex
wire[31:0] ex_writeData;
wire ex_writeReg;
wire[4:0] ex_writeRegAddr;
wire ex_writeRegHiLo;
wire ex_writeCP0;
wire[4:0] ex_writeCP0Addr;
wire[31:0] ex_writeDataHi;
wire[31:0] ex_writeDataLo;
wire[31:0] ex_storeData;
wire[2:0] ex_memOp;
wire ex_inDelaySlot;
wire[31:0] ex_insAddr;
wire[3:0] ex_exception;
wire[31:0] ex_badVAddr;
//ex_mem
wire[31:0] ex_mem_writeData;
wire ex_mem_writeReg;
wire[4:0] ex_mem_writeRegAddr;
wire ex_mem_writeRegHiLo;
wire[31:0] ex_mem_writeDataHi;
wire[31:0] ex_mem_writeDataLo;
wire ex_mem_writeCP0;
wire[4:0] ex_mem_writeCP0Addr;
wire[31:0] ex_mem_storeData;
wire[2:0] ex_mem_memOp;
wire ex_mem_inDelaySlot;
wire[31:0] ex_mem_insAddr;
wire[3:0] ex_mem_exception;
wire[31:0] ex_mem_badVAddr;
wire ex_mem_insValid;
assign led_o = ex_mem_insAddr[15:0];
assign pc_output = pc_insAddr[7:0];
//mem
wire[31:0] mem_writeData;
wire mem_writeReg;
wire[4:0] mem_writeRegAddr;
wire mem_writeRegHiLo;
wire[31:0] mem_writeDataHi;
wire[31:0] mem_writeDataLo;
wire mem_writeCP0;
wire[4:0] mem_writeCP0Addr;
wire[2:0] mem_memOp;
wire[31:0] mem_storeData;
wire[31:0] mem_memAddr;
wire mem_flush;
wire[31:0] mem_excAddr;
wire[3:0] mem_exception;
wire[31:0] mem_badVAddr;
wire[31:0] mem_insAddr;
wire mem_inDelaySlot;
//memcontrol
wire[2:0] memcontrol_ramOp;
wire[31:0] memcontrol_storeData;
wire[31:0] memcontrol_ramAddr;
wire[31:0] memcontrol_ramData;
wire[31:0] memcontrol_ins;
wire[3:0] memcontrol_exceptionMEM;
wire[3:0] memcontrol_exceptionIF;
wire[31:0] memcontrol_badVAddrIF;
//mmu
wire[2:0] mmu_sram_ramOp;
wire[31:0] mmu_sram_storeData;
wire[21:0] mmu_sram_ramAddr;
wire[15:0] mmu_rom_ramAddr;
wire[31:0] mmu_memData;
wire[3:0] mmu_exceptionMMU;
wire[2:0] mmu_serial_ramOp;
wire mmu_serial_mode;
wire[7:0] mmu_serial_storeData;
wire[2:0] mmu_flash_ramOp;
wire[22:0] mmu_flash_ramAddr;
wire[15:0] mmu_flash_storeData;
//mem_wb
wire[31:0] mem_wb_writeData;
wire mem_wb_writeReg;
wire[4:0] mem_wb_writeRegAddr;
wire mem_wb_writeRegHiLo;
wire[31:0] mem_wb_writeDataHi;
wire[31:0] mem_wb_writeDataLo;
wire mem_wb_writeCP0;
wire[4:0] mem_wb_writeCP0Addr;
wire[3:0] mem_wb_exception;
wire[31:0] mem_wb_insAddr;
wire[31:0] mem_wb_badVAddr;
wire mem_wb_inDelaySlot;
//Global 25MHz clock
reg clk25 = 0;
always @(posedge clk50) begin
clk25 <= ~clk25;
end
// reg clk12 = 0;
// always @(posedge clk25) begin
// clk12 <= ~clk12;
// end
reg clk = 0;
always @(posedge clk25) begin
clk <= ~clk;
end
// always @(*) begin
// clk <= clk50;
// end
//Global reset
wire nrst = ~rst;
//SRAM Bus
//Control
assign sram_sramEnable_o = ~sramcontrol_sramEnable;
assign sram_writeEnable_o = ~sramcontrol_writeEnable;
assign sram_readEnable_o = ~sramcontrol_readEnable;
assign sram_addr_o = sramcontrol_ramAddr;
//Write
assign sram_data_io = sramcontrol_busEnable ? sramcontrol_writeData : 32'bz;
//Read
reg[31:0] sram_readData;
always @(*) begin
sram_readData = sramcontrol_readEnable ? sram_data_io : `ZeroWord;
end
//Flash Bus
//Control
assign flash_flashByte_o = `Enable;
assign flash_flashVpen_o = `Enable;
assign flash_flashRP_o = `Enable;
assign flash_flashSTS_o = `Enable;
assign flash_flashCE1_o = `Disable;
assign flash_flashCE2_o = `Disable;
assign flash_flashEnable_o = ~flashcontrol_flashEnable;
assign flash_readEnable_o = ~flashcontrol_readEnable;
assign flash_writeEnable_o = ~flashcontrol_writeEnable;
assign flash_addr_o = flashcontrol_ramAddr;
//Write
assign flash_data_io = flashcontrol_busEnable ? flashcontrol_writeData : 16'bz;
//Read
reg[15:0] flash_readData;
always @(*) begin
flash_readData = flashcontrol_readEnable ? flash_data_io : `ZeroHalfWord;
end
registers Registers(
.clk(clk),
.rst(nrst),
.readAddr1_i(id_regReadAddr1),
.readEnable1_i(id_regEnable1),
.data1_o(reg_data1),
.readAddr2_i(id_regReadAddr2),
.readEnable2_i(id_regEnable2),
.data2_o(reg_data2),
.writeAddr_i(mem_wb_writeRegAddr),
.writeData_i(mem_wb_writeData),
.writeEnable_i(mem_wb_writeReg)
);
hilo HILO(
.clk(clk),
.rst(nrst),
.dataHi_o(reg_dataHi),
.dataLo_o(reg_dataLo),
.writeEnable_i(mem_wb_writeRegHiLo),
.writeDataHi_i(mem_wb_writeDataHi),
.writeDataLo_i(mem_wb_writeDataLo)
);
cp0 CP0(
.clk(clk),
.rst(nrst),
.pauseControl_i(con_pauseControl),
.exception_i(mem_wb_exception),
.readAddr_i(id_CP0ReadAddr),
.readEnable_i(id_CP0ReadEnable),
.data_o(cp0_data),
.writeAddr_i(mem_wb_writeCP0Addr),
.writeData_i(mem_wb_writeData),
.writeEnable_i(mem_wb_writeCP0),
.insAddr_i(mem_wb_insAddr),
.inDelaySlot_i(mem_wb_inDelaySlot),
.badVAddr_i(mem_wb_badVAddr),
.cp0_Status_o(cp0_Status),
.cp0_Index_o(cp0_Index),
.cp0_EntryLo0_o(cp0_EntryLo0),
.cp0_EntryLo1_o(cp0_EntryLo1),
.cp0_EntryHi_o(cp0_EntryHi),
.cp0_Ebase_o(cp0_Ebase),
.cp0_EPC_o(cp0_EPC),
.timeInt_o(cp0_timeInt)
);
memcontrol MemControl(
.clk(clk),
.rst(nrst),
.ramOp_i(mem_memOp),
.storeData_i(mem_storeData),
.ramAddr_i(mem_memAddr),
.insAddr_i(pc_insAddr),
.ramData_i(mmu_memData),
.exception_i(mmu_exceptionMMU),
.pauseRequest_i(flashcontrol_pauseRequest),
.pauseRequest_o(memcontrol_pauseRequest),
.ramOp_o(memcontrol_ramOp),
.storeData_o(memcontrol_storeData),
.ramAddr_o(memcontrol_ramAddr),
.ramData_o(memcontrol_ramData),
.ins_o(memcontrol_ins),
.exceptionMEM_o(memcontrol_exceptionMEM),
.exceptionIF_o(memcontrol_exceptionIF),
.badVAddrIF_o(memcontrol_badVAddrIF)
);
mmu MMU(
.clk(clk),
.rst(nrst),
.memOp_i(memcontrol_ramOp),
.storeData_i(memcontrol_storeData),
.memAddr_i(memcontrol_ramAddr),
.sram_ramData_i(sramcontrol_ramData),
.rom_ramData_i(rom_ins),
.flash_ramData_i(flashcontrol_ramData),
.serial_ramData_i(serialcontrol_ramData),
.cp0_Status_i(cp0_Status),
.cp0_Index_i(cp0_Index),
.cp0_EntryLo0_i(cp0_EntryLo0),
.cp0_EntryLo1_i(cp0_EntryLo1),
.cp0_EntryHi_i(cp0_EntryHi),
.exception_i(mem_wb_exception),
.sram_ramOp_o(mmu_sram_ramOp),
.sram_storeData_o(mmu_sram_storeData),
.sram_ramAddr_o(mmu_sram_ramAddr),
.rom_ramAddr_o(mmu_rom_ramAddr),
.flash_ramOp_o(mmu_flash_ramOp),
.flash_ramAddr_o(mmu_flash_ramAddr),
.flash_storeData_o(mmu_flash_storeData),
.serial_ramOp_o(mmu_serial_ramOp),
.serial_mode_o(mmu_serial_mode),
.serial_storeData_o(mmu_serial_storeData),
.memData_o(mmu_memData),
.exceptionMMU_o(mmu_exceptionMMU)
);
rom ROM(
.insAddr_i(mmu_rom_ramAddr),
.ins_o(rom_ins)
);
sramcontrol SRAMControl(
.clk50(clk25),
.rst(nrst),
.ramOp_i(mmu_sram_ramOp),
.storeData_i(mmu_sram_storeData),
.ramAddr_i(mmu_sram_ramAddr),
.ramData_i(sram_readData),
.ramAddr_o(sramcontrol_ramAddr),
.sramEnable_o(sramcontrol_sramEnable),
.writeEnable_o(sramcontrol_writeEnable),
.readEnable_o(sramcontrol_readEnable),
.busEnable_o(sramcontrol_busEnable),
.ramData_o(sramcontrol_ramData),
.writeData_o(sramcontrol_writeData)
);
flashcontrol FlashControl(
.clk25(clk),
.rst(nrst),
.ramOp_i(mmu_flash_ramOp),
.ramAddr_i(mmu_flash_ramAddr),
.storeData_i(mmu_flash_storeData),
.ramData_i(flash_readData),
.flashEnable_o(flashcontrol_flashEnable),
.readEnable_o(flashcontrol_readEnable),
.writeEnable_o(flashcontrol_writeEnable),
.busEnable_o(flashcontrol_busEnable),
.ramAddr_o(flashcontrol_ramAddr),
.writeData_o(flashcontrol_writeData),
.pauseRequest_o(flashcontrol_pauseRequest),
.ramData_o(flashcontrol_ramData)
);
serialcontrol SerialControl(
.clk25(clk),
.rst(nrst),
.ramOp_i(mmu_serial_ramOp),
.mode_i(mmu_serial_mode),
.storeData_i(mmu_serial_storeData),
.ramData_o(serialcontrol_ramData),
.serialInt_o(serialcontrol_serialInt),
.RxD(RxD),
.TxD(TxD)
);
pc PC(
.clk(clk),
.rst(nrst),
.bubble_i(id_bubbleRequest),
.pauseControl_i(con_pauseControl),
.flush_i(mem_flush),
.excAddr_i(mem_excAddr),
.branchEnable_i(id_branchEnable),
.branchAddr_i(id_branchAddr),
.insAddr_o(pc_insAddr)
);
if_id IF_ID(
.clk(clk),
.rst(nrst),
.bubble_i(id_bubbleRequest),
.pauseControl_i(con_pauseControl),
.flush_i(mem_flush),
.exception_i(memcontrol_exceptionIF),
.badVAddr_i(memcontrol_badVAddrIF),
.insAddr_i(pc_insAddr),
.ins_i(memcontrol_ins),
.insValid_o(if_id_insValid),
.insAddr_o(if_id_insAddr),
.ins_o(if_id_ins),
.exception_o(if_id_exception),
.badVAddr_o(if_id_badVAddr)
);
id ID(
.insAddr_i(if_id_insAddr),
.ins_i(if_id_ins),
.regData1_i(reg_data1),
.regData2_i(reg_data2),
.regDataHi_i(reg_dataHi),
.regDataLo_i(reg_dataLo),
.CP0Data_i(cp0_data),
.badVAddr_i(if_id_badVAddr),
.ex_writeReg_i(ex_writeReg),
.ex_writeRegAddr_i(ex_writeRegAddr),
.ex_writeData_i(ex_writeData),
.mem_writeReg_i(mem_writeReg),
.mem_writeRegAddr_i(mem_writeRegAddr),
.mem_writeData_i(mem_writeData),
.ex_writeRegHiLo_i(ex_writeRegHiLo),
.ex_writeDataHi_i(ex_writeDataHi),
.ex_writeDataLo_i(ex_writeDataLo),
.ex_memOp_i(id_ex_memOp),
.mem_writeRegHiLo_i(mem_writeRegHiLo),
.mem_writeDataHi_i(mem_writeDataHi),
.mem_writeDataLo_i(mem_writeDataLo),
.ex_writeCP0_i(ex_writeCP0),
.inDelaySlot_i(id_ex_nextInDelaySlot),
.exception_i(if_id_exception),
.ex_writeCP0Addr_i(ex_writeCP0Addr),
.mem_writeCP0_i(mem_writeCP0),
.mem_writeCP0Addr_i(mem_writeCP0Addr),
.regReadAddr1_o(id_regReadAddr1),
.regReadAddr2_o(id_regReadAddr2),
.regEnable1_o(id_regEnable1),
.regEnable2_o(id_regEnable2),
.CP0ReadEnable_o(id_CP0ReadEnable),
.CP0ReadAddr_o(id_CP0ReadAddr),
.bubbleRequest_o(id_bubbleRequest),
.exception_o(id_exception),
.operand1_o(id_operand1),
.operand2_o(id_operand2),
.aluOp_o(id_aluOp),
.storeData_o(id_storeData),
.memOp_o(id_memOp),
.writeReg_o(id_writeReg),
.writeRegAddr_o(id_writeRegAddr),
.writeRegHiLo_o(id_writeRegHiLo),
.writeCP0_o(id_writeCP0),
.writeCP0Addr_o(id_writeCP0Addr),
.branchEnable_o(id_branchEnable),
.branchAddr_o(id_branchAddr),
.insAddr_o(id_insAddr),
.inDelaySlot_o(id_inDelaySlot),
.nextInDelaySlot_o(id_nextInDelaySlot),
.badVAddr_o(id_badVAddr)
);
id_ex ID_EX(
.clk(clk),
.rst(nrst),
.operand1_i(id_operand1),
.operand2_i(id_operand2),
.aluOp_i(id_aluOp),
.storeData_i(id_storeData),
.memOp_i(id_memOp),
.writeReg_i(id_writeReg),
.writeRegAddr_i(id_writeRegAddr),
.writeRegHiLo_i(id_writeRegHiLo),
.writeCP0_i(id_writeCP0),
.writeCP0Addr_i(id_writeCP0Addr),
.insValid_i(if_id_insValid),
.insAddr_i(id_insAddr),
.inDelaySlot_i(id_inDelaySlot),
.nextInDelaySlot_i(id_nextInDelaySlot),
.exception_i(id_exception),
.badVAddr_i(id_badVAddr),
.pauseControl_i(con_pauseControl),
.flush_i(mem_flush),
.bubble_i(id_bubbleRequest),
.insValid_o(id_ex_insValid),
.insAddr_o(id_ex_insAddr),
.operand1_o(id_ex_operand1),
.operand2_o(id_ex_operand2),
.aluOp_o(id_ex_aluOp),
.storeData_o(id_ex_storeData),
.memOp_o(id_ex_memOp),
.writeReg_o(id_ex_writeReg),
.writeRegAddr_o(id_ex_writeRegAddr),
.writeRegHiLo_o(id_ex_writeRegHiLo),
.writeCP0_o(id_ex_writeCP0),
.writeCP0Addr_o(id_ex_writeCP0Addr),
.inDelaySlot_o(id_ex_inDelaySlot),
.nextInDelaySlot_o(id_ex_nextInDelaySlot),
.exception_o(id_ex_exception),
.badVAddr_o(id_ex_badVAddr)
);
ex EX(
.insAddr_i(id_ex_insAddr),
.operand1_i(id_ex_operand1),
.operand2_i(id_ex_operand2),
.aluOp_i(id_ex_aluOp),
.storeData_i(id_ex_storeData),
.memOp_i(id_ex_memOp),
.writeRegAddr_i(id_ex_writeRegAddr),
.writeReg_i(id_ex_writeReg),
.writeRegHiLo_i(id_ex_writeRegHiLo),
.writeCP0_i(id_ex_writeCP0),
.writeCP0Addr_i(id_ex_writeCP0Addr),
.inDelaySlot_i(id_ex_inDelaySlot),
.exception_i(id_ex_exception),
.badVAddr_i(id_ex_badVAddr),
.insAddr_o(ex_insAddr),
.writeRegAddr_o(ex_writeRegAddr),
.writeReg_o(ex_writeReg),
.writeData_o(ex_writeData),
.storeData_o(ex_storeData),
.memOp_o(ex_memOp),
.writeRegHiLo_o(ex_writeRegHiLo),
.writeDataHi_o(ex_writeDataHi),
.writeDataLo_o(ex_writeDataLo),
.writeCP0_o(ex_writeCP0),
.writeCP0Addr_o(ex_writeCP0Addr),
.inDelaySlot_o(ex_inDelaySlot),
.exception_o(ex_exception),
.badVAddr_o(ex_badVAddr)
);
ex_mem EX_MEM(
.clk(clk),
.rst(nrst),
.insAddr_i(ex_insAddr),
.storeData_i(ex_storeData),
.memOp_i(ex_memOp),
.writeData_i(ex_writeData),
.writeReg_i(ex_writeReg),
.writeRegAddr_i(ex_writeRegAddr),
.writeRegHiLo_i(ex_writeRegHiLo),
.writeDataHi_i(ex_writeDataHi),
.writeDataLo_i(ex_writeDataLo),
.writeCP0_i(ex_writeCP0),
.writeCP0Addr_i(ex_writeCP0Addr),
.insValid_i(id_ex_insValid),
.inDelaySlot_i(ex_inDelaySlot),
.exception_i(ex_exception),
.badVAddr_i(ex_badVAddr),
.pauseControl_i(con_pauseControl),
.flush_i(mem_flush),
.insAddr_o(ex_mem_insAddr),
.storeData_o(ex_mem_storeData),
.memOp_o(ex_mem_memOp),
.writeData_o(ex_mem_writeData),
.writeReg_o(ex_mem_writeReg),
.writeRegAddr_o(ex_mem_writeRegAddr),
.writeRegHiLo_o(ex_mem_writeRegHiLo),
.writeDataHi_o(ex_mem_writeDataHi),
.writeDataLo_o(ex_mem_writeDataLo),
.writeCP0_o(ex_mem_writeCP0),
.writeCP0Addr_o(ex_mem_writeCP0Addr),
.insValid_o(ex_mem_insValid),
.inDelaySlot_o(ex_mem_inDelaySlot),
.exception_o(ex_mem_exception),
.badVAddr_o(ex_mem_badVAddr)
);
mem MEM(
.memData_i(memcontrol_ramData),
.insValid_i(ex_mem_insValid),
.insAddr_i(ex_mem_insAddr),
.storeData_i(ex_mem_storeData),
.memOp_i(ex_mem_memOp),
.writeData_i(ex_mem_writeData),
.writeReg_i(ex_mem_writeReg),
.writeRegAddr_i(ex_mem_writeRegAddr),
.writeRegHiLo_i(ex_mem_writeRegHiLo),
.writeDataHi_i(ex_mem_writeDataHi),
.writeDataLo_i(ex_mem_writeDataLo),
.writeCP0_i(ex_mem_writeCP0),
.writeCP0Addr_i(ex_mem_writeCP0Addr),
.inDelaySlot_i(ex_mem_inDelaySlot),
.exception_i(ex_mem_exception),
.exceptionMC_i(memcontrol_exceptionMEM),
.badVAddr_i(ex_mem_badVAddr),
.cp0_Status_i(cp0_Status),
.cp0_EntryHi_i(cp0_EntryHi),
.cp0_Ebase_i(cp0_Ebase),
.cp0_EPC_i(cp0_EPC),
.timeInt_i(cp0_timeInt),
.serialInt_i(serialcontrol_serialInt),
.memOp_o(mem_memOp),
.storeData_o(mem_storeData),
.memAddr_o(mem_memAddr),
.writeReg_o(mem_writeReg),
.writeRegAddr_o(mem_writeRegAddr),
.writeData_o(mem_writeData),
.writeRegHiLo_o(mem_writeRegHiLo),
.writeDataHi_o(mem_writeDataHi),
.writeDataLo_o(mem_writeDataLo),
.writeCP0_o(mem_writeCP0),
.writeCP0Addr_o(mem_writeCP0Addr),
.flush_o(mem_flush),
.excAddr_o(mem_excAddr),
.inDelaySlot_o(mem_inDelaySlot),
.insAddr_o(mem_insAddr),
.exception_o(mem_exception),
.badVAddr_o(mem_badVAddr)
);
mem_wb MEM_WB(
.clk(clk),
.rst(nrst),
.writeReg_i(mem_writeReg),
.writeRegAddr_i(mem_writeRegAddr),
.writeData_i(mem_writeData),
.writeRegHiLo_i(mem_writeRegHiLo),
.writeDataHi_i(mem_writeDataHi),
.writeDataLo_i(mem_writeDataLo),
.writeCP0_i(mem_writeCP0),
.writeCP0Addr_i(mem_writeCP0Addr),
.pauseControl_i(con_pauseControl),
.exception_i(mem_exception),
.inDelaySlot_i(mem_inDelaySlot),
.insAddr_i(mem_insAddr),
.badVAddr_i(mem_badVAddr),
.writeReg_o(mem_wb_writeReg),
.writeRegAddr_o(mem_wb_writeRegAddr),
.writeData_o(mem_wb_writeData),
.writeRegHiLo_o(mem_wb_writeRegHiLo),
.writeDataHi_o(mem_wb_writeDataHi),
.writeDataLo_o(mem_wb_writeDataLo),
.writeCP0_o(mem_wb_writeCP0),
.writeCP0Addr_o(mem_wb_writeCP0Addr),
.exception_o(mem_wb_exception),
.insAddr_o(mem_wb_insAddr),
.badVAddr_o(mem_wb_badVAddr),
.inDelaySlot_o(mem_wb_inDelaySlot)
);
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* VC router
*
*/
`include "types.v"
//`include "parameters.v"
typedef flit_pri_t flit_priority_t;
module NW_vc_router (i_flit_in, i_flit_out,
i_cntrl_in, i_cntrl_out,
i_input_full_flag,
clk, rst_n);
`include "NW_functions.v"
//parameter type flit_priority_t = flit_pri_t;
parameter network_x = 4;
parameter network_y = 4;
parameter buf_len = 4;
parameter NP=5;
parameter NV=2;
// numbers of virtual-channels on entry/exit to network?
parameter router_num_vcs_on_entry = 1;
parameter router_num_vcs_on_exit = 2; //4
//
// Pipeline VC and switch allocation?
//
parameter uarch_pipeline=0;
// with or without an explicit pipelining register?
// can just read from head of FIFO twice
parameter uarch_explicit_pipeline_register=0;
//
// Check VC buffer is full (at dest.) before making a switch request?
//
parameter uarch_full_vc_check_before_switch_request=0;
//
// Switch Allocation
//
// perform VC and switch allocation in parallel
parameter swalloc_speculative=0;
//
// VC Allocation
//
parameter vcalloc_unrestricted=1;
//
// VC Selection
//
parameter vcselect_bydestinationnode = 0;
parameter vcselect_leastfullbuffer = 0;
parameter vcselect_arbstateupdate = 0;
parameter vcselect_usepacketmask = 0;
parameter vcselect_onlywhenempty = 0;
//
// Prioritised Communications
//
// prioritise switch allocation by position of flit in packet (head=0, tail=N)
parameter priority_switch_alloc_byflitid=0;
// prioritise switch allocation based on flit.control.flit_priority
parameter priority_flit_dynamic_switch_alloc=0;
// prioritise vc allocation based on flit.control.flit_priority
parameter priority_flit_dynamic_vc_alloc=0;
// size of flit.control.flit_priority field (in bits)
parameter priority_flit_bits=4;
//
// prioritise_network_traffic = 0 - no modifications to flit_priority are made by the router
// prioritise_network_traffic = 1 - router sets flit_priority to 1 on exit, traffic in network has
// priority over newly injected traffic
// prioritise_network_traffic = 2 - flit_priority is increased at each router as the flit exists
// flit_priority is determined by its current hop count
// (be careful to ensure enough priority bits are available)
// Upto a limit of 'priority_flit_limit'
parameter priority_network_traffic=0;
parameter priority_flit_limit=4;
//==================================================================
// FIFO rec. data from tile/core is full?
output [router_num_vcs_on_entry-1:0] i_input_full_flag;
// link data and control
input flit_t i_flit_in [NP-1:0];
output flit_t i_flit_out [NP-1:0];
input chan_cntrl_t i_cntrl_in [NP-1:0];
output chan_cntrl_t i_cntrl_out [NP-1:0];
input clk, rst_n;
// Credit count for each VC at each output port
logic [NP-1:0][NV-1:0][clogb2(buf_len+1)-1:0] vc_credits;
flit_priority_t req_priority [NP-1:0][NV-1:0];
logic [NP-1:0] output_valid_flit_check;
logic [NP-1:0][NV-1:0] pop_vc_valid_check;
logic [NP-1:0] free_vc_blocked;
logic [NP-1:0] no_free_vc;
logic [NP-1:0][NV-1:0] switch_req, spec_switch_req;
// vc_t x_vc_status [NP-1:0];
logic [NP-1:0][NV-1:0] x_vc_status;
logic [NP-1:0] x_push;
logic [NP-1:0][NV-1:0] x_pop;
flit_t x_flit_xbarin[NP-1:0];
flit_t x_flit_xbarin_pipe[NP-1:0];
flit_t x_flit_xbarout[NP-1:0];
// logic [clogb2(NV)-1:0] x_vc_id [NP-1:0];
// logic [clogb2(NV)-1:0] x_select [NP-1:0];
vc_index_t x_vc_id [NP-1:0];
vc_index_t x_select [NP-1:0];
flit_t x_flit_bufout [NP-1:0];
flit_t x_data_in_reg [NP-1:0];
fifov_flags_t x_flags [NP-1:0][NV-1:0];
logic [NV-1:0] x_allocated_vc [NP-1:0][NV-1:0];
logic [NV-1:0] vc_for_blocked_check [NP-1:0][NV-1:0];
logic [NP-1:0][NV-1:0] x_allocated_vc_valid;
logic [NP-1:0][NV-1:0][NV-1:0] x_vc_new;
logic [NP-1:0][NV-1:0] x_vc_new_valid;
output_port_t x_output_port [NP-1:0][NV-1:0];
output_port_t x_output_port_for_vc [NP-1:0][NV-1:0];
output_port_t x_output_port_for_sw [NP-1:0][NV-1:0];
vc_t [NP-1:0] x_free_vc;
logic [NP-1:0][NP-1:0] xbar_select;
logic [NP-1:0][NV-1:0] vc_request; // VC request from each input VC
logic [NP-1:0] vc_allocated_at_output; // for each output port, has a VC been allocated?
logic [NP-1:0][NV-1:0] allocated_vc_blocked, check_full_vc;
logic [NP-1:0][NV-1:0] switch_grant;
// logic [`PV-1:0] input_vc_mux_sel;
logic [NP-1:0][NV-1:0] input_vc_mux_sel;
logic [NP-1:0] output_used; // output channel used on this cycle?
logic [NP-1:0] outgoing_blocked, output_requested;
// logic [`PV-1:0] blocked;
// logic [NP-1:0][NV-1:0] blocked;
logic [NP-1:0][NV-1:0] pipereg_ready, pipereg_valid, pipereg_push, pipereg_pop;
flit_t pipereg_data_in [NP-1:0][NV-1:0];
flit_t pipereg_data_out [NP-1:0][NV-1:0];
flit_t routed_flit_buffer_out [NP-1:0][NV-1:0];
flit_t flit_buffer_out [NP-1:0][NV-1:0];
//
// unrestricted VC free pool/allocation
//
logic [NP-1:0][NV-1:0] vc_alloc_status; // which output VCs are free to be allocated
logic [NP-1:0][NV-1:0] vc_allocated; // indicates which VCs were allocated on this clock cycle
logic [NP-1:0][NV-1:0][NV-1:0] vc_requested; // which VCs were selected to be requested at each input VC?
//
logic [NP-1:0][NV-1:0] vc_empty; // is downstream FIFO associated with VC empty?
genvar i,j,k;
integer db_out_used, db_in_popped, p,v;
// quick parameter sanity check
// synopsys translate_off
always@(negedge rst_n) begin
if (swalloc_speculative) begin
assert (!uarch_pipeline) else begin
$error("*** Speculative switch allocation cannot be applied to pipelined designs ***");
$finish;
end
assert (!uarch_explicit_pipeline_register) else begin
$error("*** Speculative switch allocation cannot be applied to pipelined designs ***");
$finish;
end
end
if (uarch_explicit_pipeline_register) begin
assert (uarch_pipeline) else begin
$error("*** Pipelining registers can only be added if the '(uarch_)pipeline' parameter is set ***");
$finish;
end
end
end
// synopsys translate_on
// **************************************
// map new interface to old interface
// **************************************
generate
for (i=0; i<NP; i++) begin:map
// assign nearly_full_in [(i+1)*NV-1:i*NV] = i_cntrl_in[i].nearly_full;
`ifdef NEARLY_FULL_FLOW_CONTROL
for (j=0; j<NV; j++) begin:nv
assign i_cntrl_out[i].nearly_full[j] = x_flags[i][j].nearly_full;
end
`endif
end
endgenerate
// *******************************************************************************
// output ports
// *******************************************************************************
generate
for (i=0; i<NP; i++) begin:output_ports
//
// Free VC pools
//
if (i==`TILE) begin
//
// may have less than a full complement of VCs on exit from network
//
NW_vc_free_pool #(.num_vcs_local(router_num_vcs_on_exit),
.num_vcs_global(NV),
.fifo_free_pool(!vcalloc_unrestricted),
.only_allocate_vc_when_empty(vcselect_onlywhenempty)) vcfreepool
(.flit(x_flit_xbarout[i]),
.valid(output_used[i]),
// FIFO free pool
.oh_free_vc(x_free_vc[i]),
.no_free_vc(no_free_vc[i]),
.vc_consumed(vc_allocated_at_output[i]),
// Unrestricted free pool
.vc_alloc_status(vc_alloc_status[i]),
.vc_allocated(vc_allocated[i]),
.vc_empty(vc_empty[i]),
//
.clk, .rst_n);
end else begin
NW_vc_free_pool #(.num_vcs_local(NV),
.num_vcs_global(NV),
.fifo_free_pool(!vcalloc_unrestricted),
.only_allocate_vc_when_empty(vcselect_onlywhenempty)) vcfreepool
(.flit(x_flit_xbarout[i]),
.valid(output_used[i]),
// FIFO free pool
.oh_free_vc(x_free_vc[i]),
.no_free_vc(no_free_vc[i]),
.vc_consumed(vc_allocated_at_output[i]),
// Unrestricted free pool
.vc_alloc_status(vc_alloc_status[i]),
.vc_allocated(vc_allocated[i]),
.vc_empty(vc_empty[i]),
//
.clk, .rst_n);
end // else: !if(i==`TILE)
//
// Flow Control
//
NW_vc_fc_out #(.num_vcs(NV),
.init_credits(buf_len))
fcout (.flit(x_flit_xbarout[i]),
.flit_valid(output_used[i]),
.channel_cntrl_in(i_cntrl_in[i]),
.vc_status(x_vc_status[i]),
.vc_empty(vc_empty[i]),
.vc_credits(vc_credits[i]),
.clk, .rst_n);
// indicate to upstream router that new buffer is free when
// we remove flit from an input FIFO (credit-based flow-control)
`ifdef CREDIT_FLOW_CONTROL
always@(posedge clk) begin
if (!rst_n) begin
i_cntrl_out[i].credit_valid<=1'b0;
end else begin
//
// ensure 'credit' is registered before it is sent to the upstream router
//
if (uarch_explicit_pipeline_register) begin
//
// can only send one credit per cycle, so have to look at output of
// pipeline register and not FIFO->pipe-reg. transfers
//
i_cntrl_out[i].credit<=oh2bin(pipereg_pop[i]);
i_cntrl_out[i].credit_valid<=|pipereg_pop[i];
end else begin
// send credit corresponding to flit sent from this input port
i_cntrl_out[i].credit<=x_select[i];
i_cntrl_out[i].credit_valid<=|x_pop[i];
end
end
end
`endif
// assign blocked[(i+1)*NV-1:i*NV]=x_vc_status[i];
// assign blocked[i]=x_vc_status[i];
if (!vcalloc_unrestricted) begin
assign free_vc_blocked[i]=|(x_vc_status[i] & x_free_vc[i]);
end
end
endgenerate
// *******************************************************************************
// input ports (vc buffers and VC registers)
// *******************************************************************************
generate
for (i=0; i<router_num_vcs_on_entry; i++) begin:vcsx
assign i_input_full_flag[i] = x_flags[`TILE][i].full; // TILE input FIFO[i] is full?
end
for (i=0; i<NP; i++) begin:input_ports
// should support .nv and .num_vcs (e.g. for tile input that may only
// support a single input VC)
// input port 'i'
NW_vc_input_port #(.num_vcs(NV),
.buffer_length(buf_len),
.pipelined_vc_switch_alloc(uarch_pipeline),
.explicit_pipe_registers(uarch_explicit_pipeline_register)) inport
(.push(x_push[i]),
.pop(x_pop[i]),
.data_in(i_flit_in[i]),
.vc_id(x_vc_id[i]),
.select(input_vc_mux_sel[i]), // use one-hot
// .select(x_select[i]),
.data_out(x_flit_xbarin[i]),
// .output_port(x_output_port[i]),
.data_in_reg(x_data_in_reg[i]),
.flags(x_flags[i]),
// .buf_finished_empty(x_buf_finished_empty[i]),
.allocated_vc(x_allocated_vc[i]),
.allocated_vc_valid(x_allocated_vc_valid[i]),
.vc_new(x_vc_new[i]),
.vc_new_valid(x_vc_new_valid[i]),
// .head_is_tail(head_is_tail[i]),
.flit_buffer_out(flit_buffer_out[i]),
.clk, .rst_n);
//
// output port fields and flit priorities
// flit priorities come from flit.control.flit_priority (if required)
//
for (j=0; j<NV; j++) begin:allvcs2
assign x_output_port_for_vc[i][j] = flit_buffer_out[i][j].control.output_port;
//
// Explicit Pipelining Register
//
if (uarch_explicit_pipeline_register) begin
assign x_output_port_for_sw[i][j] = pipereg_data_out[i][j].control.output_port;
end else begin
assign x_output_port_for_sw[i][j] = flit_buffer_out[i][j].control.output_port;
end
end
// *** DATA IN *** //
assign x_push[i]=i_flit_in[i].control.valid;
// cast result of oh2bin to type of x_vc_id[i]
assign x_vc_id[i]= vc_index_t'(oh2bin(i_flit_in[i].control.vc_id));
// *** DATA OUT *** //
// was selected VC at input port 'i' granted access to crossbar?
// If we have performed speculative switch allocation we need
// to check flit received VC before removing it from the input FIFO.
for (j=0; j<NV; j++) begin:allvcs3
if (swalloc_speculative) begin
assign pop_vc_valid_check[i][j] = (x_allocated_vc_valid[i][j] || x_vc_new_valid[i][j]);
end else begin
assign pop_vc_valid_check[i][j] = 1'b1;
end
end
if (uarch_explicit_pipeline_register) begin
// remove from FIFO when copied to pipelining register
assign x_pop[i]= pipereg_push[i];
end else begin
if (uarch_full_vc_check_before_switch_request) begin
// VC blocked check already made before request
assign x_pop[i] = switch_grant[i] & pop_vc_valid_check[i];
end else begin
// need to check VC isn't blocked
assign x_pop[i]= switch_grant[i] & ~allocated_vc_blocked[i] & pop_vc_valid_check[i];
end
end
// convert one-hot select at input port 'i' to binary for vc_input_port
// assign x_select[i]= vc_index_t'(oh2bin(input_vc_mux_sel[(i+1)*NV-1:i*NV]));
assign x_select[i]= vc_index_t'(oh2bin(input_vc_mux_sel[i]));
/**************************************************************************/
//
// add explicit pipelining register if requested.
//
// pipelining register after VC allocation stage. Switch requests
// are in this case received from this register.
//
if (uarch_explicit_pipeline_register) begin
for (j=0; j<NV; j++) begin:allvcs
//
// push - * pipe register ready to receive
// * VC FIFO has a flit
// * flit has been allocated a VC (previously or on this cycle)
//
assign pipereg_push[i][j] = pipereg_ready[i][j] && !x_flags[i][j].empty &&
(x_allocated_vc_valid[i][j] || x_vc_new_valid[i][j]);
//
// pop
//
if (uarch_full_vc_check_before_switch_request)
assign pipereg_pop[i][j] = switch_grant[i][j];
else
assign pipereg_pop[i][j] = switch_grant[i][j] && ~allocated_vc_blocked[i][j];
//
// data_in
//
always_comb
begin
//
// flit that is stored in pipelining register always has a valid VC
//
pipereg_data_in[i][j] = flit_buffer_out[i][j];
pipereg_data_in[i][j].control.vc_id = x_allocated_vc[i][j];
end
NW_pipereg pipe_reg1
(.push(pipereg_push[i][j]),
.pop(pipereg_pop[i][j]),
.data_in(pipereg_data_in[i][j]),
.data_out(pipereg_data_out[i][j]),
.ready(pipereg_ready[i][j]),
.valid(pipereg_valid[i][j]),
.clk, .rst_n);
end
end
/**************************************************************************/
//
// Switch and Virtual-Channel allocation requests
//
for (j=0; j<NV; j++) begin:reqs
//
// VIRTUAL-CHANNEL ALLOCATION REQUESTS
//
assign vc_request[i][j]= (NW_route_valid_input_vc(i,j)) ?
!x_flags[i][j].empty & !x_allocated_vc_valid[i][j] : 1'b0;
//
// SWITCH ALLOCATION REQUESTS
//
// Full VC buffer check. Perform check prior to making a switch request or
// later at output port. Schedule-quality/clock-cycle trade-off
if (uarch_full_vc_check_before_switch_request) begin
assign check_full_vc[i][j]=!allocated_vc_blocked[i][j];
end else begin
assign check_full_vc[i][j]=1'b1; // check at end of cycle.
end
// Pipelined VC / Switch Alloc.
if (uarch_pipeline==1) begin
if (uarch_explicit_pipeline_register) begin
//
// switch req come from pipeline registers
// (as does output port info.)
//
assign switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
pipereg_valid[i][j] &&
check_full_vc[i][j] : 1'b0;
assign vc_for_blocked_check[i][j] = pipereg_data_out[i][j].control.vc_id;
end else begin
assign switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
!x_flags[i][j].empty &&
x_allocated_vc_valid[i][j] &&
check_full_vc[i][j] : 1'b0;
assign vc_for_blocked_check[i][j] = x_allocated_vc[i][j];
end
// is current VC blocked?
// - VC allocation happened in previous clock cycle so don't have to
// worry about new VCs. Just look at status of allocated VC.
unary_select_pair #(i, NP, NV) blocked_mux
(x_output_port_for_sw[i][j],
// x_allocated_vc[i][j],
vc_for_blocked_check[i][j],
// blocked,
x_vc_status,
allocated_vc_blocked[i][j]);
end else begin
//
// ** Single Cycle **
//
if (!swalloc_speculative) begin
//
// Without speculative switch alloc.
//
// VC allocation takes place first. Need to check outcome
// of this VC allocation before making request (x_vc_new_valid)
//
assign switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
!x_flags[i][j].empty &&
(x_allocated_vc_valid[i][j] || x_vc_new_valid[i][j]) &&
check_full_vc[i][j] : 1'b0;
end else begin // if (!swalloc_speculative)
//
// With speculative switch allocation
// Only make non-speculative requests when VC has been allocated
// in previous clock cycle.
//
assign switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
!x_flags[i][j].empty &&
x_allocated_vc_valid[i][j] &&
check_full_vc[i][j] : 1'b0;
// If we are performing speculative switch allocation
// need to make speculative switch requests.
// (requests from flits without allocated output VCs)
assign spec_switch_req[i][j] = (NW_route_valid_input_vc(i,j)) ?
!x_flags[i][j].empty &&
!x_allocated_vc_valid[i][j] &&
check_full_vc[i][j] : 1'b0;
end
end
end // block: reqs
end // block: input_ports
if (uarch_pipeline==0) begin
//
// if single-cycle we need to consider newly allocated
// virtual-channels too when determining if VCs are blocked
//
NW_vc_status #(.np(NP), .nv(NV)) vstat
(.output_port(x_output_port_for_sw),
.free_vc_blocked(free_vc_blocked),
.vc_requested(vc_requested),
.allocated_vc(x_allocated_vc),
.allocated_vc_valid(x_allocated_vc_valid),
// .vc_status(blocked),
.vc_status(x_vc_status),
.vc_blocked(allocated_vc_blocked));
end
endgenerate
// ----------------------------------------------------------------------
// virtual-channel allocation logic
// ----------------------------------------------------------------------
NW_vc_allocator #(.buf_len(buf_len), .np(NP), .nv(NV), .xs(network_x), .ys(network_y),
.dynamic_priority_vc_alloc( priority_flit_dynamic_vc_alloc),
.vcalloc_unrestricted(vcalloc_unrestricted),
.vcselect_bydestinationnode(vcselect_bydestinationnode),
.vcselect_leastfullbuffer(vcselect_leastfullbuffer),
.vcselect_arbstateupdate(vcselect_arbstateupdate),
.vcselect_usepacketmask(vcselect_usepacketmask))
vcalloc
(.req(vc_request),
.req_priority(req_priority),
.output_port(x_output_port_for_vc),
.vc_new(x_vc_new),
.vc_new_valid(x_vc_new_valid),
.next_free_vc(x_free_vc),
.no_free_vc(no_free_vc),
.pop_free_vc(vc_allocated_at_output),
// unrestricted VC pool
.vc_allocated(vc_allocated),
.vc_requested(vc_requested),
.vc_alloc_status(vc_alloc_status),
.flit(flit_buffer_out),
.vc_credits(vc_credits),
.clk, .rst_n);
// ----------------------------------------------------------------------
// switch-allocation logic (or speculative switch allocation)
// ----------------------------------------------------------------------
generate
if (!swalloc_speculative) begin
//
// for pipelined VC/switch allocation or switch allocation following
// VC allocation in single-cycle.
//
NW_vc_switch_allocator
#(.np(NP), .nv(NV),
.dynamic_priority_switch_alloc(priority_flit_dynamic_switch_alloc || priority_switch_alloc_byflitid)
//,
//.flit_priority_t(flit_priority_t)
)
swalloc
(.req(switch_req),
.req_priority(req_priority),
.output_port(x_output_port_for_sw),
.grant(switch_grant),
.vc_mux_sel(input_vc_mux_sel),
.xbar_select(xbar_select),
.any_request_for_output(output_requested),
.clk, .rst_n);
end else begin // if (!swalloc_speculative)
/* NW_speculative_switch_allocator
#(.np(NP), .nv(NV),
.dynamic_priority_switch_alloc(priority_flit_dynamic_switch_alloc)
//,
//.flit_priority_t(flit_priority_t)
)
specswitch
(.nonspec_req(switch_req),
.spec_req(spec_switch_req),
.req_priority(req_priority),
.output_port(x_output_port_for_sw),
.grant(switch_grant),
.vc_mux_sel(input_vc_mux_sel),
.xbar_select(xbar_select),
.any_request_for_output(output_requested),
.clk, .rst_n);*/
end // else: !if(!swalloc_speculative)
endgenerate
// ----------------------------------------------------------------------
// crossbar
// ----------------------------------------------------------------------
generate
if (uarch_explicit_pipeline_register) begin
//
// crossbar inputs come from mux fed by pipelining registers
//
for (i=0; i<NP; i++) begin:allinps
NW_route rfn (.flit_in(pipereg_data_out[i][x_select[i]]),
.flit_out(x_flit_xbarin_pipe[i]), .clk, .rst_n);
end
NW_crossbar_oh_select #( .n(NP)) myxbar
(x_flit_xbarin_pipe, xbar_select, x_flit_xbarout);
end else begin
//
// crossbar inputs from VC input ports
//
NW_crossbar_oh_select #( .n(NP)) myxbar
(x_flit_xbarin, xbar_select, x_flit_xbarout);
end
endgenerate
// ----------------------------------------------------------------------
// output port logic
// ----------------------------------------------------------------------
generate
for (i=0; i<NP; i++) begin:outports
if (swalloc_speculative) begin
// need to check flit at output has valid output VC
assign output_valid_flit_check[i] = |(x_flit_xbarout[i].control.vc_id);
end else begin
assign output_valid_flit_check[i] = 1'b1;
end
if (uarch_full_vc_check_before_switch_request) begin
//
// output is valid if any request for this output was made
// (request can only be made if 1. VC is already allocated
// and 2. vc is not blocked (full).
//
// What about two requests at same input port (different VCs)
// to different output ports?
// - 'output_requested' is request to second stage of arbiters
// in switch allocator so this is OK.
assign output_used[i] = output_requested[i] && output_valid_flit_check[i];
end else begin
//
// need to check VC id. of flit leaving on this port is
// not blocked.
//
assign outgoing_blocked[i] = |(x_flit_xbarout[i].control.vc_id & x_vc_status[i]) ;
assign output_used[i] = output_requested[i] && !outgoing_blocked[i] && output_valid_flit_check[i];
end
always_comb
begin
i_flit_out[i]=x_flit_xbarout[i];
i_flit_out[i].control.valid=output_used[i];
// injected flits from tile have the lowest priority, once in network priority is increased.
`ifdef FLIT_DYNAMIC_PRIORITY
if (priority_network_traffic==1) begin
i_flit_out[i].control.flit_priority=1; // 4
end else begin
// flit priority is determined by the number of hops the flit has taken
if (priority_network_traffic==2) begin
if (i_flit_out[i].control.flit_priority<priority_flit_limit) begin
i_flit_out[i].control.flit_priority=i_flit_out[i].control.flit_priority+1;
end
end
end
`endif
end
end // block: outports
endgenerate
// synopsys translate_off
/* -----------------------------------------------------------------------------------
* assert (only unallocated VCs are allocated to waiting packets)
* -----------------------------------------------------------------------------------
*/
always@(posedge clk) begin
if (!rst_n) begin
end else begin
for (p=0; p<NP; p++) begin
for (v=0; v<NV; v++) begin
if (x_vc_new_valid[p][v]) begin
// check x_vc_new is free to be allocated
if (vcalloc_unrestricted) begin
if (!vc_alloc_status[oh2bin(x_output_port_for_vc[p][v])][oh2bin(x_vc_new[p][v])]) begin
$display ("%m: Error: Newly allocated VC is already allocated to another packet");
$display ("Input port=%1d, VC=%1d", p,v);
$display ("Requesting Output Port %b (%1d)", x_output_port_for_vc[p][v],
oh2bin(x_output_port_for_vc[p][v]));
$display ("VC requested %b ", vc_requested[p][v]);
$display ("x_vc_new %b ", x_vc_new[p][v]);
$finish;
end
end
end
end
end
end
end
// synopsys translate_on
// synopsys translate_off
/* -----------------------------------------------------------------------------------
* assert (no. of flits leaving router == no. of flits dequeued from input FIFOs)
* -----------------------------------------------------------------------------------
*/
always@(posedge clk) begin
if (!rst_n) begin
end else begin
db_out_used = 0;
db_in_popped = 0;
// count number of outputs used.
for (p=0; p<NP; p++) begin
if (output_used[p]) db_out_used++;
end
// count number of flits removed from input fifos
for (p=0; p<NP; p++) begin
for (v=0; v<NV; v++) begin
if (x_pop[p][v]) db_in_popped++;
end
end
if (db_out_used!=db_in_popped) begin
$display ("%m: Error: more flits sent on output than dequeued from input FIFOs!");
for (p=0; p<NP; p++) begin
$display ("-------------------------------------------------");
$display ("Input Port=%1d", p);
$display ("-------------------------------------------------");
for (v=0; v<NV; v++) begin
$write ("VC=%1d: ", v);
if ((switch_req[p][v])||(spec_switch_req[p][v])||(switch_grant[p][v]))
$write ("[OUTP=%1d]", oh2bin(x_output_port_for_sw[p][v]));
if (switch_req[p][v]) $write ("(Switch_Req)");
if (spec_switch_req[p][v]) $write ("(Spec_Switch_Req)");
if (switch_grant[p][v]) $write ("(Switch_Grant)");
if (x_vc_new_valid[p][v]) $write ("(New VC Alloc'd)");
$display ("");
end
end // for (p=0; p<NP; p++)
$display ("-------------------------------------------------");
$display ("Output Used=%b", output_used);
$display ("-------------------------------------------------");
// $finish;
end // if (db_out_used!=db_in_popped)
end
end // always@ (posedge clk)
// synopsys translate_on
endmodule // simple_router
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__OR4_FUNCTIONAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:08:04 05/25/2015
// Design Name: can_tx
// Module Name: C:/Users/dagosttv.ROSE-HULMAN/Documents/School/ECE/ECE398/CAN-Bus-Controller-/Tx_test_internal.v
// Project Name: CAN_Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: can_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Tx_test_internal;
// Inputs
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;
reg clear_to_tx;
assign rx = tx;
assign bitstuffed_output = tx;
// Outputs
wire tx;
wire can_bitstuff;
wire txing;
// Instantiate the Unit Under Test (UUT)
can_tx uut (
.tx(tx),
.can_bitstuff(can_bitstuff),
.txing(txing),
.rx(rx),
.address(address),
.clk(clk),
.baud_clk(baud_clk),
.rst(rst),
.data(data),
.send_data(send_data),
.bitstuffed_output(bitstuffed_output),
.clear_to_tx(clear_to_tx)
);
initial begin
// Initialize Inputs
address = 11'h28;
clk = 0;
baud_clk = 0;
rst = 1;
data = 43;
send_data = 0;
clear_to_tx = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#10;
send_data = 1;
clear_to_tx = 1;
#300000 $stop;
// Add stimulus here
end
always #1.25 clk=~clk;
always #1000 baud_clk=~baud_clk;
endmodule
|
(** * RecordSub: Subtyping with Records *)
(** In this chapter, we combine two significant extensions of the pure
STLC -- records (from chapter [Records]) and subtyping (from
chapter [Sub]) -- and explore their interactions. Most of the
concepts have already been discussed in those chapters, so the
presentation here is somewhat terse. We just comment where things
are nonstandard. *)
Require Import Maps.
Require Import Smallstep.
Require Import MoreStlc.
(* ################################################################# *)
(** * Core Definitions *)
(* ----------------------------------------------------------------- *)
(** *** Syntax *)
Inductive ty : Type :=
(* proper types *)
| TTop : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
(* record types *)
| TRNil : ty
| TRCons : id -> ty -> ty -> ty.
Inductive tm : Type :=
(* proper terms *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tproj : tm -> id -> tm
(* record terms *)
| trnil : tm
| trcons : id -> tm -> tm -> tm.
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
(** The syntax of terms and types is a bit too loose, in the sense
that it admits things like a record type whose final "tail" is
[Top] or some arrow type rather than [Nil]. To avoid such cases,
it is useful to assume that all the record types and terms that we
see will obey some simple well-formedness conditions.
[An interesting technical question is whether the basic properties
of the system -- progress and preservation -- remain true if we
drop these conditions. I believe they do, and I would encourage
motivated readers to try to check this by dropping the conditions
from the definitions of typing and subtyping and adjusting the
proofs in the rest of the chapter accordingly. This is not a
trivial exercise (or I'd have done it!), but it should not involve
changing the basic structure of the proofs. If someone does do
it, please let me know. --BCP 5/16.] *)
Inductive record_ty : ty -> Prop :=
| RTnil :
record_ty TRNil
| RTcons : forall i T1 T2,
record_ty (TRCons i T1 T2).
Inductive record_tm : tm -> Prop :=
| rtnil :
record_tm trnil
| rtcons : forall i t1 t2,
record_tm (trcons i t1 t2).
Inductive well_formed_ty : ty -> Prop :=
| wfTTop :
well_formed_ty TTop
| wfTBase : forall i,
well_formed_ty (TBase i)
| wfTArrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty (TArrow T1 T2)
| wfTRNil :
well_formed_ty TRNil
| wfTRCons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty (TRCons i T1 T2).
Hint Constructors record_ty record_tm well_formed_ty.
(* ----------------------------------------------------------------- *)
(** *** Substitution *)
(** Substitution and reduction are as before. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if beq_id x y then s else t
| tabs y T t1 => tabs y T (if beq_id x y then t1
else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tproj t1 i => tproj (subst x s t1) i
| trnil => trnil
| trcons i t1 tr2 => trcons i (subst x s t1) (subst x s tr2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ----------------------------------------------------------------- *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_rnil : value trnil
| v_rcons : forall i v vr,
value v ->
value vr ->
value (trcons i v vr).
Hint Constructors value.
Fixpoint Tlookup (i:id) (Tr:ty) : option ty :=
match Tr with
| TRCons i' T Tr' =>
if beq_id i i' then Some T else Tlookup i Tr'
| _ => None
end.
Fixpoint tlookup (i:id) (tr:tm) : option tm :=
match tr with
| trcons i' t tr' =>
if beq_id i i' then Some t else tlookup i tr'
| _ => None
end.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_Proj1 : forall tr tr' i,
tr ==> tr' ->
(tproj tr i) ==> (tproj tr' i)
| ST_ProjRcd : forall tr i vi,
value tr ->
tlookup i tr = Some vi ->
(tproj tr i) ==> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 ==> t1' ->
(trcons i t1 tr2) ==> (trcons i t1' tr2)
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 ==> tr2' ->
(trcons i v1 tr2) ==> (trcons i v1 tr2')
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
(* ################################################################# *)
(** * Subtyping *)
(** Now we come to the interesting part, where the features we've
added start to interact. We begin by defining the subtyping
relation and developing some of its important technical
properties. *)
(* ================================================================= *)
(** ** Definition *)
(** The definition of subtyping is essentially just what we sketched
in the discussion of record subtyping in chapter [Sub], but we
need to add well-formedness side conditions to some of the rules.
Also, we replace the "n-ary" width, depth, and permutation
subtyping rules by binary rules that deal with just the first
field. *)
Reserved Notation "T '<:' U" (at level 40).
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
T <: T
| S_Trans : forall S U T,
S <: U ->
U <: T ->
S <: T
| S_Top : forall S,
well_formed_ty S ->
S <: TTop
| S_Arrow : forall S1 S2 T1 T2,
T1 <: S1 ->
S2 <: T2 ->
TArrow S1 S2 <: TArrow T1 T2
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty (TRCons i T1 T2) ->
TRCons i T1 T2 <: TRNil
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
S1 <: T1 ->
Sr2 <: Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
TRCons i S1 Sr2 <: TRCons i T1 Tr2
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty (TRCons i1 T1 (TRCons i2 T2 Tr3)) ->
i1 <> i2 ->
TRCons i1 T1 (TRCons i2 T2 Tr3)
<: TRCons i2 T2 (TRCons i1 T1 Tr3)
where "T '<:' U" := (subtype T U).
Hint Constructors subtype.
(* ================================================================= *)
(** ** Examples *)
Module Examples.
Notation x := (Id "x").
Notation y := (Id "y").
Notation z := (Id "z").
Notation j := (Id "j").
Notation k := (Id "k").
Notation i := (Id "i").
Notation A := (TBase (Id "A")).
Notation B := (TBase (Id "B")).
Notation C := (TBase (Id "C")).
Definition TRcd_j :=
(TRCons j (TArrow B B) TRNil). (* {j:B->B} *)
Definition TRcd_kj :=
TRCons k (TArrow A A) TRcd_j. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
subtype (TArrow C TRcd_kj)
(TArrow C TRNil).
(* C->{k:A->A,j:B->B} <: C->{} *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold TRcd_kj, TRcd_j. apply S_RcdWidth; auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get full
benefit, make sure you also understand how to prove them on
paper! *)
(** **** Exercise: 2 stars (subtyping_example_1) *)
Example subtyping_example_1 :
subtype TRcd_kj TRcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (subtyping_example_2) *)
Example subtyping_example_2 :
subtype (TArrow TTop TRcd_kj)
(TArrow (TArrow C C) TRcd_j).
(* Top->{k:A->A,j:B->B} <: (C->C)->{j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (subtyping_example_3) *)
Example subtyping_example_3 :
subtype (TArrow TRNil (TRCons j A TRNil))
(TArrow (TRCons k B TRNil) TRNil).
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (subtyping_example_4) *)
Example subtyping_example_4 :
subtype (TRCons x A (TRCons y B (TRCons z C TRNil)))
(TRCons z C (TRCons y B (TRCons x A TRNil))).
(* {x:A,y:B,z:C} <: {z:C,y:B,x:A} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples.
(* ================================================================= *)
(** ** Properties of Subtyping *)
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
(** To get started proving things about subtyping, we need a couple of
technical lemmas that intuitively (1) allow us to extract the
well-formedness assumptions embedded in subtyping derivations
and (2) record the fact that fields of well-formed record types
are themselves well-formed types. *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
induction Hsub;
intros; try (destruct IHHsub1; destruct IHHsub2)...
- (* S_RcdPerm *)
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
Tlookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
induction T; intros; try solve_by_invert.
- (* TRCons *)
inversion H. subst. unfold Tlookup in H0.
destruct (beq_id i i0)... inversion H0; subst... Qed.
(* ----------------------------------------------------------------- *)
(** *** Field Lookup *)
(** The record matching lemmas get a little more complicated in the
presence of subtyping, for two reasons. First, record types no
longer necessarily describe the exact structure of the
corresponding terms. And second, reasoning by induction on typing
derivations becomes harder in general, because typing is no longer
syntax directed. *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
Tlookup i T = Some Ti ->
exists Si, Tlookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
induction Hsub; intros Ti Hget;
try solve_by_invert.
- (* S_Refl *)
exists Ti...
- (* S_Trans *)
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
- (* S_RcdDepth *)
rename i0 into k.
unfold Tlookup. unfold Tlookup in Hget.
destruct (beq_id i k)...
+ (* i = k -- we're looking up the first field *)
inversion Hget. subst. exists S1...
- (* S_RcdPerm *)
exists Ti. split.
+ (* lookup *)
unfold Tlookup. unfold Tlookup in Hget.
destruct (beq_idP i i1)...
* (* i = i1 -- we're looking up the first field *)
destruct (beq_idP i i2)...
(* i = i2 -- contradictory *)
destruct H0.
subst...
+ (* subtype *)
inversion H. subst. inversion H5. subst... Qed.
(** **** Exercise: 3 stars (rcd_types_match_informal) *)
(** Write a careful informal proof of the [rcd_types_match]
lemma. *)
(* FILL IN HERE *)
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Inversion Lemmas *)
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (TArrow V1 V2) ->
exists U1, exists U2,
(U=(TArrow U1 U2)) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Typing *)
Definition context := partial_map ty.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
well_formed_ty T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
update Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in TArrow T1 T2 ->
Gamma |- t2 \in T1 ->
Gamma |- tapp t1 t2 \in T2
| T_Proj : forall Gamma i t T Ti,
Gamma |- t \in T ->
Tlookup i T = Some Ti ->
Gamma |- tproj t i \in Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
Gamma |- t \in S ->
subtype S T ->
Gamma |- t \in T
(* Rules for record terms *)
| T_RNil : forall Gamma,
Gamma |- trnil \in TRNil
| T_RCons : forall Gamma i t T tr Tr,
Gamma |- t \in T ->
Gamma |- tr \in Tr ->
record_ty Tr ->
record_tm tr ->
Gamma |- trcons i t tr \in TRCons i T Tr
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* ================================================================= *)
(** ** Typing Examples *)
Module Examples2.
Import Examples.
(** **** Exercise: 1 star (typing_example_0) *)
Definition trcd_kj :=
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil)).
Example typing_example_0 :
has_type empty
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil))
TRcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_1) *)
Example typing_example_1 :
has_type empty
(tapp (tabs x TRcd_j (tproj (tvar x) j))
(trcd_kj))
(TArrow B B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j)
{k=(\z:A.z), j=(\z:B.z)}
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_2) *)
Example typing_example_2 :
has_type empty
(tapp (tabs z (TArrow (TArrow C C) TRcd_j)
(tproj (tapp (tvar z)
(tabs x C (tvar x)))
j))
(tabs z (TArrow C C) trcd_kj))
(TArrow B B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples2.
(* ================================================================= *)
(** ** Properties of Typing *)
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
induction Htyp...
- (* T_App *)
inversion IHHtyp1...
- (* T_Proj *)
eapply wf_rcd_lookup...
- (* T_Sub *)
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr ==> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Field Lookup *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
has_type empty v T ->
Tlookup i T = Some Ti ->
exists vi, tlookup i v = Some vi /\ has_type empty vi Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. revert Ti HeqGamma Hval.
induction Htyp; intros; subst; try solve_by_invert.
- (* T_Sub *)
apply (rcd_types_match S) in H0...
destruct H0 as [Si [HgetSi Hsub]].
destruct (IHHtyp Si) as [vi [Hget Htyvi]]...
- (* T_RCons *)
simpl in H0. simpl. simpl in H1.
destruct (beq_id i i0).
+ (* i is first *)
inversion H1. subst. exists t...
+ (* i in tail *)
destruct (IHHtyp2 Ti) as [vi [get Htyvi]]...
inversion Hval... Qed.
(* ----------------------------------------------------------------- *)
(** *** Progress *)
(** **** Exercise: 3 stars (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
induction Ht;
intros HeqGamma; subst...
- (* T_Var *)
inversion H.
- (* T_App *)
right.
destruct IHHt1; subst...
+ (* t1 is a value *)
destruct IHHt2; subst...
* (* t2 is a value *)
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
* (* t2 steps *)
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_Proj *)
right. destruct IHHt...
+ (* rcd is value *)
destruct (lookup_field_in_value t T i Ti)
as [t' [Hget Ht']]...
+ (* rcd_steps *)
destruct H0 as [t' Hstp]. exists (tproj t' i)...
- (* T_RCons *)
destruct IHHt1...
+ (* head is a value *)
destruct IHHt2...
* (* tail steps *)
right. destruct H2 as [tr' Hstp].
exists (trcons i t tr')...
+ (* head steps *)
right. destruct H1 as [t' Hstp].
exists (trcons i t' tr)... Qed.
(** _Theorem_ : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t ==> t'] for some term [t'].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
proceed by induction on the given typing derivation.
- The cases where the last step in the typing derivation is
[T_Abs] or [T_RNil] are immediate because abstractions and
[{}] are always values. The case for [T_Var] is vacuous
because variables cannot be typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that [t =
t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 :
T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps.
- Suppose [t1 ==> t1'] for some term [t1']. Then [t1 t2 ==>
t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 ==> t2'] for some term [t2']. Then [t1 t2 ==>
t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By Lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for
some [x], [S1], and [s2]. But then [(\x:S1.s2) t2 ==>
[x:=t2]s2] by [ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
are a term [tr], a type [Tr], and a label [i] such that [t =
tr.i], [empty |- tr : Tr], and [Tlookup i Tr = Some T].
By the IH, either [tr] is a value or it steps. If [tr ==>
tr'] for some term [tr'], then [tr.i ==> tr'.i] by rule
[ST_Proj1].
If [tr] is a value, then Lemma [lookup_field_in_value] yields
that there is a term [ti] such that [tlookup i tr = Some ti].
It follows that [tr.i ==> ti] by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then
there exist some terms [t1] [tr], types [T1 Tr] and a label
[t] such that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm
tr], [record_tm Tr], [empty |- t1 : T1] and [empty |- tr :
Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then [{i=t1, tr}
==> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr ==> tr'] for some term [tr']. Then [{i=t1,
tr} ==> {i=t1, tr'}] by rule [ST_Rcd_Tail], since [t1] is
a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(* ----------------------------------------------------------------- *)
(** *** Inversion Lemmas *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tvar x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
induction Hty; intros;
inversion Heqt; subst; try solve_by_invert.
- (* T_Var *)
exists T...
- (* T_Sub *)
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tapp t1 t2) T2 ->
exists T1,
has_type Gamma t1 (TArrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
induction Hty; intros;
inversion Heqt; subst; try solve_by_invert.
- (* T_App *)
exists T1...
- (* T_Sub *)
destruct IHHty as [U1 [Hty1 Hty2]]...
assert (Hwf := has_type__wf _ _ _ Hty2).
exists U1... Qed.
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tabs x S1 t2) T ->
(exists S2, subtype (TArrow S1 S2) T
/\ has_type (update Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
induction H;
inversion Heqt; subst; intros; try solve_by_invert.
- (* T_Abs *)
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
- (* T_Sub *)
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma typing_inversion_proj : forall Gamma i t1 Ti,
has_type Gamma (tproj t1 i) Ti ->
exists T, exists Si,
Tlookup i T = Some Si /\ subtype Si Ti /\ has_type Gamma t1 T.
Proof with eauto.
intros Gamma i t1 Ti H.
remember (tproj t1 i) as t.
induction H;
inversion Heqt; subst; intros; try solve_by_invert.
- (* T_Proj *)
assert (well_formed_ty Ti) as Hwf.
{ (* pf of assertion *)
apply (wf_rcd_lookup i T Ti)...
apply has_type__wf in H... }
exists T. exists Ti...
- (* T_Sub *)
destruct IHhas_type as [U [Ui [Hget [Hsub Hty]]]]...
exists U. exists Ui... Qed.
Lemma typing_inversion_rcons : forall Gamma i ti tr T,
has_type Gamma (trcons i ti tr) T ->
exists Si, exists Sr,
subtype (TRCons i Si Sr) T /\ has_type Gamma ti Si /\
record_tm tr /\ has_type Gamma tr Sr.
Proof with eauto.
intros Gamma i ti tr T Hty.
remember (trcons i ti tr) as t.
induction Hty;
inversion Heqt; subst...
- (* T_Sub *)
apply IHHty in H0.
destruct H0 as [Ri [Rr [HsubRS [HtypRi HtypRr]]]].
exists Ri. exists Rr...
- (* T_RCons *)
assert (well_formed_ty (TRCons i T Tr)) as Hwf.
{ (* pf of assertion *)
apply has_type__wf in Hty1.
apply has_type__wf in Hty2... }
exists T. exists Tr... Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (update empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ----------------------------------------------------------------- *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_proj : forall x t i,
appears_free_in x t ->
appears_free_in x (tproj t i)
| afi_rhead : forall x i t tr,
appears_free_in x t ->
appears_free_in x (trcons i t tr)
| afi_rtail : forall x i t tr,
appears_free_in x tr ->
appears_free_in x (trcons i t tr).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold update, t_update. destruct (beq_idP x x0)...
- (* T_App *)
apply T_App with T1...
- (* T_RCons *)
apply T_RCons... Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; subst; inversion Hafi; subst...
- (* T_Abs *)
destruct (IHHtyp H5) as [T Hctx]. exists T.
unfold update, t_update in Hctx.
rewrite false_beq_id in Hctx... Qed.
(* ----------------------------------------------------------------- *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (update Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
induction t; intros; simpl.
- (* tvar *)
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt) as [T [Hctx Hsub]].
unfold update, t_update in Hctx.
destruct (beq_idP x y)...
+ (* x=y *)
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
destruct (subtype__wf _ _ Hsub)...
- (* tapp *)
destruct (typing_inversion_app _ _ _ _ Htypt)
as [T1 [Htypt1 Htypt2]].
eapply T_App...
- (* tabs *)
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
destruct (subtype__wf _ _ Hsub) as [Hwf1 Hwf2].
inversion Hwf2. subst.
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (beq_idP x y).
+ (* x=y *)
eapply context_invariance...
subst.
intros x Hafi. unfold update, t_update.
destruct (beq_id y x)...
+ (* x<>y *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z)...
subst. rewrite false_beq_id...
- (* tproj *)
destruct (typing_inversion_proj _ _ _ _ Htypt)
as [T [Ti [Hget [Hsub Htypt1]]]]...
- (* trnil *)
eapply context_invariance...
intros y Hcontra. inversion Hcontra.
- (* trcons *)
destruct (typing_inversion_rcons _ _ _ _ _ Htypt) as
[Ti [Tr [Hsub [HtypTi [Hrcdt2 HtypTr]]]]].
apply T_Sub with (TRCons i Ti Tr)...
apply T_RCons...
+ (* record_ty Tr *)
apply subtype__wf in Hsub. destruct Hsub. inversion H0...
+ (* record_tm ([x:=v]t2) *)
inversion Hrcdt2; subst; simpl... Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
inversion HE; subst...
+ (* ST_AppAbs *)
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
- (* T_Proj *)
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
- (* T_RCons *)
eauto using step_preserves_record_tm. Qed.
(** _Theorem_: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t ==> t'], then [empty |- t' : T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and [{}] don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [x:=t2]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [x:=t2] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr ==> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr.i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tlookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
(** $Date: 2016-10-19 09:26:05 -0400 (Wed, 19 Oct 2016) $ *)
|
module inputconditioner(clk, noisysignal, conditioned, positiveedge, negativeedge);
output reg conditioned = 0;
output reg positiveedge = 0;
output reg negativeedge = 0;
input clk, noisysignal;
// variables
parameter counterwidth = 5;
parameter waittime = 10;
reg[counterwidth-1:0] counter = 0;
reg sync0 = 0;
reg sync1 = 0;
always @(posedge clk) begin
// if last bit of buffer is the same as conditioned,
// no need to wait to see if change is consistent
if (conditioned == sync1) begin
counter <= 0;
positiveedge <= 0;
negativeedge <= 0;
// otherwise we check the counter
end else begin
// if the counter is at the end point, we approve this input
if (counter == waittime) begin
counter <= 0;
conditioned <= sync1;
// we know this is an edge--check if rising or falling
if (sync1 == 1) begin
positiveedge <= 1;
end else begin
negativeedge <= 1;
end
// otherwise we increment
end else begin
counter <= counter + 1;
end
end
sync1 = sync0;
sync0 = noisysignal;
end
endmodule
module testConditioner;
wire conditioned;
wire rising;
wire falling;
reg pin, clk;
reg ri;
always @(posedge clk) ri=rising;
inputconditioner dut(clk, pin, conditioned, rising, falling);
initial clk=0;
always #10 clk=!clk; // 50MHz Clock
initial begin
// Your Test Code
// Be sure to test each of the three things the conditioner does:
// Synchronize, Clean, Preprocess (edge finding)
$display("Test Edge Finding");
pin=0; #1010
$display("pin=0; #1010 | expect 0 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
pin=1; #20
$display("pin=1; #20 | expect 1 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
#240
$display("wait #240 | expect 1 1 1 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
#100
pin=0;
$display("wait #100 pin=0; | expect 0 1 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
#250
$display("wait #250 | expect 0 0 0 1");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
$display("----------------------------------------------------------");
$display("Test Cleaning");
#250
pin=1;
$display("wait #250 pin=1; | expect 1 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
#200
$display("wait #200 | expect 1 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
pin=0; #250
$display("pin=0; #250 | expect 0 0 0 0");
$display("pin: %b | conditioned: %b | rising: %b | falling: %b", pin, conditioned, rising, falling);
end
endmodule
|
module mac(
input wire reset,
// IN PORT
input wire [31:0] data_in,
input wire data_in_clock,
input wire data_in_enable,
input wire data_in_start,
input wire data_in_end,
// OUT PORT
output wire [31:0] data_out,
input wire data_out_clock,
input wire data_out_enable,
output wire data_out_start,
output wire data_out_end,
output wire [6:0] frame_count,
input wire tx_clock,
input wire rx_clock,
input wire carrier_sense,
input wire collision,
output wire tx_enable,
output wire [7:0] tx_data,
input wire rx_data_valid,
input wire [7:0] rx_data,
input wire rx_error
);
wire [7:0] tx_fifo_data;
wire tx_fifo_data_read;
wire tx_fifo_data_start;
wire tx_fifo_data_end;
wire [6:0] tx_fifo_count;
wire tx_fifo_retry;
wire [7:0] rx_fifo_data;
wire rx_fifo_data_write;
wire rx_fifo_data_start;
wire rx_fifo_data_end;
wire rx_fifo_full;
wire rx_fifo_error;
tx_sm U_tx_sm(
.reset(reset),
.clock(tx_clock),
.fifo_data(tx_fifo_data),
.fifo_data_read(tx_fifo_data_read),
.fifo_data_start(tx_fifo_data_start),
.fifo_data_end(tx_fifo_data_end),
.fifo_count(tx_fifo_count),
.fifo_retry(tx_fifo_retry),
.mode(1'b1),
.carrier_sense(carrier_sense),
.collision(collision),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
mac_fifo #(
.DATA_IN_WIDTH(32),
.DATA_OUT_WIDTH(8),
.FIFO_DEPTH(12)
) U_mac_fifo_tx (
.reset(reset),
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start),
.data_in_end(data_in_end),
.data_out(tx_fifo_data),
.data_out_clock(tx_clock),
.data_out_enable(tx_fifo_data_read),
.data_out_start(tx_fifo_data_start),
.data_out_end(tx_fifo_data_end),
.retry(tx_fifo_retry),
.error(1'b0),
.frame_count(tx_fifo_count)
);
rx_sm U_rx_sm(
.reset(reset),
.clock(rx_clock),
.fifo_data(rx_fifo_data),
.fifo_data_write(rx_fifo_data_write),
.fifo_data_start(rx_fifo_data_start),
.fifo_data_end(rx_fifo_data_end),
.fifo_full(rx_fifo_full),
.fifo_error(rx_fifo_error),
.rx_data_valid(rx_data_valid),
.rx_error(rx_error),
.rx_data(rx_data)
);
mac_fifo #(
.DATA_IN_WIDTH(8),
.DATA_OUT_WIDTH(32),
.FIFO_DEPTH(12)
) U_mac_fifo_rx (
.reset(reset),
.data_in(rx_fifo_data),
.data_in_clock(rx_clock),
.data_in_enable(rx_fifo_data_write),
.data_in_start(rx_fifo_data_start),
.data_in_end(rx_fifo_data_end),
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.retry(1'b0),
.error(rx_fifo_error),
.frame_count(frame_count)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_BEHAVIORAL_PP_V
|
//*************************************************************************
// > ÎļþÃû: adder_display.v
// > ÃèÊö £º¼Ó·¨Æ÷ÏÔʾģ¿é£¬µ÷ÓÃFPGA°åÉϵÄIO½Ó¿ÚºÍ´¥ÃþÆÁ
// > ×÷Õß : LOONGSON
// > ÈÕÆÚ : 2016-04-14
//*************************************************************************
module adder_display(
//ʱÖÓÓ븴λÐźÅ
input clk,
input resetn, //ºó׺"n"´ú±íµÍµçƽÓÐЧ
//²¦Â뿪¹Ø£¬ÓÃÓÚÑ¡ÔñÊäÈëÊýºÍ²úÉúcin
input input_sel, //0:ÊäÈëΪ¼ÓÊý1(add_operand1);1:ÊäÈëΪ¼ÓÊý2(add_operand2)
input sw_cin,
//ledµÆ£¬ÓÃÓÚÏÔʾcout
output led_cout,
//´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);
//-----{µ÷Óüӷ¨Ä£¿é}begin
reg [31:0] adder_operand1;
reg [31:0] adder_operand2;
wire adder_cin;
wire [31:0] adder_result ;
wire adder_cout;
adder adder_module(
.operand1(adder_operand1),
.operand2(adder_operand2),
.cin (adder_cin ),
.result (adder_result ),
.cout (adder_cout )
);
assign adder_cin = sw_cin;
assign led_cout = adder_cout;
//-----{µ÷Óüӷ¨Ä£¿é}end
//---------------------{µ÷Óô¥ÃþÆÁÄ£¿é}begin--------------------//
//-----{ʵÀý»¯´¥ÃþÆÁ}begin
//´ËС½Ú²»ÐèÒª¸ü¸Ä
reg display_valid;
reg [39:0] display_name;
reg [31:0] display_value;
wire [5 :0] display_number;
wire input_valid;
wire [31:0] input_value;
lcd_module lcd_module(
.clk (clk ), //10Mhz
.resetn (resetn ),
//µ÷Óô¥ÃþÆÁµÄ½Ó¿Ú
.display_valid (display_valid ),
.display_name (display_name ),
.display_value (display_value ),
.display_number (display_number),
.input_valid (input_valid ),
.input_value (input_value ),
//lcd´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
.lcd_rst (lcd_rst ),
.lcd_cs (lcd_cs ),
.lcd_rs (lcd_rs ),
.lcd_wr (lcd_wr ),
.lcd_rd (lcd_rd ),
.lcd_data_io (lcd_data_io ),
.lcd_bl_ctr (lcd_bl_ctr ),
.ct_int (ct_int ),
.ct_sda (ct_sda ),
.ct_scl (ct_scl ),
.ct_rstn (ct_rstn )
);
//-----{ʵÀý»¯´¥ÃþÆÁ}end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}begin
//¸ù¾Ýʵ¼ÊÐèÒªÊäÈëµÄÊýÐ޸ĴËС½Ú£¬
//½¨Òé¶Ôÿһ¸öÊýµÄÊäÈ룬±àдµ¥¶ÀÒ»¸öalways¿é
//µ±input_selΪ0ʱ£¬±íʾÊäÈëÊýΪ¼ÓÊý1£¬¼´operand1
always @(posedge clk)
begin
if (!resetn)
begin
adder_operand1 <= 32'd0;
end
else if (input_valid && !input_sel)
begin
adder_operand1 <= input_value;
end
end
//µ±input_selΪ1ʱ£¬±íʾÊäÈëÊýΪ¼ÓÊý2£¬¼´operand2
always @(posedge clk)
begin
if (!resetn)
begin
adder_operand2 <= 32'd0;
end
else if (input_valid && input_sel)
begin
adder_operand2 <= input_value;
end
end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}begin
//¸ù¾ÝÐèÒªÏÔʾµÄÊýÐ޸ĴËС½Ú£¬
//´¥ÃþÆÁÉϹ²ÓÐ44¿éÏÔʾÇøÓò£¬¿ÉÏÔʾ44×é32λÊý¾Ý
//44¿éÏÔʾÇøÓò´Ó1¿ªÊ¼±àºÅ£¬±àºÅΪ1~44£¬
always @(posedge clk)
begin
case(display_number)
6'd1 :
begin
display_valid <= 1'b1;
display_name <= "ADD_1";
display_value <= adder_operand1;
end
6'd2 :
begin
display_valid <= 1'b1;
display_name <= "ADD_2";
display_value <= adder_operand2;
end
6'd3 :
begin
display_valid <= 1'b1;
display_name <= "RESUL";
display_value <= adder_result;
end
default :
begin
display_valid <= 1'b0;
display_name <= 40'd0;
display_value <= 32'd0;
end
endcase
end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}end
//----------------------{µ÷Óô¥ÃþÆÁÄ£¿é}end---------------------//
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_2_V
`define SKY130_FD_SC_MS__O41A_2_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41a_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41a_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A32OI_BEHAVIORAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_BEHAVIORAL_V
|
`timescale 1 ns / 100 ps
`include "sm_cpu.vh"
module sm_testbench;
// simulation options
parameter Tt = 20;
parameter Ncycle = 120;
reg clk;
reg rst_n;
reg [ 4:0] regAddr;
wire [31:0] regData;
// ***** DUT start ************************
//instruction memory
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom reset_rom(imAddr, imData);
//cpu core
sm_cpu sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( regAddr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData )
);
// ***** DUT end ************************
`ifdef ICARUS
//iverilog memory dump init workaround
initial $dumpvars;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
initial $dumpvars(0, sm_cpu.rf.rf[k]);
end
`endif
// simulation init
initial begin
clk = 0;
forever clk = #(Tt/2) ~clk;
end
initial begin
rst_n = 0;
repeat (4) @(posedge clk);
rst_n = 1;
end
//register file reset
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
sm_cpu.rf.rf[i] = 0;
end
task disasmInstr
(
input [31:0] instr
);
reg [ 5:0] cmdOper;
reg [ 5:0] cmdFunk;
reg [ 4:0] cmdRs;
reg [ 4:0] cmdRt;
reg [ 4:0] cmdRd;
reg [ 4:0] cmdSa;
reg [15:0] cmdImm;
reg signed [15:0] cmdImmS;
begin
cmdOper = instr[31:26];
cmdFunk = instr[ 5:0 ];
cmdRs = instr[25:21];
cmdRt = instr[20:16];
cmdRd = instr[15:11];
cmdSa = instr[10:6 ];
cmdImm = instr[15:0 ];
cmdImmS = instr[15:0 ];
$write(" ");
casez( {cmdOper,cmdFunk} )
default : if (instr == 32'b0)
$write ("nop");
else
$write ("new/unknown");
{ `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
{ `C_SPEC, `F_SRLV } : $write ("srlv $%1d, $%1d, $%1d", cmdRd, cmdRt, cmdRs);
{ `C_BGEZ, `F_ANY } : $write ("bgez $%1d, %1d", cmdRt, cmdImm);
{ `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm);
{ `C_SPEC, `F_NOR } : $write ("nor $%1d, %1d", cmdRt, cmdImm);
{ `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
{ `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
endcase
end
endtask
//simulation debug output
integer cycle; initial cycle = 0;
initial regAddr = 0; // get PC
always @ (posedge clk)
begin
$write ("%5d pc = %2d pcaddr = %h instr = %h v0 = %1d",
cycle, regData, (regData << 2), sm_cpu.instr, sm_cpu.rf.rf[2]);
disasmInstr(sm_cpu.instr);
$write("\n");
cycle = cycle + 1;
if (cycle > Ncycle)
begin
$display ("Timeout");
$stop;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_2_V
`define SKY130_FD_SC_LP__O31A_2_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_2_V
|
//-----------------------------------------------------------------------------
// system_conware_0_wrapper.v
//-----------------------------------------------------------------------------
module system_conware_0_wrapper
(
ACLK,
ARESETN,
S_AXIS_TREADY,
S_AXIS_TDATA,
S_AXIS_TLAST,
S_AXIS_TVALID,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TLAST,
M_AXIS_TREADY,
M_AXIS_TKEEP,
M_AXIS_TSTRB,
in_states,
out_states,
num_reads,
num_writes,
read_ctr,
write_ctr
);
input ACLK;
input ARESETN;
output S_AXIS_TREADY;
input [31:0] S_AXIS_TDATA;
input S_AXIS_TLAST;
input S_AXIS_TVALID;
output M_AXIS_TVALID;
output [31:0] M_AXIS_TDATA;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
output [3:0] M_AXIS_TKEEP;
output [3:0] M_AXIS_TSTRB;
output [7:0] in_states;
output [7:0] out_states;
output [31:0] num_reads;
output [31:0] num_writes;
output [7:0] read_ctr;
output [7:0] write_ctr;
conware
conware_0 (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.S_AXIS_TREADY ( S_AXIS_TREADY ),
.S_AXIS_TDATA ( S_AXIS_TDATA ),
.S_AXIS_TLAST ( S_AXIS_TLAST ),
.S_AXIS_TVALID ( S_AXIS_TVALID ),
.M_AXIS_TVALID ( M_AXIS_TVALID ),
.M_AXIS_TDATA ( M_AXIS_TDATA ),
.M_AXIS_TLAST ( M_AXIS_TLAST ),
.M_AXIS_TREADY ( M_AXIS_TREADY ),
.M_AXIS_TKEEP ( M_AXIS_TKEEP ),
.M_AXIS_TSTRB ( M_AXIS_TSTRB ),
.in_states ( in_states ),
.out_states ( out_states ),
.num_reads ( num_reads ),
.num_writes ( num_writes ),
.read_ctr ( read_ctr ),
.write_ctr ( write_ctr )
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 21:26:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v
// Design : system_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[23:0]" */;
output [23:0]dout;
endmodule
|
/* Copyright 2005-2006, Technologic Systems
* All Rights Reserved.
*
* Author(s): Jesse Off <[email protected]>
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License v2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
module wb32_blockram(
wb_clk_i,
wb_rst_i,
wb1_adr_i,
wb1_dat_i,
wb1_dat_o,
wb1_cyc_i,
wb1_stb_i,
wb1_ack_o,
wb1_we_i,
wb1_sel_i,
wb2_adr_i,
wb2_dat_i,
wb2_dat_o,
wb2_cyc_i,
wb2_stb_i,
wb2_ack_o,
wb2_we_i,
wb2_sel_i
);
input wb_clk_i, wb_rst_i;
input [10:0] wb1_adr_i, wb2_adr_i;
input [31:0] wb1_dat_i, wb2_dat_i;
input wb1_cyc_i, wb2_cyc_i, wb1_stb_i, wb2_stb_i, wb1_we_i, wb2_we_i;
input [3:0] wb1_sel_i, wb2_sel_i;
output [31:0] wb1_dat_o, wb2_dat_o;
output reg wb1_ack_o, wb2_ack_o;
/* Set if wb1 and wb2 are opposite endianness */
parameter endian_swap = 1'b0;
reg [31:0] blockram_data_i;
reg [10:0] blockram_rdadr_i, blockram_wradr_i;
wire [31:0] blockram_data_o;
reg [3:0] blockram_wren;
altera_ram blockram0(
.clock(wb_clk_i),
.data(blockram_data_i[7:0]),
.rdaddress(blockram_rdadr_i),
.wraddress(blockram_wradr_i),
.wren(blockram_wren[0]),
.q(blockram_data_o[7:0])
);
altera_ram blockram1(
.clock(wb_clk_i),
.data(blockram_data_i[15:8]),
.rdaddress(blockram_rdadr_i),
.wraddress(blockram_wradr_i),
.wren(blockram_wren[1]),
.q(blockram_data_o[15:8])
);
altera_ram blockram2(
.clock(wb_clk_i),
.data(blockram_data_i[23:16]),
.rdaddress(blockram_rdadr_i),
.wraddress(blockram_wradr_i),
.wren(blockram_wren[2]),
.q(blockram_data_o[23:16])
);
altera_ram blockram3(
.clock(wb_clk_i),
.data(blockram_data_i[31:24]),
.rdaddress(blockram_rdadr_i),
.wraddress(blockram_wradr_i),
.wren(blockram_wren[3]),
.q(blockram_data_o[31:24])
);
reg rdowner = 1'b0;
reg wrowner = 1'b0;
reg wb1_rdreq, wb2_rdreq, wb1_wrreq, wb2_wrreq;
always @(rdowner or wrowner or wb1_adr_i or wb2_adr_i or wb1_dat_i or
wb2_dat_i or wb1_sel_i or wb2_sel_i or rdowner or wrowner or
wb2_wrreq or wb1_wrreq or endian_swap) begin
if (rdowner) blockram_rdadr_i = wb2_adr_i;
else blockram_rdadr_i = wb1_adr_i;
blockram_wren = 4'b0000;
if (wrowner) begin
blockram_wradr_i = wb2_adr_i;
if (endian_swap) begin
blockram_data_i = {wb2_dat_i[7:0], wb2_dat_i[15:8], wb2_dat_i[23:16],
wb2_dat_i[31:24]};
if (wb2_wrreq) blockram_wren = {wb2_sel_i[0], wb2_sel_i[1], wb2_sel_i[2],
wb2_sel_i[3]};
end else begin
blockram_data_i = wb2_dat_i;
if (wb2_wrreq) blockram_wren = wb2_sel_i;
end
end else begin
blockram_wradr_i = wb1_adr_i;
blockram_data_i = wb1_dat_i;
if (wb1_wrreq) blockram_wren = wb1_sel_i;
end
end
assign wb1_dat_o = blockram_data_o;
assign wb2_dat_o = endian_swap ? {blockram_data_o[7:0],
blockram_data_o[15:8], blockram_data_o[23:16], blockram_data_o[31:24]} :
blockram_data_o;
always @(wb1_cyc_i or wb1_stb_i or wb1_we_i or wb_rst_i or
wb2_cyc_i or wb2_stb_i or wb2_we_i or rdowner or wrowner or
wb1_ack_o or wb2_ack_o) begin
wb1_rdreq = wb1_cyc_i && wb1_stb_i && !wb1_we_i && !wb1_ack_o;
wb2_rdreq = wb2_cyc_i && wb2_stb_i && !wb2_we_i && !wb2_ack_o;
wb1_wrreq = wb1_cyc_i && wb1_stb_i && wb1_we_i && !wb1_ack_o;
wb2_wrreq = wb2_cyc_i && wb2_stb_i && wb2_we_i && !wb2_ack_o;
if (rdowner) begin
if (wb1_rdreq && !wb2_rdreq) rdowner = 1'b0;
else rdowner = 1'b1;
end else begin
if (!wb1_rdreq && wb2_rdreq) rdowner = 1'b1;
else rdowner = 1'b0;
end
if (wrowner) begin
if (wb1_wrreq && !wb2_wrreq) wrowner = 1'b0;
else wrowner = 1'b1;
end else begin
if (!wb1_wrreq && wb2_wrreq) wrowner = 1'b1;
else wrowner = 1'b0;
end
if (wb_rst_i) begin
rdowner = 1'b0;
wrowner = 1'b0;
end
end
always @(posedge wb_clk_i) begin
wb1_ack_o <= 1'b0;
wb2_ack_o <= 1'b0;
if (wb1_rdreq && !rdowner && !wb1_ack_o) begin
wb1_ack_o <= 1'b1;
end else if (wb2_rdreq && rdowner && !wb2_ack_o) begin
wb2_ack_o <= 1'b1;
end
if (wb1_wrreq && !wrowner && !wb1_ack_o) begin
wb1_ack_o <= 1'b1;
end else if (wb2_wrreq && wrowner && !wb2_ack_o) begin
wb2_ack_o <= 1'b1;
end
end
endmodule
|
///////////////// ** reset_ctrl ** //////////////////////////////////////////
//
// This module is clocked at 40MHz. It waits for a trigger pulse synchronous to
// 40MHz before initiating one of two reset routines
//
// idelay_rst_trig causes a reset of the idelayctrl and idelay instances. The idelayctrl
// is has its asynch reset held high for 3 cycles of 40MHz (75ns - the minimum reset time is 50ns)
// Both idelay resets are then asserted (synchronous to 40MHz as req'd) for a cycle
//
// The 200MHz clock used by idelayctrl is produced with a DCM and must be stable prior
// to reset. full_rst_trig causes the DCM to be reset first using its asynch reset line
// The DCM nominally takes 10ms to lock, after which the reset must be held for a further
// 200ms to ensure stability. The idelayctrl reset must be tied to the the DCMs locked signal
//
// 210ms = 8,400,000 cycles of 40MHz (24-bit counter)
module reset_ctrl(
input clk40,
input idelay_rst_trig,
input full_rst_trig,
output reg dcm_rst = 1'b0,
output reg idelay_rst = 1'b0
);
// Ports
/*input clk40;
input idelay_rst_trig;
input full_rst_trig;
output dcm_rst;
output idelay_rst;*/
// Internal registers
//reg dcm_rst;
//reg idelay_rst;
reg rst_flag = 1'b0;
reg [23:0] rst_count = 24'd0;
always @(posedge clk40) begin
if (rst_flag) begin
//Triggered
rst_count <= rst_count + 1'd1;
case (rst_count)
24'd0: begin
//Begin resetting DCM
dcm_rst <= 1'b1;
idelay_rst <= idelay_rst;
rst_flag <= rst_flag;
end
24'd8500000: begin
//212.5ms have passed. Stop reset then reset idelayctrl
dcm_rst <= 1'b0;
idelay_rst <= idelay_rst;
rst_flag <= rst_flag;
end
24'd8500010: begin
//idelayctrl is reset. Now do idelays
idelay_rst <= 1'b1;
dcm_rst <= dcm_rst;
rst_flag <= rst_flag;
end
24'd8500020: begin
//Finished
idelay_rst <= 1'b0;
dcm_rst <= dcm_rst;
rst_flag <= 1'b0;
end
endcase
end else begin
//Not triggered yet
if (idelay_rst_trig) begin
//Trigger partial reset
rst_flag <= 1'b1;
rst_count <= 24'd8500010;
idelay_rst <= idelay_rst;
dcm_rst <= dcm_rst;
end else begin
//Trigger full reset
if (full_rst_trig) begin
rst_flag <= 1'b1;
rst_count <= 24'd0;
idelay_rst <= idelay_rst;
dcm_rst <= dcm_rst;
end
end
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_dram_sc_bank1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//////////////////////////////////////////////////////////////////////
// Flop repeater for L2<-> dram controller signals.
// This repeter block has
// 8 row of data flops and 4 rows of ctl/addr flops.
// The 8 data rows are placed in one column ( 39 bits wide )
// the 4 addr/ctl rows are placed in one column ( 13 bits wide )
//////////////////////////////////////////////////////////////////////
module ff_dram_sc_bank1(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_d1, dram_scbuf_ecc_r2_d1,
scbuf_dram_wr_data_r5_d1, scbuf_dram_data_vld_r5_d1,
scbuf_dram_data_mecc_r5_d1, sctag_dram_rd_req_d1,
sctag_dram_rd_dummy_req_d1, sctag_dram_rd_req_id_d1,
sctag_dram_addr_d1, sctag_dram_wr_req_d1, dram_sctag_rd_ack_d1,
dram_sctag_wr_ack_d1, dram_sctag_chunk_id_r0_d1,
dram_sctag_data_vld_r0_d1, dram_sctag_rd_req_id_r0_d1,
dram_sctag_secc_err_r2_d1, dram_sctag_mecc_err_r2_d1,
dram_sctag_scb_mecc_err_d1, dram_sctag_scb_secc_err_d1, so,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err, rclk, si, se
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_d1;
output [27:0] dram_scbuf_ecc_r2_d1;
// scbuf to dram BOTTOM
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// TOP
output [63:0] scbuf_dram_wr_data_r5_d1;
output scbuf_dram_data_vld_r5_d1;
output scbuf_dram_data_mecc_r5_d1;
// sctag_dram-sctag signals INputs
// @ the bottom.
// Outputs @ the top.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
//
output sctag_dram_rd_req_d1;
output sctag_dram_rd_dummy_req_d1;
output [2:0] sctag_dram_rd_req_id_d1;
output [39:5] sctag_dram_addr_d1;
output sctag_dram_wr_req_d1;
// dram-sctag signals. Outputs @ bottom
// and Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
//
output dram_sctag_rd_ack_d1;
output dram_sctag_wr_ack_d1;
output [1:0] dram_sctag_chunk_id_r0_d1;
output dram_sctag_data_vld_r0_d1;
output [2:0] dram_sctag_rd_req_id_r0_d1;
output dram_sctag_secc_err_r2_d1 ;
output dram_sctag_mecc_err_r2_d1 ;
output dram_sctag_scb_mecc_err_d1;
output dram_sctag_scb_secc_err_d1;
input rclk;
input si, se;
output so;
// dram-scbuf signals. 8 rows of flops.
// Input at the top and output at the bottom.
dff_s #(39) ff_flop_bank0_row_0 (.q({dram_scbuf_data_r2_d1[127],
dram_scbuf_data_r2_d1[123],
dram_scbuf_data_r2_d1[119],
dram_scbuf_data_r2_d1[115],
dram_scbuf_data_r2_d1[111],
dram_scbuf_data_r2_d1[107],
dram_scbuf_data_r2_d1[103],
dram_scbuf_data_r2_d1[99],
dram_scbuf_data_r2_d1[95],
dram_scbuf_data_r2_d1[91],
dram_scbuf_data_r2_d1[87],
dram_scbuf_data_r2_d1[83],
dram_scbuf_data_r2_d1[79],
dram_scbuf_data_r2_d1[75],
dram_scbuf_data_r2_d1[71],
dram_scbuf_data_r2_d1[67],
dram_scbuf_data_r2_d1[63],
dram_scbuf_data_r2_d1[59],
dram_scbuf_data_r2_d1[55],
dram_scbuf_data_r2_d1[51],
dram_scbuf_data_r2_d1[47],
dram_scbuf_data_r2_d1[43],
dram_scbuf_data_r2_d1[39],
dram_scbuf_data_r2_d1[35],
dram_scbuf_data_r2_d1[31],
dram_scbuf_data_r2_d1[27],
dram_scbuf_data_r2_d1[23],
dram_scbuf_data_r2_d1[19],
dram_scbuf_data_r2_d1[15],
dram_scbuf_data_r2_d1[11],
dram_scbuf_data_r2_d1[7],
dram_scbuf_data_r2_d1[3],
dram_scbuf_ecc_r2_d1[27],
dram_scbuf_ecc_r2_d1[23],
dram_scbuf_ecc_r2_d1[19],
dram_scbuf_ecc_r2_d1[15],
dram_scbuf_ecc_r2_d1[11],
dram_scbuf_ecc_r2_d1[7],
dram_scbuf_ecc_r2_d1[3] }),
.din({dram_scbuf_data_r2[127],
dram_scbuf_data_r2[123],
dram_scbuf_data_r2[119],
dram_scbuf_data_r2[115],
dram_scbuf_data_r2[111],
dram_scbuf_data_r2[107],
dram_scbuf_data_r2[103],
dram_scbuf_data_r2[99],
dram_scbuf_data_r2[95],
dram_scbuf_data_r2[91],
dram_scbuf_data_r2[87],
dram_scbuf_data_r2[83],
dram_scbuf_data_r2[79],
dram_scbuf_data_r2[75],
dram_scbuf_data_r2[71],
dram_scbuf_data_r2[67],
dram_scbuf_data_r2[63],
dram_scbuf_data_r2[59],
dram_scbuf_data_r2[55],
dram_scbuf_data_r2[51],
dram_scbuf_data_r2[47],
dram_scbuf_data_r2[43],
dram_scbuf_data_r2[39],
dram_scbuf_data_r2[35],
dram_scbuf_data_r2[31],
dram_scbuf_data_r2[27],
dram_scbuf_data_r2[23],
dram_scbuf_data_r2[19],
dram_scbuf_data_r2[15],
dram_scbuf_data_r2[11],
dram_scbuf_data_r2[7],
dram_scbuf_data_r2[3],
dram_scbuf_ecc_r2[27],
dram_scbuf_ecc_r2[23],
dram_scbuf_ecc_r2[19],
dram_scbuf_ecc_r2[15],
dram_scbuf_ecc_r2[11],
dram_scbuf_ecc_r2[7],
dram_scbuf_ecc_r2[3]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_1 (.q({dram_scbuf_data_r2_d1[126],
dram_scbuf_data_r2_d1[122],
dram_scbuf_data_r2_d1[118],
dram_scbuf_data_r2_d1[114],
dram_scbuf_data_r2_d1[110],
dram_scbuf_data_r2_d1[106],
dram_scbuf_data_r2_d1[102],
dram_scbuf_data_r2_d1[98],
dram_scbuf_data_r2_d1[94],
dram_scbuf_data_r2_d1[90],
dram_scbuf_data_r2_d1[86],
dram_scbuf_data_r2_d1[82],
dram_scbuf_data_r2_d1[78],
dram_scbuf_data_r2_d1[74],
dram_scbuf_data_r2_d1[70],
dram_scbuf_data_r2_d1[66],
dram_scbuf_data_r2_d1[62],
dram_scbuf_data_r2_d1[58],
dram_scbuf_data_r2_d1[54],
dram_scbuf_data_r2_d1[50],
dram_scbuf_data_r2_d1[46],
dram_scbuf_data_r2_d1[42],
dram_scbuf_data_r2_d1[38],
dram_scbuf_data_r2_d1[34],
dram_scbuf_data_r2_d1[30],
dram_scbuf_data_r2_d1[26],
dram_scbuf_data_r2_d1[22],
dram_scbuf_data_r2_d1[18],
dram_scbuf_data_r2_d1[14],
dram_scbuf_data_r2_d1[10],
dram_scbuf_data_r2_d1[6],
dram_scbuf_data_r2_d1[2],
dram_scbuf_ecc_r2_d1[26],
dram_scbuf_ecc_r2_d1[22],
dram_scbuf_ecc_r2_d1[18],
dram_scbuf_ecc_r2_d1[14],
dram_scbuf_ecc_r2_d1[10],
dram_scbuf_ecc_r2_d1[6],
dram_scbuf_ecc_r2_d1[2] }),
.din({dram_scbuf_data_r2[126],
dram_scbuf_data_r2[122],
dram_scbuf_data_r2[118],
dram_scbuf_data_r2[114],
dram_scbuf_data_r2[110],
dram_scbuf_data_r2[106],
dram_scbuf_data_r2[102],
dram_scbuf_data_r2[98],
dram_scbuf_data_r2[94],
dram_scbuf_data_r2[90],
dram_scbuf_data_r2[86],
dram_scbuf_data_r2[82],
dram_scbuf_data_r2[78],
dram_scbuf_data_r2[74],
dram_scbuf_data_r2[70],
dram_scbuf_data_r2[66],
dram_scbuf_data_r2[62],
dram_scbuf_data_r2[58],
dram_scbuf_data_r2[54],
dram_scbuf_data_r2[50],
dram_scbuf_data_r2[46],
dram_scbuf_data_r2[42],
dram_scbuf_data_r2[38],
dram_scbuf_data_r2[34],
dram_scbuf_data_r2[30],
dram_scbuf_data_r2[26],
dram_scbuf_data_r2[22],
dram_scbuf_data_r2[18],
dram_scbuf_data_r2[14],
dram_scbuf_data_r2[10],
dram_scbuf_data_r2[6],
dram_scbuf_data_r2[2],
dram_scbuf_ecc_r2[26],
dram_scbuf_ecc_r2[22],
dram_scbuf_ecc_r2[18],
dram_scbuf_ecc_r2[14],
dram_scbuf_ecc_r2[10],
dram_scbuf_ecc_r2[6],
dram_scbuf_ecc_r2[2]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_2 (.q({dram_scbuf_data_r2_d1[125],
dram_scbuf_data_r2_d1[121],
dram_scbuf_data_r2_d1[117],
dram_scbuf_data_r2_d1[113],
dram_scbuf_data_r2_d1[109],
dram_scbuf_data_r2_d1[105],
dram_scbuf_data_r2_d1[101],
dram_scbuf_data_r2_d1[97],
dram_scbuf_data_r2_d1[93],
dram_scbuf_data_r2_d1[89],
dram_scbuf_data_r2_d1[85],
dram_scbuf_data_r2_d1[81],
dram_scbuf_data_r2_d1[77],
dram_scbuf_data_r2_d1[73],
dram_scbuf_data_r2_d1[69],
dram_scbuf_data_r2_d1[65],
dram_scbuf_data_r2_d1[61],
dram_scbuf_data_r2_d1[57],
dram_scbuf_data_r2_d1[53],
dram_scbuf_data_r2_d1[49],
dram_scbuf_data_r2_d1[45],
dram_scbuf_data_r2_d1[41],
dram_scbuf_data_r2_d1[37],
dram_scbuf_data_r2_d1[33],
dram_scbuf_data_r2_d1[29],
dram_scbuf_data_r2_d1[25],
dram_scbuf_data_r2_d1[21],
dram_scbuf_data_r2_d1[17],
dram_scbuf_data_r2_d1[13],
dram_scbuf_data_r2_d1[9],
dram_scbuf_data_r2_d1[5],
dram_scbuf_data_r2_d1[1],
dram_scbuf_ecc_r2_d1[25],
dram_scbuf_ecc_r2_d1[21],
dram_scbuf_ecc_r2_d1[17],
dram_scbuf_ecc_r2_d1[13],
dram_scbuf_ecc_r2_d1[9],
dram_scbuf_ecc_r2_d1[5],
dram_scbuf_ecc_r2_d1[1] }),
.din({dram_scbuf_data_r2[125],
dram_scbuf_data_r2[121],
dram_scbuf_data_r2[117],
dram_scbuf_data_r2[113],
dram_scbuf_data_r2[109],
dram_scbuf_data_r2[105],
dram_scbuf_data_r2[101],
dram_scbuf_data_r2[97],
dram_scbuf_data_r2[93],
dram_scbuf_data_r2[89],
dram_scbuf_data_r2[85],
dram_scbuf_data_r2[81],
dram_scbuf_data_r2[77],
dram_scbuf_data_r2[73],
dram_scbuf_data_r2[69],
dram_scbuf_data_r2[65],
dram_scbuf_data_r2[61],
dram_scbuf_data_r2[57],
dram_scbuf_data_r2[53],
dram_scbuf_data_r2[49],
dram_scbuf_data_r2[45],
dram_scbuf_data_r2[41],
dram_scbuf_data_r2[37],
dram_scbuf_data_r2[33],
dram_scbuf_data_r2[29],
dram_scbuf_data_r2[25],
dram_scbuf_data_r2[21],
dram_scbuf_data_r2[17],
dram_scbuf_data_r2[13],
dram_scbuf_data_r2[9],
dram_scbuf_data_r2[5],
dram_scbuf_data_r2[1],
dram_scbuf_ecc_r2[25],
dram_scbuf_ecc_r2[21],
dram_scbuf_ecc_r2[17],
dram_scbuf_ecc_r2[13],
dram_scbuf_ecc_r2[9],
dram_scbuf_ecc_r2[5],
dram_scbuf_ecc_r2[1]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_3 (.q({dram_scbuf_data_r2_d1[124],
dram_scbuf_data_r2_d1[120],
dram_scbuf_data_r2_d1[116],
dram_scbuf_data_r2_d1[112],
dram_scbuf_data_r2_d1[108],
dram_scbuf_data_r2_d1[104],
dram_scbuf_data_r2_d1[100],
dram_scbuf_data_r2_d1[96],
dram_scbuf_data_r2_d1[92],
dram_scbuf_data_r2_d1[88],
dram_scbuf_data_r2_d1[84],
dram_scbuf_data_r2_d1[80],
dram_scbuf_data_r2_d1[76],
dram_scbuf_data_r2_d1[72],
dram_scbuf_data_r2_d1[68],
dram_scbuf_data_r2_d1[64],
dram_scbuf_data_r2_d1[60],
dram_scbuf_data_r2_d1[56],
dram_scbuf_data_r2_d1[52],
dram_scbuf_data_r2_d1[48],
dram_scbuf_data_r2_d1[44],
dram_scbuf_data_r2_d1[40],
dram_scbuf_data_r2_d1[36],
dram_scbuf_data_r2_d1[32],
dram_scbuf_data_r2_d1[28],
dram_scbuf_data_r2_d1[24],
dram_scbuf_data_r2_d1[20],
dram_scbuf_data_r2_d1[16],
dram_scbuf_data_r2_d1[12],
dram_scbuf_data_r2_d1[8],
dram_scbuf_data_r2_d1[4],
dram_scbuf_data_r2_d1[0],
dram_scbuf_ecc_r2_d1[24],
dram_scbuf_ecc_r2_d1[20],
dram_scbuf_ecc_r2_d1[16],
dram_scbuf_ecc_r2_d1[12],
dram_scbuf_ecc_r2_d1[8],
dram_scbuf_ecc_r2_d1[4],
dram_scbuf_ecc_r2_d1[0] }),
.din({dram_scbuf_data_r2[124],
dram_scbuf_data_r2[120],
dram_scbuf_data_r2[116],
dram_scbuf_data_r2[112],
dram_scbuf_data_r2[108],
dram_scbuf_data_r2[104],
dram_scbuf_data_r2[100],
dram_scbuf_data_r2[96],
dram_scbuf_data_r2[92],
dram_scbuf_data_r2[88],
dram_scbuf_data_r2[84],
dram_scbuf_data_r2[80],
dram_scbuf_data_r2[76],
dram_scbuf_data_r2[72],
dram_scbuf_data_r2[68],
dram_scbuf_data_r2[64],
dram_scbuf_data_r2[60],
dram_scbuf_data_r2[56],
dram_scbuf_data_r2[52],
dram_scbuf_data_r2[48],
dram_scbuf_data_r2[44],
dram_scbuf_data_r2[40],
dram_scbuf_data_r2[36],
dram_scbuf_data_r2[32],
dram_scbuf_data_r2[28],
dram_scbuf_data_r2[24],
dram_scbuf_data_r2[20],
dram_scbuf_data_r2[16],
dram_scbuf_data_r2[12],
dram_scbuf_data_r2[8],
dram_scbuf_data_r2[4],
dram_scbuf_data_r2[0],
dram_scbuf_ecc_r2[24],
dram_scbuf_ecc_r2[20],
dram_scbuf_ecc_r2[16],
dram_scbuf_ecc_r2[12],
dram_scbuf_ecc_r2[8],
dram_scbuf_ecc_r2[4],
dram_scbuf_ecc_r2[0]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_bank0_row_4 (.q({scbuf_dram_wr_data_r5_d1[63],
scbuf_dram_wr_data_r5_d1[61],
scbuf_dram_wr_data_r5_d1[59],
scbuf_dram_wr_data_r5_d1[57],
scbuf_dram_wr_data_r5_d1[55],
scbuf_dram_wr_data_r5_d1[53],
scbuf_dram_wr_data_r5_d1[51],
scbuf_dram_wr_data_r5_d1[49],
scbuf_dram_wr_data_r5_d1[47],
scbuf_dram_wr_data_r5_d1[45],
scbuf_dram_wr_data_r5_d1[43],
scbuf_dram_wr_data_r5_d1[41],
scbuf_dram_wr_data_r5_d1[39],
scbuf_dram_wr_data_r5_d1[37],
scbuf_dram_wr_data_r5_d1[35],
scbuf_dram_wr_data_r5_d1[33],
scbuf_dram_wr_data_r5_d1[31],
scbuf_dram_wr_data_r5_d1[29],
scbuf_dram_wr_data_r5_d1[27],
scbuf_dram_wr_data_r5_d1[25],
scbuf_dram_wr_data_r5_d1[23],
scbuf_dram_wr_data_r5_d1[21],
scbuf_dram_wr_data_r5_d1[19],
scbuf_dram_wr_data_r5_d1[17],
scbuf_dram_wr_data_r5_d1[15],
scbuf_dram_wr_data_r5_d1[13],
scbuf_dram_wr_data_r5_d1[11],
scbuf_dram_wr_data_r5_d1[9],
scbuf_dram_wr_data_r5_d1[7],
scbuf_dram_wr_data_r5_d1[5],
scbuf_dram_wr_data_r5_d1[3],
scbuf_dram_wr_data_r5_d1[1]} ),
.din({scbuf_dram_wr_data_r5[63],
scbuf_dram_wr_data_r5[61],
scbuf_dram_wr_data_r5[59],
scbuf_dram_wr_data_r5[57],
scbuf_dram_wr_data_r5[55],
scbuf_dram_wr_data_r5[53],
scbuf_dram_wr_data_r5[51],
scbuf_dram_wr_data_r5[49],
scbuf_dram_wr_data_r5[47],
scbuf_dram_wr_data_r5[45],
scbuf_dram_wr_data_r5[43],
scbuf_dram_wr_data_r5[41],
scbuf_dram_wr_data_r5[39],
scbuf_dram_wr_data_r5[37],
scbuf_dram_wr_data_r5[35],
scbuf_dram_wr_data_r5[33],
scbuf_dram_wr_data_r5[31],
scbuf_dram_wr_data_r5[29],
scbuf_dram_wr_data_r5[27],
scbuf_dram_wr_data_r5[25],
scbuf_dram_wr_data_r5[23],
scbuf_dram_wr_data_r5[21],
scbuf_dram_wr_data_r5[19],
scbuf_dram_wr_data_r5[17],
scbuf_dram_wr_data_r5[15],
scbuf_dram_wr_data_r5[13],
scbuf_dram_wr_data_r5[11],
scbuf_dram_wr_data_r5[9],
scbuf_dram_wr_data_r5[7],
scbuf_dram_wr_data_r5[5],
scbuf_dram_wr_data_r5[3],
scbuf_dram_wr_data_r5[1]} ),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(34) ff_bank0_row_5 (.q({scbuf_dram_wr_data_r5_d1[62],
scbuf_dram_wr_data_r5_d1[60],
scbuf_dram_wr_data_r5_d1[58],
scbuf_dram_wr_data_r5_d1[56],
scbuf_dram_wr_data_r5_d1[54],
scbuf_dram_wr_data_r5_d1[52],
scbuf_dram_wr_data_r5_d1[50],
scbuf_dram_wr_data_r5_d1[48],
scbuf_dram_wr_data_r5_d1[46],
scbuf_dram_wr_data_r5_d1[44],
scbuf_dram_wr_data_r5_d1[42],
scbuf_dram_wr_data_r5_d1[40],
scbuf_dram_wr_data_r5_d1[38],
scbuf_dram_wr_data_r5_d1[36],
scbuf_dram_wr_data_r5_d1[34],
scbuf_dram_wr_data_r5_d1[32],
scbuf_dram_wr_data_r5_d1[30],
scbuf_dram_wr_data_r5_d1[28],
scbuf_dram_wr_data_r5_d1[26],
scbuf_dram_wr_data_r5_d1[24],
scbuf_dram_wr_data_r5_d1[22],
scbuf_dram_wr_data_r5_d1[20],
scbuf_dram_wr_data_r5_d1[18],
scbuf_dram_wr_data_r5_d1[16],
scbuf_dram_wr_data_r5_d1[14],
scbuf_dram_wr_data_r5_d1[12],
scbuf_dram_wr_data_r5_d1[10],
scbuf_dram_wr_data_r5_d1[8],
scbuf_dram_wr_data_r5_d1[6],
scbuf_dram_wr_data_r5_d1[4],
scbuf_dram_wr_data_r5_d1[2],
scbuf_dram_wr_data_r5_d1[0],
scbuf_dram_data_mecc_r5_d1,
scbuf_dram_data_vld_r5_d1
} ),
.din({scbuf_dram_wr_data_r5[62],
scbuf_dram_wr_data_r5[60],
scbuf_dram_wr_data_r5[58],
scbuf_dram_wr_data_r5[56],
scbuf_dram_wr_data_r5[54],
scbuf_dram_wr_data_r5[52],
scbuf_dram_wr_data_r5[50],
scbuf_dram_wr_data_r5[48],
scbuf_dram_wr_data_r5[46],
scbuf_dram_wr_data_r5[44],
scbuf_dram_wr_data_r5[42],
scbuf_dram_wr_data_r5[40],
scbuf_dram_wr_data_r5[38],
scbuf_dram_wr_data_r5[36],
scbuf_dram_wr_data_r5[34],
scbuf_dram_wr_data_r5[32],
scbuf_dram_wr_data_r5[30],
scbuf_dram_wr_data_r5[28],
scbuf_dram_wr_data_r5[26],
scbuf_dram_wr_data_r5[24],
scbuf_dram_wr_data_r5[22],
scbuf_dram_wr_data_r5[20],
scbuf_dram_wr_data_r5[18],
scbuf_dram_wr_data_r5[16],
scbuf_dram_wr_data_r5[14],
scbuf_dram_wr_data_r5[12],
scbuf_dram_wr_data_r5[10],
scbuf_dram_wr_data_r5[8],
scbuf_dram_wr_data_r5[6],
scbuf_dram_wr_data_r5[4],
scbuf_dram_wr_data_r5[2],
scbuf_dram_wr_data_r5[0],
scbuf_dram_data_mecc_r5,
scbuf_dram_data_vld_r5 }),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(41) ff_flop_bank0_col1_row012 (.q({sctag_dram_addr_d1[39:5],
sctag_dram_rd_req_id_d1[2:0],
sctag_dram_wr_req_d1,
sctag_dram_rd_dummy_req_d1,
sctag_dram_rd_req_d1}),
.din({sctag_dram_addr[39:5],
sctag_dram_rd_req_id[2:0],
sctag_dram_wr_req,
sctag_dram_rd_dummy_req,
sctag_dram_rd_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(12) ff_flop_bank0_col1_row3 (.q({dram_sctag_rd_ack_d1,
dram_sctag_wr_ack_d1,
dram_sctag_chunk_id_r0_d1[1:0],
dram_sctag_data_vld_r0_d1,
dram_sctag_rd_req_id_r0_d1[2:0],
dram_sctag_secc_err_r2_d1,
dram_sctag_mecc_err_r2_d1,
dram_sctag_scb_mecc_err_d1,
dram_sctag_scb_secc_err_d1}),
.din({dram_sctag_rd_ack,
dram_sctag_wr_ack,
dram_sctag_chunk_id_r0[1:0],
dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0[2:0],
dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2,
dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_TB_V
`define SKY130_FD_SC_LS__SDFSTP_TB_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:38:42 03/10/2014
// Design Name:
// Module Name: Runs
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// m - files: runs_limits.m
//
//////////////////////////////////////////////////////////////////////////////////
module Runs(
input wire clk,
input wire rst,
input wire rand,
output wire pass
);
parameter N = 20000;
reg [14:0] count_bits0, count_bits1, count_ones, count_runs;
reg rand1;
wire en;
wire p_1, p_2;
assign en = (count_bits1 == (N-1));
assign pass = p_1 & p_2;
decision decision(
.clk(clk),
.rst(rst),
.en(en),
.count_ones(count_ones),
.count_runs(count_runs),
.p_1(p_1),
.p_2(p_2)
);
always @(posedge clk)
if (rst) begin
count_bits0 <= 15'H7FFF;
count_bits1 <= 0;
count_ones <= 0;
count_runs <= 1;
rand1 <= 0;
end
else begin
rand1 <= rand;
count_bits0 <= count_bits0 + 1;
count_bits1 <= count_bits0;
if (count_bits0 == (N-1)) begin
count_bits0 <= 0;
end
if (rand) count_ones <= count_ones + 1;
if (rand1^rand) count_runs <= count_runs + 1;
if (count_bits1 == (N-1)) begin
count_ones <= rand;
count_runs <= rand1^rand + 1;
/* if ((count_ones <= U) && (count_ones >= L)) pass <= 1;
else pass <= 0;*/
end
end
/*parameter N = 8;
reg [14:0] count_bits, count_ones, count_runs;
reg rand1, p_1, p_2;
assign pass = p_1&p_2;
always @(posedge clk) begin
rand1 <= rand;
if (rst) begin
count_bits <= 0;
count_ones <= 0;
count_runs <= 0;
p_1 <= 1;
p_2 <= 1;
end
else begin
count_bits <= count_bits + 1;
if (rand) count_ones <= count_ones + 1;
if (rand1^rand) count_runs <= count_runs + 1;
if (count_bits == (N-1)) begin
count_bits <= 0;
count_ones <= 0;
count_runs <= 0;
end
end
end*/
endmodule
module decision (
input wire clk,
input wire rst,
input wire en,
input wire [14:0] count_ones,
input wire [14:0] count_runs,
output reg p_1, p_2
);
always @(posedge clk)
if (rst) begin
p_1 <= 0;
p_2 <= 0;
end
else begin
if(en)begin
// check upper limit
/*
count_ones 9818 9840 9874 9921 10080 10127 10161 10182
count_runs:max 10179 10180 10181 10182 10181 10180 10179
*/
if (count_ones < 9818)
p_1 <= 0;
else if (count_ones < 9840) begin
if (count_runs > 10179) p_1 <= 0;
else p_1 <= 1;
end
else if (count_ones < 9874) begin
if (count_runs > 10180) p_1 <= 0;
else p_1 <= 1;
end
else if (count_ones < 9921) begin
if (count_runs > 10181) p_1 <= 0;
else p_1 <= 1;
end
else if (count_ones < 10080) begin
if (count_runs > 10182) p_1 <= 0;
else p_1 <= 1;
end
else if (count_ones < 10127) begin
if (count_runs > 10181) p_1 <= 0;
else p_1 <= 1;
end
else if (count_ones <10161) begin
if (count_runs > 10180) p_1 <= 0;
else p_1 <= 1;
end
else if (count_ones <10182) begin
if (count_runs > 10179) p_1 <= 0;
else p_1 <= 1;
end
else
p_1 <= 0;
// check lower limit
/*
count_ones 9818 9845 9883 9940 10061 10118 10156 10182
count_runs:min 9815 9816 9817 9818 9817 9816 9815
*/
if (count_ones < 9818)
p_2 <= 0;
else if (count_ones < 9845) begin
if (count_runs < 9815) p_2 <= 0;
else p_2 <= 1;
end
else if (count_ones < 9883) begin
if (count_runs < 9816) p_2 <= 0;
else p_2 <= 1;
end
else if (count_ones < 9940) begin
if (count_runs < 9817) p_2 <= 0;
else p_2 <= 1;
end
else if (count_ones < 10061) begin
if (count_runs < 9818) p_2 <= 0;
else p_2 <= 1;
end
else if (count_ones < 10118) begin
if (count_runs < 9817) p_2 <= 0;
else p_2 <= 1;
end
else if (count_ones < 10156) begin
if (count_runs < 9816) p_2 <= 0;
else p_2 <= 1;
end
else if (count_ones <10182) begin
if (count_runs < 9815) p_2 <= 0;
else p_2 <= 1;
end
else
p_2 <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:26:25 11/01/2013
// Design Name:
// Module Name: i2s_out
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module i2s_out(input clock, input reset, input[15:0] left_data,
input[15:0] right_data, output mclk, output lrck, output sclk, output reg sdin);
wire[5:0] sclk_counter = 6'd1; // 2 - 1
wire[5:0] lrck_counter = 6'd63; // 64 - 1
reg [3:0] data_pos;
initial
begin
data_pos <= 4'b0000;
end
/** mclk es igual al clock . 50Mhz */
assign mclk = clock;
/** mclk/lrck = 64 entonces lrck se hace de 781250Hz */
clock_divider lrck_gen(
.clock(clock),
.reset(reset),
.counter(lrck_counter),
.clock_out(lrck)
);
/** sclk/lrck = 32 y mclk/sclk = 2. Entonces sclk = 25Mhz*/
clock_divider sclk_gen(
.clock(clock),
.reset(reset),
.counter(sclk_counter),
.clock_out(sclk)
);
/**
* flanco positivo de lrck = canal derecho
* flanco negativo de lrck = canal izquierdo
* los datos se mandan con sclk
**/
always @ (negedge sclk)
begin
if(lrck)
begin
if(data_pos == 4'b0000)
begin
sdin <= left_data[data_pos];
end
else
begin
sdin <= right_data[data_pos];
end
end
else
begin
if(data_pos == 4'b0000)
begin
sdin <= right_data[data_pos];
end
else
begin
sdin <= left_data[data_pos];
end
end
/** Siempre hay que cambiar la posicion */
data_pos <= data_pos - 1;
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:08:04 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "zqynq_lab_1_design_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "zqynq_lab_1_design_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// valid O 1
// addr O 32 reg
// word64 O 64
// st_amo_val O 64
// exc O 1
// exc_code O 4 reg
// RDY_server_flush_request_put O 1 reg
// RDY_server_flush_response_get O 1
// RDY_tlb_flush O 1 const
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_op I 2
// req_f3 I 3
// req_amo_funct7 I 7 reg
// req_addr I 32
// req_st_value I 64
// req_priv I 2 unused
// req_sstatus_SUM I 1 unused
// req_mstatus_MXR I 1 unused
// req_satp I 32 unused
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// EN_set_verbosity I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
// EN_server_flush_request_put I 1
// EN_server_flush_response_get I 1
// EN_tlb_flush I 1 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMMU_Cache(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_op,
req_f3,
req_amo_funct7,
req_addr,
req_st_value,
req_priv,
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
EN_req,
valid,
addr,
word64,
st_amo_val,
exc,
exc_code,
EN_server_flush_request_put,
RDY_server_flush_request_put,
EN_server_flush_response_get,
RDY_server_flush_response_get,
EN_tlb_flush,
RDY_tlb_flush,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready);
parameter [0 : 0] dmem_not_imem = 1'b0;
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [1 : 0] req_op;
input [2 : 0] req_f3;
input [6 : 0] req_amo_funct7;
input [31 : 0] req_addr;
input [63 : 0] req_st_value;
input [1 : 0] req_priv;
input req_sstatus_SUM;
input req_mstatus_MXR;
input [31 : 0] req_satp;
input EN_req;
// value method valid
output valid;
// value method addr
output [31 : 0] addr;
// value method word64
output [63 : 0] word64;
// value method st_amo_val
output [63 : 0] st_amo_val;
// value method exc
output exc;
// value method exc_code
output [3 : 0] exc_code;
// action method server_flush_request_put
input EN_server_flush_request_put;
output RDY_server_flush_request_put;
// action method server_flush_response_get
input EN_server_flush_response_get;
output RDY_server_flush_response_get;
// action method tlb_flush
input EN_tlb_flush;
output RDY_tlb_flush;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// signals for module outputs
reg [63 : 0] word64;
wire [63 : 0] mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
st_amo_val;
wire [31 : 0] addr;
wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb;
wire [3 : 0] exc_code,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] mem_master_arburst, mem_master_awburst;
wire RDY_server_flush_request_put,
RDY_server_flush_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_verbosity,
RDY_tlb_flush,
exc,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid,
valid;
// inlined wires
wire [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1,
ctr_wr_rsps_pending_crg$port1__write_1,
ctr_wr_rsps_pending_crg$port2__read,
ctr_wr_rsps_pending_crg$port3__read;
wire ctr_wr_rsps_pending_crg$EN_port2__write, dw_valid$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register ctr_wr_rsps_pending_crg
reg [3 : 0] ctr_wr_rsps_pending_crg;
wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
wire ctr_wr_rsps_pending_crg$EN;
// register rg_addr
reg [31 : 0] rg_addr;
wire [31 : 0] rg_addr$D_IN;
wire rg_addr$EN;
// register rg_amo_funct7
reg [6 : 0] rg_amo_funct7;
wire [6 : 0] rg_amo_funct7$D_IN;
wire rg_amo_funct7$EN;
// register rg_cset_in_cache
reg [6 : 0] rg_cset_in_cache;
wire [6 : 0] rg_cset_in_cache$D_IN;
wire rg_cset_in_cache$EN;
// register rg_error_during_refill
reg rg_error_during_refill;
wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;
// register rg_exc_code
reg [3 : 0] rg_exc_code;
reg [3 : 0] rg_exc_code$D_IN;
wire rg_exc_code$EN;
// register rg_f3
reg [2 : 0] rg_f3;
wire [2 : 0] rg_f3$D_IN;
wire rg_f3$EN;
// register rg_ld_val
reg [63 : 0] rg_ld_val;
reg [63 : 0] rg_ld_val$D_IN;
wire rg_ld_val$EN;
// register rg_lower_word32
reg [31 : 0] rg_lower_word32;
wire [31 : 0] rg_lower_word32$D_IN;
wire rg_lower_word32$EN;
// register rg_lower_word32_full
reg rg_lower_word32_full;
wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;
// register rg_lrsc_pa
reg [31 : 0] rg_lrsc_pa;
wire [31 : 0] rg_lrsc_pa$D_IN;
wire rg_lrsc_pa$EN;
// register rg_lrsc_valid
reg rg_lrsc_valid;
wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;
// register rg_op
reg [1 : 0] rg_op;
wire [1 : 0] rg_op$D_IN;
wire rg_op$EN;
// register rg_pa
reg [31 : 0] rg_pa;
wire [31 : 0] rg_pa$D_IN;
wire rg_pa$EN;
// register rg_pte_pa
reg [31 : 0] rg_pte_pa;
wire [31 : 0] rg_pte_pa$D_IN;
wire rg_pte_pa$EN;
// register rg_st_amo_val
reg [63 : 0] rg_st_amo_val;
wire [63 : 0] rg_st_amo_val$D_IN;
wire rg_st_amo_val$EN;
// register rg_state
reg [3 : 0] rg_state;
reg [3 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_victim_way
reg rg_victim_way;
wire rg_victim_way$D_IN, rg_victim_way$EN;
// register rg_word64_set_in_cache
reg [8 : 0] rg_word64_set_in_cache;
wire [8 : 0] rg_word64_set_in_cache$D_IN;
wire rg_word64_set_in_cache$EN;
// ports of submodule f_fabric_write_reqs
reg [98 : 0] f_fabric_write_reqs$D_IN;
wire [98 : 0] f_fabric_write_reqs$D_OUT;
wire f_fabric_write_reqs$CLR,
f_fabric_write_reqs$DEQ,
f_fabric_write_reqs$EMPTY_N,
f_fabric_write_reqs$ENQ,
f_fabric_write_reqs$FULL_N;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule master_xactor_f_rd_addr
wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT;
wire master_xactor_f_rd_addr$CLR,
master_xactor_f_rd_addr$DEQ,
master_xactor_f_rd_addr$EMPTY_N,
master_xactor_f_rd_addr$ENQ,
master_xactor_f_rd_addr$FULL_N;
// ports of submodule master_xactor_f_rd_data
wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
wire master_xactor_f_rd_data$CLR,
master_xactor_f_rd_data$DEQ,
master_xactor_f_rd_data$EMPTY_N,
master_xactor_f_rd_data$ENQ,
master_xactor_f_rd_data$FULL_N;
// ports of submodule master_xactor_f_wr_addr
wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
wire master_xactor_f_wr_addr$CLR,
master_xactor_f_wr_addr$DEQ,
master_xactor_f_wr_addr$EMPTY_N,
master_xactor_f_wr_addr$ENQ,
master_xactor_f_wr_addr$FULL_N;
// ports of submodule master_xactor_f_wr_data
wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
wire master_xactor_f_wr_data$CLR,
master_xactor_f_wr_data$DEQ,
master_xactor_f_wr_data$EMPTY_N,
master_xactor_f_wr_data$ENQ,
master_xactor_f_wr_data$FULL_N;
// ports of submodule master_xactor_f_wr_resp
wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
wire master_xactor_f_wr_resp$CLR,
master_xactor_f_wr_resp$DEQ,
master_xactor_f_wr_resp$EMPTY_N,
master_xactor_f_wr_resp$ENQ,
master_xactor_f_wr_resp$FULL_N;
// ports of submodule ram_state_and_ctag_cset
wire [45 : 0] ram_state_and_ctag_cset$DIA,
ram_state_and_ctag_cset$DIB,
ram_state_and_ctag_cset$DOB;
wire [6 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
wire ram_state_and_ctag_cset$ENA,
ram_state_and_ctag_cset$ENB,
ram_state_and_ctag_cset$WEA,
ram_state_and_ctag_cset$WEB;
// ports of submodule ram_word64_set
reg [127 : 0] ram_word64_set$DIB;
reg [8 : 0] ram_word64_set$ADDRB;
wire [127 : 0] ram_word64_set$DIA, ram_word64_set$DOB;
wire [8 : 0] ram_word64_set$ADDRA;
wire ram_word64_set$ENA,
ram_word64_set$ENB,
ram_word64_set$WEA,
ram_word64_set$WEB;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
wire soc_map$m_is_mem_addr;
// rule scheduling signals
wire CAN_FIRE_RL_rl_ST_AMO_response,
CAN_FIRE_RL_rl_cache_refill_rsps_loop,
CAN_FIRE_RL_rl_discard_write_rsp,
CAN_FIRE_RL_rl_drive_exception_rsp,
CAN_FIRE_RL_rl_fabric_send_write_req,
CAN_FIRE_RL_rl_io_AMO_SC_req,
CAN_FIRE_RL_rl_io_AMO_op_req,
CAN_FIRE_RL_rl_io_AMO_read_rsp,
CAN_FIRE_RL_rl_io_read_req,
CAN_FIRE_RL_rl_io_read_rsp,
CAN_FIRE_RL_rl_io_write_req,
CAN_FIRE_RL_rl_maintain_io_read_rsp,
CAN_FIRE_RL_rl_probe_and_immed_rsp,
CAN_FIRE_RL_rl_rereq,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_start_cache_refill,
CAN_FIRE_RL_rl_start_reset,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_req,
CAN_FIRE_server_flush_request_put,
CAN_FIRE_server_flush_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_verbosity,
CAN_FIRE_tlb_flush,
WILL_FIRE_RL_rl_ST_AMO_response,
WILL_FIRE_RL_rl_cache_refill_rsps_loop,
WILL_FIRE_RL_rl_discard_write_rsp,
WILL_FIRE_RL_rl_drive_exception_rsp,
WILL_FIRE_RL_rl_fabric_send_write_req,
WILL_FIRE_RL_rl_io_AMO_SC_req,
WILL_FIRE_RL_rl_io_AMO_op_req,
WILL_FIRE_RL_rl_io_AMO_read_rsp,
WILL_FIRE_RL_rl_io_read_req,
WILL_FIRE_RL_rl_io_read_rsp,
WILL_FIRE_RL_rl_io_write_req,
WILL_FIRE_RL_rl_maintain_io_read_rsp,
WILL_FIRE_RL_rl_probe_and_immed_rsp,
WILL_FIRE_RL_rl_rereq,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_start_cache_refill,
WILL_FIRE_RL_rl_start_reset,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_req,
WILL_FIRE_server_flush_request_put,
WILL_FIRE_server_flush_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_verbosity,
WILL_FIRE_tlb_flush;
// inputs to muxes for submodule ports
wire [127 : 0] MUX_ram_word64_set$a_put_3__VAL_1,
MUX_ram_word64_set$a_put_3__VAL_2;
wire [98 : 0] MUX_f_fabric_write_reqs$enq_1__VAL_1,
MUX_f_fabric_write_reqs$enq_1__VAL_2,
MUX_f_fabric_write_reqs$enq_1__VAL_3;
wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
MUX_rg_ld_val$write_1__VAL_2;
wire [45 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2,
MUX_ram_word64_set$b_put_2__VAL_4;
wire [6 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
wire [3 : 0] MUX_rg_exc_code$write_1__VAL_1,
MUX_rg_state$write_1__VAL_1,
MUX_rg_state$write_1__VAL_10,
MUX_rg_state$write_1__VAL_12,
MUX_rg_state$write_1__VAL_3;
wire MUX_dw_output_ld_val$wset_1__SEL_1,
MUX_dw_output_ld_val$wset_1__SEL_2,
MUX_dw_output_ld_val$wset_1__SEL_3,
MUX_dw_output_ld_val$wset_1__SEL_4,
MUX_f_fabric_write_reqs$enq_1__SEL_2,
MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1,
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1,
MUX_ram_word64_set$a_put_1__SEL_1,
MUX_ram_word64_set$b_put_1__SEL_2,
MUX_rg_error_during_refill$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_2,
MUX_rg_exc_code$write_1__SEL_3,
MUX_rg_ld_val$write_1__SEL_2,
MUX_rg_lrsc_valid$write_1__SEL_2,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_12,
MUX_rg_state$write_1__SEL_13,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4093;
reg [31 : 0] v__h4192;
reg [31 : 0] v__h4341;
reg [31 : 0] v__h19635;
reg [31 : 0] v__h23351;
reg [31 : 0] v__h26669;
reg [31 : 0] v__h27408;
reg [31 : 0] v__h27649;
reg [31 : 0] v__h30045;
reg [31 : 0] v__h30395;
reg [31 : 0] v__h31495;
reg [31 : 0] v__h31602;
reg [31 : 0] v__h31707;
reg [31 : 0] v__h31787;
reg [31 : 0] v__h31997;
reg [31 : 0] v__h32115;
reg [31 : 0] v__h32409;
reg [31 : 0] v__h32584;
reg [31 : 0] v__h34843;
reg [31 : 0] v__h32680;
reg [31 : 0] v__h35450;
reg [31 : 0] v__h35411;
reg [31 : 0] v__h3625;
reg [31 : 0] v__h35798;
reg [31 : 0] v__h3619;
reg [31 : 0] v__h4087;
reg [31 : 0] v__h4186;
reg [31 : 0] v__h4335;
reg [31 : 0] v__h19629;
reg [31 : 0] v__h23345;
reg [31 : 0] v__h26663;
reg [31 : 0] v__h27402;
reg [31 : 0] v__h27643;
reg [31 : 0] v__h30039;
reg [31 : 0] v__h30389;
reg [31 : 0] v__h31489;
reg [31 : 0] v__h31596;
reg [31 : 0] v__h31701;
reg [31 : 0] v__h31781;
reg [31 : 0] v__h31991;
reg [31 : 0] v__h32109;
reg [31 : 0] v__h32403;
reg [31 : 0] v__h32578;
reg [31 : 0] v__h32674;
reg [31 : 0] v__h34837;
reg [31 : 0] v__h35405;
reg [31 : 0] v__h35444;
reg [31 : 0] v__h35792;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30,
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33,
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34,
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35,
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50,
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29,
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_31_EQ__ETC__q52,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832,
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347,
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386,
_theResult_____2__h23875,
_theResult_____2__h32756,
ld_val__h30504,
mem_req_wr_data_wdata__h2818,
n__h20801,
n__h23737,
new_ld_val__h32710,
old_word64__h20790,
w1__h23867,
w1__h32744,
w1__h32748;
reg [7 : 0] mem_req_wr_data_wstrb__h2819;
reg [2 : 0] value__h32296, x__h2639;
wire [63 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d448,
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d525,
IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d447,
IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d524,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_1_E_ETC___d355,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340,
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455,
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d532,
_theResult___snd_fst__h2826,
cline_fabric_addr__h26722,
fabric_addr__h32167,
mem_req_wr_addr_awaddr__h2592,
new_st_val__h23573,
new_st_val__h23879,
new_st_val__h23970,
new_st_val__h24950,
new_st_val__h24954,
new_st_val__h24958,
new_st_val__h24962,
new_st_val__h24967,
new_st_val__h24973,
new_st_val__h24978,
new_st_val__h32760,
new_st_val__h32851,
new_st_val__h34711,
new_st_val__h34715,
new_st_val__h34719,
new_st_val__h34723,
new_st_val__h34728,
new_st_val__h34734,
new_st_val__h34739,
new_value__h22441,
new_value__h6012,
result__h18723,
result__h18751,
result__h18779,
result__h18807,
result__h18835,
result__h18863,
result__h18891,
result__h18919,
result__h18964,
result__h18992,
result__h19020,
result__h19048,
result__h19076,
result__h19104,
result__h19132,
result__h19160,
result__h19205,
result__h19233,
result__h19261,
result__h19289,
result__h19330,
result__h19358,
result__h19386,
result__h19414,
result__h19455,
result__h19483,
result__h19522,
result__h19550,
result__h30564,
result__h30594,
result__h30621,
result__h30648,
result__h30675,
result__h30702,
result__h30729,
result__h30756,
result__h30800,
result__h30827,
result__h30854,
result__h30881,
result__h30908,
result__h30935,
result__h30962,
result__h30989,
result__h31033,
result__h31060,
result__h31087,
result__h31114,
result__h31154,
result__h31181,
result__h31208,
result__h31235,
result__h31275,
result__h31302,
result__h31340,
result__h31367,
result__h32939,
result__h33847,
result__h33875,
result__h33903,
result__h33931,
result__h33959,
result__h33987,
result__h34015,
result__h34060,
result__h34088,
result__h34116,
result__h34144,
result__h34172,
result__h34200,
result__h34228,
result__h34256,
result__h34301,
result__h34329,
result__h34357,
result__h34385,
result__h34426,
result__h34454,
result__h34482,
result__h34510,
result__h34551,
result__h34579,
result__h34618,
result__h34646,
w1___1__h23938,
w1___1__h32819,
w2___1__h32820,
w2__h32750,
word64__h5847,
x__h20022,
x__h32739,
x__h6037,
y__h12367,
y__h6038,
y__h6052;
wire [31 : 0] IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31,
cline_addr__h26721,
ld_val0504_BITS_31_TO_0__q38,
ld_val0504_BITS_63_TO_32__q45,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10,
rg_st_amo_val_BITS_31_TO_0__q32,
w12744_BITS_31_TO_0__q51,
word64847_BITS_31_TO_0__q17,
word64847_BITS_63_TO_32__q24;
wire [21 : 0] n_ctag__h27950, pa_ctag__h5533;
wire [15 : 0] ld_val0504_BITS_15_TO_0__q37,
ld_val0504_BITS_31_TO_16__q41,
ld_val0504_BITS_47_TO_32__q44,
ld_val0504_BITS_63_TO_48__q48,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13,
word64847_BITS_15_TO_0__q16,
word64847_BITS_31_TO_16__q20,
word64847_BITS_47_TO_32__q23,
word64847_BITS_63_TO_48__q27;
wire [7 : 0] ld_val0504_BITS_15_TO_8__q39,
ld_val0504_BITS_23_TO_16__q40,
ld_val0504_BITS_31_TO_24__q42,
ld_val0504_BITS_39_TO_32__q43,
ld_val0504_BITS_47_TO_40__q46,
ld_val0504_BITS_55_TO_48__q47,
ld_val0504_BITS_63_TO_56__q49,
ld_val0504_BITS_7_TO_0__q36,
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4,
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8,
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q5,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11,
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14,
strobe64__h2756,
strobe64__h2758,
strobe64__h2760,
word64847_BITS_15_TO_8__q18,
word64847_BITS_23_TO_16__q19,
word64847_BITS_31_TO_24__q21,
word64847_BITS_39_TO_32__q22,
word64847_BITS_47_TO_40__q25,
word64847_BITS_55_TO_48__q26,
word64847_BITS_63_TO_56__q28,
word64847_BITS_7_TO_0__q15;
wire [5 : 0] shift_bits__h2606;
wire [3 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d152,
IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d154,
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d153,
access_exc_code__h2374,
b__h26623;
wire [1 : 0] tmp__h26884, tmp__h26885;
wire IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d122,
NOT_cfg_verbosity_read__0_ULE_1_1___d42,
NOT_cfg_verbosity_read__0_ULE_2_99___d600,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d162,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d369,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d372,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d378,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d382,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d393,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d535,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d547,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d577,
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d121,
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d168,
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370,
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d375,
NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d149,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d530,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d558,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570,
NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390,
NOT_rg_op_4_EQ_1_2_74_AND_ram_state_and_ctag_c_ETC___d379,
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d388,
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d548,
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d552,
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d556,
dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d124,
lrsc_result__h20012,
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111,
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117,
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d165,
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d176,
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359,
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d572,
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966,
rg_addr_9_EQ_rg_lrsc_pa_8___d166,
rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_ra_ETC___d364,
rg_lrsc_pa_8_EQ_rg_addr_9___d99,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d139,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d170,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d180,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d182,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d185,
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d178,
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d391,
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d528,
rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562,
rg_state_5_EQ_12_50_AND_rg_op_4_EQ_0_5_OR_rg_o_ETC___d652;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas ;
// value method addr
assign addr = rg_addr ;
// value method word64
always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
ld_val__h30504 or
MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h32710 or
MUX_dw_output_ld_val$wset_1__SEL_3 or
MUX_dw_output_ld_val$wset_1__VAL_3 or
MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h30504;
MUX_dw_output_ld_val$wset_1__SEL_2: word64 = new_ld_val__h32710;
MUX_dw_output_ld_val$wset_1__SEL_3:
word64 = MUX_dw_output_ld_val$wset_1__VAL_3;
MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val;
default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// value method st_amo_val
assign st_amo_val =
MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ;
// value method exc
assign exc = rg_state == 4'd4 ;
// value method exc_code
assign exc_code = rg_exc_code ;
// action method server_flush_request_put
assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;
// action method server_flush_response_get
assign RDY_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;
// action method tlb_flush
assign RDY_tlb_flush = 1'd1 ;
assign CAN_FIRE_tlb_flush = 1'd1 ;
assign WILL_FIRE_tlb_flush = EN_tlb_flush ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
// value method mem_master_m_awid
assign mem_master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
// value method mem_master_m_awlen
assign mem_master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
// value method mem_master_m_awsize
assign mem_master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
// value method mem_master_m_awburst
assign mem_master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
// value method mem_master_m_awlock
assign mem_master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
// value method mem_master_m_awcache
assign mem_master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
// value method mem_master_m_awprot
assign mem_master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
// value method mem_master_m_awqos
assign mem_master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
// value method mem_master_m_awregion
assign mem_master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
// value method mem_master_m_wdata
assign mem_master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
// value method mem_master_m_wlast
assign mem_master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = master_xactor_f_wr_resp$FULL_N ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
// value method mem_master_m_arid
assign mem_master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;
// value method mem_master_m_araddr
assign mem_master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
// value method mem_master_m_arlen
assign mem_master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
// value method mem_master_m_arsize
assign mem_master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
// value method mem_master_m_arburst
assign mem_master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
// value method mem_master_m_arlock
assign mem_master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
// value method mem_master_m_arcache
assign mem_master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
// value method mem_master_m_arprot
assign mem_master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
// value method mem_master_m_arqos
assign mem_master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
// value method mem_master_m_arregion
assign mem_master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = master_xactor_f_rd_data$FULL_N ;
// submodule f_fabric_write_reqs
FIFO2 #(.width(32'd99), .guarded(32'd1)) f_fabric_write_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fabric_write_reqs$D_IN),
.ENQ(f_fabric_write_reqs$ENQ),
.DEQ(f_fabric_write_reqs$DEQ),
.CLR(f_fabric_write_reqs$CLR),
.D_OUT(f_fabric_write_reqs$D_OUT),
.FULL_N(f_fabric_write_reqs$FULL_N),
.EMPTY_N(f_fabric_write_reqs$EMPTY_N));
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule master_xactor_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_addr$D_IN),
.ENQ(master_xactor_f_rd_addr$ENQ),
.DEQ(master_xactor_f_rd_addr$DEQ),
.CLR(master_xactor_f_rd_addr$CLR),
.D_OUT(master_xactor_f_rd_addr$D_OUT),
.FULL_N(master_xactor_f_rd_addr$FULL_N),
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
// submodule master_xactor_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_data$D_IN),
.ENQ(master_xactor_f_rd_data$ENQ),
.DEQ(master_xactor_f_rd_data$DEQ),
.CLR(master_xactor_f_rd_data$CLR),
.D_OUT(master_xactor_f_rd_data$D_OUT),
.FULL_N(master_xactor_f_rd_data$FULL_N),
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
// submodule master_xactor_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_addr$D_IN),
.ENQ(master_xactor_f_wr_addr$ENQ),
.DEQ(master_xactor_f_wr_addr$DEQ),
.CLR(master_xactor_f_wr_addr$CLR),
.D_OUT(master_xactor_f_wr_addr$D_OUT),
.FULL_N(master_xactor_f_wr_addr$FULL_N),
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
// submodule master_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_data$D_IN),
.ENQ(master_xactor_f_wr_data$ENQ),
.DEQ(master_xactor_f_wr_data$DEQ),
.CLR(master_xactor_f_wr_data$CLR),
.D_OUT(master_xactor_f_wr_data$D_OUT),
.FULL_N(master_xactor_f_wr_data$FULL_N),
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
// submodule master_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_resp$D_IN),
.ENQ(master_xactor_f_wr_resp$ENQ),
.DEQ(master_xactor_f_wr_resp$DEQ),
.CLR(master_xactor_f_wr_resp$CLR),
.D_OUT(master_xactor_f_wr_resp$D_OUT),
.FULL_N(master_xactor_f_wr_resp$FULL_N),
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
// submodule ram_state_and_ctag_cset
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd7),
.DATA_WIDTH(32'd46),
.MEMSIZE(8'd128)) ram_state_and_ctag_cset(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_state_and_ctag_cset$ADDRA),
.ADDRB(ram_state_and_ctag_cset$ADDRB),
.DIA(ram_state_and_ctag_cset$DIA),
.DIB(ram_state_and_ctag_cset$DIB),
.WEA(ram_state_and_ctag_cset$WEA),
.WEB(ram_state_and_ctag_cset$WEB),
.ENA(ram_state_and_ctag_cset$ENA),
.ENB(ram_state_and_ctag_cset$ENB),
.DOA(),
.DOB(ram_state_and_ctag_cset$DOB));
// submodule ram_word64_set
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd128),
.MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_word64_set$ADDRA),
.ADDRB(ram_word64_set$ADDRB),
.DIA(ram_word64_set$DIA),
.DIB(ram_word64_set$DIB),
.WEA(ram_word64_set$WEA),
.WEB(ram_word64_set$WEB),
.ENA(ram_word64_set$ENA),
.ENB(ram_word64_set$ENB),
.DOA(),
.DOB(ram_word64_set$DOB));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(soc_map$m_is_mem_addr),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_fabric_send_write_req
assign CAN_FIRE_RL_rl_fabric_send_write_req =
ctr_wr_rsps_pending_crg != 4'd15 &&
f_fabric_write_reqs$EMPTY_N &&
master_xactor_f_wr_addr$FULL_N &&
master_xactor_f_wr_data$FULL_N ;
assign WILL_FIRE_RL_rl_fabric_send_write_req =
CAN_FIRE_RL_rl_fabric_send_write_req ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset =
(rg_cset_in_cache != 7'd127 ||
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
rg_state == 4'd1 ;
assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;
// rule RL_rl_probe_and_immed_rsp
assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d124 &&
rg_state == 4'd3 ;
assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
CAN_FIRE_RL_rl_probe_and_immed_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_start_cache_refill
assign CAN_FIRE_RL_rl_start_cache_refill =
master_xactor_f_rd_addr$FULL_N && rg_state == 4'd8 &&
b__h26623 == 4'd0 ;
assign WILL_FIRE_RL_rl_start_cache_refill =
CAN_FIRE_RL_rl_start_cache_refill &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_cache_refill_rsps_loop
assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
master_xactor_f_rd_data$EMPTY_N && rg_state == 4'd9 ;
assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_rereq
assign CAN_FIRE_RL_rl_rereq = rg_state == 4'd10 ;
assign WILL_FIRE_RL_rl_rereq =
CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;
// rule RL_rl_ST_AMO_response
assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 4'd11 ;
assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;
// rule RL_rl_io_read_req
assign CAN_FIRE_RL_rl_io_read_req =
master_xactor_f_rd_addr$FULL_N &&
rg_state_5_EQ_12_50_AND_rg_op_4_EQ_0_5_OR_rg_o_ETC___d652 ;
assign WILL_FIRE_RL_rl_io_read_req =
CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_read_rsp
assign CAN_FIRE_RL_rl_io_read_rsp =
master_xactor_f_rd_data$EMPTY_N && rg_state == 4'd13 ;
assign WILL_FIRE_RL_rl_io_read_rsp =
CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_maintain_io_read_rsp
assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 4'd14 ;
assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
CAN_FIRE_RL_rl_maintain_io_read_rsp ;
// rule RL_rl_io_write_req
assign CAN_FIRE_RL_rl_io_write_req =
f_fabric_write_reqs$FULL_N && rg_state == 4'd12 &&
rg_op == 2'd1 ;
assign WILL_FIRE_RL_rl_io_write_req =
CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_SC_req
assign CAN_FIRE_RL_rl_io_AMO_SC_req =
rg_state == 4'd12 && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_SC_req =
CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_op_req
assign CAN_FIRE_RL_rl_io_AMO_op_req =
master_xactor_f_rd_addr$FULL_N && rg_state == 4'd12 &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] != 5'b00010 &&
rg_amo_funct7[6:2] != 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_op_req =
CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_read_rsp
assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
master_xactor_f_rd_data$EMPTY_N &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
f_fabric_write_reqs$FULL_N) &&
rg_state == 4'd15 ;
assign WILL_FIRE_RL_rl_io_AMO_read_rsp = MUX_rg_state$write_1__SEL_3 ;
// rule RL_rl_discard_write_rsp
assign CAN_FIRE_RL_rl_discard_write_rsp =
b__h26623 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_discard_write_rsp =
CAN_FIRE_RL_rl_discard_write_rsp ;
// rule RL_rl_drive_exception_rsp
assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ;
assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ;
// rule RL_rl_start_reset
assign CAN_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_2 ;
assign WILL_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_2 ;
// inputs to muxes for submodule ports
assign MUX_dw_output_ld_val$wset_1__SEL_1 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_3 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d185 ;
assign MUX_dw_output_ld_val$wset_1__SEL_4 =
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign MUX_f_fabric_write_reqs$enq_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d530 ;
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
assign MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 =
EN_req &&
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 ;
assign MUX_ram_word64_set$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_ram_word64_set$b_put_1__SEL_2 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] != 2'd3 ;
assign MUX_rg_error_during_refill$write_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_1 =
EN_req &&
NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957 ;
assign MUX_rg_exc_code$write_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_3 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_ld_val$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d382 ;
assign MUX_rg_lrsc_valid$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d180 ;
assign MUX_rg_state$write_1__SEL_2 =
f_reset_reqs$EMPTY_N && rg_state != 4'd1 ;
assign MUX_rg_state$write_1__SEL_3 =
CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
assign MUX_rg_state$write_1__SEL_10 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd3 ;
assign MUX_rg_state$write_1__SEL_12 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(dmem_not_imem && !soc_map$m_is_mem_addr ||
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d139 ||
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d149) ;
assign MUX_rg_state$write_1__SEL_13 =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ;
assign MUX_dw_output_ld_val$wset_1__VAL_3 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
new_value__h6012 :
new_value__h22441 ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_1 = { rg_f3, rg_pa, x__h32739 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_2 =
{ rg_f3,
rg_addr,
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d532 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_3 =
{ rg_f3, rg_pa, rg_st_amo_val } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
{ 4'd0, fabric_addr__h32167, 8'd0, value__h32296, 18'd65536 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
{ 4'd0, cline_fabric_addr__h26722, 29'd7143424 } ;
assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 =
{ rg_victim_way || ram_state_and_ctag_cset$DOB[45],
rg_victim_way ?
n_ctag__h27950 :
ram_state_and_ctag_cset$DOB[44:23],
!rg_victim_way || ram_state_and_ctag_cset$DOB[22],
rg_victim_way ?
ram_state_and_ctag_cset$DOB[21:0] :
n_ctag__h27950 } ;
assign MUX_ram_word64_set$a_put_3__VAL_1 =
rg_victim_way ?
{ master_xactor_f_rd_data$D_OUT[66:3],
ram_word64_set$DOB[63:0] } :
{ ram_word64_set$DOB[127:64],
master_xactor_f_rd_data$D_OUT[66:3] } ;
assign MUX_ram_word64_set$a_put_3__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
{ IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d447,
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d448 } :
{ IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d524,
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d525 } ;
assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ;
assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:5], 2'd0 } ;
assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 7'd1 ;
assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
assign MUX_rg_ld_val$write_1__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
x__h20022 :
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 ;
assign MUX_rg_state$write_1__VAL_1 =
NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957 ?
4'd4 :
4'd3 ;
assign MUX_rg_state$write_1__VAL_3 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ? 4'd14 : 4'd4 ;
assign MUX_rg_state$write_1__VAL_10 =
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) ?
4'd4 :
4'd10 ;
assign MUX_rg_state$write_1__VAL_12 =
(dmem_not_imem && !soc_map$m_is_mem_addr) ?
4'd12 :
IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d154 ;
// inlined wires
assign dw_valid$whas =
(WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_io_read_rsp) &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d185 ||
WILL_FIRE_RL_rl_drive_exception_rsp ||
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign ctr_wr_rsps_pending_crg$port0__write_1 =
ctr_wr_rsps_pending_crg + 4'd1 ;
assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h26623 - 4'd1 ;
assign ctr_wr_rsps_pending_crg$port2__read =
CAN_FIRE_RL_rl_discard_write_rsp ?
ctr_wr_rsps_pending_crg$port1__write_1 :
b__h26623 ;
assign ctr_wr_rsps_pending_crg$EN_port2__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign ctr_wr_rsps_pending_crg$port3__read =
ctr_wr_rsps_pending_crg$EN_port2__write ?
4'd0 :
ctr_wr_rsps_pending_crg$port2__read ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register ctr_wr_rsps_pending_crg
assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register rg_addr
assign rg_addr$D_IN = req_addr ;
assign rg_addr$EN = EN_req ;
// register rg_amo_funct7
assign rg_amo_funct7$D_IN = req_amo_funct7 ;
assign rg_amo_funct7$EN = EN_req ;
// register rg_cset_in_cache
assign rg_cset_in_cache$D_IN =
WILL_FIRE_RL_rl_reset ?
MUX_rg_cset_in_cache$write_1__VAL_1 :
7'd0 ;
assign rg_cset_in_cache$EN =
WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;
// register rg_error_during_refill
assign rg_error_during_refill$D_IN =
MUX_rg_error_during_refill$write_1__SEL_1 ;
assign rg_error_during_refill$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_exc_code
always@(MUX_rg_exc_code$write_1__SEL_1 or
MUX_rg_exc_code$write_1__VAL_1 or
MUX_rg_exc_code$write_1__SEL_2 or
MUX_rg_exc_code$write_1__SEL_3 or
MUX_rg_error_during_refill$write_1__SEL_1 or access_exc_code__h2374)
case (1'b1)
MUX_rg_exc_code$write_1__SEL_1:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
MUX_rg_error_during_refill$write_1__SEL_1:
rg_exc_code$D_IN = access_exc_code__h2374;
default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign rg_exc_code$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
EN_req &&
NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957 ;
// register rg_f3
assign rg_f3$D_IN = req_f3 ;
assign rg_f3$EN = EN_req ;
// register rg_ld_val
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h32710 or
MUX_rg_ld_val$write_1__SEL_2 or
MUX_rg_ld_val$write_1__VAL_2 or
WILL_FIRE_RL_rl_io_read_rsp or
ld_val__h30504 or WILL_FIRE_RL_rl_io_AMO_SC_req)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h32710;
MUX_rg_ld_val$write_1__SEL_2:
rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h30504;
WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_ld_val$EN =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d382 ||
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_SC_req ;
// register rg_lower_word32
assign rg_lower_word32$D_IN = 32'h0 ;
assign rg_lower_word32$EN = 1'b0 ;
// register rg_lower_word32_full
assign rg_lower_word32_full$D_IN = 1'd0 ;
assign rg_lower_word32_full$EN =
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_lrsc_pa
assign rg_lrsc_pa$D_IN = rg_addr ;
assign rg_lrsc_pa$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_ra_ETC___d364 ;
// register rg_lrsc_valid
assign rg_lrsc_valid$D_IN =
MUX_rg_lrsc_valid$write_1__SEL_2 &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d182 ;
assign rg_lrsc_valid$EN =
WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d180 ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_op
assign rg_op$D_IN = req_op ;
assign rg_op$EN = EN_req ;
// register rg_pa
assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ;
assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ;
// register rg_pte_pa
assign rg_pte_pa$D_IN = 32'h0 ;
assign rg_pte_pa$EN = 1'b0 ;
// register rg_st_amo_val
assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h23573 ;
assign rg_st_amo_val$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d577 ||
EN_req ;
// register rg_state
always@(EN_req or
MUX_rg_state$write_1__VAL_1 or
WILL_FIRE_RL_rl_start_reset or
WILL_FIRE_RL_rl_io_AMO_read_rsp or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_io_AMO_op_req or
WILL_FIRE_RL_rl_io_AMO_SC_req or
WILL_FIRE_RL_rl_io_write_req or
WILL_FIRE_RL_rl_io_read_rsp or
WILL_FIRE_RL_rl_io_read_req or
WILL_FIRE_RL_rl_rereq or
MUX_rg_state$write_1__SEL_10 or
MUX_rg_state$write_1__VAL_10 or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_rg_state$write_1__SEL_12 or
MUX_rg_state$write_1__VAL_12 or MUX_rg_state$write_1__SEL_13)
case (1'b1)
EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 4'd1;
WILL_FIRE_RL_rl_io_AMO_read_rsp:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 4'd15;
WILL_FIRE_RL_rl_io_AMO_SC_req || WILL_FIRE_RL_rl_io_write_req:
rg_state$D_IN = 4'd11;
WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 4'd13;
WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 4'd3;
MUX_rg_state$write_1__SEL_10:
rg_state$D_IN = MUX_rg_state$write_1__VAL_10;
WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 4'd9;
MUX_rg_state$write_1__SEL_12:
rg_state$D_IN = MUX_rg_state$write_1__VAL_12;
MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 4'd2;
default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign rg_state$EN =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd3 ||
MUX_rg_state$write_1__SEL_12 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_io_read_rsp ||
EN_req ||
WILL_FIRE_RL_rl_start_reset ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_io_AMO_SC_req ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_io_AMO_op_req ;
// register rg_victim_way
assign rg_victim_way$D_IN = tmp__h26885[0] ;
assign rg_victim_way$EN = WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_word64_set_in_cache
assign rg_word64_set_in_cache$D_IN =
MUX_ram_word64_set$b_put_1__SEL_2 ?
MUX_ram_word64_set$b_put_2__VAL_2 :
MUX_ram_word64_set$b_put_2__VAL_4 ;
assign rg_word64_set_in_cache$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] != 2'd3 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule f_fabric_write_reqs
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_1 or
MUX_f_fabric_write_reqs$enq_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_2 or
WILL_FIRE_RL_rl_io_write_req or
MUX_f_fabric_write_reqs$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_1;
MUX_f_fabric_write_reqs$enq_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_2;
WILL_FIRE_RL_rl_io_write_req:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_3;
default: f_fabric_write_reqs$D_IN =
99'h2AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_fabric_write_reqs$ENQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d530 ||
WILL_FIRE_RL_rl_io_write_req ;
assign f_fabric_write_reqs$DEQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign f_fabric_write_reqs$CLR = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
assign f_reset_reqs$ENQ =
EN_server_reset_request_put || EN_server_flush_request_put ;
assign f_reset_reqs$DEQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
assign f_reset_rsps$ENQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ;
assign f_reset_rsps$DEQ =
EN_server_flush_response_get || EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule master_xactor_f_rd_addr
assign master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
MUX_master_xactor_f_rd_addr$enq_1__VAL_1 :
MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ;
assign master_xactor_f_rd_addr$ENQ =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_start_cache_refill ;
assign master_xactor_f_rd_addr$DEQ =
master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
assign master_xactor_f_rd_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_rd_data
assign master_xactor_f_rd_data$D_IN =
{ mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast } ;
assign master_xactor_f_rd_data$ENQ =
mem_master_rvalid && master_xactor_f_rd_data$FULL_N ;
assign master_xactor_f_rd_data$DEQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop ;
assign master_xactor_f_rd_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_addr
assign master_xactor_f_wr_addr$D_IN =
{ 4'd0,
mem_req_wr_addr_awaddr__h2592,
8'd0,
x__h2639,
18'd65536 } ;
assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_addr$DEQ =
master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
assign master_xactor_f_wr_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_data
assign master_xactor_f_wr_data$D_IN =
{ mem_req_wr_data_wdata__h2818,
mem_req_wr_data_wstrb__h2819,
1'd1 } ;
assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_data$DEQ =
master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
assign master_xactor_f_wr_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_resp
assign master_xactor_f_wr_resp$D_IN = { mem_master_bid, mem_master_bresp } ;
assign master_xactor_f_wr_resp$ENQ =
mem_master_bvalid && master_xactor_f_wr_resp$FULL_N ;
assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_discard_write_rsp ;
assign master_xactor_f_wr_resp$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule ram_state_and_ctag_cset
assign ram_state_and_ctag_cset$ADDRA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
rg_addr[11:5] :
rg_cset_in_cache ;
assign ram_state_and_ctag_cset$ADDRB =
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
req_addr[11:5] :
rg_addr[11:5] ;
assign ram_state_and_ctag_cset$DIA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
46'h1555552AAAAA ;
assign ram_state_and_ctag_cset$DIB =
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
46'h2AAAAAAAAAAA /* unspecified value */ :
46'h2AAAAAAAAAAA /* unspecified value */ ;
assign ram_state_and_ctag_cset$WEA = 1'd1 ;
assign ram_state_and_ctag_cset$WEB = 1'd0 ;
assign ram_state_and_ctag_cset$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_reset ;
assign ram_state_and_ctag_cset$ENB =
EN_req &&
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 ||
WILL_FIRE_RL_rl_rereq ;
// submodule ram_word64_set
assign ram_word64_set$ADDRA =
MUX_ram_word64_set$a_put_1__SEL_1 ?
rg_word64_set_in_cache :
rg_addr[11:3] ;
always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
req_addr or
MUX_ram_word64_set$b_put_1__SEL_2 or
MUX_ram_word64_set$b_put_2__VAL_2 or
WILL_FIRE_RL_rl_rereq or
rg_addr or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_ram_word64_set$b_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
ram_word64_set$ADDRB = req_addr[11:3];
MUX_ram_word64_set$b_put_1__SEL_2:
ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2;
WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3];
WILL_FIRE_RL_rl_start_cache_refill:
ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4;
default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ;
endcase
end
assign ram_word64_set$DIA =
MUX_ram_word64_set$a_put_1__SEL_1 ?
MUX_ram_word64_set$a_put_3__VAL_1 :
MUX_ram_word64_set$a_put_3__VAL_2 ;
always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
MUX_ram_word64_set$b_put_1__SEL_2 or
WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
MUX_ram_word64_set$b_put_1__SEL_2:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_rereq:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_start_cache_refill:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
default: ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign ram_word64_set$WEA = 1'd1 ;
assign ram_word64_set$WEB = 1'd0 ;
assign ram_word64_set$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d393 ;
assign ram_word64_set$ENB =
EN_req &&
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] != 2'd3 ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = { 32'd0, rg_addr } ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d152 =
((!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117)) ?
4'd8 :
4'd11 ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d448 =
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ?
n__h20801 :
ram_word64_set$DOB[63:0] ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d525 =
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ?
n__h23737 :
ram_word64_set$DOB[63:0] ;
assign IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d447 =
(ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ?
n__h20801 :
ram_word64_set$DOB[127:64] ;
assign IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d524 =
(ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ?
n__h23737 :
ram_word64_set$DOB[127:64] ;
assign IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_1_E_ETC___d355 =
(rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
assign IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851 =
(rg_addr[2:0] == 3'h0) ? ld_val__h30504 : 64'd0 ;
assign IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340 =
(rg_addr[2:0] == 3'h0) ? word64__h5847 : 64'd0 ;
assign IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31 =
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347[31:0] ;
assign IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 =
(rg_f3 == 3'b010) ?
{ {32{rg_st_amo_val_BITS_31_TO_0__q32[31]}},
rg_st_amo_val_BITS_31_TO_0__q32 } :
rg_st_amo_val ;
assign IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d154 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd8 :
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d153 ;
assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d122 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20012 ||
f_fabric_write_reqs$FULL_N :
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d121 ;
assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d153 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
4'd11 :
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d152 ;
assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d532 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_st_amo_val :
new_st_val__h23573 ;
assign NOT_cfg_verbosity_read__0_ULE_1_1___d42 = cfg_verbosity > 4'd1 ;
assign NOT_cfg_verbosity_read__0_ULE_2_99___d600 = cfg_verbosity > 4'd2 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d162 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 &&
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d369 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d372 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d378 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d375 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d382 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
NOT_rg_op_4_EQ_1_2_74_AND_ram_state_and_ctag_c_ETC___d379) ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d393 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d391 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d535 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d547 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d577 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390 ;
assign NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d121 =
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ||
f_fabric_write_reqs$FULL_N ;
assign NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d168 =
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 ;
assign NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370 =
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d375 =
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957 =
req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
(req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
(req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d149 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d530 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d528 ||
NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390) ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d548 ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d558 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d556 ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 ;
assign NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign NOT_rg_op_4_EQ_1_2_74_AND_ram_state_and_ctag_c_ETC___d379 =
rg_op != 2'd1 &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d388 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d548 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 ;
assign NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d552 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) &&
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370 ;
assign NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d556 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign _theResult___snd_fst__h2826 =
f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h2606 ;
assign access_exc_code__h2374 =
dmem_not_imem ?
((rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd5 :
4'd7) :
4'd1 ;
assign b__h26623 =
CAN_FIRE_RL_rl_fabric_send_write_req ?
ctr_wr_rsps_pending_crg$port0__write_1 :
ctr_wr_rsps_pending_crg ;
assign cline_addr__h26721 = { rg_pa[31:5], 5'd0 } ;
assign cline_fabric_addr__h26722 = { 32'd0, cline_addr__h26721 } ;
assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d124 =
dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d122 ;
assign fabric_addr__h32167 = { 32'd0, rg_pa } ;
assign ld_val0504_BITS_15_TO_0__q37 = ld_val__h30504[15:0] ;
assign ld_val0504_BITS_15_TO_8__q39 = ld_val__h30504[15:8] ;
assign ld_val0504_BITS_23_TO_16__q40 = ld_val__h30504[23:16] ;
assign ld_val0504_BITS_31_TO_0__q38 = ld_val__h30504[31:0] ;
assign ld_val0504_BITS_31_TO_16__q41 = ld_val__h30504[31:16] ;
assign ld_val0504_BITS_31_TO_24__q42 = ld_val__h30504[31:24] ;
assign ld_val0504_BITS_39_TO_32__q43 = ld_val__h30504[39:32] ;
assign ld_val0504_BITS_47_TO_32__q44 = ld_val__h30504[47:32] ;
assign ld_val0504_BITS_47_TO_40__q46 = ld_val__h30504[47:40] ;
assign ld_val0504_BITS_55_TO_48__q47 = ld_val__h30504[55:48] ;
assign ld_val0504_BITS_63_TO_32__q45 = ld_val__h30504[63:32] ;
assign ld_val0504_BITS_63_TO_48__q48 = ld_val__h30504[63:48] ;
assign ld_val0504_BITS_63_TO_56__q49 = ld_val__h30504[63:56] ;
assign ld_val0504_BITS_7_TO_0__q36 = ld_val__h30504[7:0] ;
assign lrsc_result__h20012 =
!rg_lrsc_valid || !rg_lrsc_pa_8_EQ_rg_addr_9___d99 ;
assign master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 =
master_xactor_f_rd_data$D_OUT[10:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 =
master_xactor_f_rd_data$D_OUT[18:11] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 =
master_xactor_f_rd_data$D_OUT[18:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6 =
master_xactor_f_rd_data$D_OUT[26:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7 =
master_xactor_f_rd_data$D_OUT[34:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8 =
master_xactor_f_rd_data$D_OUT[34:27] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 =
master_xactor_f_rd_data$D_OUT[34:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q5 =
master_xactor_f_rd_data$D_OUT[42:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 =
master_xactor_f_rd_data$D_OUT[50:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 =
master_xactor_f_rd_data$D_OUT[50:43] ;
assign master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 =
master_xactor_f_rd_data$D_OUT[58:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 =
master_xactor_f_rd_data$D_OUT[66:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 =
master_xactor_f_rd_data$D_OUT[66:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 =
master_xactor_f_rd_data$D_OUT[66:59] ;
assign mem_req_wr_addr_awaddr__h2592 =
{ 32'd0, f_fabric_write_reqs$D_OUT[95:64] } ;
assign n_ctag__h27950 = { 2'd0, rg_pa[31:12] } ;
assign new_st_val__h23573 =
(rg_f3 == 3'b010) ?
new_st_val__h23879 :
_theResult_____2__h23875 ;
assign new_st_val__h23879 = { 32'd0, _theResult_____2__h23875[31:0] } ;
assign new_st_val__h23970 =
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 +
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ;
assign new_st_val__h24950 = w1__h23867 ^ w2__h32750 ;
assign new_st_val__h24954 = w1__h23867 & w2__h32750 ;
assign new_st_val__h24958 = w1__h23867 | w2__h32750 ;
assign new_st_val__h24962 =
(w1__h23867 < w2__h32750) ? w1__h23867 : w2__h32750 ;
assign new_st_val__h24967 =
(w1__h23867 <= w2__h32750) ? w2__h32750 : w1__h23867 ;
assign new_st_val__h24973 =
((IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 ^
64'h8000000000000000) <
(IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ^
64'h8000000000000000)) ?
w1__h23867 :
w2__h32750 ;
assign new_st_val__h24978 =
((IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 ^
64'h8000000000000000) <=
(IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ^
64'h8000000000000000)) ?
w2__h32750 :
w1__h23867 ;
assign new_st_val__h32760 = { 32'd0, _theResult_____2__h32756[31:0] } ;
assign new_st_val__h32851 =
new_ld_val__h32710 +
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ;
assign new_st_val__h34711 = w1__h32748 ^ w2__h32750 ;
assign new_st_val__h34715 = w1__h32748 & w2__h32750 ;
assign new_st_val__h34719 = w1__h32748 | w2__h32750 ;
assign new_st_val__h34723 =
(w1__h32748 < w2__h32750) ? w1__h32748 : w2__h32750 ;
assign new_st_val__h34728 =
(w1__h32748 <= w2__h32750) ? w2__h32750 : w1__h32748 ;
assign new_st_val__h34734 =
((new_ld_val__h32710 ^ 64'h8000000000000000) <
(IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ^
64'h8000000000000000)) ?
w1__h32748 :
w2__h32750 ;
assign new_st_val__h34739 =
((new_ld_val__h32710 ^ 64'h8000000000000000) <=
(IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ^
64'h8000000000000000)) ?
w2__h32750 :
w1__h32748 ;
assign new_value__h22441 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
64'd1 :
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_31_EQ__ETC__q52 ;
assign new_value__h6012 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
word64__h5847 :
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 ;
assign pa_ctag__h5533 = { 2'd0, rg_addr[31:12] } ;
assign ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 =
ram_state_and_ctag_cset$DOB[21:0] == pa_ctag__h5533 ;
assign ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117 =
ram_state_and_ctag_cset$DOB[44:23] == pa_ctag__h5533 ;
assign ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d165 =
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ;
assign ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d176 =
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 ;
assign ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 =
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d572 =
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 =
req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
assign result__h18723 =
{ {56{word64847_BITS_7_TO_0__q15[7]}},
word64847_BITS_7_TO_0__q15 } ;
assign result__h18751 =
{ {56{word64847_BITS_15_TO_8__q18[7]}},
word64847_BITS_15_TO_8__q18 } ;
assign result__h18779 =
{ {56{word64847_BITS_23_TO_16__q19[7]}},
word64847_BITS_23_TO_16__q19 } ;
assign result__h18807 =
{ {56{word64847_BITS_31_TO_24__q21[7]}},
word64847_BITS_31_TO_24__q21 } ;
assign result__h18835 =
{ {56{word64847_BITS_39_TO_32__q22[7]}},
word64847_BITS_39_TO_32__q22 } ;
assign result__h18863 =
{ {56{word64847_BITS_47_TO_40__q25[7]}},
word64847_BITS_47_TO_40__q25 } ;
assign result__h18891 =
{ {56{word64847_BITS_55_TO_48__q26[7]}},
word64847_BITS_55_TO_48__q26 } ;
assign result__h18919 =
{ {56{word64847_BITS_63_TO_56__q28[7]}},
word64847_BITS_63_TO_56__q28 } ;
assign result__h18964 = { 56'd0, word64__h5847[7:0] } ;
assign result__h18992 = { 56'd0, word64__h5847[15:8] } ;
assign result__h19020 = { 56'd0, word64__h5847[23:16] } ;
assign result__h19048 = { 56'd0, word64__h5847[31:24] } ;
assign result__h19076 = { 56'd0, word64__h5847[39:32] } ;
assign result__h19104 = { 56'd0, word64__h5847[47:40] } ;
assign result__h19132 = { 56'd0, word64__h5847[55:48] } ;
assign result__h19160 = { 56'd0, word64__h5847[63:56] } ;
assign result__h19205 =
{ {48{word64847_BITS_15_TO_0__q16[15]}},
word64847_BITS_15_TO_0__q16 } ;
assign result__h19233 =
{ {48{word64847_BITS_31_TO_16__q20[15]}},
word64847_BITS_31_TO_16__q20 } ;
assign result__h19261 =
{ {48{word64847_BITS_47_TO_32__q23[15]}},
word64847_BITS_47_TO_32__q23 } ;
assign result__h19289 =
{ {48{word64847_BITS_63_TO_48__q27[15]}},
word64847_BITS_63_TO_48__q27 } ;
assign result__h19330 = { 48'd0, word64__h5847[15:0] } ;
assign result__h19358 = { 48'd0, word64__h5847[31:16] } ;
assign result__h19386 = { 48'd0, word64__h5847[47:32] } ;
assign result__h19414 = { 48'd0, word64__h5847[63:48] } ;
assign result__h19455 =
{ {32{word64847_BITS_31_TO_0__q17[31]}},
word64847_BITS_31_TO_0__q17 } ;
assign result__h19483 =
{ {32{word64847_BITS_63_TO_32__q24[31]}},
word64847_BITS_63_TO_32__q24 } ;
assign result__h19522 = { 32'd0, word64__h5847[31:0] } ;
assign result__h19550 = { 32'd0, word64__h5847[63:32] } ;
assign result__h30564 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1[7]}},
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 } ;
assign result__h30594 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4[7]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 } ;
assign result__h30621 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6[7]}},
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6 } ;
assign result__h30648 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8[7]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8 } ;
assign result__h30675 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q5[7]}},
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q5 } ;
assign result__h30702 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11[7]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 } ;
assign result__h30729 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12[7]}},
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 } ;
assign result__h30756 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14[7]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 } ;
assign result__h30800 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
assign result__h30827 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
assign result__h30854 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
assign result__h30881 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
assign result__h30908 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
assign result__h30935 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
assign result__h30962 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
assign result__h30989 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
assign result__h31033 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2[15]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 } ;
assign result__h31060 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7[15]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7 } ;
assign result__h31087 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9[15]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 } ;
assign result__h31114 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13[15]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 } ;
assign result__h31154 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
assign result__h31181 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
assign result__h31208 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
assign result__h31235 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
assign result__h31275 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3[31]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 } ;
assign result__h31302 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10[31]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 } ;
assign result__h31340 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
assign result__h31367 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
assign result__h32939 =
{ {56{ld_val0504_BITS_7_TO_0__q36[7]}},
ld_val0504_BITS_7_TO_0__q36 } ;
assign result__h33847 =
{ {56{ld_val0504_BITS_15_TO_8__q39[7]}},
ld_val0504_BITS_15_TO_8__q39 } ;
assign result__h33875 =
{ {56{ld_val0504_BITS_23_TO_16__q40[7]}},
ld_val0504_BITS_23_TO_16__q40 } ;
assign result__h33903 =
{ {56{ld_val0504_BITS_31_TO_24__q42[7]}},
ld_val0504_BITS_31_TO_24__q42 } ;
assign result__h33931 =
{ {56{ld_val0504_BITS_39_TO_32__q43[7]}},
ld_val0504_BITS_39_TO_32__q43 } ;
assign result__h33959 =
{ {56{ld_val0504_BITS_47_TO_40__q46[7]}},
ld_val0504_BITS_47_TO_40__q46 } ;
assign result__h33987 =
{ {56{ld_val0504_BITS_55_TO_48__q47[7]}},
ld_val0504_BITS_55_TO_48__q47 } ;
assign result__h34015 =
{ {56{ld_val0504_BITS_63_TO_56__q49[7]}},
ld_val0504_BITS_63_TO_56__q49 } ;
assign result__h34060 = { 56'd0, ld_val__h30504[7:0] } ;
assign result__h34088 = { 56'd0, ld_val__h30504[15:8] } ;
assign result__h34116 = { 56'd0, ld_val__h30504[23:16] } ;
assign result__h34144 = { 56'd0, ld_val__h30504[31:24] } ;
assign result__h34172 = { 56'd0, ld_val__h30504[39:32] } ;
assign result__h34200 = { 56'd0, ld_val__h30504[47:40] } ;
assign result__h34228 = { 56'd0, ld_val__h30504[55:48] } ;
assign result__h34256 = { 56'd0, ld_val__h30504[63:56] } ;
assign result__h34301 =
{ {48{ld_val0504_BITS_15_TO_0__q37[15]}},
ld_val0504_BITS_15_TO_0__q37 } ;
assign result__h34329 =
{ {48{ld_val0504_BITS_31_TO_16__q41[15]}},
ld_val0504_BITS_31_TO_16__q41 } ;
assign result__h34357 =
{ {48{ld_val0504_BITS_47_TO_32__q44[15]}},
ld_val0504_BITS_47_TO_32__q44 } ;
assign result__h34385 =
{ {48{ld_val0504_BITS_63_TO_48__q48[15]}},
ld_val0504_BITS_63_TO_48__q48 } ;
assign result__h34426 = { 48'd0, ld_val__h30504[15:0] } ;
assign result__h34454 = { 48'd0, ld_val__h30504[31:16] } ;
assign result__h34482 = { 48'd0, ld_val__h30504[47:32] } ;
assign result__h34510 = { 48'd0, ld_val__h30504[63:48] } ;
assign result__h34551 =
{ {32{ld_val0504_BITS_31_TO_0__q38[31]}},
ld_val0504_BITS_31_TO_0__q38 } ;
assign result__h34579 =
{ {32{ld_val0504_BITS_63_TO_32__q45[31]}},
ld_val0504_BITS_63_TO_32__q45 } ;
assign result__h34618 = { 32'd0, ld_val__h30504[31:0] } ;
assign result__h34646 = { 32'd0, ld_val__h30504[63:32] } ;
assign rg_addr_9_EQ_rg_lrsc_pa_8___d166 = rg_addr == rg_lrsc_pa ;
assign rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_ra_ETC___d364 =
rg_amo_funct7[6:2] == 5'b00010 &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign rg_lrsc_pa_8_EQ_rg_addr_9___d99 = rg_lrsc_pa == rg_addr ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d139 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d170 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d165 ||
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d168) ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d180 =
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d170 ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d178 ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d182 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d185 =
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d182 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20012 ;
assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d178 =
rg_op == 2'd1 && rg_addr_9_EQ_rg_lrsc_pa_8___d166 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d176 ;
assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d391 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d388 ||
NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390 ;
assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d528 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) ;
assign rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562 =
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20012 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign rg_st_amo_val_BITS_31_TO_0__q32 = rg_st_amo_val[31:0] ;
assign rg_state_5_EQ_12_50_AND_rg_op_4_EQ_0_5_OR_rg_o_ETC___d652 =
rg_state == 4'd12 &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
b__h26623 == 4'd0 ;
assign shift_bits__h2606 = { f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ;
assign strobe64__h2756 = 8'b00000001 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h2758 = 8'b00000011 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h2760 = 8'b00001111 << f_fabric_write_reqs$D_OUT[66:64] ;
assign tmp__h26884 = { 1'd0, rg_victim_way } ;
assign tmp__h26885 = tmp__h26884 + 2'd1 ;
assign w12744_BITS_31_TO_0__q51 = w1__h32744[31:0] ;
assign w1___1__h23938 =
{ 32'd0,
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347[31:0] } ;
assign w1___1__h32819 = { 32'd0, w1__h32744[31:0] } ;
assign w2___1__h32820 = { 32'd0, rg_st_amo_val[31:0] } ;
assign w2__h32750 = (rg_f3 == 3'b010) ? w2___1__h32820 : rg_st_amo_val ;
assign word64847_BITS_15_TO_0__q16 = word64__h5847[15:0] ;
assign word64847_BITS_15_TO_8__q18 = word64__h5847[15:8] ;
assign word64847_BITS_23_TO_16__q19 = word64__h5847[23:16] ;
assign word64847_BITS_31_TO_0__q17 = word64__h5847[31:0] ;
assign word64847_BITS_31_TO_16__q20 = word64__h5847[31:16] ;
assign word64847_BITS_31_TO_24__q21 = word64__h5847[31:24] ;
assign word64847_BITS_39_TO_32__q22 = word64__h5847[39:32] ;
assign word64847_BITS_47_TO_32__q23 = word64__h5847[47:32] ;
assign word64847_BITS_47_TO_40__q25 = word64__h5847[47:40] ;
assign word64847_BITS_55_TO_48__q26 = word64__h5847[55:48] ;
assign word64847_BITS_63_TO_32__q24 = word64__h5847[63:32] ;
assign word64847_BITS_63_TO_48__q27 = word64__h5847[63:48] ;
assign word64847_BITS_63_TO_56__q28 = word64__h5847[63:56] ;
assign word64847_BITS_7_TO_0__q15 = word64__h5847[7:0] ;
assign word64__h5847 = x__h6037 | y__h6038 ;
assign x__h20022 = { 63'd0, lrsc_result__h20012 } ;
assign x__h32739 =
(rg_f3 == 3'b010) ?
new_st_val__h32760 :
_theResult_____2__h32756 ;
assign x__h6037 = ram_word64_set$DOB[63:0] & y__h6052 ;
assign y__h12367 =
{64{ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117}} ;
assign y__h6038 = ram_word64_set$DOB[127:64] & y__h12367 ;
assign y__h6052 =
{64{ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111}} ;
always@(f_fabric_write_reqs$D_OUT)
begin
case (f_fabric_write_reqs$D_OUT[97:96])
2'b0: x__h2639 = 3'b0;
2'b01: x__h2639 = 3'b001;
2'b10: x__h2639 = 3'b010;
2'b11: x__h2639 = 3'b011;
endcase
end
always@(rg_f3)
begin
case (rg_f3[1:0])
2'b0: value__h32296 = 3'b0;
2'b01: value__h32296 = 3'b001;
2'b10: value__h32296 = 3'b010;
2'd3: value__h32296 = 3'b011;
endcase
end
always@(f_fabric_write_reqs$D_OUT or
strobe64__h2756 or strobe64__h2758 or strobe64__h2760)
begin
case (f_fabric_write_reqs$D_OUT[97:96])
2'b0: mem_req_wr_data_wstrb__h2819 = strobe64__h2756;
2'b01: mem_req_wr_data_wstrb__h2819 = strobe64__h2758;
2'b10: mem_req_wr_data_wstrb__h2819 = strobe64__h2760;
2'b11: mem_req_wr_data_wstrb__h2819 = 8'b11111111;
endcase
end
always@(f_fabric_write_reqs$D_OUT or _theResult___snd_fst__h2826)
begin
case (f_fabric_write_reqs$D_OUT[97:96])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h2818 = _theResult___snd_fst__h2826;
2'd3: mem_req_wr_data_wdata__h2818 = f_fabric_write_reqs$D_OUT[63:0];
endcase
end
always@(ram_state_and_ctag_cset$DOB or
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117 or
ram_word64_set$DOB)
begin
case (ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117)
1'd0: old_word64__h20790 = ram_word64_set$DOB[63:0];
1'd1: old_word64__h20790 = ram_word64_set$DOB[127:64];
endcase
end
always@(rg_addr or
result__h18723 or
result__h18751 or
result__h18779 or
result__h18807 or
result__h18835 or
result__h18863 or result__h18891 or result__h18919)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18723;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18751;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18779;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18807;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18835;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18863;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18891;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18919;
endcase
end
always@(rg_addr or
result__h18964 or
result__h18992 or
result__h19020 or
result__h19048 or
result__h19076 or
result__h19104 or result__h19132 or result__h19160)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h18964;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h18992;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19020;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19048;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19076;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19104;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19132;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19160;
endcase
end
always@(rg_addr or
result__h19205 or
result__h19233 or result__h19261 or result__h19289)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
result__h19205;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
result__h19233;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
result__h19261;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
result__h19289;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
64'd0;
endcase
end
always@(rg_addr or
result__h19330 or
result__h19358 or result__h19386 or result__h19414)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
result__h19330;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
result__h19358;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
result__h19386;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
result__h19414;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
64'd0;
endcase
end
always@(rg_addr or result__h19522 or result__h19550)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338 =
result__h19522;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338 =
result__h19550;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338 =
64'd0;
endcase
end
always@(rg_addr or result__h19455 or result__h19483)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29 =
result__h19455;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29 =
result__h19483;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 or
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338)
begin
case (rg_f3)
3'b0:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287;
3'b001:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317;
3'b010:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29;
3'b011:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340;
3'b100:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304;
3'b101:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326;
3'b110:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338;
3'd7: IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 or
w1___1__h23938 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338)
begin
case (rg_f3)
3'b0:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287;
3'b001:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317;
3'b010: w1__h23867 = w1___1__h23938;
3'b011:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340;
3'b100:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304;
3'b101:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326;
3'b110:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338;
3'd7: w1__h23867 = 64'd0;
endcase
end
always@(rg_addr or old_word64__h20790 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
{ old_word64__h20790[63:16], rg_st_amo_val[15:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
{ old_word64__h20790[63:32],
rg_st_amo_val[15:0],
old_word64__h20790[15:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
{ old_word64__h20790[63:48],
rg_st_amo_val[15:0],
old_word64__h20790[31:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
{ rg_st_amo_val[15:0], old_word64__h20790[47:0] };
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
old_word64__h20790;
endcase
end
always@(rg_addr or old_word64__h20790 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:8], rg_st_amo_val[7:0] };
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:16],
rg_st_amo_val[7:0],
old_word64__h20790[7:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:24],
rg_st_amo_val[7:0],
old_word64__h20790[15:0] };
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:32],
rg_st_amo_val[7:0],
old_word64__h20790[23:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:40],
rg_st_amo_val[7:0],
old_word64__h20790[31:0] };
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:48],
rg_st_amo_val[7:0],
old_word64__h20790[39:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:56],
rg_st_amo_val[7:0],
old_word64__h20790[47:0] };
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ rg_st_amo_val[7:0], old_word64__h20790[55:0] };
endcase
end
always@(rg_addr or old_word64__h20790 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30 =
{ old_word64__h20790[63:32], rg_st_amo_val[31:0] };
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30 =
{ rg_st_amo_val[31:0], old_word64__h20790[31:0] };
default: CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30 =
old_word64__h20790;
endcase
end
always@(rg_f3 or
old_word64__h20790 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 or
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30 or
rg_st_amo_val)
begin
case (rg_f3)
3'b0:
n__h20801 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428;
3'b001:
n__h20801 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437;
3'b010:
n__h20801 = CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30;
3'b011: n__h20801 = rg_st_amo_val;
default: n__h20801 = old_word64__h20790;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 or
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338)
begin
case (rg_f3)
3'b0:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287;
3'b001:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317;
3'b010:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
{ {32{IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31[31]}},
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31 };
3'b011:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340;
3'b100:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304;
3'b101:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326;
3'b110:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338;
3'd7: IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h24978 or
new_st_val__h23970 or
w2__h32750 or
new_st_val__h24950 or
new_st_val__h24958 or
new_st_val__h24954 or
new_st_val__h24973 or new_st_val__h24962 or new_st_val__h24967)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h23875 = new_st_val__h23970;
5'b00001: _theResult_____2__h23875 = w2__h32750;
5'b00100: _theResult_____2__h23875 = new_st_val__h24950;
5'b01000: _theResult_____2__h23875 = new_st_val__h24958;
5'b01100: _theResult_____2__h23875 = new_st_val__h24954;
5'b10000: _theResult_____2__h23875 = new_st_val__h24973;
5'b11000: _theResult_____2__h23875 = new_st_val__h24962;
5'b11100: _theResult_____2__h23875 = new_st_val__h24967;
default: _theResult_____2__h23875 = new_st_val__h24978;
endcase
end
always@(rg_addr or old_word64__h20790 or new_st_val__h23573)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
{ old_word64__h20790[63:16], new_st_val__h23573[15:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
{ old_word64__h20790[63:32],
new_st_val__h23573[15:0],
old_word64__h20790[15:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
{ old_word64__h20790[63:48],
new_st_val__h23573[15:0],
old_word64__h20790[31:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
{ new_st_val__h23573[15:0], old_word64__h20790[47:0] };
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
old_word64__h20790;
endcase
end
always@(rg_addr or old_word64__h20790 or new_st_val__h23573)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:8], new_st_val__h23573[7:0] };
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:16],
new_st_val__h23573[7:0],
old_word64__h20790[7:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:24],
new_st_val__h23573[7:0],
old_word64__h20790[15:0] };
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:32],
new_st_val__h23573[7:0],
old_word64__h20790[23:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:40],
new_st_val__h23573[7:0],
old_word64__h20790[31:0] };
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:48],
new_st_val__h23573[7:0],
old_word64__h20790[39:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:56],
new_st_val__h23573[7:0],
old_word64__h20790[47:0] };
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ new_st_val__h23573[7:0], old_word64__h20790[55:0] };
endcase
end
always@(rg_addr or old_word64__h20790 or new_st_val__h23573)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33 =
{ old_word64__h20790[63:32], new_st_val__h23573[31:0] };
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33 =
{ new_st_val__h23573[31:0], old_word64__h20790[31:0] };
default: CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33 =
old_word64__h20790;
endcase
end
always@(rg_f3 or
old_word64__h20790 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 or
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33 or
new_st_val__h23573)
begin
case (rg_f3)
3'b0:
n__h23737 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505;
3'b001:
n__h23737 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514;
3'b010:
n__h23737 = CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33;
3'b011: n__h23737 = new_st_val__h23573;
default: n__h23737 = old_word64__h20790;
endcase
end
always@(rg_addr or
result__h31154 or
result__h31181 or result__h31208 or result__h31235)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
result__h31154;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
result__h31181;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
result__h31208;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
result__h31235;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
64'd0;
endcase
end
always@(rg_addr or
result__h31033 or
result__h31060 or result__h31087 or result__h31114)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
result__h31033;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
result__h31060;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
result__h31087;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
result__h31114;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
64'd0;
endcase
end
always@(rg_addr or
result__h30800 or
result__h30827 or
result__h30854 or
result__h30881 or
result__h30908 or
result__h30935 or result__h30962 or result__h30989)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30800;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30827;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30854;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30881;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30908;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30935;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30962;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30989;
endcase
end
always@(rg_addr or
result__h30564 or
result__h30594 or
result__h30621 or
result__h30648 or
result__h30675 or
result__h30702 or result__h30729 or result__h30756)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30564;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30594;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30621;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30648;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30675;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30702;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30729;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30756;
endcase
end
always@(rg_addr or result__h31275 or result__h31302)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34 =
result__h31275;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34 =
result__h31302;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34 =
64'd0;
endcase
end
always@(rg_addr or result__h31340 or result__h31367)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35 =
result__h31340;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35 =
result__h31367;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34 or
rg_addr or
master_xactor_f_rd_data$D_OUT or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35)
begin
case (rg_f3)
3'b0:
ld_val__h30504 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695;
3'b001:
ld_val__h30504 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723;
3'b010:
ld_val__h30504 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34;
3'b011:
ld_val__h30504 =
(rg_addr[2:0] == 3'h0) ?
master_xactor_f_rd_data$D_OUT[66:3] :
64'd0;
3'b100:
ld_val__h30504 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711;
3'b101:
ld_val__h30504 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731;
3'b110:
ld_val__h30504 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35;
3'd7: ld_val__h30504 = 64'd0;
endcase
end
always@(rg_addr or result__h34618 or result__h34646)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850 =
result__h34618;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850 =
result__h34646;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850 =
64'd0;
endcase
end
always@(rg_addr or
result__h34426 or
result__h34454 or result__h34482 or result__h34510)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
result__h34426;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
result__h34454;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
result__h34482;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
result__h34510;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
64'd0;
endcase
end
always@(rg_addr or
result__h34301 or
result__h34329 or result__h34357 or result__h34385)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
result__h34301;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
result__h34329;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
result__h34357;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
result__h34385;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
64'd0;
endcase
end
always@(rg_addr or
result__h34060 or
result__h34088 or
result__h34116 or
result__h34144 or
result__h34172 or
result__h34200 or result__h34228 or result__h34256)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34060;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34088;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34116;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34144;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34172;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34200;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34228;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34256;
endcase
end
always@(rg_addr or
result__h32939 or
result__h33847 or
result__h33875 or
result__h33903 or
result__h33931 or
result__h33959 or result__h33987 or result__h34015)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h32939;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33847;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33875;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33903;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33931;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33959;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33987;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h34015;
endcase
end
always@(rg_addr or result__h34551 or result__h34579)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50 =
result__h34551;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50 =
result__h34579;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 or
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850)
begin
case (rg_f3)
3'b0:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804;
3'b001:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832;
3'b010:
w1__h32744 =
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50;
3'b011:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851;
3'b100:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820;
3'b101:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840;
3'b110:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850;
3'd7: w1__h32744 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 or
w1___1__h32819 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850)
begin
case (rg_f3)
3'b0:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804;
3'b001:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832;
3'b010: w1__h32748 = w1___1__h32819;
3'b011:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851;
3'b100:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820;
3'b101:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840;
3'b110:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850;
3'd7: w1__h32748 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 or
w12744_BITS_31_TO_0__q51 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850)
begin
case (rg_f3)
3'b0:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804;
3'b001:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832;
3'b010:
new_ld_val__h32710 =
{ {32{w12744_BITS_31_TO_0__q51[31]}},
w12744_BITS_31_TO_0__q51 };
3'b011:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851;
3'b100:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820;
3'b101:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840;
3'b110:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850;
3'd7: new_ld_val__h32710 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h34739 or
new_st_val__h32851 or
w2__h32750 or
new_st_val__h34711 or
new_st_val__h34719 or
new_st_val__h34715 or
new_st_val__h34734 or new_st_val__h34723 or new_st_val__h34728)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h32756 = new_st_val__h32851;
5'b00001: _theResult_____2__h32756 = w2__h32750;
5'b00100: _theResult_____2__h32756 = new_st_val__h34711;
5'b01000: _theResult_____2__h32756 = new_st_val__h34719;
5'b01100: _theResult_____2__h32756 = new_st_val__h34715;
5'b10000: _theResult_____2__h32756 = new_st_val__h34734;
5'b11000: _theResult_____2__h32756 = new_st_val__h34723;
5'b11100: _theResult_____2__h32756 = new_st_val__h34728;
default: _theResult_____2__h32756 = new_st_val__h34739;
endcase
end
always@(rg_f3 or IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_1_E_ETC___d355)
begin
case (rg_f3)
3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_31_EQ__ETC__q52 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_1_E_ETC___d355;
3'd7: CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_31_EQ__ETC__q52 = 64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0;
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (ctr_wr_rsps_pending_crg$EN)
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
ctr_wr_rsps_pending_crg$D_IN;
if (rg_cset_in_cache$EN)
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
if (rg_lower_word32_full$EN)
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
rg_lower_word32_full$D_IN;
if (rg_lrsc_valid$EN)
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
if (rg_amo_funct7$EN)
rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
if (rg_error_during_refill$EN)
rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
rg_error_during_refill$D_IN;
if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
if (rg_lower_word32$EN)
rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
if (rg_st_amo_val$EN)
rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
if (rg_victim_way$EN)
rg_victim_way <= `BSV_ASSIGNMENT_DELAY rg_victim_way$D_IN;
if (rg_word64_set_in_cache$EN)
rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY
rg_word64_set_in_cache$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
ctr_wr_rsps_pending_crg = 4'hA;
rg_addr = 32'hAAAAAAAA;
rg_amo_funct7 = 7'h2A;
rg_cset_in_cache = 7'h2A;
rg_error_during_refill = 1'h0;
rg_exc_code = 4'hA;
rg_f3 = 3'h2;
rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
rg_lower_word32 = 32'hAAAAAAAA;
rg_lower_word32_full = 1'h0;
rg_lrsc_pa = 32'hAAAAAAAA;
rg_lrsc_valid = 1'h0;
rg_op = 2'h2;
rg_pa = 32'hAAAAAAAA;
rg_pte_pa = 32'hAAAAAAAA;
rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
rg_state = 4'hA;
rg_victim_way = 1'h0;
rg_word64_set_in_cache = 9'h0AA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", mem_req_wr_addr_awaddr__h2592);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", x__h2639);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", mem_req_wr_data_wdata__h2818);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", mem_req_wr_data_wstrb__h2819);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
begin
v__h4093 = $stime;
#0;
end
v__h4087 = v__h4093 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4087,
"D_MMU_Cache",
$signed(32'd128),
$signed(32'd2));
else
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4087,
"I_MMU_Cache",
$signed(32'd128),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
f_reset_reqs$D_OUT)
begin
v__h4192 = $stime;
#0;
end
v__h4186 = v__h4192 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: Flushed", v__h4186, "D_MMU_Cache");
else
$display("%0d: %s.rl_reset: Flushed", v__h4186, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h4341 = $stime;
#0;
end
v__h4335 = v__h4341 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4335,
"D_MMU_Cache",
rg_addr);
else
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4335,
"I_MMU_Cache",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}",
pa_ctag__h5533,
rg_addr[11:5],
rg_addr[4:3],
rg_addr[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" CSet 0x%0x: (state, tag):", rg_addr[11:5]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
ram_state_and_ctag_cset$DOB[22])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!ram_state_and_ctag_cset$DOB[22])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
ram_state_and_ctag_cset$DOB[22])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[21:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!ram_state_and_ctag_cset$DOB[22])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
ram_state_and_ctag_cset$DOB[45])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!ram_state_and_ctag_cset$DOB[45])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
ram_state_and_ctag_cset$DOB[45])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[44:23]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!ram_state_and_ctag_cset$DOB[45])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_addr[4:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" 0x%0x", ram_word64_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" 0x%0x", ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" TLB result: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("VM_Xlate_Result { ", "outcome: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("VM_XLATE_OK");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'hA, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem &&
!soc_map$m_is_mem_addr &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => IO_REQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d162)
$display(" ASSERTION ERROR: fn_test_cache_hit_or_miss: multiple hits in set at [%0d] and [%0d]",
$signed(32'd1),
1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361)
begin
v__h19635 = $stime;
#0;
end
v__h19629 = v__h19635 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h19629,
"D_MMU_Cache",
rg_addr,
word64__h5847,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h19629,
"I_MMU_Cache",
rg_addr,
word64__h5847,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d369)
$display(" AMO LR: reserving PA 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361)
$display(" Read-hit: addr 0x%0h word64 0x%0h",
rg_addr,
word64__h5847);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d372)
$display(" Read Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d378)
$display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
rg_lrsc_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d535)
$display(" ST: cancelling LR/SC reservation for PA", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
rg_lrsc_valid &&
!rg_lrsc_pa_8_EQ_rg_addr_9___d99 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
rg_lrsc_pa,
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
!rg_lrsc_valid &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" AMO SC: fail due to invalid LR/SC reservation");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d547)
$display(" AMO SC result = %0d", lrsc_result__h20012);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_addr[4:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d448);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d447);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d552)
$display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d558)
$display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d558)
$display(" => rl_write_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562)
begin
v__h23351 = $stime;
#0;
end
v__h23345 = v__h23351 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h23345,
"D_MMU_Cache",
rg_addr,
64'd1,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h23345,
"I_MMU_Cache",
rg_addr,
64'd1,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562)
$display(" AMO SC: Fail response for addr 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370)
$display(" AMO Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
rg_addr,
rg_amo_funct7,
rg_f3,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$display(" PA 0x%0h ", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$display(" Cache word64 0x%0h, load-result 0x%0h",
word64__h5847,
word64__h5847);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$display(" 0x%0h op 0x%0h -> 0x%0h",
word64__h5847,
word64__h5847,
new_st_val__h23573);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_addr[4:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d525);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d524);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d572)
$display(" AMO_op: cancelling LR/SC reservation for PA",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h26669 = $stime;
#0;
end
v__h26663 = v__h26669 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_start_cache_refill: ",
v__h26663,
"D_MMU_Cache");
else
$display("%0d: %s.rl_start_cache_refill: ",
v__h26663,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", cline_fabric_addr__h26722);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 8'd3);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" Victim way %0d; => CACHE_REFILL", tmp__h26885[0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
begin
v__h27408 = $stime;
#0;
end
v__h27402 = v__h27408 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27402,
"D_MMU_Cache");
else
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27402,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h27649 = $stime;
#0;
end
v__h27643 = v__h27649 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27643,
"D_MMU_Cache",
access_exc_code__h2374);
else
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27643,
"I_MMU_Cache",
access_exc_code__h2374);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd3 &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => MODULE_EXCEPTION_RSP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd3 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!rg_error_during_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => CACHE_REREQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new",
rg_word64_set_in_cache,
rg_word64_set_in_cache[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_word64_set_in_cache[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" 0x%0x", ram_word64_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" 0x%0x", ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_word64_set_in_cache[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" 0x%0x",
rg_victim_way ?
ram_word64_set$DOB[63:0] :
master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" 0x%0x",
rg_victim_way ?
master_xactor_f_rd_data$D_OUT[66:3] :
ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
rg_addr[11:5],
rg_addr[11:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h30045 = $stime;
#0;
end
v__h30039 = v__h30045 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h30039,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h30039,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", fabric_addr__h32167);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", value__h32296);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h30395 = $stime;
#0;
end
v__h30389 = v__h30395 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h30389,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h30389,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31495 = $stime;
#0;
end
v__h31489 = v__h31495 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31489,
"D_MMU_Cache",
rg_addr,
ld_val__h30504);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31489,
"I_MMU_Cache",
rg_addr,
ld_val__h30504);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31602 = $stime;
#0;
end
v__h31596 = v__h31602 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31596,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31596,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31707 = $stime;
#0;
end
v__h31701 = v__h31707 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31701,
"D_MMU_Cache",
rg_addr,
rg_ld_val);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31701,
"I_MMU_Cache",
rg_addr,
rg_ld_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31787 = $stime;
#0;
end
v__h31781 = v__h31787 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31781,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31781,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31997 = $stime;
#0;
end
v__h31991 = v__h31997 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31991,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31991,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" FAIL due to I/O address.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h32115 = $stime;
#0;
end
v__h32109 = v__h32115 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32109,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32109,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", fabric_addr__h32167);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", value__h32296);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h32409 = $stime;
#0;
end
v__h32403 = v__h32409 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32403,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32403,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h32584 = $stime;
#0;
end
v__h32578 = v__h32584 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32578,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32578,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h34843 = $stime;
#0;
end
v__h34837 = v__h34843 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h34837,
"D_MMU_Cache",
rg_addr,
new_ld_val__h32710);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h34837,
"I_MMU_Cache",
rg_addr,
new_ld_val__h32710);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h32680 = $stime;
#0;
end
v__h32674 = v__h32680 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32674,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32674,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h35450 = $stime;
#0;
end
v__h35444 = v__h35450 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h35444,
"D_MMU_Cache",
$unsigned(b__h26623));
else
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h35444,
"I_MMU_Cache",
$unsigned(b__h26623));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
begin
v__h35411 = $stime;
#0;
end
v__h35405 = v__h35411 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
if (dmem_not_imem)
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h35405,
"D_MMU_Cache");
else
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h35405,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
begin
v__h3625 = $stime;
#0;
end
v__h3619 = v__h3625 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
if (dmem_not_imem)
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h3619,
"D_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd32),
$signed(32'd8));
else
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h3619,
"I_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd32),
$signed(32'd8));
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h35798 = $stime;
#0;
end
v__h35792 = v__h35798 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("%0d: %m.req: op:", v__h35792);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 && req_op == 2'd0)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 && req_op == 2'd1)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_op != 2'd0 &&
req_op != 2'd1)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" f3:%0d addr:0x%0h st_value:0x%0h",
req_f3,
req_addr,
req_st_value,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" priv:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_priv == 2'b0)
$write("U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_priv == 2'b01)
$write("S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_priv == 2'b11)
$write("M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_priv != 2'b0 &&
req_priv != 2'b01 &&
req_priv != 2'b11)
$write("RESERVED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" amo_funct7 = 0x%0h", req_amo_funct7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req &&
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
req_addr[11:5],
req_addr[11:3]);
end
// synopsys translate_on
endmodule // mkMMU_Cache
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module select2 (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("select2.mif"),
.C_INIT_FILE("select2.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(2109),
.C_READ_DEPTH_A(2109),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(2109),
.C_READ_DEPTH_B(2109),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.822999 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** PCIe wrapper +
//*/
module pcie_4243_hip_s4gx_gen2_x8_128_plus (
// inputs:
app_int_sts,
app_msi_num,
app_msi_req,
app_msi_tc,
cpl_err,
cpl_pending,
fixedclk_serdes,
lmi_addr,
lmi_din,
lmi_rden,
lmi_wren,
local_rstn,
pcie_rstn,
pclk_in,
pex_msi_num,
phystatus_ext,
pipe_mode,
pld_clk,
pm_auxpwr,
pm_data,
pm_event,
pme_to_cr,
reconfig_clk,
reconfig_clk_locked,
refclk,
rx_in0,
rx_in1,
rx_in2,
rx_in3,
rx_in4,
rx_in5,
rx_in6,
rx_in7,
rx_st_mask0,
rx_st_ready0,
rxdata0_ext,
rxdata1_ext,
rxdata2_ext,
rxdata3_ext,
rxdata4_ext,
rxdata5_ext,
rxdata6_ext,
rxdata7_ext,
rxdatak0_ext,
rxdatak1_ext,
rxdatak2_ext,
rxdatak3_ext,
rxdatak4_ext,
rxdatak5_ext,
rxdatak6_ext,
rxdatak7_ext,
rxelecidle0_ext,
rxelecidle1_ext,
rxelecidle2_ext,
rxelecidle3_ext,
rxelecidle4_ext,
rxelecidle5_ext,
rxelecidle6_ext,
rxelecidle7_ext,
rxstatus0_ext,
rxstatus1_ext,
rxstatus2_ext,
rxstatus3_ext,
rxstatus4_ext,
rxstatus5_ext,
rxstatus6_ext,
rxstatus7_ext,
rxvalid0_ext,
rxvalid1_ext,
rxvalid2_ext,
rxvalid3_ext,
rxvalid4_ext,
rxvalid5_ext,
rxvalid6_ext,
rxvalid7_ext,
test_in,
tx_st_data0,
tx_st_empty0,
tx_st_eop0,
tx_st_err0,
tx_st_sop0,
tx_st_valid0,
// outputs:
app_int_ack,
app_msi_ack,
clk250_out,
clk500_out,
core_clk_out,
lane_act,
lmi_ack,
lmi_dout,
ltssm,
pme_to_sr,
powerdown_ext,
rate_ext,
rc_pll_locked,
rx_st_bardec0,
rx_st_be0,
rx_st_data0,
rx_st_empty0,
rx_st_eop0,
rx_st_err0,
rx_st_sop0,
rx_st_valid0,
rxpolarity0_ext,
rxpolarity1_ext,
rxpolarity2_ext,
rxpolarity3_ext,
rxpolarity4_ext,
rxpolarity5_ext,
rxpolarity6_ext,
rxpolarity7_ext,
srstn,
test_out,
tl_cfg_add,
tl_cfg_ctl,
tl_cfg_ctl_wr,
tl_cfg_sts,
tl_cfg_sts_wr,
tx_cred0,
tx_fifo_empty0,
tx_out0,
tx_out1,
tx_out2,
tx_out3,
tx_out4,
tx_out5,
tx_out6,
tx_out7,
tx_st_ready0,
txcompl0_ext,
txcompl1_ext,
txcompl2_ext,
txcompl3_ext,
txcompl4_ext,
txcompl5_ext,
txcompl6_ext,
txcompl7_ext,
txdata0_ext,
txdata1_ext,
txdata2_ext,
txdata3_ext,
txdata4_ext,
txdata5_ext,
txdata6_ext,
txdata7_ext,
txdatak0_ext,
txdatak1_ext,
txdatak2_ext,
txdatak3_ext,
txdatak4_ext,
txdatak5_ext,
txdatak6_ext,
txdatak7_ext,
txdetectrx_ext,
txelecidle0_ext,
txelecidle1_ext,
txelecidle2_ext,
txelecidle3_ext,
txelecidle4_ext,
txelecidle5_ext,
txelecidle6_ext,
txelecidle7_ext
)
;
output app_int_ack;
output app_msi_ack;
output clk250_out;
output clk500_out;
output core_clk_out;
output [ 3: 0] lane_act;
output lmi_ack;
output [ 31: 0] lmi_dout;
output [ 4: 0] ltssm;
output pme_to_sr;
output [ 1: 0] powerdown_ext;
output rate_ext;
output rc_pll_locked;
output [ 7: 0] rx_st_bardec0;
output [ 15: 0] rx_st_be0;
output [127: 0] rx_st_data0;
output rx_st_empty0;
output rx_st_eop0;
output rx_st_err0;
output rx_st_sop0;
output rx_st_valid0;
output rxpolarity0_ext;
output rxpolarity1_ext;
output rxpolarity2_ext;
output rxpolarity3_ext;
output rxpolarity4_ext;
output rxpolarity5_ext;
output rxpolarity6_ext;
output rxpolarity7_ext;
output srstn;
output [ 63: 0] test_out;
output [ 3: 0] tl_cfg_add;
output [ 31: 0] tl_cfg_ctl;
output tl_cfg_ctl_wr;
output [ 52: 0] tl_cfg_sts;
output tl_cfg_sts_wr;
output [ 35: 0] tx_cred0;
output tx_fifo_empty0;
output tx_out0;
output tx_out1;
output tx_out2;
output tx_out3;
output tx_out4;
output tx_out5;
output tx_out6;
output tx_out7;
output tx_st_ready0;
output txcompl0_ext;
output txcompl1_ext;
output txcompl2_ext;
output txcompl3_ext;
output txcompl4_ext;
output txcompl5_ext;
output txcompl6_ext;
output txcompl7_ext;
output [ 7: 0] txdata0_ext;
output [ 7: 0] txdata1_ext;
output [ 7: 0] txdata2_ext;
output [ 7: 0] txdata3_ext;
output [ 7: 0] txdata4_ext;
output [ 7: 0] txdata5_ext;
output [ 7: 0] txdata6_ext;
output [ 7: 0] txdata7_ext;
output txdatak0_ext;
output txdatak1_ext;
output txdatak2_ext;
output txdatak3_ext;
output txdatak4_ext;
output txdatak5_ext;
output txdatak6_ext;
output txdatak7_ext;
output txdetectrx_ext;
output txelecidle0_ext;
output txelecidle1_ext;
output txelecidle2_ext;
output txelecidle3_ext;
output txelecidle4_ext;
output txelecidle5_ext;
output txelecidle6_ext;
output txelecidle7_ext;
input app_int_sts;
input [ 4: 0] app_msi_num;
input app_msi_req;
input [ 2: 0] app_msi_tc;
input [ 6: 0] cpl_err;
input cpl_pending;
input fixedclk_serdes;
input [ 11: 0] lmi_addr;
input [ 31: 0] lmi_din;
input lmi_rden;
input lmi_wren;
input local_rstn;
input pcie_rstn;
input pclk_in;
input [ 4: 0] pex_msi_num;
input phystatus_ext;
input pipe_mode;
input pld_clk;
input pm_auxpwr;
input [ 9: 0] pm_data;
input pm_event;
input pme_to_cr;
input reconfig_clk;
input reconfig_clk_locked;
input refclk;
input rx_in0;
input rx_in1;
input rx_in2;
input rx_in3;
input rx_in4;
input rx_in5;
input rx_in6;
input rx_in7;
input rx_st_mask0;
input rx_st_ready0;
input [ 7: 0] rxdata0_ext;
input [ 7: 0] rxdata1_ext;
input [ 7: 0] rxdata2_ext;
input [ 7: 0] rxdata3_ext;
input [ 7: 0] rxdata4_ext;
input [ 7: 0] rxdata5_ext;
input [ 7: 0] rxdata6_ext;
input [ 7: 0] rxdata7_ext;
input rxdatak0_ext;
input rxdatak1_ext;
input rxdatak2_ext;
input rxdatak3_ext;
input rxdatak4_ext;
input rxdatak5_ext;
input rxdatak6_ext;
input rxdatak7_ext;
input rxelecidle0_ext;
input rxelecidle1_ext;
input rxelecidle2_ext;
input rxelecidle3_ext;
input rxelecidle4_ext;
input rxelecidle5_ext;
input rxelecidle6_ext;
input rxelecidle7_ext;
input [ 2: 0] rxstatus0_ext;
input [ 2: 0] rxstatus1_ext;
input [ 2: 0] rxstatus2_ext;
input [ 2: 0] rxstatus3_ext;
input [ 2: 0] rxstatus4_ext;
input [ 2: 0] rxstatus5_ext;
input [ 2: 0] rxstatus6_ext;
input [ 2: 0] rxstatus7_ext;
input rxvalid0_ext;
input rxvalid1_ext;
input rxvalid2_ext;
input rxvalid3_ext;
input rxvalid4_ext;
input rxvalid5_ext;
input rxvalid6_ext;
input rxvalid7_ext;
input [ 39: 0] test_in;
input [127: 0] tx_st_data0;
input tx_st_empty0;
input tx_st_eop0;
input tx_st_err0;
input tx_st_sop0;
input tx_st_valid0;
wire app_int_ack;
wire app_msi_ack;
wire busy_altgxb_reconfig;
wire busy_altgxb_reconfig_altr;
wire clk250_out;
wire clk500_out;
wire core_clk_out;
wire crst;
wire data_valid;
wire dlup_exit;
wire [ 4: 0] gnd_hpg_ctrler;
wire gxb_powerdown;
wire hotrst_exit;
wire hotrst_exit_altr;
wire l2_exit;
wire [ 3: 0] lane_act;
wire lmi_ack;
wire [ 31: 0] lmi_dout;
wire [ 4: 0] ltssm;
wire npor;
wire npor_serdes_pll_locked;
wire offset_cancellation_reset;
wire open_rx_fifo_empty0;
wire open_rx_fifo_full0;
wire open_tx_fifo_full0;
wire [ 3: 0] open_tx_fifo_rdptr0;
wire [ 3: 0] open_tx_fifo_wrptr0;
wire otb0;
wire otb1;
wire pll_powerdown;
wire pme_to_sr;
wire [ 1: 0] powerdown_ext;
wire rate_ext;
wire rc_pll_locked;
wire [ 33: 0] reconfig_fromgxb;
wire [ 3: 0] reconfig_togxb;
wire [ 3: 0] rx_eqctrl_out;
wire [ 2: 0] rx_eqdcgain_out;
wire [ 7: 0] rx_st_bardec0;
wire [ 15: 0] rx_st_be0;
wire [127: 0] rx_st_data0;
wire rx_st_empty0;
wire rx_st_eop0;
wire rx_st_err0;
wire rx_st_sop0;
wire rx_st_valid0;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire rxpolarity4_ext;
wire rxpolarity5_ext;
wire rxpolarity6_ext;
wire rxpolarity7_ext;
wire srst;
wire srstn;
wire [ 63: 0] test_out;
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
wire [ 52: 0] tl_cfg_sts;
wire tl_cfg_sts_wr;
wire [ 35: 0] tx_cred0;
wire tx_fifo_empty0;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire tx_out4;
wire tx_out5;
wire tx_out6;
wire tx_out7;
wire [ 4: 0] tx_preemp_0t_out;
wire [ 4: 0] tx_preemp_1t_out;
wire [ 4: 0] tx_preemp_2t_out;
wire tx_st_ready0;
wire [ 2: 0] tx_vodctrl_out;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire txcompl4_ext;
wire txcompl5_ext;
wire txcompl6_ext;
wire txcompl7_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire [ 7: 0] txdata4_ext;
wire [ 7: 0] txdata5_ext;
wire [ 7: 0] txdata6_ext;
wire [ 7: 0] txdata7_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdatak4_ext;
wire txdatak5_ext;
wire txdatak6_ext;
wire txdatak7_ext;
wire txdetectrx_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
wire txelecidle4_ext;
wire txelecidle5_ext;
wire txelecidle6_ext;
wire txelecidle7_ext;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
assign offset_cancellation_reset = ~reconfig_clk_locked;
assign gnd_hpg_ctrler = 0;
assign busy_altgxb_reconfig_altr = (pipe_mode==otb1)?otb0:busy_altgxb_reconfig;
assign gxb_powerdown = ~npor;
assign hotrst_exit_altr = hotrst_exit;
assign pll_powerdown = ~npor;
assign npor_serdes_pll_locked = pcie_rstn & local_rstn & rc_pll_locked;
assign npor = pcie_rstn & local_rstn;
pcie_4243_hip_s4gx_gen2_x8_128 epmap
(
.app_int_ack (app_int_ack),
.app_int_sts (app_int_sts),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.busy_altgxb_reconfig (busy_altgxb_reconfig_altr),
.cal_blk_clk (reconfig_clk),
.clk250_out (clk250_out),
.clk500_out (clk500_out),
.core_clk_out (core_clk_out),
.cpl_err (cpl_err),
.cpl_pending (cpl_pending),
.crst (crst),
.dlup_exit (dlup_exit),
.fixedclk_serdes (fixedclk_serdes),
.gxb_powerdown (gxb_powerdown),
.hotrst_exit (hotrst_exit),
.hpg_ctrler (gnd_hpg_ctrler),
.l2_exit (l2_exit),
.lane_act (lane_act),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_dout (lmi_dout),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.ltssm (ltssm),
.npor (npor),
.pclk_in (pclk_in),
.pex_msi_num (pex_msi_num),
.phystatus_ext (phystatus_ext),
.pipe_mode (pipe_mode),
.pld_clk (pld_clk),
.pll_powerdown (pll_powerdown),
.pm_auxpwr (pm_auxpwr),
.pm_data (pm_data),
.pm_event (pm_event),
.pme_to_cr (pme_to_cr),
.pme_to_sr (pme_to_sr),
.powerdown_ext (powerdown_ext),
.rate_ext (rate_ext),
.rc_pll_locked (rc_pll_locked),
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb),
.reconfig_togxb (reconfig_togxb),
.refclk (refclk),
.rx_fifo_empty0 (open_rx_fifo_empty0),
.rx_fifo_full0 (open_rx_fifo_full0),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rx_in4 (rx_in4),
.rx_in5 (rx_in5),
.rx_in6 (rx_in6),
.rx_in7 (rx_in7),
.rx_st_bardec0 (rx_st_bardec0),
.rx_st_be0 (rx_st_be0),
.rx_st_data0 (rx_st_data0),
.rx_st_empty0 (rx_st_empty0),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (rx_st_err0),
.rx_st_mask0 (rx_st_mask0),
.rx_st_ready0 (rx_st_ready0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_valid0 (rx_st_valid0),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdata4_ext (rxdata4_ext),
.rxdata5_ext (rxdata5_ext),
.rxdata6_ext (rxdata6_ext),
.rxdata7_ext (rxdata7_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxdatak4_ext (rxdatak4_ext),
.rxdatak5_ext (rxdatak5_ext),
.rxdatak6_ext (rxdatak6_ext),
.rxdatak7_ext (rxdatak7_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxelecidle4_ext (rxelecidle4_ext),
.rxelecidle5_ext (rxelecidle5_ext),
.rxelecidle6_ext (rxelecidle6_ext),
.rxelecidle7_ext (rxelecidle7_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxpolarity4_ext (rxpolarity4_ext),
.rxpolarity5_ext (rxpolarity5_ext),
.rxpolarity6_ext (rxpolarity6_ext),
.rxpolarity7_ext (rxpolarity7_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxstatus4_ext (rxstatus4_ext),
.rxstatus5_ext (rxstatus5_ext),
.rxstatus6_ext (rxstatus6_ext),
.rxstatus7_ext (rxstatus7_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.rxvalid4_ext (rxvalid4_ext),
.rxvalid5_ext (rxvalid5_ext),
.rxvalid6_ext (rxvalid6_ext),
.rxvalid7_ext (rxvalid7_ext),
.srst (srst),
.test_in (test_in),
.test_out (test_out),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr),
.tx_cred0 (tx_cred0),
.tx_fifo_empty0 (tx_fifo_empty0),
.tx_fifo_full0 (open_tx_fifo_full0),
.tx_fifo_rdptr0 (open_tx_fifo_rdptr0),
.tx_fifo_wrptr0 (open_tx_fifo_wrptr0),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.tx_out4 (tx_out4),
.tx_out5 (tx_out5),
.tx_out6 (tx_out6),
.tx_out7 (tx_out7),
.tx_st_data0 (tx_st_data0),
.tx_st_empty0 (tx_st_empty0),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (tx_st_err0),
.tx_st_ready0 (tx_st_ready0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_valid0 (tx_st_valid0),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txcompl4_ext (txcompl4_ext),
.txcompl5_ext (txcompl5_ext),
.txcompl6_ext (txcompl6_ext),
.txcompl7_ext (txcompl7_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdata4_ext (txdata4_ext),
.txdata5_ext (txdata5_ext),
.txdata6_ext (txdata6_ext),
.txdata7_ext (txdata7_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdatak4_ext (txdatak4_ext),
.txdatak5_ext (txdatak5_ext),
.txdatak6_ext (txdatak6_ext),
.txdatak7_ext (txdatak7_ext),
.txdetectrx_ext (txdetectrx_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext),
.txelecidle4_ext (txelecidle4_ext),
.txelecidle5_ext (txelecidle5_ext),
.txelecidle6_ext (txelecidle6_ext),
.txelecidle7_ext (txelecidle7_ext)
);
altpcie_reconfig_4sgx reconfig
(
.busy (busy_altgxb_reconfig),
.data_valid (data_valid),
.logical_channel_address (3'b000),
.offset_cancellation_reset (offset_cancellation_reset),
.read (1'b0),
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb),
.reconfig_togxb (reconfig_togxb),
.rx_eqctrl (4'b0000),
.rx_eqctrl_out (rx_eqctrl_out),
.rx_eqdcgain (3'b000),
.rx_eqdcgain_out (rx_eqdcgain_out),
.tx_preemp_0t (5'b00000),
.tx_preemp_0t_out (tx_preemp_0t_out),
.tx_preemp_1t (5'b00000),
.tx_preemp_1t_out (tx_preemp_1t_out),
.tx_preemp_2t (5'b00000),
.tx_preemp_2t_out (tx_preemp_2t_out),
.tx_vodctrl (3'b000),
.tx_vodctrl_out (tx_vodctrl_out),
.write_all (1'b0)
);
pcie_4243_hip_s4gx_gen2_x8_128_rs_hip rs_hip
(
.app_rstn (srstn),
.crst (crst),
.dlup_exit (dlup_exit),
.hotrst_exit (hotrst_exit_altr),
.l2_exit (l2_exit),
.ltssm (ltssm),
.npor (npor_serdes_pll_locked),
.pld_clk (pld_clk),
.srst (srst),
.test_sim (test_in[0])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_1_V
`define SKY130_FD_SC_HD__SDFRTN_1_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog wrapper for sdfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__AND4_PP_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Odintsov Oleg
//
// Create Date: 11:15:41 02/24/2012
// Design Name:
// Module Name: ag_ram
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Enable the following define to use synchronous memory instead of
// asynchronous (which has been used in real Agats).
// The use of the synchronous memory will improve hardware design on FPGA
`define AG_RAM_SYNCHRONOUS
`ifdef AG_RAM_SYNCHRONOUS
module RAM16Kx1(input CLK1, input[13:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[13:0] AB2, input CS2, output DO2);
parameter
D_00 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_01 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_02 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_03 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_04 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_05 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_06 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_07 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_08 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_09 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0A = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0B = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0C = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0D = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0E = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0F = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
// Address 4096 to 8191
D_10 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_11 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_12 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_13 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_14 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_15 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_16 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_17 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_18 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_19 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1A = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1B = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1C = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1D = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1E = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1F = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
// Address 8192 to 12287
D_20 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_21 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_22 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_23 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_24 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_25 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_26 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_27 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_28 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_29 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2A = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2B = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2C = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2D = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2E = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2F = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
// Address 12288 to 16383
D_30 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_31 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_32 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_33 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_34 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_35 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_36 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_37 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_38 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_39 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3A = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3B = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3C = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3D = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3E = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3F = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;
wire DO1x, DO2x;
assign DO1 = CS1? DO1x: 1'bZ;
assign DO2 = CS2? DO2x: 1'bZ;
// RAMB16_S1_S1: 16k x 1 Dual-Port RAM
// Spartan-3E
// Xilinx HDL Language Template, version 13.3
RAMB16_S1_S1 #(
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
.INIT_B(1'b0), // Value of output RAM registers on Port B at startup
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
.SRVAL_B(1'b0), // Port B output value upon SSR assertion
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
// The following INIT_xx declarations specify the initial contents of the RAM
// Address 0 to 4095
.INIT_00(D_00), .INIT_01(D_01), .INIT_02(D_02), .INIT_03(D_03),
.INIT_04(D_04), .INIT_05(D_05), .INIT_06(D_06), .INIT_07(D_07),
.INIT_08(D_08), .INIT_09(D_09), .INIT_0A(D_0A), .INIT_0B(D_0B),
.INIT_0C(D_0C), .INIT_0D(D_0D), .INIT_0E(D_0E), .INIT_0F(D_0F),
// Address 4096 to 8191
.INIT_10(D_10), .INIT_11(D_11), .INIT_12(D_12), .INIT_13(D_13),
.INIT_14(D_14), .INIT_15(D_15), .INIT_16(D_16), .INIT_17(D_17),
.INIT_18(D_18), .INIT_19(D_19), .INIT_1A(D_1A), .INIT_1B(D_1B),
.INIT_1C(D_1C), .INIT_1D(D_1D), .INIT_1E(D_1E), .INIT_1F(D_1F),
// Address 8192 to 12287
.INIT_20(D_20), .INIT_21(D_21), .INIT_22(D_22), .INIT_23(D_23),
.INIT_24(D_24), .INIT_25(D_25), .INIT_26(D_26), .INIT_27(D_27),
.INIT_28(D_28), .INIT_29(D_29), .INIT_2A(D_2A), .INIT_2B(D_2B),
.INIT_2C(D_2C), .INIT_2D(D_2D), .INIT_2E(D_2E), .INIT_2F(D_2F),
// Address 12288 to 16383
.INIT_30(D_30), .INIT_31(D_31), .INIT_32(D_32), .INIT_33(D_33),
.INIT_34(D_34), .INIT_35(D_35), .INIT_36(D_36), .INIT_37(D_37),
.INIT_38(D_38), .INIT_39(D_39), .INIT_3A(D_3A), .INIT_3B(D_3B),
.INIT_3C(D_3C), .INIT_3D(D_3D), .INIT_3E(D_3E), .INIT_3F(D_3F)
) RAMB16_S1_S1_inst (
.DOA(DO1x), // Port A 1-bit Data Output
.DOB(DO2x), // Port B 1-bit Data Output
.ADDRA(AB1), // Port A 14-bit Address Input
.ADDRB(AB2), // Port B 14-bit Address Input
.CLKA(CLK1), // Port A Clock
.CLKB(CLK2), // Port B Clock
.DIA(DI1), // Port A 1-bit Data Input
.DIB(1'bZ), // Port B 1-bit Data Input
.ENA(CS1), // Port A RAM Enable Input
.ENB(CS2), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(~READ), // Port A Write Enable Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
`else
module RAM1Kx1(input CLK1, input[9:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[9:0] AB2, input CS2, output DO2);
parameter FILL = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;
reg mem[0:'h3FF];
integer i;
initial
for (i = 0; i < 'h400; i = i + 1)
mem[i] = (FILL&(256'b01<<(i&'hFF)))?1'b1:1'b0;
assign DO1 = (CS1 && READ)? mem[AB1]: 1'bZ;
assign DO2 = CS2? mem[AB2]: 1'bZ;
always @(posedge CLK1) if (CS1 && !READ) mem[AB1] <= DI1;
endmodule
module RAM16Kx1(input CLK1, input[13:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[13:0] AB2, input CS2, output DO2);
wire[3:0] SEL1 = AB1[13:10];
wire[3:0] SEL2 = AB2[13:10];
RAM1Kx1 ram0(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h0), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h0), DO2);
RAM1Kx1 ram1(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h1), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h1), DO2);
RAM1Kx1 ram2(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h2), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h2), DO2);
RAM1Kx1 ram3(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h3), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h3), DO2);
RAM1Kx1 ram4(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h4), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h4), DO2);
RAM1Kx1 ram5(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h5), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h5), DO2);
RAM1Kx1 ram6(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h6), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h6), DO2);
RAM1Kx1 ram7(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h7), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h7), DO2);
RAM1Kx1 ram8(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h8), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h8), DO2);
RAM1Kx1 ram9(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h9), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h9), DO2);
RAM1Kx1 ramA(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hA), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hA), DO2);
RAM1Kx1 ramB(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hB), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hB), DO2);
RAM1Kx1 ramC(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hC), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hC), DO2);
RAM1Kx1 ramD(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hD), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hD), DO2);
RAM1Kx1 ramE(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hE), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hE), DO2);
RAM1Kx1 ramF(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hF), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hF), DO2);
endmodule
`endif // synchronous
/*
Data bus for video controller:
A0=0, DO2: A0=1, DO2:
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Data bus for processor:
A0=0, DO1/DI1: A0=1, DO1/DI1:
07 06 05 04 03 02 01 00 07 06 05 04 03 02 01 00
*/
module RAM32Kx8x16(input CLK1, input[14:0] AB1, input CS1,
input READ, output[7:0] DO1, input[7:0] DI1,
input CLK2, input[13:0] AB2, input CS2, output[15:0] DO2);
wire[1:0] CSM = {(~AB1[0]) & CS1, AB1[0] & CS1}; // CS for modules
wire[13:0] AB1x = AB1[14:1];
`include "juke-box.v"
/* RAM16Kx1 ram0(CLK1, AB1x, CSM[0], READ, DO1[0], DI1[0], CLK2, AB2, CS2, DO2[0]);
RAM16Kx1 ram1(CLK1, AB1x, CSM[0], READ, DO1[1], DI1[1], CLK2, AB2, CS2, DO2[1]);
RAM16Kx1 ram2(CLK1, AB1x, CSM[0], READ, DO1[2], DI1[2], CLK2, AB2, CS2, DO2[2]);
RAM16Kx1 ram3(CLK1, AB1x, CSM[0], READ, DO1[3], DI1[3], CLK2, AB2, CS2, DO2[3]);
RAM16Kx1 ram4(CLK1, AB1x, CSM[0], READ, DO1[4], DI1[4], CLK2, AB2, CS2, DO2[4]);
RAM16Kx1 ram5(CLK1, AB1x, CSM[0], READ, DO1[5], DI1[5], CLK2, AB2, CS2, DO2[5]);
RAM16Kx1 ram6(CLK1, AB1x, CSM[0], READ, DO1[6], DI1[6], CLK2, AB2, CS2, DO2[6]);
RAM16Kx1 ram7(CLK1, AB1x, CSM[0], READ, DO1[7], DI1[7], CLK2, AB2, CS2, DO2[7]);
RAM16Kx1 ram8(CLK1, AB1x, CSM[1], READ, DO1[0], DI1[0], CLK2, AB2, CS2, DO2[8]);
RAM16Kx1 ram9(CLK1, AB1x, CSM[1], READ, DO1[1], DI1[1], CLK2, AB2, CS2, DO2[9]);
RAM16Kx1 ramA(CLK1, AB1x, CSM[1], READ, DO1[2], DI1[2], CLK2, AB2, CS2, DO2[10]);
RAM16Kx1 ramB(CLK1, AB1x, CSM[1], READ, DO1[3], DI1[3], CLK2, AB2, CS2, DO2[11]);
RAM16Kx1 ramC(CLK1, AB1x, CSM[1], READ, DO1[4], DI1[4], CLK2, AB2, CS2, DO2[12]);
RAM16Kx1 ramD(CLK1, AB1x, CSM[1], READ, DO1[5], DI1[5], CLK2, AB2, CS2, DO2[13]);
RAM16Kx1 ramE(CLK1, AB1x, CSM[1], READ, DO1[6], DI1[6], CLK2, AB2, CS2, DO2[14]);
RAM16Kx1 ramF(CLK1, AB1x, CSM[1], READ, DO1[7], DI1[7], CLK2, AB2, CS2, DO2[15]);*/
endmodule
|
/* verilator lint_off UNUSED */
/* verilator lint_off CASEX */
/* verilator lint_off COMBDLY */
//
// address calculation Unit
//
module acu (clk, rstn, add_src , to_regf , from_regf, from_dec, db67 , seg_src );
input clk, rstn;
input [63:0] from_regf; // base&index register selected for address calculation
input [128+1+1+73+8-1:0] from_dec;
input db67;
output reg [2:0] seg_src;
output reg [31:0] add_src; // adress to read from
output [7:0] to_regf; // base&index select register for address calculation
wire [7:0] indrm; // Decoder intermediate input
wire [72:0] indic; // Decoder intermediate input
wire [127:0] in128; // Decoder intermediate input
wire sib_dec; // Decoder intermediate input
wire mod_dec; // Decoder intermediate input
wire [31:0] reg_base;
wire [31:0] reg_index;
wire [31:0] shf_index;
wire [7:0] modrm,modrmr;
wire [15:0] disp16;
wire [7:0] to_regf32,to_regf16;
reg ov;
// Split from_deco bus
//
assign {in128,mod_dec,sib_dec,indic,indrm}=from_dec;
// Select Base and index Register
//
assign modrm = in128[15:8];
assign to_regf = db67 ? to_regf32 : to_regf16;
assign to_regf32[3:0] = (&indrm[1:0]) ? {1'b0,in128[18:16]} : {1'b0,in128[10:8]};
assign to_regf32[7:4] = (&indrm[1:0]) ? {1'b0,in128[21:19]} : {4'b1111 };
assign disp16 = ({modrm[7:6],modrm[2:0]}==5'b00110) ? in128[31:16] :
({modrm[7:6]}==2'b10) ? in128[31:16] :
({modrm[7:6]}==2'b01) ? {{8{in128[23]}},in128[23:16]} :
16'b0;
assign to_regf16[3:0] = (modrm[2:1]==2'b11) ? {4'b1111} : {1'b0,2'b11,modrm[0]} ;
assign to_regf16[7:4] = ( modrm[2:1] == 2'b10 ) ? {4'b1111} :
({modrm[7:6],modrm[2:0]} == 5'b00110) ? {4'b1111} :
(modrm[2]==1'b0) ? {1'b0, modrm[1], ~modrm[1],1'b1} :
{1'b0, ~modrm[0], modrm[0],1'b1} ;
assign reg_base = from_regf[31: 0];
assign reg_index = ((in128[21:19]==4)&&(db67==1)) ? 0 : from_regf[63:32]; // ESP is illegal index
assign shf_index = (in128[23:22]==0) ? reg_index :
(in128[23:22]==1) ? {reg_index[30:0],1'b0} :
(in128[23:22]==2) ? {reg_index[29:0],2'b0} :
{reg_index[28:0],3'b0} ;
// Put in FFlops the address of memory location to be used for next operation
//
//always @(reg_base or reg_index or shf_index or in128 or mod_dec or indrm or disp16 or to_regf32 or to_regf or db67)
always @(posedge clk)
if (db67)
begin
seg_src <=0;
if (mod_dec)
casex(indrm[4:0])
5'b00110 : begin add_src <= in128[47:16] ; end // 32bit only displc
5'b10010 : begin {ov,add_src} <= reg_base + {{24{in128[23]}},in128[23:16]}; end // no sib - 8bit displc
5'b10011 : begin {ov,add_src} <= shf_index+ reg_base + {{24{in128[31]}},in128[31:24]}; end // sib - 8bit displc
5'b01010 : begin {ov,add_src} <= reg_base + in128[47:16] ; end // no sib - 32bit displc
5'b01011 : begin {ov,add_src} <= shf_index+ reg_base + in128[55:24] ; end // sib - 32bit displc
5'b00011 : if ((indrm[7]==1)&&(to_regf32[3:0]==4'b0101))
begin {ov,add_src} <= shf_index+ in128[55:24] ; end // sib - 32bit displc only
else begin {ov,add_src} <= shf_index+ reg_base ; end // sib - no displc displc
5'b00010 : begin add_src <= reg_base ; end // no sib - no displc - only base
default : begin add_src <= reg_base ; end
endcase
else begin add_src <=0; ov <=0; end
end
else
begin if ((mod_dec&indrm[6]) == 1) seg_src <= 3'b011;
else if ( mod_dec == 0 ) seg_src <= 3'b011;
else if (to_regf[7:4] == 4'b0101) seg_src <= 3'b010;
else if (to_regf[7:4] == 4'b0100) seg_src <= 3'b010;
else seg_src <= 3'b011;
ov <=0;
if (mod_dec)
begin
add_src[15:0] <= reg_base[15:0] + reg_index[15:0] + disp16;
add_src[31:16] <= 16'b0 ;
end
else add_src <=0;
end
endmodule
|
//
// Paul Gao 01/2021
//
//
module bsg_link_ddr_test_node
#(parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,parameter is_downstream_node_p = 0
,parameter lg_fifo_depth_lp = 3
,parameter width_lp = num_channels_p * channel_width_p
)
(// Node side
input node_clk_i
,input node_reset_i
,input node_en_i
,output logic error_o
,output [31:0] sent_o
,output [31:0] received_o
// Link side
,input clk_i
,input reset_i
,input v_i
,input [width_lp-1:0] data_i
,output ready_o
,output v_o
,output [width_lp-1:0] data_o
,input yumi_i
);
// Async fifo signals
logic node_async_fifo_valid_li, node_async_fifo_ready_lo;
logic node_async_fifo_valid_lo, node_async_fifo_yumi_li;
logic [width_lp-1:0] node_async_fifo_data_li;
logic [width_lp-1:0] node_async_fifo_data_lo;
if (is_downstream_node_p == 0)
begin: upstream
// Generate data packets
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p (num_channels_p)
) gen_out
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.o (node_async_fifo_data_li)
);
// Send when node is enabled
assign node_async_fifo_valid_li = node_en_i;
// Count sent packets
bsg_counter_clear_up
#(.max_val_p (1<<32-1)
,.init_val_p(0)
) sent_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.count_o(sent_o)
);
end
else
begin: downstream
// Generate checking packets
logic [width_lp-1:0] data_check;
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p (num_channels_p)
) gen_in
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (node_async_fifo_yumi_li)
,.o (data_check)
);
// Always ready
assign node_async_fifo_yumi_li = node_async_fifo_valid_lo;
// Count received packets
bsg_counter_clear_up
#(.max_val_p (1<<32-1)
,.init_val_p(0)
) received_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (node_async_fifo_yumi_li)
,.count_o(received_o)
);
// Check errors
always_ff @(posedge node_clk_i)
if (node_reset_i)
error_o <= 0;
else
if (node_async_fifo_yumi_li && data_check != node_async_fifo_data_lo)
begin
$error("%m mismatched resp data %x %x",data_check, node_async_fifo_data_lo);
error_o <= 1;
end
end
/********************* Async fifo to link *********************/
// Node side async fifo input
logic node_async_fifo_full_lo;
assign node_async_fifo_ready_lo = ~node_async_fifo_full_lo;
// Link side async fifo input
logic link_async_fifo_full_lo;
assign ready_o = ~link_async_fifo_full_lo;
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) wh_to_mc
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_enq_i (v_i & ready_o)
,.w_data_i (data_i)
,.w_full_o (link_async_fifo_full_lo)
,.r_clk_i (node_clk_i)
,.r_reset_i(node_reset_i)
,.r_deq_i (node_async_fifo_yumi_li)
,.r_data_o (node_async_fifo_data_lo)
,.r_valid_o(node_async_fifo_valid_lo)
);
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) mc_to_wh
(.w_clk_i (node_clk_i)
,.w_reset_i(node_reset_i)
,.w_enq_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.w_data_i (node_async_fifo_data_li)
,.w_full_o (node_async_fifo_full_lo)
,.r_clk_i (clk_i)
,.r_reset_i(reset_i)
,.r_deq_i (yumi_i)
,.r_data_o (data_o)
,.r_valid_o(v_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_ddr_test_node)
|
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