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//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
//
// Filename : mc_chroma_ip_1p.v
// Created On : 2013-11-20 20:08:52
// Last Modified : 2015-01-09 21:12:26
// Revision :
// Author : Yufeng Bai
// Email : [email protected]
// Description :
//-------------------------------------------------------------------
`include "enc_defines.v"
module mc_chroma_ip_1p (
clk,
rstn,
blk_start_i,
fracx_i,
fracy_i,
ref_valid_i,
refuv_p0_i,
refuv_p1_i,
refuv_p2_i,
refuv_p3_i,
fracuv_valid_o,
fracuv_p_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ;
input rstn ;
input blk_start_i ;
input [2 :0] fracx_i ;
input [2 :0] fracy_i ;
input ref_valid_i ;
input [`PIXEL_WIDTH-1:0] refuv_p0_i ;
input [`PIXEL_WIDTH-1:0] refuv_p1_i ;
input [`PIXEL_WIDTH-1:0] refuv_p2_i ;
input [`PIXEL_WIDTH-1:0] refuv_p3_i ;
output fracuv_valid_o;
output [`PIXEL_WIDTH-1:0] fracuv_p_o ;
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [2*`PIXEL_WIDTH-1:0] ver_p0 ;
reg [2*`PIXEL_WIDTH-1:0] ver_p1 ;
reg [2*`PIXEL_WIDTH-1:0] ver_p2 ;
reg [2*`PIXEL_WIDTH-1:0] ver_p3 ;
reg [2 :0] row_cnt ;
reg fracuv_valid ;
reg [2 :0] fracy_pipeline;
reg [2 :0] fracx_pipeline;
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire [2*`PIXEL_WIDTH-1:0] hor_p_out ;
wire [`PIXEL_WIDTH-1:0] ver_p_out ;
// ********************************************
//
// Combinational Logic
//
// ********************************************
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
ver_p0 <= 'd0 ;
ver_p1 <= 'd0 ;
ver_p2 <= 'd0 ;
ver_p3 <= 'd0 ;
end
else if (ref_valid_i) begin
ver_p0 <= hor_p_out ;
ver_p1 <= ver_p0 ;
ver_p2 <= ver_p1 ;
ver_p3 <= ver_p2 ;
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
fracy_pipeline <= 'd0;
fracx_pipeline <= 'd0;
end
else begin
fracy_pipeline <= fracy_i;
fracx_pipeline <= fracx_i;
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
row_cnt <= 'd0;
end
else if (blk_start_i)begin
row_cnt <= 'd0;
end
else if (ref_valid_i) begin
//if(fracy_i == 'd0 || row_cnt == 'd7)
if(fracy_pipeline == 'd0 || row_cnt == 'd7)
row_cnt <= 'd1;
else
row_cnt <= row_cnt + 'd1;
end
end
/*
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
fracuv_valid_o <= 'd0;
fracuv_p_o <= 'd0;
end
else if (fracy_i == 'd0) begin
fracuv_valid_o <= ref_valid_i;
fracuv_p_o <= hor_p_out;
end
else if (row_cnt[2]) begin // 4 <= row_cnt <= 7
fracuv_valid_o <= 1'b1;
fracuv_p_o <= ver_p_out;
end
else begin
fracuv_valid_o <= 1'b0;
fracuv_p_o <= 'd0;
end
end
*/
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
fracuv_valid <= 'd0;
end
else if (blk_start_i)
fracuv_valid <= 'd0;
else
fracuv_valid <= ref_valid_i;
end
assign fracuv_valid_o = ((fracy_pipeline == 'd0) || (row_cnt[2])) && (fracuv_valid);
assign fracuv_p_o = (fracy_pipeline == 'd0) ? ver_p0[`PIXEL_WIDTH-1:0] : ver_p_out;
/*
p p p p
p
p
p
p
*/
mc_chroma_filter_hor filter_hor(
.frac_x (fracx_i),
.frac_y (fracy_i),
.A (refuv_p0_i),
.B (refuv_p1_i),
.C (refuv_p2_i),
.D (refuv_p3_i),
.out (hor_p_out)
);
mc_chroma_filter_ver filter_ver(
.frac_x (fracx_pipeline),
.frac_y (fracy_pipeline),
.A (ver_p3),
.B (ver_p2),
.C (ver_p1),
.D (ver_p0),
.out (ver_p_out)
);
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: io_mux.v
//
// *Module Description:
// I/O mux for port function selection.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 104 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
//----------------------------------------------------------------------------
module io_mux (
// Function A (typically GPIO)
a_din,
a_dout,
a_dout_en,
// Function B (Timer A, ...)
b_din,
b_dout,
b_dout_en,
// IO Cell
io_din,
io_dout,
io_dout_en,
// Function selection (0=A, 1=B)
sel
);
// PARAMETERs
//============
parameter WIDTH = 8;
// Function A (typically GPIO)
//===============================
output [WIDTH-1:0] a_din;
input [WIDTH-1:0] a_dout;
input [WIDTH-1:0] a_dout_en;
// Function B (Timer A, ...)
//===============================
output [WIDTH-1:0] b_din;
input [WIDTH-1:0] b_dout;
input [WIDTH-1:0] b_dout_en;
// IO Cell
//===============================
input [WIDTH-1:0] io_din;
output [WIDTH-1:0] io_dout;
output [WIDTH-1:0] io_dout_en;
// Function selection (0=A, 1=B)
//===============================
input [WIDTH-1:0] sel;
//=============================================================================
// 1) I/O FUNCTION SELECTION MUX
//=============================================================================
function [WIDTH-1:0] mux (
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input [WIDTH-1:0] SEL
);
integer i;
begin
mux = {WIDTH{1'b0}};
for (i = 0; i < WIDTH; i = i + 1)
mux[i] = sel[i] ? B[i] : A[i];
end
endfunction
assign a_din = mux( io_din, {WIDTH{1'b0}}, sel);
assign b_din = mux({WIDTH{1'b0}}, io_din, sel);
assign io_dout = mux( a_dout, b_dout, sel);
assign io_dout_en = mux( a_dout_en, b_dout_en, sel);
endmodule // io_mux
|
// c2cTop.v
// Top Level Code for testing BEE3 C2C connections
// Philip Watts
// Created 7/4/2010
//
//
// Ring UP goes to the FPGA with the higher Letter, e.g., FPGA A->B, B->C, C->D, D->A.
// Ring DN goes to the FPGA with the lower Letter, e.g., FPGA A->D, B->A, C->B, D->C.
//
// Modified 20/4/2010
// Included IFDEFs to enable use as a top level module in its own right or as part of c3dTop
//`include "defines.v"
`ifdef C3D_BUILD // relative to c3dTop build directory
`include "../../interfaces/c2c/src/verilog/ring32b_bidir.v"
`else // relative to c2cTop build directory
`include "ring32b_bidir.v"
`include "../../build/verilog/mkGetOutput.v"
`include "./bluespec/FIFO1.v"
`include "./bluespec/FIFOL1.v"
`include "../../build/synth/coregen/cs_icon.v"
`include "../../build/synth/coregen/cs_ila.v"
`include "../../build/synth/coregen/cs_vio.v"
`endif
`timescale 1ns / 1ps
module c2cTop (
input [31:00] C2C_U_IN,
input [31:00] C2C_D_IN,
output [31:00] C2C_U_OUT,
output [31:00] C2C_D_OUT,
input C2C_U_LOCK_IN,
output C2C_U_LOCK_OUT,
input C2C_U_RDY_IN,
output C2C_U_RDY_OUT,
input C2C_D_LOCK_IN,
output C2C_D_LOCK_OUT,
input C2C_D_RDY_IN,
output C2C_D_RDY_OUT,
`ifdef C3D_BUILD
// Signals for use as submodule to c3dTop
input CLK,
input MCLK,
input MCLK180,
input PLL_LOCK,
input [63:00] C2C_U_TX_DATA,
output [63:00] C2C_U_RX_DATA,
input [63:00] C2C_D_TX_DATA,
output [63:00] C2C_D_RX_DATA
`else
// Signals for use as stand-alone top module
input CLK100M_N,
input CLK100M_P
`endif
);
//////////////////////////SIGNAL DEFINITIONS/////////////////////////////
wire ctrlLock;
wire [31:0] c2c1_status;
wire [31:0] c2c2_status;
wire c2c1_reset;
wire c2c2_reset;
reg pll_lock1, pll_lock2, pll_lock3;
`ifndef C3D_BUILD
// Clocks
wire CLK, MCLK, MCLK180;
wire clk100;
wire PLLBfb;
wire PLL_LOCK;
// Data
wire [63:0] C2C_U_TX_DATA;
wire [63:0] C2C_U_RX_DATA;
wire [63:0] C2C_D_TX_DATA;
wire [63:0] C2C_D_RX_DATA;
// Chipscope Signals
wire [35:0] CONTROL0;
wire [35:0] CONTROL1;
wire [35:0] CONTROL2;
wire [35:0] CONTROL3;
wire [35:0] CONTROL4;
wire [35:0] CONTROL5;
wire [255:0] TRIG0;
wire [255:0] TRIG1;
wire [255:0] TRIG2;
wire [255:0] TRIG3;
wire [31:0] VIO0;
`endif
////////////////////////////CLOCKS//////////////////////////////////////
`ifndef C3D_BUILD // Only required if using as top level module
// Generate 100 MHz clock
IBUFGDS #(
.DIFF_TERM("TRUE"), // Differential Termination (Virtex-4/5, Spartan-3E/3A)
.IOSTANDARD("LVDS_25") // Specifies the I/O standard for this buffer
) CLK100buf(
.O(clk100), // Clock buffer output
.I(CLK100M_P), // Diff_p clock buffer input
.IB(CLK100M_N) // Diff_n clock buffer input
);
// This PLL generates the main system clock, cx4 and C2C clocks from the cx4 output clock
// This has been modified to use the 100M clock input so that it can be used independently of the
// CX4 module. Outputs are at 150M presently.
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(6), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN_PERIOD(10), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(4), // Division factor for CLKOUT0 (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(2), // Division factor for CLKOUT1 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(16), // Division factor for CLKOUT2 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.375), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(4), // Division factor for CLKOUT3 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(180.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(8), // Division factor for CLKOUT4 (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(4), // Division factor for CLKOUT5 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(180.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
.REF_JITTER(0.100) // Input reference jitter (0.000 to 0.999 UI%)
) clkBPLL (
.CLKFBOUT(PLLBfb), // General output feedback signal
.CLKOUT0(MCLK), // 156.25 MHz system clock before buffering
.CLKOUT1(), // 312.5 MHz clock for GTP TXUSRCLK
.CLKOUT2(), //
.CLKOUT3(MCLK180), // 156.25 MHz system clock before buffering, 180deg
.CLKOUT4(), //
.CLKOUT5(), //
.LOCKED(PLL_LOCK), // Active high PLL lock signal
.CLKFBIN(PLLBfb), // Clock feedback input
.CLKIN(clk100), // 312.5 MHz clock input from GTP
.RST(1'b0)
);
// Buffer main system clock (CLK)
BUFG bufM (.O(CLK), .I(MCLK));
`endif
////////////////////////END OF CLOCKS///////////////////////////////
//////////////////////////RESETS////////////////////////////////////
always @ (posedge CLK) begin
pll_lock3 <= pll_lock2;
pll_lock2 <= pll_lock1;
pll_lock1 <= PLL_LOCK;
end
`ifdef C3D_BUILD
assign c2c1_reset = !(pll_lock3 & C2C_U_RDY_IN);
assign c2c2_reset = !(pll_lock3 & C2C_D_RDY_IN);
`else
assign c2c1_reset = (!(pll_lock3 & C2C_U_RDY_IN)) | VIO0[0];
assign c2c2_reset = (!(pll_lock3 & C2C_D_RDY_IN)) | VIO0[0];
`endif
////////////////////////C2C Modules///////////////////////////////
//Instantiate C2C wrapper
ring32b_bidir inst_c2c_up(
.CLK (CLK),
.swClk0 (MCLK),
.swClk180 (MCLK180),
.Reset (c2c1_reset),
.din (C2C_U_TX_DATA),
.dout (C2C_U_RX_DATA),
.RING_OUT (C2C_U_OUT),
.RING_IN (C2C_U_IN),
.lock_in (C2C_U_LOCK_IN),
.lock_out (C2C_U_LOCK_OUT),
.partner_ready (C2C_U_RDY_IN),
.test_sigs (c2c1_status));
ring32b_bidir inst_c2c_dn(
.CLK (CLK),
.swClk0 (MCLK),
.swClk180 (MCLK180),
.Reset (c2c2_reset),
.din (C2C_D_TX_DATA),
.dout (C2C_D_RX_DATA),
.RING_OUT (C2C_D_OUT),
.RING_IN (C2C_D_IN),
.lock_in (C2C_D_LOCK_IN),
.lock_out (C2C_D_LOCK_OUT),
.partner_ready (C2C_D_RDY_IN),
.test_sigs (c2c2_status));
assign C2C_U_RDY_OUT = PLL_LOCK;
assign C2C_D_RDY_OUT = PLL_LOCK;
//instantiate an idelayctrl for alignment of ring interconnect.
IDELAYCTRL idelayctrl0 (
.RDY (),
.REFCLK (CLK),
.RST (~pll_lock3)
) /* synthesis syn_noprune =1 */ ;
////////////////////////End of C2C Modules/////////////////////////
`ifndef C3D_BUILD
////////////////////////Simple Traffic Gen//////////////////////////
// Bluespec Interface traffic generator (only required for c2c test)
mkGetOutput trafficgen1 (
.CLK(CLK),
.RST_N(pll_lock3),
.EN_tx_sink_get(1'b1),
.tx_sink_get(C2C_U_TX_DATA),
.RDY_tx_sink_get());
assign C2C_D_TX_DATA = C2C_U_TX_DATA;
///////////////////////Chipscope Debug//////////////////////////////
cs_icon inst_icon (
.CONTROL0(CONTROL0),
.CONTROL1(CONTROL1),
.CONTROL2(CONTROL2),
.CONTROL3(CONTROL3),
.CONTROL4(CONTROL4),
.CONTROL5(CONTROL5)) /* synthesis syn_noprune =1 */ ;
cs_vio inst_vio (
.CONTROL(CONTROL0),
.ASYNC_OUT(VIO0),
.ASYNC_IN(32'b0)) /* synthesis syn_noprune =1 */ ;
cs_ila inst_ila_cx4_1 (
.CONTROL(CONTROL1),
.CLK(CLK),
.TRIG0(TRIG0)) /* synthesis syn_noprune =1 */ ;
cs_ila inst_ila_cx4_2 (
.CONTROL(CONTROL2),
.CLK(CLK),
.TRIG0(TRIG1)) /* synthesis syn_noprune =1 */ ;
cs_ila inst_ila_c2c1 (
.CONTROL(CONTROL3),
.CLK(CLK),
.TRIG0(TRIG2)) /* synthesis syn_noprune =1 */ ;
cs_ila inst_ila_c2c2 (
.CONTROL(CONTROL4),
.CLK(CLK),
.TRIG0(TRIG3)) /* synthesis syn_noprune =1 */ ;
cs_ila inst_ila_spare (
.CONTROL(CONTROL5),
.CLK(CLK),
.TRIG0(TRIG4)) /* synthesis syn_noprune =1 */ ;
assign TRIG0 = {256'h0000000000000000000000000000000000000000000000000000000000000000};
assign TRIG1 = {256'h0000000000000000000000000000000000000000000000000000000000000000};
assign TRIG2 = {c2c1_status,c2c1_reset,C2C_U_RDY_IN,PLL_LOCK,C2C_U_LOCK_IN, C2C_U_LOCK_OUT, C2C_U_RX_DATA, C2C_U_TX_DATA};
assign TRIG3 = {c2c2_status,c2c2_reset,C2C_D_RDY_IN,PLL_LOCK,C2C_D_LOCK_IN, C2C_D_LOCK_OUT, C2C_D_RX_DATA, C2C_D_TX_DATA};
assign TRIG4 = {256'h0000000000000000000000000000000000000000000000000000000000000000};
//////////////////////End of Chipscope Debug/////////////////////////
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_PP_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire or0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_PP_V
|
module ShiftReg16(
input clk,
input shiftBypass,
input signed [15:0] din,
input [4:0] tap,
(* shreg_extract = "no" *) output reg signed [15:0] dout = 16'd0
);
parameter SRL_SIZE = 32;
//(* shreg_extract = "yes" *) reg [15:0] dsh_in [0:SRL_SIZE-1];
(* shreg_extract = "yes" *) reg [15:0] dsh_in [0:SRL_SIZE-3];
//reg [12:0] dsh_in [0:SRL_SIZE-1];
(* shreg_extract = "no" *) reg [4:0] tap_b = 5'd0;
(* shreg_extract = "no" *) reg shiftBypass_b = 1'b1;
//reg [12:0] dsh_out;
integer n;
`ifdef XILINX_ISIM
integer i;
//initial for (i=0; i < SRL_SIZE; i=i+1) dsh_in[i]=16'd0; // for simulation ONLY
initial for (i=0; i < (SRL_SIZE-2); i=i+1) dsh_in[i]=16'd0; // for simulation ONLY
`endif
always @(posedge clk) begin
shiftBypass_b <= shiftBypass;
//tap_b <= tap - 5'd2;
tap_b <= (tap < 5'd2) ? 5'd0 : (tap - 5'd2);
dsh_in[0] <= din;
//for (i=1; i < SRL_SIZE; i=i+1) dsh_in[i] <= dsh_in[i-1];
//for (n=SRL_SIZE-1; n > 0; n=n-1) dsh_in[n] <= dsh_in[n-1];
for (n=SRL_SIZE-3; n > 0; n=n-1) dsh_in[n] <= dsh_in[n-1];
//dsh_in[1:SRL_SIZE-1] <= dsh_in[0:SRL_SIZE-2];
dout <= (shiftBypass_b) ? din : dsh_in[tap_b];
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam NO = 10; // number of access events
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
localparam WS = 15; // $bits(struct_bg)
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to x)
if (cnt[30:2]==0) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==1) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==2) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==3) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==4) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==5) struct_bg <= {WS{1'bx}};
end else if (cnt[1:0]==2'd1) begin
// write value to structure
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_bg <= {WS{1'b1}};
else if (cnt[30:2]==2) struct_bg.e0 <= {WS{1'b1}};
else if (cnt[30:2]==3) struct_bg.e1 <= {WS{1'b1}};
else if (cnt[30:2]==4) struct_bg.e2 <= {WS{1'b1}};
else if (cnt[30:2]==5) struct_bg.e3 <= {WS{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check structure value
if (cnt[30:2]==0) begin if (struct_bg !== 15'bxxxxxxxxxxxxxxx) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1xxxxxxxxxxxxxx) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_bg !== 15'bx11xxxxxxxxxxxx) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_bg !== 15'bxxx1111xxxxxxxx) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_bg !== 15'bxxxxxxx11111111) begin $display("%b", struct_bg); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from structure (not a very good test for now)
if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'bx}}) $stop(); end
else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to x)
if (cnt[30:2]==0) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==1) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==2) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==3) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==4) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==5) struct_lt <= {WS{1'bx}};
end else if (cnt[1:0]==2'd1) begin
// write value to structure
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_lt <= {WS{1'b1}};
else if (cnt[30:2]==2) struct_lt.e0 <= {WS{1'b1}};
else if (cnt[30:2]==3) struct_lt.e1 <= {WS{1'b1}};
else if (cnt[30:2]==4) struct_lt.e2 <= {WS{1'b1}};
else if (cnt[30:2]==5) struct_lt.e3 <= {WS{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check structure value
if (cnt[30:2]==0) begin if (struct_lt !== 15'bxxxxxxxxxxxxxxx) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1xxxxxxxxxxxxxx) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_lt !== 15'bx11xxxxxxxxxxxx) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_lt !== 15'bxxx1111xxxxxxxx) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_lt !== 15'bxxxxxxx11111111) begin $display("%b", struct_lt); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from structure (not a very good test for now)
if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'bx}}) $stop(); end
else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart_transceiver(
input sys_rst,
input sys_clk,
input uart_rxd,
output reg uart_txd,
input [15:0] divisor,
output reg [7:0] rx_data,
output reg rx_done,
input [7:0] tx_data,
input tx_wr,
output reg tx_done
);
//-----------------------------------------------------------------
// enable16 generator
//-----------------------------------------------------------------
reg [15:0] enable16_counter;
wire enable16;
assign enable16 = (enable16_counter == 16'd0);
always @(posedge sys_clk) begin
if(sys_rst)
enable16_counter <= divisor - 16'b1;
else begin
enable16_counter <= enable16_counter - 16'd1;
if(enable16)
enable16_counter <= divisor - 16'b1;
end
end
//-----------------------------------------------------------------
// Synchronize uart_rxd
//-----------------------------------------------------------------
reg uart_rxd1;
reg uart_rxd2;
always @(posedge sys_clk) begin
uart_rxd1 <= uart_rxd;
uart_rxd2 <= uart_rxd1;
end
//-----------------------------------------------------------------
// UART RX Logic
//-----------------------------------------------------------------
reg rx_busy;
reg [3:0] rx_count16;
reg [3:0] rx_bitcount;
reg [7:0] rxd_reg;
always @(posedge sys_clk) begin
if(sys_rst) begin
rx_done <= 1'b0;
rx_busy <= 1'b0;
rx_count16 <= 4'd0;
rx_bitcount <= 4'd0;
end else begin
rx_done <= 1'b0;
if(enable16) begin
if(~rx_busy) begin // look for start bit
if(~uart_rxd2) begin // start bit found
rx_busy <= 1'b1;
rx_count16 <= 4'd7;
rx_bitcount <= 4'd0;
end
end else begin
rx_count16 <= rx_count16 + 4'd1;
if(rx_count16 == 4'd0) begin // sample
rx_bitcount <= rx_bitcount + 4'd1;
if(rx_bitcount == 4'd0) begin // verify startbit
if(uart_rxd2)
rx_busy <= 1'b0;
end else if(rx_bitcount == 4'd9) begin
rx_busy <= 1'b0;
if(uart_rxd2) begin // stop bit ok
rx_data <= rxd_reg;
rx_done <= 1'b1;
end // ignore RX error
end else
rxd_reg <= {uart_rxd2, rxd_reg[7:1]};
end
end
end
end
end
//-----------------------------------------------------------------
// UART TX Logic
//-----------------------------------------------------------------
reg tx_busy;
reg [3:0] tx_bitcount;
reg [3:0] tx_count16;
reg [7:0] txd_reg;
always @(posedge sys_clk) begin
if(sys_rst) begin
tx_done <= 1'b0;
tx_busy <= 1'b0;
uart_txd <= 1'b1;
end else begin
tx_done <= 1'b0;
if(tx_wr) begin
txd_reg <= tx_data;
tx_bitcount <= 4'd0;
tx_count16 <= 4'd1;
tx_busy <= 1'b1;
uart_txd <= 1'b0;
`ifdef SIMULATION
$display("UART: %c", tx_data);
`endif
end else if(enable16 && tx_busy) begin
tx_count16 <= tx_count16 + 4'd1;
if(tx_count16 == 4'd0) begin
tx_bitcount <= tx_bitcount + 4'd1;
if(tx_bitcount == 4'd8) begin
uart_txd <= 1'b1;
end else if(tx_bitcount == 4'd9) begin
uart_txd <= 1'b1;
tx_busy <= 1'b0;
tx_done <= 1'b1;
end else begin
uart_txd <= txd_reg[0];
txd_reg <= {1'b0, txd_reg[7:1]};
end
end
end
end
end
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-----------------------------------------------------------------------------------------------------------------------------
// Filename : cabac_binari_sao_offset.v
// Author : chewein
// Created : 2014-9-11
// Description : binarization an cu , cu size is 8x8 , 16x16 , 32x32 64x64
//-----------------------------------------------------------------------------------------------------------------------------
`include"enc_defines.v"
module cabac_binari_sao_offset(
sao_data_i ,
sao_compidx_i ,
sao_merge_i ,
cu_binary_sao_0_o ,
cu_binary_sao_1_o ,
cu_binary_sao_2_o ,
cu_binary_sao_3_o ,
cu_binary_sao_4_o ,
cu_binary_sao_5_o ,
cu_binary_sao_6_o ,
cu_binary_sao_7_o
);
// -----------------------------------------------------------------------------------------------------------------------------
//
// INPUT and OUTPUT DECLARATION
//
// -----------------------------------------------------------------------------------------------------------------------------
input [19:0] sao_data_i ;
input [ 1:0] sao_compidx_i ;
input sao_merge_i ;
output [10:0] cu_binary_sao_0_o ;
output [10:0] cu_binary_sao_1_o ;
output [10:0] cu_binary_sao_2_o ;
output [10:0] cu_binary_sao_3_o ;
output [10:0] cu_binary_sao_4_o ;
output [10:0] cu_binary_sao_5_o ;
output [10:0] cu_binary_sao_6_o ;
output [10:0] cu_binary_sao_7_o ;
// -----------------------------------------------------------------------------------------------------------------------------
//
// wire and reg signals declaration
//
// -----------------------------------------------------------------------------------------------------------------------------
reg [10:0] cu_binary_sao_0_r ;
reg [10:0] cu_binary_sao_1_r ;
reg [10:0] cu_binary_sao_2_r ;
reg [10:0] cu_binary_sao_3_r ;
reg [10:0] cu_binary_sao_4_r ;
reg [10:0] cu_binary_sao_5_r ;
reg [10:0] cu_binary_sao_6_r ;
reg [10:0] cu_binary_sao_7_r ;
wire [2:0] sao_type_w ;
wire [4:0] sao_sub_type_w ;
wire signed [2:0] sao_offset_0_w ;
wire signed [2:0] sao_offset_1_w ;
wire signed [2:0] sao_offset_2_w ;
wire signed [2:0] sao_offset_3_w ;
reg [2:0] sao_offset_0_r ;
reg [2:0] sao_offset_1_r ;
reg [2:0] sao_offset_2_r ;
reg [2:0] sao_offset_3_r ;
reg [4:0] sao_max_uvlc_0_r ;// [4:0]:bins
reg [4:0] sao_max_uvlc_1_r ;// [4:0]:bins
reg [4:0] sao_max_uvlc_2_r ;// [4:0]:bins
reg [4:0] sao_max_uvlc_3_r ;// [4:0]:bins
wire [2:0] sao_max_uvlc_num_0_w ;
wire [2:0] sao_max_uvlc_num_1_w ;
wire [2:0] sao_max_uvlc_num_2_w ;
wire [2:0] sao_max_uvlc_num_3_w ;
wire sao_offset_neq0_0_w ;
wire sao_offset_neq0_1_w ;
wire sao_offset_neq0_2_w ;
wire sao_offset_neq0_3_w ;
reg [4:0] sao_bo_offset_sign_r ;
wire [2:0] sao_bo_offset_num_w ;
wire [2:0] ui_symbol_w ;
assign sao_type_w = sao_data_i[19:17] ;
assign sao_sub_type_w = sao_data_i[16:12] ;
assign sao_offset_3_w = sao_data_i[11:9 ] ;
assign sao_offset_2_w = sao_data_i[ 8:6 ] ;
assign sao_offset_1_w = sao_data_i[ 5:3 ] ;
assign sao_offset_0_w = sao_data_i[ 2:0 ] ;
assign ui_symbol_w = sao_type_w + 2'b1 ;
// sao_offset_abs
always @* begin
case(sao_offset_0_w[2])
1'b1: sao_offset_0_r = (~sao_offset_0_w) + 2'b1 ;
1'b0: sao_offset_0_r = sao_offset_0_w ;
endcase
end
always @* begin
case(sao_offset_1_w[2])
1'b1: sao_offset_1_r = (~sao_offset_1_w) + 2'b1 ;
1'b0: sao_offset_1_r = sao_offset_1_w ;
endcase
end
always @* begin
case(sao_offset_2_w[2])
1'b1: sao_offset_2_r = (~sao_offset_2_w) + 2'b1 ;
1'b0: sao_offset_2_r = sao_offset_2_w ;
endcase
end
always @* begin
case(sao_offset_3_w[2])
1'b1: sao_offset_3_r = (~sao_offset_3_w) + 2'b1 ;
1'b0: sao_offset_3_r = sao_offset_3_w ;
endcase
end
// sao_max_uvlc
always @* begin
case(sao_offset_0_r)
3'd0 : sao_max_uvlc_0_r = 5'b0000_0 ;
3'd1 : sao_max_uvlc_0_r = 5'b0001_0 ;
3'd2 : sao_max_uvlc_0_r = 5'b0011_0 ;
3'd3 : sao_max_uvlc_0_r = 5'b0111_0 ;
3'd4 : sao_max_uvlc_0_r = 5'b1111_0 ;
3'd5 : sao_max_uvlc_0_r = 5'b1111_1 ;
3'd6 : sao_max_uvlc_0_r = 5'b1111_1 ;
3'd7 : sao_max_uvlc_0_r = 5'b1111_1 ;
endcase
end
always @* begin
case(sao_offset_1_r)
3'd0 : sao_max_uvlc_1_r = 5'b0000_0 ;
3'd1 : sao_max_uvlc_1_r = 5'b0001_0 ;
3'd2 : sao_max_uvlc_1_r = 5'b0011_0 ;
3'd3 : sao_max_uvlc_1_r = 5'b0111_0 ;
3'd4 : sao_max_uvlc_1_r = 5'b1111_0 ;
3'd5 : sao_max_uvlc_1_r = 5'b1111_1 ;
3'd6 : sao_max_uvlc_1_r = 5'b1111_1 ;
3'd7 : sao_max_uvlc_1_r = 5'b1111_1 ;
endcase
end
always @* begin
case(sao_offset_2_r)
3'd0 : sao_max_uvlc_2_r = 5'b0000_0 ;
3'd1 : sao_max_uvlc_2_r = 5'b0001_0 ;
3'd2 : sao_max_uvlc_2_r = 5'b0011_0 ;
3'd3 : sao_max_uvlc_2_r = 5'b0111_0 ;
3'd4 : sao_max_uvlc_2_r = 5'b1111_0 ;
3'd5 : sao_max_uvlc_2_r = 5'b1111_1 ;
3'd6 : sao_max_uvlc_2_r = 5'b1111_1 ;
3'd7 : sao_max_uvlc_2_r = 5'b1111_1 ;
endcase
end
always @* begin
case(sao_offset_3_r)
3'd0 : sao_max_uvlc_3_r = 5'b0000_0 ;
3'd1 : sao_max_uvlc_3_r = 5'b0001_0 ;
3'd2 : sao_max_uvlc_3_r = 5'b0011_0 ;
3'd3 : sao_max_uvlc_3_r = 5'b0111_0 ;
3'd4 : sao_max_uvlc_3_r = 5'b1111_0 ;
3'd5 : sao_max_uvlc_3_r = 5'b1111_1 ;
3'd6 : sao_max_uvlc_3_r = 5'b1111_1 ;
3'd7 : sao_max_uvlc_3_r = 5'b1111_1 ;
endcase
end
assign sao_max_uvlc_num_0_w = sao_offset_0_r + 2'b1 ;
assign sao_max_uvlc_num_1_w = sao_offset_1_r + 2'b1 ;
assign sao_max_uvlc_num_2_w = sao_offset_2_r + 2'b1 ;
assign sao_max_uvlc_num_3_w = sao_offset_3_r + 2'b1 ;
assign sao_offset_neq0_0_w = !(!sao_offset_0_w) ;
assign sao_offset_neq0_1_w = !(!sao_offset_1_w) ;
assign sao_offset_neq0_2_w = !(!sao_offset_2_w) ;
assign sao_offset_neq0_3_w = !(!sao_offset_3_w) ;
assign sao_bo_offset_num_w = sao_offset_neq0_0_w + sao_offset_neq0_1_w +
sao_offset_neq0_2_w + sao_offset_neq0_3_w ;
always @*begin
case({sao_offset_neq0_0_w,sao_offset_neq0_1_w,sao_offset_neq0_2_w,sao_offset_neq0_3_w})
4'b0000: sao_bo_offset_sign_r = 5'b0;
4'b0001: sao_bo_offset_sign_r = {4'b0,sao_offset_3_w[2]} ;
4'b0010: sao_bo_offset_sign_r = {4'b0,sao_offset_2_w[2]} ;
4'b0011: sao_bo_offset_sign_r = {3'b0,sao_offset_2_w[2],sao_offset_3_w[2]};
4'b0100: sao_bo_offset_sign_r = {4'b0,sao_offset_1_w[2]} ;
4'b0101: sao_bo_offset_sign_r = {3'b0,sao_offset_1_w[2],sao_offset_3_w[2]};
4'b0110: sao_bo_offset_sign_r = {3'b0,sao_offset_1_w[2],sao_offset_2_w[2]};
4'b0111: sao_bo_offset_sign_r = {2'b0,sao_offset_1_w[2],sao_offset_2_w[2],sao_offset_3_w[2]};
4'b1000: sao_bo_offset_sign_r = {4'b0,sao_offset_0_w[2]} ;
4'b1001: sao_bo_offset_sign_r = {3'b0,sao_offset_0_w[2],sao_offset_3_w[2]};
4'b1010: sao_bo_offset_sign_r = {3'b0,sao_offset_0_w[2],sao_offset_2_w[2]};
4'b1011: sao_bo_offset_sign_r = {2'b0,sao_offset_0_w[2],sao_offset_2_w[2],sao_offset_3_w[2]};
4'b1100: sao_bo_offset_sign_r = {3'b0,sao_offset_0_w[2],sao_offset_1_w[2]};
4'b1101: sao_bo_offset_sign_r = {2'b0,sao_offset_0_w[2],sao_offset_1_w[2],sao_offset_3_w[2]};
4'b1110: sao_bo_offset_sign_r = {2'b0,sao_offset_0_w[2],sao_offset_1_w[2],sao_offset_2_w[2]};
4'b1111: sao_bo_offset_sign_r = {1'b0,sao_offset_0_w[2],sao_offset_1_w[2],sao_offset_2_w[2],sao_offset_3_w[2]};
endcase
end
// saoTypeIdx
always @* begin
if (sao_merge_i)begin // sao_merge_i = merge_left || merge_top
cu_binary_sao_0_r = {2'b01,1'b0,8'hff };
cu_binary_sao_1_r = {2'b01,1'b0,8'hff };
end
else if(sao_compidx_i[1]) begin // sao_compidx_i == 2
cu_binary_sao_0_r = {2'b01,1'b0,8'hff };
cu_binary_sao_1_r = {2'b01,1'b0,8'hff };
end
else if(ui_symbol_w==3'd6) begin // ui_symbol_w ==6
cu_binary_sao_0_r = {2'b00,1'b0,3'd4,5'd20};
cu_binary_sao_1_r = {2'b01,1'b0,8'hff };
end
else begin
cu_binary_sao_0_r = {2'b00,1'b1,3'd4,5'd20};
cu_binary_sao_1_r = {2'b10,1'b0,3'd1,4'b0,(!sao_type_w[2])};
end
end
// sao_offset
always @* begin
if (sao_merge_i)begin // sao_merge_i = merge_left || merge_top
cu_binary_sao_2_r = {2'b01,1'b0,8'hff};
cu_binary_sao_3_r = {2'b01,1'b0,8'hff};
cu_binary_sao_4_r = {2'b01,1'b0,8'hff};
cu_binary_sao_5_r = {2'b01,1'b0,8'hff};
end
else if(ui_symbol_w==3'd6)begin
cu_binary_sao_2_r = {2'b01,1'b0,8'hff};
cu_binary_sao_3_r = {2'b01,1'b0,8'hff};
cu_binary_sao_4_r = {2'b01,1'b0,8'hff};
cu_binary_sao_5_r = {2'b01,1'b0,8'hff};
end
else begin
cu_binary_sao_2_r = {2'b10,1'b0,sao_max_uvlc_num_0_w,sao_max_uvlc_0_r} ;
cu_binary_sao_3_r = {2'b10,1'b0,sao_max_uvlc_num_1_w,sao_max_uvlc_1_r} ;
cu_binary_sao_4_r = {2'b10,1'b0,sao_max_uvlc_num_2_w,sao_max_uvlc_2_r} ;
cu_binary_sao_5_r = {2'b10,1'b0,sao_max_uvlc_num_3_w,sao_max_uvlc_3_r} ;
end
end
// sao_bo_offsetsign
always @* begin
if (sao_merge_i) // sao_merge_i = merge_left || merge_top
cu_binary_sao_6_r = {2'b01,1'b0,8'hff};
else if(ui_symbol_w==3'd6)
cu_binary_sao_6_r = {2'b01,1'b0,8'hff};
else if(sao_type_w==3'd4) // SAO_BO
cu_binary_sao_6_r = {2'b10,1'b0,sao_bo_offset_num_w,sao_bo_offset_sign_r};
else
cu_binary_sao_6_r = {2'b01,1'b0,8'hff};
end
// sao_subTypeIdx
always @* begin
if (sao_merge_i) // sao_merge_i = merge_left || merge_top
cu_binary_sao_7_r = {2'b01,1'b0,8'hff};
else if(ui_symbol_w==3'd6)
cu_binary_sao_7_r = {2'b01,1'b0,8'hff};
else if(sao_type_w[2]) // SAO_BO
cu_binary_sao_7_r = {2'b10,1'b0,3'd5,sao_sub_type_w};
else if(sao_compidx_i[1]) // comp_idx ==2
cu_binary_sao_7_r = {2'b01,1'b0,8'hff};
else
cu_binary_sao_7_r = {2'b10,1'b0,3'd2,2'd0,sao_type_w};
end
assign cu_binary_sao_0_o = cu_binary_sao_0_r ;
assign cu_binary_sao_1_o = cu_binary_sao_1_r ;
assign cu_binary_sao_2_o = cu_binary_sao_2_r ;
assign cu_binary_sao_3_o = cu_binary_sao_3_r ;
assign cu_binary_sao_4_o = cu_binary_sao_4_r ;
assign cu_binary_sao_5_o = cu_binary_sao_5_r ;
assign cu_binary_sao_6_o = cu_binary_sao_6_r ;
assign cu_binary_sao_7_o = cu_binary_sao_7_r ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__OR2B_BEHAVIORAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or2b (
X ,
A ,
B_N
);
// Module ports
output X ;
input A ;
input B_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2B_BEHAVIORAL_V
|
////////////////////////////////////////////////////////////////
// File: new_pipeline.v
// Author: B. Brown
// About: Top-level module for experiment.
////////////////////////////////////////////////////////////////
//=======================================================
// Ports generated by Terasic System Builder
//=======================================================
module new_pipeline(
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
//////////// LED //////////
output [8:0] LEDG,
output [17:0] LEDR,
//////////// KEY //////////
input [3:0] KEY,
//////////// VGA //////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
//////////// I2C for Tv-Decoder //////////
output I2C_SCLK,
inout I2C_SDAT,
//////////// TV Decoder //////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [31:0] DRAM_DQ,
output [3:0] DRAM_DQM,
output DRAM_RAS_N,
output DRAM_WE_N
);
// Input Resolution Parameters (units: pixels)
localparam NTSC_RES_H = 720;
// Output Resolution Parameters (units: pixels)
localparam VGA_RES_POLAR = 1'b0; // HS and VS are active-low for these settings
localparam VGA_RES_H_FRONT = 16; // Horizontal Front Porch
localparam VGA_RES_H_SYNC = 98; // Horizontal Sync Length
localparam VGA_RES_H_BACK = 46; // Horizontal Back Porch
localparam VGA_RES_H_ACT = 640; // Horizontal Actual (Visible)
localparam VGA_RES_V_FRONT = 11; // Vertical Front Porch
localparam VGA_RES_V_SYNC = 2; // Vertical Sync Length
localparam VGA_RES_V_BACK = 31; // Vertical Back Porch
localparam VGA_RES_V_ACT = 480; // Vertical Actual (Visible)
localparam VGA_RES_V_ACT_2 = 240; // Just divide the above number by 2
// SDRAM Parameters (units: pixels)
localparam LINES_ODD_START = VGA_RES_V_FRONT + VGA_RES_V_SYNC;
localparam LINES_ODD_END = LINES_ODD_START + VGA_RES_V_ACT_2;
localparam LINES_EVEN_START = LINES_ODD_END + LINES_ODD_START + 1;
localparam LINES_EVEN_END = LINES_EVEN_START + VGA_RES_V_ACT_2;
// Global Reset
wire aresetn;
// TV Decode Pipeline Output
wire [9:0] Red; // RGB data after YCbCr conversion
wire [9:0] Green; // RGB data after YCbCr conversion
wire [9:0] Blue; // RGB data after YCbCr conversion
wire RGB_valid; // Valid RGB data after YCbCr conversion, unused
// Field Select
wire [15:0] rgb_packed_write; // SDRAM write data
wire [15:0] rgb_packed_read; // SDRAM read data muxed for odd or even field
wire [15:0] rgb_packed_odd; // SDRAM data odd field
wire [15:0] rgb_packed_even; // SDRAM data even field
wire vga_odd_ready; // VGA data request odd field
wire vga_even_ready; // VGA data request even field
// VGA Controller Output
wire [10:0] vga_x; // VGA position, used in 422:444 converter
wire [10:0] vga_y; // VGA vertical position, used to determine odd or even field
wire vga_ready; // VGA data request
// Reset to Key
assign aresetn = KEY[0];
// Video Input Decode Pipeline
video_input video_input_inst
(
.aresetn (aresetn),
// TV Decoder
.TD_CLK27 (TD_CLK27),
.TD_DATA (TD_DATA),
.TD_HS (TD_HS),
.TD_RESET_N (TD_RESET_N),
.TD_VS (TD_VS),
// RGB
.R_out (Red),
.B_out (Blue),
.G_out (Green),
.RGB_valid (RGB_valid)
);
// RGB 30-bit to RGB 16-bit
assign rgb_packed_write = {Red[9:5], Green[9:4], Blue[9:5]};
// SDRAM Frame Buffer
Sdram_Control_4Port sdram_control_inst
(
.REF_CLK (TD_CLK27),
.RESET_N (aresetn),
// FIFO Write Side 1
.WR1_DATA (rgb_packed_write),
.WR1 (RGB_valid), // Write Enable
.WR1_ADDR (0), // Base address
.WR1_MAX_ADDR (VGA_RES_H_ACT*LINES_EVEN_END), // Store every pixel of every line. Blanking lines, odd lines, blanking lines, and even lines.
.WR1_LENGTH (9'h80), // The valid signal drops low every 8 samples, 16*8 = 128 bits per burst?
.WR1_LOAD (~aresetn), // Clears FIFO
.WR1_CLK (TD_CLK27),
// FIFO Read Side 1 (Odd Field, Bypass Blanking)
.RD1_DATA (rgb_packed_odd),
.RD1 (vga_odd_ready), // Read Enable
.RD1_ADDR (VGA_RES_H_ACT*LINES_ODD_START), // Bypass the blanking lines
.RD1_MAX_ADDR (VGA_RES_H_ACT*LINES_ODD_END ), // Read out of the valid odd lines
.RD1_LENGTH (9'h80), // Just being consistent with write length?
.RD1_LOAD (~aresetn), // Clears FIFO
.RD1_CLK (TD_CLK27),
// FIFO Read Side 2 (Even Field, Bypass Blanking)
.RD2_DATA (rgb_packed_even),
.RD2 (vga_even_ready), // Read Enable
.RD2_ADDR (VGA_RES_H_ACT*LINES_EVEN_START), // Bypass the blanking lines
.RD2_MAX_ADDR (VGA_RES_H_ACT*LINES_EVEN_END ), // Read out of the valid even lines
.RD2_LENGTH (9'h80), // Just being consistent with write length?
.RD2_LOAD (~aresetn), // Clears FIFO
.RD2_CLK (TD_CLK27),
// SDRAM
.SA (DRAM_ADDR),
.BA (DRAM_BA),
.CS_N (DRAM_CS_N),
.CKE (DRAM_CKE),
.RAS_N (DRAM_RAS_N),
.CAS_N (DRAM_CAS_N),
.WE_N (DRAM_WE_N),
.DQ (DRAM_DQ),
.DQM ({DRAM_DQM[1], DRAM_DQM[0]}),
.SDR_CLK (DRAM_CLK)
);
// Field Select Logic (Odd/Even)
assign vga_odd_ready = vga_y[0] ? 1'b0 : vga_ready;
assign vga_even_ready = vga_y[0] ? vga_ready : 1'b0;
assign rgb_packed_read = ~vga_y[0] ? rgb_packed_odd : rgb_packed_even;
// VGA Controller
vga_sync #(
.H_TOTAL_WIDTH (11),
.V_TOTAL_WIDTH (11),
.POLARITY (VGA_RES_POLAR),
.H_FRONT (VGA_RES_H_FRONT),
.H_SYNC (VGA_RES_H_SYNC),
.H_BACK (VGA_RES_H_BACK),
.H_ACT (VGA_RES_H_ACT),
.V_FRONT (VGA_RES_V_FRONT),
.V_SYNC (VGA_RES_V_SYNC),
.V_BACK (VGA_RES_V_BACK),
.V_ACT (VGA_RES_V_ACT)
) vga_sync_inst (
.clock (TD_CLK27),
.aresetn (aresetn),
// Input Data
.R_in ({rgb_packed_read[15:11], 5'b00000}),
.G_in ({rgb_packed_read[10: 5], 4'b0000 }),
.B_in ({rgb_packed_read[ 4: 0], 5'b00000}),
// Output Control Logic
.current_x (vga_x),
.current_y (vga_y),
.ready (vga_ready),
// Output VGA Signals
.vga_clk (VGA_CLK),
.R_out (VGA_R),
.G_out (VGA_G),
.B_out (VGA_B),
.h_sync (VGA_HS),
.v_sync (VGA_VS),
.blank_n (VGA_BLANK_N),
.sync_n (VGA_SYNC_N)
);
endmodule
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=5 clk1_phase_shift="-1500" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=44288 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 15.1 cbx_altclkbuf 2016:02:01:19:04:59:SJ cbx_altiobuf_bidir 2016:02:01:19:04:59:SJ cbx_altiobuf_in 2016:02:01:19:04:59:SJ cbx_altiobuf_out 2016:02:01:19:04:59:SJ cbx_altpll 2016:02:01:19:04:59:SJ cbx_altpll_avalon 2016:02:01:19:04:59:SJ cbx_cycloneii 2016:02:01:19:04:59:SJ cbx_lpm_add_sub 2016:02:01:19:04:59:SJ cbx_lpm_compare 2016:02:01:19:04:59:SJ cbx_lpm_counter 2016:02:01:19:04:59:SJ cbx_lpm_decode 2016:02:01:19:04:59:SJ cbx_lpm_mux 2016:02:01:19:04:59:SJ cbx_lpm_shiftreg 2016:02:01:19:04:59:SJ cbx_mgl 2016:02:01:19:07:00:SJ cbx_nadder 2016:02:01:19:04:59:SJ cbx_stratix 2016:02:01:19:05:00:SJ cbx_stratixii 2016:02:01:19:05:00:SJ cbx_stratixiii 2016:02:01:19:05:00:SJ cbx_stratixv 2016:02:01:19:05:00:SJ cbx_util_mgl 2016:02:01:19:04:59:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 15.1 cbx_mgl 2016:02:01:19:07:00:SJ cbx_stratixii 2016:02:01:19:05:00:SJ cbx_util_mgl 2016:02:01:19:04:59:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 15.1 cbx_mgl 2016:02:01:19:07:00:SJ cbx_stratixii 2016:02:01:19:05:00:SJ cbx_util_mgl 2016:02:01:19:04:59:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module wasca_altpll_0_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //wasca_altpll_0_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_0_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
wasca_altpll_0_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //wasca_altpll_0_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=5 clk1_phase_shift="-1500" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=44288 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 15.1 cbx_altclkbuf 2016:02:01:19:04:59:SJ cbx_altiobuf_bidir 2016:02:01:19:04:59:SJ cbx_altiobuf_in 2016:02:01:19:04:59:SJ cbx_altiobuf_out 2016:02:01:19:04:59:SJ cbx_altpll 2016:02:01:19:04:59:SJ cbx_cycloneii 2016:02:01:19:04:59:SJ cbx_lpm_add_sub 2016:02:01:19:04:59:SJ cbx_lpm_compare 2016:02:01:19:04:59:SJ cbx_lpm_counter 2016:02:01:19:04:59:SJ cbx_lpm_decode 2016:02:01:19:04:59:SJ cbx_lpm_mux 2016:02:01:19:04:59:SJ cbx_mgl 2016:02:01:19:07:00:SJ cbx_nadder 2016:02:01:19:04:59:SJ cbx_stratix 2016:02:01:19:05:00:SJ cbx_stratixii 2016:02:01:19:05:00:SJ cbx_stratixiii 2016:02:01:19:05:00:SJ cbx_stratixv 2016:02:01:19:05:00:SJ cbx_util_mgl 2016:02:01:19:04:59:SJ VERSION_END
//synthesis_resources = fiftyfivenm_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module wasca_altpll_0_altpll_4i92
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
fiftyfivenm_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 5,
pll7.clk0_phase_shift = "0",
pll7.clk1_divide_by = 1,
pll7.clk1_duty_cycle = 50,
pll7.clk1_multiply_by = 5,
pll7.clk1_phase_shift = "-1500",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 44288,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "fiftyfivenm_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //wasca_altpll_0_altpll_4i92
//synthesis_resources = fiftyfivenm_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_0
(
address,
areset,
c0,
c1,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
wasca_altpll_0_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
wasca_altpll_0_altpll_4i92 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //wasca_altpll_0
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKINV_BLACKBOX_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
|
`default_nettype none
`timescale 1ns/1ns
module tb_func_level;
localparam PL_CORE_CYCLE = 20; //It's necessary "Core Clock == Bus Clock". This restriction is removed near future.
localparam PL_BUS_CYCLE = 20; //
localparam PL_DPS_CYCLE = 18;
localparam PL_RESET_TIME = 20;
localparam PL_GCI_SIZE = 32'h0001_0000;
/****************************************
System
****************************************/
reg iCORE_CLOCK;
reg iBUS_CLOCK;
reg iDPS_CLOCK;
reg inRESET;
/****************************************
SCI
****************************************/
wire oSCI_TXD;
reg iSCI_RXD;
/****************************************
Memory BUS
****************************************/
//Req
wire oMEMORY_REQ;
wire iMEMORY_LOCK;
wire [1:0] oMEMORY_ORDER; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
wire [3:0] oMEMORY_MASK;
wire oMEMORY_RW; //1:Write | 0:Read
wire [31:0] oMEMORY_ADDR;
//This -> Data RAM
wire [31:0] oMEMORY_DATA;
//Data RAM -> This
wire iMEMORY_VALID;
wire oMEMORY_BUSY;
wire [63:0] iMEMORY_DATA;
/****************************************
GCI BUS
****************************************/
//Request
wire oGCI_REQ; //Input
reg iGCI_BUSY;
wire oGCI_RW; //0=Read : 1=Write
wire [31:0] oGCI_ADDR;
wire [31:0] oGCI_DATA;
//Return
reg iGCI_REQ; //Output
wire oGCI_BUSY;
reg [31:0] iGCI_DATA;
//Interrupt
reg iGCI_IRQ_REQ;
reg [5:0] iGCI_IRQ_NUM;
wire oGCI_IRQ_ACK;
//Interrupt Controll
wire oIO_IRQ_CONFIG_TABLE_REQ;
wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY;
wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK;
wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID;
wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL;
wire [31:0] oDEBUG_PC;
wire [31:0] oDEBUG0;
/****************************************
Debug
****************************************/
reg iDEBUG_UART_RXD;
wire oDEBUG_UART_TXD;
reg iDEBUG_PARA_REQ;
wire oDEBUG_PARA_BUSY;
reg [7:0] iDEBUG_PARA_CMD;
reg [31:0] iDEBUG_PARA_DATA;
wire oDEBUG_PARA_VALID;
reg iDEBUG_PARA_BUSY;
wire oDEBUG_PARA_ERROR;
wire [31:0] oDEBUG_PARA_DATA;
/******************************************************
Target
******************************************************/
mist1032isa TARGET(
/****************************************
System
****************************************/
/*
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(iBUS_CLOCK),
.iDPS_CLOCK(iDPS_CLOCK),
*/
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(iCORE_CLOCK),
.iDPS_CLOCK(iCORE_CLOCK),
.inRESET(inRESET),
/****************************************
SCI
****************************************/
.oSCI_TXD(oSCI_TXD),
.iSCI_RXD(iSCI_RXD),
/****************************************
Memory BUS
****************************************/
//Req
.oMEMORY_REQ(oMEMORY_REQ),
.iMEMORY_LOCK(iMEMORY_LOCK),
.oMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.oMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.oMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.iMEMORY_VALID(iMEMORY_VALID),
.oMEMORY_BUSY(oMEMORY_BUSY),
.iMEMORY_DATA(iMEMORY_DATA),
/****************************************
GCI BUS
****************************************/
//Request
.oGCI_REQ(oGCI_REQ), //Input
.iGCI_BUSY(iGCI_BUSY),
.oGCI_RW(oGCI_RW), //0=Read : 1=Write
.oGCI_ADDR(oGCI_ADDR),
.oGCI_DATA(oGCI_DATA),
//Return
.iGCI_REQ(iGCI_REQ), //Output
.oGCI_BUSY(oGCI_BUSY),
.iGCI_DATA(iGCI_DATA),
//Interrupt
.iGCI_IRQ_REQ(iGCI_IRQ_REQ),
.iGCI_IRQ_NUM(iGCI_IRQ_NUM),
.oGCI_IRQ_ACK(oGCI_IRQ_ACK),
//Interrupt Controll
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
.oDEBUG_PC(oDEBUG_PC),
.oDEBUG0(oDEBUG0),
/****************************************
Debug
****************************************/
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA)
);
/******************************************************
Clock
******************************************************/
always#(PL_CORE_CYCLE/2)begin
iCORE_CLOCK = !iCORE_CLOCK;
end
always#(PL_BUS_CYCLE/2)begin
iBUS_CLOCK = !iBUS_CLOCK;
end
always#(PL_DPS_CYCLE/2)begin
iDPS_CLOCK = !iDPS_CLOCK;
end
/******************************************************
State
******************************************************/
initial begin
$display("Check Start");
//Initial
iCORE_CLOCK = 1'b0;
iBUS_CLOCK = 1'b0;
iDPS_CLOCK = 1'b0;
inRESET = 1'b0;
iSCI_RXD = 1'b1;
iGCI_BUSY = 1'b0;
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
iGCI_IRQ_REQ = 1'b0;
iGCI_IRQ_NUM = 6'h0;
iDEBUG_UART_RXD = 1'b1;
iDEBUG_PARA_REQ = 1'b0;
iDEBUG_PARA_CMD = 8'h0;
iDEBUG_PARA_DATA = 32'h0;
iDEBUG_PARA_BUSY = 1'b0;
//Reset After
#(PL_RESET_TIME);
inRESET = 1'b1;
//GCI Init
#(PL_BUS_CYCLE*32);
while(oGCI_BUSY) #(PL_BUS_CYCLE);
iGCI_REQ = 1'b1;
iGCI_DATA = PL_GCI_SIZE;
#(PL_BUS_CYCLE);
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
#15000000 begin
$finish;
end
end
/******************************************************
Memory Model
******************************************************/
sim_memory_model #(1, "tb_func_test.hex") MEMORY_MODEL(
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
//Req
.iMEMORY_REQ(oMEMORY_REQ),
.oMEMORY_LOCK(iMEMORY_LOCK),
.iMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iMEMORY_MASK(oMEMORY_MASK),
.iMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.iMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.iMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.oMEMORY_VALID(iMEMORY_VALID),
.iMEMORY_LOCK(oMEMORY_BUSY),
.oMEMORY_DATA(iMEMORY_DATA)
);
/******************************************************
Assertion
******************************************************/
reg assert_check_flag;
reg [31:0] assert_wrong_number;
reg [31:0] assert_wrong_type;
reg [31:0] assert_result;
reg [31:0] assert_expect;
always@(posedge iCORE_CLOCK)begin
if(inRESET && oMEMORY_REQ && !iMEMORY_LOCK && oMEMORY_ORDER == 2'h2 && oMEMORY_RW)begin
//Finish Check
if(oMEMORY_ADDR == 32'h0002_0004)begin
if(!assert_check_flag)begin
$display("[SIM-ERR]Wrong Data.");
$display("[SIM-ERR]Wrong Type : %d", assert_wrong_type);
$display("[SIM-ERR]Index:%d, Expect:%x, Result:%x", assert_wrong_number, assert_expect, assert_result);
$display("[SIM-ERR]Simulation Finished.");
$finish;
end
else begin
$display("[SIM-OK]Simulation Finished.");
$finish;
end
end
//Check Log
else if(oMEMORY_ADDR == 32'h0002_0008)begin
$display("[SIM-LOG]#d", {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]});
end
//Check Flag
else if(oMEMORY_ADDR == 32'h0002_0000)begin
assert_check_flag = oMEMORY_DATA[24];
end
//Error Number
else if(oMEMORY_ADDR == 32'h0002_0010)begin
assert_wrong_number = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Type
else if(oMEMORY_ADDR == 32'h0002_000c)begin
assert_wrong_type = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Result
else if(oMEMORY_ADDR == 32'h0002_0014)begin
assert_result = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Expect
else if(oMEMORY_ADDR == 32'h0002_0018)begin
assert_expect = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
end
end
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_M_V
`define SKY130_FD_SC_LP__A2111OI_M_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_m (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_m (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_SYMBOL_V
`define SKY130_FD_SC_HVL__A21O_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_SYMBOL_V
|
`timescale 1ns / 1ps
module ADAU1761Top(
input clk,
input filter_onoff,
input AC_GPIO1,
input AC_GPIO2,
input AC_GPIO3,
output AC_GPIO0,
output AC_ADR0,
output AC_ADR1,
output AC_MCLK,
output AC_SCK,
inout AC_SDA,
input [3:0] shift,
output [2:0] display_rgb1,
output [2:0] display_rgb2,
output [3:0] display_addr,
output display_clk,
output display_oe,
output display_lat,
//input on_off,
output spi_clk,
output spi_mosi,
output spi_cs,
input spi_miso,
input rst,
output [7:0] sample
);
wire throwaway, bt1, bt2, uart1, uart2, clean;
reg [3:0] height;
reg mode, on_off;
initial begin
height <=0;
mode <=1;
on_off <=0;
end
always @(posedge CLK_OUT2) begin
if (mode == 1'b0 && clean == 1'b1) begin
on_off <= ~on_off;
end
end
always @ (posedge clk_48) begin
if (filter_onoff) begin
height <= ((((headphone_left[14:0] >>> 14) ^ headphone_left) - (headphone_left >>>14)) >> shift) - 15;
end
else begin
height <= (((fft_out_l >>> 15) ^ fft_out_l) - (fft_out_l >>> 15)) >> 6;
//height <= fft_out_l ;
end
end
// 48 MHz clock
wire clk_48, CLK_OUT1, CLK_OUT2, LOCKED;
Clock48MHZ c48(// Clock in ports
.CLK_100(clk),
.CLK_48(clk_48),
.CLK_OUT1(CLK_OUT1),
.CLK_OUT2(CLK_OUT2),
// Status and control signals
.LOCKED(LOCKED)
);
MicrophoneSampler microphone(
spi_clk,
spi_mosi,
spi_cs,
spi_miso,
CLK_OUT2,
rst,
sample);
/* Clock48MHZ c48(
.CLK_100(clk),
.CLK_48(clk_48)
);*/
// Audio module
wire [15:0] headphone_left, headphone_right, linein_left, linein_right;
wire new_sample;
wire data_in_ready, data_in_valid, data_out_valid, slave_ready;
wire [7:0] output_index_l;
wire [15:0] fft_out_l;
assign data_in_valid = 1'b1;
assign slave_ready = 1'b1;
wrap_FFT fft_wrapper_left (
.clk(clk_48),
.data_in(linein_left),
.data_out(fft_out_l),
.data_out_valid(data_out_valid),
.data_in_ready(data_in_ready),
.data_in_valid(data_in_valid),
.slave_ready(slave_ready),
.output_index(output_index_l)
);
adau1761_izedboard(
.clk_48(clk_48),
.AC_GPIO1(AC_GPIO1),
.AC_GPIO2(AC_GPIO2),
.AC_GPIO3(AC_GPIO3),
.hphone_l(headphone_left),
.hphone_r(headphone_right),
.AC_SDA(AC_SDA),
.AC_ADR0(AC_ADR0),
.AC_ADR1(AC_ADR1),
.AC_GPIO0(AC_GPIO0),
.AC_MCLK(AC_MCLK),
.AC_SCK(AC_SCK),
.line_in_l(linein_left),
.line_in_r(linein_right),
.new_sample(new_sample)
);
fpga_top(
.clk(clk),
.led(throwaway),
.bluetooth_rxd(bt1),
.bluetooth_txd(bt2),
.display_rgb1(display_rgb1),
.display_rgb2(display_rgb2),
.display_addr(display_addr),
.display_clk(display_clk),
.display_oe(display_oe),
.display_lat(display_lat),
.usb_rxd(uart1),
.usb_txd(uart2),
.height(height),
.mode(mode),
.on_off(on_off),
.sysclk(CLK_OUT1),
.xn_index(output_index_l),
.pll_locked(LOCKED));
wire [15:0] filter_out_left, filter_out_right;
SystolicFilter(clk_48, new_sample, linein_left, filter_out_left);
SystolicFilter(clk_48, new_sample, linein_right, filter_out_right);
assign headphone_left = (filter_onoff) ? filter_out_left : linein_left;
assign headphone_right = (filter_onoff) ? filter_out_right : linein_right;
endmodule
module debouncer(clk, button, clean);
input clk, button;
output reg clean;
parameter delay = 500;
reg [8:0] delay_count;
always@(posedge clk)
if (button==1) begin
if (delay_count==delay) begin
assign delay_count=delay_count+1'b1;
assign clean=1;
end else begin
if(delay_count==9'b1111_11111) begin
assign clean=0;
assign delay_count=9'b1111_11111;
end else begin
assign delay_count=delay_count+1'b1;
assign clean=0;
end
end
end else begin
assign delay_count=0;
assign clean=0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLRBP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_BLACKBOX_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module altera_mem_if_ddr3_phy_0001_read_valid_selector(
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select(
.data (latency_counter),
.eq (selector)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.enable ()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM;
defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
selector_reg <= {LATENCY_NUM{1'b0}};
else
selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end
else
begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:06:45 03/31/2015
// Design Name:
// Module Name: Adder64
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Adder64(
input [63:0] A,
input [63:0] B,
input C0,
output [3:0] P,
output [3:0] G,
output [63:0] sum,
output SF,
output CF,
output OF,
output PF,
output ZF
);
wire[15:0] _p_,_g_;
wire[4:0] C;
wire[3:0] _sf_,_cf_,_of_,_pf_,_zf_;
pg_to_PG pgtoPG(_p_,_g_,P,G);
ParallelCarry4 PC(P,G,C0,C);
Adder16
a1(A[15: 0],B[15: 0],C[0],_p_[ 3: 0],_g_[ 3: 0],sum[15: 0],_sf_[0],_cf_[0],_of_[0],_pf_[0],_zf_[0]),
a2(A[31:16],B[31:16],C[1],_p_[ 7: 4],_g_[ 7: 4],sum[31:16],_sf_[1],_cf_[1],_of_[1],_pf_[1],_zf_[1]),
a3(A[47:32],B[47:32],C[2],_p_[11: 8],_g_[11: 8],sum[47:32],_sf_[2],_cf_[2],_of_[2],_pf_[2],_zf_[2]),
a4(A[63:48],B[63:48],C[3],_p_[15:12],_g_[15:12],sum[63:48],_sf_[3],_cf_[3],_of_[3],_pf_[3],_zf_[3]);
assign SF=_sf_[3],
CF=C[4],
OF=_of_[3],
PF=^_pf_[3:0],
ZF= ~|(~_zf_[3:0]);
endmodule
|
`default_nettype none
module plle2_test
(
input wire CLK,
input wire RST,
input wire I_CLKINSEL,
output wire O_LOCKED,
output wire [5:0] O_CNT
);
// ============================================================================
// Input clock divider (to get different clkins)
wire clk100;
reg clk50;
assign clk100 = CLK;
always @(posedge clk100)
clk50 <= !clk50;
// ============================================================================
// The PLL
wire clk_fb_o;
wire clk_fb_i;
wire [5:0] clk;
PLLE2_ADV #
(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("BUF_IN"),
.CLKIN1_PERIOD (20.0), // 50MHz
.CLKIN2_PERIOD (10.0), // 100MHz
.CLKFBOUT_MULT (16),
.CLKFBOUT_PHASE (0.0),
.CLKOUT0_DIVIDE (16),
.CLKOUT0_DUTY_CYCLE (0.53125),
.CLKOUT0_PHASE (45.0),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_DUTY_CYCLE (0.5),
.CLKOUT1_PHASE (90.0),
.CLKOUT2_DIVIDE (48),
.CLKOUT2_DUTY_CYCLE (0.5),
.CLKOUT2_PHASE (135.0),
.CLKOUT3_DIVIDE (64),
.CLKOUT3_DUTY_CYCLE (0.5),
.CLKOUT3_PHASE (-45.0),
.CLKOUT4_DIVIDE (80),
.CLKOUT4_DUTY_CYCLE (0.5),
.CLKOUT4_PHASE (-90.0),
.CLKOUT5_DIVIDE (96),
.CLKOUT5_DUTY_CYCLE (0.5),
.CLKOUT5_PHASE (-135.0),
.STARTUP_WAIT ("FALSE")
)
pll
(
.CLKIN1 (clk50),
.CLKIN2 (clk100),
.CLKINSEL (I_CLKINSEL),
.RST (RST),
.LOCKED (O_LOCKED),
.CLKFBIN (clk_fb_i),
.CLKFBOUT (clk_fb_o),
.CLKOUT0 (clk[0]),
.CLKOUT1 (clk[1]),
.CLKOUT2 (clk[2]),
.CLKOUT3 (clk[3]),
.CLKOUT4 (clk[4]),
.CLKOUT5 (clk[5])
);
BUFG clk_fb_buf (.I(clk_fb_o), .O(clk_fb_i));
// ============================================================================
// Counters
wire rst = RST || !O_LOCKED;
genvar i;
generate for (i=0; i<6; i=i+1) begin
reg [23:0] counter;
always @(posedge clk[i] or posedge rst)
if (rst) counter <= 0;
else counter <= counter + 1;
assign O_CNT[i] = counter[21];
end endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTN_TB_V
`define SKY130_FD_SC_MS__DLXTN_TB_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxtn.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_ms__dlxtn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog wrapper for lsbufhv2lv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbufhv2lv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbufhv2lv base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbufhv2lv base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 14:48:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_pll_0_0 -prefix
// system_vga_pll_0_0_ system_vga_pll_0_0_stub.v
// Design : system_vga_pll_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_pll,Vivado 2016.4" *)
module system_vga_pll_0_0(clk_100, clk_50, clk_25, clk_12_5, clk_6_25)
/* synthesis syn_black_box black_box_pad_pin="clk_100,clk_50,clk_25,clk_12_5,clk_6_25" */;
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:04:01 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_processing_system7_0_0 -prefix
// system_processing_system7_0_0_ system_processing_system7_0_0_stub.v
// Design : system_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module system_processing_system7_0_0(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
`include "alu_ops.vh"
`include "rv32_opcodes.vh"
module alu(
input [`ALU_OP_WIDTH-1:0] op,
input [`XPR_LEN-1:0] in1,
input [`XPR_LEN-1:0] in2,
output reg [`XPR_LEN-1:0] out
);
wire [`SHAMT_WIDTH-1:0] shamt;
assign shamt = in2[`SHAMT_WIDTH-1:0];
always @(*) begin
case (op)
`ALU_OP_ADD : out = in1 + in2;
`ALU_OP_SLL : out = in1 << shamt;
`ALU_OP_XOR : out = in1 ^ in2;
`ALU_OP_OR : out = in1 | in2;
`ALU_OP_AND : out = in1 & in2;
`ALU_OP_SRL : out = in1 >> shamt;
`ALU_OP_SEQ : out = {31'b0, in1 == in2};
`ALU_OP_SNE : out = {31'b0, in1 != in2};
`ALU_OP_SUB : out = in1 - in2;
`ALU_OP_SRA : out = $signed(in1) >>> shamt;
`ALU_OP_SLT : out = {31'b0, $signed(in1) < $signed(in2)};
`ALU_OP_SGE : out = {31'b0, $signed(in1) >= $signed(in2)};
`ALU_OP_SLTU : out = {31'b0, in1 < in2};
`ALU_OP_SGEU : out = {31'b0, in1 >= in2};
default : out = 0;
endcase // case op
end
endmodule // alu
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_1_V
`define SKY130_FD_SC_LP__EINVP_1_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_1 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_1 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_1_V
|
module count_hours(
twentyfour_mode,
manual_inc,
automatic_inc,
ones_digit,
tens_digit,
am,
pm,
count_out
);
// port declarations
input twentyfour_mode;
input manual_inc;
input automatic_inc;
output [3:0] ones_digit;
output [3:0] tens_digit;
output reg am;
output reg pm;
output reg count_out;
// wire declarations
wire carry;
reg module_reset;
reg pre_count;
reg increment;
// teh logikz
initial module_reset <= 0;
bcd_counter u1(
module_reset,
increment,
ones_digit,
carry
);
bcd_counter u2(
module_reset,
carry,
tens_digit,
);
always begin
// We handle manual increments by making it
if (manual_inc) begin
count_out <= 0;
increment <= 1;
// Since twelve hour mode cannot allow 0 hours (damn you, non computer
// - scientists / engineers!), we have to take care of the case in which
// - it becomes zero.
end else if (!twentyfour_mode && tens_digit == 4'h0 && ones_digit == 4'h0)
begin
increment <= 1;
#1 increment <= 0;
// I had to add this here to make it work; I don't know why.
increment <= automatic_inc;
// This is the general case.
end else begin
increment <= automatic_inc;
count_out <= module_reset;
end
module_reset <= (
!twentyfour_mode && tens_digit == 4'h1 && ones_digit == 4'h3
|| twentyfour_mode && tens_digit == 4'h2 && ones_digit == 4'h4
);
end
always @ (posedge module_reset) begin
if (!twentyfour_mode)
if (am) begin
pm <= 1;
am <= 0;
end else begin
am <= 1;
pm <= 0;
end
else begin
am <= 0;
pm <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_TB_V
`define SKY130_FD_SC_HS__NAND3B_TB_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A_N = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A_N = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A_N = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A_N = 1'bx;
end
sky130_fd_sc_hs__nand3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_PP_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatchhv_pp_plg_s/sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_PP_V
|
//Ivan Castellanos
module multi (P, A, B);
input [7:0] A;
input [7:0] B;
output [15:0] P;
//row b0
wire wa10,wa20,wa30,wa40,wa50,wa60,wn70;
//row b1
wire wmhc01,wmhc11,wmhc21,wmhc31,wmhc41,wmhc51,wmhc61;
wire wmhs11,wmhs21,wmhs31,wmhs41,wmhs51,wmhs61,wn71;
//row b2
wire wmfc02,wmfc12,wmfc22,wmfc32,wmfc42,wmfc52,wmfc62;
wire wmfs12,wmfs22,wmfs32,wmfs42,wmfs52,wmfs62,wn72;
//row b3
wire wmfc03,wmfc13,wmfc23,wmfc33,wmfc43,wmfc53,wmfc63;
wire wmfs13,wmfs23,wmfs33,wmfs43,wmfs53,wmfs63,wn73;
//row b4
wire wmfc04,wmfc14,wmfc24,wmfc34,wmfc44,wmfc54,wmfc64;
wire wmfs14,wmfs24,wmfs34,wmfs44,wmfs54,wmfs64,wn74;
//row b5
wire wmfc05,wmfc15,wmfc25,wmfc35,wmfc45,wmfc55,wmfc65;
wire wmfs15,wmfs25,wmfs35,wmfs45,wmfs55,wmfs65,wn75;
//row b6
wire wmfc06,wmfc16,wmfc26,wmfc36,wmfc46,wmfc56,wmfc66;
wire wmfs16,wmfs26,wmfs36,wmfs46,wmfs56,wmfs66,wn76;
//row b7
wire wnmfc07,wnmfc17,wnmfc27,wnmfc37,wnmfc47,wnmfc57,wnmfc67;
wire wnmfs17,wnmfs27,wnmfs37,wnmfs47,wnmfs57,wnmfs67,wa77;
//row b8
wire wfac08,wfac18,wfac28,wfac38,wfac48,wfac58,wfac68;
//Row bo Implementation
and a00(P[0] , A[0], B[0]);
and a10(wa10 ,A[1], B[0]);
and a20(wa20 ,A[2], B[0]);
and a30(wa30 ,A[3], B[0]);
and a40(wa40 ,A[4], B[0]);
and a50(wa50 ,A[5], B[0]);
and a60(wa60 ,A[6], B[0]);
nand n70(wn70 ,A[7], B[0]);
//Row b1
MHA mha01(.Sum(P[1]), .Cout(wmhc01), .A(A[0]), .B(B[1]), .Sin(wa10));
MHA mha11(.Sum(wmhs11), .Cout(wmhc11), .A(A[1]), .B(B[1]), .Sin(wa20));
MHA mha21(.Sum(wmhs21), .Cout(wmhc21), .A(A[2]), .B(B[1]), .Sin(wa30));
MHA mha31(.Sum(wmhs31), .Cout(wmhc31), .A(A[3]), .B(B[1]), .Sin(wa40));
MHA mha41(.Sum(wmhs41), .Cout(wmhc41), .A(A[4]), .B(B[1]), .Sin(wa50));
MHA mha51(.Sum(wmhs51), .Cout(wmhc51), .A(A[5]), .B(B[1]), .Sin(wa60));
MHA mha61(.Sum(wmhs61), .Cout(wmhc61), .A(A[6]), .B(B[1]), .Sin(wn70));
nand n71(wn71, A[7], B[1]);
//Row b2
MFA mfa02(.Sum(P[2]), .Cout(wmfc02), .A(A[0]), .B(B[2]), .Sin(wmhs11), .Cin(wmhc01));
MFA mfa12(.Sum(wmfs12), .Cout(wmfc12), .A(A[1]), .B(B[2]), .Sin(wmhs21), .Cin(wmhc11));
MFA mfa22(.Sum(wmfs22), .Cout(wmfc22), .A(A[2]), .B(B[2]), .Sin(wmhs31), .Cin(wmhc21));
MFA mfa32(.Sum(wmfs32), .Cout(wmfc32), .A(A[3]), .B(B[2]), .Sin(wmhs41), .Cin(wmhc31));
MFA mfa42(.Sum(wmfs42), .Cout(wmfc42), .A(A[4]), .B(B[2]), .Sin(wmhs51), .Cin(wmhc41));
MFA mfa52(.Sum(wmfs52), .Cout(wmfc52), .A(A[5]), .B(B[2]), .Sin(wmhs61), .Cin(wmhc51));
MFA mfa62(.Sum(wmfs62), .Cout(wmfc62), .A(A[6]), .B(B[2]), .Sin(wn71), .Cin(wmhc61));
nand n72(wn72, A[7], B[2]);
//Row b3
MFA mfa03(.Sum(P[3]), .Cout(wmfc03), .A(A[0]), .B(B[3]), .Sin(wmfs12), .Cin(wmfc02));
MFA mfa13(.Sum(wmfs13), .Cout(wmfc13), .A(A[1]), .B(B[3]), .Sin(wmfs22), .Cin(wmfc12));
MFA mfa23(.Sum(wmfs23), .Cout(wmfc23), .A(A[2]), .B(B[3]), .Sin(wmfs32), .Cin(wmfc22));
MFA mfa33(.Sum(wmfs33), .Cout(wmfc33), .A(A[3]), .B(B[3]), .Sin(wmfs42), .Cin(wmfc32));
MFA mfa43(.Sum(wmfs43), .Cout(wmfc43), .A(A[4]), .B(B[3]), .Sin(wmfs52), .Cin(wmfc42));
MFA mfa53(.Sum(wmfs53), .Cout(wmfc53), .A(A[5]), .B(B[3]), .Sin(wmfs62), .Cin(wmfc52));
MFA mfa63(.Sum(wmfs63), .Cout(wmfc63), .A(A[6]), .B(B[3]), .Sin(wn72), .Cin(wmfc62));
nand n73(wn73, A[7], B[3]);
//Row b4
MFA mfa04(.Sum(P[4]), .Cout(wmfc04), .A(A[0]), .B(B[4]), .Sin(wmfs13), .Cin(wmfc03));
MFA mfa14(.Sum(wmfs14), .Cout(wmfc14), .A(A[1]), .B(B[4]), .Sin(wmfs23), .Cin(wmfc13));
MFA mfa24(.Sum(wmfs24), .Cout(wmfc24), .A(A[2]), .B(B[4]), .Sin(wmfs33), .Cin(wmfc23));
MFA mfa34(.Sum(wmfs34), .Cout(wmfc34), .A(A[3]), .B(B[4]), .Sin(wmfs43), .Cin(wmfc33));
MFA mfa44(.Sum(wmfs44), .Cout(wmfc44), .A(A[4]), .B(B[4]), .Sin(wmfs53), .Cin(wmfc43));
MFA mfa54(.Sum(wmfs54), .Cout(wmfc54), .A(A[5]), .B(B[4]), .Sin(wmfs63), .Cin(wmfc53));
MFA mfa64(.Sum(wmfs64), .Cout(wmfc64), .A(A[6]), .B(B[4]), .Sin(wn73), .Cin(wmfc63));
nand n74(wn74, A[7], B[4]);
//Row b5
MFA mfa05(.Sum(P[5]), .Cout(wmfc05), .A(A[0]), .B(B[5]), .Sin(wmfs14), .Cin(wmfc04));
MFA mfa15(.Sum(wmfs15), .Cout(wmfc15), .A(A[1]), .B(B[5]), .Sin(wmfs24), .Cin(wmfc14));
MFA mfa25(.Sum(wmfs25), .Cout(wmfc25), .A(A[2]), .B(B[5]), .Sin(wmfs34), .Cin(wmfc24));
MFA mfa35(.Sum(wmfs35), .Cout(wmfc35), .A(A[3]), .B(B[5]), .Sin(wmfs44), .Cin(wmfc34));
MFA mfa45(.Sum(wmfs45), .Cout(wmfc45), .A(A[4]), .B(B[5]), .Sin(wmfs54), .Cin(wmfc44));
MFA mfa55(.Sum(wmfs55), .Cout(wmfc55), .A(A[5]), .B(B[5]), .Sin(wmfs64), .Cin(wmfc54));
MFA mfa65(.Sum(wmfs65), .Cout(wmfc65), .A(A[6]), .B(B[5]), .Sin(wn74), .Cin(wmfc64));
nand n75(wn75, A[7], B[5]);
//Row b6
MFA mfa06(.Sum(P[6]), .Cout(wmfc06), .A(A[0]), .B(B[6]), .Sin(wmfs15), .Cin(wmfc05));
MFA mfa16(.Sum(wmfs16), .Cout(wmfc16), .A(A[1]), .B(B[6]), .Sin(wmfs25), .Cin(wmfc15));
MFA mfa26(.Sum(wmfs26), .Cout(wmfc26), .A(A[2]), .B(B[6]), .Sin(wmfs35), .Cin(wmfc25));
MFA mfa36(.Sum(wmfs36), .Cout(wmfc36), .A(A[3]), .B(B[6]), .Sin(wmfs45), .Cin(wmfc35));
MFA mfa46(.Sum(wmfs46), .Cout(wmfc46), .A(A[4]), .B(B[6]), .Sin(wmfs55), .Cin(wmfc45));
MFA mfa56(.Sum(wmfs56), .Cout(wmfc56), .A(A[5]), .B(B[6]), .Sin(wmfs65), .Cin(wmfc55));
MFA mfa66(.Sum(wmfs66), .Cout(wmfc66), .A(A[6]), .B(B[6]), .Sin(wn75), .Cin(wmfc65));
nand n76(wn76, A[7], B[6]);
//Row b7
NMFA nmfa07(.Sum(P[7]), .Cout(wnmfc07), .A(A[0]), .B(B[7]), .Sin(wmfs16), .Cin(wmfc06));
NMFA nmfa17(.Sum(wnmfs17), .Cout(wnmfc17), .A(A[1]), .B(B[7]), .Sin(wmfs26), .Cin(wmfc16));
NMFA nmfa27(.Sum(wnmfs27), .Cout(wnmfc27), .A(A[2]), .B(B[7]), .Sin(wmfs36), .Cin(wmfc26));
NMFA nmfa37(.Sum(wnmfs37), .Cout(wnmfc37), .A(A[3]), .B(B[7]), .Sin(wmfs46), .Cin(wmfc36));
NMFA nmfa47(.Sum(wnmfs47), .Cout(wnmfc47), .A(A[4]), .B(B[7]), .Sin(wmfs56), .Cin(wmfc46));
NMFA nmfa57(.Sum(wnmfs57), .Cout(wnmfc57), .A(A[5]), .B(B[7]), .Sin(wmfs66), .Cin(wmfc56));
NMFA nmfa67(.Sum(wnmfs67), .Cout(wnmfc67), .A(A[6]), .B(B[7]), .Sin(wn76), .Cin(wmfc66));
and a77(wa77, A[7], B[7]);
//Row b8
FA fa08(.Sum(P[8]), .Cout(wfac08), .A(wnmfc07), .B(wnmfs17), .Cin(1'b1));
FA fa18(.Sum(P[9]), .Cout(wfac18), .A(wnmfc17), .B(wnmfs27), .Cin(wfac08));
FA fa28(.Sum(P[10]), .Cout(wfac28), .A(wnmfc27), .B(wnmfs37), .Cin(wfac18));
FA fa38(.Sum(P[11]), .Cout(wfac38), .A(wnmfc37), .B(wnmfs47), .Cin(wfac28));
FA fa48(.Sum(P[12]), .Cout(wfac48), .A(wnmfc47), .B(wnmfs57), .Cin(wfac38));
FA fa58(.Sum(P[13]), .Cout(wfac58), .A(wnmfc57), .B(wnmfs67), .Cin(wfac48));
FA fa68(.Sum(P[14]), .Cout(wfac68), .A(wnmfc67), .B(wa77), .Cin(wfac58));
not inv1(P[15], wfac68);
endmodule // multi
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_1_V
`define SKY130_FD_SC_HVL__SDFRBP_1_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_PP_SYMBOL_V
`define SKY130_FD_SC_LP__FILL_PP_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fill (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_PP_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Tue Nov 8 02:24:52 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
input [1:0] r_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_B_1_, intDX_63_, intAS, sign_final_result,
Exp_Operation_Module_Data_S_8_, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1493, n1494, n1496, n1497, n1499, n1500, n1501, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1515, n1517,
n1518, n1519, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1675, n1676, n1677, n1678,
n1679, n1680, n1682, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1772, n1773,
n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783,
n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793,
n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803,
n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813,
n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823,
n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833,
n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843,
n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913,
n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923,
n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953,
n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2443, n2444, n2445, n2446,
n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456,
n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466,
n2467, n2468, n2469, n2470, n2471, n2472, n2475, n2476, n2477, n2478,
n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488,
n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498,
n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508,
n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518,
n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528,
n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538,
n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548,
n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558,
n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568,
n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578,
n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588,
n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598,
n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608,
n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618,
n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628,
n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638,
n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648,
n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658,
n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668,
n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678,
n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688,
n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698,
n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708,
n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718,
n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728,
n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738,
n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748,
n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758,
n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768,
n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778,
n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798,
n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808,
n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818,
n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828,
n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838,
n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848,
n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858,
n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868,
n2869, n2870, n2871, n2872, n2873, n2874, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3459, n3460, n3461, n3462,
n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472,
n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482,
n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492,
n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502,
n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512,
n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522,
n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532,
n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542,
n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552,
n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562,
n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572,
n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582,
n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592,
n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602,
n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612,
n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622,
n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632,
n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642,
n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755,
n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765,
n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775,
n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785,
n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795,
n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035,
n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045,
n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105,
n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115,
n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125,
n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135,
n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145,
n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155,
n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165,
n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175,
n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185,
n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195,
n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205,
n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215,
n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225,
n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235,
n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245,
n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255,
n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265,
n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275,
n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285,
n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295,
n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305,
n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315,
n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325,
n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335,
n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345,
n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355,
n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365,
n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375,
n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385,
n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395,
n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405,
n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415,
n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425,
n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435,
n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445,
n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455,
n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465,
n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475,
n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485,
n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495,
n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505,
n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515,
n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525,
n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535,
n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545,
n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555,
n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565,
n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575,
n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585,
n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595,
n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605,
n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615,
n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625,
n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635,
n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645,
n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655,
n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665,
n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675,
n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685,
n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695,
n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705,
n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715,
n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725,
n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735,
n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745,
n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755, n5756,
n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765, n5766,
n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775, n5776,
n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785, n5786,
n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795, n5796,
n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805, n5806,
n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815, n5816,
n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826,
n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835, n5836,
n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845, n5846,
n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855, n5856,
n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865, n5866,
n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875, n5876,
n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885, n5886,
n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895, n5896,
n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905, n5906,
n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915, n5916,
n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, n5926,
n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935, n5936,
n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945, n5946,
n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955, n5956,
n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965, n5966,
n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975, n5976,
n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, n5986,
n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995, n5996,
n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005, n6006,
n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015, n6016,
n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025, n6026,
n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035, n6036,
n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045, n6046,
n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055, n6056,
n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065, n6066,
n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075, n6076,
n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085, n6086,
n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095, n6096,
n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, n6106,
n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, n6116,
n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, n6126,
n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, n6136,
n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, n6146,
n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, n6156,
n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, n6166,
n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, n6176,
n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, n6186,
n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, n6196,
n6197, n6200, n6201, n6202, n6203, n6204, n6205, n6206, n6207, n6208,
n6209, n6210, n6211, n6212, n6213, n6214, n6215, n6216, n6217, n6218,
n6219, n6220, n6221, n6222, n6223, n6224, n6225, n6226, n6227, n6228,
n6229, n6230, n6231, n6232, n6233, n6234, n6235, n6236, n6237, n6238,
n6239, n6240, n6241, n6242, n6243, n6244, n6245, n6246, n6247, n6248,
n6249, n6250, n6251, n6252, n6254, n6255, n6256, n6257, n6258, n6259,
n6260, n6261, n6262, n6263, n6264, n6265, n6266, n6267, n6268, n6269,
n6270, n6271, n6272, n6273, n6274, n6275, n6276, n6277, n6278, n6279,
n6280, n6281, n6282, n6283, n6284, n6285, n6286, n6287, n6288, n6289,
n6290, n6291, n6292, n6293, n6294, n6295, n6296, n6297, n6298, n6299,
n6300, n6301, n6302, n6303, n6304, n6305, n6306, n6307, n6308, n6309,
n6310, n6311, n6312, n6313, n6314, n6315, n6316, n6317, n6318, n6319,
n6320, n6321, n6322, n6323, n6324, n6325, n6326, n6327, n6328, n6329,
n6330, n6331, n6332, n6333, n6334, n6335, n6336, n6337, n6338, n6339,
n6340, n6341, n6342, n6343, n6344, n6345, n6346, n6347, n6348, n6349,
n6350, n6351, n6352, n6353, n6354, n6355, n6356, n6357, n6358, n6359,
n6360, n6361, n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369,
n6370, n6371, n6372, n6373, n6374, n6375, n6376, n6377, n6378, n6379,
n6380, n6381, n6382, n6383, n6384, n6385, n6386, n6387, n6388, n6389,
n6390, n6391, n6392, n6393, n6394, n6395, n6396, n6397, n6398, n6399,
n6400, n6401, n6402, n6403, n6404, n6405, n6406, n6407, n6408, n6409,
n6410, n6411, n6412, n6413, n6414, n6415, n6416, n6417, n6418, n6419,
n6420, n6421, n6422, n6423, n6424, n6425, n6426, n6427, n6428, n6429,
n6430, n6431, n6432, n6433, n6434, n6435, n6436, n6437, n6438, n6439,
n6440, n6441, n6442, n6443, n6444, n6445, n6446, n6447, n6448, n6449,
n6450, n6451, n6452, n6453, n6454, n6455, n6456, n6457, n6458, n6459,
n6460, n6461, n6462, n6463, n6464, n6465, n6466, n6467, n6468, n6469,
n6470, n6471, n6472, n6473, n6474, n6475, n6476, n6477, n6478, n6479,
n6480, n6481, n6482, n6483, n6484, n6485, n6486, n6487, n6488, n6489,
n6490, n6491, n6492, n6493, n6494, n6495, n6496, n6497, n6498, n6499,
n6500, n6501, n6502, n6503, n6504, n6505, n6506, n6507, n6508, n6509,
n6510, n6511, n6512, n6513, n6514, n6515, n6516, n6517, n6518, n6519,
n6520, n6521, n6522, n6523, n6524, n6525, n6526, n6527, n6528, n6529,
n6530, n6531, n6532, n6533, n6534, n6535, n6536, n6537, n6538, n6539,
n6540, n6541, n6542, n6543, n6544, n6547;
wire [63:45] intDY;
wire [56:8] DMP;
wire [62:5] DmP;
wire [7:0] exp_oper_result;
wire [16:0] Add_Subt_result;
wire [54:0] Sgf_normalized_result;
wire [106:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1442), .CK(clk),
.RN(n6547), .Q(Sgf_normalized_result[0]), .QN(n6234) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n1511), .CK(clk),
.RN(n6413), .Q(Add_Subt_result[8]), .QN(n6257) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n1510), .CK(clk),
.RN(n6420), .Q(Add_Subt_result[7]), .QN(n6236) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n1506), .CK(clk),
.RN(n6435), .Q(Add_Subt_result[3]), .QN(n6235) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1438), .CK(clk),
.RN(n6420), .Q(exp_oper_result[0]), .QN(n6200) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .CK(clk), .RN(n6424),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[100]), .QN(n6239) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .CK(clk), .RN(n6426),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[98]), .QN(n6250) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .CK(clk), .RN(n6427),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[97]), .QN(n6249) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .CK(clk), .RN(n6428),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[96]), .QN(n6248) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .CK(clk), .RN(n6432),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[95]), .QN(n6247) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .CK(clk), .RN(n6423),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[93]), .QN(n6252) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .CK(clk), .RN(n6424),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[92]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .CK(clk), .RN(n6427),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[88]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .CK(clk), .RN(n6431),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[87]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .CK(clk), .RN(n6422),
.QN(n2484) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .CK(clk), .RN(n6424),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .CK(clk), .RN(n6425),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .CK(clk), .RN(n6426),
.QN(n2578) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .CK(clk), .RN(n6427),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .CK(clk), .RN(n6430),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[81]), .QN(n2419) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n6424),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n6424),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n6425),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .CK(clk), .RN(n6431),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[103]), .QN(n6241) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[52]), .CK(clk), .RN(n6428),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[104]), .QN(n6243) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .CK(clk), .RN(n6424),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[101]), .QN(n6245) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n1485), .CK(clk),
.RN(n6422), .Q(Sgf_normalized_result[43]), .QN(n6232) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n1487), .CK(clk),
.RN(n6422), .Q(Sgf_normalized_result[45]), .QN(n6219) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n1483), .CK(clk),
.RN(n6421), .Q(Sgf_normalized_result[41]), .QN(n6231) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n1482), .CK(clk),
.RN(n6421), .Q(Sgf_normalized_result[40]), .QN(n6220) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1464), .CK(clk),
.RN(n6417), .Q(Sgf_normalized_result[22]), .QN(n6230) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n1481), .CK(clk),
.RN(n6421), .Q(Sgf_normalized_result[39]), .QN(n6218) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n1490), .CK(clk),
.RN(n6424), .Q(Sgf_normalized_result[48]), .QN(n6206) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n1491), .CK(clk),
.RN(n6425), .Q(Sgf_normalized_result[49]), .QN(n6215) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n1494), .CK(clk),
.RN(n6428), .Q(Sgf_normalized_result[52]), .QN(n6205) );
DFFRX4TS XRegister_Q_reg_63_ ( .D(n1296), .CK(clk), .RN(n6449), .Q(intDX_63_), .QN(n6233) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n1214), .CK(clk),
.RN(n6424), .Q(DMP[45]) );
DFFRX4TS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1167), .CK(clk),
.RN(n6270), .Q(sign_final_result), .QN(n6256) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1131), .CK(clk),
.RN(n6430), .Q(DmP[26]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1130), .CK(clk),
.RN(n6430), .Q(DmP[25]) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n1480), .CK(clk),
.RN(n6421), .Q(Sgf_normalized_result[38]), .QN(n6225) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n1486), .CK(clk),
.RN(n6422), .Q(Sgf_normalized_result[44]), .QN(n6217) );
DFFSX4TS R_14 ( .D(n6478), .CK(clk), .SN(n6269), .Q(n6389) );
DFFSX4TS R_17 ( .D(n6469), .CK(clk), .SN(n6436), .Q(n6386) );
DFFSX4TS R_23 ( .D(n6475), .CK(clk), .SN(n2736), .Q(n6380) );
DFFSX4TS R_26 ( .D(n6481), .CK(clk), .SN(n2737), .Q(n6377) );
DFFSX4TS R_29 ( .D(n6484), .CK(clk), .SN(n6264), .Q(n6374) );
DFFSX4TS R_45 ( .D(n6400), .CK(clk), .SN(n6270), .Q(n6371) );
DFFSX4TS R_48 ( .D(n2733), .CK(clk), .SN(n6270), .Q(n6368) );
DFFSX4TS R_51 ( .D(n2733), .CK(clk), .SN(n6271), .Q(n6365) );
DFFSX4TS R_57 ( .D(n2733), .CK(clk), .SN(n6262), .Q(n6360) );
DFFSX4TS R_56 ( .D(n2508), .CK(clk), .SN(n6262), .Q(n6361) );
DFFSX4TS R_55 ( .D(n6530), .CK(clk), .SN(n6262), .QN(n2546) );
DFFSX4TS R_59 ( .D(n2529), .CK(clk), .SN(n6263), .Q(n6359) );
DFFSX4TS R_60 ( .D(n2733), .CK(clk), .SN(n6263), .Q(n6358) );
DFFSX4TS R_62 ( .D(n6401), .CK(clk), .SN(n6263), .Q(n6357) );
DFFSX4TS R_63 ( .D(n2733), .CK(clk), .SN(n6263), .Q(n6356) );
DFFRX4TS R_65 ( .D(n1430), .CK(clk), .RN(n6434), .Q(n6354) );
DFFSX4TS R_69 ( .D(n2733), .CK(clk), .SN(n6414), .Q(n6351) );
DFFSX4TS R_68 ( .D(n3501), .CK(clk), .SN(n6438), .Q(n6352) );
DFFSX4TS R_75 ( .D(n2733), .CK(clk), .SN(n6272), .Q(n6345) );
DFFSX2TS R_77 ( .D(n6404), .CK(clk), .SN(n6270), .Q(n6343) );
DFFSX2TS R_76 ( .D(n6460), .CK(clk), .SN(n6272), .Q(n6344) );
DFFSX4TS R_81 ( .D(n2733), .CK(clk), .SN(n2764), .Q(n6340), .QN(n2269) );
DFFSX4TS R_84 ( .D(n6400), .CK(clk), .SN(n6438), .Q(n6337) );
DFFSX4TS R_83 ( .D(n2509), .CK(clk), .SN(n2721), .Q(n6338) );
DFFSX4TS R_82 ( .D(n6538), .CK(clk), .SN(n2764), .Q(n6339) );
DFFSX4TS R_87 ( .D(n2733), .CK(clk), .SN(n6262), .Q(n6334) );
DFFSX4TS R_94 ( .D(n6533), .CK(clk), .SN(n2764), .Q(n6330) );
DFFSX4TS R_95 ( .D(n6009), .CK(clk), .SN(n2764), .Q(n6329) );
DFFSX4TS R_97 ( .D(n6536), .CK(clk), .SN(n2764), .Q(n6327) );
DFFSX4TS R_98 ( .D(n6063), .CK(clk), .SN(n2764), .Q(n6326) );
DFFSX4TS R_104 ( .D(n6523), .CK(clk), .SN(n6264), .Q(n6320) );
DFFSX4TS R_113 ( .D(n6466), .CK(clk), .SN(n6264), .Q(n6311) );
DFFSX4TS R_137 ( .D(n6463), .CK(clk), .SN(n6268), .Q(n6287) );
DFFSX4TS R_143 ( .D(n6487), .CK(clk), .SN(n6269), .Q(n6281) );
DFFSX4TS R_152 ( .D(n6528), .CK(clk), .SN(n6269), .QN(n2544) );
DFFSX4TS R_153 ( .D(n3499), .CK(clk), .SN(n6263), .Q(n6277) );
DFFSX4TS R_154 ( .D(n6400), .CK(clk), .SN(n6268), .Q(n6276) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n1410),
.CK(clk), .RN(n6412), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n1409),
.CK(clk), .RN(n6412), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1408),
.CK(clk), .RN(n6412), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n1405),
.CK(clk), .RN(n6412), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n1398),
.CK(clk), .RN(n6272), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n1397),
.CK(clk), .RN(n6272), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n1396),
.CK(clk), .RN(n6272), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n1395),
.CK(clk), .RN(n6268), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n1394),
.CK(clk), .RN(n6269), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n1393),
.CK(clk), .RN(n4871), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n1392),
.CK(clk), .RN(n4869), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n1391),
.CK(clk), .RN(n4868), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n1384),
.CK(clk), .RN(n6411), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n1383),
.CK(clk), .RN(n6411), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n1382),
.CK(clk), .RN(n6411), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n1381),
.CK(clk), .RN(n6411), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n1380),
.CK(clk), .RN(n6410), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n1379),
.CK(clk), .RN(n6410), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n1377),
.CK(clk), .RN(n6410), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n1376),
.CK(clk), .RN(n6410), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n1370),
.CK(clk), .RN(n6409), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n1369),
.CK(clk), .RN(n6409), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n1367),
.CK(clk), .RN(n6409), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n1366),
.CK(clk), .RN(n6409), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n1365),
.CK(clk), .RN(n6409), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n1364),
.CK(clk), .RN(n6409), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n1363),
.CK(clk), .RN(n6409), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n1423),
.CK(clk), .RN(n6408), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n1422),
.CK(clk), .RN(n6408), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n1421),
.CK(clk), .RN(n6408), .Q(final_result_ieee[56]) );
DFFSX2TS R_9 ( .D(n6539), .CK(clk), .SN(n2728), .Q(n6392) );
DFFSX1TS R_7 ( .D(n6541), .CK(clk), .SN(n2728), .Q(n6394) );
DFFSX2TS R_88 ( .D(n2056), .CK(clk), .SN(n6437), .Q(n6333) );
DFFSX2TS R_71 ( .D(n6403), .CK(clk), .SN(n6271), .Q(n6349) );
DFFSX2TS R_93 ( .D(n6534), .CK(clk), .SN(n2764), .Q(n6331) );
DFFSX2TS R_96 ( .D(n6535), .CK(clk), .SN(n2764), .Q(n6328) );
DFFSX1TS R_19 ( .D(n6473), .CK(clk), .SN(n2737), .Q(n6384) );
DFFSX2TS R_106 ( .D(n6491), .CK(clk), .SN(n6267), .Q(n6318) );
DFFSX2TS R_112 ( .D(n6467), .CK(clk), .SN(n6268), .Q(n6312) );
DFFSX2TS R_115 ( .D(n6497), .CK(clk), .SN(n6267), .Q(n6309) );
DFFSX2TS R_118 ( .D(n6518), .CK(clk), .SN(n6266), .Q(n6306) );
DFFSX2TS R_130 ( .D(n6506), .CK(clk), .SN(n6266), .Q(n6294) );
DFFSX2TS R_133 ( .D(n6494), .CK(clk), .SN(n6265), .Q(n6291) );
DFFSX2TS R_139 ( .D(n6509), .CK(clk), .SN(n6265), .Q(n6285) );
DFFSX2TS R_145 ( .D(n6515), .CK(clk), .SN(n6265), .Q(n6279) );
DFFSX1TS R_18 ( .D(n6474), .CK(clk), .SN(n6450), .Q(n6385) );
DFFSX2TS R_99 ( .D(n6513), .CK(clk), .SN(n6267), .Q(n6325) );
DFFSX2TS R_105 ( .D(n6492), .CK(clk), .SN(n6267), .Q(n6319) );
DFFSX2TS R_114 ( .D(n6498), .CK(clk), .SN(n6266), .Q(n6310) );
DFFSX2TS R_117 ( .D(n6519), .CK(clk), .SN(n6266), .Q(n6307) );
DFFSX2TS R_129 ( .D(n6507), .CK(clk), .SN(n6265), .Q(n6295) );
DFFSX2TS R_138 ( .D(n6510), .CK(clk), .SN(n6265), .Q(n6286) );
DFFSX2TS R_144 ( .D(n6516), .CK(clk), .SN(n6265), .Q(n6280) );
DFFSX2TS R_119 ( .D(n6517), .CK(clk), .SN(n6266), .Q(n6305) );
DFFSX2TS R_131 ( .D(n6505), .CK(clk), .SN(n6266), .Q(n6293) );
DFFSX2TS R_134 ( .D(n6493), .CK(clk), .SN(n6265), .Q(n6290) );
DFFSX2TS R_146 ( .D(n6514), .CK(clk), .SN(n6265), .Q(n6278) );
DFFSX2TS R_43 ( .D(n6461), .CK(clk), .SN(n6270), .Q(n6373) );
DFFSX2TS R_16 ( .D(n6470), .CK(clk), .SN(n6449), .Q(n6387) );
DFFSX2TS R_13 ( .D(n6479), .CK(clk), .SN(n6450), .Q(n6390) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n1468), .CK(clk),
.RN(n6418), .Q(Sgf_normalized_result[26]), .QN(n6229) );
DFFSX2TS R_47 ( .D(n3500), .CK(clk), .SN(n6270), .Q(n6369) );
DFFSX2TS R_103 ( .D(n6524), .CK(clk), .SN(n6263), .Q(n6321) );
DFFSX2TS R_102 ( .D(n6525), .CK(clk), .SN(n6268), .Q(n6322) );
DFFSX2TS R_46 ( .D(n6459), .CK(clk), .SN(n6270), .Q(n6370) );
DFFRHQX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n1412),
.CK(clk), .RN(n2736), .Q(final_result_ieee[2]) );
DFFRHQX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n1361),
.CK(clk), .RN(n2737), .Q(final_result_ieee[63]) );
DFFSX4TS R_6 ( .D(n6542), .CK(clk), .SN(n6420), .Q(n6395) );
DFFRHQX8TS YRegister_Q_reg_45_ ( .D(n1277), .CK(clk), .RN(n6438), .Q(
intDY[45]) );
DFFRHQX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n1503), .CK(clk), .RN(n2736), .Q(Add_Subt_result[0]) );
DFFRX2TS R_89 ( .D(n1429), .CK(clk), .RN(n6420), .Q(n6332) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n1144), .CK(clk),
.RN(n6431), .Q(DmP[39]), .QN(n2121) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n1139), .CK(clk),
.RN(n6431), .Q(DmP[34]) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n1136), .CK(clk),
.RN(n6430), .Q(DmP[31]) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1117), .CK(clk),
.RN(n6429), .Q(DmP[12]) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1116), .CK(clk),
.RN(n6429), .Q(DmP[11]), .QN(n1922) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n6426),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n6424),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n6423),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n6426),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n6429),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFSX4TS R_116 ( .D(n6496), .CK(clk), .SN(n6266), .Q(n6308) );
DFFRHQX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n1504), .CK(clk), .RN(n6438), .Q(Add_Subt_result[1]) );
DFFRHQX8TS Sel_B_Q_reg_1_ ( .D(n1439), .CK(clk), .RN(n1360), .Q(
FSM_selector_B_1_) );
DFFRHQX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n1518), .CK(
clk), .RN(n2737), .Q(Add_Subt_result[15]) );
DFFRHQX8TS R_91_IP ( .D(n1441), .CK(clk), .RN(n1360), .Q(n6451) );
DFFSX4TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n2531), .CK(clk),
.SN(n2721), .Q(n6204), .QN(Sgf_normalized_result[50]) );
DFFSX2TS R_136 ( .D(n6464), .CK(clk), .SN(n6264), .Q(n6288) );
DFFSX2TS R_111 ( .D(n6468), .CK(clk), .SN(n6269), .Q(n6313) );
DFFSX2TS R_135 ( .D(n6465), .CK(clk), .SN(n6268), .Q(n6289) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n1213), .CK(clk),
.RN(n6423), .Q(DMP[44]), .QN(n6207) );
DFFSX2TS R_142 ( .D(n6488), .CK(clk), .SN(n6426), .Q(n6282) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1435), .CK(clk),
.RN(n6437), .Q(exp_oper_result[3]), .QN(n6210) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1191), .CK(clk),
.RN(n6418), .Q(DMP[22]), .QN(n6216) );
DFFSX2TS R_25 ( .D(n6482), .CK(clk), .SN(n6264), .Q(n6378) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n1517), .CK(clk),
.RN(n6434), .Q(Add_Subt_result[14]), .QN(n6223) );
DFFSX4TS R_164 ( .D(n6399), .CK(clk), .SN(n6262), .Q(n6274) );
DFFSX2TS R_86 ( .D(n3497), .CK(clk), .SN(n6262), .Q(n6335) );
DFFSX2TS R_28 ( .D(n6485), .CK(clk), .SN(n6264), .Q(n6375) );
DFFSX2TS R_141 ( .D(n6489), .CK(clk), .SN(n6269), .Q(n6283) );
DFFSX4TS R_165 ( .D(n6400), .CK(clk), .SN(n6262), .Q(n6273) );
DFFSX4TS R_50 ( .D(n3496), .CK(clk), .SN(n6271), .Q(n6366) );
DFFSX2TS R_85 ( .D(n6527), .CK(clk), .SN(n6263), .Q(n6336) );
DFFSX4TS R_72 ( .D(n6400), .CK(clk), .SN(n6271), .Q(n6348) );
DFFSX2TS R_22 ( .D(n6476), .CK(clk), .SN(n6268), .Q(n6381) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1436), .CK(clk),
.RN(n6435), .Q(exp_oper_result[2]), .QN(n6203) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1437), .CK(clk),
.RN(n6436), .Q(exp_oper_result[1]), .QN(n6211) );
DFFSX2TS R_12 ( .D(n6480), .CK(clk), .SN(n6269), .Q(n6391) );
DFFSX2TS R_24 ( .D(n6483), .CK(clk), .SN(n6425), .Q(n6379) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n1505), .CK(clk),
.RN(n2728), .Q(Add_Subt_result[2]), .QN(n6238) );
DFFSX4TS R_101 ( .D(n6511), .CK(clk), .SN(n6267), .Q(n6323) );
DFFSX4TS R_140 ( .D(n6508), .CK(clk), .SN(n6265), .Q(n6284) );
DFFSX4TS R_80 ( .D(n2507), .CK(clk), .SN(n2728), .Q(n6341) );
DFFSX2TS R_27 ( .D(n6486), .CK(clk), .SN(n6264), .Q(n6376) );
DFFSX2TS R_121 ( .D(n6521), .CK(clk), .SN(n2736), .Q(n6303) );
DFFSX2TS R_124 ( .D(n6453), .CK(clk), .SN(n6272), .Q(n6300) );
DFFSX4TS R_78 ( .D(n6400), .CK(clk), .SN(n6270), .Q(n6342) );
DFFSX2TS R_21 ( .D(n6477), .CK(clk), .SN(n6269), .Q(n6382) );
DFFSX2TS R_15 ( .D(n6471), .CK(clk), .SN(n2737), .Q(n6388) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1190), .CK(clk),
.RN(n6418), .Q(DMP[21]) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n1472), .CK(clk),
.RN(n6419), .Q(Sgf_normalized_result[30]), .QN(n6227) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n1470), .CK(clk),
.RN(n6419), .Q(Sgf_normalized_result[28]), .QN(n6228) );
DFFRX4TS ASRegister_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n2744), .Q(intAS),
.QN(n6259) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n6425),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n6423),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n6422),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n1147), .CK(clk),
.RN(n6432), .Q(DmP[42]) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1432), .CK(clk),
.RN(n6413), .Q(exp_oper_result[6]), .QN(n6201) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1434), .CK(clk),
.RN(n6435), .Q(exp_oper_result[4]), .QN(n6202) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n1414),
.CK(clk), .RN(n6435), .Q(final_result_ieee[0]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n1411),
.CK(clk), .RN(n6437), .Q(final_result_ieee[3]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n1413),
.CK(clk), .RN(n6434), .Q(final_result_ieee[1]) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1183), .CK(clk),
.RN(n6416), .Q(DMP[14]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n6428),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .CK(clk), .RN(n6427),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[89]) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n1493), .CK(clk),
.RN(n6427), .Q(Sgf_normalized_result[51]), .QN(n6214) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n6427),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n1390),
.CK(clk), .RN(n6411), .Q(final_result_ieee[24]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n1389),
.CK(clk), .RN(n6411), .Q(final_result_ieee[25]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n1388),
.CK(clk), .RN(n6411), .Q(final_result_ieee[26]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n1387),
.CK(clk), .RN(n6411), .Q(final_result_ieee[27]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n1386),
.CK(clk), .RN(n6411), .Q(final_result_ieee[28]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n1385),
.CK(clk), .RN(n6411), .Q(final_result_ieee[29]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1407),
.CK(clk), .RN(n6412), .Q(final_result_ieee[7]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n1406),
.CK(clk), .RN(n6412), .Q(final_result_ieee[8]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n1404),
.CK(clk), .RN(n6412), .Q(final_result_ieee[10]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n1403),
.CK(clk), .RN(n6412), .Q(final_result_ieee[11]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n1402),
.CK(clk), .RN(n6412), .Q(final_result_ieee[12]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n1401),
.CK(clk), .RN(n6412), .Q(final_result_ieee[13]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n1368),
.CK(clk), .RN(n6409), .Q(final_result_ieee[46]) );
DFFRX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n1424),
.CK(clk), .RN(n6409), .Q(final_result_ieee[53]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n1425),
.CK(clk), .RN(n6409), .Q(final_result_ieee[52]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n1375),
.CK(clk), .RN(n6410), .Q(final_result_ieee[39]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n1374),
.CK(clk), .RN(n6410), .Q(final_result_ieee[40]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n1373),
.CK(clk), .RN(n6410), .Q(final_result_ieee[41]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n1372),
.CK(clk), .RN(n6410), .Q(final_result_ieee[42]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n1371),
.CK(clk), .RN(n6410), .Q(final_result_ieee[43]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n1378),
.CK(clk), .RN(n6410), .Q(final_result_ieee[36]) );
DFFSX2TS R_44 ( .D(n2506), .CK(clk), .SN(n6270), .Q(n6372) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n6425),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .CK(clk), .RN(n6425),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[99]), .QN(n6251) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .CK(clk), .RN(n6425),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[102]), .QN(n6240) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .CK(clk), .RN(n6426),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n6426),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n6426),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFSX2TS R_123 ( .D(n6454), .CK(clk), .SN(n6271), .Q(n6301) );
DFFSX2TS R_125 ( .D(n6452), .CK(clk), .SN(n6271), .Q(n6299) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n1420),
.CK(clk), .RN(n6408), .Q(final_result_ieee[57]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n1419),
.CK(clk), .RN(n6408), .Q(final_result_ieee[58]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n1418),
.CK(clk), .RN(n6408), .Q(final_result_ieee[59]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n1417),
.CK(clk), .RN(n6408), .Q(final_result_ieee[60]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n1416),
.CK(clk), .RN(n6408), .Q(final_result_ieee[61]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n1415),
.CK(clk), .RN(n6408), .Q(final_result_ieee[62]) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n1508), .CK(clk),
.RN(n6414), .Q(Add_Subt_result[5]), .QN(n6221) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n1157), .CK(clk),
.RN(n6429), .Q(DmP[52]), .QN(n1957) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1433), .CK(clk),
.RN(n6262), .Q(exp_oper_result[5]), .QN(n6208) );
DFFRX4TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n6422),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFSX4TS R_54 ( .D(n6400), .CK(clk), .SN(n6271), .Q(n6362) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n6547),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(n1563), .CK(clk),
.RN(n6547), .Q(Sgf_normalized_result[54]), .QN(n6226) );
DFFRX4TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n6547),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFSX2TS R_122 ( .D(n6520), .CK(clk), .SN(n6441), .Q(n6302) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n1399),
.CK(clk), .RN(n2721), .Q(final_result_ieee[15]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n1400),
.CK(clk), .RN(n4870), .Q(final_result_ieee[14]) );
DFFSX4TS R_107 ( .D(n6490), .CK(clk), .SN(n6267), .Q(n6317) );
DFFRHQX8TS R_40 ( .D(n1560), .CK(clk), .RN(n6433), .Q(n2714) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1123), .CK(clk),
.RN(n6420), .Q(DmP[18]) );
DFFSX2TS R_120 ( .D(n6522), .CK(clk), .SN(n6263), .Q(n6304) );
DFFRHQX8TS FS_Module_state_reg_reg_3_ ( .D(n1561), .CK(clk), .RN(n6435), .Q(
n2703) );
DFFRHQX8TS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1179), .CK(clk),
.RN(n6416), .Q(n2693) );
DFFSX4TS R_127 ( .D(n6503), .CK(clk), .SN(n6266), .Q(n6297) );
DFFRHQX8TS FS_Module_state_reg_reg_2_ ( .D(n1558), .CK(clk), .RN(n6437), .Q(
n2682) );
DFFRHQX8TS R_11 ( .D(n1441), .CK(clk), .RN(n1360), .Q(n2670) );
DFFRHQX8TS R_92 ( .D(n1441), .CK(clk), .RN(n6261), .Q(n2668) );
DFFSX4TS R_128 ( .D(n6502), .CK(clk), .SN(n6266), .Q(n6296) );
DFFRHQX8TS YRegister_Q_reg_7_ ( .D(n1239), .CK(clk), .RN(n2744), .Q(n2665)
);
DFFRHQX8TS XRegister_Q_reg_3_ ( .D(n1300), .CK(clk), .RN(n6443), .Q(n2660)
);
DFFRHQX8TS XRegister_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n6443), .Q(n2652)
);
DFFSX2TS R_70 ( .D(n6455), .CK(clk), .SN(n6272), .Q(n6350) );
DFFSX1TS R_132 ( .D(n6495), .CK(clk), .SN(n6265), .Q(n6292) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1119), .CK(clk),
.RN(n6429), .Q(DmP[14]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1120), .CK(clk),
.RN(n6430), .Q(DmP[15]) );
DFFRHQX8TS YRegister_Q_reg_3_ ( .D(n1235), .CK(clk), .RN(n2745), .Q(n2636)
);
DFFRHQX8TS R_161 ( .D(n1441), .CK(clk), .RN(n6261), .Q(n2633) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n1473), .CK(clk),
.RN(n6419), .Q(n2631) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1126), .CK(clk),
.RN(n2721), .Q(DmP[21]) );
DFFRHQX8TS R_151 ( .D(n1441), .CK(clk), .RN(n6261), .Q(n2629) );
DFFRHQX8TS YRegister_Q_reg_5_ ( .D(n1237), .CK(clk), .RN(n2744), .Q(n2626)
);
DFFSHQX8TS R_150 ( .D(n6398), .CK(clk), .SN(n1360), .Q(n2620) );
DFFSX2TS R_109 ( .D(n6500), .CK(clk), .SN(n6267), .Q(n6315) );
DFFSX4TS R_110 ( .D(n6499), .CK(clk), .SN(n6267), .Q(n6314) );
DFFRHQX8TS XRegister_Q_reg_2_ ( .D(n1299), .CK(clk), .RN(n6443), .Q(n2616)
);
DFFSX4TS R_49 ( .D(n6458), .CK(clk), .SN(n6271), .Q(n6367) );
DFFRHQX8TS XRegister_Q_reg_9_ ( .D(n1306), .CK(clk), .RN(n6444), .Q(n2610)
);
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .CK(clk), .RN(n6425),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[91]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n6427),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n6424),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n6423),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1461), .CK(clk),
.RN(n6417), .Q(n2470) );
DFFSX2TS R_67 ( .D(n6462), .CK(clk), .SN(n6268), .Q(n6353) );
DFFRHQX8TS R_162 ( .D(n1441), .CK(clk), .RN(n6261), .Q(n2467) );
DFFSHQX8TS R_33_IP ( .D(n6398), .CK(clk), .SN(n1360), .Q(n2465) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1449), .CK(clk),
.RN(n6436), .Q(n2463) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1447), .CK(clk),
.RN(n6413), .Q(n2461) );
DFFSX2TS R_79 ( .D(n6532), .CK(clk), .SN(n6436), .Q(n2268) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1446), .CK(clk),
.RN(n6414), .Q(n2450) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1445), .CK(clk),
.RN(n2728), .Q(n2441) );
DFFRHQX8TS YRegister_Q_reg_1_ ( .D(n1233), .CK(clk), .RN(n2745), .Q(n2439)
);
DFFRHQX8TS YRegister_Q_reg_2_ ( .D(n1234), .CK(clk), .RN(n2745), .Q(n2436)
);
DFFRHQX8TS XRegister_Q_reg_31_ ( .D(n1328), .CK(clk), .RN(n6446), .Q(n2434)
);
DFFRHQX8TS XRegister_Q_reg_5_ ( .D(n1302), .CK(clk), .RN(n6444), .Q(n2432)
);
DFFSHQX8TS R_10 ( .D(n6398), .CK(clk), .SN(n1360), .Q(n2427) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1459), .CK(clk),
.RN(n6416), .Q(n2425) );
DFFSHQX8TS R_41 ( .D(n6398), .CK(clk), .SN(n1360), .Q(n2422) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n1161), .CK(clk),
.RN(n6414), .Q(DmP[56]) );
DFFRHQX8TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1169), .CK(clk),
.RN(n6434), .Q(n2409) );
DFFRHQX8TS YRegister_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n6440), .Q(n2405)
);
DFFRHQX8TS YRegister_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n6415), .Q(n2403)
);
DFFRHQX8TS YRegister_Q_reg_34_ ( .D(n1266), .CK(clk), .RN(n6440), .Q(n2401)
);
DFFRHQX8TS YRegister_Q_reg_11_ ( .D(n1243), .CK(clk), .RN(n6450), .Q(n2399)
);
DFFRHQX8TS YRegister_Q_reg_55_ ( .D(n1287), .CK(clk), .RN(n6442), .Q(n2397)
);
DFFRHQX8TS YRegister_Q_reg_53_ ( .D(n1285), .CK(clk), .RN(n6442), .Q(n2395)
);
DFFRHQX8TS XRegister_Q_reg_42_ ( .D(n1339), .CK(clk), .RN(n6447), .Q(n2393)
);
DFFRHQX8TS YRegister_Q_reg_49_ ( .D(n1281), .CK(clk), .RN(n6442), .Q(n2391)
);
DFFRHQX8TS XRegister_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n6444), .Q(n2389)
);
DFFRHQX8TS YRegister_Q_reg_8_ ( .D(n1240), .CK(clk), .RN(n6450), .Q(n2387)
);
DFFRHQX8TS XRegister_Q_reg_37_ ( .D(n1334), .CK(clk), .RN(n6447), .Q(n2384)
);
DFFRHQX8TS XRegister_Q_reg_6_ ( .D(n1303), .CK(clk), .RN(n6444), .Q(n2380)
);
DFFRHQX8TS XRegister_Q_reg_39_ ( .D(n1336), .CK(clk), .RN(n6447), .Q(n2378)
);
DFFRHQX8TS YRegister_Q_reg_35_ ( .D(n1267), .CK(clk), .RN(n6440), .Q(n2376)
);
DFFRHQX8TS XRegister_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n6445), .Q(n2374)
);
DFFRHQX8TS Sel_C_Q_reg_0_ ( .D(n1557), .CK(clk), .RN(n6261), .Q(n2372) );
DFFRHQX8TS XRegister_Q_reg_15_ ( .D(n1312), .CK(clk), .RN(n6445), .Q(n2369)
);
DFFRHQX8TS XRegister_Q_reg_36_ ( .D(n1333), .CK(clk), .RN(n6447), .Q(n2365)
);
DFFRHQX8TS XRegister_Q_reg_16_ ( .D(n1313), .CK(clk), .RN(n6445), .Q(n2363)
);
DFFRHQX8TS YRegister_Q_reg_44_ ( .D(n1276), .CK(clk), .RN(n6441), .Q(n2361)
);
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1129), .CK(clk),
.RN(n6430), .Q(DmP[24]) );
DFFSX2TS R_5 ( .D(n6543), .CK(clk), .SN(n6414), .Q(n6396) );
DFFRHQX8TS YRegister_Q_reg_9_ ( .D(n1241), .CK(clk), .RN(n6450), .Q(n2356)
);
DFFRHQX8TS YRegister_Q_reg_38_ ( .D(n1270), .CK(clk), .RN(n6441), .Q(n2354)
);
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1124), .CK(clk),
.RN(n2744), .Q(DmP[19]), .QN(n2349) );
DFFRHQX8TS YRegister_Q_reg_37_ ( .D(n1269), .CK(clk), .RN(n6440), .Q(n2343)
);
DFFSX2TS R_126 ( .D(n6504), .CK(clk), .SN(n6266), .Q(n6298) );
DFFRHQX8TS YRegister_Q_reg_51_ ( .D(n1283), .CK(clk), .RN(n6442), .Q(n2336)
);
DFFRHQX8TS YRegister_Q_reg_39_ ( .D(n1271), .CK(clk), .RN(n6441), .Q(n2334)
);
DFFSX2TS R_108 ( .D(n6501), .CK(clk), .SN(n6267), .Q(n6316) );
DFFRHQX8TS YRegister_Q_reg_27_ ( .D(n1259), .CK(clk), .RN(n6439), .Q(n2331)
);
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1188), .CK(clk),
.RN(n6417), .Q(n2330) );
DFFRHQX8TS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1193), .CK(clk),
.RN(n6418), .Q(n2326) );
DFFRHQX8TS YRegister_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n6442), .Q(n2321)
);
DFFRHQX8TS YRegister_Q_reg_41_ ( .D(n1273), .CK(clk), .RN(n6441), .Q(n2320)
);
DFFRHQX8TS Sel_B_Q_reg_0_ ( .D(n1440), .CK(clk), .RN(n1360), .Q(n2318) );
DFFRHQX8TS YRegister_Q_reg_25_ ( .D(n1257), .CK(clk), .RN(n6439), .Q(n2313)
);
DFFRHQX8TS YRegister_Q_reg_43_ ( .D(n1275), .CK(clk), .RN(n6441), .Q(n2311)
);
DFFRHQX8TS YRegister_Q_reg_42_ ( .D(n1274), .CK(clk), .RN(n6441), .Q(n2309)
);
DFFRHQX8TS YRegister_Q_reg_29_ ( .D(n1261), .CK(clk), .RN(n6440), .Q(n2304)
);
DFFRHQX8TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1170), .CK(clk),
.RN(n6437), .Q(n2295) );
DFFRHQX8TS YRegister_Q_reg_31_ ( .D(n1263), .CK(clk), .RN(n6440), .Q(n2293)
);
DFFRHQX8TS YRegister_Q_reg_14_ ( .D(n1246), .CK(clk), .RN(n6429), .Q(n2291)
);
DFFRHQX8TS YRegister_Q_reg_15_ ( .D(n1247), .CK(clk), .RN(n6268), .Q(n2287)
);
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1466), .CK(clk),
.RN(n6418), .Q(n2283) );
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n1515), .CK(clk),
.RN(n6434), .Q(Add_Subt_result[12]), .QN(n6237) );
DFFRHQX8TS YRegister_Q_reg_56_ ( .D(n1288), .CK(clk), .RN(n6442), .Q(n2265)
);
DFFRHQX8TS YRegister_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n6269), .Q(n2263)
);
DFFRHQX8TS YRegister_Q_reg_19_ ( .D(n1251), .CK(clk), .RN(n6439), .Q(n2260)
);
DFFRHQX8TS YRegister_Q_reg_50_ ( .D(n1282), .CK(clk), .RN(n6442), .Q(n2257)
);
DFFRHQX8TS YRegister_Q_reg_18_ ( .D(n1250), .CK(clk), .RN(n6439), .Q(n2255)
);
DFFRHQX8TS YRegister_Q_reg_30_ ( .D(n1262), .CK(clk), .RN(n6440), .Q(n2253)
);
DFFRHQX8TS XRegister_Q_reg_56_ ( .D(n1353), .CK(clk), .RN(n6449), .Q(n2251)
);
DFFRHQX8TS XRegister_Q_reg_43_ ( .D(n1340), .CK(clk), .RN(n6447), .Q(n2249)
);
DFFRHQX8TS XRegister_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n6449), .Q(n2247)
);
DFFRHQX8TS XRegister_Q_reg_28_ ( .D(n1325), .CK(clk), .RN(n6446), .Q(n2245)
);
DFFRHQX8TS XRegister_Q_reg_55_ ( .D(n1352), .CK(clk), .RN(n6449), .Q(n2243)
);
DFFRHQX8TS XRegister_Q_reg_38_ ( .D(n1335), .CK(clk), .RN(n6447), .Q(n2241)
);
DFFRHQX8TS XRegister_Q_reg_21_ ( .D(n1318), .CK(clk), .RN(n6445), .Q(n2239)
);
DFFRHQX4TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n1501),
.CK(clk), .RN(n6547), .Q(n2237) );
DFFRHQX8TS XRegister_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n6444), .Q(n2235)
);
DFFRHQX8TS YRegister_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n2744), .Q(n2232)
);
DFFRHQX8TS YRegister_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n2745), .Q(n2230)
);
DFFRHQX8TS XRegister_Q_reg_23_ ( .D(n1320), .CK(clk), .RN(n6445), .Q(n2227)
);
DFFRHQX8TS YRegister_Q_reg_52_ ( .D(n1284), .CK(clk), .RN(n6442), .Q(n2225)
);
DFFRHQX8TS YRegister_Q_reg_59_ ( .D(n1291), .CK(clk), .RN(n6443), .Q(n2223)
);
DFFRHQX8TS XRegister_Q_reg_27_ ( .D(n1324), .CK(clk), .RN(n6446), .Q(n2221)
);
DFFRHQX8TS XRegister_Q_reg_29_ ( .D(n1326), .CK(clk), .RN(n6446), .Q(n2219)
);
DFFRHQX8TS XRegister_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(n6445), .Q(n2217)
);
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1463), .CK(clk),
.RN(n6417), .Q(n2215) );
DFFRHQX8TS YRegister_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n6439), .Q(n2212)
);
DFFRHQX2TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n1499),
.CK(clk), .RN(n6408), .Q(n2209) );
DFFRHQX8TS YRegister_Q_reg_40_ ( .D(n1272), .CK(clk), .RN(n6441), .Q(n2207)
);
DFFRHQX8TS XRegister_Q_reg_51_ ( .D(n1348), .CK(clk), .RN(n6448), .Q(n2205)
);
DFFRHQX8TS XRegister_Q_reg_8_ ( .D(n1305), .CK(clk), .RN(n6444), .Q(n2202)
);
DFFRHQX8TS YRegister_Q_reg_61_ ( .D(n1293), .CK(clk), .RN(n6443), .Q(n2200)
);
DFFRHQX8TS XRegister_Q_reg_45_ ( .D(n1342), .CK(clk), .RN(n6448), .Q(n2196)
);
DFFRHQX8TS XRegister_Q_reg_57_ ( .D(n1354), .CK(clk), .RN(n6449), .Q(n2194)
);
DFFRHQX8TS XRegister_Q_reg_1_ ( .D(n1298), .CK(clk), .RN(n6443), .Q(n2190)
);
DFFRHQX8TS YRegister_Q_reg_32_ ( .D(n1264), .CK(clk), .RN(n6440), .Q(n2182)
);
DFFRHQX8TS YRegister_Q_reg_54_ ( .D(n1286), .CK(clk), .RN(n6442), .Q(n2180)
);
DFFSX2TS R_100 ( .D(n6512), .CK(clk), .SN(n6267), .Q(n6324) );
DFFRHQX8TS XRegister_Q_reg_32_ ( .D(n1329), .CK(clk), .RN(n6446), .Q(n2178)
);
DFFRHQX8TS XRegister_Q_reg_60_ ( .D(n1357), .CK(clk), .RN(n6449), .Q(n2174)
);
DFFRHQX8TS YRegister_Q_reg_47_ ( .D(n1279), .CK(clk), .RN(n6441), .Q(n2172)
);
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n1484), .CK(clk),
.RN(n6421), .Q(n2169) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n1479), .CK(clk),
.RN(n6434), .Q(n2167) );
DFFRHQX8TS XRegister_Q_reg_40_ ( .D(n1337), .CK(clk), .RN(n6447), .Q(n2164)
);
DFFRHQX8TS XRegister_Q_reg_50_ ( .D(n1347), .CK(clk), .RN(n6448), .Q(n2162)
);
DFFRHQX8TS XRegister_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n6443), .Q(n2160)
);
DFFRHQX8TS XRegister_Q_reg_20_ ( .D(n1317), .CK(clk), .RN(n6445), .Q(n2158)
);
DFFRHQX8TS YRegister_Q_reg_20_ ( .D(n1252), .CK(clk), .RN(n6439), .Q(n2156)
);
DFFRHQX8TS XRegister_Q_reg_44_ ( .D(n1341), .CK(clk), .RN(n6447), .Q(n2151)
);
DFFRHQX8TS XRegister_Q_reg_47_ ( .D(n1344), .CK(clk), .RN(n6448), .Q(n2149)
);
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n1471), .CK(clk),
.RN(n6419), .Q(n2146) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1448), .CK(clk),
.RN(n6433), .Q(n2143) );
DFFRHQX8TS XRegister_Q_reg_33_ ( .D(n1330), .CK(clk), .RN(n6446), .Q(n2141)
);
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1450), .CK(clk),
.RN(n6415), .Q(n2138) );
DFFRHQX8TS XRegister_Q_reg_17_ ( .D(n1314), .CK(clk), .RN(n6445), .Q(n2136)
);
DFFRHQX8TS YRegister_Q_reg_58_ ( .D(n1290), .CK(clk), .RN(n6443), .Q(n2134)
);
DFFRHQX8TS XRegister_Q_reg_54_ ( .D(n1351), .CK(clk), .RN(n6448), .Q(n2132)
);
DFFRHQX8TS XRegister_Q_reg_52_ ( .D(n1349), .CK(clk), .RN(n6448), .Q(n2127)
);
DFFSX4TS R_64 ( .D(Exp_Operation_Module_Data_S_8_), .CK(clk), .SN(n6435),
.Q(n6355) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n1469), .CK(clk),
.RN(n6418), .Q(n2124) );
DFFRHQX8TS XRegister_Q_reg_35_ ( .D(n1332), .CK(clk), .RN(n6447), .Q(n2122)
);
DFFRHQX8TS YRegister_Q_reg_10_ ( .D(n1242), .CK(clk), .RN(n6450), .Q(n2119)
);
DFFRHQX8TS XRegister_Q_reg_10_ ( .D(n1307), .CK(clk), .RN(n6444), .Q(n2117)
);
DFFSX4TS R_74 ( .D(n3502), .CK(clk), .SN(n6272), .Q(n6346) );
DFFRHQX8TS XRegister_Q_reg_53_ ( .D(n1350), .CK(clk), .RN(n6448), .Q(n2114)
);
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n2721),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRHQX8TS XRegister_Q_reg_41_ ( .D(n1338), .CK(clk), .RN(n6447), .Q(n2109)
);
DFFRX4TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n1519), .CK(clk),
.RN(n6262), .Q(Add_Subt_result[16]), .QN(n6255) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1443), .CK(clk),
.RN(n6547), .Q(n2107) );
DFFRHQX8TS XRegister_Q_reg_25_ ( .D(n1322), .CK(clk), .RN(n6446), .Q(n2105)
);
DFFRHQX8TS YRegister_Q_reg_28_ ( .D(n1260), .CK(clk), .RN(n6440), .Q(n2102)
);
DFFRHQX8TS YRegister_Q_reg_36_ ( .D(n1268), .CK(clk), .RN(n6440), .Q(n2099)
);
DFFRHQX8TS XRegister_Q_reg_19_ ( .D(n1316), .CK(clk), .RN(n6445), .Q(n2097)
);
DFFRHQX8TS XRegister_Q_reg_34_ ( .D(n1331), .CK(clk), .RN(n6446), .Q(n2095)
);
DFFRHQX8TS XRegister_Q_reg_59_ ( .D(n1356), .CK(clk), .RN(n6449), .Q(n2093)
);
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1456), .CK(clk),
.RN(n6416), .Q(n2089) );
DFFRHQX8TS YRegister_Q_reg_62_ ( .D(n1294), .CK(clk), .RN(n6443), .Q(n2087)
);
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1444), .CK(clk),
.RN(n6413), .Q(n2083) );
DFFRHQX8TS YRegister_Q_reg_46_ ( .D(n1278), .CK(clk), .RN(n6441), .Q(n2080)
);
DFFRHQX8TS XRegister_Q_reg_24_ ( .D(n1321), .CK(clk), .RN(n6445), .Q(n2078)
);
DFFRHQX8TS XRegister_Q_reg_49_ ( .D(n1346), .CK(clk), .RN(n6448), .Q(n2071)
);
DFFRHQX8TS XRegister_Q_reg_12_ ( .D(n1309), .CK(clk), .RN(n6444), .Q(n2063)
);
DFFRHQX8TS XRegister_Q_reg_14_ ( .D(n1311), .CK(clk), .RN(n6444), .Q(n2060)
);
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n1104), .CK(clk),
.RN(n6434), .Q(DmP[62]), .QN(n2051) );
DFFRHQX8TS XRegister_Q_reg_48_ ( .D(n1345), .CK(clk), .RN(n6448), .Q(n2043)
);
DFFRHQX8TS XRegister_Q_reg_13_ ( .D(n1310), .CK(clk), .RN(n6444), .Q(n2041)
);
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n1164), .CK(clk),
.RN(n6420), .Q(DmP[59]), .QN(n2040) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n1137), .CK(clk),
.RN(n6431), .Q(DmP[32]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n1219), .CK(clk),
.RN(n2745), .Q(DMP[50]) );
DFFRHQX8TS XRegister_Q_reg_26_ ( .D(n1323), .CK(clk), .RN(n6446), .Q(n2034)
);
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n1156), .CK(clk),
.RN(n2745), .Q(DmP[51]), .QN(n2030) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1113), .CK(clk), .RN(
n6429), .Q(DmP[8]) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1454), .CK(clk),
.RN(n6415), .Q(n2021) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1125), .CK(clk),
.RN(n2745), .Q(DmP[20]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n1140), .CK(clk),
.RN(n6431), .Q(DmP[35]) );
DFFRHQX2TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ ( .D(n1496),
.CK(clk), .RN(n6435), .Q(n2009) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n1141), .CK(clk),
.RN(n6431), .Q(n2008) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1462), .CK(clk),
.RN(n6417), .Q(n2006) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n1151), .CK(clk),
.RN(n6432), .Q(n2004) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1128), .CK(clk),
.RN(n2764), .Q(n2003) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1122), .CK(clk),
.RN(n2744), .Q(n2002) );
DFFRHQX8TS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1172), .CK(clk),
.RN(n6413), .Q(n2001) );
DFFRX4TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1431), .CK(clk),
.RN(n6414), .Q(exp_oper_result[7]), .QN(n6209) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n1143), .CK(clk),
.RN(n6431), .Q(n2000) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n1475), .CK(clk),
.RN(n2728), .Q(n1997) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n1166), .CK(clk),
.RN(n6420), .Q(DmP[61]), .QN(n1996) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1199), .CK(clk),
.RN(n6433), .Q(n2415) );
DFFRHQX8TS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1186), .CK(clk),
.RN(n6417), .Q(n1994) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1453), .CK(clk),
.RN(n6415), .Q(n1992) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1460), .CK(clk),
.RN(n6417), .Q(n1979) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n1202), .CK(clk),
.RN(n6436), .Q(n1976) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n1152), .CK(clk),
.RN(n6432), .Q(n1970) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n1225), .CK(clk),
.RN(n2728), .Q(DMP[56]) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1467), .CK(clk),
.RN(n6418), .Q(n1968) );
DFFRX4TS Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n1158), .CK(clk),
.RN(n6434), .Q(DmP[53]), .QN(n1967) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n1478), .CK(clk),
.RN(n6413), .Q(n1958) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1189), .CK(clk),
.RN(n6418), .Q(n2324) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1178), .CK(clk),
.RN(n6415), .Q(n2685) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1133), .CK(clk),
.RN(n6430), .Q(DmP[28]), .QN(n1962) );
DFFRHQX8TS XRegister_Q_reg_61_ ( .D(n1358), .CK(clk), .RN(n6449), .Q(n1942)
);
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n1145), .CK(clk),
.RN(n6432), .Q(n1940) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1132), .CK(clk),
.RN(n6430), .Q(n1933) );
DFFRHQX8TS XRegister_Q_reg_30_ ( .D(n1327), .CK(clk), .RN(n6446), .Q(n1916)
);
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1115), .CK(clk),
.RN(n6429), .Q(DmP[10]), .QN(n1914) );
DFFRX4TS Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n1227), .CK(clk),
.RN(n6437), .QN(n6224) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n1223), .CK(clk),
.RN(n6433), .Q(n1902) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1106), .CK(clk),
.RN(n6438), .Q(n1900) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n1142), .CK(clk),
.RN(n6431), .Q(n1897) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n1155), .CK(clk),
.RN(n6432), .Q(n1896) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1107), .CK(clk),
.RN(n6428), .Q(n1892) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1111), .CK(clk),
.RN(n6438), .Q(n1889) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1108), .CK(clk),
.RN(n6428), .Q(n1887) );
DFFRHQX8TS YRegister_Q_reg_12_ ( .D(n1244), .CK(clk), .RN(n4871), .Q(n1872)
);
DFFRHQX8TS XRegister_Q_reg_46_ ( .D(n1343), .CK(clk), .RN(n6448), .Q(n1869)
);
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1118), .CK(clk),
.RN(n6429), .Q(n1971) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n1200), .CK(clk),
.RN(n6414), .Q(n1974) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1114), .CK(clk),
.RN(n6429), .Q(n1966) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n1203), .CK(clk),
.RN(n6433), .Q(n1929) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1134), .CK(clk),
.RN(n6430), .Q(DmP[29]) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n1204), .CK(clk),
.RN(n6421), .Q(n2339) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1174), .CK(clk),
.RN(n6415), .Q(n2045) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1127), .CK(clk),
.RN(n2764), .Q(DmP[22]) );
DFFRHQX4TS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1121), .CK(clk),
.RN(n2745), .Q(n1857) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1176), .CK(clk),
.RN(n6415), .Q(n2417) );
DFFRHQX8TS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1180), .CK(clk),
.RN(n6416), .Q(n2691) );
DFFRHQX8TS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1181), .CK(clk),
.RN(n6416), .Q(n2689) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1184), .CK(clk),
.RN(n6417), .Q(n2687) );
DFFRHQX8TS YRegister_Q_reg_24_ ( .D(n1256), .CK(clk), .RN(n6439), .Q(n1854)
);
DFFRHQX8TS YRegister_Q_reg_48_ ( .D(n1280), .CK(clk), .RN(n6442), .Q(n1850)
);
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n1230), .CK(clk),
.RN(n6433), .Q(n2411) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n1206), .CK(clk),
.RN(n6421), .Q(n2346) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1173), .CK(clk),
.RN(n6435), .Q(n2285) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n1224), .CK(clk),
.RN(n6414), .Q(n1923) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n1226), .CK(clk),
.RN(n6436), .Q(n1885) );
DFFSX4TS R_61 ( .D(n6529), .CK(clk), .SN(n6263), .QN(n2545) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1458), .CK(clk),
.RN(n6416), .Q(n1845) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1196), .CK(clk),
.RN(n6419), .Q(n1836) );
DFFSX2TS R_8 ( .D(n6540), .CK(clk), .SN(n6436), .Q(n6393) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1452), .CK(clk),
.RN(n6415), .Q(n1826) );
DFFSX2TS R_4 ( .D(n6544), .CK(clk), .SN(n6420), .Q(n6397) );
DFFRHQX8TS FS_Module_state_reg_reg_1_ ( .D(n1559), .CK(clk), .RN(n6547), .Q(
n2645) );
DFFSX4TS R_58 ( .D(n6531), .CK(clk), .SN(n6263), .QN(n2547) );
DFFSX4TS R_176 ( .D(n6406), .CK(clk), .SN(n6433), .Q(n1815) );
DFFSHQX8TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n3510),
.CK(clk), .SN(n2721), .Q(n1812) );
DFFRHQX2TS Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(n1428), .CK(clk),
.RN(n6414), .Q(n2650) );
DFFRX4TS YRegister_Q_reg_63_ ( .D(n1231), .CK(clk), .RN(n2744), .Q(intDY[63]), .QN(n6260) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n1488), .CK(clk),
.RN(n6423), .Q(n2210) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1195), .CK(clk),
.RN(n6419), .Q(n1810) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n6423),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n6427),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .CK(clk), .RN(n6422),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[94]), .QN(n6246) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1182), .CK(clk),
.RN(n6416), .Q(n1960) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1105), .CK(clk),
.RN(n6428), .Q(n1925) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1171), .CK(clk),
.RN(n6436), .Q(n1893) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n1162), .CK(clk),
.RN(n6435), .Q(n1931) );
DFFRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n1477), .CK(clk),
.RN(n6435), .Q(n1610) );
DFFRHQX8TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n1562),
.CK(clk), .RN(n6547), .Q(n2453) );
DFFSX4TS R_163 ( .D(n6526), .CK(clk), .SN(n6262), .Q(n6275) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1175), .CK(clk),
.RN(n6415), .Q(n1955) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1455), .CK(clk),
.RN(n6416), .Q(n2012) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1187), .CK(clk),
.RN(n6417), .Q(n1862) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1185), .CK(clk),
.RN(n6417), .Q(n2416) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1451), .CK(clk),
.RN(n6415), .Q(n2047) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n1201), .CK(clk),
.RN(n6437), .Q(n1973) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1198), .CK(clk),
.RN(n6419), .Q(n1975) );
DFFSRHQX2TS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1177), .CK(clk),
.SN(1'b1), .RN(n6438), .Q(DMP[8]) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1194), .CK(clk),
.RN(n6419), .Q(n1877) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1457), .CK(clk),
.RN(n6416), .Q(n1913) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1465), .CK(clk),
.RN(n6418), .Q(n1867) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1197), .CK(clk),
.RN(n6419), .Q(n2299) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n1221), .CK(clk),
.RN(n6437), .Q(n1908) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1192), .CK(clk),
.RN(n6418), .Q(n2328) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n1207), .CK(clk),
.RN(n6421), .Q(n2300) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n1205), .CK(clk),
.RN(n6421), .Q(n1898) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n1476), .CK(clk),
.RN(n6434), .Q(n1833) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n1474), .CK(clk),
.RN(n6419), .Q(n1991) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n1211), .CK(clk),
.RN(n6422), .Q(n2076) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n1209), .CK(clk),
.RN(n6422), .Q(n1945) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n1210), .CK(clk),
.RN(n6422), .Q(n2345) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n1217), .CK(clk),
.RN(n6427), .Q(n1937) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n1218), .CK(clk),
.RN(n6428), .Q(n1894) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n1215), .CK(clk),
.RN(n6425), .Q(n1879) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n1216), .CK(clk),
.RN(n6426), .Q(n1935) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n1489), .CK(clk),
.RN(n6423), .Q(n1883) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n1208), .CK(clk),
.RN(n6421), .Q(n2406) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n1212), .CK(clk),
.RN(n6423), .Q(n1881) );
DFFSX2TS R_52 ( .D(n6456), .CK(clk), .SN(n6271), .Q(n6364) );
DFFSX2TS R_73 ( .D(n6457), .CK(clk), .SN(n6272), .Q(n6347) );
DFFSX2TS R_53 ( .D(n6402), .CK(clk), .SN(n6271), .Q(n6363) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n1220), .CK(clk),
.RN(n6270), .Q(n2407) );
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n1222), .CK(clk),
.RN(n6413), .Q(n1910) );
DFFSRHQX2TS Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n1159), .CK(clk),
.SN(1'b1), .RN(n6438), .Q(DmP[54]) );
DFFSX1TS R_20 ( .D(n6472), .CK(clk), .SN(n2736), .Q(n6383) );
DFFRHQX4TS YRegister_Q_reg_22_ ( .D(n1254), .CK(clk), .RN(n6439), .Q(n2382)
);
DFFRHQX4TS XRegister_Q_reg_62_ ( .D(n1359), .CK(clk), .RN(n6449), .Q(n1848)
);
DFFRHQX4TS YRegister_Q_reg_23_ ( .D(n1255), .CK(clk), .RN(n6439), .Q(n2192)
);
DFFRHQX4TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n1500),
.CK(clk), .RN(n6437), .Q(n2678) );
DFFRHQX4TS YRegister_Q_reg_21_ ( .D(n1253), .CK(clk), .RN(n6439), .Q(n2367)
);
DFFRHQX4TS YRegister_Q_reg_0_ ( .D(n1232), .CK(clk), .RN(n2745), .Q(n2447)
);
DFFRHQX4TS YRegister_Q_reg_17_ ( .D(n1249), .CK(clk), .RN(n6264), .Q(n2635)
);
DFFRHQX4TS YRegister_Q_reg_60_ ( .D(n1292), .CK(clk), .RN(n6443), .Q(n2289)
);
DFFRHQX2TS Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n1228), .CK(clk),
.RN(n6434), .Q(n2413) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n1160), .CK(clk),
.RN(n6413), .Q(n1926) );
DFFSX2TS Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(n3508), .CK(clk),
.SN(n2721), .Q(n6213), .QN(Sgf_normalized_result[53]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n1513), .CK(clk),
.RN(n6437), .Q(Add_Subt_result[10]), .QN(n6254) );
DFFRHQX4TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n1497),
.CK(clk), .RN(n2728), .Q(n2316) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n1165), .CK(clk),
.RN(n6436), .Q(n1939) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n1163), .CK(clk),
.RN(n2728), .Q(n1961) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n1512), .CK(clk),
.RN(n6433), .Q(Add_Subt_result[9]), .QN(n6212) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n1229), .CK(clk),
.RN(n6433), .Q(n1904) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n1509), .CK(clk),
.RN(n6433), .Q(Add_Subt_result[6]), .QN(n6222) );
DFFRHQX4TS Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n1168), .CK(clk),
.RN(n6413), .Q(n1906) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n1507), .CK(clk),
.RN(n6436), .Q(Add_Subt_result[4]), .QN(n6258) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .CK(clk), .RN(n6423),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[86]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n6547),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[54]), .CK(clk), .RN(n6438),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[106]), .QN(n6244) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .CK(clk), .RN(n6426),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[90]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[53]), .CK(clk), .RN(n6420),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[105]), .QN(n6242) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .CK(clk), .RN(n6427),
.QN(n6537) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n1149), .CK(clk),
.RN(n6414), .Q(DmP[44]), .QN(n2029) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n1154), .CK(clk),
.RN(n6432), .Q(DmP[49]) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1135), .CK(clk),
.RN(n6430), .Q(DmP[30]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1110), .CK(clk), .RN(
n6428), .Q(DmP[5]), .QN(n2023) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1112), .CK(clk),
.RN(n2744), .Q(n2130) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n1148), .CK(clk),
.RN(n6432), .Q(n1987) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n1146), .CK(clk),
.RN(n6432), .Q(n2298) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n1150), .CK(clk),
.RN(n2744), .Q(n1986) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n1138), .CK(clk),
.RN(n6431), .Q(n1965) );
DFFRHQX2TS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1109), .CK(clk),
.RN(n6428), .Q(n1856) );
DFFRX2TS Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n1153), .CK(clk),
.RN(n6432), .Q(DmP[48]) );
NAND2X1TS U1759 ( .A(n5999), .B(n6003), .Y(n6478) );
NAND2X1TS U1760 ( .A(n2493), .B(underflow_flag), .Y(n6539) );
OAI2BB1X2TS U1761 ( .A0N(n2664), .A1N(n5715), .B0(n5108), .Y(n1452) );
BUFX16TS U1762 ( .A(n5810), .Y(n2735) );
AOI22X1TS U1763 ( .A0(n5887), .A1(n2722), .B0(n2215), .B1(n3255), .Y(n5141)
);
AOI22X1TS U1764 ( .A0(n2677), .A1(n5669), .B0(n5687), .B1(n5229), .Y(n5676)
);
AOI22X1TS U1765 ( .A0(n2673), .A1(n5618), .B0(n5654), .B1(n5617), .Y(n5625)
);
NAND2X2TS U1766 ( .A(n5415), .B(n5396), .Y(n5400) );
AOI22X1TS U1767 ( .A0(n2759), .A1(n5621), .B0(n5610), .B1(n5680), .Y(n5581)
);
AOI22X1TS U1768 ( .A0(n2889), .A1(n5684), .B0(n5682), .B1(n5668), .Y(n5677)
);
AOI22X1TS U1769 ( .A0(n2887), .A1(n5572), .B0(n5570), .B1(n5680), .Y(n5302)
);
AOI22X1TS U1770 ( .A0(n2760), .A1(n5617), .B0(n5618), .B1(n2697), .Y(n5604)
);
INVX2TS U1771 ( .A(n5972), .Y(n2747) );
BUFX16TS U1772 ( .A(n5795), .Y(n5845) );
AOI22X1TS U1773 ( .A0(n5663), .A1(n5619), .B0(n5617), .B1(n2699), .Y(n5328)
);
AOI22X1TS U1774 ( .A0(n2698), .A1(n5591), .B0(n5573), .B1(n5648), .Y(n5300)
);
AOI22X1TS U1775 ( .A0(n5893), .A1(n4965), .B0(n5732), .B1(n1845), .Y(n5155)
);
AOI22X1TS U1776 ( .A0(n6050), .A1(n5622), .B0(n5579), .B1(n2699), .Y(n5582)
);
AOI22X1TS U1777 ( .A0(n5476), .A1(n5532), .B0(n5668), .B1(n5477), .Y(n5228)
);
AOI22X1TS U1778 ( .A0(n5476), .A1(n2673), .B0(n5668), .B1(n5478), .Y(n5237)
);
AOI22X1TS U1779 ( .A0(n5145), .A1(n4965), .B0(n5784), .B1(n1979), .Y(n5146)
);
INVX4TS U1780 ( .A(n6033), .Y(n4909) );
NAND2X2TS U1781 ( .A(n5781), .B(n1647), .Y(n5095) );
AOI22X1TS U1782 ( .A0(n2712), .A1(n5567), .B0(n5663), .B1(n5589), .Y(n5299)
);
AOI22X1TS U1783 ( .A0(n5662), .A1(n2505), .B0(n2889), .B1(n5609), .Y(n5444)
);
INVX3TS U1784 ( .A(n6033), .Y(n6040) );
NAND2X2TS U1785 ( .A(n5764), .B(n1647), .Y(n2957) );
AOI22X1TS U1786 ( .A0(n5733), .A1(n4965), .B0(n2138), .B1(n5895), .Y(n5005)
);
INVX4TS U1787 ( .A(n2323), .Y(n5929) );
AOI2BB2X1TS U1788 ( .B0(n2143), .B1(n3255), .A0N(n5738), .A1N(n5107), .Y(
n4989) );
AOI22X2TS U1789 ( .A0(n2741), .A1(n2034), .B0(n1810), .B1(n5859), .Y(n5855)
);
OAI21X1TS U1790 ( .A0(n5891), .A1(n5892), .B0(n2663), .Y(n5156) );
INVX3TS U1791 ( .A(n5972), .Y(n2748) );
OR2X2TS U1792 ( .A(n3474), .B(n5971), .Y(n2540) );
AOI22X2TS U1793 ( .A0(n5860), .A1(n2136), .B0(n1994), .B1(n5859), .Y(n5761)
);
OR2X2TS U1794 ( .A(n3289), .B(n1819), .Y(n3286) );
NAND2X1TS U1795 ( .A(n2580), .B(n2663), .Y(n4990) );
BUFX3TS U1796 ( .A(n4793), .Y(n5952) );
AOI22X1TS U1797 ( .A0(n2761), .A1(n5656), .B0(n5629), .B1(n2698), .Y(n5520)
);
AOI22X1TS U1798 ( .A0(n5704), .A1(n2722), .B0(n5732), .B1(n2047), .Y(n2570)
);
AOI22X1TS U1799 ( .A0(n5712), .A1(n4965), .B0(n5732), .B1(n2012), .Y(n5020)
);
AOI22X2TS U1800 ( .A0(n2732), .A1(n2221), .B0(n1836), .B1(n5871), .Y(n5205)
);
AOI22X1TS U1801 ( .A0(n2674), .A1(n5672), .B0(n5654), .B1(n5669), .Y(n5659)
);
AOI2BB2X1TS U1802 ( .B0(n2461), .B1(n5140), .A0N(n5743), .A1N(n5107), .Y(
n4976) );
CLKAND2X2TS U1803 ( .A(n5940), .B(n5941), .Y(n2494) );
OAI21X1TS U1804 ( .A0(n6021), .A1(n6020), .B0(n6019), .Y(n6030) );
AOI22X1TS U1805 ( .A0(n5663), .A1(n5669), .B0(n5672), .B1(n2700), .Y(n5664)
);
AOI22X1TS U1806 ( .A0(n2677), .A1(n5570), .B0(n5569), .B1(n5680), .Y(n5394)
);
NAND2BXLTS U1807 ( .AN(n2827), .B(n1988), .Y(n5201) );
NAND2BXLTS U1808 ( .AN(n4394), .B(n3023), .Y(n3156) );
AOI2BB2X1TS U1809 ( .B0(n2450), .B1(n3255), .A0N(n4979), .A1N(n5107), .Y(
n4980) );
NAND2BX2TS U1810 ( .AN(n3066), .B(n2607), .Y(n2606) );
NAND2BXLTS U1811 ( .AN(n4574), .B(n6009), .Y(n2829) );
AOI22X1TS U1812 ( .A0(n5685), .A1(n5570), .B0(n2887), .B1(n5569), .Y(n5576)
);
AOI22X1TS U1813 ( .A0(n5663), .A1(n5569), .B0(n5567), .B1(n2698), .Y(n5387)
);
AOI22X1TS U1814 ( .A0(n5663), .A1(n5618), .B0(n5622), .B1(n2700), .Y(n5487)
);
AOI22X1TS U1815 ( .A0(n5655), .A1(n5683), .B0(n5686), .B1(n5670), .Y(n5658)
);
AOI22X1TS U1816 ( .A0(n5668), .A1(n2505), .B0(n5609), .B1(n5670), .Y(n5460)
);
BUFX12TS U1817 ( .A(n3229), .Y(n1599) );
NAND2X2TS U1818 ( .A(n5476), .B(n5642), .Y(n5202) );
NAND2X2TS U1819 ( .A(n5742), .B(n5780), .Y(n1605) );
AOI22X1TS U1820 ( .A0(n2675), .A1(n5578), .B0(n5603), .B1(n5608), .Y(n5463)
);
AOI22X1TS U1821 ( .A0(n5476), .A1(n5634), .B0(n2677), .B1(n2504), .Y(n5247)
);
NAND2X2TS U1822 ( .A(n5195), .B(n2662), .Y(n5089) );
AOI22X2TS U1823 ( .A0(n2740), .A1(n2384), .B0(n2346), .B1(n5842), .Y(n5757)
);
NAND2BX2TS U1824 ( .AN(n2785), .B(n3530), .Y(n2784) );
NAND3X4TS U1825 ( .A(n3407), .B(n3403), .C(n3406), .Y(n3399) );
NAND2X2TS U1826 ( .A(n5571), .B(n5396), .Y(n5279) );
NAND2X2TS U1827 ( .A(n5189), .B(n5194), .Y(n5193) );
AOI22X1TS U1828 ( .A0(n4965), .A1(n5707), .B0(n5732), .B1(n2021), .Y(n5029)
);
NAND2X2TS U1829 ( .A(n5476), .B(n5631), .Y(n5422) );
NOR2X4TS U1830 ( .A(n3113), .B(n3112), .Y(n3111) );
AOI22X1TS U1831 ( .A0(n5673), .A1(n5622), .B0(n5621), .B1(n2699), .Y(n5623)
);
AOI21X1TS U1832 ( .A0(n2753), .A1(n5707), .B0(n5706), .Y(n5708) );
NAND2X2TS U1833 ( .A(n5415), .B(n2555), .Y(n5369) );
OAI21XLTS U1834 ( .A0(n4897), .A1(n6024), .B0(n5987), .Y(n4898) );
NAND2X4TS U1835 ( .A(n3109), .B(n3110), .Y(n3114) );
OR2X2TS U1836 ( .A(n2726), .B(n1703), .Y(n5703) );
OR2X1TS U1837 ( .A(n2726), .B(n1702), .Y(n5904) );
NAND2X1TS U1838 ( .A(n2930), .B(n5933), .Y(n2928) );
AOI21X2TS U1839 ( .A0(n2710), .A1(n2602), .B0(n3472), .Y(n2600) );
INVX8TS U1840 ( .A(n1634), .Y(n2699) );
BUFX8TS U1841 ( .A(n5427), .Y(n5670) );
INVX8TS U1842 ( .A(n2672), .Y(n2673) );
BUFX8TS U1843 ( .A(n5566), .Y(n5584) );
BUFX8TS U1844 ( .A(n5426), .Y(n2761) );
INVX4TS U1845 ( .A(n5768), .Y(n5777) );
INVX6TS U1846 ( .A(n5931), .Y(n3968) );
BUFX8TS U1847 ( .A(n5386), .Y(n5685) );
INVX8TS U1848 ( .A(n5679), .Y(n5627) );
BUFX8TS U1849 ( .A(n5642), .Y(n2886) );
INVX8TS U1850 ( .A(n2672), .Y(n2675) );
BUFX8TS U1851 ( .A(n5386), .Y(n5532) );
AO22X1TS U1852 ( .A0(n2746), .A1(n6007), .B0(n5645), .B1(Add_Subt_result[0]),
.Y(n2528) );
CLKINVX6TS U1853 ( .A(n5807), .Y(n2039) );
NAND2X1TS U1854 ( .A(n4335), .B(n4334), .Y(n4782) );
INVX12TS U1855 ( .A(n2888), .Y(n2759) );
NAND2X4TS U1856 ( .A(n5647), .B(n5646), .Y(n5684) );
OAI2BB1X2TS U1857 ( .A0N(Sgf_normalized_result[44]), .A1N(n5154), .B0(n2727),
.Y(n5716) );
OAI2BB2X1TS U1858 ( .B0(n5748), .B1(n5107), .A0N(n2463), .A1N(n3255), .Y(
n2870) );
NAND2XLTS U1859 ( .A(n4831), .B(n4830), .Y(n4832) );
BUFX16TS U1860 ( .A(n5386), .Y(n5628) );
NOR2X4TS U1861 ( .A(n3230), .B(n4192), .Y(n3229) );
NOR2X1TS U1862 ( .A(n4246), .B(n5999), .Y(n3068) );
NOR2X1TS U1863 ( .A(n4314), .B(n1672), .Y(n4317) );
NOR2BX2TS U1864 ( .AN(n4759), .B(n3405), .Y(n3403) );
INVX4TS U1865 ( .A(n4494), .Y(n1730) );
CLKINVX2TS U1866 ( .A(n3475), .Y(n1832) );
CLKAND2X2TS U1867 ( .A(n4478), .B(n4477), .Y(n2511) );
NAND3X6TS U1868 ( .A(n5271), .B(n5270), .C(n5269), .Y(n5595) );
NAND3X6TS U1869 ( .A(n5225), .B(n5224), .C(n5223), .Y(n5579) );
NAND2X2TS U1870 ( .A(n3939), .B(n4798), .Y(n2569) );
NAND3X6TS U1871 ( .A(n5448), .B(n5447), .C(n5446), .Y(n5621) );
NAND2X1TS U1872 ( .A(n5177), .B(n1695), .Y(n5695) );
NAND2XLTS U1873 ( .A(n5732), .B(Sgf_normalized_result[52]), .Y(n5785) );
AND2X4TS U1874 ( .A(n2953), .B(n3279), .Y(n3282) );
CLKAND2X2TS U1875 ( .A(n4753), .B(n4602), .Y(n2561) );
NOR2X2TS U1876 ( .A(n2977), .B(n1988), .Y(n5396) );
CLKINVX1TS U1877 ( .A(n1652), .Y(n1921) );
BUFX8TS U1878 ( .A(n5386), .Y(n5603) );
NOR2X4TS U1879 ( .A(n5242), .B(n1852), .Y(n5233) );
OAI21X1TS U1880 ( .A0(n4753), .A1(n4602), .B0(n4793), .Y(n2996) );
CLKBUFX2TS U1881 ( .A(Sgf_normalized_result[22]), .Y(n1677) );
NAND2X1TS U1882 ( .A(n4775), .B(n4776), .Y(n4573) );
NOR2BX1TS U1883 ( .AN(n5935), .B(n4726), .Y(n2927) );
AND2X4TS U1884 ( .A(n4062), .B(n5694), .Y(n4071) );
CLKBUFX2TS U1885 ( .A(Sgf_normalized_result[28]), .Y(n1687) );
NAND2X1TS U1886 ( .A(n4349), .B(n4348), .Y(n4388) );
BUFX6TS U1887 ( .A(n5426), .Y(n5634) );
NAND2X2TS U1888 ( .A(n2781), .B(n3538), .Y(n2787) );
OAI21X1TS U1889 ( .A0(n4900), .A1(n2723), .B0(n5977), .Y(n6026) );
AND2X2TS U1890 ( .A(n4726), .B(n1722), .Y(n2930) );
CLKINVX1TS U1891 ( .A(n1975), .Y(n2353) );
NOR2X1TS U1892 ( .A(n2726), .B(n2479), .Y(n2783) );
XNOR2X2TS U1893 ( .A(n4921), .B(n4920), .Y(n4922) );
OR2X2TS U1894 ( .A(n2726), .B(n5191), .Y(n2789) );
INVX2TS U1895 ( .A(n1615), .Y(n1613) );
INVX2TS U1896 ( .A(n1616), .Y(n1614) );
NOR2X1TS U1897 ( .A(n2726), .B(n2480), .Y(n2792) );
NAND2X2TS U1898 ( .A(n5514), .B(n5997), .Y(n5169) );
NAND2X2TS U1899 ( .A(n5510), .B(Add_Subt_result[15]), .Y(n5374) );
NAND2X1TS U1900 ( .A(n5148), .B(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n4054) );
NAND2X1TS U1901 ( .A(n2754), .B(n2003), .Y(n5293) );
NAND2X2TS U1902 ( .A(n5510), .B(n6010), .Y(n5253) );
NAND2X2TS U1903 ( .A(n2731), .B(n1686), .Y(n5375) );
NAND2X1TS U1904 ( .A(n5150), .B(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n5048) );
NAND2X1TS U1905 ( .A(n2723), .B(DmP[14]), .Y(n5376) );
NAND2X2TS U1906 ( .A(n2746), .B(n5406), .Y(n5325) );
NAND2X2TS U1907 ( .A(n2725), .B(Add_Subt_result[16]), .Y(n5377) );
NAND2X4TS U1908 ( .A(n5510), .B(n3250), .Y(n5433) );
NAND2X2TS U1909 ( .A(n2731), .B(n6008), .Y(n5345) );
NAND2X1TS U1910 ( .A(n2754), .B(n1965), .Y(n5304) );
NAND2X2TS U1911 ( .A(n5148), .B(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n5044) );
INVX1TS U1912 ( .A(n4634), .Y(n4636) );
NAND2X1TS U1913 ( .A(n3013), .B(n4931), .Y(n4926) );
INVX2TS U1914 ( .A(n1643), .Y(n2104) );
NAND2X1TS U1915 ( .A(n2754), .B(DmP[15]), .Y(n5356) );
INVX2TS U1916 ( .A(n4364), .Y(n3471) );
NAND2X2TS U1917 ( .A(n2746), .B(n6002), .Y(n5497) );
NAND2X2TS U1918 ( .A(n2725), .B(Add_Subt_result[2]), .Y(n5640) );
INVX6TS U1919 ( .A(n5871), .Y(n2028) );
INVX2TS U1920 ( .A(n4346), .Y(n3279) );
BUFX3TS U1921 ( .A(n5698), .Y(n5140) );
NAND2X1TS U1922 ( .A(n5452), .B(DmP[51]), .Y(n5166) );
NAND2X1TS U1923 ( .A(n5506), .B(DmP[39]), .Y(n5326) );
INVX2TS U1924 ( .A(n2503), .Y(n2445) );
NAND2X1TS U1925 ( .A(n2729), .B(n2002), .Y(n5342) );
NAND2X1TS U1926 ( .A(n5148), .B(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n4046) );
INVX8TS U1927 ( .A(n1819), .Y(n2753) );
NAND2X1TS U1928 ( .A(n5452), .B(n1987), .Y(n5436) );
NAND2X1TS U1929 ( .A(n4416), .B(n4415), .Y(n4423) );
NOR2X4TS U1930 ( .A(n5260), .B(n5259), .Y(n5365) );
OA21X2TS U1931 ( .A0(n4480), .A1(n5969), .B0(n2621), .Y(n2487) );
INVX2TS U1932 ( .A(n4843), .Y(n1652) );
NAND2X1TS U1933 ( .A(n2729), .B(DmP[19]), .Y(n5350) );
NAND2X1TS U1934 ( .A(n2729), .B(n1966), .Y(n5512) );
AOI22X1TS U1935 ( .A0(n5104), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .Y(n5025) );
INVX2TS U1936 ( .A(n5655), .Y(n2053) );
CLKINVX6TS U1937 ( .A(n3170), .Y(n1769) );
INVX4TS U1938 ( .A(n6011), .Y(n5980) );
NAND2X1TS U1939 ( .A(n3996), .B(n3995), .Y(n3997) );
NAND2X2TS U1940 ( .A(n5639), .B(n5984), .Y(n5453) );
OR2X2TS U1941 ( .A(n3252), .B(n6223), .Y(n5322) );
INVX4TS U1942 ( .A(n5768), .Y(n5825) );
NAND2X1TS U1943 ( .A(n5452), .B(n1986), .Y(n5432) );
AOI22X1TS U1944 ( .A0(n5102), .A1(n2743), .B0(n5150), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n5026) );
INVX2TS U1945 ( .A(n4764), .Y(n3405) );
NAND2X1TS U1946 ( .A(n4620), .B(n4618), .Y(n4371) );
INVX2TS U1947 ( .A(n5258), .Y(n4574) );
NAND2XLTS U1948 ( .A(n6022), .B(n1985), .Y(n6023) );
NAND2X2TS U1949 ( .A(n5717), .B(n2421), .Y(n5024) );
NAND2X2TS U1950 ( .A(n5639), .B(Add_Subt_result[12]), .Y(n5449) );
NAND2X2TS U1951 ( .A(n5434), .B(Add_Subt_result[2]), .Y(n1633) );
INVX2TS U1952 ( .A(n4347), .Y(n4349) );
NAND2X1TS U1953 ( .A(n5082), .B(n2742), .Y(n5037) );
NAND2BX2TS U1954 ( .AN(n4569), .B(n4016), .Y(n4570) );
NAND2XLTS U1955 ( .A(n5496), .B(DmP[29]), .Y(n5249) );
NAND2X6TS U1956 ( .A(n4846), .B(n3056), .Y(n1798) );
NAND2X2TS U1957 ( .A(n5434), .B(Add_Subt_result[9]), .Y(n5435) );
NAND2X2TS U1958 ( .A(n5639), .B(Add_Subt_result[10]), .Y(n5446) );
NAND2X2TS U1959 ( .A(n5434), .B(Add_Subt_result[4]), .Y(n5223) );
NAND2X2TS U1960 ( .A(n5639), .B(Add_Subt_result[7]), .Y(n5431) );
NAND2X1TS U1961 ( .A(n5506), .B(DmP[48]), .Y(n5224) );
NAND2X4TS U1962 ( .A(n1801), .B(n1804), .Y(n1803) );
NAND2X1TS U1963 ( .A(n4500), .B(n4532), .Y(n2116) );
INVX3TS U1964 ( .A(n2418), .Y(n5092) );
NAND2X2TS U1965 ( .A(n5516), .B(n5991), .Y(n5407) );
AND2X2TS U1966 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(n2638) );
AND2X2TS U1967 ( .A(n3147), .B(n4352), .Y(n2717) );
OAI21X2TS U1968 ( .A0(n1831), .A1(n4453), .B0(n4454), .Y(n4455) );
NAND2X2TS U1969 ( .A(n2731), .B(n6006), .Y(n5341) );
CLKINVX6TS U1970 ( .A(n1650), .Y(n1988) );
NAND2X2TS U1971 ( .A(n5282), .B(n5291), .Y(n5292) );
INVX4TS U1972 ( .A(n5196), .Y(n2662) );
BUFX4TS U1973 ( .A(n3675), .Y(n2781) );
NAND2X1TS U1974 ( .A(n5732), .B(Sgf_normalized_result[50]), .Y(n3538) );
BUFX4TS U1975 ( .A(n5697), .Y(n5885) );
NAND2X2TS U1976 ( .A(n5516), .B(n5990), .Y(n5355) );
NAND2X6TS U1977 ( .A(n4472), .B(n2644), .Y(n3251) );
NAND2X1TS U1978 ( .A(n5496), .B(DmP[20]), .Y(n5297) );
OAI21X2TS U1979 ( .A0(n4026), .A1(n4447), .B0(n4446), .Y(n4448) );
BUFX12TS U1980 ( .A(n5566), .Y(n5668) );
INVX2TS U1981 ( .A(n4213), .Y(n2602) );
NAND2XLTS U1982 ( .A(n4857), .B(n4856), .Y(n4207) );
INVX2TS U1983 ( .A(n3340), .Y(n3337) );
NAND2X1TS U1984 ( .A(n5506), .B(DmP[32]), .Y(n5307) );
CLKBUFX2TS U1985 ( .A(n1841), .Y(n1786) );
AND3X6TS U1986 ( .A(n3285), .B(n4340), .C(n3284), .Y(n2548) );
NAND2X2TS U1987 ( .A(n2731), .B(n1675), .Y(n5500) );
NAND2BX2TS U1988 ( .AN(n4596), .B(Add_Subt_result[12]), .Y(n4597) );
NAND2X2TS U1989 ( .A(n5639), .B(Add_Subt_result[5]), .Y(n5230) );
BUFX4TS U1990 ( .A(n5697), .Y(n5194) );
NAND2X2TS U1991 ( .A(n5282), .B(n5348), .Y(n5251) );
NAND2X2TS U1992 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n3676) );
NAND2BX2TS U1993 ( .AN(n4579), .B(n3172), .Y(n3171) );
CLKAND2X2TS U1994 ( .A(n3943), .B(n4797), .Y(n2520) );
NOR2X6TS U1995 ( .A(n2838), .B(n5924), .Y(n2842) );
NAND2X2TS U1996 ( .A(n5149), .B(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n5043) );
INVX6TS U1997 ( .A(n5768), .Y(n5807) );
NAND2X1TS U1998 ( .A(n2982), .B(n4656), .Y(n4713) );
NAND2X2TS U1999 ( .A(n5514), .B(Add_Subt_result[4]), .Y(n5646) );
NAND2X6TS U2000 ( .A(n2756), .B(n5993), .Y(n5451) );
OAI21X1TS U2001 ( .A0(n6056), .A1(n6043), .B0(n6044), .Y(n4921) );
NOR2X2TS U2002 ( .A(n4826), .B(n4447), .Y(n4449) );
BUFX8TS U2003 ( .A(n5426), .Y(n5673) );
NAND2X2TS U2004 ( .A(n5510), .B(Add_Subt_result[3]), .Y(n5643) );
NAND2X2TS U2005 ( .A(n5150), .B(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n5042) );
INVX3TS U2006 ( .A(n4844), .Y(n3368) );
INVX2TS U2007 ( .A(n3169), .Y(n4583) );
BUFX4TS U2008 ( .A(n5697), .Y(n5897) );
NAND2X2TS U2009 ( .A(n2723), .B(n1857), .Y(n5338) );
AOI22X2TS U2010 ( .A0(n5639), .A1(n5998), .B0(n1856), .B1(n2723), .Y(n5492)
);
NOR2X2TS U2011 ( .A(n4747), .B(n3489), .Y(n2572) );
CLKBUFX2TS U2012 ( .A(Sgf_normalized_result[41]), .Y(n1594) );
NAND2X4TS U2013 ( .A(n1866), .B(n2858), .Y(n1584) );
INVX4TS U2014 ( .A(n2070), .Y(n5306) );
NAND2X1TS U2015 ( .A(n5149), .B(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n3664) );
OAI21X1TS U2016 ( .A0(n4213), .A1(n1581), .B0(n4214), .Y(n4034) );
OAI21X1TS U2017 ( .A0(n1876), .A1(n3982), .B0(n1695), .Y(n3983) );
NAND2X2TS U2018 ( .A(n5083), .B(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n3677) );
NAND2X2TS U2019 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[106]), .Y(n5078) );
NAND2X2TS U2020 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[105]), .Y(n5032) );
NAND2X2TS U2021 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[102]), .Y(n5036) );
NOR2X1TS U2022 ( .A(n4103), .B(n1581), .Y(n4035) );
INVX6TS U2023 ( .A(n5988), .Y(n3023) );
NAND2X2TS U2024 ( .A(n3248), .B(n5363), .Y(n3140) );
CLKINVX2TS U2025 ( .A(n2460), .Y(n4693) );
NAND2X4TS U2026 ( .A(n5645), .B(n5344), .Y(n5347) );
NAND2X1TS U2027 ( .A(n5149), .B(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n4045) );
CLKINVX6TS U2028 ( .A(n5928), .Y(n3412) );
NOR2X4TS U2029 ( .A(n4552), .B(n4399), .Y(n4557) );
NOR2BX1TS U2030 ( .AN(n4240), .B(n3026), .Y(n3025) );
NOR2X1TS U2031 ( .A(n3974), .B(n3982), .Y(n3984) );
OAI21X2TS U2032 ( .A0(n5949), .A1(n1736), .B0(n5948), .Y(n2987) );
NOR2X2TS U2033 ( .A(n4399), .B(n1644), .Y(n4790) );
INVX4TS U2034 ( .A(n2565), .Y(n1616) );
INVX4TS U2035 ( .A(n4561), .Y(n1615) );
AND2X2TS U2036 ( .A(n5148), .B(n2743), .Y(n2655) );
NAND2X2TS U2037 ( .A(n5052), .B(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n5008) );
BUFX3TS U2038 ( .A(n3663), .Y(n5090) );
INVX6TS U2039 ( .A(n1770), .Y(n5207) );
INVX6TS U2040 ( .A(n3195), .Y(n5215) );
INVX2TS U2041 ( .A(n4314), .Y(n5693) );
NAND2X1TS U2042 ( .A(n1642), .B(n4196), .Y(n4605) );
NAND2X2TS U2043 ( .A(n5645), .B(n5281), .Y(n5286) );
NAND2X1TS U2044 ( .A(n2581), .B(n6241), .Y(n3537) );
NAND2X4TS U2045 ( .A(n5221), .B(n2977), .Y(n2891) );
OAI2BB1X2TS U2046 ( .A0N(n6010), .A1N(n4586), .B0(n3270), .Y(n4491) );
BUFX3TS U2047 ( .A(n5698), .Y(n5784) );
NAND2X1TS U2048 ( .A(n2729), .B(DmP[5]), .Y(n5504) );
BUFX4TS U2049 ( .A(n5698), .Y(n5732) );
NAND2X1TS U2050 ( .A(n4860), .B(n4859), .Y(n4866) );
OA21X2TS U2051 ( .A0(n4618), .A1(n4614), .B0(n4613), .Y(n5183) );
INVX2TS U2052 ( .A(n4547), .Y(n3309) );
NAND2X2TS U2053 ( .A(n5514), .B(n6003), .Y(n5172) );
BUFX6TS U2054 ( .A(n3408), .Y(n3237) );
NAND2X1TS U2055 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .Y(n3524) );
BUFX3TS U2056 ( .A(n5698), .Y(n3255) );
NAND2X1TS U2057 ( .A(n2729), .B(DmP[21]), .Y(n5285) );
OR2X2TS U2058 ( .A(n6053), .B(n6052), .Y(n2424) );
AO21X1TS U2059 ( .A0(n4758), .A1(n4763), .B0(n4527), .Y(n2495) );
NAND2X1TS U2060 ( .A(n5148), .B(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n5137) );
NAND2X1TS U2061 ( .A(n4849), .B(n4848), .Y(n4843) );
CLKINVX6TS U2062 ( .A(n4835), .Y(n4661) );
INVX2TS U2063 ( .A(n5923), .Y(n2838) );
NOR2X2TS U2064 ( .A(n3074), .B(n3077), .Y(n3073) );
CLKBUFX2TS U2065 ( .A(n4320), .Y(n2066) );
NAND2X4TS U2066 ( .A(n3353), .B(n3174), .Y(n1766) );
AND2X2TS U2067 ( .A(n2101), .B(n1656), .Y(n2155) );
AND4X4TS U2068 ( .A(n2961), .B(n2960), .C(n2959), .D(n2958), .Y(n2541) );
NAND2X1TS U2069 ( .A(n2754), .B(n2008), .Y(n5313) );
BUFX3TS U2070 ( .A(n4437), .Y(n2460) );
INVX2TS U2071 ( .A(n4746), .Y(n2457) );
NOR2X4TS U2072 ( .A(n1831), .B(n4646), .Y(n3462) );
INVX2TS U2073 ( .A(n2131), .Y(n6041) );
NAND2X1TS U2074 ( .A(n5506), .B(n2004), .Y(n5240) );
NAND2X2TS U2075 ( .A(n5639), .B(Add_Subt_result[8]), .Y(n5428) );
CLKINVX1TS U2076 ( .A(n4931), .Y(n4932) );
CLKINVX1TS U2077 ( .A(n1628), .Y(n1978) );
CLKINVX2TS U2078 ( .A(n4785), .Y(n3272) );
NOR2BX2TS U2079 ( .AN(n2582), .B(n3089), .Y(n3088) );
BUFX16TS U2080 ( .A(n2644), .Y(n2713) );
CLKINVX2TS U2081 ( .A(n6024), .Y(n4876) );
INVX2TS U2082 ( .A(n4632), .Y(n1797) );
INVX2TS U2083 ( .A(n4552), .Y(n4556) );
BUFX3TS U2084 ( .A(n5154), .Y(n5895) );
BUFX12TS U2085 ( .A(n5129), .Y(n5768) );
NAND2X4TS U2086 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[103]), .Y(n3192) );
CLKBUFX2TS U2087 ( .A(n5176), .Y(n1695) );
NAND2BX2TS U2088 ( .AN(n4361), .B(n2921), .Y(n2588) );
NAND2X2TS U2089 ( .A(n5434), .B(Add_Subt_result[3]), .Y(n5170) );
NAND2X2TS U2090 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(n4997) );
NAND3X6TS U2091 ( .A(n5320), .B(n5319), .C(n5318), .Y(n5616) );
NAND2X4TS U2092 ( .A(n5104), .B(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n3294) );
OR2X4TS U2093 ( .A(underflow_flag), .B(overflow_flag), .Y(n1624) );
NOR3X1TS U2094 ( .A(n3344), .B(n3553), .C(Add_Subt_result[9]), .Y(n3343) );
NOR2X2TS U2095 ( .A(n3128), .B(n4172), .Y(n3127) );
NAND2X2TS U2096 ( .A(n4462), .B(n4461), .Y(n4465) );
NAND2X2TS U2097 ( .A(n5639), .B(Add_Subt_result[6]), .Y(n5239) );
NAND2X2TS U2098 ( .A(n4763), .B(n4762), .Y(n4764) );
NAND2X2TS U2099 ( .A(n4731), .B(n4504), .Y(n4718) );
NAND2X2TS U2100 ( .A(n5102), .B(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n2949) );
AND2X4TS U2101 ( .A(n5906), .B(n4096), .Y(n4490) );
NAND2X2TS U2102 ( .A(n2581), .B(n6537), .Y(n3658) );
NAND2X2TS U2103 ( .A(n2581), .B(n6240), .Y(n4975) );
NAND2X2TS U2104 ( .A(n4746), .B(n4310), .Y(n3489) );
BUFX3TS U2105 ( .A(n4236), .Y(n1737) );
NAND2X2TS U2106 ( .A(n5942), .B(n4102), .Y(n5947) );
AOI21X2TS U2107 ( .A0(n1941), .A1(n4504), .B0(n4716), .Y(n4717) );
NAND2X2TS U2108 ( .A(n4087), .B(n4394), .Y(n3172) );
CLKBUFX2TS U2109 ( .A(n4690), .Y(n1736) );
CLKBUFX2TS U2110 ( .A(n4640), .Y(n1728) );
NAND2X2TS U2111 ( .A(n5148), .B(n2763), .Y(n5152) );
NAND2X2TS U2112 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(n5085) );
NAND2X2TS U2113 ( .A(ready), .B(n4892), .Y(n5978) );
CLKBUFX2TS U2114 ( .A(n4817), .Y(n1592) );
AOI21X2TS U2115 ( .A0(n1941), .A1(n4644), .B0(n4643), .Y(n4645) );
NAND2X1TS U2116 ( .A(n5103), .B(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .Y(n2815) );
CLKBUFX2TS U2117 ( .A(n4673), .Y(n2032) );
NAND2X2TS U2118 ( .A(n2725), .B(n2847), .Y(n5158) );
CLKAND2X2TS U2119 ( .A(n3453), .B(n3233), .Y(n2154) );
NAND2X2TS U2120 ( .A(n5052), .B(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n5014) );
NAND2X1TS U2121 ( .A(n2581), .B(n6245), .Y(n4988) );
BUFX16TS U2122 ( .A(n3663), .Y(n5104) );
INVX8TS U2123 ( .A(n4025), .Y(n4826) );
NAND2X2TS U2124 ( .A(n5149), .B(
Barrel_Shifter_module_Mux_Array_Data_array[56]), .Y(n2939) );
INVX2TS U2125 ( .A(n2656), .Y(n4533) );
INVX2TS U2126 ( .A(n4708), .Y(n4727) );
INVX2TS U2127 ( .A(n3999), .Y(n5177) );
BUFX16TS U2128 ( .A(n5103), .Y(n2724) );
INVX4TS U2129 ( .A(n4753), .Y(n4111) );
INVX8TS U2130 ( .A(n4507), .Y(n5963) );
NOR2X1TS U2131 ( .A(sign_final_result), .B(r_mode[1]), .Y(n4873) );
NAND2X1TS U2132 ( .A(n5506), .B(n1889), .Y(n5508) );
NAND2X1TS U2133 ( .A(n6238), .B(Add_Subt_result[1]), .Y(n3599) );
NAND2X2TS U2134 ( .A(n4788), .B(n4792), .Y(n3445) );
CLKINVX1TS U2135 ( .A(n4196), .Y(n2594) );
NAND2X4TS U2136 ( .A(n2515), .B(n3506), .Y(n4785) );
INVX2TS U2137 ( .A(n4663), .Y(n4683) );
OR2X2TS U2138 ( .A(n2832), .B(n6248), .Y(n3654) );
CLKINVX1TS U2139 ( .A(n4936), .Y(n4937) );
CLKBUFX2TS U2140 ( .A(n4947), .Y(n1838) );
BUFX6TS U2141 ( .A(n5934), .Y(n1722) );
NOR2X4TS U2142 ( .A(n2625), .B(n4733), .Y(n4736) );
NAND2X6TS U2143 ( .A(n5645), .B(n4376), .Y(n5289) );
NAND2X4TS U2144 ( .A(n4787), .B(n4792), .Y(n4563) );
NAND2X4TS U2145 ( .A(n1650), .B(n3207), .Y(n2341) );
BUFX3TS U2146 ( .A(n2475), .Y(n1672) );
CLKINVX2TS U2147 ( .A(n4470), .Y(n2198) );
INVX6TS U2148 ( .A(n1726), .Y(n4747) );
NOR2BX2TS U2149 ( .AN(n3067), .B(n4246), .Y(n3479) );
NAND2X2TS U2150 ( .A(n2581), .B(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n4970) );
NAND2X2TS U2151 ( .A(n3668), .B(n6242), .Y(n2933) );
BUFX12TS U2152 ( .A(n5282), .Y(n5516) );
NAND2X2TS U2153 ( .A(n2581), .B(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n4983) );
NAND2X4TS U2154 ( .A(n2756), .B(n5990), .Y(n5320) );
CLKBUFX2TS U2155 ( .A(n4814), .Y(n3216) );
NAND2X2TS U2156 ( .A(n5102), .B(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n2879) );
NAND2X2TS U2157 ( .A(n5149), .B(
Barrel_Shifter_module_Mux_Array_Data_array[55]), .Y(n2959) );
NAND2X2TS U2158 ( .A(n4087), .B(n4086), .Y(n3352) );
CLKAND2X2TS U2159 ( .A(n3552), .B(n6536), .Y(n3342) );
INVX2TS U2160 ( .A(n4395), .Y(n4310) );
NAND2X2TS U2161 ( .A(n2731), .B(n4394), .Y(n5276) );
OR2X2TS U2162 ( .A(n2832), .B(n6251), .Y(n4984) );
AOI21X2TS U2163 ( .A0(n4850), .A1(n4849), .B0(n4543), .Y(n4851) );
BUFX12TS U2164 ( .A(n5139), .Y(n1647) );
INVX4TS U2165 ( .A(n4103), .Y(n5942) );
NOR2X4TS U2166 ( .A(n3962), .B(n2342), .Y(n3964) );
INVX2TS U2167 ( .A(n1983), .Y(n4214) );
INVX4TS U2168 ( .A(n1740), .Y(n1757) );
AND2X6TS U2169 ( .A(n4628), .B(n4757), .Y(n2515) );
BUFX3TS U2170 ( .A(n4204), .Y(n3061) );
INVX2TS U2171 ( .A(n5291), .Y(n1664) );
AND2X6TS U2172 ( .A(n4024), .B(n4029), .Y(n1874) );
INVX2TS U2173 ( .A(n5336), .Y(n5918) );
CLKINVX2TS U2174 ( .A(n3890), .Y(n4203) );
NAND2X6TS U2175 ( .A(n1754), .B(n5406), .Y(n4582) );
BUFX16TS U2176 ( .A(n5321), .Y(n5645) );
OR2X6TS U2177 ( .A(n5055), .B(n6252), .Y(n3682) );
INVX6TS U2178 ( .A(n3477), .Y(n4025) );
OR2X2TS U2179 ( .A(n4514), .B(n4641), .Y(n2625) );
NOR2X6TS U2180 ( .A(n3574), .B(n1740), .Y(n5920) );
INVX4TS U2181 ( .A(n4521), .Y(n5969) );
INVX2TS U2182 ( .A(n4852), .Y(n3433) );
NAND2X4TS U2183 ( .A(n1650), .B(n5401), .Y(n5290) );
BUFX16TS U2184 ( .A(n3662), .Y(n2738) );
NAND3X1TS U2185 ( .A(n5912), .B(n1675), .C(n5911), .Y(n5913) );
BUFX16TS U2186 ( .A(n4043), .Y(n5101) );
INVX4TS U2187 ( .A(n4777), .Y(n4571) );
NOR2X6TS U2188 ( .A(n2538), .B(n6000), .Y(n5917) );
CLKBUFX2TS U2189 ( .A(n4195), .Y(n3163) );
INVX2TS U2190 ( .A(n4715), .Y(n4734) );
INVX3TS U2191 ( .A(n4730), .Y(n4733) );
BUFX3TS U2192 ( .A(n2482), .Y(n2025) );
CLKBUFX2TS U2193 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(
n2763) );
INVX2TS U2194 ( .A(n3945), .Y(n3993) );
INVX2TS U2195 ( .A(n5961), .Y(n5966) );
NOR2X6TS U2196 ( .A(n2848), .B(n2516), .Y(n4799) );
INVX2TS U2197 ( .A(n5153), .Y(n3291) );
INVX4TS U2198 ( .A(n4375), .Y(n4376) );
BUFX16TS U2199 ( .A(n5103), .Y(n5149) );
OA21X2TS U2200 ( .A0(n3991), .A1(n2723), .B0(n3949), .Y(n2493) );
CLKAND2X2TS U2201 ( .A(n6221), .B(n3598), .Y(n3246) );
OAI21X1TS U2202 ( .A0(n4934), .A1(n4936), .B0(n2924), .Y(n2204) );
BUFX12TS U2203 ( .A(n4101), .Y(n1581) );
BUFX4TS U2204 ( .A(n5989), .Y(n1686) );
NOR2X4TS U2205 ( .A(n1843), .B(n1984), .Y(n4875) );
INVX4TS U2206 ( .A(n4624), .Y(n4763) );
NOR2X4TS U2207 ( .A(n4083), .B(n4082), .Y(n4087) );
INVX3TS U2208 ( .A(n4545), .Y(n4749) );
INVX2TS U2209 ( .A(n4773), .Y(n4776) );
AND2X2TS U2210 ( .A(n4629), .B(n3345), .Y(n4784) );
NOR2X4TS U2211 ( .A(n4745), .B(n4549), .Y(n3483) );
NOR2BX1TS U2212 ( .AN(n5344), .B(n3579), .Y(n1756) );
NOR2BX1TS U2213 ( .AN(n4088), .B(n3351), .Y(n3350) );
BUFX6TS U2214 ( .A(n2581), .Y(n3668) );
BUFX6TS U2215 ( .A(n5129), .Y(n6019) );
NAND2XLTS U2216 ( .A(n4375), .B(n5281), .Y(n4085) );
NAND2X1TS U2217 ( .A(n4089), .B(n4099), .Y(n3351) );
INVX2TS U2218 ( .A(n6010), .Y(n4577) );
INVX6TS U2219 ( .A(n5515), .Y(n2723) );
CLKINVX2TS U2220 ( .A(n4729), .Y(n4730) );
BUFX3TS U2221 ( .A(n4471), .Y(n2085) );
CLKINVX6TS U2222 ( .A(n5261), .Y(n3248) );
INVX1TS U2223 ( .A(n4092), .Y(n3579) );
INVX4TS U2224 ( .A(n2883), .Y(n2639) );
INVX3TS U2225 ( .A(n2882), .Y(n2430) );
OR2X6TS U2226 ( .A(n3345), .B(n4629), .Y(n3506) );
INVX3TS U2227 ( .A(n4787), .Y(n1644) );
NAND2X2TS U2228 ( .A(n3954), .B(n3953), .Y(n3955) );
INVX4TS U2229 ( .A(n4354), .Y(n3146) );
INVX2TS U2230 ( .A(n6392), .Y(n1809) );
OAI21X2TS U2231 ( .A0(n4917), .A1(n6044), .B0(n4918), .Y(n3437) );
CLKBUFX3TS U2232 ( .A(n4809), .Y(n2654) );
NAND2X4TS U2233 ( .A(n4565), .B(n3436), .Y(n4631) );
CLKINVX3TS U2234 ( .A(n3527), .Y(n3513) );
BUFX6TS U2235 ( .A(n4827), .Y(n1598) );
BUFX4TS U2236 ( .A(n5983), .Y(n5506) );
OR2X4TS U2237 ( .A(n1649), .B(n2834), .Y(n2538) );
INVX2TS U2238 ( .A(n4072), .Y(n4378) );
NAND2X6TS U2239 ( .A(n1783), .B(n4406), .Y(n2857) );
INVX12TS U2240 ( .A(n3521), .Y(n5153) );
CLKINVX6TS U2241 ( .A(n3310), .Y(n3992) );
OR2X2TS U2242 ( .A(n4627), .B(n4762), .Y(n2488) );
NOR2X6TS U2243 ( .A(n4765), .B(n4769), .Y(n4757) );
NOR2X4TS U2244 ( .A(n3808), .B(n3881), .Y(n3884) );
OR2X4TS U2245 ( .A(n3969), .B(n1743), .Y(n3201) );
XNOR2X1TS U2246 ( .A(n2097), .B(n2260), .Y(n4137) );
BUFX8TS U2247 ( .A(n5056), .Y(n5052) );
NAND2X2TS U2248 ( .A(n3374), .B(n1654), .Y(n4626) );
BUFX4TS U2249 ( .A(n5983), .Y(n5452) );
INVX6TS U2250 ( .A(n5321), .Y(n2755) );
INVX4TS U2251 ( .A(n2683), .Y(n1843) );
NAND2X2TS U2252 ( .A(n2262), .B(n2846), .Y(n2845) );
NAND2X2TS U2253 ( .A(n4092), .B(n3580), .Y(n3574) );
INVX8TS U2254 ( .A(n5988), .Y(n6407) );
OAI21X1TS U2255 ( .A0(n6004), .A1(n4097), .B0(n4096), .Y(n4098) );
NAND2X1TS U2256 ( .A(n3958), .B(n3957), .Y(n3961) );
MXI2X2TS U2257 ( .A(n1907), .B(n2651), .S0(n1725), .Y(n2516) );
CLKINVX6TS U2258 ( .A(n5254), .Y(n4394) );
INVX6TS U2259 ( .A(n3951), .Y(n1612) );
INVX2TS U2260 ( .A(n5295), .Y(n5937) );
INVX2TS U2261 ( .A(n5992), .Y(n4077) );
BUFX3TS U2262 ( .A(n2777), .Y(n1673) );
INVX4TS U2263 ( .A(n5272), .Y(n5254) );
INVX4TS U2264 ( .A(n3549), .Y(n4485) );
NOR2X4TS U2265 ( .A(n4624), .B(n4627), .Y(n4628) );
CLKINVX6TS U2266 ( .A(n4081), .Y(n4021) );
NAND2X6TS U2267 ( .A(n4294), .B(n1630), .Y(n4296) );
NAND2X6TS U2268 ( .A(n4504), .B(n1774), .Y(n4519) );
NAND2X4TS U2269 ( .A(n3777), .B(n3741), .Y(n3780) );
NAND2X2TS U2270 ( .A(n6226), .B(n2428), .Y(n4849) );
INVX4TS U2271 ( .A(n2709), .Y(n4375) );
XNOR2X2TS U2272 ( .A(n2243), .B(n2397), .Y(n4178) );
XNOR2X2TS U2273 ( .A(n2127), .B(n2225), .Y(n4177) );
XNOR2X1TS U2274 ( .A(n2141), .B(n2405), .Y(n4117) );
XNOR2X1TS U2275 ( .A(n2164), .B(n2207), .Y(n4114) );
XNOR2X1TS U2276 ( .A(n2196), .B(intDY[45]), .Y(n4121) );
XNOR2X1TS U2277 ( .A(n2616), .B(n2436), .Y(n4158) );
XNOR2X1TS U2278 ( .A(n1916), .B(n2253), .Y(n4142) );
BUFX4TS U2279 ( .A(n5268), .Y(n1590) );
NAND2X6TS U2280 ( .A(n5274), .B(n5515), .Y(n2873) );
BUFX4TS U2281 ( .A(n5340), .Y(n1606) );
NAND2X2TS U2282 ( .A(n4525), .B(n4524), .Y(n4771) );
NAND2X6TS U2283 ( .A(n4404), .B(n4396), .Y(n4405) );
NAND2X4TS U2284 ( .A(n3244), .B(n1657), .Y(n3949) );
NOR2X6TS U2285 ( .A(n3555), .B(n3554), .Y(n3600) );
NAND2X6TS U2286 ( .A(n3318), .B(n3317), .Y(n3408) );
INVX4TS U2287 ( .A(n5344), .Y(n4091) );
XNOR2X1TS U2288 ( .A(n2114), .B(n2395), .Y(n4184) );
NAND2X2TS U2289 ( .A(n4566), .B(n4565), .Y(n4538) );
NOR2X4TS U2290 ( .A(n2619), .B(n4032), .Y(n4633) );
AND2X6TS U2291 ( .A(n4266), .B(n3123), .Y(n4634) );
INVX2TS U2292 ( .A(n1885), .Y(n1886) );
INVX2TS U2293 ( .A(n1923), .Y(n1924) );
OAI21X2TS U2294 ( .A0(n2678), .A1(n2316), .B0(n3519), .Y(n3515) );
INVX8TS U2295 ( .A(n4709), .Y(n4659) );
NOR2X4TS U2296 ( .A(n4542), .B(n6213), .Y(n4565) );
NAND2X4TS U2297 ( .A(n2849), .B(n2777), .Y(n3957) );
NAND2X6TS U2298 ( .A(n4437), .B(n3629), .Y(n4252) );
NAND2X4TS U2299 ( .A(n2049), .B(n3784), .Y(n3847) );
NAND2X2TS U2300 ( .A(n4515), .B(n4516), .Y(n4732) );
INVX6TS U2301 ( .A(n4106), .Y(n2979) );
NAND2X4TS U2302 ( .A(n3799), .B(n3865), .Y(n3866) );
NAND2X4TS U2303 ( .A(n3731), .B(n3751), .Y(n3754) );
INVX4TS U2304 ( .A(n3152), .Y(n3569) );
CLKINVX6TS U2305 ( .A(n2704), .Y(n1989) );
NAND2X4TS U2306 ( .A(n3703), .B(n3721), .Y(n3724) );
NAND2X4TS U2307 ( .A(n4278), .B(n4277), .Y(n4635) );
NAND2X4TS U2308 ( .A(n3803), .B(n3872), .Y(n3806) );
NAND2X2TS U2309 ( .A(n3733), .B(n3743), .Y(n3734) );
NOR2X6TS U2310 ( .A(n4265), .B(n4032), .Y(n5933) );
NAND2X4TS U2311 ( .A(n3825), .B(n3788), .Y(n3828) );
NOR2X4TS U2312 ( .A(n3546), .B(n3563), .Y(n3218) );
NAND2X4TS U2313 ( .A(n3347), .B(n4297), .Y(n4298) );
NOR2X6TS U2314 ( .A(n4301), .B(n4300), .Y(n5961) );
BUFX6TS U2315 ( .A(n3265), .Y(n1657) );
NAND2X4TS U2316 ( .A(n4301), .B(n4300), .Y(n5964) );
NAND2X6TS U2317 ( .A(n1602), .B(n3636), .Y(n3318) );
NAND2X6TS U2318 ( .A(n4510), .B(n4509), .Y(n4642) );
NAND2X4TS U2319 ( .A(n3233), .B(n3453), .Y(n4856) );
NAND2X2TS U2320 ( .A(n2704), .B(n5983), .Y(n3295) );
NAND2X2TS U2321 ( .A(n4065), .B(n2990), .Y(n4066) );
NAND2X4TS U2322 ( .A(n2767), .B(n3926), .Y(n2766) );
NAND2X2TS U2323 ( .A(n4250), .B(n4256), .Y(n4348) );
NAND2X2TS U2324 ( .A(n1952), .B(n4286), .Y(n4287) );
INVX12TS U2325 ( .A(n5496), .Y(n5515) );
BUFX16TS U2326 ( .A(n1661), .Y(n2874) );
INVX4TS U2327 ( .A(n1805), .Y(n4525) );
INVX6TS U2328 ( .A(n4276), .Y(n4297) );
INVX6TS U2329 ( .A(n3434), .Y(n3374) );
OR2X6TS U2330 ( .A(n1849), .B(n2087), .Y(n3876) );
INVX2TS U2331 ( .A(n1902), .Y(n1903) );
INVX6TS U2332 ( .A(n3373), .Y(n4558) );
BUFX6TS U2333 ( .A(n4094), .Y(n3152) );
INVX8TS U2334 ( .A(n2714), .Y(n2715) );
NOR2X6TS U2335 ( .A(n2603), .B(n1621), .Y(n3703) );
INVX6TS U2336 ( .A(n4271), .Y(n4289) );
NAND2X2TS U2337 ( .A(n4517), .B(n4506), .Y(n3427) );
INVX6TS U2338 ( .A(n4272), .Y(n4290) );
NAND2X4TS U2339 ( .A(n1661), .B(exp_oper_result[4]), .Y(n3215) );
NAND2X2TS U2340 ( .A(n4524), .B(n1805), .Y(n4532) );
NAND2X6TS U2341 ( .A(n3369), .B(n4249), .Y(n3493) );
NAND2X4TS U2342 ( .A(n4012), .B(n3154), .Y(n4392) );
INVX3TS U2343 ( .A(n5998), .Y(n3562) );
OR2X2TS U2344 ( .A(n2165), .B(n2207), .Y(n2267) );
NAND2X4TS U2345 ( .A(n3613), .B(n2614), .Y(n4411) );
NOR2X6TS U2346 ( .A(n3786), .B(n3823), .Y(n3825) );
INVX3TS U2347 ( .A(n4273), .Y(n4301) );
NOR2X6TS U2348 ( .A(n4227), .B(n3150), .Y(n4216) );
AND2X2TS U2349 ( .A(n4585), .B(n4867), .Y(n3325) );
NOR2X6TS U2350 ( .A(n4509), .B(n4502), .Y(n4395) );
OAI21X2TS U2351 ( .A0(n3766), .A1(n3765), .B0(n3764), .Y(n3772) );
INVX2TS U2352 ( .A(n2682), .Y(n2683) );
INVX4TS U2353 ( .A(n4505), .Y(n4516) );
OAI21X2TS U2354 ( .A0(n3710), .A1(n3711), .B0(n3709), .Y(n3712) );
NAND2X6TS U2355 ( .A(n4509), .B(n4502), .Y(n4402) );
NAND2X6TS U2356 ( .A(n2020), .B(n3003), .Y(n3649) );
NAND2X4TS U2357 ( .A(n4094), .B(n5905), .Y(n3560) );
NAND3X2TS U2358 ( .A(n3257), .B(n3927), .C(n1926), .Y(n2767) );
NOR2X2TS U2359 ( .A(n3692), .B(n3688), .Y(n3689) );
NOR2X2TS U2360 ( .A(n2824), .B(n2823), .Y(n2822) );
NOR2X6TS U2361 ( .A(n5206), .B(n3071), .Y(n4407) );
NOR2X4TS U2362 ( .A(n2907), .B(n2906), .Y(n3743) );
NAND2X4TS U2363 ( .A(n5164), .B(n3921), .Y(n3922) );
NAND2X2TS U2364 ( .A(n1663), .B(n2019), .Y(n3611) );
NOR2X4TS U2365 ( .A(n3871), .B(n3802), .Y(n3872) );
NOR2X4TS U2366 ( .A(n3795), .B(n3857), .Y(n3858) );
NOR2X4TS U2367 ( .A(n4678), .B(n5948), .Y(n3467) );
NOR2X4TS U2368 ( .A(n3702), .B(n3719), .Y(n3721) );
INVX4TS U2369 ( .A(n4266), .Y(n4278) );
AND2X6TS U2370 ( .A(n4522), .B(n4508), .Y(n2656) );
OR2X6TS U2371 ( .A(n4524), .B(n1805), .Y(n4500) );
INVX2TS U2372 ( .A(n2223), .Y(n2224) );
INVX2TS U2373 ( .A(n2320), .Y(n2279) );
NOR2X4TS U2374 ( .A(n4710), .B(n4655), .Y(n2983) );
AND2X6TS U2375 ( .A(n2942), .B(n2941), .Y(n4028) );
BUFX8TS U2376 ( .A(n4254), .Y(n3369) );
INVX4TS U2377 ( .A(n2212), .Y(n2213) );
AND2X4TS U2378 ( .A(n2235), .B(n2278), .Y(n3695) );
NAND2X2TS U2379 ( .A(n2246), .B(n2102), .Y(n3765) );
NAND2X2TS U2380 ( .A(n2252), .B(n2265), .Y(n3868) );
NOR2X6TS U2381 ( .A(n3612), .B(n3082), .Y(n5206) );
NAND2BX2TS U2382 ( .AN(n2060), .B(n2291), .Y(n3718) );
INVX4TS U2383 ( .A(n2635), .Y(n2909) );
INVX4TS U2384 ( .A(n2119), .Y(n2120) );
NAND2X6TS U2385 ( .A(n4271), .B(n4288), .Y(n5948) );
NOR2X6TS U2386 ( .A(n2195), .B(n2321), .Y(n3869) );
NOR2X6TS U2387 ( .A(n6000), .B(n6006), .Y(n3578) );
NAND2X4TS U2388 ( .A(n2420), .B(n3624), .Y(n4228) );
NAND2BX2TS U2389 ( .AN(n2178), .B(n2182), .Y(n3810) );
NAND2X2TS U2390 ( .A(n2248), .B(n2134), .Y(n3870) );
AND2X4TS U2391 ( .A(n2063), .B(n1873), .Y(n2603) );
NOR2X6TS U2392 ( .A(n3620), .B(n2065), .Y(n3622) );
OR2X4TS U2393 ( .A(n1916), .B(n2254), .Y(n3768) );
INVX2TS U2394 ( .A(n3511), .Y(n2895) );
NAND2X2TS U2395 ( .A(n2072), .B(n2391), .Y(n3852) );
NAND2X2TS U2396 ( .A(n2133), .B(n2180), .Y(n3863) );
NAND2X4TS U2397 ( .A(n4300), .B(n4273), .Y(n4477) );
NAND2X2TS U2398 ( .A(n2366), .B(n2099), .Y(n3819) );
NAND2X6TS U2399 ( .A(n4009), .B(n4008), .Y(n4827) );
NAND2X2TS U2400 ( .A(n2044), .B(n1850), .Y(n3853) );
NAND2X2TS U2401 ( .A(n2220), .B(n2304), .Y(n3764) );
INVX2TS U2402 ( .A(n2200), .Y(n2201) );
NAND2X2TS U2403 ( .A(n2163), .B(n2257), .Y(n3856) );
NOR2X2TS U2404 ( .A(n2364), .B(n2263), .Y(n3732) );
AND2X4TS U2405 ( .A(n2671), .B(Sgf_normalized_result[45]), .Y(n4503) );
NAND2X6TS U2406 ( .A(n1944), .B(n3205), .Y(n3197) );
NAND2X2TS U2407 ( .A(n2244), .B(n2397), .Y(n3862) );
NAND2X2TS U2408 ( .A(n2364), .B(n2263), .Y(n2910) );
NOR2X6TS U2409 ( .A(n4273), .B(n4300), .Y(n4361) );
NAND2X2TS U2410 ( .A(n2433), .B(n2626), .Y(n3690) );
NOR2X4TS U2411 ( .A(n5336), .B(n5340), .Y(n3329) );
NAND2X4TS U2412 ( .A(n3388), .B(n3973), .Y(n3387) );
NAND2X2TS U2413 ( .A(n2079), .B(n1854), .Y(n3756) );
NOR2X6TS U2414 ( .A(n2134), .B(n2248), .Y(n3802) );
NOR2X4TS U2415 ( .A(n1917), .B(n2253), .Y(n3736) );
NAND2X2TS U2416 ( .A(n3228), .B(n3985), .Y(n4001) );
NAND2X2TS U2417 ( .A(n2064), .B(n1872), .Y(n3716) );
NAND2X2TS U2418 ( .A(n2042), .B(n2403), .Y(n3715) );
NAND2X2TS U2419 ( .A(n4286), .B(n4270), .Y(n4104) );
NOR2X6TS U2420 ( .A(n3634), .B(n3221), .Y(n3319) );
INVX8TS U2421 ( .A(n2849), .Y(n2775) );
NAND2X2TS U2422 ( .A(n2375), .B(n2255), .Y(n2905) );
NAND2X2TS U2423 ( .A(n2617), .B(n2436), .Y(n2819) );
NOR2X6TS U2424 ( .A(n3306), .B(n4272), .Y(n4678) );
INVX6TS U2425 ( .A(n2665), .Y(n2278) );
NAND2X4TS U2426 ( .A(n2591), .B(n2590), .Y(n3509) );
INVX2TS U2427 ( .A(n2210), .Y(n2211) );
INVX4TS U2428 ( .A(n2380), .Y(n2381) );
BUFX16TS U2429 ( .A(n2850), .Y(n2866) );
INVX6TS U2430 ( .A(n3978), .Y(n3634) );
INVX6TS U2431 ( .A(n1743), .Y(n1651) );
NOR2X4TS U2432 ( .A(n2670), .B(n2170), .Y(n4273) );
OR2X6TS U2433 ( .A(n2428), .B(n3099), .Y(n2459) );
NAND2X6TS U2434 ( .A(n2916), .B(n2917), .Y(n3009) );
INVX6TS U2435 ( .A(n4005), .Y(n3642) );
NOR2X6TS U2436 ( .A(n4542), .B(n6206), .Y(n4508) );
BUFX8TS U2437 ( .A(n3986), .Y(n3228) );
NOR2X6TS U2438 ( .A(n6215), .B(n2428), .Y(n1805) );
NAND2X6TS U2439 ( .A(n1785), .B(n3007), .Y(n4243) );
NAND2X6TS U2440 ( .A(n4277), .B(n4266), .Y(n4724) );
AND2X4TS U2441 ( .A(n6276), .B(n6277), .Y(n2549) );
NOR2X6TS U2442 ( .A(n4249), .B(n4254), .Y(n4072) );
INVX12TS U2443 ( .A(n4913), .Y(n3046) );
INVX2TS U2444 ( .A(n4859), .Y(n3385) );
INVX8TS U2445 ( .A(n4267), .Y(n3371) );
NAND3X6TS U2446 ( .A(n6381), .B(n6382), .C(n6380), .Y(n5986) );
BUFX12TS U2447 ( .A(n4272), .Y(n1595) );
NOR2X4TS U2448 ( .A(n4618), .B(n4614), .Y(n3032) );
INVX4TS U2449 ( .A(n3977), .Y(n3633) );
INVX4TS U2450 ( .A(n3071), .Y(n3065) );
NAND2X2TS U2451 ( .A(n6356), .B(n6357), .Y(n3326) );
NAND2X6TS U2452 ( .A(n2641), .B(n4267), .Y(n4710) );
INVX4TS U2453 ( .A(n3975), .Y(n3631) );
NAND2X6TS U2454 ( .A(n1824), .B(n4060), .Y(n4775) );
NOR2X6TS U2455 ( .A(n5182), .B(n4222), .Y(n3029) );
NAND3X6TS U2456 ( .A(n6318), .B(n6319), .C(n6317), .Y(n5992) );
INVX3TS U2457 ( .A(n2033), .Y(n4275) );
INVX3TS U2458 ( .A(n4223), .Y(n3030) );
INVX2TS U2459 ( .A(n4613), .Y(n3034) );
NOR2X4TS U2460 ( .A(n4947), .B(n4818), .Y(n3904) );
MXI2X4TS U2461 ( .A(n6364), .B(n6363), .S0(n6362), .Y(n5268) );
NAND2X6TS U2462 ( .A(n2614), .B(n3905), .Y(n4461) );
AND2X6TS U2463 ( .A(n3615), .B(n3619), .Y(n1743) );
AND2X6TS U2464 ( .A(n2229), .B(n1997), .Y(n4266) );
BUFX8TS U2465 ( .A(n3257), .Y(n2897) );
INVX12TS U2466 ( .A(n2864), .Y(n2850) );
NOR2X6TS U2467 ( .A(n4542), .B(n6214), .Y(n4536) );
NAND2X4TS U2468 ( .A(n3978), .B(n3221), .Y(n4223) );
AND2X6TS U2469 ( .A(n6360), .B(n6361), .Y(n1626) );
INVX2TS U2470 ( .A(n2237), .Y(n2238) );
INVX1TS U2471 ( .A(n1935), .Y(n1936) );
INVX1TS U2472 ( .A(n1879), .Y(n1880) );
NOR2X6TS U2473 ( .A(n2125), .B(n2428), .Y(n4019) );
NAND2X6TS U2474 ( .A(n2972), .B(n2971), .Y(n3124) );
BUFX8TS U2475 ( .A(FSM_selector_B_1_), .Y(n1950) );
INVX6TS U2476 ( .A(n1871), .Y(n4002) );
NAND2X6TS U2477 ( .A(n3082), .B(n3612), .Y(n1574) );
NAND2X4TS U2478 ( .A(n2065), .B(n3972), .Y(n4859) );
INVX3TS U2479 ( .A(n1883), .Y(n1884) );
NAND2X6TS U2480 ( .A(n2671), .B(Sgf_normalized_result[40]), .Y(n2033) );
NAND2X6TS U2481 ( .A(n2992), .B(n2991), .Y(n1842) );
INVX6TS U2482 ( .A(n4010), .Y(n3003) );
NOR2X6TS U2483 ( .A(n3905), .B(n2614), .Y(n4421) );
CLKINVX6TS U2484 ( .A(n3331), .Y(n3330) );
INVX12TS U2485 ( .A(n3042), .Y(n4818) );
INVX8TS U2486 ( .A(n2176), .Y(n4268) );
INVX8TS U2487 ( .A(n2622), .Y(n4947) );
NOR2X4TS U2488 ( .A(n3323), .B(n2406), .Y(n2852) );
INVX6TS U2489 ( .A(n3392), .Y(n4004) );
BUFX8TS U2490 ( .A(n2864), .Y(n1575) );
INVX6TS U2491 ( .A(n1952), .Y(n4270) );
OR2X6TS U2492 ( .A(n1790), .B(n2630), .Y(n4918) );
CLKINVX2TS U2493 ( .A(n1898), .Y(n1899) );
INVX2TS U2494 ( .A(n2326), .Y(n2327) );
CLKINVX6TS U2495 ( .A(Sgf_normalized_result[0]), .Y(n1777) );
CLKINVX6TS U2496 ( .A(n3612), .Y(n3081) );
CLKINVX2TS U2497 ( .A(n1968), .Y(n1696) );
NAND2X4TS U2498 ( .A(n1742), .B(n1991), .Y(n2619) );
CLKINVX2TS U2499 ( .A(n2328), .Y(n2329) );
INVX2TS U2500 ( .A(n1958), .Y(n1959) );
BUFX16TS U2501 ( .A(n2428), .Y(n4542) );
INVX1TS U2502 ( .A(n2300), .Y(n2301) );
NAND2X2TS U2503 ( .A(n2422), .B(n2427), .Y(n1776) );
INVX2TS U2504 ( .A(n2631), .Y(n2632) );
INVX2TS U2505 ( .A(n1833), .Y(n1834) );
INVX3TS U2506 ( .A(n2169), .Y(n2170) );
INVX6TS U2507 ( .A(n3637), .Y(n2092) );
INVX2TS U2508 ( .A(n1976), .Y(n2350) );
INVX6TS U2509 ( .A(n3043), .Y(n2019) );
INVX4TS U2510 ( .A(n2671), .Y(n2184) );
NOR2X4TS U2511 ( .A(n3257), .B(n1812), .Y(n3918) );
INVX8TS U2512 ( .A(n3616), .Y(n3505) );
NAND2X6TS U2513 ( .A(n1810), .B(n1782), .Y(n1689) );
NOR2X6TS U2514 ( .A(n4036), .B(n1969), .Y(n4010) );
NAND2X4TS U2515 ( .A(n3211), .B(n1878), .Y(n3159) );
NAND2X4TS U2516 ( .A(n2229), .B(n1610), .Y(n2176) );
NOR2X6TS U2517 ( .A(Sgf_normalized_result[30]), .B(n3211), .Y(n3208) );
INVX2TS U2518 ( .A(n6339), .Y(n3333) );
NAND2X6TS U2519 ( .A(n2752), .B(n2022), .Y(n3040) );
BUFX4TS U2520 ( .A(n3971), .Y(n3210) );
INVX2TS U2521 ( .A(n3614), .Y(n1662) );
INVX2TS U2522 ( .A(n1610), .Y(n1611) );
NAND2X6TS U2523 ( .A(n1845), .B(n2669), .Y(n3624) );
OR2X6TS U2524 ( .A(n1846), .B(n2422), .Y(n2591) );
INVX2TS U2525 ( .A(n1973), .Y(n2351) );
CLKINVX2TS U2526 ( .A(n2693), .Y(n2694) );
NAND2X6TS U2527 ( .A(n1827), .B(n2669), .Y(n3613) );
CLKINVX2TS U2528 ( .A(n1877), .Y(n1878) );
INVX2TS U2529 ( .A(n1968), .Y(n1969) );
INVX3TS U2530 ( .A(n2021), .Y(n2022) );
INVX6TS U2531 ( .A(n1918), .Y(n2989) );
NAND2X6TS U2532 ( .A(n1742), .B(n2012), .Y(n3619) );
INVX3TS U2533 ( .A(n2146), .Y(n2147) );
INVX12TS U2534 ( .A(n3609), .Y(n1656) );
INVX3TS U2535 ( .A(n2124), .Y(n2125) );
NAND2X4TS U2536 ( .A(n1778), .B(n1913), .Y(n1779) );
INVX3TS U2537 ( .A(n2283), .Y(n2284) );
INVX6TS U2538 ( .A(n3901), .Y(n1659) );
NAND2X4TS U2539 ( .A(n3105), .B(n1930), .Y(n3104) );
INVX8TS U2540 ( .A(n4003), .Y(n3641) );
CLKBUFX3TS U2541 ( .A(n2324), .Y(n2325) );
NOR2X6TS U2542 ( .A(n2864), .B(n2047), .Y(n3235) );
NOR2X4TS U2543 ( .A(n2668), .B(n2090), .Y(n3971) );
INVX4TS U2544 ( .A(n1778), .Y(n1781) );
BUFX3TS U2545 ( .A(n1826), .Y(n1827) );
BUFX3TS U2546 ( .A(n2687), .Y(n2688) );
INVX2TS U2547 ( .A(n1997), .Y(n1998) );
INVX2TS U2548 ( .A(n1974), .Y(n2352) );
CLKINVX2TS U2549 ( .A(n1958), .Y(n1724) );
CLKINVX2TS U2550 ( .A(n1929), .Y(n1930) );
INVX2TS U2551 ( .A(n2215), .Y(n2216) );
NAND2X4TS U2552 ( .A(n2468), .B(n2330), .Y(n1596) );
INVX2TS U2553 ( .A(n1994), .Y(n1995) );
INVX4TS U2554 ( .A(n2470), .Y(n2471) );
NAND2X6TS U2555 ( .A(n1755), .B(n2007), .Y(n2971) );
NAND2X6TS U2556 ( .A(n2464), .B(n3394), .Y(n2911) );
INVX4TS U2557 ( .A(n2215), .Y(n1597) );
NAND2X4TS U2558 ( .A(n1980), .B(n1752), .Y(n1700) );
INVX6TS U2559 ( .A(n2425), .Y(n2426) );
INVX2TS U2560 ( .A(n2689), .Y(n2690) );
INVX2TS U2561 ( .A(n2691), .Y(n2692) );
CLKINVX2TS U2562 ( .A(n2339), .Y(n2340) );
INVX4TS U2563 ( .A(n2001), .Y(n2075) );
INVX8TS U2564 ( .A(n2461), .Y(n2462) );
INVX4TS U2565 ( .A(n1979), .Y(n1980) );
NAND2X6TS U2566 ( .A(n2670), .B(n2185), .Y(n2917) );
INVX4TS U2567 ( .A(n2138), .Y(n2139) );
INVX4TS U2568 ( .A(n2463), .Y(n2464) );
INVX3TS U2569 ( .A(n2143), .Y(n1579) );
INVX3TS U2570 ( .A(n2012), .Y(n2013) );
INVX2TS U2571 ( .A(n2167), .Y(n2168) );
NAND2X6TS U2572 ( .A(n1791), .B(n3323), .Y(n1788) );
INVX4TS U2573 ( .A(n3099), .Y(n2185) );
INVX4TS U2574 ( .A(n2083), .Y(n2084) );
INVX4TS U2575 ( .A(n2441), .Y(n1791) );
INVX6TS U2576 ( .A(n2450), .Y(n3099) );
NAND2X8TS U2577 ( .A(n4030), .B(n4029), .Y(n1710) );
CLKINVX12TS U2578 ( .A(n3452), .Y(n4026) );
NOR2X8TS U2579 ( .A(n2475), .B(n3640), .Y(n4321) );
NAND2X4TS U2580 ( .A(n2933), .B(n5054), .Y(n5138) );
NAND4X6TS U2581 ( .A(n4972), .B(n4971), .C(n4991), .D(n4970), .Y(n5879) );
NAND2X4TS U2582 ( .A(n1605), .B(n1604), .Y(n1491) );
AND2X6TS U2583 ( .A(n2786), .B(n3540), .Y(n2531) );
AOI22X2TS U2584 ( .A0(n5829), .A1(n2610), .B0(n2685), .B1(n5735), .Y(n4956)
);
AOI22X2TS U2585 ( .A0(n2887), .A1(n5578), .B0(n5579), .B1(n5680), .Y(n5246)
);
AOI22X2TS U2586 ( .A0(n2886), .A1(n5570), .B0(n5573), .B1(n5680), .Y(n5384)
);
AOI22X2TS U2587 ( .A0(n2676), .A1(n5682), .B0(n5681), .B1(n5680), .Y(n5690)
);
NAND4BX4TS U2588 ( .AN(n5652), .B(n5650), .C(n5649), .D(n5651), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
INVX4TS U2589 ( .A(n1948), .Y(n5649) );
NAND2X4TS U2590 ( .A(n2957), .B(n2955), .Y(n1442) );
NAND2X4TS U2591 ( .A(n5123), .B(n5122), .Y(n1464) );
AO22X4TS U2592 ( .A0(n5104), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[60]), .Y(n2623) );
AOI22X2TS U2593 ( .A0(n2677), .A1(n5558), .B0(n5603), .B1(n5559), .Y(n5544)
);
NAND3X8TS U2594 ( .A(n5377), .B(n5376), .C(n5375), .Y(n5559) );
NAND3X8TS U2595 ( .A(n5289), .B(n5288), .C(n5287), .Y(n5570) );
INVX6TS U2596 ( .A(n4696), .Y(n4699) );
AND3X4TS U2597 ( .A(n5890), .B(n3185), .C(n5076), .Y(n2490) );
NAND2X4TS U2598 ( .A(n5074), .B(n5194), .Y(n3185) );
BUFX12TS U2599 ( .A(n5427), .Y(n5630) );
BUFX12TS U2600 ( .A(n5427), .Y(n5648) );
BUFX12TS U2601 ( .A(n5427), .Y(n5688) );
BUFX12TS U2602 ( .A(n5427), .Y(n5661) );
AOI22X2TS U2603 ( .A0(n5532), .A1(n5478), .B0(n5579), .B1(n5630), .Y(n5479)
);
NAND3X8TS U2604 ( .A(n5172), .B(n5171), .C(n5170), .Y(n5478) );
AOI22X2TS U2605 ( .A0(n5116), .A1(n2722), .B0(n2006), .B1(n5140), .Y(n5117)
);
NAND3BX4TS U2606 ( .AN(n5979), .B(n3126), .C(n3125), .Y(n1558) );
INVX4TS U2607 ( .A(n5982), .Y(n3126) );
NAND2X8TS U2608 ( .A(n1657), .B(n4875), .Y(n6024) );
AOI22X2TS U2609 ( .A0(n5634), .A1(n5596), .B0(n5602), .B1(n2695), .Y(n5597)
);
AOI22X2TS U2610 ( .A0(n5685), .A1(n5686), .B0(n5683), .B1(n5670), .Y(n5675)
);
NAND3X8TS U2611 ( .A(n5059), .B(n5002), .C(n5001), .Y(n5700) );
OAI21X4TS U2612 ( .A0(n2424), .A1(n2155), .B0(n6041), .Y(n4916) );
AOI22X2TS U2613 ( .A0(n5627), .A1(n5656), .B0(n2758), .B1(n5629), .Y(n5540)
);
AOI22X2TS U2614 ( .A0(n5584), .A1(n5593), .B0(n5596), .B1(n5630), .Y(n5547)
);
AOI22X2TS U2615 ( .A0(n2673), .A1(n5593), .B0(n5603), .B1(n5592), .Y(n5599)
);
AOI22X2TS U2616 ( .A0(n5584), .A1(n5592), .B0(n5593), .B1(n5648), .Y(n5555)
);
AOI22X2TS U2617 ( .A0(n6050), .A1(n5683), .B0(n2889), .B1(n5686), .Y(n5553)
);
NAND4X4TS U2618 ( .A(n5034), .B(n5033), .C(n5032), .D(n5031), .Y(n5064) );
NAND3BX4TS U2619 ( .AN(n2795), .B(n5199), .C(n5198), .Y(n1466) );
MXI2X4TS U2620 ( .A(n4930), .B(n6258), .S0(n6405), .Y(n1507) );
AOI22X2TS U2621 ( .A0(n2676), .A1(n5656), .B0(n5628), .B1(n5671), .Y(n5552)
);
NAND3X8TS U2622 ( .A(n5513), .B(n5512), .C(n5511), .Y(n5656) );
NAND4X4TS U2623 ( .A(n5038), .B(n5037), .C(n5036), .D(n5035), .Y(n5065) );
AOI2BB2X2TS U2624 ( .B0(n2083), .B1(n5140), .A0N(n5783), .A1N(n5107), .Y(
n5094) );
AOI2BB2X2TS U2625 ( .B0(n2441), .B1(n3255), .A0N(n4966), .A1N(n5107), .Y(
n4967) );
INVX16TS U2626 ( .A(n5107), .Y(n4965) );
INVX12TS U2627 ( .A(n5364), .Y(n1650) );
NAND3X8TS U2628 ( .A(n3136), .B(n3129), .C(n3127), .Y(n6021) );
XNOR2X4TS U2629 ( .A(n4042), .B(n4041), .Y(n2506) );
AOI22X2TS U2630 ( .A0(n6050), .A1(n5672), .B0(n2758), .B1(n5671), .Y(n5531)
);
MXI2X2TS U2631 ( .A(n1852), .B(n6051), .S0(n5590), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[54]) );
AOI22X2TS U2632 ( .A0(n2759), .A1(n5683), .B0(n5590), .B1(n5682), .Y(n5523)
);
AOI22X2TS U2633 ( .A0(n5590), .A1(n5477), .B0(n2889), .B1(n2504), .Y(n5424)
);
NAND2X2TS U2634 ( .A(n5125), .B(n5885), .Y(n4050) );
OAI2BB1X4TS U2635 ( .A0N(n5851), .A1N(n2660), .B0(n5865), .Y(n1108) );
AOI22X1TS U2636 ( .A0(n5653), .A1(n5669), .B0(n2887), .B1(n5672), .Y(n5536)
);
AOI22X2TS U2637 ( .A0(n5627), .A1(n5686), .B0(n2889), .B1(n5669), .Y(n5638)
);
BUFX20TS U2638 ( .A(n5698), .Y(n5154) );
AOI22X2TS U2639 ( .A0(n5829), .A1(n2389), .B0(n2691), .B1(n5735), .Y(n5096)
);
AOI22X2TS U2640 ( .A0(n5829), .A1(n2063), .B0(n2689), .B1(n5735), .Y(n5097)
);
XNOR2X4TS U2641 ( .A(n4442), .B(n4441), .Y(n3500) );
OAI2BB1X4TS U2642 ( .A0N(n5851), .A1N(n2391), .B0(n5779), .Y(n1218) );
OAI2BB1X4TS U2643 ( .A0N(n5851), .A1N(n2099), .B0(n5134), .Y(n1205) );
OAI2BB1X4TS U2644 ( .A0N(n2243), .A1N(n5845), .B0(n5844), .Y(n1160) );
INVX16TS U2645 ( .A(n5391), .Y(n2672) );
NOR2X6TS U2646 ( .A(n5290), .B(n3248), .Y(n5391) );
AOI22X1TS U2647 ( .A0(n2760), .A1(n5570), .B0(n5573), .B1(n2698), .Y(n5351)
);
AOI22X2TS U2648 ( .A0(n2760), .A1(n5592), .B0(n5591), .B1(n5661), .Y(n5278)
);
AOI22X2TS U2649 ( .A0(n2760), .A1(n5561), .B0(n5560), .B1(n2699), .Y(n5542)
);
AOI22X2TS U2650 ( .A0(n2760), .A1(n2505), .B0(n5609), .B1(n2701), .Y(n5456)
);
AOI22X2TS U2651 ( .A0(n2760), .A1(n5568), .B0(n5569), .B1(n2700), .Y(n5378)
);
NAND2X8TS U2652 ( .A(n2936), .B(n2935), .Y(n4969) );
NAND3X8TS U2653 ( .A(n5449), .B(n5450), .C(n5451), .Y(n5618) );
AOI22X2TS U2654 ( .A0(n2674), .A1(n5617), .B0(n5603), .B1(n5619), .Y(n5489)
);
NAND2X2TS U2655 ( .A(n5571), .B(n5382), .Y(n5301) );
OAI2BB1X4TS U2656 ( .A0N(n5845), .A1N(n2263), .B0(n5734), .Y(n1185) );
AOI22X2TS U2657 ( .A0(n2674), .A1(n5610), .B0(n5628), .B1(n5621), .Y(n5458)
);
INVX16TS U2658 ( .A(n2672), .Y(n2674) );
BUFX20TS U2659 ( .A(n6031), .Y(n4911) );
NAND2X4TS U2660 ( .A(n2756), .B(n6008), .Y(n5308) );
BUFX20TS U2661 ( .A(n4965), .Y(n2722) );
MX2X4TS U2662 ( .A(n5928), .B(exp_oper_result[3]), .S0(n6406), .Y(n1435) );
NAND2X2TS U2663 ( .A(n4919), .B(n4918), .Y(n4920) );
AOI22X2TS U2664 ( .A0(n2760), .A1(n5616), .B0(n5615), .B1(n2698), .Y(n5546)
);
AOI22X2TS U2665 ( .A0(n2676), .A1(n5592), .B0(n5596), .B1(n2698), .Y(n5399)
);
AOI22X2TS U2666 ( .A0(n5590), .A1(n5610), .B0(n5477), .B1(n2698), .Y(n5438)
);
AOI22X2TS U2667 ( .A0(n5673), .A1(n5629), .B0(n5633), .B1(n2698), .Y(n5550)
);
NAND3X8TS U2668 ( .A(n5265), .B(n5266), .C(n5267), .Y(n5591) );
AOI22X2TS U2669 ( .A0(n2675), .A1(n5591), .B0(n5594), .B1(n2697), .Y(n5402)
);
AOI22X2TS U2670 ( .A0(n2674), .A1(n5594), .B0(n5593), .B1(n2697), .Y(n5280)
);
AOI22X2TS U2671 ( .A0(n5532), .A1(n5477), .B0(n5243), .B1(n2697), .Y(n5244)
);
AOI22X2TS U2672 ( .A0(n5829), .A1(n2202), .B0(DMP[8]), .B1(n5735), .Y(n5188)
);
AOI22X2TS U2673 ( .A0(n5590), .A1(n5632), .B0(n2759), .B1(n5541), .Y(n5381)
);
NAND3X8TS U2674 ( .A(n5374), .B(n5373), .C(n2017), .Y(n5541) );
AOI22X2TS U2675 ( .A0(n5584), .A1(n5669), .B0(n5672), .B1(n5630), .Y(n5551)
);
NAND3X8TS U2676 ( .A(n5502), .B(n5501), .C(n5500), .Y(n5672) );
NAND3X6TS U2677 ( .A(n3535), .B(n2659), .C(n3536), .Y(n4978) );
AOI22X2TS U2678 ( .A0(n2759), .A1(n5579), .B0(n5477), .B1(n5648), .Y(n5235)
);
NAND3X8TS U2679 ( .A(n5169), .B(n5168), .C(n1633), .Y(n5477) );
NAND4X4TS U2680 ( .A(n5358), .B(n5360), .C(n5361), .D(n5359), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
AOI22X2TS U2681 ( .A0(n2675), .A1(n5567), .B0(n5532), .B1(n5569), .Y(n5360)
);
AOI22X2TS U2682 ( .A0(n2759), .A1(n2505), .B0(n5609), .B1(n5668), .Y(n5439)
);
AOI22X2TS U2683 ( .A0(n5673), .A1(n5558), .B0(n5561), .B1(n2700), .Y(n5537)
);
AOI22X2TS U2684 ( .A0(n5688), .A1(n5416), .B0(n6050), .B1(n5572), .Y(n2214)
);
AOI22X2TS U2685 ( .A0(n6050), .A1(n5619), .B0(n2758), .B1(n5617), .Y(n5459)
);
AOI22X2TS U2686 ( .A0(n2759), .A1(n5416), .B0(n6050), .B1(n5573), .Y(n5419)
);
AOI22X2TS U2687 ( .A0(n5584), .A1(n5686), .B0(n5669), .B1(n5648), .Y(n5521)
);
NAND3X8TS U2688 ( .A(n5503), .B(n5504), .C(n5505), .Y(n5686) );
AOI22X2TS U2689 ( .A0(n2761), .A1(n5541), .B0(n5559), .B1(n2701), .Y(n5528)
);
AOI22X2TS U2690 ( .A0(n2673), .A1(n5559), .B0(n5603), .B1(n5541), .Y(n5539)
);
AOI22X2TS U2691 ( .A0(n5584), .A1(n5541), .B0(n5559), .B1(n5648), .Y(n5411)
);
BUFX20TS U2692 ( .A(n5401), .Y(n2977) );
NAND2BX4TS U2693 ( .AN(n5889), .B(n2877), .Y(n2876) );
XNOR2X2TS U2694 ( .A(n4916), .B(n4915), .Y(n4923) );
NAND2X2TS U2695 ( .A(n5415), .B(n5414), .Y(n5420) );
AOI22X2TS U2696 ( .A0(n2760), .A1(n5593), .B0(n5595), .B1(n5661), .Y(n5397)
);
NAND2X4TS U2697 ( .A(n2756), .B(n5998), .Y(n5241) );
AOI22X2TS U2698 ( .A0(n5655), .A1(n5632), .B0(n5541), .B1(n5670), .Y(n5543)
);
AOI22X2TS U2699 ( .A0(n2760), .A1(n5632), .B0(n5541), .B1(n2699), .Y(n5533)
);
AOI22X2TS U2700 ( .A0(n5655), .A1(n5633), .B0(n5632), .B1(n5661), .Y(n5538)
);
AOI22X2TS U2701 ( .A0(n2673), .A1(n5541), .B0(n5603), .B1(n5632), .Y(n5526)
);
AOI22X2TS U2702 ( .A0(n2761), .A1(n5633), .B0(n5632), .B1(n2697), .Y(n5635)
);
AO22X2TS U2703 ( .A0(n3261), .A1(n2143), .B0(final_result_ieee[4]), .B1(
n4910), .Y(n1410) );
NAND2X4TS U2704 ( .A(n2973), .B(n2285), .Y(n1578) );
AOI21X2TS U2705 ( .A0(n5694), .A1(n4704), .B0(n4703), .Y(n4707) );
AOI21X4TS U2706 ( .A0(n5694), .A1(n4440), .B0(n4439), .Y(n4442) );
AOI21X4TS U2707 ( .A0(n5694), .A1(n2449), .B0(n4235), .Y(n4238) );
AOI21X4TS U2708 ( .A0(n5694), .A1(n4221), .B0(n4220), .Y(n4226) );
AOI22X2TS U2709 ( .A0(n5476), .A1(n2698), .B0(n5627), .B1(n5609), .Y(n5482)
);
AOI22X2TS U2710 ( .A0(n5634), .A1(n5672), .B0(n5671), .B1(n2697), .Y(n5674)
);
NAND3X8TS U2711 ( .A(n5499), .B(n5498), .C(n5497), .Y(n5671) );
INVX16TS U2712 ( .A(n2696), .Y(n2697) );
AOI22X2TS U2713 ( .A0(n2889), .A1(n5591), .B0(n5590), .B1(n5589), .Y(n5600)
);
AOI22X2TS U2714 ( .A0(n2677), .A1(n5632), .B0(n5628), .B1(n5633), .Y(n5530)
);
NAND3X8TS U2715 ( .A(n5409), .B(n5408), .C(n5407), .Y(n5633) );
NAND4X4TS U2716 ( .A(n4055), .B(n4054), .C(n4053), .D(n4052), .Y(n5144) );
OR2X8TS U2717 ( .A(n5055), .B(n6250), .Y(n4971) );
AND3X6TS U2718 ( .A(n3630), .B(n2951), .C(n2950), .Y(n3648) );
NAND3X4TS U2719 ( .A(n2881), .B(n2880), .C(n2879), .Y(n2878) );
NAND4X4TS U2720 ( .A(n3666), .B(n3665), .C(n3664), .D(n2571), .Y(n5115) );
INVX4TS U2721 ( .A(n2655), .Y(n3665) );
NAND2X2TS U2722 ( .A(n5189), .B(n2664), .Y(n5000) );
AOI22X2TS U2723 ( .A0(n5685), .A1(n5684), .B0(n5683), .B1(n5673), .Y(n5689)
);
NAND2X8TS U2724 ( .A(n5492), .B(n5491), .Y(n5683) );
NAND2X4TS U2725 ( .A(n5145), .B(n2421), .Y(n3535) );
AOI22X2TS U2726 ( .A0(n5685), .A1(n5595), .B0(n5668), .B1(n5589), .Y(n5277)
);
AOI22X2TS U2727 ( .A0(n5655), .A1(n5687), .B0(n5684), .B1(n5648), .Y(n5650)
);
NAND3X8TS U2728 ( .A(n5093), .B(n5092), .C(n5091), .Y(n5781) );
AOI22X2TS U2729 ( .A0(n2761), .A1(n5608), .B0(n5578), .B1(n2699), .Y(n5469)
);
AOI22X2TS U2730 ( .A0(n2759), .A1(n5608), .B0(n5578), .B1(n5680), .Y(n5480)
);
AOI22X2TS U2731 ( .A0(n5634), .A1(n5478), .B0(n5608), .B1(n5670), .Y(n5440)
);
NAND2X2TS U2732 ( .A(n5653), .B(n5478), .Y(n5173) );
AOI22X2TS U2733 ( .A0(n5653), .A1(n5561), .B0(n2886), .B1(n5560), .Y(n5354)
);
AOI22X2TS U2734 ( .A0(n5653), .A1(n5570), .B0(n5628), .B1(n5589), .Y(n5405)
);
NAND2X4TS U2735 ( .A(n5415), .B(n5382), .Y(n5385) );
NAND2X8TS U2736 ( .A(n3141), .B(n3140), .Y(n5415) );
AOI22X2TS U2737 ( .A0(n5663), .A1(n5559), .B0(n5558), .B1(n2700), .Y(n5524)
);
NAND3X8TS U2738 ( .A(n5357), .B(n5356), .C(n5355), .Y(n5558) );
INVX16TS U2739 ( .A(n1634), .Y(n2700) );
NAND2X4TS U2740 ( .A(n2581), .B(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n3532) );
NAND2X2TS U2741 ( .A(n2581), .B(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n3653) );
BUFX20TS U2742 ( .A(n5849), .Y(n5736) );
NOR2X6TS U2743 ( .A(n4071), .B(n4070), .Y(n4074) );
AOI22X2TS U2744 ( .A0(n5631), .A1(n5560), .B0(n5568), .B1(n5688), .Y(n5359)
);
NAND3X8TS U2745 ( .A(n5343), .B(n5342), .C(n5341), .Y(n5560) );
AOI22X2TS U2746 ( .A0(n5584), .A1(n5619), .B0(n5617), .B1(n5648), .Y(n5465)
);
NAND3X8TS U2747 ( .A(n5324), .B(n5323), .C(n5322), .Y(n5619) );
AOI22X2TS U2748 ( .A0(n2677), .A1(n5579), .B0(n5654), .B1(n5578), .Y(n5441)
);
NAND3X8TS U2749 ( .A(n5232), .B(n5231), .C(n5230), .Y(n5578) );
INVX16TS U2750 ( .A(n2672), .Y(n2677) );
AOI22X2TS U2751 ( .A0(n2761), .A1(n5601), .B0(n5616), .B1(n2701), .Y(n5554)
);
AOI22X2TS U2752 ( .A0(n5631), .A1(n5602), .B0(n5601), .B1(n5688), .Y(n5333)
);
AOI22X2TS U2753 ( .A0(n5668), .A1(n5601), .B0(n5616), .B1(n5661), .Y(n5329)
);
AOI22X2TS U2754 ( .A0(n2674), .A1(n5601), .B0(n5628), .B1(n5602), .Y(n5548)
);
AOI22X2TS U2755 ( .A0(n2712), .A1(n5602), .B0(n2886), .B1(n5601), .Y(n5607)
);
NOR2X8TS U2756 ( .A(n1852), .B(n5153), .Y(n4993) );
INVX8TS U2757 ( .A(n6054), .Y(n3608) );
NAND2X4TS U2758 ( .A(n5718), .B(n5719), .Y(n1486) );
AND3X6TS U2759 ( .A(n4572), .B(n4571), .C(n4570), .Y(n3503) );
XNOR2X4TS U2760 ( .A(n5696), .B(n2073), .Y(n3499) );
INVX16TS U2761 ( .A(n4940), .Y(n4043) );
NAND4X4TS U2762 ( .A(n5080), .B(n5079), .C(n5078), .D(n5077), .Y(n5195) );
AOI21X4TS U2763 ( .A0(n4245), .A1(n4243), .B0(n3910), .Y(n3913) );
AOI22X2TS U2764 ( .A0(n2761), .A1(n5602), .B0(n5601), .B1(n2697), .Y(n5483)
);
NAND2X2TS U2765 ( .A(n5052), .B(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n5023) );
NAND2X4TS U2766 ( .A(n5052), .B(n6244), .Y(n3680) );
NAND2X4TS U2767 ( .A(n5052), .B(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(n5002) );
NAND2X4TS U2768 ( .A(n5052), .B(n2742), .Y(n3516) );
NAND2X2TS U2769 ( .A(n5052), .B(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n5019) );
NAND2X4TS U2770 ( .A(n5052), .B(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n5004) );
NAND2X4TS U2771 ( .A(n5052), .B(n6239), .Y(n5053) );
NAND2X4TS U2772 ( .A(n5052), .B(
Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(n5028) );
AOI22X2TS U2773 ( .A0(n5631), .A1(n5596), .B0(n5602), .B1(n5630), .Y(n5473)
);
NAND3X8TS U2774 ( .A(n5305), .B(n5304), .C(n5303), .Y(n5602) );
AOI22X2TS U2775 ( .A0(n5590), .A1(n5559), .B0(n2758), .B1(n5558), .Y(n5565)
);
INVX16TS U2776 ( .A(n2888), .Y(n2758) );
OAI21X4TS U2777 ( .A0(n4702), .A1(n4693), .B0(n4696), .Y(n4439) );
NAND2X2TS U2778 ( .A(n6045), .B(n6044), .Y(n6046) );
AOI22X2TS U2779 ( .A0(n2673), .A1(n5596), .B0(n5654), .B1(n5593), .Y(n5485)
);
NAND3X8TS U2780 ( .A(n5251), .B(n5252), .C(n5253), .Y(n5593) );
BUFX20TS U2781 ( .A(n5386), .Y(n5654) );
NAND2X4TS U2782 ( .A(n4814), .B(n3048), .Y(n3012) );
BUFX20TS U2783 ( .A(n3512), .Y(n5055) );
AOI22X2TS U2784 ( .A0(n5639), .A1(n5997), .B0(n1925), .B1(n2723), .Y(n5641)
);
NAND3X6TS U2785 ( .A(n5161), .B(n5160), .C(n3923), .Y(n3959) );
NAND2X4TS U2786 ( .A(n5750), .B(n2783), .Y(n2782) );
INVX8TS U2787 ( .A(n2469), .Y(n4933) );
NAND4X6TS U2788 ( .A(n3683), .B(n3682), .C(n4991), .D(n3681), .Y(n5121) );
NAND4X8TS U2789 ( .A(n3513), .B(n2639), .C(n2430), .D(n3256), .Y(n4991) );
XOR2X4TS U2790 ( .A(n4950), .B(n4949), .Y(n4954) );
NAND3BX4TS U2791 ( .AN(n2574), .B(n5084), .C(n5085), .Y(n2899) );
NAND2X4TS U2792 ( .A(n5148), .B(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .Y(n2960) );
AOI22X2TS U2793 ( .A0(n5627), .A1(n5579), .B0(n2887), .B1(n5478), .Y(n5226)
);
AOI2BB2X2TS U2794 ( .B0(n2596), .B1(n2399), .A0N(n2039), .A1N(n1922), .Y(
n5798) );
AOI2BB2X2TS U2795 ( .B0(n2596), .B1(n2119), .A0N(n1990), .A1N(n1914), .Y(
n5799) );
AOI22X2TS U2796 ( .A0(n2596), .A1(n2117), .B0(n2693), .B1(n5735), .Y(n5098)
);
AOI22X2TS U2797 ( .A0(n2596), .A1(n2369), .B0(n2687), .B1(n5735), .Y(n5100)
);
OAI2BB1X2TS U2798 ( .A0N(n2664), .A1N(n5720), .B0(n5012), .Y(n1453) );
AOI22X1TS U2799 ( .A0(n5662), .A1(n5620), .B0(n2758), .B1(n5619), .Y(n5588)
);
AOI22X2TS U2800 ( .A0(n2675), .A1(n5620), .B0(n5603), .B1(n5615), .Y(n5330)
);
AOI22X2TS U2801 ( .A0(n5653), .A1(n5615), .B0(n2758), .B1(n5620), .Y(n5467)
);
AOI22X2TS U2802 ( .A0(n5655), .A1(n5615), .B0(n5620), .B1(n5670), .Y(n5488)
);
OAI2BB1X2TS U2803 ( .A0N(n3229), .A1N(n2387), .B0(n5188), .Y(n1177) );
AOI22X2TS U2804 ( .A0(n6021), .A1(n3229), .B0(n6019), .B1(intDX_63_), .Y(
n3249) );
OAI2BB1X2TS U2805 ( .A0N(n2403), .A1N(n1599), .B0(n5099), .Y(n1182) );
OAI2BB1X2TS U2806 ( .A0N(n1599), .A1N(n2665), .B0(n5737), .Y(n1176) );
OAI2BB1X2TS U2807 ( .A0N(n1599), .A1N(n2356), .B0(n4956), .Y(n1178) );
OAI2BB1X2TS U2808 ( .A0N(n1599), .A1N(n2399), .B0(n5096), .Y(n1180) );
OAI2BB1X2TS U2809 ( .A0N(n1599), .A1N(n1872), .B0(n5097), .Y(n1181) );
INVX12TS U2810 ( .A(n5679), .Y(n5590) );
NAND2X2TS U2811 ( .A(n5321), .B(n1686), .Y(n5314) );
NAND2X2TS U2812 ( .A(n5321), .B(n5992), .Y(n5455) );
OAI2BB1X4TS U2813 ( .A0N(n2182), .A1N(n2734), .B0(n5131), .Y(n1201) );
OAI2BB1X4TS U2814 ( .A0N(n2405), .A1N(n2734), .B0(n5135), .Y(n1202) );
OAI2BB1X4TS U2815 ( .A0N(n2304), .A1N(n2734), .B0(n5204), .Y(n1198) );
OAI2BB1X4TS U2816 ( .A0N(n2041), .A1N(n2734), .B0(n5806), .Y(n1118) );
OAI2BB1X4TS U2817 ( .A0N(n2293), .A1N(n2734), .B0(n5130), .Y(n1200) );
NAND2X4TS U2818 ( .A(n4906), .B(n4905), .Y(n1559) );
AOI22X2TS U2819 ( .A0(n5655), .A1(n5595), .B0(n5594), .B1(n5670), .Y(n5598)
);
NAND3X8TS U2820 ( .A(n5250), .B(n5249), .C(n5248), .Y(n5594) );
OAI2BB1X4TS U2821 ( .A0N(n2384), .A1N(n5827), .B0(n5816), .Y(n1142) );
OAI2BB1X4TS U2822 ( .A0N(n2376), .A1N(n5827), .B0(n5132), .Y(n1204) );
OAI2BB1X4TS U2823 ( .A0N(n5827), .A1N(n2380), .B0(n5864), .Y(n1111) );
NAND3X4TS U2824 ( .A(n3111), .B(n3115), .C(n3114), .Y(n6485) );
AOI22X2TS U2825 ( .A0(n2758), .A1(n5602), .B0(n5590), .B1(n5596), .Y(n5331)
);
NAND2X2TS U2826 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n2571) );
NAND2X6TS U2827 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[104]), .Y(n3187) );
OAI2BB1X4TS U2828 ( .A0N(n5873), .A1N(n2334), .B0(n5758), .Y(n1208) );
OAI2BB1X4TS U2829 ( .A0N(n5873), .A1N(n2087), .B0(n5769), .Y(n1168) );
OAI2BB1X4TS U2830 ( .A0N(n5873), .A1N(n1854), .B0(n5857), .Y(n1193) );
OAI2BB1X4TS U2831 ( .A0N(n5873), .A1N(n2180), .B0(n5791), .Y(n1223) );
OAI2BB1X4TS U2832 ( .A0N(n5876), .A1N(n2223), .B0(n5776), .Y(n1228) );
OAI2BB1X4TS U2833 ( .A0N(n5876), .A1N(n2320), .B0(n5755), .Y(n1210) );
OAI2BB1X4TS U2834 ( .A0N(n5876), .A1N(n2200), .B0(n5772), .Y(n1230) );
OAI2BB1X4TS U2835 ( .A0N(n5729), .A1N(n2397), .B0(n5770), .Y(n1224) );
OAI2BB1X4TS U2836 ( .A0N(n5729), .A1N(n2156), .B0(n5861), .Y(n1189) );
OAI2BB1X4TS U2837 ( .A0N(n5729), .A1N(n2447), .B0(n5724), .Y(n1169) );
NAND2BX4TS U2838 ( .AN(n1875), .B(n2953), .Y(n2951) );
BUFX20TS U2839 ( .A(n3271), .Y(n2953) );
OAI2BB1X2TS U2840 ( .A0N(n1599), .A1N(n2287), .B0(n5100), .Y(n1184) );
OAI2BB1X4TS U2841 ( .A0N(n2158), .A1N(n5856), .B0(n5804), .Y(n1125) );
NOR2X6TS U2842 ( .A(n1740), .B(n3556), .Y(n2314) );
OAI2BB1X2TS U2843 ( .A0N(n1599), .A1N(n2119), .B0(n5098), .Y(n1179) );
NAND2X4TS U2844 ( .A(n2952), .B(n4253), .Y(n4345) );
NAND2X4TS U2845 ( .A(n2725), .B(n6002), .Y(n5448) );
NOR3X6TS U2846 ( .A(n6002), .B(n5995), .C(n6005), .Y(n4094) );
MXI2X4TS U2847 ( .A(n4962), .B(n4961), .S0(n6060), .Y(n4963) );
XOR2X4TS U2848 ( .A(n5215), .B(n4960), .Y(n4961) );
OAI21X2TS U2849 ( .A0(n4212), .A1(n6063), .B0(n3217), .Y(n1517) );
BUFX12TS U2850 ( .A(n6031), .Y(n4907) );
INVX6TS U2851 ( .A(n3118), .Y(n3109) );
OAI2BB1X4TS U2852 ( .A0N(n5831), .A1N(n2105), .B0(n5753), .Y(n1130) );
AOI22X2TS U2853 ( .A0(n5102), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n5150), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n5017) );
MXI2X8TS U2854 ( .A(n5365), .B(n5362), .S0(n3207), .Y(n5571) );
OR2X4TS U2855 ( .A(n5055), .B(n6241), .Y(n5027) );
AO22X4TS U2856 ( .A0(n5829), .A1(n2212), .B0(DmP[26]), .B1(n5820), .Y(n1928)
);
NOR2X4TS U2857 ( .A(n5919), .B(Add_Subt_result[16]), .Y(n3327) );
NAND2X8TS U2858 ( .A(n3418), .B(n3417), .Y(n3416) );
AOI22X2TS U2859 ( .A0(n5104), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .Y(n5010) );
NAND2X6TS U2860 ( .A(n6220), .B(n1617), .Y(n3446) );
BUFX20TS U2861 ( .A(n4398), .Y(n1726) );
NAND2X4TS U2862 ( .A(n3395), .B(n2168), .Y(n3107) );
NOR2X8TS U2863 ( .A(n2094), .B(n2223), .Y(n3871) );
INVX8TS U2864 ( .A(n2093), .Y(n2094) );
NAND2X6TS U2865 ( .A(n4649), .B(n4283), .Y(n4663) );
NOR2X6TS U2866 ( .A(n3735), .B(n3766), .Y(n3737) );
BUFX12TS U2867 ( .A(n2703), .Y(n1951) );
INVX16TS U2868 ( .A(n2779), .Y(n3265) );
AND2X8TS U2869 ( .A(n1575), .B(n1909), .Y(n2778) );
NAND2X4TS U2870 ( .A(n2857), .B(n2853), .Y(n3164) );
BUFX8TS U2871 ( .A(n3394), .Y(n2993) );
INVX12TS U2872 ( .A(n1574), .Y(n1628) );
INVX12TS U2873 ( .A(n1576), .Y(n4913) );
NAND2X8TS U2874 ( .A(n1790), .B(n3899), .Y(n1576) );
NAND2X8TS U2875 ( .A(n1787), .B(n1788), .Y(n1790) );
NOR2X8TS U2876 ( .A(n1593), .B(n4817), .Y(n3048) );
NOR2X8TS U2877 ( .A(n1829), .B(n3607), .Y(n4817) );
INVX12TS U2878 ( .A(n3044), .Y(n3011) );
NAND3X8TS U2879 ( .A(n1577), .B(n3017), .C(n3012), .Y(n2423) );
NAND3X8TS U2880 ( .A(n2553), .B(n3047), .C(n3013), .Y(n1577) );
INVX16TS U2881 ( .A(n6451), .Y(n2973) );
NAND2X6TS U2882 ( .A(n2923), .B(n2920), .Y(n2919) );
BUFX20TS U2883 ( .A(n1752), .Y(n1755) );
INVX6TS U2884 ( .A(n1828), .Y(n2446) );
OAI21X4TS U2885 ( .A0(n2973), .A1(n1579), .B0(n1578), .Y(n1828) );
NAND2X8TS U2886 ( .A(n2589), .B(n2586), .Y(n2585) );
NAND2X8TS U2887 ( .A(n1580), .B(n3371), .Y(n4652) );
INVX4TS U2888 ( .A(n3440), .Y(n1580) );
NAND2X8TS U2889 ( .A(n3441), .B(n3442), .Y(n3440) );
INVX12TS U2890 ( .A(n4061), .Y(n4065) );
NOR2X8TS U2891 ( .A(n2641), .B(n3371), .Y(n4650) );
CLKINVX12TS U2892 ( .A(n2797), .Y(n1725) );
NOR2X6TS U2893 ( .A(n1635), .B(n4405), .Y(n2856) );
NAND3X6TS U2894 ( .A(n3033), .B(n3028), .C(n3031), .Y(n3027) );
CLKINVX12TS U2895 ( .A(n4000), .Y(n1642) );
BUFX20TS U2896 ( .A(n2861), .Y(n2858) );
NAND2X8TS U2897 ( .A(n4107), .B(n4362), .Y(n3451) );
NAND2X8TS U2898 ( .A(n1582), .B(n3456), .Y(n1783) );
NAND2X8TS U2899 ( .A(n2979), .B(n3239), .Y(n1582) );
XOR2X4TS U2900 ( .A(n1583), .B(n1652), .Y(n4544) );
NAND2X8TS U2901 ( .A(n3426), .B(n1584), .Y(n1583) );
NAND2X8TS U2902 ( .A(n1713), .B(n3428), .Y(n1671) );
XOR2X4TS U2903 ( .A(n1585), .B(n1832), .Y(n5973) );
OAI2BB1X4TS U2904 ( .A0N(n5970), .A1N(n3050), .B0(n1640), .Y(n1585) );
NAND2X8TS U2905 ( .A(n5943), .B(n3470), .Y(n3468) );
NOR2X8TS U2906 ( .A(n1659), .B(n2451), .Y(n3184) );
MXI2X8TS U2907 ( .A(n2462), .B(n2075), .S0(n2465), .Y(n2451) );
INVX8TS U2908 ( .A(n4105), .Y(n4037) );
NAND2X8TS U2909 ( .A(n4037), .B(n1983), .Y(n3469) );
NAND2X4TS U2910 ( .A(n1828), .B(n3902), .Y(n4948) );
BUFX3TS U2911 ( .A(n3448), .Y(n1586) );
BUFX3TS U2912 ( .A(n4251), .Y(n1587) );
INVX12TS U2913 ( .A(n1588), .Y(n2522) );
NAND2X8TS U2914 ( .A(n3454), .B(n3453), .Y(n1588) );
XOR2X4TS U2915 ( .A(n1589), .B(n2303), .Y(n4786) );
NAND2X6TS U2916 ( .A(n1716), .B(n3155), .Y(n1589) );
NAND2X8TS U2917 ( .A(n4581), .B(n2845), .Y(n2844) );
XOR2X4TS U2918 ( .A(n1591), .B(n4311), .Y(n4312) );
OAI2BB1X4TS U2919 ( .A0N(n4309), .A1N(n3050), .B0(n2166), .Y(n1591) );
INVX16TS U2920 ( .A(n2942), .Y(n3390) );
AOI21X4TS U2921 ( .A0(n2912), .A1(n2911), .B0(n1663), .Y(n1593) );
NAND3X6TS U2922 ( .A(n3401), .B(n3400), .C(n3399), .Y(n6486) );
OAI21X4TS U2923 ( .A0(n2468), .A1(n1597), .B0(n1596), .Y(n3986) );
NOR2X8TS U2924 ( .A(n4541), .B(n2464), .Y(n3903) );
INVX6TS U2925 ( .A(n6451), .Y(n2229) );
NAND3X6TS U2926 ( .A(n1798), .B(n3368), .C(n1796), .Y(n1795) );
NOR2X8TS U2927 ( .A(n4528), .B(n4845), .Y(n3224) );
OAI2BB1X4TS U2928 ( .A0N(n2389), .A1N(n5856), .B0(n5798), .Y(n1116) );
OAI2BB1X4TS U2929 ( .A0N(n2117), .A1N(n5831), .B0(n5799), .Y(n1115) );
AOI21X4TS U2930 ( .A0(n1600), .A1(n3713), .B0(n3712), .Y(n3725) );
OAI21X4TS U2931 ( .A0(n2517), .A1(n3708), .B0(n3707), .Y(n1600) );
OAI2BB1X4TS U2932 ( .A0N(n5873), .A1N(n2343), .B0(n5757), .Y(n1206) );
NOR2X8TS U2933 ( .A(n4694), .B(n2177), .Y(n3629) );
NAND2X6TS U2934 ( .A(n3154), .B(n3626), .Y(n3459) );
NOR2X8TS U2935 ( .A(n2943), .B(n2944), .Y(n3154) );
INVX16TS U2936 ( .A(n1601), .Y(n1661) );
NAND2X8TS U2937 ( .A(n3927), .B(n3511), .Y(n1601) );
OAI21X4TS U2938 ( .A0(n4228), .A1(n3150), .B0(n3632), .Y(n1602) );
INVX16TS U2939 ( .A(n3181), .Y(n3898) );
INVX8TS U2940 ( .A(n3947), .Y(n3952) );
OR2X8TS U2941 ( .A(n1603), .B(n3438), .Y(n1944) );
NOR3X8TS U2942 ( .A(n4917), .B(n6043), .C(n6056), .Y(n3438) );
OAI21X4TS U2943 ( .A0(n4917), .A1(n6044), .B0(n4918), .Y(n1603) );
NOR2X6TS U2944 ( .A(n2546), .B(n6360), .Y(n3328) );
AND2X8TS U2945 ( .A(n2427), .B(n2441), .Y(n3899) );
OR2X8TS U2946 ( .A(n1752), .B(n1975), .Y(n1727) );
INVX4TS U2947 ( .A(n2276), .Y(n1984) );
NOR2BX4TS U2948 ( .AN(n5745), .B(n2794), .Y(n1604) );
NOR2X8TS U2949 ( .A(n2110), .B(n2320), .Y(n3830) );
NAND2X4TS U2950 ( .A(n3713), .B(n3705), .Y(n3706) );
AO22X4TS U2951 ( .A0(n3269), .A1(n1854), .B0(DmP[24]), .B1(n5871), .Y(n2302)
);
NOR2X4TS U2952 ( .A(n2203), .B(n2387), .Y(n3704) );
NAND2X8TS U2953 ( .A(n2422), .B(DMP[14]), .Y(n2590) );
NOR2X8TS U2954 ( .A(n3616), .B(n3167), .Y(n3071) );
XOR2X4TS U2955 ( .A(n1607), .B(n3651), .Y(n6404) );
OAI21X4TS U2956 ( .A0(n2306), .A1(n2307), .B0(n2308), .Y(n1607) );
CLKINVX12TS U2957 ( .A(n2297), .Y(n1608) );
INVX16TS U2958 ( .A(n1608), .Y(n1609) );
MXI2X2TS U2959 ( .A(n4452), .B(n1590), .S0(n3023), .Y(n6456) );
NOR3X6TS U2960 ( .A(n3337), .B(n5925), .C(n2537), .Y(n3336) );
AND2X6TS U2961 ( .A(n2276), .B(n2682), .Y(n3120) );
NAND2X6TS U2962 ( .A(n2575), .B(n2644), .Y(n2862) );
NAND2X6TS U2963 ( .A(n2644), .B(n4499), .Y(n3428) );
NAND3X6TS U2964 ( .A(n1688), .B(n2903), .C(n4348), .Y(n3006) );
OAI2BB1X4TS U2965 ( .A0N(n6254), .A1N(n6212), .B0(n1754), .Y(n3340) );
INVX12TS U2966 ( .A(n2726), .Y(n2727) );
INVX8TS U2967 ( .A(n3166), .Y(n3951) );
OR2X6TS U2968 ( .A(n4760), .B(n4845), .Y(n3406) );
INVX12TS U2969 ( .A(n4845), .Y(n1643) );
NOR2X6TS U2970 ( .A(n1718), .B(n1717), .Y(n1716) );
NOR2X6TS U2971 ( .A(n1738), .B(n4093), .Y(n4579) );
INVX6TS U2972 ( .A(n2647), .Y(n1738) );
XOR2X4TS U2973 ( .A(n2806), .B(n1613), .Y(n2805) );
XOR2X4TS U2974 ( .A(n3491), .B(n1614), .Y(n4794) );
NAND2X8TS U2975 ( .A(n3009), .B(n2459), .Y(n4931) );
INVX8TS U2976 ( .A(n3443), .Y(n1617) );
INVX12TS U2977 ( .A(n3395), .Y(n3443) );
NAND2X2TS U2978 ( .A(n2242), .B(n2354), .Y(n3822) );
NAND2X2TS U2979 ( .A(n2370), .B(n2287), .Y(n3717) );
AND2X2TS U2980 ( .A(n5984), .B(n6237), .Y(n2846) );
AND2X2TS U2981 ( .A(n1849), .B(n2087), .Y(n3875) );
NOR2X4TS U2982 ( .A(n3814), .B(n3790), .Y(n3816) );
NAND2X2TS U2983 ( .A(n4290), .B(n3306), .Y(n4291) );
XNOR2X1TS U2984 ( .A(n2610), .B(n2356), .Y(n4167) );
XNOR2X1TS U2985 ( .A(n2247), .B(n2134), .Y(n4175) );
NAND2X2TS U2986 ( .A(n2941), .B(n3390), .Y(n3627) );
INVX4TS U2987 ( .A(n2006), .Y(n2007) );
XNOR2X1TS U2988 ( .A(n2034), .B(n2212), .Y(n4146) );
INVX12TS U2989 ( .A(n2031), .Y(n4535) );
INVX4TS U2990 ( .A(n2685), .Y(n2686) );
INVX2TS U2991 ( .A(n2515), .Y(n4838) );
AOI21X1TS U2992 ( .A0(n2199), .A1(n5966), .B0(n5965), .Y(n5967) );
OA21XLTS U2993 ( .A0(n5213), .A1(n5208), .B0(n5209), .Y(n2145) );
NAND2X2TS U2994 ( .A(n3976), .B(n3631), .Y(n3632) );
INVX2TS U2995 ( .A(n5214), .Y(n4958) );
OR2X1TS U2996 ( .A(n4982), .B(n6244), .Y(n4985) );
AO21X2TS U2997 ( .A0(n4342), .A1(n4331), .B0(n4330), .Y(n2969) );
INVX2TS U2998 ( .A(n2277), .Y(n4456) );
OR2X4TS U2999 ( .A(n4100), .B(n4596), .Y(n1761) );
INVX2TS U3000 ( .A(n5669), .Y(n1949) );
NAND2X2TS U3001 ( .A(n5516), .B(n6000), .Y(n5337) );
AND2X2TS U3002 ( .A(n4601), .B(n1912), .Y(n5970) );
OA21X2TS U3003 ( .A0(n4753), .A1(n4547), .B0(n4546), .Y(n4548) );
OR2X1TS U3004 ( .A(n4982), .B(n6537), .Y(n3655) );
OR2X2TS U3005 ( .A(n2832), .B(n6239), .Y(n5058) );
NAND2X2TS U3006 ( .A(n5516), .B(n5993), .Y(n5517) );
NAND2X2TS U3007 ( .A(n2756), .B(n6001), .Y(n5311) );
NAND2X1TS U3008 ( .A(n5452), .B(n1896), .Y(n5168) );
NAND2X1TS U3009 ( .A(n2754), .B(DmP[49]), .Y(n5171) );
NAND2X2TS U3010 ( .A(n4490), .B(n4487), .Y(n3575) );
CLKINVX3TS U3011 ( .A(n5874), .Y(n1990) );
AND2X2TS U3012 ( .A(n4246), .B(n5988), .Y(n2492) );
NOR2X1TS U3013 ( .A(n3023), .B(n4246), .Y(n3022) );
INVX4TS U3014 ( .A(n5820), .Y(n2360) );
NOR2X2TS U3015 ( .A(n4900), .B(n5515), .Y(n5981) );
AND2X2TS U3016 ( .A(n1982), .B(n4679), .Y(n5951) );
INVX4TS U3017 ( .A(n5196), .Y(n2664) );
AO21X2TS U3018 ( .A0(n3288), .A1(n3292), .B0(n5196), .Y(n2884) );
NAND2X1TS U3019 ( .A(n5877), .B(n5897), .Y(n5882) );
INVX6TS U3020 ( .A(n2190), .Y(n2191) );
INVX2TS U3021 ( .A(n2260), .Y(n2261) );
INVX6TS U3022 ( .A(n2387), .Y(n2388) );
INVX2TS U3023 ( .A(n2333), .Y(n2126) );
NOR2X1TS U3024 ( .A(n5980), .B(n5981), .Y(n3125) );
CLKINVX6TS U3025 ( .A(n1429), .Y(n6034) );
NAND2X1TS U3026 ( .A(n2781), .B(n3659), .Y(n2793) );
NAND2BX1TS U3027 ( .AN(n5942), .B(n2599), .Y(n2597) );
BUFX4TS U3028 ( .A(n6033), .Y(n6035) );
NAND2X1TS U3029 ( .A(n5124), .B(n5885), .Y(n4049) );
AOI22X1TS U3030 ( .A0(n5233), .A1(n5222), .B0(n5688), .B1(n2504), .Y(n5227)
);
AND2X8TS U3031 ( .A(n6358), .B(n6359), .Y(n1620) );
AND2X8TS U3032 ( .A(n2041), .B(n2404), .Y(n1621) );
XOR2X1TS U3033 ( .A(n6037), .B(n6057), .Y(n1622) );
AND2X6TS U3034 ( .A(n3395), .B(n2170), .Y(n1623) );
NAND2X4TS U3035 ( .A(n2756), .B(n5348), .Y(n1625) );
MXI2X4TS U3036 ( .A(n1886), .B(n6208), .S0(n2866), .Y(n1627) );
INVX2TS U3037 ( .A(n1945), .Y(n1946) );
AOI22X1TS U3038 ( .A0(n3269), .A1(n2172), .B0(n1970), .B1(n5825), .Y(n1629)
);
AND2X8TS U3039 ( .A(n3366), .B(n2564), .Y(n1630) );
INVX2TS U3040 ( .A(n2172), .Y(n2173) );
AND2X8TS U3041 ( .A(n1661), .B(n1961), .Y(n1632) );
INVX2TS U3042 ( .A(n4473), .Y(n1733) );
INVX6TS U3043 ( .A(n5139), .Y(n5196) );
OR2X8TS U3044 ( .A(n5421), .B(n5242), .Y(n1634) );
INVX2TS U3045 ( .A(n4553), .Y(n5954) );
NAND2X1TS U3046 ( .A(n2622), .B(n4948), .Y(n4951) );
AND2X8TS U3047 ( .A(n3448), .B(n3451), .Y(n1635) );
OA22X4TS U3048 ( .A0(n3617), .A1(n4411), .B0(n1662), .B1(n1706), .Y(n1636)
);
AND3X6TS U3049 ( .A(n3188), .B(n3187), .C(n3186), .Y(n1637) );
NAND2X2TS U3050 ( .A(n3294), .B(n3293), .Y(n1638) );
OA21X2TS U3051 ( .A0(n4753), .A1(n2457), .B0(n1635), .Y(n1639) );
OA21X4TS U3052 ( .A0(n1831), .A1(n5968), .B0(n5967), .Y(n1640) );
NOR2X4TS U3053 ( .A(n3395), .B(n1945), .Y(n1729) );
NAND4X8TS U3054 ( .A(n2982), .B(n2980), .C(n2981), .D(n4709), .Y(n1665) );
OAI2BB1X2TS U3055 ( .A0N(n2734), .A1N(n2194), .B0(n5840), .Y(n1162) );
NAND2X6TS U3056 ( .A(n1643), .B(n1797), .Y(n1796) );
NOR2X4TS U3057 ( .A(n3471), .B(n5971), .Y(n2562) );
NAND2X2TS U3058 ( .A(n5747), .B(n2664), .Y(n2869) );
INVX2TS U3059 ( .A(n4391), .Y(n1800) );
NAND2X6TS U3060 ( .A(n5144), .B(n5885), .Y(n4058) );
NAND2X2TS U3061 ( .A(n4978), .B(n1647), .Y(n4981) );
INVX4TS U3062 ( .A(n1693), .Y(n4778) );
INVX3TS U3063 ( .A(n2052), .Y(n5605) );
NAND2X2TS U3064 ( .A(n5887), .B(n2753), .Y(n5888) );
NAND2X2TS U3065 ( .A(n3445), .B(n4791), .Y(n3444) );
MXI2X2TS U3066 ( .A(n4924), .B(n6235), .S0(n6405), .Y(n1506) );
INVX12TS U3067 ( .A(n5972), .Y(n1641) );
AO22X2TS U3068 ( .A0(n3262), .A1(n2146), .B0(final_result_ieee[27]), .B1(
n4908), .Y(n1387) );
INVX2TS U3069 ( .A(n4788), .Y(n4789) );
AO22X2TS U3070 ( .A0(n3262), .A1(Sgf_normalized_result[30]), .B0(
final_result_ieee[28]), .B1(n4908), .Y(n1386) );
NAND2X2TS U3071 ( .A(n3162), .B(n2654), .Y(n4810) );
AO22X2TS U3072 ( .A0(n3262), .A1(n2631), .B0(final_result_ieee[29]), .B1(
n4908), .Y(n1385) );
AO22X2TS U3073 ( .A0(n3262), .A1(n1687), .B0(final_result_ieee[26]), .B1(
n4890), .Y(n1388) );
BUFX12TS U3074 ( .A(n5566), .Y(n5680) );
INVX2TS U3075 ( .A(n5592), .Y(n2680) );
NAND2X2TS U3076 ( .A(n6063), .B(n6010), .Y(n6452) );
NAND2X4TS U3077 ( .A(n5589), .B(n3207), .Y(n3141) );
BUFX12TS U3078 ( .A(n5566), .Y(n5631) );
AO22X2TS U3079 ( .A0(n3260), .A1(n2283), .B0(final_result_ieee[22]), .B1(
n4890), .Y(n1392) );
NAND3X6TS U3080 ( .A(n2488), .B(n3001), .C(n4626), .Y(n4836) );
AO22X2TS U3081 ( .A0(n3260), .A1(n2215), .B0(final_result_ieee[19]), .B1(
n4890), .Y(n1395) );
NAND2X6TS U3082 ( .A(n2550), .B(n2515), .Y(n4632) );
AO22X2TS U3083 ( .A0(n3260), .A1(n2006), .B0(final_result_ieee[18]), .B1(
n4890), .Y(n1396) );
NAND2X6TS U3084 ( .A(n1647), .B(n3290), .Y(n1820) );
AO22X2TS U3085 ( .A0(n3260), .A1(n2470), .B0(final_result_ieee[17]), .B1(
n4890), .Y(n1397) );
BUFX12TS U3086 ( .A(n5566), .Y(n5655) );
BUFX8TS U3087 ( .A(n3231), .Y(n2421) );
BUFX20TS U3088 ( .A(n6407), .Y(n6405) );
NOR2X2TS U3089 ( .A(n1705), .B(n6218), .Y(n1702) );
INVX2TS U3090 ( .A(n1646), .Y(n1811) );
INVX2TS U3091 ( .A(n2827), .Y(n5243) );
INVX3TS U3092 ( .A(n5177), .Y(n3982) );
INVX8TS U3093 ( .A(n3291), .Y(n3290) );
INVX2TS U3094 ( .A(n3098), .Y(n4822) );
NAND2X6TS U3095 ( .A(n4202), .B(n3064), .Y(n3623) );
NAND2X6TS U3096 ( .A(n5906), .B(n4098), .Y(n4580) );
NOR2X2TS U3097 ( .A(n1705), .B(n1704), .Y(n1703) );
INVX2TS U3098 ( .A(n4465), .Y(n4463) );
AND2X2TS U3099 ( .A(n4755), .B(n3427), .Y(n2011) );
INVX8TS U3100 ( .A(n5927), .Y(n1648) );
INVX2TS U3101 ( .A(n4199), .Y(n1685) );
BUFX4TS U3102 ( .A(n4216), .Y(n2449) );
INVX2TS U3103 ( .A(n4612), .Y(n5181) );
INVX6TS U3104 ( .A(n5768), .Y(n5874) );
INVX12TS U3105 ( .A(n5768), .Y(n5820) );
NAND2X6TS U3106 ( .A(n2989), .B(n3097), .Y(n2799) );
INVX2TS U3107 ( .A(n4533), .Y(n1714) );
INVX2TS U3108 ( .A(n5732), .Y(n1705) );
NAND2X6TS U3109 ( .A(n3007), .B(n3909), .Y(n4239) );
AND2X2TS U3110 ( .A(n5154), .B(n1883), .Y(n2479) );
NAND2X6TS U3111 ( .A(n4004), .B(n1839), .Y(n4606) );
NAND2X2TS U3112 ( .A(n3139), .B(n3138), .Y(n3137) );
INVX2TS U3113 ( .A(n2452), .Y(n4620) );
NAND2X6TS U3114 ( .A(n3641), .B(n4004), .Y(n4428) );
NAND2X4TS U3115 ( .A(n1655), .B(n3619), .Y(n3894) );
INVX12TS U3116 ( .A(n3615), .Y(n1655) );
NAND2X6TS U3117 ( .A(n3805), .B(n3876), .Y(n3878) );
INVX6TS U3118 ( .A(n4508), .Y(n4523) );
INVX3TS U3119 ( .A(n3619), .Y(n3911) );
NAND2X6TS U3120 ( .A(n6055), .B(n6054), .Y(n6056) );
NOR2X4TS U3121 ( .A(n3738), .B(n3757), .Y(n3739) );
INVX12TS U3122 ( .A(n1984), .Y(n1985) );
NOR2X4TS U3123 ( .A(n3729), .B(n3746), .Y(n3731) );
INVX4TS U3124 ( .A(n2059), .Y(n1706) );
NOR2X4TS U3125 ( .A(n3874), .B(n3804), .Y(n3805) );
INVX8TS U3126 ( .A(n3981), .Y(n3637) );
INVX2TS U3127 ( .A(n5991), .Y(n4096) );
INVX8TS U3128 ( .A(n1848), .Y(n1849) );
AND2X4TS U3129 ( .A(n6372), .B(n6371), .Y(n2315) );
OA21X2TS U3130 ( .A0(n6397), .A1(n6396), .B0(n6395), .Y(n1821) );
INVX2TS U3131 ( .A(n1937), .Y(n1938) );
INVX2TS U3132 ( .A(n1894), .Y(n1895) );
INVX3TS U3133 ( .A(n1955), .Y(n1956) );
INVX2TS U3134 ( .A(n2650), .Y(n2651) );
INVX2TS U3135 ( .A(n1906), .Y(n1907) );
INVX4TS U3136 ( .A(n2107), .Y(n2108) );
INVX8TS U3137 ( .A(n2105), .Y(n2106) );
INVX1TS U3138 ( .A(n2009), .Y(n2010) );
INVX2TS U3139 ( .A(n2413), .Y(n2414) );
INVX2TS U3140 ( .A(n1910), .Y(n1911) );
INVX4TS U3141 ( .A(n2178), .Y(n2179) );
INVX8TS U3142 ( .A(n2205), .Y(n2206) );
INVX2TS U3143 ( .A(n2346), .Y(n2347) );
INVX4TS U3144 ( .A(n1850), .Y(n1851) );
INVX2TS U3145 ( .A(n2076), .Y(n2077) );
INVX6TS U3146 ( .A(n2151), .Y(n2152) );
INVX6TS U3147 ( .A(n1992), .Y(n1993) );
NAND2X4TS U3148 ( .A(n3398), .B(n3405), .Y(n3400) );
NAND3X4TS U3149 ( .A(n2604), .B(n3069), .C(n2606), .Y(n1519) );
XNOR2X2TS U3150 ( .A(n4226), .B(n4225), .Y(n2509) );
NAND2X4TS U3151 ( .A(n1800), .B(n1803), .Y(n1802) );
NAND2X2TS U3152 ( .A(n2869), .B(n2871), .Y(n1449) );
NAND2X4TS U3153 ( .A(n4247), .B(n3022), .Y(n3021) );
NAND2X2TS U3154 ( .A(n5731), .B(n2664), .Y(n5006) );
NAND2X2TS U3155 ( .A(n5115), .B(n5885), .Y(n2577) );
NAND2X4TS U3156 ( .A(n2898), .B(n5194), .Y(n5088) );
NOR2X4TS U3157 ( .A(n4826), .B(n2966), .Y(n1804) );
NAND2X2TS U3158 ( .A(n5064), .B(n5194), .Y(n5041) );
NAND2X2TS U3159 ( .A(n5064), .B(n2662), .Y(n5068) );
NAND2X2TS U3160 ( .A(n2781), .B(n5785), .Y(n2790) );
NAND2X2TS U3161 ( .A(n2781), .B(n5744), .Y(n2794) );
NAND2X2TS U3162 ( .A(n2781), .B(n5739), .Y(n2796) );
NAND2X2TS U3163 ( .A(n2781), .B(n3529), .Y(n2785) );
AO22X2TS U3164 ( .A0(n3262), .A1(Sgf_normalized_result[26]), .B0(
final_result_ieee[24]), .B1(n4910), .Y(n1390) );
AO22X2TS U3165 ( .A0(n3262), .A1(n2124), .B0(final_result_ieee[25]), .B1(
n4890), .Y(n1389) );
INVX4TS U3166 ( .A(n5616), .Y(n2681) );
NAND2X4TS U3167 ( .A(n1874), .B(n4383), .Y(n4385) );
INVX2TS U3168 ( .A(n4687), .Y(n4689) );
INVX6TS U3169 ( .A(n1634), .Y(n2701) );
INVX2TS U3170 ( .A(n4038), .Y(n1847) );
NAND2X4TS U3171 ( .A(n1757), .B(n1756), .Y(n3353) );
AO22X2TS U3172 ( .A0(n3262), .A1(n1997), .B0(final_result_ieee[31]), .B1(
n4908), .Y(n1383) );
AO22X2TS U3173 ( .A0(n3262), .A1(n1833), .B0(final_result_ieee[32]), .B1(
n4908), .Y(n1382) );
AO22X2TS U3174 ( .A0(n3262), .A1(n1968), .B0(final_result_ieee[23]), .B1(
n4910), .Y(n1391) );
OAI21X1TS U3175 ( .A0(n6081), .A1(n2720), .B0(n3010), .Y(n1346) );
NOR2X1TS U3176 ( .A(n4234), .B(n4217), .Y(n4221) );
NAND2X4TS U3177 ( .A(n2828), .B(n1612), .Y(n3948) );
INVX6TS U3178 ( .A(n3623), .Y(n1750) );
BUFX12TS U3179 ( .A(n5426), .Y(n5663) );
INVX3TS U3180 ( .A(n5570), .Y(n2271) );
NAND2X6TS U3181 ( .A(n1647), .B(n3290), .Y(n5782) );
NAND2X6TS U3182 ( .A(n1647), .B(n3290), .Y(n1819) );
AO22X2TS U3183 ( .A0(n4907), .A1(n1991), .B0(final_result_ieee[30]), .B1(
n4908), .Y(n1384) );
INVX3TS U3184 ( .A(n3163), .Y(n2593) );
NAND2X2TS U3185 ( .A(n3023), .B(n1664), .Y(n1691) );
NAND2X4TS U3186 ( .A(n4758), .B(n4628), .Y(n3001) );
INVX2TS U3187 ( .A(n2530), .Y(n2303) );
OR2X2TS U3188 ( .A(n4982), .B(n6242), .Y(n4972) );
INVX4TS U3189 ( .A(n3601), .Y(n1741) );
BUFX20TS U3190 ( .A(n6407), .Y(n6063) );
NOR2X4TS U3191 ( .A(n3132), .B(n3130), .Y(n3129) );
NAND2X4TS U3192 ( .A(n2725), .B(n5995), .Y(n5430) );
BUFX20TS U3193 ( .A(n2751), .Y(n6174) );
INVX2TS U3194 ( .A(n4630), .Y(n2999) );
NAND2X4TS U3195 ( .A(n4893), .B(n5978), .Y(n6028) );
BUFX16TS U3196 ( .A(n2750), .Y(n6163) );
BUFX12TS U3197 ( .A(n2751), .Y(n6075) );
INVX6TS U3198 ( .A(n4792), .Y(n4562) );
BUFX16TS U3199 ( .A(n2750), .Y(n6119) );
BUFX16TS U3200 ( .A(n2750), .Y(n6097) );
NAND2X2TS U3201 ( .A(n4092), .B(n3587), .Y(n1759) );
BUFX20TS U3202 ( .A(n2751), .Y(n6196) );
INVX2TS U3203 ( .A(n2116), .Y(n2113) );
INVX2TS U3204 ( .A(n2621), .Y(n2199) );
BUFX20TS U3205 ( .A(n2751), .Y(n6185) );
BUFX20TS U3206 ( .A(n2750), .Y(n2719) );
INVX1TS U3207 ( .A(n5221), .Y(n5222) );
BUFX12TS U3208 ( .A(n6011), .Y(n6406) );
NAND2X6TS U3209 ( .A(n2799), .B(n2582), .Y(n3098) );
BUFX12TS U3210 ( .A(n2750), .Y(n6086) );
BUFX20TS U3211 ( .A(n2751), .Y(n6108) );
INVX4TS U3212 ( .A(n6019), .Y(n5842) );
BUFX20TS U3213 ( .A(n2750), .Y(n2720) );
BUFX20TS U3214 ( .A(n2751), .Y(n6130) );
NAND2X2TS U3215 ( .A(n2101), .B(n1656), .Y(n2111) );
BUFX20TS U3216 ( .A(n2751), .Y(n6151) );
NOR2X4TS U3217 ( .A(n3137), .B(n4152), .Y(n3136) );
INVX8TS U3218 ( .A(n3435), .Y(n4629) );
INVX3TS U3219 ( .A(n4679), .Y(n3457) );
OR2X4TS U3220 ( .A(n1360), .B(beg_FSM), .Y(n4893) );
NAND2X8TS U3221 ( .A(n2978), .B(n5164), .Y(n5401) );
INVX8TS U3222 ( .A(n6033), .Y(n4910) );
BUFX20TS U3223 ( .A(n3494), .Y(n2750) );
NAND2X6TS U3224 ( .A(n4877), .B(n1985), .Y(n5927) );
INVX2TS U3225 ( .A(n4206), .Y(n4857) );
NAND2X6TS U3226 ( .A(n3322), .B(n3321), .Y(n3435) );
NAND2X4TS U3227 ( .A(n3919), .B(n5163), .Y(n3920) );
INVX2TS U3228 ( .A(n4421), .Y(n4462) );
NOR2X4TS U3229 ( .A(n3800), .B(n3866), .Y(n3807) );
NAND2X8TS U3230 ( .A(n5162), .B(n5163), .Y(n5364) );
AND2X4TS U3231 ( .A(n1871), .B(n4001), .Y(n4318) );
NOR2X4TS U3232 ( .A(n3135), .B(n4132), .Y(n3134) );
NOR2X4TS U3233 ( .A(n3754), .B(n3734), .Y(n3741) );
INVX4TS U3234 ( .A(n5918), .Y(n1835) );
NAND2X8TS U3235 ( .A(n4888), .B(n2153), .Y(n3494) );
NAND2X6TS U3236 ( .A(n3434), .B(n1654), .Y(n3373) );
NOR2X8TS U3237 ( .A(n4880), .B(n1843), .Y(n4888) );
NOR2X8TS U3238 ( .A(n1985), .B(n2683), .Y(n4889) );
INVX2TS U3239 ( .A(n5905), .Y(n4487) );
NOR2X4TS U3240 ( .A(n3634), .B(n3221), .Y(n2186) );
NAND2X8TS U3241 ( .A(n3525), .B(n1701), .Y(n5698) );
INVX2TS U3242 ( .A(n1985), .Y(n1947) );
INVX8TS U3243 ( .A(n4536), .Y(n1654) );
MX2X4TS U3244 ( .A(n2408), .B(n6213), .S0(n2866), .Y(n3436) );
INVX8TS U3245 ( .A(n1814), .Y(n5163) );
INVX3TS U3246 ( .A(n3145), .Y(n3144) );
INVX6TS U3247 ( .A(n3985), .Y(n3638) );
INVX8TS U3248 ( .A(n5515), .Y(n2729) );
NOR2X4TS U3249 ( .A(n3797), .B(n3861), .Y(n3799) );
NAND2X6TS U3250 ( .A(n1745), .B(n1744), .Y(n3615) );
NOR2X8TS U3251 ( .A(n2153), .B(n1989), .Y(n6022) );
BUFX12TS U3252 ( .A(n3979), .Y(n3221) );
INVX6TS U3253 ( .A(n3250), .Y(n3363) );
INVX2TS U3254 ( .A(n6058), .Y(n6037) );
NOR2X2TS U3255 ( .A(n3589), .B(n3588), .Y(n3590) );
AND2X4TS U3256 ( .A(n2043), .B(n1851), .Y(n3794) );
INVX2TS U3257 ( .A(n5986), .Y(n5908) );
NAND2X6TS U3258 ( .A(n2669), .B(n1992), .Y(n3614) );
NOR2X4TS U3259 ( .A(n2428), .B(n6234), .Y(n6058) );
NAND2X6TS U3260 ( .A(n1746), .B(n2013), .Y(n1745) );
INVX2TS U3261 ( .A(n3598), .Y(n3588) );
INVX2TS U3262 ( .A(n1908), .Y(n1909) );
INVX2TS U3263 ( .A(n2407), .Y(n2408) );
INVX6TS U3264 ( .A(n2174), .Y(n2175) );
NOR2X4TS U3265 ( .A(Add_Subt_result[4]), .B(Add_Subt_result[3]), .Y(n3598)
);
INVX2TS U3266 ( .A(n2411), .Y(n2412) );
INVX8TS U3267 ( .A(n2318), .Y(n3511) );
INVX2TS U3268 ( .A(Sgf_normalized_result[45]), .Y(n1704) );
INVX6TS U3269 ( .A(n2089), .Y(n2090) );
INVX2TS U3270 ( .A(n1904), .Y(n1905) );
CLKBUFX2TS U3271 ( .A(n2678), .Y(n2679) );
INVX6TS U3272 ( .A(n2158), .Y(n2159) );
INVX6TS U3273 ( .A(n2063), .Y(n2064) );
INVX6TS U3274 ( .A(n2034), .Y(n2035) );
INVX8TS U3275 ( .A(n2384), .Y(n2385) );
INVX6TS U3276 ( .A(n2043), .Y(n2044) );
INVX2TS U3277 ( .A(n1812), .Y(n1813) );
INVX6TS U3278 ( .A(n1869), .Y(n1870) );
INVX6TS U3279 ( .A(n1916), .Y(n1917) );
INVX8TS U3280 ( .A(n2660), .Y(n2661) );
INVX6TS U3281 ( .A(n2080), .Y(n2081) );
INVX8TS U3282 ( .A(n2378), .Y(n2379) );
INVX6TS U3283 ( .A(n2060), .Y(n2061) );
AND2X4TS U3284 ( .A(n6340), .B(n6341), .Y(n2558) );
INVX8TS U3285 ( .A(n2217), .Y(n2218) );
INVX6TS U3286 ( .A(n2117), .Y(n2118) );
INVX6TS U3287 ( .A(n2078), .Y(n2079) );
INVX6TS U3288 ( .A(n2127), .Y(n2128) );
NAND2X2TS U3289 ( .A(n2826), .B(n3276), .Y(n1428) );
NOR2X6TS U3290 ( .A(n3283), .B(n3282), .Y(n4351) );
NAND3X4TS U3291 ( .A(n3021), .B(n2579), .C(n3019), .Y(n1515) );
NOR2X4TS U3292 ( .A(n3473), .B(n2587), .Y(n2586) );
XNOR2X2TS U3293 ( .A(n4238), .B(n4237), .Y(n2529) );
XNOR2X2TS U3294 ( .A(n4325), .B(n4324), .Y(n6401) );
XNOR2X2TS U3295 ( .A(n4436), .B(n4435), .Y(n3501) );
NAND2X4TS U3296 ( .A(n3474), .B(n5971), .Y(n3473) );
OAI2BB1X2TS U3297 ( .A0N(n2249), .A1N(n5845), .B0(n5867), .Y(n1148) );
OAI2BB1X2TS U3298 ( .A0N(n5851), .A1N(n2309), .B0(n5847), .Y(n1211) );
NAND2X4TS U3299 ( .A(n3020), .B(n2492), .Y(n3019) );
NAND2X6TS U3300 ( .A(n2605), .B(n3068), .Y(n2604) );
NAND2X2TS U3301 ( .A(n5006), .B(n5005), .Y(n1450) );
NAND4X4TS U3302 ( .A(n5089), .B(n5088), .C(n5890), .D(n5087), .Y(n1472) );
NAND2X2TS U3303 ( .A(n2934), .B(n2931), .Y(n1443) );
NAND4BX2TS U3304 ( .AN(n5883), .B(n5882), .C(n5881), .D(n5880), .Y(n1479) );
INVX8TS U3305 ( .A(n4359), .Y(n5863) );
OAI21X4TS U3306 ( .A0(n5115), .A1(n5114), .B0(n2662), .Y(n5118) );
NAND2X2TS U3307 ( .A(n5095), .B(n5094), .Y(n1444) );
NOR3X6TS U3308 ( .A(n1730), .B(n4496), .C(n3234), .Y(n4497) );
NAND4X4TS U3309 ( .A(n1882), .B(n3577), .C(n3576), .D(n3575), .Y(n3597) );
NAND2X2TS U3310 ( .A(n5705), .B(n5897), .Y(n5709) );
MX2X2TS U3311 ( .A(n4946), .B(n2124), .S0(n5895), .Y(n1469) );
NAND2X4TS U3312 ( .A(n2801), .B(n2762), .Y(n2800) );
INVX4TS U3313 ( .A(n3177), .Y(n1721) );
NAND2X4TS U3314 ( .A(n5887), .B(n3291), .Y(n2935) );
NOR2X6TS U3315 ( .A(n2710), .B(n2602), .Y(n2599) );
NOR2X6TS U3316 ( .A(n5974), .B(n2493), .Y(n3420) );
INVX8TS U3317 ( .A(n5924), .Y(n1765) );
INVX2TS U3318 ( .A(n4429), .Y(n4322) );
INVX2TS U3319 ( .A(n2892), .Y(n3967) );
OR2X2TS U3320 ( .A(n5138), .B(n1820), .Y(n3530) );
OR2X2TS U3321 ( .A(n5783), .B(n5782), .Y(n5786) );
INVX2TS U3322 ( .A(n5947), .Y(n5944) );
AOI22X2TS U3323 ( .A0(n5688), .A1(n5687), .B0(n5686), .B1(n2701), .Y(n2068)
);
INVX4TS U3324 ( .A(n3963), .Y(n1708) );
INVX3TS U3325 ( .A(n4571), .Y(n1825) );
NAND3X4TS U3326 ( .A(n2940), .B(n2939), .C(n2938), .Y(n2937) );
NAND3X4TS U3327 ( .A(n2814), .B(n2813), .C(n2815), .Y(n2808) );
INVX2TS U3328 ( .A(n4795), .Y(n3939) );
INVX2TS U3329 ( .A(n4427), .Y(n4323) );
NAND2X6TS U3330 ( .A(n4580), .B(n3176), .Y(n1764) );
NAND2X4TS U3331 ( .A(n3000), .B(n2998), .Y(n4844) );
NOR2X4TS U3332 ( .A(n5138), .B(n5153), .Y(n5886) );
INVX4TS U3333 ( .A(n2444), .Y(n4987) );
NAND2X6TS U3334 ( .A(n3348), .B(n3352), .Y(n5924) );
OR2X2TS U3335 ( .A(n5748), .B(n1820), .Y(n5749) );
NOR2X4TS U3336 ( .A(n5765), .B(n5153), .Y(n5119) );
AND2X4TS U3337 ( .A(n4203), .B(n4202), .Y(n2568) );
OR2X2TS U3338 ( .A(n4979), .B(n1820), .Y(n3539) );
OR2X2TS U3339 ( .A(n4966), .B(n5782), .Y(n3660) );
NAND2X4TS U3340 ( .A(n2588), .B(n4477), .Y(n2587) );
INVX2TS U3341 ( .A(n3237), .Y(n5692) );
NOR2X4TS U3342 ( .A(n4979), .B(n5153), .Y(n5143) );
NOR2X4TS U3343 ( .A(n4966), .B(n3290), .Y(n5124) );
INVX4TS U3344 ( .A(n1875), .Y(n4343) );
OR2X2TS U3345 ( .A(n5765), .B(n5782), .Y(n5766) );
AOI22X2TS U3346 ( .A0(n5081), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n5101), .B1(n2743), .Y(n2659) );
MXI2X2TS U3347 ( .A(n6048), .B(n6047), .S0(n6060), .Y(n6049) );
OR2X2TS U3348 ( .A(n5743), .B(n5782), .Y(n5745) );
INVX12TS U3349 ( .A(n5972), .Y(n2733) );
INVX2TS U3350 ( .A(n2667), .Y(n4712) );
INVX12TS U3351 ( .A(n5972), .Y(n2749) );
INVX2TS U3352 ( .A(n4836), .Y(n4837) );
AOI21X2TS U3353 ( .A0(n6030), .A1(n6029), .B0(n6028), .Y(n1560) );
AO22X2TS U3354 ( .A0(n4911), .A1(n2210), .B0(final_result_ieee[44]), .B1(
n6040), .Y(n1370) );
AO22X2TS U3355 ( .A0(n3260), .A1(n1845), .B0(final_result_ieee[14]), .B1(
n4909), .Y(n1400) );
AO22X2TS U3356 ( .A0(n3260), .A1(n1913), .B0(final_result_ieee[13]), .B1(
n4909), .Y(n1401) );
AO22X2TS U3357 ( .A0(n4911), .A1(n2083), .B0(final_result_ieee[0]), .B1(
n6013), .Y(n1414) );
AO22X2TS U3358 ( .A0(n4911), .A1(n2441), .B0(final_result_ieee[1]), .B1(
n4910), .Y(n1413) );
OR2X2TS U3359 ( .A(n5055), .B(n6240), .Y(n5018) );
AO22X2TS U3360 ( .A0(n3260), .A1(n1979), .B0(final_result_ieee[16]), .B1(
n4909), .Y(n1398) );
NAND2X4TS U3361 ( .A(n4683), .B(n1630), .Y(n4687) );
AO22X2TS U3362 ( .A0(n3260), .A1(n1677), .B0(final_result_ieee[20]), .B1(
n4910), .Y(n1394) );
INVX12TS U3363 ( .A(n2055), .Y(n2505) );
INVX2TS U3364 ( .A(n1642), .Y(n3974) );
XOR2X2TS U3365 ( .A(n4938), .B(n3088), .Y(n3085) );
INVX2TS U3366 ( .A(n5233), .Y(n5423) );
NAND2X2TS U3367 ( .A(n6063), .B(Add_Subt_result[15]), .Y(n3057) );
INVX2TS U3368 ( .A(n1685), .Y(n4607) );
NAND2X6TS U3369 ( .A(n3384), .B(n3387), .Y(n3383) );
OAI21X2TS U3370 ( .A0(n6405), .A1(n2153), .B0(n2723), .Y(n1557) );
NAND2X4TS U3371 ( .A(n3483), .B(n4746), .Y(n4752) );
NAND2X4TS U3372 ( .A(n2628), .B(n4746), .Y(n4547) );
AO22X2TS U3373 ( .A0(n4911), .A1(Sgf_normalized_result[49]), .B0(
final_result_ieee[47]), .B1(n6013), .Y(n1367) );
AO22X2TS U3374 ( .A0(n4911), .A1(Sgf_normalized_result[50]), .B0(
final_result_ieee[48]), .B1(n6013), .Y(n1366) );
NAND2X2TS U3375 ( .A(n5233), .B(n1988), .Y(n5234) );
AO22X2TS U3376 ( .A0(n4911), .A1(Sgf_normalized_result[51]), .B0(
final_result_ieee[49]), .B1(n6013), .Y(n1365) );
AO22X2TS U3377 ( .A0(n4911), .A1(Sgf_normalized_result[52]), .B0(
final_result_ieee[50]), .B1(n6013), .Y(n1364) );
AND2X2TS U3378 ( .A(n1685), .B(n4606), .Y(n4324) );
AO22X2TS U3379 ( .A0(n3260), .A1(n2425), .B0(final_result_ieee[15]), .B1(
n4909), .Y(n1399) );
AO22X2TS U3380 ( .A0(n4911), .A1(Sgf_normalized_result[53]), .B0(
final_result_ieee[51]), .B1(n6013), .Y(n1363) );
NAND2X2TS U3381 ( .A(n6063), .B(Add_Subt_result[14]), .Y(n3217) );
NOR2X4TS U3382 ( .A(n4208), .B(n3201), .Y(n3200) );
OR2X2TS U3383 ( .A(n4982), .B(n6245), .Y(n3683) );
INVX6TS U3384 ( .A(n3950), .Y(n1707) );
MXI2X2TS U3385 ( .A(n6175), .B(n2332), .S0(n6174), .Y(n1259) );
MXI2X2TS U3386 ( .A(n6190), .B(n2404), .S0(n6196), .Y(n1245) );
INVX2TS U3387 ( .A(n1853), .Y(n4011) );
MXI2X2TS U3388 ( .A(n6176), .B(n2213), .S0(n6185), .Y(n1258) );
NAND2X6TS U3389 ( .A(n1680), .B(n2855), .Y(n2854) );
MXI2X2TS U3390 ( .A(n6079), .B(n2206), .S0(n6086), .Y(n1348) );
MXI2X2TS U3391 ( .A(n6078), .B(n2128), .S0(n6097), .Y(n1349) );
MXI2X2TS U3392 ( .A(n6177), .B(n2259), .S0(n6185), .Y(n1257) );
INVX6TS U3393 ( .A(n1441), .Y(n6398) );
INVX2TS U3394 ( .A(n4758), .Y(n4759) );
MXI2X2TS U3395 ( .A(n6157), .B(n2312), .S0(n6119), .Y(n1275) );
MXI2X2TS U3396 ( .A(n6172), .B(n2305), .S0(n6174), .Y(n1261) );
MXI2X2TS U3397 ( .A(n4885), .B(n2448), .S0(n6163), .Y(n1232) );
NAND2X2TS U3398 ( .A(n6038), .B(n6002), .Y(n6514) );
NAND2X1TS U3399 ( .A(n6009), .B(n5990), .Y(n6505) );
NAND2X2TS U3400 ( .A(n6009), .B(n6000), .Y(n6517) );
INVX2TS U3401 ( .A(n2684), .Y(n1711) );
INVX2TS U3402 ( .A(n4784), .Y(n4840) );
INVX6TS U3403 ( .A(n4090), .Y(n3349) );
NAND2X2TS U3404 ( .A(n6407), .B(n3256), .Y(n3463) );
NAND2X2TS U3405 ( .A(n6038), .B(n6007), .Y(n6472) );
NAND2X2TS U3406 ( .A(n6009), .B(n5997), .Y(n6481) );
NAND2X2TS U3407 ( .A(n6038), .B(n5996), .Y(n6484) );
MXI2X2TS U3408 ( .A(n6121), .B(n2042), .S0(n6130), .Y(n1310) );
NAND2X2TS U3409 ( .A(n6038), .B(n6001), .Y(n6511) );
NAND2X2TS U3410 ( .A(n5999), .B(n5995), .Y(n6508) );
NAND2X2TS U3411 ( .A(n6038), .B(n5992), .Y(n6490) );
NAND2X2TS U3412 ( .A(n6009), .B(n5991), .Y(n6499) );
MXI2X2TS U3413 ( .A(n6150), .B(n1851), .S0(n6151), .Y(n1280) );
NAND2X2TS U3414 ( .A(n6038), .B(n6004), .Y(n6466) );
NAND2X1TS U3415 ( .A(n6009), .B(n1675), .Y(n6463) );
NAND2X2TS U3416 ( .A(n6038), .B(n5998), .Y(n6487) );
NAND2X4TS U3417 ( .A(n4261), .B(n2373), .Y(n3076) );
NAND2X2TS U3418 ( .A(n6009), .B(n6008), .Y(n6523) );
INVX8TS U3419 ( .A(n5988), .Y(n6009) );
NAND2X4TS U3420 ( .A(n4631), .B(n4630), .Y(n2530) );
AND2X2TS U3421 ( .A(n4530), .B(n4626), .Y(n4531) );
INVX8TS U3422 ( .A(n5988), .Y(n6038) );
AND2X2TS U3423 ( .A(n5895), .B(n1867), .Y(n5191) );
INVX12TS U3424 ( .A(n2868), .Y(n5103) );
INVX12TS U3425 ( .A(n6019), .Y(n3230) );
CLKBUFX2TS U3426 ( .A(n4713), .Y(n4657) );
CLKBUFX2TS U3427 ( .A(n4369), .Y(n4311) );
NAND2X6TS U3428 ( .A(n2524), .B(n4771), .Y(n4758) );
NAND2X2TS U3429 ( .A(n4020), .B(n4027), .Y(n4705) );
NAND2X2TS U3430 ( .A(n5927), .B(n2237), .Y(n3240) );
INVX2TS U3431 ( .A(n3892), .Y(n4240) );
INVX3TS U3432 ( .A(n2026), .Y(n5370) );
INVX4TS U3433 ( .A(n2028), .Y(n1645) );
AND2X2TS U3434 ( .A(n4393), .B(n4392), .Y(n4441) );
INVX8TS U3435 ( .A(n5988), .Y(n5999) );
INVX16TS U3436 ( .A(n6033), .Y(n6013) );
NAND2X4TS U3437 ( .A(n3359), .B(n2542), .Y(n5362) );
INVX2TS U3438 ( .A(n2499), .Y(n1646) );
BUFX20TS U3439 ( .A(n3494), .Y(n2751) );
NOR2X4TS U3440 ( .A(n3144), .B(n2746), .Y(n3143) );
NAND2X6TS U3441 ( .A(n3807), .B(n3879), .Y(n3881) );
NAND2X4TS U3442 ( .A(n4526), .B(n4535), .Y(n4762) );
NAND2X4TS U3443 ( .A(n3134), .B(n3133), .Y(n3132) );
INVX8TS U3444 ( .A(n1698), .Y(n2475) );
NAND2X2TS U3445 ( .A(n5516), .B(n6001), .Y(n2017) );
INVX6TS U3446 ( .A(n5129), .Y(n5871) );
INVX2TS U3447 ( .A(n4754), .Y(n4755) );
NAND2X4TS U3448 ( .A(n1981), .B(n4005), .Y(n4433) );
NAND2X4TS U3449 ( .A(n3374), .B(n4536), .Y(n4559) );
INVX8TS U3450 ( .A(n3581), .Y(n1649) );
INVX8TS U3451 ( .A(n3436), .Y(n4566) );
INVX2TS U3452 ( .A(n1736), .Y(n5946) );
INVX2TS U3453 ( .A(n4227), .Y(n4230) );
INVX12TS U3454 ( .A(n3252), .Y(n2731) );
INVX16TS U3455 ( .A(n2831), .Y(n5129) );
AND2X2TS U3456 ( .A(n4744), .B(n4748), .Y(n4721) );
AND2X4TS U3457 ( .A(n4889), .B(n4896), .Y(ready) );
INVX12TS U3458 ( .A(n2062), .Y(n4032) );
NAND2BX2TS U3459 ( .AN(n4151), .B(n3131), .Y(n3130) );
INVX8TS U3460 ( .A(n3613), .Y(n3905) );
OR2X4TS U3461 ( .A(n2866), .B(DMP[50]), .Y(n3322) );
INVX8TS U3462 ( .A(n3236), .Y(n3976) );
NAND2X2TS U3463 ( .A(n2723), .B(DmP[12]), .Y(n5371) );
INVX8TS U3464 ( .A(n2619), .Y(n4265) );
NAND2X6TS U3465 ( .A(n3929), .B(n3928), .Y(n3930) );
CLKINVX6TS U3466 ( .A(n2038), .Y(n3606) );
INVX4TS U3467 ( .A(n4021), .Y(n1653) );
NAND2X4TS U3468 ( .A(n3052), .B(n3051), .Y(n3906) );
INVX6TS U3469 ( .A(n4506), .Y(n4518) );
BUFX6TS U3470 ( .A(n5506), .Y(n2754) );
NAND2X6TS U3471 ( .A(n1781), .B(n1960), .Y(n1780) );
NAND2X6TS U3472 ( .A(n6216), .B(n3211), .Y(n2954) );
BUFX16TS U3473 ( .A(n3120), .Y(n1701) );
INVX6TS U3474 ( .A(n1430), .Y(n6032) );
INVX12TS U3475 ( .A(n4585), .Y(n1658) );
INVX1TS U3476 ( .A(n5997), .Y(n5909) );
INVX16TS U3477 ( .A(n2715), .Y(n2153) );
INVX6TS U3478 ( .A(n3624), .Y(n1660) );
NAND2X6TS U3479 ( .A(n1778), .B(n2426), .Y(n1732) );
INVX12TS U3480 ( .A(n3903), .Y(n1663) );
INVX8TS U3481 ( .A(n1942), .Y(n1943) );
INVX3TS U3482 ( .A(n2047), .Y(n2048) );
INVX4TS U3483 ( .A(n1867), .Y(n1868) );
INVX3TS U3484 ( .A(n1845), .Y(n1846) );
INVX4TS U3485 ( .A(n2045), .Y(n2046) );
MX2X4TS U3486 ( .A(n6355), .B(n6354), .S0(n1815), .Y(n1430) );
NAND3X6TS U3487 ( .A(n6288), .B(n6289), .C(n6287), .Y(n6005) );
NOR2X2TS U3488 ( .A(n6256), .B(r_mode[0]), .Y(n4874) );
INVX6TS U3489 ( .A(n2114), .Y(n2115) );
INVX8TS U3490 ( .A(n2365), .Y(n2366) );
INVX6TS U3491 ( .A(n1872), .Y(n1873) );
INVX6TS U3492 ( .A(n2295), .Y(n2296) );
MXI2X4TS U3493 ( .A(n6275), .B(n6274), .S0(n6273), .Y(n5295) );
INVX8TS U3494 ( .A(n2162), .Y(n2163) );
INVX8TS U3495 ( .A(n2071), .Y(n2072) );
INVX8TS U3496 ( .A(n2363), .Y(n2364) );
INVX2TS U3497 ( .A(Add_Subt_result[0]), .Y(n6039) );
INVX6TS U3498 ( .A(n1854), .Y(n1855) );
INVX3TS U3499 ( .A(n1836), .Y(n1837) );
INVX8TS U3500 ( .A(n2432), .Y(n2433) );
INVX4TS U3501 ( .A(n2164), .Y(n2165) );
INVX8TS U3502 ( .A(n2095), .Y(n2096) );
INVX6TS U3503 ( .A(n2041), .Y(n2042) );
CLKAND2X2TS U3504 ( .A(n6238), .B(n6221), .Y(n3602) );
INVX8TS U3505 ( .A(n2241), .Y(n2242) );
INVX8TS U3506 ( .A(n2227), .Y(n2228) );
INVX8TS U3507 ( .A(n2247), .Y(n2248) );
INVX8TS U3508 ( .A(n2239), .Y(n2240) );
INVX8TS U3509 ( .A(n2132), .Y(n2133) );
INVX8TS U3510 ( .A(n2243), .Y(n2244) );
NAND2X8TS U3511 ( .A(n1666), .B(n1665), .Y(n3239) );
NOR2X8TS U3512 ( .A(n2983), .B(n3375), .Y(n1666) );
NAND2X6TS U3513 ( .A(n4420), .B(n3907), .Y(n2915) );
NAND2X8TS U3514 ( .A(n3222), .B(n1667), .Y(n3422) );
NAND2X8TS U3515 ( .A(n2797), .B(n1956), .Y(n1667) );
INVX12TS U3516 ( .A(n1785), .Y(n3909) );
NAND2X8TS U3517 ( .A(n3040), .B(n3041), .Y(n1785) );
CLKINVX2TS U3518 ( .A(n4352), .Y(n4353) );
CLKBUFX2TS U3519 ( .A(n4879), .Y(n1668) );
XOR2X4TS U3520 ( .A(n1669), .B(n2530), .Y(n4568) );
NAND2X6TS U3521 ( .A(n3498), .B(n1670), .Y(n1669) );
NAND2X4TS U3522 ( .A(n4564), .B(n2858), .Y(n1670) );
NAND3BX4TS U3523 ( .AN(Exp_Operation_Module_Data_S_8_), .B(n2323), .C(n4813),
.Y(n6540) );
XOR2X4TS U3524 ( .A(n1671), .B(n2113), .Y(n4501) );
NOR2X8TS U3525 ( .A(n2033), .B(n2481), .Y(n4453) );
NOR2X6TS U3526 ( .A(n4288), .B(n4271), .Y(n4690) );
NAND2X8TS U3527 ( .A(n3311), .B(n3312), .Y(n3454) );
INVX2TS U3528 ( .A(n3265), .Y(n2780) );
NAND2X4TS U3529 ( .A(n2643), .B(n3372), .Y(n2923) );
BUFX6TS U3530 ( .A(n6005), .Y(n1675) );
NAND2X6TS U3531 ( .A(n4586), .B(n4484), .Y(n4584) );
MXI2X4TS U3532 ( .A(n3915), .B(n3914), .S0(n6060), .Y(n6535) );
INVX6TS U3533 ( .A(n1694), .Y(n4443) );
OAI2BB2X4TS U3534 ( .B0(n2696), .B1(n2271), .A0N(n5426), .A1N(n5572), .Y(
n2272) );
AOI21X4TS U3535 ( .A0(n4241), .A1(n4240), .B0(n3026), .Y(n3897) );
AOI21X4TS U3536 ( .A0(n4320), .A1(n3645), .B0(n3644), .Y(n3646) );
OAI21X4TS U3537 ( .A0(n4315), .A1(n3640), .B0(n3639), .Y(n4320) );
NOR2X8TS U3538 ( .A(n1676), .B(n3444), .Y(n3498) );
NOR2X8TS U3539 ( .A(n5956), .B(n4563), .Y(n1676) );
XNOR2X4TS U3540 ( .A(n2715), .B(n1951), .Y(n3525) );
NOR2X8TS U3541 ( .A(n6231), .B(n2670), .Y(n4276) );
AOI21X4TS U3542 ( .A0(n2716), .A1(n3993), .B0(n3992), .Y(n3998) );
NAND3X6TS U3543 ( .A(n2885), .B(n2514), .C(n3953), .Y(n2716) );
NOR2X8TS U3544 ( .A(n3247), .B(n3466), .Y(n3478) );
INVX6TS U3545 ( .A(n3835), .Y(n2188) );
NOR2X6TS U3546 ( .A(n2188), .B(n3830), .Y(n2189) );
OR2X8TS U3547 ( .A(n5955), .B(n5956), .Y(n3117) );
NOR2X6TS U3548 ( .A(n1760), .B(n1758), .Y(n3595) );
NOR2X1TS U3549 ( .A(n4894), .B(n2704), .Y(n4899) );
AOI2BB2X4TS U3550 ( .B0(n2740), .B1(n2194), .A0N(n1886), .A1N(n1990), .Y(
n5778) );
OAI2BB1X4TS U3551 ( .A0N(n2321), .A1N(n5873), .B0(n5778), .Y(n1226) );
NAND2X8TS U3552 ( .A(n4888), .B(n2715), .Y(n1360) );
NAND3X8TS U3553 ( .A(n3947), .B(n3954), .C(n3166), .Y(n2885) );
NAND2X8TS U3554 ( .A(n2774), .B(n3957), .Y(n3947) );
NAND2X6TS U3555 ( .A(n3223), .B(n3357), .Y(n1684) );
NAND4X6TS U3556 ( .A(n3055), .B(n3054), .C(n1830), .D(n3053), .Y(n2706) );
INVX8TS U3557 ( .A(n3380), .Y(n3409) );
NAND2X8TS U3558 ( .A(n2770), .B(n2768), .Y(n3415) );
BUFX20TS U3559 ( .A(n2262), .Y(n1754) );
INVX12TS U3560 ( .A(n1678), .Y(n2512) );
NAND2X8TS U3561 ( .A(n2974), .B(n3079), .Y(n1678) );
NAND3X8TS U3562 ( .A(n6301), .B(n6300), .C(n6299), .Y(n6010) );
NOR2X6TS U3563 ( .A(n4542), .B(n6205), .Y(n4625) );
OAI21X4TS U3564 ( .A0(n4853), .A1(n5956), .B0(n3432), .Y(n4854) );
INVX2TS U3565 ( .A(n5086), .Y(n1679) );
OR2X8TS U3566 ( .A(n2899), .B(n1679), .Y(n2898) );
INVX12TS U3567 ( .A(n2867), .Y(n5056) );
NAND2X8TS U3568 ( .A(n3514), .B(n3515), .Y(n2867) );
INVX2TS U3569 ( .A(n4403), .Y(n1680) );
NAND2X8TS U3570 ( .A(n2971), .B(n2972), .Y(n1793) );
NAND2X4TS U3571 ( .A(n2622), .B(n3042), .Y(n2988) );
NAND2BX4TS U3572 ( .AN(n1840), .B(n6400), .Y(n6498) );
BUFX16TS U3573 ( .A(n5969), .Y(n1831) );
NOR2X8TS U3574 ( .A(n3999), .B(n4002), .Y(n4196) );
NOR2X8TS U3575 ( .A(n1792), .B(n2092), .Y(n3999) );
AOI22X2TS U3576 ( .A0(n5829), .A1(n2304), .B0(DmP[29]), .B1(n5777), .Y(n5822) );
AOI21X4TS U3577 ( .A0(n1801), .A1(n4609), .B0(n4608), .Y(n3002) );
OAI21X4TS U3578 ( .A0(n3303), .A1(n3866), .B0(n1682), .Y(n3300) );
AOI21X4TS U3579 ( .A0(n3302), .A1(n3865), .B0(n3301), .Y(n1682) );
NOR2X6TS U3580 ( .A(n2544), .B(n6276), .Y(n3324) );
NOR2X8TS U3581 ( .A(n2115), .B(n2395), .Y(n3861) );
OAI21X4TS U3582 ( .A0(n2819), .A1(n2824), .B0(n2618), .Y(n2817) );
OAI2BB1X4TS U3583 ( .A0N(n4787), .A1N(n1712), .B0(n4789), .Y(n1731) );
INVX12TS U3584 ( .A(n3106), .Y(n4286) );
NAND2X8TS U3585 ( .A(n2915), .B(n1863), .Y(n3091) );
NOR2X6TS U3586 ( .A(n3117), .B(n5959), .Y(n3113) );
MX2X6TS U3587 ( .A(n1938), .B(n6204), .S0(n2993), .Y(n2031) );
OAI21X4TS U3588 ( .A0(n4402), .A1(n4401), .B0(n4400), .Y(n4545) );
INVX12TS U3589 ( .A(n2668), .Y(n2669) );
AO21X4TS U3590 ( .A0(n4836), .A1(n3506), .B0(n4784), .Y(n1718) );
XOR2X4TS U3591 ( .A(n1684), .B(n4531), .Y(n3356) );
INVX4TS U3592 ( .A(n5937), .Y(n5938) );
AOI2BB2X2TS U3593 ( .B0(n2758), .B1(n5593), .A0N(n5679), .A1N(n2680), .Y(
n5475) );
NOR2X8TS U3594 ( .A(n4302), .B(n4274), .Y(n4365) );
NOR2X8TS U3595 ( .A(n3484), .B(n3485), .Y(n4302) );
AOI2BB1X4TS U3596 ( .A0N(n4584), .A1N(n5258), .B0(n4595), .Y(n4598) );
AND2X8TS U3597 ( .A(n1799), .B(n2327), .Y(n2944) );
NOR2X8TS U3598 ( .A(n4511), .B(n4512), .Y(n4514) );
NOR2X8TS U3599 ( .A(n3430), .B(n3397), .Y(n4511) );
NOR2X8TS U3600 ( .A(n3194), .B(n3315), .Y(n2262) );
NAND3X8TS U3601 ( .A(n3551), .B(n2129), .C(n3550), .Y(n3315) );
OAI21X2TS U3602 ( .A0(n6008), .A1(n5938), .B0(n4586), .Y(n4594) );
NAND3X8TS U3603 ( .A(n2556), .B(n4029), .C(n4024), .Y(n3476) );
MX2X4TS U3604 ( .A(n1993), .B(n2686), .S0(n2465), .Y(n2970) );
AOI21X2TS U3605 ( .A0(n1864), .A1(n4310), .B0(n4108), .Y(n3488) );
BUFX6TS U3606 ( .A(n3079), .Y(n2050) );
NOR2X8TS U3607 ( .A(n3077), .B(n3074), .Y(n1830) );
NOR2X8TS U3608 ( .A(n1822), .B(n4263), .Y(n3077) );
NAND2X8TS U3609 ( .A(n4380), .B(n4031), .Y(n1688) );
OAI21X4TS U3610 ( .A0(n1690), .A1(n3004), .B0(n1689), .Y(n1824) );
CLKINVX12TS U3611 ( .A(Sgf_normalized_result[28]), .Y(n1690) );
OAI21X4TS U3612 ( .A0(n1692), .A1(n3023), .B0(n1691), .Y(n6457) );
XOR2X4TS U3613 ( .A(n4783), .B(n4782), .Y(n1692) );
OAI2BB1X4TS U3614 ( .A0N(n3005), .A1N(n4776), .B0(n4775), .Y(n1693) );
BUFX6TS U3615 ( .A(n4379), .Y(n1694) );
BUFX20TS U3616 ( .A(n3367), .Y(n3049) );
NAND2X8TS U3617 ( .A(n2862), .B(n2533), .Y(n2863) );
NAND2X8TS U3618 ( .A(n1755), .B(n2147), .Y(n2991) );
NAND2X6TS U3619 ( .A(n3371), .B(n3440), .Y(n4709) );
NOR2X4TS U3620 ( .A(n2752), .B(n2299), .Y(n2552) );
NAND2X8TS U3621 ( .A(n1755), .B(n1696), .Y(n3410) );
OAI2BB1X4TS U3622 ( .A0N(n2858), .A1N(n4368), .B0(n1639), .Y(n3266) );
INVX12TS U3623 ( .A(n2275), .Y(n4256) );
OAI2BB1X4TS U3624 ( .A0N(n2576), .A1N(n2858), .B0(n4548), .Y(n2642) );
NAND2X8TS U3625 ( .A(n3124), .B(n3981), .Y(n1698) );
NOR2X8TS U3626 ( .A(n3633), .B(n3100), .Y(n4217) );
INVX12TS U3627 ( .A(n1699), .Y(n3100) );
NAND2X8TS U3628 ( .A(n3101), .B(n1700), .Y(n1699) );
NOR2X8TS U3629 ( .A(n4248), .B(n6407), .Y(n6400) );
AOI21X2TS U3630 ( .A0(n4699), .A1(n4698), .B0(n4697), .Y(n4700) );
OA21X4TS U3631 ( .A0(n1977), .A1(n2025), .B0(n3649), .Y(n4696) );
NAND3X8TS U3632 ( .A(n3096), .B(n3094), .C(n3095), .Y(n3093) );
INVX16TS U3633 ( .A(n1752), .Y(n3211) );
NAND2X4TS U3634 ( .A(n3090), .B(n3616), .Y(n3062) );
CLKINVX12TS U3635 ( .A(n4060), .Y(n4064) );
BUFX20TS U3636 ( .A(n5752), .Y(n5849) );
BUFX20TS U3637 ( .A(n6451), .Y(n4036) );
OAI22X4TS U3638 ( .A0(n3756), .A1(n3757), .B0(n2105), .B1(n2259), .Y(n3763)
);
NAND4BBX4TS U3639 ( .AN(n3264), .BN(n3275), .C(n3414), .D(n3968), .Y(n6541)
);
AOI22X2TS U3640 ( .A0(n5584), .A1(n5559), .B0(n5558), .B1(n5648), .Y(n5379)
);
NAND4X4TS U3641 ( .A(n2585), .B(n2583), .C(n2540), .D(n2584), .Y(n6491) );
BUFX4TS U3642 ( .A(n4252), .Y(n1875) );
NAND2X6TS U3643 ( .A(n4419), .B(n3973), .Y(n3204) );
NAND2X6TS U3644 ( .A(n3004), .B(n2329), .Y(n3165) );
NAND2X8TS U3645 ( .A(n2090), .B(n2752), .Y(n3311) );
AND2X6TS U3646 ( .A(n2671), .B(Sgf_normalized_result[38]), .Y(n4271) );
NAND2X8TS U3647 ( .A(n2713), .B(n4364), .Y(n2589) );
NAND2X2TS U3648 ( .A(n5282), .B(n3250), .Y(n5503) );
INVX12TS U3649 ( .A(n3396), .Y(n4509) );
NAND2X6TS U3650 ( .A(n4545), .B(n4404), .Y(n2855) );
NOR2X8TS U3651 ( .A(n4754), .B(n4549), .Y(n4404) );
NOR2X6TS U3652 ( .A(n4515), .B(n4505), .Y(n4549) );
MXI2X8TS U3653 ( .A(n6207), .B(n2211), .S0(n3395), .Y(n4515) );
NOR2X8TS U3654 ( .A(n4517), .B(n4506), .Y(n4754) );
NOR2X8TS U3655 ( .A(n3423), .B(n3424), .Y(n4517) );
NAND2X4TS U3656 ( .A(n4503), .B(n4511), .Y(n4400) );
NOR2X8TS U3657 ( .A(n4503), .B(n4511), .Y(n4401) );
NAND2X8TS U3658 ( .A(n4993), .B(n5139), .Y(n3675) );
INVX12TS U3659 ( .A(n2726), .Y(n5890) );
NAND2X8TS U3660 ( .A(n3052), .B(n3051), .Y(n2614) );
NAND2X4TS U3661 ( .A(DMP[8]), .B(n2465), .Y(n3051) );
NAND2X6TS U3662 ( .A(n1746), .B(n1826), .Y(n3052) );
NOR2X6TS U3663 ( .A(n2059), .B(n3614), .Y(n3617) );
MXI2X8TS U3664 ( .A(n2686), .B(n1993), .S0(n1746), .Y(n2059) );
INVX16TS U3665 ( .A(n2465), .Y(n1746) );
NAND2X8TS U3666 ( .A(n1707), .B(n3954), .Y(n2514) );
OR2X8TS U3667 ( .A(n2319), .B(n2140), .Y(n3954) );
NOR2X6TS U3668 ( .A(n3224), .B(n2495), .Y(n3223) );
NAND2X8TS U3669 ( .A(n2864), .B(n2410), .Y(n3182) );
OA21X4TS U3670 ( .A0(n1831), .A1(n1728), .B0(n4308), .Y(n2166) );
NAND2X8TS U3671 ( .A(n3196), .B(n3197), .Y(n3198) );
INVX12TS U3672 ( .A(n2861), .Y(n2859) );
INVX12TS U3673 ( .A(n3123), .Y(n4277) );
NAND2X8TS U3674 ( .A(n4260), .B(n4251), .Y(n4262) );
NAND3BX4TS U3675 ( .AN(n4569), .B(n2297), .C(n4025), .Y(n4572) );
OAI2BB1X4TS U3676 ( .A0N(n2716), .A1N(n3964), .B0(n1708), .Y(n2015) );
NAND2X8TS U3677 ( .A(n3105), .B(n2340), .Y(n3108) );
INVX16TS U3678 ( .A(n1709), .Y(n2893) );
INVX12TS U3679 ( .A(n2624), .Y(n1709) );
AND2X8TS U3680 ( .A(n6219), .B(n3323), .Y(n3430) );
NAND2X8TS U3681 ( .A(n1751), .B(n1636), .Y(n4204) );
NOR2X8TS U3682 ( .A(n3545), .B(n3559), .Y(n3551) );
NAND2X8TS U3683 ( .A(n1710), .B(n2527), .Y(n4777) );
NOR2X4TS U3684 ( .A(n3402), .B(n3404), .Y(n3401) );
OAI2BB1X4TS U3685 ( .A0N(n3050), .A1N(n4649), .B0(n1711), .Y(n2454) );
INVX16TS U3686 ( .A(n1712), .Y(n5956) );
NAND2X8TS U3687 ( .A(n2853), .B(n2857), .Y(n1712) );
NOR2X8TS U3688 ( .A(Sgf_normalized_result[41]), .B(n2864), .Y(n2851) );
NAND2X2TS U3689 ( .A(n5917), .B(n6006), .Y(n5922) );
AND2X8TS U3690 ( .A(n6232), .B(n2865), .Y(n3484) );
INVX2TS U3691 ( .A(n2519), .Y(n4498) );
OAI21X2TS U3692 ( .A0(n4281), .A1(n4652), .B0(n4280), .Y(n2148) );
NOR2X8TS U3693 ( .A(n4690), .B(n4678), .Y(n3470) );
NOR2X8TS U3694 ( .A(n1715), .B(n1714), .Y(n1713) );
NOR2X8TS U3695 ( .A(n5956), .B(n4498), .Y(n1715) );
NOR2X8TS U3696 ( .A(n4785), .B(n4845), .Y(n1717) );
BUFX6TS U3697 ( .A(n3439), .Y(n1719) );
INVX6TS U3698 ( .A(n1720), .Y(n3426) );
OAI2BB1X4TS U3699 ( .A0N(n3180), .A1N(n3164), .B0(n1721), .Y(n1720) );
NAND2X6TS U3700 ( .A(n4289), .B(n4288), .Y(n4675) );
NOR2X8TS U3701 ( .A(n3380), .B(n4314), .Y(n2974) );
BUFX6TS U3702 ( .A(n3927), .Y(n1723) );
NAND2X8TS U3703 ( .A(n1725), .B(n1724), .Y(n3103) );
NAND2X8TS U3704 ( .A(n3215), .B(n3929), .Y(n3523) );
NOR2X8TS U3705 ( .A(n3619), .B(n1655), .Y(n3893) );
OAI21X4TS U3706 ( .A0(n3008), .A1(n2631), .B0(n1727), .Y(n2275) );
AOI21X2TS U3707 ( .A0(n1864), .A1(n3483), .B0(n4750), .Y(n4751) );
OA21X4TS U3708 ( .A0(n2186), .A1(n4219), .B0(n3635), .Y(n3317) );
INVX16TS U3709 ( .A(n1752), .Y(n3004) );
OAI2BB1X4TS U3710 ( .A0N(n3050), .A1N(n4601), .B0(n1831), .Y(n2456) );
NOR2X8TS U3711 ( .A(n1623), .B(n1729), .Y(n4300) );
NOR2X8TS U3712 ( .A(n3892), .B(n3893), .Y(n4202) );
AOI21X4TS U3713 ( .A0(n2643), .A1(n4790), .B0(n1731), .Y(n3491) );
OAI21X4TS U3714 ( .A0(n1778), .A1(n2688), .B0(n1732), .Y(n3236) );
XOR2X4TS U3715 ( .A(n3161), .B(n1733), .Y(n4460) );
NOR2X8TS U3716 ( .A(n2757), .B(n6228), .Y(n4060) );
XNOR2X4TS U3717 ( .A(n3277), .B(n2520), .Y(n3275) );
NAND2X8TS U3718 ( .A(n3032), .B(n3980), .Y(n3031) );
CLKINVX12TS U3719 ( .A(n1752), .Y(n3008) );
OR2X8TS U3720 ( .A(n1752), .B(n2416), .Y(n3101) );
INVX8TS U3721 ( .A(n4655), .Y(n2982) );
XOR2X4TS U3722 ( .A(n1734), .B(n1733), .Y(n4474) );
NAND2X8TS U3723 ( .A(n3251), .B(n2560), .Y(n1734) );
BUFX6TS U3724 ( .A(n2219), .Y(n1735) );
NOR2X8TS U3725 ( .A(n4006), .B(n3642), .Y(n1784) );
OAI21X4TS U3726 ( .A0(n4428), .A1(n1784), .B0(n3643), .Y(n3644) );
NOR2X8TS U3727 ( .A(n3774), .B(n3740), .Y(n3777) );
OR2X8TS U3728 ( .A(n4579), .B(n2557), .Y(n2489) );
NOR3X8TS U3729 ( .A(n5986), .B(n6003), .C(n5985), .Y(n3355) );
NOR2X6TS U3730 ( .A(n4275), .B(n2481), .Y(n4112) );
INVX16TS U3731 ( .A(n1739), .Y(n6004) );
INVX12TS U3732 ( .A(n6004), .Y(n3358) );
AND3X8TS U3733 ( .A(n6312), .B(n6313), .C(n6311), .Y(n1739) );
BUFX20TS U3734 ( .A(n3315), .Y(n1740) );
OAI2BB1X4TS U3735 ( .A0N(n6222), .A1N(n6258), .B0(n4080), .Y(n3176) );
NOR2BX4TS U3736 ( .AN(n1741), .B(n1740), .Y(n4080) );
NAND2X4TS U3737 ( .A(n2692), .B(n2465), .Y(n1744) );
INVX3TS U3738 ( .A(n6451), .Y(n1742) );
NAND2X8TS U3739 ( .A(n1749), .B(n1747), .Y(n3273) );
AOI21X4TS U3740 ( .A0(n2027), .A1(n3064), .B0(n1748), .Y(n1747) );
OAI21X4TS U3741 ( .A0(n4856), .A1(n3622), .B0(n3621), .Y(n1748) );
OAI21X4TS U3742 ( .A0(n3893), .A1(n4239), .B0(n3894), .Y(n2027) );
NAND2X8TS U3743 ( .A(n4204), .B(n1750), .Y(n1749) );
NAND2X8TS U3744 ( .A(n4408), .B(n3618), .Y(n1751) );
BUFX20TS U3745 ( .A(n2633), .Y(n1752) );
NAND2X4TS U3746 ( .A(n1754), .B(n6536), .Y(n4596) );
AND2X4TS U3747 ( .A(n1754), .B(n3342), .Y(n1860) );
NOR2X4TS U3748 ( .A(n1740), .B(n1759), .Y(n1758) );
NOR2X4TS U3749 ( .A(n4575), .B(n3586), .Y(n1760) );
NAND2X4TS U3750 ( .A(n4312), .B(n1641), .Y(n6516) );
OAI21X4TS U3751 ( .A0(n1762), .A1(n1768), .B0(n1648), .Y(n1767) );
NAND3X8TS U3752 ( .A(n1761), .B(n1763), .C(n1765), .Y(n1762) );
NOR2X8TS U3753 ( .A(n1764), .B(n1766), .Y(n1763) );
NOR2BX4TS U3754 ( .AN(n3176), .B(n1766), .Y(n4599) );
OAI2BB1X4TS U3755 ( .A0N(n5927), .A1N(n2679), .B0(n1767), .Y(n1500) );
NAND4BBX4TS U3756 ( .AN(n3173), .BN(n3171), .C(n4583), .D(n1769), .Y(n1768)
);
NAND2X4TS U3757 ( .A(n4842), .B(n1641), .Y(n6483) );
BUFX6TS U3758 ( .A(n2423), .Y(n1770) );
OA21X4TS U3759 ( .A0(n1775), .A1(n4519), .B0(n1772), .Y(n2273) );
AOI21X4TS U3760 ( .A0(n4715), .A1(n1774), .B0(n1773), .Y(n1772) );
OAI21X4TS U3761 ( .A0(n4740), .A1(n4732), .B0(n3429), .Y(n1773) );
OAI21X4TS U3762 ( .A0(n4642), .A1(n4514), .B0(n4513), .Y(n4715) );
NOR2X8TS U3763 ( .A(n4729), .B(n4740), .Y(n1774) );
NOR2X8TS U3764 ( .A(n4641), .B(n4514), .Y(n4504) );
AOI21X4TS U3765 ( .A0(n4479), .A1(n4307), .B0(n4306), .Y(n1775) );
OAI21X4TS U3766 ( .A0(n4305), .A1(n5964), .B0(n4304), .Y(n4306) );
NOR2X8TS U3767 ( .A(n4305), .B(n5961), .Y(n4307) );
OAI21X4TS U3768 ( .A0(n4454), .A1(n4299), .B0(n4298), .Y(n4479) );
INVX12TS U3769 ( .A(n2427), .Y(n2428) );
NOR2X8TS U3770 ( .A(n1777), .B(n1776), .Y(n6053) );
BUFX20TS U3771 ( .A(n2467), .Y(n1778) );
NAND2X8TS U3772 ( .A(n1780), .B(n1779), .Y(n2065) );
BUFX16TS U3773 ( .A(n1799), .Y(n1782) );
INVX12TS U3774 ( .A(n2633), .Y(n1799) );
INVX12TS U3775 ( .A(n1783), .Y(n4753) );
NOR2X8TS U3776 ( .A(n2483), .B(n1784), .Y(n3645) );
NOR2X8TS U3777 ( .A(n1841), .B(n2482), .Y(n4437) );
NOR2X8TS U3778 ( .A(n3625), .B(n4009), .Y(n1841) );
NAND2X8TS U3779 ( .A(n2864), .B(n2296), .Y(n1787) );
INVX12TS U3780 ( .A(n1789), .Y(n4917) );
NAND2X8TS U3781 ( .A(n1790), .B(n2630), .Y(n1789) );
INVX6TS U3782 ( .A(n3899), .Y(n2630) );
CLKINVX12TS U3783 ( .A(n1793), .Y(n1792) );
OR2X8TS U3784 ( .A(n1793), .B(n2092), .Y(n4315) );
NAND2X4TS U3785 ( .A(n1794), .B(n1641), .Y(n6474) );
XOR2X4TS U3786 ( .A(n1795), .B(n1921), .Y(n1794) );
NOR2X8TS U3787 ( .A(n1782), .B(n1867), .Y(n3391) );
BUFX20TS U3788 ( .A(n2297), .Y(n1801) );
XOR2X4TS U3789 ( .A(n1802), .B(n4441), .Y(n3157) );
NAND2X8TS U3790 ( .A(n1807), .B(n1806), .Y(n4788) );
OA21X4TS U3791 ( .A0(n4558), .A1(n5957), .B0(n4559), .Y(n1806) );
NAND2X4TS U3792 ( .A(n4535), .B(n4534), .Y(n5957) );
NAND2X8TS U3793 ( .A(n4553), .B(n4537), .Y(n1807) );
NOR2X8TS U3794 ( .A(n4558), .B(n4551), .Y(n4537) );
NAND2X8TS U3795 ( .A(n3346), .B(n4532), .Y(n4553) );
AND2X8TS U3796 ( .A(n4075), .B(n2501), .Y(n3169) );
CLKINVX12TS U3797 ( .A(n1808), .Y(underflow_flag) );
AOI22X2TS U3798 ( .A0(n5104), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .Y(n5106) );
AOI2BB1X4TS U3799 ( .A0N(n6394), .A1N(n6393), .B0(n1809), .Y(n1808) );
INVX8TS U3800 ( .A(n2616), .Y(n2617) );
NOR2X4TS U3801 ( .A(n2617), .B(n2436), .Y(n2823) );
XOR2X4TS U3802 ( .A(n3389), .B(n1811), .Y(n4728) );
INVX16TS U3803 ( .A(n3394), .Y(n2797) );
NAND3X4TS U3804 ( .A(n3118), .B(n3117), .C(n3116), .Y(n3115) );
BUFX12TS U3805 ( .A(n5983), .Y(n5496) );
NOR3X6TS U3806 ( .A(n5983), .B(n1951), .C(n3256), .Y(n3526) );
AND2X6TS U3807 ( .A(n3120), .B(n2780), .Y(n2525) );
NAND2X6TS U3808 ( .A(n2209), .B(n3927), .Y(n2431) );
AND2X4TS U3809 ( .A(n3918), .B(n3927), .Y(n1814) );
BUFX4TS U3810 ( .A(n3916), .Y(n3244) );
CLKMX2X4TS U3811 ( .A(n6333), .B(n6332), .S0(n1815), .Y(n1429) );
NOR2BX4TS U3812 ( .AN(n6373), .B(n6371), .Y(n3320) );
NOR2X8TS U3813 ( .A(n3333), .B(n6337), .Y(n3332) );
NAND2X6TS U3814 ( .A(n6337), .B(n6338), .Y(n3331) );
NAND2BX4TS U3815 ( .AN(n6348), .B(n6350), .Y(n3361) );
NAND2BX4TS U3816 ( .AN(n6342), .B(n6344), .Y(n3378) );
NAND2X2TS U3817 ( .A(n6342), .B(n6343), .Y(n3379) );
NAND2X4TS U3818 ( .A(n6348), .B(n6349), .Y(n3360) );
INVX4TS U3819 ( .A(n1590), .Y(n1816) );
NOR2X8TS U3820 ( .A(n2549), .B(n3324), .Y(n5344) );
NOR2X8TS U3821 ( .A(n2315), .B(n3320), .Y(n2709) );
MXI2X4TS U3822 ( .A(n6336), .B(n6335), .S0(n6334), .Y(n5283) );
MXI2X4TS U3823 ( .A(n6336), .B(n6335), .S0(n6334), .Y(n1817) );
OR2X8TS U3824 ( .A(n2545), .B(n6356), .Y(n2559) );
MXI2X8TS U3825 ( .A(n6347), .B(n6346), .S0(n6345), .Y(n5291) );
MXI2X8TS U3826 ( .A(n6353), .B(n6352), .S0(n6351), .Y(n5281) );
NOR2X8TS U3827 ( .A(n2547), .B(n6358), .Y(n3334) );
MXI2X4TS U3828 ( .A(n6370), .B(n6369), .S0(n6368), .Y(n5272) );
MXI2X4TS U3829 ( .A(n6367), .B(n6366), .S0(n6365), .Y(n5273) );
NOR2X8TS U3830 ( .A(n3328), .B(n1626), .Y(n5919) );
NAND2X8TS U3831 ( .A(n2647), .B(n5348), .Y(n3270) );
NOR2X6TS U3832 ( .A(n2703), .B(n2645), .Y(n4879) );
INVX12TS U3833 ( .A(n2645), .Y(n2276) );
NAND2X8TS U3834 ( .A(n4889), .B(n2704), .Y(n5987) );
MXI2X4TS U3835 ( .A(n4497), .B(n2317), .S0(n5927), .Y(n1497) );
OR2X8TS U3836 ( .A(n4496), .B(n5927), .Y(n2833) );
NAND3X8TS U3837 ( .A(n4879), .B(n3917), .C(n2563), .Y(n3314) );
INVX4TS U3838 ( .A(n1668), .Y(n4880) );
OAI21X2TS U3839 ( .A0(n2476), .A1(n4659), .B0(n4710), .Y(n4711) );
XOR2X4TS U3840 ( .A(n3486), .B(n4648), .Y(n4110) );
NAND3X4TS U3841 ( .A(n5011), .B(n5010), .C(n5009), .Y(n5720) );
NAND2X2TS U3842 ( .A(n4878), .B(n6025), .Y(n1439) );
OA21X4TS U3843 ( .A0(n4702), .A1(n1786), .B0(n1977), .Y(n2308) );
INVX8TS U3844 ( .A(n3271), .Y(n4702) );
AND2X8TS U3845 ( .A(n3329), .B(n3327), .Y(n1818) );
BUFX12TS U3846 ( .A(n4262), .Y(n1822) );
NAND2X4TS U3847 ( .A(n1837), .B(n1799), .Y(n2992) );
NAND2X4TS U3848 ( .A(n4438), .B(n3629), .Y(n3078) );
MX2X6TS U3849 ( .A(Sgf_normalized_result[28]), .B(n1810), .S0(n1799), .Y(
n1823) );
XNOR2X1TS U3850 ( .A(n2194), .B(n2321), .Y(n4180) );
NOR2X2TS U3851 ( .A(n3801), .B(n3869), .Y(n3803) );
NOR2X8TS U3852 ( .A(n2752), .B(DMP[21]), .Y(n3214) );
NAND2X6TS U3853 ( .A(n3034), .B(n3980), .Y(n3033) );
MX2X6TS U3854 ( .A(n2143), .B(n2285), .S0(n2973), .Y(n1829) );
XNOR2X2TS U3855 ( .A(n4371), .B(n4264), .Y(n2607) );
INVX8TS U3856 ( .A(n2610), .Y(n2611) );
NOR2X2TS U3857 ( .A(n3708), .B(n3704), .Y(n3705) );
NOR2X6TS U3858 ( .A(n2611), .B(n2356), .Y(n3708) );
NAND3X8TS U3859 ( .A(n5509), .B(n5508), .C(n5507), .Y(n5669) );
INVX12TS U3860 ( .A(n3898), .Y(n2282) );
NAND2X2TS U3861 ( .A(n4344), .B(n4342), .Y(n3285) );
NOR2X6TS U3862 ( .A(n6010), .B(n6008), .Y(n3564) );
OAI21X2TS U3863 ( .A0(n3857), .A1(n3856), .B0(n3855), .Y(n3304) );
NOR2X8TS U3864 ( .A(n2206), .B(n2336), .Y(n3857) );
NOR2X2TS U3865 ( .A(n4259), .B(n4337), .Y(n2373) );
NAND2X6TS U3866 ( .A(n4407), .B(n3618), .Y(n3890) );
OR2X2TS U3867 ( .A(n4009), .B(n3625), .Y(n2466) );
NOR2X8TS U3868 ( .A(n3204), .B(n3203), .Y(n3202) );
NAND3X6TS U3869 ( .A(n4243), .B(n1651), .C(n3907), .Y(n3203) );
INVX8TS U3870 ( .A(n3641), .Y(n1839) );
XOR2X4TS U3871 ( .A(n4481), .B(n2511), .Y(n1840) );
INVX16TS U3872 ( .A(n6400), .Y(n5972) );
NAND2X6TS U3873 ( .A(n3886), .B(n6019), .Y(n2595) );
AND4X4TS U3874 ( .A(n3336), .B(n3338), .C(n1859), .D(n3335), .Y(n2024) );
NAND2X4TS U3875 ( .A(n2992), .B(n2991), .Y(n2708) );
NAND2X2TS U3876 ( .A(n4084), .B(n3593), .Y(n3594) );
NOR2X6TS U3877 ( .A(n4381), .B(n4443), .Y(n4383) );
CLKINVX6TS U3878 ( .A(n2703), .Y(n2704) );
NAND2X2TS U3879 ( .A(n4419), .B(n3907), .Y(n4208) );
BUFX16TS U3880 ( .A(n3323), .Y(n2865) );
XOR2X4TS U3881 ( .A(n2624), .B(n3930), .Y(n1844) );
NOR2X8TS U3882 ( .A(n4808), .B(n3965), .Y(n2772) );
NOR2X6TS U3883 ( .A(n3105), .B(Sgf_normalized_result[39]), .Y(n3307) );
NAND2X4TS U3884 ( .A(n5714), .B(n5713), .Y(n1483) );
NAND3X4TS U3885 ( .A(n5017), .B(n5016), .C(n5015), .Y(n5710) );
NOR2X8TS U3886 ( .A(n4303), .B(n4302), .Y(n4305) );
NAND2X8TS U3887 ( .A(n4284), .B(n4285), .Y(n4666) );
XOR2X4TS U3888 ( .A(n3370), .B(n1847), .Y(n4039) );
AOI22X2TS U3889 ( .A0(n5631), .A1(n5656), .B0(n5629), .B1(n5688), .Y(n5529)
);
NAND3X8TS U3890 ( .A(n5519), .B(n5518), .C(n5517), .Y(n5629) );
OAI21X4TS U3891 ( .A0(n4429), .A1(n2483), .B0(n4428), .Y(n4430) );
INVX8TS U3892 ( .A(n2196), .Y(n2197) );
NOR2X4TS U3893 ( .A(n3839), .B(n3783), .Y(n3784) );
NOR2X8TS U3894 ( .A(n2197), .B(intDY[45]), .Y(n3839) );
NOR2X8TS U3895 ( .A(n4101), .B(n4105), .Y(n4102) );
NAND2X4TS U3896 ( .A(n3901), .B(n2451), .Y(n2924) );
MXI2X2TS U3897 ( .A(n5187), .B(n1606), .S0(n3023), .Y(n6538) );
AOI22X2TS U3898 ( .A0(n5634), .A1(n5620), .B0(n5619), .B1(n2700), .Y(n5332)
);
NAND3X8TS U3899 ( .A(n5311), .B(n5310), .C(n5309), .Y(n5620) );
NOR2X8TS U3900 ( .A(n4659), .B(n4655), .Y(n4033) );
INVX12TS U3901 ( .A(n2467), .Y(n2468) );
NOR2X6TS U3902 ( .A(n3978), .B(n3979), .Y(n4222) );
MXI2X8TS U3903 ( .A(n2471), .B(n1995), .S0(n2468), .Y(n3979) );
NOR2X8TS U3904 ( .A(n3098), .B(n2988), .Y(n3205) );
MX2X6TS U3905 ( .A(n2077), .B(n6217), .S0(n3394), .Y(n3396) );
NOR2BX4TS U3906 ( .AN(n2347), .B(n3395), .Y(n3308) );
NOR2X8TS U3907 ( .A(n4395), .B(n4401), .Y(n4396) );
MXI2X2TS U3908 ( .A(n6067), .B(n1849), .S0(n6075), .Y(n1359) );
MXI2X4TS U3909 ( .A(n1658), .B(n4201), .S0(n3067), .Y(n6529) );
NOR2X8TS U3910 ( .A(n4036), .B(n2007), .Y(n3981) );
NAND3BX4TS U3911 ( .AN(n4684), .B(n2713), .C(n5942), .Y(n2601) );
BUFX20TS U3912 ( .A(n2702), .Y(n2976) );
AOI21X4TS U3913 ( .A0(n3763), .A1(n2069), .B0(n3761), .Y(n3775) );
AOI21X4TS U3914 ( .A0(n3877), .A1(n3876), .B0(n3875), .Y(n3297) );
AOI22X2TS U3915 ( .A0(n5760), .A1(n2376), .B0(DmP[35]), .B1(n5842), .Y(n5830) );
NOR2X8TS U3916 ( .A(n2176), .B(n4279), .Y(n4281) );
NAND2X4TS U3917 ( .A(n4111), .B(n2984), .Y(n3474) );
INVX16TS U3918 ( .A(n5987), .Y(n5988) );
AOI22X4TS U3919 ( .A0(n5736), .A1(n1942), .B0(n2411), .B1(n5777), .Y(n5772)
);
NOR2X4TS U3920 ( .A(n2222), .B(n2331), .Y(n3760) );
OAI2BB1X4TS U3921 ( .A0N(n5851), .A1N(n2230), .B0(n5728), .Y(n1173) );
AOI2BB2X4TS U3922 ( .B0(n2976), .B1(n2652), .A0N(n2286), .A1N(n2360), .Y(
n5728) );
BUFX20TS U3923 ( .A(n5795), .Y(n5851) );
XOR2X4TS U3924 ( .A(n4200), .B(n2458), .Y(n4201) );
AOI21X4TS U3925 ( .A0(n4198), .A1(n1609), .B0(n2592), .Y(n4200) );
INVX6TS U3926 ( .A(n3902), .Y(n3607) );
NAND2X4TS U3927 ( .A(n2866), .B(n6205), .Y(n3321) );
NOR2X4TS U3928 ( .A(n2865), .B(n2345), .Y(n3485) );
OR2X4TS U3929 ( .A(n4188), .B(n4189), .Y(n3135) );
NAND2X4TS U3930 ( .A(n2739), .B(n2763), .Y(n2813) );
INVX2TS U3931 ( .A(n3580), .Y(n3587) );
INVX4TS U3932 ( .A(n4378), .Y(n4381) );
NAND2X2TS U3933 ( .A(n2739), .B(
Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(n3193) );
NAND2X4TS U3934 ( .A(n4566), .B(n4567), .Y(n4630) );
INVX6TS U3935 ( .A(n3940), .Y(n4796) );
OR2X4TS U3936 ( .A(n4149), .B(n4129), .Y(n3128) );
INVX2TS U3937 ( .A(n2484), .Y(n2742) );
NAND2X4TS U3938 ( .A(n2282), .B(n1656), .Y(n2281) );
NAND2X2TS U3939 ( .A(n5747), .B(n5780), .Y(n5750) );
NAND2X4TS U3940 ( .A(n1874), .B(n1694), .Y(n4447) );
NOR2X4TS U3941 ( .A(n5743), .B(n5153), .Y(n5878) );
NOR2X4TS U3942 ( .A(n5738), .B(n5153), .Y(n5892) );
NAND2X4TS U3943 ( .A(n5052), .B(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n3681) );
NAND2X2TS U3944 ( .A(n2746), .B(n5281), .Y(n5248) );
INVX2TS U3945 ( .A(n2313), .Y(n2259) );
NOR2X4TS U3946 ( .A(n2163), .B(n2257), .Y(n3795) );
NOR2X4TS U3947 ( .A(n2375), .B(n2255), .Y(n2906) );
NAND2X4TS U3948 ( .A(n2653), .B(n2230), .Y(n3691) );
NAND2X4TS U3949 ( .A(n3355), .B(n2847), .Y(n3563) );
INVX4TS U3950 ( .A(n4534), .Y(n4526) );
AND2X4TS U3951 ( .A(n4338), .B(n3280), .Y(n4344) );
INVX12TS U3952 ( .A(n1915), .Y(n2526) );
NAND2X4TS U3953 ( .A(n3323), .B(n2084), .Y(n3183) );
MXI2X4TS U3954 ( .A(n1905), .B(n6032), .S0(n4542), .Y(n3934) );
NOR2X6TS U3955 ( .A(n3935), .B(n3934), .Y(n4354) );
OR2X6TS U3956 ( .A(n5996), .B(n5986), .Y(n3582) );
NOR3X2TS U3957 ( .A(n1675), .B(n5995), .C(n3566), .Y(n3567) );
INVX2TS U3958 ( .A(n6002), .Y(n3566) );
INVX2TS U3959 ( .A(n1874), .Y(n4569) );
NAND2X4TS U3960 ( .A(n4736), .B(n4731), .Y(n4738) );
INVX2TS U3961 ( .A(n6001), .Y(n4097) );
NAND2X4TS U3962 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n2940) );
NOR2X2TS U3963 ( .A(n4190), .B(n4130), .Y(n3133) );
NOR2X2TS U3964 ( .A(n4169), .B(n4131), .Y(n3131) );
NOR2X2TS U3965 ( .A(n4150), .B(n4191), .Y(n3138) );
NOR2X2TS U3966 ( .A(n4170), .B(n4171), .Y(n3139) );
NAND2X2TS U3967 ( .A(n5150), .B(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(n5151) );
INVX4TS U3968 ( .A(n3900), .Y(n3097) );
INVX2TS U3969 ( .A(n4089), .Y(n3344) );
NAND2X1TS U3970 ( .A(n4246), .B(n3067), .Y(n3066) );
INVX2TS U3971 ( .A(n6255), .Y(n3070) );
INVX2TS U3972 ( .A(n3932), .Y(n3148) );
NAND2X2TS U3973 ( .A(n5104), .B(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n2812) );
NAND2X2TS U3974 ( .A(n5700), .B(n3231), .Y(n2816) );
NAND2X1TS U3975 ( .A(n4242), .B(n4243), .Y(n4244) );
INVX2TS U3976 ( .A(n6237), .Y(n3024) );
BUFX4TS U3977 ( .A(n4777), .Y(n3005) );
INVX6TS U3978 ( .A(n2403), .Y(n2404) );
NAND2X4TS U3979 ( .A(n5054), .B(n3537), .Y(n4979) );
NAND2X4TS U3980 ( .A(n5054), .B(n5053), .Y(n5748) );
NAND3X4TS U3981 ( .A(n5063), .B(n2872), .C(n5062), .Y(n5747) );
NAND2X2TS U3982 ( .A(n5900), .B(n5109), .Y(n2872) );
NAND2X4TS U3983 ( .A(n1874), .B(n4776), .Y(n4774) );
NOR2X2TS U3984 ( .A(n4738), .B(n5963), .Y(n3431) );
INVX2TS U3985 ( .A(n3088), .Y(n3087) );
NAND2X4TS U3986 ( .A(n5054), .B(n3658), .Y(n4966) );
INVX4TS U3987 ( .A(n5365), .Y(n5416) );
NAND2X2TS U3988 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n5079) );
OAI21X2TS U3989 ( .A0(n4381), .A1(n4444), .B0(n3493), .Y(n4382) );
NOR2X2TS U3990 ( .A(n6234), .B(n2422), .Y(n6057) );
NAND3X2TS U3991 ( .A(n3193), .B(n3192), .C(n3191), .Y(n3190) );
INVX2TS U3992 ( .A(n5962), .Y(n4480) );
INVX2TS U3993 ( .A(n4363), .Y(n2984) );
INVX2TS U3994 ( .A(n5183), .Y(n3226) );
INVX2TS U3995 ( .A(n1737), .Y(n5180) );
NAND2X2TS U3996 ( .A(n3668), .B(n6243), .Y(n3667) );
NAND2X4TS U3997 ( .A(n5054), .B(n4975), .Y(n5743) );
NAND2X4TS U3998 ( .A(n5054), .B(n4988), .Y(n5738) );
NAND2X2TS U3999 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n3679) );
NAND2X2TS U4000 ( .A(n5704), .B(n5109), .Y(n5015) );
NAND2X4TS U4001 ( .A(n5712), .B(n5109), .Y(n3292) );
INVX2TS U4002 ( .A(n5704), .Y(n3289) );
NAND2X2TS U4003 ( .A(n5722), .B(n5109), .Y(n5009) );
INVX4TS U4004 ( .A(n2082), .Y(n5165) );
NAND2X2TS U4005 ( .A(n5150), .B(n2763), .Y(n2958) );
AOI22X1TS U4006 ( .A0(n3269), .A1(n2382), .B0(DmP[22]), .B1(n5825), .Y(n5802) );
INVX2TS U4007 ( .A(n1931), .Y(n1932) );
AOI22X2TS U4008 ( .A0(n5860), .A1(n2374), .B0(n1862), .B1(n5859), .Y(n5762)
);
AOI22X2TS U4009 ( .A0(n5860), .A1(n2105), .B0(n1877), .B1(n5859), .Y(n5858)
);
INVX2TS U4010 ( .A(n1900), .Y(n1901) );
INVX2TS U4011 ( .A(n1926), .Y(n1927) );
INVX2TS U4012 ( .A(n1933), .Y(n1934) );
AOI2BB2X1TS U4013 ( .B0(n5829), .B1(n2102), .A0N(n1962), .A1N(n1990), .Y(
n5821) );
AOI22X1TS U4014 ( .A0(n5849), .A1(n2162), .B0(DMP[50]), .B1(n5871), .Y(n5788) );
AO22X2TS U4015 ( .A0(n5849), .A1(n2182), .B0(DmP[32]), .B1(n5871), .Y(n2005)
);
INVX2TS U4016 ( .A(n2334), .Y(n2335) );
INVX2TS U4017 ( .A(n2343), .Y(n2344) );
INVX2TS U4018 ( .A(n2361), .Y(n2362) );
INVX2TS U4019 ( .A(n2367), .Y(n2368) );
NAND2X4TS U4020 ( .A(n2035), .B(n2212), .Y(n3759) );
NOR2X4TS U4021 ( .A(n2150), .B(n2172), .Y(n3842) );
NAND2X4TS U4022 ( .A(n1870), .B(n2080), .Y(n3841) );
INVX4TS U4023 ( .A(n2168), .Y(n1953) );
NAND2X4TS U4024 ( .A(n3796), .B(n3858), .Y(n3800) );
INVX6TS U4025 ( .A(n2409), .Y(n2410) );
OAI21X2TS U4026 ( .A0(n5996), .A1(n5908), .B0(n5907), .Y(n5910) );
INVX2TS U4027 ( .A(n6003), .Y(n5907) );
INVX4TS U4028 ( .A(n4656), .Y(n3375) );
NOR2X4TS U4029 ( .A(n2941), .B(n3390), .Y(n3628) );
INVX4TS U4030 ( .A(n4366), .Y(n3449) );
INVX6TS U4031 ( .A(n3908), .Y(n3007) );
INVX12TS U4032 ( .A(n3522), .Y(n2882) );
NAND2X4TS U4033 ( .A(n3252), .B(n5255), .Y(n5257) );
INVX4TS U4034 ( .A(n3184), .Y(n3014) );
INVX6TS U4035 ( .A(n2582), .Y(n4934) );
INVX2TS U4036 ( .A(n2578), .Y(n2743) );
NAND2X4TS U4037 ( .A(n5101), .B(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n2814) );
INVX2TS U4038 ( .A(n4588), .Y(n4591) );
INVX2TS U4039 ( .A(n4079), .Y(n3175) );
INVX2TS U4040 ( .A(n4991), .Y(n4992) );
NAND2X4TS U4041 ( .A(n3168), .B(n4581), .Y(n3170) );
NAND2X4TS U4042 ( .A(n5102), .B(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n3188) );
NAND2X4TS U4043 ( .A(n5083), .B(n2743), .Y(n3186) );
INVX2TS U4044 ( .A(n4757), .Y(n4760) );
INVX2TS U4045 ( .A(n5953), .Y(n5955) );
NAND2X2TS U4046 ( .A(n5101), .B(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n2938) );
INVX6TS U4047 ( .A(n3971), .Y(n3453) );
CLKINVX3TS U4048 ( .A(n4745), .Y(n2628) );
NAND2X6TS U4049 ( .A(n3379), .B(n3378), .Y(n4833) );
NAND2X4TS U4050 ( .A(n2897), .B(exp_oper_result[0]), .Y(n5159) );
INVX6TS U4051 ( .A(n2054), .Y(n2537) );
NOR2X4TS U4052 ( .A(n4489), .B(n3599), .Y(n5925) );
INVX2TS U4053 ( .A(n4951), .Y(n4949) );
INVX6TS U4054 ( .A(n2141), .Y(n2142) );
CLKINVX6TS U4055 ( .A(n2202), .Y(n2203) );
NAND2X2TS U4056 ( .A(n5149), .B(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n2881) );
INVX2TS U4057 ( .A(n4083), .Y(n3573) );
CLKINVX12TS U4058 ( .A(n2249), .Y(n2250) );
INVX8TS U4059 ( .A(n2251), .Y(n2252) );
INVX6TS U4060 ( .A(n2253), .Y(n2254) );
INVX2TS U4061 ( .A(n4063), .Y(n4069) );
INVX2TS U4062 ( .A(n4688), .Y(n3219) );
AND2X6TS U4063 ( .A(n4854), .B(n3479), .Y(n3466) );
INVX2TS U4064 ( .A(n4605), .Y(n4198) );
INVX2TS U4065 ( .A(n2272), .Y(n5358) );
INVX2TS U4066 ( .A(n2018), .Y(n5443) );
INVX6TS U4067 ( .A(n4008), .Y(n3625) );
NAND2X4TS U4068 ( .A(n5644), .B(n5643), .Y(n5687) );
INVX2TS U4069 ( .A(n5959), .Y(n3110) );
OAI21X2TS U4070 ( .A0(n5959), .A1(n5954), .B0(n5960), .Y(n3112) );
NAND2BX1TS U4071 ( .AN(n4341), .B(n4338), .Y(n3284) );
OR2X4TS U4072 ( .A(n6054), .B(n6055), .Y(n3504) );
INVX2TS U4073 ( .A(n1941), .Y(n4308) );
INVX2TS U4074 ( .A(n5968), .Y(n1912) );
NOR2BX2TS U4075 ( .AN(n1726), .B(n4476), .Y(n3372) );
INVX2TS U4076 ( .A(n4540), .Y(n3180) );
NAND2X4TS U4077 ( .A(n3179), .B(n3178), .Y(n3177) );
INVX2TS U4078 ( .A(n4850), .Y(n3178) );
INVX2TS U4079 ( .A(n3459), .Y(n4697) );
INVX8TS U4080 ( .A(n6033), .Y(n4908) );
BUFX8TS U4081 ( .A(n4907), .Y(n3262) );
INVX2TS U4082 ( .A(n2952), .Y(n2306) );
NOR2X4TS U4083 ( .A(n5783), .B(n5153), .Y(n5114) );
INVX4TS U4084 ( .A(n5679), .Y(n5653) );
INVX4TS U4085 ( .A(n5679), .Y(n5662) );
INVX6TS U4086 ( .A(n6051), .Y(n5476) );
INVX2TS U4087 ( .A(n1971), .Y(n1972) );
INVX2TS U4088 ( .A(n1887), .Y(n1888) );
INVX2TS U4089 ( .A(n1889), .Y(n1890) );
NAND2X2TS U4090 ( .A(n5065), .B(n2662), .Y(n5040) );
NAND4BX2TS U4091 ( .AN(n3687), .B(n3686), .C(n3685), .D(n3684), .Y(n1474) );
NAND2X2TS U4092 ( .A(n5120), .B(n5885), .Y(n3686) );
AOI22X1TS U4093 ( .A0(n2722), .A1(n5722), .B0(n5784), .B1(n1992), .Y(n5012)
);
NAND2X2TS U4094 ( .A(n6086), .B(n2071), .Y(n3010) );
INVX2TS U4095 ( .A(n2087), .Y(n2088) );
NAND2X2TS U4096 ( .A(n5113), .B(n5112), .Y(n1456) );
NAND2X2TS U4097 ( .A(n2057), .B(n2664), .Y(n5113) );
INVX2TS U4098 ( .A(n2099), .Y(n2100) );
INVX2TS U4099 ( .A(n2102), .Y(n2103) );
INVX2TS U4100 ( .A(n5138), .Y(n2932) );
NAND2X2TS U4101 ( .A(n5999), .B(n3070), .Y(n3069) );
NAND4X2TS U4102 ( .A(n4945), .B(n4944), .C(n4943), .D(n4942), .Y(n4946) );
INVX2TS U4103 ( .A(n2134), .Y(n2135) );
INVX2TS U4104 ( .A(n2156), .Y(n2157) );
INVX2TS U4105 ( .A(n2180), .Y(n2181) );
INVX2TS U4106 ( .A(n2182), .Y(n2183) );
INVX2TS U4107 ( .A(n2192), .Y(n2193) );
INVX2TS U4108 ( .A(n2207), .Y(n2208) );
NAND3X2TS U4109 ( .A(n2811), .B(n2810), .C(n2809), .Y(n1488) );
NAND2X2TS U4110 ( .A(n2753), .B(n5733), .Y(n2809) );
NAND2X2TS U4111 ( .A(n5731), .B(n5780), .Y(n2811) );
INVX2TS U4112 ( .A(n2225), .Y(n2226) );
INVX2TS U4113 ( .A(n2230), .Y(n2231) );
INVX2TS U4114 ( .A(n2255), .Y(n2256) );
INVX2TS U4115 ( .A(n2257), .Y(n2258) );
INVX2TS U4116 ( .A(n2263), .Y(n2264) );
INVX2TS U4117 ( .A(n2265), .Y(n2266) );
NAND2X2TS U4118 ( .A(n2781), .B(n5197), .Y(n2795) );
INVX2TS U4119 ( .A(n2285), .Y(n2286) );
INVX2TS U4120 ( .A(n2287), .Y(n2288) );
INVX2TS U4121 ( .A(n2289), .Y(n2290) );
INVX2TS U4122 ( .A(n2291), .Y(n2292) );
INVX2TS U4123 ( .A(n2293), .Y(n2294) );
INVX2TS U4124 ( .A(n2304), .Y(n2305) );
INVX2TS U4125 ( .A(n2309), .Y(n2310) );
INVX2TS U4126 ( .A(n2311), .Y(n2312) );
INVX2TS U4127 ( .A(n2316), .Y(n2317) );
INVX2TS U4128 ( .A(n2321), .Y(n2322) );
INVX2TS U4129 ( .A(n2331), .Y(n2332) );
INVX2TS U4130 ( .A(n2336), .Y(n2337) );
INVX2TS U4131 ( .A(n2354), .Y(n2355) );
INVX2TS U4132 ( .A(n2356), .Y(n2357) );
INVX2TS U4133 ( .A(n2376), .Y(n2377) );
BUFX3TS U4134 ( .A(n6450), .Y(n6439) );
INVX2TS U4135 ( .A(n2382), .Y(n2383) );
INVX2TS U4136 ( .A(n2391), .Y(n2392) );
INVX2TS U4137 ( .A(n2395), .Y(n2396) );
INVX2TS U4138 ( .A(n2397), .Y(n2398) );
INVX2TS U4139 ( .A(n2399), .Y(n2400) );
INVX2TS U4140 ( .A(n2401), .Y(n2402) );
OAI21X2TS U4141 ( .A0(n5877), .A1(n5878), .B0(n2663), .Y(n5047) );
BUFX3TS U4142 ( .A(n4869), .Y(n6446) );
INVX2TS U4143 ( .A(n2436), .Y(n2437) );
INVX2TS U4144 ( .A(n2439), .Y(n2440) );
INVX2TS U4145 ( .A(n2447), .Y(n2448) );
INVX2TS U4146 ( .A(n4324), .Y(n2458) );
NAND2X2TS U4147 ( .A(n5742), .B(n2662), .Y(n4977) );
INVX2TS U4148 ( .A(n2870), .Y(n2871) );
NOR2X2TS U4149 ( .A(n4605), .B(n4607), .Y(n4609) );
NOR2X2TS U4150 ( .A(n4826), .B(n4774), .Y(n4781) );
INVX2TS U4151 ( .A(n2626), .Y(n2627) );
INVX3TS U4152 ( .A(rst), .Y(n2745) );
NAND2X2TS U4153 ( .A(n4741), .B(n3429), .Y(n4742) );
NAND2X2TS U4154 ( .A(n6406), .B(n2650), .Y(n3276) );
BUFX3TS U4155 ( .A(n4868), .Y(n6443) );
INVX2TS U4156 ( .A(n2665), .Y(n2666) );
NOR2X4TS U4157 ( .A(n6028), .B(n3244), .Y(n4894) );
CLKBUFX3TS U4158 ( .A(n2737), .Y(n4870) );
BUFX3TS U4159 ( .A(n4868), .Y(n6441) );
NAND2X2TS U4160 ( .A(n3085), .B(n6060), .Y(n3084) );
AOI22X1TS U4161 ( .A0(n2712), .A1(n5568), .B0(n5567), .B1(n5566), .Y(n5577)
);
BUFX3TS U4162 ( .A(n6264), .Y(n6419) );
NAND4X4TS U4163 ( .A(n2523), .B(n2929), .C(n2928), .D(n2926), .Y(n6453) );
INVX3TS U4164 ( .A(rst), .Y(n2744) );
NOR2X2TS U4165 ( .A(n4826), .B(n4385), .Y(n4387) );
AOI22X2TS U4166 ( .A0(n2596), .A1(n2151), .B0(DMP[44]), .B1(n3230), .Y(n5850) );
NAND2X4TS U4167 ( .A(n4978), .B(n5780), .Y(n3540) );
AOI2BB2X2TS U4168 ( .B0(n2975), .B1(n2334), .A0N(n2121), .A1N(n5768), .Y(
n5814) );
INVX2TS U4169 ( .A(intDY[45]), .Y(n6154) );
BUFX3TS U4170 ( .A(n6272), .Y(n6418) );
NAND2X4TS U4171 ( .A(n3189), .B(n2490), .Y(n1468) );
NAND2X2TS U4172 ( .A(n5075), .B(n1647), .Y(n3189) );
MXI2X2TS U4173 ( .A(n5939), .B(n5938), .S0(n6038), .Y(n6526) );
MXI2X2TS U4174 ( .A(n4377), .B(n4376), .S0(n3023), .Y(n6461) );
BUFX3TS U4175 ( .A(n2736), .Y(n6450) );
CLKBUFX3TS U4176 ( .A(n6269), .Y(n6265) );
CLKBUFX3TS U4177 ( .A(n6268), .Y(n6266) );
NAND4X2TS U4178 ( .A(n2601), .B(n2600), .C(n2598), .D(n2597), .Y(n6518) );
INVX2TS U4179 ( .A(n2997), .Y(n2994) );
CLKBUFX3TS U4180 ( .A(n6438), .Y(n6267) );
BUFX3TS U4181 ( .A(n4869), .Y(n6408) );
BUFX3TS U4182 ( .A(n4869), .Y(n6409) );
BUFX3TS U4183 ( .A(n4869), .Y(n6410) );
BUFX3TS U4184 ( .A(n4871), .Y(n6411) );
CLKBUFX3TS U4185 ( .A(n2736), .Y(n4868) );
CLKBUFX3TS U4186 ( .A(n2736), .Y(n4869) );
CLKBUFX3TS U4187 ( .A(n6450), .Y(n4871) );
BUFX3TS U4188 ( .A(n4871), .Y(n6412) );
NAND2X2TS U4189 ( .A(n1695), .B(n5177), .Y(n2073) );
CLKBUFX3TS U4190 ( .A(n6420), .Y(n6268) );
CLKBUFX3TS U4191 ( .A(n4871), .Y(n6272) );
INVX2TS U4192 ( .A(n2187), .Y(n4235) );
CLKBUFX3TS U4193 ( .A(n4871), .Y(n6263) );
INVX2TS U4194 ( .A(n5999), .Y(n2455) );
CLKBUFX3TS U4195 ( .A(n4871), .Y(n6271) );
CLKINVX3TS U4196 ( .A(rst), .Y(n2736) );
NAND2X4TS U4197 ( .A(n2947), .B(n2946), .Y(n2945) );
NAND2X4TS U4198 ( .A(n5891), .B(n5897), .Y(n2946) );
CLKBUFX3TS U4199 ( .A(n4871), .Y(n6270) );
BUFX3TS U4200 ( .A(n4869), .Y(n6449) );
BUFX3TS U4201 ( .A(n6450), .Y(n6417) );
BUFX3TS U4202 ( .A(n4869), .Y(n6430) );
BUFX3TS U4203 ( .A(n2736), .Y(n6425) );
BUFX3TS U4204 ( .A(n4868), .Y(n6422) );
BUFX3TS U4205 ( .A(n4868), .Y(n6431) );
BUFX3TS U4206 ( .A(n2737), .Y(n6432) );
BUFX3TS U4207 ( .A(n2737), .Y(n6428) );
BUFX3TS U4208 ( .A(n2737), .Y(n6427) );
BUFX3TS U4209 ( .A(n2737), .Y(n6426) );
BUFX3TS U4210 ( .A(n4871), .Y(n6424) );
XNOR2X2TS U4211 ( .A(n2497), .B(n4927), .Y(n4928) );
INVX2TS U4212 ( .A(n5765), .Y(n2956) );
NAND2X4TS U4213 ( .A(n4517), .B(n4518), .Y(n3429) );
NAND2X8TS U4214 ( .A(n3528), .B(n3256), .Y(n1852) );
OAI21X4TS U4215 ( .A0(n3238), .A1(n1598), .B0(n4830), .Y(n1853) );
CLKBUFX2TS U4216 ( .A(n3965), .Y(n2892) );
BUFX4TS U4217 ( .A(n4040), .Y(n1977) );
NAND3X8TS U4218 ( .A(n2841), .B(n5926), .C(n2842), .Y(n2840) );
NOR2X4TS U4219 ( .A(n4489), .B(n3599), .Y(n2386) );
OR2X8TS U4220 ( .A(n4079), .B(n4077), .Y(n4090) );
AOI21X2TS U4221 ( .A0(n4846), .A1(n3049), .B0(n2762), .Y(n3482) );
INVX2TS U4222 ( .A(n1857), .Y(n1858) );
NOR2X8TS U4223 ( .A(n1860), .B(n1861), .Y(n1859) );
AND3X6TS U4224 ( .A(n2314), .B(n3588), .C(n6221), .Y(n1861) );
NOR2X8TS U4225 ( .A(n2914), .B(n3080), .Y(n1863) );
NOR2X4TS U4226 ( .A(n3080), .B(n2914), .Y(n2913) );
INVX6TS U4227 ( .A(n4415), .Y(n3080) );
NOR2X4TS U4228 ( .A(n3214), .B(n3391), .Y(n1981) );
NAND2X4TS U4229 ( .A(n3451), .B(n1586), .Y(n1864) );
OA21X4TS U4230 ( .A0(n2085), .A1(n4457), .B0(n4458), .Y(n1865) );
NAND2X6TS U4231 ( .A(n2481), .B(n4275), .Y(n4471) );
NOR2X8TS U4232 ( .A(n4254), .B(n4255), .Y(n4337) );
NOR2X4TS U4233 ( .A(n4399), .B(n4540), .Y(n1866) );
INVX16TS U4234 ( .A(n3394), .Y(n3105) );
OAI21X2TS U4235 ( .A0(n4753), .A1(n3489), .B0(n3488), .Y(n3487) );
NOR2X6TS U4236 ( .A(n5985), .B(n6007), .Y(n4590) );
OAI21X2TS U4237 ( .A0(n4749), .A1(n4549), .B0(n4748), .Y(n4750) );
AO22X2TS U4238 ( .A0(n2739), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n5150), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n2058) );
NAND2X4TS U4239 ( .A(n2140), .B(n2319), .Y(n3953) );
OAI2BB1X4TS U4240 ( .A0N(n4407), .A1N(n1770), .B0(n4409), .Y(n4464) );
XOR2X4TS U4241 ( .A(n3922), .B(n2624), .Y(n2319) );
NOR2BX1TS U4242 ( .AN(n4649), .B(n4653), .Y(n4654) );
NOR2X8TS U4243 ( .A(n4633), .B(n4634), .Y(n4649) );
OR2X6TS U4244 ( .A(n3986), .B(n3985), .Y(n1871) );
NOR2X8TS U4245 ( .A(n4028), .B(n4023), .Y(n4029) );
NOR2X8TS U4246 ( .A(n3624), .B(n3509), .Y(n4227) );
INVX16TS U4247 ( .A(n2274), .Y(n4845) );
CLKINVX12TS U4248 ( .A(n4012), .Y(n3626) );
NOR2X8TS U4249 ( .A(n4036), .B(n6229), .Y(n4012) );
OAI21X1TS U4250 ( .A0(underflow_flag), .A1(sign_final_result), .B0(n1821),
.Y(n6015) );
OAI21X1TS U4251 ( .A0(n5183), .A1(n1737), .B0(n5182), .Y(n5184) );
NOR2X1TS U4252 ( .A(n5181), .B(n1737), .Y(n5185) );
OR2X8TS U4253 ( .A(n1862), .B(n2752), .Y(n2972) );
INVX16TS U4254 ( .A(n1799), .Y(n2752) );
NOR2X6TS U4255 ( .A(n2711), .B(n2518), .Y(n3945) );
NOR2X6TS U4256 ( .A(n5983), .B(n2714), .Y(n3917) );
NAND2X8TS U4257 ( .A(n2703), .B(n2714), .Y(n2779) );
BUFX20TS U4258 ( .A(n2624), .Y(n2777) );
NAND2X6TS U4259 ( .A(n3443), .B(n2351), .Y(n3442) );
NAND2X6TS U4260 ( .A(n3105), .B(n2352), .Y(n3122) );
NAND2X4TS U4261 ( .A(n3395), .B(n1998), .Y(n3121) );
NAND2X4TS U4262 ( .A(n3395), .B(n2139), .Y(n3222) );
NAND2X2TS U4263 ( .A(n4024), .B(n4393), .Y(n4007) );
AND3X4TS U4264 ( .A(n3033), .B(n3031), .C(n3028), .Y(n1876) );
NOR2X8TS U4265 ( .A(n4290), .B(n3306), .Y(n4292) );
XNOR2X1TS U4266 ( .A(n2043), .B(n1850), .Y(n4122) );
AOI2BB2X4TS U4267 ( .B0(n2740), .B1(n2263), .A0N(n1858), .A1N(n2039), .Y(
n5803) );
AOI22X4TS U4268 ( .A0(n2718), .A1(n2251), .B0(DMP[56]), .B1(n5820), .Y(n5775) );
OAI2BB1X4TS U4269 ( .A0N(n2734), .A1N(n1942), .B0(n5837), .Y(n1166) );
AND2X8TS U4270 ( .A(n1859), .B(n3335), .Y(n1882) );
MXI2X4TS U4271 ( .A(n2462), .B(n2075), .S0(n2465), .Y(n2038) );
OAI2BB1X4TS U4272 ( .A0N(n2434), .A1N(n5831), .B0(n1891), .Y(n1136) );
AOI22X2TS U4273 ( .A0(n5849), .A1(n2293), .B0(DmP[31]), .B1(n5777), .Y(n1891) );
OAI2BB1X4TS U4274 ( .A0N(n1916), .A1N(n5831), .B0(n5828), .Y(n1135) );
NAND2BX4TS U4275 ( .AN(n3977), .B(n3100), .Y(n4219) );
NOR2X8TS U4276 ( .A(n4036), .B(n1980), .Y(n3977) );
OAI21X4TS U4277 ( .A0(n4606), .A1(n4432), .B0(n4433), .Y(n3036) );
AOI22X2TS U4278 ( .A0(n2718), .A1(n2257), .B0(n1896), .B1(n1645), .Y(n5815)
);
AOI22X2TS U4279 ( .A0(n2718), .A1(n2343), .B0(n1897), .B1(n1645), .Y(n5816)
);
NOR2X8TS U4280 ( .A(n3390), .B(n2941), .Y(n2177) );
AOI2BB2X4TS U4281 ( .B0(n2976), .B1(n2247), .A0N(n1990), .A1N(n6224), .Y(
n5771) );
NAND2X8TS U4282 ( .A(n2912), .B(n2911), .Y(n3043) );
INVX4TS U4283 ( .A(n5963), .Y(n4601) );
NAND2X8TS U4284 ( .A(n4196), .B(n3038), .Y(n1915) );
AND3X2TS U4285 ( .A(n1816), .B(n4483), .C(n4482), .Y(n4484) );
AND2X4TS U4286 ( .A(n4483), .B(n3578), .Y(n2543) );
BUFX4TS U4287 ( .A(n4228), .Y(n1920) );
NAND2X4TS U4288 ( .A(n3762), .B(n3739), .Y(n3740) );
AND3X8TS U4289 ( .A(n3551), .B(n3218), .C(n3550), .Y(n2647) );
NAND2X8TS U4290 ( .A(n2917), .B(n2916), .Y(n1918) );
AND2X8TS U4291 ( .A(n2671), .B(Sgf_normalized_result[43]), .Y(n4274) );
OAI2BB1X2TS U4292 ( .A0N(n5851), .A1N(n1850), .B0(n5839), .Y(n1217) );
NAND2X6TS U4293 ( .A(n2033), .B(n2481), .Y(n4454) );
INVX8TS U4294 ( .A(n3476), .Y(n3039) );
NAND2X4TS U4295 ( .A(n2752), .B(n2284), .Y(n3151) );
NOR2X4TS U4296 ( .A(n4673), .B(n4292), .Y(n1919) );
NOR2X8TS U4297 ( .A(n4288), .B(n4289), .Y(n4673) );
NAND4X8TS U4298 ( .A(n3354), .B(n3581), .C(n2543), .D(n2485), .Y(n4083) );
OAI2BB1X4TS U4299 ( .A0N(n2369), .A1N(n5827), .B0(n5794), .Y(n1120) );
OAI2BB1X4TS U4300 ( .A0N(n2060), .A1N(n5856), .B0(n5793), .Y(n1119) );
OR2X8TS U4301 ( .A(n4508), .B(n4522), .Y(n2519) );
NOR2X6TS U4302 ( .A(n4523), .B(n4522), .Y(n4765) );
NAND3X6TS U4303 ( .A(n3050), .B(n3272), .C(n4661), .Y(n3155) );
AOI2BB2X4TS U4304 ( .B0(n2976), .B1(n2626), .A0N(n2028), .A1N(n2023), .Y(
n5866) );
OAI2BB1X4TS U4305 ( .A0N(n2374), .A1N(n5827), .B0(n5796), .Y(n1123) );
AOI2BB2X4TS U4306 ( .B0(n2741), .B1(n2395), .A0N(n1967), .A1N(n1990), .Y(
n5841) );
AO21X4TS U4307 ( .A0(n2735), .A1(n2034), .B0(n1928), .Y(n1131) );
OR2X8TS U4308 ( .A(n1950), .B(n2615), .Y(n5164) );
OR2X8TS U4309 ( .A(n3511), .B(n2238), .Y(n2615) );
AOI2BB2X2TS U4310 ( .B0(n2718), .B1(n2132), .A0N(n1903), .A1N(n2039), .Y(
n5791) );
NOR2X6TS U4311 ( .A(n4477), .B(n4365), .Y(n3450) );
NAND2X4TS U4312 ( .A(n4836), .B(n2550), .Y(n3000) );
OAI2BB1X4TS U4313 ( .A0N(n1735), .A1N(n5856), .B0(n5822), .Y(n1134) );
AO21X4TS U4314 ( .A0(n4307), .A1(n4479), .B0(n4306), .Y(n1941) );
OAI21X4TS U4315 ( .A0(n5207), .A1(n5206), .B0(n1978), .Y(n5212) );
NOR2X8TS U4316 ( .A(n4036), .B(n2216), .Y(n3985) );
INVX8TS U4317 ( .A(n4666), .Y(n3365) );
NAND2XLTS U4318 ( .A(n4936), .B(n2799), .Y(n4927) );
AOI2BB2X2TS U4319 ( .B0(n2976), .B1(n2397), .A0N(n1927), .A1N(n2028), .Y(
n5844) );
AOI2BB2X2TS U4320 ( .B0(n2732), .B1(n2178), .A0N(n2351), .A1N(n2360), .Y(
n5131) );
AOI2BB2X2TS U4321 ( .B0(n2732), .B1(n2434), .A0N(n2352), .A1N(n2360), .Y(
n5130) );
AOI2BB2X2TS U4322 ( .B0(n2732), .B1(n1735), .A0N(n2353), .A1N(n2360), .Y(
n5204) );
AOI2BB2X2TS U4323 ( .B0(n2732), .B1(n2403), .A0N(n1972), .A1N(n2360), .Y(
n5806) );
NOR2X8TS U4324 ( .A(n3490), .B(n4242), .Y(n3232) );
NOR2X8TS U4325 ( .A(n2522), .B(n3227), .Y(n3973) );
OAI2BB2X4TS U4326 ( .B0(n1949), .B1(n2696), .A0N(n5673), .A1N(n5686), .Y(
n1948) );
INVX6TS U4327 ( .A(n2695), .Y(n2696) );
AOI22X2TS U4328 ( .A0(n2596), .A1(n2291), .B0(n5807), .B1(DmP[14]), .Y(n5793) );
AOI22X2TS U4329 ( .A0(n2596), .A1(n2287), .B0(n5777), .B1(DmP[15]), .Y(n5794) );
AOI22X2TS U4330 ( .A0(n2596), .A1(n2255), .B0(DmP[18]), .B1(n5807), .Y(n5796) );
BUFX12TS U4331 ( .A(n5752), .Y(n2596) );
NAND2X8TS U4332 ( .A(n1918), .B(n3900), .Y(n4936) );
NAND2X8TS U4333 ( .A(n2229), .B(n1953), .Y(n1952) );
NOR2X8TS U4334 ( .A(n4453), .B(n4299), .Y(n5962) );
AOI2BB2X2TS U4335 ( .B0(n2975), .B1(n2361), .A0N(n2029), .A1N(n2028), .Y(
n5868) );
AOI22X2TS U4336 ( .A0(n2730), .A1(n2432), .B0(n2045), .B1(n1645), .Y(n5725)
);
AOI22X2TS U4337 ( .A0(n5860), .A1(n2190), .B0(n2295), .B1(n1645), .Y(n5727)
);
AO21X4TS U4338 ( .A0(n2095), .A1(n2734), .B0(n1954), .Y(n1139) );
AO22X4TS U4339 ( .A0(n3269), .A1(n2401), .B0(DmP[34]), .B1(n5820), .Y(n1954)
);
AOI2BB2X1TS U4340 ( .B0(n3269), .B1(n2331), .A0N(n1934), .A1N(n2028), .Y(
n5819) );
AOI2BB2X1TS U4341 ( .B0(n3269), .B1(n2321), .A0N(n1932), .A1N(n2039), .Y(
n5840) );
AOI2BB2X4TS U4342 ( .B0(n5736), .B1(n2164), .A0N(n1946), .A1N(n2028), .Y(
n5846) );
AOI22X1TS U4343 ( .A0(n5572), .A1(n2700), .B0(n2761), .B1(n5567), .Y(n5562)
);
AOI2BB2X2TS U4344 ( .B0(n2975), .B1(n2225), .A0N(n1957), .A1N(n2039), .Y(
n5833) );
NOR2X6TS U4345 ( .A(n5214), .B(n5208), .Y(n4419) );
NAND3X2TS U4346 ( .A(n5920), .B(n3604), .C(Add_Subt_result[16]), .Y(n3576)
);
AOI21X4TS U4347 ( .A0(n4466), .A1(n4462), .B0(n4422), .Y(n4424) );
OA21X4TS U4348 ( .A0(n4753), .A1(n4752), .B0(n4751), .Y(n2533) );
BUFX12TS U4349 ( .A(n5752), .Y(n5760) );
NOR2X6TS U4350 ( .A(Sgf_normalized_result[26]), .B(n3008), .Y(n2943) );
XOR2X4TS U4351 ( .A(n2454), .B(n1646), .Y(n4660) );
NOR2X4TS U4352 ( .A(n3878), .B(n3806), .Y(n2074) );
OR2X8TS U4353 ( .A(n3105), .B(n1833), .Y(n3441) );
AOI2BB2X4TS U4354 ( .B0(n2730), .B1(n2223), .A0N(n2040), .A1N(n2360), .Y(
n5838) );
INVX12TS U4355 ( .A(n3102), .Y(n4284) );
AO21X4TS U4356 ( .A0(n2253), .A1(n2735), .B0(n1963), .Y(n1199) );
AO22X4TS U4357 ( .A0(n5736), .A1(n1916), .B0(n2415), .B1(n5825), .Y(n1963)
);
NAND3BX4TS U4358 ( .AN(n3257), .B(n2316), .C(n3927), .Y(n3929) );
INVX2TS U4359 ( .A(n4341), .Y(n1964) );
OAI21X4TS U4360 ( .A0(n4634), .A1(n5940), .B0(n4635), .Y(n2684) );
NOR2X8TS U4361 ( .A(n4206), .B(n3622), .Y(n3064) );
MX2X4TS U4362 ( .A(DMP[56]), .B(exp_oper_result[4]), .S0(n2850), .Y(n2513)
);
CLKINVX12TS U4363 ( .A(n3419), .Y(n3413) );
NAND2X8TS U4364 ( .A(n4612), .B(n3980), .Y(n4000) );
OR2X4TS U4365 ( .A(n3306), .B(n1595), .Y(n1982) );
NOR2X8TS U4366 ( .A(n2184), .B(n6218), .Y(n4272) );
AOI21X4TS U4367 ( .A0(n6008), .A1(n5917), .B0(n4491), .Y(n4492) );
NOR2X8TS U4368 ( .A(n1823), .B(n4064), .Y(n4326) );
AND2X8TS U4369 ( .A(n4284), .B(n4269), .Y(n1983) );
NOR2X8TS U4370 ( .A(n3890), .B(n3623), .Y(n3045) );
OA21X1TS U4371 ( .A0(n1711), .A1(n4653), .B0(n4652), .Y(n2500) );
CLKAND2X2TS U4372 ( .A(n4709), .B(n4710), .Y(n2499) );
MXI2X4TS U4373 ( .A(n1911), .B(n6211), .S0(n2865), .Y(n2532) );
NOR2X4TS U4374 ( .A(n4747), .B(n2457), .Y(n4368) );
NOR2X4TS U4375 ( .A(n4752), .B(n4747), .Y(n2575) );
AND2X8TS U4376 ( .A(n2708), .B(n4065), .Y(n4333) );
INVX12TS U4377 ( .A(n1842), .Y(n2990) );
NAND2X2TS U4378 ( .A(n4256), .B(n4257), .Y(n4258) );
OR2X6TS U4379 ( .A(n3493), .B(n4347), .Y(n2903) );
NOR2X8TS U4380 ( .A(n4256), .B(n4250), .Y(n4347) );
OA21X1TS U4381 ( .A0(n4723), .A1(n1722), .B0(n4724), .Y(n2476) );
NOR2X4TS U4382 ( .A(n2704), .B(n1843), .Y(n5975) );
NOR2BX4TS U4383 ( .AN(n2678), .B(FSM_selector_B_1_), .Y(n2900) );
NAND2X6TS U4384 ( .A(n2895), .B(n2900), .Y(n3926) );
BUFX12TS U4385 ( .A(n5274), .Y(n3252) );
AND2X8TS U4386 ( .A(n2682), .B(n2453), .Y(n2563) );
NOR2X6TS U4387 ( .A(n4012), .B(n3154), .Y(n4023) );
NOR2X4TS U4388 ( .A(n2491), .B(n3364), .Y(n3354) );
NAND3X8TS U4389 ( .A(n6283), .B(n6282), .C(n6281), .Y(n5998) );
AOI2BB2X2TS U4390 ( .B0(n2740), .B1(n2636), .A0N(n2028), .A1N(n1888), .Y(
n5865) );
NOR2X8TS U4391 ( .A(n4067), .B(n4326), .Y(n4251) );
INVX6TS U4392 ( .A(n3149), .Y(n3933) );
NAND2X2TS U4393 ( .A(n2848), .B(n2516), .Y(n4797) );
NAND2X8TS U4394 ( .A(n2671), .B(n1893), .Y(n2916) );
NOR2X4TS U4395 ( .A(n4862), .B(n3227), .Y(n3386) );
AOI2BB2X2TS U4396 ( .B0(n5760), .B1(n2200), .A0N(n1996), .A1N(n2028), .Y(
n5837) );
OAI2BB1X4TS U4397 ( .A0N(n5851), .A1N(n2393), .B0(n5870), .Y(n1147) );
AOI22X2TS U4398 ( .A0(n5760), .A1(n2309), .B0(DmP[42]), .B1(n5871), .Y(n5870) );
AO21X4TS U4399 ( .A0(n2202), .A1(n5862), .B0(n1999), .Y(n1113) );
AO22X4TS U4400 ( .A0(n5849), .A1(n2387), .B0(DmP[8]), .B1(n5777), .Y(n1999)
);
NAND2X6TS U4401 ( .A(n4723), .B(n4724), .Y(n2980) );
OAI2BB1X4TS U4402 ( .A0N(n5845), .A1N(n2257), .B0(n5788), .Y(n1219) );
AO21X4TS U4403 ( .A0(n2178), .A1(n5831), .B0(n2005), .Y(n1137) );
OAI21X2TS U4404 ( .A0(n4026), .A1(n2966), .B0(n4011), .Y(n4391) );
AOI22X2TS U4405 ( .A0(n2976), .A1(n2289), .B0(n1939), .B1(n5842), .Y(n5836)
);
AO22X4TS U4406 ( .A0(n2976), .A1(n2180), .B0(DmP[54]), .B1(n5871), .Y(n2037)
);
XOR2X4TS U4407 ( .A(n2863), .B(n2011), .Y(n4756) );
OR2X8TS U4408 ( .A(n3736), .B(n2014), .Y(n3774) );
NAND2BX4TS U4409 ( .AN(n3769), .B(n3737), .Y(n2014) );
AOI2BB2X2TS U4410 ( .B0(n2976), .B1(n2243), .A0N(n2028), .A1N(n1924), .Y(
n5770) );
XOR2X4TS U4411 ( .A(n2015), .B(n2016), .Y(n5931) );
AND2X4TS U4412 ( .A(n3967), .B(n3966), .Y(n2016) );
NOR2X4TS U4413 ( .A(n1881), .B(n2850), .Y(n3397) );
MXI2X8TS U4414 ( .A(n1936), .B(n6215), .S0(n2850), .Y(n4524) );
AO22X4TS U4415 ( .A0(n2676), .A1(n5478), .B0(n5608), .B1(n5668), .Y(n2018)
);
AOI22X2TS U4416 ( .A0(n5760), .A1(n2253), .B0(DmP[30]), .B1(n5820), .Y(n5828) );
AOI22X2TS U4417 ( .A0(n5760), .A1(n2313), .B0(DmP[25]), .B1(n5820), .Y(n5753) );
AOI22X2TS U4418 ( .A0(n5760), .A1(n2156), .B0(DmP[20]), .B1(n5825), .Y(n5804) );
AND2X6TS U4419 ( .A(n3410), .B(n3165), .Y(n2020) );
BUFX20TS U4420 ( .A(n3663), .Y(n5082) );
MXI2X4TS U4421 ( .A(n2010), .B(n2024), .S0(n1648), .Y(n1496) );
NAND2X4TS U4422 ( .A(n4099), .B(n3553), .Y(n3554) );
AOI21X2TS U4423 ( .A0(n4102), .A1(n3239), .B0(n5943), .Y(n5949) );
AOI22X2TS U4424 ( .A0(n2674), .A1(n5683), .B0(n5654), .B1(n5682), .Y(n5651)
);
NOR2X8TS U4425 ( .A(n1823), .B(n4060), .Y(n4773) );
NOR2BX4TS U4426 ( .AN(n5516), .B(n3358), .Y(n2026) );
NOR2X4TS U4427 ( .A(n2668), .B(n2022), .Y(n3908) );
OAI2BB1X4TS U4428 ( .A0N(n2141), .A1N(n2735), .B0(n5824), .Y(n1138) );
AOI2BB2X2TS U4429 ( .B0(n2740), .B1(n2232), .A0N(n2360), .A1N(n1890), .Y(
n5864) );
AOI2BB2X4TS U4430 ( .B0(n2730), .B1(n2336), .A0N(n2030), .A1N(n2039), .Y(
n5869) );
XOR2X4TS U4431 ( .A(n2036), .B(n2478), .Y(n4662) );
AOI21X4TS U4432 ( .A0(n3050), .A1(n4661), .B0(n1643), .Y(n2036) );
NAND2X4TS U4433 ( .A(n5116), .B(n2421), .Y(n5091) );
AO21X4TS U4434 ( .A0(n5827), .A1(n2132), .B0(n2037), .Y(n1159) );
AOI2BB2X2TS U4435 ( .B0(n2718), .B1(n2439), .A0N(n2039), .A1N(n1901), .Y(
n5875) );
NAND2X4TS U4436 ( .A(n3100), .B(n3977), .Y(n5182) );
OAI2BB1X4TS U4437 ( .A0N(n5876), .A1N(n2265), .B0(n5775), .Y(n1225) );
OAI2BB1X4TS U4438 ( .A0N(n5876), .A1N(n2395), .B0(n5789), .Y(n1222) );
NAND3X8TS U4439 ( .A(n5339), .B(n5338), .C(n5337), .Y(n5561) );
OAI2BB1X4TS U4440 ( .A0N(n2063), .A1N(n2735), .B0(n5800), .Y(n1117) );
AOI22X2TS U4441 ( .A0(n1872), .A1(n5760), .B0(DmP[12]), .B1(n5874), .Y(n5800) );
OAI2BB1X4TS U4442 ( .A0N(n5831), .A1N(n2311), .B0(n5848), .Y(n1212) );
OAI2BB1X4TS U4443 ( .A0N(n2735), .A1N(n2313), .B0(n5858), .Y(n1194) );
OAI2BB1X4TS U4444 ( .A0N(n5862), .A1N(n2080), .B0(n5754), .Y(n1215) );
OAI2BB1X4TS U4445 ( .A0N(n5862), .A1N(n2636), .B0(n4313), .Y(n1172) );
OAI2BB1X4TS U4446 ( .A0N(n2331), .A1N(n5862), .B0(n5205), .Y(n1196) );
OAI2BB1X4TS U4447 ( .A0N(n2212), .A1N(n5831), .B0(n5855), .Y(n1195) );
NOR2X8TS U4448 ( .A(n2856), .B(n2854), .Y(n2853) );
AOI22X2TS U4449 ( .A0(n2741), .A1(n2041), .B0(n1960), .B1(n5735), .Y(n5099)
);
OAI2BB1X4TS U4450 ( .A0N(n5831), .A1N(n2626), .B0(n5725), .Y(n1174) );
MXI2X8TS U4451 ( .A(n2412), .B(n6034), .S0(n4542), .Y(n3937) );
AOI2BB2X4TS U4452 ( .B0(n1869), .B1(n2081), .A0N(n2150), .A1N(n2172), .Y(
n2049) );
NOR2X2TS U4453 ( .A(n4835), .B(n4765), .Y(n4768) );
NOR2X2TS U4454 ( .A(n4835), .B(n4528), .Y(n4529) );
AOI2BB2X4TS U4455 ( .B0(n2730), .B1(n2087), .A0N(n2051), .A1N(n2360), .Y(
n5834) );
NOR2X8TS U4456 ( .A(n4773), .B(n4333), .Y(n4379) );
NAND2X4TS U4457 ( .A(n3564), .B(n3565), .Y(n2491) );
NAND2X6TS U4458 ( .A(n4107), .B(n4475), .Y(n4397) );
OAI2BB2X4TS U4459 ( .B0(n2053), .B1(n2681), .A0N(n5615), .A1N(n5661), .Y(
n2052) );
OAI2BB1X4TS U4460 ( .A0N(n6222), .A1N(n3602), .B0(n4080), .Y(n2054) );
AND3X6TS U4461 ( .A(n5430), .B(n5429), .C(n5428), .Y(n2055) );
XNOR2X4TS U4462 ( .A(n3416), .B(n2569), .Y(n2056) );
NAND3BX4TS U4463 ( .AN(n2058), .B(n5111), .C(n5110), .Y(n2057) );
OR2X8TS U4464 ( .A(n3124), .B(n3637), .Y(n5176) );
AOI21X1TS U4465 ( .A0(n5784), .A1(n2210), .B0(n2726), .Y(n2810) );
NOR2X4TS U4466 ( .A(n4516), .B(n4515), .Y(n4729) );
MXI2X4TS U4467 ( .A(n2415), .B(n1991), .S0(n3395), .Y(n2062) );
INVX8TS U4468 ( .A(n4249), .Y(n4255) );
NOR2X8TS U4469 ( .A(n2757), .B(n6227), .Y(n4249) );
INVX2TS U4470 ( .A(n4734), .Y(n4716) );
INVX8TS U4471 ( .A(n4503), .Y(n4512) );
NOR2X8TS U4472 ( .A(n2661), .B(n2636), .Y(n2824) );
NOR2X6TS U4473 ( .A(n1672), .B(n3640), .Y(n2067) );
NAND2X8TS U4474 ( .A(n1660), .B(n2420), .Y(n4618) );
AOI2BB2X4TS U4475 ( .B0(n2034), .B1(n2213), .A0N(n2331), .A1N(n2222), .Y(
n2069) );
AOI21X4TS U4476 ( .A0(n1609), .A1(n4449), .B0(n4448), .Y(n4451) );
AND2X4TS U4477 ( .A(n5434), .B(n5344), .Y(n2070) );
INVX2TS U4478 ( .A(n4326), .Y(n4331) );
AO22X4TS U4479 ( .A0(n5104), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[61]), .Y(n2503) );
NAND2X6TS U4480 ( .A(n3413), .B(n3412), .Y(n3411) );
NOR2X2TS U4481 ( .A(n2715), .B(n1989), .Y(n4895) );
OAI2BB1X4TS U4482 ( .A0N(n3195), .A1N(n4419), .B0(n2145), .Y(n4466) );
AND2X4TS U4483 ( .A(n5639), .B(Add_Subt_result[1]), .Y(n2082) );
AOI2BB2X4TS U4484 ( .B0(n1869), .B1(n2081), .A0N(n2150), .A1N(n2172), .Y(
n3844) );
NOR2X2TS U4485 ( .A(n5963), .B(n4718), .Y(n4720) );
NAND2X8TS U4486 ( .A(n2954), .B(n3151), .Y(n2091) );
INVX16TS U4487 ( .A(n2091), .Y(n4009) );
BUFX6TS U4488 ( .A(n2282), .Y(n2101) );
CLKINVX12TS U4489 ( .A(n2893), .Y(n2776) );
AND2X8TS U4490 ( .A(n2970), .B(n3614), .Y(n4414) );
AOI2BB2X4TS U4491 ( .B0(n2034), .B1(n2213), .A0N(n2331), .A1N(n2222), .Y(
n3762) );
INVX12TS U4492 ( .A(n2097), .Y(n2098) );
MX2X2TS U4493 ( .A(n5932), .B(exp_oper_result[7]), .S0(n6406), .Y(n1431) );
NOR2X4TS U4494 ( .A(n3736), .B(n3769), .Y(n3771) );
NOR2X8TS U4495 ( .A(n6013), .B(n1624), .Y(n6031) );
NAND2X2TS U4496 ( .A(n5900), .B(n2753), .Y(n5901) );
NAND3X4TS U4497 ( .A(n5059), .B(n5008), .C(n5007), .Y(n5722) );
NAND3X4TS U4498 ( .A(n5059), .B(n5004), .C(n5003), .Y(n5733) );
INVX12TS U4499 ( .A(n2109), .Y(n2110) );
NAND3X8TS U4500 ( .A(n5286), .B(n5285), .C(n5284), .Y(n5572) );
NAND2X2TS U4501 ( .A(n5516), .B(n1817), .Y(n5284) );
INVX8TS U4502 ( .A(n3454), .Y(n3233) );
BUFX12TS U4503 ( .A(n3167), .Y(n3090) );
NOR2X4TS U4504 ( .A(n4399), .B(n4563), .Y(n4564) );
NOR2X4TS U4505 ( .A(n3702), .B(n3719), .Y(n2112) );
NOR2X8TS U4506 ( .A(n2291), .B(n2061), .Y(n3702) );
NOR2X8TS U4507 ( .A(n5989), .B(n5990), .Y(n4486) );
OR2X2TS U4508 ( .A(n5963), .B(n4453), .Y(n2277) );
INVX12TS U4509 ( .A(n2122), .Y(n2123) );
NAND2X4TS U4510 ( .A(n4474), .B(n5952), .Y(n6500) );
NAND2X2TS U4511 ( .A(n2115), .B(n2395), .Y(n3859) );
NAND2X6TS U4512 ( .A(n2019), .B(n3903), .Y(n4819) );
OAI2BB1X4TS U4513 ( .A0N(n2239), .A1N(n5862), .B0(n2126), .Y(n1126) );
NOR2X8TS U4514 ( .A(n3546), .B(n3563), .Y(n2129) );
NOR2X8TS U4515 ( .A(n2282), .B(n1656), .Y(n2131) );
INVX16TS U4516 ( .A(n2765), .Y(n2624) );
XNOR2X2TS U4517 ( .A(n2132), .B(n2180), .Y(n4179) );
OAI2BB1X4TS U4518 ( .A0N(n5729), .A1N(n2225), .B0(n5790), .Y(n1221) );
NOR2X6TS U4519 ( .A(n2133), .B(n2180), .Y(n3798) );
AOI22X2TS U4520 ( .A0(n2730), .A1(n2134), .B0(n1961), .B1(n5842), .Y(n5835)
);
INVX12TS U4521 ( .A(n2136), .Y(n2137) );
INVX16TS U4522 ( .A(n2858), .Y(n3439) );
XOR2X4TS U4523 ( .A(n2612), .B(n4657), .Y(n4714) );
XNOR2X1TS U4524 ( .A(n2365), .B(n2099), .Y(n4118) );
MXI2X2TS U4525 ( .A(n6124), .B(n2118), .S0(n6130), .Y(n1307) );
NAND2X8TS U4526 ( .A(n2591), .B(n2590), .Y(n2420) );
NAND2X6TS U4527 ( .A(n3898), .B(n1656), .Y(n6044) );
NAND3X6TS U4528 ( .A(n6295), .B(n6294), .C(n6293), .Y(n5990) );
NAND3BX2TS U4529 ( .AN(n1875), .B(n5694), .C(n4253), .Y(n2950) );
OAI2BB1X4TS U4530 ( .A0N(n5944), .A1N(n2858), .B0(n5949), .Y(n2925) );
MXI2X4TS U4531 ( .A(n6203), .B(n1903), .S0(n1575), .Y(n2140) );
BUFX20TS U4532 ( .A(n2620), .Y(n2864) );
INVX6TS U4533 ( .A(n2143), .Y(n2144) );
NAND2X4TS U4534 ( .A(n2176), .B(n4279), .Y(n4280) );
OAI2BB1X4TS U4535 ( .A0N(n5792), .A1N(n1848), .B0(n5834), .Y(n1104) );
NAND3X2TS U4536 ( .A(n4488), .B(n6221), .C(Add_Subt_result[0]), .Y(n3589) );
NAND2X4TS U4537 ( .A(n3341), .B(n4582), .Y(n3339) );
NOR2X8TS U4538 ( .A(n2422), .B(n2108), .Y(n6055) );
INVX12TS U4539 ( .A(n2149), .Y(n2150) );
NAND2X2TS U4540 ( .A(n2898), .B(n2662), .Y(n5198) );
NAND2X4TS U4541 ( .A(n3257), .B(n1950), .Y(n5160) );
NOR2X4TS U4542 ( .A(n3257), .B(FSM_selector_B_1_), .Y(n3519) );
AOI22X2TS U4543 ( .A0(n5476), .A1(n5688), .B0(n5668), .B1(n2504), .Y(n5175)
);
AOI22X2TS U4544 ( .A0(n5532), .A1(n2504), .B0(n6050), .B1(n5578), .Y(n5236)
);
NAND3X8TS U4545 ( .A(n5167), .B(n5166), .C(n5165), .Y(n2504) );
INVX8TS U4546 ( .A(n2160), .Y(n2161) );
NAND2X6TS U4547 ( .A(n2020), .B(n2348), .Y(n4830) );
NAND2X2TS U4548 ( .A(n4877), .B(n1947), .Y(n6025) );
NOR2X4TS U4549 ( .A(n2019), .B(n1663), .Y(n2171) );
NAND4X4TS U4550 ( .A(n2649), .B(Exp_Operation_Module_Data_S_8_), .C(n3275),
.D(n4812), .Y(n6543) );
INVX8TS U4551 ( .A(n2859), .Y(n2643) );
NAND2X4TS U4552 ( .A(n5510), .B(n5985), .Y(n5167) );
OA21X4TS U4553 ( .A0(n3150), .A1(n1920), .B0(n3632), .Y(n2187) );
MXI2X8TS U4554 ( .A(Sgf_normalized_result[22]), .B(n2325), .S0(n1799), .Y(
n3392) );
NAND2X4TS U4555 ( .A(n2267), .B(n2189), .Y(n3785) );
INVX12TS U4556 ( .A(n2194), .Y(n2195) );
NAND2X4TS U4557 ( .A(n1719), .B(n2599), .Y(n2598) );
NAND2X4TS U4558 ( .A(n1719), .B(n2930), .Y(n2929) );
AOI2BB2X2TS U4559 ( .B0(n2758), .B1(n5615), .A0N(n5679), .A1N(n2681), .Y(
n5626) );
AOI22X2TS U4560 ( .A0(n5655), .A1(n5620), .B0(n5619), .B1(n5670), .Y(n5624)
);
NAND2X4TS U4561 ( .A(n2805), .B(n4793), .Y(n6479) );
NAND2X4TS U4562 ( .A(n2990), .B(n4061), .Y(n4334) );
NAND2X8TS U4563 ( .A(n3063), .B(n3062), .Y(n4408) );
NOR2X6TS U4564 ( .A(n4461), .B(n4414), .Y(n2914) );
MXI2X2TS U4565 ( .A(n6082), .B(n2044), .S0(n2719), .Y(n1345) );
INVX12TS U4566 ( .A(n2219), .Y(n2220) );
XNOR2X1TS U4567 ( .A(n2158), .B(n2156), .Y(n4144) );
INVX12TS U4568 ( .A(n2221), .Y(n2222) );
NAND2X6TS U4569 ( .A(n3268), .B(n3267), .Y(n1499) );
NAND2X8TS U4570 ( .A(n2840), .B(n1648), .Y(n3268) );
NAND2X2TS U4571 ( .A(n2884), .B(n2570), .Y(n1451) );
NOR2BX1TS U4572 ( .AN(n3244), .B(n2715), .Y(n3989) );
INVX12TS U4573 ( .A(n2232), .Y(n2233) );
AO21X4TS U4574 ( .A0(n2684), .A1(n4283), .B0(n2148), .Y(n2234) );
INVX8TS U4575 ( .A(n2235), .Y(n2236) );
INVX16TS U4576 ( .A(FSM_selector_B_1_), .Y(n3927) );
XNOR2X1TS U4577 ( .A(n2178), .B(n2182), .Y(n4148) );
INVX12TS U4578 ( .A(n2245), .Y(n2246) );
NOR2X4TS U4579 ( .A(n3569), .B(n3250), .Y(n3570) );
NAND2X4TS U4580 ( .A(n5645), .B(n1606), .Y(n5343) );
NOR2X4TS U4581 ( .A(n1606), .B(n5344), .Y(n3580) );
NOR2X6TS U4582 ( .A(n5933), .B(n4723), .Y(n4708) );
NAND2X2TS U4583 ( .A(n5645), .B(n1817), .Y(n5250) );
NOR2X8TS U4584 ( .A(n1740), .B(n3556), .Y(n4075) );
NOR2X8TS U4585 ( .A(n4525), .B(n4524), .Y(n4769) );
INVX16TS U4586 ( .A(n2973), .Y(n2757) );
NOR2X8TS U4587 ( .A(n2757), .B(n1834), .Y(n4267) );
AND2X4TS U4588 ( .A(n4788), .B(n3433), .Y(n2554) );
NOR2X6TS U4589 ( .A(n2242), .B(n2354), .Y(n3786) );
NAND2X4TS U4590 ( .A(n3689), .B(n3697), .Y(n3700) );
INVX16TS U4591 ( .A(n2620), .Y(n3323) );
XNOR2X1TS U4592 ( .A(n2652), .B(n2230), .Y(n4164) );
OR2X8TS U4593 ( .A(n3270), .B(n1658), .Y(n4581) );
INVX8TS U4594 ( .A(n2652), .Y(n2653) );
OAI22X4TS U4595 ( .A0(n3873), .A1(n3874), .B0(n1942), .B1(n2201), .Y(n3877)
);
AOI21X4TS U4596 ( .A0(n3872), .A1(n3299), .B0(n3298), .Y(n3242) );
AO21X4TS U4597 ( .A0(n2268), .A1(n2269), .B0(n2558), .Y(n2270) );
INVX12TS U4598 ( .A(n2270), .Y(n5348) );
NOR2X8TS U4599 ( .A(n3878), .B(n3806), .Y(n3879) );
NAND2BX4TS U4600 ( .AN(n2164), .B(n2207), .Y(n3829) );
NAND2X4TS U4601 ( .A(n2152), .B(n2361), .Y(n3838) );
NAND2BX4TS U4602 ( .AN(n2095), .B(n2401), .Y(n3813) );
AND2X8TS U4603 ( .A(n2427), .B(n2107), .Y(n6054) );
NAND4X8TS U4604 ( .A(n2836), .B(n2837), .C(n2539), .D(n2486), .Y(n2835) );
INVX16TS U4605 ( .A(n2318), .Y(n3257) );
AND2X4TS U4606 ( .A(n4334), .B(n2902), .Y(n4444) );
OAI2BB1X4TS U4607 ( .A0N(n4520), .A1N(n4521), .B0(n2273), .Y(n2274) );
AOI21X4TS U4608 ( .A0(n2908), .A1(n3743), .B0(n2904), .Y(n3755) );
NAND2X4TS U4609 ( .A(n4269), .B(n3102), .Y(n2564) );
OAI2BB1X4TS U4610 ( .A0N(n2592), .A1N(n1685), .B0(n4606), .Y(n4608) );
AOI21X4TS U4611 ( .A0(n4777), .A1(n2556), .B0(n3006), .Y(n3213) );
AND2X6TS U4612 ( .A(n2078), .B(n1855), .Y(n3738) );
OAI21X4TS U4613 ( .A0(n3755), .A1(n3754), .B0(n3753), .Y(n3778) );
OAI22X4TS U4614 ( .A0(n3871), .A1(n3870), .B0(n2093), .B1(n2224), .Y(n3298)
);
AOI22X4TS U4615 ( .A0(n2278), .A1(n2235), .B0(n2233), .B1(n2380), .Y(n3697)
);
AND3X8TS U4616 ( .A(n3557), .B(n1818), .C(n3325), .Y(n4587) );
NOR2X8TS U4617 ( .A(n2137), .B(n2635), .Y(n3742) );
NOR2X8TS U4618 ( .A(n3100), .B(n3977), .Y(n4236) );
AOI21X4TS U4619 ( .A0(n2117), .A1(n2120), .B0(n3711), .Y(n3713) );
OAI22X4TS U4620 ( .A0(n3830), .A1(n3829), .B0(n2109), .B1(n2279), .Y(n3836)
);
NAND2BX4TS U4621 ( .AN(n2122), .B(n2376), .Y(n3812) );
AND2X8TS U4622 ( .A(n2141), .B(n2280), .Y(n3811) );
INVX6TS U4623 ( .A(n2405), .Y(n2280) );
BUFX20TS U4624 ( .A(n5810), .Y(n5827) );
BUFX20TS U4625 ( .A(n5810), .Y(n2734) );
BUFX20TS U4626 ( .A(n5795), .Y(n5729) );
BUFX20TS U4627 ( .A(n5795), .Y(n5873) );
BUFX20TS U4628 ( .A(n5795), .Y(n5792) );
BUFX20TS U4629 ( .A(n5795), .Y(n5876) );
NOR2X8TS U4630 ( .A(n4036), .B(n2471), .Y(n3978) );
BUFX20TS U4631 ( .A(n5030), .Y(n5810) );
BUFX20TS U4632 ( .A(n2477), .Y(n2297) );
NAND3X4TS U4633 ( .A(n3096), .B(n3094), .C(n3095), .Y(n2477) );
AO21X4TS U4634 ( .A0(n5827), .A1(n2078), .B0(n2302), .Y(n1129) );
NOR2X6TS U4635 ( .A(n5348), .B(n5344), .Y(n3557) );
NOR2X4TS U4636 ( .A(n3009), .B(n2459), .Y(n4925) );
NOR2X4TS U4637 ( .A(n2670), .B(n1884), .Y(n4506) );
OR2X4TS U4638 ( .A(n4695), .B(n1786), .Y(n2307) );
NAND3X6TS U4639 ( .A(n4587), .B(n3600), .C(n6222), .Y(n3556) );
NOR2X8TS U4640 ( .A(n2709), .B(n5281), .Y(n3592) );
NAND2X4TS U4641 ( .A(n2746), .B(n2709), .Y(n5269) );
BUFX8TS U4642 ( .A(n3886), .Y(n4192) );
NOR2X4TS U4643 ( .A(n2704), .B(n2153), .Y(n4896) );
NOR2X4TS U4644 ( .A(n2653), .B(n2230), .Y(n3688) );
OAI2BB1X4TS U4645 ( .A0N(n5856), .A1N(n2102), .B0(n5203), .Y(n1197) );
OAI2BB1X4TS U4646 ( .A0N(n5729), .A1N(n2354), .B0(n5759), .Y(n1207) );
OAI2BB1X4TS U4647 ( .A0N(n2109), .A1N(n5851), .B0(n5817), .Y(n1146) );
OAI2BB1X4TS U4648 ( .A0N(n5792), .A1N(n2114), .B0(n5841), .Y(n1158) );
NAND2X4TS U4649 ( .A(n5879), .B(n5109), .Y(n4973) );
AOI22X2TS U4650 ( .A0(n5879), .A1(n2722), .B0(n5784), .B1(n2425), .Y(n5046)
);
NAND2X2TS U4651 ( .A(n5879), .B(n5899), .Y(n5880) );
AND2X8TS U4652 ( .A(n4796), .B(n4801), .Y(n2510) );
XNOR2X4TS U4653 ( .A(n4805), .B(n4804), .Y(n2323) );
AOI22X4TS U4654 ( .A0(n2741), .A1(n2217), .B0(DMP[22]), .B1(n5859), .Y(n5853) );
AOI22X4TS U4655 ( .A0(n5860), .A1(n2239), .B0(DMP[21]), .B1(n5859), .Y(n5854) );
AO22X4TS U4656 ( .A0(n3269), .A1(n2367), .B0(DmP[21]), .B1(n5825), .Y(n2333)
);
BUFX20TS U4657 ( .A(n5810), .Y(n5831) );
NAND3X8TS U4658 ( .A(n6316), .B(n6315), .C(n6314), .Y(n5991) );
NOR2X4TS U4659 ( .A(n5993), .B(n5991), .Y(n3544) );
XNOR2X4TS U4660 ( .A(n2338), .B(n4705), .Y(n4022) );
AO21X4TS U4661 ( .A0(n1609), .A1(n4018), .B0(n4017), .Y(n2338) );
OR2X6TS U4662 ( .A(n2867), .B(n3521), .Y(n2868) );
NAND2X4TS U4663 ( .A(n1653), .B(n5515), .Y(n3359) );
NAND2BX1TS U4664 ( .AN(n4081), .B(n5258), .Y(n4578) );
OAI2BB1X4TS U4665 ( .A0N(n2251), .A1N(n5873), .B0(n5843), .Y(n1161) );
OAI2BB1X4TS U4666 ( .A0N(n5792), .A1N(intDY[45]), .B0(n5756), .Y(n1214) );
OAI2BB1X4TS U4667 ( .A0N(n5862), .A1N(n2232), .B0(n5730), .Y(n1175) );
OAI2BB1X4TS U4668 ( .A0N(n5876), .A1N(n2160), .B0(n3889), .Y(n1105) );
OAI2BB1X4TS U4669 ( .A0N(n5792), .A1N(n2652), .B0(n3887), .Y(n1109) );
AND2X8TS U4670 ( .A(n3454), .B(n3210), .Y(n4206) );
OAI2BB1X4TS U4671 ( .A0N(n5792), .A1N(n2127), .B0(n5833), .Y(n1157) );
NAND2X4TS U4672 ( .A(n3257), .B(DmP[52]), .Y(n3923) );
OAI2BB1X4TS U4673 ( .A0N(n5792), .A1N(n2093), .B0(n5838), .Y(n1164) );
OAI2BB1X4TS U4674 ( .A0N(n5873), .A1N(n2247), .B0(n5835), .Y(n1163) );
NOR2X8TS U4675 ( .A(n2977), .B(n2341), .Y(n5642) );
OAI2BB2X1TS U4676 ( .B0(n5679), .B1(n5678), .A0N(n5642), .A1N(n5681), .Y(
n5652) );
BUFX12TS U4677 ( .A(n5642), .Y(n2887) );
INVX8TS U4678 ( .A(n5642), .Y(n2888) );
NOR2X4TS U4679 ( .A(n2152), .B(n2361), .Y(n3783) );
MXI2X2TS U4680 ( .A(n6080), .B(n2163), .S0(n2720), .Y(n1347) );
OAI2BB1X4TS U4681 ( .A0N(n5845), .A1N(n2289), .B0(n5774), .Y(n1229) );
OAI2BB1X4TS U4682 ( .A0N(n2235), .A1N(n2735), .B0(n5801), .Y(n1112) );
OAI2BB1X4TS U4683 ( .A0N(n5856), .A1N(n2610), .B0(n5809), .Y(n1114) );
OAI2BB1X4TS U4684 ( .A0N(n2196), .A1N(n5876), .B0(n5872), .Y(n1150) );
OAI2BB1X4TS U4685 ( .A0N(n2205), .A1N(n5876), .B0(n5869), .Y(n1156) );
OAI2BB1X4TS U4686 ( .A0N(n2151), .A1N(n5729), .B0(n5868), .Y(n1149) );
AOI22X2TS U4687 ( .A0(n5104), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .Y(n5016) );
BUFX20TS U4688 ( .A(n3662), .Y(n5102) );
AOI22X2TS U4689 ( .A0(n2730), .A1(n2405), .B0(n1965), .B1(n1645), .Y(n5824)
);
INVX6TS U4690 ( .A(n4802), .Y(n3417) );
INVX4TS U4691 ( .A(n3162), .Y(n2342) );
OAI2BB1X4TS U4692 ( .A0N(n5729), .A1N(n2616), .B0(n3888), .Y(n1107) );
OAI2BB1X4TS U4693 ( .A0N(n5873), .A1N(n2436), .B0(n5726), .Y(n1171) );
OAI2BB1X4TS U4694 ( .A0N(n2401), .A1N(n5856), .B0(n5133), .Y(n1203) );
INVX4TS U4695 ( .A(n3003), .Y(n2348) );
AOI2BB2X4TS U4696 ( .B0(n2732), .B1(n2260), .A0N(n2349), .A1N(n2360), .Y(
n5808) );
AOI2BB2X4TS U4697 ( .B0(n2732), .B1(n2141), .A0N(n2350), .A1N(n2360), .Y(
n5135) );
AO21X4TS U4698 ( .A0(n4829), .A1(n2297), .B0(n4828), .Y(n3253) );
OAI21X2TS U4699 ( .A0(n3568), .A1(n3582), .B0(n4589), .Y(n3571) );
OR2X2TS U4700 ( .A(n5055), .B(n6247), .Y(n3670) );
OR2X8TS U4701 ( .A(n4286), .B(n1952), .Y(n3366) );
OAI2BB1X4TS U4702 ( .A0N(n5873), .A1N(n2432), .B0(n5866), .Y(n1110) );
OAI2BB1X4TS U4703 ( .A0N(n5729), .A1N(n2134), .B0(n5771), .Y(n1227) );
OAI2BB1X4TS U4704 ( .A0N(n5729), .A1N(n2172), .B0(n5751), .Y(n1216) );
NOR2X4TS U4705 ( .A(n4314), .B(n3380), .Y(n4253) );
AND4X4TS U4706 ( .A(n3054), .B(n3053), .C(n3055), .D(n3073), .Y(n2472) );
NAND2X4TS U4707 ( .A(n5702), .B(n5701), .Y(n1482) );
NAND4BBX4TS U4708 ( .AN(n2358), .BN(n2359), .C(n4997), .D(n4996), .Y(n5190)
);
AND2X2TS U4709 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n2358) );
AND2X2TS U4710 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n2359) );
NAND2X8TS U4711 ( .A(n4307), .B(n5962), .Y(n4640) );
OAI2BB1X4TS U4712 ( .A0N(n5876), .A1N(n2260), .B0(n5763), .Y(n1188) );
OAI2BB1X4TS U4713 ( .A0N(n5729), .A1N(n2635), .B0(n5761), .Y(n1186) );
BUFX20TS U4714 ( .A(n5810), .Y(n5862) );
OAI2BB1X4TS U4715 ( .A0N(n5845), .A1N(n2192), .B0(n5852), .Y(n1192) );
OAI2BB1X4TS U4716 ( .A0N(n5792), .A1N(n2382), .B0(n5853), .Y(n1191) );
OAI2BB1X4TS U4717 ( .A0N(n5792), .A1N(n2367), .B0(n5854), .Y(n1190) );
OAI2BB1X4TS U4718 ( .A0N(n5845), .A1N(n2255), .B0(n5762), .Y(n1187) );
NOR2X8TS U4719 ( .A(n2192), .B(n2228), .Y(n3749) );
NAND4X8TS U4720 ( .A(n3055), .B(n3054), .C(n3053), .D(n1830), .Y(n3367) );
NAND2X8TS U4721 ( .A(n3973), .B(n1651), .Y(n3490) );
INVX12TS U4722 ( .A(n2369), .Y(n2370) );
NAND3BX4TS U4723 ( .AN(n2371), .B(n3657), .C(n3656), .Y(n4964) );
AO22X2TS U4724 ( .A0(n5081), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .B1(n5101), .Y(n2371)
);
NOR2X8TS U4725 ( .A(n4257), .B(n4256), .Y(n4259) );
INVX12TS U4726 ( .A(n2374), .Y(n2375) );
NAND4X2TS U4727 ( .A(n5073), .B(n5072), .C(n5890), .D(n5071), .Y(n1470) );
NAND2X8TS U4728 ( .A(n4075), .B(n3246), .Y(n4489) );
NAND2X6TS U4729 ( .A(n4586), .B(n4482), .Y(n4575) );
INVX12TS U4730 ( .A(n2389), .Y(n2390) );
NOR2X4TS U4731 ( .A(n2246), .B(n2102), .Y(n3735) );
INVX12TS U4732 ( .A(n2393), .Y(n2394) );
NOR2X6TS U4733 ( .A(n5348), .B(n1658), .Y(n4092) );
OAI2BB1X4TS U4734 ( .A0N(n2378), .A1N(n5827), .B0(n5814), .Y(n1144) );
OAI2BB1X2TS U4735 ( .A0N(n5845), .A1N(n2336), .B0(n5773), .Y(n1220) );
NAND2BX4TS U4736 ( .AN(n4727), .B(n4709), .Y(n2667) );
NOR2X4TS U4737 ( .A(n3323), .B(n2417), .Y(n3225) );
OAI2BB2X4TS U4738 ( .B0(n2443), .B1(n2419), .A0N(n2739), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n2418) );
XNOR2X1TS U4739 ( .A(n2239), .B(n2367), .Y(n4135) );
OAI2BB1X4TS U4740 ( .A0N(n2043), .A1N(n5856), .B0(n5823), .Y(n1153) );
AOI22X2TS U4741 ( .A0(n5849), .A1(n1850), .B0(DmP[48]), .B1(n5777), .Y(n5823) );
AOI22X2TS U4742 ( .A0(n5760), .A1(n2060), .B0(DMP[14]), .B1(n5735), .Y(n4957) );
NAND2X2TS U4743 ( .A(n5148), .B(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n3678) );
NAND2X8TS U4744 ( .A(n3933), .B(n3932), .Y(n4352) );
OAI21X4TS U4745 ( .A0(n5120), .A1(n5119), .B0(n2662), .Y(n5123) );
OAI2BB1X4TS U4746 ( .A0N(n5876), .A1N(n2207), .B0(n5846), .Y(n1209) );
OAI2BB1X4TS U4747 ( .A0N(n5792), .A1N(n2361), .B0(n5850), .Y(n1213) );
INVX8TS U4748 ( .A(n3944), .Y(n3147) );
NAND2X2TS U4749 ( .A(n4964), .B(n2662), .Y(n4968) );
AOI22X2TS U4750 ( .A0(n6050), .A1(n5595), .B0(n2886), .B1(n5594), .Y(n5557)
);
BUFX20TS U4751 ( .A(n5752), .Y(n5829) );
INVX8TS U4752 ( .A(n5273), .Y(n5258) );
OR2X8TS U4753 ( .A(n2431), .B(n3257), .Y(n5161) );
INVX3TS U4754 ( .A(n4808), .Y(n3162) );
NAND2X6TS U4755 ( .A(n2707), .B(n3958), .Y(n2774) );
NAND3X8TS U4756 ( .A(n3265), .B(n3916), .C(n3256), .Y(n3313) );
XOR2X4TS U4757 ( .A(n1673), .B(n3959), .Y(n3960) );
NAND2X4TS U4758 ( .A(n5510), .B(n5996), .Y(n5225) );
NOR2X6TS U4759 ( .A(n5997), .B(n5996), .Y(n3561) );
NAND3X8TS U4760 ( .A(n6376), .B(n6375), .C(n6374), .Y(n5996) );
NAND2X8TS U4761 ( .A(n3924), .B(n3925), .Y(n2894) );
NAND2X2TS U4762 ( .A(n5927), .B(n2209), .Y(n3267) );
BUFX16TS U4763 ( .A(n3663), .Y(n5148) );
INVX4TS U4764 ( .A(n3970), .Y(n3388) );
XNOR2X2TS U4765 ( .A(n2122), .B(n2376), .Y(n4119) );
INVX12TS U4766 ( .A(n2434), .Y(n2435) );
CLKINVX12TS U4767 ( .A(n3968), .Y(n2438) );
MXI2X4TS U4768 ( .A(n4824), .B(n6236), .S0(n5999), .Y(n1510) );
AOI21X2TS U4769 ( .A0(n2297), .A1(n4025), .B0(n4016), .Y(n4374) );
INVX12TS U4770 ( .A(n4026), .Y(n4016) );
INVX6TS U4771 ( .A(n4043), .Y(n2443) );
AO22X2TS U4772 ( .A0(n2738), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n5101), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n2444) );
NAND3X8TS U4773 ( .A(n2445), .B(n4987), .C(n4986), .Y(n2580) );
NAND2X8TS U4774 ( .A(n2446), .B(n3607), .Y(n2622) );
AO22X2TS U4775 ( .A0(n5081), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(n5101), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(n2640) );
OR2X4TS U4776 ( .A(n1790), .B(n3899), .Y(n4914) );
OAI21X4TS U4777 ( .A0(n5144), .A1(n5143), .B0(n1647), .Y(n5147) );
OAI21X4TS U4778 ( .A0(exp_oper_result[4]), .A1(exp_oper_result[3]), .B0(
n1661), .Y(n3514) );
OAI21X4TS U4779 ( .A0(n5896), .A1(n5898), .B0(n2664), .Y(n5061) );
BUFX20TS U4780 ( .A(n2702), .Y(n2975) );
NAND2X6TS U4781 ( .A(n5364), .B(n5261), .Y(n5421) );
INVX8TS U4782 ( .A(n4019), .Y(n2941) );
BUFX20TS U4783 ( .A(n2702), .Y(n2718) );
AOI21X4TS U4784 ( .A0(n5694), .A1(n4323), .B0(n4322), .Y(n4325) );
BUFX20TS U4785 ( .A(n5261), .Y(n3207) );
NAND3X8TS U4786 ( .A(n5159), .B(n5160), .C(n5161), .Y(n5261) );
NOR2X8TS U4787 ( .A(n2420), .B(n1660), .Y(n2452) );
AOI22X2TS U4788 ( .A0(n5685), .A1(n5594), .B0(n5591), .B1(n5680), .Y(n5398)
);
NOR2X8TS U4789 ( .A(n2977), .B(n5238), .Y(n5566) );
AOI21X4TS U4790 ( .A0(n3050), .A1(n4683), .B0(n2234), .Y(n4685) );
NOR2X6TS U4791 ( .A(n6004), .B(n6001), .Y(n5905) );
MXI2X4TS U4792 ( .A(n4954), .B(n4953), .S0(n6060), .Y(n4955) );
NAND4BX2TS U4793 ( .AN(n3674), .B(n2577), .C(n3673), .D(n3672), .Y(n1476) );
INVX16TS U4794 ( .A(n2859), .Y(n2644) );
MXI2X4TS U4795 ( .A(n1835), .B(n4617), .S0(n2455), .Y(n6531) );
XNOR2X4TS U4796 ( .A(n2456), .B(n4603), .Y(n4604) );
AO21X1TS U4797 ( .A0(n2167), .A1(n5895), .B0(n2726), .Y(n5883) );
INVX16TS U4798 ( .A(n3675), .Y(n2726) );
INVX8TS U4799 ( .A(n4397), .Y(n4746) );
OAI2BB1X4TS U4800 ( .A0N(n5897), .A1N(n5720), .B0(n5723), .Y(n1485) );
AOI21X2TS U4801 ( .A0(n5899), .A1(n5722), .B0(n5721), .Y(n5723) );
XNOR2X4TS U4802 ( .A(n3987), .B(n4318), .Y(n3988) );
NOR2X8TS U4803 ( .A(n6055), .B(n3608), .Y(n6052) );
XNOR2X4TS U4804 ( .A(n1801), .B(n4371), .Y(n2605) );
AND3X2TS U4805 ( .A(n3016), .B(n3015), .C(n4914), .Y(n2469) );
NOR2X8TS U4806 ( .A(n2990), .B(n4065), .Y(n4067) );
BUFX4TS U4807 ( .A(n3281), .Y(n3271) );
INVX4TS U4808 ( .A(n4250), .Y(n4257) );
NOR2X8TS U4809 ( .A(n2757), .B(n2632), .Y(n4250) );
NAND2X2TS U4810 ( .A(n2460), .B(n4698), .Y(n4701) );
NOR2X8TS U4811 ( .A(n5238), .B(n5242), .Y(n5426) );
AOI22X2TS U4812 ( .A0(n5685), .A1(n5591), .B0(n5594), .B1(n2760), .Y(n5418)
);
AOI21X4TS U4813 ( .A0(n3050), .A1(n4839), .B0(n3258), .Y(n4841) );
NOR2X8TS U4814 ( .A(n4284), .B(n4269), .Y(n4101) );
NAND2X8TS U4815 ( .A(n4406), .B(n4398), .Y(n4399) );
AND2X8TS U4816 ( .A(n4031), .B(n4379), .Y(n2556) );
NAND2X4TS U4817 ( .A(n2713), .B(n2562), .Y(n2583) );
INVX2TS U4818 ( .A(n3562), .Y(n3364) );
CLKINVX6TS U4819 ( .A(n4396), .Y(n4745) );
INVX2TS U4820 ( .A(n4112), .Y(n4470) );
INVX2TS U4821 ( .A(n4372), .Y(n4825) );
INVX2TS U4822 ( .A(n1865), .Y(n2921) );
INVX4TS U4823 ( .A(n4684), .Y(n2710) );
AND2X4TS U4824 ( .A(n2519), .B(n4533), .Y(n2478) );
AND2X2TS U4825 ( .A(n5154), .B(Sgf_normalized_result[54]), .Y(n2480) );
AND2X8TS U4826 ( .A(n3446), .B(n3447), .Y(n2481) );
INVX12TS U4827 ( .A(n3252), .Y(n2746) );
INVX6TS U4828 ( .A(n5196), .Y(n2663) );
INVX8TS U4829 ( .A(n5679), .Y(n6050) );
AND2X8TS U4830 ( .A(n3160), .B(n4010), .Y(n2482) );
AND2X8TS U4831 ( .A(n4003), .B(n3392), .Y(n2483) );
AND3X8TS U4832 ( .A(n3561), .B(n3355), .C(n2847), .Y(n2485) );
AO21X4TS U4833 ( .A0(n1664), .A1(n4578), .B0(n4584), .Y(n2486) );
INVX4TS U4834 ( .A(n4925), .Y(n3013) );
INVX2TS U4835 ( .A(n5971), .Y(n3475) );
BUFX3TS U4836 ( .A(n4871), .Y(n6438) );
INVX2TS U4837 ( .A(rst), .Y(n2721) );
INVX2TS U4838 ( .A(n4543), .Y(n4848) );
INVX2TS U4839 ( .A(n4549), .Y(n4744) );
INVX2TS U4840 ( .A(n4261), .Y(n4341) );
NOR2X1TS U4841 ( .A(n4487), .B(n4486), .Y(n2496) );
OR2X4TS U4842 ( .A(n3437), .B(n3438), .Y(n2497) );
AND2X2TS U4843 ( .A(n5946), .B(n5948), .Y(n2498) );
OAI21X1TS U4844 ( .A0(Add_Subt_result[4]), .A1(n6235), .B0(n6221), .Y(n2501)
);
OA21X2TS U4845 ( .A0(n4242), .A1(n1743), .B0(n3970), .Y(n2502) );
INVX2TS U4846 ( .A(n1876), .Y(n4197) );
BUFX8TS U4847 ( .A(n6031), .Y(n3259) );
BUFX8TS U4848 ( .A(n6031), .Y(n3261) );
BUFX8TS U4849 ( .A(n6031), .Y(n3260) );
XNOR2X4TS U4850 ( .A(n4319), .B(n4318), .Y(n2507) );
XNOR2X4TS U4851 ( .A(n4233), .B(n4232), .Y(n2508) );
INVX8TS U4852 ( .A(n4253), .Y(n4695) );
INVX8TS U4853 ( .A(n1634), .Y(n2698) );
INVX8TS U4854 ( .A(n2847), .Y(n6007) );
AND3X6TS U4855 ( .A(n6383), .B(n6384), .C(n6385), .Y(n2847) );
OR2X8TS U4856 ( .A(n2202), .B(n2388), .Y(n2517) );
MXI2X4TS U4857 ( .A(n1924), .B(n6210), .S0(n2866), .Y(n2518) );
INVX2TS U4858 ( .A(n5960), .Y(n3472) );
MXI2X4TS U4859 ( .A(n6224), .B(n6201), .S0(n2866), .Y(n2521) );
OA21X2TS U4860 ( .A0(n4726), .A1(n1722), .B0(n4793), .Y(n2523) );
INVX6TS U4861 ( .A(n4625), .Y(n3345) );
OR2X8TS U4862 ( .A(n4769), .B(n4766), .Y(n2524) );
OA21X4TS U4863 ( .A0(n4392), .A1(n4028), .B0(n4027), .Y(n2527) );
NAND2X4TS U4864 ( .A(n4629), .B(n4625), .Y(n4791) );
OA21X4TS U4865 ( .A0(n3628), .A1(n3459), .B0(n3627), .Y(n2534) );
OR2X2TS U4866 ( .A(n5963), .B(n4480), .Y(n2535) );
OR2X8TS U4867 ( .A(n5916), .B(n5915), .Y(n2536) );
AND2X8TS U4868 ( .A(n4582), .B(n4580), .Y(n2539) );
OR2X2TS U4869 ( .A(n5515), .B(DmP[25]), .Y(n2542) );
AND2X8TS U4870 ( .A(n3506), .B(n4631), .Y(n2550) );
AND2X8TS U4871 ( .A(n2865), .B(n6200), .Y(n2551) );
AND2X8TS U4872 ( .A(n3048), .B(n3014), .Y(n2553) );
INVX2TS U4873 ( .A(n4565), .Y(n4567) );
AND2X2TS U4874 ( .A(n2977), .B(n1988), .Y(n2555) );
AND2X2TS U4875 ( .A(n5912), .B(n3250), .Y(n2557) );
AND2X4TS U4876 ( .A(n3149), .B(n3148), .Y(n3944) );
AND2X8TS U4877 ( .A(n3455), .B(n2085), .Y(n2560) );
NAND2X1TS U4878 ( .A(n4792), .B(n4791), .Y(n2565) );
NAND2X2TS U4879 ( .A(n3506), .B(n4840), .Y(n2566) );
NAND2X2TS U4880 ( .A(n4771), .B(n4770), .Y(n2567) );
INVX2TS U4881 ( .A(n4243), .Y(n3969) );
INVX2TS U4882 ( .A(n4361), .Y(n4478) );
AND2X4TS U4883 ( .A(n1658), .B(n2647), .Y(n2573) );
CLKINVX6TS U4884 ( .A(n1587), .Y(n4339) );
INVX4TS U4885 ( .A(n4339), .Y(n3280) );
AND2X4TS U4886 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n2574) );
AND2X2TS U4887 ( .A(n3309), .B(n1726), .Y(n2576) );
NAND2X2TS U4888 ( .A(n6405), .B(n3024), .Y(n2579) );
INVX2TS U4889 ( .A(n6407), .Y(n3067) );
INVX12TS U4890 ( .A(n4246), .Y(n6060) );
INVX12TS U4891 ( .A(n4246), .Y(n2762) );
INVX2TS U4892 ( .A(n4239), .Y(n3026) );
INVX2TS U4893 ( .A(Add_Subt_result[15]), .Y(n4867) );
CLKBUFX3TS U4894 ( .A(n6450), .Y(n6262) );
BUFX3TS U4895 ( .A(n4869), .Y(n6415) );
CLKBUFX3TS U4896 ( .A(n2728), .Y(n6264) );
CLKINVX3TS U4897 ( .A(rst), .Y(n6547) );
NAND2X4TS U4898 ( .A(n2580), .B(n5780), .Y(n5741) );
BUFX20TS U4899 ( .A(n5056), .Y(n2581) );
NAND2X8TS U4900 ( .A(n3606), .B(n1659), .Y(n2582) );
AOI21X4TS U4901 ( .A0(n2587), .A1(n3475), .B0(n3472), .Y(n2584) );
OAI21X4TS U4902 ( .A0(n1876), .A1(n2594), .B0(n2593), .Y(n2592) );
INVX16TS U4903 ( .A(n2595), .Y(n5752) );
NAND2X4TS U4904 ( .A(n1655), .B(n3911), .Y(n3970) );
NOR2X8TS U4905 ( .A(n3011), .B(n3273), .Y(n4264) );
NOR2X8TS U4906 ( .A(n3167), .B(n3505), .Y(n5208) );
OR2X8TS U4907 ( .A(n2048), .B(n2668), .Y(n3616) );
NOR2X8TS U4908 ( .A(n3235), .B(n3225), .Y(n3167) );
XOR2X4TS U4909 ( .A(n2716), .B(n2608), .Y(n5928) );
AND2X6TS U4910 ( .A(n3993), .B(n3946), .Y(n2608) );
NOR2X8TS U4911 ( .A(n3626), .B(n3154), .Y(n4694) );
XOR2X4TS U4912 ( .A(n2777), .B(n2894), .Y(n2609) );
AND2X6TS U4913 ( .A(n2874), .B(DmP[61]), .Y(n3936) );
AOI21X4TS U4914 ( .A0(n2644), .A1(n4712), .B0(n4711), .Y(n2612) );
XOR2X4TS U4915 ( .A(n2777), .B(n1632), .Y(n2613) );
NAND2X4TS U4916 ( .A(n2142), .B(n2405), .Y(n3809) );
BUFX20TS U4917 ( .A(n5752), .Y(n3269) );
NAND2X4TS U4918 ( .A(n1726), .B(n2858), .Y(n2997) );
NAND2X4TS U4919 ( .A(n3119), .B(n2644), .Y(n3118) );
NOR2X8TS U4920 ( .A(n5364), .B(n3207), .Y(n5221) );
BUFX8TS U4921 ( .A(n3662), .Y(n5081) );
OR2X4TS U4922 ( .A(n2660), .B(n2818), .Y(n2618) );
INVX6TS U4923 ( .A(n2636), .Y(n2818) );
NAND2X4TS U4924 ( .A(n5121), .B(n5109), .Y(n2962) );
NAND2X2TS U4925 ( .A(n5121), .B(n5899), .Y(n3684) );
NAND2X4TS U4926 ( .A(n2057), .B(n5897), .Y(n5702) );
AOI2BB2X4TS U4927 ( .B0(n4490), .B1(n2496), .A0N(n4489), .A1N(n4488), .Y(
n4494) );
NAND2X4TS U4928 ( .A(n4964), .B(n5780), .Y(n3661) );
AOI22X2TS U4929 ( .A0(n5090), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n5083), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[57]), .Y(n5093) );
XOR2X4TS U4930 ( .A(n3920), .B(n2624), .Y(n2896) );
AOI22X2TS U4931 ( .A0(n5634), .A1(n5615), .B0(n5620), .B1(n2700), .Y(n5472)
);
NAND3X8TS U4932 ( .A(n5308), .B(n5307), .C(n5306), .Y(n5596) );
XOR2X4TS U4933 ( .A(n2919), .B(n2511), .Y(n2918) );
OA21X4TS U4934 ( .A0(n4454), .A1(n4299), .B0(n4298), .Y(n2621) );
NOR2X8TS U4935 ( .A(n2287), .B(n2370), .Y(n3719) );
AOI22X1TS U4936 ( .A0(n5900), .A1(n4965), .B0(n3255), .B1(n1913), .Y(n5060)
);
INVX12TS U4937 ( .A(n3523), .Y(n2883) );
AOI22X2TS U4938 ( .A0(n5685), .A1(n5683), .B0(n5684), .B1(n5680), .Y(n5665)
);
AOI22X2TS U4939 ( .A0(n5662), .A1(n5681), .B0(n5682), .B1(n5661), .Y(n5667)
);
NOR2X4TS U4940 ( .A(n4632), .B(n4835), .Y(n4846) );
NAND4X4TS U4941 ( .A(n5045), .B(n5044), .C(n5043), .D(n5042), .Y(n5877) );
NAND3BX4TS U4942 ( .AN(n2623), .B(n4974), .C(n4973), .Y(n5742) );
AOI22X2TS U4943 ( .A0(n2886), .A1(n5596), .B0(n5653), .B1(n5593), .Y(n5335)
);
NAND4BX2TS U4944 ( .AN(n1686), .B(n5906), .C(n5990), .D(n5905), .Y(n5923) );
OAI2BB1X2TS U4945 ( .A0N(n1869), .A1N(n2735), .B0(n5818), .Y(n1151) );
NAND2X8TS U4946 ( .A(n3464), .B(n3463), .Y(n3247) );
OAI2BB1X2TS U4947 ( .A0N(n2149), .A1N(n2734), .B0(n1629), .Y(n1152) );
AND2X8TS U4948 ( .A(n4081), .B(n3358), .Y(n3542) );
XOR2X4TS U4949 ( .A(n3212), .B(n4648), .Y(n3460) );
NAND2X2TS U4950 ( .A(n5195), .B(n5194), .Y(n5199) );
OAI2BB1X2TS U4951 ( .A0N(n5856), .A1N(n2136), .B0(n5797), .Y(n1122) );
AOI22X2TS U4952 ( .A0(n2673), .A1(n5416), .B0(n2712), .B1(n5569), .Y(n5368)
);
OAI2BB1X2TS U4953 ( .A0N(n2217), .A1N(n5862), .B0(n5802), .Y(n1127) );
INVX6TS U4954 ( .A(n4493), .Y(n3173) );
NOR2X6TS U4955 ( .A(n4112), .B(n4457), .Y(n4475) );
NOR2X8TS U4956 ( .A(n4510), .B(n4509), .Y(n4641) );
OAI2BB1X4TS U4957 ( .A0N(n2071), .A1N(n5827), .B0(n5826), .Y(n1154) );
OAI21X4TS U4958 ( .A0(n3841), .A1(n3842), .B0(n3840), .Y(n3843) );
AOI2BB1X2TS U4959 ( .A0N(n4745), .A1N(n1635), .B0(n4545), .Y(n4546) );
NAND2X2TS U4960 ( .A(n5209), .B(n5210), .Y(n5216) );
AOI22X4TS U4961 ( .A0(n2976), .A1(intDX_63_), .B0(n5842), .B1(
sign_final_result), .Y(n4193) );
OAI2BB1X2TS U4962 ( .A0N(n2227), .A1N(n2735), .B0(n5805), .Y(n1128) );
NAND2BX4TS U4963 ( .AN(n2788), .B(n5193), .Y(n1465) );
NAND2X4TS U4964 ( .A(n3105), .B(n2301), .Y(n3447) );
MX2X4TS U4965 ( .A(n4812), .B(exp_oper_result[4]), .S0(n6406), .Y(n1434) );
NOR2X4TS U4966 ( .A(n5930), .B(n4812), .Y(n4813) );
NAND2X4TS U4967 ( .A(n3306), .B(n1595), .Y(n4679) );
AND2X4TS U4968 ( .A(n2913), .B(n2915), .Y(n2634) );
NAND2X2TS U4969 ( .A(n3275), .B(n5980), .Y(n2826) );
NAND2X4TS U4970 ( .A(n2752), .B(n2125), .Y(n3158) );
NAND2X8TS U4971 ( .A(n3027), .B(n2526), .Y(n3037) );
NAND4BBX4TS U4972 ( .AN(n2637), .BN(n2638), .C(n4995), .D(n4994), .Y(n5189)
);
OR2X4TS U4973 ( .A(n4992), .B(n4993), .Y(n2637) );
NAND2X6TS U4974 ( .A(n2711), .B(n2518), .Y(n3310) );
NOR2X2TS U4975 ( .A(n4835), .B(n4760), .Y(n4761) );
MXI2X2TS U4976 ( .A(n6118), .B(n2370), .S0(n6163), .Y(n1312) );
NOR3X6TS U4977 ( .A(n2839), .B(n2536), .C(n2386), .Y(n2841) );
MXI2X4TS U4978 ( .A(n4611), .B(n5281), .S0(n6063), .Y(n6462) );
NAND4X8TS U4979 ( .A(n5926), .B(n4598), .C(n4599), .D(n4597), .Y(n4600) );
NAND2X4TS U4980 ( .A(n3347), .B(n4276), .Y(n4458) );
NOR2X8TS U4981 ( .A(n2390), .B(n2399), .Y(n3711) );
NOR2X8TS U4982 ( .A(n2072), .B(n2391), .Y(n3854) );
NOR2X4TS U4983 ( .A(n2922), .B(n2921), .Y(n2920) );
AOI22X2TS U4984 ( .A0(n5627), .A1(n5560), .B0(n5567), .B1(n5661), .Y(n5392)
);
AOI22X2TS U4985 ( .A0(n5627), .A1(n5541), .B0(n2886), .B1(n5559), .Y(n5390)
);
AOI22X2TS U4986 ( .A0(n5627), .A1(n5617), .B0(n5608), .B1(n2697), .Y(n5614)
);
OAI2BB1X4TS U4987 ( .A0N(n5845), .A1N(n2190), .B0(n5875), .Y(n1106) );
AND2X8TS U4988 ( .A(n3441), .B(n3442), .Y(n2641) );
OAI2BB1X2TS U4989 ( .A0N(n2164), .A1N(n2735), .B0(n5812), .Y(n1145) );
INVX16TS U4990 ( .A(n3422), .Y(n3082) );
NAND2X4TS U4991 ( .A(n4761), .B(n3050), .Y(n3407) );
OAI21X2TS U4992 ( .A0(n4754), .A1(n4748), .B0(n3427), .Y(n4403) );
NOR2X4TS U4993 ( .A(DMP[45]), .B(n2850), .Y(n3424) );
BUFX16TS U4994 ( .A(n3662), .Y(n2739) );
XOR2X4TS U4995 ( .A(n2642), .B(n4721), .Y(n4550) );
OAI2BB1X4TS U4996 ( .A0N(n5856), .A1N(n2363), .B0(n5803), .Y(n1121) );
XOR2X4TS U4997 ( .A(n4841), .B(n2566), .Y(n4842) );
NAND3X4TS U4998 ( .A(n1723), .B(n2897), .C(DmP[54]), .Y(n3921) );
OAI2BB1X2TS U4999 ( .A0N(n2241), .A1N(n5831), .B0(n5811), .Y(n1143) );
NAND3X4TS U5000 ( .A(n6292), .B(n6291), .C(n6290), .Y(n5994) );
NAND2X4TS U5001 ( .A(n5893), .B(n2421), .Y(n4986) );
XNOR2X1TS U5002 ( .A(n2432), .B(n2626), .Y(n4155) );
AOI22X2TS U5003 ( .A0(n5081), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(n5150), .B1(n2742), .Y(n5021) );
NAND2X6TS U5004 ( .A(n3465), .B(n2713), .Y(n3464) );
OAI2BB1X2TS U5005 ( .A0N(n2245), .A1N(n5827), .B0(n5821), .Y(n1133) );
OAI2BB1X2TS U5006 ( .A0N(n2122), .A1N(n5862), .B0(n5830), .Y(n1140) );
NAND2X4TS U5007 ( .A(n5733), .B(n3231), .Y(n5110) );
OAI2BB1X2TS U5008 ( .A0N(n2365), .A1N(n5862), .B0(n5813), .Y(n1141) );
NAND2X4TS U5009 ( .A(n4788), .B(n4847), .Y(n3179) );
NOR2X8TS U5010 ( .A(n2379), .B(n2334), .Y(n3823) );
OAI2BB1X1TS U5011 ( .A0N(n3366), .A1N(n3365), .B0(n4287), .Y(n2646) );
NAND2X6TS U5012 ( .A(n3076), .B(n3075), .Y(n3074) );
NAND2X2TS U5013 ( .A(n2197), .B(intDY[45]), .Y(n3837) );
AND2X8TS U5014 ( .A(n3468), .B(n2648), .Y(n3456) );
NOR2X4TS U5015 ( .A(n3467), .B(n3457), .Y(n2648) );
AND3X6TS U5016 ( .A(n5932), .B(n4360), .C(n5928), .Y(n2649) );
NAND2X4TS U5017 ( .A(n5075), .B(n5194), .Y(n5072) );
NAND3X8TS U5018 ( .A(n4483), .B(n3561), .C(n3564), .Y(n3546) );
NAND2X4TS U5019 ( .A(n5190), .B(n2662), .Y(n5192) );
NAND2X2TS U5020 ( .A(n5136), .B(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n2880) );
NAND4X8TS U5021 ( .A(n3592), .B(n3565), .C(n3542), .D(n3541), .Y(n3545) );
NOR2X8TS U5022 ( .A(n5268), .B(n5291), .Y(n3565) );
NAND2X4TS U5023 ( .A(n5126), .B(n5109), .Y(n3656) );
AOI22X2TS U5024 ( .A0(n5090), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[58]), .Y(n3657) );
NOR2X4TS U5025 ( .A(n3906), .B(n3613), .Y(n4410) );
NOR2X6TS U5026 ( .A(n2668), .B(n2144), .Y(n3902) );
NAND2X4TS U5027 ( .A(n5054), .B(n3667), .Y(n5783) );
OAI21X4TS U5028 ( .A0(n4292), .A1(n4675), .B0(n4291), .Y(n4293) );
NAND2X8TS U5029 ( .A(n4600), .B(n1648), .Y(n3241) );
NAND2X4TS U5030 ( .A(n2896), .B(n2532), .Y(n3950) );
NAND2X6TS U5031 ( .A(n5767), .B(n2792), .Y(n2791) );
NAND2X8TS U5032 ( .A(n5764), .B(n5885), .Y(n5767) );
XNOR2X4TS U5033 ( .A(n2776), .B(n3936), .Y(n3938) );
OAI2BB1X4TS U5034 ( .A0N(n2162), .A1N(n2735), .B0(n5815), .Y(n1155) );
NOR2X2TS U5035 ( .A(n4695), .B(n4701), .Y(n4704) );
NAND2X4TS U5036 ( .A(n1627), .B(n2609), .Y(n4809) );
NOR2X8TS U5037 ( .A(n2977), .B(n5421), .Y(n5427) );
XOR2X4TS U5038 ( .A(n2777), .B(n2657), .Y(n3149) );
NAND2X4TS U5039 ( .A(n2874), .B(DmP[59]), .Y(n2657) );
XNOR2X4TS U5040 ( .A(n2777), .B(n2658), .Y(n3935) );
NAND2X4TS U5041 ( .A(n2874), .B(n1939), .Y(n2658) );
NOR2X4TS U5042 ( .A(n3406), .B(n4764), .Y(n3402) );
NAND2X4TS U5043 ( .A(n4523), .B(n4522), .Y(n4766) );
NOR2X8TS U5044 ( .A(n3785), .B(n3847), .Y(n3850) );
AOI22X2TS U5045 ( .A0(n6050), .A1(n5558), .B0(n2887), .B1(n5561), .Y(n5361)
);
BUFX12TS U5046 ( .A(n5642), .Y(n2889) );
NAND3X8TS U5047 ( .A(n5327), .B(n5326), .C(n5325), .Y(n5617) );
OAI21X4TS U5048 ( .A0(n3746), .A1(n3745), .B0(n3744), .Y(n3752) );
NAND2X2TS U5049 ( .A(n5190), .B(n5194), .Y(n4998) );
AOI22X2TS U5050 ( .A0(n2674), .A1(n5608), .B0(n5578), .B1(n5663), .Y(n5583)
);
NAND2X4TS U5051 ( .A(n5896), .B(n5897), .Y(n5903) );
NAND2X4TS U5052 ( .A(n5715), .B(n5780), .Y(n5719) );
NOR2X4TS U5053 ( .A(n2428), .B(n6204), .Y(n4534) );
AOI22X2TS U5054 ( .A0(n5592), .A1(n2889), .B0(n6050), .B1(n5594), .Y(n5549)
);
NAND4X4TS U5055 ( .A(n2056), .B(n5929), .C(n2438), .D(n5930), .Y(n6544) );
NOR2X8TS U5056 ( .A(n2250), .B(n2311), .Y(n3833) );
NAND2X4TS U5057 ( .A(n2314), .B(n3590), .Y(n3605) );
NOR2X4TS U5058 ( .A(n4399), .B(n4853), .Y(n4855) );
NOR2X2TS U5059 ( .A(n4826), .B(n4372), .Y(n4829) );
INVX16TS U5060 ( .A(n2427), .Y(n4541) );
AOI22X1TS U5061 ( .A0(n5849), .A1(n2192), .B0(n2003), .B1(n5820), .Y(n5805)
);
AOI22X2TS U5062 ( .A0(n2741), .A1(n2660), .B0(n2001), .B1(n1645), .Y(n4313)
);
AOI22X2TS U5063 ( .A0(n2718), .A1(n1848), .B0(n5874), .B1(n1906), .Y(n5769)
);
AOI22X2TS U5064 ( .A0(n2732), .A1(n2380), .B0(n1955), .B1(n1645), .Y(n5730)
);
AOI22X2TS U5065 ( .A0(n2730), .A1(n2230), .B0(n5807), .B1(n1856), .Y(n3887)
);
AOI22X2TS U5066 ( .A0(n5860), .A1(n2447), .B0(n5874), .B1(n1925), .Y(n3889)
);
AOI22X2TS U5067 ( .A0(n2976), .A1(n2043), .B0(n5820), .B1(n1937), .Y(n5839)
);
AOI22X2TS U5068 ( .A0(n2976), .A1(n2149), .B0(n3230), .B1(n1935), .Y(n5751)
);
AOI22X2TS U5069 ( .A0(n2740), .A1(n2174), .B0(n5807), .B1(n1904), .Y(n5774)
);
AOI22X2TS U5070 ( .A0(n2740), .A1(n2436), .B0(n1892), .B1(n5777), .Y(n3888)
);
OAI2BB1X2TS U5071 ( .A0N(n2291), .A1N(n1599), .B0(n4957), .Y(n1183) );
AOI22X2TS U5072 ( .A0(n2700), .A1(n2504), .B0(n5578), .B1(n5648), .Y(n5442)
);
INVX16TS U5073 ( .A(n2670), .Y(n2671) );
INVX12TS U5074 ( .A(n2672), .Y(n2676) );
AOI22X2TS U5075 ( .A0(n5148), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n5149), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .Y(n5111) );
OR2X4TS U5076 ( .A(n2832), .B(n6244), .Y(n5003) );
BUFX20TS U5077 ( .A(n3512), .Y(n2832) );
NAND2X4TS U5078 ( .A(n4268), .B(n4279), .Y(n4656) );
NAND2X4TS U5079 ( .A(n4787), .B(n4847), .Y(n4540) );
OR2X8TS U5080 ( .A(n5272), .B(n5273), .Y(n3376) );
NOR2X4TS U5081 ( .A(n5421), .B(n5242), .Y(n2695) );
BUFX20TS U5082 ( .A(n5752), .Y(n2702) );
NAND2X2TS U5083 ( .A(n2150), .B(n2172), .Y(n3840) );
NAND2X6TS U5084 ( .A(n2502), .B(n3199), .Y(n4865) );
OAI21X4TS U5085 ( .A0(n3760), .A1(n3759), .B0(n3758), .Y(n3761) );
OAI21X4TS U5086 ( .A0(n3310), .A1(n2773), .B0(n3995), .Y(n2705) );
OAI21X4TS U5087 ( .A0(n3839), .A1(n3838), .B0(n3837), .Y(n3845) );
BUFX6TS U5088 ( .A(n3198), .Y(n3195) );
OAI21X4TS U5089 ( .A0(n4539), .A1(n4791), .B0(n4538), .Y(n4850) );
NOR2X8TS U5090 ( .A(n4566), .B(n4565), .Y(n4539) );
NAND3X8TS U5091 ( .A(n6304), .B(n6303), .C(n6302), .Y(n6006) );
NAND2X4TS U5092 ( .A(n2756), .B(n6006), .Y(n5305) );
BUFX20TS U5093 ( .A(n2453), .Y(n3256) );
AND2X4TS U5094 ( .A(n2865), .B(n1884), .Y(n3423) );
XOR2X4TS U5095 ( .A(n3316), .B(n2567), .Y(n4772) );
XOR2X4TS U5096 ( .A(n2893), .B(n3959), .Y(n2707) );
AOI22X2TS U5097 ( .A0(n2676), .A1(n5616), .B0(n5628), .B1(n5601), .Y(n5474)
);
NAND2X2TS U5098 ( .A(n4302), .B(n4303), .Y(n4304) );
INVX4TS U5099 ( .A(n4274), .Y(n4303) );
OAI2BB1X4TS U5100 ( .A0N(n2097), .A1N(n5831), .B0(n5808), .Y(n1124) );
OAI21X4TS U5101 ( .A0(n3823), .A1(n3822), .B0(n3821), .Y(n3824) );
NAND2X4TS U5102 ( .A(n1661), .B(exp_oper_result[5]), .Y(n3520) );
NAND2X4TS U5103 ( .A(n1661), .B(exp_oper_result[1]), .Y(n5162) );
OAI21X4TS U5104 ( .A0(n3814), .A1(n3813), .B0(n3812), .Y(n3815) );
OAI21X4TS U5105 ( .A0(n3749), .A1(n3748), .B0(n3747), .Y(n3750) );
NOR2X8TS U5106 ( .A(n3749), .B(n3730), .Y(n3751) );
OAI21X4TS U5107 ( .A0(n3719), .A1(n3718), .B0(n3717), .Y(n3720) );
NOR2X8TS U5108 ( .A(n2773), .B(n3945), .Y(n4807) );
NOR2X8TS U5109 ( .A(n3994), .B(n2513), .Y(n2773) );
NOR2X8TS U5110 ( .A(n3798), .B(n3864), .Y(n3865) );
NAND2X2TS U5111 ( .A(n2228), .B(n2192), .Y(n3747) );
NOR2X8TS U5112 ( .A(n2106), .B(n2313), .Y(n3757) );
AOI22X2TS U5113 ( .A0(n2674), .A1(n5595), .B0(n5592), .B1(n2699), .Y(n5417)
);
NAND3X8TS U5114 ( .A(n5264), .B(n5263), .C(n5262), .Y(n5592) );
NAND2X4TS U5115 ( .A(n4529), .B(n3049), .Y(n3357) );
NOR2X8TS U5116 ( .A(n2385), .B(n2343), .Y(n3820) );
OAI21X4TS U5117 ( .A0(n3820), .A1(n3819), .B0(n3818), .Y(n3826) );
NAND2X4TS U5118 ( .A(n4728), .B(n5952), .Y(n6524) );
OAI21X4TS U5119 ( .A0(n3811), .A1(n3810), .B0(n3809), .Y(n3817) );
NOR2X8TS U5120 ( .A(n2435), .B(n2293), .Y(n3769) );
OAI21X4TS U5121 ( .A0(n3768), .A1(n3769), .B0(n3767), .Y(n3770) );
XOR2X4TS U5122 ( .A(n2624), .B(n2766), .Y(n2711) );
NOR2X8TS U5123 ( .A(n5295), .B(n5283), .Y(n4483) );
INVX4TS U5124 ( .A(n5679), .Y(n2712) );
AOI21X2TS U5125 ( .A0(n2753), .A1(n5700), .B0(n5699), .Y(n5701) );
AND2X4TS U5126 ( .A(n2671), .B(Sgf_normalized_result[44]), .Y(n4502) );
NAND3X8TS U5127 ( .A(n6379), .B(n6378), .C(n6377), .Y(n5997) );
NOR2X4TS U5128 ( .A(n5992), .B(n5994), .Y(n3543) );
NAND3X8TS U5129 ( .A(n3543), .B(n4486), .C(n3544), .Y(n3559) );
OAI22X2TS U5130 ( .A0(n4083), .A1(n1653), .B0(n2538), .B1(n3578), .Y(n3596)
);
NAND3X4TS U5131 ( .A(n5059), .B(n5014), .C(n5013), .Y(n5704) );
NAND3X4TS U5132 ( .A(n5059), .B(n5058), .C(n5057), .Y(n5900) );
NOR2X8TS U5133 ( .A(n3081), .B(n3082), .Y(n5214) );
BUFX20TS U5134 ( .A(n2629), .Y(n3394) );
XOR2X4TS U5135 ( .A(n3415), .B(n2717), .Y(n5932) );
XOR2X4TS U5136 ( .A(n3263), .B(n4713), .Y(n3421) );
AOI21X2TS U5137 ( .A0(n2759), .A1(n5477), .B0(n5233), .Y(n5174) );
AOI22X1TS U5138 ( .A0(n5760), .A1(n2099), .B0(n2008), .B1(n5842), .Y(n5813)
);
AOI22X2TS U5139 ( .A0(n2741), .A1(n2320), .B0(n2298), .B1(n5825), .Y(n5817)
);
MXI2X2TS U5140 ( .A(n6084), .B(n1870), .S0(n6119), .Y(n1343) );
BUFX3TS U5141 ( .A(n4870), .Y(n6437) );
BUFX3TS U5142 ( .A(n4870), .Y(n6435) );
BUFX3TS U5143 ( .A(n4870), .Y(n6413) );
BUFX3TS U5144 ( .A(n4870), .Y(n6420) );
BUFX3TS U5145 ( .A(n4870), .Y(n6414) );
BUFX3TS U5146 ( .A(n4870), .Y(n6434) );
BUFX3TS U5147 ( .A(n4870), .Y(n6433) );
BUFX3TS U5148 ( .A(n4870), .Y(n6436) );
BUFX3TS U5149 ( .A(n4870), .Y(n2728) );
CLKINVX3TS U5150 ( .A(rst), .Y(n2737) );
CLKINVX3TS U5151 ( .A(rst), .Y(n2764) );
AOI22X2TS U5152 ( .A0(n2722), .A1(n2932), .B0(n5784), .B1(n2107), .Y(n2931)
);
AOI22X2TS U5153 ( .A0(n2956), .A1(n2722), .B0(Sgf_normalized_result[0]),
.B1(n5784), .Y(n2955) );
AOI21X2TS U5154 ( .A0(n2297), .A1(n4620), .B0(n4619), .Y(n4622) );
AOI22X2TS U5155 ( .A0(n5104), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[59]), .Y(n3536) );
AOI22X2TS U5156 ( .A0(n5627), .A1(n5629), .B0(n2887), .B1(n5633), .Y(n5545)
);
AOI22X2TS U5157 ( .A0(n5590), .A1(n5601), .B0(n2889), .B1(n5616), .Y(n5490)
);
AOI22X2TS U5158 ( .A0(n2889), .A1(n5618), .B0(n5622), .B1(n5680), .Y(n5613)
);
AOI22X2TS U5159 ( .A0(n2887), .A1(n5567), .B0(n5572), .B1(n5668), .Y(n5367)
);
AOI22X2TS U5160 ( .A0(n2887), .A1(n5573), .B0(n5595), .B1(n2761), .Y(n5404)
);
BUFX20TS U5161 ( .A(n5321), .Y(n2725) );
NAND2X4TS U5162 ( .A(n5645), .B(n3377), .Y(n5294) );
NAND2X2TS U5163 ( .A(n5510), .B(Add_Subt_result[6]), .Y(n5491) );
BUFX20TS U5164 ( .A(n5829), .Y(n2730) );
AOI22X2TS U5165 ( .A0(n2718), .A1(n2114), .B0(n1910), .B1(n5842), .Y(n5789)
);
AOI22X2TS U5166 ( .A0(n2718), .A1(n2127), .B0(n1908), .B1(n5842), .Y(n5790)
);
BUFX20TS U5167 ( .A(n3269), .Y(n2741) );
BUFX20TS U5168 ( .A(n5282), .Y(n5639) );
NAND2X2TS U5169 ( .A(n2731), .B(n3377), .Y(n5265) );
NAND2X2TS U5170 ( .A(n2731), .B(n6010), .Y(n5349) );
BUFX20TS U5171 ( .A(n5829), .Y(n2732) );
AOI22X2TS U5172 ( .A0(n2730), .A1(n2311), .B0(n1987), .B1(n5871), .Y(n5867)
);
AOI22X2TS U5173 ( .A0(n2730), .A1(n2356), .B0(n1966), .B1(n5807), .Y(n5809)
);
AOI22X2TS U5174 ( .A0(n2741), .A1(n2393), .B0(n2076), .B1(n3230), .Y(n5847)
);
AOI22X2TS U5175 ( .A0(n2718), .A1(n2095), .B0(n1929), .B1(n5825), .Y(n5133)
);
AOI22X2TS U5176 ( .A0(n2741), .A1(n2665), .B0(n2130), .B1(n5820), .Y(n5801)
);
AOI22X2TS U5177 ( .A0(n2730), .A1(intDY[45]), .B0(n1986), .B1(n5871), .Y(
n5872) );
AOI22X2TS U5178 ( .A0(n2740), .A1(n2365), .B0(n1898), .B1(n5871), .Y(n5134)
);
AOI22X2TS U5179 ( .A0(n2732), .A1(n2122), .B0(n2339), .B1(n1645), .Y(n5132)
);
BUFX20TS U5180 ( .A(n2702), .Y(n2740) );
AOI22X2TS U5181 ( .A0(n2718), .A1(n2109), .B0(n2345), .B1(n3230), .Y(n5755)
);
AOI22X2TS U5182 ( .A0(n2975), .A1(n2265), .B0(DmP[56]), .B1(n5842), .Y(n5843) );
AOI22X2TS U5183 ( .A0(n2596), .A1(n1869), .B0(n1879), .B1(n3230), .Y(n5754)
);
AOI22X2TS U5184 ( .A0(n2975), .A1(n2196), .B0(DMP[45]), .B1(n3230), .Y(n5756) );
AOI22X2TS U5185 ( .A0(n5736), .A1(n2378), .B0(n2406), .B1(n3230), .Y(n5758)
);
BUFX3TS U5186 ( .A(n6264), .Y(n6423) );
CLKBUFX3TS U5187 ( .A(n2744), .Y(n6269) );
BUFX3TS U5188 ( .A(n2745), .Y(n6429) );
BUFX3TS U5189 ( .A(n4868), .Y(n6416) );
BUFX3TS U5190 ( .A(n2736), .Y(n6421) );
BUFX3TS U5191 ( .A(n4869), .Y(n6448) );
BUFX3TS U5192 ( .A(n4869), .Y(n6447) );
BUFX3TS U5193 ( .A(n4868), .Y(n6442) );
BUFX3TS U5194 ( .A(n4868), .Y(n6444) );
BUFX3TS U5195 ( .A(n4868), .Y(n6445) );
BUFX3TS U5196 ( .A(n4868), .Y(n6440) );
AND2X8TS U5197 ( .A(n3991), .B(n3990), .Y(n6011) );
AOI22X2TS U5198 ( .A0(n2746), .A1(n5996), .B0(n1892), .B1(n2723), .Y(n5647)
);
AOI22X2TS U5199 ( .A0(n2746), .A1(n6003), .B0(n1900), .B1(n2723), .Y(n5644)
);
NAND2X4TS U5200 ( .A(n2746), .B(n1658), .Y(n5262) );
OAI21X2TS U5201 ( .A0(n4759), .A1(n4764), .B0(n1641), .Y(n3404) );
AOI21X2TS U5202 ( .A0(n2753), .A1(n5717), .B0(n5716), .Y(n5718) );
NAND2X2TS U5203 ( .A(n5145), .B(n2753), .Y(n4056) );
INVX4TS U5204 ( .A(n1820), .Y(n5899) );
INVX16TS U5205 ( .A(n2755), .Y(n2756) );
BUFX20TS U5206 ( .A(n5321), .Y(n5510) );
BUFX20TS U5207 ( .A(n5321), .Y(n5514) );
OAI2BB1X2TS U5208 ( .A0N(n2221), .A1N(n5862), .B0(n5819), .Y(n1132) );
AOI22X2TS U5209 ( .A0(n2699), .A1(n5416), .B0(n2759), .B1(n5568), .Y(n5395)
);
BUFX8TS U5210 ( .A(n5426), .Y(n2760) );
INVX12TS U5211 ( .A(n4248), .Y(n4246) );
OAI21X1TS U5212 ( .A0(n2187), .A1(n4217), .B0(n4219), .Y(n4220) );
OR4X2TS U5213 ( .A(n5982), .B(n4899), .C(n6026), .D(n4898), .Y(n1561) );
NAND2X4TS U5214 ( .A(n4725), .B(n4724), .Y(n4726) );
CLKINVX1TS U5215 ( .A(n4723), .Y(n4725) );
NAND2X2TS U5216 ( .A(n2724), .B(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .Y(n3293) );
NAND2X2TS U5217 ( .A(n5083), .B(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n3191) );
AOI22X2TS U5218 ( .A0(n2739), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n5101), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n4974) );
NAND2X2TS U5219 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n2961) );
NAND2X8TS U5220 ( .A(n3313), .B(n3314), .Y(n2765) );
AOI21X4TS U5221 ( .A0(n4806), .A1(n2772), .B0(n2769), .Y(n2768) );
OAI21X4TS U5222 ( .A0(n3965), .A1(n4809), .B0(n3966), .Y(n2769) );
OAI21X4TS U5223 ( .A0(n2773), .A1(n3310), .B0(n3995), .Y(n4806) );
NAND2X4TS U5224 ( .A(n2513), .B(n1844), .Y(n3995) );
NAND2X8TS U5225 ( .A(n3206), .B(n2771), .Y(n2770) );
AND2X8TS U5226 ( .A(n4807), .B(n2772), .Y(n2771) );
NOR2X8TS U5227 ( .A(n2798), .B(n2521), .Y(n3965) );
NOR2X8TS U5228 ( .A(n3931), .B(n1627), .Y(n4808) );
NAND3X8TS U5229 ( .A(n2885), .B(n2514), .C(n3953), .Y(n3206) );
NAND2X8TS U5230 ( .A(n2776), .B(n2775), .Y(n3958) );
NOR2X8TS U5231 ( .A(n2551), .B(n2778), .Y(n2849) );
NAND2X8TS U5232 ( .A(n3295), .B(n2525), .Y(n3527) );
OR2X8TS U5233 ( .A(n2827), .B(n2883), .Y(n5059) );
NAND2X8TS U5234 ( .A(n2827), .B(n2867), .Y(n5054) );
NAND2X8TS U5235 ( .A(n3256), .B(n3528), .Y(n2827) );
NAND2BX4TS U5236 ( .AN(n2782), .B(n5749), .Y(n1489) );
NOR2BX4TS U5237 ( .AN(n3531), .B(n2784), .Y(n3508) );
NOR2BX4TS U5238 ( .AN(n3539), .B(n2787), .Y(n2786) );
NAND2BX4TS U5239 ( .AN(n2789), .B(n5192), .Y(n2788) );
NAND3BX4TS U5240 ( .AN(n2790), .B(n5786), .C(n5787), .Y(n1494) );
NAND2BX4TS U5241 ( .AN(n2791), .B(n5766), .Y(n1563) );
NAND3BX4TS U5242 ( .AN(n2793), .B(n3660), .C(n3661), .Y(n1493) );
NAND3BX4TS U5243 ( .AN(n2796), .B(n5740), .C(n5741), .Y(n1490) );
NAND2X8TS U5244 ( .A(n2797), .B(n2046), .Y(n2912) );
NAND2X4TS U5245 ( .A(n2521), .B(n2613), .Y(n3966) );
XOR2X4TS U5246 ( .A(n2893), .B(n1632), .Y(n2798) );
OAI21X4TS U5247 ( .A0(n2803), .A1(n2762), .B0(n2800), .Y(n4824) );
XOR2X4TS U5248 ( .A(n2802), .B(n4823), .Y(n2801) );
OAI21X2TS U5249 ( .A0(n4952), .A1(n1838), .B0(n4948), .Y(n2802) );
AOI21X4TS U5250 ( .A0(n4822), .A1(n2497), .B0(n2204), .Y(n4952) );
XNOR2X4TS U5251 ( .A(n2804), .B(n4820), .Y(n2803) );
OAI21X4TS U5252 ( .A0(n4950), .A1(n1592), .B0(n4816), .Y(n2804) );
AOI21X4TS U5253 ( .A0(n4815), .A1(n4933), .B0(n3216), .Y(n4950) );
NAND3X8TS U5254 ( .A(n6387), .B(n6388), .C(n6386), .Y(n5985) );
NAND3X8TS U5255 ( .A(n6390), .B(n6391), .C(n6389), .Y(n6003) );
OAI2BB1X4TS U5256 ( .A0N(n4556), .A1N(n3164), .B0(n4555), .Y(n2807) );
AOI21X4TS U5257 ( .A0(n2644), .A1(n4557), .B0(n2807), .Y(n2806) );
NAND3BX4TS U5258 ( .AN(n2808), .B(n2812), .C(n2816), .Y(n5731) );
NOR2X8TS U5259 ( .A(n4079), .B(n3495), .Y(n5906) );
NAND2X8TS U5260 ( .A(n5912), .B(n3570), .Y(n4079) );
AOI21X4TS U5261 ( .A0(n2820), .A1(n2822), .B0(n2817), .Y(n3701) );
OAI2BB1X4TS U5262 ( .A0N(n2439), .A1N(n2191), .B0(n2821), .Y(n2820) );
OAI22X4TS U5263 ( .A0(n2191), .A1(n2439), .B0(n2161), .B1(n2447), .Y(n2821)
);
INVX4TS U5264 ( .A(n4269), .Y(n4285) );
XOR2X4TS U5265 ( .A(n2825), .B(n4721), .Y(n4722) );
AOI21X4TS U5266 ( .A0(n3049), .A1(n4720), .B0(n4719), .Y(n2825) );
INVX16TS U5267 ( .A(n2372), .Y(n5983) );
INVX2TS U5268 ( .A(n3992), .Y(n3946) );
NAND2X4TS U5269 ( .A(n5710), .B(n5897), .Y(n5714) );
OAI2BB1X4TS U5270 ( .A0N(n5845), .A1N(n2174), .B0(n5836), .Y(n1165) );
NOR2X8TS U5271 ( .A(n2220), .B(n2304), .Y(n3766) );
BUFX6TS U5272 ( .A(n3950), .Y(n2828) );
MX2X4TS U5273 ( .A(n5931), .B(exp_oper_result[6]), .S0(n6406), .Y(n1432) );
OAI21X4TS U5274 ( .A0(n3692), .A1(n3691), .B0(n3690), .Y(n3698) );
NAND2X2TS U5275 ( .A(n2435), .B(n2293), .Y(n3767) );
INVX12TS U5276 ( .A(n5401), .Y(n5242) );
AOI21X4TS U5277 ( .A0(n4658), .A1(n4283), .B0(n4282), .Y(n4665) );
OAI21X4TS U5278 ( .A0(n5940), .A1(n4634), .B0(n4635), .Y(n4658) );
OAI2BB1X4TS U5279 ( .A0N(n5851), .A1N(n2439), .B0(n5727), .Y(n1170) );
NAND2X4TS U5280 ( .A(n3381), .B(n5952), .Y(n6488) );
OAI21X4TS U5281 ( .A0(n2830), .A1(n6407), .B0(n2829), .Y(n6458) );
XOR2X4TS U5282 ( .A(n3503), .B(n4573), .Y(n2830) );
OAI2BB1X4TS U5283 ( .A0N(n4654), .A1N(n3050), .B0(n2500), .Y(n3263) );
CLKINVX12TS U5284 ( .A(n4358), .Y(n5832) );
NAND2X4TS U5285 ( .A(n3482), .B(n3481), .Y(n3480) );
NOR2X2TS U5286 ( .A(n4826), .B(n4007), .Y(n4018) );
NAND2X8TS U5287 ( .A(n3244), .B(n6022), .Y(n2831) );
NOR2X8TS U5288 ( .A(n3549), .B(n3548), .Y(n3550) );
NAND3X4TS U5289 ( .A(n2897), .B(n1723), .C(DmP[53]), .Y(n3919) );
NOR3X4TS U5290 ( .A(n5998), .B(n6002), .C(n6001), .Y(n3547) );
OAI22X4TS U5291 ( .A0(n3597), .A1(n2833), .B0(n1813), .B1(n1648), .Y(n3510)
);
AOI22X2TS U5292 ( .A0(n5121), .A1(n2722), .B0(n1677), .B1(n5784), .Y(n5122)
);
NAND3X8TS U5293 ( .A(n1625), .B(n5350), .C(n5349), .Y(n5569) );
XNOR2X4TS U5294 ( .A(n4858), .B(n4207), .Y(n4211) );
INVX12TS U5295 ( .A(n2834), .Y(n5912) );
NAND2X8TS U5296 ( .A(n2485), .B(n3562), .Y(n2834) );
INVX12TS U5297 ( .A(n2835), .Y(n5926) );
NOR2X8TS U5298 ( .A(n3169), .B(n2843), .Y(n2836) );
NOR2X8TS U5299 ( .A(n2489), .B(n2844), .Y(n2837) );
NAND2X4TS U5300 ( .A(n5921), .B(n5922), .Y(n2839) );
AOI21X4TS U5301 ( .A0(n4577), .A1(n4576), .B0(n4575), .Y(n2843) );
XOR2X4TS U5302 ( .A(n2777), .B(n3942), .Y(n2848) );
NOR2X8TS U5303 ( .A(n2852), .B(n2851), .Y(n3347) );
NOR2X8TS U5304 ( .A(n4405), .B(n4397), .Y(n4406) );
NAND3X8TS U5305 ( .A(n2860), .B(n3153), .C(n3213), .Y(n2861) );
NAND2X8TS U5306 ( .A(n3093), .B(n3092), .Y(n2860) );
AOI21X4TS U5307 ( .A0(n2643), .A1(n2572), .B0(n3487), .Y(n3486) );
NAND2X8TS U5308 ( .A(n3520), .B(n3925), .Y(n3521) );
NAND2X8TS U5309 ( .A(n5780), .B(n5153), .Y(n5107) );
INVX16TS U5310 ( .A(n2873), .Y(n5321) );
NAND2X8TS U5311 ( .A(n3526), .B(n3120), .Y(n5274) );
NAND2X6TS U5312 ( .A(n1661), .B(exp_oper_result[3]), .Y(n2901) );
NOR2X8TS U5313 ( .A(n4982), .B(n5109), .Y(n3662) );
NAND2BX4TS U5314 ( .AN(n2876), .B(n5888), .Y(n1475) );
OAI21X4TS U5315 ( .A0(n5884), .A1(n5886), .B0(n5885), .Y(n2877) );
NAND2BX4TS U5316 ( .AN(n2878), .B(n5137), .Y(n5884) );
OR3X6TS U5317 ( .A(n3521), .B(n2883), .C(n2882), .Y(n4940) );
NOR2BX4TS U5318 ( .AN(n5021), .B(n1638), .Y(n3288) );
OR2X8TS U5319 ( .A(n2896), .B(n2532), .Y(n3166) );
OAI2BB1X4TS U5320 ( .A0N(n2528), .A1N(n5590), .B0(n2890), .Y(n5691) );
NAND2BX4TS U5321 ( .AN(n5678), .B(n2889), .Y(n2890) );
NOR2X1TS U5322 ( .A(n2977), .B(n1650), .Y(n5414) );
INVX12TS U5323 ( .A(n2891), .Y(n5386) );
XOR2X4TS U5324 ( .A(n2777), .B(n2894), .Y(n3931) );
XOR2X4TS U5325 ( .A(n2624), .B(n3930), .Y(n3994) );
NAND2X4TS U5326 ( .A(n4796), .B(n3415), .Y(n3418) );
AOI21X4TS U5327 ( .A0(n3415), .A1(n3147), .B0(n4353), .Y(n4357) );
AOI21X4TS U5328 ( .A0(n3415), .A1(n2510), .B0(n4803), .Y(n4805) );
NAND2X8TS U5329 ( .A(n2901), .B(n3926), .Y(n3522) );
NOR2X8TS U5330 ( .A(n4072), .B(n4347), .Y(n4031) );
NAND2X8TS U5331 ( .A(n2902), .B(n4334), .Y(n4380) );
OR2X8TS U5332 ( .A(n4333), .B(n4775), .Y(n2902) );
OAI22X4TS U5333 ( .A0(n2907), .A1(n2905), .B0(n2097), .B1(n2261), .Y(n2904)
);
NOR2X8TS U5334 ( .A(n2098), .B(n2260), .Y(n2907) );
OAI22X4TS U5335 ( .A0(n3742), .A1(n2910), .B0(n2136), .B1(n2909), .Y(n2908)
);
NAND2X8TS U5336 ( .A(n3043), .B(n1663), .Y(n3042) );
AOI21X4TS U5337 ( .A0(n2643), .A1(n5950), .B0(n2987), .Y(n2986) );
NOR2X8TS U5338 ( .A(n4421), .B(n4414), .Y(n3907) );
OAI21X4TS U5339 ( .A0(n5213), .A1(n5208), .B0(n5209), .Y(n4420) );
NAND2X8TS U5340 ( .A(n3090), .B(n3505), .Y(n5209) );
NAND2X4TS U5341 ( .A(n2918), .B(n5960), .Y(n6497) );
NOR2X2TS U5342 ( .A(n4753), .B(n4476), .Y(n2922) );
OR2X8TS U5343 ( .A(n2139), .B(n2668), .Y(n3612) );
INVX2TS U5344 ( .A(n2924), .Y(n3089) );
OAI21X4TS U5345 ( .A0(n4934), .A1(n4936), .B0(n2924), .Y(n4821) );
XOR2X4TS U5346 ( .A(n2925), .B(n2498), .Y(n5945) );
NAND2X4TS U5347 ( .A(n2713), .B(n2927), .Y(n2926) );
NAND2X2TS U5348 ( .A(n4969), .B(n2664), .Y(n2934) );
NOR2BX4TS U5349 ( .AN(n3524), .B(n2937), .Y(n2936) );
NAND2X4TS U5350 ( .A(n3390), .B(n4019), .Y(n4027) );
NAND2X8TS U5351 ( .A(n3159), .B(n3158), .Y(n2942) );
OR2X8TS U5352 ( .A(n5894), .B(n2945), .Y(n1480) );
AOI22X4TS U5353 ( .A0(n2753), .A1(n5893), .B0(n5885), .B1(n5892), .Y(n2947)
);
NAND3BX4TS U5354 ( .AN(n2948), .B(n2949), .C(n5152), .Y(n5891) );
OAI2BB1X4TS U5355 ( .A0N(Barrel_Shifter_module_Mux_Array_Data_array[71]),
.A1N(n5149), .B0(n5151), .Y(n2948) );
NAND2X8TS U5356 ( .A(n6018), .B(n2422), .Y(n4248) );
NAND2X8TS U5357 ( .A(n4902), .B(n2422), .Y(n1441) );
INVX16TS U5358 ( .A(n4264), .Y(n5694) );
BUFX20TS U5359 ( .A(n5694), .Y(n2952) );
NAND2X8TS U5360 ( .A(n3072), .B(n3646), .Y(n3281) );
NAND2X8TS U5361 ( .A(n4009), .B(n3625), .Y(n4040) );
AND2X8TS U5362 ( .A(n3160), .B(n3003), .Y(n3238) );
NAND2X8TS U5363 ( .A(n3410), .B(n3165), .Y(n3160) );
NAND2X8TS U5364 ( .A(n2962), .B(n2541), .Y(n5764) );
OAI21X4TS U5365 ( .A0(n2963), .A1(n6063), .B0(n3057), .Y(n1518) );
AOI22X4TS U5366 ( .A0(n2965), .A1(n2762), .B0(n3058), .B1(n2964), .Y(n2963)
);
INVX2TS U5367 ( .A(n2762), .Y(n2964) );
XOR2X4TS U5368 ( .A(n3060), .B(n4866), .Y(n2965) );
INVX2TS U5369 ( .A(n4024), .Y(n2966) );
XOR2X4TS U5370 ( .A(n2967), .B(n4336), .Y(n3502) );
OAI2BB1X4TS U5371 ( .A0N(n4332), .A1N(n2953), .B0(n2968), .Y(n2967) );
AOI21X4TS U5372 ( .A0(n4327), .A1(n2952), .B0(n2969), .Y(n2968) );
NAND2X8TS U5373 ( .A(n4216), .B(n3636), .Y(n4314) );
NOR2X8TS U5374 ( .A(n3319), .B(n4217), .Y(n3636) );
NAND2X8TS U5375 ( .A(n4321), .B(n3645), .Y(n3380) );
NOR2X8TS U5376 ( .A(n4252), .B(n4262), .Y(n3079) );
NOR2X8TS U5377 ( .A(n4337), .B(n4259), .Y(n4260) );
NAND2X8TS U5378 ( .A(n2874), .B(exp_oper_result[2]), .Y(n2978) );
NAND2X8TS U5379 ( .A(n3470), .B(n4102), .Y(n4106) );
NAND2X8TS U5380 ( .A(n5934), .B(n4724), .Y(n2981) );
NAND2X4TS U5381 ( .A(n2985), .B(n5952), .Y(n6512) );
XNOR2X4TS U5382 ( .A(n2986), .B(n5951), .Y(n2985) );
MXI2X8TS U5383 ( .A(n1880), .B(n6206), .S0(n2993), .Y(n4522) );
OAI2BB1X4TS U5384 ( .A0N(n4603), .A1N(n2994), .B0(n2995), .Y(n6467) );
AOI21X4TS U5385 ( .A0(n2997), .A1(n2561), .B0(n2996), .Y(n2995) );
AOI21X4TS U5386 ( .A0(n4631), .A1(n4784), .B0(n2999), .Y(n2998) );
XOR2X4TS U5387 ( .A(n3002), .B(n4610), .Y(n4611) );
NAND2X8TS U5388 ( .A(n3004), .B(n2690), .Y(n3312) );
NOR2X8TS U5389 ( .A(n3909), .B(n3007), .Y(n3892) );
NAND2X8TS U5390 ( .A(n3011), .B(n2512), .Y(n3055) );
NAND3X8TS U5391 ( .A(n2281), .B(n3046), .C(n4912), .Y(n3016) );
OAI21X4TS U5392 ( .A0(n4931), .A1(n3184), .B0(n3610), .Y(n4814) );
NAND3X8TS U5393 ( .A(n3016), .B(n3015), .C(n4914), .Y(n3047) );
NOR2X1TS U5394 ( .A(n4925), .B(n3184), .Y(n4815) );
NAND2X8TS U5395 ( .A(n2131), .B(n3046), .Y(n3015) );
OA21X4TS U5396 ( .A0(n4816), .A1(n2171), .B0(n3611), .Y(n3017) );
XOR2X4TS U5397 ( .A(n4241), .B(n3025), .Y(n3020) );
OAI21X4TS U5398 ( .A0(n5207), .A1(n3890), .B0(n3891), .Y(n4241) );
NOR2X8TS U5399 ( .A(n3030), .B(n3029), .Y(n3028) );
NOR2X8TS U5400 ( .A(n4236), .B(n4222), .Y(n3980) );
NAND2X8TS U5401 ( .A(n3452), .B(n3039), .Y(n3153) );
NAND2X8TS U5402 ( .A(n3037), .B(n3035), .Y(n3452) );
AOI21X4TS U5403 ( .A0(n4195), .A1(n3038), .B0(n3036), .Y(n3035) );
OAI21X4TS U5404 ( .A0(n5176), .A1(n4002), .B0(n4001), .Y(n4195) );
NOR2X8TS U5405 ( .A(n4199), .B(n4432), .Y(n3038) );
NAND2X8TS U5406 ( .A(n3211), .B(n2694), .Y(n3041) );
NAND2X8TS U5407 ( .A(n2423), .B(n3045), .Y(n3044) );
NOR2X8TS U5408 ( .A(n6053), .B(n6052), .Y(n4912) );
BUFX20TS U5409 ( .A(n2706), .Y(n3050) );
NAND2X8TS U5410 ( .A(n3281), .B(n2050), .Y(n3053) );
NAND2X8TS U5411 ( .A(n2512), .B(n3273), .Y(n3054) );
BUFX20TS U5412 ( .A(n3367), .Y(n3056) );
OAI2BB1X4TS U5413 ( .A0N(n4647), .A1N(n3056), .B0(n3461), .Y(n3212) );
XOR2X4TS U5414 ( .A(n3059), .B(n4861), .Y(n3058) );
AOI21X4TS U5415 ( .A0(n4858), .A1(n4857), .B0(n2154), .Y(n3059) );
AOI21X4TS U5416 ( .A0(n4865), .A1(n4864), .B0(n4863), .Y(n3060) );
NOR2X8TS U5417 ( .A(n4410), .B(n3617), .Y(n3618) );
NAND2X8TS U5418 ( .A(n3065), .B(n1628), .Y(n3063) );
NAND2X8TS U5419 ( .A(n3408), .B(n3409), .Y(n3072) );
OA21X4TS U5420 ( .A0(n4259), .A1(n4340), .B0(n4258), .Y(n3075) );
OAI21X4TS U5421 ( .A0(n4067), .A1(n4329), .B0(n4066), .Y(n4261) );
AND2X8TS U5422 ( .A(n3078), .B(n2534), .Y(n4263) );
NAND2X8TS U5423 ( .A(n3082), .B(n3081), .Y(n5213) );
AOI21X4TS U5424 ( .A0(n3904), .A1(n4821), .B0(n3083), .Y(n3196) );
OAI21X4TS U5425 ( .A0(n4818), .A1(n4948), .B0(n4819), .Y(n3083) );
OAI21X4TS U5426 ( .A0(n3086), .A1(n2762), .B0(n3084), .Y(n4939) );
XNOR2X4TS U5427 ( .A(n4935), .B(n3087), .Y(n3086) );
NAND2X8TS U5428 ( .A(n3198), .B(n3202), .Y(n3096) );
NOR2X8TS U5429 ( .A(n3476), .B(n3477), .Y(n3092) );
NAND2X8TS U5430 ( .A(n2526), .B(n1642), .Y(n3477) );
NAND3X8TS U5431 ( .A(n3091), .B(n4243), .C(n3209), .Y(n3094) );
NOR2X8TS U5432 ( .A(n3232), .B(n3383), .Y(n3095) );
NOR2X8TS U5433 ( .A(n2462), .B(n4541), .Y(n3901) );
NAND2X8TS U5434 ( .A(n3104), .B(n3103), .Y(n3102) );
NOR2X8TS U5435 ( .A(n4286), .B(n4270), .Y(n4105) );
NAND2X8TS U5436 ( .A(n3108), .B(n3107), .Y(n3106) );
NOR2X4TS U5437 ( .A(n4399), .B(n5955), .Y(n3119) );
NOR2BX4TS U5438 ( .AN(n5959), .B(n4553), .Y(n3116) );
NAND2X8TS U5439 ( .A(n3122), .B(n3121), .Y(n3123) );
OAI21X4TS U5440 ( .A0(n4891), .A1(n6021), .B0(n6013), .Y(n5982) );
NAND2X8TS U5441 ( .A(n5276), .B(n3142), .Y(n5589) );
NOR2BX4TS U5442 ( .AN(n5275), .B(n3143), .Y(n3142) );
NOR2BX4TS U5443 ( .AN(n5515), .B(n5258), .Y(n3145) );
NAND2X8TS U5444 ( .A(n3147), .B(n3146), .Y(n3940) );
NOR2X8TS U5445 ( .A(n3631), .B(n3976), .Y(n3150) );
NAND2X6TS U5446 ( .A(n3241), .B(n3240), .Y(n1501) );
NAND3X2TS U5447 ( .A(n2647), .B(n4587), .C(Add_Subt_result[14]), .Y(n4593)
);
AND4X4TS U5448 ( .A(n4359), .B(n4358), .C(n5974), .D(n5980), .Y(n4360) );
NAND2X2TS U5449 ( .A(n2739), .B(n2742), .Y(n5045) );
NAND3BX4TS U5450 ( .AN(n4495), .B(n4493), .C(n4492), .Y(n3234) );
OAI21X4TS U5451 ( .A0(n3157), .A1(n6407), .B0(n3156), .Y(n6459) );
OAI21X2TS U5452 ( .A0(n4026), .A1(n4372), .B0(n1598), .Y(n4828) );
MXI2X4TS U5453 ( .A(n4834), .B(n3377), .S0(n3023), .Y(n6460) );
NAND2X2TS U5454 ( .A(n2756), .B(n6004), .Y(n5324) );
AOI22X2TS U5455 ( .A0(n2673), .A1(n5619), .B0(n5603), .B1(n5620), .Y(n5606)
);
AOI21X2TS U5456 ( .A0(n2753), .A1(n5712), .B0(n5711), .Y(n5713) );
AOI21X4TS U5457 ( .A0(n3056), .A1(n4456), .B0(n4455), .Y(n3161) );
OAI2BB1X4TS U5458 ( .A0N(n2705), .A1N(n3162), .B0(n2654), .Y(n3963) );
NAND3X2TS U5459 ( .A(n5000), .B(n4999), .C(n4998), .Y(n1473) );
CLKINVX12TS U5460 ( .A(n3490), .Y(n3209) );
AOI21X2TS U5461 ( .A0(n4342), .A1(n3280), .B0(n1964), .Y(n4068) );
NAND2X4TS U5462 ( .A(n4367), .B(n4366), .Y(n5971) );
AOI21X4TS U5463 ( .A0(n4084), .A1(n4376), .B0(n4095), .Y(n3168) );
NAND2BX4TS U5464 ( .AN(n4078), .B(n3175), .Y(n3174) );
AND2X8TS U5465 ( .A(n5953), .B(n4537), .Y(n4787) );
OAI21X4TS U5466 ( .A0(n4471), .A1(n4457), .B0(n4458), .Y(n4362) );
NOR2X8TS U5467 ( .A(n3347), .B(n4276), .Y(n4457) );
NOR2X8TS U5468 ( .A(n4541), .B(n2083), .Y(n3609) );
NAND2X8TS U5469 ( .A(n3183), .B(n3182), .Y(n3181) );
NAND2X8TS U5470 ( .A(n5069), .B(n1637), .Y(n5074) );
NAND2BX4TS U5471 ( .AN(n3190), .B(n5070), .Y(n5075) );
NAND2X8TS U5472 ( .A(n4587), .B(n6223), .Y(n3194) );
NAND3X8TS U5473 ( .A(n6285), .B(n6286), .C(n6284), .Y(n5995) );
NAND3X8TS U5474 ( .A(n6279), .B(n6280), .C(n6278), .Y(n6002) );
AOI2BB2X4TS U5475 ( .B0(n3195), .B1(n3200), .A0N(n2634), .A1N(n3201), .Y(
n3199) );
NAND2X2TS U5476 ( .A(n3221), .B(n3634), .Y(n3635) );
AOI21X4TS U5477 ( .A0(n5694), .A1(n4431), .B0(n4430), .Y(n4436) );
NAND2X2TS U5478 ( .A(n2379), .B(n2334), .Y(n3821) );
NOR2X8TS U5479 ( .A(n3972), .B(n2065), .Y(n3227) );
NAND2X2TS U5480 ( .A(n3146), .B(n4355), .Y(n4356) );
OR2X2TS U5481 ( .A(n2832), .B(n6537), .Y(n5007) );
NAND2X2TS U5482 ( .A(n3638), .B(n3228), .Y(n3639) );
NAND2X8TS U5483 ( .A(n3469), .B(n4104), .Y(n5943) );
NOR2X8TS U5484 ( .A(n2552), .B(n3208), .Y(n4254) );
OAI21X4TS U5485 ( .A0(n3695), .A1(n3694), .B0(n3693), .Y(n3696) );
OR2X2TS U5486 ( .A(n5055), .B(n6242), .Y(n5013) );
MXI2X4TS U5487 ( .A(n4955), .B(n6222), .S0(n6063), .Y(n1509) );
NAND2X2TS U5488 ( .A(n2222), .B(n2331), .Y(n3758) );
OR2X2TS U5489 ( .A(n5055), .B(n6243), .Y(n5022) );
OAI2BB1X4TS U5490 ( .A0N(n2663), .A1N(n5710), .B0(n5020), .Y(n1455) );
OAI2BB1X4TS U5491 ( .A0N(n2664), .A1N(n5705), .B0(n5029), .Y(n1454) );
INVX12TS U5492 ( .A(n3620), .Y(n3972) );
NAND2X8TS U5493 ( .A(n2669), .B(n1913), .Y(n3620) );
XOR2X2TS U5494 ( .A(n2424), .B(n6042), .Y(n6048) );
MXI2X2TS U5495 ( .A(n6049), .B(n6238), .S0(n6405), .Y(n1505) );
NOR2X2TS U5496 ( .A(n2443), .B(n6537), .Y(n4941) );
NOR2X8TS U5497 ( .A(n3214), .B(n3391), .Y(n4006) );
NAND2X2TS U5498 ( .A(n2390), .B(n2399), .Y(n3709) );
AOI22X2TS U5499 ( .A0(n5663), .A1(n5591), .B0(n5595), .B1(n2698), .Y(n5383)
);
OR2X2TS U5500 ( .A(n5055), .B(n6249), .Y(n3533) );
OAI21X4TS U5501 ( .A0(n2472), .A1(n2535), .B0(n2487), .Y(n4481) );
NAND2X8TS U5502 ( .A(n4032), .B(n2619), .Y(n5940) );
MXI2X4TS U5503 ( .A(n5220), .B(n6212), .S0(n6405), .Y(n1512) );
OAI21X4TS U5504 ( .A0(n5215), .A1(n5214), .B0(n5213), .Y(n5217) );
NAND2X2TS U5505 ( .A(n4485), .B(n4081), .Y(n3591) );
INVX2TS U5506 ( .A(n4551), .Y(n5958) );
OAI2BB1X4TS U5507 ( .A0N(n2568), .A1N(n1770), .B0(n4205), .Y(n4858) );
AOI21X4TS U5508 ( .A0(n3056), .A1(n4689), .B0(n3219), .Y(n4691) );
NAND2X4TS U5509 ( .A(n5514), .B(Add_Subt_result[12]), .Y(n5519) );
NOR2X8TS U5510 ( .A(n3976), .B(n3975), .Y(n4614) );
INVX2TS U5511 ( .A(n5940), .Y(n3220) );
AOI21X4TS U5512 ( .A0(n3049), .A1(n5941), .B0(n3220), .Y(n4638) );
NAND2X2TS U5513 ( .A(n4757), .B(n4763), .Y(n4528) );
NAND2X2TS U5514 ( .A(n3620), .B(n2065), .Y(n3621) );
NOR2X8TS U5515 ( .A(n3238), .B(n4372), .Y(n4024) );
NAND3X2TS U5516 ( .A(n5228), .B(n5227), .C(n5226), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[50]) );
AOI22X2TS U5517 ( .A0(n2677), .A1(n5573), .B0(n5572), .B1(n5670), .Y(n5574)
);
AOI21X4TS U5518 ( .A0(n1609), .A1(n4612), .B0(n3226), .Y(n4616) );
NAND4X2TS U5519 ( .A(n4167), .B(n4168), .C(n4166), .D(n4165), .Y(n4169) );
AOI22X2TS U5520 ( .A0(n5662), .A1(n5671), .B0(n2887), .B1(n5656), .Y(n5527)
);
NAND2X2TS U5521 ( .A(n5516), .B(n5992), .Y(n5511) );
BUFX3TS U5522 ( .A(n5109), .Y(n3231) );
NAND2X2TS U5523 ( .A(n2236), .B(n2665), .Y(n3693) );
NAND2BX4TS U5524 ( .AN(n4844), .B(n4843), .Y(n3245) );
OAI21X4TS U5525 ( .A0(n4040), .A1(n2482), .B0(n3649), .Y(n4438) );
MXI2X8TS U5526 ( .A(n2350), .B(n1611), .S0(n3394), .Y(n4279) );
NAND2X4TS U5527 ( .A(n3793), .B(n3850), .Y(n3808) );
INVX2TS U5528 ( .A(n6008), .Y(n4482) );
NAND2X8TS U5529 ( .A(n3233), .B(n3210), .Y(n4862) );
NAND2X2TS U5530 ( .A(n2195), .B(n2321), .Y(n3867) );
MXI2X4TS U5531 ( .A(n4929), .B(n4928), .S0(n2762), .Y(n4930) );
OR2X8TS U5532 ( .A(n3376), .B(n3377), .Y(n3549) );
INVX2TS U5533 ( .A(n4651), .Y(n4653) );
NAND2X4TS U5534 ( .A(n5781), .B(n5780), .Y(n5787) );
NOR2X8TS U5535 ( .A(n2276), .B(n2682), .Y(n3916) );
MXI2X4TS U5536 ( .A(n4939), .B(n6221), .S0(n6405), .Y(n1508) );
INVX2TS U5537 ( .A(n4444), .Y(n4445) );
OAI21X4TS U5538 ( .A0(n3848), .A1(n3847), .B0(n3846), .Y(n3849) );
NOR2X8TS U5539 ( .A(n4281), .B(n4650), .Y(n4283) );
XOR2X4TS U5540 ( .A(n4418), .B(n4417), .Y(n4426) );
MXI2X4TS U5541 ( .A(n4426), .B(n4425), .S0(n2762), .Y(n6534) );
NAND2X2TS U5542 ( .A(n2206), .B(n2336), .Y(n3855) );
OAI21X2TS U5543 ( .A0(n4799), .A1(n4798), .B0(n4797), .Y(n4800) );
XNOR2X4TS U5544 ( .A(n4707), .B(n4706), .Y(n6403) );
BUFX20TS U5545 ( .A(n4043), .Y(n5136) );
AOI2BB2X4TS U5546 ( .B0(n4084), .B1(n1658), .A0N(n4575), .A1N(n4076), .Y(
n4493) );
NAND2X2TS U5547 ( .A(n2218), .B(n2382), .Y(n3748) );
NAND2X2TS U5548 ( .A(n5061), .B(n5060), .Y(n1457) );
NAND2X2TS U5549 ( .A(n5118), .B(n5117), .Y(n1462) );
NAND2X2TS U5550 ( .A(n5128), .B(n5127), .Y(n1461) );
NAND2X2TS U5551 ( .A(n5147), .B(n5146), .Y(n1460) );
NAND2X2TS U5552 ( .A(n5156), .B(n5155), .Y(n1458) );
OAI21X4TS U5553 ( .A0(n3242), .A1(n3878), .B0(n3297), .Y(n3296) );
OAI21X4TS U5554 ( .A0(n3243), .A1(n3828), .B0(n3827), .Y(n3851) );
AOI21X4TS U5555 ( .A0(n3817), .A1(n3816), .B0(n3815), .Y(n3243) );
OAI21X4TS U5556 ( .A0(n1621), .A1(n3716), .B0(n3715), .Y(n3722) );
NOR2X8TS U5557 ( .A(n4279), .B(n4268), .Y(n4655) );
NAND2X4TS U5558 ( .A(n6296), .B(n6297), .Y(n3274) );
NAND2X4TS U5559 ( .A(n5945), .B(n5960), .Y(n6503) );
NOR2X4TS U5560 ( .A(n4695), .B(n4063), .Y(n4062) );
AOI2BB1X4TS U5561 ( .A0N(n2104), .A1N(n4632), .B0(n3245), .Y(n3481) );
NAND2X2TS U5562 ( .A(n2385), .B(n2343), .Y(n3818) );
NAND2X4TS U5563 ( .A(n5953), .B(n5958), .Y(n4552) );
MXI2X2TS U5564 ( .A(n4963), .B(n6257), .S0(n6405), .Y(n1511) );
NAND2X2TS U5565 ( .A(n4958), .B(n5213), .Y(n4960) );
NAND2X2TS U5566 ( .A(n5962), .B(n5966), .Y(n5968) );
NAND2X2TS U5567 ( .A(n2250), .B(n2311), .Y(n3831) );
OAI21X4TS U5568 ( .A0(n3833), .A1(n3832), .B0(n3831), .Y(n3834) );
NAND2X4TS U5569 ( .A(n3578), .B(n3547), .Y(n3548) );
NAND2X2TS U5570 ( .A(n5047), .B(n5046), .Y(n1459) );
NAND2X2TS U5571 ( .A(n5142), .B(n5141), .Y(n1463) );
NAND2X4TS U5572 ( .A(n3460), .B(n2749), .Y(n6465) );
MXI2X4TS U5573 ( .A(n4468), .B(n4467), .S0(n6060), .Y(n4469) );
NAND2X4TS U5574 ( .A(n4731), .B(n4644), .Y(n4646) );
AOI22X2TS U5575 ( .A0(n2675), .A1(n5477), .B0(n2504), .B1(n5663), .Y(n5481)
);
BUFX8TS U5576 ( .A(n6031), .Y(n6036) );
OAI21X4TS U5577 ( .A0(n3249), .A1(n4194), .B0(n4193), .Y(n1167) );
BUFX6TS U5578 ( .A(n5994), .Y(n3250) );
AOI21X4TS U5579 ( .A0(n3573), .A1(n4574), .B0(n3572), .Y(n3577) );
NOR3X2TS U5580 ( .A(n3567), .B(n5998), .C(n3250), .Y(n3568) );
AOI21X4TS U5581 ( .A0(n3056), .A1(n4677), .B0(n4676), .Y(n4680) );
NAND2X4TS U5582 ( .A(n5975), .B(n2715), .Y(n6012) );
NOR2X2TS U5583 ( .A(n4904), .B(n4903), .Y(n4905) );
INVX2TS U5584 ( .A(n4023), .Y(n4393) );
XNOR2X4TS U5585 ( .A(n3253), .B(n4832), .Y(n4834) );
XNOR2X4TS U5586 ( .A(n3254), .B(n5186), .Y(n5187) );
AO21X4TS U5587 ( .A0(n2297), .A1(n5185), .B0(n5184), .Y(n3254) );
NAND2X4TS U5588 ( .A(n2731), .B(n1590), .Y(n5287) );
NOR2X8TS U5589 ( .A(n2284), .B(n4036), .Y(n4008) );
NAND3X2TS U5590 ( .A(n5175), .B(n5174), .C(n5173), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[51]) );
NAND2X2TS U5591 ( .A(n4990), .B(n4989), .Y(n1448) );
NOR2X8TS U5592 ( .A(n5154), .B(n3252), .Y(n5697) );
NAND2X2TS U5593 ( .A(n2451), .B(n1659), .Y(n3610) );
OAI21X4TS U5594 ( .A0(n4845), .A1(n4838), .B0(n4837), .Y(n3258) );
AOI21X4TS U5595 ( .A0(n4674), .A1(n1919), .B0(n4293), .Y(n4295) );
AOI21X4TS U5596 ( .A0(n2716), .A1(n4807), .B0(n2705), .Y(n4811) );
NAND4X2TS U5597 ( .A(n5540), .B(n5539), .C(n5538), .D(n5537), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
NOR2X8TS U5598 ( .A(n4747), .B(n4363), .Y(n4364) );
AOI22X2TS U5599 ( .A0(n5102), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n5101), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n5063) );
BUFX20TS U5600 ( .A(n2629), .Y(n3395) );
OR2X8TS U5601 ( .A(n5932), .B(n3411), .Y(n3264) );
XNOR2X4TS U5602 ( .A(n3266), .B(n4369), .Y(n4370) );
NAND2X4TS U5603 ( .A(n3356), .B(n2748), .Y(n6480) );
NOR4X2TS U5604 ( .A(n6003), .B(n6000), .C(n5997), .D(n6006), .Y(n3583) );
OAI21X4TS U5605 ( .A0(n3775), .A1(n3774), .B0(n3773), .Y(n3776) );
NAND2X4TS U5606 ( .A(n4568), .B(n4793), .Y(n6470) );
OAI21X4TS U5607 ( .A0(n4845), .A1(n4765), .B0(n4766), .Y(n4767) );
NOR2X4TS U5608 ( .A(n3794), .B(n3854), .Y(n3796) );
NAND3BX4TS U5609 ( .AN(n2640), .B(n5106), .C(n5105), .Y(n5715) );
NAND2X2TS U5610 ( .A(n5709), .B(n5708), .Y(n1484) );
NAND2X4TS U5611 ( .A(n4794), .B(n4793), .Y(n6482) );
NOR2X8TS U5612 ( .A(n2452), .B(n4614), .Y(n4612) );
NAND2X2TS U5613 ( .A(n2611), .B(n2356), .Y(n3707) );
OR2X2TS U5614 ( .A(n2832), .B(n6246), .Y(n3517) );
NAND2X8TS U5615 ( .A(n4708), .B(n4033), .Y(n4103) );
NOR2X4TS U5616 ( .A(n4747), .B(n2198), .Y(n4472) );
NAND3X4TS U5617 ( .A(n4089), .B(n6223), .C(n6212), .Y(n3555) );
OAI21X2TS U5618 ( .A0(n6007), .A1(n5914), .B0(n5913), .Y(n5915) );
AOI21X4TS U5619 ( .A0(n1825), .A1(n4383), .B0(n4382), .Y(n4384) );
NAND2BX4TS U5620 ( .AN(n3274), .B(n6298), .Y(n5989) );
XOR2X4TS U5621 ( .A(n3439), .B(n5936), .Y(n5939) );
BUFX12TS U5622 ( .A(n4793), .Y(n5960) );
XOR2X2TS U5623 ( .A(n2472), .B(n2494), .Y(n6399) );
AOI21X4TS U5624 ( .A0(n3415), .A1(n3941), .B0(n3278), .Y(n3277) );
OAI21X4TS U5625 ( .A0(n3417), .A1(n4795), .B0(n4798), .Y(n3278) );
OAI21X4TS U5626 ( .A0(n4346), .A1(n4345), .B0(n2548), .Y(n3283) );
NAND3BX4TS U5627 ( .AN(n5703), .B(n3287), .C(n3286), .Y(n1487) );
OAI2BB1X4TS U5628 ( .A0N(n3288), .A1N(n3292), .B0(n5780), .Y(n3287) );
NAND2X8TS U5629 ( .A(n3527), .B(n3949), .Y(n3528) );
AOI21X4TS U5630 ( .A0(n3300), .A1(n2074), .B0(n3296), .Y(n3880) );
OAI21X4TS U5631 ( .A0(n3869), .A1(n3868), .B0(n3867), .Y(n3299) );
OAI21X4TS U5632 ( .A0(n3864), .A1(n3863), .B0(n3862), .Y(n3301) );
OAI21X4TS U5633 ( .A0(n3861), .A1(n3860), .B0(n3859), .Y(n3302) );
AOI21X4TS U5634 ( .A0(n3305), .A1(n3858), .B0(n3304), .Y(n3303) );
OAI21X4TS U5635 ( .A0(n3853), .A1(n3854), .B0(n3852), .Y(n3305) );
NOR2X8TS U5636 ( .A(n3308), .B(n3307), .Y(n3306) );
AOI21X4TS U5637 ( .A0(n3049), .A1(n3431), .B0(n4739), .Y(n3393) );
NOR2X8TS U5638 ( .A(n4103), .B(n4106), .Y(n4398) );
NOR2X8TS U5639 ( .A(n3638), .B(n3228), .Y(n3640) );
AOI21X4TS U5640 ( .A0(n3049), .A1(n4768), .B0(n4767), .Y(n3316) );
OAI21X4TS U5641 ( .A0(n4827), .A1(n3238), .B0(n4830), .Y(n4030) );
NAND2X8TS U5642 ( .A(n2559), .B(n3326), .Y(n4585) );
NOR2X8TS U5643 ( .A(n3330), .B(n3332), .Y(n5340) );
NOR2X8TS U5644 ( .A(n3334), .B(n1620), .Y(n5336) );
AOI21X4TS U5645 ( .A0(n1754), .A1(n3343), .B0(n5916), .Y(n3335) );
NOR2BX4TS U5646 ( .AN(n3605), .B(n3339), .Y(n3338) );
OAI2BB1X4TS U5647 ( .A0N(n3603), .A1N(n3604), .B0(n5920), .Y(n3341) );
NAND2X8TS U5648 ( .A(n3435), .B(n3345), .Y(n4792) );
NAND2X8TS U5649 ( .A(n4500), .B(n2656), .Y(n3346) );
NOR2X8TS U5650 ( .A(n4297), .B(n3347), .Y(n4299) );
AOI21X4TS U5651 ( .A0(n1754), .A1(n3350), .B0(n3349), .Y(n3348) );
NAND2X8TS U5652 ( .A(n3361), .B(n3360), .Y(n4081) );
AND2X2TS U5653 ( .A(n5912), .B(n3362), .Y(n4095) );
NOR2BX4TS U5654 ( .AN(n3363), .B(n3152), .Y(n3362) );
AOI21X4TS U5655 ( .A0(n3056), .A1(n4669), .B0(n4668), .Y(n4671) );
OAI2BB1X4TS U5656 ( .A0N(n3366), .A1N(n3365), .B0(n4287), .Y(n4674) );
AOI21X4TS U5657 ( .A0(n2644), .A1(n4035), .B0(n4034), .Y(n3370) );
MXI2X8TS U5658 ( .A(n1899), .B(n6225), .S0(n3395), .Y(n4288) );
NOR2X8TS U5659 ( .A(n3374), .B(n1654), .Y(n4627) );
NOR2X8TS U5660 ( .A(n4277), .B(n4266), .Y(n4723) );
NAND2X8TS U5661 ( .A(n4265), .B(n4032), .Y(n5934) );
NOR2BX4TS U5662 ( .AN(n2647), .B(n3558), .Y(n5916) );
INVX12TS U5663 ( .A(n4833), .Y(n3377) );
XOR2X4TS U5664 ( .A(n3382), .B(n2478), .Y(n3381) );
OAI21X4TS U5665 ( .A0(n3439), .A1(n4399), .B0(n5956), .Y(n3382) );
NOR2X8TS U5666 ( .A(n3386), .B(n3385), .Y(n3384) );
OAI21X4TS U5667 ( .A0(n3439), .A1(n4727), .B0(n2476), .Y(n3389) );
NOR2X8TS U5668 ( .A(n4005), .B(n4006), .Y(n4432) );
XOR2X4TS U5669 ( .A(n3393), .B(n4742), .Y(n4743) );
INVX6TS U5670 ( .A(n3407), .Y(n3398) );
NAND2X4TS U5671 ( .A(n3607), .B(n1829), .Y(n4816) );
AOI21X4TS U5672 ( .A0(n2952), .A1(n4317), .B0(n4316), .Y(n4319) );
NAND2X4TS U5673 ( .A(n3421), .B(n2749), .Y(n6522) );
NAND2X2TS U5674 ( .A(n5571), .B(n5414), .Y(n5403) );
NOR2X2TS U5675 ( .A(n3252), .B(n5258), .Y(n5259) );
AOI21X2TS U5676 ( .A0(n4553), .A1(n5958), .B0(n4554), .Y(n4555) );
NAND2X8TS U5677 ( .A(n3369), .B(n4255), .Y(n4340) );
AOI21X4TS U5678 ( .A0(n1941), .A1(n4736), .B0(n4735), .Y(n4737) );
OR2X8TS U5679 ( .A(n1644), .B(n4852), .Y(n4853) );
XOR2X4TS U5680 ( .A(n3416), .B(n2569), .Y(n3414) );
NAND3X8TS U5681 ( .A(n5832), .B(n5863), .C(n3420), .Y(n3419) );
AND2X8TS U5682 ( .A(n4500), .B(n2519), .Y(n5953) );
NOR2BX4TS U5683 ( .AN(n4851), .B(n2554), .Y(n3432) );
MX2X6TS U5684 ( .A(n1895), .B(n6214), .S0(n2865), .Y(n3434) );
NOR2X8TS U5685 ( .A(n3450), .B(n3449), .Y(n3448) );
NOR2X8TS U5686 ( .A(n4361), .B(n4365), .Y(n4107) );
NAND2BX4TS U5687 ( .AN(n2198), .B(n4111), .Y(n3455) );
NOR2BX4TS U5688 ( .AN(n4645), .B(n3462), .Y(n3461) );
AND2X8TS U5689 ( .A(n4855), .B(n3479), .Y(n3465) );
NOR2X8TS U5690 ( .A(n4004), .B(n1839), .Y(n4199) );
OAI21X4TS U5691 ( .A0(n3480), .A1(n3023), .B0(n3478), .Y(n1562) );
NAND2BX4TS U5692 ( .AN(n3492), .B(n4378), .Y(n4450) );
INVX2TS U5693 ( .A(n3493), .Y(n3492) );
XOR2X4TS U5694 ( .A(n3897), .B(n3896), .Y(n3915) );
XOR2X4TS U5695 ( .A(n5207), .B(n4959), .Y(n4962) );
XOR2X4TS U5696 ( .A(n3913), .B(n3912), .Y(n3914) );
NAND4BX4TS U5697 ( .AN(n3596), .B(n3595), .C(n3605), .D(n3594), .Y(n4496) );
NAND4X2TS U5698 ( .A(n5302), .B(n5301), .C(n5300), .D(n5299), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
NAND2X4TS U5699 ( .A(n4587), .B(n3600), .Y(n3601) );
NAND2X4TS U5700 ( .A(n5514), .B(Add_Subt_result[14]), .Y(n5372) );
NAND2X4TS U5701 ( .A(n2725), .B(n5291), .Y(n5267) );
NAND2X4TS U5702 ( .A(n2725), .B(n5991), .Y(n5327) );
NAND2X4TS U5703 ( .A(n5510), .B(Add_Subt_result[10]), .Y(n5499) );
NAND2X4TS U5704 ( .A(n5645), .B(n5984), .Y(n5513) );
NAND2X4TS U5705 ( .A(n5514), .B(n1590), .Y(n5271) );
BUFX20TS U5706 ( .A(n5697), .Y(n5780) );
NAND4X2TS U5707 ( .A(n5607), .B(n5604), .C(n5606), .D(n5605), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[35]) );
NAND2X4TS U5708 ( .A(n5645), .B(Add_Subt_result[8]), .Y(n5509) );
NAND2X4TS U5709 ( .A(n5514), .B(Add_Subt_result[7]), .Y(n5505) );
NAND2X4TS U5710 ( .A(n5645), .B(Add_Subt_result[9]), .Y(n5502) );
OAI21X4TS U5711 ( .A0(n3882), .A1(n3881), .B0(n3880), .Y(n3883) );
NAND4X2TS U5712 ( .A(n5524), .B(n5526), .C(n5525), .D(n5527), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI21X4TS U5713 ( .A0(n3836), .A1(n3835), .B0(n3834), .Y(n3848) );
BUFX20TS U5714 ( .A(n5282), .Y(n5434) );
AOI21X2TS U5715 ( .A0(n2497), .A1(n2799), .B0(n4937), .Y(n4938) );
AOI21X2TS U5716 ( .A0(n4485), .A1(n1664), .B0(n4584), .Y(n4495) );
NAND3X4TS U5717 ( .A(n5026), .B(n5025), .C(n5024), .Y(n5705) );
NAND2X4TS U5718 ( .A(n2725), .B(n1835), .Y(n5339) );
NOR2X8TS U5719 ( .A(n4008), .B(n4009), .Y(n4372) );
NAND4X2TS U5720 ( .A(n5353), .B(n5351), .C(n5352), .D(n5354), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
XNOR2X2TS U5721 ( .A(n4933), .B(n4926), .Y(n4929) );
AOI21X2TS U5722 ( .A0(n4933), .A1(n3013), .B0(n4932), .Y(n4935) );
AOI22X2TS U5723 ( .A0(n2741), .A1(n2241), .B0(n2300), .B1(n5777), .Y(n5759)
);
MX2X4TS U5724 ( .A(n5930), .B(exp_oper_result[5]), .S0(n6406), .Y(n1433) );
NAND2X4TS U5725 ( .A(n2725), .B(n5406), .Y(n5409) );
XNOR2X4TS U5726 ( .A(n4466), .B(n4465), .Y(n4467) );
XOR2X2TS U5727 ( .A(n4424), .B(n4423), .Y(n4425) );
NOR2X2TS U5728 ( .A(n6027), .B(n6026), .Y(n6029) );
NAND3X2TS U5729 ( .A(n6025), .B(n6024), .C(n6023), .Y(n6027) );
NOR2X2TS U5730 ( .A(n4993), .B(n4941), .Y(n4945) );
OAI21X4TS U5731 ( .A0(n3701), .A1(n3700), .B0(n3699), .Y(n3728) );
NOR2X8TS U5732 ( .A(n3782), .B(n3833), .Y(n3835) );
AOI22X2TS U5733 ( .A0(n5760), .A1(n2391), .B0(DmP[49]), .B1(n5807), .Y(n5826) );
NOR2X8TS U5734 ( .A(n2240), .B(n2367), .Y(n3746) );
NAND2X4TS U5735 ( .A(n2240), .B(n2367), .Y(n3744) );
BUFX20TS U5736 ( .A(n4043), .Y(n5150) );
NOR2X8TS U5737 ( .A(n4083), .B(n3591), .Y(n4084) );
AOI21X4TS U5738 ( .A0(n3005), .A1(n1694), .B0(n4445), .Y(n4446) );
NOR2X4TS U5739 ( .A(n4695), .B(n4693), .Y(n4440) );
NOR2X4TS U5740 ( .A(n3828), .B(n3792), .Y(n3793) );
NAND2X4TS U5741 ( .A(n3791), .B(n3816), .Y(n3792) );
XNOR2X4TS U5742 ( .A(n4245), .B(n4244), .Y(n4247) );
NOR2X4TS U5743 ( .A(n2175), .B(n2289), .Y(n3804) );
XNOR2X4TS U5744 ( .A(n2174), .B(n2289), .Y(n4185) );
NAND2X4TS U5745 ( .A(n5054), .B(n3680), .Y(n5765) );
NOR2X2TS U5746 ( .A(n2252), .B(n2265), .Y(n3801) );
NOR2X8TS U5747 ( .A(n2244), .B(n2397), .Y(n3864) );
AOI22X2TS U5748 ( .A0(n5104), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2724), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[62]), .Y(n5062) );
NOR2X8TS U5749 ( .A(n2433), .B(n2626), .Y(n3692) );
MXI2X4TS U5750 ( .A(n4469), .B(n6254), .S0(n6063), .Y(n1513) );
NAND4BX2TS U5751 ( .AN(n5904), .B(n5903), .C(n5902), .D(n5901), .Y(n1481) );
NAND2X4TS U5752 ( .A(n4897), .B(n4876), .Y(n4902) );
NAND4X2TS U5753 ( .A(n4184), .B(n4183), .C(n4182), .D(n4181), .Y(n4189) );
NOR2X8TS U5754 ( .A(n1649), .B(n3584), .Y(n4586) );
NAND3X4TS U5755 ( .A(n4588), .B(n4590), .C(n3583), .Y(n3584) );
NOR2X4TS U5756 ( .A(n2128), .B(n2225), .Y(n3797) );
NAND2X4TS U5757 ( .A(n2128), .B(n2225), .Y(n3860) );
AO21X4TS U5758 ( .A0(n4802), .A1(n4801), .B0(n4800), .Y(n4803) );
NAND2X2TS U5759 ( .A(n4977), .B(n4976), .Y(n1447) );
NAND2X2TS U5760 ( .A(n4981), .B(n4980), .Y(n1446) );
NAND2X2TS U5761 ( .A(n4968), .B(n4967), .Y(n1445) );
AOI21X4TS U5762 ( .A0(n2297), .A1(n1642), .B0(n4197), .Y(n5178) );
NAND2X4TS U5763 ( .A(n4344), .B(n4343), .Y(n4346) );
NAND2X4TS U5764 ( .A(n5514), .B(n1675), .Y(n5437) );
NAND4X2TS U5765 ( .A(n5489), .B(n5488), .C(n5490), .D(n5487), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[36]) );
NAND4X2TS U5766 ( .A(n5600), .B(n5599), .C(n5598), .D(n5597), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[28]) );
MXI2X2TS U5767 ( .A(n5863), .B(n6211), .S0(n6406), .Y(n1437) );
NAND4X2TS U5768 ( .A(n5328), .B(n5330), .C(n5329), .D(n5331), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[34]) );
AOI21X4TS U5769 ( .A0(n2952), .A1(n4230), .B0(n4229), .Y(n4233) );
NAND4X2TS U5770 ( .A(n5463), .B(n5462), .C(n5461), .D(n5460), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[44]) );
NAND2X4TS U5771 ( .A(n5973), .B(n2748), .Y(n6492) );
NOR2X4TS U5772 ( .A(n4795), .B(n4799), .Y(n4801) );
NOR2X2TS U5773 ( .A(n4427), .B(n2483), .Y(n4431) );
NAND2X4TS U5774 ( .A(n5693), .B(n2067), .Y(n4427) );
AOI21X2TS U5775 ( .A0(n5694), .A1(n4253), .B0(n2953), .Y(n4042) );
AO21X4TS U5776 ( .A0(n2952), .A1(n5693), .B0(n3237), .Y(n5696) );
NAND2X2TS U5777 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n5069) );
NAND4X2TS U5778 ( .A(n5041), .B(n5040), .C(n5890), .D(n5039), .Y(n1467) );
AOI21X4TS U5779 ( .A0(n3826), .A1(n3825), .B0(n3824), .Y(n3827) );
NOR2X8TS U5780 ( .A(n4640), .B(n4519), .Y(n4520) );
NOR2X4TS U5781 ( .A(n2394), .B(n2309), .Y(n3782) );
NOR2X8TS U5782 ( .A(n2123), .B(n2376), .Y(n3814) );
INVX2TS U5783 ( .A(n4799), .Y(n3943) );
OR2X4TS U5784 ( .A(n2832), .B(n6245), .Y(n5001) );
INVX4TS U5785 ( .A(n6012), .Y(n4877) );
NAND4X2TS U5786 ( .A(n5445), .B(n5444), .C(n5443), .D(n5442), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[46]) );
NOR2X4TS U5787 ( .A(n3724), .B(n3706), .Y(n3727) );
NAND4X2TS U5788 ( .A(n5441), .B(n5438), .C(n5440), .D(n5439), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[45]) );
NAND4X2TS U5789 ( .A(n5402), .B(n5404), .C(n5403), .D(n5405), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
NAND2X4TS U5790 ( .A(n1662), .B(n2059), .Y(n4415) );
NOR2X4TS U5791 ( .A(Add_Subt_result[8]), .B(Add_Subt_result[7]), .Y(n3553)
);
NAND4X2TS U5792 ( .A(n5237), .B(n5235), .C(n5236), .D(n5234), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[49]) );
NAND4X2TS U5793 ( .A(n5577), .B(n5576), .C(n5575), .D(n5574), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
NAND4X2TS U5794 ( .A(n5457), .B(n5458), .C(n5456), .D(n5459), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[40]) );
NAND4X2TS U5795 ( .A(n5588), .B(n5587), .C(n5586), .D(n5585), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[39]) );
NAND4X2TS U5796 ( .A(n5467), .B(n5466), .C(n5464), .D(n5465), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[38]) );
NAND4X2TS U5797 ( .A(n5626), .B(n5624), .C(n5623), .D(n5625), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[37]) );
NAND4X2TS U5798 ( .A(n5475), .B(n5474), .C(n5472), .D(n5473), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[32]) );
NAND4X2TS U5799 ( .A(n5483), .B(n5486), .C(n5484), .D(n5485), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[29]) );
NAND4X2TS U5800 ( .A(n5562), .B(n5565), .C(n5563), .D(n5564), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
NAND4X2TS U5801 ( .A(n5387), .B(n5389), .C(n5388), .D(n5390), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
NAND4X2TS U5802 ( .A(n5381), .B(n5380), .C(n5379), .D(n5378), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
NAND4X2TS U5803 ( .A(n5531), .B(n5528), .C(n5529), .D(n5530), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
NAND4X2TS U5804 ( .A(n5553), .B(n5552), .C(n5551), .D(n5550), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
NAND4X2TS U5805 ( .A(n5546), .B(n5547), .C(n5548), .D(n5549), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[31]) );
NAND4X2TS U5806 ( .A(n5520), .B(n5522), .C(n5523), .D(n5521), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
NAND4X2TS U5807 ( .A(n5400), .B(n5399), .C(n5397), .D(n5398), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[27]) );
NAND4X2TS U5808 ( .A(n5420), .B(n5419), .C(n5418), .D(n5417), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
NAND4X2TS U5809 ( .A(n5393), .B(n5394), .C(n5395), .D(n5392), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
NAND4X2TS U5810 ( .A(n5369), .B(n5368), .C(n5367), .D(n5366), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
NAND4X2TS U5811 ( .A(n5479), .B(n5480), .C(n5481), .D(n5482), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[47]) );
NAND4X2TS U5812 ( .A(n5247), .B(n5246), .C(n5245), .D(n5244), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[48]) );
NAND4X2TS U5813 ( .A(n5471), .B(n5469), .C(n5470), .D(n5468), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[42]) );
NAND4X2TS U5814 ( .A(n5614), .B(n5611), .C(n5612), .D(n5613), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[41]) );
NAND4X2TS U5815 ( .A(n5580), .B(n5582), .C(n5581), .D(n5583), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[43]) );
NAND4X2TS U5816 ( .A(n5278), .B(n5279), .C(n5280), .D(n5277), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[26]) );
AOI21X4TS U5817 ( .A0(n3697), .A1(n3698), .B0(n3696), .Y(n3699) );
AOI21X4TS U5818 ( .A0(n3850), .A1(n3851), .B0(n3849), .Y(n3882) );
NOR2X6TS U5819 ( .A(n4526), .B(n4535), .Y(n4624) );
NAND4X2TS U5820 ( .A(n5412), .B(n5410), .C(n5413), .D(n5411), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
OAI21X2TS U5821 ( .A0(n1831), .A1(n4738), .B0(n4737), .Y(n4739) );
NAND2X4TS U5822 ( .A(n5158), .B(n5157), .Y(n6051) );
MXI2X2TS U5823 ( .A(n5179), .B(n5344), .S0(n6038), .Y(n6528) );
XOR2X4TS U5824 ( .A(n5178), .B(n5695), .Y(n5179) );
NAND2X6TS U5825 ( .A(n3248), .B(n5364), .Y(n5238) );
INVX16TS U5826 ( .A(n5274), .Y(n5282) );
NAND2X4TS U5827 ( .A(n5510), .B(n1658), .Y(n5298) );
NOR2X8TS U5828 ( .A(n4673), .B(n4292), .Y(n4294) );
NAND4X4TS U5829 ( .A(n5051), .B(n5050), .C(n5049), .D(n5048), .Y(n5896) );
NAND2X2TS U5830 ( .A(n5148), .B(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n5050) );
NAND2X2TS U5831 ( .A(n4475), .B(n4478), .Y(n4363) );
AOI21X4TS U5832 ( .A0(n3722), .A1(n2112), .B0(n3720), .Y(n3723) );
NOR2X8TS U5833 ( .A(n2757), .B(n6230), .Y(n4003) );
OAI21X4TS U5834 ( .A0(n4652), .A1(n4281), .B0(n4280), .Y(n4282) );
AOI21X4TS U5835 ( .A0(n3777), .A1(n3778), .B0(n3776), .Y(n3779) );
XOR2X4TS U5836 ( .A(n4357), .B(n4356), .Y(Exp_Operation_Module_Data_S_8_) );
NOR2X4TS U5837 ( .A(n2159), .B(n2156), .Y(n3729) );
NAND2X4TS U5838 ( .A(n2159), .B(n2156), .Y(n3745) );
NAND2X2TS U5839 ( .A(n5707), .B(n3231), .Y(n5105) );
NAND4BX2TS U5840 ( .AN(n2573), .B(n4594), .C(n4593), .D(n4592), .Y(n4595) );
OAI21X2TS U5841 ( .A0(n4682), .A1(n4667), .B0(n4666), .Y(n4668) );
NOR2X4TS U5842 ( .A(n3940), .B(n4795), .Y(n3941) );
AOI21X4TS U5843 ( .A0(n3844), .A1(n3845), .B0(n3843), .Y(n3846) );
OAI21X4TS U5844 ( .A0(n3725), .A1(n3724), .B0(n3723), .Y(n3726) );
OAI21X4TS U5845 ( .A0(n3952), .A1(n3951), .B0(n2828), .Y(n3956) );
AOI22X2TS U5846 ( .A0(n5514), .A1(Add_Subt_result[1]), .B0(n5985), .B1(n2746), .Y(n5678) );
XNOR2X4TS U5847 ( .A(n4865), .B(n4209), .Y(n4210) );
NOR2X4TS U5848 ( .A(n3820), .B(n3787), .Y(n3788) );
OAI21X2TS U5849 ( .A0(n4688), .A1(n2032), .B0(n4675), .Y(n4676) );
XNOR2X4TS U5850 ( .A(n4464), .B(n4463), .Y(n4468) );
NAND2X2TS U5851 ( .A(n1701), .B(n4895), .Y(n4900) );
INVX16TS U5852 ( .A(n4890), .Y(n6033) );
NAND3X4TS U5853 ( .A(n3927), .B(n3257), .C(DmP[56]), .Y(n3928) );
XNOR2X4TS U5854 ( .A(n3961), .B(n3960), .Y(n5974) );
NOR2X2TS U5855 ( .A(n2428), .B(n6226), .Y(n4543) );
NOR2X4TS U5856 ( .A(n2096), .B(n2401), .Y(n3790) );
NAND4X2TS U5857 ( .A(n5068), .B(n5067), .C(n5890), .D(n5066), .Y(n1471) );
OAI21X4TS U5858 ( .A0(n3781), .A1(n3780), .B0(n3779), .Y(n3885) );
AOI21X4TS U5859 ( .A0(n3728), .A1(n3727), .B0(n3726), .Y(n3781) );
NOR2X8TS U5860 ( .A(n4518), .B(n4517), .Y(n4740) );
AOI21X4TS U5861 ( .A0(n3752), .A1(n3751), .B0(n3750), .Y(n3753) );
NAND2X4TS U5862 ( .A(n4274), .B(n4302), .Y(n4366) );
INVX16TS U5863 ( .A(n5229), .Y(n5679) );
AND2X8TS U5864 ( .A(n5242), .B(n5221), .Y(n5229) );
NAND2X4TS U5865 ( .A(n2381), .B(n2232), .Y(n3694) );
AOI21X4TS U5866 ( .A0(n3771), .A1(n3772), .B0(n3770), .Y(n3773) );
NOR2X8TS U5867 ( .A(n2757), .B(n1868), .Y(n4005) );
NAND2X2TS U5868 ( .A(n2175), .B(n2289), .Y(n3873) );
NOR2X8TS U5869 ( .A(n1943), .B(n2200), .Y(n3874) );
NAND2X6TS U5870 ( .A(n3938), .B(n3937), .Y(n4798) );
NOR2X4TS U5871 ( .A(n3789), .B(n3811), .Y(n3791) );
NOR2X2TS U5872 ( .A(n2179), .B(n2182), .Y(n3789) );
INVX8TS U5873 ( .A(n4502), .Y(n4510) );
NAND2X2TS U5874 ( .A(n4511), .B(n4512), .Y(n4513) );
NOR2X8TS U5875 ( .A(n4562), .B(n4539), .Y(n4847) );
OAI2BB1X2TS U5876 ( .A0N(n4590), .A1N(n3571), .B0(n4090), .Y(n3572) );
NAND4X4TS U5877 ( .A(n4985), .B(n4984), .C(n4991), .D(n4983), .Y(n5893) );
NAND4X4TS U5878 ( .A(n3534), .B(n4991), .C(n3533), .D(n3532), .Y(n5145) );
NAND2X8TS U5879 ( .A(n4507), .B(n4520), .Y(n4835) );
NAND2X2TS U5880 ( .A(n2394), .B(n2309), .Y(n3832) );
NAND2X4TS U5881 ( .A(n5510), .B(n5938), .Y(n5264) );
NOR2X4TS U5882 ( .A(n2218), .B(n2382), .Y(n3730) );
NAND2X4TS U5883 ( .A(n1824), .B(n4064), .Y(n4329) );
NAND2X4TS U5884 ( .A(n2118), .B(n2119), .Y(n3710) );
NAND2X4TS U5885 ( .A(n1661), .B(n1931), .Y(n3924) );
NOR2X4TS U5886 ( .A(n3732), .B(n3742), .Y(n3733) );
NOR2X4TS U5887 ( .A(n4399), .B(n4498), .Y(n4499) );
NOR2X4TS U5888 ( .A(n6005), .B(n5995), .Y(n3541) );
NAND2X8TS U5889 ( .A(n2882), .B(n3523), .Y(n4982) );
NAND2X4TS U5890 ( .A(n3935), .B(n3934), .Y(n4355) );
NAND2X2TS U5891 ( .A(n3642), .B(n1981), .Y(n3643) );
AOI22X2TS U5892 ( .A0(n5736), .A1(n2363), .B0(n2416), .B1(n5735), .Y(n5734)
);
AOI22X2TS U5893 ( .A0(n2740), .A1(n2616), .B0(n1893), .B1(n5842), .Y(n5726)
);
AOI22X2TS U5894 ( .A0(n5736), .A1(n2160), .B0(n2409), .B1(n1645), .Y(n5724)
);
AOI22X2TS U5895 ( .A0(n2740), .A1(n2071), .B0(n1894), .B1(n5777), .Y(n5779)
);
AOI22X2TS U5896 ( .A0(n5736), .A1(n2093), .B0(n2413), .B1(n5807), .Y(n5776)
);
AOI22X2TS U5897 ( .A0(n5736), .A1(n2205), .B0(n2407), .B1(n5820), .Y(n5773)
);
BUFX20TS U5898 ( .A(n3521), .Y(n5109) );
NAND2X8TS U5899 ( .A(n2883), .B(n3522), .Y(n3512) );
AOI22X2TS U5900 ( .A0(n5860), .A1(n2227), .B0(n2328), .B1(n5859), .Y(n5852)
);
AOI22X2TS U5901 ( .A0(n5860), .A1(n2158), .B0(n2324), .B1(n5859), .Y(n5861)
);
AOI22X2TS U5902 ( .A0(n5860), .A1(n2078), .B0(n2326), .B1(n5859), .Y(n5857)
);
AOI22X2TS U5903 ( .A0(n5860), .A1(n2097), .B0(n2330), .B1(n5859), .Y(n5763)
);
AOI22X2TS U5904 ( .A0(n5736), .A1(n2235), .B0(n2417), .B1(n5735), .Y(n5737)
);
NAND4X4TS U5905 ( .A(n3655), .B(n3654), .C(n4991), .D(n3653), .Y(n5126) );
NAND4X4TS U5906 ( .A(n3518), .B(n3517), .C(n4991), .D(n3516), .Y(n5887) );
NOR2X8TS U5907 ( .A(n2757), .B(n2147), .Y(n4061) );
NAND2X4TS U5908 ( .A(n4515), .B(n4505), .Y(n4748) );
NAND3X8TS U5909 ( .A(n5347), .B(n5346), .C(n5345), .Y(n5568) );
NOR3X2TS U5910 ( .A(n4874), .B(n4873), .C(n4872), .Y(n4897) );
OAI2BB2X1TS U5911 ( .B0(n2107), .B1(Sgf_normalized_result[0]), .A0N(
r_mode[0]), .A1N(r_mode[1]), .Y(n4872) );
BUFX20TS U5912 ( .A(n5810), .Y(n5856) );
NOR2X2TS U5913 ( .A(n5947), .B(n1736), .Y(n5950) );
NAND4X4TS U5914 ( .A(n3671), .B(n3670), .C(n4991), .D(n3669), .Y(n5116) );
NAND2X2TS U5915 ( .A(n3668), .B(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(n3669) );
NAND3X4TS U5916 ( .A(n5059), .B(n5028), .C(n5027), .Y(n5707) );
NAND3X4TS U5917 ( .A(n5059), .B(n5019), .C(n5018), .Y(n5712) );
NAND3X4TS U5918 ( .A(n5059), .B(n5023), .C(n5022), .Y(n5717) );
NOR2X4TS U5919 ( .A(n3582), .B(n5998), .Y(n4588) );
NOR2X8TS U5920 ( .A(n1656), .B(n3898), .Y(n6043) );
NAND3X8TS U5921 ( .A(n5298), .B(n5297), .C(n5296), .Y(n5567) );
NAND2X4TS U5922 ( .A(n2731), .B(n5938), .Y(n5296) );
NAND4X2TS U5923 ( .A(n5535), .B(n5536), .C(n5533), .D(n5534), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
NAND4X2TS U5924 ( .A(n5638), .B(n5637), .C(n5636), .D(n5635), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
NAND4X2TS U5925 ( .A(n5542), .B(n5544), .C(n5543), .D(n5545), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
XOR2X4TS U5926 ( .A(n3948), .B(n3952), .Y(n4359) );
XNOR2X4TS U5927 ( .A(n3956), .B(n3955), .Y(n4358) );
NAND2X4TS U5928 ( .A(n4343), .B(n3280), .Y(n4063) );
NOR2X4TS U5929 ( .A(n2366), .B(n2099), .Y(n3787) );
NOR2X8TS U5930 ( .A(n4192), .B(n3230), .Y(n5030) );
NAND4X2TS U5931 ( .A(n5664), .B(n5666), .C(n5665), .D(n5667), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
NAND4X2TS U5932 ( .A(n5658), .B(n5659), .C(n5660), .D(n5657), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
NAND4BX2TS U5933 ( .AN(n5691), .B(n5690), .C(n5689), .D(n2068), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND3X8TS U5934 ( .A(n5433), .B(n5432), .C(n5431), .Y(n5609) );
NAND3X6TS U5935 ( .A(n5241), .B(n5240), .C(n5239), .Y(n5608) );
NAND3X6TS U5936 ( .A(n5455), .B(n5454), .C(n5453), .Y(n5622) );
NAND3X8TS U5937 ( .A(n5437), .B(n5436), .C(n5435), .Y(n5610) );
NOR2X8TS U5938 ( .A(n4663), .B(n4296), .Y(n4507) );
NAND2X4TS U5939 ( .A(n5641), .B(n5640), .Y(n5681) );
OAI21X2TS U5940 ( .A0(n4734), .A1(n4733), .B0(n4732), .Y(n4735) );
NAND2X4TS U5941 ( .A(n3909), .B(n3908), .Y(n4242) );
MXI2X4TS U5942 ( .A(n2414), .B(n6209), .S0(n4542), .Y(n3932) );
BUFX20TS U5943 ( .A(n5030), .Y(n5795) );
NAND3X8TS U5944 ( .A(n6310), .B(n6309), .C(n6308), .Y(n5993) );
NOR2X4TS U5945 ( .A(n4695), .B(n4328), .Y(n4327) );
NAND2X4TS U5946 ( .A(n4343), .B(n4331), .Y(n4328) );
INVX2TS U5947 ( .A(n4807), .Y(n3962) );
NOR2X8TS U5948 ( .A(n5406), .B(Add_Subt_result[10]), .Y(n4089) );
NOR2X8TS U5949 ( .A(n4036), .B(n1959), .Y(n4269) );
NOR2X4TS U5950 ( .A(n4535), .B(n4534), .Y(n4551) );
NOR2X8TS U5951 ( .A(Add_Subt_result[12]), .B(n5984), .Y(n4099) );
MXI2X8TS U5952 ( .A(n6331), .B(n6330), .S0(n6329), .Y(n5984) );
NOR2X2TS U5953 ( .A(n4664), .B(n4667), .Y(n4669) );
INVX2TS U5954 ( .A(n4683), .Y(n4664) );
AND2X4TS U5955 ( .A(n2671), .B(n2210), .Y(n4505) );
NOR2X2TS U5956 ( .A(n4687), .B(n2032), .Y(n4677) );
NAND3X8TS U5957 ( .A(n5495), .B(n5494), .C(n5493), .Y(n5682) );
NAND2X4TS U5958 ( .A(n2725), .B(Add_Subt_result[5]), .Y(n5495) );
NOR2X8TS U5959 ( .A(n3938), .B(n3937), .Y(n4795) );
XOR2X4TS U5960 ( .A(n3998), .B(n3997), .Y(n4812) );
NOR2X8TS U5961 ( .A(n5109), .B(n3512), .Y(n3663) );
NAND3X8TS U5962 ( .A(n6325), .B(n6324), .C(n6323), .Y(n6001) );
BUFX20TS U5963 ( .A(n5103), .Y(n5083) );
OAI21X4TS U5964 ( .A0(n4354), .A1(n4352), .B0(n4355), .Y(n4802) );
NAND3X6TS U5965 ( .A(n5317), .B(n5316), .C(n5315), .Y(n5601) );
NAND4X2TS U5966 ( .A(n5333), .B(n5334), .C(n5332), .D(n5335), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[33]) );
NAND4X2TS U5967 ( .A(n5554), .B(n5556), .C(n5555), .D(n5557), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[30]) );
NAND3X6TS U5968 ( .A(n5314), .B(n5313), .C(n5312), .Y(n5615) );
NAND3X8TS U5969 ( .A(n5294), .B(n5293), .C(n5292), .Y(n5573) );
NAND4X2TS U5970 ( .A(n5677), .B(n5676), .C(n5675), .D(n5674), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
NAND4X2TS U5971 ( .A(n2214), .B(n5385), .C(n5384), .D(n5383), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
NAND3X6TS U5972 ( .A(n5372), .B(n5371), .C(n5370), .Y(n5632) );
NAND3X8TS U5973 ( .A(n6307), .B(n6306), .C(n6305), .Y(n6000) );
NAND3X8TS U5974 ( .A(n6322), .B(n6321), .C(n6320), .Y(n6008) );
NOR2X6TS U5975 ( .A(n2428), .B(n3099), .Y(n3900) );
XOR2X4TS U5976 ( .A(n4811), .B(n4810), .Y(n5930) );
MXI2X8TS U5977 ( .A(n6328), .B(n6327), .S0(n6326), .Y(n5406) );
OR2X2TS U5978 ( .A(n5993), .B(n5992), .Y(n3495) );
INVX2TS U5979 ( .A(n4670), .Y(n4038) );
XNOR2X4TS U5980 ( .A(n3648), .B(n3647), .Y(n3496) );
XNOR2X4TS U5981 ( .A(n4351), .B(n4350), .Y(n3497) );
INVX2TS U5982 ( .A(n2449), .Y(n4234) );
NAND2X1TS U5983 ( .A(n6058), .B(n6057), .Y(n3507) );
INVX2TS U5984 ( .A(n2234), .Y(n4682) );
INVX2TS U5985 ( .A(n3239), .Y(n4213) );
INVX2TS U5986 ( .A(n4263), .Y(n4342) );
INVX2TS U5987 ( .A(ack_FSM), .Y(n4892) );
INVX2TS U5988 ( .A(n3989), .Y(n3990) );
INVX2TS U5989 ( .A(Data_Y[7]), .Y(n6197) );
INVX2TS U5990 ( .A(Data_Y[21]), .Y(n6181) );
INVX2TS U5991 ( .A(Data_Y[35]), .Y(n6166) );
INVX2TS U5992 ( .A(Data_Y[49]), .Y(n6149) );
INVX2TS U5993 ( .A(Data_X[63]), .Y(n6066) );
INVX2TS U5994 ( .A(Data_X[26]), .Y(n6106) );
INVX2TS U5995 ( .A(Data_X[40]), .Y(n6091) );
INVX2TS U5996 ( .A(Data_X[53]), .Y(n6077) );
OR2X1TS U5997 ( .A(n4982), .B(n6240), .Y(n3518) );
NAND2X6TS U5998 ( .A(n3519), .B(n2009), .Y(n3925) );
NAND2X2TS U5999 ( .A(n4969), .B(n5194), .Y(n3531) );
NOR2X8TS U6000 ( .A(n5282), .B(n5154), .Y(n5139) );
NAND2X1TS U6001 ( .A(n5784), .B(Sgf_normalized_result[53]), .Y(n3529) );
OR2X1TS U6002 ( .A(n4982), .B(n6243), .Y(n3534) );
INVX4TS U6003 ( .A(n5406), .Y(n6536) );
INVX2TS U6004 ( .A(n4099), .Y(n3552) );
NAND4X1TS U6005 ( .A(n3557), .B(n4585), .C(Add_Subt_result[15]), .D(n1818),
.Y(n3558) );
NOR2X8TS U6006 ( .A(n3560), .B(n3559), .Y(n3581) );
NOR2X1TS U6007 ( .A(n6003), .B(n5997), .Y(n4589) );
NOR2X1TS U6008 ( .A(n5919), .B(n5336), .Y(n3604) );
INVX2TS U6009 ( .A(n4483), .Y(n3585) );
NAND2X1TS U6010 ( .A(n3585), .B(n4577), .Y(n3586) );
NOR2X1TS U6011 ( .A(Add_Subt_result[2]), .B(Add_Subt_result[1]), .Y(n4488)
);
INVX2TS U6012 ( .A(n3592), .Y(n3593) );
NOR2X1TS U6015 ( .A(Add_Subt_result[16]), .B(Add_Subt_result[14]), .Y(n3603)
);
NOR2X8TS U6016 ( .A(n2668), .B(n2426), .Y(n3975) );
INVX2TS U6017 ( .A(n4342), .Y(n3630) );
INVX2TS U6018 ( .A(n4573), .Y(n3647) );
INVX2TS U6019 ( .A(n2025), .Y(n3650) );
NAND2X2TS U6020 ( .A(n3650), .B(n3649), .Y(n3651) );
NAND2X1TS U6021 ( .A(n5140), .B(Sgf_normalized_result[51]), .Y(n3659) );
OAI2BB1X1TS U6022 ( .A0N(n1833), .A1N(n5895), .B0(n5890), .Y(n3674) );
NAND2X1TS U6023 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n3666) );
NAND2X1TS U6024 ( .A(n5114), .B(n5885), .Y(n3673) );
OR2X1TS U6025 ( .A(n4982), .B(n6241), .Y(n3671) );
NAND2X1TS U6026 ( .A(n5116), .B(n5899), .Y(n3672) );
OAI2BB1X1TS U6027 ( .A0N(n1991), .A1N(n5895), .B0(n3675), .Y(n3687) );
NAND4X4TS U6028 ( .A(n3679), .B(n3678), .C(n3677), .D(n3676), .Y(n5120) );
NAND2X1TS U6029 ( .A(n5119), .B(n5194), .Y(n3685) );
AOI21X4TS U6030 ( .A0(n3885), .A1(n3884), .B0(n3883), .Y(n3886) );
INVX2TS U6031 ( .A(n3061), .Y(n3891) );
INVX2TS U6032 ( .A(n3893), .Y(n3895) );
NAND2X1TS U6033 ( .A(n3894), .B(n3895), .Y(n3896) );
OAI21X4TS U6034 ( .A0(n5215), .A1(n4208), .B0(n2634), .Y(n4245) );
INVX2TS U6035 ( .A(n4242), .Y(n3910) );
NAND2X1TS U6036 ( .A(n1651), .B(n3970), .Y(n3912) );
XNOR2X4TS U6037 ( .A(intDY[63]), .B(intAS), .Y(n4194) );
XOR2X4TS U6038 ( .A(n4194), .B(n6233), .Y(n6018) );
AND2X2TS U6039 ( .A(n1661), .B(DmP[62]), .Y(n3942) );
NAND2X2TS U6040 ( .A(n1701), .B(n6022), .Y(n3991) );
NAND2X4TS U6041 ( .A(n3976), .B(n3975), .Y(n4613) );
AOI21X4TS U6042 ( .A0(n1801), .A1(n3984), .B0(n3983), .Y(n3987) );
MXI2X4TS U6043 ( .A(n3988), .B(n5348), .S0(n6009), .Y(n6532) );
OR2X2TS U6044 ( .A(n1844), .B(n2513), .Y(n3996) );
INVX2TS U6045 ( .A(n4007), .Y(n4015) );
INVX2TS U6046 ( .A(n4392), .Y(n4013) );
AOI21X1TS U6047 ( .A0(n1853), .A1(n4393), .B0(n4013), .Y(n4014) );
OAI2BB1X4TS U6048 ( .A0N(n4016), .A1N(n4015), .B0(n4014), .Y(n4017) );
INVX2TS U6049 ( .A(n4028), .Y(n4020) );
MXI2X4TS U6050 ( .A(n4022), .B(n4021), .S0(n3023), .Y(n6455) );
CLKINVX1TS U6051 ( .A(n1581), .Y(n4215) );
NAND2X1TS U6052 ( .A(n4037), .B(n4104), .Y(n4670) );
AND2X8TS U6053 ( .A(n4248), .B(n5988), .Y(n4793) );
NAND2X4TS U6054 ( .A(n4039), .B(n5952), .Y(n6506) );
NAND2X2TS U6055 ( .A(n2466), .B(n1977), .Y(n4041) );
OAI2BB1X1TS U6056 ( .A0N(n1610), .A1N(n5895), .B0(n5890), .Y(n4051) );
NAND2X1TS U6057 ( .A(n2739), .B(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n4047) );
NAND2X1TS U6058 ( .A(n5150), .B(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n4044) );
NAND4X4TS U6059 ( .A(n4047), .B(n4046), .C(n4045), .D(n4044), .Y(n5125) );
NAND2X1TS U6060 ( .A(n5126), .B(n5899), .Y(n4048) );
NAND4BX2TS U6061 ( .AN(n4051), .B(n4050), .C(n4049), .D(n4048), .Y(n1477) );
OAI2BB1X1TS U6062 ( .A0N(n1958), .A1N(n5895), .B0(n5890), .Y(n4059) );
NAND2X1TS U6063 ( .A(n2739), .B(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(n4055) );
NAND2X1TS U6064 ( .A(n5149), .B(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n4053) );
NAND2X1TS U6065 ( .A(n5150), .B(
Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(n4052) );
NAND2X1TS U6066 ( .A(n5143), .B(n5885), .Y(n4057) );
NAND4BX2TS U6067 ( .AN(n4059), .B(n4058), .C(n4057), .D(n4056), .Y(n1478) );
OAI2BB1X4TS U6068 ( .A0N(n2953), .A1N(n4069), .B0(n4068), .Y(n4070) );
INVX2TS U6069 ( .A(n4450), .Y(n4073) );
XNOR2X4TS U6070 ( .A(n4074), .B(n4073), .Y(n6402) );
NAND3X1TS U6071 ( .A(n4483), .B(n1590), .C(n4577), .Y(n4076) );
OAI21XLTS U6072 ( .A0(n6004), .A1(n5993), .B0(n4077), .Y(n4078) );
NAND2X1TS U6073 ( .A(n4081), .B(n5258), .Y(n4082) );
AOI21X1TS U6074 ( .A0(n4085), .A1(n4833), .B0(n4394), .Y(n4086) );
OAI21X1TS U6075 ( .A0(Add_Subt_result[8]), .A1(n6236), .B0(n6212), .Y(n4088)
);
NAND3X1TS U6076 ( .A(n4092), .B(n4091), .C(n1606), .Y(n4093) );
OAI21X1TS U6077 ( .A0(Add_Subt_result[10]), .A1(Add_Subt_result[8]), .B0(
n4099), .Y(n4100) );
INVX2TS U6078 ( .A(n4402), .Y(n4108) );
INVX2TS U6079 ( .A(n4401), .Y(n4109) );
NAND2X2TS U6080 ( .A(n4109), .B(n4400), .Y(n4648) );
NAND2X4TS U6081 ( .A(n4110), .B(n4793), .Y(n6464) );
NAND2X2TS U6082 ( .A(n4470), .B(n2085), .Y(n4602) );
XNOR2X1TS U6083 ( .A(n2071), .B(n2391), .Y(n4116) );
XNOR2X1TS U6084 ( .A(n2378), .B(n2334), .Y(n4115) );
XNOR2X1TS U6085 ( .A(n2384), .B(n2343), .Y(n4113) );
NAND4X1TS U6086 ( .A(n4116), .B(n4115), .C(n4114), .D(n4113), .Y(n4132) );
XNOR2X1TS U6087 ( .A(n2241), .B(n2354), .Y(n4120) );
NAND4X1TS U6088 ( .A(n4120), .B(n4119), .C(n4118), .D(n4117), .Y(n4131) );
XNOR2X1TS U6089 ( .A(n2095), .B(n2401), .Y(n4124) );
XNOR2X1TS U6090 ( .A(n2149), .B(n2172), .Y(n4123) );
NAND4X1TS U6091 ( .A(n4124), .B(n4123), .C(n4122), .D(n4121), .Y(n4130) );
XNOR2X1TS U6092 ( .A(n1869), .B(n2080), .Y(n4128) );
XNOR2X1TS U6093 ( .A(n2249), .B(n2311), .Y(n4127) );
XNOR2X1TS U6094 ( .A(n2151), .B(n2361), .Y(n4126) );
XNOR2X1TS U6095 ( .A(n2109), .B(n2320), .Y(n4125) );
NAND4X1TS U6096 ( .A(n4128), .B(n4127), .C(n4126), .D(n4125), .Y(n4129) );
XNOR2X1TS U6097 ( .A(n2393), .B(n2309), .Y(n4136) );
XNOR2X1TS U6098 ( .A(n2217), .B(n2382), .Y(n4134) );
XNOR2X1TS U6099 ( .A(n2227), .B(n2192), .Y(n4133) );
NAND4X1TS U6100 ( .A(n4136), .B(n4135), .C(n4134), .D(n4133), .Y(n4152) );
XNOR2X1TS U6101 ( .A(n2078), .B(n1854), .Y(n4140) );
XNOR2X1TS U6102 ( .A(n2136), .B(n2635), .Y(n4139) );
XNOR2X1TS U6103 ( .A(n2374), .B(n2255), .Y(n4138) );
NAND4X1TS U6104 ( .A(n4140), .B(n4139), .C(n4138), .D(n4137), .Y(n4151) );
XNOR2X1TS U6105 ( .A(n1735), .B(n2304), .Y(n4143) );
XNOR2X1TS U6106 ( .A(n2434), .B(n2293), .Y(n4141) );
NAND4X1TS U6107 ( .A(n4144), .B(n4143), .C(n4142), .D(n4141), .Y(n4150) );
XNOR2X1TS U6108 ( .A(n2105), .B(n2313), .Y(n4147) );
XNOR2X1TS U6109 ( .A(n2221), .B(n2331), .Y(n4145) );
NAND4X1TS U6110 ( .A(n4148), .B(n4147), .C(n4146), .D(n4145), .Y(n4149) );
XNOR2X1TS U6111 ( .A(n2245), .B(n2102), .Y(n4156) );
XNOR2X1TS U6112 ( .A(n2380), .B(n2232), .Y(n4154) );
XNOR2X1TS U6113 ( .A(n2235), .B(n2665), .Y(n4153) );
NAND4X1TS U6114 ( .A(n4156), .B(n4155), .C(n4154), .D(n4153), .Y(n4172) );
XNOR2X1TS U6115 ( .A(n2202), .B(n2387), .Y(n4160) );
XNOR2X1TS U6116 ( .A(n2160), .B(n2447), .Y(n4159) );
XNOR2X1TS U6117 ( .A(n2660), .B(n2636), .Y(n4157) );
NAND4X1TS U6118 ( .A(n4160), .B(n4159), .C(n4158), .D(n4157), .Y(n4171) );
XNOR2X1TS U6119 ( .A(n2041), .B(n2403), .Y(n4163) );
XNOR2X1TS U6120 ( .A(n2060), .B(n2291), .Y(n4162) );
XNOR2X1TS U6121 ( .A(n2369), .B(n2287), .Y(n4161) );
NAND4X1TS U6122 ( .A(n4164), .B(n4163), .C(n4162), .D(n4161), .Y(n4170) );
XNOR2X1TS U6123 ( .A(n2363), .B(n2263), .Y(n4168) );
XNOR2X1TS U6124 ( .A(n2117), .B(n2119), .Y(n4166) );
XNOR2X1TS U6125 ( .A(n2389), .B(n2399), .Y(n4165) );
XNOR2X1TS U6126 ( .A(n1942), .B(n2200), .Y(n4176) );
XNOR2X1TS U6127 ( .A(n2093), .B(n2223), .Y(n4174) );
XNOR2X1TS U6128 ( .A(n2251), .B(n2265), .Y(n4173) );
NAND4X1TS U6129 ( .A(n4176), .B(n4175), .C(n4174), .D(n4173), .Y(n4191) );
NAND4X1TS U6130 ( .A(n4180), .B(n4179), .C(n4178), .D(n4177), .Y(n4190) );
XNOR2X1TS U6131 ( .A(n2162), .B(n2257), .Y(n4183) );
XNOR2X1TS U6132 ( .A(n2205), .B(n2336), .Y(n4182) );
XNOR2X1TS U6133 ( .A(n2190), .B(n2439), .Y(n4181) );
XNOR2X1TS U6134 ( .A(n2063), .B(n1872), .Y(n4187) );
XNOR2X1TS U6135 ( .A(n1848), .B(n2087), .Y(n4186) );
NAND3X1TS U6136 ( .A(n4187), .B(n4186), .C(n4185), .Y(n4188) );
AOI21X4TS U6137 ( .A0(n3061), .A1(n4202), .B0(n2027), .Y(n4205) );
INVX2TS U6138 ( .A(n2522), .Y(n4864) );
NAND2X1TS U6139 ( .A(n4864), .B(n4862), .Y(n4209) );
MXI2X4TS U6140 ( .A(n4211), .B(n4210), .S0(n6060), .Y(n4212) );
NAND2X2TS U6141 ( .A(n4215), .B(n4214), .Y(n4684) );
INVX2TS U6142 ( .A(n4222), .Y(n4224) );
NAND2X2TS U6143 ( .A(n4224), .B(n4223), .Y(n5186) );
INVX2TS U6144 ( .A(n5186), .Y(n4225) );
INVX2TS U6145 ( .A(n1920), .Y(n4229) );
INVX2TS U6146 ( .A(n4614), .Y(n4231) );
NAND2X2TS U6147 ( .A(n4231), .B(n4613), .Y(n4621) );
INVX2TS U6148 ( .A(n4621), .Y(n4232) );
NAND2X2TS U6149 ( .A(n5182), .B(n5180), .Y(n4615) );
INVX2TS U6150 ( .A(n4615), .Y(n4237) );
NOR2X2TS U6151 ( .A(n5963), .B(n1728), .Y(n4309) );
OAI21X4TS U6152 ( .A0(n4665), .A1(n4296), .B0(n4295), .Y(n4521) );
NAND2X1TS U6153 ( .A(n4310), .B(n4402), .Y(n4369) );
OAI21X2TS U6154 ( .A0(n5692), .A1(n1672), .B0(n4315), .Y(n4316) );
AOI21X4TS U6155 ( .A0(n3237), .A1(n2067), .B0(n2066), .Y(n4429) );
INVX2TS U6156 ( .A(n4328), .Y(n4332) );
INVX2TS U6157 ( .A(n4329), .Y(n4330) );
INVX2TS U6158 ( .A(n4333), .Y(n4335) );
INVX2TS U6159 ( .A(n4782), .Y(n4336) );
CLKINVX1TS U6160 ( .A(n4337), .Y(n4338) );
INVX2TS U6161 ( .A(n4388), .Y(n4350) );
CLKINVX1TS U6162 ( .A(n4365), .Y(n4367) );
NAND2X4TS U6163 ( .A(n4370), .B(n5960), .Y(n6515) );
NAND2X2TS U6164 ( .A(n1598), .B(n4825), .Y(n4373) );
XOR2X4TS U6165 ( .A(n4374), .B(n4373), .Y(n4377) );
OAI21X2TS U6166 ( .A0(n4026), .A1(n4385), .B0(n4384), .Y(n4386) );
AOI21X4TS U6167 ( .A0(n1801), .A1(n4387), .B0(n4386), .Y(n4389) );
XOR2X4TS U6168 ( .A(n4389), .B(n4388), .Y(n4390) );
MXI2X4TS U6169 ( .A(n4390), .B(n1817), .S0(n6009), .Y(n6527) );
CLKINVX1TS U6170 ( .A(n4408), .Y(n4409) );
INVX2TS U6171 ( .A(n4410), .Y(n4413) );
INVX2TS U6172 ( .A(n4411), .Y(n4412) );
AOI21X2TS U6173 ( .A0(n4464), .A1(n4413), .B0(n4412), .Y(n4418) );
INVX2TS U6174 ( .A(n4414), .Y(n4416) );
INVX2TS U6175 ( .A(n4423), .Y(n4417) );
INVX2TS U6176 ( .A(n4461), .Y(n4422) );
INVX2TS U6177 ( .A(n4432), .Y(n4434) );
NAND2X2TS U6178 ( .A(n4434), .B(n4433), .Y(n4610) );
INVX2TS U6179 ( .A(n4610), .Y(n4435) );
XOR2X4TS U6180 ( .A(n4451), .B(n4450), .Y(n4452) );
INVX2TS U6181 ( .A(n4457), .Y(n4459) );
NAND2X1TS U6182 ( .A(n4459), .B(n4458), .Y(n4473) );
NAND2X4TS U6183 ( .A(n4460), .B(n6400), .Y(n6501) );
CLKINVX1TS U6184 ( .A(n4475), .Y(n4476) );
NAND2X4TS U6185 ( .A(n4501), .B(n4793), .Y(n6476) );
INVX2TS U6186 ( .A(n4762), .Y(n4527) );
INVX2TS U6187 ( .A(n4627), .Y(n4530) );
NAND2X4TS U6188 ( .A(n4544), .B(n4793), .Y(n6473) );
NAND2X4TS U6189 ( .A(n4550), .B(n5960), .Y(n6509) );
INVX2TS U6190 ( .A(n5957), .Y(n4554) );
INVX2TS U6191 ( .A(n4558), .Y(n4560) );
NAND2X1TS U6192 ( .A(n4560), .B(n4559), .Y(n4561) );
NAND2X1TS U6193 ( .A(n5937), .B(n1817), .Y(n4576) );
NAND3X1TS U6194 ( .A(n4591), .B(n4590), .C(n4589), .Y(n4592) );
INVX2TS U6195 ( .A(n4602), .Y(n4603) );
NAND2X4TS U6196 ( .A(n4604), .B(n2749), .Y(n6468) );
XOR2X4TS U6197 ( .A(n4616), .B(n4615), .Y(n4617) );
INVX2TS U6198 ( .A(n4618), .Y(n4619) );
XOR2X4TS U6199 ( .A(n4622), .B(n4621), .Y(n4623) );
MXI2X2TS U6200 ( .A(n4623), .B(n5919), .S0(n6063), .Y(n6530) );
INVX2TS U6201 ( .A(n4633), .Y(n5941) );
NAND2X2TS U6202 ( .A(n4636), .B(n4635), .Y(n4637) );
XOR2X4TS U6203 ( .A(n4638), .B(n4637), .Y(n4639) );
NAND2X4TS U6204 ( .A(n4639), .B(n2747), .Y(n6454) );
CLKINVX6TS U6205 ( .A(n4640), .Y(n4731) );
INVX2TS U6206 ( .A(n4641), .Y(n4644) );
NOR2X1TS U6207 ( .A(n5963), .B(n4646), .Y(n4647) );
INVX2TS U6208 ( .A(n4642), .Y(n4643) );
CLKINVX1TS U6209 ( .A(n4650), .Y(n4651) );
NAND2X4TS U6210 ( .A(n4660), .B(n1641), .Y(n6525) );
NAND2X4TS U6211 ( .A(n4662), .B(n2748), .Y(n6489) );
INVX2TS U6212 ( .A(n2564), .Y(n4667) );
XOR2X4TS U6213 ( .A(n4671), .B(n4038), .Y(n4672) );
NAND2X4TS U6214 ( .A(n4672), .B(n2733), .Y(n6507) );
AOI21X4TS U6215 ( .A0(n2234), .A1(n1630), .B0(n2646), .Y(n4688) );
XOR2X4TS U6216 ( .A(n4680), .B(n5951), .Y(n4681) );
NAND2X4TS U6217 ( .A(n4681), .B(n2749), .Y(n6513) );
XOR2X4TS U6218 ( .A(n4685), .B(n2710), .Y(n4686) );
NAND2X4TS U6219 ( .A(n4686), .B(n2749), .Y(n6519) );
XOR2X4TS U6220 ( .A(n4691), .B(n2498), .Y(n4692) );
NAND2X4TS U6221 ( .A(n4692), .B(n2748), .Y(n6504) );
CLKINVX1TS U6222 ( .A(n4694), .Y(n4698) );
OAI21X2TS U6223 ( .A0(n4702), .A1(n4701), .B0(n4700), .Y(n4703) );
INVX2TS U6224 ( .A(n4705), .Y(n4706) );
NAND2X4TS U6225 ( .A(n4714), .B(n5960), .Y(n6521) );
OAI21X2TS U6226 ( .A0(n1831), .A1(n4718), .B0(n4717), .Y(n4719) );
NAND2X4TS U6227 ( .A(n4722), .B(n2748), .Y(n6510) );
INVX2TS U6228 ( .A(n4740), .Y(n4741) );
NAND2X4TS U6229 ( .A(n4743), .B(n2747), .Y(n6495) );
NAND2X4TS U6230 ( .A(n4756), .B(n5952), .Y(n6494) );
INVX2TS U6231 ( .A(n4769), .Y(n4770) );
NAND2X4TS U6232 ( .A(n4772), .B(n2749), .Y(n6477) );
INVX2TS U6233 ( .A(n4774), .Y(n4779) );
OAI2BB1X4TS U6234 ( .A0N(n4016), .A1N(n4779), .B0(n4778), .Y(n4780) );
AOI21X4TS U6235 ( .A0(n1801), .A1(n4781), .B0(n4780), .Y(n4783) );
NAND2X4TS U6236 ( .A(n4786), .B(n2747), .Y(n6471) );
INVX2TS U6237 ( .A(n1673), .Y(n4804) );
NAND2X1TS U6238 ( .A(n3042), .B(n4819), .Y(n4823) );
INVX2TS U6239 ( .A(n4823), .Y(n4820) );
INVX2TS U6240 ( .A(n3238), .Y(n4831) );
NOR2BX4TS U6241 ( .AN(n4661), .B(n4838), .Y(n4839) );
NAND2X4TS U6242 ( .A(n4847), .B(n4849), .Y(n4852) );
CLKINVX1TS U6243 ( .A(n3227), .Y(n4860) );
INVX2TS U6244 ( .A(n4866), .Y(n4861) );
INVX2TS U6245 ( .A(n4862), .Y(n4863) );
MXI2X1TS U6246 ( .A(n3256), .B(n1950), .S0(n5927), .Y(n4878) );
OAI21X4TS U6247 ( .A0(n6397), .A1(n6396), .B0(n6395), .Y(overflow_flag) );
INVX2TS U6248 ( .A(Data_Y[4]), .Y(n4881) );
MXI2X1TS U6249 ( .A(n4881), .B(n2231), .S0(n2719), .Y(n1236) );
INVX2TS U6250 ( .A(Data_Y[3]), .Y(n4882) );
MXI2X2TS U6251 ( .A(n4882), .B(n2818), .S0(n6086), .Y(n1235) );
INVX2TS U6252 ( .A(Data_Y[2]), .Y(n4883) );
MXI2X1TS U6253 ( .A(n4883), .B(n2437), .S0(n6119), .Y(n1234) );
INVX2TS U6254 ( .A(Data_Y[1]), .Y(n4884) );
MXI2X1TS U6255 ( .A(n4884), .B(n2440), .S0(n6097), .Y(n1233) );
INVX2TS U6256 ( .A(Data_Y[0]), .Y(n4885) );
INVX2TS U6257 ( .A(Data_Y[5]), .Y(n4886) );
MXI2X1TS U6258 ( .A(n4886), .B(n2627), .S0(n2720), .Y(n1237) );
INVX2TS U6259 ( .A(Data_Y[6]), .Y(n4887) );
MXI2X2TS U6260 ( .A(n4887), .B(n2233), .S0(n2719), .Y(n1238) );
NAND2X1TS U6261 ( .A(n6018), .B(n6019), .Y(n4891) );
NAND2X8TS U6262 ( .A(n1701), .B(n1657), .Y(n4890) );
NAND2X1TS U6263 ( .A(n1701), .B(n4896), .Y(n5977) );
NAND2X1TS U6264 ( .A(n6028), .B(n1947), .Y(n4906) );
NAND2X1TS U6265 ( .A(n5988), .B(n2714), .Y(n4901) );
NAND4BX1TS U6266 ( .AN(n5981), .B(n6025), .C(n4901), .D(n2750), .Y(n4904) );
NAND3X1TS U6267 ( .A(n4902), .B(n5807), .C(n6013), .Y(n4903) );
AO22X1TS U6268 ( .A0(n3259), .A1(Sgf_normalized_result[44]), .B0(
final_result_ieee[42]), .B1(n6040), .Y(n1372) );
AO22X1TS U6269 ( .A0(n3259), .A1(Sgf_normalized_result[43]), .B0(
final_result_ieee[41]), .B1(n6040), .Y(n1373) );
AO22X1TS U6270 ( .A0(n3259), .A1(n2169), .B0(final_result_ieee[40]), .B1(
n6040), .Y(n1374) );
AO22X1TS U6271 ( .A0(n3261), .A1(n2461), .B0(final_result_ieee[3]), .B1(
n4910), .Y(n1411) );
AO22X1TS U6272 ( .A0(n3259), .A1(n1594), .B0(final_result_ieee[39]), .B1(
n6040), .Y(n1375) );
AO22X1TS U6273 ( .A0(n6031), .A1(n1867), .B0(final_result_ieee[21]), .B1(
n4910), .Y(n1393) );
AO22X1TS U6274 ( .A0(n3259), .A1(Sgf_normalized_result[40]), .B0(
final_result_ieee[38]), .B1(n4908), .Y(n1376) );
AO22X1TS U6275 ( .A0(n3261), .A1(n2463), .B0(final_result_ieee[5]), .B1(
n4910), .Y(n1409) );
AO22X1TS U6276 ( .A0(n3261), .A1(n2012), .B0(final_result_ieee[11]), .B1(
n4909), .Y(n1403) );
AO22X1TS U6277 ( .A0(n3259), .A1(Sgf_normalized_result[39]), .B0(
final_result_ieee[37]), .B1(n6040), .Y(n1377) );
AO22X1TS U6278 ( .A0(n3261), .A1(n2089), .B0(final_result_ieee[12]), .B1(
n4909), .Y(n1402) );
AO22X1TS U6279 ( .A0(n3261), .A1(n2138), .B0(final_result_ieee[6]), .B1(
n4910), .Y(n1408) );
AO22X1TS U6280 ( .A0(n3259), .A1(n1958), .B0(final_result_ieee[34]), .B1(
n4908), .Y(n1380) );
AO22X1TS U6281 ( .A0(n3261), .A1(n2021), .B0(final_result_ieee[10]), .B1(
n4909), .Y(n1404) );
AO22X1TS U6282 ( .A0(n3259), .A1(n2167), .B0(final_result_ieee[35]), .B1(
n4908), .Y(n1379) );
AO22X1TS U6283 ( .A0(n4907), .A1(n2047), .B0(final_result_ieee[7]), .B1(
n4909), .Y(n1407) );
AO22X1TS U6284 ( .A0(n3259), .A1(Sgf_normalized_result[38]), .B0(
final_result_ieee[36]), .B1(n6040), .Y(n1378) );
AO22X1TS U6285 ( .A0(n3261), .A1(n1992), .B0(final_result_ieee[9]), .B1(
n4909), .Y(n1405) );
AO22X1TS U6286 ( .A0(n6031), .A1(n1610), .B0(final_result_ieee[33]), .B1(
n4908), .Y(n1381) );
AO22X1TS U6287 ( .A0(n3261), .A1(n1826), .B0(final_result_ieee[8]), .B1(
n4909), .Y(n1406) );
AO22X2TS U6288 ( .A0(n3261), .A1(Sgf_normalized_result[48]), .B0(
final_result_ieee[46]), .B1(n6040), .Y(n1368) );
AO22X2TS U6289 ( .A0(n4911), .A1(Sgf_normalized_result[45]), .B0(
final_result_ieee[43]), .B1(n6040), .Y(n1371) );
AO22X2TS U6290 ( .A0(n3260), .A1(n1883), .B0(final_result_ieee[45]), .B1(
n6040), .Y(n1369) );
AO22X2TS U6291 ( .A0(n4911), .A1(n2450), .B0(final_result_ieee[2]), .B1(
n4910), .Y(n1412) );
NAND2X1TS U6292 ( .A(n3046), .B(n4914), .Y(n4915) );
CLKINVX1TS U6293 ( .A(n4917), .Y(n4919) );
MXI2X2TS U6294 ( .A(n4923), .B(n4922), .S0(n2762), .Y(n4924) );
NAND2X1TS U6295 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n4944) );
NAND2X1TS U6296 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n4943) );
NAND2X1TS U6297 ( .A(n5083), .B(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n4942) );
XOR2X1TS U6298 ( .A(n4952), .B(n4951), .Y(n4953) );
INVX6TS U6299 ( .A(n5129), .Y(n5735) );
INVX2TS U6300 ( .A(n4960), .Y(n4959) );
NAND2X1TS U6301 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n4995) );
NAND2X1TS U6302 ( .A(n5083), .B(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n4994) );
NAND2X1TS U6303 ( .A(n5732), .B(n2631), .Y(n4999) );
NAND2X1TS U6304 ( .A(n5083), .B(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n4996) );
AOI22X1TS U6305 ( .A0(n5102), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B1(n5101), .Y(n5011)
);
NAND2X1TS U6306 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n5034) );
NAND2X1TS U6307 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n5033) );
NAND2X1TS U6308 ( .A(n5083), .B(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n5031) );
NAND2X1TS U6309 ( .A(n2738), .B(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n5038) );
NAND2X1TS U6310 ( .A(n5083), .B(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n5035) );
NAND2X1TS U6311 ( .A(n5784), .B(n1968), .Y(n5039) );
NAND2X1TS U6312 ( .A(n2739), .B(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n5051) );
NAND2X1TS U6313 ( .A(n5149), .B(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .Y(n5049) );
NOR2X6TS U6314 ( .A(n5748), .B(n5153), .Y(n5898) );
NAND2X1TS U6315 ( .A(n2581), .B(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n5057) );
NAND2X2TS U6316 ( .A(n5065), .B(n5194), .Y(n5067) );
NAND2X1TS U6317 ( .A(n5784), .B(n2146), .Y(n5066) );
NAND2X1TS U6318 ( .A(n5074), .B(n2663), .Y(n5073) );
NAND2X1TS U6319 ( .A(n5082), .B(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(n5070) );
NAND2X1TS U6320 ( .A(n5732), .B(n1687), .Y(n5071) );
NAND2X1TS U6321 ( .A(n3255), .B(Sgf_normalized_result[26]), .Y(n5076) );
NAND2X1TS U6322 ( .A(n5102), .B(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n5080) );
NAND2X1TS U6323 ( .A(n5083), .B(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n5077) );
NAND2X1TS U6324 ( .A(n5102), .B(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(n5086) );
NAND2X1TS U6325 ( .A(n5103), .B(n2763), .Y(n5084) );
NAND2X2TS U6326 ( .A(n5732), .B(Sgf_normalized_result[30]), .Y(n5087) );
AOI22X1TS U6327 ( .A0(n5717), .A1(n4965), .B0(n1826), .B1(n3255), .Y(n5108)
);
AOI22X1TS U6328 ( .A0(n5700), .A1(n4965), .B0(n2089), .B1(n5140), .Y(n5112)
);
OAI21X2TS U6329 ( .A0(n5125), .A1(n5124), .B0(n2662), .Y(n5128) );
AOI22X1TS U6330 ( .A0(n5126), .A1(n4965), .B0(n2470), .B1(n5140), .Y(n5127)
);
OAI21X2TS U6331 ( .A0(n5884), .A1(n5886), .B0(n2664), .Y(n5142) );
NAND2X2TS U6332 ( .A(n2731), .B(n6039), .Y(n5157) );
NAND2X1TS U6333 ( .A(n5140), .B(n2283), .Y(n5197) );
NAND2X2TS U6334 ( .A(n5627), .B(n2504), .Y(n5200) );
NAND4X1TS U6335 ( .A(n5423), .B(n5202), .C(n5201), .D(n5200), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[53]) );
AOI22X2TS U6336 ( .A0(n2741), .A1(n2245), .B0(n2299), .B1(n5777), .Y(n5203)
);
CLKINVX1TS U6337 ( .A(n5208), .Y(n5210) );
INVX2TS U6338 ( .A(n5216), .Y(n5211) );
XNOR2X4TS U6339 ( .A(n5212), .B(n5211), .Y(n5219) );
XNOR2X4TS U6340 ( .A(n5217), .B(n5216), .Y(n5218) );
MXI2X4TS U6341 ( .A(n5219), .B(n5218), .S0(n6060), .Y(n5220) );
NAND2X1TS U6342 ( .A(n5321), .B(n5986), .Y(n5232) );
NAND2X1TS U6343 ( .A(n5452), .B(n1970), .Y(n5231) );
AOI22X1TS U6344 ( .A0(n5662), .A1(n5608), .B0(n5478), .B1(n5630), .Y(n5245)
);
NAND2X1TS U6345 ( .A(n5496), .B(DmP[31]), .Y(n5252) );
NOR2X6TS U6346 ( .A(n5254), .B(n5452), .Y(n5255) );
NAND2X1TS U6347 ( .A(n5496), .B(DmP[24]), .Y(n5256) );
NAND2X2TS U6348 ( .A(n5257), .B(n5256), .Y(n5260) );
NAND2X1TS U6349 ( .A(n5496), .B(DmP[30]), .Y(n5263) );
NAND2X1TS U6350 ( .A(n5496), .B(n1933), .Y(n5266) );
NAND2X1TS U6351 ( .A(n5496), .B(DmP[28]), .Y(n5270) );
NAND2X1TS U6352 ( .A(n5496), .B(DmP[26]), .Y(n5275) );
NAND2X2TS U6353 ( .A(n2729), .B(DmP[22]), .Y(n5288) );
INVX2TS U6354 ( .A(n5290), .Y(n5382) );
NAND2X2TS U6355 ( .A(n5434), .B(n1606), .Y(n5303) );
NAND2X1TS U6356 ( .A(n5506), .B(n1897), .Y(n5310) );
NAND2X1TS U6357 ( .A(n5434), .B(Add_Subt_result[15]), .Y(n5309) );
NAND2X1TS U6358 ( .A(n5434), .B(Add_Subt_result[16]), .Y(n5312) );
NAND2X1TS U6359 ( .A(n5321), .B(n6000), .Y(n5317) );
NAND2X1TS U6360 ( .A(n5496), .B(DmP[34]), .Y(n5316) );
NAND2X1TS U6361 ( .A(n5434), .B(n5336), .Y(n5315) );
NAND2X2TS U6362 ( .A(n2754), .B(DmP[35]), .Y(n5319) );
NAND2X2TS U6363 ( .A(n5434), .B(n5919), .Y(n5318) );
NAND2X1TS U6364 ( .A(n5506), .B(n2000), .Y(n5323) );
AOI22X1TS U6365 ( .A0(n2677), .A1(n5615), .B0(n5532), .B1(n5616), .Y(n5334)
);
AOI22X1TS U6366 ( .A0(n2675), .A1(n5572), .B0(n5603), .B1(n5567), .Y(n5353)
);
NAND2X2TS U6367 ( .A(n2729), .B(DmP[18]), .Y(n5346) );
AOI22X1TS U6368 ( .A0(n5655), .A1(n5568), .B0(n5569), .B1(n5661), .Y(n5352)
);
NAND2X2TS U6369 ( .A(n5514), .B(n5919), .Y(n5357) );
INVX2TS U6370 ( .A(n5362), .Y(n5363) );
AOI22X1TS U6371 ( .A0(n5532), .A1(n5573), .B0(n5570), .B1(n5648), .Y(n5366)
);
NAND2X1TS U6372 ( .A(n2729), .B(n1971), .Y(n5373) );
AOI22X1TS U6373 ( .A0(n2674), .A1(n5560), .B0(n5654), .B1(n5561), .Y(n5380)
);
AOI22X1TS U6374 ( .A0(n2676), .A1(n5568), .B0(n5628), .B1(n5560), .Y(n5389)
);
AOI22X1TS U6375 ( .A0(n5584), .A1(n5558), .B0(n5561), .B1(n5630), .Y(n5388)
);
AOI22X1TS U6376 ( .A0(n5685), .A1(n5572), .B0(n5573), .B1(n5673), .Y(n5393)
);
NAND2X2TS U6377 ( .A(n2729), .B(DmP[11]), .Y(n5408) );
AOI22X1TS U6378 ( .A0(n2712), .A1(n5633), .B0(n2886), .B1(n5632), .Y(n5413)
);
AOI22X1TS U6379 ( .A0(n2677), .A1(n5561), .B0(n5654), .B1(n5558), .Y(n5412)
);
AOI22X1TS U6380 ( .A0(n2761), .A1(n5560), .B0(n5568), .B1(n2699), .Y(n5410)
);
NOR2XLTS U6381 ( .A(n1852), .B(n5421), .Y(n5425) );
NAND4BX1TS U6382 ( .AN(n5425), .B(n5424), .C(n5423), .D(n5422), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[52]) );
NAND2X1TS U6383 ( .A(n5452), .B(DmP[44]), .Y(n5429) );
AOI22X1TS U6384 ( .A0(n5532), .A1(n5579), .B0(n5477), .B1(n5634), .Y(n5445)
);
NAND2X1TS U6385 ( .A(n5452), .B(DmP[42]), .Y(n5447) );
NAND2X1TS U6386 ( .A(n5452), .B(n1940), .Y(n5450) );
NAND2X1TS U6387 ( .A(n5452), .B(n2298), .Y(n5454) );
AOI22X1TS U6388 ( .A0(n5631), .A1(n5618), .B0(n5622), .B1(n5630), .Y(n5457)
);
AOI22X1TS U6389 ( .A0(n2712), .A1(n5621), .B0(n2759), .B1(n5610), .Y(n5462)
);
AOI22X1TS U6390 ( .A0(n2761), .A1(n5579), .B0(n5478), .B1(n2700), .Y(n5461)
);
AOI22X1TS U6391 ( .A0(n2675), .A1(n5622), .B0(n5654), .B1(n5618), .Y(n5466)
);
AOI22X1TS U6392 ( .A0(n5673), .A1(n5621), .B0(n5610), .B1(n2695), .Y(n5464)
);
AOI22X1TS U6393 ( .A0(n2712), .A1(n5618), .B0(n2758), .B1(n5622), .Y(n5471)
);
AOI22X1TS U6394 ( .A0(n2676), .A1(n5609), .B0(n5532), .B1(n2505), .Y(n5470)
);
AOI22X1TS U6395 ( .A0(n5631), .A1(n5621), .B0(n5610), .B1(n5688), .Y(n5468)
);
AOI22X1TS U6396 ( .A0(n5662), .A1(n5591), .B0(n2886), .B1(n5595), .Y(n5486)
);
AOI22X1TS U6397 ( .A0(n5584), .A1(n5594), .B0(n5592), .B1(n5670), .Y(n5484)
);
NAND2X1TS U6398 ( .A(n5506), .B(n1887), .Y(n5494) );
NAND2X1TS U6399 ( .A(n5282), .B(n5986), .Y(n5493) );
NAND2X1TS U6400 ( .A(n5496), .B(DmP[8]), .Y(n5498) );
NAND2X1TS U6401 ( .A(n5506), .B(n2130), .Y(n5501) );
AOI22X1TS U6402 ( .A0(n2674), .A1(n5671), .B0(n5654), .B1(n5672), .Y(n5522)
);
NAND2X1TS U6403 ( .A(n5282), .B(n5995), .Y(n5507) );
NAND2X2TS U6404 ( .A(n2729), .B(DmP[10]), .Y(n5518) );
AOI22X1TS U6405 ( .A0(n5655), .A1(n5629), .B0(n5633), .B1(n5661), .Y(n5525)
);
AOI22X1TS U6406 ( .A0(n2676), .A1(n5633), .B0(n5532), .B1(n5629), .Y(n5535)
);
AOI22X1TS U6407 ( .A0(n5631), .A1(n5671), .B0(n5656), .B1(n5688), .Y(n5534)
);
AOI22X1TS U6408 ( .A0(n2675), .A1(n5602), .B0(n5654), .B1(n5596), .Y(n5556)
);
AOI22X1TS U6409 ( .A0(n2675), .A1(n5569), .B0(n5628), .B1(n5568), .Y(n5564)
);
AOI22X1TS U6410 ( .A0(n5631), .A1(n5561), .B0(n5560), .B1(n5630), .Y(n5563)
);
NAND2X1TS U6411 ( .A(n5571), .B(n2555), .Y(n5575) );
AOI22X1TS U6412 ( .A0(n5685), .A1(n5609), .B0(n2505), .B1(n5661), .Y(n5580)
);
AOI22X1TS U6413 ( .A0(n2675), .A1(n5621), .B0(n5628), .B1(n5622), .Y(n5587)
);
AOI22X1TS U6414 ( .A0(n5584), .A1(n5617), .B0(n5618), .B1(n5630), .Y(n5586)
);
AOI22X1TS U6415 ( .A0(n5663), .A1(n5610), .B0(n2505), .B1(n2701), .Y(n5585)
);
AOI22X1TS U6416 ( .A0(n2673), .A1(n2505), .B0(n5609), .B1(n5673), .Y(n5612)
);
AOI22X1TS U6417 ( .A0(n5685), .A1(n5610), .B0(n5621), .B1(n5688), .Y(n5611)
);
AOI22X1TS U6418 ( .A0(n2673), .A1(n5629), .B0(n5628), .B1(n5656), .Y(n5637)
);
AOI22X1TS U6419 ( .A0(n5631), .A1(n5672), .B0(n5671), .B1(n5630), .Y(n5636)
);
AOI22X1TS U6420 ( .A0(n5662), .A1(n5684), .B0(n2886), .B1(n5682), .Y(n5660)
);
AOI22X1TS U6421 ( .A0(n5673), .A1(n5671), .B0(n5656), .B1(n2695), .Y(n5657)
);
AOI22X1TS U6422 ( .A0(n2676), .A1(n5686), .B0(n5687), .B1(n5642), .Y(n5666)
);
OAI2BB1X1TS U6423 ( .A0N(Sgf_normalized_result[40]), .A1N(n5140), .B0(n2727),
.Y(n5699) );
OAI2BB1X1TS U6424 ( .A0N(n2169), .A1N(n5140), .B0(n2727), .Y(n5706) );
OAI2BB1X1TS U6425 ( .A0N(n1594), .A1N(n5140), .B0(n2727), .Y(n5711) );
OAI2BB1X1TS U6426 ( .A0N(Sgf_normalized_result[43]), .A1N(n5154), .B0(n2727),
.Y(n5721) );
OR2X1TS U6427 ( .A(n5738), .B(n5782), .Y(n5740) );
NAND2X1TS U6428 ( .A(n3255), .B(Sgf_normalized_result[48]), .Y(n5739) );
NAND2X1TS U6429 ( .A(n3255), .B(Sgf_normalized_result[49]), .Y(n5744) );
BUFX20TS U6430 ( .A(n3269), .Y(n5860) );
INVX8TS U6431 ( .A(n6019), .Y(n5859) );
AOI22X1TS U6432 ( .A0(n5849), .A1(n2635), .B0(n2002), .B1(n5825), .Y(n5797)
);
AOI22X1TS U6433 ( .A0(n5849), .A1(n2354), .B0(n2000), .B1(n5825), .Y(n5811)
);
AOI22X1TS U6434 ( .A0(n5829), .A1(n2207), .B0(n1940), .B1(n5825), .Y(n5812)
);
AOI22X1TS U6435 ( .A0(n5849), .A1(n2080), .B0(n2004), .B1(n5807), .Y(n5818)
);
MXI2X1TS U6436 ( .A(n5832), .B(n6203), .S0(n6011), .Y(n1436) );
AOI22X2TS U6437 ( .A0(n2596), .A1(n2249), .B0(n1881), .B1(n3230), .Y(n5848)
);
NAND2X1TS U6438 ( .A(n5878), .B(n5897), .Y(n5881) );
OAI2BB1X1TS U6439 ( .A0N(n1997), .A1N(n5895), .B0(n2727), .Y(n5889) );
OAI2BB1X1TS U6440 ( .A0N(Sgf_normalized_result[38]), .A1N(n5895), .B0(n5890),
.Y(n5894) );
NAND2X1TS U6441 ( .A(n5898), .B(n5897), .Y(n5902) );
AOI21X1TS U6442 ( .A0(n5910), .A1(n5909), .B0(n5985), .Y(n5914) );
CLKINVX1TS U6443 ( .A(n5995), .Y(n5911) );
NAND3X2TS U6444 ( .A(n5920), .B(n5919), .C(n5918), .Y(n5921) );
INVX2TS U6445 ( .A(n5933), .Y(n5935) );
NAND2X1TS U6446 ( .A(n5935), .B(n1722), .Y(n5936) );
NAND2X2TS U6447 ( .A(n5958), .B(n5957), .Y(n5959) );
INVX2TS U6448 ( .A(n5964), .Y(n5965) );
CLKMX2X2TS U6449 ( .A(n5974), .B(exp_oper_result[0]), .S0(n6406), .Y(n1438)
);
NAND2X1TS U6450 ( .A(n5975), .B(n1985), .Y(n5976) );
NAND3X1TS U6451 ( .A(n5978), .B(n5977), .C(n5976), .Y(n5979) );
INVX2TS U6452 ( .A(n5984), .Y(n6533) );
CLKBUFX2TS U6453 ( .A(n1360), .Y(n6261) );
NAND2X1TS U6454 ( .A(n5987), .B(n5985), .Y(n6469) );
NAND2X1TS U6455 ( .A(n5987), .B(n5986), .Y(n6475) );
NAND2X2TS U6456 ( .A(n5999), .B(n1686), .Y(n6502) );
NAND2X2TS U6457 ( .A(n6038), .B(n5993), .Y(n6496) );
NAND2X1TS U6458 ( .A(n5999), .B(n3250), .Y(n6493) );
NAND2X2TS U6459 ( .A(n5999), .B(n6006), .Y(n6520) );
NAND2X1TS U6460 ( .A(n6011), .B(overflow_flag), .Y(n6542) );
MXI2X1TS U6461 ( .A(n3256), .B(n2897), .S0(n6012), .Y(n1440) );
INVX2TS U6462 ( .A(final_result_ieee[63]), .Y(n6014) );
MXI2X1TS U6463 ( .A(n6015), .B(n6014), .S0(n6013), .Y(n1361) );
INVX2TS U6464 ( .A(Data_Y[63]), .Y(n6016) );
MXI2X1TS U6465 ( .A(n6016), .B(n6260), .S0(n6119), .Y(n1231) );
INVX2TS U6466 ( .A(add_subt), .Y(n6017) );
MXI2X1TS U6467 ( .A(n6017), .B(n6259), .S0(n6086), .Y(n1295) );
CLKINVX1TS U6468 ( .A(n6018), .Y(n6020) );
AOI2BB2X1TS U6469 ( .B0(n3259), .B1(n6200), .A0N(n6035), .A1N(
final_result_ieee[52]), .Y(n1425) );
AOI2BB2X1TS U6470 ( .B0(n6036), .B1(n6202), .A0N(n6035), .A1N(
final_result_ieee[56]), .Y(n1421) );
AOI2BB2X1TS U6471 ( .B0(n6036), .B1(n6208), .A0N(n6035), .A1N(
final_result_ieee[57]), .Y(n1420) );
AOI2BB2X1TS U6472 ( .B0(n6036), .B1(n6210), .A0N(n6035), .A1N(
final_result_ieee[55]), .Y(n1422) );
AOI2BB2X1TS U6473 ( .B0(n6036), .B1(n6209), .A0N(n6035), .A1N(
final_result_ieee[59]), .Y(n1418) );
AOI2BB2X1TS U6474 ( .B0(n6036), .B1(n2651), .A0N(n6035), .A1N(
final_result_ieee[62]), .Y(n1415) );
AOI2BB2X1TS U6475 ( .B0(n6036), .B1(n6201), .A0N(n6035), .A1N(
final_result_ieee[58]), .Y(n1419) );
AOI2BB2X1TS U6476 ( .B0(n6036), .B1(n6032), .A0N(n6033), .A1N(
final_result_ieee[60]), .Y(n1417) );
AOI2BB2X1TS U6477 ( .B0(n6036), .B1(n6034), .A0N(n6033), .A1N(
final_result_ieee[61]), .Y(n1416) );
AOI2BB2X1TS U6478 ( .B0(n6036), .B1(n6203), .A0N(n6035), .A1N(
final_result_ieee[54]), .Y(n1423) );
AOI2BB2X1TS U6479 ( .B0(n6036), .B1(n6211), .A0N(n6035), .A1N(
final_result_ieee[53]), .Y(n1424) );
MXI2X1TS U6480 ( .A(n1622), .B(n6039), .S0(n5999), .Y(n1503) );
NAND2X1TS U6481 ( .A(n2111), .B(n6041), .Y(n6042) );
CLKINVX1TS U6482 ( .A(n6043), .Y(n6045) );
XOR2X1TS U6483 ( .A(n6056), .B(n6046), .Y(n6047) );
XOR2X1TS U6484 ( .A(n6053), .B(n6052), .Y(n6062) );
NAND2X1TS U6485 ( .A(n3504), .B(n6056), .Y(n6059) );
XOR2X1TS U6486 ( .A(n6059), .B(n3507), .Y(n6061) );
MXI2X1TS U6487 ( .A(n6062), .B(n6061), .S0(n6060), .Y(n6065) );
INVX2TS U6488 ( .A(Add_Subt_result[1]), .Y(n6064) );
MXI2X1TS U6489 ( .A(n6065), .B(n6064), .S0(n6405), .Y(n1504) );
MXI2X1TS U6490 ( .A(n6066), .B(n6233), .S0(n6075), .Y(n1296) );
INVX2TS U6491 ( .A(Data_X[62]), .Y(n6067) );
INVX2TS U6492 ( .A(Data_X[61]), .Y(n6068) );
MXI2X2TS U6493 ( .A(n6068), .B(n1943), .S0(n6075), .Y(n1358) );
INVX2TS U6494 ( .A(Data_X[60]), .Y(n6069) );
MXI2X2TS U6495 ( .A(n6069), .B(n2175), .S0(n6075), .Y(n1357) );
INVX2TS U6496 ( .A(Data_X[59]), .Y(n6070) );
MXI2X2TS U6497 ( .A(n6070), .B(n2094), .S0(n6075), .Y(n1356) );
INVX2TS U6498 ( .A(Data_X[58]), .Y(n6071) );
MXI2X2TS U6499 ( .A(n6071), .B(n2248), .S0(n6075), .Y(n1355) );
INVX2TS U6500 ( .A(Data_X[57]), .Y(n6072) );
MXI2X2TS U6501 ( .A(n6072), .B(n2195), .S0(n6075), .Y(n1354) );
INVX2TS U6502 ( .A(Data_X[56]), .Y(n6073) );
MXI2X2TS U6503 ( .A(n6073), .B(n2252), .S0(n6075), .Y(n1353) );
INVX2TS U6504 ( .A(Data_X[55]), .Y(n6074) );
MXI2X2TS U6505 ( .A(n6074), .B(n2244), .S0(n6075), .Y(n1352) );
INVX2TS U6506 ( .A(Data_X[54]), .Y(n6076) );
MXI2X2TS U6507 ( .A(n6076), .B(n2133), .S0(n6075), .Y(n1351) );
MXI2X1TS U6508 ( .A(n6077), .B(n2115), .S0(n2720), .Y(n1350) );
INVX2TS U6509 ( .A(Data_X[52]), .Y(n6078) );
INVX2TS U6510 ( .A(Data_X[51]), .Y(n6079) );
INVX2TS U6511 ( .A(Data_X[50]), .Y(n6080) );
INVX2TS U6512 ( .A(Data_X[49]), .Y(n6081) );
INVX2TS U6513 ( .A(Data_X[48]), .Y(n6082) );
INVX2TS U6514 ( .A(Data_X[47]), .Y(n6083) );
MXI2X2TS U6515 ( .A(n6083), .B(n2150), .S0(n2719), .Y(n1344) );
INVX2TS U6516 ( .A(Data_X[46]), .Y(n6084) );
INVX2TS U6517 ( .A(Data_X[45]), .Y(n6085) );
MXI2X1TS U6518 ( .A(n6085), .B(n2197), .S0(n6163), .Y(n1342) );
INVX2TS U6519 ( .A(Data_X[44]), .Y(n6087) );
MXI2X1TS U6520 ( .A(n6087), .B(n2152), .S0(n6163), .Y(n1341) );
INVX2TS U6521 ( .A(Data_X[43]), .Y(n6088) );
MXI2X2TS U6522 ( .A(n6088), .B(n2250), .S0(n6119), .Y(n1340) );
INVX2TS U6523 ( .A(Data_X[42]), .Y(n6089) );
MXI2X2TS U6524 ( .A(n6089), .B(n2394), .S0(n2720), .Y(n1339) );
INVX2TS U6525 ( .A(Data_X[41]), .Y(n6090) );
MXI2X2TS U6526 ( .A(n6090), .B(n2110), .S0(n6086), .Y(n1338) );
MXI2X1TS U6527 ( .A(n6091), .B(n2165), .S0(n2720), .Y(n1337) );
INVX2TS U6528 ( .A(Data_X[39]), .Y(n6092) );
MXI2X1TS U6529 ( .A(n6092), .B(n2379), .S0(n6097), .Y(n1336) );
INVX2TS U6530 ( .A(Data_X[38]), .Y(n6093) );
MXI2X2TS U6531 ( .A(n6093), .B(n2242), .S0(n2719), .Y(n1335) );
INVX2TS U6532 ( .A(Data_X[37]), .Y(n6094) );
MXI2X2TS U6533 ( .A(n6094), .B(n2385), .S0(n6086), .Y(n1334) );
INVX2TS U6534 ( .A(Data_X[36]), .Y(n6095) );
MXI2X2TS U6535 ( .A(n6095), .B(n2366), .S0(n2720), .Y(n1333) );
INVX2TS U6536 ( .A(Data_X[35]), .Y(n6096) );
MXI2X2TS U6537 ( .A(n6096), .B(n2123), .S0(n2720), .Y(n1332) );
INVX2TS U6538 ( .A(Data_X[34]), .Y(n6098) );
MXI2X2TS U6539 ( .A(n6098), .B(n2096), .S0(n2719), .Y(n1331) );
INVX2TS U6540 ( .A(Data_X[33]), .Y(n6099) );
MXI2X2TS U6541 ( .A(n6099), .B(n2142), .S0(n6108), .Y(n1330) );
INVX2TS U6542 ( .A(Data_X[32]), .Y(n6100) );
MXI2X2TS U6543 ( .A(n6100), .B(n2179), .S0(n6108), .Y(n1329) );
INVX2TS U6544 ( .A(Data_X[31]), .Y(n6101) );
MXI2X2TS U6545 ( .A(n6101), .B(n2435), .S0(n6108), .Y(n1328) );
INVX2TS U6546 ( .A(Data_X[30]), .Y(n6102) );
MXI2X2TS U6547 ( .A(n6102), .B(n1917), .S0(n6108), .Y(n1327) );
INVX2TS U6548 ( .A(Data_X[29]), .Y(n6103) );
MXI2X2TS U6549 ( .A(n6103), .B(n2220), .S0(n6108), .Y(n1326) );
INVX2TS U6550 ( .A(Data_X[28]), .Y(n6104) );
MXI2X2TS U6551 ( .A(n6104), .B(n2246), .S0(n6108), .Y(n1325) );
INVX2TS U6552 ( .A(Data_X[27]), .Y(n6105) );
MXI2X2TS U6553 ( .A(n6105), .B(n2222), .S0(n6108), .Y(n1324) );
MXI2X2TS U6554 ( .A(n6106), .B(n2035), .S0(n6108), .Y(n1323) );
INVX2TS U6555 ( .A(Data_X[25]), .Y(n6107) );
MXI2X2TS U6556 ( .A(n6107), .B(n2106), .S0(n6108), .Y(n1322) );
INVX2TS U6557 ( .A(Data_X[24]), .Y(n6109) );
MXI2X2TS U6558 ( .A(n6109), .B(n2079), .S0(n6108), .Y(n1321) );
INVX2TS U6559 ( .A(Data_X[23]), .Y(n6110) );
MXI2X2TS U6560 ( .A(n6110), .B(n2228), .S0(n2719), .Y(n1320) );
INVX2TS U6561 ( .A(Data_X[22]), .Y(n6111) );
MXI2X2TS U6562 ( .A(n6111), .B(n2218), .S0(n6086), .Y(n1319) );
INVX2TS U6563 ( .A(Data_X[21]), .Y(n6112) );
MXI2X2TS U6564 ( .A(n6112), .B(n2240), .S0(n6086), .Y(n1318) );
INVX2TS U6565 ( .A(Data_X[20]), .Y(n6113) );
MXI2X1TS U6566 ( .A(n6113), .B(n2159), .S0(n6163), .Y(n1317) );
INVX2TS U6567 ( .A(Data_X[19]), .Y(n6114) );
MXI2X2TS U6568 ( .A(n6114), .B(n2098), .S0(n6097), .Y(n1316) );
INVX2TS U6569 ( .A(Data_X[18]), .Y(n6115) );
MXI2X2TS U6570 ( .A(n6115), .B(n2375), .S0(n6163), .Y(n1315) );
INVX2TS U6571 ( .A(Data_X[17]), .Y(n6116) );
MXI2X2TS U6572 ( .A(n6116), .B(n2137), .S0(n6119), .Y(n1314) );
INVX2TS U6573 ( .A(Data_X[16]), .Y(n6117) );
MXI2X2TS U6574 ( .A(n6117), .B(n2364), .S0(n2719), .Y(n1313) );
INVX2TS U6575 ( .A(Data_X[15]), .Y(n6118) );
INVX2TS U6576 ( .A(Data_X[14]), .Y(n6120) );
MXI2X2TS U6577 ( .A(n6120), .B(n2061), .S0(n6097), .Y(n1311) );
INVX2TS U6578 ( .A(Data_X[13]), .Y(n6121) );
INVX2TS U6579 ( .A(Data_X[12]), .Y(n6122) );
MXI2X2TS U6580 ( .A(n6122), .B(n2064), .S0(n6130), .Y(n1309) );
INVX2TS U6581 ( .A(Data_X[11]), .Y(n6123) );
MXI2X2TS U6582 ( .A(n6123), .B(n2390), .S0(n6130), .Y(n1308) );
INVX2TS U6583 ( .A(Data_X[10]), .Y(n6124) );
INVX2TS U6584 ( .A(Data_X[9]), .Y(n6125) );
MXI2X2TS U6585 ( .A(n6125), .B(n2611), .S0(n6130), .Y(n1306) );
INVX2TS U6586 ( .A(Data_X[8]), .Y(n6126) );
MXI2X2TS U6587 ( .A(n6126), .B(n2203), .S0(n6130), .Y(n1305) );
INVX2TS U6588 ( .A(Data_X[7]), .Y(n6127) );
MXI2X2TS U6589 ( .A(n6127), .B(n2236), .S0(n6130), .Y(n1304) );
INVX2TS U6590 ( .A(Data_X[6]), .Y(n6128) );
MXI2X2TS U6591 ( .A(n6128), .B(n2381), .S0(n6130), .Y(n1303) );
INVX2TS U6592 ( .A(Data_X[5]), .Y(n6129) );
MXI2X2TS U6593 ( .A(n6129), .B(n2433), .S0(n6130), .Y(n1302) );
INVX2TS U6594 ( .A(Data_X[4]), .Y(n6131) );
MXI2X2TS U6595 ( .A(n6131), .B(n2653), .S0(n6130), .Y(n1301) );
INVX2TS U6596 ( .A(Data_X[3]), .Y(n6132) );
MXI2X1TS U6597 ( .A(n6132), .B(n2661), .S0(n6163), .Y(n1300) );
INVX2TS U6598 ( .A(Data_X[2]), .Y(n6133) );
MXI2X2TS U6599 ( .A(n6133), .B(n2617), .S0(n6097), .Y(n1299) );
INVX2TS U6600 ( .A(Data_X[1]), .Y(n6134) );
MXI2X2TS U6601 ( .A(n6134), .B(n2191), .S0(n6119), .Y(n1298) );
INVX2TS U6602 ( .A(Data_X[0]), .Y(n6135) );
MXI2X1TS U6603 ( .A(n6135), .B(n2161), .S0(n6097), .Y(n1297) );
INVX2TS U6604 ( .A(Data_Y[62]), .Y(n6136) );
MXI2X1TS U6605 ( .A(n6136), .B(n2088), .S0(n6086), .Y(n1294) );
INVX2TS U6606 ( .A(Data_Y[61]), .Y(n6137) );
MXI2X1TS U6607 ( .A(n6137), .B(n2201), .S0(n2720), .Y(n1293) );
INVX2TS U6608 ( .A(Data_Y[60]), .Y(n6138) );
MXI2X1TS U6609 ( .A(n6138), .B(n2290), .S0(n2719), .Y(n1292) );
INVX2TS U6610 ( .A(Data_Y[59]), .Y(n6139) );
MXI2X1TS U6611 ( .A(n6139), .B(n2224), .S0(n6097), .Y(n1291) );
INVX2TS U6612 ( .A(Data_Y[58]), .Y(n6140) );
MXI2X1TS U6613 ( .A(n6140), .B(n2135), .S0(n6086), .Y(n1290) );
INVX2TS U6614 ( .A(Data_Y[57]), .Y(n6141) );
MXI2X1TS U6615 ( .A(n6141), .B(n2322), .S0(n2720), .Y(n1289) );
INVX2TS U6616 ( .A(Data_Y[56]), .Y(n6142) );
MXI2X1TS U6617 ( .A(n6142), .B(n2266), .S0(n6151), .Y(n1288) );
INVX2TS U6618 ( .A(Data_Y[55]), .Y(n6143) );
MXI2X1TS U6619 ( .A(n6143), .B(n2398), .S0(n6151), .Y(n1287) );
INVX2TS U6620 ( .A(Data_Y[54]), .Y(n6144) );
MXI2X1TS U6621 ( .A(n6144), .B(n2181), .S0(n6151), .Y(n1286) );
INVX2TS U6622 ( .A(Data_Y[53]), .Y(n6145) );
MXI2X1TS U6623 ( .A(n6145), .B(n2396), .S0(n6151), .Y(n1285) );
INVX2TS U6624 ( .A(Data_Y[52]), .Y(n6146) );
MXI2X1TS U6625 ( .A(n6146), .B(n2226), .S0(n6151), .Y(n1284) );
INVX2TS U6626 ( .A(Data_Y[51]), .Y(n6147) );
MXI2X1TS U6627 ( .A(n6147), .B(n2337), .S0(n6151), .Y(n1283) );
INVX2TS U6628 ( .A(Data_Y[50]), .Y(n6148) );
MXI2X1TS U6629 ( .A(n6148), .B(n2258), .S0(n6151), .Y(n1282) );
MXI2X1TS U6630 ( .A(n6149), .B(n2392), .S0(n6151), .Y(n1281) );
INVX2TS U6631 ( .A(Data_Y[48]), .Y(n6150) );
INVX2TS U6632 ( .A(Data_Y[47]), .Y(n6152) );
MXI2X2TS U6633 ( .A(n6152), .B(n2173), .S0(n6151), .Y(n1279) );
INVX2TS U6634 ( .A(Data_Y[46]), .Y(n6153) );
MXI2X1TS U6635 ( .A(n6153), .B(n2081), .S0(n6097), .Y(n1278) );
INVX2TS U6636 ( .A(Data_Y[45]), .Y(n6155) );
MXI2X2TS U6637 ( .A(n6155), .B(n6154), .S0(n2719), .Y(n1277) );
INVX2TS U6638 ( .A(Data_Y[44]), .Y(n6156) );
MXI2X1TS U6639 ( .A(n6156), .B(n2362), .S0(n6119), .Y(n1276) );
INVX2TS U6640 ( .A(Data_Y[43]), .Y(n6157) );
INVX2TS U6641 ( .A(Data_Y[42]), .Y(n6158) );
MXI2X1TS U6642 ( .A(n6158), .B(n2310), .S0(n6163), .Y(n1274) );
INVX2TS U6643 ( .A(Data_Y[41]), .Y(n6159) );
MXI2X1TS U6644 ( .A(n6159), .B(n2279), .S0(n6097), .Y(n1273) );
INVX2TS U6645 ( .A(Data_Y[40]), .Y(n6160) );
MXI2X1TS U6646 ( .A(n6160), .B(n2208), .S0(n6119), .Y(n1272) );
INVX2TS U6647 ( .A(Data_Y[39]), .Y(n6161) );
MXI2X1TS U6648 ( .A(n6161), .B(n2335), .S0(n6119), .Y(n1271) );
INVX2TS U6649 ( .A(Data_Y[38]), .Y(n6162) );
MXI2X1TS U6650 ( .A(n6162), .B(n2355), .S0(n6163), .Y(n1270) );
INVX2TS U6651 ( .A(Data_Y[37]), .Y(n6164) );
MXI2X1TS U6652 ( .A(n6164), .B(n2344), .S0(n6163), .Y(n1269) );
INVX2TS U6653 ( .A(Data_Y[36]), .Y(n6165) );
MXI2X1TS U6654 ( .A(n6165), .B(n2100), .S0(n6174), .Y(n1268) );
MXI2X1TS U6655 ( .A(n6166), .B(n2377), .S0(n6174), .Y(n1267) );
INVX2TS U6656 ( .A(Data_Y[34]), .Y(n6167) );
MXI2X1TS U6657 ( .A(n6167), .B(n2402), .S0(n6174), .Y(n1266) );
INVX2TS U6658 ( .A(Data_Y[33]), .Y(n6168) );
MXI2X1TS U6659 ( .A(n6168), .B(n2280), .S0(n6174), .Y(n1265) );
INVX2TS U6660 ( .A(Data_Y[32]), .Y(n6169) );
MXI2X1TS U6661 ( .A(n6169), .B(n2183), .S0(n6174), .Y(n1264) );
INVX2TS U6662 ( .A(Data_Y[31]), .Y(n6170) );
MXI2X1TS U6663 ( .A(n6170), .B(n2294), .S0(n6174), .Y(n1263) );
INVX2TS U6664 ( .A(Data_Y[30]), .Y(n6171) );
MXI2X2TS U6665 ( .A(n6171), .B(n2254), .S0(n6174), .Y(n1262) );
INVX2TS U6666 ( .A(Data_Y[29]), .Y(n6172) );
INVX2TS U6667 ( .A(Data_Y[28]), .Y(n6173) );
MXI2X1TS U6668 ( .A(n6173), .B(n2103), .S0(n6174), .Y(n1260) );
INVX2TS U6669 ( .A(Data_Y[27]), .Y(n6175) );
INVX2TS U6670 ( .A(Data_Y[26]), .Y(n6176) );
INVX2TS U6671 ( .A(Data_Y[25]), .Y(n6177) );
INVX2TS U6672 ( .A(Data_Y[24]), .Y(n6178) );
MXI2X2TS U6673 ( .A(n6178), .B(n1855), .S0(n6185), .Y(n1256) );
INVX2TS U6674 ( .A(Data_Y[23]), .Y(n6179) );
MXI2X1TS U6675 ( .A(n6179), .B(n2193), .S0(n6185), .Y(n1255) );
INVX2TS U6676 ( .A(Data_Y[22]), .Y(n6180) );
MXI2X1TS U6677 ( .A(n6180), .B(n2383), .S0(n6185), .Y(n1254) );
MXI2X1TS U6678 ( .A(n6181), .B(n2368), .S0(n6185), .Y(n1253) );
INVX2TS U6679 ( .A(Data_Y[20]), .Y(n6182) );
MXI2X1TS U6680 ( .A(n6182), .B(n2157), .S0(n6185), .Y(n1252) );
INVX2TS U6681 ( .A(Data_Y[19]), .Y(n6183) );
MXI2X2TS U6682 ( .A(n6183), .B(n2261), .S0(n6185), .Y(n1251) );
INVX2TS U6683 ( .A(Data_Y[18]), .Y(n6184) );
MXI2X1TS U6684 ( .A(n6184), .B(n2256), .S0(n6185), .Y(n1250) );
INVX2TS U6685 ( .A(Data_Y[17]), .Y(n6186) );
MXI2X2TS U6686 ( .A(n6186), .B(n2909), .S0(n6185), .Y(n1249) );
INVX2TS U6687 ( .A(Data_Y[16]), .Y(n6187) );
MXI2X1TS U6688 ( .A(n6187), .B(n2264), .S0(n6196), .Y(n1248) );
INVX2TS U6689 ( .A(Data_Y[15]), .Y(n6188) );
MXI2X1TS U6690 ( .A(n6188), .B(n2288), .S0(n6196), .Y(n1247) );
INVX2TS U6691 ( .A(Data_Y[14]), .Y(n6189) );
MXI2X1TS U6692 ( .A(n6189), .B(n2292), .S0(n6196), .Y(n1246) );
INVX2TS U6693 ( .A(Data_Y[13]), .Y(n6190) );
INVX2TS U6694 ( .A(Data_Y[12]), .Y(n6191) );
MXI2X2TS U6695 ( .A(n6191), .B(n1873), .S0(n6196), .Y(n1244) );
INVX2TS U6696 ( .A(Data_Y[11]), .Y(n6192) );
MXI2X1TS U6697 ( .A(n6192), .B(n2400), .S0(n6196), .Y(n1243) );
INVX2TS U6698 ( .A(Data_Y[10]), .Y(n6193) );
MXI2X2TS U6699 ( .A(n6193), .B(n2120), .S0(n6196), .Y(n1242) );
INVX2TS U6700 ( .A(Data_Y[9]), .Y(n6194) );
MXI2X1TS U6701 ( .A(n6194), .B(n2357), .S0(n6196), .Y(n1241) );
INVX2TS U6702 ( .A(Data_Y[8]), .Y(n6195) );
MXI2X2TS U6703 ( .A(n6195), .B(n2388), .S0(n6196), .Y(n1240) );
MXI2X1TS U6704 ( .A(n6197), .B(n2666), .S0(n6196), .Y(n1239) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk1.tcl_syn.sdf");
endmodule
|
module tx_sm #(
parameter STATE_DEFER = 4'h0,
parameter STATE_IFG = 4'h1,
parameter STATE_IDLE = 4'h2,
parameter STATE_PREAMBLE = 4'h3,
parameter STATE_SFD = 4'h4,
parameter STATE_DATA = 4'h5,
parameter STATE_PAD = 4'h6,
parameter STATE_JAM = 4'h7,
parameter STATE_BACKOFF = 4'h8,
parameter STATE_FCS = 4'h9,
parameter STATE_JAM_DROP = 4'hA,
parameter STATE_NEXT = 4'hB
)(
input wire reset,
input wire clock,
input wire [7:0] fifo_data,
output reg fifo_data_read,
input wire fifo_data_start,
input wire fifo_data_end,
input wire fifo_data_available,
output reg fifo_retry,
input wire mode,
input wire carrier_sense,
input wire collision,
output reg tx_enable,
output reg [7:0] tx_data
);
localparam HALF_DUPLEX = 0;
localparam FULL_DUPLEX = 1;
localparam CRC_POLYNOMIAL = 32'h04C11DB7;
localparam CRC_SEED = 32'hFFFFFFFF;
localparam MAX_SIZE = 1518;
localparam MIN_SIZE = 64;
reg [3:0] state;
reg [3:0] prev_state;
reg [3:0] next_state;
reg [7:0] frame_length_count;
reg [5:0] padding_length_count;
reg [4:0] jam_length_count;
reg [3:0] inter_frame_gap_count;
reg [3:0] preamble_count;
reg [3:0] retry_count;
reg crc_init;
reg crc_enable;
wire [31:0] crc_out;
wire [31:0] crc_rev;
integer crc_index;
reg random_init;
wire random_trigger;
// State update
always @(posedge clock or posedge reset)
if (reset)
state <= STATE_DEFER;
else
begin
prev_state = state;
state = next_state;
end
// State Machine
always @ (*)
case (state)
STATE_DEFER:
if ((mode == FULL_DUPLEX) || (mode == HALF_DUPLEX && !carrier_sense))
next_state = STATE_IFG;
else
next_state = STATE_DEFER;
STATE_IFG:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && inter_frame_gap_count == 12 - 4) || (mode == HALF_DUPLEX && !carrier_sense && inter_frame_gap_count == 12 - 4)) // Drop IFG by four to account for state transitions
next_state = STATE_IDLE;
else
next_state = STATE_IFG;
STATE_IDLE:
if (mode == HALF_DUPLEX && carrier_sense)
next_state = STATE_DEFER;
else if ((mode == FULL_DUPLEX && fifo_data_available) || (mode == HALF_DUPLEX && !carrier_sense && fifo_data_available))
next_state = STATE_PREAMBLE;
else
next_state = STATE_IDLE;
STATE_PREAMBLE:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if ((mode == FULL_DUPLEX && preamble_count == 7) || (mode == HALF_DUPLEX && !collision && preamble_count == 7))
next_state = STATE_SFD;
else
next_state = STATE_PREAMBLE;
STATE_SFD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else
next_state = STATE_DATA;
STATE_DATA:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (fifo_data_end && frame_length_count >= 59 )
next_state = STATE_FCS;
else if (fifo_data_end)
next_state = STATE_PAD;
else
next_state = STATE_DATA;
STATE_PAD:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (frame_length_count >= 59)
next_state = STATE_FCS;
else
next_state = STATE_PAD;
STATE_JAM:
if (retry_count <= 2 && jam_length_count == 16)
next_state = STATE_BACKOFF;
else if (retry_count > 2)
next_state = STATE_JAM_DROP;
else
next_state = STATE_JAM;
STATE_BACKOFF:
if (random_trigger)
next_state = STATE_DEFER;
else
next_state = STATE_BACKOFF;
STATE_FCS:
if (mode == HALF_DUPLEX && collision)
next_state = STATE_JAM;
else if (crc_index > 24)
next_state = STATE_NEXT;
else
next_state = STATE_FCS;
STATE_JAM_DROP:
if (fifo_data_end)
next_state = STATE_NEXT;
else
next_state = STATE_JAM_DROP;
STATE_NEXT:
next_state = STATE_DEFER;
default:
next_state = STATE_DEFER;
endcase
genvar j;
generate
for (j = 31; j >= 0; j = j - 1)
begin : crc_reverse
assign crc_rev[31-j] = crc_out[j];
end
endgenerate
// Counts
// Frame Length
always @(posedge clock or posedge reset)
if (reset)
frame_length_count <= 0;
else if (state == STATE_DEFER)
frame_length_count <= 0;
else if (state == STATE_DATA || state == STATE_PAD)
frame_length_count <= frame_length_count+1;
// Padding Length
always @(posedge clock or posedge reset)
if (reset)
padding_length_count <=0;
else if (state != STATE_PAD)
padding_length_count <= 0;
else
padding_length_count <= padding_length_count + 1;
// Jam Length
always @ (posedge clock or posedge reset)
if (reset)
jam_length_count <= 0;
else if (state == STATE_JAM || next_state == STATE_JAM)
jam_length_count <= jam_length_count + 1;
else
jam_length_count <= 0;
// Inter-Frame Gap
always @ (posedge clock or posedge reset)
if (reset)
inter_frame_gap_count <= 0;
else if (state != STATE_IFG)
inter_frame_gap_count <= 0;
else
inter_frame_gap_count <= inter_frame_gap_count + 1;
// Preamble
always @ (posedge clock or posedge reset)
if (reset)
preamble_count <= 0;
else if (state != STATE_PREAMBLE)
preamble_count <= 0;
else
preamble_count <= preamble_count + 1;
// Retry Counter
always @ (posedge clock or posedge reset)
if (reset)
retry_count <= 0;
else if (state == STATE_NEXT)
retry_count <= 0;
else if (state == STATE_JAM && next_state == STATE_BACKOFF)
retry_count <= retry_count + 1;
// State Output Actions
// FIFO
always @ (*)
if ((state == STATE_DATA ||
state == STATE_SFD ||
state == STATE_JAM_DROP ) &&
next_state != STATE_FCS)
fifo_data_read = 1;
else
fifo_data_read = 0;
always @ (state)
if (state == STATE_JAM)
fifo_retry = 1;
else
fifo_retry = 0;
// Transmit Enable
always @(prev_state)
if (prev_state == STATE_PREAMBLE ||
prev_state == STATE_SFD ||
prev_state == STATE_DATA ||
prev_state == STATE_FCS ||
prev_state == STATE_PAD ||
prev_state == STATE_JAM )
tx_enable <= 1;
else
tx_enable <= 0;
reg [7:0] tx_data_tmp;
// Transmit Data
always @(posedge clock)
case (state)
STATE_PREAMBLE:
tx_data_tmp <= 8'h55;
STATE_SFD:
tx_data_tmp <= 8'hD5;
STATE_DATA:
tx_data_tmp <= fifo_data;
STATE_PAD:
tx_data_tmp <= 8'h00;
STATE_JAM:
tx_data_tmp <= 8'h01;
STATE_FCS:
$display("CRC: %x", ~crc_rev);
//tx_data <= ~crc_rev[crc_index+:8];
default:
tx_data_tmp <= 8'b00;
endcase
always @(posedge clock)
if (prev_state == STATE_FCS)
tx_data <= ~crc_rev[crc_index+:8];
else
tx_data <= tx_data_tmp;
always @(posedge clock)
if(prev_state == STATE_FCS)
crc_index <= crc_index + 8;
else
crc_index <= 0;
// CRC
always @(state)
if (state == STATE_SFD)
crc_init = 1;
else
crc_init = 0;
reg crc_enable_tmp;
always @(state)
if (state == STATE_DATA || state == STATE_PAD)
crc_enable_tmp = 1;
else
crc_enable_tmp = 0;
always @ (posedge clock)
crc_enable <= crc_enable_tmp;
// Random Calculation for Backoff
always @(state or next_state)
if (state == STATE_JAM && next_state == STATE_BACKOFF)
random_init = 1;
else
random_init = 0;
// Submodule Initialisation
// CRC
crc #( .POLYNOMIAL(CRC_POLYNOMIAL),
.DATA_WIDTH(8),
.CRC_WIDTH(32),
.SEED(CRC_SEED))
U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(tx_data_tmp),
.data_enable(crc_enable),
.crc_out(crc_out)
);
random_gen U_random_gen(
.reset(reset),
.clock(clock),
.init(random_init),
.retry_count(retry_count),
.trigger(random_trigger)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:46:06 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_axi_intc_0/system_microblaze_0_axi_intc_0_sim_netlist.v
// Design : system_microblaze_0_axi_intc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_microblaze_0_axi_intc_0,axi_intc,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_intc,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_microblaze_0_axi_intc_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
intr,
processor_clk,
processor_rst,
irq,
processor_ack,
interrupt_address);
(* x_interface_info = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 s_resetn RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT" *) input [6:0]intr;
(* x_interface_info = "xilinx.com:signal:clock:1.0 proc_clock CLK" *) input processor_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 proc_reset RST" *) input processor_rst;
(* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT" *) output irq;
(* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 interrupt ACK" *) input [1:0]processor_ack;
(* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 interrupt ADDRESS" *) output [31:0]interrupt_address;
wire [31:0]interrupt_address;
wire [6:0]intr;
wire irq;
wire [1:0]processor_ack;
wire processor_clk;
wire processor_rst;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [1:0]NLW_U0_processor_ack_out_UNCONNECTED;
(* C_ASYNC_INTR = "-62" *)
(* C_CASCADE_MASTER = "0" *)
(* C_DISABLE_SYNCHRONIZERS = "0" *)
(* C_ENABLE_ASYNC = "0" *)
(* C_EN_CASCADE_MODE = "0" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_CIE = "1" *)
(* C_HAS_FAST = "1" *)
(* C_HAS_ILR = "0" *)
(* C_HAS_IPR = "1" *)
(* C_HAS_IVR = "1" *)
(* C_HAS_SIE = "1" *)
(* C_INSTANCE = "system_microblaze_0_axi_intc_0" *)
(* C_IRQ_ACTIVE = "1'b1" *)
(* C_IRQ_IS_LEVEL = "1" *)
(* C_IVAR_RESET_VALUE = "16" *)
(* C_KIND_OF_EDGE = "-1" *)
(* C_KIND_OF_INTR = "-78" *)
(* C_KIND_OF_LVL = "-1" *)
(* C_MB_CLK_NOT_CONNECTED = "1" *)
(* C_NUM_INTR_INPUTS = "7" *)
(* C_NUM_SW_INTR = "0" *)
(* C_NUM_SYNC_FF = "2" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* hdl = "VHDL" *)
(* imp_netlist = "TRUE" *)
(* ip_group = "LOGICORE" *)
(* iptype = "PERIPHERAL" *)
(* run_ngcbuild = "TRUE" *)
(* style = "HDL" *)
system_microblaze_0_axi_intc_0_axi_intc U0
(.interrupt_address(interrupt_address),
.interrupt_address_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.intr(intr),
.irq(irq),
.irq_in(1'b0),
.processor_ack(processor_ack),
.processor_ack_out(NLW_U0_processor_ack_out_UNCONNECTED[1:0]),
.processor_clk(processor_clk),
.processor_rst(processor_rst),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module system_microblaze_0_axi_intc_0_address_decoder
(p_17_in,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
ip2bus_wrack_prev2,
Or128_vec2stdlogic,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ,
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ,
bus2ip_wrce__0,
bus2ip_wrce,
D,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ,
\mer_int_reg[0] ,
\mer_int_reg[1] ,
Q,
s_axi_aclk,
ip2bus_wrack_int_d1,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ,
p_0_in2_in,
p_0_in5_in,
p_0_in8_in,
p_0_in11_in,
p_0_in14_in,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ,
is_write_reg,
ip2bus_wrack,
is_read,
ip2bus_rdack,
s_axi_aresetn,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
\bus2ip_addr_i_reg[8] ,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0 ,
\bus2ip_addr_i_reg[5] ,
\Douta_reg[31] ,
\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1] ,
\bus2ip_addr_i_reg[3] ,
\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2] ,
\bus2ip_addr_i_reg[2] ,
\bus2ip_addr_i_reg[3]_0 ,
\bus2ip_addr_i_reg[5]_0 ,
\bus2ip_addr_i_reg[3]_1 ,
\bus2ip_addr_i_reg[5]_1 ,
\bus2ip_addr_i_reg[3]_2 ,
\bus2ip_addr_i_reg[5]_2 ,
\bus2ip_addr_i_reg[3]_3 ,
\bus2ip_addr_i_reg[5]_3 ,
\bus2ip_addr_i_reg[6] ,
ip2bus_rdack_int_d1,
s_axi_wdata,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 ,
p_0_in118_in,
p_0_in107_in,
p_0_in96_in,
p_0_in85_in,
p_0_in74_in,
p_0_in64_in,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ,
p_0_in59_in,
p_0_in57_in,
p_0_in55_in,
p_0_in53_in,
p_0_in51_in,
p_0_in49_in,
\mer_int_reg[0]_0 ,
p_0_in,
bus2ip_rnw_i_reg);
output p_17_in;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output ip2bus_wrack_prev2;
output Or128_vec2stdlogic;
output \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ;
output \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ;
output \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ;
output \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ;
output \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ;
output \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ;
output \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output [31:0]D;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ;
output \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ;
output \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ;
output \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ;
output \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ;
output \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ;
output \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ;
output \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ;
output \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ;
output \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ;
output \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ;
output \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ;
output \mer_int_reg[0] ;
output \mer_int_reg[1] ;
input Q;
input s_axi_aclk;
input ip2bus_wrack_int_d1;
input \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ;
input p_0_in2_in;
input p_0_in5_in;
input p_0_in8_in;
input p_0_in11_in;
input p_0_in14_in;
input \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ;
input is_write_reg;
input ip2bus_wrack;
input is_read;
input ip2bus_rdack;
input s_axi_aresetn;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input [6:0]\bus2ip_addr_i_reg[8] ;
input \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0 ;
input \bus2ip_addr_i_reg[5] ;
input [31:0]\Douta_reg[31] ;
input \REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1] ;
input \bus2ip_addr_i_reg[3] ;
input \REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2] ;
input \bus2ip_addr_i_reg[2] ;
input \bus2ip_addr_i_reg[3]_0 ;
input \bus2ip_addr_i_reg[5]_0 ;
input \bus2ip_addr_i_reg[3]_1 ;
input \bus2ip_addr_i_reg[5]_1 ;
input \bus2ip_addr_i_reg[3]_2 ;
input \bus2ip_addr_i_reg[5]_2 ;
input \bus2ip_addr_i_reg[3]_3 ;
input \bus2ip_addr_i_reg[5]_3 ;
input \bus2ip_addr_i_reg[6] ;
input ip2bus_rdack_int_d1;
input [6:0]s_axi_wdata;
input \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 ;
input p_0_in118_in;
input p_0_in107_in;
input p_0_in96_in;
input p_0_in85_in;
input p_0_in74_in;
input p_0_in64_in;
input \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
input p_0_in59_in;
input p_0_in57_in;
input p_0_in55_in;
input p_0_in53_in;
input p_0_in51_in;
input p_0_in49_in;
input \mer_int_reg[0]_0 ;
input p_0_in;
input bus2ip_rnw_i_reg;
wire Bus_RNW_reg_i_1_n_0;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ;
wire \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ;
wire \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ;
wire \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ;
wire \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ;
wire \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ;
wire [31:0]D;
wire [31:0]\Douta_reg[31] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire Or128_vec2stdlogic;
wire Or128_vec2stdlogic19_out;
wire Q;
wire \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ;
wire \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0 ;
wire \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ;
wire \REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1] ;
wire \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ;
wire \REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2] ;
wire \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ;
wire \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ;
wire \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ;
wire \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ;
wire \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 ;
wire \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ;
wire \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ;
wire \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ;
wire \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ;
wire \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ;
wire \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ;
wire \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[3] ;
wire \bus2ip_addr_i_reg[3]_0 ;
wire \bus2ip_addr_i_reg[3]_1 ;
wire \bus2ip_addr_i_reg[3]_2 ;
wire \bus2ip_addr_i_reg[3]_3 ;
wire \bus2ip_addr_i_reg[5] ;
wire \bus2ip_addr_i_reg[5]_0 ;
wire \bus2ip_addr_i_reg[5]_1 ;
wire \bus2ip_addr_i_reg[5]_2 ;
wire \bus2ip_addr_i_reg[5]_3 ;
wire \bus2ip_addr_i_reg[6] ;
wire [6:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire cs_ce_clr;
wire eqOp__2;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_int_d1_i_2_n_0;
wire ip2bus_wrack_int_d1_i_3_n_0;
wire ip2bus_wrack_int_d1_i_4_n_0;
wire ip2bus_wrack_int_d1_i_5_n_0;
wire ip2bus_wrack_prev2;
wire is_read;
wire is_write_reg;
wire \mer_int_reg[0] ;
wire \mer_int_reg[0]_0 ;
wire \mer_int_reg[1] ;
wire p_0_in;
wire p_0_in107_in;
wire p_0_in118_in;
wire p_0_in11_in;
wire p_0_in14_in;
wire p_0_in2_in;
wire p_0_in49_in;
wire p_0_in51_in;
wire p_0_in53_in;
wire p_0_in55_in;
wire p_0_in57_in;
wire p_0_in59_in;
wire p_0_in5_in;
wire p_0_in64_in;
wire p_0_in74_in;
wire p_0_in85_in;
wire p_0_in8_in;
wire p_0_in96_in;
wire p_10_in;
wire p_10_out;
wire p_11_in;
wire p_11_out;
wire p_12_in;
wire p_13_in;
wire p_13_out;
wire p_14_in;
wire p_14_out;
wire p_15_in;
wire p_15_out;
wire p_16_in;
wire p_17_in;
wire p_1_out;
wire p_2_in;
wire p_2_out;
wire p_3_in;
wire p_3_out;
wire p_4_in;
wire p_5_in;
wire p_5_out;
wire p_6_in;
wire p_6_out;
wire p_7_in;
wire p_7_out;
wire p_8_in;
wire p_8_out;
wire p_9_in;
wire p_9_out;
wire pselect_hit_i_0;
wire pselect_hit_i_1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata_i[31]_i_3_n_0 ;
wire \s_axi_rdata_i[6]_i_4_n_0 ;
wire \s_axi_rdata_i[6]_i_5_n_0 ;
wire [6:0]s_axi_wdata;
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(Q),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.R(1'b0));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[0].cie[0]_i_1
(.I0(s_axi_aresetn),
.I1(\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(p_12_in),
.I4(s_axi_wdata[0]),
.O(\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[1].cie[1]_i_1
(.I0(s_axi_aresetn),
.I1(p_0_in59_in),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(p_12_in),
.I4(s_axi_wdata[1]),
.O(\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[2].cie[2]_i_1
(.I0(s_axi_aresetn),
.I1(p_0_in57_in),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(p_12_in),
.I4(s_axi_wdata[2]),
.O(\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[3].cie[3]_i_1
(.I0(s_axi_aresetn),
.I1(p_0_in55_in),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(p_12_in),
.I4(s_axi_wdata[3]),
.O(\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[4].cie[4]_i_1
(.I0(s_axi_aresetn),
.I1(p_0_in53_in),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(p_12_in),
.I4(s_axi_wdata[4]),
.O(\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[5].cie[5]_i_1
(.I0(s_axi_aresetn),
.I1(p_0_in51_in),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(p_12_in),
.I4(s_axi_wdata[5]),
.O(\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[6].cie[6]_i_1
(.I0(s_axi_aresetn),
.I1(p_0_in49_in),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(p_12_in),
.I4(s_axi_wdata[6]),
.O(\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h02))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.O(\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ),
.Q(p_17_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h20))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.O(p_5_out));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi_aclk),
.CE(Q),
.D(p_5_out),
.Q(p_7_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h80))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.O(\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000001000000000))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(\bus2ip_addr_i_reg[8] [4]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [3]),
.O(\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0 ),
.Q(p_6_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0002))
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.I3(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_3_out));
FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]
(.C(s_axi_aclk),
.CE(Q),
.D(p_3_out),
.Q(p_5_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0008))
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_2_out));
FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]
(.C(s_axi_aclk),
.CE(Q),
.D(p_2_out),
.Q(p_4_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0008))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.I3(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_1_out));
FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]
(.C(s_axi_aclk),
.CE(Q),
.D(p_1_out),
.Q(p_3_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0080))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_15_out));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFFEFFFFF))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2
(.I0(\bus2ip_addr_i_reg[8] [5]),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[8] [4]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]
(.C(s_axi_aclk),
.CE(Q),
.D(p_15_out),
.Q(p_2_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFFFFFCF8FFFFFFFF))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1
(.I0(is_write_reg),
.I1(eqOp__2),
.I2(ip2bus_wrack),
.I3(is_read),
.I4(ip2bus_rdack),
.I5(s_axi_aresetn),
.O(cs_ce_clr));
LUT3 #(
.INIT(8'h40))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_2
(.I0(\bus2ip_addr_i_reg[8] [5]),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(Q),
.O(pselect_hit_i_0));
LUT4 #(
.INIT(16'h0100))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.O(eqOp__2));
FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]
(.C(s_axi_aclk),
.CE(Q),
.D(pselect_hit_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'h20))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.O(p_14_out));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(p_14_out),
.Q(p_16_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h20))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.O(p_13_out));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(p_13_out),
.Q(p_15_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h80))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(\bus2ip_addr_i_reg[8] [4]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[8] [6]),
.I4(\bus2ip_addr_i_reg[8] [5]),
.I5(\bus2ip_addr_i_reg[8] [3]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ),
.Q(p_14_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0001))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.I3(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_11_out));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(Q),
.D(p_11_out),
.Q(p_13_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0004))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_10_out));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(Q),
.D(p_10_out),
.Q(p_12_in),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h00080000))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.I3(\bus2ip_addr_i_reg[8] [3]),
.I4(pselect_hit_i_1),
.O(p_9_out));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0004))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2
(.I0(\bus2ip_addr_i_reg[8] [4]),
.I1(Q),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [5]),
.O(pselect_hit_i_1));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(Q),
.D(p_9_out),
.Q(p_11_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0040))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_8_out));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(Q),
.D(p_8_out),
.Q(p_10_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h02))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.O(p_7_out));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi_aclk),
.CE(Q),
.D(p_7_out),
.Q(p_9_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h20))
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.O(p_6_out));
FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]
(.C(s_axi_aclk),
.CE(Q),
.D(p_6_out),
.Q(p_8_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h04))
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_2
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_14_in),
.I2(\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ),
.O(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\REG_GEN[0].IMR_FAST_MODE_GEN.imr[0]_i_1
(.I0(p_9_in),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.O(bus2ip_wrce[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h2))
\REG_GEN[0].ier[0]_i_2
(.I0(p_15_in),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.O(bus2ip_wrce__0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h04))
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_2
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_14_in),
.I2(p_0_in14_in),
.O(\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h04))
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_2
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_14_in),
.I2(p_0_in11_in),
.O(\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h04))
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_2
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_14_in),
.I2(p_0_in8_in),
.O(\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h04))
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_2
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_14_in),
.I2(p_0_in5_in),
.O(\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h04))
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_2
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_14_in),
.I2(p_0_in2_in),
.O(\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h04))
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_2
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_14_in),
.I2(\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ),
.O(\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[0].sie[0]_i_1
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_13_in),
.I2(s_axi_wdata[0]),
.I3(s_axi_aresetn),
.I4(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 ),
.O(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[1].sie[1]_i_1
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_13_in),
.I2(s_axi_wdata[1]),
.I3(s_axi_aresetn),
.I4(p_0_in118_in),
.O(\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[2].sie[2]_i_1
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_13_in),
.I2(s_axi_wdata[2]),
.I3(s_axi_aresetn),
.I4(p_0_in107_in),
.O(\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[3].sie[3]_i_1
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_13_in),
.I2(s_axi_wdata[3]),
.I3(s_axi_aresetn),
.I4(p_0_in96_in),
.O(\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[4].sie[4]_i_1
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_13_in),
.I2(s_axi_wdata[4]),
.I3(s_axi_aresetn),
.I4(p_0_in85_in),
.O(\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[5].sie[5]_i_1
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_13_in),
.I2(s_axi_wdata[5]),
.I3(s_axi_aresetn),
.I4(p_0_in74_in),
.O(\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[6].sie[6]_i_1
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_13_in),
.I2(s_axi_wdata[6]),
.I3(s_axi_aresetn),
.I4(p_0_in64_in),
.O(\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ));
LUT6 #(
.INIT(64'h00000000FFFFCCC8))
ip2bus_rdack_i_1
(.I0(p_14_in),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(ip2bus_wrack_int_d1_i_4_n_0),
.I4(\s_axi_rdata_i[31]_i_3_n_0 ),
.I5(ip2bus_rdack_int_d1),
.O(ip2bus_rdack_prev2));
LUT5 #(
.INIT(32'hFFAAFEAA))
ip2bus_rdack_int_d1_i_1
(.I0(\s_axi_rdata_i[31]_i_3_n_0 ),
.I1(ip2bus_wrack_int_d1_i_4_n_0),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I4(p_14_in),
.O(Or128_vec2stdlogic19_out));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h0000FF32))
ip2bus_wrack_i_1
(.I0(ip2bus_wrack_int_d1_i_4_n_0),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(ip2bus_wrack_int_d1_i_2_n_0),
.I4(ip2bus_wrack_int_d1),
.O(ip2bus_wrack_prev2));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAFAE))
ip2bus_wrack_int_d1_i_1
(.I0(ip2bus_wrack_int_d1_i_2_n_0),
.I1(ip2bus_wrack_int_d1_i_3_n_0),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(ip2bus_wrack_int_d1_i_4_n_0),
.O(Or128_vec2stdlogic));
LUT5 #(
.INIT(32'h00FF00FE))
ip2bus_wrack_int_d1_i_2
(.I0(p_14_in),
.I1(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I2(p_10_in),
.I3(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I4(p_15_in),
.O(ip2bus_wrack_int_d1_i_2_n_0));
LUT5 #(
.INIT(32'hFFFFFFFE))
ip2bus_wrack_int_d1_i_3
(.I0(p_16_in),
.I1(p_9_in),
.I2(p_17_in),
.I3(p_8_in),
.I4(p_11_in),
.O(ip2bus_wrack_int_d1_i_3_n_0));
LUT5 #(
.INIT(32'hFFFFFFFE))
ip2bus_wrack_int_d1_i_4
(.I0(p_5_in),
.I1(p_4_in),
.I2(p_7_in),
.I3(p_6_in),
.I4(ip2bus_wrack_int_d1_i_5_n_0),
.O(ip2bus_wrack_int_d1_i_4_n_0));
LUT4 #(
.INIT(16'hFFFE))
ip2bus_wrack_int_d1_i_5
(.I0(p_2_in),
.I1(p_3_in),
.I2(p_13_in),
.I3(p_12_in),
.O(ip2bus_wrack_int_d1_i_5_n_0));
LUT4 #(
.INIT(16'hFB08))
\mer_int[0]_i_1
(.I0(s_axi_wdata[0]),
.I1(p_10_in),
.I2(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I3(\mer_int_reg[0]_0 ),
.O(\mer_int_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFF20))
\mer_int[1]_i_1
(.I0(s_axi_wdata[1]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(p_10_in),
.I3(p_0_in),
.O(\mer_int_reg[1] ));
LUT2 #(
.INIT(4'h2))
ram_reg_0_15_0_0_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.O(bus2ip_wrce[0]));
LUT5 #(
.INIT(32'hFFE0E0E0))
\s_axi_rdata_i[0]_i_1
(.I0(\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[5] ),
.I2(\s_axi_rdata_i[6]_i_4_n_0 ),
.I3(\Douta_reg[31] [0]),
.I4(\s_axi_rdata_i[6]_i_5_n_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[10]_i_1
(.I0(\Douta_reg[31] [10]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[10]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[11]_i_1
(.I0(\Douta_reg[31] [11]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[11]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[12]_i_1
(.I0(\Douta_reg[31] [12]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[12]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[13]_i_1
(.I0(\Douta_reg[31] [13]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[13]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[14]_i_1
(.I0(\Douta_reg[31] [14]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[14]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[15]_i_1
(.I0(\Douta_reg[31] [15]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[15]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[16]_i_1
(.I0(\Douta_reg[31] [16]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[16]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[17]_i_1
(.I0(\Douta_reg[31] [17]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[17]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[18]_i_1
(.I0(\Douta_reg[31] [18]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[18]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[19]_i_1
(.I0(\Douta_reg[31] [19]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[19]));
LUT5 #(
.INIT(32'hFFE0E0E0))
\s_axi_rdata_i[1]_i_1
(.I0(\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1] ),
.I1(\bus2ip_addr_i_reg[5] ),
.I2(\s_axi_rdata_i[6]_i_4_n_0 ),
.I3(\Douta_reg[31] [1]),
.I4(\s_axi_rdata_i[6]_i_5_n_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[20]_i_1
(.I0(\Douta_reg[31] [20]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[20]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[21]_i_1
(.I0(\Douta_reg[31] [21]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[21]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[22]_i_1
(.I0(\Douta_reg[31] [22]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[22]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[23]_i_1
(.I0(\Douta_reg[31] [23]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[23]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[24]_i_1
(.I0(\Douta_reg[31] [24]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[24]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[25]_i_1
(.I0(\Douta_reg[31] [25]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[25]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[26]_i_1
(.I0(\Douta_reg[31] [26]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[26]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[27]_i_1
(.I0(\Douta_reg[31] [27]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[27]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[28]_i_1
(.I0(\Douta_reg[31] [28]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[28]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[29]_i_1
(.I0(\Douta_reg[31] [29]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[29]));
LUT6 #(
.INIT(64'hFFFFFE00FE00FE00))
\s_axi_rdata_i[2]_i_1
(.I0(\bus2ip_addr_i_reg[3] ),
.I1(\bus2ip_addr_i_reg[5] ),
.I2(\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2] ),
.I3(\s_axi_rdata_i[6]_i_4_n_0 ),
.I4(\Douta_reg[31] [2]),
.I5(\s_axi_rdata_i[6]_i_5_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[30]_i_1
(.I0(\Douta_reg[31] [30]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[30]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[31]_i_2
(.I0(\Douta_reg[31] [31]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[31]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hFE00))
\s_axi_rdata_i[31]_i_3
(.I0(ip2bus_wrack_int_d1_i_3_n_0),
.I1(p_10_in),
.I2(p_15_in),
.I3(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.O(\s_axi_rdata_i[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFE00FE00FE00))
\s_axi_rdata_i[3]_i_1
(.I0(\bus2ip_addr_i_reg[2] ),
.I1(\bus2ip_addr_i_reg[3]_0 ),
.I2(\bus2ip_addr_i_reg[5]_0 ),
.I3(\s_axi_rdata_i[6]_i_4_n_0 ),
.I4(\Douta_reg[31] [3]),
.I5(\s_axi_rdata_i[6]_i_5_n_0 ),
.O(D[3]));
LUT6 #(
.INIT(64'hFFFFFE00FE00FE00))
\s_axi_rdata_i[4]_i_1
(.I0(\bus2ip_addr_i_reg[2] ),
.I1(\bus2ip_addr_i_reg[3]_1 ),
.I2(\bus2ip_addr_i_reg[5]_1 ),
.I3(\s_axi_rdata_i[6]_i_4_n_0 ),
.I4(\Douta_reg[31] [4]),
.I5(\s_axi_rdata_i[6]_i_5_n_0 ),
.O(D[4]));
LUT6 #(
.INIT(64'hFFFFFE00FE00FE00))
\s_axi_rdata_i[5]_i_1
(.I0(\bus2ip_addr_i_reg[2] ),
.I1(\bus2ip_addr_i_reg[3]_2 ),
.I2(\bus2ip_addr_i_reg[5]_2 ),
.I3(\s_axi_rdata_i[6]_i_4_n_0 ),
.I4(\Douta_reg[31] [5]),
.I5(\s_axi_rdata_i[6]_i_5_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hFFFFFE00FE00FE00))
\s_axi_rdata_i[6]_i_1
(.I0(\bus2ip_addr_i_reg[2] ),
.I1(\bus2ip_addr_i_reg[3]_3 ),
.I2(\bus2ip_addr_i_reg[5]_3 ),
.I3(\s_axi_rdata_i[6]_i_4_n_0 ),
.I4(\Douta_reg[31] [6]),
.I5(\s_axi_rdata_i[6]_i_5_n_0 ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000AAA8))
\s_axi_rdata_i[6]_i_4
(.I0(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I1(p_15_in),
.I2(p_10_in),
.I3(ip2bus_wrack_int_d1_i_3_n_0),
.I4(\bus2ip_addr_i_reg[6] ),
.O(\s_axi_rdata_i[6]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00000008))
\s_axi_rdata_i[6]_i_5
(.I0(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(p_15_in),
.I3(p_10_in),
.I4(ip2bus_wrack_int_d1_i_3_n_0),
.O(\s_axi_rdata_i[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[7]_i_1
(.I0(\Douta_reg[31] [7]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[7]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[8]_i_1
(.I0(\Douta_reg[31] [8]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[8]));
LUT6 #(
.INIT(64'h00800080FF800080))
\s_axi_rdata_i[9]_i_1
(.I0(\Douta_reg[31] [9]),
.I1(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.I2(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I3(\s_axi_rdata_i[31]_i_3_n_0 ),
.I4(\bus2ip_addr_i_reg[2] ),
.I5(\bus2ip_addr_i_reg[6] ),
.O(D[9]));
endmodule
(* C_ASYNC_INTR = "-62" *) (* C_CASCADE_MASTER = "0" *) (* C_DISABLE_SYNCHRONIZERS = "0" *)
(* C_ENABLE_ASYNC = "0" *) (* C_EN_CASCADE_MODE = "0" *) (* C_FAMILY = "artix7" *)
(* C_HAS_CIE = "1" *) (* C_HAS_FAST = "1" *) (* C_HAS_ILR = "0" *)
(* C_HAS_IPR = "1" *) (* C_HAS_IVR = "1" *) (* C_HAS_SIE = "1" *)
(* C_INSTANCE = "system_microblaze_0_axi_intc_0" *) (* C_IRQ_ACTIVE = "1'b1" *) (* C_IRQ_IS_LEVEL = "1" *)
(* C_IVAR_RESET_VALUE = "16" *) (* C_KIND_OF_EDGE = "-1" *) (* C_KIND_OF_INTR = "-78" *)
(* C_KIND_OF_LVL = "-1" *) (* C_MB_CLK_NOT_CONNECTED = "1" *) (* C_NUM_INTR_INPUTS = "7" *)
(* C_NUM_SW_INTR = "0" *) (* C_NUM_SYNC_FF = "2" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* ORIG_REF_NAME = "axi_intc" *) (* hdl = "VHDL" *)
(* imp_netlist = "TRUE" *) (* ip_group = "LOGICORE" *) (* iptype = "PERIPHERAL" *)
(* run_ngcbuild = "TRUE" *) (* style = "HDL" *)
module system_microblaze_0_axi_intc_0_axi_intc
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
intr,
processor_clk,
processor_rst,
irq,
processor_ack,
interrupt_address,
irq_in,
interrupt_address_in,
processor_ack_out);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rstn" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* BUFFER_TYPE = "none" *) input [6:0]intr;
input processor_clk;
input processor_rst;
output irq;
input [1:0]processor_ack;
output [31:0]interrupt_address;
input irq_in;
input [31:0]interrupt_address_in;
output [1:0]processor_ack_out;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_10;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire AXI_LITE_IPIF_I_n_26;
wire AXI_LITE_IPIF_I_n_27;
wire AXI_LITE_IPIF_I_n_28;
wire AXI_LITE_IPIF_I_n_29;
wire AXI_LITE_IPIF_I_n_30;
wire AXI_LITE_IPIF_I_n_31;
wire AXI_LITE_IPIF_I_n_32;
wire AXI_LITE_IPIF_I_n_33;
wire AXI_LITE_IPIF_I_n_34;
wire AXI_LITE_IPIF_I_n_35;
wire AXI_LITE_IPIF_I_n_36;
wire AXI_LITE_IPIF_I_n_37;
wire AXI_LITE_IPIF_I_n_38;
wire AXI_LITE_IPIF_I_n_39;
wire AXI_LITE_IPIF_I_n_40;
wire AXI_LITE_IPIF_I_n_41;
wire AXI_LITE_IPIF_I_n_8;
wire AXI_LITE_IPIF_I_n_9;
wire [31:0]Douta;
wire INTC_CORE_I_n_0;
wire INTC_CORE_I_n_16;
wire INTC_CORE_I_n_23;
wire INTC_CORE_I_n_30;
wire INTC_CORE_I_n_32;
wire INTC_CORE_I_n_39;
wire INTC_CORE_I_n_40;
wire INTC_CORE_I_n_41;
wire INTC_CORE_I_n_42;
wire INTC_CORE_I_n_7;
wire INTC_CORE_I_n_8;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ;
wire Or128_vec2stdlogic;
wire Or128_vec2stdlogic19_out;
wire [5:2]bus2ip_addr;
wire [8:0]bus2ip_wrce;
wire [14:14]bus2ip_wrce__0;
wire [31:0]interrupt_address;
wire [6:0]intr;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_prev2;
wire [6:0]ipr;
wire irq;
wire p_0_in;
wire p_0_in107_in;
wire p_0_in118_in;
wire p_0_in11_in;
wire p_0_in14_in;
wire p_0_in19_in;
wire p_0_in20_in;
wire p_0_in22_in;
wire p_0_in24_in;
wire p_0_in26_in;
wire p_0_in28_in;
wire p_0_in2_in;
wire p_0_in49_in;
wire p_0_in51_in;
wire p_0_in53_in;
wire p_0_in55_in;
wire p_0_in57_in;
wire p_0_in59_in;
wire p_0_in5_in;
wire p_0_in64_in;
wire p_0_in74_in;
wire p_0_in85_in;
wire p_0_in8_in;
wire p_0_in96_in;
wire p_0_in_0;
wire p_1_in;
wire p_1_in21_in;
wire p_1_in23_in;
wire p_1_in25_in;
wire p_1_in27_in;
wire p_1_in29_in;
wire [1:0]processor_ack;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rstn" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:1]\^s_axi_bresp ;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:1]\^s_axi_rresp ;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign processor_ack_out[1] = \<const0> ;
assign processor_ack_out[0] = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \^s_axi_bresp [1];
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rresp[1] = \^s_axi_rresp [1];
assign s_axi_rresp[0] = \<const0> ;
system_microblaze_0_axi_intc_0_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (AXI_LITE_IPIF_I_n_33),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 (INTC_CORE_I_n_23),
.\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] (AXI_LITE_IPIF_I_n_34),
.\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] (AXI_LITE_IPIF_I_n_35),
.\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] (AXI_LITE_IPIF_I_n_36),
.\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] (AXI_LITE_IPIF_I_n_37),
.\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] (AXI_LITE_IPIF_I_n_38),
.\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] (AXI_LITE_IPIF_I_n_39),
.\Douta_reg[31] (Douta),
.\IPR_GEN.ipr_reg[6] (ipr),
.\IVR_GEN.ivr_reg[0] (INTC_CORE_I_n_39),
.\IVR_GEN.ivr_reg[0]_0 (INTC_CORE_I_n_40),
.\IVR_GEN.ivr_reg[1] (INTC_CORE_I_n_41),
.\IVR_GEN.ivr_reg[2] (INTC_CORE_I_n_42),
.Or128_vec2stdlogic(Or128_vec2stdlogic),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.Q(bus2ip_addr),
.\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] (AXI_LITE_IPIF_I_n_14),
.\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] (INTC_CORE_I_n_0),
.\REG_GEN[0].ier_reg[0] (INTC_CORE_I_n_8),
.\REG_GEN[0].isr_reg[0] (INTC_CORE_I_n_32),
.\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] (AXI_LITE_IPIF_I_n_13),
.\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] (AXI_LITE_IPIF_I_n_12),
.\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] (AXI_LITE_IPIF_I_n_11),
.\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] (AXI_LITE_IPIF_I_n_10),
.\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] (AXI_LITE_IPIF_I_n_9),
.\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] (AXI_LITE_IPIF_I_n_8),
.\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] (INTC_CORE_I_n_7),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (AXI_LITE_IPIF_I_n_26),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 (INTC_CORE_I_n_16),
.\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] (AXI_LITE_IPIF_I_n_27),
.\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] (AXI_LITE_IPIF_I_n_28),
.\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] (AXI_LITE_IPIF_I_n_29),
.\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] (AXI_LITE_IPIF_I_n_30),
.\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] (AXI_LITE_IPIF_I_n_31),
.\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] (AXI_LITE_IPIF_I_n_32),
.SS(p_0_in),
.bus2ip_wrce({bus2ip_wrce[8],bus2ip_wrce[0]}),
.bus2ip_wrce__0(bus2ip_wrce__0),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.\mer_int_reg[0] (AXI_LITE_IPIF_I_n_40),
.\mer_int_reg[0]_0 (INTC_CORE_I_n_30),
.\mer_int_reg[1] (AXI_LITE_IPIF_I_n_41),
.p_0_in(p_0_in_0),
.p_0_in107_in(p_0_in107_in),
.p_0_in118_in(p_0_in118_in),
.p_0_in11_in(p_0_in11_in),
.p_0_in14_in(p_0_in14_in),
.p_0_in19_in(p_0_in19_in),
.p_0_in20_in(p_0_in20_in),
.p_0_in22_in(p_0_in22_in),
.p_0_in24_in(p_0_in24_in),
.p_0_in26_in(p_0_in26_in),
.p_0_in28_in(p_0_in28_in),
.p_0_in2_in(p_0_in2_in),
.p_0_in49_in(p_0_in49_in),
.p_0_in51_in(p_0_in51_in),
.p_0_in53_in(p_0_in53_in),
.p_0_in55_in(p_0_in55_in),
.p_0_in57_in(p_0_in57_in),
.p_0_in59_in(p_0_in59_in),
.p_0_in5_in(p_0_in5_in),
.p_0_in64_in(p_0_in64_in),
.p_0_in74_in(p_0_in74_in),
.p_0_in85_in(p_0_in85_in),
.p_0_in8_in(p_0_in8_in),
.p_0_in96_in(p_0_in96_in),
.p_17_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
.p_1_in(p_1_in),
.p_1_in21_in(p_1_in21_in),
.p_1_in23_in(p_1_in23_in),
.p_1_in25_in(p_1_in25_in),
.p_1_in27_in(p_1_in27_in),
.p_1_in29_in(p_1_in29_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[8:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[8:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(\^s_axi_bresp ),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(\^s_axi_rresp ),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata[6:0]),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
system_microblaze_0_axi_intc_0_intc_core INTC_CORE_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_26),
.Bus_RNW_reg_reg_0(AXI_LITE_IPIF_I_n_27),
.Bus_RNW_reg_reg_1(AXI_LITE_IPIF_I_n_28),
.Bus_RNW_reg_reg_10(AXI_LITE_IPIF_I_n_11),
.Bus_RNW_reg_reg_11(AXI_LITE_IPIF_I_n_10),
.Bus_RNW_reg_reg_12(AXI_LITE_IPIF_I_n_9),
.Bus_RNW_reg_reg_13(AXI_LITE_IPIF_I_n_8),
.Bus_RNW_reg_reg_2(AXI_LITE_IPIF_I_n_29),
.Bus_RNW_reg_reg_3(AXI_LITE_IPIF_I_n_30),
.Bus_RNW_reg_reg_4(AXI_LITE_IPIF_I_n_31),
.Bus_RNW_reg_reg_5(AXI_LITE_IPIF_I_n_32),
.Bus_RNW_reg_reg_6(AXI_LITE_IPIF_I_n_41),
.Bus_RNW_reg_reg_7(AXI_LITE_IPIF_I_n_14),
.Bus_RNW_reg_reg_8(AXI_LITE_IPIF_I_n_13),
.Bus_RNW_reg_reg_9(AXI_LITE_IPIF_I_n_12),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 (AXI_LITE_IPIF_I_n_33),
.\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0 (AXI_LITE_IPIF_I_n_34),
.\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0 (AXI_LITE_IPIF_I_n_35),
.\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0 (AXI_LITE_IPIF_I_n_36),
.\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0 (AXI_LITE_IPIF_I_n_37),
.\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0 (AXI_LITE_IPIF_I_n_38),
.\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0 (AXI_LITE_IPIF_I_n_39),
.Douta(Douta),
.\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] (AXI_LITE_IPIF_I_n_40),
.\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0 (INTC_CORE_I_n_41),
.\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 (INTC_CORE_I_n_30),
.\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1 (INTC_CORE_I_n_42),
.\IVR_GEN.ivr_reg[1]_0 (INTC_CORE_I_n_8),
.\IVR_GEN.ivr_reg[1]_1 (INTC_CORE_I_n_32),
.Q(INTC_CORE_I_n_40),
.\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0 (INTC_CORE_I_n_0),
.\REG_GEN[0].ier_reg[0]_0 (INTC_CORE_I_n_16),
.\REG_GEN[0].ier_reg[0]_1 (INTC_CORE_I_n_23),
.\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0 (INTC_CORE_I_n_7),
.SS(p_0_in),
.\bus2ip_addr_i_reg[5] (bus2ip_addr),
.bus2ip_wrce({bus2ip_wrce[8],bus2ip_wrce[0]}),
.bus2ip_wrce__0(bus2ip_wrce__0),
.interrupt_address(interrupt_address),
.intr(intr),
.irq(irq),
.p_0_in(p_0_in_0),
.p_0_in107_in(p_0_in107_in),
.p_0_in118_in(p_0_in118_in),
.p_0_in11_in(p_0_in11_in),
.p_0_in14_in(p_0_in14_in),
.p_0_in19_in(p_0_in19_in),
.p_0_in20_in(p_0_in20_in),
.p_0_in22_in(p_0_in22_in),
.p_0_in24_in(p_0_in24_in),
.p_0_in26_in(p_0_in26_in),
.p_0_in28_in(p_0_in28_in),
.p_0_in2_in(p_0_in2_in),
.p_0_in49_in(p_0_in49_in),
.p_0_in51_in(p_0_in51_in),
.p_0_in53_in(p_0_in53_in),
.p_0_in55_in(p_0_in55_in),
.p_0_in57_in(p_0_in57_in),
.p_0_in59_in(p_0_in59_in),
.p_0_in5_in(p_0_in5_in),
.p_0_in64_in(p_0_in64_in),
.p_0_in74_in(p_0_in74_in),
.p_0_in85_in(p_0_in85_in),
.p_0_in8_in(p_0_in8_in),
.p_0_in96_in(p_0_in96_in),
.p_17_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
.p_1_in(p_1_in),
.p_1_in21_in(p_1_in21_in),
.p_1_in23_in(p_1_in23_in),
.p_1_in25_in(p_1_in25_in),
.p_1_in27_in(p_1_in27_in),
.p_1_in29_in(p_1_in29_in),
.processor_ack(processor_ack),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.\s_axi_rdata_i_reg[3] (INTC_CORE_I_n_39),
.\s_axi_rdata_i_reg[6] (ipr),
.s_axi_wdata(s_axi_wdata));
FDRE ip2bus_rdack_int_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Or128_vec2stdlogic19_out),
.Q(ip2bus_rdack_int_d1),
.R(p_0_in));
FDRE ip2bus_rdack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_prev2),
.Q(ip2bus_rdack),
.R(p_0_in));
FDRE ip2bus_wrack_int_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Or128_vec2stdlogic),
.Q(ip2bus_wrack_int_d1),
.R(p_0_in));
FDRE ip2bus_wrack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_prev2),
.Q(ip2bus_wrack),
.R(p_0_in));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module system_microblaze_0_axi_intc_0_axi_lite_ipif
(p_17_in,
s_axi_rresp,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
ip2bus_wrack_prev2,
Or128_vec2stdlogic,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ,
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ,
s_axi_wready,
s_axi_arready,
bus2ip_wrce__0,
bus2ip_wrce,
Q,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ,
\mer_int_reg[0] ,
\mer_int_reg[1] ,
s_axi_rdata,
SS,
s_axi_aclk,
ip2bus_wrack_int_d1,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ,
p_0_in2_in,
p_0_in5_in,
p_0_in8_in,
p_0_in11_in,
p_0_in14_in,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ,
ip2bus_wrack,
ip2bus_rdack,
s_axi_aresetn,
s_axi_arvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
\Douta_reg[31] ,
\IPR_GEN.ipr_reg[6] ,
\REG_GEN[0].ier_reg[0] ,
\REG_GEN[0].isr_reg[0] ,
p_0_in28_in,
p_1_in29_in,
p_0_in26_in,
p_1_in27_in,
p_0_in24_in,
p_1_in25_in,
p_0_in22_in,
p_1_in23_in,
p_0_in20_in,
p_1_in21_in,
p_0_in19_in,
p_1_in,
\IVR_GEN.ivr_reg[0] ,
\mer_int_reg[0]_0 ,
\IVR_GEN.ivr_reg[0]_0 ,
p_0_in,
\IVR_GEN.ivr_reg[1] ,
\IVR_GEN.ivr_reg[2] ,
ip2bus_rdack_int_d1,
s_axi_wstrb,
s_axi_wdata,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ,
p_0_in118_in,
p_0_in107_in,
p_0_in96_in,
p_0_in85_in,
p_0_in74_in,
p_0_in64_in,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ,
p_0_in59_in,
p_0_in57_in,
p_0_in55_in,
p_0_in53_in,
p_0_in51_in,
p_0_in49_in);
output p_17_in;
output [0:0]s_axi_rresp;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output ip2bus_wrack_prev2;
output Or128_vec2stdlogic;
output \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ;
output \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ;
output \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ;
output \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ;
output \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ;
output \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ;
output \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ;
output s_axi_wready;
output s_axi_arready;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output [3:0]Q;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ;
output \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ;
output \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ;
output \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ;
output \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ;
output \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ;
output \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ;
output \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ;
output \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ;
output \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ;
output \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ;
output \mer_int_reg[0] ;
output \mer_int_reg[1] ;
output [31:0]s_axi_rdata;
input [0:0]SS;
input s_axi_aclk;
input ip2bus_wrack_int_d1;
input \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ;
input p_0_in2_in;
input p_0_in5_in;
input p_0_in8_in;
input p_0_in11_in;
input p_0_in14_in;
input \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ;
input ip2bus_wrack;
input ip2bus_rdack;
input s_axi_aresetn;
input s_axi_arvalid;
input [6:0]s_axi_araddr;
input [6:0]s_axi_awaddr;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input [31:0]\Douta_reg[31] ;
input [6:0]\IPR_GEN.ipr_reg[6] ;
input \REG_GEN[0].ier_reg[0] ;
input \REG_GEN[0].isr_reg[0] ;
input p_0_in28_in;
input p_1_in29_in;
input p_0_in26_in;
input p_1_in27_in;
input p_0_in24_in;
input p_1_in25_in;
input p_0_in22_in;
input p_1_in23_in;
input p_0_in20_in;
input p_1_in21_in;
input p_0_in19_in;
input p_1_in;
input \IVR_GEN.ivr_reg[0] ;
input \mer_int_reg[0]_0 ;
input [0:0]\IVR_GEN.ivr_reg[0]_0 ;
input p_0_in;
input \IVR_GEN.ivr_reg[1] ;
input \IVR_GEN.ivr_reg[2] ;
input ip2bus_rdack_int_d1;
input [3:0]s_axi_wstrb;
input [6:0]s_axi_wdata;
input \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ;
input p_0_in118_in;
input p_0_in107_in;
input p_0_in96_in;
input p_0_in85_in;
input p_0_in74_in;
input p_0_in64_in;
input \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
input p_0_in59_in;
input p_0_in57_in;
input p_0_in55_in;
input p_0_in53_in;
input p_0_in51_in;
input p_0_in49_in;
wire Bus_RNW_reg;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ;
wire \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ;
wire \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ;
wire \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ;
wire \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ;
wire \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ;
wire [31:0]\Douta_reg[31] ;
wire [6:0]\IPR_GEN.ipr_reg[6] ;
wire \IVR_GEN.ivr_reg[0] ;
wire [0:0]\IVR_GEN.ivr_reg[0]_0 ;
wire \IVR_GEN.ivr_reg[1] ;
wire \IVR_GEN.ivr_reg[2] ;
wire Or128_vec2stdlogic;
wire Or128_vec2stdlogic19_out;
wire [3:0]Q;
wire \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ;
wire \REG_GEN[0].ier_reg[0] ;
wire \REG_GEN[0].isr_reg[0] ;
wire \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ;
wire \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ;
wire \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ;
wire \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ;
wire \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ;
wire \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ;
wire \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ;
wire \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ;
wire \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ;
wire \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ;
wire \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ;
wire \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ;
wire \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ;
wire [0:0]SS;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_prev2;
wire \mer_int_reg[0] ;
wire \mer_int_reg[0]_0 ;
wire \mer_int_reg[1] ;
wire p_0_in;
wire p_0_in107_in;
wire p_0_in118_in;
wire p_0_in11_in;
wire p_0_in14_in;
wire p_0_in19_in;
wire p_0_in20_in;
wire p_0_in22_in;
wire p_0_in24_in;
wire p_0_in26_in;
wire p_0_in28_in;
wire p_0_in2_in;
wire p_0_in49_in;
wire p_0_in51_in;
wire p_0_in53_in;
wire p_0_in55_in;
wire p_0_in57_in;
wire p_0_in59_in;
wire p_0_in5_in;
wire p_0_in64_in;
wire p_0_in74_in;
wire p_0_in85_in;
wire p_0_in8_in;
wire p_0_in96_in;
wire p_17_in;
wire p_1_in;
wire p_1_in21_in;
wire p_1_in23_in;
wire p_1_in25_in;
wire p_1_in27_in;
wire p_1_in29_in;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire [6:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
system_microblaze_0_axi_intc_0_slave_attachment I_SLAVE_ATTACHMENT
(.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 (\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ),
.\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] (\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ),
.\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] (\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ),
.\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] (\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ),
.\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] (\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ),
.\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] (\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ),
.\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] (\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ),
.\Douta_reg[31] (\Douta_reg[31] ),
.\IPR_GEN.ipr_reg[6] (\IPR_GEN.ipr_reg[6] ),
.\IVR_GEN.ivr_reg[0] (\IVR_GEN.ivr_reg[0] ),
.\IVR_GEN.ivr_reg[0]_0 (\IVR_GEN.ivr_reg[0]_0 ),
.\IVR_GEN.ivr_reg[1] (\IVR_GEN.ivr_reg[1] ),
.\IVR_GEN.ivr_reg[2] (\IVR_GEN.ivr_reg[2] ),
.Or128_vec2stdlogic(Or128_vec2stdlogic),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.Q(Q),
.\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] (\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ),
.\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] (\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ),
.\REG_GEN[0].ier_reg[0] (\REG_GEN[0].ier_reg[0] ),
.\REG_GEN[0].isr_reg[0] (\REG_GEN[0].isr_reg[0] ),
.\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] (\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ),
.\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] (\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ),
.\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] (\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ),
.\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] (\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ),
.\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] (\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ),
.\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] (\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ),
.\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] (\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (Bus_RNW_reg),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ),
.\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] (\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ),
.\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] (\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ),
.\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] (\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ),
.\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] (\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ),
.\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] (\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ),
.\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] (\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ),
.SS(SS),
.bus2ip_wrce(bus2ip_wrce),
.bus2ip_wrce__0(bus2ip_wrce__0),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.\mer_int_reg[0] (\mer_int_reg[0] ),
.\mer_int_reg[0]_0 (\mer_int_reg[0]_0 ),
.\mer_int_reg[1] (\mer_int_reg[1] ),
.p_0_in(p_0_in),
.p_0_in107_in(p_0_in107_in),
.p_0_in118_in(p_0_in118_in),
.p_0_in11_in(p_0_in11_in),
.p_0_in14_in(p_0_in14_in),
.p_0_in19_in(p_0_in19_in),
.p_0_in20_in(p_0_in20_in),
.p_0_in22_in(p_0_in22_in),
.p_0_in24_in(p_0_in24_in),
.p_0_in26_in(p_0_in26_in),
.p_0_in28_in(p_0_in28_in),
.p_0_in2_in(p_0_in2_in),
.p_0_in49_in(p_0_in49_in),
.p_0_in51_in(p_0_in51_in),
.p_0_in53_in(p_0_in53_in),
.p_0_in55_in(p_0_in55_in),
.p_0_in57_in(p_0_in57_in),
.p_0_in59_in(p_0_in59_in),
.p_0_in5_in(p_0_in5_in),
.p_0_in64_in(p_0_in64_in),
.p_0_in74_in(p_0_in74_in),
.p_0_in85_in(p_0_in85_in),
.p_0_in8_in(p_0_in8_in),
.p_0_in96_in(p_0_in96_in),
.p_17_in(p_17_in),
.p_1_in(p_1_in),
.p_1_in21_in(p_1_in21_in),
.p_1_in23_in(p_1_in23_in),
.p_1_in25_in(p_1_in25_in),
.p_1_in27_in(p_1_in27_in),
.p_1_in29_in(p_1_in29_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "intc_core" *)
module system_microblaze_0_axi_intc_0_intc_core
(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0 ,
SS,
p_0_in14_in,
p_0_in11_in,
p_0_in8_in,
p_0_in5_in,
p_0_in2_in,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0 ,
\IVR_GEN.ivr_reg[1]_0 ,
p_0_in28_in,
p_0_in26_in,
p_0_in24_in,
p_0_in22_in,
p_0_in20_in,
p_0_in19_in,
irq,
\REG_GEN[0].ier_reg[0]_0 ,
p_0_in118_in,
p_0_in107_in,
p_0_in96_in,
p_0_in85_in,
p_0_in74_in,
p_0_in64_in,
\REG_GEN[0].ier_reg[0]_1 ,
p_0_in59_in,
p_0_in57_in,
p_0_in55_in,
p_0_in53_in,
p_0_in51_in,
p_0_in49_in,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ,
p_0_in,
\IVR_GEN.ivr_reg[1]_1 ,
p_1_in29_in,
p_1_in27_in,
p_1_in25_in,
p_1_in23_in,
p_1_in21_in,
p_1_in,
\s_axi_rdata_i_reg[3] ,
Q,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0 ,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1 ,
\s_axi_rdata_i_reg[6] ,
Douta,
interrupt_address,
bus2ip_wrce,
s_axi_wdata,
s_axi_aclk,
intr,
Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0 ,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0 ,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0 ,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0 ,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0 ,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0 ,
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ,
Bus_RNW_reg_reg_6,
s_axi_aresetn,
bus2ip_wrce__0,
\bus2ip_addr_i_reg[5] ,
processor_ack,
Bus_RNW_reg_reg_7,
Bus_RNW_reg_reg_8,
Bus_RNW_reg_reg_9,
Bus_RNW_reg_reg_10,
Bus_RNW_reg_reg_11,
Bus_RNW_reg_reg_12,
Bus_RNW_reg_reg_13,
Bus_RNW_reg,
p_17_in);
output \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0 ;
output [0:0]SS;
output p_0_in14_in;
output p_0_in11_in;
output p_0_in8_in;
output p_0_in5_in;
output p_0_in2_in;
output \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0 ;
output \IVR_GEN.ivr_reg[1]_0 ;
output p_0_in28_in;
output p_0_in26_in;
output p_0_in24_in;
output p_0_in22_in;
output p_0_in20_in;
output p_0_in19_in;
output irq;
output \REG_GEN[0].ier_reg[0]_0 ;
output p_0_in118_in;
output p_0_in107_in;
output p_0_in96_in;
output p_0_in85_in;
output p_0_in74_in;
output p_0_in64_in;
output \REG_GEN[0].ier_reg[0]_1 ;
output p_0_in59_in;
output p_0_in57_in;
output p_0_in55_in;
output p_0_in53_in;
output p_0_in51_in;
output p_0_in49_in;
output \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ;
output p_0_in;
output \IVR_GEN.ivr_reg[1]_1 ;
output p_1_in29_in;
output p_1_in27_in;
output p_1_in25_in;
output p_1_in23_in;
output p_1_in21_in;
output p_1_in;
output \s_axi_rdata_i_reg[3] ;
output [0:0]Q;
output \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0 ;
output \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1 ;
output [6:0]\s_axi_rdata_i_reg[6] ;
output [31:0]Douta;
output [31:0]interrupt_address;
input [1:0]bus2ip_wrce;
input [31:0]s_axi_wdata;
input s_axi_aclk;
input [6:0]intr;
input Bus_RNW_reg_reg;
input Bus_RNW_reg_reg_0;
input Bus_RNW_reg_reg_1;
input Bus_RNW_reg_reg_2;
input Bus_RNW_reg_reg_3;
input Bus_RNW_reg_reg_4;
input Bus_RNW_reg_reg_5;
input \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
input \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0 ;
input \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0 ;
input \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0 ;
input \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0 ;
input \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0 ;
input \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0 ;
input \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
input Bus_RNW_reg_reg_6;
input s_axi_aresetn;
input [0:0]bus2ip_wrce__0;
input [3:0]\bus2ip_addr_i_reg[5] ;
input [1:0]processor_ack;
input Bus_RNW_reg_reg_7;
input Bus_RNW_reg_reg_8;
input Bus_RNW_reg_reg_9;
input Bus_RNW_reg_reg_10;
input Bus_RNW_reg_reg_11;
input Bus_RNW_reg_reg_12;
input Bus_RNW_reg_reg_13;
input Bus_RNW_reg;
input p_17_in;
wire \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0 ;
wire \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0 ;
wire \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0 ;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire Bus_RNW_reg_reg_10;
wire Bus_RNW_reg_reg_11;
wire Bus_RNW_reg_reg_12;
wire Bus_RNW_reg_reg_13;
wire Bus_RNW_reg_reg_2;
wire Bus_RNW_reg_reg_3;
wire Bus_RNW_reg_reg_4;
wire Bus_RNW_reg_reg_5;
wire Bus_RNW_reg_reg_6;
wire Bus_RNW_reg_reg_7;
wire Bus_RNW_reg_reg_8;
wire Bus_RNW_reg_reg_9;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0 ;
wire [31:0]Douta;
wire \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
wire \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ;
wire \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0 ;
wire \INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0 ;
wire \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0 ;
wire \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0 ;
wire \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0 ;
wire \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0 ;
wire \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0 ;
(* async_reg = "true" *) wire \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1] ;
wire \INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0 ;
wire \IPR_GEN.ipr[0]_i_1_n_0 ;
wire \IPR_GEN.ipr[1]_i_1_n_0 ;
wire \IPR_GEN.ipr[2]_i_1_n_0 ;
wire \IPR_GEN.ipr[3]_i_1_n_0 ;
wire \IPR_GEN.ipr[4]_i_1_n_0 ;
wire \IPR_GEN.ipr[5]_i_1_n_0 ;
wire \IPR_GEN.ipr[6]_i_1_n_0 ;
wire \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0 ;
wire \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0 ;
wire \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0 ;
wire \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0] ;
wire \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1] ;
wire \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0 ;
wire \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0 ;
wire \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0 ;
wire \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0 ;
wire \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0 ;
wire \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ;
wire \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1 ;
wire \IVR_GEN.ivr[0]_i_2_n_0 ;
wire \IVR_GEN.ivr[1]_i_1_n_0 ;
wire \IVR_GEN.ivr[1]_i_2_n_0 ;
wire \IVR_GEN.ivr[1]_i_3_n_0 ;
wire \IVR_GEN.ivr[2]_i_1_n_0 ;
wire \IVR_GEN.ivr_reg[1]_0 ;
wire \IVR_GEN.ivr_reg[1]_1 ;
wire Irq_i;
wire [0:0]Q;
wire \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0 ;
wire \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0 ;
wire \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0 ;
wire \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0] ;
wire \REG_GEN[0].ier_reg[0]_0 ;
wire \REG_GEN[0].ier_reg[0]_1 ;
wire \REG_GEN[0].isr[0]_i_2_n_0 ;
wire \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0 ;
wire \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0 ;
wire \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1] ;
wire \REG_GEN[1].isr[1]_i_2_n_0 ;
wire \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0 ;
wire \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0 ;
wire \REG_GEN[2].isr[2]_i_2_n_0 ;
wire \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0 ;
wire \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0 ;
wire \REG_GEN[3].isr[3]_i_2_n_0 ;
wire \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0 ;
wire \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0 ;
wire \REG_GEN[4].isr[4]_i_2_n_0 ;
wire \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0 ;
wire \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0 ;
wire \REG_GEN[5].isr[5]_i_2_n_0 ;
wire \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0 ;
wire \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0 ;
wire \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0 ;
wire \REG_GEN[6].isr[6]_i_2_n_0 ;
wire [0:0]SS;
wire ack_or;
wire ack_or_i;
wire ack_or_i_2_n_0;
wire [3:0]\bus2ip_addr_i_reg[5] ;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire [1:0]current_state;
wire first_ack;
wire first_ack_active;
wire [6:0]hw_intr;
wire idle_and_irq;
wire idle_and_irq_d1;
wire in_idle;
wire [31:0]interrupt_address;
wire [6:0]intr;
wire intr_d1;
(* async_reg = "true" *) wire [0:1]intr_ff;
wire irq;
wire irq_gen;
wire irq_gen_i_1_n_0;
wire irq_gen_i_2_n_0;
wire [2:0]ivar_index_axi_clk;
wire ivar_index_sample_en;
wire ivar_index_sample_en_i;
wire [0:0]ivr_in;
wire p_0_in;
wire p_0_in107_in;
wire p_0_in118_in;
wire p_0_in11_in;
wire p_0_in14_in;
wire p_0_in19_in;
wire p_0_in20_in;
wire p_0_in22_in;
wire p_0_in24_in;
wire p_0_in26_in;
wire p_0_in28_in;
wire p_0_in2_in;
wire p_0_in49_in;
wire p_0_in51_in;
wire p_0_in53_in;
wire p_0_in55_in;
wire p_0_in57_in;
wire p_0_in59_in;
wire p_0_in5_in;
wire p_0_in64_in;
wire p_0_in74_in;
wire p_0_in85_in;
wire p_0_in8_in;
wire p_0_in96_in;
wire p_17_in;
wire p_17_out;
wire p_1_in;
wire p_1_in21_in;
wire p_1_in23_in;
wire p_1_in25_in;
wire p_1_in27_in;
wire p_1_in29_in;
(* async_reg = "true" *) wire [0:0]p_1_out__0;
wire p_21_out;
wire p_25_out;
wire p_29_out;
wire p_2_in;
wire p_33_out;
wire p_37_out;
wire p_3_in;
wire p_41_out;
wire p_42_out;
wire p_43_out;
wire p_44_out;
wire p_45_out;
wire p_46_out;
wire p_47_out;
wire p_48_out;
wire p_4_in;
wire p_5_in;
wire p_6_in;
wire [1:0]processor_ack;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata_i_reg[3] ;
wire [6:0]\s_axi_rdata_i_reg[6] ;
wire [31:0]s_axi_wdata;
wire second_ack;
wire second_ack_sync_d1;
wire second_ack_sync_d2;
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h32))
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1
(.I0(processor_ack[0]),
.I1(processor_ack[1]),
.I2(first_ack_active),
.O(\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0 ));
FDRE \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0 ),
.Q(first_ack_active),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h2))
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1
(.I0(processor_ack[0]),
.I1(processor_ack[1]),
.O(\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0 ));
FDRE \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0 ),
.Q(first_ack),
.R(SS));
LUT2 #(
.INIT(4'h8))
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1
(.I0(first_ack_active),
.I1(processor_ack[1]),
.O(\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0 ));
FDRE \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0 ),
.Q(second_ack),
.R(SS));
FDRE \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_sync_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(second_ack),
.Q(second_ack_sync_d1),
.R(SS));
FDRE \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_sync_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(second_ack_sync_d1),
.Q(second_ack_sync_d2),
.R(SS));
FDRE \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ),
.Q(\REG_GEN[0].ier_reg[0]_1 ),
.R(1'b0));
FDRE \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0 ),
.Q(p_0_in59_in),
.R(1'b0));
FDRE \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0 ),
.Q(p_0_in57_in),
.R(1'b0));
FDRE \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0 ),
.Q(p_0_in55_in),
.R(1'b0));
FDRE \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0 ),
.Q(p_0_in53_in),
.R(1'b0));
FDRE \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0 ),
.Q(p_0_in51_in),
.R(1'b0));
FDRE \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0 ),
.Q(p_0_in49_in),
.R(1'b0));
LUT4 #(
.INIT(16'h00E0))
\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1
(.I0(hw_intr[0]),
.I1(intr[0]),
.I2(s_axi_aresetn),
.I3(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0] ),
.O(\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ),
.Q(hw_intr[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr[1]),
.Q(intr_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_ff[0]),
.Q(intr_ff[1]),
.R(1'b0));
LUT5 #(
.INIT(32'h0000AE00))
\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1
(.I0(hw_intr[1]),
.I1(intr_ff[1]),
.I2(intr_d1),
.I3(s_axi_aresetn),
.I4(\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1] ),
.O(\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0 ),
.Q(hw_intr[1]),
.R(1'b0));
FDRE \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.intr_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_ff[1]),
.Q(intr_d1),
.R(SS));
LUT4 #(
.INIT(16'h00E0))
\INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1
(.I0(hw_intr[2]),
.I1(intr[2]),
.I2(s_axi_aresetn),
.I3(p_2_in),
.O(\INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0 ),
.Q(hw_intr[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h00E0))
\INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1
(.I0(hw_intr[3]),
.I1(intr[3]),
.I2(s_axi_aresetn),
.I3(p_3_in),
.O(\INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0 ),
.Q(hw_intr[3]),
.R(1'b0));
LUT5 #(
.INIT(32'h0000AE00))
\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1
(.I0(hw_intr[4]),
.I1(intr[4]),
.I2(\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0 ),
.I3(s_axi_aresetn),
.I4(p_4_in),
.O(\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0 ),
.Q(hw_intr[4]),
.R(1'b0));
FDRE \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr[4]),
.Q(\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0 ),
.R(SS));
LUT5 #(
.INIT(32'h0000AE00))
\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1
(.I0(hw_intr[5]),
.I1(intr[5]),
.I2(\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0 ),
.I3(s_axi_aresetn),
.I4(p_5_in),
.O(\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0 ),
.Q(hw_intr[5]),
.R(1'b0));
FDRE \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr[5]),
.Q(\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0 ),
.R(SS));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr[6]),
.Q(p_1_out__0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_out__0),
.Q(\INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1] ),
.R(1'b0));
LUT4 #(
.INIT(16'h00E0))
\INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1
(.I0(hw_intr[6]),
.I1(\INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1] ),
.I2(s_axi_aresetn),
.I3(p_6_in),
.O(\INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0 ),
.Q(hw_intr[6]),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[0]_i_1
(.I0(\IVR_GEN.ivr_reg[1]_1 ),
.I1(\IVR_GEN.ivr_reg[1]_0 ),
.O(\IPR_GEN.ipr[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[1]_i_1
(.I0(p_1_in29_in),
.I1(p_0_in28_in),
.O(\IPR_GEN.ipr[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[2]_i_1
(.I0(p_1_in27_in),
.I1(p_0_in26_in),
.O(\IPR_GEN.ipr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[3]_i_1
(.I0(p_1_in25_in),
.I1(p_0_in24_in),
.O(\IPR_GEN.ipr[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[4]_i_1
(.I0(p_1_in23_in),
.I1(p_0_in22_in),
.O(\IPR_GEN.ipr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[5]_i_1
(.I0(p_1_in21_in),
.I1(p_0_in20_in),
.O(\IPR_GEN.ipr[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[6]_i_1
(.I0(p_1_in),
.I1(p_0_in19_in),
.O(\IPR_GEN.ipr[6]_i_1_n_0 ));
FDRE \IPR_GEN.ipr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[0]_i_1_n_0 ),
.Q(\s_axi_rdata_i_reg[6] [0]),
.R(SS));
FDRE \IPR_GEN.ipr_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[1]_i_1_n_0 ),
.Q(\s_axi_rdata_i_reg[6] [1]),
.R(SS));
FDRE \IPR_GEN.ipr_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[2]_i_1_n_0 ),
.Q(\s_axi_rdata_i_reg[6] [2]),
.R(SS));
FDRE \IPR_GEN.ipr_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[3]_i_1_n_0 ),
.Q(\s_axi_rdata_i_reg[6] [3]),
.R(SS));
FDRE \IPR_GEN.ipr_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[4]_i_1_n_0 ),
.Q(\s_axi_rdata_i_reg[6] [4]),
.R(SS));
FDRE \IPR_GEN.ipr_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[5]_i_1_n_0 ),
.Q(\s_axi_rdata_i_reg[6] [5]),
.R(SS));
FDRE \IPR_GEN.ipr_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[6]_i_1_n_0 ),
.Q(\s_axi_rdata_i_reg[6] [6]),
.R(SS));
LUT1 #(
.INIT(2'h1))
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_i_1
(.I0(s_axi_aresetn),
.O(SS));
LUT2 #(
.INIT(4'h2))
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_i_2
(.I0(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0] ),
.I1(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1] ),
.O(Irq_i));
FDRE \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Irq_i),
.Q(irq),
.R(SS));
LUT6 #(
.INIT(64'h00000000737F404C))
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[0]_i_1
(.I0(first_ack),
.I1(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0] ),
.I2(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0 ),
.I3(ack_or),
.I4(ivar_index_sample_en),
.I5(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1] ),
.O(current_state[0]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'h00C05500))
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_1
(.I0(second_ack_sync_d2),
.I1(first_ack),
.I2(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0 ),
.I3(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1] ),
.I4(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0] ),
.O(current_state[1]));
LUT6 #(
.INIT(64'hCFAFCFA0C0AFC0A0))
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3
(.I0(p_0_in14_in),
.I1(p_0_in8_in),
.I2(ivar_index_axi_clk[0]),
.I3(ivar_index_axi_clk[1]),
.I4(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0 ),
.I5(p_0_in11_in),
.O(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00CCF0AA))
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4
(.I0(p_0_in5_in),
.I1(\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0 ),
.I2(p_0_in2_in),
.I3(ivar_index_axi_clk[0]),
.I4(ivar_index_axi_clk[1]),
.O(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0 ));
FDRE \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(current_state[0]),
.Q(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0] ),
.R(SS));
FDRE \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(current_state[1]),
.Q(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1] ),
.R(SS));
MUXF7 \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2
(.I0(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0 ),
.I1(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0 ),
.O(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0 ),
.S(ivar_index_axi_clk[2]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h1))
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1
(.I0(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0] ),
.I1(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1] ),
.O(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0 ));
FDRE \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0 ),
.Q(in_idle),
.R(SS));
system_microblaze_0_axi_intc_0_shared_ram_ivar \IVAR_FAST_MODE_GEN.IVAR_REG_MEM_AXI_CLK_GEN.IVAR_REG_MEM_I
(.Douta(Douta),
.\bus2ip_addr_i_reg[5] (\bus2ip_addr_i_reg[5] ),
.bus2ip_wrce(bus2ip_wrce[0]),
.interrupt_address(interrupt_address),
.ivar_index_axi_clk(ivar_index_axi_clk),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h80))
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.idle_and_irq_d1_i_1
(.I0(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ),
.I1(in_idle),
.I2(irq_gen),
.O(idle_and_irq));
FDRE \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.idle_and_irq_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(idle_and_irq),
.Q(idle_and_irq_d1),
.R(SS));
LUT6 #(
.INIT(64'hFFFFBFFF00008000))
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1
(.I0(Q),
.I1(irq_gen),
.I2(in_idle),
.I3(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ),
.I4(idle_and_irq_d1),
.I5(ivar_index_axi_clk[0]),
.O(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFBFFF00008000))
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1
(.I0(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0 ),
.I1(irq_gen),
.I2(in_idle),
.I3(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ),
.I4(idle_and_irq_d1),
.I5(ivar_index_axi_clk[1]),
.O(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFBFFF00008000))
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1
(.I0(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1 ),
.I1(irq_gen),
.I2(in_idle),
.I3(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ),
.I4(idle_and_irq_d1),
.I5(ivar_index_axi_clk[2]),
.O(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0 ));
FDRE \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0 ),
.Q(ivar_index_axi_clk[0]),
.R(SS));
FDRE \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0 ),
.Q(ivar_index_axi_clk[1]),
.R(SS));
FDRE \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0 ),
.Q(ivar_index_axi_clk[2]),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h0080))
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_sample_en_i_1
(.I0(irq_gen),
.I1(in_idle),
.I2(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ),
.I3(idle_and_irq_d1),
.O(ivar_index_sample_en_i));
FDRE \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_sample_en_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ivar_index_sample_en_i),
.Q(ivar_index_sample_en),
.R(SS));
LUT6 #(
.INIT(64'h00FF002A002A002A))
\IVR_GEN.ivr[0]_i_1
(.I0(\IVR_GEN.ivr[0]_i_2_n_0 ),
.I1(p_0_in26_in),
.I2(p_1_in27_in),
.I3(\IPR_GEN.ipr[0]_i_1_n_0 ),
.I4(p_1_in29_in),
.I5(p_0_in28_in),
.O(ivr_in));
LUT6 #(
.INIT(64'h88888888F888FFFF))
\IVR_GEN.ivr[0]_i_2
(.I0(p_1_in25_in),
.I1(p_0_in24_in),
.I2(p_0_in20_in),
.I3(p_1_in21_in),
.I4(\IPR_GEN.ipr[6]_i_1_n_0 ),
.I5(\IPR_GEN.ipr[4]_i_1_n_0 ),
.O(\IVR_GEN.ivr[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h5555555555F7F7F7))
\IVR_GEN.ivr[1]_i_1
(.I0(s_axi_aresetn),
.I1(\IVR_GEN.ivr[1]_i_2_n_0 ),
.I2(\IVR_GEN.ivr[1]_i_3_n_0 ),
.I3(\IVR_GEN.ivr_reg[1]_0 ),
.I4(\IVR_GEN.ivr_reg[1]_1 ),
.I5(\IPR_GEN.ipr[1]_i_1_n_0 ),
.O(\IVR_GEN.ivr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'hF888))
\IVR_GEN.ivr[1]_i_2
(.I0(p_0_in20_in),
.I1(p_1_in21_in),
.I2(p_0_in22_in),
.I3(p_1_in23_in),
.O(\IVR_GEN.ivr[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'hF888))
\IVR_GEN.ivr[1]_i_3
(.I0(p_0_in24_in),
.I1(p_1_in25_in),
.I2(p_0_in26_in),
.I3(p_1_in27_in),
.O(\IVR_GEN.ivr[1]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h7))
\IVR_GEN.ivr[2]_i_1
(.I0(s_axi_aresetn),
.I1(irq_gen_i_2_n_0),
.O(\IVR_GEN.ivr[2]_i_1_n_0 ));
FDSE \IVR_GEN.ivr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ivr_in),
.Q(Q),
.S(SS));
FDRE \IVR_GEN.ivr_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IVR_GEN.ivr[1]_i_1_n_0 ),
.Q(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0 ),
.R(1'b0));
FDRE \IVR_GEN.ivr_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IVR_GEN.ivr[2]_i_1_n_0 ),
.Q(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1 ),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000EA400000))
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1
(.I0(Bus_RNW_reg_reg_7),
.I1(\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0 ),
.I2(second_ack),
.I3(s_axi_wdata[0]),
.I4(s_axi_aresetn),
.I5(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0] ),
.O(\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000040))
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3
(.I0(ivar_index_axi_clk[2]),
.I1(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0 ),
.I2(second_ack),
.I3(ivar_index_axi_clk[0]),
.I4(ivar_index_axi_clk[1]),
.O(\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0 ));
FDRE \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0 ),
.Q(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0] ),
.R(1'b0));
FDRE \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[0]),
.Q(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0 ),
.R(SS));
LUT6 #(
.INIT(64'h0C0C0C080C0C0008))
\REG_GEN[0].ier[0]_i_1
(.I0(\IVR_GEN.ivr_reg[1]_0 ),
.I1(s_axi_aresetn),
.I2(\REG_GEN[0].ier_reg[0]_1 ),
.I3(bus2ip_wrce__0),
.I4(\REG_GEN[0].ier_reg[0]_0 ),
.I5(s_axi_wdata[0]),
.O(p_41_out));
FDRE \REG_GEN[0].ier_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_41_out),
.Q(\IVR_GEN.ivr_reg[1]_0 ),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\REG_GEN[0].isr[0]_i_1
(.I0(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0] ),
.I1(s_axi_aresetn),
.O(p_48_out));
LUT6 #(
.INIT(64'hAAAAFCFFAAAA0C00))
\REG_GEN[0].isr[0]_i_2
(.I0(hw_intr[0]),
.I1(s_axi_wdata[0]),
.I2(Bus_RNW_reg),
.I3(p_17_in),
.I4(p_0_in),
.I5(\IVR_GEN.ivr_reg[1]_1 ),
.O(\REG_GEN[0].isr[0]_i_2_n_0 ));
FDRE \REG_GEN[0].isr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[0].isr[0]_i_2_n_0 ),
.Q(\IVR_GEN.ivr_reg[1]_1 ),
.R(p_48_out));
LUT6 #(
.INIT(64'h00000000EA400000))
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1
(.I0(Bus_RNW_reg_reg_8),
.I1(\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0 ),
.I2(first_ack),
.I3(s_axi_wdata[1]),
.I4(s_axi_aresetn),
.I5(\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1] ),
.O(\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00400000))
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3
(.I0(ivar_index_axi_clk[2]),
.I1(p_0_in14_in),
.I2(first_ack),
.I3(ivar_index_axi_clk[1]),
.I4(ivar_index_axi_clk[0]),
.O(\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0 ));
FDRE \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0 ),
.Q(\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1] ),
.R(1'b0));
FDRE \REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[1]),
.Q(p_0_in14_in),
.R(SS));
LUT6 #(
.INIT(64'h0C0C0C080C0C0008))
\REG_GEN[1].ier[1]_i_1
(.I0(p_0_in28_in),
.I1(s_axi_aresetn),
.I2(p_0_in59_in),
.I3(bus2ip_wrce__0),
.I4(p_0_in118_in),
.I5(s_axi_wdata[1]),
.O(p_37_out));
FDRE \REG_GEN[1].ier_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_37_out),
.Q(p_0_in28_in),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\REG_GEN[1].isr[1]_i_1
(.I0(\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1] ),
.I1(s_axi_aresetn),
.O(p_47_out));
LUT6 #(
.INIT(64'hAAAAFCFFAAAA0C00))
\REG_GEN[1].isr[1]_i_2
(.I0(hw_intr[1]),
.I1(s_axi_wdata[1]),
.I2(Bus_RNW_reg),
.I3(p_17_in),
.I4(p_0_in),
.I5(p_1_in29_in),
.O(\REG_GEN[1].isr[1]_i_2_n_0 ));
FDRE \REG_GEN[1].isr_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[1].isr[1]_i_2_n_0 ),
.Q(p_1_in29_in),
.R(p_47_out));
LUT6 #(
.INIT(64'h00000000EA400000))
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1
(.I0(Bus_RNW_reg_reg_9),
.I1(\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0 ),
.I2(second_ack),
.I3(s_axi_wdata[2]),
.I4(s_axi_aresetn),
.I5(p_2_in),
.O(\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00400000))
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3
(.I0(ivar_index_axi_clk[2]),
.I1(p_0_in11_in),
.I2(second_ack),
.I3(ivar_index_axi_clk[0]),
.I4(ivar_index_axi_clk[1]),
.O(\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0 ));
FDRE \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0 ),
.Q(p_2_in),
.R(1'b0));
FDRE \REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[2]),
.Q(p_0_in11_in),
.R(SS));
LUT6 #(
.INIT(64'h0C0C0C080C0C0008))
\REG_GEN[2].ier[2]_i_1
(.I0(p_0_in26_in),
.I1(s_axi_aresetn),
.I2(p_0_in57_in),
.I3(bus2ip_wrce__0),
.I4(p_0_in107_in),
.I5(s_axi_wdata[2]),
.O(p_33_out));
FDRE \REG_GEN[2].ier_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_33_out),
.Q(p_0_in26_in),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\REG_GEN[2].isr[2]_i_1
(.I0(p_2_in),
.I1(s_axi_aresetn),
.O(p_46_out));
LUT6 #(
.INIT(64'hAAAAFCFFAAAA0C00))
\REG_GEN[2].isr[2]_i_2
(.I0(hw_intr[2]),
.I1(s_axi_wdata[2]),
.I2(Bus_RNW_reg),
.I3(p_17_in),
.I4(p_0_in),
.I5(p_1_in27_in),
.O(\REG_GEN[2].isr[2]_i_2_n_0 ));
FDRE \REG_GEN[2].isr_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[2].isr[2]_i_2_n_0 ),
.Q(p_1_in27_in),
.R(p_46_out));
LUT6 #(
.INIT(64'h00000000EA400000))
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1
(.I0(Bus_RNW_reg_reg_10),
.I1(\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0 ),
.I2(second_ack),
.I3(s_axi_wdata[3]),
.I4(s_axi_aresetn),
.I5(p_3_in),
.O(\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08000000))
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3
(.I0(ivar_index_axi_clk[0]),
.I1(ivar_index_axi_clk[1]),
.I2(ivar_index_axi_clk[2]),
.I3(second_ack),
.I4(p_0_in8_in),
.O(\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0 ));
FDRE \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0 ),
.Q(p_3_in),
.R(1'b0));
FDRE \REG_GEN[3].IMR_FAST_MODE_GEN.imr_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[3]),
.Q(p_0_in8_in),
.R(SS));
LUT6 #(
.INIT(64'h0C0C0C080C0C0008))
\REG_GEN[3].ier[3]_i_1
(.I0(p_0_in24_in),
.I1(s_axi_aresetn),
.I2(p_0_in55_in),
.I3(bus2ip_wrce__0),
.I4(p_0_in96_in),
.I5(s_axi_wdata[3]),
.O(p_29_out));
FDRE \REG_GEN[3].ier_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_29_out),
.Q(p_0_in24_in),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\REG_GEN[3].isr[3]_i_1
(.I0(p_3_in),
.I1(s_axi_aresetn),
.O(p_45_out));
LUT6 #(
.INIT(64'hAAAAFCFFAAAA0C00))
\REG_GEN[3].isr[3]_i_2
(.I0(hw_intr[3]),
.I1(s_axi_wdata[3]),
.I2(Bus_RNW_reg),
.I3(p_17_in),
.I4(p_0_in),
.I5(p_1_in25_in),
.O(\REG_GEN[3].isr[3]_i_2_n_0 ));
FDRE \REG_GEN[3].isr_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[3].isr[3]_i_2_n_0 ),
.Q(p_1_in25_in),
.R(p_45_out));
LUT6 #(
.INIT(64'h00000000EA400000))
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1
(.I0(Bus_RNW_reg_reg_11),
.I1(\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0 ),
.I2(first_ack),
.I3(s_axi_wdata[4]),
.I4(s_axi_aresetn),
.I5(p_4_in),
.O(\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3
(.I0(ivar_index_axi_clk[2]),
.I1(p_0_in5_in),
.I2(first_ack),
.I3(ivar_index_axi_clk[0]),
.I4(ivar_index_axi_clk[1]),
.O(\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0 ));
FDRE \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0 ),
.Q(p_4_in),
.R(1'b0));
FDRE \REG_GEN[4].IMR_FAST_MODE_GEN.imr_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[4]),
.Q(p_0_in5_in),
.R(SS));
LUT6 #(
.INIT(64'h0C0C0C080C0C0008))
\REG_GEN[4].ier[4]_i_1
(.I0(p_0_in22_in),
.I1(s_axi_aresetn),
.I2(p_0_in53_in),
.I3(bus2ip_wrce__0),
.I4(p_0_in85_in),
.I5(s_axi_wdata[4]),
.O(p_25_out));
FDRE \REG_GEN[4].ier_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_25_out),
.Q(p_0_in22_in),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\REG_GEN[4].isr[4]_i_1
(.I0(p_4_in),
.I1(s_axi_aresetn),
.O(p_44_out));
LUT6 #(
.INIT(64'hAAAAFCFFAAAA0C00))
\REG_GEN[4].isr[4]_i_2
(.I0(hw_intr[4]),
.I1(s_axi_wdata[4]),
.I2(Bus_RNW_reg),
.I3(p_17_in),
.I4(p_0_in),
.I5(p_1_in23_in),
.O(\REG_GEN[4].isr[4]_i_2_n_0 ));
FDRE \REG_GEN[4].isr_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[4].isr[4]_i_2_n_0 ),
.Q(p_1_in23_in),
.R(p_44_out));
LUT6 #(
.INIT(64'h00000000EA400000))
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1
(.I0(Bus_RNW_reg_reg_12),
.I1(\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0 ),
.I2(first_ack),
.I3(s_axi_wdata[5]),
.I4(s_axi_aresetn),
.I5(p_5_in),
.O(\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00800000))
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3
(.I0(ivar_index_axi_clk[2]),
.I1(p_0_in2_in),
.I2(first_ack),
.I3(ivar_index_axi_clk[1]),
.I4(ivar_index_axi_clk[0]),
.O(\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0 ));
FDRE \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0 ),
.Q(p_5_in),
.R(1'b0));
FDRE \REG_GEN[5].IMR_FAST_MODE_GEN.imr_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[5]),
.Q(p_0_in2_in),
.R(SS));
LUT6 #(
.INIT(64'h0C0C0C080C0C0008))
\REG_GEN[5].ier[5]_i_1
(.I0(p_0_in20_in),
.I1(s_axi_aresetn),
.I2(p_0_in51_in),
.I3(bus2ip_wrce__0),
.I4(p_0_in74_in),
.I5(s_axi_wdata[5]),
.O(p_21_out));
FDRE \REG_GEN[5].ier_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_21_out),
.Q(p_0_in20_in),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\REG_GEN[5].isr[5]_i_1
(.I0(p_5_in),
.I1(s_axi_aresetn),
.O(p_43_out));
LUT6 #(
.INIT(64'hAAAAFCFFAAAA0C00))
\REG_GEN[5].isr[5]_i_2
(.I0(hw_intr[5]),
.I1(s_axi_wdata[5]),
.I2(Bus_RNW_reg),
.I3(p_17_in),
.I4(p_0_in),
.I5(p_1_in21_in),
.O(\REG_GEN[5].isr[5]_i_2_n_0 ));
FDRE \REG_GEN[5].isr_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[5].isr[5]_i_2_n_0 ),
.Q(p_1_in21_in),
.R(p_43_out));
LUT6 #(
.INIT(64'h00000000EA400000))
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1
(.I0(Bus_RNW_reg_reg_13),
.I1(\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0 ),
.I2(second_ack),
.I3(s_axi_wdata[6]),
.I4(s_axi_aresetn),
.I5(p_6_in),
.O(\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00800000))
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3
(.I0(ivar_index_axi_clk[2]),
.I1(\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0 ),
.I2(second_ack),
.I3(ivar_index_axi_clk[0]),
.I4(ivar_index_axi_clk[1]),
.O(\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0 ));
FDRE \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0 ),
.Q(p_6_in),
.R(1'b0));
FDRE \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[6]),
.Q(\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0 ),
.R(SS));
LUT6 #(
.INIT(64'h0C0C0C080C0C0008))
\REG_GEN[6].ier[6]_i_1
(.I0(p_0_in19_in),
.I1(s_axi_aresetn),
.I2(p_0_in49_in),
.I3(bus2ip_wrce__0),
.I4(p_0_in64_in),
.I5(s_axi_wdata[6]),
.O(p_17_out));
FDRE \REG_GEN[6].ier_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_17_out),
.Q(p_0_in19_in),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\REG_GEN[6].isr[6]_i_1
(.I0(p_6_in),
.I1(s_axi_aresetn),
.O(p_42_out));
LUT6 #(
.INIT(64'hAAAAFCFFAAAA0C00))
\REG_GEN[6].isr[6]_i_2
(.I0(hw_intr[6]),
.I1(s_axi_wdata[6]),
.I2(Bus_RNW_reg),
.I3(p_17_in),
.I4(p_0_in),
.I5(p_1_in),
.O(\REG_GEN[6].isr[6]_i_2_n_0 ));
FDRE \REG_GEN[6].isr_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[6].isr[6]_i_2_n_0 ),
.Q(p_1_in),
.R(p_42_out));
FDRE \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg),
.Q(\REG_GEN[0].ier_reg[0]_0 ),
.R(1'b0));
FDRE \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_0),
.Q(p_0_in118_in),
.R(1'b0));
FDRE \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_1),
.Q(p_0_in107_in),
.R(1'b0));
FDRE \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_2),
.Q(p_0_in96_in),
.R(1'b0));
FDRE \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_3),
.Q(p_0_in85_in),
.R(1'b0));
FDRE \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_4),
.Q(p_0_in74_in),
.R(1'b0));
FDRE \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_5),
.Q(p_0_in64_in),
.R(1'b0));
LUT4 #(
.INIT(16'hFFFE))
ack_or_i_1
(.I0(ack_or_i_2_n_0),
.I1(p_6_in),
.I2(\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1] ),
.I3(p_3_in),
.O(ack_or_i));
LUT4 #(
.INIT(16'hFFFE))
ack_or_i_2
(.I0(p_4_in),
.I1(\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0] ),
.I2(p_2_in),
.I3(p_5_in),
.O(ack_or_i_2_n_0));
FDRE ack_or_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ack_or_i),
.Q(ack_or),
.R(SS));
LUT6 #(
.INIT(64'hFFFFFFFFFFF8F8F8))
irq_gen_i_1
(.I0(p_0_in19_in),
.I1(p_1_in),
.I2(irq_gen_i_2_n_0),
.I3(p_0_in20_in),
.I4(p_1_in21_in),
.I5(\IPR_GEN.ipr[4]_i_1_n_0 ),
.O(irq_gen_i_1_n_0));
LUT6 #(
.INIT(64'hFFFFFEEEFEEEFEEE))
irq_gen_i_2
(.I0(\IPR_GEN.ipr[1]_i_1_n_0 ),
.I1(\IPR_GEN.ipr[0]_i_1_n_0 ),
.I2(p_1_in27_in),
.I3(p_0_in26_in),
.I4(p_1_in25_in),
.I5(p_0_in24_in),
.O(irq_gen_i_2_n_0));
FDRE irq_gen_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irq_gen_i_1_n_0),
.Q(irq_gen),
.R(SS));
FDRE \mer_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ),
.Q(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0 ),
.R(SS));
FDRE \mer_int_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_6),
.Q(p_0_in),
.R(SS));
LUT6 #(
.INIT(64'h0000800080008000))
\s_axi_rdata_i[31]_i_6
(.I0(Q),
.I1(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0 ),
.I2(\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1 ),
.I3(\bus2ip_addr_i_reg[5] [2]),
.I4(\bus2ip_addr_i_reg[5] [0]),
.I5(\bus2ip_addr_i_reg[5] [1]),
.O(\s_axi_rdata_i_reg[3] ));
endmodule
(* ORIG_REF_NAME = "shared_ram_ivar" *)
module system_microblaze_0_axi_intc_0_shared_ram_ivar
(Douta,
interrupt_address,
s_axi_aclk,
s_axi_wdata,
bus2ip_wrce,
\bus2ip_addr_i_reg[5] ,
ivar_index_axi_clk);
output [31:0]Douta;
output [31:0]interrupt_address;
input s_axi_aclk;
input [31:0]s_axi_wdata;
input [0:0]bus2ip_wrce;
input [3:0]\bus2ip_addr_i_reg[5] ;
input [2:0]ivar_index_axi_clk;
wire [31:0]Douta;
wire [31:0]Doutb0;
wire [3:0]\bus2ip_addr_i_reg[5] ;
wire [0:0]bus2ip_wrce;
wire [31:0]interrupt_address;
wire [2:0]ivar_index_axi_clk;
wire ram_reg_0_15_0_0_n_1;
wire ram_reg_0_15_10_10_n_1;
wire ram_reg_0_15_11_11_n_1;
wire ram_reg_0_15_12_12_n_1;
wire ram_reg_0_15_13_13_n_1;
wire ram_reg_0_15_14_14_n_1;
wire ram_reg_0_15_15_15_n_1;
wire ram_reg_0_15_16_16_n_1;
wire ram_reg_0_15_17_17_n_1;
wire ram_reg_0_15_18_18_n_1;
wire ram_reg_0_15_19_19_n_1;
wire ram_reg_0_15_1_1_n_1;
wire ram_reg_0_15_20_20_n_1;
wire ram_reg_0_15_21_21_n_1;
wire ram_reg_0_15_22_22_n_1;
wire ram_reg_0_15_23_23_n_1;
wire ram_reg_0_15_24_24_n_1;
wire ram_reg_0_15_25_25_n_1;
wire ram_reg_0_15_26_26_n_1;
wire ram_reg_0_15_27_27_n_1;
wire ram_reg_0_15_28_28_n_1;
wire ram_reg_0_15_29_29_n_1;
wire ram_reg_0_15_2_2_n_1;
wire ram_reg_0_15_30_30_n_1;
wire ram_reg_0_15_31_31_n_1;
wire ram_reg_0_15_3_3_n_1;
wire ram_reg_0_15_4_4_n_1;
wire ram_reg_0_15_5_5_n_1;
wire ram_reg_0_15_6_6_n_1;
wire ram_reg_0_15_7_7_n_1;
wire ram_reg_0_15_8_8_n_1;
wire ram_reg_0_15_9_9_n_1;
wire s_axi_aclk;
wire [31:0]s_axi_wdata;
FDRE \Douta_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_0_0_n_1),
.Q(Douta[0]),
.R(1'b0));
FDRE \Douta_reg[10]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_10_10_n_1),
.Q(Douta[10]),
.R(1'b0));
FDRE \Douta_reg[11]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_11_11_n_1),
.Q(Douta[11]),
.R(1'b0));
FDRE \Douta_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_12_12_n_1),
.Q(Douta[12]),
.R(1'b0));
FDRE \Douta_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_13_13_n_1),
.Q(Douta[13]),
.R(1'b0));
FDRE \Douta_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_14_14_n_1),
.Q(Douta[14]),
.R(1'b0));
FDRE \Douta_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_15_15_n_1),
.Q(Douta[15]),
.R(1'b0));
FDRE \Douta_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_16_16_n_1),
.Q(Douta[16]),
.R(1'b0));
FDRE \Douta_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_17_17_n_1),
.Q(Douta[17]),
.R(1'b0));
FDRE \Douta_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_18_18_n_1),
.Q(Douta[18]),
.R(1'b0));
FDRE \Douta_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_19_19_n_1),
.Q(Douta[19]),
.R(1'b0));
FDRE \Douta_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_1_1_n_1),
.Q(Douta[1]),
.R(1'b0));
FDRE \Douta_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_20_20_n_1),
.Q(Douta[20]),
.R(1'b0));
FDRE \Douta_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_21_21_n_1),
.Q(Douta[21]),
.R(1'b0));
FDRE \Douta_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_22_22_n_1),
.Q(Douta[22]),
.R(1'b0));
FDRE \Douta_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_23_23_n_1),
.Q(Douta[23]),
.R(1'b0));
FDRE \Douta_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_24_24_n_1),
.Q(Douta[24]),
.R(1'b0));
FDRE \Douta_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_25_25_n_1),
.Q(Douta[25]),
.R(1'b0));
FDRE \Douta_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_26_26_n_1),
.Q(Douta[26]),
.R(1'b0));
FDRE \Douta_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_27_27_n_1),
.Q(Douta[27]),
.R(1'b0));
FDRE \Douta_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_28_28_n_1),
.Q(Douta[28]),
.R(1'b0));
FDRE \Douta_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_29_29_n_1),
.Q(Douta[29]),
.R(1'b0));
FDRE \Douta_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_2_2_n_1),
.Q(Douta[2]),
.R(1'b0));
FDRE \Douta_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_30_30_n_1),
.Q(Douta[30]),
.R(1'b0));
FDRE \Douta_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_31_31_n_1),
.Q(Douta[31]),
.R(1'b0));
FDRE \Douta_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_3_3_n_1),
.Q(Douta[3]),
.R(1'b0));
FDRE \Douta_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_4_4_n_1),
.Q(Douta[4]),
.R(1'b0));
FDRE \Douta_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_5_5_n_1),
.Q(Douta[5]),
.R(1'b0));
FDRE \Douta_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_6_6_n_1),
.Q(Douta[6]),
.R(1'b0));
FDRE \Douta_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_7_7_n_1),
.Q(Douta[7]),
.R(1'b0));
FDRE \Douta_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_8_8_n_1),
.Q(Douta[8]),
.R(1'b0));
FDRE \Douta_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ram_reg_0_15_9_9_n_1),
.Q(Douta[9]),
.R(1'b0));
FDRE \Doutb_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[0]),
.Q(interrupt_address[0]),
.R(1'b0));
FDRE \Doutb_reg[10]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[10]),
.Q(interrupt_address[10]),
.R(1'b0));
FDRE \Doutb_reg[11]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[11]),
.Q(interrupt_address[11]),
.R(1'b0));
FDRE \Doutb_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[12]),
.Q(interrupt_address[12]),
.R(1'b0));
FDRE \Doutb_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[13]),
.Q(interrupt_address[13]),
.R(1'b0));
FDRE \Doutb_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[14]),
.Q(interrupt_address[14]),
.R(1'b0));
FDRE \Doutb_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[15]),
.Q(interrupt_address[15]),
.R(1'b0));
FDRE \Doutb_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[16]),
.Q(interrupt_address[16]),
.R(1'b0));
FDRE \Doutb_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[17]),
.Q(interrupt_address[17]),
.R(1'b0));
FDRE \Doutb_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[18]),
.Q(interrupt_address[18]),
.R(1'b0));
FDRE \Doutb_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[19]),
.Q(interrupt_address[19]),
.R(1'b0));
FDRE \Doutb_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[1]),
.Q(interrupt_address[1]),
.R(1'b0));
FDRE \Doutb_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[20]),
.Q(interrupt_address[20]),
.R(1'b0));
FDRE \Doutb_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[21]),
.Q(interrupt_address[21]),
.R(1'b0));
FDRE \Doutb_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[22]),
.Q(interrupt_address[22]),
.R(1'b0));
FDRE \Doutb_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[23]),
.Q(interrupt_address[23]),
.R(1'b0));
FDRE \Doutb_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[24]),
.Q(interrupt_address[24]),
.R(1'b0));
FDRE \Doutb_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[25]),
.Q(interrupt_address[25]),
.R(1'b0));
FDRE \Doutb_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[26]),
.Q(interrupt_address[26]),
.R(1'b0));
FDRE \Doutb_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[27]),
.Q(interrupt_address[27]),
.R(1'b0));
FDRE \Doutb_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[28]),
.Q(interrupt_address[28]),
.R(1'b0));
FDRE \Doutb_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[29]),
.Q(interrupt_address[29]),
.R(1'b0));
FDRE \Doutb_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[2]),
.Q(interrupt_address[2]),
.R(1'b0));
FDRE \Doutb_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[30]),
.Q(interrupt_address[30]),
.R(1'b0));
FDRE \Doutb_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[31]),
.Q(interrupt_address[31]),
.R(1'b0));
FDRE \Doutb_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[3]),
.Q(interrupt_address[3]),
.R(1'b0));
FDRE \Doutb_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[4]),
.Q(interrupt_address[4]),
.R(1'b0));
FDRE \Doutb_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[5]),
.Q(interrupt_address[5]),
.R(1'b0));
FDRE \Doutb_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[6]),
.Q(interrupt_address[6]),
.R(1'b0));
FDRE \Doutb_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[7]),
.Q(interrupt_address[7]),
.R(1'b0));
FDRE \Doutb_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[8]),
.Q(interrupt_address[8]),
.R(1'b0));
FDRE \Doutb_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Doutb0[9]),
.Q(interrupt_address[9]),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_0_0
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[0]),
.DPO(Doutb0[0]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_0_0_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_10_10
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[10]),
.DPO(Doutb0[10]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_10_10_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_11_11
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[11]),
.DPO(Doutb0[11]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_11_11_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_12_12
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[12]),
.DPO(Doutb0[12]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_12_12_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_13_13
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[13]),
.DPO(Doutb0[13]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_13_13_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_14_14
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[14]),
.DPO(Doutb0[14]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_14_14_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_15_15
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[15]),
.DPO(Doutb0[15]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_15_15_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_16_16
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[16]),
.DPO(Doutb0[16]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_16_16_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_17_17
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[17]),
.DPO(Doutb0[17]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_17_17_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_18_18
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[18]),
.DPO(Doutb0[18]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_18_18_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_19_19
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[19]),
.DPO(Doutb0[19]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_19_19_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_1_1
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[1]),
.DPO(Doutb0[1]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_1_1_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_20_20
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[20]),
.DPO(Doutb0[20]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_20_20_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_21_21
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[21]),
.DPO(Doutb0[21]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_21_21_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_22_22
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[22]),
.DPO(Doutb0[22]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_22_22_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_23_23
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[23]),
.DPO(Doutb0[23]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_23_23_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_24_24
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[24]),
.DPO(Doutb0[24]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_24_24_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_25_25
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[25]),
.DPO(Doutb0[25]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_25_25_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_26_26
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[26]),
.DPO(Doutb0[26]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_26_26_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_27_27
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[27]),
.DPO(Doutb0[27]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_27_27_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_28_28
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[28]),
.DPO(Doutb0[28]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_28_28_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_29_29
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[29]),
.DPO(Doutb0[29]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_29_29_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_2_2
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[2]),
.DPO(Doutb0[2]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_2_2_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_30_30
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[30]),
.DPO(Doutb0[30]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_30_30_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_31_31
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[31]),
.DPO(Doutb0[31]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_31_31_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_3_3
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[3]),
.DPO(Doutb0[3]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_3_3_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h0000FFFF))
ram_reg_0_15_4_4
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[4]),
.DPO(Doutb0[4]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_4_4_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_5_5
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[5]),
.DPO(Doutb0[5]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_5_5_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_6_6
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[6]),
.DPO(Doutb0[6]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_6_6_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_7_7
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[7]),
.DPO(Doutb0[7]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_7_7_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_8_8
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[8]),
.DPO(Doutb0[8]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_8_8_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
(* XILINX_LEGACY_PRIM = "RAM16X1D" *)
RAM32X1D #(
.INIT(32'h00000000))
ram_reg_0_15_9_9
(.A0(\bus2ip_addr_i_reg[5] [0]),
.A1(\bus2ip_addr_i_reg[5] [1]),
.A2(\bus2ip_addr_i_reg[5] [2]),
.A3(\bus2ip_addr_i_reg[5] [3]),
.A4(1'b0),
.D(s_axi_wdata[9]),
.DPO(Doutb0[9]),
.DPRA0(ivar_index_axi_clk[0]),
.DPRA1(ivar_index_axi_clk[1]),
.DPRA2(ivar_index_axi_clk[2]),
.DPRA3(1'b0),
.DPRA4(1'b0),
.SPO(ram_reg_0_15_9_9_n_1),
.WCLK(s_axi_aclk),
.WE(bus2ip_wrce));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module system_microblaze_0_axi_intc_0_slave_attachment
(p_17_in,
s_axi_rresp,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
ip2bus_wrack_prev2,
Or128_vec2stdlogic,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ,
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ,
s_axi_wready,
s_axi_arready,
bus2ip_wrce__0,
bus2ip_wrce,
Q,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ,
\mer_int_reg[0] ,
\mer_int_reg[1] ,
s_axi_rdata,
SS,
s_axi_aclk,
ip2bus_wrack_int_d1,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ,
p_0_in2_in,
p_0_in5_in,
p_0_in8_in,
p_0_in11_in,
p_0_in14_in,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ,
ip2bus_wrack,
ip2bus_rdack,
s_axi_aresetn,
s_axi_arvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
\Douta_reg[31] ,
\IPR_GEN.ipr_reg[6] ,
\REG_GEN[0].ier_reg[0] ,
\REG_GEN[0].isr_reg[0] ,
p_0_in28_in,
p_1_in29_in,
p_0_in26_in,
p_1_in27_in,
p_0_in24_in,
p_1_in25_in,
p_0_in22_in,
p_1_in23_in,
p_0_in20_in,
p_1_in21_in,
p_0_in19_in,
p_1_in,
\IVR_GEN.ivr_reg[0] ,
\mer_int_reg[0]_0 ,
\IVR_GEN.ivr_reg[0]_0 ,
p_0_in,
\IVR_GEN.ivr_reg[1] ,
\IVR_GEN.ivr_reg[2] ,
ip2bus_rdack_int_d1,
s_axi_wstrb,
s_axi_wdata,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 ,
p_0_in118_in,
p_0_in107_in,
p_0_in96_in,
p_0_in85_in,
p_0_in74_in,
p_0_in64_in,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ,
p_0_in59_in,
p_0_in57_in,
p_0_in55_in,
p_0_in53_in,
p_0_in51_in,
p_0_in49_in);
output p_17_in;
output [0:0]s_axi_rresp;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output ip2bus_wrack_prev2;
output Or128_vec2stdlogic;
output \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ;
output \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ;
output \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ;
output \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ;
output \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ;
output \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ;
output \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ;
output s_axi_wready;
output s_axi_arready;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output [3:0]Q;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ;
output \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ;
output \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ;
output \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ;
output \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ;
output \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ;
output \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ;
output \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ;
output \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ;
output \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ;
output \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ;
output \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ;
output \mer_int_reg[0] ;
output \mer_int_reg[1] ;
output [31:0]s_axi_rdata;
input [0:0]SS;
input s_axi_aclk;
input ip2bus_wrack_int_d1;
input \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ;
input p_0_in2_in;
input p_0_in5_in;
input p_0_in8_in;
input p_0_in11_in;
input p_0_in14_in;
input \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ;
input ip2bus_wrack;
input ip2bus_rdack;
input s_axi_aresetn;
input s_axi_arvalid;
input [6:0]s_axi_araddr;
input [6:0]s_axi_awaddr;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input [31:0]\Douta_reg[31] ;
input [6:0]\IPR_GEN.ipr_reg[6] ;
input \REG_GEN[0].ier_reg[0] ;
input \REG_GEN[0].isr_reg[0] ;
input p_0_in28_in;
input p_1_in29_in;
input p_0_in26_in;
input p_1_in27_in;
input p_0_in24_in;
input p_1_in25_in;
input p_0_in22_in;
input p_1_in23_in;
input p_0_in20_in;
input p_1_in21_in;
input p_0_in19_in;
input p_1_in;
input \IVR_GEN.ivr_reg[0] ;
input \mer_int_reg[0]_0 ;
input [0:0]\IVR_GEN.ivr_reg[0]_0 ;
input p_0_in;
input \IVR_GEN.ivr_reg[1] ;
input \IVR_GEN.ivr_reg[2] ;
input ip2bus_rdack_int_d1;
input [3:0]s_axi_wstrb;
input [6:0]s_axi_wdata;
input \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 ;
input p_0_in118_in;
input p_0_in107_in;
input p_0_in96_in;
input p_0_in85_in;
input p_0_in74_in;
input p_0_in64_in;
input \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
input p_0_in59_in;
input p_0_in57_in;
input p_0_in55_in;
input p_0_in53_in;
input p_0_in51_in;
input p_0_in49_in;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ;
wire \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ;
wire \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ;
wire \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ;
wire \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ;
wire \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ;
wire [31:0]\Douta_reg[31] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire [31:0]IP2Bus_Data;
wire [6:0]\IPR_GEN.ipr_reg[6] ;
wire \IVR_GEN.ivr_reg[0] ;
wire [0:0]\IVR_GEN.ivr_reg[0]_0 ;
wire \IVR_GEN.ivr_reg[1] ;
wire \IVR_GEN.ivr_reg[2] ;
wire Or128_vec2stdlogic;
wire Or128_vec2stdlogic19_out;
wire [3:0]Q;
wire \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ;
wire \REG_GEN[0].ier_reg[0] ;
wire \REG_GEN[0].isr_reg[0] ;
wire \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ;
wire \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ;
wire \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ;
wire \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ;
wire \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ;
wire \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ;
wire \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 ;
wire \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ;
wire \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ;
wire \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ;
wire \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ;
wire \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ;
wire \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ;
wire [0:0]SS;
wire [8:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[4]_i_1_n_0 ;
wire \bus2ip_addr_i[5]_i_1_n_0 ;
wire \bus2ip_addr_i[6]_i_1_n_0 ;
wire \bus2ip_addr_i[7]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire bus2ip_rnw_i_i_1_n_0;
wire bus2ip_rnw_i_reg_n_0;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire ip2bus_error;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_prev2;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire \mer_int_reg[0] ;
wire \mer_int_reg[0]_0 ;
wire \mer_int_reg[1] ;
wire p_0_in;
wire p_0_in107_in;
wire p_0_in118_in;
wire p_0_in11_in;
wire p_0_in14_in;
wire p_0_in19_in;
wire p_0_in20_in;
wire p_0_in22_in;
wire p_0_in24_in;
wire p_0_in26_in;
wire p_0_in28_in;
wire p_0_in2_in;
wire p_0_in49_in;
wire p_0_in51_in;
wire p_0_in53_in;
wire p_0_in55_in;
wire p_0_in57_in;
wire p_0_in59_in;
wire p_0_in5_in;
wire p_0_in64_in;
wire p_0_in74_in;
wire p_0_in85_in;
wire p_0_in8_in;
wire p_0_in96_in;
wire p_17_in;
wire p_1_in;
wire p_1_in21_in;
wire p_1_in23_in;
wire p_1_in25_in;
wire p_1_in27_in;
wire p_1_in29_in;
wire [3:0]plusOp;
wire rst;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire \s_axi_bresp_i[1]_i_1_n_0 ;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [31:0]s_axi_rdata;
wire s_axi_rdata_i;
wire \s_axi_rdata_i[0]_i_2_n_0 ;
wire \s_axi_rdata_i[0]_i_3_n_0 ;
wire \s_axi_rdata_i[0]_i_4_n_0 ;
wire \s_axi_rdata_i[1]_i_2_n_0 ;
wire \s_axi_rdata_i[1]_i_3_n_0 ;
wire \s_axi_rdata_i[1]_i_4_n_0 ;
wire \s_axi_rdata_i[2]_i_2_n_0 ;
wire \s_axi_rdata_i[2]_i_3_n_0 ;
wire \s_axi_rdata_i[2]_i_4_n_0 ;
wire \s_axi_rdata_i[31]_i_4_n_0 ;
wire \s_axi_rdata_i[31]_i_5_n_0 ;
wire \s_axi_rdata_i[3]_i_2_n_0 ;
wire \s_axi_rdata_i[3]_i_3_n_0 ;
wire \s_axi_rdata_i[4]_i_2_n_0 ;
wire \s_axi_rdata_i[4]_i_3_n_0 ;
wire \s_axi_rdata_i[5]_i_2_n_0 ;
wire \s_axi_rdata_i[5]_i_3_n_0 ;
wire \s_axi_rdata_i[6]_i_2_n_0 ;
wire \s_axi_rdata_i[6]_i_3_n_0 ;
wire \s_axi_rdata_i[6]_i_6_n_0 ;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [6:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[0]_i_1_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
system_microblaze_0_axi_intc_0_address_decoder I_DECODER
(.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 (\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ),
.\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] (\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1] ),
.\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] (\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2] ),
.\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] (\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3] ),
.\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] (\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4] ),
.\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] (\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5] ),
.\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] (\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6] ),
.D(IP2Bus_Data),
.\Douta_reg[31] (\Douta_reg[31] ),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Or128_vec2stdlogic(Or128_vec2stdlogic),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.Q(start2),
.\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] (\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0] ),
.\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] (\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ),
.\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0 (\s_axi_rdata_i[0]_i_2_n_0 ),
.\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] (\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1] ),
.\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1] (\s_axi_rdata_i[1]_i_2_n_0 ),
.\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] (\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2] ),
.\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2] (\s_axi_rdata_i[2]_i_4_n_0 ),
.\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] (\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3] ),
.\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] (\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4] ),
.\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] (\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5] ),
.\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] (\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6] ),
.\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] (\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0 ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1 ),
.\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] (\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1] ),
.\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] (\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2] ),
.\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] (\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3] ),
.\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] (\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4] ),
.\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] (\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5] ),
.\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] (\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6] ),
.\bus2ip_addr_i_reg[2] (\s_axi_rdata_i[31]_i_4_n_0 ),
.\bus2ip_addr_i_reg[3] (\s_axi_rdata_i[2]_i_2_n_0 ),
.\bus2ip_addr_i_reg[3]_0 (\s_axi_rdata_i[3]_i_2_n_0 ),
.\bus2ip_addr_i_reg[3]_1 (\s_axi_rdata_i[4]_i_2_n_0 ),
.\bus2ip_addr_i_reg[3]_2 (\s_axi_rdata_i[5]_i_2_n_0 ),
.\bus2ip_addr_i_reg[3]_3 (\s_axi_rdata_i[6]_i_2_n_0 ),
.\bus2ip_addr_i_reg[5] (\s_axi_rdata_i[2]_i_3_n_0 ),
.\bus2ip_addr_i_reg[5]_0 (\s_axi_rdata_i[3]_i_3_n_0 ),
.\bus2ip_addr_i_reg[5]_1 (\s_axi_rdata_i[4]_i_3_n_0 ),
.\bus2ip_addr_i_reg[5]_2 (\s_axi_rdata_i[5]_i_3_n_0 ),
.\bus2ip_addr_i_reg[5]_3 (\s_axi_rdata_i[6]_i_3_n_0 ),
.\bus2ip_addr_i_reg[6] (\s_axi_rdata_i[31]_i_5_n_0 ),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr,Q}),
.bus2ip_rnw_i_reg(bus2ip_rnw_i_reg_n_0),
.bus2ip_wrce(bus2ip_wrce),
.bus2ip_wrce__0(bus2ip_wrce__0),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.\mer_int_reg[0] (\mer_int_reg[0] ),
.\mer_int_reg[0]_0 (\mer_int_reg[0]_0 ),
.\mer_int_reg[1] (\mer_int_reg[1] ),
.p_0_in(p_0_in),
.p_0_in107_in(p_0_in107_in),
.p_0_in118_in(p_0_in118_in),
.p_0_in11_in(p_0_in11_in),
.p_0_in14_in(p_0_in14_in),
.p_0_in2_in(p_0_in2_in),
.p_0_in49_in(p_0_in49_in),
.p_0_in51_in(p_0_in51_in),
.p_0_in53_in(p_0_in53_in),
.p_0_in55_in(p_0_in55_in),
.p_0_in57_in(p_0_in57_in),
.p_0_in59_in(p_0_in59_in),
.p_0_in5_in(p_0_in5_in),
.p_0_in64_in(p_0_in64_in),
.p_0_in74_in(p_0_in74_in),
.p_0_in85_in(p_0_in85_in),
.p_0_in8_in(p_0_in8_in),
.p_0_in96_in(p_0_in96_in),
.p_17_in(p_17_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[2]),
.O(\bus2ip_addr_i[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[5]_i_1
(.I0(s_axi_araddr[3]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[3]),
.O(\bus2ip_addr_i[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[6]_i_1
(.I0(s_axi_araddr[4]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[4]),
.O(\bus2ip_addr_i[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[7]_i_1
(.I0(s_axi_araddr[5]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[5]),
.O(\bus2ip_addr_i[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h03020202))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_awvalid),
.I4(s_axi_wvalid),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hFFFB0008))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[6]),
.I1(s_axi_arvalid),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_awaddr[6]),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(Q[0]),
.R(rst));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(Q[1]),
.R(rst));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[4]_i_1_n_0 ),
.Q(Q[2]),
.R(rst));
FDRE \bus2ip_addr_i_reg[5]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[5]_i_1_n_0 ),
.Q(Q[3]),
.R(rst));
FDRE \bus2ip_addr_i_reg[6]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[6]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(rst));
FDRE \bus2ip_addr_i_reg[7]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[7]_i_1_n_0 ),
.Q(bus2ip_addr[7]),
.R(rst));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[8]),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i_i_1_n_0));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i_i_1_n_0),
.Q(bus2ip_rnw_i_reg_n_0),
.R(rst));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(rst));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(rst));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(SS),
.Q(rst),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(is_read),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I5(ip2bus_rdack),
.O(s_axi_arready));
LUT4 #(
.INIT(16'hFB08))
\s_axi_bresp_i[1]_i_1
(.I0(ip2bus_error),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bresp),
.O(\s_axi_bresp_i[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_bresp_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\s_axi_bresp_i[1]_i_1_n_0 ),
.Q(s_axi_bresp),
.R(rst));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(rst));
LUT6 #(
.INIT(64'h02FF02FF02FF0200))
\s_axi_rdata_i[0]_i_2
(.I0(\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0] ),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[3]),
.I4(\s_axi_rdata_i[0]_i_3_n_0 ),
.I5(\s_axi_rdata_i[0]_i_4_n_0 ),
.O(\s_axi_rdata_i[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h8C008000))
\s_axi_rdata_i[0]_i_3
(.I0(\mer_int_reg[0]_0 ),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(\IVR_GEN.ivr_reg[0]_0 ),
.O(\s_axi_rdata_i[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h1505110114041000))
\s_axi_rdata_i[0]_i_4
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\IPR_GEN.ipr_reg[6] [0]),
.I4(\REG_GEN[0].ier_reg[0] ),
.I5(\REG_GEN[0].isr_reg[0] ),
.O(\s_axi_rdata_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h02FF02FF02FF0200))
\s_axi_rdata_i[1]_i_2
(.I0(p_0_in14_in),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[3]),
.I4(\s_axi_rdata_i[1]_i_3_n_0 ),
.I5(\s_axi_rdata_i[1]_i_4_n_0 ),
.O(\s_axi_rdata_i[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h8C008000))
\s_axi_rdata_i[1]_i_3
(.I0(p_0_in),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(\IVR_GEN.ivr_reg[1] ),
.O(\s_axi_rdata_i[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h1505110114041000))
\s_axi_rdata_i[1]_i_4
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\IPR_GEN.ipr_reg[6] [1]),
.I4(p_0_in28_in),
.I5(p_1_in29_in),
.O(\s_axi_rdata_i[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h2A0A220228082000))
\s_axi_rdata_i[2]_i_2
(.I0(\s_axi_rdata_i[6]_i_6_n_0 ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\IPR_GEN.ipr_reg[6] [2]),
.I4(p_0_in26_in),
.I5(p_1_in27_in),
.O(\s_axi_rdata_i[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0020))
\s_axi_rdata_i[2]_i_3
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(\s_axi_rdata_i[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00220C0000220000))
\s_axi_rdata_i[2]_i_4
(.I0(p_0_in11_in),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(\IVR_GEN.ivr_reg[2] ),
.O(\s_axi_rdata_i[2]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'h000AC000))
\s_axi_rdata_i[31]_i_4
(.I0(Q[0]),
.I1(\IVR_GEN.ivr_reg[0] ),
.I2(Q[2]),
.I3(Q[1]),
.I4(Q[3]),
.O(\s_axi_rdata_i[31]_i_4_n_0 ));
LUT3 #(
.INIT(8'hFE))
\s_axi_rdata_i[31]_i_5
(.I0(bus2ip_addr[6]),
.I1(bus2ip_addr[8]),
.I2(bus2ip_addr[7]),
.O(\s_axi_rdata_i[31]_i_5_n_0 ));
LUT6 #(
.INIT(64'h2A0A220228082000))
\s_axi_rdata_i[3]_i_2
(.I0(\s_axi_rdata_i[6]_i_6_n_0 ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\IPR_GEN.ipr_reg[6] [3]),
.I4(p_0_in24_in),
.I5(p_1_in25_in),
.O(\s_axi_rdata_i[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0200))
\s_axi_rdata_i[3]_i_3
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.I3(p_0_in8_in),
.O(\s_axi_rdata_i[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h2A0A220228082000))
\s_axi_rdata_i[4]_i_2
(.I0(\s_axi_rdata_i[6]_i_6_n_0 ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\IPR_GEN.ipr_reg[6] [4]),
.I4(p_0_in22_in),
.I5(p_1_in23_in),
.O(\s_axi_rdata_i[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h0200))
\s_axi_rdata_i[4]_i_3
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.I3(p_0_in5_in),
.O(\s_axi_rdata_i[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h2A0A220228082000))
\s_axi_rdata_i[5]_i_2
(.I0(\s_axi_rdata_i[6]_i_6_n_0 ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\IPR_GEN.ipr_reg[6] [5]),
.I4(p_0_in20_in),
.I5(p_1_in21_in),
.O(\s_axi_rdata_i[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h0200))
\s_axi_rdata_i[5]_i_3
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.I3(p_0_in2_in),
.O(\s_axi_rdata_i[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'h2A0A220228082000))
\s_axi_rdata_i[6]_i_2
(.I0(\s_axi_rdata_i[6]_i_6_n_0 ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\IPR_GEN.ipr_reg[6] [6]),
.I4(p_0_in19_in),
.I5(p_1_in),
.O(\s_axi_rdata_i[6]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0200))
\s_axi_rdata_i[6]_i_3
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.I3(\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6] ),
.O(\s_axi_rdata_i[6]_i_3_n_0 ));
LUT2 #(
.INIT(4'h1))
\s_axi_rdata_i[6]_i_6
(.I0(Q[2]),
.I1(Q[3]),
.O(\s_axi_rdata_i[6]_i_6_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[0]),
.Q(s_axi_rdata[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[10]),
.Q(s_axi_rdata[10]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[11]),
.Q(s_axi_rdata[11]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[12]),
.Q(s_axi_rdata[12]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[13]),
.Q(s_axi_rdata[13]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[14]),
.Q(s_axi_rdata[14]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[15]),
.Q(s_axi_rdata[15]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[16]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[16]),
.Q(s_axi_rdata[16]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[17]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[17]),
.Q(s_axi_rdata[17]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[18]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[18]),
.Q(s_axi_rdata[18]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[19]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[19]),
.Q(s_axi_rdata[19]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[1]),
.Q(s_axi_rdata[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[20]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[20]),
.Q(s_axi_rdata[20]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[21]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[21]),
.Q(s_axi_rdata[21]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[22]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[22]),
.Q(s_axi_rdata[22]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[23]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[23]),
.Q(s_axi_rdata[23]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[24]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[24]),
.Q(s_axi_rdata[24]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[25]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[25]),
.Q(s_axi_rdata[25]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[26]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[26]),
.Q(s_axi_rdata[26]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[27]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[27]),
.Q(s_axi_rdata[27]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[28]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[28]),
.Q(s_axi_rdata[28]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[29]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[29]),
.Q(s_axi_rdata[29]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[2]),
.Q(s_axi_rdata[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[30]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[30]),
.Q(s_axi_rdata[30]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[31]),
.Q(s_axi_rdata[31]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[3]),
.Q(s_axi_rdata[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[4]),
.Q(s_axi_rdata[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[5]),
.Q(s_axi_rdata[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[6]),
.Q(s_axi_rdata[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[7]),
.Q(s_axi_rdata[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[8]),
.Q(s_axi_rdata[8]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[9]),
.Q(s_axi_rdata[9]),
.R(rst));
LUT5 #(
.INIT(32'h070F0F0F))
\s_axi_rresp_i[1]_i_1
(.I0(s_axi_wstrb[1]),
.I1(s_axi_wstrb[2]),
.I2(bus2ip_rnw_i_reg_n_0),
.I3(s_axi_wstrb[0]),
.I4(s_axi_wstrb[3]),
.O(ip2bus_error));
FDRE #(
.INIT(1'b0))
\s_axi_rresp_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(ip2bus_error),
.Q(s_axi_rresp),
.R(rst));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(rst));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(is_write_reg_n_0),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I5(ip2bus_wrack),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h000F0008))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arvalid),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(rst));
LUT5 #(
.INIT(32'h55FFE4E4))
\state[0]_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wready),
.I3(state1__2),
.I4(state[0]),
.O(\state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h3AFF3AF0))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state1__2),
.I2(state[1]),
.I3(state[0]),
.I4(\state[1]_i_3_n_0 ),
.O(\state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(state[1]),
.R(rst));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLXBN_PP_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_PP_BLACKBOX_V
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length adjuster
*/
module axis_frame_length_adjust #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire status_valid,
input wire status_ready,
output wire status_frame_pad,
output wire status_frame_truncate,
output wire [15:0] status_frame_length,
output wire [15:0] status_frame_original_length,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
// bus word width
localparam DATA_WORD_WIDTH = DATA_WIDTH / KEEP_WIDTH;
// bus width assertions
initial begin
if (DATA_WORD_WIDTH * KEEP_WIDTH != DATA_WIDTH) begin
$error("Error: data width not evenly divisble (instance %m)");
$finish;
end
end
// state register
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_TRANSFER = 3'd1,
STATE_PAD = 3'd2,
STATE_TRUNCATE = 3'd3;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_last_word;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
// frame length counters
reg [15:0] short_counter_reg = 16'd0, short_counter_next = 16'd0;
reg [15:0] long_counter_reg = 16'd0, long_counter_next = 16'd0;
reg [DATA_WIDTH-1:0] last_word_data_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] last_word_keep_reg = {KEEP_WIDTH{1'b0}};
reg [ID_WIDTH-1:0] last_word_id_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] last_word_dest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] last_word_user_reg = {USER_WIDTH{1'b0}};
reg status_valid_reg = 1'b0, status_valid_next;
reg status_frame_pad_reg = 1'b0, status_frame_pad_next;
reg status_frame_truncate_reg = 1'b0, status_frame_truncate_next;
reg [15:0] status_frame_length_reg = 16'd0, status_frame_length_next;
reg [15:0] status_frame_original_length_reg = 16'd0, status_frame_original_length_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
assign s_axis_tready = s_axis_tready_reg;
assign status_valid = status_valid_reg;
assign status_frame_pad = status_frame_pad_reg;
assign status_frame_truncate = status_frame_truncate_reg;
assign status_frame_length = status_frame_length_reg;
assign status_frame_original_length = status_frame_original_length_reg;
integer i, word_cnt;
always @* begin
state_next = STATE_IDLE;
store_last_word = 1'b0;
frame_ptr_next = frame_ptr_reg;
short_counter_next = short_counter_reg;
long_counter_next = long_counter_reg;
m_axis_tdata_int = {DATA_WIDTH{1'b0}};
m_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tid_int = {ID_WIDTH{1'b0}};
m_axis_tdest_int = {DEST_WIDTH{1'b0}};
m_axis_tuser_int = {USER_WIDTH{1'b0}};
s_axis_tready_next = 1'b0;
status_valid_next = status_valid_reg && !status_ready;
status_frame_pad_next = status_frame_pad_reg;
status_frame_truncate_next = status_frame_truncate_reg;
status_frame_length_next = status_frame_length_reg;
status_frame_original_length_next = status_frame_original_length_reg;
if (KEEP_ENABLE) begin
for (i = 0; i < KEEP_WIDTH; i = i + 1) begin
s_axis_tdata_masked[i*DATA_WORD_WIDTH +: DATA_WORD_WIDTH] = s_axis_tkeep[i] ? s_axis_tdata[i*DATA_WORD_WIDTH +: DATA_WORD_WIDTH] : {DATA_WORD_WIDTH{1'b0}};
end
end else begin
s_axis_tdata_masked = s_axis_tdata;
end
case (state_reg)
STATE_IDLE: begin
// idle state
// accept data next cycle if output register ready next cycle
s_axis_tready_next = m_axis_tready_int_early && (!status_valid_reg || status_ready);
m_axis_tdata_int = s_axis_tdata_masked;
m_axis_tkeep_int = s_axis_tkeep;
m_axis_tvalid_int = s_axis_tvalid;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = s_axis_tid;
m_axis_tdest_int = s_axis_tdest;
m_axis_tuser_int = s_axis_tuser;
short_counter_next = length_min;
long_counter_next = length_max;
if (s_axis_tready && s_axis_tvalid) begin
// transfer through
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (s_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (long_counter_reg <= word_cnt) begin
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-long_counter_reg);
if (s_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = word_cnt > long_counter_reg;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
m_axis_tvalid_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_TRUNCATE;
end
end else begin
if (s_axis_tlast) begin
status_frame_original_length_next = frame_ptr_reg+word_cnt;
if (short_counter_reg > word_cnt) begin
if (short_counter_reg > KEEP_WIDTH) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
s_axis_tready_next = 1'b0;
m_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
m_axis_tlast_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_PAD;
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-(length_min - frame_ptr_reg));
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b0;
status_frame_length_next = frame_ptr_reg+word_cnt;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_TRANSFER: begin
// transfer data
// accept data next cycle if output register ready next cycle
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = s_axis_tdata_masked;
m_axis_tkeep_int = s_axis_tkeep;
m_axis_tvalid_int = s_axis_tvalid;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = s_axis_tid;
m_axis_tdest_int = s_axis_tdest;
m_axis_tuser_int = s_axis_tuser;
if (s_axis_tready && s_axis_tvalid) begin
// transfer through
word_cnt = 1;
for (i = 1; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (s_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (long_counter_reg <= word_cnt) begin
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-long_counter_reg);
if (s_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = word_cnt > long_counter_reg;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
m_axis_tvalid_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_TRUNCATE;
end
end else begin
if (s_axis_tlast) begin
status_frame_original_length_next = frame_ptr_reg+word_cnt;
if (short_counter_reg > word_cnt) begin
if (short_counter_reg > KEEP_WIDTH) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
s_axis_tready_next = 1'b0;
m_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
m_axis_tlast_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_PAD;
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg);
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b0;
status_frame_length_next = frame_ptr_reg+word_cnt;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
STATE_PAD: begin
// pad to minimum length
s_axis_tready_next = 1'b0;
m_axis_tdata_int = {DATA_WIDTH{1'b0}};
m_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_int = 1'b1;
m_axis_tlast_int = 1'b0;
m_axis_tid_int = last_word_id_reg;
m_axis_tdest_int = last_word_dest_reg;
m_axis_tuser_int = last_word_user_reg;
if (m_axis_tready_int_reg) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (short_counter_reg <= KEEP_WIDTH) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg);
m_axis_tlast_int = 1'b1;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAD;
end
end else begin
state_next = STATE_PAD;
end
end
STATE_TRUNCATE: begin
// drop after maximum length
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = last_word_data_reg;
m_axis_tkeep_int = last_word_keep_reg;
m_axis_tvalid_int = s_axis_tvalid && s_axis_tlast;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = last_word_id_reg;
m_axis_tdest_int = last_word_dest_reg;
m_axis_tuser_int = s_axis_tuser;
if (s_axis_tready && s_axis_tvalid) begin
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (s_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (s_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b1;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRUNCATE;
end
end else begin
state_next = STATE_TRUNCATE;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
short_counter_reg <= 16'd0;
long_counter_reg <= 16'd0;
s_axis_tready_reg <= 1'b0;
status_valid_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
short_counter_reg <= short_counter_next;
long_counter_reg <= long_counter_next;
s_axis_tready_reg <= s_axis_tready_next;
status_valid_reg <= status_valid_next;
end
status_frame_pad_reg <= status_frame_pad_next;
status_frame_truncate_reg <= status_frame_truncate_next;
status_frame_length_reg <= status_frame_length_next;
status_frame_original_length_reg <= status_frame_original_length_next;
if (store_last_word) begin
last_word_data_reg <= m_axis_tdata_int;
last_word_keep_reg <= m_axis_tkeep_int;
last_word_id_reg <= m_axis_tid_int;
last_word_dest_reg <= m_axis_tdest_int;
last_word_user_reg <= m_axis_tuser_int;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ccnu
// Engineer: Poyi Xiong
//
// Create Date: 01/13/2017 11:27:24 AM
// Design Name:
// Module Name: SR_Control_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SR_Control_tb();
reg [WIDTH-1:0] din;
reg clk;
reg rst;
reg start;
wire clk_sr;
wire din_sr;
wire load_sr;
parameter WIDTH=170;
SR_Control DUT2(
.din(din),
.clk(clk),
.rst(rst),
.start(start),
.clk_sr(clk_sr),
.din_sr(din_sr),
.load_sr(load_sr)
);
initial begin
$dumpfile("sr_control.dump");
$dumpvars(0,SR_Control);
end
initial begin
clk=0;
forever #50 clk=~clk;
end
initial begin
rst=1;
#200 rst=0;
end
initial begin
din={1'b1,169'b1011};
start=0;
#450 start=1;
#100 start=0;
end
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/slowadt7410.v:1" *)
(* top = 1 *)
module SlowADT7410(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, I2C_ReceiveSend_n_o, I2C_ReadCount_o, I2C_StartProcess_o, I2C_Busy_i, I2C_FIFOReadNext_o, I2C_FIFOWrite_o, I2C_Data_o, I2C_Data_i, I2C_Error_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, WaitCounterPresetH_i, WaitCounterPresetL_i);
wire \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.Overflow_s ;
wire \$techmap\I2CFSM_1.$procmux$1156_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1168_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1169_CMP ;
wire [7:0] \$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.Overflow_s ;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/slowadt7410.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/slowadt7410.v:9" *)
output CpuIntr_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/slowadt7410.v:7" *)
input Enable_i;
(* src = "../../verilog/i2cfsm.v:10" *)
wire [7:0] \I2CFSM_1.Byte0_o ;
(* src = "../../verilog/i2cfsm.v:11" *)
wire [7:0] \I2CFSM_1.Byte1_o ;
(* src = "../../verilog/i2cfsm.v:8" *)
wire \I2CFSM_1.Done_o ;
(* src = "../../verilog/i2cfsm.v:9" *)
wire \I2CFSM_1.Error_o ;
(* src = "../../verilog/i2cfsm.v:78" *)
wire \I2CFSM_1.I2C_FSM_TimerEnable ;
(* src = "../../verilog/i2cfsm.v:76" *)
wire \I2CFSM_1.I2C_FSM_TimerOvfl ;
(* src = "../../verilog/i2cfsm.v:77" *)
wire \I2CFSM_1.I2C_FSM_TimerPreset ;
(* src = "../../verilog/i2cfsm.v:80" *)
wire \I2CFSM_1.I2C_FSM_Wr0 ;
(* src = "../../verilog/i2cfsm.v:79" *)
wire \I2CFSM_1.I2C_FSM_Wr1 ;
(* src = "../../verilog/i2cfsm.v:7" *)
wire \I2CFSM_1.Start_i ;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_Busy" *)
(* src = "../../verilog/slowadt7410.v:17" *)
input I2C_Busy_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_DataOut" *)
(* src = "../../verilog/slowadt7410.v:25" *)
input [7:0] I2C_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_DataIn" *)
(* src = "../../verilog/slowadt7410.v:23" *)
output [7:0] I2C_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_Error" *)
(* src = "../../verilog/slowadt7410.v:27" *)
input I2C_Error_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_FIFOReadNext" *)
(* src = "../../verilog/slowadt7410.v:19" *)
output I2C_FIFOReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_FIFOWrite" *)
(* src = "../../verilog/slowadt7410.v:21" *)
output I2C_FIFOWrite_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "I2C_ReadCount" *)
(* src = "../../verilog/slowadt7410.v:13" *)
output [7:0] I2C_ReadCount_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_ReceiveSend_n" *)
(* src = "../../verilog/slowadt7410.v:11" *)
output I2C_ReceiveSend_n_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "I2C_StartProcess" *)
(* src = "../../verilog/slowadt7410.v:15" *)
output I2C_StartProcess_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetH_i" *)
(* src = "../../verilog/slowadt7410.v:29" *)
input [15:0] PeriodCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetL_i" *)
(* src = "../../verilog/slowadt7410.v:31" *)
input [15:0] PeriodCounterPresetL_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/slowadt7410.v:3" *)
input Reset_n_i;
(* src = "../../verilog/sensorfsm.v:42" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:36" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:34" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:40" *)
wire [15:0] \SensorFSM_1.SensorValue ;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/slowadt7410.v:33" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/slowadt7410.v:35" *)
input [15:0] Threshold_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "WaitCounterPresetH_i" *)
(* src = "../../verilog/slowadt7410.v:37" *)
input [15:0] WaitCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "WaitCounterPresetL_i" *)
(* src = "../../verilog/slowadt7410.v:39" *)
input [15:0] WaitCounterPresetL_i;
Byte2Word \$extract$\Byte2Word$2915 (
.H_i(\I2CFSM_1.Byte1_o ),
.L_i(\I2CFSM_1.Byte0_o ),
.Y_o(\SensorFSM_1.SensorValue )
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2910 (
.A_i(8'b00000000),
.B_i(8'b00000010),
.S_i(I2C_ReceiveSend_n_o),
.Y_o(I2C_ReadCount_o)
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2911 (
.A_i(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ),
.B_i(8'b00000011),
.S_i(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Y_o(I2C_Data_o)
);
ByteMuxQuad \$techmap\I2CFSM_1.$extract$\ByteMuxQuad$2909 (
.A_i(8'b00000000),
.B_i(8'b10010001),
.C_i(8'b10010000),
.D_i(8'b00100000),
.SAB_i(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.SC_i(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.SD_i(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Y_o(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y )
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2906 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr0 ),
.Q_o(\I2CFSM_1.Byte0_o ),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2907 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr1 ),
.Q_o(\I2CFSM_1.Byte1_o ),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DH_s ),
.DL_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DL_s ),
.Direction_i(1'b1),
.Enable_i(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Overflow_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.Overflow_s ),
.PresetValH_i(WaitCounterPresetH_i),
.PresetValL_i(WaitCounterPresetL_i),
.Preset_i(\I2CFSM_1.I2C_FSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\I2CFSM_1.I2C_FSM_TimerOvfl )
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/i2cfsm.v:74" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000100),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000001110),
.NAME("\\I2C_FSM_State"),
.STATE_BITS(32'b00000000000000000000000000000100),
.STATE_NUM(32'b00000000000000000000000000001101),
.STATE_NUM_LOG2(32'b00000000000000000000000000000100),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(52'b0111101100110101100100010110101000101100010010000000),
.TRANS_NUM(32'b00000000000000000000000000010011),
.TRANS_TABLE(494'b1100zzzz0001010000010000001011zzzz0011010100000100001010zzzz0010010000010000001001z0zz1001001000100000001001z1zz0110110000100000001000zzzz0101010000011000000111zzzz0100110000000001000110zzzz1100110000000000000101zzz01011010110001000000101zzz10101010000001000000100zzzz1010110000000000100011zzzz0000010000000010000010zz001001001000000000000010zz010010010000000000000010zz1z0000010001000000000001zzz01000110000000000010001zzz100010100000000000100001zzz01111100001000000000000zzz000001000010000000)
) \$techmap\I2CFSM_1.$fsm$\I2C_FSM_State$2843 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ \I2CFSM_1.Start_i , \I2CFSM_1.I2C_FSM_TimerOvfl , I2C_Error_i, I2C_Busy_i }),
.CTRL_OUT({ I2C_FIFOWrite_o, \I2CFSM_1.I2C_FSM_TimerPreset , \I2CFSM_1.I2C_FSM_TimerEnable , I2C_FIFOReadNext_o, \I2CFSM_1.I2C_FSM_Wr1 , \I2CFSM_1.Error_o , \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 , I2C_StartProcess_o, I2C_ReceiveSend_n_o, \I2CFSM_1.I2C_FSM_Wr0 , \I2CFSM_1.Done_o , \$techmap\I2CFSM_1.$procmux$1169_CMP , \$techmap\I2CFSM_1.$procmux$1168_CMP , \$techmap\I2CFSM_1.$procmux$1156_CMP })
);
AbsDiff \$techmap\SensorFSM_1.$extract$\AbsDiff$2904 (
.A_i(\SensorFSM_1.SensorValue ),
.B_i(SensorValue_o),
.D_o(\SensorFSM_1.AbsDiffResult )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.ThisAddSubCmp (
.A_i(\SensorFSM_1.AbsDiffResult ),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.D_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ),
.Sign_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ),
.Zero_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s )
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DH_s ),
.DL_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DL_s ),
.Direction_i(1'b1),
.Enable_i(\SensorFSM_1.SensorFSM_TimerEnable ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.Overflow_s ),
.PresetValH_i(PeriodCounterPresetH_i),
.PresetValL_i(PeriodCounterPresetL_i),
.Preset_i(\SensorFSM_1.SensorFSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SensorFSM_1.SensorFSM_TimerOvfl )
);
WordRegister \$techmap\SensorFSM_1.$extract$\WordRegister$2905 (
.Clk_i(Clk_i),
.D_i(\SensorFSM_1.SensorValue ),
.Enable_i(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/sensorfsm.v:30" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000110),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000101),
.NAME("\\SensorFSM_State"),
.STATE_BITS(32'b00000000000000000000000000000011),
.STATE_NUM(32'b00000000000000000000000000000101),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(15'b011001010100000),
.TRANS_NUM(32'b00000000000000000000000000001101),
.TRANS_TABLE(221'b100zzzzzz01110100011zz0zz101101000011zz1zz101001001011zzzzz00000100001001z01z100010100101zz01z0111000001000z01z01110000010zzz00z01010000010zzz1zz00110100001zzzzz100110000001zzzzz000010000000zzzzz101101000000zzzzz000010000)
) \$techmap\SensorFSM_1.$fsm$\SensorFSM_State$2836 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s , \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s , \SensorFSM_1.SensorFSM_TimerOvfl , \I2CFSM_1.Error_o , \I2CFSM_1.Done_o , Enable_i }),
.CTRL_OUT({ \SensorFSM_1.SensorFSM_TimerPreset , \SensorFSM_1.SensorFSM_TimerEnable , CpuIntr_o, \SensorFSM_1.SensorFSM_StoreNewValue , \I2CFSM_1.Start_i })
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
|
`timescale 1ns/10ps
module pll_vga_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("25.0 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.rst (rst),
.refclk (refclk)
);
endmodule
|
// file: Clock70MHz_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module Clock70MHz_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
Clock70MHz clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int),
// Status and control signals
.LOCKED (LOCKED));
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
// (C) 1992-2018 Intel Corporation.
// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
// and/or other countries. Other marks and brands may be claimed as the property
// of others. See Trademarks on intel.com for full list of Intel trademarks or
// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
module top (
fpga_clk_50,
fpga_reset_n,
fpga_led_output,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl,
LCD_TE,
LCD_SDI,
LCD_WR_SCLK,
LCD_CS,
LCD_RS_HSD,
LCD_RD_VSD,
LCD_DATA,
LCD_ENABLE,
LCD_PCLK,
TOUCH_SCK,
TOUCH_SDA,
TOUCH_INT
);
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [3:0] fpga_led_output;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
/// GPIO_0
input wire LCD_TE;
inout wire LCD_SDI;
output wire LCD_WR_SCLK;
output wire LCD_CS;
output wire LCD_RS_HSD;
output wire LCD_RD_VSD;
inout wire [23:0] LCD_DATA;
output wire LCD_ENABLE;
output wire LCD_PCLK;
output wire TOUCH_SCK;
inout wire TOUCH_SDA;
input wire TOUCH_INT;
wire [29:0] fpga_internal_led;
wire kernel_clk;
wire [7:0] NC_wire;
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT), // .hps_io_usb1_inst_NXT
.acl_iface_tft_lcd_export_cs (LCD_CS), // acl_iface_tft_lcd_export.cs
.acl_iface_tft_lcd_export_rs (LCD_RS_HSD), // .rs
.acl_iface_tft_lcd_export_wr (LCD_WR_SCLK), // .wr
.acl_iface_tft_lcd_export_rd (LCD_RD_VSD), // .rd
.acl_iface_tft_lcd_export_data ({NC_wire,LCD_DATA}) // .data
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
endmodule
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule
|
/*!
* <b>Module:</b>gtx_10x8dec
* @file gtx_10x8dec.v
* @date 2015-07-11
* @author Alexey
*
* @brief 8x10 encoder implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* gtx_10x8dec.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtx_10x8dec.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
module gtx_10x8dec(
input wire rst,
input wire clk,
input wire [19:0] indata,
output wire [15:0] outdata,
output wire [1:0] outisk,
output wire [1:0] notintable,
output wire [1:0] disperror
/* uncomment if necessary
input wire [0:0] inaux,
output wire [0:0] outaux, */
);
/*
uncomment if necessary
// bypass auxilary informational signals
reg [0:0] aux_r;
reg [0:0] aux_rr;
always @ (posedge clk)
begin
aux_r <= inaux;
aux_rr <= aux_r;
end
assign outaux = aux_rr;
*/
// split incoming data in 2 bytes
wire [9:0] addr0;
wire [9:0] addr1;
assign addr0 = indata[9:0];
assign addr1 = indata[19:10];
// get decoded values after 2 clock cycles, all '1's = cannot be decoded
wire [15:0] table0_out;
wire [15:0] table1_out;
wire [10:0] table0;
wire [10:0] table1;
assign table0 = table0_out[10:0];
assign table1 = table1_out[10:0];
assign outdata = {table1[7:0], table0[7:0]};
assign outisk = {table1[8], table0[8]};
assign notintable = {&table1, &table0};
// disparity control
// last clock disparity
reg disparity;
// disparity after 1st byte
wire disparity_interm;
// delayed ones
reg disp0_r;
reg disp0_rr;
reg disp1_r;
reg disp1_rr;
always @ (posedge clk)
begin
disp0_r <= disparity;
disp0_rr <= disp0_r;
disp1_r <= disparity_interm;
disp1_rr <= disp1_r;
end
// overall expected disparity when the table values would apper - disp0_r.
// disp1_rr shows expected after 0st byte would be considered
reg correct_table_disp;
wire expected_disparity;
wire expected_disparity_interm;
assign expected_disparity = disp0_rr ^ correct_table_disp;
assign expected_disparity_interm = disp1_rr ^ correct_table_disp;
// invert disparity after a byte
// if current encoded word containg an equal amount of 1s and 0s (i.e. 5 x '1'), disp shall stay the same
// if amounts are unequal, there are either 4 or 6 '1's. in either case disp shall be inverted
wire inv_disp0;
wire inv_disp1;
assign inv_disp0 = ~^(indata[9:0]);
assign inv_disp1 = ~^(indata[19:10]);
assign disparity_interm = inv_disp0 ? ~disparity : disparity;
always @ (posedge clk)
disparity <= rst ? 1'b0 : inv_disp1 ^ inv_disp0 ? ~disparity : disparity;
// to correct disparity if once an error occured
always @ (posedge clk)
correct_table_disp <= rst ? 1'b0 : disperror[1] ? ~correct_table_disp : correct_table_disp;
// calculate disparity on table values
wire table_pos_disp0;
wire table_neg_disp0;
wire table_pos_disp1;
wire table_neg_disp1;
// table_pos_disp - for current 10-bit word disparity can be positive
// _neg_ - can be negative
// neg & pos - can be either of them
assign table_pos_disp0 = table0[10];
assign table_neg_disp0 = table0[9];
assign table_pos_disp1 = table1[10];
assign table_neg_disp1 = table1[9];
assign disperror = ~{table_pos_disp0 & expected_disparity | table_neg_disp0 & ~expected_disparity, table_pos_disp1 & expected_disparity_interm | table_neg_disp1 & ~expected_disparity_interm};
// TODO change mem to 18 instead of 36, so the highest address bit could be dropped
ramt_var_w_var_r #(
.REGISTERS_A (1),
.REGISTERS_B (1),
.LOG2WIDTH_A (4),
.LOG2WIDTH_B (4)
`include "gtx_10x8dec_init.v"
)
decoding_table(
.clk_a (clk),
.addr_a ({1'b0, addr0}),
.en_a (1'b1),
.regen_a (1'b1),
.we_a (1'b0),
.data_out_a (table0_out),
.data_in_a (16'h0),
.clk_b (clk),
.addr_b ({1'b0, addr1}),
.en_b (1'b1),
.regen_b (1'b1),
.we_b (1'b0),
.data_out_b (table1_out),
.data_in_b (16'h0)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 22:04:02 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
(E,
bid_gets_fifo_load,
bvalid_cnt_inc,
bid_gets_fifo_load_d1_reg,
D,
axi_wdata_full_cmb114_out,
SR,
s_axi_aclk,
\bvalid_cnt_reg[2] ,
wr_addr_sm_cs,
\bvalid_cnt_reg[2]_0 ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
axi_awaddr_full,
bram_addr_ld_en,
bid_gets_fifo_load_d1,
s_axi_bready,
axi_bvalid_int_reg,
bvalid_cnt,
Q,
s_axi_awid,
\bvalid_cnt_reg[1] ,
aw_active,
s_axi_awready,
s_axi_awvalid,
curr_awlen_reg_1_or_2,
axi_awlen_pipe_1_or_2,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
last_data_ack_mod,
out,
axi_wr_burst,
s_axi_wvalid,
s_axi_wlast);
output [0:0]E;
output bid_gets_fifo_load;
output bvalid_cnt_inc;
output bid_gets_fifo_load_d1_reg;
output [11:0]D;
output axi_wdata_full_cmb114_out;
input [0:0]SR;
input s_axi_aclk;
input \bvalid_cnt_reg[2] ;
input wr_addr_sm_cs;
input \bvalid_cnt_reg[2]_0 ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input axi_awaddr_full;
input bram_addr_ld_en;
input bid_gets_fifo_load_d1;
input s_axi_bready;
input axi_bvalid_int_reg;
input [2:0]bvalid_cnt;
input [11:0]Q;
input [11:0]s_axi_awid;
input \bvalid_cnt_reg[1] ;
input aw_active;
input s_axi_awready;
input s_axi_awvalid;
input curr_awlen_reg_1_or_2;
input axi_awlen_pipe_1_or_2;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input last_data_ack_mod;
input [2:0]out;
input axi_wr_burst;
input s_axi_wvalid;
input s_axi_wlast;
wire \Addr_Counters[0].FDRE_I_n_0 ;
wire \Addr_Counters[1].FDRE_I_n_0 ;
wire \Addr_Counters[2].FDRE_I_n_0 ;
wire \Addr_Counters[3].FDRE_I_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
wire CI;
wire [11:0]D;
wire D_0;
wire Data_Exists_DFF_i_2_n_0;
wire Data_Exists_DFF_i_3_n_0;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire [11:0]Q;
wire S;
wire S0_out;
wire S1_out;
wire [0:0]SR;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire \axi_bid_int[11]_i_3_n_0 ;
wire axi_bvalid_int_i_4_n_0;
wire axi_bvalid_int_i_5_n_0;
wire axi_bvalid_int_i_6_n_0;
wire axi_bvalid_int_reg;
wire axi_wdata_full_cmb114_out;
wire axi_wr_burst;
wire [11:0]bid_fifo_ld;
wire bid_fifo_not_empty;
wire [11:0]bid_fifo_rd;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_3_n_0;
wire bid_gets_fifo_load_d1_reg;
wire bram_addr_ld_en;
wire [2:0]bvalid_cnt;
wire bvalid_cnt_inc;
wire \bvalid_cnt_reg[1] ;
wire \bvalid_cnt_reg[2] ;
wire \bvalid_cnt_reg[2]_0 ;
wire curr_awlen_reg_1_or_2;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire [11:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_wlast;
wire s_axi_wvalid;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire wr_addr_sm_cs;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_3),
.Q(\Addr_Counters[0].FDRE_I_n_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[0].MUXCY_L_I_i_1
(.I0(\Addr_Counters[1].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[0].FDRE_I_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h8AAAAAAAAAAAAAAA))
\Addr_Counters[0].MUXCY_L_I_i_2
(.I0(bram_addr_ld_en),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[1].FDRE_I_n_0 ),
.I4(\Addr_Counters[3].FDRE_I_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(CI));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_2),
.Q(\Addr_Counters[1].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[1].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[1].FDRE_I_n_0 ),
.O(S1_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_1),
.Q(\Addr_Counters[2].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[2].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(S0_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_0),
.Q(\Addr_Counters[3].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[3].XORCY_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[3].FDRE_I_n_0 ),
.O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D_0),
.Q(bid_fifo_not_empty),
.R(SR));
LUT4 #(
.INIT(16'hFE0A))
Data_Exists_DFF_i_1
(.I0(bram_addr_ld_en),
.I1(Data_Exists_DFF_i_2_n_0),
.I2(Data_Exists_DFF_i_3_n_0),
.I3(bid_fifo_not_empty),
.O(D_0));
LUT6 #(
.INIT(64'h000000000000FFFD))
Data_Exists_DFF_i_2
(.I0(bvalid_cnt_inc),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(bid_gets_fifo_load_d1_reg),
.I5(bid_gets_fifo_load_d1),
.O(Data_Exists_DFF_i_2_n_0));
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(\Addr_Counters[2].FDRE_I_n_0 ),
.O(Data_Exists_DFF_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[11]),
.Q(bid_fifo_rd[11]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[0].SRL16E_I_i_1
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.O(bid_fifo_ld[11]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[10].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[1]),
.Q(bid_fifo_rd[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[10].SRL16E_I_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.O(bid_fifo_ld[1]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[11].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[0]),
.Q(bid_fifo_rd[0]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[11].SRL16E_I_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.O(bid_fifo_ld[0]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[1].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[10]),
.Q(bid_fifo_rd[10]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[1].SRL16E_I_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.O(bid_fifo_ld[10]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[2].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[9]),
.Q(bid_fifo_rd[9]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[2].SRL16E_I_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.O(bid_fifo_ld[9]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[3].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[8]),
.Q(bid_fifo_rd[8]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[3].SRL16E_I_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.O(bid_fifo_ld[8]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[4].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[7]),
.Q(bid_fifo_rd[7]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[4].SRL16E_I_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.O(bid_fifo_ld[7]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[5].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[6]),
.Q(bid_fifo_rd[6]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[5].SRL16E_I_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.O(bid_fifo_ld[6]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[6].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[5]),
.Q(bid_fifo_rd[5]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[6].SRL16E_I_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.O(bid_fifo_ld[5]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[7].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[4]),
.Q(bid_fifo_rd[4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[7].SRL16E_I_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.O(bid_fifo_ld[4]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[8].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[3]),
.Q(bid_fifo_rd[3]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[8].SRL16E_I_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.O(bid_fifo_ld[3]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[9].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[2]),
.Q(bid_fifo_rd[2]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[9].SRL16E_I_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.O(bid_fifo_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[0]_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[10]_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[10]),
.O(D[10]));
LUT2 #(
.INIT(4'hE))
\axi_bid_int[11]_i_1
(.I0(bid_gets_fifo_load),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[11]_i_2
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[11]),
.O(D[11]));
LUT6 #(
.INIT(64'hA888AAAAA8888888))
\axi_bid_int[11]_i_3
(.I0(bid_fifo_not_empty),
.I1(bid_gets_fifo_load_d1),
.I2(s_axi_bready),
.I3(axi_bvalid_int_reg),
.I4(bid_gets_fifo_load_d1_i_3_n_0),
.I5(bvalid_cnt_inc),
.O(\axi_bid_int[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[1]_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[2]_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[3]_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[4]_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[5]_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[6]_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[7]_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[8]_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[9]_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[9]),
.O(D[9]));
LUT6 #(
.INIT(64'h000055FD00000000))
axi_bvalid_int_i_2
(.I0(out[2]),
.I1(axi_wdata_full_cmb114_out),
.I2(axi_bvalid_int_i_4_n_0),
.I3(axi_wr_burst),
.I4(out[1]),
.I5(axi_bvalid_int_i_5_n_0),
.O(bvalid_cnt_inc));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'hFE000000))
axi_bvalid_int_i_3
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(axi_bvalid_int_reg),
.I4(s_axi_bready),
.O(bid_gets_fifo_load_d1_reg));
LUT6 #(
.INIT(64'h1F11000000000000))
axi_bvalid_int_i_4
(.I0(axi_bvalid_int_i_6_n_0),
.I1(\bvalid_cnt_reg[2] ),
.I2(wr_addr_sm_cs),
.I3(\bvalid_cnt_reg[2]_0 ),
.I4(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I5(axi_awaddr_full),
.O(axi_bvalid_int_i_4_n_0));
LUT5 #(
.INIT(32'h74446444))
axi_bvalid_int_i_5
(.I0(out[0]),
.I1(out[2]),
.I2(s_axi_wvalid),
.I3(s_axi_wlast),
.I4(axi_wdata_full_cmb114_out),
.O(axi_bvalid_int_i_5_n_0));
LUT5 #(
.INIT(32'hFEFFFFFF))
axi_bvalid_int_i_6
(.I0(curr_awlen_reg_1_or_2),
.I1(axi_awlen_pipe_1_or_2),
.I2(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I3(axi_awaddr_full),
.I4(last_data_ack_mod),
.O(axi_bvalid_int_i_6_n_0));
LUT6 #(
.INIT(64'h7F7F7F007F007F00))
axi_wready_int_mod_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(aw_active),
.I4(s_axi_awready),
.I5(s_axi_awvalid),
.O(axi_wdata_full_cmb114_out));
LUT6 #(
.INIT(64'h00000800AA00AA00))
bid_gets_fifo_load_d1_i_1
(.I0(bram_addr_ld_en),
.I1(bid_gets_fifo_load_d1_reg),
.I2(bid_fifo_not_empty),
.I3(bvalid_cnt_inc),
.I4(\bvalid_cnt_reg[1] ),
.I5(bid_gets_fifo_load_d1_i_3_n_0),
.O(bid_gets_fifo_load));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hFE))
bid_gets_fifo_load_d1_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(bid_gets_fifo_load_d1_i_3_n_0));
endmodule
(* C_BRAM_ADDR_WIDTH = "11" *) (* C_BRAM_INST_MODE = "EXTERNAL" *) (* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *) (* C_ECC_TYPE = "0" *) (* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *) (* C_MEMORY_DEPTH = "2048" *) (* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *) (* C_S_AXI_ADDR_WIDTH = "13" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
(s_axi_aclk,
s_axi_aresetn,
ecc_interrupt,
ecc_ue,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_ctrl_awvalid,
s_axi_ctrl_awready,
s_axi_ctrl_awaddr,
s_axi_ctrl_wdata,
s_axi_ctrl_wvalid,
s_axi_ctrl_wready,
s_axi_ctrl_bresp,
s_axi_ctrl_bvalid,
s_axi_ctrl_bready,
s_axi_ctrl_araddr,
s_axi_ctrl_arvalid,
s_axi_ctrl_arready,
s_axi_ctrl_rdata,
s_axi_ctrl_rresp,
s_axi_ctrl_rvalid,
s_axi_ctrl_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
input s_axi_aclk;
input s_axi_aresetn;
output ecc_interrupt;
output ecc_ue;
input [11:0]s_axi_awid;
input [12:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [12:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_ctrl_awvalid;
output s_axi_ctrl_awready;
input [31:0]s_axi_ctrl_awaddr;
input [31:0]s_axi_ctrl_wdata;
input s_axi_ctrl_wvalid;
output s_axi_ctrl_wready;
output [1:0]s_axi_ctrl_bresp;
output s_axi_ctrl_bvalid;
input s_axi_ctrl_bready;
input [31:0]s_axi_ctrl_araddr;
input s_axi_ctrl_arvalid;
output s_axi_ctrl_arready;
output [31:0]s_axi_ctrl_rdata;
output [1:0]s_axi_ctrl_rresp;
output s_axi_ctrl_rvalid;
input s_axi_ctrl_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [12:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [12:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
wire \<const0> ;
wire [12:2]\^bram_addr_a ;
wire [12:2]\^bram_addr_b ;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [12:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [12:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign bram_addr_a[12:2] = \^bram_addr_a [12:2];
assign bram_addr_a[1] = \<const0> ;
assign bram_addr_a[0] = \<const0> ;
assign bram_addr_b[12:2] = \^bram_addr_b [12:2];
assign bram_addr_b[1] = \<const0> ;
assign bram_addr_b[0] = \<const0> ;
assign bram_clk_a = s_axi_aclk;
assign bram_clk_b = s_axi_aclk;
assign bram_rst_b = bram_rst_a;
assign bram_we_b[3] = \<const0> ;
assign bram_we_b[2] = \<const0> ;
assign bram_we_b[1] = \<const0> ;
assign bram_we_b[0] = \<const0> ;
assign bram_wrdata_b[31] = \<const0> ;
assign bram_wrdata_b[30] = \<const0> ;
assign bram_wrdata_b[29] = \<const0> ;
assign bram_wrdata_b[28] = \<const0> ;
assign bram_wrdata_b[27] = \<const0> ;
assign bram_wrdata_b[26] = \<const0> ;
assign bram_wrdata_b[25] = \<const0> ;
assign bram_wrdata_b[24] = \<const0> ;
assign bram_wrdata_b[23] = \<const0> ;
assign bram_wrdata_b[22] = \<const0> ;
assign bram_wrdata_b[21] = \<const0> ;
assign bram_wrdata_b[20] = \<const0> ;
assign bram_wrdata_b[19] = \<const0> ;
assign bram_wrdata_b[18] = \<const0> ;
assign bram_wrdata_b[17] = \<const0> ;
assign bram_wrdata_b[16] = \<const0> ;
assign bram_wrdata_b[15] = \<const0> ;
assign bram_wrdata_b[14] = \<const0> ;
assign bram_wrdata_b[13] = \<const0> ;
assign bram_wrdata_b[12] = \<const0> ;
assign bram_wrdata_b[11] = \<const0> ;
assign bram_wrdata_b[10] = \<const0> ;
assign bram_wrdata_b[9] = \<const0> ;
assign bram_wrdata_b[8] = \<const0> ;
assign bram_wrdata_b[7] = \<const0> ;
assign bram_wrdata_b[6] = \<const0> ;
assign bram_wrdata_b[5] = \<const0> ;
assign bram_wrdata_b[4] = \<const0> ;
assign bram_wrdata_b[3] = \<const0> ;
assign bram_wrdata_b[2] = \<const0> ;
assign bram_wrdata_b[1] = \<const0> ;
assign bram_wrdata_b[0] = \<const0> ;
assign ecc_interrupt = \<const0> ;
assign ecc_ue = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_ctrl_arready = \<const0> ;
assign s_axi_ctrl_awready = \<const0> ;
assign s_axi_ctrl_bresp[1] = \<const0> ;
assign s_axi_ctrl_bresp[0] = \<const0> ;
assign s_axi_ctrl_bvalid = \<const0> ;
assign s_axi_ctrl_rdata[31] = \<const0> ;
assign s_axi_ctrl_rdata[30] = \<const0> ;
assign s_axi_ctrl_rdata[29] = \<const0> ;
assign s_axi_ctrl_rdata[28] = \<const0> ;
assign s_axi_ctrl_rdata[27] = \<const0> ;
assign s_axi_ctrl_rdata[26] = \<const0> ;
assign s_axi_ctrl_rdata[25] = \<const0> ;
assign s_axi_ctrl_rdata[24] = \<const0> ;
assign s_axi_ctrl_rdata[23] = \<const0> ;
assign s_axi_ctrl_rdata[22] = \<const0> ;
assign s_axi_ctrl_rdata[21] = \<const0> ;
assign s_axi_ctrl_rdata[20] = \<const0> ;
assign s_axi_ctrl_rdata[19] = \<const0> ;
assign s_axi_ctrl_rdata[18] = \<const0> ;
assign s_axi_ctrl_rdata[17] = \<const0> ;
assign s_axi_ctrl_rdata[16] = \<const0> ;
assign s_axi_ctrl_rdata[15] = \<const0> ;
assign s_axi_ctrl_rdata[14] = \<const0> ;
assign s_axi_ctrl_rdata[13] = \<const0> ;
assign s_axi_ctrl_rdata[12] = \<const0> ;
assign s_axi_ctrl_rdata[11] = \<const0> ;
assign s_axi_ctrl_rdata[10] = \<const0> ;
assign s_axi_ctrl_rdata[9] = \<const0> ;
assign s_axi_ctrl_rdata[8] = \<const0> ;
assign s_axi_ctrl_rdata[7] = \<const0> ;
assign s_axi_ctrl_rdata[6] = \<const0> ;
assign s_axi_ctrl_rdata[5] = \<const0> ;
assign s_axi_ctrl_rdata[4] = \<const0> ;
assign s_axi_ctrl_rdata[3] = \<const0> ;
assign s_axi_ctrl_rdata[2] = \<const0> ;
assign s_axi_ctrl_rdata[1] = \<const0> ;
assign s_axi_ctrl_rdata[0] = \<const0> ;
assign s_axi_ctrl_rresp[1] = \<const0> ;
assign s_axi_ctrl_rresp[0] = \<const0> ;
assign s_axi_ctrl_rvalid = \<const0> ;
assign s_axi_ctrl_wready = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top \gext_inst.abcv4_0_ext_inst
(.bram_addr_a(\^bram_addr_a ),
.bram_addr_b(\^bram_addr_b ),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[12:2]),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[12:2]),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [10:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [10:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [10:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire [10:0]bram_addr_a;
wire [10:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi \GEN_AXI4.I_FULL_AXI
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [10:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [10:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [10:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire I_WR_CHNL_n_36;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [10:0]bram_addr_a;
wire [10:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl I_RD_CHNL
(.\GEN_AWREADY.axi_aresetn_d2_reg (I_WR_CHNL_n_36),
.Q(bram_addr_b[9:0]),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_b(bram_addr_b[10]),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl I_WR_CHNL
(.\GEN_AW_DUAL.aw_active_reg_0 (I_WR_CHNL_n_36),
.SR(bram_rst_a),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_a(bram_addr_a),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
(bram_rst_a,
s_axi_rdata,
s_axi_rlast,
s_axi_rvalid,
bram_en_b,
Q,
s_axi_arready,
bram_addr_b,
s_axi_rid,
s_axi_araddr,
s_axi_aclk,
\GEN_AWREADY.axi_aresetn_d2_reg ,
s_axi_rready,
s_axi_aresetn,
s_axi_arlen,
axi_aresetn_d2,
s_axi_arvalid,
axi_aresetn_re_reg,
s_axi_arid,
s_axi_arburst,
bram_rddata_b);
output bram_rst_a;
output [31:0]s_axi_rdata;
output s_axi_rlast;
output s_axi_rvalid;
output bram_en_b;
output [9:0]Q;
output s_axi_arready;
output [0:0]bram_addr_b;
output [11:0]s_axi_rid;
input [10:0]s_axi_araddr;
input s_axi_aclk;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input s_axi_rready;
input s_axi_aresetn;
input [7:0]s_axi_arlen;
input axi_aresetn_d2;
input s_axi_arvalid;
input axi_aresetn_re_reg;
input [11:0]s_axi_arid;
input [1:0]s_axi_arburst;
input [31:0]bram_rddata_b;
wire \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ;
wire \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ;
wire \/i__n_0 ;
wire \FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ;
wire \GEN_ARREADY.axi_arready_int_i_1_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_2_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_1_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_2_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_4_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_5_n_0 ;
wire \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_full_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[10]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_2_n_0 ;
wire \GEN_RID.axi_rid_temp[1]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[2]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[3]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[4]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[5]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[6]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[7]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[8]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp_full_i_1_n_0 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_5;
wire I_WRAP_BRST_n_6;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [9:0]Q;
wire act_rd_burst;
wire act_rd_burst_i_1_n_0;
wire act_rd_burst_i_3_n_0;
wire act_rd_burst_i_4_n_0;
wire act_rd_burst_set;
wire act_rd_burst_two;
wire act_rd_burst_two_i_1_n_0;
wire ar_active;
wire araddr_pipe_ld43_out;
wire axi_araddr_full;
wire [1:0]axi_arburst_pipe;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [11:0]axi_arid_pipe;
wire [7:0]axi_arlen_pipe;
wire axi_arlen_pipe_1_or_2;
wire axi_arready_int;
wire [1:1]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_arsize_pipe_max_i_1_n_0;
wire axi_b2b_brst;
wire axi_b2b_brst_i_1_n_0;
wire axi_b2b_brst_i_3_n_0;
wire axi_early_arready_int;
wire axi_rd_burst;
wire axi_rd_burst_i_1_n_0;
wire axi_rd_burst_i_2_n_0;
wire axi_rd_burst_i_3_n_0;
wire axi_rd_burst_two;
wire axi_rd_burst_two_i_1_n_0;
wire axi_rd_burst_two_reg_n_0;
wire [11:0]axi_rid_temp;
wire [11:0]axi_rid_temp2;
wire [11:0]axi_rid_temp20_in;
wire axi_rid_temp2_full;
wire axi_rid_temp_full;
wire axi_rid_temp_full_d1;
wire axi_rlast_int_i_1_n_0;
wire axi_rlast_set;
wire axi_rvalid_clr_ok;
wire axi_rvalid_clr_ok_i_1_n_0;
wire axi_rvalid_clr_ok_i_2_n_0;
wire axi_rvalid_clr_ok_i_3_n_0;
wire axi_rvalid_int_i_1_n_0;
wire axi_rvalid_set;
wire axi_rvalid_set_cmb;
wire [0:0]bram_addr_b;
wire bram_addr_ld_en;
wire bram_en_b;
wire bram_en_int_i_10_n_0;
wire bram_en_int_i_11_n_0;
wire bram_en_int_i_1_n_0;
wire bram_en_int_i_2_n_0;
wire bram_en_int_i_3_n_0;
wire bram_en_int_i_4_n_0;
wire bram_en_int_i_6_n_0;
wire bram_en_int_i_7_n_0;
wire bram_en_int_i_9_n_0;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [7:0]brst_cnt;
wire \brst_cnt[0]_i_1_n_0 ;
wire \brst_cnt[1]_i_1_n_0 ;
wire \brst_cnt[2]_i_1_n_0 ;
wire \brst_cnt[3]_i_1_n_0 ;
wire \brst_cnt[4]_i_1_n_0 ;
wire \brst_cnt[4]_i_2_n_0 ;
wire \brst_cnt[5]_i_1_n_0 ;
wire \brst_cnt[6]_i_1_n_0 ;
wire \brst_cnt[6]_i_2_n_0 ;
wire \brst_cnt[7]_i_1_n_0 ;
wire \brst_cnt[7]_i_2_n_0 ;
wire \brst_cnt[7]_i_3_n_0 ;
wire \brst_cnt[7]_i_4_n_0 ;
wire brst_cnt_max;
wire brst_cnt_max_d1;
wire brst_one;
wire brst_one0;
wire brst_one_i_1_n_0;
wire brst_zero;
wire brst_zero_i_1_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire disable_b2b_brst_cmb;
wire disable_b2b_brst_i_2_n_0;
wire disable_b2b_brst_i_3_n_0;
wire disable_b2b_brst_i_4_n_0;
wire end_brst_rd;
wire end_brst_rd_clr;
wire end_brst_rd_clr_i_1_n_0;
wire end_brst_rd_i_1_n_0;
wire last_bram_addr;
wire last_bram_addr0;
wire last_bram_addr_i_10_n_0;
wire last_bram_addr_i_2_n_0;
wire last_bram_addr_i_3_n_0;
wire last_bram_addr_i_4_n_0;
wire last_bram_addr_i_5_n_0;
wire last_bram_addr_i_6_n_0;
wire last_bram_addr_i_7_n_0;
wire last_bram_addr_i_8_n_0;
wire last_bram_addr_i_9_n_0;
wire no_ar_ack;
wire no_ar_ack_i_1_n_0;
wire p_0_in13_in;
wire p_13_out;
wire p_26_out;
wire p_48_out;
wire p_4_out;
wire p_9_out;
wire pend_rd_op;
wire pend_rd_op_i_1_n_0;
wire pend_rd_op_i_2_n_0;
wire pend_rd_op_i_3_n_0;
wire pend_rd_op_i_4_n_0;
wire pend_rd_op_i_5_n_0;
wire pend_rd_op_i_6_n_0;
wire pend_rd_op_i_7_n_0;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire [3:0]rd_data_sm_cs;
wire \rd_data_sm_cs[0]_i_1_n_0 ;
wire \rd_data_sm_cs[0]_i_2_n_0 ;
wire \rd_data_sm_cs[0]_i_3_n_0 ;
wire \rd_data_sm_cs[0]_i_4_n_0 ;
wire \rd_data_sm_cs[1]_i_1_n_0 ;
wire \rd_data_sm_cs[1]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_1_n_0 ;
wire \rd_data_sm_cs[2]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_4_n_0 ;
wire \rd_data_sm_cs[2]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_2_n_0 ;
wire \rd_data_sm_cs[3]_i_3_n_0 ;
wire \rd_data_sm_cs[3]_i_4_n_0 ;
wire \rd_data_sm_cs[3]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_6_n_0 ;
wire \rd_data_sm_cs[3]_i_7_n_0 ;
wire rd_data_sm_ns;
wire [31:0]rd_skid_buf;
wire rd_skid_buf_ld;
wire rd_skid_buf_ld_cmb;
wire rd_skid_buf_ld_reg;
wire rddata_mux_sel;
wire rddata_mux_sel_cmb;
wire rddata_mux_sel_i_1_n_0;
wire rddata_mux_sel_i_3_n_0;
(* RTL_KEEP = "yes" *) wire [2:0]rlast_sm_cs;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
LUT6 #(
.INIT(64'h0011001300130013))
\/FSM_sequential_rlast_sm_cs[0]_i_2
(.I0(axi_rd_burst),
.I1(rlast_sm_cs[1]),
.I2(act_rd_burst_two),
.I3(axi_rd_burst_two_reg_n_0),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h003F007F003F0055))
\/FSM_sequential_rlast_sm_cs[1]_i_2
(.I0(axi_rd_burst),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rlast_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_two),
.O(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF000F111F000E000))
\/i_
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rlast_sm_cs[0]),
.I5(last_bram_addr),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h00008080000F8080))
\/i___0
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[1]),
.I4(rlast_sm_cs[2]),
.I5(s_axi_rlast),
.O(axi_rlast_set));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[0]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[0]),
.O(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[1]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[1]),
.O(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A4FFFF00A40000))
\FSM_sequential_rlast_sm_cs[2]_i_1
(.I0(rlast_sm_cs[1]),
.I1(p_0_in13_in),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[2]),
.I4(\/i__n_0 ),
.I5(rlast_sm_cs[2]),
.O(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\FSM_sequential_rlast_sm_cs[2]_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst),
.O(p_0_in13_in));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ),
.Q(rlast_sm_cs[0]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ),
.Q(rlast_sm_cs[1]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ),
.Q(rlast_sm_cs[2]),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAEEE))
\GEN_ARREADY.axi_arready_int_i_1
(.I0(p_9_out),
.I1(axi_arready_int),
.I2(s_axi_arvalid),
.I3(axi_araddr_full),
.I4(araddr_pipe_ld43_out),
.O(\GEN_ARREADY.axi_arready_int_i_1_n_0 ));
LUT4 #(
.INIT(16'hBAAA))
\GEN_ARREADY.axi_arready_int_i_2
(.I0(axi_aresetn_re_reg),
.I1(axi_early_arready_int),
.I2(axi_araddr_full),
.I3(bram_addr_ld_en),
.O(p_9_out));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_ARREADY.axi_arready_int_i_1_n_0 ),
.Q(axi_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h0000000000000200))
\GEN_ARREADY.axi_early_arready_int_i_1
(.I0(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ),
.I1(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ),
.I2(rd_data_sm_cs[3]),
.I3(brst_one),
.I4(axi_arready_int),
.I5(I_WRAP_BRST_n_23),
.O(p_48_out));
LUT6 #(
.INIT(64'h00CC304400000044))
\GEN_ARREADY.axi_early_arready_int_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h7))
\GEN_ARREADY.axi_early_arready_int_i_3
(.I0(axi_araddr_full),
.I1(s_axi_arvalid),
.O(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_early_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_48_out),
.Q(axi_early_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCDCDCDDDCCCCCCCC))
\GEN_AR_DUAL.ar_active_i_1
(.I0(\GEN_AR_DUAL.ar_active_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(\GEN_AR_DUAL.ar_active_i_3_n_0 ),
.I3(end_brst_rd),
.I4(brst_zero),
.I5(ar_active),
.O(\GEN_AR_DUAL.ar_active_i_1_n_0 ));
LUT6 #(
.INIT(64'h808880808088A280))
\GEN_AR_DUAL.ar_active_i_2
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(rd_data_sm_cs[1]),
.I2(\GEN_AR_DUAL.ar_active_i_5_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(axi_rd_burst),
.O(\GEN_AR_DUAL.ar_active_i_2_n_0 ));
LUT6 #(
.INIT(64'h0010000000000000))
\GEN_AR_DUAL.ar_active_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\GEN_AR_DUAL.ar_active_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h1))
\GEN_AR_DUAL.ar_active_i_4
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.O(\GEN_AR_DUAL.ar_active_i_4_n_0 ));
LUT6 #(
.INIT(64'h8A88000000000000))
\GEN_AR_DUAL.ar_active_i_5
(.I0(I_WRAP_BRST_n_24),
.I1(brst_zero),
.I2(axi_b2b_brst),
.I3(end_brst_rd),
.I4(rd_adv_buf67_out),
.I5(rd_data_sm_cs[0]),
.O(\GEN_AR_DUAL.ar_active_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_DUAL.ar_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.ar_active_i_1_n_0 ),
.Q(ar_active),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
LUT6 #(
.INIT(64'h10001000F0F01000))
\GEN_AR_DUAL.rd_addr_sm_cs_i_1
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I4(last_bram_addr),
.I5(I_WRAP_BRST_n_23),
.O(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ));
FDRE \GEN_AR_DUAL.rd_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ),
.Q(rd_addr_sm_cs),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[8]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[9]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[10]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[0]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[1]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[2]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[3]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[4]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[5]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[6]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[7]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.R(1'b0));
LUT6 #(
.INIT(64'h00C08888CCCC8888))
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1
(.I0(araddr_pipe_ld43_out),
.I1(s_axi_aresetn),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I4(axi_araddr_full),
.I5(bram_addr_ld_en),
.O(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ),
.Q(axi_araddr_full),
.R(1'b0));
LUT4 #(
.INIT(16'h03AA))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.I1(s_axi_arburst[0]),
.I2(s_axi_arburst[1]),
.I3(araddr_pipe_ld43_out),
.O(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[0]),
.Q(axi_arburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[1]),
.Q(axi_arburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[0]),
.Q(axi_arid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[10]),
.Q(axi_arid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[11]),
.Q(axi_arid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[1]),
.Q(axi_arid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[2]),
.Q(axi_arid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[3]),
.Q(axi_arid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[4]),
.Q(axi_arid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[5]),
.Q(axi_arid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[6]),
.Q(axi_arid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[7]),
.Q(axi_arid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[8]),
.Q(axi_arid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[9]),
.Q(axi_arid_pipe[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h220022002A002200))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1
(.I0(axi_aresetn_d2),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I2(rd_addr_sm_cs),
.I3(s_axi_arvalid),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I5(axi_araddr_full),
.O(araddr_pipe_ld43_out));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'hB))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2
(.I0(I_WRAP_BRST_n_23),
.I1(last_bram_addr),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3
(.I0(no_ar_ack),
.I1(pend_rd_op),
.I2(ar_active),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1
(.I0(s_axi_arlen[7]),
.I1(s_axi_arlen[1]),
.I2(s_axi_arlen[3]),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ),
.O(p_13_out));
LUT4 #(
.INIT(16'hFFFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2
(.I0(s_axi_arlen[5]),
.I1(s_axi_arlen[4]),
.I2(s_axi_arlen[2]),
.I3(s_axi_arlen[6]),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(p_13_out),
.Q(axi_arlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[0]),
.Q(axi_arlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[1]),
.Q(axi_arlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[2]),
.Q(axi_arlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[3]),
.Q(axi_arlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[4]),
.Q(axi_arlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[5]),
.Q(axi_arlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[6]),
.Q(axi_arlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[7]),
.Q(axi_arlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(1'b1),
.Q(axi_arsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000BAAA0000))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1
(.I0(brst_cnt_max),
.I1(pend_rd_op),
.I2(ar_active),
.I3(brst_zero),
.I4(s_axi_aresetn),
.I5(bram_addr_ld_en),
.O(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ),
.Q(brst_cnt_max),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(Q[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(I_WRAP_BRST_n_20),
.I3(Q[5]),
.I4(Q[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hE2))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(I_WRAP_BRST_n_21),
.I1(I_WRAP_BRST_n_7),
.I2(bram_addr_b),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_10),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_9),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ),
.Q(bram_addr_b),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_18),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_17),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_16),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_15),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_14),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_13),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_12),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_11),
.Q(Q[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1
(.I0(rd_skid_buf[0]),
.I1(bram_rddata_b[0]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ),
.Q(s_axi_rdata[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1
(.I0(rd_skid_buf[10]),
.I1(bram_rddata_b[10]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ),
.Q(s_axi_rdata[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1
(.I0(rd_skid_buf[11]),
.I1(bram_rddata_b[11]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ),
.Q(s_axi_rdata[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1
(.I0(rd_skid_buf[12]),
.I1(bram_rddata_b[12]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ),
.Q(s_axi_rdata[12]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1
(.I0(rd_skid_buf[13]),
.I1(bram_rddata_b[13]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ),
.Q(s_axi_rdata[13]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1
(.I0(rd_skid_buf[14]),
.I1(bram_rddata_b[14]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ),
.Q(s_axi_rdata[14]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1
(.I0(rd_skid_buf[15]),
.I1(bram_rddata_b[15]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ),
.Q(s_axi_rdata[15]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1
(.I0(rd_skid_buf[16]),
.I1(bram_rddata_b[16]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ),
.Q(s_axi_rdata[16]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1
(.I0(rd_skid_buf[17]),
.I1(bram_rddata_b[17]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ),
.Q(s_axi_rdata[17]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1
(.I0(rd_skid_buf[18]),
.I1(bram_rddata_b[18]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ),
.Q(s_axi_rdata[18]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1
(.I0(rd_skid_buf[19]),
.I1(bram_rddata_b[19]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ),
.Q(s_axi_rdata[19]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1
(.I0(rd_skid_buf[1]),
.I1(bram_rddata_b[1]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ),
.Q(s_axi_rdata[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1
(.I0(rd_skid_buf[20]),
.I1(bram_rddata_b[20]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ),
.Q(s_axi_rdata[20]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1
(.I0(rd_skid_buf[21]),
.I1(bram_rddata_b[21]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ),
.Q(s_axi_rdata[21]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1
(.I0(rd_skid_buf[22]),
.I1(bram_rddata_b[22]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ),
.Q(s_axi_rdata[22]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1
(.I0(rd_skid_buf[23]),
.I1(bram_rddata_b[23]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ),
.Q(s_axi_rdata[23]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1
(.I0(rd_skid_buf[24]),
.I1(bram_rddata_b[24]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ),
.Q(s_axi_rdata[24]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1
(.I0(rd_skid_buf[25]),
.I1(bram_rddata_b[25]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ),
.Q(s_axi_rdata[25]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1
(.I0(rd_skid_buf[26]),
.I1(bram_rddata_b[26]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ),
.Q(s_axi_rdata[26]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1
(.I0(rd_skid_buf[27]),
.I1(bram_rddata_b[27]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ),
.Q(s_axi_rdata[27]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1
(.I0(rd_skid_buf[28]),
.I1(bram_rddata_b[28]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ),
.Q(s_axi_rdata[28]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1
(.I0(rd_skid_buf[29]),
.I1(bram_rddata_b[29]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ),
.Q(s_axi_rdata[29]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1
(.I0(rd_skid_buf[2]),
.I1(bram_rddata_b[2]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ),
.Q(s_axi_rdata[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1
(.I0(rd_skid_buf[30]),
.I1(bram_rddata_b[30]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ),
.Q(s_axi_rdata[30]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1414545410000404))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2
(.I0(rd_skid_buf[31]),
.I1(bram_rddata_b[31]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h1))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.Q(s_axi_rdata[31]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1
(.I0(rd_skid_buf[3]),
.I1(bram_rddata_b[3]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ),
.Q(s_axi_rdata[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1
(.I0(rd_skid_buf[4]),
.I1(bram_rddata_b[4]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ),
.Q(s_axi_rdata[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1
(.I0(rd_skid_buf[5]),
.I1(bram_rddata_b[5]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ),
.Q(s_axi_rdata[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1
(.I0(rd_skid_buf[6]),
.I1(bram_rddata_b[6]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ),
.Q(s_axi_rdata[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1
(.I0(rd_skid_buf[7]),
.I1(bram_rddata_b[7]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ),
.Q(s_axi_rdata[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1
(.I0(rd_skid_buf[8]),
.I1(bram_rddata_b[8]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ),
.Q(s_axi_rdata[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1
(.I0(rd_skid_buf[9]),
.I1(bram_rddata_b[9]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ),
.Q(s_axi_rdata[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAEAA))
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1
(.I0(rd_skid_buf_ld_reg),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[3]),
.O(rd_skid_buf_ld));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[0]),
.Q(rd_skid_buf[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[10]),
.Q(rd_skid_buf[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[11]),
.Q(rd_skid_buf[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[12]),
.Q(rd_skid_buf[12]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[13]),
.Q(rd_skid_buf[13]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[14]),
.Q(rd_skid_buf[14]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[15]),
.Q(rd_skid_buf[15]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[16]),
.Q(rd_skid_buf[16]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[17]),
.Q(rd_skid_buf[17]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[18]),
.Q(rd_skid_buf[18]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[19]),
.Q(rd_skid_buf[19]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[1]),
.Q(rd_skid_buf[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[20]),
.Q(rd_skid_buf[20]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[21]),
.Q(rd_skid_buf[21]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[22]),
.Q(rd_skid_buf[22]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[23]),
.Q(rd_skid_buf[23]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[24]),
.Q(rd_skid_buf[24]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[25]),
.Q(rd_skid_buf[25]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[26]),
.Q(rd_skid_buf[26]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[27]),
.Q(rd_skid_buf[27]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[28]),
.Q(rd_skid_buf[28]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[29]),
.Q(rd_skid_buf[29]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[2]),
.Q(rd_skid_buf[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[30]),
.Q(rd_skid_buf[30]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[31]),
.Q(rd_skid_buf[31]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[3]),
.Q(rd_skid_buf[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[4]),
.Q(rd_skid_buf[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[5]),
.Q(rd_skid_buf[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[6]),
.Q(rd_skid_buf[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[7]),
.Q(rd_skid_buf[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[8]),
.Q(rd_skid_buf[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[9]),
.Q(rd_skid_buf[9]),
.R(bram_rst_a));
LUT4 #(
.INIT(16'h08FF))
\GEN_RID.axi_rid_int[11]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.I2(axi_b2b_brst),
.I3(s_axi_aresetn),
.O(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEAAA))
\GEN_RID.axi_rid_int[11]_i_2
(.I0(axi_rvalid_set),
.I1(s_axi_rready),
.I2(s_axi_rlast),
.I3(axi_b2b_brst),
.O(p_4_out));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[0]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[0]),
.Q(s_axi_rid[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[10]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[10]),
.Q(s_axi_rid[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[11]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[11]),
.Q(s_axi_rid[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[1]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[1]),
.Q(s_axi_rid[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[2]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[2]),
.Q(s_axi_rid[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[3]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[3]),
.Q(s_axi_rid[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[4]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[4]),
.Q(s_axi_rid[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[5]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[5]),
.Q(s_axi_rid[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[6]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[6]),
.Q(s_axi_rid[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[7]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[7]),
.Q(s_axi_rid[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[8]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[8]),
.Q(s_axi_rid[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[9]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[9]),
.Q(s_axi_rid[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.O(axi_rid_temp20_in[0]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.O(axi_rid_temp20_in[10]));
LUT2 #(
.INIT(4'h8))
\GEN_RID.axi_rid_temp2[11]_i_1
(.I0(axi_rid_temp_full),
.I1(bram_addr_ld_en),
.O(p_26_out));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.O(axi_rid_temp20_in[11]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.O(axi_rid_temp20_in[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.O(axi_rid_temp20_in[2]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.O(axi_rid_temp20_in[3]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.O(axi_rid_temp20_in[4]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.O(axi_rid_temp20_in[5]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.O(axi_rid_temp20_in[6]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.O(axi_rid_temp20_in[7]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.O(axi_rid_temp20_in[8]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.O(axi_rid_temp20_in[9]));
LUT6 #(
.INIT(64'h08080000C8C800C0))
\GEN_RID.axi_rid_temp2_full_i_1
(.I0(bram_addr_ld_en),
.I1(s_axi_aresetn),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full_d1),
.I4(axi_rid_temp_full),
.I5(p_4_out),
.O(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ),
.Q(axi_rid_temp2_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[0]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[0]),
.Q(axi_rid_temp2[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[10]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[10]),
.Q(axi_rid_temp2[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[11]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[11]),
.Q(axi_rid_temp2[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[1]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[1]),
.Q(axi_rid_temp2[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[2]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[2]),
.Q(axi_rid_temp2[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[3]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[3]),
.Q(axi_rid_temp2[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[4]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[4]),
.Q(axi_rid_temp2[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[5]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[5]),
.Q(axi_rid_temp2[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[6]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[6]),
.Q(axi_rid_temp2[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[7]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[7]),
.Q(axi_rid_temp2[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[8]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[8]),
.Q(axi_rid_temp2[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[9]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[9]),
.Q(axi_rid_temp2[9]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[0]),
.O(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[10]),
.O(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hA0FFA0E0))
\GEN_RID.axi_rid_temp[11]_i_1
(.I0(p_4_out),
.I1(axi_rid_temp_full_d1),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.O(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[11]),
.O(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[1]),
.O(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[2]),
.O(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[3]),
.O(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[4]),
.O(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[5]),
.O(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[6]),
.O(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[7]),
.O(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[8]),
.O(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[9]),
.O(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rid_temp_full),
.Q(axi_rid_temp_full_d1),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0F0F0E000F0A0A0))
\GEN_RID.axi_rid_temp_full_i_1
(.I0(bram_addr_ld_en),
.I1(axi_rid_temp_full_d1),
.I2(s_axi_aresetn),
.I3(p_4_out),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2_full),
.O(\GEN_RID.axi_rid_temp_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp_full_i_1_n_0 ),
.Q(axi_rid_temp_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ),
.Q(axi_rid_temp[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ),
.Q(axi_rid_temp[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ),
.Q(axi_rid_temp[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ),
.Q(axi_rid_temp[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ),
.Q(axi_rid_temp[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ),
.Q(axi_rid_temp[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ),
.Q(axi_rid_temp[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ),
.Q(axi_rid_temp[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ),
.Q(axi_rid_temp[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ),
.Q(axi_rid_temp[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ),
.Q(axi_rid_temp[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ),
.Q(axi_rid_temp[9]),
.R(bram_rst_a));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 I_WRAP_BRST
(.D({I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16,I_WRAP_BRST_n_17,I_WRAP_BRST_n_18}),
.E(I_WRAP_BRST_n_6),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg (\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] (axi_arlen_pipe[3:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_0),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 (I_WRAP_BRST_n_7),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 (I_WRAP_BRST_n_8),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 (Q),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (I_WRAP_BRST_n_20),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ),
.Q(rd_data_sm_cs),
.SR(bram_rst_a),
.ar_active(ar_active),
.axi_araddr_full(axi_araddr_full),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_arlen_pipe_1_or_2(axi_arlen_pipe_1_or_2),
.axi_arsize_pipe(axi_arsize_pipe),
.axi_arsize_pipe_max(axi_arsize_pipe_max),
.axi_b2b_brst(axi_b2b_brst),
.axi_b2b_brst_reg(I_WRAP_BRST_n_24),
.axi_rd_burst(axi_rd_burst),
.axi_rd_burst_two_reg(axi_rd_burst_two_reg_n_0),
.axi_rvalid_int_reg(s_axi_rvalid),
.bram_addr_ld_en(bram_addr_ld_en),
.brst_zero(brst_zero),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.disable_b2b_brst(disable_b2b_brst),
.end_brst_rd(end_brst_rd),
.last_bram_addr(last_bram_addr),
.no_ar_ack(no_ar_ack),
.pend_rd_op(pend_rd_op),
.rd_addr_sm_cs(rd_addr_sm_cs),
.rd_adv_buf67_out(rd_adv_buf67_out),
.\rd_data_sm_cs_reg[1] (I_WRAP_BRST_n_22),
.\rd_data_sm_cs_reg[3] (I_WRAP_BRST_n_25),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arlen(s_axi_arlen[3:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.\save_init_bram_addr_ld_reg[12]_0 (I_WRAP_BRST_n_21),
.\save_init_bram_addr_ld_reg[12]_1 (I_WRAP_BRST_n_23),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_2),
.\wrap_burst_total_reg[0]_1 (I_WRAP_BRST_n_3),
.\wrap_burst_total_reg[0]_2 (I_WRAP_BRST_n_4),
.\wrap_burst_total_reg[0]_3 (I_WRAP_BRST_n_5));
LUT6 #(
.INIT(64'h000000002EEE22E2))
act_rd_burst_i_1
(.I0(act_rd_burst),
.I1(act_rd_burst_set),
.I2(bram_addr_ld_en),
.I3(axi_rd_burst_two),
.I4(axi_rd_burst),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'hA8A8AAA8A8A8A8A8))
act_rd_burst_i_2
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(act_rd_burst_i_4_n_0),
.I2(axi_b2b_brst_i_3_n_0),
.I3(\rd_data_sm_cs[2]_i_4_n_0 ),
.I4(last_bram_addr_i_8_n_0),
.I5(bram_addr_ld_en),
.O(act_rd_burst_set));
LUT6 #(
.INIT(64'h02000004FFFFFFFF))
act_rd_burst_i_3
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(\rd_data_sm_cs[3]_i_6_n_0 ),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(s_axi_aresetn),
.O(act_rd_burst_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h4440))
act_rd_burst_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.O(act_rd_burst_i_4_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_i_1_n_0),
.Q(act_rd_burst),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000E2EEE222))
act_rd_burst_two_i_1
(.I0(act_rd_burst_two),
.I1(act_rd_burst_set),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_two_i_1_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_two_i_1_n_0),
.Q(act_rd_burst_two),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
axi_arsize_pipe_max_i_1
(.I0(araddr_pipe_ld43_out),
.I1(axi_arsize_pipe_max),
.O(axi_arsize_pipe_max_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_arsize_pipe_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_arsize_pipe_max_i_1_n_0),
.Q(axi_arsize_pipe_max),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCC0CCC55CC0CCCCC))
axi_b2b_brst_i_1
(.I0(I_WRAP_BRST_n_24),
.I1(axi_b2b_brst),
.I2(disable_b2b_brst_i_2_n_0),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(axi_b2b_brst_i_3_n_0),
.O(axi_b2b_brst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000088880080))
axi_b2b_brst_i_3
(.I0(\rd_data_sm_cs[0]_i_3_n_0 ),
.I1(rd_adv_buf67_out),
.I2(end_brst_rd),
.I3(axi_b2b_brst),
.I4(brst_zero),
.I5(I_WRAP_BRST_n_24),
.O(axi_b2b_brst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_b2b_brst_i_1_n_0),
.Q(axi_b2b_brst),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h303000A0))
axi_rd_burst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000004))
axi_rd_burst_i_2
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(axi_rd_burst_i_3_n_0),
.I2(I_WRAP_BRST_n_4),
.I3(\brst_cnt[7]_i_3_n_0 ),
.I4(I_WRAP_BRST_n_3),
.I5(I_WRAP_BRST_n_2),
.O(axi_rd_burst_i_2_n_0));
LUT5 #(
.INIT(32'h00053305))
axi_rd_burst_i_3
(.I0(s_axi_arlen[5]),
.I1(axi_arlen_pipe[5]),
.I2(s_axi_arlen[4]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[4]),
.O(axi_rd_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_i_1_n_0),
.Q(axi_rd_burst),
.R(1'b0));
LUT5 #(
.INIT(32'hC0C000A0))
axi_rd_burst_two_i_1
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst_two),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_two_i_1_n_0));
LUT4 #(
.INIT(16'hA808))
axi_rd_burst_two_i_2
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(axi_rd_burst_two));
FDRE #(
.INIT(1'b0))
axi_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_two_i_1_n_0),
.Q(axi_rd_burst_two_reg_n_0),
.R(1'b0));
LUT4 #(
.INIT(16'h88A8))
axi_rlast_int_i_1
(.I0(s_axi_aresetn),
.I1(axi_rlast_set),
.I2(s_axi_rlast),
.I3(s_axi_rready),
.O(axi_rlast_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rlast_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rlast_int_i_1_n_0),
.Q(s_axi_rlast),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFFEEEA))
axi_rvalid_clr_ok_i_1
(.I0(axi_rvalid_clr_ok),
.I1(last_bram_addr),
.I2(disable_b2b_brst),
.I3(disable_b2b_brst_cmb),
.I4(axi_rvalid_clr_ok_i_2_n_0),
.I5(axi_rvalid_clr_ok_i_3_n_0),
.O(axi_rvalid_clr_ok_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hAAAABAAA))
axi_rvalid_clr_ok_i_2
(.I0(bram_addr_ld_en),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(axi_rvalid_clr_ok_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'h4F))
axi_rvalid_clr_ok_i_3
(.I0(I_WRAP_BRST_n_23),
.I1(bram_addr_ld_en),
.I2(s_axi_aresetn),
.O(axi_rvalid_clr_ok_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_clr_ok_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_clr_ok_i_1_n_0),
.Q(axi_rvalid_clr_ok),
.R(1'b0));
LUT6 #(
.INIT(64'h00E0E0E0E0E0E0E0))
axi_rvalid_int_i_1
(.I0(s_axi_rvalid),
.I1(axi_rvalid_set),
.I2(s_axi_aresetn),
.I3(axi_rvalid_clr_ok),
.I4(s_axi_rlast),
.I5(s_axi_rready),
.O(axi_rvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_int_i_1_n_0),
.Q(s_axi_rvalid),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0100))
axi_rvalid_set_i_1
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.O(axi_rvalid_set_cmb));
FDRE #(
.INIT(1'b0))
axi_rvalid_set_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_set_cmb),
.Q(axi_rvalid_set),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hEEEEFFFEEEEE000E))
bram_en_int_i_1
(.I0(bram_en_int_i_2_n_0),
.I1(bram_en_int_i_3_n_0),
.I2(bram_en_int_i_4_n_0),
.I3(I_WRAP_BRST_n_25),
.I4(bram_en_int_i_6_n_0),
.I5(bram_en_b),
.O(bram_en_int_i_1_n_0));
LUT6 #(
.INIT(64'hFFFF777FFFFFFFFF))
bram_en_int_i_10
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(act_rd_burst),
.I3(act_rd_burst_two),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_10_n_0));
LUT6 #(
.INIT(64'hD0D000F0D0D0F0F0))
bram_en_int_i_11
(.I0(\rd_data_sm_cs[3]_i_7_n_0 ),
.I1(I_WRAP_BRST_n_24),
.I2(rd_data_sm_cs[1]),
.I3(brst_one),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(bram_en_int_i_11_n_0));
LUT6 #(
.INIT(64'h00000000FDF50000))
bram_en_int_i_2
(.I0(rd_data_sm_cs[2]),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[1]),
.I5(bram_en_int_i_7_n_0),
.O(bram_en_int_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAEEAFAAAAAAEE))
bram_en_int_i_3
(.I0(I_WRAP_BRST_n_0),
.I1(bram_addr_ld_en),
.I2(p_0_in13_in),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_3_n_0));
LUT6 #(
.INIT(64'h000F007F0000007F))
bram_en_int_i_4
(.I0(pend_rd_op),
.I1(rd_adv_buf67_out),
.I2(\rd_data_sm_cs[0]_i_3_n_0 ),
.I3(bram_en_int_i_9_n_0),
.I4(bram_addr_ld_en),
.I5(bram_en_int_i_10_n_0),
.O(bram_en_int_i_4_n_0));
LUT6 #(
.INIT(64'h1010111111111110))
bram_en_int_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(bram_en_int_i_11_n_0),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_6_n_0));
LUT6 #(
.INIT(64'h3330131003001310))
bram_en_int_i_7
(.I0(\rd_data_sm_cs[2]_i_5_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.I3(axi_rd_burst_two_reg_n_0),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_7_n_0 ),
.O(bram_en_int_i_7_n_0));
LUT6 #(
.INIT(64'h1111111111111000))
bram_en_int_i_9
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(brst_zero),
.I5(end_brst_rd),
.O(bram_en_int_i_9_n_0));
FDRE #(
.INIT(1'b0))
bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_int_i_1_n_0),
.Q(bram_en_b),
.R(bram_rst_a));
LUT5 #(
.INIT(32'hD1DDD111))
\brst_cnt[0]_i_1
(.I0(brst_cnt[0]),
.I1(bram_addr_ld_en),
.I2(axi_arlen_pipe[0]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[0]),
.O(\brst_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[1]_i_1
(.I0(axi_arlen_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8B88B))
\brst_cnt[2]_i_1
(.I0(I_WRAP_BRST_n_2),
.I1(bram_addr_ld_en),
.I2(brst_cnt[2]),
.I3(brst_cnt[1]),
.I4(brst_cnt[0]),
.O(\brst_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B8B88B))
\brst_cnt[3]_i_1
(.I0(I_WRAP_BRST_n_3),
.I1(bram_addr_ld_en),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[4]_i_1
(.I0(axi_arlen_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[4]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[4]),
.I5(\brst_cnt[4]_i_2_n_0 ),
.O(\brst_cnt[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
\brst_cnt[4]_i_2
(.I0(brst_cnt[2]),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.I3(brst_cnt[3]),
.O(\brst_cnt[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[5]_i_1
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hB88BB8B8))
\brst_cnt[6]_i_1
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[6]),
.I3(brst_cnt[5]),
.I4(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[6]_i_2
(.I0(axi_arlen_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[6]),
.O(\brst_cnt[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\brst_cnt[7]_i_1
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_8),
.O(\brst_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B88BB8B8B8B8))
\brst_cnt[7]_i_2
(.I0(\brst_cnt[7]_i_3_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[7]),
.I3(brst_cnt[6]),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[7]_i_3
(.I0(axi_arlen_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[7]),
.O(\brst_cnt[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000001))
\brst_cnt[7]_i_4
(.I0(brst_cnt[3]),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.O(\brst_cnt[7]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
brst_cnt_max_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_cnt_max),
.Q(brst_cnt_max_d1),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[0]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[0]_i_1_n_0 ),
.Q(brst_cnt[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[1]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[1]_i_1_n_0 ),
.Q(brst_cnt[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[2]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[2]_i_1_n_0 ),
.Q(brst_cnt[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[3]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[3]_i_1_n_0 ),
.Q(brst_cnt[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[4]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[4]_i_1_n_0 ),
.Q(brst_cnt[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[5]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[5]_i_1_n_0 ),
.Q(brst_cnt[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[6]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[6]_i_1_n_0 ),
.Q(brst_cnt[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[7]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[7]_i_2_n_0 ),
.Q(brst_cnt[7]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h00000000E0EE0000))
brst_one_i_1
(.I0(brst_one),
.I1(brst_one0),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(s_axi_aresetn),
.I5(last_bram_addr_i_7_n_0),
.O(brst_one_i_1_n_0));
LUT6 #(
.INIT(64'h80FF808080808080))
brst_one_i_2
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_5),
.I2(axi_rd_burst_i_2_n_0),
.I3(brst_cnt[0]),
.I4(brst_cnt[1]),
.I5(last_bram_addr_i_9_n_0),
.O(brst_one0));
FDRE #(
.INIT(1'b0))
brst_one_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_one_i_1_n_0),
.Q(brst_one),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h00E0))
brst_zero_i_1
(.I0(brst_zero),
.I1(last_bram_addr_i_7_n_0),
.I2(s_axi_aresetn),
.I3(last_bram_addr_i_3_n_0),
.O(brst_zero_i_1_n_0));
FDRE #(
.INIT(1'b0))
brst_zero_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_zero_i_1_n_0),
.Q(brst_zero),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_1
(.I0(s_axi_arburst[0]),
.I1(axi_arburst_pipe[0]),
.I2(s_axi_arburst[1]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[1]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_fixed_burst),
.Q(curr_fixed_burst_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_1
(.I0(s_axi_arburst[1]),
.I1(axi_arburst_pipe[1]),
.I2(s_axi_arburst[0]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_wrap_burst),
.Q(curr_wrap_burst_reg),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF000D0000))
disable_b2b_brst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst_i_2_n_0),
.I5(disable_b2b_brst_i_3_n_0),
.O(disable_b2b_brst_cmb));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h2))
disable_b2b_brst_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.O(disable_b2b_brst_i_2_n_0));
LUT6 #(
.INIT(64'hFE7D0000FE7DFE7D))
disable_b2b_brst_i_3
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst),
.I5(disable_b2b_brst_i_4_n_0),
.O(disable_b2b_brst_i_3_n_0));
LUT6 #(
.INIT(64'hDFDFDFDFDFDFDFFF))
disable_b2b_brst_i_4
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(brst_zero),
.I4(end_brst_rd),
.I5(brst_one),
.O(disable_b2b_brst_i_4_n_0));
FDRE #(
.INIT(1'b0))
disable_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(disable_b2b_brst_cmb),
.Q(disable_b2b_brst),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFEFEFEFF10100000))
end_brst_rd_clr_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[0]),
.I5(end_brst_rd_clr),
.O(end_brst_rd_clr_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_clr_i_1_n_0),
.Q(end_brst_rd_clr),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h0020F020))
end_brst_rd_i_1
(.I0(brst_cnt_max),
.I1(brst_cnt_max_d1),
.I2(s_axi_aresetn),
.I3(end_brst_rd),
.I4(end_brst_rd_clr),
.O(end_brst_rd_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_i_1_n_0),
.Q(end_brst_rd),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF57550000))
last_bram_addr_i_1
(.I0(last_bram_addr_i_2_n_0),
.I1(last_bram_addr_i_3_n_0),
.I2(last_bram_addr_i_4_n_0),
.I3(last_bram_addr_i_5_n_0),
.I4(last_bram_addr_i_6_n_0),
.I5(last_bram_addr_i_7_n_0),
.O(last_bram_addr0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'hE))
last_bram_addr_i_10
(.I0(brst_cnt[6]),
.I1(brst_cnt[5]),
.O(last_bram_addr_i_10_n_0));
LUT6 #(
.INIT(64'hAABFFFBFFFBFFFBF))
last_bram_addr_i_2
(.I0(rd_data_sm_cs[2]),
.I1(last_bram_addr_i_8_n_0),
.I2(bram_addr_ld_en),
.I3(rd_data_sm_cs[3]),
.I4(rd_adv_buf67_out),
.I5(p_0_in13_in),
.O(last_bram_addr_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h8A80AAAA))
last_bram_addr_i_3
(.I0(bram_addr_ld_en),
.I1(axi_arlen_pipe[0]),
.I2(axi_araddr_full),
.I3(s_axi_arlen[0]),
.I4(axi_rd_burst_i_2_n_0),
.O(last_bram_addr_i_3_n_0));
LUT6 #(
.INIT(64'hDDDDDDDDFFFDFFFF))
last_bram_addr_i_4
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(last_bram_addr_i_4_n_0));
LUT4 #(
.INIT(16'h8880))
last_bram_addr_i_5
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(bram_addr_ld_en),
.I3(pend_rd_op),
.O(last_bram_addr_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h81))
last_bram_addr_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.O(last_bram_addr_i_6_n_0));
LUT3 #(
.INIT(8'h08))
last_bram_addr_i_7
(.I0(last_bram_addr_i_9_n_0),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.O(last_bram_addr_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h02A2))
last_bram_addr_i_8
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(last_bram_addr_i_8_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
last_bram_addr_i_9
(.I0(I_WRAP_BRST_n_8),
.I1(last_bram_addr_i_10_n_0),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.I5(brst_cnt[7]),
.O(last_bram_addr_i_9_n_0));
FDRE #(
.INIT(1'b0))
last_bram_addr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(last_bram_addr0),
.Q(last_bram_addr),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAAAAA88C8AAAA))
no_ar_ack_i_1
(.I0(no_ar_ack),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[0]),
.I5(I_WRAP_BRST_n_25),
.O(no_ar_ack_i_1_n_0));
FDRE #(
.INIT(1'b0))
no_ar_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(no_ar_ack_i_1_n_0),
.Q(no_ar_ack),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAFFFEAAAA0002))
pend_rd_op_i_1
(.I0(pend_rd_op_i_2_n_0),
.I1(pend_rd_op_i_3_n_0),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.I4(pend_rd_op_i_4_n_0),
.I5(pend_rd_op),
.O(pend_rd_op_i_1_n_0));
LUT6 #(
.INIT(64'h0FFCC8C80CCCC8C8))
pend_rd_op_i_2
(.I0(p_0_in13_in),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(pend_rd_op_i_5_n_0),
.O(pend_rd_op_i_2_n_0));
LUT6 #(
.INIT(64'h0303070733F3FFFF))
pend_rd_op_i_3
(.I0(p_0_in13_in),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(s_axi_rlast),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(pend_rd_op_i_3_n_0));
LUT6 #(
.INIT(64'h00000000BBBABB00))
pend_rd_op_i_4
(.I0(pend_rd_op_i_6_n_0),
.I1(rd_data_sm_cs[0]),
.I2(pend_rd_op_i_5_n_0),
.I3(bram_addr_ld_en),
.I4(pend_rd_op_i_7_n_0),
.I5(I_WRAP_BRST_n_25),
.O(pend_rd_op_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_5
(.I0(ar_active),
.I1(end_brst_rd),
.O(pend_rd_op_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h8000FFFF))
pend_rd_op_i_6
(.I0(pend_rd_op),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(pend_rd_op_i_6_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFF0008888))
pend_rd_op_i_7
(.I0(pend_rd_op),
.I1(s_axi_rlast),
.I2(ar_active),
.I3(end_brst_rd),
.I4(rd_data_sm_cs[0]),
.I5(rd_data_sm_cs[1]),
.O(pend_rd_op_i_7_n_0));
FDRE #(
.INIT(1'b0))
pend_rd_op_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(pend_rd_op_i_1_n_0),
.Q(pend_rd_op),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF54005555))
\rd_data_sm_cs[0]_i_1
(.I0(\rd_data_sm_cs[0]_i_2_n_0 ),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[0]_i_3_n_0 ),
.I5(\rd_data_sm_cs[0]_i_4_n_0 ),
.O(\rd_data_sm_cs[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEAAAAAAFEAAFEAA))
\rd_data_sm_cs[0]_i_2
(.I0(I_WRAP_BRST_n_25),
.I1(act_rd_burst_two),
.I2(act_rd_burst),
.I3(disable_b2b_brst_i_2_n_0),
.I4(bram_addr_ld_en),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h8))
\rd_data_sm_cs[0]_i_3
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000300BF0003008F))
\rd_data_sm_cs[0]_i_4
(.I0(rd_adv_buf67_out),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(p_0_in13_in),
.O(\rd_data_sm_cs[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\rd_data_sm_cs[1]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(I_WRAP_BRST_n_25),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(I_WRAP_BRST_n_22),
.I5(\rd_data_sm_cs[1]_i_3_n_0 ),
.O(\rd_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hC0CCCCCC88888888))
\rd_data_sm_cs[1]_i_3
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(I_WRAP_BRST_n_24),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAABAAABAEAFAAAB))
\rd_data_sm_cs[2]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[3]),
.I3(\rd_data_sm_cs[2]_i_3_n_0 ),
.I4(\rd_data_sm_cs[2]_i_4_n_0 ),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(\rd_data_sm_cs[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000000DF00000))
\rd_data_sm_cs[2]_i_2
(.I0(bram_addr_ld_en),
.I1(\rd_data_sm_cs[3]_i_6_n_0 ),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(rd_data_sm_cs[3]),
.O(\rd_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00C0FFFF33F3BBBB))
\rd_data_sm_cs[2]_i_3
(.I0(axi_rd_burst),
.I1(rd_data_sm_cs[0]),
.I2(rd_adv_buf67_out),
.I3(I_WRAP_BRST_n_24),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(\rd_data_sm_cs[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_5
(.I0(brst_zero),
.I1(end_brst_rd),
.O(\rd_data_sm_cs[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFCCCBBBB3000B888))
\rd_data_sm_cs[3]_i_1
(.I0(\rd_data_sm_cs[3]_i_3_n_0 ),
.I1(\rd_data_sm_cs[3]_i_4_n_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(\rd_data_sm_cs[3]_i_5_n_0 ),
.I5(bram_addr_ld_en),
.O(rd_data_sm_ns));
LUT6 #(
.INIT(64'h0000004050005040))
\rd_data_sm_cs[3]_i_2
(.I0(I_WRAP_BRST_n_25),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(\rd_data_sm_cs[3]_i_6_n_0 ),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF5EFFFF))
\rd_data_sm_cs[3]_i_3
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[3]),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_7_n_0 ),
.O(\rd_data_sm_cs[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hBFAD))
\rd_data_sm_cs[3]_i_4
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0035))
\rd_data_sm_cs[3]_i_5
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h1FFF))
\rd_data_sm_cs[3]_i_6
(.I0(act_rd_burst_two),
.I1(act_rd_burst),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\rd_data_sm_cs[3]_i_6_n_0 ));
LUT3 #(
.INIT(8'hBA))
\rd_data_sm_cs[3]_i_7
(.I0(brst_zero),
.I1(axi_b2b_brst),
.I2(end_brst_rd),
.O(\rd_data_sm_cs[3]_i_7_n_0 ));
FDRE \rd_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[0]_i_1_n_0 ),
.Q(rd_data_sm_cs[0]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[1]_i_1_n_0 ),
.Q(rd_data_sm_cs[1]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[2]_i_1_n_0 ),
.Q(rd_data_sm_cs[2]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[3]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[3]_i_2_n_0 ),
.Q(rd_data_sm_cs[3]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h1110011001100110))
rd_skid_buf_ld_reg_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(s_axi_rready),
.I5(s_axi_rvalid),
.O(rd_skid_buf_ld_cmb));
FDRE #(
.INIT(1'b0))
rd_skid_buf_ld_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rd_skid_buf_ld_cmb),
.Q(rd_skid_buf_ld_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFE02))
rddata_mux_sel_i_1
(.I0(rddata_mux_sel_cmb),
.I1(rd_data_sm_cs[3]),
.I2(rddata_mux_sel_i_3_n_0),
.I3(rddata_mux_sel),
.O(rddata_mux_sel_i_1_n_0));
LUT6 #(
.INIT(64'hF0F010F00F00F000))
rddata_mux_sel_i_2
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.I5(rd_adv_buf67_out),
.O(rddata_mux_sel_cmb));
LUT6 #(
.INIT(64'hF700070FF70F070F))
rddata_mux_sel_i_3
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(rddata_mux_sel_i_3_n_0));
FDRE #(
.INIT(1'b0))
rddata_mux_sel_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rddata_mux_sel_i_1_n_0),
.Q(rddata_mux_sel),
.R(bram_rst_a));
LUT4 #(
.INIT(16'hEAAA))
s_axi_arready_INST_0
(.I0(axi_arready_int),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(axi_early_arready_int),
.O(s_axi_arready));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
(axi_aresetn_d2,
axi_aresetn_re_reg,
bram_en_a,
bram_wrdata_a,
s_axi_bvalid,
\GEN_AW_DUAL.aw_active_reg_0 ,
s_axi_wready,
s_axi_awready,
bram_addr_a,
s_axi_bid,
bram_we_a,
SR,
s_axi_aclk,
s_axi_awaddr,
s_axi_aresetn,
s_axi_wdata,
s_axi_wvalid,
s_axi_wlast,
s_axi_bready,
s_axi_awburst,
s_axi_awid,
s_axi_awvalid,
s_axi_awlen,
s_axi_wstrb);
output axi_aresetn_d2;
output axi_aresetn_re_reg;
output bram_en_a;
output [31:0]bram_wrdata_a;
output s_axi_bvalid;
output \GEN_AW_DUAL.aw_active_reg_0 ;
output s_axi_wready;
output s_axi_awready;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output [3:0]bram_we_a;
input [0:0]SR;
input s_axi_aclk;
input [10:0]s_axi_awaddr;
input s_axi_aresetn;
input [31:0]s_axi_wdata;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_bready;
input [1:0]s_axi_awburst;
input [11:0]s_axi_awid;
input s_axi_awvalid;
input [7:0]s_axi_awlen;
input [3:0]s_axi_wstrb;
wire BID_FIFO_n_0;
wire BID_FIFO_n_10;
wire BID_FIFO_n_11;
wire BID_FIFO_n_12;
wire BID_FIFO_n_13;
wire BID_FIFO_n_14;
wire BID_FIFO_n_15;
wire BID_FIFO_n_3;
wire BID_FIFO_n_4;
wire BID_FIFO_n_5;
wire BID_FIFO_n_6;
wire BID_FIFO_n_7;
wire BID_FIFO_n_8;
wire BID_FIFO_n_9;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_1_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_2_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_3_n_0 ;
wire \GEN_AW_DUAL.aw_active_i_2_n_0 ;
wire \GEN_AW_DUAL.aw_active_reg_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ;
wire \I_RD_CHNL/axi_aresetn_d1 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_5;
wire I_WRAP_BRST_n_6;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [0:0]SR;
wire aw_active;
wire axi_aresetn_d2;
wire axi_aresetn_re;
wire axi_aresetn_re_reg;
wire axi_awaddr_full;
wire [1:0]axi_awburst_pipe;
wire [11:0]axi_awid_pipe;
wire [7:0]axi_awlen_pipe;
wire axi_awlen_pipe_1_or_2;
wire [1:1]axi_awsize_pipe;
wire axi_bvalid_int_i_1_n_0;
wire axi_wdata_full_cmb;
wire axi_wdata_full_cmb114_out;
wire axi_wdata_full_reg;
wire axi_wr_burst;
wire axi_wr_burst_cmb;
wire axi_wr_burst_cmb0;
wire axi_wr_burst_i_1_n_0;
wire axi_wr_burst_i_3_n_0;
wire axi_wready_int_mod_i_1_n_0;
wire axi_wready_int_mod_i_3_n_0;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_2_n_0;
wire [10:0]bram_addr_a;
wire bram_addr_inc;
wire [10:10]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire bram_en_a;
wire bram_en_cmb;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire [2:0]bvalid_cnt;
wire \bvalid_cnt[0]_i_1_n_0 ;
wire \bvalid_cnt[1]_i_1_n_0 ;
wire \bvalid_cnt[2]_i_1_n_0 ;
wire bvalid_cnt_inc;
wire bvalid_cnt_inc11_out;
wire clr_bram_we;
wire clr_bram_we_cmb;
wire curr_awlen_reg_1_or_2;
wire curr_awlen_reg_1_or_20;
wire curr_awlen_reg_1_or_2_i_2_n_0;
wire curr_awlen_reg_1_or_2_i_3_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire delay_aw_active_clr;
wire last_data_ack_mod;
wire p_18_out;
wire p_9_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire wr_addr_sm_cs;
(* RTL_KEEP = "yes" *) wire [2:0]wr_data_sm_cs;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO BID_FIFO
(.D({BID_FIFO_n_4,BID_FIFO_n_5,BID_FIFO_n_6,BID_FIFO_n_7,BID_FIFO_n_8,BID_FIFO_n_9,BID_FIFO_n_10,BID_FIFO_n_11,BID_FIFO_n_12,BID_FIFO_n_13,BID_FIFO_n_14,BID_FIFO_n_15}),
.E(BID_FIFO_n_0),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.Q(axi_awid_pipe),
.SR(SR),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_bvalid_int_reg(s_axi_bvalid),
.axi_wdata_full_cmb114_out(axi_wdata_full_cmb114_out),
.axi_wr_burst(axi_wr_burst),
.bid_gets_fifo_load(bid_gets_fifo_load),
.bid_gets_fifo_load_d1(bid_gets_fifo_load_d1),
.bid_gets_fifo_load_d1_reg(BID_FIFO_n_3),
.bram_addr_ld_en(bram_addr_ld_en),
.bvalid_cnt(bvalid_cnt),
.bvalid_cnt_inc(bvalid_cnt_inc),
.\bvalid_cnt_reg[1] (bid_gets_fifo_load_d1_i_2_n_0),
.\bvalid_cnt_reg[2] (I_WRAP_BRST_n_17),
.\bvalid_cnt_reg[2]_0 (I_WRAP_BRST_n_16),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.wr_addr_sm_cs(wr_addr_sm_cs));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[0]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h05051F1A))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(axi_wr_burst_cmb0),
.I2(wr_data_sm_cs[0]),
.I3(axi_wdata_full_cmb114_out),
.I4(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT4 #(
.INIT(16'h5515))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3
(.I0(I_WRAP_BRST_n_18),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.O(axi_wr_burst_cmb0));
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[1]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000554000555540))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(s_axi_wlast),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[2]),
.I5(axi_wr_burst),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h44010001))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2
(.I0(wr_data_sm_cs[2]),
.I1(wr_data_sm_cs[1]),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h7774777774744444))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[0]),
.I5(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ),
.Q(wr_data_sm_cs[0]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ),
.Q(wr_data_sm_cs[1]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ),
.Q(wr_data_sm_cs[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn),
.Q(\I_RD_CHNL/axi_aresetn_d1 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\I_RD_CHNL/axi_aresetn_d1 ),
.Q(axi_aresetn_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\GEN_AWREADY.axi_aresetn_re_reg_i_1
(.I0(s_axi_aresetn),
.I1(\I_RD_CHNL/axi_aresetn_d1 ),
.O(axi_aresetn_re));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_re_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_aresetn_re),
.Q(axi_aresetn_re_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFBFBFFFFFAA00))
\GEN_AWREADY.axi_awready_int_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(bram_addr_ld_en),
.I4(axi_aresetn_re_reg),
.I5(s_axi_awready),
.O(\GEN_AWREADY.axi_awready_int_i_1_n_0 ));
LUT6 #(
.INIT(64'h5444444400000000))
\GEN_AWREADY.axi_awready_int_i_2
(.I0(\GEN_AWREADY.axi_awready_int_i_3_n_0 ),
.I1(aw_active),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(s_axi_awvalid),
.O(\GEN_AWREADY.axi_awready_int_i_2_n_0 ));
LUT6 #(
.INIT(64'hAABABABABABABABA))
\GEN_AWREADY.axi_awready_int_i_3
(.I0(wr_addr_sm_cs),
.I1(I_WRAP_BRST_n_18),
.I2(last_data_ack_mod),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\GEN_AWREADY.axi_awready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_awready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AWREADY.axi_awready_int_i_1_n_0 ),
.Q(s_axi_awready),
.R(SR));
LUT1 #(
.INIT(2'h1))
\GEN_AW_DUAL.aw_active_i_1
(.I0(axi_aresetn_d2),
.O(\GEN_AW_DUAL.aw_active_reg_0 ));
LUT6 #(
.INIT(64'hFFFFF7FFFFFF0000))
\GEN_AW_DUAL.aw_active_i_2
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(wr_data_sm_cs[2]),
.I3(delay_aw_active_clr),
.I4(bram_addr_ld_en),
.I5(aw_active),
.O(\GEN_AW_DUAL.aw_active_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.aw_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.aw_active_i_2_n_0 ),
.Q(aw_active),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'h80))
\GEN_AW_DUAL.last_data_ack_mod_i_1
(.I0(s_axi_wready),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(p_18_out));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.last_data_ack_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_18_out),
.Q(last_data_ack_mod),
.R(SR));
LUT6 #(
.INIT(64'h0010001000100000))
\GEN_AW_DUAL.wr_addr_sm_cs_i_1
(.I0(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ),
.I1(wr_addr_sm_cs),
.I2(s_axi_awvalid),
.I3(axi_awaddr_full),
.I4(I_WRAP_BRST_n_17),
.I5(aw_active),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_AW_DUAL.wr_addr_sm_cs_i_2
(.I0(I_WRAP_BRST_n_17),
.I1(last_data_ack_mod),
.I2(axi_awaddr_full),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(axi_awlen_pipe_1_or_2),
.I5(curr_awlen_reg_1_or_2),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ));
FDRE \GEN_AW_DUAL.wr_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ),
.Q(wr_addr_sm_cs),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[8]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[9]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[10]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[0]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[1]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[2]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[3]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[4]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[5]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[6]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[7]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.R(1'b0));
LUT5 #(
.INIT(32'h4000EA00))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(s_axi_aresetn),
.I4(bram_addr_ld_en),
.O(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ),
.Q(axi_awaddr_full),
.R(1'b0));
LUT6 #(
.INIT(64'hBF00BF00BF00FF40))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(s_axi_awburst[0]),
.I5(s_axi_awburst[1]),
.O(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[0]),
.Q(axi_awburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[1]),
.Q(axi_awburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[0]),
.Q(axi_awid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[10]),
.Q(axi_awid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[11]),
.Q(axi_awid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[1]),
.Q(axi_awid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[2]),
.Q(axi_awid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[3]),
.Q(axi_awid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[4]),
.Q(axi_awid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[5]),
.Q(axi_awid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[6]),
.Q(axi_awid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[7]),
.Q(axi_awid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[8]),
.Q(axi_awid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[9]),
.Q(axi_awid_pipe[9]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(s_axi_awlen[3]),
.I2(s_axi_awlen[2]),
.I3(s_axi_awlen[1]),
.O(p_9_out));
LUT4 #(
.INIT(16'h0001))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2
(.I0(s_axi_awlen[4]),
.I1(s_axi_awlen[6]),
.I2(s_axi_awlen[7]),
.I3(s_axi_awlen[5]),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(p_9_out),
.Q(axi_awlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[0]),
.Q(axi_awlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[1]),
.Q(axi_awlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[2]),
.Q(axi_awlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[3]),
.Q(axi_awlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[4]),
.Q(axi_awlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[5]),
.Q(axi_awlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[6]),
.Q(axi_awlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[7]),
.Q(axi_awlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(1'b1),
.Q(axi_awsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0
(.I0(bram_addr_a[4]),
.I1(bram_addr_a[1]),
.I2(bram_addr_a[0]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[3]),
.I5(bram_addr_a[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(s_axi_wvalid),
.O(bram_addr_inc));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(wr_data_sm_cs[1]),
.O(bram_addr_rst_cmb));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0
(.I0(bram_addr_a[6]),
.I1(bram_addr_a[4]),
.I2(I_WRAP_BRST_n_14),
.I3(bram_addr_a[5]),
.I4(bram_addr_a[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ));
LUT4 #(
.INIT(16'h00E2))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(bram_addr_a[10]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_ld),
.I3(I_WRAP_BRST_n_0),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_4),
.Q(bram_addr_a[8]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_3),
.Q(bram_addr_a[9]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ),
.Q(bram_addr_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_12),
.Q(bram_addr_a[0]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_11),
.Q(bram_addr_a[1]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_10),
.Q(bram_addr_a[2]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_9),
.Q(bram_addr_a[3]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_8),
.Q(bram_addr_a[4]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_7),
.Q(bram_addr_a[5]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_6),
.Q(bram_addr_a[6]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_5),
.Q(bram_addr_a[7]),
.R(I_WRAP_BRST_n_0));
LUT5 #(
.INIT(32'h15FF1500))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.O(axi_wdata_full_cmb));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wdata_full_cmb),
.Q(axi_wdata_full_reg),
.R(SR));
LUT6 #(
.INIT(64'h4777477444444444))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(s_axi_wvalid),
.O(bram_en_cmb));
LUT3 #(
.INIT(8'h15))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_cmb),
.Q(bram_en_a),
.R(SR));
LUT6 #(
.INIT(64'h0010001000101110))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1
(.I0(wr_data_sm_cs[0]),
.I1(wr_data_sm_cs[1]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I5(axi_wr_burst),
.O(clr_bram_we_cmb));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'h80))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(clr_bram_we_cmb),
.Q(clr_bram_we),
.R(SR));
LUT6 #(
.INIT(64'hFEAAFEFF02AA0200))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ),
.I1(axi_wr_burst),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ),
.I5(delay_aw_active_clr),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ));
LUT5 #(
.INIT(32'h0000222E))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2
(.I0(s_axi_wlast),
.I1(wr_data_sm_cs[2]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[1]),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ));
LUT6 #(
.INIT(64'h8B338B0088008800))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3
(.I0(delay_aw_active_clr),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(bvalid_cnt_inc11_out),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4
(.I0(s_axi_wvalid),
.I1(s_axi_wlast),
.O(bvalid_cnt_inc11_out));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ),
.Q(delay_aw_active_clr),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[0].bram_wrdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[0]),
.Q(bram_wrdata_a[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[10].bram_wrdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[10]),
.Q(bram_wrdata_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[11].bram_wrdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[11]),
.Q(bram_wrdata_a[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[12].bram_wrdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[12]),
.Q(bram_wrdata_a[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[13].bram_wrdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[13]),
.Q(bram_wrdata_a[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[14].bram_wrdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[14]),
.Q(bram_wrdata_a[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[15].bram_wrdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[15]),
.Q(bram_wrdata_a[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[16].bram_wrdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[16]),
.Q(bram_wrdata_a[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[17].bram_wrdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[17]),
.Q(bram_wrdata_a[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[18].bram_wrdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[18]),
.Q(bram_wrdata_a[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[19].bram_wrdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[19]),
.Q(bram_wrdata_a[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[1].bram_wrdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[1]),
.Q(bram_wrdata_a[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[20].bram_wrdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[20]),
.Q(bram_wrdata_a[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[21].bram_wrdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[21]),
.Q(bram_wrdata_a[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[22].bram_wrdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[22]),
.Q(bram_wrdata_a[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[23].bram_wrdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[23]),
.Q(bram_wrdata_a[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[24].bram_wrdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[24]),
.Q(bram_wrdata_a[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[25].bram_wrdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[25]),
.Q(bram_wrdata_a[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[26].bram_wrdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[26]),
.Q(bram_wrdata_a[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[27].bram_wrdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[27]),
.Q(bram_wrdata_a[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[28].bram_wrdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[28]),
.Q(bram_wrdata_a[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[29].bram_wrdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[29]),
.Q(bram_wrdata_a[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[2].bram_wrdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[2]),
.Q(bram_wrdata_a[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[30].bram_wrdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[30]),
.Q(bram_wrdata_a[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[31].bram_wrdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[31]),
.Q(bram_wrdata_a[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[3].bram_wrdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[3]),
.Q(bram_wrdata_a[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[4].bram_wrdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[4]),
.Q(bram_wrdata_a[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[5].bram_wrdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[5]),
.Q(bram_wrdata_a[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[6].bram_wrdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[6]),
.Q(bram_wrdata_a[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[7].bram_wrdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[7]),
.Q(bram_wrdata_a[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[8].bram_wrdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[8]),
.Q(bram_wrdata_a[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[9].bram_wrdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[9]),
.Q(bram_wrdata_a[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hD0FF))
\GEN_WR_NO_ECC.bram_we_int[3]_i_1
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(clr_bram_we),
.I3(s_axi_aresetn),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\GEN_WR_NO_ECC.bram_we_int[3]_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[0]),
.Q(bram_we_a[0]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[1]),
.Q(bram_we_a[1]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[2]),
.Q(bram_we_a[2]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[3]),
.Q(bram_we_a[3]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst I_WRAP_BRST
(.D({I_WRAP_BRST_n_3,I_WRAP_BRST_n_4,I_WRAP_BRST_n_5,I_WRAP_BRST_n_6,I_WRAP_BRST_n_7,I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12}),
.E(I_WRAP_BRST_n_2),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_0),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (I_WRAP_BRST_n_14),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ),
.Q(axi_awlen_pipe[3:0]),
.SR(SR),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_awsize_pipe(axi_awsize_pipe),
.bram_addr_a(bram_addr_a[9:0]),
.bram_addr_inc(bram_addr_inc),
.bram_addr_ld_en(bram_addr_ld_en),
.bram_addr_ld_en_mod(bram_addr_ld_en_mod),
.bram_addr_rst_cmb(bram_addr_rst_cmb),
.bvalid_cnt(bvalid_cnt),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.curr_fixed_burst(curr_fixed_burst),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_fixed_burst_reg_reg(I_WRAP_BRST_n_19),
.curr_wrap_burst(curr_wrap_burst),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.curr_wrap_burst_reg_reg(I_WRAP_BRST_n_20),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen[3:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wvalid(s_axi_wvalid),
.\save_init_bram_addr_ld_reg[12]_0 (bram_addr_ld),
.\save_init_bram_addr_ld_reg[12]_1 (I_WRAP_BRST_n_16),
.\save_init_bram_addr_ld_reg[12]_2 (I_WRAP_BRST_n_17),
.\save_init_bram_addr_ld_reg[12]_3 (I_WRAP_BRST_n_18),
.wr_addr_sm_cs(wr_addr_sm_cs));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[0]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_15),
.Q(s_axi_bid[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[10]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_5),
.Q(s_axi_bid[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[11]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_4),
.Q(s_axi_bid[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[1]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_14),
.Q(s_axi_bid[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[2]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_13),
.Q(s_axi_bid[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[3]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_12),
.Q(s_axi_bid[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[4]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_11),
.Q(s_axi_bid[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[5]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_10),
.Q(s_axi_bid[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[6]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_9),
.Q(s_axi_bid[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[7]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_8),
.Q(s_axi_bid[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[8]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_7),
.Q(s_axi_bid[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[9]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_6),
.Q(s_axi_bid[9]),
.R(SR));
LUT6 #(
.INIT(64'hAAAAAAAAAAAA8A88))
axi_bvalid_int_i_1
(.I0(s_axi_aresetn),
.I1(bvalid_cnt_inc),
.I2(BID_FIFO_n_3),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(bvalid_cnt[1]),
.O(axi_bvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_bvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_int_i_1_n_0),
.Q(s_axi_bvalid),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
axi_wr_burst_i_1
(.I0(axi_wr_burst_cmb),
.I1(axi_wr_burst_i_3_n_0),
.I2(axi_wr_burst),
.O(axi_wr_burst_i_1_n_0));
LUT5 #(
.INIT(32'h3088FCBB))
axi_wr_burst_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wlast),
.O(axi_wr_burst_cmb));
LUT6 #(
.INIT(64'h00000000AAAAA222))
axi_wr_burst_i_3
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[0]),
.I2(axi_wr_burst_cmb0),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[1]),
.I5(wr_data_sm_cs[2]),
.O(axi_wr_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wr_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wr_burst_i_1_n_0),
.Q(axi_wr_burst),
.R(SR));
LUT6 #(
.INIT(64'hEA00EAFF00000000))
axi_wready_int_mod_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.I5(s_axi_aresetn),
.O(axi_wready_int_mod_i_1_n_0));
LUT5 #(
.INIT(32'hF8F9F0F0))
axi_wready_int_mod_i_3
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(axi_wdata_full_reg),
.I3(axi_wdata_full_cmb114_out),
.I4(s_axi_wvalid),
.O(axi_wready_int_mod_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wready_int_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wready_int_mod_i_1_n_0),
.Q(s_axi_wready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hEF))
bid_gets_fifo_load_d1_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.O(bid_gets_fifo_load_d1_i_2_n_0));
FDRE #(
.INIT(1'b0))
bid_gets_fifo_load_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bid_gets_fifo_load),
.Q(bid_gets_fifo_load_d1),
.R(SR));
LUT6 #(
.INIT(64'h95956A6A95956AAA))
\bvalid_cnt[0]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD5D5BFBF2A2A4000))
\bvalid_cnt[1]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD52AFF00FF00BF00))
\bvalid_cnt[2]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[0]_i_1_n_0 ),
.Q(bvalid_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[1]_i_1_n_0 ),
.Q(bvalid_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[2]_i_1_n_0 ),
.Q(bvalid_cnt[2]),
.R(SR));
LUT6 #(
.INIT(64'h5000303050003000))
curr_awlen_reg_1_or_2_i_1
(.I0(axi_awlen_pipe[3]),
.I1(s_axi_awlen[3]),
.I2(curr_awlen_reg_1_or_2_i_2_n_0),
.I3(curr_awlen_reg_1_or_2_i_3_n_0),
.I4(axi_awaddr_full),
.I5(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.O(curr_awlen_reg_1_or_20));
LUT5 #(
.INIT(32'h00053305))
curr_awlen_reg_1_or_2_i_2
(.I0(s_axi_awlen[2]),
.I1(axi_awlen_pipe[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(axi_awlen_pipe[1]),
.O(curr_awlen_reg_1_or_2_i_2_n_0));
LUT5 #(
.INIT(32'h00000100))
curr_awlen_reg_1_or_2_i_3
(.I0(axi_awlen_pipe[4]),
.I1(axi_awlen_pipe[7]),
.I2(axi_awlen_pipe[6]),
.I3(axi_awaddr_full),
.I4(axi_awlen_pipe[5]),
.O(curr_awlen_reg_1_or_2_i_3_n_0));
FDRE #(
.INIT(1'b0))
curr_awlen_reg_1_or_2_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_awlen_reg_1_or_20),
.Q(curr_awlen_reg_1_or_2),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_19),
.Q(curr_fixed_burst_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_20),
.Q(curr_wrap_burst_reg),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
bram_addr_ld_en_mod,
E,
D,
\save_init_bram_addr_ld_reg[12]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
bram_addr_ld_en,
\save_init_bram_addr_ld_reg[12]_1 ,
\save_init_bram_addr_ld_reg[12]_2 ,
\save_init_bram_addr_ld_reg[12]_3 ,
curr_fixed_burst_reg_reg,
curr_wrap_burst_reg_reg,
curr_fixed_burst_reg,
bram_addr_inc,
bram_addr_rst_cmb,
s_axi_aresetn,
out,
s_axi_wvalid,
bram_addr_a,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ,
axi_awaddr_full,
s_axi_awaddr,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
wr_addr_sm_cs,
last_data_ack_mod,
bvalid_cnt,
aw_active,
s_axi_awvalid,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
axi_awlen_pipe_1_or_2,
curr_awlen_reg_1_or_2,
curr_wrap_burst_reg,
Q,
s_axi_awlen,
axi_awsize_pipe,
curr_fixed_burst,
curr_wrap_burst,
SR,
s_axi_aclk);
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output bram_addr_ld_en_mod;
output [0:0]E;
output [9:0]D;
output [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
output bram_addr_ld_en;
output \save_init_bram_addr_ld_reg[12]_1 ;
output \save_init_bram_addr_ld_reg[12]_2 ;
output \save_init_bram_addr_ld_reg[12]_3 ;
output curr_fixed_burst_reg_reg;
output curr_wrap_burst_reg_reg;
input curr_fixed_burst_reg;
input bram_addr_inc;
input bram_addr_rst_cmb;
input s_axi_aresetn;
input [2:0]out;
input s_axi_wvalid;
input [9:0]bram_addr_a;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
input axi_awaddr_full;
input [10:0]s_axi_awaddr;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input wr_addr_sm_cs;
input last_data_ack_mod;
input [2:0]bvalid_cnt;
input aw_active;
input s_axi_awvalid;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input axi_awlen_pipe_1_or_2;
input curr_awlen_reg_1_or_2;
input curr_wrap_burst_reg;
input [3:0]Q;
input [3:0]s_axi_awlen;
input [0:0]axi_awsize_pipe;
input curr_fixed_burst;
input curr_wrap_burst;
input [0:0]SR;
input s_axi_aclk;
wire [9:0]D;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
wire [3:0]Q;
wire [0:0]SR;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire [0:0]axi_awsize_pipe;
wire [9:0]bram_addr_a;
wire bram_addr_inc;
wire [9:1]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire [2:0]bvalid_cnt;
wire curr_awlen_reg_1_or_2;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_fixed_burst_reg_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire curr_wrap_burst_reg_reg;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [10:0]s_axi_awaddr;
wire [3:0]s_axi_awlen;
wire s_axi_awvalid;
wire s_axi_wvalid;
wire [12:3]save_init_bram_addr_ld;
wire \save_init_bram_addr_ld[12]_i_6_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2__0_n_0 ;
wire [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
wire \save_init_bram_addr_ld_reg[12]_1 ;
wire \save_init_bram_addr_ld_reg[12]_2 ;
wire \save_init_bram_addr_ld_reg[12]_3 ;
wire wr_addr_sm_cs;
wire [2:0]wrap_burst_total;
wire \wrap_burst_total[0]_i_1__0_n_0 ;
wire \wrap_burst_total[0]_i_2__0_n_0 ;
wire \wrap_burst_total[0]_i_3_n_0 ;
wire \wrap_burst_total[1]_i_1__0_n_0 ;
wire \wrap_burst_total[1]_i_2__0_n_0 ;
wire \wrap_burst_total[1]_i_3__0_n_0 ;
wire \wrap_burst_total[2]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_2__0_n_0 ;
wire \wrap_burst_total[2]_i_3_n_0 ;
LUT6 #(
.INIT(64'hBB8BBBBB88B88888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1
(.I0(bram_addr_ld[8]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[7]),
.I5(bram_addr_a[8]),
.O(D[8]));
LUT5 #(
.INIT(32'h4500FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(bram_addr_inc),
.I3(bram_addr_rst_cmb),
.I4(s_axi_aresetn),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(E));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3
(.I0(bram_addr_ld[9]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[9]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ),
.I4(bram_addr_a[8]),
.O(D[9]));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(bram_addr_ld_en_mod));
LUT6 #(
.INIT(64'h55555555FFFFFFDF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3
(.I0(curr_wrap_burst_reg),
.I1(wrap_burst_total[1]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[0]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000008F00C000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4
(.I0(bram_addr_a[2]),
.I1(bram_addr_a[1]),
.I2(wrap_burst_total[1]),
.I3(bram_addr_a[0]),
.I4(wrap_burst_total[0]),
.I5(wrap_burst_total[2]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'hB800B800B800FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1
(.I0(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.I1(axi_awaddr_full),
.I2(s_axi_awaddr[0]),
.I3(bram_addr_ld_en),
.I4(bram_addr_ld_en_mod),
.I5(bram_addr_a[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h8BB8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1
(.I0(bram_addr_ld[1]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[1]),
.I3(bram_addr_a[0]),
.O(D[1]));
LUT5 #(
.INIT(32'h8BB8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1
(.I0(bram_addr_ld[2]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[0]),
.I4(bram_addr_a[1]),
.O(D[2]));
LUT6 #(
.INIT(64'h8BB8B8B8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1
(.I0(bram_addr_ld[3]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[3]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[0]),
.I5(bram_addr_a[1]),
.O(D[3]));
LUT4 #(
.INIT(16'hB88B))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1
(.I0(bram_addr_ld[4]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.O(D[4]));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1
(.I0(bram_addr_ld[5]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[5]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I4(bram_addr_a[4]),
.O(D[5]));
LUT6 #(
.INIT(64'hB8B88BB8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1
(.I0(bram_addr_ld[6]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(bram_addr_a[4]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(bram_addr_a[5]),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0
(.I0(bram_addr_a[1]),
.I1(bram_addr_a[0]),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1
(.I0(bram_addr_ld[7]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[6]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT4 #(
.INIT(16'h00E2))
curr_fixed_burst_reg_i_1__0
(.I0(curr_fixed_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_fixed_burst),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.O(curr_fixed_burst_reg_reg));
LUT4 #(
.INIT(16'h00E2))
curr_wrap_burst_reg_i_1__0
(.I0(curr_wrap_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_wrap_burst),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.O(curr_wrap_burst_reg_reg));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1
(.I0(save_init_bram_addr_ld[10]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[8]),
.O(bram_addr_ld[8]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1
(.I0(save_init_bram_addr_ld[11]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[9]),
.O(bram_addr_ld[9]));
LUT6 #(
.INIT(64'h0808080808AA0808))
\save_init_bram_addr_ld[12]_i_1
(.I0(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I1(\save_init_bram_addr_ld_reg[12]_1 ),
.I2(wr_addr_sm_cs),
.I3(\save_init_bram_addr_ld_reg[12]_2 ),
.I4(last_data_ack_mod),
.I5(\save_init_bram_addr_ld_reg[12]_3 ),
.O(bram_addr_ld_en));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[12]_i_2
(.I0(save_init_bram_addr_ld[12]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[10]),
.O(\save_init_bram_addr_ld_reg[12]_0 ));
LUT6 #(
.INIT(64'h007F007F007F0000))
\save_init_bram_addr_ld[12]_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.I3(aw_active),
.I4(axi_awaddr_full),
.I5(s_axi_awvalid),
.O(\save_init_bram_addr_ld_reg[12]_1 ));
LUT3 #(
.INIT(8'h80))
\save_init_bram_addr_ld[12]_i_4
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(\save_init_bram_addr_ld_reg[12]_2 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'hFFFD))
\save_init_bram_addr_ld[12]_i_5
(.I0(axi_awaddr_full),
.I1(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I2(axi_awlen_pipe_1_or_2),
.I3(curr_awlen_reg_1_or_2),
.O(\save_init_bram_addr_ld_reg[12]_3 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h1))
\save_init_bram_addr_ld[12]_i_6
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ),
.O(\save_init_bram_addr_ld[12]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1
(.I0(\save_init_bram_addr_ld[3]_i_2__0_n_0 ),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[1]),
.O(bram_addr_ld[1]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'hC80C))
\save_init_bram_addr_ld[3]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(save_init_bram_addr_ld[3]),
.I2(wrap_burst_total[1]),
.I3(wrap_burst_total[2]),
.O(\save_init_bram_addr_ld[3]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1
(.I0(\save_init_bram_addr_ld[4]_i_2__0_n_0 ),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[2]),
.O(bram_addr_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2__0
(.I0(save_init_bram_addr_ld[4]),
.I1(wrap_burst_total[0]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h8F808F8F8F808080))
\save_init_bram_addr_ld[5]_i_1
(.I0(save_init_bram_addr_ld[5]),
.I1(\save_init_bram_addr_ld[5]_i_2__0_n_0 ),
.I2(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I3(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.I4(axi_awaddr_full),
.I5(s_axi_awaddr[3]),
.O(bram_addr_ld[3]));
LUT3 #(
.INIT(8'hFB))
\save_init_bram_addr_ld[5]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(wrap_burst_total[2]),
.I2(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[5]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1
(.I0(save_init_bram_addr_ld[6]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[4]),
.O(bram_addr_ld[4]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1
(.I0(save_init_bram_addr_ld[7]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[5]),
.O(bram_addr_ld[5]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1
(.I0(save_init_bram_addr_ld[8]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[6]),
.O(bram_addr_ld[6]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1
(.I0(save_init_bram_addr_ld[9]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[7]),
.O(bram_addr_ld[7]));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[8]),
.Q(save_init_bram_addr_ld[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[9]),
.Q(save_init_bram_addr_ld[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld_reg[12]_0 ),
.Q(save_init_bram_addr_ld[12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[1]),
.Q(save_init_bram_addr_ld[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[2]),
.Q(save_init_bram_addr_ld[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[3]),
.Q(save_init_bram_addr_ld[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[4]),
.Q(save_init_bram_addr_ld[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[5]),
.Q(save_init_bram_addr_ld[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[6]),
.Q(save_init_bram_addr_ld[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[7]),
.Q(save_init_bram_addr_ld[9]),
.R(SR));
LUT6 #(
.INIT(64'h0000A22200000000))
\wrap_burst_total[0]_i_1__0
(.I0(\wrap_burst_total[0]_i_2__0_n_0 ),
.I1(\wrap_burst_total[0]_i_3_n_0 ),
.I2(Q[1]),
.I3(Q[2]),
.I4(\wrap_burst_total[2]_i_2__0_n_0 ),
.I5(\wrap_burst_total[1]_i_2__0_n_0 ),
.O(\wrap_burst_total[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hCCA533A5FFA5FFA5))
\wrap_burst_total[0]_i_2__0
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.I5(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3
(.I0(axi_awaddr_full),
.I1(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h08000800F3000000))
\wrap_burst_total[1]_i_1__0
(.I0(\wrap_burst_total[2]_i_3_n_0 ),
.I1(axi_awaddr_full),
.I2(axi_awsize_pipe),
.I3(\wrap_burst_total[1]_i_2__0_n_0 ),
.I4(\wrap_burst_total[1]_i_3__0_n_0 ),
.I5(\wrap_burst_total[2]_i_2__0_n_0 ),
.O(\wrap_burst_total[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_2__0
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[0]),
.O(\wrap_burst_total[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_3__0
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[1]),
.O(\wrap_burst_total[1]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hA000000088008800))
\wrap_burst_total[2]_i_1__0
(.I0(\wrap_burst_total[2]_i_2__0_n_0 ),
.I1(s_axi_awlen[0]),
.I2(Q[0]),
.I3(\wrap_burst_total[2]_i_3_n_0 ),
.I4(axi_awsize_pipe),
.I5(axi_awaddr_full),
.O(\wrap_burst_total[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_2__0
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[3]),
.O(\wrap_burst_total[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_3
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.O(\wrap_burst_total[2]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1__0_n_0 ),
.Q(wrap_burst_total[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1__0_n_0 ),
.Q(wrap_burst_total[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1__0_n_0 ),
.Q(wrap_burst_total[2]),
.R(SR));
endmodule
(* ORIG_REF_NAME = "wrap_brst" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
SR,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[0]_1 ,
\wrap_burst_total_reg[0]_2 ,
\wrap_burst_total_reg[0]_3 ,
E,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ,
D,
bram_addr_ld_en,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\save_init_bram_addr_ld_reg[12]_0 ,
\rd_data_sm_cs_reg[1] ,
\save_init_bram_addr_ld_reg[12]_1 ,
axi_b2b_brst_reg,
\rd_data_sm_cs_reg[3] ,
rd_adv_buf67_out,
end_brst_rd,
brst_zero,
Q,
axi_rvalid_int_reg,
s_axi_rready,
s_axi_aresetn,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ,
axi_arsize_pipe,
axi_araddr_full,
s_axi_arlen,
curr_fixed_burst_reg,
s_axi_araddr,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ,
curr_wrap_burst_reg,
axi_rd_burst_two_reg,
axi_rd_burst,
axi_aresetn_d2,
rd_addr_sm_cs,
last_bram_addr,
ar_active,
pend_rd_op,
no_ar_ack,
s_axi_arvalid,
axi_b2b_brst,
axi_arsize_pipe_max,
disable_b2b_brst,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ,
axi_arlen_pipe_1_or_2,
s_axi_aclk);
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output [0:0]SR;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[0]_1 ;
output \wrap_burst_total_reg[0]_2 ;
output \wrap_burst_total_reg[0]_3 ;
output [0:0]E;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
output [9:0]D;
output bram_addr_ld_en;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
output [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
output \rd_data_sm_cs_reg[1] ;
output \save_init_bram_addr_ld_reg[12]_1 ;
output axi_b2b_brst_reg;
output \rd_data_sm_cs_reg[3] ;
output rd_adv_buf67_out;
input end_brst_rd;
input brst_zero;
input [3:0]Q;
input axi_rvalid_int_reg;
input s_axi_rready;
input s_axi_aresetn;
input [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
input [0:0]axi_arsize_pipe;
input axi_araddr_full;
input [3:0]s_axi_arlen;
input curr_fixed_burst_reg;
input [10:0]s_axi_araddr;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
input [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
input curr_wrap_burst_reg;
input axi_rd_burst_two_reg;
input axi_rd_burst;
input axi_aresetn_d2;
input rd_addr_sm_cs;
input last_bram_addr;
input ar_active;
input pend_rd_op;
input no_ar_ack;
input s_axi_arvalid;
input axi_b2b_brst;
input axi_arsize_pipe_max;
input disable_b2b_brst;
input \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
input axi_arlen_pipe_1_or_2;
input s_axi_aclk;
wire [9:0]D;
wire [0:0]E;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
wire [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
wire [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire [3:0]Q;
wire [0:0]SR;
wire ar_active;
wire axi_araddr_full;
wire axi_aresetn_d2;
wire axi_arlen_pipe_1_or_2;
wire [0:0]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_b2b_brst;
wire axi_b2b_brst_reg;
wire axi_rd_burst;
wire axi_rd_burst_two_reg;
wire axi_rvalid_int_reg;
wire bram_addr_ld_en;
wire brst_zero;
wire curr_fixed_burst_reg;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire end_brst_rd;
wire last_bram_addr;
wire no_ar_ack;
wire pend_rd_op;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire \rd_data_sm_cs_reg[1] ;
wire \rd_data_sm_cs_reg[3] ;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire s_axi_aresetn;
wire [3:0]s_axi_arlen;
wire s_axi_arvalid;
wire s_axi_rready;
wire \save_init_bram_addr_ld[10]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[11]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[12]_i_3__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2_n_0 ;
wire \save_init_bram_addr_ld[4]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2_n_0 ;
wire \save_init_bram_addr_ld[5]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2_n_0 ;
wire \save_init_bram_addr_ld[6]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[7]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[8]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[9]_i_1__0_n_0 ;
wire [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
wire \save_init_bram_addr_ld_reg[12]_1 ;
wire \save_init_bram_addr_ld_reg_n_0_[10] ;
wire \save_init_bram_addr_ld_reg_n_0_[11] ;
wire \save_init_bram_addr_ld_reg_n_0_[12] ;
wire \save_init_bram_addr_ld_reg_n_0_[3] ;
wire \save_init_bram_addr_ld_reg_n_0_[4] ;
wire \save_init_bram_addr_ld_reg_n_0_[5] ;
wire \save_init_bram_addr_ld_reg_n_0_[6] ;
wire \save_init_bram_addr_ld_reg_n_0_[7] ;
wire \save_init_bram_addr_ld_reg_n_0_[8] ;
wire \save_init_bram_addr_ld_reg_n_0_[9] ;
wire \wrap_burst_total[0]_i_1_n_0 ;
wire \wrap_burst_total[0]_i_3__0_n_0 ;
wire \wrap_burst_total[1]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_2_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[0]_1 ;
wire \wrap_burst_total_reg[0]_2 ;
wire \wrap_burst_total_reg[0]_3 ;
wire \wrap_burst_total_reg_n_0_[0] ;
wire \wrap_burst_total_reg_n_0_[1] ;
wire \wrap_burst_total_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hDF20FFFFDF200000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [8]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.O(D[8]));
LUT3 #(
.INIT(8'h5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ),
.I2(curr_fixed_burst_reg),
.O(E));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [8]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hE0E0F0F0E0E0FFF0))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ),
.I2(\rd_data_sm_cs_reg[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.I4(Q[1]),
.I5(Q[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0
(.I0(axi_rd_burst_two_reg),
.I1(Q[0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h0000000080800080))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6
(.I0(Q[0]),
.I1(axi_rvalid_int_reg),
.I2(s_axi_rready),
.I3(end_brst_rd),
.I4(axi_b2b_brst),
.I5(brst_zero),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2__0
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ));
LUT6 #(
.INIT(64'h00000000A808FD5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0
(.I0(bram_addr_ld_en),
.I1(s_axi_araddr[0]),
.I2(axi_araddr_full),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.O(D[0]));
LUT5 #(
.INIT(32'h88A80000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ),
.I2(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(curr_wrap_burst_reg),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000008F00A000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I4(\wrap_burst_total_reg_n_0_[0] ),
.I5(\wrap_burst_total_reg_n_0_[2] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6F60))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I3(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.O(D[1]));
LUT5 #(
.INIT(32'h6AFF6A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h6AAAFFFF6AAA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [3]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.O(D[3]));
LUT4 #(
.INIT(16'h9F90))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I3(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [5]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hA6AAFFFFA6AA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [5]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.O(D[7]));
LUT2 #(
.INIT(4'h8))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4
(.I0(axi_rvalid_int_reg),
.I1(s_axi_rready),
.O(rd_adv_buf67_out));
LUT5 #(
.INIT(32'hFFFDFFFF))
axi_b2b_brst_i_2
(.I0(axi_arsize_pipe_max),
.I1(disable_b2b_brst),
.I2(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ),
.I3(axi_arlen_pipe_1_or_2),
.I4(axi_araddr_full),
.O(axi_b2b_brst_reg));
LUT2 #(
.INIT(4'hB))
bram_en_int_i_5
(.I0(Q[3]),
.I1(Q[2]),
.O(\rd_data_sm_cs_reg[3] ));
LUT6 #(
.INIT(64'h0010000000000000))
bram_en_int_i_8
(.I0(end_brst_rd),
.I1(brst_zero),
.I2(Q[2]),
.I3(Q[0]),
.I4(axi_rvalid_int_reg),
.I5(s_axi_rready),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT1 #(
.INIT(2'h1))
bram_rst_b_INST_0
(.I0(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'h000F000E000F0000))
\rd_data_sm_cs[1]_i_2
(.I0(axi_rd_burst_two_reg),
.I1(axi_rd_burst),
.I2(Q[3]),
.I3(Q[2]),
.I4(Q[1]),
.I5(Q[0]),
.O(\rd_data_sm_cs_reg[1] ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[10] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[8]),
.O(\save_init_bram_addr_ld[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[9]),
.O(\save_init_bram_addr_ld[11]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h02AA0202))
\save_init_bram_addr_ld[12]_i_1__0
(.I0(axi_aresetn_d2),
.I1(rd_addr_sm_cs),
.I2(\save_init_bram_addr_ld[12]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld_reg[12]_1 ),
.I4(last_bram_addr),
.O(bram_addr_ld_en));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[12]_i_2__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[12] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[10]),
.O(\save_init_bram_addr_ld_reg[12]_0 ));
LUT5 #(
.INIT(32'hFEFEFEFF))
\save_init_bram_addr_ld[12]_i_3__0
(.I0(ar_active),
.I1(pend_rd_op),
.I2(no_ar_ack),
.I3(s_axi_arvalid),
.I4(axi_araddr_full),
.O(\save_init_bram_addr_ld[12]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\save_init_bram_addr_ld[12]_i_4__0
(.I0(axi_b2b_brst_reg),
.I1(Q[0]),
.I2(Q[1]),
.I3(\rd_data_sm_cs_reg[3] ),
.I4(brst_zero),
.I5(rd_adv_buf67_out),
.O(\save_init_bram_addr_ld_reg[12]_1 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1__0
(.I0(\save_init_bram_addr_ld[3]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[1]),
.O(\save_init_bram_addr_ld[3]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hA282))
\save_init_bram_addr_ld[3]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[3] ),
.I1(\wrap_burst_total_reg_n_0_[1] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[0] ),
.O(\save_init_bram_addr_ld[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1__0
(.I0(\save_init_bram_addr_ld[4]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[2]),
.O(\save_init_bram_addr_ld[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[4] ),
.I1(\wrap_burst_total_reg_n_0_[0] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\save_init_bram_addr_ld[5]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[5] ),
.I1(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.I4(axi_araddr_full),
.I5(s_axi_araddr[3]),
.O(\save_init_bram_addr_ld[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h04))
\save_init_bram_addr_ld[5]_i_2
(.I0(\wrap_burst_total_reg_n_0_[0] ),
.I1(\wrap_burst_total_reg_n_0_[2] ),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[6] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[4]),
.O(\save_init_bram_addr_ld[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[7] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[5]),
.O(\save_init_bram_addr_ld[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[8] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[6]),
.O(\save_init_bram_addr_ld[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[9] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[7]),
.O(\save_init_bram_addr_ld[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[10] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[11] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld_reg[12]_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[12] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[7] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[8] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[9] ),
.R(SR));
LUT6 #(
.INIT(64'h3202010100000000))
\wrap_burst_total[0]_i_1
(.I0(\wrap_burst_total_reg[0]_0 ),
.I1(\wrap_burst_total_reg[0]_1 ),
.I2(\wrap_burst_total[0]_i_3__0_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I4(\wrap_burst_total_reg[0]_2 ),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[2]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3__0
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.O(\wrap_burst_total[0]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h20CF000000000000))
\wrap_burst_total[1]_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(axi_arsize_pipe),
.I2(axi_araddr_full),
.I3(\wrap_burst_total_reg[0]_1 ),
.I4(\wrap_burst_total_reg[0]_3 ),
.I5(\wrap_burst_total_reg[0]_2 ),
.O(\wrap_burst_total[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_2
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[3]),
.O(\wrap_burst_total_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_3
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [0]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[0]),
.O(\wrap_burst_total_reg[0]_3 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_4
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.O(\wrap_burst_total_reg[0]_2 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000D580))
\wrap_burst_total[2]_i_1
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.I2(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I3(s_axi_arlen[2]),
.I4(\wrap_burst_total[2]_i_2_n_0 ),
.O(\wrap_burst_total[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3FFF5F5F3FFFFFFF))
\wrap_burst_total[2]_i_2
(.I0(s_axi_arlen[3]),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I2(\wrap_burst_total_reg[0]_3 ),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I4(axi_araddr_full),
.I5(s_axi_arlen[1]),
.O(\wrap_burst_total[2]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[2] ),
.R(SR));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_bram_ctrl,Vivado 2017.2.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [12:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input s_axi_awlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [12:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input s_axi_arlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) output bram_rst_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) output bram_clk_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) output bram_en_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) output [3:0]bram_we_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) output [12:0]bram_addr_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) output [31:0]bram_wrdata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) input [31:0]bram_rddata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) output bram_rst_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) output bram_clk_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) output bram_en_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) output [3:0]bram_we_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) output [12:0]bram_addr_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) output [31:0]bram_wrdata_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) input [31:0]bram_rddata_b;
wire [12:0]bram_addr_a;
wire [12:0]bram_addr_b;
wire bram_clk_a;
wire bram_clk_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_a;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire bram_rst_b;
wire [3:0]bram_we_a;
wire [3:0]bram_we_b;
wire [31:0]bram_wrdata_a;
wire [31:0]bram_wrdata_b;
wire s_axi_aclk;
wire [12:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arlock;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [12:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awlock;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ecc_interrupt_UNCONNECTED;
wire NLW_U0_ecc_ue_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_arready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_awready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_wready_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_ctrl_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_rresp_UNCONNECTED;
(* C_BRAM_ADDR_WIDTH = "11" *)
(* C_BRAM_INST_MODE = "EXTERNAL" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *)
(* C_ECC_TYPE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *)
(* C_MEMORY_DEPTH = "2048" *)
(* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *)
(* C_S_AXI_ADDR_WIDTH = "13" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *)
(* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl U0
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_clk_a(bram_clk_a),
.bram_clk_b(bram_clk_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_a(bram_rddata_a),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_rst_b(bram_rst_b),
.bram_we_a(bram_we_a),
.bram_we_b(bram_we_b),
.bram_wrdata_a(bram_wrdata_a),
.bram_wrdata_b(bram_wrdata_b),
.ecc_interrupt(NLW_U0_ecc_interrupt_UNCONNECTED),
.ecc_ue(NLW_U0_ecc_ue_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_ctrl_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_arready(NLW_U0_s_axi_ctrl_arready_UNCONNECTED),
.s_axi_ctrl_arvalid(1'b0),
.s_axi_ctrl_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_awready(NLW_U0_s_axi_ctrl_awready_UNCONNECTED),
.s_axi_ctrl_awvalid(1'b0),
.s_axi_ctrl_bready(1'b0),
.s_axi_ctrl_bresp(NLW_U0_s_axi_ctrl_bresp_UNCONNECTED[1:0]),
.s_axi_ctrl_bvalid(NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED),
.s_axi_ctrl_rdata(NLW_U0_s_axi_ctrl_rdata_UNCONNECTED[31:0]),
.s_axi_ctrl_rready(1'b0),
.s_axi_ctrl_rresp(NLW_U0_s_axi_ctrl_rresp_UNCONNECTED[1:0]),
.s_axi_ctrl_rvalid(NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED),
.s_axi_ctrl_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_wready(NLW_U0_s_axi_ctrl_wready_UNCONNECTED),
.s_axi_ctrl_wvalid(1'b0),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
This file was generated automatically by the Mojo IDE version B1.3.6.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
/*
Parameters:
FACTOR = 5
*/
module serdes_n_to_1_22 (
input ioclk,
input strobe,
input rst,
input gclk,
input [4:0] data,
output reg iob_out
);
localparam FACTOR = 3'h5;
reg [7:0] padded_data;
integer i;
wire [1-1:0] M_mserdes_OQ;
wire [1-1:0] M_mserdes_TQ;
wire [1-1:0] M_mserdes_SHIFTOUT1;
wire [1-1:0] M_mserdes_SHIFTOUT2;
wire [1-1:0] M_mserdes_SHIFTOUT3;
wire [1-1:0] M_mserdes_SHIFTOUT4;
reg [1-1:0] M_mserdes_IOCE;
reg [1-1:0] M_mserdes_D1;
reg [1-1:0] M_mserdes_D2;
reg [1-1:0] M_mserdes_D3;
reg [1-1:0] M_mserdes_D4;
reg [1-1:0] M_mserdes_OCE;
reg [1-1:0] M_mserdes_T1;
reg [1-1:0] M_mserdes_T2;
reg [1-1:0] M_mserdes_T3;
reg [1-1:0] M_mserdes_T4;
reg [1-1:0] M_mserdes_TCE;
reg [1-1:0] M_mserdes_SHIFTIN1;
reg [1-1:0] M_mserdes_SHIFTIN2;
reg [1-1:0] M_mserdes_SHIFTIN3;
reg [1-1:0] M_mserdes_SHIFTIN4;
reg [1-1:0] M_mserdes_TRAIN;
OSERDES2 #(.DATA_WIDTH(5), .DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .SERDES_MODE("MASTER"), .OUTPUT_MODE("DIFFERENTIAL")) mserdes (
.CLK0(ioclk),
.CLK1(1'h0),
.RST(rst),
.CLKDIV(gclk),
.IOCE(M_mserdes_IOCE),
.D1(M_mserdes_D1),
.D2(M_mserdes_D2),
.D3(M_mserdes_D3),
.D4(M_mserdes_D4),
.OCE(M_mserdes_OCE),
.T1(M_mserdes_T1),
.T2(M_mserdes_T2),
.T3(M_mserdes_T3),
.T4(M_mserdes_T4),
.TCE(M_mserdes_TCE),
.SHIFTIN1(M_mserdes_SHIFTIN1),
.SHIFTIN2(M_mserdes_SHIFTIN2),
.SHIFTIN3(M_mserdes_SHIFTIN3),
.SHIFTIN4(M_mserdes_SHIFTIN4),
.TRAIN(M_mserdes_TRAIN),
.OQ(M_mserdes_OQ),
.TQ(M_mserdes_TQ),
.SHIFTOUT1(M_mserdes_SHIFTOUT1),
.SHIFTOUT2(M_mserdes_SHIFTOUT2),
.SHIFTOUT3(M_mserdes_SHIFTOUT3),
.SHIFTOUT4(M_mserdes_SHIFTOUT4)
);
wire [1-1:0] M_sserdes_OQ;
wire [1-1:0] M_sserdes_TQ;
wire [1-1:0] M_sserdes_SHIFTOUT1;
wire [1-1:0] M_sserdes_SHIFTOUT2;
wire [1-1:0] M_sserdes_SHIFTOUT3;
wire [1-1:0] M_sserdes_SHIFTOUT4;
reg [1-1:0] M_sserdes_IOCE;
reg [1-1:0] M_sserdes_D1;
reg [1-1:0] M_sserdes_D2;
reg [1-1:0] M_sserdes_D3;
reg [1-1:0] M_sserdes_D4;
reg [1-1:0] M_sserdes_OCE;
reg [1-1:0] M_sserdes_T1;
reg [1-1:0] M_sserdes_T2;
reg [1-1:0] M_sserdes_T3;
reg [1-1:0] M_sserdes_T4;
reg [1-1:0] M_sserdes_TCE;
reg [1-1:0] M_sserdes_SHIFTIN1;
reg [1-1:0] M_sserdes_SHIFTIN2;
reg [1-1:0] M_sserdes_SHIFTIN3;
reg [1-1:0] M_sserdes_SHIFTIN4;
reg [1-1:0] M_sserdes_TRAIN;
OSERDES2 #(.DATA_WIDTH(5), .DATA_RATE_OQ("SDR"), .DATA_RATE_OT("SDR"), .SERDES_MODE("SLAVE"), .OUTPUT_MODE("DIFFERENTIAL")) sserdes (
.CLK0(ioclk),
.CLK1(1'h0),
.RST(rst),
.CLKDIV(gclk),
.IOCE(M_sserdes_IOCE),
.D1(M_sserdes_D1),
.D2(M_sserdes_D2),
.D3(M_sserdes_D3),
.D4(M_sserdes_D4),
.OCE(M_sserdes_OCE),
.T1(M_sserdes_T1),
.T2(M_sserdes_T2),
.T3(M_sserdes_T3),
.T4(M_sserdes_T4),
.TCE(M_sserdes_TCE),
.SHIFTIN1(M_sserdes_SHIFTIN1),
.SHIFTIN2(M_sserdes_SHIFTIN2),
.SHIFTIN3(M_sserdes_SHIFTIN3),
.SHIFTIN4(M_sserdes_SHIFTIN4),
.TRAIN(M_sserdes_TRAIN),
.OQ(M_sserdes_OQ),
.TQ(M_sserdes_TQ),
.SHIFTOUT1(M_sserdes_SHIFTOUT1),
.SHIFTOUT2(M_sserdes_SHIFTOUT2),
.SHIFTOUT3(M_sserdes_SHIFTOUT3),
.SHIFTOUT4(M_sserdes_SHIFTOUT4)
);
always @* begin
padded_data = 8'h00;
for (i = 1'h0; i < 3'h5; i = i + 1) begin
padded_data[(i)*1+0-:1] = data[(i)*1+0-:1];
end
M_mserdes_OCE = 1'h1;
M_mserdes_IOCE = strobe;
M_mserdes_D4 = padded_data[7+0-:1];
M_mserdes_D3 = padded_data[6+0-:1];
M_mserdes_D2 = padded_data[5+0-:1];
M_mserdes_D1 = padded_data[4+0-:1];
M_mserdes_T1 = 1'h0;
M_mserdes_T2 = 1'h0;
M_mserdes_T3 = 1'h0;
M_mserdes_T4 = 1'h0;
M_mserdes_TRAIN = 1'h0;
M_mserdes_TCE = 1'h1;
M_mserdes_SHIFTIN1 = 1'h1;
M_mserdes_SHIFTIN2 = 1'h1;
M_mserdes_SHIFTIN3 = M_sserdes_SHIFTOUT3;
M_mserdes_SHIFTIN4 = M_sserdes_SHIFTOUT4;
M_sserdes_OCE = 1'h1;
M_sserdes_IOCE = strobe;
M_sserdes_D4 = padded_data[3+0-:1];
M_sserdes_D3 = padded_data[2+0-:1];
M_sserdes_D2 = padded_data[1+0-:1];
M_sserdes_D1 = padded_data[0+0-:1];
M_sserdes_T1 = 1'h0;
M_sserdes_T2 = 1'h0;
M_sserdes_T3 = 1'h0;
M_sserdes_T4 = 1'h0;
M_sserdes_TRAIN = 1'h0;
M_sserdes_TCE = 1'h1;
M_sserdes_SHIFTIN1 = M_mserdes_SHIFTOUT1;
M_sserdes_SHIFTIN2 = M_mserdes_SHIFTOUT2;
M_sserdes_SHIFTIN3 = 1'h1;
M_sserdes_SHIFTIN4 = 1'h1;
iob_out = M_mserdes_OQ;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , mux_out, CLK, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_FUNCTIONAL_V
|
// Ethernet_v6.v -
// Contains
// i) block-level-wrapper
// ii) EMAC wrapper
// iii) GMII code
//-----------------------------------------------------------------------------
// Title : Block-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_5_block.v
// Version : 1.5
//-----------------------------------------------------------------------------
// Description: This is the block-level wrapper for the Virtex-6 Embedded
// Tri-Mode Ethernet MAC. It is intended that this example design
// can be quickly adapted and downloaded onto an FPGA to provide
// a hardware test environment.
//
// The block-level wrapper:
//
// * instantiates appropriate PHY interface modules (GMII, MII,
// RGMII, SGMII or 1000BASE-X) as required per the user
// configuration;
//
// * instantiates some clocking and reset resources to operate
// the EMAC and its example design.
//
// Please refer to the Datasheet, Getting Started Guide, and
// the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
// further information.
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Module declaration for the block-level wrapper
//-----------------------------------------------------------------------------
module v6_emac_v1_5_block
(
// TX clock output
TX_CLK_OUT,
// TX clock input from BUFG
TX_CLK,
// Client receiver interface
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client transmitter interface
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC control interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Receive-side PHY clock on regional buffer, to EMAC
PHY_RX_CLK,
// Clock signal
GTX_CLK,
// GMII interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// Asynchronous reset
RESET
);
//-----------------------------------------------------------------------------
// Port declarations
//-----------------------------------------------------------------------------
// TX clock output
output TX_CLK_OUT;
// TX clock input from BUFG
input TX_CLK;
// Client receiver interface
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client transmitter interface
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC control interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Receive-side PHY clock on regional buffer, to EMAC
input PHY_RX_CLK;
// Clock signal
input GTX_CLK;
// GMII interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// Asynchronous reset
input RESET;
//-----------------------------------------------------------------------------
// Wire and register declarations
//-----------------------------------------------------------------------------
// Asynchronous reset signals
wire reset_ibuf_i;
wire reset_i;
// Client clocking signals
wire rx_client_clk_out_i;
wire rx_client_clk_in_i;
wire tx_client_clk_out_i;
wire tx_client_clk_in_i;
wire tx_gmii_mii_clk_out_i;
wire tx_gmii_mii_clk_in_i;
// Physical interface signals
wire gmii_tx_en_i;
wire gmii_tx_er_i;
wire [7:0] gmii_txd_i;
wire gmii_rx_dv_r;
wire gmii_rx_er_r;
wire [7:0] gmii_rxd_r;
wire gmii_rx_clk_i;
// 125MHz reference clock
wire gtx_clk_ibufg_i;
//-----------------------------------------------------------------------------
// Main body of code
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Main reset circuitry
//-------------------------------------------------------------------------
assign reset_ibuf_i = RESET;
assign reset_i = reset_ibuf_i;
//-------------------------------------------------------------------------
// GMII circuitry for the physical interface
//-------------------------------------------------------------------------
gmii_if gmii (
.RESET (reset_i),
.GMII_TXD (GMII_TXD),
.GMII_TX_EN (GMII_TX_EN),
.GMII_TX_ER (GMII_TX_ER),
.GMII_TX_CLK (GMII_TX_CLK),
.GMII_RXD (GMII_RXD),
.GMII_RX_DV (GMII_RX_DV),
.GMII_RX_ER (GMII_RX_ER),
.TXD_FROM_MAC (gmii_txd_i),
.TX_EN_FROM_MAC (gmii_tx_en_i),
.TX_ER_FROM_MAC (gmii_tx_er_i),
.TX_CLK (tx_gmii_mii_clk_in_i),
.RXD_TO_MAC (gmii_rxd_r),
.RX_DV_TO_MAC (gmii_rx_dv_r),
.RX_ER_TO_MAC (gmii_rx_er_r),
.RX_CLK (GMII_RX_CLK)
);
// GTX reference clock
assign gtx_clk_ibufg_i = GTX_CLK;
// GMII PHY-side transmit clock
assign tx_gmii_mii_clk_in_i = TX_CLK;
// GMII PHY-side receive clock, regionally-buffered
assign gmii_rx_clk_i = PHY_RX_CLK;
// GMII client-side transmit clock
assign tx_client_clk_in_i = TX_CLK;
// GMII client-side receive clock
assign rx_client_clk_in_i = gmii_rx_clk_i;
// TX clock output
assign TX_CLK_OUT = tx_gmii_mii_clk_out_i;
//------------------------------------------------------------------------
// Instantiate the primitive-level EMAC wrapper (v6_emac_v1_5.v)
//------------------------------------------------------------------------
v6_emac_v1_5 v6_emac_v1_5_inst
(
// Client receiver interface
.EMACCLIENTRXCLIENTCLKOUT (rx_client_clk_out_i),
.CLIENTEMACRXCLIENTCLKIN (rx_client_clk_in_i),
.EMACCLIENTRXD (EMACCLIENTRXD),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
// Client transmitter interface
.EMACCLIENTTXCLIENTCLKOUT (tx_client_clk_out_i),
.CLIENTEMACTXCLIENTCLKIN (tx_client_clk_in_i),
.CLIENTEMACTXD (CLIENTEMACTXD),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (1'b0),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
// MAC control interface
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
// Clock signals
.GTX_CLK (gtx_clk_ibufg_i),
.EMACPHYTXGMIIMIICLKOUT (tx_gmii_mii_clk_out_i),
.PHYEMACTXGMIIMIICLKIN (tx_gmii_mii_clk_in_i),
// GMII interface
.GMII_TXD (gmii_txd_i),
.GMII_TX_EN (gmii_tx_en_i),
.GMII_TX_ER (gmii_tx_er_i),
.GMII_RXD (gmii_rxd_r),
.GMII_RX_DV (gmii_rx_dv_r),
.GMII_RX_ER (gmii_rx_er_r),
.GMII_RX_CLK (gmii_rx_clk_i),
// MMCM lock indicator
.MMCM_LOCKED (1'b1),
// Asynchronous reset
.RESET (reset_i)
);
endmodule
//-----------------------------------------------------------------------------
// Title : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_5.v
// Version : 1.5
//-----------------------------------------------------------------------------
// Description: This wrapper file instantiates the full Virtex-6 Embedded
// Tri-Mode Ethernet MAC (EMAC) primitive, where:
//
// * all unused input ports on the primitive are tied to the
// appropriate logic level;
//
// * all unused output ports on the primitive are left
// unconnected;
//
// * the attributes are set based on the options selected
// from CORE Generator;
//
// * only used ports are connected to the ports of this
// wrapper file.
//
// This simplified wrapper should therefore be used as the
// instantiation template for the EMAC primitive in customer
// designs.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//------------------------------------------------------------------------------
// Module declaration for the primitive-level wrapper
//------------------------------------------------------------------------------
(* X_CORE_INFO = "v6_emac_v1_5, Coregen 11.3" *)
(* CORE_GENERATION_INFO = "v6_emac_v1_5,v6_emac_v1_5,{c_has_mii=false,c_has_gmii=true,c_has_rgmii_v1_5=false,c_has_rgmii_v2_0=false,c_has_sgmii=false,c_has_gpcs=false,c_tri_speed=false,c_speed_10=false,c_speed_100=false,c_speed_1000=true,c_has_host=false,c_has_dcr=false,c_has_mdio=false,c_client_16=false,c_add_filter=false,c_has_clock_enable=false,c_serial_mode_switch_en=false,c_overclocking_rate_2000mbps=false,c_overclocking_rate_2500mbps=false,}" *)
module v6_emac_v1_5
(
// Client Receiver Interface
EMACCLIENTRXCLIENTCLKOUT,
CLIENTEMACRXCLIENTCLKIN,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client Transmitter Interface
EMACCLIENTTXCLIENTCLKOUT,
CLIENTEMACTXCLIENTCLKIN,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC Control Interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Clock Signals
GTX_CLK,
PHYEMACTXGMIIMIICLKIN,
EMACPHYTXGMIIMIICLKOUT,
// GMII Interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// MMCM Lock Indicator
MMCM_LOCKED,
// Asynchronous Reset
RESET
);
//--------------------------------------------------------------------------
// Port declarations
//--------------------------------------------------------------------------
// Client Receiver Interface
output EMACCLIENTRXCLIENTCLKOUT;
input CLIENTEMACRXCLIENTCLKIN;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXDVLDMSW;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client Transmitter Interface
output EMACCLIENTTXCLIENTCLKOUT;
input CLIENTEMACTXCLIENTCLKIN;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
input CLIENTEMACTXDVLDMSW;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC Control Interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Clock Signals
input GTX_CLK;
output EMACPHYTXGMIIMIICLKOUT;
input PHYEMACTXGMIIMIICLKIN;
// GMII Interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// MMCM Lock Indicator
input MMCM_LOCKED;
// Asynchronous Reset
input RESET;
//--------------------------------------------------------------------------
// Wire declarations
//--------------------------------------------------------------------------
wire [15:0] client_rx_data_i;
wire [15:0] client_tx_data_i;
//--------------------------------------------------------------------------
// Main body of code
//--------------------------------------------------------------------------
// Use the 8-bit client data interface
assign EMACCLIENTRXD = client_rx_data_i[7:0];
assign #4000 client_tx_data_i = {8'b00000000, CLIENTEMACTXD};
// Instantiate the Virtex-6 Embedded Tri-Mode Ethernet MAC
TEMAC_SINGLE #(
// PCS/PMA logic is not in use
.EMAC_PHYINITAUTONEG_ENABLE ("FALSE"),
.EMAC_PHYISOLATE ("FALSE"),
.EMAC_PHYLOOPBACKMSB ("FALSE"),
.EMAC_PHYPOWERDOWN ("FALSE"),
.EMAC_PHYRESET ("TRUE"),
.EMAC_GTLOOPBACK ("FALSE"),
.EMAC_UNIDIRECTION_ENABLE ("FALSE"),
.EMAC_LINKTIMERVAL (9'h000),
.EMAC_MDIO_IGNORE_PHYADZERO ("FALSE"),
// Configure the EMAC operating mode
// MDIO is not enabled
.EMAC_MDIO_ENABLE ("FALSE"),
// Speed is defaulted to 1000 Mb/s
.EMAC_SPEED_LSB ("FALSE"),
.EMAC_SPEED_MSB ("TRUE"),
// Clock Enable advanced clocking is not in use
.EMAC_USECLKEN ("FALSE"),
// Byte PHY advanced clocking is not supported. Do not modify.
.EMAC_BYTEPHY ("FALSE"),
// RGMII physical interface is not in use
.EMAC_RGMII_ENABLE ("FALSE"),
// SGMII physical interface is not in use
.EMAC_SGMII_ENABLE ("FALSE"),
.EMAC_1000BASEX_ENABLE ("FALSE"),
// The host interface is not enabled
.EMAC_HOST_ENABLE ("FALSE"),
// The Tx-side 8-bit client data interface is used
.EMAC_TX16BITCLIENT_ENABLE ("FALSE"),
// The Rx-side 8-bit client data interface is used
.EMAC_RX16BITCLIENT_ENABLE ("FALSE"),
// The address filter is not enabled
.EMAC_ADDRFILTER_ENABLE ("FALSE"),
// EMAC configuration defaults
// Rx Length/Type checking is enabled
.EMAC_LTCHECK_DISABLE ("FALSE"),
// Rx control frame length checking is enabled
.EMAC_CTRLLENCHECK_DISABLE ("FALSE"),
// Rx flow control is not enabled
.EMAC_RXFLOWCTRL_ENABLE ("FALSE"),
// Tx flow control is not enabled
.EMAC_TXFLOWCTRL_ENABLE ("FALSE"),
// Transmitter is not held in reset
.EMAC_TXRESET ("FALSE"),
// Transmitter Jumbo frames are not enabled
.EMAC_TXJUMBOFRAME_ENABLE ("FALSE"),
// Transmitter in-band FCS is not enabled
.EMAC_TXINBANDFCS_ENABLE ("FALSE"),
// Transmitter is enabled
.EMAC_TX_ENABLE ("TRUE"),
// Transmitter VLAN frames are not enabled
.EMAC_TXVLAN_ENABLE ("FALSE"),
// Transmitter full-duplex mode is enabled
.EMAC_TXHALFDUPLEX ("FALSE"),
// Transmitter IFG Adjust is not enabled
.EMAC_TXIFGADJUST_ENABLE ("FALSE"),
// Receiver is not held in reset
.EMAC_RXRESET ("FALSE"),
// Receiver Jumbo frames are not enabled
.EMAC_RXJUMBOFRAME_ENABLE ("FALSE"),
// Receiver in-band FCS is not enabled
.EMAC_RXINBANDFCS_ENABLE ("FALSE"),
// Receiver is enabled
.EMAC_RX_ENABLE ("TRUE"),
// Receiver VLAN frames are not enabled
.EMAC_RXVLAN_ENABLE ("FALSE"),
// Receiver full-duplex mode is enabled
.EMAC_RXHALFDUPLEX ("FALSE"),
// Configure the EMAC addressing
// Set the PAUSE address default
.EMAC_PAUSEADDR (48'hFFEEDDCCBBAA),
// Do not set the unicast address (address filter is unused)
.EMAC_UNICASTADDR (48'h000000000000),
// Do not set the DCR base address (DCR is unused)
.EMAC_DCRBASEADDR (8'h00)
)
v6_emac
(
.RESET (RESET),
.EMACCLIENTRXCLIENTCLKOUT (EMACCLIENTRXCLIENTCLKOUT),
.CLIENTEMACRXCLIENTCLKIN (CLIENTEMACRXCLIENTCLKIN),
.EMACCLIENTRXD (client_rx_data_i),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (EMACCLIENTRXDVLDMSW),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
.EMACCLIENTTXCLIENTCLKOUT (EMACCLIENTTXCLIENTCLKOUT),
.CLIENTEMACTXCLIENTCLKIN (CLIENTEMACTXCLIENTCLKIN),
.CLIENTEMACTXD (client_tx_data_i),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (CLIENTEMACTXDVLDMSW),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
.PHYEMACGTXCLK (GTX_CLK),
.EMACPHYTXGMIIMIICLKOUT (EMACPHYTXGMIIMIICLKOUT),
.PHYEMACTXGMIIMIICLKIN (PHYEMACTXGMIIMIICLKIN),
.PHYEMACRXCLK (GMII_RX_CLK),
.PHYEMACRXD (GMII_RXD),
.PHYEMACRXDV (GMII_RX_DV),
.PHYEMACRXER (GMII_RX_ER),
.EMACPHYTXCLK (),
.EMACPHYTXD (GMII_TXD),
.EMACPHYTXEN (GMII_TX_EN),
.EMACPHYTXER (GMII_TX_ER),
.PHYEMACMIITXCLK (1'b0),
.PHYEMACCOL (1'b0),
.PHYEMACCRS (1'b0),
.CLIENTEMACDCMLOCKED (MMCM_LOCKED),
.EMACCLIENTANINTERRUPT (),
.PHYEMACSIGNALDET (1'b0),
.PHYEMACPHYAD (5'b00000),
.EMACPHYENCOMMAALIGN (),
.EMACPHYLOOPBACKMSB (),
.EMACPHYMGTRXRESET (),
.EMACPHYMGTTXRESET (),
.EMACPHYPOWERDOWN (),
.EMACPHYSYNCACQSTATUS (),
.PHYEMACRXCLKCORCNT (3'b000),
.PHYEMACRXBUFSTATUS (2'b00),
.PHYEMACRXCHARISCOMMA (1'b0),
.PHYEMACRXCHARISK (1'b0),
.PHYEMACRXDISPERR (1'b0),
.PHYEMACRXNOTINTABLE (1'b0),
.PHYEMACRXRUNDISP (1'b0),
.PHYEMACTXBUFERR (1'b0),
.EMACPHYTXCHARDISPMODE (),
.EMACPHYTXCHARDISPVAL (),
.EMACPHYTXCHARISK (),
.EMACPHYMCLKOUT (),
.PHYEMACMCLKIN (1'b0),
.PHYEMACMDIN (1'b1),
.EMACPHYMDOUT (),
.EMACPHYMDTRI (),
.EMACSPEEDIS10100 (),
.HOSTCLK (1'b0),
.HOSTOPCODE (2'b00),
.HOSTREQ (1'b0),
.HOSTMIIMSEL (1'b0),
.HOSTADDR (10'b0000000000),
.HOSTWRDATA (32'h00000000),
.HOSTMIIMRDY (),
.HOSTRDDATA (),
.DCREMACCLK (1'b0),
.DCREMACABUS (10'h000),
.DCREMACREAD (1'b0),
.DCREMACWRITE (1'b0),
.DCREMACDBUS (32'h00000000),
.EMACDCRACK (),
.EMACDCRDBUS (),
.DCREMACENABLE (1'b0),
.DCRHOSTDONEIR ()
);
endmodule
//----------------------------------------------------------------------
// Title : Gigabit Media Independent Interface (GMII) Physical I/F
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : gmii_if.v
// Version : 1.5
//-----------------------------------------------------------------------------
// Description: This module creates a Gigabit Media Independent
// Interface (GMII) by instantiating Input/Output buffers
// and Input/Output flip-flops as required.
//
// This interface is used to connect the Ethernet MAC to
// an external 1000Mb/s (or Tri-speed) Ethernet PHY.
//----------------------------------------------------------------------
`timescale 1 ps / 1 ps
module gmii_if (
RESET,
// GMII Interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
// MAC Interface
TXD_FROM_MAC,
TX_EN_FROM_MAC,
TX_ER_FROM_MAC,
TX_CLK,
RXD_TO_MAC,
RX_DV_TO_MAC,
RX_ER_TO_MAC,
RX_CLK
);
input RESET;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input [7:0] TXD_FROM_MAC;
input TX_EN_FROM_MAC;
input TX_ER_FROM_MAC;
input TX_CLK;
output [7:0] RXD_TO_MAC;
output RX_DV_TO_MAC;
output RX_ER_TO_MAC;
input RX_CLK;
reg [7:0] RXD_TO_MAC;
reg RX_DV_TO_MAC;
reg RX_ER_TO_MAC;
reg [7:0] GMII_TXD;
reg GMII_TX_EN;
reg GMII_TX_ER;
wire [7:0] GMII_RXD_DLY;
wire GMII_RX_DV_DLY;
wire GMII_RX_ER_DLY;
//------------------------------------------------------------------------
// GMII Transmitter Clock Management
//------------------------------------------------------------------------
// Instantiate a DDR output register. This is a good way to drive
// GMII_TX_CLK since the clock-to-pad delay will be the same as that for
// data driven from IOB Ouput flip-flops, eg. GMII_TXD[7:0].
ODDR gmii_tx_clk_oddr (
.Q (GMII_TX_CLK),
.C (TX_CLK),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (RESET),
.S (1'b0)
);
//------------------------------------------------------------------------
// GMII Transmitter Logic : Drive TX signals through IOBs onto the
// GMII interface
//------------------------------------------------------------------------
// Infer IOB Output flip-flops
always @(posedge TX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
GMII_TX_EN <= 1'b0;
GMII_TX_ER <= 1'b0;
GMII_TXD <= 8'h00;
end
else
begin
GMII_TX_EN <= TX_EN_FROM_MAC;
GMII_TX_ER <= TX_ER_FROM_MAC;
GMII_TXD <= TXD_FROM_MAC;
end
end
//------------------------------------------------------------------------
// Route GMII inputs through IODELAY blocks, using IDELAY function
//------------------------------------------------------------------------
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld0 (
.IDATAIN(GMII_RXD[0]),
.DATAOUT(GMII_RXD_DLY[0]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld1 (
.IDATAIN(GMII_RXD[1]),
.DATAOUT(GMII_RXD_DLY[1]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld2 (
.IDATAIN(GMII_RXD[2]),
.DATAOUT(GMII_RXD_DLY[2]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld3 (
.IDATAIN(GMII_RXD[3]),
.DATAOUT(GMII_RXD_DLY[3]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld4 (
.IDATAIN(GMII_RXD[4]),
.DATAOUT(GMII_RXD_DLY[4]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld5 (
.IDATAIN(GMII_RXD[5]),
.DATAOUT(GMII_RXD_DLY[5]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld6 (
.IDATAIN(GMII_RXD[6]),
.DATAOUT(GMII_RXD_DLY[6]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld7 (
.IDATAIN(GMII_RXD[7]),
.DATAOUT(GMII_RXD_DLY[7]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideldv(
.IDATAIN(GMII_RX_DV),
.DATAOUT(GMII_RX_DV_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideler(
.IDATAIN(GMII_RX_ER),
.DATAOUT(GMII_RX_ER_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
//------------------------------------------------------------------------
// GMII Receiver Logic : Receive RX signals through IOBs from the
// GMII interface
//------------------------------------------------------------------------
// Infer IOB Input flip-flops
always @(posedge RX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
RX_DV_TO_MAC <= 1'b0;
RX_ER_TO_MAC <= 1'b0;
RXD_TO_MAC <= 8'h00;
end
else
begin
RX_DV_TO_MAC <= GMII_RX_DV_DLY;
RX_ER_TO_MAC <= GMII_RX_ER_DLY;
RXD_TO_MAC <= GMII_RXD_DLY;
end
end
endmodule
|
//======================================================================
//
// chacha_qr.v
// -----------
// Verilog 2001 implementation of the stream cipher ChaCha.
// This is the combinational QR logic as a separade module to allow
// us to build versions of the cipher with 1, 2, 4 and even 8
// parallel qr functions.
//
//
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module chacha_qr(
input wire [31 : 0] a,
input wire [31 : 0] b,
input wire [31 : 0] c,
input wire [31 : 0] d,
output wire [31 : 0] a_prim,
output wire [31 : 0] b_prim,
output wire [31 : 0] c_prim,
output wire [31 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] internal_a_prim;
reg [31 : 0] internal_b_prim;
reg [31 : 0] internal_c_prim;
reg [31 : 0] internal_d_prim;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
//----------------------------------------------------------------
// qr
//
// The actual quarterround function.
//----------------------------------------------------------------
always @*
begin : qr
reg [31 : 0] a0;
reg [31 : 0] a1;
reg [31 : 0] b0;
reg [31 : 0] b1;
reg [31 : 0] b2;
reg [31 : 0] b3;
reg [31 : 0] c0;
reg [31 : 0] c1;
reg [31 : 0] d0;
reg [31 : 0] d1;
reg [31 : 0] d2;
reg [31 : 0] d3;
a0 = a + b;
d0 = d ^ a0;
d1 = {d0[15 : 0], d0[31 : 16]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[19 : 0], b0[31 : 20]};
a1 = a0 + b1;
d2 = d1 ^ a1;
d3 = {d2[23 : 0], d2[31 : 24]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[24 : 0], b2[31 : 25]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end // qr
endmodule // chacha_qr
//======================================================================
// EOF chacha_qr.v
//======================================================================
|
//----------------------------------------------------------------------------
// Copyright (C) 2011 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA Top-level for the DE0 Nano Soc
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
`include "openmsp430/openMSP430_defines.v"
module openMSP430_fpga (
//-----------------------------
// USER CLOCKS
//-----------------------------
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
//-----------------------------
// USER INTERFACE (FPGA)
//-----------------------------
input [1:0] KEY,
input [3:0] SW,
output [7:0] LED,
//-----------------------------
// GPIO
//-----------------------------
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
//-----------------------------
// ARDUINO DIGITAL INTERFACE
//-----------------------------
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
//-----------------------------
// ADC
//-----------------------------
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO
);
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
// openMSP430 Program memory bus
wire [`PMEM_MSB:0] pmem_addr;
wire [15:0] pmem_din;
wire pmem_cen;
wire [1:0] pmem_wen;
wire [15:0] pmem_dout;
// openMSP430 Data memory bus
wire [`DMEM_MSB:0] dmem_addr;
wire [15:0] dmem_din;
wire dmem_cen;
wire [1:0] dmem_wen;
wire [15:0] dmem_dout;
// openMSP430 Peripheral memory bus
wire [13:0] per_addr;
wire [15:0] per_din;
wire per_en;
wire [1:0] per_we;
wire [15:0] per_dout;
// openMSP430 IRQs
wire nmi;
wire [13:0] irq_bus;
wire [13:0] irq_acc;
// openMSP430 debug interface
wire dbg_freeze;
wire [6:0] dbg_i2c_addr;
wire [6:0] dbg_i2c_broadcast;
wire dbg_i2c_scl;
wire dbg_i2c_sda_in;
wire dbg_i2c_sda_out;
wire dbg_uart_txd;
wire dbg_uart_rxd;
// openMSP430 clocks and resets
wire dco_clk;
wire lfxt_clk;
wire aclk_en;
wire smclk_en;
wire mclk;
wire reset_n;
wire puc_rst;
// LED / KEY / SW
wire irq_key;
wire irq_sw;
wire [15:0] per_dout_led_key_sw;
// Timer A
wire irq_ta0;
wire irq_ta1;
wire [15:0] per_dout_tA;
// Graphic Controller
wire irq_gfx;
wire [15:0] per_dout_gfx;
wire [8:0] lut_ram_addr;
wire lut_ram_wen;
wire lut_ram_cen;
wire [15:0] lut_ram_din;
wire [15:0] lut_ram_dout;
wire [16:0] vid_ram_addr;
wire vid_ram_wen;
wire vid_ram_cen;
wire [15:0] vid_ram_din;
wire [15:0] vid_ram_dout;
// Touch-Screen Controller
wire irq_touch;
//=============================================================================
// 2) CLOCK AND RESET GENERATION
//=============================================================================
assign dco_clk = FPGA_CLK1_50;
wire reset_in_n = KEY[0];
// Release system reset a few clock cyles after the FPGA power-on-reset
reg [7:0] reset_dly_chain;
always @ (posedge dco_clk or negedge reset_in_n)
if (!reset_in_n) reset_dly_chain <= 8'h00;
else reset_dly_chain <= {1'b1, reset_dly_chain[7:1]};
assign reset_n = reset_dly_chain[0];
// Generate a slow reference clock LFXT_CLK (10us period)
reg [8:0] lfxt_clk_cnt;
always @ (posedge dco_clk or negedge reset_n)
if (!reset_n) lfxt_clk_cnt <= 9'h000;
else lfxt_clk_cnt <= lfxt_clk_cnt + 9'h001;
assign lfxt_clk = lfxt_clk_cnt[8];
//=============================================================================
// 3) OPENMSP430
//=============================================================================
openMSP430 openmsp430_0 (
// OUTPUTs
.aclk (), // ASIC ONLY: ACLK
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dco_enable (), // ASIC ONLY: Fast oscillator enable
.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
.mclk (mclk), // Main system clock
.dma_dout (), // Direct Memory Access data output
.dma_ready (), // Direct Memory Access is complete
.dma_resp (), // Direct Memory Access response (0:Okay / 1:Error)
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc_rst (puc_rst), // Main system reset
.smclk (), // ASIC ONLY: SMCLK
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
// INPUTs
.cpu_en (1'b1), // Enable CPU code execution (asynchronous and non-glitchy)
.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_bus), // Maskable interrupts
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.dma_addr (15'h0000), // Direct Memory Access address
.dma_din (16'h0000), // Direct Memory Access data input
.dma_en (1'b0), // Direct Memory Access enable (high active)
.dma_priority (1'b0), // Direct Memory Access priority (0:low / 1:high)
.dma_we (2'b00), // Direct Memory Access write byte enable (high active)
.dma_wkup (1'b0), // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
.scan_mode (1'b0), // ASIC ONLY: Scan mode
.wkup (1'b0) // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
);
//=============================================================================
// 4) OPENMSP430 PERIPHERALS
//=============================================================================
//-----------------------------
// LED / KEY / SW interface
//-----------------------------
omsp_de0_nano_soc_led_key_sw de0_nano_soc_led_key_sw_0 (
// OUTPUTs
.irq_key (irq_key), // Key/Button interrupt
.irq_sw (irq_sw), // Switch interrupt
.led (LED), // LED output control
.per_dout (per_dout_led_key_sw), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.key (KEY), // key/button inputs
.sw (SW), // switches inputs
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
//-----------------------------
// Timer A
//-----------------------------
omsp_timerA timerA_0 (
// OUTPUTs
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
.per_dout (per_dout_tA), // Peripheral data output
.ta_out0 (), // Timer A output 0
.ta_out0_en (), // Timer A output 0 enable
.ta_out1 (), // Timer A output 1
.ta_out1_en (), // Timer A output 1 enable
.ta_out2 (), // Timer A output 2
.ta_out2_en (), // Timer A output 2 enable
// INPUTs
.aclk_en (aclk_en), // ACLK enable (from CPU)
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
.inclk (1'b0), // INCLK external timer clock (SLOW)
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.ta_cci0a (1'b0), // Timer A capture 0 input A
.ta_cci0b (1'b0), // Timer A capture 0 input B
.ta_cci1a (1'b0), // Timer A capture 1 input A
.ta_cci1b (1'b0), // Timer A capture 1 input B
.ta_cci2a (1'b0), // Timer A capture 2 input A
.ta_cci2b (1'b0), // Timer A capture 2 input B
.taclk (1'b0) // TACLK external timer clock (SLOW)
);
//-------------------------------
// GRAPHIC CONTROLER
// (Interfacing with LT24 board)
//-------------------------------
// Bidirectional data bus
wire [15:0] lt24_data;
wire [15:0] lt24_d_out;
wire lt24_d_out_en;
io_buf io_buf_lt24_data_00 (.datain(lt24_d_out[0]), .oe(lt24_d_out_en), .dataout(lt24_data[0]), .dataio(GPIO_0[8]) );
io_buf io_buf_lt24_data_01 (.datain(lt24_d_out[1]), .oe(lt24_d_out_en), .dataout(lt24_data[1]), .dataio(GPIO_0[7]) );
io_buf io_buf_lt24_data_02 (.datain(lt24_d_out[2]), .oe(lt24_d_out_en), .dataout(lt24_data[2]), .dataio(GPIO_0[6]) );
io_buf io_buf_lt24_data_03 (.datain(lt24_d_out[3]), .oe(lt24_d_out_en), .dataout(lt24_data[3]), .dataio(GPIO_0[5]) );
io_buf io_buf_lt24_data_04 (.datain(lt24_d_out[4]), .oe(lt24_d_out_en), .dataout(lt24_data[4]), .dataio(GPIO_0[13]));
io_buf io_buf_lt24_data_05 (.datain(lt24_d_out[5]), .oe(lt24_d_out_en), .dataout(lt24_data[5]), .dataio(GPIO_0[14]));
io_buf io_buf_lt24_data_06 (.datain(lt24_d_out[6]), .oe(lt24_d_out_en), .dataout(lt24_data[6]), .dataio(GPIO_0[15]));
io_buf io_buf_lt24_data_07 (.datain(lt24_d_out[7]), .oe(lt24_d_out_en), .dataout(lt24_data[7]), .dataio(GPIO_0[16]));
io_buf io_buf_lt24_data_08 (.datain(lt24_d_out[8]), .oe(lt24_d_out_en), .dataout(lt24_data[8]), .dataio(GPIO_0[17]));
io_buf io_buf_lt24_data_09 (.datain(lt24_d_out[9]), .oe(lt24_d_out_en), .dataout(lt24_data[9]), .dataio(GPIO_0[18]));
io_buf io_buf_lt24_data_10 (.datain(lt24_d_out[10]), .oe(lt24_d_out_en), .dataout(lt24_data[10]), .dataio(GPIO_0[19]));
io_buf io_buf_lt24_data_11 (.datain(lt24_d_out[11]), .oe(lt24_d_out_en), .dataout(lt24_data[11]), .dataio(GPIO_0[20]));
io_buf io_buf_lt24_data_12 (.datain(lt24_d_out[12]), .oe(lt24_d_out_en), .dataout(lt24_data[12]), .dataio(GPIO_0[21]));
io_buf io_buf_lt24_data_13 (.datain(lt24_d_out[13]), .oe(lt24_d_out_en), .dataout(lt24_data[13]), .dataio(GPIO_0[22]));
io_buf io_buf_lt24_data_14 (.datain(lt24_d_out[14]), .oe(lt24_d_out_en), .dataout(lt24_data[14]), .dataio(GPIO_0[23]));
io_buf io_buf_lt24_data_15 (.datain(lt24_d_out[15]), .oe(lt24_d_out_en), .dataout(lt24_data[15]), .dataio(GPIO_0[24]));
openGFX430 #(.BASE_ADDR(16'h0200)) opengfx430_0 (
// OUTPUTs
.irq_gfx_o (irq_gfx), // Graphic Controller interrupt
.lt24_cs_n_o (GPIO_0[25]), // LT24 Chip select (Active low)
.lt24_rd_n_o (GPIO_0[10]), // LT24 Read strobe (Active low)
.lt24_wr_n_o (GPIO_0[11]), // LT24 Write strobe (Active low)
.lt24_rs_o (GPIO_0[12]), // LT24 Command/Param selection (Cmd=0/Param=1)
.lt24_d_o (lt24_d_out), // LT24 Data output
.lt24_d_en_o (lt24_d_out_en), // LT24 Data output enable
.lt24_reset_n_o (GPIO_0[33]), // LT24 Reset (Active Low)
.lt24_on_o (GPIO_0[35]), // LT24 on/off
.per_dout_o (per_dout_gfx), // Peripheral data output
.lut_ram_addr_o (lut_ram_addr), // LUT-RAM address
.lut_ram_wen_o (lut_ram_wen ), // LUT-RAM write enable (active low)
.lut_ram_cen_o (lut_ram_cen ), // LUT-RAM enable (active low)
.lut_ram_din_o (lut_ram_din ), // LUT-RAM data input
.vid_ram_addr_o (vid_ram_addr), // Video-RAM address
.vid_ram_wen_o (vid_ram_wen ), // Video-RAM write enable (active low)
.vid_ram_cen_o (vid_ram_cen ), // Video-RAM enable (active low)
.vid_ram_din_o (vid_ram_din ), // Video-RAM data input
// INPUTs
.dbg_freeze_i (dbg_freeze), // Freeze address auto-incr on read
.mclk (mclk), // Main system clock
.per_addr_i (per_addr), // Peripheral address
.per_din_i (per_din), // Peripheral data input
.per_en_i (per_en), // Peripheral enable (high active)
.per_we_i (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.lt24_d_i (lt24_data), // LT24 Data input
.lut_ram_dout_i (lut_ram_dout), // LUT-RAM data output
.vid_ram_dout_i (vid_ram_dout) // Video-RAM data output
);
// Video memory
ram_16x75k vid_ram_16x75k_0 (
.address ( vid_ram_addr),
.byteena (~{2{vid_ram_wen}}),
.clken (~vid_ram_cen),
.clock ( mclk),
.data ( vid_ram_din),
.wren (~vid_ram_wen),
.q ( vid_ram_dout)
);
// LUT memory
ram_16x512 lut_ram_16x512_0 (
.address ( lut_ram_addr),
.byteena (~{2{lut_ram_wen}}),
.clken (~lut_ram_cen),
.clock ( mclk),
.data ( lut_ram_din),
.wren (~lut_ram_wen),
.q ( lut_ram_dout)
);
assign GPIO_0[34] = 1'b1; // .adc_cs_n (GPIO_0[34]), // ADC Chip select (Active low)
assign GPIO_0[4] = 1'b0; // .adc_dclk (GPIO_0[4]), // ADC Clock
assign GPIO_0[3] = 1'b0; // .adc_din (GPIO_0[3]), // ADC Data input
assign irq_touch = 1'b0; //
// .adc_busy (GPIO_0[2]), // ADC Busy output
// .adc_dount (GPIO_0[1]), // ADC Data output
// .adc_penirq_n (GPIO_0[0]), // Pen IRQ from touch controller
//-----------------------------
// Combine peripheral
// data buses
//-----------------------------
assign per_dout = per_dout_led_key_sw |
per_dout_tA |
per_dout_gfx;
//-----------------------------
// Assign interrupts
//-----------------------------
assign nmi = 1'b0;
assign irq_bus = {1'b0, // Vector 13 (0xFFFA)
1'b0, // Vector 12 (0xFFF8)
1'b0, // Vector 11 (0xFFF6)
1'b0, // Vector 10 (0xFFF4) - Watchdog -
irq_ta0, // Vector 9 (0xFFF2)
irq_ta1, // Vector 8 (0xFFF0)
1'b0, // Vector 7 (0xFFEE)
irq_gfx, // Vector 6 (0xFFEC)
irq_touch, // Vector 5 (0xFFEA)
1'b0, // Vector 4 (0xFFE8)
irq_key, // Vector 3 (0xFFE6)
irq_sw, // Vector 2 (0xFFE4)
1'b0, // Vector 1 (0xFFE2)
1'b0}; // Vector 0 (0xFFE0)
//=============================================================================
// 5) PROGRAM AND DATA MEMORIES
//=============================================================================
ram_16x16k pmem_0 (
.address ( pmem_addr),
.byteena (~pmem_wen),
.clken (~pmem_cen),
.clock ( mclk),
.data ( pmem_din),
.wren (~(&pmem_wen)),
.q ( pmem_dout)
);
ram_16x8k dmem_0 (
.address ( dmem_addr),
.byteena (~dmem_wen),
.clken (~dmem_cen),
.clock ( mclk),
.data ( dmem_din),
.wren (~(&dmem_wen)),
.q ( dmem_dout)
);
//=============================================================================
// 6) DEBUG INTERFACE
//=============================================================================
assign dbg_i2c_addr = 7'd50;
assign dbg_i2c_broadcast = 7'd49;
assign dbg_i2c_scl = ARDUINO_IO[15];
io_buf io_buf_sda_0 (.datain(1'b0), .oe(~dbg_i2c_sda_out), .dataout(dbg_i2c_sda_in), .dataio(ARDUINO_IO[14]));
assign dbg_uart_rxd = 1'b0;
// Unused stuff
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
assign ARDUINO_IO[13:0] = 14'hzzzz;
assign ARDUINO_RESET_N = 1'hz;
assign ADC_CONVST = 1'hz;
assign ADC_SCK = 1'hz;
assign ADC_SDI = 1'hz;
endmodule
|
/*
###########################################################################
# **EMMU**
#
# This block uses the upper 12 bits [31:20] of a memory address as an index
# to read an entry from a table.
#
# The table is written from the mi_* configuration interface.
#
# The table can be configured as 12 bits wide or 44 bits wide.
#
# 32bit address output = {table_data[11:0],dstaddr[19:0]}
# 64bit address output = {table_data[43:0],dstaddr[19:0]}
#
############################################################################
*/
module emmu (/*AUTOARG*/
// Outputs
mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out,
// Inputs
reset, rd_clk, wr_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr,
mi_din, emesh_access_in, emesh_packet_in, emesh_rd_wait,
emesh_wr_wait
);
parameter DW = 32; //data width
parameter AW = 32; //address width
parameter PW = 104;
parameter EPW = 136; //extended by 32 bits
parameter MW = 48; //width of table
parameter MAW = 12; //memory addres width (entries = 1<<MAW)
parameter GROUP = 0;
/*****************************/
/*DATAPATH CLOCk */
/*****************************/
input reset;
input rd_clk;
input wr_clk;
/*****************************/
/*MMU LOOKUP DATA */
/*****************************/
input mmu_en; //enables mmu (static)
input mmu_bp; //bypass mmu on read response
/*****************************/
/*Register Access Interface */
/*****************************/
input mi_en; //memory access
input mi_we; //byte wise write enable
input [14:0] mi_addr; //address
input [DW-1:0] mi_din; //input data
output [DW-1:0] mi_dout; //read back (TODO?? not implemented)
/*****************************/
/*EMESH INPUTS */
/*****************************/
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
input emesh_rd_wait;
input emesh_wr_wait;
/*****************************/
/*EMESH OUTPUTS */
/*****************************/
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
output [31:0] emesh_packet_hi_out;
/*****************************/
/*REGISTERS */
/*****************************/
reg emesh_access_out;
reg [PW-1:0] emesh_packet_reg;
wire [63:0] emesh_dstaddr_out;
wire [MW-1:0] emmu_lookup_data;
wire [63:0] mi_wr_data;
wire [5:0] mi_wr_vec;
wire mi_match;
wire [MW-1:0] emmu_rd_addr;
wire write_in;
/*****************************/
/*MMU WRITE LOGIC */
/*****************************/
//write controls
assign mi_wr_vec[5:0] = (mi_en & mi_we & ~mi_addr[2]) ? 6'b001111 :
(mi_en & mi_we & mi_addr[2]) ? 6'b110000 :
6'b000000 ;
//write data
assign mi_wr_data[63:0] = {mi_din[31:0], mi_din[31:0]};
//todo: implement readback? worth it?
assign mi_dout[DW-1:0] = 'b0;
/*****************************/
/*MMU READ LOGIC */
/*****************************/
//TODO: could we do with less entries?
assign write_in = emesh_packet_in[1];
assign emmu_rd_addr[MAW-1:0] = emesh_packet_in[39:28];
memory_dp #(.DW(MW),.AW(MAW)) memory_dp (
// Outputs
.rd_data (emmu_lookup_data[MW-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_en (mi_wr_vec[5:0]),
.wr_addr (mi_addr[14:3]),
.wr_data (mi_wr_data[MW-1:0]),
.rd_clk (rd_clk),
.rd_en (emesh_access_in),
.rd_addr (emmu_rd_addr[MAW-1:0])
);
/*****************************/
/*EMESH OUTPUT TRANSACTION */
/*****************************/
//pipeline to compensate for table lookup pipeline
//assumes one cycle memory access!
always @ (posedge rd_clk)
if (reset)
begin
emesh_access_out <= 1'b0;
end
else if((write_in & ~emesh_wr_wait) | (~write_in & ~emesh_rd_wait))
begin
emesh_access_out <= emesh_access_in;
emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];
end
assign emesh_dstaddr_out[63:0] = (mmu_en & ~mmu_bp) ? {emmu_lookup_data[43:0], emesh_packet_reg[27:8]} :
{32'b0,emesh_packet_reg[39:8]};
//Concatenating output packet
assign emesh_packet_out[PW-1:0] = {emesh_packet_reg[PW-1:40],
emesh_dstaddr_out[31:0],
emesh_packet_reg[7:0]
};
assign emesh_packet_hi_out[31:0] = emesh_dstaddr_out[63:32];
endmodule // emmu
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../memory/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: ff_40x32_fwft_async.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ff_40x32_fwft_async (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [39:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [39:0] q;
output rdempty;
output [4:0] rdusedw;
output wrfull;
output [4:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [39:0] sub_wire1;
wire sub_wire2;
wire [4:0] sub_wire3;
wire [4:0] sub_wire4;
wire wrfull = sub_wire0;
wire [39:0] q = sub_wire1[39:0];
wire rdempty = sub_wire2;
wire [4:0] wrusedw = sub_wire3[4:0];
wire [4:0] rdusedw = sub_wire4[4:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdusedw (sub_wire4),
.rdfull (),
.wrempty ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
dcfifo_component.lpm_numwords = 32,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 40,
dcfifo_component.lpm_widthu = 5,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "40"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "40"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "40"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 40 0 INPUT NODEFVAL "data[39..0]"
// Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 5 0 OUTPUT NODEFVAL "rdusedw[4..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL "wrusedw[4..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 40 0 data 0 0 40 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 40 0 @q 0 0 40 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 5 0 @rdusedw 0 0 5 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_async.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_async.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_async.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_async.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_async_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_async_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_TB_V
`define SKY130_FD_SC_HDLL__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_TB_V
|
`timescale 1ns / 1ps
module MainActivity
(
input [7:0] estado,
input [7:0]RG1_P,
input [7:0]RG2_P,
input [7:0]RG3_P,
input escribiendo,
input en_out,
input [3:0] dig0, dig1,
input [3:0] direccion,
input clk, reset, off_alarma,on_alarma,//clock signal 100M
output [7:0] COLOUR_OUT,//bit patters for colour that goes to VGA port
output HS, //Horizontal Synch signal that goes into VGA port
output VS, //Vertical Synch signal that goes into VGA port7
output [7:0] seg_Ti,
output [7:0] min_Ti,
output [7:0] hor_Ti
);
reg DOWNCOUNTER = 0;
reg [7:0] COLOUR_IN, COLOUR_IN_co, COLOUR_IN_fe, COLOUR_IN_re, COLOUR_IN_cr;
reg en_conf, en_fecha, en_reloj, en_crono;
wire [31:0] STATE1,STATE2, STATE3, STATE4;
wire TrigRefresh; //Trigger gives a pulse when displayed refreshed
wire [9:0] ADDRH; //wire for getting Horizontal pixel value
wire [8:0] ADDRV; //wire for getting vertical pixel value
// signal declaration
//reg [1:0] state_reg, state_next;
wire CLK;
wire [8:0] text_on;
wire [2:0] text_rgb;
wire [3:0] RG1_Unit;
wire [3:0] RG2_Unit;
wire [3:0] RG3_Unit;
wire [3:0] RG1_Dec;
wire [3:0] RG2_Dec;
wire [3:0] RG3_Dec;
assign RG1_Unit= RG1_P[3:0];
assign RG2_Unit= RG2_P[3:0];
assign RG3_Unit= RG3_P[3:0];
assign RG1_Dec= RG1_P[7:4];
assign RG2_Dec= RG2_P[7:4];
assign RG3_Dec= RG3_P[7:4];
clk_div clk_div (
.clk(clk),
.out_clk(CLK)
);
//Divisor a 25MHz
always @(posedge CLK)begin
DOWNCOUNTER <= ~DOWNCOUNTER; //Slow down the counter to 25MHz
end
//VGA Interface gets values of ADDRH & ADDRV and by puting COLOUR_IN, gets valid output COLOUR_OUT
VGAInterface VGA(
.CLK(DOWNCOUNTER),
.COLOUR_IN (COLOUR_IN),
.COLOUR_OUT(COLOUR_OUT),
.HS(HS),
.VS(VS),
.REFRESH(TrigRefresh),
.ADDRH(ADDRH),
.ADDRV(ADDRV),
.DOWNCOUNTER(DOWNCOUNTER)
);
VGA_text text_unit
(
.estado(estado),
.RG1_Unit(RG1_Unit),
.RG2_Unit(RG2_Unit),
.RG3_Unit(RG3_Unit),
.RG1_Dec(RG1_Dec),
.RG2_Dec(RG2_Dec),
.RG3_Dec(RG3_Dec),
.escribiendo(escribiendo),
.en_out(en_out),
.CLK(DOWNCOUNTER), .off_alarma(off_alarma), .on_alarma(on_alarma), .direccion(direccion),
.dig0_Dec(dig0), .dig1_Unit(dig1),
.pix_x(ADDRH), .pix_y(ADDRV),
.text_on(text_on),
.text_rgb(text_rgb),
.seg_Ti(seg_Ti),
.min_Ti(min_Ti),
.hor_Ti(hor_Ti)
);
//------DATO-FECHA-------------------------------------------------------------------------------------
//-------------------COLOCACION DE IMAGENES-----------------------------------------------------
//------INFORMACIÓN DE CONFIGURACIÓN------------------------------------------------------------
localparam Xc = 360;
localparam Yc = 30;
reg [7:0] COLOUR_DATA [0:configuracion2-1];
parameter configuracion2 = 16'd46872;
parameter configuracion2X = 8'd248;
parameter configuracion2Y = 8'd189;
initial
$readmemh ("Instrucciones.png.list", COLOUR_DATA);
assign STATE1 = ((ADDRH-Xc)*configuracion2Y)+ADDRV-Yc;
always @(posedge CLK) begin
if (ADDRH>=Xc && ADDRH<Xc +configuracion2X
&& ADDRV>=Yc && ADDRV<Yc+configuracion2Y)
begin
COLOUR_IN_co <= COLOUR_DATA[{STATE1}];
en_conf<=1;
end
else
begin
COLOUR_IN_co <= 8'hFF;
en_conf<=0;
end
end
//------------------------------------------------------------------------------------------------
//------TITULO-FECHA-------------------------------------------------------------------------------------
localparam Xf = 0;
localparam Yf = 45;
reg [7:0] COLOUR_DATA_f [0:fecha-1];
parameter fecha = 13'd3936;
parameter fechaX = 7'd123;
parameter fechaY = 6'd32;
initial
$readmemh ("Fecha.png.list", COLOUR_DATA_f);
assign STATE2 = ((ADDRH-Xf)*fechaY)+ADDRV-Yf;
always @(posedge CLK) begin
if (ADDRH>=Xf && ADDRH<Xf+fechaX
&& ADDRV>=Yf && ADDRV<Yf+fechaY)
begin
COLOUR_IN_fe <= COLOUR_DATA_f[{STATE2}];
en_fecha<=1;
end
else
begin
COLOUR_IN_fe <= 8'hFF;
en_fecha<=0;
end
end
//------------------------------------------------------------------------------------------------
//------TITULO-RELOJ-------------------------------------------------------------------------------------
localparam Xr = 0;
localparam Yr = 166;
reg [7:0] COLOUR_DATA_r [0:reloj-1];
parameter reloj = 13'd4446;
parameter relojX = 7'd114;
parameter relojY = 6'd39;
initial
$readmemh ("Hora.png.list", COLOUR_DATA_r);
assign STATE3 = ((ADDRH-Xr)*relojY)+ADDRV-Yr;
always @(posedge CLK) begin
if (ADDRH>=Xr && ADDRH<Xr+relojX
&& ADDRV>=Yr && ADDRV<Yr+relojY)
begin
COLOUR_IN_re <= COLOUR_DATA_r[{STATE3}];
en_reloj<=1;
end
else
begin
COLOUR_IN_re <= 8'hFF;
en_reloj<=0;
end
end
//------------------------------------------------------------------------------------------------
//------TITULO-CRONOMETRO-------------------------------------------------------------------------------------
localparam Xcr = 0;
localparam Ycr = 286;
reg [7:0] COLOUR_DATA_cr [0:cronometro-1];
parameter cronometro = 14'd9102;
parameter cronometroX = 8'd222;
parameter cronometroY = 6'd41;
initial
$readmemh ("Cronometro.png.list", COLOUR_DATA_cr);
assign STATE4 = ((ADDRH-Xcr)*cronometroY)+ADDRV-Ycr;
always @(posedge CLK) begin
if (ADDRH>=Xcr && ADDRH<Xcr+cronometroX
&& ADDRV>=Ycr && ADDRV<Ycr+cronometroY)
begin
COLOUR_IN_cr <= COLOUR_DATA_cr[{STATE4}];
en_crono<=1;
end
else
begin
COLOUR_IN_cr <= 8'hFF;
en_crono<=0;
end
end
//------------------------------------------------------------------------------------------------
wire [7:0]color;
assign color={text_rgb[2],text_rgb[2],text_rgb[1],text_rgb[1],text_rgb[1],text_rgb[0],text_rgb[0],text_rgb[0]};
//--------MUX------------------------------------------------------------------------------------
always @ (posedge DOWNCOUNTER )
begin
if (text_on[2])
COLOUR_IN<=color;
else if (text_on[4])
COLOUR_IN<=color;
else if (text_on[3])
COLOUR_IN<=color;
else if (text_on[3])
COLOUR_IN<=color;
else if (en_fecha)
COLOUR_IN<=COLOUR_IN_fe;
else if (en_reloj)
COLOUR_IN<=COLOUR_IN_re;
else if (en_crono)
COLOUR_IN<=COLOUR_IN_cr;
else if (en_conf)
begin
COLOUR_IN<=COLOUR_IN_co;
end
else
COLOUR_IN<=COLOUR_IN;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_dmul_64ns_64ns_64_6_max_dsp
#(parameter
ID = 13,
NUM_STAGE = 6,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
HLS_accel_ap_dmul_4_max_dsp_64 HLS_accel_ap_dmul_4_max_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Hasan Hassan
//
// Create Date: 08/18/2015 09:16:16 PM
// Design Name:
// Module Name: pcie_data_receiver
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "riffa.vh"
//Gets data from RIFFA and informs the Scheduler about data waiting to be processed
module pcie_data_receiver #(parameter C_PCI_DATA_WIDTH = 128) (
input clk,
input rst,
//RIFFA Interface
input CHNL_RX,
output reg CHNL_RX_ACK,
output CHNL_RX_DATA_REN,
input CHNL_RX_DATA_VALID,
input[C_PCI_DATA_WIDTH - 1:0] CHNL_RX_DATA,
input[`SIG_CHNL_LENGTH_W - 1:0] CHNL_RX_LEN,
//Scheduler Interface
input dna_rd_en,
output[C_PCI_DATA_WIDTH - 1:0] dna_data, //TODO: consider separate pci and dna data widths
output[C_PCI_DATA_WIDTH - 1:0] dna_data_ref,
output dna_valid,
//Sender Interface
output reg[`SIG_CHNL_LENGTH_W - 1:0] dna_len,
input sender_ready,
output reg sender_en
);
reg[C_PCI_DATA_WIDTH - 1:0] dna_r, dna_ref_r;
//reg dna_valid_r = 0;
reg[1:0] state = 0, state_next;
localparam STATE_IDLE = 2'b00;
localparam STATE_FETCH_REF = 2'b01;
localparam STATE_PROCESSING = 2'b10;
wire recv_fifo_full, recv_fifo_empty;
reg recv_fifo_wren = 1'b0;
//assign CHNL_RX_ACK = ~recv_fifo_full;
assign CHNL_RX_DATA_REN = (state != STATE_IDLE);
//next state combinational logic
always@* begin
CHNL_RX_ACK = 1'b0;
state_next = state;
case(state)
STATE_IDLE: begin
//accept the transaction if the sender is ready
if(sender_ready & CHNL_RX) begin
state_next = STATE_FETCH_REF;
CHNL_RX_ACK = 1'b1;
end
end //STATE_IDLE
STATE_FETCH_REF: begin
if(CHNL_RX_DATA_VALID) begin
state_next <= STATE_PROCESSING;
end
end //STATE_FETCH_REF
STATE_PROCESSING: begin
if(CHNL_RX_DATA_VALID) begin
if(dna_len == 1) begin
state_next = STATE_IDLE;
end
end
end //STATE_PROCESSING
endcase
end
//next state sequential logic
always@(posedge clk) begin
if(rst) begin
state <= STATE_IDLE;
end
else begin
state <= state_next;
end
end
//calculate the length of the mapping and keep track of received data
always@(posedge clk) begin
if(rst) begin
dna_len <= 0;
sender_en <= 1'b0;
end
else begin
sender_en <= 1'b0;
if(CHNL_RX_ACK) begin
dna_len <= CHNL_RX_LEN >> 2; //the first 4 words (16 bytes) are the reference dna data
sender_en <= 1'b1;
end
else begin
if(CHNL_RX_DATA_VALID) begin
dna_len <= dna_len - 1;
end
end
end
end
//save the refrence dna data
always@(posedge clk) begin
if(rst) begin
dna_ref_r <= 0;
dna_r <= 0;
end
else begin
if(CHNL_RX_DATA_VALID) begin
case(state)
STATE_FETCH_REF: begin
dna_ref_r <= CHNL_RX_DATA;
end
STATE_PROCESSING: begin
dna_r <= CHNL_RX_DATA;
recv_fifo_wren <= 1'b1;
end
endcase
end
end
end
/*always@(posedge clk) begin
if(rst) begin
dna_valid_r <= 1'b0;
dna_r <= 0;
dna_ref_r <= 0;
recv_fifo_wren <= 1'b0;
state <= STATE_IDLE;
end
else begin
recv_fifo_wren <= 1'b0;
if(~recv_fifo_full) begin
case(state)
STATE_IDLE: begin
if(sender_ready) begin
end
if(CHNL_RX_DATA_VALID) begin
state <= S_DATA_REF;
dna_r <= CHNL_RX_DATA;
end
end //S_DATA
S_DATA_REF: begin
if(CHNL_RX_DATA_VALID) begin
state <= S_DATA;
dna_ref_r <= CHNL_RX_DATA;
recv_fifo_wren <= 1'b1;
end
end //S_DATA_REF
endcase
end
end
end*/
/*always@(posedge clk) begin
if(rst) begin
dna_len <= 0;
end
else begin
if(CHNL_RX) begin
dna_len <= CHNL_RX_LEN >> 5;
end
end
end*/
pcie_recv_fifo i_recv_fifo(
.clk(clk), // input wire clk
.srst(rst), // input wire srst
.din({dna_r, dna_ref_r}), // input wire [255 : 0] din
.wr_en(recv_fifo_wren), // input wire wr_en
.rd_en(dna_rd_en), // input wire rd_en
.dout({dna_data, dna_data_ref}), // output wire [255 : 0] dout
.full(recv_fifo_full), // output wire full
.empty(recv_fifo_empty) // output wire empty
);
assign dna_valid = ~recv_fifo_empty;
endmodule
|
/**
* bsg_cache_dma_to_wormhole.v
*
* This module interfaces bsg_cache_dma to a wormhole link.
* dma_pkts come in two flavors:
* - Write packets send a wormhole header flit, then an address flit, then N data flits (the
* evicted data)
* - Read packets send a womrhole header flit, then an address flit, then recieve
* N data flits (the fill data) asynchronously.
*/
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
`include "bsg_cache.vh"
// TODO: Should be part of basejump stl
`include "bp_me_cache_defines.svh"
module bsg_cache_dma_to_wormhole
import bsg_noc_pkg::*;
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(dma_addr_width_p) // cache addr width (byte addr)
, parameter `BSG_INV_PARAM(dma_burst_len_p) // num of data beats in dma transfer
// flit width should match the cache dma width.
, parameter `BSG_INV_PARAM(wh_flit_width_p)
, parameter `BSG_INV_PARAM(wh_cid_width_p)
, parameter `BSG_INV_PARAM(wh_len_width_p)
, parameter `BSG_INV_PARAM(wh_cord_width_p)
, parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(dma_addr_width_p)
, parameter wh_link_sif_width_lp=`bsg_ready_and_link_sif_width(wh_flit_width_p)
, parameter dma_data_width_lp=wh_flit_width_p
// Whether to buffer the returning data flits. May be necessary for timing purposes
, parameter buffer_return_p = 1
)
(
input clk_i
, input reset_i
, input [dma_pkt_width_lp-1:0] dma_pkt_i
, input dma_pkt_v_i
, output dma_pkt_yumi_o
, output logic [dma_data_width_lp-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_ready_and_i
, input [dma_data_width_lp-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_yumi_o
, input [wh_link_sif_width_lp-1:0] wh_link_sif_i
, output logic [wh_link_sif_width_lp-1:0] wh_link_sif_o
, input [wh_cord_width_p-1:0] my_wh_cord_i
, input [wh_cord_width_p-1:0] dest_wh_cord_i
, input [wh_cid_width_p-1:0] my_wh_cid_i
, input [wh_cid_width_p-1:0] dest_wh_cid_i
);
`declare_bsg_cache_dma_pkt_s(dma_addr_width_p);
`declare_bsg_ready_and_link_sif_s(wh_flit_width_p, wh_link_sif_s);
wh_link_sif_s wh_link_sif_in;
wh_link_sif_s wh_link_sif_out;
assign wh_link_sif_in = wh_link_sif_i;
assign wh_link_sif_o = wh_link_sif_out;
// dma pkt fifo
logic dma_pkt_ready_lo;
logic dma_pkt_v_lo;
logic dma_pkt_yumi_li;
bsg_cache_dma_pkt_s dma_pkt_lo;
// two fifo is needed here to avoid bubble between consecutive dma_pkts,
// which can occur with during a writeback->fill operation
bsg_two_fifo #(
.width_p(dma_pkt_width_lp)
) dma_pkt_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(dma_pkt_v_i)
,.data_i(dma_pkt_i)
,.ready_o(dma_pkt_ready_lo)
,.v_o(dma_pkt_v_lo)
,.data_o(dma_pkt_lo)
,.yumi_i(dma_pkt_yumi_li)
);
assign dma_pkt_yumi_o = dma_pkt_ready_lo & dma_pkt_v_i;
// FIFO for wormhole flits coming back to vcache.
logic return_fifo_v_lo;
logic [wh_flit_width_p-1:0] return_fifo_data_lo;
logic return_fifo_ready_li, return_fifo_yumi_li;
if (buffer_return_p) begin : br
bsg_two_fifo #(
.width_p(wh_flit_width_p)
) return_fifo (
.clk_i (clk_i)
,.reset_i (reset_i)
,.v_i (wh_link_sif_in.v)
,.data_i (wh_link_sif_in.data)
,.ready_o (wh_link_sif_out.ready_and_rev)
,.v_o (return_fifo_v_lo)
,.data_o (return_fifo_data_lo)
,.yumi_i (return_fifo_yumi_li)
);
assign return_fifo_yumi_li = return_fifo_ready_li & return_fifo_v_lo;
end else begin : nbr
assign return_fifo_v_lo = wh_link_sif_in.v;
assign return_fifo_data_lo = wh_link_sif_in.data;
assign wh_link_sif_out.ready_and_rev = return_fifo_ready_li;
assign return_fifo_yumi_li = wh_link_sif_out.ready_and_rev & wh_link_sif_in.v;
end
// counter
localparam count_width_lp = `BSG_SAFE_CLOG2(dma_burst_len_p);
logic send_clear_li;
logic send_up_li;
logic [count_width_lp-1:0] send_count_lo;
bsg_counter_clear_up #(
.max_val_p(dma_burst_len_p-1)
,.init_val_p(0)
) send_count (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(send_clear_li)
,.up_i(send_up_li)
,.count_o(send_count_lo)
);
// send FSM
enum logic [1:0] {
SEND_RESET
, SEND_READY
, SEND_ADDR
, SEND_DATA
} send_state_n, send_state_r;
`declare_bsg_cache_wh_header_flit_s(wh_flit_width_p,wh_cord_width_p,wh_len_width_p,wh_cid_width_p);
bsg_cache_wh_header_flit_s header_flit;
assign header_flit.unused = '0;
assign header_flit.write_not_read = dma_pkt_lo.write_not_read;
assign header_flit.src_cid = my_wh_cid_i;
assign header_flit.src_cord = my_wh_cord_i;
assign header_flit.len = dma_pkt_lo.write_not_read
? wh_len_width_p'(1+dma_burst_len_p) // header + addr + data
: wh_len_width_p'(1); // header + addr
assign header_flit.cord = dest_wh_cord_i;
assign header_flit.cid = dest_wh_cid_i;
always_comb begin
send_state_n = send_state_r;
dma_pkt_yumi_li = 1'b0;
send_clear_li = 1'b0;
send_up_li = 1'b0;
wh_link_sif_out.v = 1'b0;
wh_link_sif_out.data = dma_data_i;
dma_data_yumi_o = 1'b0;
case (send_state_r)
SEND_RESET: begin
send_state_n = SEND_READY;
end
SEND_READY: begin
wh_link_sif_out.data = header_flit;
if (dma_pkt_v_lo) begin
wh_link_sif_out.v = 1'b1;
send_state_n = (wh_link_sif_in.ready_and_rev & wh_link_sif_out.v)
? SEND_ADDR
: SEND_READY;
end
end
SEND_ADDR: begin
wh_link_sif_out.data = wh_flit_width_p'(dma_pkt_lo.addr);
if (dma_pkt_v_lo) begin
wh_link_sif_out.v = 1'b1;
dma_pkt_yumi_li = wh_link_sif_in.ready_and_rev & wh_link_sif_out.v;
send_state_n = dma_pkt_yumi_li
? (dma_pkt_lo.write_not_read ? SEND_DATA : SEND_READY)
: SEND_ADDR;
end
end
SEND_DATA: begin
wh_link_sif_out.data = dma_data_i;
if (dma_data_v_i) begin
wh_link_sif_out.v = 1'b1;
dma_data_yumi_o = wh_link_sif_in.ready_and_rev & wh_link_sif_out.v;
send_up_li = dma_data_yumi_o & (send_count_lo != dma_burst_len_p-1);
send_clear_li = dma_data_yumi_o & (send_count_lo == dma_burst_len_p-1);
send_state_n = send_clear_li
? SEND_READY
: SEND_DATA;
end
end
// should never happen
default: begin
send_state_n = SEND_READY;
end
endcase
end
// receiver FSM
logic recv_clear_li;
logic recv_up_li;
logic [count_width_lp-1:0] recv_count_lo;
bsg_counter_clear_up #(
.max_val_p(dma_burst_len_p-1)
,.init_val_p(0)
) recv_count (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(recv_clear_li)
,.up_i(recv_up_li)
,.count_o(recv_count_lo)
);
typedef enum logic [1:0] {
RECV_RESET
, RECV_READY
, RECV_DATA
} recv_state_e;
recv_state_e recv_state_r, recv_state_n;
always_comb begin
recv_state_n = recv_state_r;
recv_clear_li = 1'b0;
recv_up_li = 1'b0;
return_fifo_ready_li = 1'b0;
dma_data_v_o = 1'b0;
dma_data_o = return_fifo_data_lo;
case (recv_state_r)
RECV_RESET: begin
recv_state_n = RECV_READY;
end
RECV_READY: begin
return_fifo_ready_li = 1'b1;
recv_state_n = return_fifo_yumi_li
? RECV_DATA
: RECV_READY;
end
RECV_DATA: begin
return_fifo_ready_li = dma_data_ready_and_i;
dma_data_v_o = return_fifo_v_lo;
recv_up_li = return_fifo_yumi_li & (recv_count_lo != dma_burst_len_p-1);
recv_clear_li = return_fifo_yumi_li & (recv_count_lo == dma_burst_len_p-1);
recv_state_n = recv_clear_li
? RECV_READY
: RECV_DATA;
end
default: begin
recv_state_n = RECV_READY;
end
endcase
end
// sequential logic
always_ff @ (posedge clk_i) begin
if (reset_i) begin
send_state_r <= SEND_RESET;
recv_state_r <= RECV_RESET;
end
else begin
send_state_r <= send_state_n;
recv_state_r <= recv_state_n;
end
end
//synopsys translate_off
if (wh_flit_width_p != dma_data_width_lp)
$error("WH flit width must be equal to DMA data width");
if (wh_flit_width_p < dma_addr_width_p)
$error("WH flit width must be larger than address width");
if (wh_len_width_p < `BSG_WIDTH(dma_burst_len_p+1))
$error("WH len width %d must be large enough to hold the dma transfer size %d", wh_len_width_p, `BSG_WIDTH(dma_burst_len_p+1));
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_dma_to_wormhole)
|
module crc_gen (
input Reset,
input Clk,
input Init,
input [7:0] Frame_data,
input Data_en,
input CRC_rd,
output [31:0] CRC_out,
output reg CRC_end
);
reg [31:0] CRC_reg;
reg [3:0] Counter;
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
always @ ( negedge Clk )
if (Reset)
CRC_reg <= 32'hffffffff;
else
CRC_reg <= Init ? 32'hffffffff : Data_en ? NextCRC(Frame_data, CRC_reg ) : CRC_reg;
assign CRC_out = ~{ CRC_reg[24],CRC_reg[25],CRC_reg[26],CRC_reg[27],CRC_reg[28],CRC_reg[29],CRC_reg[30],CRC_reg[31], CRC_reg[16],CRC_reg[17],CRC_reg[18],CRC_reg[19],CRC_reg[20],CRC_reg[21],CRC_reg[22],CRC_reg[23], CRC_reg[ 8],CRC_reg[ 9],CRC_reg[10],CRC_reg[11],CRC_reg[12],CRC_reg[13],CRC_reg[14],CRC_reg[15], CRC_reg[ 0],CRC_reg[ 1],CRC_reg[ 2],CRC_reg[ 3],CRC_reg[ 4],CRC_reg[ 5],CRC_reg[ 6],CRC_reg[ 7] };
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_BLACKBOX_V
`define SKY130_FD_SC_HVL__AND2_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SRDLXTP_FUNCTIONAL_V
/**
* srdlxtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_p_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlxtp (
Q ,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input GATE ;
input SLEEP_B;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
wire kapwr ;
wire vgnd ;
wire vpwr ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, SLEEP_B, kapwr, vgnd, vpwr);
bufif1 bufif10 (Q , buf_Q, vpwr );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_FUNCTIONAL_V
|
`timescale 1ns/100ps
module testbench();
reg clock, reset;
initial begin clock=0; reset=1; end
always
begin
#10;
clock = !clock;
end
//
// Instantiate advanced trigger...
//
reg validIn;
reg [31:0] dataIn;
reg arm;
reg wrSelect, wrChain;
reg [31:0] config_data;
trigger_adv adv (
clock, reset,
dataIn, validIn, arm,
wrSelect, wrChain, config_data,
// outputs...
run, capture);
always @ (posedge clock)
begin
#1;
if (capture) $display ("%t: Capture", $realtime);
if (run) $display ("%t: Run (triggered)", $realtime);
end
task issue_idle;
begin
#1; dataIn = 0; validIn=1'b1;
@(posedge clock);
#0.1; validIn=1'b0;
end
endtask
task issue_data;
input [31:0] value;
begin
$display ("%t: Issue Data: %08x", $realtime, value);
#1; dataIn = value; validIn=1'b1;
@(posedge clock);
#0.1; validIn=1'b0;
end
endtask
task write_select;
input [31:0] value;
begin
#1; config_data = value; wrSelect = 1'b1;
@(posedge clock);
#0.1; wrSelect = 1'b0;
end
endtask
task write_chain;
input [31:0] value;
begin
#1; config_data = value; wrChain = 1'b1;
@(posedge clock);
#1; wrChain = 1'b0;
repeat (32) @(posedge clock);
end
endtask
// Write trigger state...
task write_trigstate;
input [3:0] state;
input trigger;
input [1:0] start_timer;
input [1:0] clear_timer;
input [1:0] stop_timer;
input [3:0] else_state;
input [19:0] obtain_count;
begin
write_select(state);
write_chain({trigger,start_timer,clear_timer,stop_timer,else_state,obtain_count});
end
endtask
// Write one of the 10 trigger terms...
task write_trigterm;
input [3:0] termnum;
input [31:0] value;
input [31:0] mask;
reg [4:0] i;
reg [15:0] x0,x1,x2,x3,y0,y1,y2,y3;
reg [31:0] compare;
reg [127:0] chain;
begin
{x0,x1,x2,x3,y0,y1,y2,y3}=0;
for (i=0; i<16; i=i+1)
begin
compare = ({~i[3:0],~i[3:0],~i[3:0],~i[3:0],~i[3:0],~i[3:0],~i[3:0],~i[3:0]} ^ value) & mask;
x0 = {x0,~|compare[3:0]};
x1 = {x1,~|compare[7:4]};
x2 = {x2,~|compare[11:8]};
x3 = {x3,~|compare[15:12]};
y0 = {y0,~|compare[19:16]};
y1 = {y1,~|compare[23:20]};
y2 = {y2,~|compare[27:24]};
y3 = {y3,~|compare[31:28]};
end
chain = {y3,y2,y1,y0,x3,x2,x1,x0};
$display ("term %d: value=%x, mask=%x, chain=%x",termnum,value,mask,chain);
// Write adv trigger select index...
write_select(8'h20 + termnum);
// Write adv trigger chain data... Bit 127 is first shifted into the chain.
write_chain(chain[127:96]);
write_chain(chain[95:64]);
write_chain(chain[63:32]);
write_chain(chain[31:0]);
end
endtask
//
// Specify desired operations for combining trigger terms.
// a-b, c-range1, d-edge1, e-timer1, f-g, h-range2, i-edge2, j-timer2 terms:
//
// Inputs:
// statenum = which of the available states
// stateterm = 0=hit-term, 1=else-term, 2=capture-term
// op's = OP_AND, OP_NAND, OP_OR, OP_NOR4, OP_XOR, OP_NXOR, OP_A, OP_B, OP_NOP
//
// The op fields combine trigger-terms using one of the listed operations...
//
// a \__(op_ab)________
// b / \
// c \__(op_c_range1)___\
// range1 / \__(op_mid1)__
// d \__(op_d_edge1)_____/ \
// edge1 / / \
// e \__(op_e_timer1)__/ \
// timer1 / \__(op_final)__ hit
// f \__(op_fg)________ /
// g / \ /
// h \__(op_h_range2)___\ /
// range2 / \__(op_mid2)__/
// i \__(op_i_edge2)_____/
// edge2 / /
// j \__(op_j_timer2)__/
// timer2 /
//
// The mid1/mid2 ops combine the first & last four edge op's respectfully.
// The final op combines the mid ops.
//
parameter [3:0]
OP_NOP=0, OP_AND=1, OP_NAND=2, OP_OR=3, OP_NOR=4, OP_XOR=5, OP_NXOR=6, OP_A=7, OP_B=8;
reg [15:0] pairvalue[0:8];
reg [15:0] midvalue[0:8];
reg [15:0] finalvalue[0:8];
initial
begin
pairvalue[0]=16'h0000; midvalue[0]=16'h0000; finalvalue[0]=16'h0000; // NOP
pairvalue[1]=16'h8000; midvalue[1]=16'h8000; finalvalue[1]=16'h0008; // AND
pairvalue[2]=16'h7FFF; midvalue[2]=16'h7FFF; finalvalue[2]=16'h0007; // NAND
pairvalue[3]=16'hF888; midvalue[3]=16'hFFFE; finalvalue[3]=16'h000E; // OR
pairvalue[4]=16'h0777; midvalue[4]=16'h0001; finalvalue[4]=16'h0001; // NOR
pairvalue[5]=16'h7888; midvalue[5]=16'h0116; finalvalue[5]=16'h0006; // XOR
pairvalue[6]=16'h8777; midvalue[6]=16'hFEE9; finalvalue[6]=16'h0009; // NXOR
pairvalue[7]=16'h8888; // A-only
pairvalue[8]=16'hF000; // B-only
end
task write_trigsum;
input [3:0] statenum;
input [1:0] stateterm;
input [3:0] op_ab, op_c_range1, op_d_edge1, op_e_timer1; // edge sums
input [3:0] op_fg, op_h_range2, op_i_edge2, op_j_timer2;
input [3:0] op_mid1, op_mid2, op_final;
reg [191:0] chain;
begin
write_select (8'h40+(statenum*4)+stateterm);
chain = {
16'h0, // padding to make 32-bit aligned
finalvalue[op_final],
midvalue[op_mid2],
midvalue[op_mid1],
pairvalue[op_j_timer2],
pairvalue[op_i_edge2],
pairvalue[op_h_range2],
pairvalue[op_fg],
pairvalue[op_e_timer1],
pairvalue[op_d_edge1],
pairvalue[op_c_range1],
pairvalue[op_ab]};
$display ("termsum state/term %d/%d: %d/%d/%d/%d/%d/%d/%d/%d %d/%d/%d, chain=%x",
statenum, stateterm,
op_ab, op_c_range1, op_d_edge1, op_e_timer1,
op_fg, op_h_range2, op_i_edge2, op_j_timer2,
op_mid1, op_mid2, op_final,
chain);
// Write adv trigger chain data... MSB is first shifted into the chain.
write_chain(chain[191:160]);
write_chain(chain[159:128]);
write_chain(chain[127:96]);
write_chain(chain[95:64]);
write_chain(chain[63:32]);
write_chain(chain[31:0]);
end
endtask
//
// The range detectors are basically just carry-look-ahead adders.
// They are setup to "add" a value to in the input. If the carry output
// asserts, then they hit.
//
// 32-bit adders are used (two for each range check). If the sum
// of the input & the programed value are greater than 0xFFFFFFFF
// then the adder "carry" output asserts, indicating a hit.
//
// Lower value carry's are used directly. Upper value carry's are
// inverted to produce the following tests:
// indata >= lower
// indata <= upper
//
// Individual CLB LUT RAM's are configured to XOR between input
// on LUT addr 0 & the target value.
//
// ------------------------------------------------------------------
//
// It is possible for this to range check a non-contiguous value.
// ie: range check on indata bits 0, 7, 9, 11, 15 & no others.
//
// To do this, the disused range bit CLB's must be configured to NOP
// and not disturb the fast-carry-chain connecting them.
//
// LUT RAM's of disused CLB should be set to all 1's (ie: 0xFFFF).
//
// ------------------------------------------------------------------
//
// A given range target is bitwise inverted before being programmed
// (see code below). For non-contigues range checks, it must also be
// spaced out (currently not supported by this task).
//
// Lower values: ~(target-1)
// Upper values: ~target
//
// Yields a hit if: (upper >= indata >= lower)
//
// ------------------------------------------------------------------
//
// Example:
// lower=0x10000000. value-to-program-for-lower=0xF0000000 = ~(0x10000000-1)
// upper=0xE0000000. value-to-program-for-upper=0x1FFFFFFF = ~(0xE0000000)
//
// If indata=0x00000100, then lower misses. No match. Miss.
// If indata=0x0FFFFFFF, then lower misses (0x0FFFFFFF+0xF0000000 = no carry). Miss.
// If indata=0x10000000, then lower hits (0x1000000+0xF000000 = lower-carry) & upper hits. Match!
// If indata=0xE0000000, then lower hits & upper hits. Match!
// If indata=0xE0000001, then lower hits & upper misses (0xE0000001+0x1FFFFFFF = upper-carry). Miss!
//
parameter RANGE_XOR0 = 16'hAAAA;
parameter RANGE_XOR1 = 16'h5555;
task write_range;
input [1:0] rangesel; // 0=range1-lower, 1=range1-upper, 2=range2-lower, 3=range2-upper
input [31:0] target;
reg [31:0] value;
reg [31:0] chain; // Full chain is 16X this (512 bits total)
integer i;
begin
write_select (8'h30+rangesel);
if (rangesel[0])
value = ~target; // upper target
else value = ~(target-1); // lower value
// Write adv trigger chain data... MSB is first shifted into the chain.
for (i=0; i<16; i=i+1)
begin
chain = (value[31]) ? RANGE_XOR1 : RANGE_XOR0;
chain = {chain, (value[30]) ? RANGE_XOR1 : RANGE_XOR0};
$display ("range %d: i=%d chain=%x",rangesel, i, chain);
value = {value,2'b0};
write_chain(chain);
end
end
endtask
//
// The edge detector uses delay flops to detect rising & falling edges, both, or neither.
// Each 4-input CLB evalutes two bits of input, and two bits of delayed input.
//
parameter
EDGE_RISE0=16'h0A0A,
EDGE_RISE1=16'h00CC,
EDGE_FALL0=16'h5050,
EDGE_FALL1=16'h3300,
EDGE_BOTH0=16'h5A5A, // rise0|fall0
EDGE_BOTH1=16'h33CC, // rise1|fall1
EDGE_NEITHER0=16'hA5A5, // ~both0
EDGE_NEITHER1=16'hCC33; // ~both1
task write_edge;
input edgesel; // 0=edge1, 1=edge2
input [31:0] rising_edges;
input [31:0] falling_edges;
input [31:0] neither_edge;
reg [255:0] chain;
begin
write_select (8'h34+edgesel);
chain = 0;
for (i=31; i>0; i=i-2)
begin
chain = {chain,16'h0};
if (neither_edge[i])
chain[15:0] = chain[15:0] | EDGE_NEITHER1; // neither edge
else
case ({rising_edges[i],falling_edges[i]})
2'b01 : chain[15:0] = chain[15:0] | EDGE_FALL1; // falling edges
2'b10 : chain[15:0] = chain[15:0] | EDGE_RISE1; // rising edges
2'b11 : chain[15:0] = chain[15:0] | EDGE_BOTH1; // both edges
endcase
if (neither_edge[i-1])
chain[15:0] = chain[15:0] | EDGE_NEITHER0; // neither edge
else
case ({rising_edges[i-1],falling_edges[i-1]})
2'b01 : chain[15:0] = chain[15:0] | EDGE_FALL0; // falling edges
2'b10 : chain[15:0] = chain[15:0] | EDGE_RISE0; // rising edges
2'b11 : chain[15:0] = chain[15:0] | EDGE_BOTH0; // both edges
endcase
end
// Write adv trigger chain data... MSB is first shifted into the chain.
write_chain(chain[255:224]);
write_chain(chain[223:192]);
write_chain(chain[191:160]);
write_chain(chain[159:128]);
write_chain(chain[127:96]);
write_chain(chain[95:64]);
write_chain(chain[63:32]);
write_chain(chain[31:0]);
end
endtask
task write_timer_limit;
input timersel;
input [35:0] value;
begin
write_select (8'h38+timersel*2);
write_chain (value[31:0]);
write_select (8'h39+timersel*2);
write_chain ({28'h0,value[35:32]});
end
endtask
//
// Generate test sequence...
//
initial
begin : test
integer i;
validIn=0;
dataIn=0;
arm=0;
wrSelect=0;
wrChain=0;
config_data=0;
repeat (10) @(posedge clock);
reset = 0;
repeat (10) @(posedge clock);
// Configure simple two state trigger...
$display ("%t: Trigger Terms...", $realtime);
// term, value, mask
write_trigterm ( 0, 32'h00000011, 32'h000000FF); // terma = look for 0x11 in bits[7:0]
write_trigterm ( 1, 32'h00000042, 32'h000000FF); // termb = look for 0x42 in bits[7:0]
write_trigterm ( 2, 32'h00000033, 32'h000000FF); // termc = look for 0x33 in bits[7:0]
for (i=3; i<10; i=i+1) write_trigterm (i, 32'h00000000, 32'h00000000);
$display ("%t: Trigger Range 1 Lower...", $realtime);
write_range (0, 32'h00001234);
$display ("%t: Trigger Range 1 Upper...", $realtime);
write_range (1, 32'h00005678);
$display ("%t: Trigger Range 2 Lower...", $realtime);
write_range (2, 32'h00009ABC);
$display ("%t: Trigger Range 2 Upper...", $realtime);
write_range (3, 32'h0000DEF0);
$display ("%t: Trigger Edges...", $realtime);
write_edge (0, 32'h04010000, 32'h80200000, 32'h00000000); // edge1
write_edge (1, 32'h00000000, 32'h00000000, 32'h00000000); // edge2
$display ("%t: Trigger Timer Limits...", $realtime);
write_timer_limit (0, 1000); // 10000ns (1000 clocks)
write_timer_limit (1, 100000); // 1000000ns (100000 clocks)
$display ("%t: Trigger State FSM...", $realtime);
// state, trig, starttimer, cleartimer, stoptimer, elsestate, obtaincount
write_trigstate (4'h0, 1'b0, 2'b00, 2'b0, 2'b0, 4'h0, 20'h0); // on hit goto 1
write_trigstate (4'h1, 1'b0, 2'b01, 2'b0, 2'b0, 4'h0, 20'h0); // on hit start timer1 & goto 2, else 0
write_trigstate (4'h2, 1'b0, 2'b00, 2'b0, 2'b0, 4'h1, 20'h0); // on hit goto 3, else 1
write_trigstate (4'h3, 1'b1, 2'b00, 2'b0, 2'b0, 4'h2, 20'h0); // on hit trigger, else 2
// Trigsum fields:
// term: 0=hit, 1=else, 2=capture
// ops: OP_AND, OP_NAND, OP_OR, OP_NOR, OP_XOR, OP_NXOR, OP_A, OP_B, OP_NOP
$display ("%t: Trigger State Combination/Summing Ops...", $realtime);
// state, term, ab, c-r1, d-e1, e-t1, fg, h-r2, i-e2, j-t2, mid1, mid2, final
write_trigsum ( 0, 0, OP_A, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // hit=terma (0x11)
write_trigsum ( 0, 1, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // nop
write_trigsum ( 0, 2, OP_A, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // capture=terma
write_trigsum ( 1, 0, OP_B, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // hit=termb (0x42)
write_trigsum ( 1, 1, OP_A, OP_A, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // else=terma | termc (0x11 or 0x33)
write_trigsum ( 1, 2, OP_B, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // capture=termb
write_trigsum ( 2, 0, OP_NOP, OP_NOP, OP_NOP, OP_B, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // hit=timer1
write_trigsum ( 2, 1, OP_NOP, OP_NOP, OP_B, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // else-edge1
write_trigsum ( 2, 2, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR);
write_trigsum ( 3, 0, OP_NOP, OP_B, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR); // hit=range1
write_trigsum ( 3, 1, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR);
write_trigsum ( 3, 2, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_NOP, OP_OR, OP_OR, OP_OR);
repeat (10) @(posedge clock);
#1; arm=1;
repeat (10) @(posedge clock);
issue_data (32'h0); // start in state 0
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h00000001); // nop
issue_data (32'h00000011); // goes to state 1
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h0); // nop
issue_data (32'h00000011); // go back to state 0
issue_data (32'h00000001); // nop
issue_data (32'h00000011); // go back to state 1
issue_data (32'h00000001); // nop
issue_data (32'h00000033); // go back to state 0
issue_data (32'h00000003); // nop
issue_data (32'h00000011); // go back to state 1
issue_data (32'h00000001); // nop
issue_data (32'h00000002); // nop
issue_data (32'h00000042); // goto state 2
// waiting for state 3...
repeat (500) issue_idle; // wait for state 3
issue_data (32'h80002345); // hits range, but nop because still in state 2
issue_data (32'h80000000); //
issue_data (32'h00000000); // falling edge - back to state 1
issue_data (32'h00000042); // back to state 2
issue_data (32'h00010000); // rising edge - back to state 1
issue_data (32'h00000042); // back to state 2
repeat (1000) issue_idle; // wait for state 3
issue_data (32'h00002345); // trigger!
repeat (100) issue_idle;
$finish;
end
//
// Initialized wavedump...
//
reg [0:511] targetsst[0:0];
reg gotsst;
integer i;
initial
begin
$timeformat (-9,1," ns",0);
$display ("%t: Starting wave dump...",$realtime);
$dumpfile ("waves.dump");
$dumpvars(0);
end
endmodule
|
`timescale 1ns / 1ps
module computer #(
parameter bootrom_file = "example.hex"
)
(
`ifdef VERILATOR
input clk,
input reset
`endif
);
wire iack;
wire [63:0] iadr;
wire istb;
wire [31:0] idatiL;
wire [63:32] idatiH; // unused; just to make iverilog happy.
wire [63:0] ddato, ddati, dadr;
wire [1:0] dsiz;
wire dwe, dcyc, dstb, dsigned, dack;
wire [11:0] cadr;
wire coe, cwe, cvalid;
wire [63:0] cdato, cdati;
wire STB;
wire [63:0] romQ;
wire [1:0] xsiz;
wire [63:0] xadr;
wire [63:0] xdati, xdato;
wire xstb, xack, xsigned;
// initial begin
// $dumpfile("wtf.vcd"); $dumpvars;
// end
`ifndef VERILATOR
reg clk, reset;
initial begin
clk <= 0;
reset <= 1;
#60; reset <= 0;
end
always begin
#20 clk <= ~clk;
end
`endif
PolarisCPU cpu(
.fence_o(),
.trap_o(),
.cause_o(),
.mepc_o(),
.mpie_o(),
.mie_o(),
.ddat_o(ddato),
.dadr_o(dadr),
.dwe_o(dwe),
.dcyc_o(dcyc),
.dstb_o(dstb),
.dsiz_o(dsiz),
.dsigned_o(dsigned),
.irq_i(1'b0),
.iack_i(iack),
.idat_i(idatiL),
.iadr_o(iadr),
.istb_o(istb),
.dack_i(dack),
.ddat_i(ddati),
.cadr_o(cadr),
.coe_o(coe),
.cwe_o(cwe),
.cvalid_i(cvalid),
.cdat_o(cdato),
.cdat_i(cdati),
.clk_i(clk),
.reset_i(reset)
);
arbiter arbiter(
.idat_i(64'd0), // CPU cannot write via I-port.
.iadr_i(iadr),
.iwe_i(1'b0),
.icyc_i(istb),
.istb_i(istb),
.isiz_i({istb, 1'b0}),
.isigned_i(1'b0),
.iack_o(iack),
.idat_o({idatiH, idatiL}),
.ddat_i(ddato),
.dadr_i(dadr),
.dwe_i(dwe),
.dcyc_i(dcyc),
.dstb_i(dstb),
.dsiz_i(dsiz),
.dsigned_i(dsigned),
.dack_o(dack),
.ddat_o(ddati),
.xdat_o(xdato),
.xadr_o(xadr),
.xwe_o(),
.xcyc_o(),
.xstb_o(xstb),
.xsiz_o(xsiz),
.xsigned_o(xsigned),
.xack_i(xack),
.xdat_i(xdati),
.clk_i(clk),
.reset_i(reset)
);
bridge bridge(
.f_signed_i(xsigned),
.f_siz_i(xsiz),
.f_adr_i(xadr[2:0]),
.f_dat_i(xdato),
.f_dat_o(xdati),
.wb_sel_o(),
.wb_dat_i(romQ),
.wb_dat_o()
);
rom #(.bootrom_file(bootrom_file)) rom(
.A(xadr[11:3]),
.Q(romQ),
.STB(STB)
);
address_decode ad(
.iadr_i(xadr[12]),
.istb_i(xstb),
.iack_o(xack),
.STB_o(STB)
);
output_csr outcsr(
.cadr_i(cadr),
.cvalid_o(cvalid),
.cdat_o(cdati),
.cdat_i(cdato),
.coe_i(coe),
.cwe_i(cwe),
.clk_i(clk)
);
endmodule
|
/***************************************************************************
* pcx2mb_entry.v: A single buffer entry for the SPARC PCX to MicroBlaze
* FSL Fifo. This register entry will be instantiated 9 times.
*
* NOTE: Pipeline stages from SPARC point of view are
* PQ Initial Request
* PA Data sent for request.
* PX Grant returned, Request sent to cache
* PX2 Data sent to cache
*
* $Id: /import/bw-rainbow/rainbow_cvs/niagara/design/sys/iop/ccx2mb/rtl/pcx2mb_entry.v,v 1.2 2007/04/12 00:08:31 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module pcx2mb_entry (
// Outputs
e_data,
e_active,
e_dest,
// Inputs
rclk,
reset_l,
any_req_pa,
spc_pcx_data_pa,
req_dest_pa,
req_atom_pa,
any_req_px,
req_dest_px,
req_atom_px,
load_data,
prev_data,
prev_active,
prev_dest,
next_active
);
`ifdef PCX2MB_5_BIT_REQ
parameter PCX_REQ_WIDTH = 5;
`else
parameter PCX_REQ_WIDTH = 2;
`endif
output [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
output e_active;
output [4:0] e_dest;
input rclk;
input reset_l;
input any_req_pa;
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input [4:0] req_dest_pa;
input req_atom_pa;
input any_req_px;
input [4:0] req_dest_px;
input req_atom_px;
input load_data;
input [`PCX_WIDTH+PCX_REQ_WIDTH:0] prev_data;
input prev_active;
input [4:0] prev_dest;
input next_active;
reg [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
reg e_active;
reg [4:0] e_dest;
// Code for entry here. If a new request is received while the next entry
// is active, and this entry is not active, it will be placed into this one.
always @(posedge rclk) begin
if (!reset_l) begin
e_data <= {`PCX_WIDTH+PCX_REQ_WIDTH+1{1'b0}};
e_active <= 1'b0;
e_dest <= 5'b00000;
end
else if (load_data && prev_active) begin
e_data <= prev_data;
e_active <= prev_active;
e_dest <= prev_dest;
end
else if (any_req_pa && (
(next_active && !load_data && !e_active) ||
(next_active && load_data && e_active && !prev_active)))
begin
`ifdef PCX2MB_5_BIT_REQ
e_data <= { req_dest_pa[4:0], req_atom_pa, spc_pcx_data_pa};
`else
e_data <= { req_dest_pa[4], (|req_dest_pa[3:0]), req_atom_pa,
spc_pcx_data_pa};
`endif
e_active <= 1'b1;
e_dest <= req_dest_pa;
end
else if (any_req_px && req_atom_px && (
(next_active && !load_data && !e_active) ||
(next_active && load_data && e_active && !prev_active)))
begin
`ifdef PCX2MB_5_BIT_REQ
e_data <= { req_dest_px[4:0], req_atom_px, spc_pcx_data_pa};
`else
e_data <= { req_dest_px[4], (|req_dest_px[3:0]), 1'b0,
spc_pcx_data_pa};
`endif
e_active <= 1'b1;
e_dest <= req_dest_px;
end
else begin
e_data <= e_data;
e_dest <= e_dest;
if (load_data && e_active) begin
e_active <= 1'b0;
end
else begin
e_active <= e_active;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_1_V
`define SKY130_FD_SC_HD__O22AI_1_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-need to work on dual mode for pn sequence
`timescale 1ns/100ps
module axi_axis_rx_core (
// adc interface
adc_clk,
adc_valid,
adc_data,
// dma interface
dma_clk,
dma_valid,
dma_last,
dma_data,
dma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
// adc interface
input adc_clk;
input adc_valid;
input [DW:0] adc_data;
// dma interface
input dma_clk;
output dma_valid;
output dma_last;
output [DW:0] dma_data;
input dma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal clocks and resets
wire adc_rst;
wire dma_rst;
// internal signals
wire dma_ovf_s;
wire dma_unf_s;
wire dma_status_s;
wire [31:0] dma_bw_s;
wire dma_start_s;
wire dma_stream_s;
wire [31:0] dma_count_s;
// dma interface
ad_axis_dma_rx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_dma_rx (
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_valid (dma_valid),
.dma_last (dma_last),
.dma_data (dma_data),
.dma_ready (dma_ready),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_status (dma_status_s),
.dma_bw (dma_bw_s),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_data (adc_data),
.dma_start (dma_start_s),
.dma_stream (dma_stream_s),
.dma_count (dma_count_s));
// processor control
up_axis_dma_rx i_up_axis_dma_rx (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_start (dma_start_s),
.dma_stream (dma_stream_s),
.dma_count (dma_count_s),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_status (dma_status_s),
.dma_bw (dma_bw_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
Floating Point Registers
Registers implement the conversion process.
*/
`include "CoreDefs.v"
`include "FpuFp32To64.v"
`include "FpuFp64To32.v"
module RegFPR(
/* verilator lint_off UNUSED */
clock, reset,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRm, regValRm,
regIdRn, regValRn,
regMode, regCsFl,
regStMode,
ctlInFpul, ctlOutFpul
);
input clock;
input reset;
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRm;
input[6:0] regIdRn;
output[63:0] regValRs;
output[63:0] regValRt;
output[63:0] regValRm;
input[63:0] regValRn;
input[1:0] regMode; //get mode
input[15:0] regCsFl;
input[1:0] regStMode; //set mode
input[31:0] ctlInFpul; //FPUL in
output[31:0] ctlOutFpul; //FPUL out
reg[31:0] regFprH[15:0]; //FR0, FR2, FR4, ...
reg[31:0] regFprL[15:0]; //FR1, FR3, FR5, ...
/* verilator lint_off UNOPTFLAT */
reg[31:0] tRegValRsF;
reg[31:0] tRegValRtF;
reg[31:0] tRegValRmF;
wire[63:0] tRegValRsD;
wire[63:0] tRegValRtD;
wire[63:0] tRegValRmD;
/* verilator lint_on UNOPTFLAT */
// reg[63:0] tRegValRnD;
wire[31:0] tRegValRnF;
reg[31:0] tRegValRnF2;
reg[63:0] tRegValRs;
reg[63:0] tRegValRt;
reg[63:0] tRegValRm;
reg[31:0] tFpul;
reg cvtF32To64;
reg accF32Raw;
reg cvtStF32To64;
reg accStF32Raw;
FpuFp32To64 fpCvtRs(clock, cvtF32To64, tRegValRsF, tRegValRsD);
FpuFp32To64 fpCvtRt(clock, cvtF32To64, tRegValRtF, tRegValRtD);
FpuFp32To64 fpCvtRm(clock, cvtF32To64, tRegValRmF, tRegValRmD);
//FpuFp64To32 fpCvtRn(clock, cvtF32To64, tRegValRnD, tRegValRnF);
FpuFp64To32 fpCvtRn(clock, cvtF32To64, regValRn, tRegValRnF);
assign regValRs = tRegValRs;
assign regValRt = tRegValRt;
assign regValRm = tRegValRm;
assign ctlOutFpul = tFpul;
// always @ (clock)
always @*
begin
tRegValRs=0;
tRegValRt=0;
tRegValRm=0;
tRegValRsF=0;
// tRegValRsD=0;
tRegValRtF=0;
// tRegValRtD=0;
tRegValRmF=0;
// tRegValRmD=0;
// tFpul = ctlInFpul;
// tRegValRnD = regValRn;
cvtF32To64=0;
accF32Raw=1;
cvtStF32To64=0;
accStF32Raw=1;
/*
case(regMode)
2'b00: begin //Float
cvtF32To64=1;
accF32Raw=0;
end
2'b01: begin //Double
cvtF32To64=0;
accF32Raw=0;
end
2'b10: begin //Raw Float
cvtF32To64=0;
accF32Raw=1;
end
2'b11: begin //Raw Double?
cvtF32To64=0;
accF32Raw=0;
end
endcase
*/
/*
case(regStMode)
2'b00: begin //Float
cvtStF32To64=1;
accStF32Raw=0;
end
2'b01: begin //Double
cvtStF32To64=0;
accStF32Raw=0;
end
2'b10: begin //Raw Float
cvtStF32To64=0;
accStF32Raw=1;
end
2'b11: begin //Raw Double?
cvtStF32To64=0;
accStF32Raw=0;
end
endcase
*/
if(regIdRs[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRsF=regIdRs[0]?
regFprL[regIdRs[4:1]]:
regFprH[regIdRs[4:1]];
if(accF32Raw)
tRegValRs[31:0]=tRegValRsF;
else
tRegValRs=tRegValRsD;
end
else
begin
tRegValRs[31: 0]=regFprL[regIdRs[4:1]];
tRegValRs[63:32]=regFprH[regIdRs[4:1]];
end
end
else if(regIdRs==UREG_FPUL)
begin
tRegValRsF = ctlInFpul;
tRegValRs = tRegValRtD;
if(accF32Raw)
tRegValRs[31:0]=ctlInFpul[31:0];
end
if(regIdRt[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRtF=regIdRt[0]?
regFprL[regIdRt[4:1]]:
regFprH[regIdRt[4:1]];
if(accF32Raw)
tRegValRt[31:0]=tRegValRtF;
else
tRegValRt=tRegValRtD;
end
else
begin
tRegValRt[31: 0]=regFprL[regIdRt[4:1]];
tRegValRt[63:32]=regFprH[regIdRt[4:1]];
end
end
else if(regIdRt==UREG_FPUL)
begin
tRegValRtF = ctlInFpul;
tRegValRt = tRegValRtD;
if(accF32Raw)
tRegValRt[31:0]=ctlInFpul[31:0];
end
if(regIdRm[6:5]==2'b10)
begin
if(cvtF32To64 || accF32Raw)
begin
tRegValRmF=regIdRs[0]?
regFprL[regIdRm[4:1]]:
regFprH[regIdRm[4:1]];
if(accF32Raw)
tRegValRm[31:0]=tRegValRmF;
else
tRegValRm=tRegValRmD;
end
else
begin
tRegValRm[31: 0]=regFprL[regIdRm[4:1]];
tRegValRm[63:32]=regFprH[regIdRm[4:1]];
end
end
/*
if(regIdRn==UREG_FPUL)
begin
case(regStMode)
2'b00: tFpul = tRegValRnF;
2'b01: tFpul = tRegValRnF;
2'b10: tFpul = regValRn[31:0];
2'b11: tFpul = regValRn[31:0];
endcase
end
// else
// tFpul = ctlInFpul;
*/
if(cvtStF32To64 || accStF32Raw)
begin
tRegValRnF2 = accStF32Raw ?
regValRn[31:0] :
tRegValRnF;
end
end
always @ (posedge clock)
begin
if(regIdRn[6:5]==2'b10)
begin
if(cvtStF32To64 || accStF32Raw)
begin
if(regIdRn[0])
regFprL[regIdRn[4:1]] <= tRegValRnF2;
else
regFprH[regIdRn[4:1]] <= tRegValRnF2;
end
else
begin
regFprL[regIdRn[4:1]] <= regValRn[31: 0];
regFprH[regIdRn[4:1]] <= regValRn[63:32];
end
end
if(regIdRn==UREG_FPUL)
begin
case(regStMode)
2'b00: tFpul <= tRegValRnF2;
2'b01: tFpul <= tRegValRnF2;
2'b10: tFpul <= regValRn[31:0];
2'b11: tFpul <= regValRn[31:0];
endcase
end
else
tFpul <= ctlInFpul;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_V
`define SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the advanced register file
// Import the modules that will be tested for in this testbench
`include "regfileww.v"
// IMPORTANT: To run this, try: ncverilog -f regfileww.f +gui
module tb_regfileww();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the advanced register file
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// rd1data or rd2data output signals
wire [127:0] rd1_d,rd2_d;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, wren,rd1en,rd2en;
reg clock,wr_en,r1_en,r2_en;
// wrdata
reg [127:0] wr_d;
// wraddr, rd1addr, rd2addr
reg [4:0] w_addr,r1_addr,r2_addr;
// wrbyteen
reg [15:0] wrbytn;
// 32 Words of 128-bits
reg r[0:31];
reg [127:0] r_row;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#2.5 clock = 0;
#2.5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
RegFileWW rg (
// instance_name(signal name),
// Signal name can be the same as the instance name
rd1_d,rd2_d,wr_d,r1_addr,r2_addr,w_addr,r1_en,r2_en,
wr_en,wrbytn,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/*
for(count=0;count<=size_of_input;count=count+1)
begin
#10
//$display("Next");
r_row=r[count];
$display("Next",r_row);
end
*/
// Write to 8 data locations
#20
wr_d=128'h787897ea12fec60cae787897eac22354;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd0;
wrbytn=16'hff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h72348973465465465464645664654666;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd1;
wrbytn=16'h7f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h48545618548486131875531264684565;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd2;
wrbytn=16'h3f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h48646517897894613514684987984614;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd3;
wrbytn=16'h1f;
r1_en=0;
r2_en=0;
wr_en=1;
// ===================================
#20
wr_d=128'hcaacecce09c4ae54864c6ae464ca3544;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd4;
wrbytn=16'hfff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'hceac45564c1ae151c53ae15c153ae1c4;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd5;
wrbytn=16'h7ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'hdc46da456c1ad561c65ad1c6ad61c455;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd6;
wrbytn=16'h3ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
//wr_d=128'h18342cad864c65da4654cad646c5d4a564cd56ca552;
wr_d=128'hc65da4654cad646c5d4a564cd56ca552;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd7;
wrbytn=16'h1ff;
r1_en=0;
r2_en=0;
wr_en=1;
// Read the data from the aforementioned locations
#20
wr_d=128'd12345;
r1_addr=5'd0;
r2_addr=5'd7;
w_addr=5'd20;
wrbytn=16'hffff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd1;
r2_addr=5'd6;
w_addr=5'd20;
wrbytn=16'h7fff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd2;
r2_addr=5'd5;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd3;
r2_addr=5'd4;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// ====================================================
#20
wr_d=128'd12345;
r1_addr=5'd4;
r2_addr=5'd3;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd5;
r2_addr=5'd2;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd6;
r2_addr=5'd1;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd7;
r2_addr=5'd0;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
(** * Rel: Properties of Relations *)
(* $Date: 2013-04-01 09:15:45 -0400 (Mon, 01 Apr 2013) $ *)
Require Export SfLib.
(** A (binary) _relation_ is just a parameterized proposition. As you know
from your undergraduate discrete math course, there are a lot of
ways of discussing and describing relations _in general_ -- ways
of classifying relations (are they reflexive, transitive, etc.),
theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. Let us pause here to review a few that will be useful in
what follows. *)
(** A (binary) relation _on_ a set [X] is a proposition parameterized by two
[X]s -- i.e., it is a logical assertion involving two values from
the set [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-that-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====>
Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m
*)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined in Logic.v is a
partial function. *)
(* Print next_nat.
(* ====>
Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n)
*)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed. *)
(** However, the [<=] relation on numbers is not a partial function.
This can be shown by contradiction. In short: Assume, for a
contradiction, that [<=] is a partial function. But then, since
[0 <= 0] and [0 <= 1], it follows that [0 = 1]. This is nonsense,
so our assumption was contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
Case "Proof of assertion".
apply Hc with (x := 0).
apply le_n.
apply le_S. apply le_n.
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in Logic.v is not a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined in Logic.v is a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
Case "le_n". apply Hnm.
Case "le_S". apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
- apply le_S. apply Hnm.
- apply le_S. apply IHHm'o.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
- inversion Hmo.
- inversion Hmo.
+ rewrite <- H0. apply le_S. apply Hnm.
+ apply le_S. apply IHo'. apply H0.
Qed.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
intros. inversion H.
+ apply le_n.
+ apply le_S_n. apply H.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
_Proof_: By induction on [n].
- First, suppose [n = 0]. Then, we must show that [~(S 0 <= 0)].
Now, assume [S 0 <= 0]. By the definition of [<=], it follows that [S 0 = 0], a contradiction. Therefore, it follows [~(S 0 <= 0)].
- Next, suppose [n = S n']. To show that [~(S (S n') <= S n'],
we can assume [S (S n') <= S n'] and derive a contradiction.
By [le_S_n], [S (S n') <= S n'] implies that [S n' <= n']. By the induction
hypothesis, this is a contradiction.
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
intros. unfold not. intros H. induction n as [|n'].
- inversion H.
- apply IHn'. apply le_S_n. apply H.
Qed.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
unfold not. unfold symmetric. intros.
assert (1 <= 0) as Nonsense.
- apply H. apply le_S. apply le_n.
- inversion Nonsense.
Qed.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
unfold antisymmetric. intros a b H. destruct H.
- reflexivity.
- intros. apply ex_falso_quodlibet. assert (S m <= m) as Nonsense.
+ apply le_trans with a. apply H0. apply H.
+ destruct le_Sn_n with m. apply Nonsense.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
intros. unfold lt in H. apply le_S_n. apply le_trans with m. apply H. apply H0.
Qed.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
Case "refl". apply le_reflexive.
split.
Case "antisym". apply le_antisymmetric.
Case "transitive.". apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
Case "->".
intro H. induction H.
SCase "le_n". apply rt_refl.
SCase "le_S".
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
Case "<-".
intro H. induction H.
SCase "rt_step". inversion H. apply le_S. apply le_n.
SCase "rt_refl". apply le_n.
SCase "rt_trans".
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** (The following [Tactic Notation] definitions are explained in
Imp.v. You can ignore them if you haven't read that chapter
yet.) *)
Tactic Notation "rt_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rt_step" | Case_aux c "rt_refl"
| Case_aux c "rt_trans" ].
Tactic Notation "rsc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rsc_refl" | Case_aux c "rsc_step" ].
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
intros. generalize dependent z. induction H.
- intros. apply H0.
- intros. apply rsc_step with y. apply H. apply IHrefl_step_closure. apply H1.
Qed.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
intros. split.
- intros. induction H as [x y|x|x y z xy Hxy yz Hyz].
+ apply rsc_R. apply H.
+ apply rsc_refl.
+ apply rsc_trans with y. apply Hxy. apply Hyz.
- intros. induction H as [|x y z Rxy Cyz Hxy].
+ apply rt_refl.
+ apply rt_trans with y.
* apply rt_step. apply Rxy.
* apply Hxy.
Qed.
(** [] *)
|
// megafunction wizard: %Virtual JTAG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: sld_virtual_jtag
// ============================================================
// File Name: vji.v
// Megafunction Name(s):
// sld_virtual_jtag
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vji (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir);
input [1:0] ir_out;
input tdo;
output [1:0] ir_in;
output tck;
output tdi;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
wire sub_wire0;
wire sub_wire1;
wire [1:0] sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire sub_wire7;
wire sub_wire8;
wire sub_wire9;
wire sub_wire10;
wire virtual_state_cir = sub_wire0;
wire virtual_state_pdr = sub_wire1;
wire [1:0] ir_in = sub_wire2[1:0];
wire tdi = sub_wire3;
wire virtual_state_udr = sub_wire4;
wire tck = sub_wire5;
wire virtual_state_e1dr = sub_wire6;
wire virtual_state_uir = sub_wire7;
wire virtual_state_cdr = sub_wire8;
wire virtual_state_e2dr = sub_wire9;
wire virtual_state_sdr = sub_wire10;
sld_virtual_jtag sld_virtual_jtag_component (
.ir_out (ir_out),
.tdo (tdo),
.virtual_state_cir (sub_wire0),
.virtual_state_pdr (sub_wire1),
.ir_in (sub_wire2),
.tdi (sub_wire3),
.virtual_state_udr (sub_wire4),
.tck (sub_wire5),
.virtual_state_e1dr (sub_wire6),
.virtual_state_uir (sub_wire7),
.virtual_state_cdr (sub_wire8),
.virtual_state_e2dr (sub_wire9),
.virtual_state_sdr (sub_wire10)
// synopsys translate_off
,
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_e1ir (),
.jtag_state_e2dr (),
.jtag_state_e2ir (),
.jtag_state_pdr (),
.jtag_state_pir (),
.jtag_state_rti (),
.jtag_state_sdr (),
.jtag_state_sdrs (),
.jtag_state_sir (),
.jtag_state_sirs (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.tms ()
// synopsys translate_on
);
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = 2,
sld_virtual_jtag_component.sld_sim_action = "",
sld_virtual_jtag_component.sld_sim_n_scan = 0,
sld_virtual_jtag_component.sld_sim_total_length = 0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: show_jtag_state STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "2"
// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING ""
// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "0"
// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "0"
// Retrieval info: USED_PORT: ir_in 0 0 2 0 OUTPUT NODEFVAL "ir_in[1..0]"
// Retrieval info: USED_PORT: ir_out 0 0 2 0 INPUT NODEFVAL "ir_out[1..0]"
// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck"
// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi"
// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo"
// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr"
// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir"
// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr"
// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr"
// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr"
// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr"
// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr"
// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir"
// Retrieval info: CONNECT: @ir_out 0 0 2 0 ir_out 0 0 2 0
// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0
// Retrieval info: CONNECT: ir_in 0 0 2 0 @ir_in 0 0 2 0
// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0
// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0
// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0
// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vji.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vji.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vji.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vji.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vji_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vji_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length Encoder, remove zero sequences ////
//// ////
//// - Detect (15,0) (0,0) seqence ////
//// - Replace them by (0,0) ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rzs.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rzs.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rzs(clk, ena, rst, deni, dci, rleni, sizei, ampi, deno, dco, rleno, sizeo, ampo);
//
// inputs & outputs
//
input clk;
input ena;
input rst;
input deni;
input dci;
input [ 3:0] sizei;
input [ 3:0] rleni;
input [11:0] ampi;
output deno;
output dco;
output [ 3:0] sizeo;
output [ 3:0] rleno;
output [11:0] ampo;
reg deno, dco;
reg [ 3:0] sizeo, rleno;
reg [11:0] ampo;
//
// variables
//
reg [ 3:0] size;
reg [ 3:0] rlen;
reg [11:0] amp;
reg den;
reg dc;
wire eob;
wire zerobl;
reg state;
//
// module body
//
always @(posedge clk)
if(ena & deni)
begin
size <= #1 sizei;
rlen <= #1 rleni;
amp <= #1 ampi;
end
always @(posedge clk)
if(ena)
begin
sizeo <= #1 size;
rleno <= #1 rlen;
ampo <= #1 amp;
dc <= #1 dci;
dco <= #1 dc;
end
assign zerobl = &rleni & ~|sizei & deni;
assign eob = ~|{rleni, sizei} & deni & ~dci;
always @(posedge clk or negedge rst)
if (!rst)
begin
state <= #1 1'b0;
den <= #1 1'b0;
deno <= #1 1'b0;
end
else
if(ena)
case (state) // synopsys full_case parallel_case
1'b0:
begin
if (zerobl)
begin
state <= #1 1'b1; // go to zero-detection state
den <= #1 1'b0; // do not yet set data output enable
deno <= #1 den; // output previous data
end
else
begin
state <= #1 1'b0; // stay in 'normal' state
den <= #1 deni; // set data output enable
deno <= #1 den; // output previous data
end
end
1'b1:
begin
deno <= #1 1'b0;
if (deni)
if (zerobl)
begin
state <= #1 1'b1; // stay in zero-detection state
den <= #1 1'b0; // hold current zer-block
deno <= #1 1'b1; // output previous zero-block
end
else if (eob)
begin
state <= #1 1'b0; // go to 'normal' state
den <= #1 1'b1; // set output enable for EOB
deno <= #1 1'b0; // (was already zero), maybe optimize ??
end
else
begin
state <= #1 1'b0; // go to normal state
den <= #1 1'b1; // set data output enable
deno <= #1 1'b1; // oops, zero-block should have been output
end
end
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__OR4B_PP_SYMBOL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4B_PP_SYMBOL_V
|
/***********************************************************
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable single 10 or 12 bit byte lane.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
//`include "phy.vh"
module mig_7series_v2_0_ddr_byte_lane #(
// these are used to scale the index into phaser,calib,scan,mc vectors
// to access fields used in this instance
parameter ABCD = "A", // A,B,C, or D
parameter PO_DATA_CTL = "FALSE",
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b1111_1111_1111,
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter RCLK_SELECT_LANE = "B",
parameter PC_CLK_RATIO = 4,
parameter USE_PRE_POST_FIFO = "FALSE",
//OUT_FIFO
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_ARRAY_MODE = "UNDECLARED",
parameter OF_OUTPUT_DISABLE = "FALSE",
parameter OF_SYNCHRONOUS_MODE = "TRUE",
//IN_FIFO
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_ARRAY_MODE = "UNDECLARED",
parameter IF_SYNCHRONOUS_MODE = "TRUE",
//PHASER_IN
parameter PI_BURST_MODE = "TRUE",
parameter PI_CLKOUT_DIV = 2,
parameter PI_FREQ_REF_DIV = "NONE",
parameter PI_FINE_DELAY = 1,
parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter PI_SEL_CLK_OFFSET = 0,
parameter PI_SYNC_IN_DIV_RST = "FALSE",
//PHASER_OUT
parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2,
parameter PO_FINE_DELAY = 0,
parameter PO_COARSE_BYPASS = "FALSE",
parameter PO_COARSE_DELAY = 0,
parameter PO_OCLK_DELAY = 0,
parameter PO_OCLKDELAY_INV = "TRUE",
parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PO_SYNC_IN_DIV_RST = "FALSE",
// OSERDES
parameter OSERDES_DATA_RATE = "DDR",
parameter OSERDES_DATA_WIDTH = 4,
//IDELAY
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
// local constants, do not pass in from above
parameter BUS_WIDTH = 12,
parameter MSB_BURST_PEND_PO = 3,
parameter MSB_BURST_PEND_PI = 7,
parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8,
parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1
,parameter CKE_ODT_AUX = "FALSE"
)(
input rst,
input phy_clk,
input freq_refclk,
input mem_refclk,
input idelayctrl_refclk,
input sync_pulse,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input [9:0] mem_dq_in,
output mem_dqs_out,
output mem_dqs_ts,
input mem_dqs_in,
output [11:0] ddr_ck_out,
output rclk,
input if_empty_def,
output if_a_empty,
output if_empty,
output if_a_full,
output if_full,
output of_a_empty,
output of_empty,
output of_a_full,
output of_full,
output pre_fifo_a_full,
output [79:0] phy_din,
input [79:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input if_rst,
input [2:0] byte_rd_en_oth_lanes,
input [1:0] byte_rd_en_oth_banks,
output byte_rd_en,
output po_coarse_overflow,
output po_fine_overflow,
output [8:0] po_counter_read_val,
input po_fine_enable,
input po_coarse_enable,
input [1:0] po_en_calib,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input [1:0] pi_en_calib,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output wire pi_iserdes_rst,
output pi_phase_locked,
output pi_fine_overflow,
output [5:0] pi_counter_read_val,
output wire pi_dqs_found,
output dqs_out_of_range
);
localparam PHASER_INDEX =
(ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0));
localparam L_OF_ARRAY_MODE =
(OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE :
(PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4";
localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE :
(PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8";
localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ;
localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4;
localparam real L_FREQ_REF_PERIOD_NS = TCK > 2500.0 ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0;
localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0;
localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0;
localparam ODDR_CLK_EDGE = "SAME_EDGE";
localparam PO_DCD_CORRECTION = "ON";
localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000;
localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? 1 : 0;
localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? "001" : "000";
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [3:0] of_q9;
wire [3:0] of_q8;
wire [3:0] of_q7;
wire [7:0] of_q6;
wire [7:0] of_q5;
wire [3:0] of_q4;
wire [3:0] of_q3;
wire [3:0] of_q2;
wire [3:0] of_q1;
wire [3:0] of_q0;
wire [7:0] of_d9;
wire [7:0] of_d8;
wire [7:0] of_d7;
wire [7:0] of_d6;
wire [7:0] of_d5;
wire [7:0] of_d4;
wire [7:0] of_d3;
wire [7:0] of_d2;
wire [7:0] of_d1;
wire [7:0] of_d0;
wire [7:0] if_q9;
wire [7:0] if_q8;
wire [7:0] if_q7;
wire [7:0] if_q6;
wire [7:0] if_q5;
wire [7:0] if_q4;
wire [7:0] if_q3;
wire [7:0] if_q2;
wire [7:0] if_q1;
wire [7:0] if_q0;
wire [3:0] if_d9;
wire [3:0] if_d8;
wire [3:0] if_d7;
wire [3:0] if_d6;
wire [3:0] if_d5;
wire [3:0] if_d4;
wire [3:0] if_d3;
wire [3:0] if_d2;
wire [3:0] if_d1;
wire [3:0] if_d0;
wire [3:0] dummy_i5;
wire [3:0] dummy_i6;
wire [48-1:0] of_dqbus;
wire [10*4-1:0] iserdes_dout;
wire iserdes_clk;
wire iserdes_clkdiv;
wire ififo_wr_enable;
wire phy_rd_en_;
wire dqs_to_phaser;
wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en;
wire if_empty_;
wire if_a_empty_;
wire if_full_;
wire if_a_full_;
wire po_oserdes_rst;
wire empty_post_fifo;
reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */;
wire [79:0] rd_data;
reg [79:0] rd_data_r;
reg ififo_rst = 1'b1;
reg ofifo_rst = 1'b1;
wire of_wren_pre;
wire [79:0] pre_fifo_dout;
wire pre_fifo_full;
wire pre_fifo_rden;
wire [5:0] ddr_ck_out_q;
wire ififo_rd_en_in /* synthesis syn_maxfan = 10 */;
wire oserdes_clkdiv;
wire oserdes_clk_delayed;
wire po_rd_enable;
always @(posedge phy_clk) begin
ififo_rst <= #1 pi_rst_dqs_find | if_rst ;
// reset only data o-fifos on reset of dqs_found
ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst;
end
// IN_FIFO EMPTY->RDEN TIMING FIX:
// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO
// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty
assign #(25) phy_rd_en_ = 1'b1;
//assign #(25) phy_rd_en_ = phy_rd_en;
generate
if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null
assign if_empty = 0;
assign if_a_empty = 0;
assign if_full = 0;
assign if_a_full = 0;
end
else begin : if_empty_gen
assign if_empty = empty_post_fifo;
assign if_a_empty = if_a_empty_;
assign if_full = if_full_;
assign if_a_full = if_a_full_;
end
endgenerate
generate
if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48
assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign phy_din = 80'h0;
assign byte_rd_en = 1'b1;
end
else begin : dq_gen_40
assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) :
((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en);
if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen
// IN_FIFO EMPTY->RDEN TIMING FIX:
assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
always @(posedge phy_clk) begin
rd_data_r <= #(025) rd_data;
if_empty_r[0] <= #(025) if_empty_;
if_empty_r[1] <= #(025) if_empty_;
if_empty_r[2] <= #(025) if_empty_;
if_empty_r[3] <= #(025) if_empty_;
end
mig_7series_v2_0_ddr_if_post_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (4), //2 // depth - account for up to 2 cycles of skew
.WIDTH (80) // width
)
u_ddr_if_post_fifo
(
.clk (phy_clk),
.rst (ififo_rst),
.empty_in (if_empty_r),
.rd_en_in (ififo_rd_en_in),
.d_in (rd_data_r),
.empty_out (empty_post_fifo),
.byte_rd_en (byte_rd_en),
.d_out (phy_din)
);
end
else begin : phy_din_gen
assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
assign empty_post_fifo = if_empty_;
end
end
endgenerate
assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;
wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);
generate
if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout;
mig_7series_v2_0_ddr_of_pre_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (9), // depth - set to 9 to accommodate flow control
.WIDTH (80) // width
)
u_ddr_of_pre_fifo
(
.clk (phy_clk),
.rst (ofifo_rst),
.full_in (of_full),
.wr_en_in (phy_wr_en),
.d_in (phy_dout),
.wr_en_out (of_wren_pre),
.d_out (pre_fifo_dout),
.afull (pre_fifo_a_full)
);
end
else begin
// wire direct to ofifo
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout;
assign of_wren_pre = phy_wr_en;
end
endgenerate
generate
if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen
PHASER_IN_PHY #(
.BURST_MODE ( PI_BURST_MODE),
.CLKOUT_DIV ( PI_CLKOUT_DIV),
.DQS_AUTO_RECAL ( DQS_AUTO_RECAL),
.DQS_FIND_PATTERN ( DQS_FIND_PATTERN),
.SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),
.FINE_DELAY ( PI_FINE_DELAY),
.FREQ_REF_DIV ( PI_FREQ_REF_DIV),
.OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)
) phaser_in (
.DQSFOUND (pi_dqs_found),
.DQSOUTOFRANGE (dqs_out_of_range),
.FINEOVERFLOW (pi_fine_overflow),
.PHASELOCKED (pi_phase_locked),
.ISERDESRST (pi_iserdes_rst),
.ICLKDIV (iserdes_clkdiv),
.ICLK (iserdes_clk),
.COUNTERREADVAL (pi_counter_read_val),
.RCLK (rclk),
.WRENABLE (ififo_wr_enable),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
.ENCALIBPHY (pi_en_calib),
.FINEENABLE (pi_fine_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (rank_sel_i),
.PHASEREFCLK (dqs_to_phaser),
.RSTDQSFIND (pi_rst_dqs_find),
.RST (rst),
.FINEINC (pi_fine_inc),
.COUNTERLOADEN (pi_counter_load_en),
.COUNTERREADEN (pi_counter_read_en),
.COUNTERLOADVAL (pi_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
else begin
assign pi_dqs_found = 1'b1;
// assign pi_dqs_out_of_range = 1'b0;
assign pi_phase_locked = 1'b1;
end
endgenerate
wire #0 phase_ref = freq_refclk;
wire oserdes_clk;
PHASER_OUT_PHY #(
.CLKOUT_DIV ( PO_CLKOUT_DIV),
.DATA_CTL_N ( PO_DATA_CTL ),
.FINE_DELAY ( PO_FINE_DELAY),
.COARSE_BYPASS ( PO_COARSE_BYPASS ),
.COARSE_DELAY ( PO_COARSE_DELAY),
.OCLK_DELAY ( PO_OCLK_DELAY),
.OCLKDELAY_INV ( PO_OCLKDELAY_INV),
.OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( 1), // dummy, not used
.PO ( PO_DCD_SETTING ),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS)
) phaser_out (
.COARSEOVERFLOW (po_coarse_overflow),
.CTSBUS (oserdes_dqs_ts),
.DQSBUS (oserdes_dqs),
.DTSBUS (oserdes_dq_ts),
.FINEOVERFLOW (po_fine_overflow),
.OCLKDIV (oserdes_clkdiv),
.OCLK (oserdes_clk),
.OCLKDELAYED (oserdes_clk_delayed),
.COUNTERREADVAL (po_counter_read_val),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),
.ENCALIBPHY (po_en_calib),
.RDENABLE (po_rd_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.PHASEREFCLK (/*phase_ref*/),
.RST (rst),
.OSERDESRST (po_oserdes_rst),
.COARSEENABLE (po_coarse_enable),
.FINEENABLE (po_fine_enable),
.COARSEINC (po_coarse_inc),
.FINEINC (po_fine_inc),
.SELFINEOCLKDELAY (po_sel_fine_oclk_delay),
.COUNTERLOADEN (po_counter_load_en),
.COUNTERREADEN (po_counter_read_en),
.COUNTERLOADVAL (po_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
generate
if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen
IN_FIFO #(
.ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
.ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
.ARRAY_MODE ( L_IF_ARRAY_MODE),
.SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
) in_fifo (
.ALMOSTEMPTY (if_a_empty_),
.ALMOSTFULL (if_a_full_),
.EMPTY (if_empty_),
.FULL (if_full_),
.Q0 (if_q0),
.Q1 (if_q1),
.Q2 (if_q2),
.Q3 (if_q3),
.Q4 (if_q4),
.Q5 (if_q5),
.Q6 (if_q6),
.Q7 (if_q7),
.Q8 (if_q8),
.Q9 (if_q9),
//===
.D0 (if_d0),
.D1 (if_d1),
.D2 (if_d2),
.D3 (if_d3),
.D4 (if_d4),
.D5 ({dummy_i5,if_d5}),
.D6 ({dummy_i6,if_d6}),
.D7 (if_d7),
.D8 (if_d8),
.D9 (if_d9),
.RDCLK (phy_clk),
.RDEN (phy_rd_en_),
.RESET (ififo_rst),
.WRCLK (iserdes_clkdiv),
.WREN (ififo_wr_enable)
);
end
endgenerate
OUT_FIFO #(
.ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.ARRAY_MODE (L_OF_ARRAY_MODE),
.OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
.SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)
) out_fifo (
.ALMOSTEMPTY (of_a_empty),
.ALMOSTFULL (of_a_full),
.EMPTY (of_empty),
.FULL (of_full),
.Q0 (of_q0),
.Q1 (of_q1),
.Q2 (of_q2),
.Q3 (of_q3),
.Q4 (of_q4),
.Q5 (of_q5),
.Q6 (of_q6),
.Q7 (of_q7),
.Q8 (of_q8),
.Q9 (of_q9),
.D0 (of_d0),
.D1 (of_d1),
.D2 (of_d2),
.D3 (of_d3),
.D4 (of_d4),
.D5 (of_d5),
.D6 (of_d6),
.D7 (of_d7),
.D8 (of_d8),
.D9 (of_d9),
.RDCLK (oserdes_clkdiv),
.RDEN (po_rd_enable),
.RESET (ofifo_rst),
.WRCLK (phy_clk),
.WREN (of_wren_pre)
);
mig_7series_v2_0_ddr_byte_group_io #
(
.PO_DATA_CTL (PO_DATA_CTL),
.BITLANES (BITLANES),
.BITLANES_OUTONLY (BITLANES_OUTONLY),
.OSERDES_DATA_RATE (L_OSERDES_DATA_RATE),
.OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH),
.IODELAY_GRP (IODELAY_GRP),
.IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),
.SYNTHESIS (SYNTHESIS)
)
ddr_byte_group_io
(
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_in (mem_dqs_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.rst (rst),
.oserdes_rst (po_oserdes_rst),
.iserdes_rst (pi_iserdes_rst ),
.iserdes_dout (iserdes_dout),
.dqs_to_phaser (dqs_to_phaser),
.phy_clk (phy_clk),
.iserdes_clk (iserdes_clk),
.iserdes_clkb (!iserdes_clk),
.iserdes_clkdiv (iserdes_clkdiv),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.idelayctrl_refclk (idelayctrl_refclk),
.oserdes_clk (oserdes_clk),
.oserdes_clk_delayed (oserdes_clk_delayed),
.oserdes_clkdiv (oserdes_clkdiv),
.oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),
.oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),
.oserdes_dq (of_dqbus),
.oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]})
);
genvar i;
generate
for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop
if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen
ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
ddr_ck (
.C (oserdes_clk),
.R (1'b0),
.S (),
.D1 (1'b0),
.D2 (1'b1),
.CE (1'b1),
.Q (ddr_ck_out_q[i])
);
OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1]));
end // ddr_ck_gen
else begin : ddr_ck_null
assign ddr_ck_out[i*2+1:i*2] = 2'b0;
end
end // ddr_ck_gen_loop
endgenerate
endmodule // byte_lane
|
// this is the 32 colour colour table
// because this module also supports EHB (extra half brite) mode,
// it actually has a 6bit colour select input
// the 6th bit selects EHB colour while the lower 5 bit select the actual colour register
module denise_colortable
(
input wire clk, // 28MHz clock
input wire clk7_en, // 7MHz clock enable
input wire [ 9-1:1] reg_address_in, // register adress inputs
input wire [ 12-1:0] data_in, // bus data in
input wire [ 8-1:0] select, // colour select input
input wire [ 8-1:0] bplxor, // clut address xor value
input wire [ 3-1:0] bank, // color bank select
input wire loct, // 12-bit pallete select
input wire ehb_en, // EHB enable
output reg [ 24-1:0] rgb // RGB output
);
// register names and adresses
parameter COLORBASE = 9'h180; // colour table base address
// select xor
wire [ 8-1:0] select_xored = select;// ^ bplxor;
// color ram
wire [ 8-1:0] wr_adr = {bank[2:0], reg_address_in[5:1]};
wire wr_en = (reg_address_in[8:6] == COLORBASE[8:6]) && clk7_en;
wire [32-1:0] wr_dat = {4'b0, data_in[11:0], 4'b0, data_in[11:0]};
wire [ 4-1:0] wr_bs = loct ? 4'b0011 : 4'b1111;
wire [ 8-1:0] rd_adr = ehb_en ? {3'b000, select_xored[4:0]} : select_xored;
wire [32-1:0] rd_dat;
reg ehb_sel;
// color lut
denise_colortable_ram_mf clut
(
.clock (clk ),
.enable (1'b1 ),
.wraddress (wr_adr ),
.wren (wr_en ),
.byteena_a (wr_bs ),
.data (wr_dat ),
.rdaddress (rd_adr ),
.q (rd_dat )
);
// register half-brite bit
always @ (posedge clk) begin
ehb_sel <= #1 select_xored[5];
end
// pack color values
wire [12-1:0] color_hi = rd_dat[12-1+16:0+16];
wire [12-1:0] color_lo = rd_dat[12-1+ 0:0+ 0];
wire [24-1:0] color = {color_hi[11:8], color_lo[11:8], color_hi[7:4], color_lo[7:4], color_hi[3:0], color_lo[3:0]};
// extra half brite mode shifter
always @ (*) begin
if (ehb_sel && ehb_en) // half bright, shift every component 1 position to the right
rgb = {1'b0,color[23:17],1'b0,color[15:9],1'b0,color[7:1]};
else // normal colour select
rgb = color;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_dtl_impctl_pullup.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_dtl_impctl_pullup(rclk ,ctu_io_sscan_update ,ctu_global_snap ,
tclk ,ctu_io_sscan_se ,si ,we_csr ,from_csr ,se ,ctu_io_sscan_in ,
hard_reset_n ,clk_dis_l ,vddo ,z ,to_csr ,so_l ,imped_shadow_so ,
deltabit ,pad );
output [7:0] z ;
output [7:0] to_csr ;
input [7:0] from_csr ;
output so_l ;
output imped_shadow_so ;
output deltabit ;
input rclk ;
input ctu_io_sscan_update ;
input ctu_global_snap ;
input tclk ;
input ctu_io_sscan_se ;
input si ;
input we_csr ;
input se ;
input ctu_io_sscan_in ;
input hard_reset_n ;
input clk_dis_l ;
input vddo ;
inout pad ;
supply1 vdd ;
wire [7:0] z_post ;
wire [7:0] d ;
wire [7:0] net097 ;
wire [7:0] net47 ;
wire [7:0] net054 ;
wire clk ;
wire above ;
wire global_reset_n ;
wire sodr_l ;
wire bypass ;
wire updclk ;
wire sos ;
wire net0110 ;
wire clk_en_l ;
wire net081 ;
wire sclk ;
wire avgcntr_rst ;
bw_u1_inv_5x I44_0_ (
.z (net054[7] ),
.a (d[7] ) );
bw_u1_inv_5x I43_2_ (
.z (net097[5] ),
.a (net054[5] ) );
bw_u1_inv_4x I28_1_ (
.z (net47[6] ),
.a (z_post[6] ) );
bw_u1_inv_10x I29_7_ (
.z (z[7] ),
.a (net47[0] ) );
bw_u1_inv_5x I44_1_ (
.z (net054[6] ),
.a (d[6] ) );
bw_u1_inv_5x I43_3_ (
.z (net097[4] ),
.a (net054[4] ) );
bw_u1_inv_4x I28_2_ (
.z (net47[5] ),
.a (z_post[5] ) );
bw_u1_inv_10x I29_0_ (
.z (z[0] ),
.a (net47[7] ) );
bw_io_impctl_dtl_uprcn I241 (
.cbu ({net097[0] ,net097[1] ,net097[2] ,net097[3] ,
net097[4] ,net097[5] ,net097[6] ,net097[7] } ),
.si_l (net081 ),
.so_l (sodr_l ),
.pad (pad ),
.sclk (sclk ),
.vddo (vddo ),
.above (above ),
.clk (clk ),
.se (se ),
.global_reset_n (global_reset_n ) );
bw_u1_inv_5x I44_2_ (
.z (net054[5] ),
.a (d[5] ) );
bw_u1_inv_5x I43_4_ (
.z (net097[3] ),
.a (net054[3] ) );
bw_u1_inv_4x I28_3_ (
.z (net47[4] ),
.a (z_post[4] ) );
bw_u1_inv_10x I29_1_ (
.z (z[1] ),
.a (net47[6] ) );
bw_u1_inv_5x I44_3_ (
.z (net054[4] ),
.a (d[4] ) );
bw_u1_inv_5x I43_5_ (
.z (net097[2] ),
.a (net054[2] ) );
bw_u1_inv_4x I28_4_ (
.z (net47[3] ),
.a (z_post[3] ) );
bw_u1_inv_10x I29_2_ (
.z (z[2] ),
.a (net47[5] ) );
bw_u1_inv_5x I44_4_ (
.z (net054[3] ),
.a (d[3] ) );
bw_u1_inv_5x I43_6_ (
.z (net097[1] ),
.a (net054[1] ) );
bw_u1_inv_4x I28_5_ (
.z (net47[2] ),
.a (z_post[2] ) );
bw_u1_inv_10x I29_3_ (
.z (z[3] ),
.a (net47[4] ) );
bw_io_impctl_smachine_new I23 (
.z_post ({z_post } ),
.from_csr ({from_csr } ),
.to_csr ({to_csr } ),
.d ({d } ),
.deltabit (deltabit ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.updclk (updclk ),
.we_csr (we_csr ),
.l2clk (rclk ),
.ctu_io_sscan_in (ctu_io_sscan_in ),
.above (above ),
.bypass (bypass ),
.config_pmos (vdd ),
.global_reset_n (global_reset_n ),
.hard_reset_n (hard_reset_n ),
.ctu_global_snap (ctu_global_snap ),
.sclk (sclk ),
.avgcntr_rst (avgcntr_rst ),
.so (sos ),
.se (se ),
.si_l (sodr_l ),
.io_ctu_sscan_out (imped_shadow_so ),
.tclk (tclk ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.clk_en_l (clk_en_l ) );
bw_io_impctl_dtl_clkgen I24 (
.se (se ),
.updclk (updclk ),
.clk (clk ),
.so_l (so_l ),
.si_l (sos ),
.synced_upd_imped (ctu_io_sscan_update ),
.avgcntr_rst (avgcntr_rst ),
.bypass (bypass ),
.global_reset_n (global_reset_n ),
.hard_reset_n (hard_reset_n ),
.sclk (sclk ),
.reset_l (vdd ) );
bw_u1_inv_5x I44_5_ (
.z (net054[2] ),
.a (d[2] ) );
bw_u1_inv_5x I43_7_ (
.z (net097[0] ),
.a (net054[0] ) );
bw_u1_inv_4x I28_6_ (
.z (net47[1] ),
.a (z_post[1] ) );
bw_u1_inv_10x I29_4_ (
.z (z[4] ),
.a (net47[3] ) );
bw_u1_ckenbuf_14x I30 (
.clk (clk ),
.rclk (rclk ),
.en_l (clk_en_l ),
.tm_l (net0110 ) );
bw_u1_inv_10x I34 (
.z (clk_en_l ),
.a (clk_dis_l ) );
bw_u1_inv_5x I43_0_ (
.z (net097[7] ),
.a (net054[7] ) );
bw_u1_inv_5x I44_6_ (
.z (net054[1] ),
.a (d[1] ) );
bw_u1_inv_4x I28_7_ (
.z (net47[0] ),
.a (z_post[0] ) );
bw_u1_inv_10x I29_5_ (
.z (z[5] ),
.a (net47[2] ) );
bw_u1_inv_8x I41 (
.z (net081 ),
.a (si ) );
bw_u1_inv_4x I42 (
.z (net0110 ),
.a (se ) );
bw_u1_inv_5x I43_1_ (
.z (net097[6] ),
.a (net054[6] ) );
bw_u1_inv_5x I44_7_ (
.z (net054[0] ),
.a (d[0] ) );
bw_u1_inv_4x I28_0_ (
.z (net47[7] ),
.a (z_post[7] ) );
bw_u1_inv_10x I29_6_ (
.z (z[6] ),
.a (net47[1] ) );
endmodule
|
`timescale 1 ns / 1 ps
//Input clock 125 MHz
module dac_control
(
input clk,
input enable_update,
input enable,
input [7:0]dbA,
input [7:0]dbB,
input [7:0]dbC,
input [7:0]dbD,
output reg [7:0]db,
output wire clr_n,
output wire pd_n,
output reg cs_n,
output reg wr_n,
output reg [1:0]A,
output reg ldac_n
);
reg [7:0] clk_div;
reg clk_int;
always @(posedge clk) begin
clk_div <= clk_div + 1;
clk_int <= (clk_div == 8'HFF);
/* if (clk_div == 8'HFF) */
/* clk_int <= 1; */
/* else */
/* clk_int <= 0; */
end
assign clr_n = enable;
assign pd_n = 1;
reg [7:0]dbA_prev;
reg [7:0]dbB_prev;
reg [7:0]dbC_prev;
reg [7:0]dbD_prev;
reg update_trigger;
always @(posedge clk_int && enable_update) begin
if ((dbA != dbA_prev) || (dbB != dbB_prev) || (dbC != dbC_prev) || (dbD != dbD_prev))
update_trigger <= 1;
else
update_trigger <= 0;
dbA_prev <= dbA;
dbB_prev <= dbB;
dbC_prev <= dbC;
dbD_prev <= dbD;
end
reg [3:0] cntr;
always @(posedge clk_int) begin
if ((update_trigger == 1) || (cntr != 0)) begin
cntr <= (cntr + 1) % 10;
case (cntr)
0 : begin
A <= 2'b00;
db <= dbA;
end
1 :
wr_n <= 1;
2 : begin
A <= 2'b01;
db <= dbB;
wr_n <= 0;
end
3 :
wr_n <= 1;
4 : begin
A <= 2'b10;
db <= dbC;
wr_n <= 0;
end
5 :
wr_n <= 1;
6 : begin
A <= 2'b11;
db <= dbD;
wr_n <= 0;
end
7 :
wr_n <= 1;
8 :
wr_n <= 0;
9 :
ldac_n <= 1;
10 :
ldac_n <= 0;
endcase
end
end
endmodule
|
module EX_MEM(
input Clk,
input stall,
input flush,
input [31:0]Branch_addr_EX,
input [5:0]op_EX,
input [2:0]Condition_EX,
input Branch_EX,
input MemWrite_EX,
input RegWrite_EX,
input MemRead_EX,
input [31:0]MemData_EX,
input [31:0]WBData_EX,
input Less_EX,
input Zero_EX,
input Overflow_EX,
input [4:0]Rd_EX,
output reg [31:0]Branch_addr_MEM,
output reg [5:0]op_MEM,
output reg [2:0]Condition_MEM,
output reg Branch_MEM,
output reg MemWrite_MEM,
output reg RegWrite_MEM,
output reg MemRead_MEM,
output reg [31:0]MemData_MEM,
output reg [31:0]WBData_MEM,
output reg Less_MEM,
output reg Zero_MEM,
output reg Overflow_MEM,
output reg [4:0]Rd_MEM
);
initial
begin
Branch_addr_MEM=32'b0;
op_MEM=6'b0;
Condition_MEM=3'b0;
Branch_MEM=0;
MemWrite_MEM=0;
RegWrite_MEM=0;
MemRead_MEM=0;
MemData_MEM=2'b0;
WBData_MEM=32'b0;
Less_MEM=0;
Zero_MEM=0;
Overflow_MEM=0;
Rd_MEM=5'b0;
end
always @(negedge Clk)begin
if(flush)begin//冲刷，防止出错
op_MEM <= 0;
Condition_MEM <= 0;
Branch_MEM <= 0;
MemWrite_MEM <= 0;
RegWrite_MEM <= 0;
MemRead_MEM <= 0;
MemData_MEM <= 0;
WBData_MEM <= 0;
Less_MEM <= 0;
Zero_MEM <= 0;
Overflow_MEM <= 0;
Rd_MEM <= 0;
end
else if(!stall)begin//如果不是保持就继续向下传递流水
Branch_addr_MEM <= Branch_addr_EX;
op_MEM <= op_EX;
Condition_MEM <= Condition_EX;
Branch_MEM <= Branch_EX;
MemWrite_MEM <= MemWrite_EX;
RegWrite_MEM <= RegWrite_EX;
MemRead_MEM <= MemRead_EX;
MemData_MEM <= MemData_EX;
WBData_MEM <= WBData_EX;
Less_MEM <= Less_EX;
Zero_MEM <= Zero_EX;
Overflow_MEM <= Overflow_EX;
Rd_MEM <= Rd_EX;
end
// 否则就是保持，也即什么赋值也不需要做继续保持
end
endmodule
|
// megafunction wizard: %ALTFP_EXP%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_EXP
// ============================================================
// File Name: fp_exp.v
// Megafunction Name(s):
// ALTFP_EXP
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_exp CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=25 ROUNDING="TO_NEAREST" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 8.1 cbx_altfp_exp 2008:09:02:18:52:52:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_clshift 2008:08:18:00:16:00:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_mult 2008:08:08:14:38:02:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_padd 2008:07:31:17:08:03:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_add_sub 9 lpm_clshift 1 lpm_compare 3 lpm_mult 5 lpm_mux 3 mux21 224 reg 1543
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_exp_altfp_exp_o7d
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes0;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes1;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes2;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes3;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes4;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes5;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes6;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes7;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes8;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes9;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes10;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes11;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes12;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes13;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes14;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes15;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes16;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes17;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes18;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes19;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes20;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes21;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes22;
reg [0:0] distance_overflow_dffe2_23_pipes0;
reg [0:0] distance_overflow_dffe2_23_pipes1;
reg [0:0] distance_overflow_dffe2_23_pipes2;
reg [0:0] distance_overflow_dffe2_23_pipes3;
reg [0:0] distance_overflow_dffe2_23_pipes4;
reg [0:0] distance_overflow_dffe2_23_pipes5;
reg [0:0] distance_overflow_dffe2_23_pipes6;
reg [0:0] distance_overflow_dffe2_23_pipes7;
reg [0:0] distance_overflow_dffe2_23_pipes8;
reg [0:0] distance_overflow_dffe2_23_pipes9;
reg [0:0] distance_overflow_dffe2_23_pipes10;
reg [0:0] distance_overflow_dffe2_23_pipes11;
reg [0:0] distance_overflow_dffe2_23_pipes12;
reg [0:0] distance_overflow_dffe2_23_pipes13;
reg [0:0] distance_overflow_dffe2_23_pipes14;
reg [0:0] distance_overflow_dffe2_23_pipes15;
reg [0:0] distance_overflow_dffe2_23_pipes16;
reg [0:0] distance_overflow_dffe2_23_pipes17;
reg [0:0] distance_overflow_dffe2_23_pipes18;
reg [0:0] distance_overflow_dffe2_23_pipes19;
reg [0:0] distance_overflow_dffe2_23_pipes20;
reg [0:0] distance_overflow_dffe2_23_pipes21;
reg [0:0] distance_overflow_dffe2_23_pipes22;
reg [10:0] exp_value_b4_bias_dffe_0;
reg [10:0] exp_value_b4_bias_dffe_1;
reg [10:0] exp_value_b4_bias_dffe_10;
reg [10:0] exp_value_b4_bias_dffe_11;
reg [10:0] exp_value_b4_bias_dffe_12;
reg [10:0] exp_value_b4_bias_dffe_13;
reg [10:0] exp_value_b4_bias_dffe_14;
reg [10:0] exp_value_b4_bias_dffe_15;
reg [10:0] exp_value_b4_bias_dffe_16;
reg [10:0] exp_value_b4_bias_dffe_17;
reg [10:0] exp_value_b4_bias_dffe_18;
reg [10:0] exp_value_b4_bias_dffe_2;
reg [10:0] exp_value_b4_bias_dffe_3;
reg [10:0] exp_value_b4_bias_dffe_4;
reg [10:0] exp_value_b4_bias_dffe_5;
reg [10:0] exp_value_b4_bias_dffe_6;
reg [10:0] exp_value_b4_bias_dffe_7;
reg [10:0] exp_value_b4_bias_dffe_8;
reg [10:0] exp_value_b4_bias_dffe_9;
reg [11:0] exp_value_dffe1;
reg extra_ln2_dffe_0;
reg extra_ln2_dffe_1;
reg extra_ln2_dffe_10;
reg extra_ln2_dffe_11;
reg extra_ln2_dffe_2;
reg extra_ln2_dffe_3;
reg extra_ln2_dffe_4;
reg extra_ln2_dffe_5;
reg extra_ln2_dffe_6;
reg extra_ln2_dffe_7;
reg extra_ln2_dffe_8;
reg extra_ln2_dffe_9;
reg [51:0] fraction_dffe1;
reg [0:0] input_is_infinity_24_pipes0;
reg [0:0] input_is_infinity_24_pipes1;
reg [0:0] input_is_infinity_24_pipes2;
reg [0:0] input_is_infinity_24_pipes3;
reg [0:0] input_is_infinity_24_pipes4;
reg [0:0] input_is_infinity_24_pipes5;
reg [0:0] input_is_infinity_24_pipes6;
reg [0:0] input_is_infinity_24_pipes7;
reg [0:0] input_is_infinity_24_pipes8;
reg [0:0] input_is_infinity_24_pipes9;
reg [0:0] input_is_infinity_24_pipes10;
reg [0:0] input_is_infinity_24_pipes11;
reg [0:0] input_is_infinity_24_pipes12;
reg [0:0] input_is_infinity_24_pipes13;
reg [0:0] input_is_infinity_24_pipes14;
reg [0:0] input_is_infinity_24_pipes15;
reg [0:0] input_is_infinity_24_pipes16;
reg [0:0] input_is_infinity_24_pipes17;
reg [0:0] input_is_infinity_24_pipes18;
reg [0:0] input_is_infinity_24_pipes19;
reg [0:0] input_is_infinity_24_pipes20;
reg [0:0] input_is_infinity_24_pipes21;
reg [0:0] input_is_infinity_24_pipes22;
reg [0:0] input_is_infinity_24_pipes23;
reg [0:0] input_is_nan_24_pipes0;
reg [0:0] input_is_nan_24_pipes1;
reg [0:0] input_is_nan_24_pipes2;
reg [0:0] input_is_nan_24_pipes3;
reg [0:0] input_is_nan_24_pipes4;
reg [0:0] input_is_nan_24_pipes5;
reg [0:0] input_is_nan_24_pipes6;
reg [0:0] input_is_nan_24_pipes7;
reg [0:0] input_is_nan_24_pipes8;
reg [0:0] input_is_nan_24_pipes9;
reg [0:0] input_is_nan_24_pipes10;
reg [0:0] input_is_nan_24_pipes11;
reg [0:0] input_is_nan_24_pipes12;
reg [0:0] input_is_nan_24_pipes13;
reg [0:0] input_is_nan_24_pipes14;
reg [0:0] input_is_nan_24_pipes15;
reg [0:0] input_is_nan_24_pipes16;
reg [0:0] input_is_nan_24_pipes17;
reg [0:0] input_is_nan_24_pipes18;
reg [0:0] input_is_nan_24_pipes19;
reg [0:0] input_is_nan_24_pipes20;
reg [0:0] input_is_nan_24_pipes21;
reg [0:0] input_is_nan_24_pipes22;
reg [0:0] input_is_nan_24_pipes23;
reg [0:0] input_is_zero_24_pipes0;
reg [0:0] input_is_zero_24_pipes1;
reg [0:0] input_is_zero_24_pipes2;
reg [0:0] input_is_zero_24_pipes3;
reg [0:0] input_is_zero_24_pipes4;
reg [0:0] input_is_zero_24_pipes5;
reg [0:0] input_is_zero_24_pipes6;
reg [0:0] input_is_zero_24_pipes7;
reg [0:0] input_is_zero_24_pipes8;
reg [0:0] input_is_zero_24_pipes9;
reg [0:0] input_is_zero_24_pipes10;
reg [0:0] input_is_zero_24_pipes11;
reg [0:0] input_is_zero_24_pipes12;
reg [0:0] input_is_zero_24_pipes13;
reg [0:0] input_is_zero_24_pipes14;
reg [0:0] input_is_zero_24_pipes15;
reg [0:0] input_is_zero_24_pipes16;
reg [0:0] input_is_zero_24_pipes17;
reg [0:0] input_is_zero_24_pipes18;
reg [0:0] input_is_zero_24_pipes19;
reg [0:0] input_is_zero_24_pipes20;
reg [0:0] input_is_zero_24_pipes21;
reg [0:0] input_is_zero_24_pipes22;
reg [0:0] input_is_zero_24_pipes23;
reg man_overflow_dffe15;
reg [119:0] man_prod_dffe14;
reg [51:0] man_round_dffe15;
reg [62:0] result_pipe_dffe16;
reg round_up_dffe15;
reg [0:0] sign_dffe0;
reg [0:0] sign_dffe1;
reg [0:0] sign_dffe2;
reg [0:0] sign_dffe3;
reg [0:0] sign_dffe4;
reg [0:0] sign_dffe5;
reg [0:0] sign_dffe6;
reg [0:0] sign_dffe7;
reg [0:0] sign_dffe8;
reg [0:0] sign_dffe9;
reg [0:0] sign_dffe10;
reg [0:0] sign_dffe11;
reg [0:0] sign_dffe12;
reg [0:0] sign_dffe13;
reg [0:0] sign_dffe14;
reg [0:0] sign_dffe15;
reg [0:0] sign_dffe16;
reg [0:0] sign_dffe17;
reg [0:0] sign_dffe18;
reg [0:0] sign_dffe19;
reg [0:0] sign_dffe20;
reg [0:0] sign_dffe21;
reg [0:0] sign_dffe22;
reg [0:0] sign_dffe23;
reg [0:0] tbl1_compare_dffe11_10_pipes0;
reg [0:0] tbl1_compare_dffe11_10_pipes1;
reg [0:0] tbl1_compare_dffe11_10_pipes2;
reg [0:0] tbl1_compare_dffe11_10_pipes3;
reg [0:0] tbl1_compare_dffe11_10_pipes4;
reg [0:0] tbl1_compare_dffe11_10_pipes5;
reg [0:0] tbl1_compare_dffe11_10_pipes6;
reg [0:0] tbl1_compare_dffe11_10_pipes7;
reg [0:0] tbl1_compare_dffe11_10_pipes8;
reg [0:0] tbl1_compare_dffe11_10_pipes9;
reg [59:0] tbl1_tbl2_prod_dffe12;
reg [59:0] tbl3_taylor_prod_dffe12;
reg [69:0] x_fixed_dffe_0;
reg [69:0] x_fixed_dffe_1;
reg [69:0] x_fixed_dffe_2;
reg [69:0] x_fixed_dffe_3;
reg [69:0] x_fixed_dffe_4;
reg [69:0] x_fixed_dffe_5;
reg [69:0] x_fixed_dffe_6;
reg [69:0] xf_pre_2_dffe10;
reg [69:0] xf_pre_dffe9;
reg [10:0] xi_exp_value_dffe4;
reg [80:0] xi_ln2_prod_dffe7;
reg [26:0] xi_prod_dffe3;
wire [11:0] wire_exp_minus_bias_result;
wire [11:0] wire_exp_value_add_bias_result;
wire [11:0] wire_exp_value_man_over_result;
wire [10:0] wire_invert_exp_value_result;
wire [51:0] wire_man_round_result;
wire [59:0] wire_one_minus_xf_result;
wire [69:0] wire_x_fixed_minus_xiln2_result;
wire [59:0] wire_xf_minus_ln2_result;
wire [10:0] wire_xi_add_one_result;
wire [69:0] wire_rbarrel_shift_result;
wire wire_distance_overflow_comp_agb;
wire wire_tbl1_compare_ageb;
wire wire_underflow_compare_agb;
wire [119:0] wire_man_prod_result;
wire [121:0] wire_tbl1_tbl2_prod_result;
wire [119:0] wire_tbl3_taylor_prod_result;
wire [80:0] wire_xi_ln2_prod_result;
wire [26:0] wire_xi_prod_result;
wire [60:0] wire_table_one_result;
wire [41:0] wire_table_three_result;
wire [50:0] wire_table_two_result;
wire wire_cin_to_bias_dataout;
wire [10:0]wire_exp_result_mux_prea_dataout;
wire [10:0]wire_exp_value_b4_biasa_dataout;
wire [6:0]wire_exp_value_selecta_dataout;
wire [10:0]wire_exp_value_to_compare_muxa_dataout;
wire [10:0]wire_exp_value_to_ln2a_dataout;
wire [59:0]wire_extra_ln2_muxa_dataout;
wire [51:0]wire_man_result_muxa_dataout;
wire [59:0]wire_xf_muxa_dataout;
wire aclr;
wire [8:0] addr_val_more_than_one;
wire [69:0] barrel_shifter_data;
wire [6:0] barrel_shifter_distance;
wire barrel_shifter_underflow;
wire barrel_shifter_underflow_wi;
wire distance_overflow;
wire [10:0] distance_overflow_val_w;
wire distance_overflow_wi;
wire [10:0] exp_bias;
wire [10:0] exp_bias_all_ones_w;
wire [10:0] exp_data_all_one_w;
wire [10:0] exp_data_not_zero_w;
wire [10:0] exp_invert;
wire [10:0] exp_one;
wire [10:0] exp_out_all_one_w;
wire [10:0] exp_out_not_zero_w;
wire [10:0] exp_result_out;
wire [10:0] exp_result_w;
wire [11:0] exp_value;
wire [11:0] exp_value_wi;
wire [11:0] exp_value_wo;
wire [10:0] exp_w;
wire extra_ln2;
wire [51:0] fraction;
wire [51:0] fraction_wi;
wire [51:0] fraction_wo;
wire gnd_w;
wire guard_bit;
wire input_is_infinity_wi;
wire input_is_infinity_wo;
wire input_is_nan_wi;
wire input_is_nan_wo;
wire input_is_zero_wi;
wire input_is_zero_wo;
wire [69:0] ln2_w;
wire [51:0] man_data_not_zero_w;
wire man_overflow;
wire man_overflow_wi;
wire man_overflow_wo;
wire [119:0] man_prod_result;
wire [119:0] man_prod_shifted;
wire [119:0] man_prod_wi;
wire [119:0] man_prod_wire;
wire [119:0] man_prod_wo;
wire [51:0] man_result_all_ones;
wire [51:0] man_result_w;
wire [51:0] man_round_wi;
wire [51:0] man_round_wo;
wire nan_w;
wire negative_infinity;
wire [11:0] one_over_ln2_w;
wire overflow_w;
wire positive_infinity;
wire [62:0] result_pipe_wi;
wire [62:0] result_pipe_wo;
wire result_underflow_w;
wire round_bit;
wire round_up;
wire round_up_wi;
wire round_up_wo;
wire shifted_value;
wire sign_w;
wire [4:0] sticky_bits;
wire [31231:0] table_one_data;
wire [60:0] table_one_out;
wire [21503:0] table_three_data;
wire [60:0] table_three_out;
wire [41:0] table_three_out_tmp;
wire [26111:0] table_two_data;
wire [60:0] table_two_out;
wire [50:0] table_two_out_tmp;
wire tbl1_compare_wi;
wire tbl1_compare_wo;
wire [59:0] tbl1_tbl2_prod_wi;
wire [59:0] tbl1_tbl2_prod_wo;
wire [59:0] tbl3_taylor_prod_wi;
wire [59:0] tbl3_taylor_prod_wo;
wire [10:0] underflow_compare_val_w;
wire underflow_w;
wire [69:0] x_fixed;
wire [59:0] xf;
wire [69:0] xf_pre;
wire [69:0] xf_pre_2_wi;
wire [69:0] xf_pre_2_wo;
wire [69:0] xf_pre_wi;
wire [69:0] xf_pre_wo;
wire [10:0] xi_exp_value;
wire [10:0] xi_exp_value_wi;
wire [10:0] xi_exp_value_wo;
wire [80:0] xi_ln2_prod_wi;
wire [80:0] xi_ln2_prod_wo;
wire [26:0] xi_prod_wi;
wire [26:0] xi_prod_wo;
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes0 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes0 <= barrel_shifter_underflow_wi;
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes1 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes1 <= barrel_shifter_underflow_dffe2_23_pipes0[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes2 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes2 <= barrel_shifter_underflow_dffe2_23_pipes1[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes3 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes3 <= barrel_shifter_underflow_dffe2_23_pipes2[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes4 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes4 <= barrel_shifter_underflow_dffe2_23_pipes3[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes5 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes5 <= barrel_shifter_underflow_dffe2_23_pipes4[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes6 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes6 <= barrel_shifter_underflow_dffe2_23_pipes5[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes7 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes7 <= barrel_shifter_underflow_dffe2_23_pipes6[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes8 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes8 <= barrel_shifter_underflow_dffe2_23_pipes7[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes9 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes9 <= barrel_shifter_underflow_dffe2_23_pipes8[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes10 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes10 <= barrel_shifter_underflow_dffe2_23_pipes9[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes11 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes11 <= barrel_shifter_underflow_dffe2_23_pipes10[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes12 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes12 <= barrel_shifter_underflow_dffe2_23_pipes11[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes13 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes13 <= barrel_shifter_underflow_dffe2_23_pipes12[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes14 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes14 <= barrel_shifter_underflow_dffe2_23_pipes13[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes15 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes15 <= barrel_shifter_underflow_dffe2_23_pipes14[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes16 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes16 <= barrel_shifter_underflow_dffe2_23_pipes15[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes17 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes17 <= barrel_shifter_underflow_dffe2_23_pipes16[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes18 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes18 <= barrel_shifter_underflow_dffe2_23_pipes17[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes19 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes19 <= barrel_shifter_underflow_dffe2_23_pipes18[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes20 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes20 <= barrel_shifter_underflow_dffe2_23_pipes19[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes21 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes21 <= barrel_shifter_underflow_dffe2_23_pipes20[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes22 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes22 <= barrel_shifter_underflow_dffe2_23_pipes21[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes0 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes0 <= distance_overflow_wi;
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes1 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes1 <= distance_overflow_dffe2_23_pipes0[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes2 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes2 <= distance_overflow_dffe2_23_pipes1[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes3 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes3 <= distance_overflow_dffe2_23_pipes2[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes4 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes4 <= distance_overflow_dffe2_23_pipes3[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes5 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes5 <= distance_overflow_dffe2_23_pipes4[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes6 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes6 <= distance_overflow_dffe2_23_pipes5[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes7 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes7 <= distance_overflow_dffe2_23_pipes6[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes8 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes8 <= distance_overflow_dffe2_23_pipes7[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes9 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes9 <= distance_overflow_dffe2_23_pipes8[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes10 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes10 <= distance_overflow_dffe2_23_pipes9[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes11 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes11 <= distance_overflow_dffe2_23_pipes10[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes12 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes12 <= distance_overflow_dffe2_23_pipes11[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes13 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes13 <= distance_overflow_dffe2_23_pipes12[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes14 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes14 <= distance_overflow_dffe2_23_pipes13[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes15 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes15 <= distance_overflow_dffe2_23_pipes14[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes16 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes16 <= distance_overflow_dffe2_23_pipes15[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes17 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes17 <= distance_overflow_dffe2_23_pipes16[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes18 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes18 <= distance_overflow_dffe2_23_pipes17[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes19 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes19 <= distance_overflow_dffe2_23_pipes18[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes20 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes20 <= distance_overflow_dffe2_23_pipes19[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes21 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes21 <= distance_overflow_dffe2_23_pipes20[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes22 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes22 <= distance_overflow_dffe2_23_pipes21[0:0];
// synopsys translate_off
initial
exp_value_b4_bias_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_0 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_0 <= wire_exp_value_b4_biasa_dataout;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_1 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_1 <= exp_value_b4_bias_dffe_0;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_10 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_10 <= exp_value_b4_bias_dffe_9;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_11 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_11 <= exp_value_b4_bias_dffe_10;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_12 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_12 <= exp_value_b4_bias_dffe_11;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_13 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_13 <= exp_value_b4_bias_dffe_12;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_14 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_14 <= exp_value_b4_bias_dffe_13;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_15 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_15 <= exp_value_b4_bias_dffe_14;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_16 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_16 <= exp_value_b4_bias_dffe_15;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_17 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_17 <= exp_value_b4_bias_dffe_16;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_18 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_18 <= exp_value_b4_bias_dffe_17;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_2 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_2 <= exp_value_b4_bias_dffe_1;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_3 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_3 <= exp_value_b4_bias_dffe_2;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_4 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_4 <= exp_value_b4_bias_dffe_3;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_5 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_5 <= exp_value_b4_bias_dffe_4;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_6 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_6 <= exp_value_b4_bias_dffe_5;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_7 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_7 <= exp_value_b4_bias_dffe_6;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_8 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_8 <= exp_value_b4_bias_dffe_7;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_9 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_9 <= exp_value_b4_bias_dffe_8;
// synopsys translate_off
initial
exp_value_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_dffe1 <= 12'b0;
else if (clk_en == 1'b1) exp_value_dffe1 <= exp_value_wi;
// synopsys translate_off
initial
extra_ln2_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_0 <= extra_ln2;
// synopsys translate_off
initial
extra_ln2_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_1 <= extra_ln2_dffe_0;
// synopsys translate_off
initial
extra_ln2_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_10 <= extra_ln2_dffe_9;
// synopsys translate_off
initial
extra_ln2_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_11 <= extra_ln2_dffe_10;
// synopsys translate_off
initial
extra_ln2_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_2 <= extra_ln2_dffe_1;
// synopsys translate_off
initial
extra_ln2_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_3 <= extra_ln2_dffe_2;
// synopsys translate_off
initial
extra_ln2_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_4 <= extra_ln2_dffe_3;
// synopsys translate_off
initial
extra_ln2_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_5 <= extra_ln2_dffe_4;
// synopsys translate_off
initial
extra_ln2_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_6 <= extra_ln2_dffe_5;
// synopsys translate_off
initial
extra_ln2_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_7 <= extra_ln2_dffe_6;
// synopsys translate_off
initial
extra_ln2_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_8 <= extra_ln2_dffe_7;
// synopsys translate_off
initial
extra_ln2_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_9 <= extra_ln2_dffe_8;
// synopsys translate_off
initial
fraction_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) fraction_dffe1 <= 52'b0;
else if (clk_en == 1'b1) fraction_dffe1 <= fraction_wi;
// synopsys translate_off
initial
input_is_infinity_24_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes0 <= input_is_infinity_wi;
// synopsys translate_off
initial
input_is_infinity_24_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes1 <= input_is_infinity_24_pipes0[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes2 <= input_is_infinity_24_pipes1[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes3 <= input_is_infinity_24_pipes2[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes4 <= input_is_infinity_24_pipes3[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes5 <= input_is_infinity_24_pipes4[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes6 <= input_is_infinity_24_pipes5[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes7 <= input_is_infinity_24_pipes6[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes8 <= input_is_infinity_24_pipes7[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes9 <= input_is_infinity_24_pipes8[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes10 <= input_is_infinity_24_pipes9[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes11 <= input_is_infinity_24_pipes10[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes12 <= input_is_infinity_24_pipes11[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes13 <= input_is_infinity_24_pipes12[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes14 <= input_is_infinity_24_pipes13[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes15 <= input_is_infinity_24_pipes14[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes16 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes16 <= input_is_infinity_24_pipes15[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes17 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes17 <= input_is_infinity_24_pipes16[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes18 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes18 <= input_is_infinity_24_pipes17[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes19 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes19 <= input_is_infinity_24_pipes18[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes20 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes20 <= input_is_infinity_24_pipes19[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes21 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes21 <= input_is_infinity_24_pipes20[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes22 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes22 <= input_is_infinity_24_pipes21[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes23 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes23 <= input_is_infinity_24_pipes22[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes0 <= input_is_nan_wi;
// synopsys translate_off
initial
input_is_nan_24_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes1 <= input_is_nan_24_pipes0[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes2 <= input_is_nan_24_pipes1[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes3 <= input_is_nan_24_pipes2[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes4 <= input_is_nan_24_pipes3[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes5 <= input_is_nan_24_pipes4[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes6 <= input_is_nan_24_pipes5[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes7 <= input_is_nan_24_pipes6[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes8 <= input_is_nan_24_pipes7[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes9 <= input_is_nan_24_pipes8[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes10 <= input_is_nan_24_pipes9[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes11 <= input_is_nan_24_pipes10[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes12 <= input_is_nan_24_pipes11[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes13 <= input_is_nan_24_pipes12[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes14 <= input_is_nan_24_pipes13[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes15 <= input_is_nan_24_pipes14[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes16 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes16 <= input_is_nan_24_pipes15[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes17 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes17 <= input_is_nan_24_pipes16[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes18 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes18 <= input_is_nan_24_pipes17[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes19 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes19 <= input_is_nan_24_pipes18[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes20 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes20 <= input_is_nan_24_pipes19[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes21 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes21 <= input_is_nan_24_pipes20[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes22 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes22 <= input_is_nan_24_pipes21[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes23 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes23 <= input_is_nan_24_pipes22[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes0 <= input_is_zero_wi;
// synopsys translate_off
initial
input_is_zero_24_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes1 <= input_is_zero_24_pipes0[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes2 <= input_is_zero_24_pipes1[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes3 <= input_is_zero_24_pipes2[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes4 <= input_is_zero_24_pipes3[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes5 <= input_is_zero_24_pipes4[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes6 <= input_is_zero_24_pipes5[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes7 <= input_is_zero_24_pipes6[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes8 <= input_is_zero_24_pipes7[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes9 <= input_is_zero_24_pipes8[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes10 <= input_is_zero_24_pipes9[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes11 <= input_is_zero_24_pipes10[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes12 <= input_is_zero_24_pipes11[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes13 <= input_is_zero_24_pipes12[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes14 <= input_is_zero_24_pipes13[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes15 <= input_is_zero_24_pipes14[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes16 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes16 <= input_is_zero_24_pipes15[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes17 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes17 <= input_is_zero_24_pipes16[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes18 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes18 <= input_is_zero_24_pipes17[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes19 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes19 <= input_is_zero_24_pipes18[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes20 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes20 <= input_is_zero_24_pipes19[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes21 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes21 <= input_is_zero_24_pipes20[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes22 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes22 <= input_is_zero_24_pipes21[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes23 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes23 <= input_is_zero_24_pipes22[0:0];
// synopsys translate_off
initial
man_overflow_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_overflow_dffe15 <= 1'b0;
else if (clk_en == 1'b1) man_overflow_dffe15 <= man_overflow_wi;
// synopsys translate_off
initial
man_prod_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_prod_dffe14 <= 120'b0;
else if (clk_en == 1'b1) man_prod_dffe14 <= man_prod_wi;
// synopsys translate_off
initial
man_round_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_dffe15 <= 52'b0;
else if (clk_en == 1'b1) man_round_dffe15 <= man_round_wi;
// synopsys translate_off
initial
result_pipe_dffe16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_pipe_dffe16 <= 63'b0;
else if (clk_en == 1'b1) result_pipe_dffe16 <= result_pipe_wi;
// synopsys translate_off
initial
round_up_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_up_dffe15 <= 1'b0;
else if (clk_en == 1'b1) round_up_dffe15 <= round_up_wi;
// synopsys translate_off
initial
sign_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe0 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe0 <= sign_w;
// synopsys translate_off
initial
sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe1 <= sign_dffe0[0:0];
// synopsys translate_off
initial
sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe2 <= sign_dffe1[0:0];
// synopsys translate_off
initial
sign_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe3 <= sign_dffe2[0:0];
// synopsys translate_off
initial
sign_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe4 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe4 <= sign_dffe3[0:0];
// synopsys translate_off
initial
sign_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe5 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe5 <= sign_dffe4[0:0];
// synopsys translate_off
initial
sign_dffe6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe6 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe6 <= sign_dffe5[0:0];
// synopsys translate_off
initial
sign_dffe7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe7 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe7 <= sign_dffe6[0:0];
// synopsys translate_off
initial
sign_dffe8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe8 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe8 <= sign_dffe7[0:0];
// synopsys translate_off
initial
sign_dffe9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe9 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe9 <= sign_dffe8[0:0];
// synopsys translate_off
initial
sign_dffe10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe10 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe10 <= sign_dffe9[0:0];
// synopsys translate_off
initial
sign_dffe11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe11 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe11 <= sign_dffe10[0:0];
// synopsys translate_off
initial
sign_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe12 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe12 <= sign_dffe11[0:0];
// synopsys translate_off
initial
sign_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe13 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe13 <= sign_dffe12[0:0];
// synopsys translate_off
initial
sign_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe14 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe14 <= sign_dffe13[0:0];
// synopsys translate_off
initial
sign_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe15 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe15 <= sign_dffe14[0:0];
// synopsys translate_off
initial
sign_dffe16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe16 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe16 <= sign_dffe15[0:0];
// synopsys translate_off
initial
sign_dffe17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe17 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe17 <= sign_dffe16[0:0];
// synopsys translate_off
initial
sign_dffe18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe18 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe18 <= sign_dffe17[0:0];
// synopsys translate_off
initial
sign_dffe19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe19 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe19 <= sign_dffe18[0:0];
// synopsys translate_off
initial
sign_dffe20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe20 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe20 <= sign_dffe19[0:0];
// synopsys translate_off
initial
sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe21 <= sign_dffe20[0:0];
// synopsys translate_off
initial
sign_dffe22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe22 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe22 <= sign_dffe21[0:0];
// synopsys translate_off
initial
sign_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe23 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe23 <= sign_dffe22[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes0 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes0 <= tbl1_compare_wi;
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes1 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes1 <= tbl1_compare_dffe11_10_pipes0[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes2 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes2 <= tbl1_compare_dffe11_10_pipes1[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes3 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes3 <= tbl1_compare_dffe11_10_pipes2[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes4 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes4 <= tbl1_compare_dffe11_10_pipes3[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes5 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes5 <= tbl1_compare_dffe11_10_pipes4[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes6 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes6 <= tbl1_compare_dffe11_10_pipes5[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes7 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes7 <= tbl1_compare_dffe11_10_pipes6[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes8 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes8 <= tbl1_compare_dffe11_10_pipes7[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes9 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes9 <= tbl1_compare_dffe11_10_pipes8[0:0];
// synopsys translate_off
initial
tbl1_tbl2_prod_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_tbl2_prod_dffe12 <= 60'b0;
else if (clk_en == 1'b1) tbl1_tbl2_prod_dffe12 <= tbl1_tbl2_prod_wi;
// synopsys translate_off
initial
tbl3_taylor_prod_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl3_taylor_prod_dffe12 <= 60'b0;
else if (clk_en == 1'b1) tbl3_taylor_prod_dffe12 <= tbl3_taylor_prod_wi;
// synopsys translate_off
initial
x_fixed_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_0 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_0 <= x_fixed;
// synopsys translate_off
initial
x_fixed_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_1 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_1 <= x_fixed_dffe_0;
// synopsys translate_off
initial
x_fixed_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_2 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_2 <= x_fixed_dffe_1;
// synopsys translate_off
initial
x_fixed_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_3 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_3 <= x_fixed_dffe_2;
// synopsys translate_off
initial
x_fixed_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_4 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_4 <= x_fixed_dffe_3;
// synopsys translate_off
initial
x_fixed_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_5 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_5 <= x_fixed_dffe_4;
// synopsys translate_off
initial
x_fixed_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_6 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_6 <= x_fixed_dffe_5;
// synopsys translate_off
initial
xf_pre_2_dffe10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xf_pre_2_dffe10 <= 70'b0;
else if (clk_en == 1'b1) xf_pre_2_dffe10 <= xf_pre_2_wi;
// synopsys translate_off
initial
xf_pre_dffe9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xf_pre_dffe9 <= 70'b0;
else if (clk_en == 1'b1) xf_pre_dffe9 <= xf_pre_wi;
// synopsys translate_off
initial
xi_exp_value_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_exp_value_dffe4 <= 11'b0;
else if (clk_en == 1'b1) xi_exp_value_dffe4 <= xi_exp_value_wi;
// synopsys translate_off
initial
xi_ln2_prod_dffe7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_ln2_prod_dffe7 <= 81'b0;
else if (clk_en == 1'b1) xi_ln2_prod_dffe7 <= xi_ln2_prod_wi;
// synopsys translate_off
initial
xi_prod_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_prod_dffe3 <= 27'b0;
else if (clk_en == 1'b1) xi_prod_dffe3 <= xi_prod_wi;
lpm_add_sub exp_minus_bias
(
.cout(),
.dataa({1'b0, exp_w}),
.datab({1'b0, exp_bias}),
.overflow(),
.result(wire_exp_minus_bias_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
exp_minus_bias.lpm_direction = "SUB",
exp_minus_bias.lpm_representation = "SIGNED",
exp_minus_bias.lpm_width = 12,
exp_minus_bias.lpm_type = "lpm_add_sub";
lpm_add_sub exp_value_add_bias
(
.aclr(aclr),
.cin(wire_cin_to_bias_dataout),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b0, exp_value_b4_bias_dffe_18}),
.datab({1'b0, exp_bias[10:1], (~ extra_ln2_dffe_11)}),
.overflow(),
.result(wire_exp_value_add_bias_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
exp_value_add_bias.lpm_direction = "ADD",
exp_value_add_bias.lpm_pipeline = 1,
exp_value_add_bias.lpm_representation = "SIGNED",
exp_value_add_bias.lpm_width = 12,
exp_value_add_bias.lpm_type = "lpm_add_sub";
lpm_add_sub exp_value_man_over
(
.cout(),
.dataa(wire_exp_value_add_bias_result),
.datab({11'b00000000000, man_overflow_wo}),
.overflow(),
.result(wire_exp_value_man_over_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
exp_value_man_over.lpm_direction = "ADD",
exp_value_man_over.lpm_representation = "SIGNED",
exp_value_man_over.lpm_width = 12,
exp_value_man_over.lpm_type = "lpm_add_sub";
lpm_add_sub invert_exp_value
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({11{1'b0}}),
.datab(exp_value[10:0]),
.overflow(),
.result(wire_invert_exp_value_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
invert_exp_value.lpm_direction = "SUB",
invert_exp_value.lpm_pipeline = 1,
invert_exp_value.lpm_representation = "SIGNED",
invert_exp_value.lpm_width = 11,
invert_exp_value.lpm_type = "lpm_add_sub";
lpm_add_sub man_round
(
.cout(),
.dataa(man_round_wo),
.datab({51'b000000000000000000000000000000000000000000000000000, round_up_wo}),
.overflow(),
.result(wire_man_round_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
man_round.lpm_direction = "ADD",
man_round.lpm_representation = "SIGNED",
man_round.lpm_width = 52,
man_round.lpm_type = "lpm_add_sub";
lpm_add_sub one_minus_xf
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b1, 59'b00000000000000000000000000000000000000000000000000000000000}),
.datab(wire_extra_ln2_muxa_dataout),
.overflow(),
.result(wire_one_minus_xf_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
one_minus_xf.lpm_direction = "SUB",
one_minus_xf.lpm_pipeline = 1,
one_minus_xf.lpm_representation = "SIGNED",
one_minus_xf.lpm_width = 60,
one_minus_xf.lpm_type = "lpm_add_sub";
lpm_add_sub x_fixed_minus_xiln2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(x_fixed_dffe_6),
.datab({1'b0, xi_ln2_prod_wo[80:12]}),
.overflow(),
.result(wire_x_fixed_minus_xiln2_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
x_fixed_minus_xiln2.lpm_direction = "SUB",
x_fixed_minus_xiln2.lpm_pipeline = 1,
x_fixed_minus_xiln2.lpm_representation = "SIGNED",
x_fixed_minus_xiln2.lpm_width = 70,
x_fixed_minus_xiln2.lpm_type = "lpm_add_sub";
lpm_add_sub xf_minus_ln2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(xf_pre[59:0]),
.datab({2'b00, ln2_w[69:12]}),
.overflow(),
.result(wire_xf_minus_ln2_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
xf_minus_ln2.lpm_direction = "SUB",
xf_minus_ln2.lpm_pipeline = 1,
xf_minus_ln2.lpm_representation = "SIGNED",
xf_minus_ln2.lpm_width = 60,
xf_minus_ln2.lpm_type = "lpm_add_sub";
lpm_add_sub xi_add_one
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(xi_exp_value),
.datab(11'b00000000001),
.overflow(),
.result(wire_xi_add_one_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
xi_add_one.lpm_direction = "ADD",
xi_add_one.lpm_pipeline = 1,
xi_add_one.lpm_representation = "SIGNED",
xi_add_one.lpm_width = 11,
xi_add_one.lpm_type = "lpm_add_sub";
lpm_clshift rbarrel_shift
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(barrel_shifter_data),
.direction(exp_value_wo[11]),
.distance(barrel_shifter_distance),
.overflow(),
.result(wire_rbarrel_shift_result),
.underflow());
defparam
rbarrel_shift.lpm_pipeline = 2,
rbarrel_shift.lpm_shifttype = "LOGICAL",
rbarrel_shift.lpm_width = 70,
rbarrel_shift.lpm_widthdist = 7,
rbarrel_shift.lpm_type = "lpm_clshift";
lpm_compare distance_overflow_comp
(
.aeb(),
.agb(wire_distance_overflow_comp_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_exp_value_to_compare_muxa_dataout),
.datab(distance_overflow_val_w)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
distance_overflow_comp.lpm_representation = "UNSIGNED",
distance_overflow_comp.lpm_width = 11,
distance_overflow_comp.lpm_type = "lpm_compare";
lpm_compare tbl1_compare
(
.aeb(),
.agb(),
.ageb(wire_tbl1_compare_ageb),
.alb(),
.aleb(),
.aneb(),
.dataa(xf[57:49]),
.datab(addr_val_more_than_one)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
tbl1_compare.lpm_representation = "UNSIGNED",
tbl1_compare.lpm_width = 9,
tbl1_compare.lpm_type = "lpm_compare";
lpm_compare underflow_compare
(
.aeb(),
.agb(wire_underflow_compare_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_exp_value_to_compare_muxa_dataout),
.datab(underflow_compare_val_w)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
underflow_compare.lpm_representation = "UNSIGNED",
underflow_compare.lpm_width = 11,
underflow_compare.lpm_type = "lpm_compare";
lpm_mult man_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(tbl1_tbl2_prod_wo),
.datab(tbl3_taylor_prod_wo),
.result(wire_man_prod_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
man_prod.lpm_pipeline = 4,
man_prod.lpm_representation = "UNSIGNED",
man_prod.lpm_widtha = 60,
man_prod.lpm_widthb = 60,
man_prod.lpm_widthp = 120,
man_prod.lpm_type = "lpm_mult",
man_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult tbl1_tbl2_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(table_one_out),
.datab(table_two_out),
.result(wire_tbl1_tbl2_prod_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
tbl1_tbl2_prod.lpm_pipeline = 4,
tbl1_tbl2_prod.lpm_representation = "UNSIGNED",
tbl1_tbl2_prod.lpm_widtha = 61,
tbl1_tbl2_prod.lpm_widthb = 61,
tbl1_tbl2_prod.lpm_widthp = 122,
tbl1_tbl2_prod.lpm_type = "lpm_mult",
tbl1_tbl2_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult tbl3_taylor_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(table_three_out),
.datab({1'b1, 27'b000000000000000000000000000, xf[30:0]}),
.result(wire_tbl3_taylor_prod_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
tbl3_taylor_prod.lpm_pipeline = 4,
tbl3_taylor_prod.lpm_representation = "UNSIGNED",
tbl3_taylor_prod.lpm_widtha = 61,
tbl3_taylor_prod.lpm_widthb = 59,
tbl3_taylor_prod.lpm_widthp = 120,
tbl3_taylor_prod.lpm_type = "lpm_mult",
tbl3_taylor_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult xi_ln2_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_exp_value_to_ln2a_dataout),
.datab(ln2_w),
.result(wire_xi_ln2_prod_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
xi_ln2_prod.lpm_pipeline = 4,
xi_ln2_prod.lpm_representation = "UNSIGNED",
xi_ln2_prod.lpm_widtha = 11,
xi_ln2_prod.lpm_widthb = 70,
xi_ln2_prod.lpm_widthp = 81,
xi_ln2_prod.lpm_type = "lpm_mult",
xi_ln2_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult xi_prod
(
.dataa(x_fixed[69:55]),
.datab(one_over_ln2_w),
.result(wire_xi_prod_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.sum({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
xi_prod.lpm_representation = "UNSIGNED",
xi_prod.lpm_widtha = 15,
xi_prod.lpm_widthb = 12,
xi_prod.lpm_widthp = 27,
xi_prod.lpm_type = "lpm_mult",
xi_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mux table_one
(
.data(table_one_data),
.result(wire_table_one_result),
.sel(xf[57:49])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
table_one.lpm_size = 512,
table_one.lpm_width = 61,
table_one.lpm_widths = 9,
table_one.lpm_type = "lpm_mux";
lpm_mux table_three
(
.data(table_three_data),
.result(wire_table_three_result),
.sel(xf[39:31])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
table_three.lpm_size = 512,
table_three.lpm_width = 42,
table_three.lpm_widths = 9,
table_three.lpm_type = "lpm_mux";
lpm_mux table_two
(
.data(table_two_data),
.result(wire_table_two_result),
.sel(xf[48:40])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
table_two.lpm_size = 512,
table_two.lpm_width = 51,
table_two.lpm_widths = 9,
table_two.lpm_type = "lpm_mux";
assign
wire_cin_to_bias_dataout = shifted_value;
assign wire_exp_result_mux_prea_dataout = (((((barrel_shifter_underflow | overflow_w) | input_is_zero_wo) | nan_w) | positive_infinity) === 1'b1) ? exp_one : exp_result_w;
assign wire_exp_value_b4_biasa_dataout = (sign_dffe3[0:0] === 1'b1) ? exp_invert : xi_exp_value;
assign wire_exp_value_selecta_dataout = (exp_value_wo[11] === 1'b1) ? wire_invert_exp_value_result[6:0] : exp_value_wo[6:0];
assign wire_exp_value_to_compare_muxa_dataout = (exp_value_wo[11] === 1'b1) ? wire_invert_exp_value_result : exp_value_wo[10:0];
assign wire_exp_value_to_ln2a_dataout = (sign_dffe4[0:0] === 1'b1) ? wire_xi_add_one_result : xi_exp_value_wo;
assign wire_extra_ln2_muxa_dataout = (extra_ln2_dffe_0 === 1'b1) ? wire_xf_minus_ln2_result : xf_pre_wo[59:0];
assign wire_man_result_muxa_dataout = (((((overflow_w | underflow_w) | nan_w) | input_is_zero_wo) | input_is_infinity_wo) === 1'b1) ? {nan_w, 51'b000000000000000000000000000000000000000000000000000} : wire_man_round_result;
assign wire_xf_muxa_dataout = (sign_dffe12[0:0] === 1'b1) ? wire_one_minus_xf_result : xf_pre_2_wo[59:0];
assign
aclr = 1'b0,
addr_val_more_than_one = 9'b101100011,
barrel_shifter_data = {11'b00000000000, 1'b1, fraction_wo, 6'b000000},
barrel_shifter_distance = wire_exp_value_selecta_dataout,
barrel_shifter_underflow = barrel_shifter_underflow_dffe2_23_pipes22[0:0],
barrel_shifter_underflow_wi = (wire_underflow_compare_agb & exp_value_wo[11]),
distance_overflow = distance_overflow_dffe2_23_pipes22[0:0],
distance_overflow_val_w = 11'b00000001001,
distance_overflow_wi = (wire_distance_overflow_comp_agb & (~ exp_value_wo[11])),
exp_bias = 11'b01111111111,
exp_bias_all_ones_w = {11{1'b1}},
exp_data_all_one_w = {(data[62] & exp_data_all_one_w[9]), (data[61] & exp_data_all_one_w[8]), (data[60] & exp_data_all_one_w[7]), (data[59] & exp_data_all_one_w[6]), (data[58] & exp_data_all_one_w[5]), (data[57] & exp_data_all_one_w[4]), (data[56] & exp_data_all_one_w[3]), (data[55] & exp_data_all_one_w[2]), (data[54] & exp_data_all_one_w[1]), (data[53] & exp_data_all_one_w[0]), data[52]},
exp_data_not_zero_w = {(data[62] | exp_data_not_zero_w[9]), (data[61] | exp_data_not_zero_w[8]), (data[60] | exp_data_not_zero_w[7]), (data[59] | exp_data_not_zero_w[6]), (data[58] | exp_data_not_zero_w[5]), (data[57] | exp_data_not_zero_w[4]), (data[56] | exp_data_not_zero_w[3]), (data[55] | exp_data_not_zero_w[2]), (data[54] | exp_data_not_zero_w[1]), (data[53] | exp_data_not_zero_w[0]), data[52]},
exp_invert = (xi_exp_value ^ exp_bias_all_ones_w),
exp_one = {((overflow_w | nan_w) | positive_infinity), 10'b1111111111},
exp_out_all_one_w = {(exp_result_w[10] & exp_out_all_one_w[9]), (exp_result_w[9] & exp_out_all_one_w[8]), (exp_result_w[8] & exp_out_all_one_w[7]), (exp_result_w[7] & exp_out_all_one_w[6]), (exp_result_w[6] & exp_out_all_one_w[5]), (exp_result_w[5] & exp_out_all_one_w[4]), (exp_result_w[4] & exp_out_all_one_w[3]), (exp_result_w[3] & exp_out_all_one_w[2]), (exp_result_w[2] & exp_out_all_one_w[1]), (exp_result_w[1] & exp_out_all_one_w[0]), exp_result_w[0]},
exp_out_not_zero_w = {(exp_result_w[10] | exp_out_not_zero_w[9]), (exp_result_w[9] | exp_out_not_zero_w[8]), (exp_result_w[8] | exp_out_not_zero_w[7]), (exp_result_w[7] | exp_out_not_zero_w[6]), (exp_result_w[6] | exp_out_not_zero_w[5]), (exp_result_w[5] | exp_out_not_zero_w[4]), (exp_result_w[4] | exp_out_not_zero_w[3]), (exp_result_w[3] | exp_out_not_zero_w[2]), (exp_result_w[2] | exp_out_not_zero_w[1]), (exp_result_w[1] | exp_out_not_zero_w[0]), exp_result_w[0]},
exp_result_out = (wire_exp_result_mux_prea_dataout & {11{(~ ((underflow_w & (~ barrel_shifter_underflow)) | negative_infinity))}}),
exp_result_w = wire_exp_value_man_over_result[10:0],
exp_value = wire_exp_minus_bias_result,
exp_value_wi = exp_value,
exp_value_wo = exp_value_dffe1,
exp_w = data[62:52],
extra_ln2 = ((~ xf_pre[69]) & sign_dffe10[0:0]),
fraction = {data[51:0]},
fraction_wi = fraction,
fraction_wo = fraction_dffe1,
gnd_w = 1'b0,
guard_bit = man_prod_result[64],
input_is_infinity_wi = (exp_data_all_one_w[10] & (~ man_data_not_zero_w[51])),
input_is_infinity_wo = input_is_infinity_24_pipes23[0:0],
input_is_nan_wi = (exp_data_all_one_w[10] & man_data_not_zero_w[51]),
input_is_nan_wo = input_is_nan_24_pipes23[0:0],
input_is_zero_wi = (~ exp_data_not_zero_w[10]),
input_is_zero_wo = input_is_zero_24_pipes23[0:0],
ln2_w = 70'b1011000101110010000101111111011111010001110011110111100110101011110010,
man_data_not_zero_w = {(data[51] | man_data_not_zero_w[50]), (data[50] | man_data_not_zero_w[49]), (data[49] | man_data_not_zero_w[48]), (data[48] | man_data_not_zero_w[47]), (data[47] | man_data_not_zero_w[46]), (data[46] | man_data_not_zero_w[45]), (data[45] | man_data_not_zero_w[44]), (data[44] | man_data_not_zero_w[43]), (data[43] | man_data_not_zero_w[42]), (data[42] | man_data_not_zero_w[41]), (data[41] | man_data_not_zero_w[40]), (data[40] | man_data_not_zero_w[39]), (data[39] | man_data_not_zero_w[38]), (data[38] | man_data_not_zero_w[37]), (data[37] | man_data_not_zero_w[36]), (data[36] | man_data_not_zero_w[35]), (data[35] | man_data_not_zero_w[34]), (data[34] | man_data_not_zero_w[33]), (data[33] | man_data_not_zero_w[32]), (data[32] | man_data_not_zero_w[31]), (data[31] | man_data_not_zero_w[30]), (data[30] | man_data_not_zero_w[29]), (data[29] | man_data_not_zero_w[28]), (data[28] | man_data_not_zero_w[27]), (data[27] | man_data_not_zero_w[26]), (data[26] | man_data_not_zero_w[25]), (data[25] | man_data_not_zero_w[24]), (data[24] | man_data_not_zero_w[23]), (data[23] | man_data_not_zero_w[22]), (data[22] | man_data_not_zero_w[21]), (data[21] | man_data_not_zero_w[20]), (data[20] | man_data_not_zero_w[19]), (data[19] | man_data_not_zero_w[18]), (data[18] | man_data_not_zero_w[17]), (data[17] | man_data_not_zero_w[16]), (data[16] | man_data_not_zero_w[15]), (data[15] | man_data_not_zero_w[14]), (data[14] | man_data_not_zero_w[13]), (data[13] | man_data_not_zero_w[12]), (data[12] | man_data_not_zero_w[11]), (data[11] | man_data_not_zero_w[10]), (data[10] | man_data_not_zero_w[9]), (data[9] | man_data_not_zero_w[8]), (data[8] | man_data_not_zero_w[7]), (data[7] | man_data_not_zero_w[6]), (data[6] | man_data_not_zero_w[5]), (data[5] | man_data_not_zero_w[4]), (data[4] | man_data_not_zero_w[3]), (data[3] | man_data_not_zero_w[2]), (data[2] | man_data_not_zero_w[1]), (data[1] | man_data_not_zero_w[0]), data[0]},
man_overflow = (round_up & man_result_all_ones[51]),
man_overflow_wi = man_overflow,
man_overflow_wo = man_overflow_dffe15,
man_prod_result = ((man_prod_shifted & {120{man_prod_wo[117]}}) | (man_prod_wire & {120{(~ man_prod_wo[117])}})),
man_prod_shifted = {gnd_w, man_prod_wo[119:1]},
man_prod_wi = wire_man_prod_result,
man_prod_wire = man_prod_wo,
man_prod_wo = man_prod_dffe14,
man_result_all_ones = {(man_round_wi[51] & man_result_all_ones[50]), (man_round_wi[50] & man_result_all_ones[49]), (man_round_wi[49] & man_result_all_ones[48]), (man_round_wi[48] & man_result_all_ones[47]), (man_round_wi[47] & man_result_all_ones[46]), (man_round_wi[46] & man_result_all_ones[45]), (man_round_wi[45] & man_result_all_ones[44]), (man_round_wi[44] & man_result_all_ones[43]), (man_round_wi[43] & man_result_all_ones[42]), (man_round_wi[42] & man_result_all_ones[41]), (man_round_wi[41] & man_result_all_ones[40]), (man_round_wi[40] & man_result_all_ones[39]), (man_round_wi[39] & man_result_all_ones[38]), (man_round_wi[38] & man_result_all_ones[37]), (man_round_wi[37] & man_result_all_ones[36]), (man_round_wi[36] & man_result_all_ones[35]), (man_round_wi[35] & man_result_all_ones[34]), (man_round_wi[34] & man_result_all_ones[33]), (man_round_wi[33] & man_result_all_ones[32]), (man_round_wi[32] & man_result_all_ones[31]), (man_round_wi[31] & man_result_all_ones[30]), (man_round_wi[30] & man_result_all_ones[29]), (man_round_wi[29] & man_result_all_ones[28]), (man_round_wi[28] & man_result_all_ones[27]), (man_round_wi[27] & man_result_all_ones[26]), (man_round_wi[26] & man_result_all_ones[25]), (man_round_wi[25] & man_result_all_ones[24]), (man_round_wi[24] & man_result_all_ones[23]), (man_round_wi[23] & man_result_all_ones[22]), (man_round_wi[22] & man_result_all_ones[21]), (man_round_wi[21] & man_result_all_ones[20]), (man_round_wi[20] & man_result_all_ones[19]), (man_round_wi[19] & man_result_all_ones[18]), (man_round_wi[18] & man_result_all_ones[17]), (man_round_wi[17] & man_result_all_ones[16]), (man_round_wi[16] & man_result_all_ones[15]), (man_round_wi[15] & man_result_all_ones[14]), (man_round_wi[14] & man_result_all_ones[13]), (man_round_wi[13] & man_result_all_ones[12]), (man_round_wi[12] & man_result_all_ones[11]), (man_round_wi[11] & man_result_all_ones[10]), (man_round_wi[10] & man_result_all_ones[9]), (man_round_wi[9] & man_result_all_ones[8]), (man_round_wi[8] & man_result_all_ones[7]), (man_round_wi[7]
& man_result_all_ones[6]), (man_round_wi[6] & man_result_all_ones[5]), (man_round_wi[5] & man_result_all_ones[4]), (man_round_wi[4] & man_result_all_ones[3]), (man_round_wi[3] & man_result_all_ones[2]), (man_round_wi[2] & man_result_all_ones[1]), (man_round_wi[1] & man_result_all_ones[0]), man_round_wi[0]},
man_result_w = wire_man_result_muxa_dataout,
man_round_wi = man_prod_result[115:64],
man_round_wo = man_round_dffe15,
nan_w = input_is_nan_wo,
negative_infinity = (sign_dffe23[0:0] & input_is_infinity_wo),
one_over_ln2_w = 12'b101110001010,
overflow_w = ((((~ sign_dffe23[0:0]) & (((distance_overflow | wire_exp_value_add_bias_result[11]) | exp_out_all_one_w[10]) | wire_exp_value_man_over_result[11])) & (~ underflow_w)) & (~ input_is_nan_wo)),
positive_infinity = ((~ sign_dffe23[0:0]) & input_is_infinity_wo),
result = {1'b0, result_pipe_wo},
result_pipe_wi = {exp_result_out, man_result_w},
result_pipe_wo = result_pipe_dffe16,
result_underflow_w = ((~ exp_out_not_zero_w[10]) & (((~ wire_exp_value_man_over_result[11]) & (~ sign_dffe23[0:0])) | sign_dffe23[0:0])),
round_bit = man_prod_result[63],
round_up = (round_bit & (guard_bit | sticky_bits[4])),
round_up_wi = round_up,
round_up_wo = round_up_dffe15,
shifted_value = (tbl1_compare_wo | man_prod_wo[117]),
sign_w = data[63],
sticky_bits = {(man_prod_result[58] | sticky_bits[3]), (man_prod_result[59] | sticky_bits[2]), (man_prod_result[60] | sticky_bits[1]), (man_prod_result[61] | sticky_bits[0]), man_prod_result[62]},
table_one_data = {61'b1010110110100001011011011110100111100001100100011101100101101, 61'b1010110101001010101100101110001101111100110010100110001010000, 61'b1010110011110100001000110010111111000101101000101101100100011, 61'b1010110010011101101111101011100100011000001011011101101111110, 61'b1010110001000111100001010110100111011011010011010100110010000, 61'b1010101111110001011101110010110010000000101011001110100010011, 61'b1010101110011011100100111110101110000100101111001110011011010, 61'b1010101101000101110110111001000101101110101011001001010110101, 61'b1010101011110000010011100000100011010000011001001111110101011, 61'b1010101010011010111010110011110001000110100000111000010000110, 61'b1010101001000101101100110001011001111000010101001001010111101, 61'b1010100111110000101001011000001000010111110011100100110101001, 61'b1010100110011011110000100110100111100001100010110010000011011, 61'b1010100101000111000010011011100010011100110001001001000111010, 61'b1010100011110010011110110101100100011011010011011101111000000, 61'b1010100010011110000101110011011000111001100011101011010001100, 61'b1010100001001001110111010011101011011110011111011110101111101, 61'b1010011111110101110011010101000111111011100111000011110110010, 61'b1010011110100001111001110110011010001100111011110000000010001, 61'b1010011101001110001010110110001110011000111110101110100101000, 61'b1010011011111010100110010011010000110000101111101100101100101, 61'b1010011010100111001100001100001101101111101011100101110010110, 61'b1010011001010011111100011111110001111011101011001111111001110, 61'b1010011000000000110111001100101010000101000010001000010001011, 61'b1010010110101101111100010001100011000110011101000000001000000, 61'b1010010101011011001011101101001010000101000000101001100100111, 61'b1010010100001000100101011110001100010000001000100100101101000, 61'b1010010010110110001001100011010111000001100101101100110011001, 61'b1010010001100011110111111011010111111101011101000101110001000, 61'b1010010000010001110000100100111100110010000110101001101011101, 61'b1010001110111111110011011110110011011000001011110110100001111
, 61'b1010001101101110000000100111101001110010100110011100000100101, 61'b1010001100011100010111111110001110001110011111001001111010000, 61'b1010001011001010111001100001001111000011001100011101101010100, 61'b1010001001111001100101001111011010110010010001010001011000011, 61'b1010001000101000011011000111100000000111011011101010000001000, 61'b1010000111010111011011001000001101111000100011100110001000110, 61'b1010000110000110100101010000010011000101101001101100110000101, 61'b1010000100110101111001011110011110111000110101111100010110101, 61'b1010000011100101010111110001100000100110010110011001111111101, 61'b1010000010010101000000001000000111101100011110000000101011101, 61'b1010000001000100110010100001000011110011100011010000110100001, 61'b1001111111110100101110111011000100101101111110111111110100100, 61'b1001111110100100110101010100111010011000001011000111111100000, 61'b1001111101010101000101101101010100111000100001011000001010111, 61'b1001111100000101100000000011000100011111011010000100011000001, 61'b1001111010110110000100010100111001100111001010110101100010001, 61'b1001111001100110110010100001100100110100000101011010001001000, 61'b1001111000010111101010100111110110110100010110010110110010111, 61'b1001110111001000101100100110100000100000000011110110111010000, 61'b1001110101111001111000011100010010111001001100011101100101000, 61'b1001110100101011001110000111111111001011100101110110101000100, 61'b1001110011011100101101101000010110101100111011100111110011101, 61'b1001110010001110010110111100001010111100101110000010000100101, 61'b1001110001000000001010000010001101100100010000110011001001110, 61'b1001101111110010000110111001010000010110101001110111001001011, 61'b1001101110100100001101100000000101010000110000001010010101100, 61'b1001101101010110011101110101011110011001001010011011001000111, 61'b1001101100001000110111111000001110000000001101111100001101010, 61'b1001101010111011011011100111000110011111111101010110101011111, 61'b1001101001101110001001000000111010011100000111011100100111011, 61'b1001101000100001000000000100011100100010000101111011011111111
, 61'b1001100111010100000000110000011111101000111100001110111111111, 61'b1001100110000111001011000011110110110001010110010011110011100, 61'b1001100100111010011110111101010101000101100111011010101001011, 61'b1001100011101101111100011011101101111001101000111011011100111, 61'b1001100010100001100011011101110100101010111001001000101001110, 61'b1001100001010101010100000010011101000000011010000010101001110, 61'b1001100000001001001110001000011010101010110000001011011011111, 61'b1001011110111101010001101110100001100100000001011010010100110, 61'b1001011101110001011110110011100101101111110011101111111000011, 61'b1001011100100101110101010110011011011011001100001001111110011, 61'b1001011011011010010101010101110110111100101101010111111110110, 61'b1001011010001110111110110000101100110100010110101111001000011, 61'b1001011001000011110001100101110001101011100010111111000000111, 61'b1001010111111000101101110011111010010101000111000110001110011, 61'b1001010110101101110011011001111011101101010001000111001010001, 61'b1001010101100011000010010110101010111001100110111100111100111, 61'b1001010100011000011010101000111101001001000101010000100100001, 61'b1001010011001101111100001111100111110011111110001110000001011, 61'b1001010010000011100111001001100000011011111000011001110010010, 61'b1001010000111001011011010101011100101011101101100110010010011, 61'b1001001111101111011000110010010010010111101001101001100101110, 61'b1001001110100101011111011110110111011101001001010011001101101, 61'b1001001101011011101111011010000010000010111001000010000101010, 61'b1001001100010010001000100010101000011000110011111010101001001, 61'b1001001011001000101010110111100000111000000010011101000110100, 61'b1001001001111111010110010111100010000010111001011011110100111, 61'b1001001000110110001011000001100010100100111000110001111000000, 61'b1001000111101101001000110100011001010010101010011001101011101, 61'b1001000110100100001111101110111101001010000001000011111000000, 61'b1001000101011011011111110000000101010001110111001110001111110, 61'b1001000100010010111000110110101000111010001101111010110110110
, 61'b1001000011001010011011000001011111011100001011100111010010000, 61'b1001000010000010000110001111100000011001111011000100000001000, 61'b1001000000111001111010011111100011011110101010001011111111111, 61'b1000111111110001110111110000100000011110101000111100010010010, 61'b1000111110101001111110000001001111010111001000001011111000000, 61'b1000111101100010001101010000101000001110011000100011101010001, 61'b1000111100011010100101011101100011010011101001010110100001000, 61'b1000111011010011000110100110111000111111000111011001100100000, 61'b1000111010001011110000101011100001110001111011111100100001011, 61'b1000111001000100100011101010010110010110001011100010001111011, 61'b1000110111111101011111100010001111011110110100111001010110101, 61'b1000110110110110100100010010000110000111101111110101000100110, 61'b1000110101101111110001111000110011010101101100000110001000010, 61'b1000110100101001001000010101010000010110010000010011110101101, 61'b1000110011100010100111100110010110011111111000110101010100101, 61'b1000110010011100001111101010111111010001110110101010110110111, 61'b1000110001010110000000100010000100010100001110010111010111000, 61'b1000110000001111111010001010011111010111110110111010000000101, 61'b1000101111001001111100100011001010010110011000101000000001110, 61'b1000101110000100000111101010111111010010001100000110100011101, 61'b1000101100111110011011100000111000010110011001000100101101110, 61'b1000101011111000111000000011101111110110110101010101110000100, 61'b1000101010110011011101010010100000010000000011101011011001100, 61'b1000101001101110001011001100000100000111010010110000001111110, 61'b1000101000101001000001101111010110001010011100000010011000110, 61'b1000100111100100000000111011010001010000000010101110000111001, 61'b1000100110011111001000101110110000010111010010101000110000011, 61'b1000100101011010011001001000101110100111111111001011101100010, 61'b1000100100010101110010001000000111010010100010001111011100111, 61'b1000100011010001010011101011110101101111111011000110111111000, 61'b1000100010001100111101110010110101100001101101011011000010101
, 61'b1000100001001000110000011100000010010010000000000101101101001, 61'b1000100000000100101011100110010111110011011100001110000011001, 61'b1000011111000000101111010000110010000001001100000011111010110, 61'b1000011101111100111011011010001100111110111001111011110111101, 61'b1000011100111001010000000001100100111000101111001011001101101, 61'b1000011011110101101101000101110110000011010011000100001101110, 61'b1000011010110010010010100101111100111011101001110010011010011, 61'b1000011001101111000000100000110110000111010011010111000100001, 61'b1000011000101011110110110101011110010100001010100101110000000, 61'b1000010111101000110101100010110010011000100100000001000100101, 61'b1000010110100101111100100111101111010011001100110111100000111, 61'b1000010101100011001100000011010010001011001010000000011010110, 61'b1000010100100000100011110100011000001111110110111001000110010, 61'b1000010011011110000011111001111110111001000100100010000100100, 61'b1000010010011011101100010011000011100110111000011100011100010, 61'b1000010001011001011100111110100100000001101011100111011001001, 61'b1000010000010111010101111011011101111010001001011101110100111, 61'b1000001111010101010111001000101111001001001110110100000111011, 61'b1000001110010011100000100101010101110000001000110101111111101, 61'b1000001101010001110010010000001111111000010100000100100101011, 61'b1000001100010000001100001000011011110011011011010100100010100, 61'b1000001011001110101110001100110111111011010110101100010011111, 61'b1000001010001101011000011100100010110010001010100010100100101, 61'b1000001001001100001010110110011011000010000110011100101110111, 61'b1000001000001011000101011001011111011101100100001101100110110, 61'b1000000111001010001000000100101110111111000110110100001100110, 61'b1000000110001001010010110111001000101001011001011010100111111, 61'b1000000101001000100101101111101011100111001110010101001000101, 61'b1000000100001000000000101101010111001011011110000001010011111, 61'b1000000011000111100011101111001010110001000110000101010101010, 61'b1000000010000111001110110100000101111011001000001111011010110
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, 61'b1000001111001110001100110110101001001110010111001001110110001, 61'b1000001110001100010111001100011110100001000001000010011101111, 61'b1000001101001010101001110000100000001011100011001111111110000, 61'b1000001100001001000100100001101100100000100001101110100010100, 61'b1000001011000111100111011111000001111010101101100101000010101, 61'b1000001010000110010010100111011110111101000100000011011011100, 61'b1000001001000101000101111010000010010010101101100001010010111, 61'b1000001000000100000001010101101010101110111100011100100010111, 61'b1000000111000011000100111001010111001101001100011000001100101, 61'b1000000110000010010000100100000110110001000000111011010100000, 61'b1000000101000001100100010100111000100110000100110000000011001, 61'b1000000100000001000000001010101100000000001000100010110110000, 61'b1000000011000000100100000100100000011011000010000001101110100, 61'b1000000010000000010000000001010101011010101010111011101111101, 61'b1000000001000000000100000000001010101011000000000000100010001, 61'b1000000000000000000000000000000000000000000000000000000000000},
table_one_out = wire_table_one_result,
table_three_data = {42'b111111111000000000011111111000000000101010, 42'b111111110000000000011111110000000010001010, 42'b111111101000000000011111101000000100101010, 42'b111111100000000000011111100000001000001010, 42'b111111011000000000011111011000001100101010, 42'b111111010000000000011111010000010010001010, 42'b111111001000000000011111001000011000101010, 42'b111111000000000000011111000000100000001010, 42'b111110111000000000011110111000101000101010, 42'b111110110000000000011110110000110010001010, 42'b111110101000000000011110101000111100101001, 42'b111110100000000000011110100001001000001001, 42'b111110011000000000011110011001010100101001, 42'b111110010000000000011110010001100010001001, 42'b111110001000000000011110001001110000101001, 42'b111110000000000000011110000010000000001001, 42'b111101111000000000011101111010010000101001, 42'b111101110000000000011101110010100010001001, 42'b111101101000000000011101101010110100101001, 42'b111101100000000000011101100011001000001001, 42'b111101011000000000011101011011011100101001, 42'b111101010000000000011101010011110010001001, 42'b111101001000000000011101001100001000101001, 42'b111101000000000000011101000100100000001001, 42'b111100111000000000011100111100111000101001, 42'b111100110000000000011100110101010010001001, 42'b111100101000000000011100101101101100101001, 42'b111100100000000000011100100110001000001001, 42'b111100011000000000011100011110100100101000, 42'b111100010000000000011100010111000010001000, 42'b111100001000000000011100001111100000101000, 42'b111100000000000000011100001000000000001000, 42'b111011111000000000011100000000100000101000, 42'b111011110000000000011011111001000010001000, 42'b111011101000000000011011110001100100101000, 42'b111011100000000000011011101010001000001000, 42'b111011011000000000011011100010101100101000, 42'b111011010000000000011011011011010010001000, 42'b111011001000000000011011010011111000101000, 42'b111011000000000000011011001100100000001000, 42'b111010111000000000011011000101001000101000, 42'b111010110000000000011010111101110010001000, 42'b111010101000000000011010110110011100101000
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, 42'b001010001000000000000000110011010000100000, 42'b001010000000000000000000110010000000000000, 42'b001001111000000000000000110000110000100000, 42'b001001110000000000000000101111100010000000, 42'b001001101000000000000000101110010100100000, 42'b001001100000000000000000101101001000000000, 42'b001001011000000000000000101011111100100000, 42'b001001010000000000000000101010110010000000, 42'b001001001000000000000000101001101000100000, 42'b001001000000000000000000101000100000000000, 42'b001000111000000000000000100111011000100000, 42'b001000110000000000000000100110010010000000, 42'b001000101000000000000000100101001100100000, 42'b001000100000000000000000100100001000000000, 42'b001000011000000000000000100011000100100000, 42'b001000010000000000000000100010000010000000, 42'b001000001000000000000000100001000000100000, 42'b001000000000000000000000100000000000000000, 42'b000111111000000000000000011111000000100000, 42'b000111110000000000000000011110000010000000, 42'b000111101000000000000000011101000100100000, 42'b000111100000000000000000011100001000000000, 42'b000111011000000000000000011011001100100000, 42'b000111010000000000000000011010010010000000, 42'b000111001000000000000000011001011000100000, 42'b000111000000000000000000011000100000000000, 42'b000110111000000000000000010111101000100000, 42'b000110110000000000000000010110110010000000, 42'b000110101000000000000000010101111100100000, 42'b000110100000000000000000010101001000000000, 42'b000110011000000000000000010100010100100000, 42'b000110010000000000000000010011100010000000, 42'b000110001000000000000000010010110000100000, 42'b000110000000000000000000010010000000000000, 42'b000101111000000000000000010001010000100000, 42'b000101110000000000000000010000100010000000, 42'b000101101000000000000000001111110100100000, 42'b000101100000000000000000001111001000000000, 42'b000101011000000000000000001110011100100000, 42'b000101010000000000000000001101110010000000, 42'b000101001000000000000000001101001000100000, 42'b000101000000000000000000001100100000000000, 42'b000100111000000000000000001011111000100000
, 42'b000100110000000000000000001011010010000000, 42'b000100101000000000000000001010101100100000, 42'b000100100000000000000000001010001000000000, 42'b000100011000000000000000001001100100100000, 42'b000100010000000000000000001001000010000000, 42'b000100001000000000000000001000100000100000, 42'b000100000000000000000000001000000000000000, 42'b000011111000000000000000000111100000100000, 42'b000011110000000000000000000111000010000000, 42'b000011101000000000000000000110100100100000, 42'b000011100000000000000000000110001000000000, 42'b000011011000000000000000000101101100100000, 42'b000011010000000000000000000101010010000000, 42'b000011001000000000000000000100111000100000, 42'b000011000000000000000000000100100000000000, 42'b000010111000000000000000000100001000100000, 42'b000010110000000000000000000011110010000000, 42'b000010101000000000000000000011011100100000, 42'b000010100000000000000000000011001000000000, 42'b000010011000000000000000000010110100100000, 42'b000010010000000000000000000010100010000000, 42'b000010001000000000000000000010010000100000, 42'b000010000000000000000000000010000000000000, 42'b000001111000000000000000000001110000100000, 42'b000001110000000000000000000001100010000000, 42'b000001101000000000000000000001010100100000, 42'b000001100000000000000000000001001000000000, 42'b000001011000000000000000000000111100100000, 42'b000001010000000000000000000000110010000000, 42'b000001001000000000000000000000101000100000, 42'b000001000000000000000000000000100000000000, 42'b000000111000000000000000000000011000100000, 42'b000000110000000000000000000000010010000000, 42'b000000101000000000000000000000001100100000, 42'b000000100000000000000000000000001000000000, 42'b000000011000000000000000000000000100100000, 42'b000000010000000000000000000000000010000000, 42'b000000001000000000000000000000000000100000, 42'b000000000000000000000000000000000000000000},
table_three_out = {1'b1, 18'b000000000000000000, table_three_out_tmp},
table_three_out_tmp = wire_table_three_result,
table_two_data = {51'b111111111011111111001010101011000000010101110111110, 51'b111111110011111110001010110011000001101011001001011, 51'b111111101011111101001011000011000100000000001111000, 51'b111111100011111100001011011011000111010101000000101, 51'b111111011011111011001011111011001011101001010110001, 51'b111111010011111010001100100011010000111101000111101, 51'b111111001011111001001101010011010111010000001100111, 51'b111111000011111000001110001011011110100010011110001, 51'b111110111011110111001111001011100110110011110011010, 51'b111110110011110110010000010011110000000100000100010, 51'b111110101011110101010001100011111010010011001001001, 51'b111110100011110100010010111100000101100000111001110, 51'b111110011011110011010100011100010001101101001110010, 51'b111110010011110010010110000100011110110111111110101, 51'b111110001011110001010111110100101101000001000010101, 51'b111110000011110000011001101100111100001000010010100, 51'b111101111011101111011011101101001100001101100110001, 51'b111101110011101110011101110101011101010000110101011, 51'b111101101011101101100000000101101111010001111000100, 51'b111101100011101100100010011110000010010000100111010, 51'b111101011011101011100100111110010110001100111001110, 51'b111101010011101010100111100110101011000110100111111, 51'b111101001011101001101010010111000000111101101001110, 51'b111101000011101000101101001111010111110001110111010, 51'b111100111011100111110000001111101111100011001000011, 51'b111100110011100110110011011000001000010001010101000, 51'b111100101011100101110110101000100001111100010101011, 51'b111100100011100100111010000000111100100100000001011, 51'b111100011011100011111101100001011000001000010000111, 51'b111100010011100011000001001001110100101000111011111, 51'b111100001011100010000100111010010010000101111010100, 51'b111100000011100001001000110010110000011111000100101, 51'b111011111011100000001100110011001111110100010010011, 51'b111011110011011111010000111011110000000101011011100, 51'b111011101011011110010101001100010001010010011000001, 51'b111011100011011101011001100100110011011011000000010
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, 51'b110110111010111100010011110010100000000100010100110, 51'b110110110010111011011100111011100100001011111110100, 51'b110110101010111010100110001100101001001010011011000, 51'b110110100010111001101111100101101110111111100010100, 51'b110110011010111000111001000110110101101011001100111, 51'b110110010010111000000010101111111101001101010010001, 51'b110110001010110111001100100001000101100101101010010, 51'b110110000010110110010110011010001110110100001101010, 51'b110101111010110101100000011011011000111000110011001, 51'b110101110010110100101010100100100011110011010011111, 51'b110101101010110011110100110101101111100011100111011, 51'b110101100010110010111111001110111100001001100101101, 51'b110101011010110010001001110000001001100101000110110, 51'b110101010010110001010100011001010111110110000010110, 51'b110101001010110000011111001010100110111100010001011, 51'b110101000010101111101010000011110110110111101010111, 51'b110100111010101110110101000101000111101000000111000, 51'b110100110010101110000000001110011001001101011101111, 51'b110100101010101101001011011111101011100111100111100, 51'b110100100010101100010110111000111110110110011011111, 51'b110100011010101011100010011010010010111001110010111, 51'b110100010010101010101110000011100111110001100100101, 51'b110100001010101001111001110100111101011101101001000, 51'b110100000010101001000101101110010011111101111000000, 51'b110011111010101000010001101111101011010010001001110, 51'b110011110010100111011101111001000011011010010110000, 51'b110011101010100110101010001010011100010110010100111, 51'b110011100010100101110110100011110110000101111110100, 51'b110011011010100101000011000101010000101001001010100, 51'b110011010010100100001111101110101011111111110001010, 51'b110011001010100011011100100000001000001001101010100, 51'b110011000010100010101001011001100101000110101110011, 51'b110010111010100001110110011011000010110110110100101, 51'b110010110010100001000011100100100001011001110101101, 51'b110010101010100000010000110110000000101111101001000, 51'b110010100010011111011110001111100000111000000110111
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table_two_out = {1'b1, 9'b000000000, table_two_out_tmp},
table_two_out_tmp = wire_table_two_result,
tbl1_compare_wi = wire_tbl1_compare_ageb,
tbl1_compare_wo = tbl1_compare_dffe11_10_pipes9[0:0],
tbl1_tbl2_prod_wi = wire_tbl1_tbl2_prod_result[121:62],
tbl1_tbl2_prod_wo = tbl1_tbl2_prod_dffe12,
tbl3_taylor_prod_wi = wire_tbl3_taylor_prod_result[119:60],
tbl3_taylor_prod_wo = tbl3_taylor_prod_dffe12,
underflow_compare_val_w = 11'b00000111010,
underflow_w = (((((result_underflow_w | barrel_shifter_underflow) | (sign_dffe23[0:0] & (distance_overflow | (~ wire_exp_value_add_bias_result[11])))) & (~ input_is_zero_wo)) & (~ input_is_infinity_wo)) & (~ input_is_nan_wo)),
x_fixed = wire_rbarrel_shift_result,
xf = wire_xf_muxa_dataout,
xf_pre = wire_x_fixed_minus_xiln2_result,
xf_pre_2_wi = xf_pre_wo,
xf_pre_2_wo = xf_pre_2_dffe10,
xf_pre_wi = xf_pre,
xf_pre_wo = xf_pre_dffe9,
xi_exp_value = xi_prod_wo[24:14],
xi_exp_value_wi = xi_exp_value,
xi_exp_value_wo = xi_exp_value_dffe4,
xi_ln2_prod_wi = wire_xi_ln2_prod_result,
xi_ln2_prod_wo = xi_ln2_prod_dffe7,
xi_prod_wi = wire_xi_prod_result,
xi_prod_wo = xi_prod_dffe3;
endmodule //fp_exp_altfp_exp_o7d
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fp_exp (
clk_en,
clock,
data,
result);
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
fp_exp_altfp_exp_o7d fp_exp_altfp_exp_o7d_component (
.clk_en (clk_en),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_exp"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "25"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT GND "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT GND "data[63..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT GND "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.cmp FALSE TRUE
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_valid,
src_adc_data,
src_adc_enable,
dst_adc_valid,
dst_adc_data,
dst_adc_enable
);
parameter CHANNEL_ID = 0;
parameter DATA_WIDTH = 32;
localparam SYMBOL_WIDTH = 2;
localparam RP_ID = 8'hA2;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_valid;
input [(DATA_WIDTH-1):0] src_adc_data;
input src_adc_enable;
output dst_adc_valid;
output [(DATA_WIDTH-1):0] dst_adc_data;
output dst_adc_enable;
reg dst_adc_valid = 'h0;
reg [(DATA_WIDTH-1):0] dst_adc_data = 'h0;
reg dst_adc_enable = 'h0;
reg [ 7:0] adc_pn_data = 'hF1;
reg [31:0] status = 'h0;
reg [ 3:0] mode = 'h0;
reg [ 3:0] channel_sel = 'h0;
wire adc_valid;
wire [(SYMBOL_WIDTH-1):0] adc_data_s;
wire [ 7:0] adc_pn_data_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
reg [ 7:0] dout;
begin
dout[7] = din[6];
dout[6] = din[5];
dout[5] = din[4];
dout[4] = din[3];
dout[3] = din[2];
dout[2] = din[1];
dout[1] = din[7] ^ din[4];
dout[0] = din[6] ^ din[3];
pn = dout;
end
endfunction
// update control and status registers
always @(posedge clk) begin
channel_sel <= control[ 3:0];
mode <= control[ 7:4];
end
assign adc_valid = src_adc_valid & src_adc_enable;
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? {adc_pn_data[7:2], adc_data_s} : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(8)
) i_pn_mon (
.adc_clk(clk),
.adc_valid_in(adc_valid),
.adc_data_in({adc_pn_data[7:2], adc_data_s}),
.adc_data_pn(adc_pn_data_s),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// prbs generation
always @(posedge clk) begin
if(adc_valid == 1'b1) begin
adc_pn_data <= pn(adc_pn_data);
end
end
// qpsk demodulator
qpsk_demod i_qpsk_demod1 (
.clk(clk),
.data_qpsk_i(src_adc_data[15: 0]),
.data_qpsk_q(src_adc_data[31:16]),
.data_valid(adc_valid),
.data_output(adc_data_s)
);
// output logic for data ans status
always @(posedge clk) begin
dst_adc_valid <= src_adc_valid;
dst_adc_enable <= src_adc_enable;
case(mode)
4'h0 : begin
dst_adc_data <= src_adc_data;
end
4'h1 : begin
dst_adc_data <= 32'h0;
end
4'h2 : begin
dst_adc_data <= {30'h0, adc_data_s};
end
default : begin
dst_adc_data <= src_adc_data;
end
endcase
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__MUX2_FUNCTIONAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hdll__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_FUNCTIONAL_V
|
`default_nettype none
module gci_std_display_command #(
parameter P_AREA_H = 640,
parameter P_AREA_V = 480,
parameter P_AREAA_HV_N = 19,
parameter P_MEM_ADDR_N = 23
)(
input wire iCLOCK,
input wire inRESET,
//Register
input wire iREG_MODE, //[0]Bitmap | [1]Charactor
//BUS
input wire iIF_VALID,
input wire iIF_SEQ,
output wire oIF_BUSY,
input wire iIF_RW,
input wire [P_MEM_ADDR_N-1:0] iIF_ADDR,
input wire [31:0] iIF_DATA,
//Output
output wire oIF_VALID,
input wire iIF_BUSY,
output wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
output wire [23:0] oIF_DATA
);
localparam P_L_REQ_STT_BITMAP = 3'h0;
localparam P_L_REQ_STT_CLARACTER = 3'h1;
localparam P_L_REQ_STT_CLARACTER_WAIT = 3'h2;
localparam P_L_REQ_STT_SEAQUENCER = 3'h3;
localparam P_L_REQ_STT_SEAQUENCER_WAIT = 3'h4;
//State
reg [2:0] b_req_state;
//FIFO
wire reqfifo_wr_full;
wire reqfifo_rd_empty;
wire reqfifo_rd_mode;
wire reqfifo_rd_seq;
wire reqfifo_rd_rw;
wire [31:0] reqfifo_rd_data;
wire [P_MEM_ADDR_N-1:0] reqfifo_rd_addr;
//Bitmap Latch
reg b_req_valid;
reg [P_MEM_ADDR_N-1:0] b_req_addr;
reg [23:0] b_req_data;
//Charactor
wire character_busy;
wire character_finish;
wire character_out_valid;
wire [P_MEM_ADDR_N-1:0] character_out_addr;
wire [23:0] character_out_data;
//Sequencer
wire sequencer_busy;
wire sequencer_finish;
wire sequencer_out_valid;
wire [P_MEM_ADDR_N-1:0] sequencer_out_addr;
wire [23:0] sequencer_out_data;
//Condition
reg fifo_read_condition;
always @* begin
case(b_req_state)
P_L_REQ_STT_BITMAP : fifo_read_condition = !reqfifo_rd_empty && !iIF_BUSY;
P_L_REQ_STT_CLARACTER : fifo_read_condition = !reqfifo_rd_empty && !character_busy;
P_L_REQ_STT_CLARACTER_WAIT : fifo_read_condition = 1'b0;
P_L_REQ_STT_SEAQUENCER : fifo_read_condition = !reqfifo_rd_empty && !sequencer_busy;
P_L_REQ_STT_SEAQUENCER_WAIT : fifo_read_condition = 1'b0;
default : fifo_read_condition = 1'b0;
endcase
end //conb
wire seaquencer_start_condition = fifo_read_condition && reqfifo_rd_seq;
wire charactor_start_condition = fifo_read_condition && reqfifo_rd_mode && !reqfifo_rd_seq;
gci_std_display_sync_fifo #(35+P_MEM_ADDR_N, 16, 4) REQ_FIFO
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(1'b0),
//Counter
.oCOUNT(),
//WR
.iWR_EN(iIF_VALID && !reqfifo_wr_full),
.iWR_DATA({iREG_MODE, iIF_SEQ, iIF_RW, iIF_DATA, iIF_DATA}),
.oWR_FULL(reqfifo_wr_full),
.oWR_ALMOST_FULL(),
//RD
.iRD_EN(fifo_read_condition),
.oRD_DATA({reqfifo_rd_mode, reqfifo_rd_seq, reqfifo_rd_rw, reqfifo_rd_addr, reqfifo_rd_data}),
.oRD_EMPTY(reqfifo_rd_empty),
.oRD_ALMOST_EMPTY()
);
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req_state <= P_L_REQ_STT_BITMAP;
end
else begin
case(b_req_state)
P_L_REQ_STT_BITMAP:
begin
if(seaquencer_start_condition)begin
b_req_state <= P_L_REQ_STT_SEAQUENCER;
end
else if(charactor_start_condition)begin
b_req_state <= P_L_REQ_STT_CLARACTER;
end
else begin
b_req_state <= P_L_REQ_STT_BITMAP;
end
end
P_L_REQ_STT_CLARACTER:
begin
if(!character_busy)begin
b_req_state <= P_L_REQ_STT_CLARACTER_WAIT;
end
end
P_L_REQ_STT_CLARACTER_WAIT:
begin
if(character_finish)begin
b_req_state <= P_L_REQ_STT_BITMAP;
end
end
P_L_REQ_STT_SEAQUENCER:
begin
if(!sequencer_busy)begin
b_req_state <= P_L_REQ_STT_SEAQUENCER_WAIT;
end
end
P_L_REQ_STT_SEAQUENCER_WAIT:
begin
if(sequencer_finish)begin
b_req_state <= P_L_REQ_STT_BITMAP;
end
end
default:
begin
b_req_state <= P_L_REQ_STT_BITMAP;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req_valid <= 1'b0;
b_req_addr <= {P_MEM_ADDR_N{1'b0}};
b_req_data <= 24'h0;
end
else begin
if(!iIF_BUSY)begin
b_req_valid <= !reqfifo_rd_empty;
b_req_addr <= reqfifo_rd_addr;
b_req_data <= reqfifo_rd_data[23:0];
end
end
end
gci_std_display_character #(P_AREA_H, P_AREA_V, P_AREAA_HV_N, P_MEM_ADDR_N) CHARACTER_CONTROLLER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
//Req
.iIF_VALID(b_req_state == P_L_REQ_STT_CLARACTER),
.oIF_BUSY(character_busy),
.iIF_ADDR(reqfifo_rd_addr), //Charactor Addr
.iIF_DATA(reqfifo_rd_data),
//Out
.oIF_FINISH(character_finish)
.oIF_VALID(character_out_valid),
.iIF_BUSY(iIF_BUSY),
.oIF_ADDR(character_out_addr),
.oIF_DATA(character_out_data)
);
gci_std_display_sequencer #(P_AREA_H, P_AREA_V, P_AREAA_HV_N, P_MEM_ADDR_N) SEQUENCER_CONTROLLER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
//Req
.iIF_VALID(b_req_state == P_L_REQ_STT_SEAQUENCER),
.oIF_BUSY(sequencer_busy),
.iIF_DATA(reqfifo_rd_data),
//Out
.oIF_FINISH(sequencer_finish)
.oIF_VALID(sequencer_out_valid),
.iIF_BUSY(iIF_BUSY),
.oIF_ADDR(sequencer_out_addr),
.oIF_DATA(sequencer_out_data)
);
reg if_out_valid;
reg [P_MEM_ADDR_N-1:0] if_out_addr;
reg [23:0] if_out_data;
always @* begin
case(b_req_state)
P_L_REQ_STT_BITMAP:
begin
if_out_valid = b_req_valid;
if_out_addr = b_req_addr;
if_out_data = b_req_data;
end
P_L_REQ_STT_CLARACTER_WAIT:
begin
if_out_valid = character_out_valid;
if_out_addr = character_out_addr;
if_out_data = character_out_data;
end
P_L_REQ_STT_SEAQUENCER_WAIT:
begin
if_out_valid = sequencer_out_valid;
if_out_addr = sequencer_out_addr;
if_out_data = sequencer_out_data;
end
default:
begin
if_out_valid = b_req_valid;
if_out_addr = b_req_addr;
if_out_data = b_req_data;
end
endcase
end
assign oIF_BUSY = reqfifo_wr_full;
assign oIF_VALID = !iIF_BUSY && if_out_valid;
assign oIF_ADDR = if_out_addr;
assign oIF_DATA = if_out_data;
endmodule
`default_nettype wire
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes to the ssram chip on the DE2-70 board, *
* with 4-cycle read latency and one cycle write latency. *
* *
******************************************************************************/
module nios_system_Pixel_Buffer (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// Bi-Directional
SRAM_DQ,
SRAM_DPA,
// Outputs
readdata,
readdatavalid,
waitrequest,
SRAM_CLK,
SRAM_ADDR,
SRAM_ADSC_N,
SRAM_ADSP_N,
SRAM_ADV_N,
SRAM_BE_N,
SRAM_CE1_N,
SRAM_CE2,
SRAM_CE3_N,
SRAM_GW_N,
SRAM_OE_N,
SRAM_WE_N
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [18: 0] address;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
// Bi-Directional
inout [31: 0] SRAM_DQ; // SRAM Data Bus 32 Bits
inout [ 3: 0] SRAM_DPA; // SRAM Parity Data Bus
// Outputs
output reg [31: 0] readdata;
output readdatavalid;
output waitrequest;
output SRAM_CLK; // SRAM Clock
output reg [18: 0] SRAM_ADDR; // SRAM Address bus 21 Bits
output reg SRAM_ADSC_N; // SRAM Controller Address Status
output reg SRAM_ADSP_N; // SRAM Processor Address Status
output reg SRAM_ADV_N; // SRAM Burst Address Advance
output reg [ 3: 0] SRAM_BE_N; // SRAM Byte Write Enable
output reg SRAM_CE1_N; // SRAM Chip Enable
output reg SRAM_CE2; // SRAM Chip Enable
output reg SRAM_CE3_N; // SRAM Chip Enable
output reg SRAM_GW_N; // SRAM Global Write Enable
output reg SRAM_OE_N; // SRAM Output Enable
output reg SRAM_WE_N; // SRAM Write Enable
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 3: 0] internal_byteenable;
wire start_write;
// Internal Registers
reg [ 3: 0] read_pipeline;
reg [ 3: 0] byteenable_reg;
reg [31: 0] writedata_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
readdata <= SRAM_DQ;
SRAM_ADDR <= address;
SRAM_ADSP_N <= 1'b1;
SRAM_ADSC_N <= ~(read | start_write);
SRAM_ADV_N <= 1'b1;
SRAM_BE_N[3] <= ~internal_byteenable[3];
SRAM_BE_N[2] <= ~internal_byteenable[2];
SRAM_BE_N[1] <= ~internal_byteenable[1];
SRAM_BE_N[0] <= ~internal_byteenable[0];
SRAM_CE1_N <= ~(read | start_write);
SRAM_CE2 <= (read | start_write);
SRAM_CE3_N <= ~(read | start_write);
SRAM_GW_N <= 1'b1;
SRAM_OE_N <= ~(read_pipeline[1]);
SRAM_WE_N <= ~start_write;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
read_pipeline <= 4'h0;
else
read_pipeline <= {read_pipeline[2:0], read};
end
always @(posedge clk)
begin
if (reset)
byteenable_reg <= 4'h0;
else
byteenable_reg <= internal_byteenable;
end
always @(posedge clk)
begin
writedata_reg <= writedata;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign readdatavalid = read_pipeline[3];
assign waitrequest = write & (|(read_pipeline[2:0]));
assign SRAM_DQ[31:24] = (internal_byteenable[3]) ? writedata_reg[31:24] : 8'hzz;
assign SRAM_DQ[23:16] = (internal_byteenable[2]) ? writedata_reg[23:16] : 8'hzz;
assign SRAM_DQ[15: 8] = (internal_byteenable[1]) ? writedata_reg[15: 8] : 8'hzz;
assign SRAM_DQ[ 7: 0] = (internal_byteenable[0]) ? writedata_reg[ 7: 0] : 8'hzz;
assign SRAM_DPA = 4'hz;
assign SRAM_CLK = clk;
// Internal Assignments
assign internal_byteenable[3] = byteenable[3] & start_write;
assign internal_byteenable[2] = byteenable[2] & start_write;
assign internal_byteenable[1] = byteenable[1] & start_write;
assign internal_byteenable[0] = byteenable[0] & start_write;
assign start_write = write & ~(|(read_pipeline[2:0]));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module altera_mem_if_ddr3_phy_0001_addr_cmd_datapath(
clk,
reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_ddio_odt
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
input reset_n;
input clk;
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
output [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
output [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
output [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
wire [AFI_ADDRESS_WIDTH-1:0] afi_address_r = afi_address;
wire [AFI_BANK_WIDTH-1:0] afi_bank_r = afi_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r = afi_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] afi_cke_r = afi_cke;
wire [AFI_ODT_WIDTH-1:0] afi_odt_r = afi_odt;
wire [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r = afi_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r = afi_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_we_n_r = afi_we_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r = afi_rst_n;
wire [1:0] shift_fr_cycle =
(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
2'b11 )));
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_address(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_address_r),
.dataout (phy_ddio_address)
);
defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_bank(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_bank_r),
.dataout (phy_ddio_bank)
);
defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_cke(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cke_r),
.dataout (phy_ddio_cke)
);
defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_cs_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cs_n_r),
.dataout (phy_ddio_cs_n)
);
defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_odt(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_odt_r),
.dataout (phy_ddio_odt)
);
defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_ras_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_ras_n_r),
.dataout (phy_ddio_ras_n)
);
defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_cas_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cas_n_r),
.dataout (phy_ddio_cas_n)
);
defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_we_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_we_n_r),
.dataout (phy_ddio_we_n)
);
defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_rst_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_rst_n_r),
.dataout (phy_ddio_reset_n)
);
defparam uaddr_cmd_shift_rst_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_rst_n.REG_POST_RESET_HIGH = "true";
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// valid O 1
// word_fst O 64
// word_snd O 5
// verbosity I 4
// CLK I 1 clock
// RST_N I 1 reset
// req_opcode I 7
// req_f7 I 7
// req_rm I 3
// req_rs2 I 5
// req_v1 I 64
// req_v2 I 64
// req_v3 I 64
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFBox_Top(verbosity,
CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input [3 : 0] verbosity;
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid;
// ports of submodule fbox_core
wire [63 : 0] fbox_core$req_v1,
fbox_core$req_v2,
fbox_core$req_v3,
fbox_core$word_fst;
wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode;
wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd;
wire [2 : 0] fbox_core$req_rm;
wire fbox_core$EN_req,
fbox_core$EN_server_reset_request_put,
fbox_core$EN_server_reset_response_get,
fbox_core$RDY_server_reset_request_put,
fbox_core$RDY_server_reset_response_get,
fbox_core$valid;
// rule scheduling signals
wire CAN_FIRE_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
WILL_FIRE_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get;
// action method server_reset_request_put
assign RDY_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign CAN_FIRE_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign CAN_FIRE_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = fbox_core$valid ;
// value method word_fst
assign word_fst = fbox_core$word_fst ;
// value method word_snd
assign word_snd = fbox_core$word_snd ;
// submodule fbox_core
mkFBox_Core fbox_core(.verbosity(verbosity),
.CLK(CLK),
.RST_N(RST_N),
.req_f7(fbox_core$req_f7),
.req_opcode(fbox_core$req_opcode),
.req_rm(fbox_core$req_rm),
.req_rs2(fbox_core$req_rs2),
.req_v1(fbox_core$req_v1),
.req_v2(fbox_core$req_v2),
.req_v3(fbox_core$req_v3),
.EN_server_reset_request_put(fbox_core$EN_server_reset_request_put),
.EN_server_reset_response_get(fbox_core$EN_server_reset_response_get),
.EN_req(fbox_core$EN_req),
.RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get),
.valid(fbox_core$valid),
.word_fst(fbox_core$word_fst),
.word_snd(fbox_core$word_snd));
// submodule fbox_core
assign fbox_core$req_f7 = req_f7 ;
assign fbox_core$req_opcode = req_opcode ;
assign fbox_core$req_rm = req_rm ;
assign fbox_core$req_rs2 = req_rs2 ;
assign fbox_core$req_v1 = req_v1 ;
assign fbox_core$req_v2 = req_v2 ;
assign fbox_core$req_v3 = req_v3 ;
assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ;
assign fbox_core$EN_server_reset_response_get =
EN_server_reset_response_get ;
assign fbox_core$EN_req = EN_req ;
endmodule // mkFBox_Top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_TB_V
`define SKY130_FD_SC_MS__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_TB_V
|
`include "bsg_defines.v"
module test_bsg_data_gen #(parameter `BSG_INV_PARAM( channel_width_p )
, parameter `BSG_INV_PARAM(num_channels_p )
, parameter debug_p = 0
)
(input clk_i
, input reset_i
, input yumi_i
, output [channel_width_p*num_channels_p-1:0] o
);
logic [channel_width_p-1:0] data_r;
always @(posedge clk_i)
if (reset_i)
data_r <= 0;
else
if (yumi_i)
data_r <= data_r + 1;
wire [channel_width_p*num_channels_p-1:0] send_data;
localparam lg_ring_bytes_lp = $clog2(num_channels_p);
localparam ring_width = `BSG_MAX(lg_ring_bytes_lp-1,0);
wire [ring_width:0] ring_bytes = ring_width ' (num_channels_p);
genvar i;
if (num_channels_p > 1)
for (i = 0; i < num_channels_p; i++)
begin
wire [lg_ring_bytes_lp-1:0] my_id = i[lg_ring_bytes_lp-1:0];
if (lg_ring_bytes_lp < channel_width_p)
assign send_data[i*channel_width_p+:channel_width_p]
= { my_id, data_r[0+:channel_width_p-lg_ring_bytes_lp]};
else
assign send_data[i*channel_width_p+:channel_width_p]
= { data_r[0+:channel_width_p]};
end
else
assign send_data[0+:channel_width_p] = data_r;
assign o = send_data;
if (debug_p)
always @(negedge clk_i)
if (yumi_i)
$display("## test_bsg_data_gen %m %x",o);
endmodule // test_bsg_data_gen
`BSG_ABSTRACT_MODULE(test_bsg_data_gen)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_0_V
`define SKY130_FD_SC_LP__AND2_0_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_0 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_0_V
|
//*******************************************************************************************
//Author: Yejoong Kim
//Last Modified: Dec 16 2016
//Description: MBus Master Controller
// Structural verilog netlist using sc_x_hvt_tsmc180
//Update History: May 21 2016 - Updated for MBus r03 (Yejoong Kim)
// Combined the following three modules into one:
// lname_mbus_master_sleep_ctrl
// lname_mbus_master_wire_ctrl
// lname_mbus_int_ctrl
// Fixed potential hold-time violation in ext_int_dout & EXTERNAL_INT
// OLD: int_busy = wakeup_req_ored & mbus_busy_b
// ext_int_dout and EXTERNAL_INT set to mbus_busy_b @ (posedge int_busy)
// NEW: int_busy = wakeup_req_ored & mbus_busy_b & LRC_SLEEP
// ext_int_dout and EXTERNAL_INT set to 1 @ (posedge int_busy)
// Dec 16 2016 - Updated for MBus r04
// Fixed CIN glitch issue
// Now MBUS_BUSY_B is generated in mbus_node
// Apr 28 2017 - Updated for MBus r04p1
// SLEEP_REQ* and MBUS_BUSY are isolated here, rather than in mbus_isolation.
//*******************************************************************************************
module lname_mbus_master_ctrl (
input CLK,
input RESETn,
// MBus Clock & Data
input CIN,
input DIN,
input COUT_FROM_BUS,
input DOUT_FROM_BUS,
output COUT,
output DOUT,
// Sleep & Wakeup Requests
input SLEEP_REQ0,
input SLEEP_REQ1,
input WAKEUP_REQ0,
input WAKEUP_REQ1,
input WAKEUP_REQ2,
input WAKEUP_REQ3,
// Power-Gating Signals
output MBC_ISOLATE,
output MBC_ISOLATE_B,
output MBC_RESET,
output MBC_RESET_B,
output MBC_SLEEP,
output MBC_SLEEP_B,
// Handshaking with MBus Ctrl
input CLR_EXT_INT,
output EXTERNAL_INT,
// Misc
input LRC_SLEEP,
input MBUS_BUSY
);
//****************************************************************************
// Internal Wire Declaration
//****************************************************************************
wire reset;
wire reset_b;
wire din_b;
wire mbc_isolate_b_int;
wire mbc_reset_b_int;
wire mbc_sleep_b_int;
wire mbc_sleep_b_unbuf;
wire mbc_sleep_unbuf;
wire wr01_nor;
wire wr23_nor;
wire wakeup_req_ored_b;
wire wakeup_req_ored;
wire sleep_req0_b;
wire sleep_req1_b;
wire sleep_req;
wire sleep_req_b;
wire set_tran_to_wake_in_sleep;
wire going_sleep;
wire setn_tran_to_wake;
wire rstn_tran_to_wake;
wire tran_to_wake_int;
wire tran_to_wake_b;
wire tran_to_wake;
wire next_mbc_isolate;
wire next_mbc_sleep_int;
wire mbc_isolate_int;
wire mbc_sleep_int;
wire mbc_reset_int;
wire clr_ext_int_iso;
wire clr_ext_int_b;
wire RESETn_local;
wire RESETn_local2;
wire mbus_busy_b_isol;
wire int_busy;
wire int_busy_b;
wire ext_int_dout;
wire cout_from_bus_iso;
wire cout_int;
wire cout_unbuf;
wire dout_from_bus_iso;
wire dout_int_1;
wire dout_int_0;
wire dout_unbuf;
// ---------------------------------------------
// NOTE: Functional Relationship:
// ---------------------------------------------
// MBC_ISOLATE = mbc_isolate_int
// MBC_ISOLATE_B = mbc_isolate_b_int
// MBC_RESET = mbc_reset_int
// MBC_SLEEP = mbc_sleep_unbuf
// MBC_SLEEP_B = mbc_sleep_b_unbuf
// ---------------------------------------------
// clr_ext_int_b = ~clr_ext_int_iso
// ---------------------------------------------
// MBC_SLEEP != mbc_sleep_int
// MBC_SLEEP_B != mbc_sleep_b)int
// ---------------------------------------------
//****************************************************************************
// GLOBAL
//****************************************************************************
// Global Reset Buffer
INVX1HVT INV_reset (.Y(reset), .A(RESETn));
INVX1HVT INV_reset_b (.Y(reset_b), .A(reset));
// din_b = ~DIN
INVX1HVT INV_din_b (.A(DIN), .Y(din_b));
//****************************************************************************
// SLEEP CONTROLLER
//****************************************************************************
// assign MBC_ISOLATE_B = ~MBC_ISOLATE;
INVX8HVT INV_MBC_ISOLATE_B (.Y(MBC_ISOLATE_B), .A(mbc_isolate_int));
INVX8HVT INV_MBC_ISOLATE (.Y(MBC_ISOLATE), .A(mbc_isolate_b_int));
INVX8HVT INV_mbc_isolate_b_int (.Y(mbc_isolate_b_int), .A(mbc_isolate_int));
// assign MBC_RESET_B = ~MBC_RESET;
INVX1HVT INV_mbc_reset_b_int (.Y(mbc_reset_b_int), .A(mbc_reset_int));
INVX8HVT INV_MBC_RESET (.Y(MBC_RESET), .A(mbc_reset_b_int));
INVX8HVT INV_MBC_RESET_B (.Y(MBC_RESET_B), .A(mbc_reset_int));
// assign MBC_SLEEP_B = ~MBC_SLEEP;
INVX8HVT INV_mbc_sleep_b_int (.Y(mbc_sleep_b_int), .A(mbc_sleep_int));
INVX1HVT INV_mbc_sleep_b_unbuf (.Y(mbc_sleep_b_unbuf), .A(mbc_sleep_unbuf));
INVX8HVT INV_MBC_SLEEP_B (.Y(MBC_SLEEP_B), .A(mbc_sleep_unbuf));
INVX8HVT INV_MBC_SLEEP (.Y(MBC_SLEEP), .A(mbc_sleep_b_unbuf));
// assign MBC_SLEEP = mbc_sleep_int & DIN;
AND2X1HVT AND2_mbc_sleep_unbuf (.A(DIN), .B(mbc_sleep_int), .Y(mbc_sleep_unbuf));
// wire wakeup_req_ored = WAKEUP_REQ0 | WAKEUP_REQ1 | WAKEUP_REQ2 | WAKEUP_REQ3;
NOR2X1HVT NOR2_wr01_nor (.A(WAKEUP_REQ0), .B(WAKEUP_REQ1), .Y(wr01_nor));
NOR2X1HVT NOR2_wr23_nor (.A(WAKEUP_REQ2), .B(WAKEUP_REQ3), .Y(wr23_nor));
AND2X1HVT AND2_wakeup_req_ored_b (.A(wr01_nor), .B(wr23_nor), .Y(wakeup_req_ored_b));
INVX1HVT INV_wakeup_req_ored (.Y(wakeup_req_ored), .A(wakeup_req_ored_b));
// wire sleep_req = (~MBC_ISOLATE) & (SLEEP_REQ0 | SLEEP_REQ1);
NAND2X1HVT NAND2_sleep_req0_b (.Y(sleep_req0_b), .A(SLEEP_REQ0), .B(mbc_isolate_b_int));
NAND2X1HVT NAND2_sleep_req1_b (.Y(sleep_req1_b), .A(SLEEP_REQ1), .B(mbc_isolate_b_int));
NAND2X1HVT NAND2_sleep_req (.Y(sleep_req), .A(sleep_req1_b), .B(sleep_req0_b));
INVX1HVT INV_sleep_req_b (.Y(sleep_req_b), .A(sleep_req));
// wire set_tran_to_wake_in_sleep = mbc_sleep_int & ~DIN;
AND2X1HVT AND2_set_tran_to_wake_in_sleep (.A(din_b), .B(mbc_sleep_int), .Y(set_tran_to_wake_in_sleep));
// wire going_sleep = ~set_tran_to_wake_in_sleep & sleep_req;
NOR2X1HVT NOR2_going_sleep (.B(sleep_req_b), .A(set_tran_to_wake_in_sleep), .Y(going_sleep));
// setn_tran_to_wake (= ~set_tran_to_wake)
NAND2X1HVT NAND2_setn_tran_to_wake (.B(reset_b), .A(set_tran_to_wake_in_sleep), .Y(setn_tran_to_wake));
// rstn_tran_to_wake (= ~rst_tran_to_wake)
NOR2X1HVT NOR2_rstn_tran_to_wake (.Y(rstn_tran_to_wake), .A(reset), .B(going_sleep));
// tran_to_wake
NAND2X1HVT NAND2_tran_to_wake_int (.A(setn_tran_to_wake), .B(tran_to_wake_b), .Y(tran_to_wake_int));
NAND2X1HVT NAND2_tran_to_wake_b (.A(rstn_tran_to_wake), .B(tran_to_wake_int), .Y(tran_to_wake_b));
INVX2HVT INV_tran_to_wake (.A(tran_to_wake_b), .Y(tran_to_wake));
// wire next_mbc_isolate = mbc_sleep_int | ~tran_to_wake;
NAND2X1HVT NAND2_next_mbc_isolate (.Y(next_mbc_isolate), .A(mbc_sleep_b_int), .B(tran_to_wake));
// wire next_mbc_sleep_int = MBC_ISOLATE & ~tran_to_wake;
NOR2X1HVT NOR2_next_mbc_sleep_int (.B(tran_to_wake), .A(mbc_isolate_b_int), .Y(next_mbc_sleep_int));
// MBC_ISOLATE, mbc_sleep_int, MBC_RESET
DFFSX1HVT DFFS_mbc_isolate_int (.SN(reset_b), .CK(CLK), .Q(mbc_isolate_int), .D(next_mbc_isolate));
DFFSX1HVT DFFS_mbc_sleep_int (.SN(reset_b), .CK(CLK), .Q(mbc_sleep_int), .D(next_mbc_sleep_int));
DFFSX1HVT DFFS_mbc_reset_int (.SN(reset_b), .CK(CLK), .Q(mbc_reset_int), .D(mbc_isolate_int));
//****************************************************************************
// INTERRUPT CONTROLLER
//****************************************************************************
//wire clr_ext_int_b = ~(MBC_ISOLATE_B & CLR_EXT_INT);
AND2X1HVT AND2_clr_ext_int_iso (.Y(clr_ext_int_iso), .A(MBC_ISOLATE_B), .B(CLR_EXT_INT));
INVX1HVT INV_clr_ext_int_b (.Y(clr_ext_int_b), .A(clr_ext_int_iso));
//wire RESETn_local = RESETn & CIN;
AND2X1HVT AND2_RESETn_local (.Y(RESETn_local), .A(CIN), .B(RESETn));
//wire RESETn_local2 = RESETn & clr_ext_int_b;
AND2X1HVT AND2_RESETn_local2 (.Y(RESETn_local2), .A(clr_ext_int_b), .B(RESETn));
//wire mbus_busy_b_isol = ~(MBUS_BUSY & MBC_RESET_B);
NAND2X1HVT NAND2_mbus_busy_b_isol (.A(MBUS_BUSY), .B(MBC_RESET_B), .Y(mbus_busy_b_isol));
//wire int_busy = (wakeup_req_ored & mbus_busy_b_isol & LRC_SLEEP)
NAND3X1HVT NAND3_int_busy_b (.A(wakeup_req_ored), .B(mbus_busy_b_isol), .C(LRC_SLEEP), .Y(int_busy_b));
INVX2HVT INV_int_busy (.Y(int_busy), .A(int_busy_b));
// ext_int_dout
DFFRX1HVT DFFR_ext_int_dout (.RN(RESETn_local), .CK(int_busy), .Q(ext_int_dout), .D(1'b1));
// EXTERNAL_INT
DFFRX1HVT DFFR_EXTERNAL_INT (.RN(RESETn_local2), .CK(int_busy), .Q(EXTERNAL_INT), .D(1'b1));
//****************************************************************************
// WIRE CONTROLLER
//****************************************************************************
// COUT
OR2X1HVT OR2_cout_from_bus_iso (.Y(cout_from_bus_iso), .A(COUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2GFX1HVT MUX2_cout_int (.S(MBC_ISOLATE), .A(cout_from_bus_iso), .Y(cout_int), .B(1'b1));
MUX2GFX1HVT MUX2_cout_unbuf (.S(RESETn), .A(1'b1), .Y(cout_unbuf), .B(cout_int));
BUFX4HVT BUF_COUT (.A(cout_unbuf), .Y(COUT));
// DOUT
OR2X1HVT OR2_dout_from_bus_iso (.Y(dout_from_bus_iso), .A(DOUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2GFX1HVT MUX2_dout_int_1 (.S(MBC_ISOLATE), .A(dout_from_bus_iso), .Y(dout_int_1), .B(1'b1));
MUX2GFX1HVT MUX2_dout_int_0 (.S(ext_int_dout), .A(dout_int_1), .Y(dout_int_0), .B(1'b0));
MUX2GFX1HVT MUX2_dout_unbuf (.S(RESETn), .A(1'b1), .Y(dout_unbuf), .B(dout_int_0));
BUFX4HVT BUF_DOUT (.A(dout_unbuf), .Y(DOUT));
endmodule // lname_mbus_master_ctrl
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND4B_PP_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_PP_BLACKBOX_V
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mux
// ============================================================
// File Name: scorecopymux.v
// Megafunction Name(s):
// lpm_mux
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module scorecopymux (
data0x,
data1x,
data2x,
data3x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input [3:0] data2x;
input [3:0] data3x;
input [1:0] sel;
output [3:0] result;
wire [3:0] sub_wire0;
wire [3:0] sub_wire5 = data3x[3:0];
wire [3:0] sub_wire4 = data1x[3:0];
wire [3:0] sub_wire3 = data0x[3:0];
wire [3:0] result = sub_wire0[3:0];
wire [3:0] sub_wire1 = data2x[3:0];
wire [15:0] sub_wire2 = {sub_wire5, sub_wire1, sub_wire4, sub_wire3};
lpm_mux lpm_mux_component (
.sel (sel),
.data (sub_wire2),
.result (sub_wire0)
// synopsys translate_off
,
.clock (),
.clken (),
.aclr ()
// synopsys translate_on
);
defparam
lpm_mux_component.lpm_size = 4,
lpm_mux_component.lpm_type = "LPM_MUX",
lpm_mux_component.lpm_width = 4,
lpm_mux_component.lpm_widths = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
// Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL data0x[3..0]
// Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL data1x[3..0]
// Retrieval info: USED_PORT: data2x 0 0 4 0 INPUT NODEFVAL data2x[3..0]
// Retrieval info: USED_PORT: data3x 0 0 4 0 INPUT NODEFVAL data3x[3..0]
// Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL result[3..0]
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
// Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 12 data3x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 8 data2x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 4 data1x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 0 data0x 0 0 4 0
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL scorecopymux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL scorecopymux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scorecopymux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scorecopymux.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scorecopymux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL scorecopymux_bb.v TRUE
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module sram_fifo
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter DEPTH = 21'h10_0000,
parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent
parameter FIFO_ALMOST_EMPTY_THRESHOLD = 5 // in percent
) (
// input BUS_CLK270,
input wire BUS_CLK,
input wire BUS_RST,
input wire [15:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire [19:0] SRAM_A,
inout wire [15:0] SRAM_IO,
output wire SRAM_BHE_B,
output wire SRAM_BLE_B,
output wire SRAM_CE1_B,
output wire SRAM_OE_B,
output wire SRAM_WE_B,
input wire USB_READ,
output wire [7:0] USB_DATA,
output wire FIFO_READ_NEXT_OUT,
input wire FIFO_EMPTY_IN,
input wire [31:0] FIFO_DATA,
output wire FIFO_NOT_EMPTY,
output wire FIFO_FULL,
output wire FIFO_NEAR_FULL,
output wire FIFO_READ_ERROR
);
wire IP_RD, IP_WR;
wire [15:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
sram_fifo_core #(
.DEPTH(DEPTH),
.FIFO_ALMOST_FULL_THRESHOLD(FIFO_ALMOST_FULL_THRESHOLD),
.FIFO_ALMOST_EMPTY_THRESHOLD(FIFO_ALMOST_EMPTY_THRESHOLD)
) i_sram_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.USB_READ(USB_READ),
.USB_DATA(USB_DATA),
.FIFO_READ_NEXT_OUT(FIFO_READ_NEXT_OUT),
.FIFO_EMPTY_IN(FIFO_EMPTY_IN),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(FIFO_NOT_EMPTY),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
.FIFO_READ_ERROR(FIFO_READ_ERROR)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND3_PP_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : DIFFINBUF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// 10/22/14 808642 Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DIFFINBUF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter ISTANDARD = "UNUSED",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
output O_B,
input DIFF_IN_N,
input DIFF_IN_P,
input [3:0] OSC,
input [1:0] OSC_EN,
input VREF
);
// define constants
localparam MODULE_NAME = "DIFFINBUF";
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 0;
localparam DIFF_TERM_TRUE = 1;
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
reg trig_attr = 1'b0;
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
wire DIFF_TERM_BIN;
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg O_B_out;
reg O_out;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
`ifdef XIL_TIMING
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
`endif
reg O_OSC_in;
reg O_B_OSC_in;
integer OSC_int = 0;
assign O = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out;
assign O_B = (OSC_EN_in === 2'b11) ? O_B_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_B_out;
`ifdef XIL_TIMING
assign OSC_EN_in[0] = OSC_EN_delay[0];
assign OSC_EN_in[1] = OSC_EN_delay[1];
assign OSC_in = OSC_delay;
`else
assign OSC_EN_in[0] = OSC_EN[0];
assign OSC_EN_in[1] = OSC_EN[1];
assign OSC_in = OSC;
`endif
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_FALSE;
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-106] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin
$display("Error: [Unisim %s-111] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-104] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in === 2'b11) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin
O_OSC_in <= ~O_OSC_in;
O_B_OSC_in <= ~O_B_OSC_in;
end
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0) begin
O_OSC_in <= 1'bx;
O_B_OSC_in <= 1'bx;
end
end
always @(DIFF_IN_P or DIFF_IN_N or DQS_BIAS_BIN) begin
if (DIFF_IN_P == 1'b1 && DIFF_IN_N == 1'b0) begin
O_out <= 1'b1;
O_B_out <= 1'b0;
end
else if (DIFF_IN_P == 1'b0 && DIFF_IN_N == 1'b1) begin
O_out <= 1'b0;
O_B_out <= 1'b1;
end
else if ((DIFF_IN_P === 1'bz || DIFF_IN_P == 1'b0) && (DIFF_IN_N === 1'bz || DIFF_IN_N == 1'b1)) begin
if (DQS_BIAS_BIN == 1'b1) begin
O_out <= 1'b0;
O_B_out <= 1'b1;
end
else begin
O_out <= 1'bx;
O_B_out <= 1'bx;
end
end else if ((DIFF_IN_P === 1'bx) || (DIFF_IN_N === 1'bx)) begin
O_out <= 1'bx;
O_B_out <= 1'bx;
end
// O_out <= DIFF_IN_P;
// O_B_out <= DIFF_IN_N;
end
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(DIFF_IN_N => O) = (0:0:0, 0:0:0);
(DIFF_IN_N => O_B) = (0:0:0, 0:0:0);
(DIFF_IN_P => O) = (0:0:0, 0:0:0);
(DIFF_IN_P => O_B) = (0:0:0, 0:0:0);
(OSC *> O) = (0:0:0, 0:0:0);
(OSC *> O_B) = (0:0:0, 0:0:0);
(OSC_EN *> O) = (0:0:0, 0:0:0);
(OSC_EN *> O_B) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$setuphold (negedge OSC_EN, negedge OSC, 0:0:0, 0:0:0, notifier, , , OSC_EN_delay, OSC_delay);
$setuphold (negedge OSC_EN, posedge OSC, 0:0:0, 0:0:0, notifier, , , OSC_EN_delay, OSC_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:03:21 10/28/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart(
input clk,
input reset,
input rxin,
output txout,
output [7:0] Led
);
`define TXREG 3'b001
`define CONTROLTX 3'b011
`define RXREG 3'b101
`define CONTROLRX 3'b111
`define TXR 2'b00
`define CTX 2'b01
`define RXR 2'b10
`define CRX 2'b11
`define START 3'b000
`define WAITRX 3'b001
`define PASSTX 3'b010
`define WRTX 3'b011
`define WAITTX 3'b100
`define CLRTX 3'b101
`define WAITWRTX 3'b110
`define STOP 3'b111//used for debug
`define RXREADY to_tx[1]
`define TXREADY tx_out[1]
`define TXWRRDY tx_out[0]
wire [7:0] to_tx;
wire [1:0] tx_out;
reg [2:0] addr, pstate, nstate;
reg [1:0] addmux;
reg [3:0] din;
reg [7:0] cache, leds;
reg wr_rx, rd_rx, wr_tx, rd_tx, ld, cl;
uart_rx #(.PERIOD(8'h0C)) RX(
.clk (clk),
.reset (reset),
.wren (wr_rx),
.rden (rd_rx),
.din (1'b1),
.dout (to_tx),
.rxin (rxin),
.addr (addr)
);
uart_tx #(.PERIOD(8'h0C)) TX(
.clk (clk),
.reset (reset),
.wren (wr_tx),
.rden (rd_tx),
.din (cache),
.dout (tx_out),
.txout (txout),
.addr (addr)
);
assign Led = leds;
always @* begin
addr = 3'b010;
case(addmux)
`TXR:
addr = `TXREG;
`CTX:
addr = `CONTROLTX;
`RXR:
addr = `RXREG;
`CRX:
addr = `CONTROLRX;
endcase
end
always @(posedge clk or posedge reset) begin
if(reset) begin
cache <= 8'b11111111;
leds <= 8'b11111111;
end
else begin
if(ld)
cache <= to_tx + 1;
if(cl) begin
cache <= 8'b00000000;
leds <= cache;
end
end
end
always @(posedge clk or posedge reset) begin
if(reset)
pstate <= `START;
else begin
pstate <= nstate;
end
end
always @* begin
wr_rx = 0; rd_rx = 0;
wr_tx = 0; rd_tx = 0;
ld = 0; cl = 0;
addmux = `CRX;
nstate = pstate;
case(pstate)
`START: begin
wr_rx = 1;
nstate = `WAITRX;
end
`WAITRX: begin
rd_rx = 1;
if(`RXREADY)
nstate = `PASSTX;
end
`PASSTX: begin
rd_rx = 1;
addmux = `RXR;
ld = 1;
nstate = `WAITWRTX;
end
`WAITWRTX: begin
rd_tx = 1;
addmux = `CTX;
if(~`TXWRRDY)
nstate = `WRTX;
end
`WRTX: begin
wr_tx = 1;
addmux = `TXR;
nstate = `WAITTX;
end
`WAITTX: begin
rd_tx = 1;
addmux = `CTX;
if(`TXREADY) begin
cl = 1;
nstate = `CLRTX;
end
end
`CLRTX: begin
wr_tx = 1;
addmux = `CTX;
nstate = `WAITRX;
end
`STOP: begin
nstate = `STOP;
end
endcase
end
endmodule
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