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// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_125_250.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Internal Build 139 08/21/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_125_250 (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire2 = 1'h0;
wire [0:0] sub_wire4 = 1'h1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
altpll altpll_component (
.clkena (sub_wire3),
.inclk (sub_wire6),
.extclkena (sub_wire7),
.areset (areset),
.clk (sub_wire0)
// synopsys translate_off
,
.scanclk (),
.pllena (),
.sclkout1 (),
.sclkout0 (),
.fbin (),
.scandone (),
.clkloss (),
.extclk (),
.clkswitch (),
.pfdena (),
.scanaclr (),
.clkbad (),
.scandata (),
.enable1 (),
.scandataout (),
.enable0 (),
.scanwrite (),
.locked (),
.activeclock (),
.scanread ()
// synopsys translate_on
);
defparam
altpll_component.bandwidth = 500000,
altpll_component.bandwidth_type = "CUSTOM",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 8000,
altpll_component.intended_device_family = "Stratix GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "ENHANCED",
altpll_component.spread_frequency = 0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "250.000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_wave*.jpg FALSE FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A211O_PP_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DFBBN_PP_SYMBOL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_PP_SYMBOL_V
|
//
// Generated by Bluespec Compiler, version 2011.03.beta1 (build 23381, 2011-03-08)
//
// On Tue May 24 06:35:33 EDT 2011
//
// Method conflict info:
// Method: portA_request_put
// Conflict-free: portA_response_get, portAClear
// Conflicts: portA_request_put
//
// Method: portA_response_get
// Conflict-free: portA_request_put
// Sequenced before (restricted): portAClear
// Conflicts: portA_response_get
//
// Method: portAClear
// Conflict-free: portA_request_put
// Sequenced after (restricted): portA_response_get
// Conflicts: portAClear
//
//
// Ports:
// Name I/O size props
// RDY_portA_request_put O 1
// portA_response_get O 32
// RDY_portA_response_get O 1
// CLK I 1 clock
// RST_N I 1 reset
// portA_request_put I 44
// EN_portA_request_put I 1
// EN_portAClear I 1
// EN_portA_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkBRAM100(CLK,
RST_N,
portA_request_put,
EN_portA_request_put,
RDY_portA_request_put,
EN_portA_response_get,
portA_response_get,
RDY_portA_response_get,
EN_portAClear);
input CLK;
input RST_N;
// action method portA_request_put
input [43 : 0] portA_request_put;
input EN_portA_request_put;
output RDY_portA_request_put;
// actionvalue method portA_response_get
input EN_portA_response_get;
output [31 : 0] portA_response_get;
output RDY_portA_response_get;
// action method portAClear
input EN_portAClear;
// signals for module outputs
wire [31 : 0] portA_response_get;
wire RDY_portA_request_put, RDY_portA_response_get;
// inlined wires
wire [1 : 0] bram_serverAdapter_s1_1$wget;
wire bram_serverAdapter_cnt_1$whas,
bram_serverAdapter_outData_enqData$whas,
bram_serverAdapter_outData_outData$whas,
bram_serverAdapter_s1_1$whas;
// register bram_serverAdapter_cnt
reg [2 : 0] bram_serverAdapter_cnt;
wire [2 : 0] bram_serverAdapter_cnt$D_IN;
wire bram_serverAdapter_cnt$EN;
// register bram_serverAdapter_s1
reg [1 : 0] bram_serverAdapter_s1;
wire [1 : 0] bram_serverAdapter_s1$D_IN;
wire bram_serverAdapter_s1$EN;
// ports of submodule bram_memory
wire [31 : 0] bram_memory$DI, bram_memory$DO;
wire [9 : 0] bram_memory$ADDR;
wire bram_memory$EN, bram_memory$WE;
// ports of submodule bram_serverAdapter_outDataCore
wire [31 : 0] bram_serverAdapter_outDataCore$D_IN,
bram_serverAdapter_outDataCore$D_OUT;
wire bram_serverAdapter_outDataCore$CLR,
bram_serverAdapter_outDataCore$DEQ,
bram_serverAdapter_outDataCore$EMPTY_N,
bram_serverAdapter_outDataCore$ENQ,
bram_serverAdapter_outDataCore$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_bram_serverAdapter_outData_enqAndDeq;
// inputs to muxes for submodule ports
wire [1 : 0] MUX_bram_serverAdapter_s1_1$wset_1__VAL_1;
// remaining internal signals
wire [2 : 0] bram_serverAdapter_cnt_6_PLUS_IF_bram_serverAd_ETC___d32;
wire [1 : 0] portA_request_put_BITS_43_TO_42__q1;
// action method portA_request_put
assign RDY_portA_request_put = (bram_serverAdapter_cnt ^ 3'h4) < 3'd7 ;
// actionvalue method portA_response_get
assign portA_response_get =
bram_serverAdapter_outDataCore$EMPTY_N ?
bram_serverAdapter_outDataCore$D_OUT :
bram_memory$DO ;
assign RDY_portA_response_get =
(bram_serverAdapter_outDataCore$EMPTY_N ||
bram_serverAdapter_outData_enqData$whas) &&
bram_serverAdapter_outData_outData$whas ;
// submodule bram_memory
BRAM1 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) bram_memory(.CLK(CLK),
.ADDR(bram_memory$ADDR),
.DI(bram_memory$DI),
.WE(bram_memory$WE),
.EN(bram_memory$EN),
.DO(bram_memory$DO));
// submodule bram_serverAdapter_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_serverAdapter_outDataCore(.RST_N(RST_N),
.CLK(CLK),
.D_IN(bram_serverAdapter_outDataCore$D_IN),
.ENQ(bram_serverAdapter_outDataCore$ENQ),
.DEQ(bram_serverAdapter_outDataCore$DEQ),
.CLR(bram_serverAdapter_outDataCore$CLR),
.D_OUT(bram_serverAdapter_outDataCore$D_OUT),
.FULL_N(bram_serverAdapter_outDataCore$FULL_N),
.EMPTY_N(bram_serverAdapter_outDataCore$EMPTY_N));
// rule RL_bram_serverAdapter_outData_enqAndDeq
assign WILL_FIRE_RL_bram_serverAdapter_outData_enqAndDeq =
bram_serverAdapter_outDataCore$EMPTY_N &&
bram_serverAdapter_outDataCore$FULL_N &&
EN_portA_response_get &&
bram_serverAdapter_outData_enqData$whas ;
// inputs to muxes for submodule ports
assign MUX_bram_serverAdapter_s1_1$wset_1__VAL_1 =
{ 1'd1,
!portA_request_put_BITS_43_TO_42__q1[1] ||
portA_request_put_BITS_43_TO_42__q1[0] } ;
// inlined wires
assign bram_serverAdapter_outData_enqData$whas =
bram_serverAdapter_outDataCore$FULL_N &&
bram_serverAdapter_s1[1] &&
bram_serverAdapter_s1[0] ;
assign bram_serverAdapter_outData_outData$whas =
bram_serverAdapter_outDataCore$EMPTY_N ||
!bram_serverAdapter_outDataCore$EMPTY_N &&
bram_serverAdapter_outData_enqData$whas ;
assign bram_serverAdapter_cnt_1$whas =
EN_portA_request_put &&
(!portA_request_put_BITS_43_TO_42__q1[1] ||
portA_request_put_BITS_43_TO_42__q1[0]) ;
assign bram_serverAdapter_s1_1$wget =
EN_portA_request_put ?
MUX_bram_serverAdapter_s1_1$wset_1__VAL_1 :
2'd0 ;
assign bram_serverAdapter_s1_1$whas =
EN_portA_request_put || EN_portAClear ;
// register bram_serverAdapter_cnt
assign bram_serverAdapter_cnt$D_IN =
EN_portAClear ?
3'd0 :
bram_serverAdapter_cnt_6_PLUS_IF_bram_serverAd_ETC___d32 ;
assign bram_serverAdapter_cnt$EN =
bram_serverAdapter_cnt_1$whas || EN_portA_response_get ||
EN_portAClear ;
// register bram_serverAdapter_s1
assign bram_serverAdapter_s1$D_IN =
{ bram_serverAdapter_s1_1$whas &&
bram_serverAdapter_s1_1$wget[1],
bram_serverAdapter_s1_1$wget[0] } ;
assign bram_serverAdapter_s1$EN = 1'd1 ;
// submodule bram_memory
assign bram_memory$ADDR = portA_request_put[41:32] ;
assign bram_memory$DI = portA_request_put[31:0] ;
assign bram_memory$WE = portA_request_put[43] ;
assign bram_memory$EN = EN_portA_request_put ;
// submodule bram_serverAdapter_outDataCore
assign bram_serverAdapter_outDataCore$D_IN = bram_memory$DO ;
assign bram_serverAdapter_outDataCore$ENQ =
WILL_FIRE_RL_bram_serverAdapter_outData_enqAndDeq ||
bram_serverAdapter_outDataCore$FULL_N &&
!EN_portA_response_get &&
bram_serverAdapter_outData_enqData$whas ;
assign bram_serverAdapter_outDataCore$DEQ =
WILL_FIRE_RL_bram_serverAdapter_outData_enqAndDeq ||
bram_serverAdapter_outDataCore$EMPTY_N &&
EN_portA_response_get &&
!bram_serverAdapter_outData_enqData$whas ;
assign bram_serverAdapter_outDataCore$CLR = EN_portAClear ;
// remaining internal signals
assign bram_serverAdapter_cnt_6_PLUS_IF_bram_serverAd_ETC___d32 =
bram_serverAdapter_cnt +
(bram_serverAdapter_cnt_1$whas ? 3'd1 : 3'd0) +
(EN_portA_response_get ? 3'd7 : 3'd0) ;
assign portA_request_put_BITS_43_TO_42__q1 = portA_request_put[43:42] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
bram_serverAdapter_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_serverAdapter_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (bram_serverAdapter_cnt$EN)
bram_serverAdapter_cnt <= `BSV_ASSIGNMENT_DELAY
bram_serverAdapter_cnt$D_IN;
if (bram_serverAdapter_s1$EN)
bram_serverAdapter_s1 <= `BSV_ASSIGNMENT_DELAY
bram_serverAdapter_s1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
bram_serverAdapter_cnt = 3'h2;
bram_serverAdapter_s1 = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N)
if (bram_serverAdapter_s1[1] && !bram_serverAdapter_outDataCore$FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
end
// synopsys translate_on
endmodule // mkBRAM100
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: two_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module two_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/two_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/two_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//
// Copyright (C) 2015 Markus Hiienkari <[email protected]>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`define STATE_IDLE 2'b00
`define STATE_LEADVERIFY 2'b01
`define STATE_DATARCV 2'b10
module ir_rcv (
input clk50,
input reset_n,
input ir_rx,
output reg [31:0] ir_code,
output reg ir_code_ack
);
// 20ns clock period
parameter LEADCODE_LO_THOLD = 230000; //4.60ms
parameter LEADCODE_HI_THOLD = 210000; //4.20ms
parameter LEADCODE_HI_RPT_THOLD = 105000; //2.1ms
parameter RPT_RELEASE_THOLD = 6000000; //120ms
parameter BIT_ONE_THOLD = 41500; //0.83ms
parameter BIT_DETECT_THOLD = 20000; //0.4ms
parameter IDLE_THOLD = 262143; //5.24ms
reg [1:0] state; // 3 states
reg [31:0] databuf; // temp. buffer
reg [5:0] bits_detected; // max. 63, effectively between 0 and 33
reg [17:0] act_cnt; // max. 5.2ms
reg [17:0] leadvrf_cnt; // max. 5.2ms
reg [17:0] datarcv_cnt; // max. 5.2ms
reg [22:0] rpt_cnt; // max. 166ms
// activity when signal is low
always @(posedge clk50 or negedge reset_n)
begin
if (!reset_n)
act_cnt <= 0;
else
begin
if ((state == `STATE_IDLE) & (~ir_rx))
act_cnt <= act_cnt + 1'b1;
else
act_cnt <= 0;
end
end
// lead code verify counter
always @(posedge clk50 or negedge reset_n)
begin
if (!reset_n)
leadvrf_cnt <= 0;
else
begin
if ((state == `STATE_LEADVERIFY) & ir_rx)
leadvrf_cnt <= leadvrf_cnt + 1'b1;
else
leadvrf_cnt <= 0;
end
end
// '0' and '1' are differentiated by high phase duration preceded by constant length low phase
always @(posedge clk50 or negedge reset_n)
begin
if (!reset_n)
begin
datarcv_cnt <= 0;
bits_detected <= 0;
databuf <= 0;
end
else
begin
if (state == `STATE_DATARCV)
begin
if (ir_rx)
datarcv_cnt <= datarcv_cnt + 1'b1;
else
datarcv_cnt <= 0;
if (datarcv_cnt == BIT_DETECT_THOLD)
bits_detected <= bits_detected + 1'b1;
if (datarcv_cnt == BIT_ONE_THOLD)
databuf[32-bits_detected] <= 1'b1;
end
else
begin
datarcv_cnt <= 0;
bits_detected <= 0;
databuf <= 0;
end
end
end
// read and validate data after 32 bits detected (last bit may change to '1' at any time)
always @(posedge clk50 or negedge reset_n)
begin
if (!reset_n)
begin
ir_code_ack <= 1'b0;
ir_code <= 32'h00000000;
end
else
begin
if ((bits_detected == 32) & (databuf[15:8] == ~databuf[7:0]))
begin
ir_code <= databuf;
ir_code_ack <= 1'b1;
end
else if (rpt_cnt >= RPT_RELEASE_THOLD)
begin
ir_code <= 32'h00000000;
ir_code_ack <= 1'b0;
end
else
ir_code_ack <= 1'b0;
end
end
always @(posedge clk50 or negedge reset_n)
begin
if (!reset_n)
begin
state <= `STATE_IDLE;
rpt_cnt <= 0;
end
else
begin
rpt_cnt <= rpt_cnt + 1'b1;
case (state)
`STATE_IDLE:
if (act_cnt >= LEADCODE_LO_THOLD)
state <= `STATE_LEADVERIFY;
`STATE_LEADVERIFY:
begin
if (leadvrf_cnt == LEADCODE_HI_RPT_THOLD)
rpt_cnt <= 0;
if (leadvrf_cnt >= LEADCODE_HI_THOLD)
state <= `STATE_DATARCV;
end
`STATE_DATARCV:
if ((datarcv_cnt >= IDLE_THOLD) | (bits_detected >= 33))
state <= `STATE_IDLE;
default:
state <= `STATE_IDLE;
endcase
end
end
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_systeminit_mrdwr.v
// Version : v1.0
// Description: master read channel: Issue read commands based on the
// cmdgen block output
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_systeminit_mrdwr #
(
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_M_AXI_AWUSER_WIDTH = 8 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_ATG_SYSTEM_INIT = 0 ,
parameter C_ATG_SYSTEM_TEST = 0 ,
parameter C_ATG_SYSTEM_CMD_MAX_RETRY = 32'hA ,
parameter C_ATG_SYSTEM_TEST_MAX_CLKS = 1000 ,
parameter C_ATG_SYSTEM_MAX_CHANNELS = 32'h1 ,
parameter C_ATG_SYSTEM_CH1_LOW = 32'h0000_0000 ,
parameter C_ATG_SYSTEM_CH1_HIGH = 32'h0000_00FF ,
parameter C_ATG_SYSTEM_CH2_LOW = 32'h0000_0100 ,
parameter C_ATG_SYSTEM_CH2_HIGH = 32'h0000_01FF ,
parameter C_ATG_SYSTEM_CH3_LOW = 32'h0000_0200 ,
parameter C_ATG_SYSTEM_CH3_HIGH = 32'h0000_02FF ,
parameter C_ATG_SYSTEM_CH4_LOW = 32'h0000_0300 ,
parameter C_ATG_SYSTEM_CH4_HIGH = 32'h0000_03FF ,
parameter C_ATG_SYSTEM_CH5_LOW = 32'h0000_0400 ,
parameter C_ATG_SYSTEM_CH5_HIGH = 32'h0000_04FF
) (
// system
input Clk ,
input rst_l ,
//CH1
output [31:0] ch1_awaddr_m ,
output ch1_awvalid_m ,
input ch1_awready_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch1_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch1_wstrb_m ,
output ch1_wvalid_m ,
input ch1_wready_m ,
input [1:0] ch1_bresp_m ,
input ch1_bvalid_m ,
output ch1_bready_m ,
output [31:0] ch1_araddr_m ,
output ch1_arvalid_m ,
input ch1_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch1_rdata_m ,
input ch1_rvalid_m ,
input [1:0] ch1_rresp_m ,
output ch1_rready_m ,
//CH2
output [31:0] ch2_awaddr_m ,
output ch2_awvalid_m ,
input ch2_awready_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch2_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch2_wstrb_m ,
output ch2_wvalid_m ,
input ch2_wready_m ,
input [1:0] ch2_bresp_m ,
input ch2_bvalid_m ,
output ch2_bready_m ,
output [31:0] ch2_araddr_m ,
output ch2_arvalid_m ,
input ch2_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch2_rdata_m ,
input ch2_rvalid_m ,
input [1:0] ch2_rresp_m ,
output ch2_rready_m ,
//CH3
output [31:0] ch3_awaddr_m ,
output ch3_awvalid_m ,
input ch3_awready_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch3_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch3_wstrb_m ,
output ch3_wvalid_m ,
input ch3_wready_m ,
input [1:0] ch3_bresp_m ,
input ch3_bvalid_m ,
output ch3_bready_m ,
output [31:0] ch3_araddr_m ,
output ch3_arvalid_m ,
input ch3_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch3_rdata_m ,
input ch3_rvalid_m ,
input [1:0] ch3_rresp_m ,
output ch3_rready_m ,
//CH4
output [31:0] ch4_awaddr_m ,
output ch4_awvalid_m ,
input ch4_awready_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch4_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch4_wstrb_m ,
output ch4_wvalid_m ,
input ch4_wready_m ,
input [1:0] ch4_bresp_m ,
input ch4_bvalid_m ,
output ch4_bready_m ,
output [31:0] ch4_araddr_m ,
output ch4_arvalid_m ,
input ch4_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch4_rdata_m ,
input ch4_rvalid_m ,
input [1:0] ch4_rresp_m ,
output ch4_rready_m ,
//CH5
output [31:0] ch5_awaddr_m ,
output ch5_awvalid_m ,
input ch5_awready_m ,
output [C_M_AXI_DATA_WIDTH-1:0] ch5_wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] ch5_wstrb_m ,
output ch5_wvalid_m ,
input ch5_wready_m ,
input [1:0] ch5_bresp_m ,
input ch5_bvalid_m ,
output ch5_bready_m ,
output [31:0] ch5_araddr_m ,
output ch5_arvalid_m ,
input ch5_arready_m ,
input [C_M_AXI_DATA_WIDTH-1:0] ch5_rdata_m ,
input ch5_rvalid_m ,
input [1:0] ch5_rresp_m ,
output ch5_rready_m ,
output [9:0] rom_addr_ptr ,
output [9:0] rom_data_ptr ,
input [C_M_AXI_DATA_WIDTH-1:0] rom_data ,
input [C_M_AXI_DATA_WIDTH-1:0] rom_ctrl ,
input [C_M_AXI_DATA_WIDTH-1:0] rom_mask ,
input [127:0] cmd_out_mw ,
output irq_out ,
output reg done ,
output reg [31:0] status
);
//-------Input Decode ---------
wire [31:0] addr_mif_entry;
wire [31:0] data_mif_entry;
wire [31:0] mask_mif_entry;
wire [31:0] ctrl_mif_entry;
assign addr_mif_entry = cmd_out_mw[31:0];
assign data_mif_entry = rom_data[31:0];
generate if(C_ATG_SYSTEM_TEST ==1 ) begin : ATG_SYSTEST_MIF
assign mask_mif_entry = rom_mask[31:0];
assign ctrl_mif_entry = rom_ctrl[31:0];
end
endgenerate
generate if(C_ATG_SYSTEM_INIT ==1 ) begin : ATG_SYSINIT_MIF
assign mask_mif_entry = 32'hFFFFFFFF;
assign ctrl_mif_entry = 32'h00010000;
end
endgenerate
wire cmd_valid;
wire cmd_type_wnr; //r-0,w-1
wire [1:0] rd_cmp_type; // equal=2'b00,Less than = 2'b01,Greater than = 2'b10
wire cnt_as_error;
wire [7:0] fail_mif_index;
wire [7:0] pass_mif_index;
//NOTE::ctrl_mif_entry[19:18] are always reserved Should NOT be used.
assign cmd_valid = cmd_out_mw[63];
assign rd_cmp_type = ctrl_mif_entry[21:20];
assign cnt_as_error = ctrl_mif_entry[17];
assign cmd_type_wnr = ctrl_mif_entry[16];
assign pass_mif_index = ctrl_mif_entry[15:8];
assign fail_mif_index = ctrl_mif_entry[7:0];
//-------Input Decode Done---------
wire block_outputs;
wire cmdr1_valid,cmdw1_valid;
wire cmdr2_valid,cmdw2_valid;
wire cmdr3_valid,cmdw3_valid;
wire cmdr4_valid,cmdw4_valid;
wire cmdr5_valid,cmdw5_valid;
wire ch1_select;
wire ch2_select;
wire ch3_select;
wire ch4_select;
wire ch5_select;
//
//Generate ch*_select signals based on address decoding.
//NOTE:ch*_select generate statements can also be made with <= condition.
// But expilicit decoding based on no.of channels is coded.
generate if(C_ATG_SYSTEM_MAX_CHANNELS ==1 ) begin : ATG_SYSINIT_CHNLS1
assign ch1_select = ((C_ATG_SYSTEM_CH1_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH1_HIGH )) ? 1'b1 : 1'b0;
assign ch2_select = 1'b0;
assign ch3_select = 1'b0;
assign ch4_select = 1'b0;
assign ch5_select = 1'b0;
end
endgenerate
generate if(C_ATG_SYSTEM_MAX_CHANNELS ==2 ) begin : ATG_SYSINIT_CHNLS2
assign ch1_select = ((C_ATG_SYSTEM_CH1_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH1_HIGH )) ? 1'b1 : 1'b0;
assign ch2_select = ((C_ATG_SYSTEM_CH2_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH2_HIGH )) ? 1'b1 : 1'b0;
assign ch3_select = 1'b0;
assign ch4_select = 1'b0;
assign ch5_select = 1'b0;
end
endgenerate
generate if(C_ATG_SYSTEM_MAX_CHANNELS ==3 ) begin : ATG_SYSINIT_CHNLS3
assign ch1_select = ((C_ATG_SYSTEM_CH1_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH1_HIGH )) ? 1'b1 : 1'b0;
assign ch2_select = ((C_ATG_SYSTEM_CH2_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH2_HIGH )) ? 1'b1 : 1'b0;
assign ch3_select = ((C_ATG_SYSTEM_CH3_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH3_HIGH )) ? 1'b1 : 1'b0;
assign ch4_select = 1'b0;
assign ch5_select = 1'b0;
end
endgenerate
generate if(C_ATG_SYSTEM_MAX_CHANNELS ==4 ) begin : ATG_SYSINIT_CHNLS4
assign ch1_select = ((C_ATG_SYSTEM_CH1_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH1_HIGH )) ? 1'b1 : 1'b0;
assign ch2_select = ((C_ATG_SYSTEM_CH2_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH2_HIGH )) ? 1'b1 : 1'b0;
assign ch3_select = ((C_ATG_SYSTEM_CH3_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH3_HIGH )) ? 1'b1 : 1'b0;
assign ch4_select = ((C_ATG_SYSTEM_CH4_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH4_HIGH )) ? 1'b1 : 1'b0;
assign ch5_select = 1'b0;
end
endgenerate
generate if(C_ATG_SYSTEM_MAX_CHANNELS ==5 ) begin : ATG_SYSINIT_CHNLS5
assign ch1_select = ((C_ATG_SYSTEM_CH1_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH1_HIGH )) ? 1'b1 : 1'b0;
assign ch2_select = ((C_ATG_SYSTEM_CH2_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH2_HIGH )) ? 1'b1 : 1'b0;
assign ch3_select = ((C_ATG_SYSTEM_CH3_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH3_HIGH )) ? 1'b1 : 1'b0;
assign ch4_select = ((C_ATG_SYSTEM_CH4_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH4_HIGH )) ? 1'b1 : 1'b0;
assign ch5_select = ((C_ATG_SYSTEM_CH5_LOW <= addr_mif_entry ) &
(addr_mif_entry <= C_ATG_SYSTEM_CH5_HIGH )) ? 1'b1 : 1'b0;
end
endgenerate
assign cmdr1_valid = ch1_select & cmd_valid & ~cmd_type_wnr;
assign cmdw1_valid = ch1_select & cmd_valid & cmd_type_wnr;
assign cmdr2_valid = ch2_select & cmd_valid & ~cmd_type_wnr;
assign cmdw2_valid = ch2_select & cmd_valid & cmd_type_wnr;
assign cmdr3_valid = ch3_select & cmd_valid & ~cmd_type_wnr;
assign cmdw3_valid = ch3_select & cmd_valid & cmd_type_wnr;
assign cmdr4_valid = ch4_select & cmd_valid & ~cmd_type_wnr;
assign cmdw4_valid = ch4_select & cmd_valid & cmd_type_wnr;
assign cmdr5_valid = ch5_select & cmd_valid & ~cmd_type_wnr;
assign cmdw5_valid = ch5_select & cmd_valid & cmd_type_wnr;
wire cmdr_valid;
wire cmdw_valid;
assign cmdr_valid = cmdr1_valid | cmdr2_valid | cmdr3_valid | cmdr4_valid | cmdr5_valid;
assign cmdw_valid = cmdw1_valid | cmdw2_valid | cmdw3_valid | cmdw4_valid | cmdw5_valid;
//Internal protocol signals
reg [31:0] awaddr_m ;
reg awvalid_m ;
wire awready_m ;
reg [31:0] wdata_m ;
wire [3:0] wstrb_m ;
reg wvalid_m ;
wire wready_m ;
wire [1:0] bresp_m ;
wire bvalid_m ;
reg bready_m ;
reg [31:0] araddr_m ;
reg arvalid_m ;
wire arready_m ;
wire [31:0] rdata_m ;
wire rvalid_m ;
wire [1:0] rresp_m ;
reg rready_m ;
//Core operation starts here
wire out_of_reset;
reg rst_l_ff;
reg rst_l_2ff;
reg rst_l_3ff;
always @(posedge Clk) begin
rst_l_ff <= rst_l;
rst_l_2ff <= rst_l_ff;
rst_l_3ff <= rst_l_2ff;
end
assign out_of_reset = (rst_l_2ff == 1'b1) && (rst_l_3ff == 1'b0);
wire r_complete;
assign r_complete = rvalid_m && rready_m;
reg r_complete_ff;
reg r_complete_2ff;
reg r_complete_3ff;
reg b_complete_ff;
reg b_complete_2ff;
reg b_complete_3ff;
always @(posedge Clk) begin
r_complete_ff <= (rst_l) ? r_complete : 1'b0;
r_complete_2ff <= (rst_l) ? r_complete_ff : 1'b0;
r_complete_3ff <= (rst_l) ? r_complete_2ff : 1'b0;
end
wire launch_new_rd;
assign launch_new_rd = ((out_of_reset || r_complete_3ff || b_complete_3ff) & cmdr_valid & ~block_outputs ) ;
//AR
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
arvalid_m <= 1'b0;
end else if(arready_m && arvalid_m) begin
arvalid_m <= 1'b0;
end else if(launch_new_rd ) begin
arvalid_m <= 1'b1;
end else begin
arvalid_m <= arvalid_m;
end
end
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
araddr_m <= 'h0;
end else if(launch_new_rd ) begin
araddr_m <= addr_mif_entry[31:0];
end else begin
araddr_m <= araddr_m;
end
end
//R
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
rready_m <= 1'b0;
end else if(rvalid_m && rready_m) begin
rready_m <= 1'b0;
end else if(launch_new_rd ) begin
rready_m <= 1'b1;
end else begin
rready_m <= rready_m;
end
end
wire b_complete;
assign b_complete = bvalid_m && bready_m;
always @(posedge Clk) begin
b_complete_ff <= (rst_l) ? b_complete : 1'b0;
b_complete_2ff <= (rst_l) ? b_complete_ff : 1'b0;
b_complete_3ff <= (rst_l) ? b_complete_2ff : 1'b0;
end
wire launch_new_wr;
assign launch_new_wr = ((out_of_reset || b_complete_3ff || r_complete_3ff) & cmdw_valid & ~block_outputs);
//AW
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
awvalid_m <= 1'b0;
end else if(awready_m && awvalid_m) begin
awvalid_m <= 1'b0;
end else if(launch_new_wr ) begin
awvalid_m <= 1'b1;
end else begin
awvalid_m <= awvalid_m;
end
end
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
awaddr_m <= 'h0;
end else if(launch_new_wr ) begin
awaddr_m <= addr_mif_entry[31:0];
end else begin
awaddr_m <= awaddr_m;
end
end
//W
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
wvalid_m <= 1'b0;
end else if(wready_m && wvalid_m) begin
wvalid_m <= 1'b0;
end else if(launch_new_wr ) begin
wvalid_m <= 1'b1;
end else begin
wvalid_m <= wvalid_m;
end
end
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
wdata_m <= 'h0;
end else if(launch_new_wr ) begin
wdata_m <= data_mif_entry[31:0];
end else begin
wdata_m <= wdata_m;
end
end
assign wstrb_m = {(C_M_AXI_DATA_WIDTH/8) {1'b1}};
//B
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
bready_m <= 1'b0;
end else if(bvalid_m && bready_m) begin
bready_m <= 1'b0;
end else if(launch_new_wr ) begin
bready_m <= 1'b1;
end else begin
bready_m <= bready_m;
end
end
//current transaction status
reg cur_trn_status;
wire [31:0] expected_data;
wire [31:0] actual_data;
assign expected_data = data_mif_entry&mask_mif_entry;
assign actual_data = rdata_m&mask_mif_entry;
//read compare check
reg rd_check;
always@(*) begin
if(rd_cmp_type == 2'b00 &
actual_data == expected_data) begin
rd_check = 1'b1; //Pass
end else if( rd_cmp_type == 2'b01 &
actual_data < expected_data) begin
rd_check = 1'b1; //Pass
end else if( rd_cmp_type == 2'b10 &
actual_data > expected_data) begin
rd_check = 1'b1; //Pass
end else begin
rd_check = 1'b0; //Fail
end
end
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
cur_trn_status <= 1'b0;
end else if(cmdw_valid & b_complete )begin
cur_trn_status <= |bresp_m;
end else if(cmdr_valid & r_complete )begin
if((rd_check == 1'b1)&(rresp_m == 2'b00)) begin
cur_trn_status <= 1'b0;
end else begin
cur_trn_status <= 1'b1;
end
end else begin
cur_trn_status <= 1'b0;
end
end
//Decide Nxt Index based on the Current Trn Status and update error counters
reg [8:0] nxt_rom_ptr;
reg [31:0] test_err_cntr;
wire cur_trn_done;
assign cur_trn_done = r_complete_ff | b_complete_ff ;
generate if(C_ATG_SYSTEM_TEST == 1 ) begin : ATG_SYSTEST_NXT_PTR
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
nxt_rom_ptr <= 9'h0;
test_err_cntr <= 32'h0;
end else if(cur_trn_done)begin
if(cur_trn_status) begin
nxt_rom_ptr <= fail_mif_index;
test_err_cntr <= (cnt_as_error) ? test_err_cntr + 1'b1: test_err_cntr;
end else begin
nxt_rom_ptr <= pass_mif_index;
test_err_cntr <= test_err_cntr;
end
end
end
end
endgenerate
generate if(C_ATG_SYSTEM_INIT == 1 ) begin : ATG_SYSINIT_NXT_PTR
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
nxt_rom_ptr <= 9'h0;
test_err_cntr <= 32'h0;
end else if(cur_trn_done)begin
nxt_rom_ptr <= nxt_rom_ptr + 1'b1;
test_err_cntr <= test_err_cntr;
end
end
end
endgenerate
//ROM Address Generation
wire get_nxt_rom_entry;
assign get_nxt_rom_entry = b_complete_2ff | r_complete_2ff;
wire[8:0] rom_ptr;
reg[8:0] rom_ptr_ff;
assign rom_ptr = (get_nxt_rom_entry) ? nxt_rom_ptr : rom_ptr_ff;
always @(posedge Clk) begin
rom_ptr_ff <= (rst_l) ? rom_ptr : 10'h0;
end
assign rom_addr_ptr = rom_ptr;
assign rom_data_ptr = rom_ptr;
//Fail-safe Counters.
reg [31:0] max_retry_cntr;
reg [31:0] max_test_time_cntr;
reg [1:0] cur_trn_type;
reg [1:0] new_trn_type;
reg [31:0] cur_trn_addr;
reg [31:0] new_trn_addr;
reg first_tran_done;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
cur_trn_type <= 2'b00;
cur_trn_addr <= 32'h0;
new_trn_type <= 2'b00;
new_trn_addr <= 32'h0;
first_tran_done <= 1'b0;
end else if(awvalid_m & awready_m)begin
if(first_tran_done) begin
new_trn_type <= 2'b01;
new_trn_addr <= awaddr_m;
first_tran_done <= 1'b0;
end else begin
cur_trn_type <= 2'b01;
cur_trn_addr <= awaddr_m;
first_tran_done <= 1'b1;
end
end else if(arvalid_m & arready_m)begin
if(first_tran_done) begin
new_trn_type <= 2'b10;
new_trn_addr <= araddr_m;
first_tran_done <= 1'b0;
end else begin
cur_trn_type <= 2'b10;
cur_trn_addr <= araddr_m;
first_tran_done <= 1'b1;
end
end
end
reg start_retry_check;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
start_retry_check <= 1'b0;
end else if((awvalid_m & awready_m) |(arvalid_m & arready_m))begin
start_retry_check <= 1'b1;
end
end
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
max_retry_cntr <= 32'h0;
end else if(start_retry_check & (r_complete | b_complete)) begin
if((cur_trn_addr == new_trn_addr &
cur_trn_type == new_trn_type)) begin
max_retry_cntr <= max_retry_cntr + 1'b1;
end else begin
max_retry_cntr <= 32'h0;
end
end
end
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
max_test_time_cntr <= 32'h0;
end else if((max_test_time_cntr == C_ATG_SYSTEM_TEST_MAX_CLKS)|(block_outputs == 1'b1)) begin
max_test_time_cntr <= max_test_time_cntr;
end else begin
max_test_time_cntr <= max_test_time_cntr + 1'b1;
end
end
//Report Status
//all channels idle
//arvalid =0
//rready =0
//awvalid =0
//wvalid =0
//bready =0
wire channels_idle;
reg rom_eof;
wire first_entry_avlbl;
assign first_entry_avlbl = rst_l_2ff ;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
rom_eof <= 1'b0;
end else if(first_entry_avlbl == 1'b1) begin
rom_eof <= ~cmdr_valid & ~cmdw_valid;
end
end
assign channels_idle = (arvalid_m == 1'b0) &
( rready_m == 1'b0) &
(awvalid_m == 1'b0) &
( wvalid_m == 1'b0) &
( bready_m == 1'b0) ;
assign irq_out = 1'b0;//Not Used In system testm mode.
wire rom_eof_reached;
wire max_retry_reached;
wire max_test_time_reached;
assign rom_eof_reached = (rom_eof == 1'b1) ;
assign max_retry_reached = (max_retry_cntr == C_ATG_SYSTEM_CMD_MAX_RETRY);
assign max_test_time_reached = (max_test_time_cntr == C_ATG_SYSTEM_TEST_MAX_CLKS);
//
//Stop all:
// Generating transactions.
// Counters(Test time counters)--
//
assign block_outputs = rom_eof_reached | max_retry_reached | max_test_time_reached;
reg done_i;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
done_i <= 1'b0;
end else if(((rom_eof_reached & channels_idle) |
(max_retry_reached & channels_idle) |
max_test_time_reached)
)begin
done_i <= 1'b1;
end
end
//Test error counters will be updated 1 clk after beat sampled.
//So,delay done by 1 clk to account for last beat comparision
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
done <= 1'b0;
end else begin
done <= done_i;
end
end
reg [7:0] cur_rom_ptr;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
cur_rom_ptr <= 8'h00;
end else if(r_complete | b_complete) begin
cur_rom_ptr <= rom_ptr[7:0];
end
end
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
status <= 32'h0;
end else if(done_i)begin
status <= status;
end else if( max_retry_reached | max_test_time_reached)begin
status[1:0] <= 2'b11;
status[9:2] <= nxt_rom_ptr[7:0];
status[15:10] <= 6'h0;
status[31:16] <= test_err_cntr;
end else if (rom_eof_reached) begin
status[1:0] <= (test_err_cntr == 32'h0) ? 2'b01 : 2'b10;
//status[9:2] <= cur_rom_ptr;
status[9:2] <= nxt_rom_ptr[7:0];
status[15:10] <= 6'h0;
status[31:16] <= test_err_cntr;
end
end
//
//Mux based on ch.Selected
//
assign ch1_awaddr_m = awaddr_m;
assign ch1_awvalid_m = ch1_select & awvalid_m;
assign ch1_wvalid_m = ch1_select & wvalid_m;
assign ch1_wdata_m = wdata_m;
assign ch1_wstrb_m = wstrb_m;
assign ch1_bready_m = ch1_select & bready_m;
assign ch2_awaddr_m = awaddr_m;
assign ch2_awvalid_m = ch2_select & awvalid_m;
assign ch2_wvalid_m = ch2_select & wvalid_m;
assign ch2_wdata_m = wdata_m;
assign ch2_wstrb_m = wstrb_m;
assign ch2_bready_m = ch2_select & bready_m;
assign ch3_awaddr_m = awaddr_m;
assign ch3_awvalid_m = ch3_select & awvalid_m;
assign ch3_wvalid_m = ch3_select & wvalid_m;
assign ch3_wdata_m = wdata_m;
assign ch3_wstrb_m = wstrb_m;
assign ch3_bready_m = ch3_select & bready_m;
assign ch4_awaddr_m = awaddr_m;
assign ch4_awvalid_m = ch4_select & awvalid_m;
assign ch4_wvalid_m = ch4_select & wvalid_m;
assign ch4_wdata_m = wdata_m;
assign ch4_wstrb_m = wstrb_m;
assign ch4_bready_m = ch4_select & bready_m;
assign ch5_awaddr_m = awaddr_m;
assign ch5_awvalid_m = ch5_select & awvalid_m;
assign ch5_wvalid_m = ch5_select & wvalid_m;
assign ch5_wdata_m = wdata_m;
assign ch5_wstrb_m = wstrb_m;
assign ch5_bready_m = ch5_select & bready_m;
assign awready_m = ((ch1_select & ch1_awready_m) |
(ch2_select & ch2_awready_m) |
(ch3_select & ch3_awready_m) |
(ch4_select & ch4_awready_m) |
(ch5_select & ch5_awready_m)
);
assign wready_m = ((ch1_select & ch1_wready_m) |
(ch2_select & ch2_wready_m) |
(ch3_select & ch3_wready_m) |
(ch4_select & ch4_wready_m) |
(ch5_select & ch5_wready_m)
);
assign bvalid_m = ((ch1_select & ch1_bvalid_m) |
(ch2_select & ch2_bvalid_m) |
(ch3_select & ch3_bvalid_m) |
(ch4_select & ch4_bvalid_m) |
(ch5_select & ch5_bvalid_m)
);
assign bresp_m = ((ch1_select & ch1_bresp_m) |
(ch2_select & ch2_bresp_m) |
(ch3_select & ch3_bresp_m) |
(ch4_select & ch4_bresp_m) |
(ch5_select & ch5_bresp_m)
);
assign ch1_araddr_m = araddr_m;
assign ch1_arvalid_m = ch1_select & arvalid_m;
assign ch1_rready_m = ch1_select & rready_m;
assign ch2_araddr_m = araddr_m;
assign ch2_arvalid_m = ch2_select & arvalid_m;
assign ch2_rready_m = ch2_select & rready_m;
assign ch3_araddr_m = araddr_m;
assign ch3_arvalid_m = ch3_select & arvalid_m;
assign ch3_rready_m = ch3_select & rready_m;
assign ch4_araddr_m = araddr_m;
assign ch4_arvalid_m = ch4_select & arvalid_m;
assign ch4_rready_m = ch4_select & rready_m;
assign ch5_araddr_m = araddr_m;
assign ch5_arvalid_m = ch5_select & arvalid_m;
assign ch5_rready_m = ch5_select & rready_m;
assign arready_m = (
(ch1_select & ch1_arready_m) |
(ch2_select & ch2_arready_m) |
(ch3_select & ch3_arready_m) |
(ch4_select & ch4_arready_m) |
(ch5_select & ch5_arready_m)
);
assign rdata_m = (
(({32{ch1_select}}) & ch1_rdata_m) |
(({32{ch2_select}}) & ch2_rdata_m) |
(({32{ch3_select}}) & ch3_rdata_m) |
(({32{ch4_select}}) & ch4_rdata_m) |
(({32{ch5_select}}) & ch5_rdata_m)
);
assign rvalid_m = (
(ch1_select & ch1_rvalid_m) |
(ch2_select & ch2_rvalid_m) |
(ch3_select & ch3_rvalid_m) |
(ch4_select & ch4_rvalid_m) |
(ch5_select & ch5_rvalid_m)
);
assign rresp_m = (
(({2{ch1_select}}) & ch1_rresp_m) |
(({2{ch2_select}}) & ch2_rresp_m) |
(({2{ch3_select}}) & ch3_rresp_m) |
(({2{ch4_select}}) & ch4_rresp_m) |
(({2{ch5_select}}) & ch5_rresp_m)
);
endmodule
|
module ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output reg[3:0] CU, input MFC, Reset,Clk, input [31:0] IR,input [3:0] SR);
reg [4:0] State, NextState;
task registerTask;
input [17:0] signals;
//6 7 8 12 14 16
fork
//#2 set the alu signals
#2 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = {signals[17],1'b0,signals[15],1'b0,signals[13],1'b0,signals[11:9],1'b0,1'b0,1'b0,signals[5:0]};
//#4 set the register signals
#4 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
//#6 let data be saved
#6 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
join
endtask
always @ (negedge Clk, posedge Reset)
if (Reset) begin
State <= 5'b00000; end
else
State <= NextState;
always @ (State, MFC)
case (State)
5'b00000 : if(Reset) NextState = 5'b00000; else NextState = 5'b00001;
5'b00001 : NextState = 5'b00010;
5'b00010 : NextState = 5'b00011;
5'b00011 : NextState = 5'b00100;
5'b00100 : NextState = 5'b00101;
5'b00101 : NextState = 5'b00110;
5'b00110 : NextState = 5'b00111;
5'b00111 : NextState = 5'b01000;
5'b01000 : NextState = 5'b01001;
5'b01001 : NextState = 5'b01010;
5'b01010 : NextState = 5'b01011;
5'b01011 : NextState = 5'b01100;
5'b01100 : NextState = 5'b01101;
5'b01101 : NextState = 5'b01110;
5'b01110 : NextState = 5'b01111;
5'b01111 : NextState = 5'b10000;
5'b10000 : NextState = 5'b10001;
5'b10001 : NextState = 5'b00000;
endcase
always @ (State, MFC)
case (State)
5'b00000 : begin opcode = 0; ALUSTORE = 1 ; end
5'b00001 : begin opcode = 1; ALUSTORE = 1 ; end // send pc to mar: ircu = 1 cu = 1111,MARLOAD = 1
5'b00010 : begin opcode = 2; ALUSTORE = 1 ; end // increment pc : loadpc = 1 ircu = 1 cu = 1111 op = 17
5'b00011 : begin opcode = 3; ALUSTORE = 1 ; end // wait for MFC: MFA = 1 LOADIR = 1 read_write = 1 word_byte = 1
5'b00100 : begin opcode = 4; ALUSTORE = 1 ; end // transfer data to IR
5'b00101 : begin opcode = 5; ALUSTORE = 1 ; end // Check status codes
5'b00110 : begin opcode = 6; ALUSTORE = 1 ; end // Decode instruction type and set out signals
5'b00111 : begin opcode = 7; ALUSTORE = 1 ; end
5'b01000 : begin opcode = 8; ALUSTORE = 1 ; end
5'b01001 : begin opcode = 9; ALUSTORE = 1 ; end
5'b01010 : begin opcode = 10; ALUSTORE = 1 ; end
5'b01011 : begin opcode = 11; ALUSTORE = 1 ; end
5'b01100 : begin opcode = 12; ALUSTORE = 1 ; end
5'b01101 : begin opcode = 13; ALUSTORE = 1 ; end
5'b01110 : begin opcode = 14; ALUSTORE = 1 ; end
5'b01111 : begin opcode = 15; ALUSTORE = 1 ; end
5'b10000 : begin opcode = 16; ALUSTORE = 1 ; end
5'b10001 : begin opcode = 17; ALUSTORE = 1 ; end
/*branch and load_store instruction*/
default : begin end
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_4_V
`define SKY130_FD_SC_HS__XOR3_4_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_4_V
|
//-----------------------------------------------------------------------------------------
//-- txchar: Uart_tx example 1
//-- Continuous transmission of a character when the DTR signal is activated
//-- The reset signal is connected to the dtr signal (in file txchar.pcf)
//-- Fot this example to work is necessary to open a serial terminal (gtkterm for example)
//-- and deactivate DTR. A lot of "A" will be received on the terminal
//-- Fixed BAUDRATE: 115200
//-----------------------------------------------------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//-----------------------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-- Top entity
module txchar (
input wire clk, //-- System clock
input wire rstn, //-- Reset (active low)
output wire tx //-- Serial data output
);
//-- Serial Unit instantation
uart_tx #(
.BAUDRATE(`B115200) //-- Set the baudrate
) TX0 (
.clk(clk),
.rstn(rstn),
.data("A"), //-- Fixed character to transmit (always the same)
.start(1'b1), //-- Start signal always set to 1
.tx(tx)
); //-- Port ready not used
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N );
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_V
|
module ZedBoardWrapper(input clk, input reset,
output csr_AWREADY,
input csr_AWVALID,
input [31:0] csr_AWADDR,
input [2:0] csr_AWPROT,
output csr_WREADY,
input csr_WVALID,
input [31:0] csr_WDATA,
input [3:0] csr_WSTRB,
input csr_BREADY,
output csr_BVALID,
output[1:0] csr_BRESP,
output csr_ARREADY,
input csr_ARVALID,
input [31:0] csr_ARADDR,
input [2:0] csr_ARPROT,
input csr_RREADY,
output csr_RVALID,
output[31:0] csr_RDATA,
output[1:0] csr_RRESP,
input mem3_AWREADY,
output mem3_AWVALID,
output[31:0] mem3_AWADDR,
output[2:0] mem3_AWSIZE,
output[7:0] mem3_AWLEN,
output[1:0] mem3_AWBURST,
output[5:0] mem3_AWID,
output mem3_AWLOCK,
output[3:0] mem3_AWCACHE,
output[2:0] mem3_AWPROT,
output[3:0] mem3_AWQOS,
input mem3_WREADY,
output mem3_WVALID,
output[63:0] mem3_WDATA,
output[7:0] mem3_WSTRB,
output mem3_WLAST,
output mem3_BREADY,
input mem3_BVALID,
input [5:0] mem3_BID,
input [1:0] mem3_BRESP,
input mem3_ARREADY,
output mem3_ARVALID,
output[31:0] mem3_ARADDR,
output[2:0] mem3_ARSIZE,
output[7:0] mem3_ARLEN,
output[1:0] mem3_ARBURST,
output[5:0] mem3_ARID,
output mem3_ARLOCK,
output[3:0] mem3_ARCACHE,
output[2:0] mem3_ARPROT,
output[3:0] mem3_ARQOS,
output mem3_RREADY,
input mem3_RVALID,
input [63:0] mem3_RDATA,
input [5:0] mem3_RID,
input mem3_RLAST,
input [1:0] mem3_RRESP,
input mem2_AWREADY,
output mem2_AWVALID,
output[31:0] mem2_AWADDR,
output[2:0] mem2_AWSIZE,
output[7:0] mem2_AWLEN,
output[1:0] mem2_AWBURST,
output[5:0] mem2_AWID,
output mem2_AWLOCK,
output[3:0] mem2_AWCACHE,
output[2:0] mem2_AWPROT,
output[3:0] mem2_AWQOS,
input mem2_WREADY,
output mem2_WVALID,
output[63:0] mem2_WDATA,
output[7:0] mem2_WSTRB,
output mem2_WLAST,
output mem2_BREADY,
input mem2_BVALID,
input [5:0] mem2_BID,
input [1:0] mem2_BRESP,
input mem2_ARREADY,
output mem2_ARVALID,
output[31:0] mem2_ARADDR,
output[2:0] mem2_ARSIZE,
output[7:0] mem2_ARLEN,
output[1:0] mem2_ARBURST,
output[5:0] mem2_ARID,
output mem2_ARLOCK,
output[3:0] mem2_ARCACHE,
output[2:0] mem2_ARPROT,
output[3:0] mem2_ARQOS,
output mem2_RREADY,
input mem2_RVALID,
input [63:0] mem2_RDATA,
input [5:0] mem2_RID,
input mem2_RLAST,
input [1:0] mem2_RRESP,
input mem1_AWREADY,
output mem1_AWVALID,
output[31:0] mem1_AWADDR,
output[2:0] mem1_AWSIZE,
output[7:0] mem1_AWLEN,
output[1:0] mem1_AWBURST,
output[5:0] mem1_AWID,
output mem1_AWLOCK,
output[3:0] mem1_AWCACHE,
output[2:0] mem1_AWPROT,
output[3:0] mem1_AWQOS,
input mem1_WREADY,
output mem1_WVALID,
output[63:0] mem1_WDATA,
output[7:0] mem1_WSTRB,
output mem1_WLAST,
output mem1_BREADY,
input mem1_BVALID,
input [5:0] mem1_BID,
input [1:0] mem1_BRESP,
input mem1_ARREADY,
output mem1_ARVALID,
output[31:0] mem1_ARADDR,
output[2:0] mem1_ARSIZE,
output[7:0] mem1_ARLEN,
output[1:0] mem1_ARBURST,
output[5:0] mem1_ARID,
output mem1_ARLOCK,
output[3:0] mem1_ARCACHE,
output[2:0] mem1_ARPROT,
output[3:0] mem1_ARQOS,
output mem1_RREADY,
input mem1_RVALID,
input [63:0] mem1_RDATA,
input [5:0] mem1_RID,
input mem1_RLAST,
input [1:0] mem1_RRESP,
input mem0_AWREADY,
output mem0_AWVALID,
output[31:0] mem0_AWADDR,
output[2:0] mem0_AWSIZE,
output[7:0] mem0_AWLEN,
output[1:0] mem0_AWBURST,
output[5:0] mem0_AWID,
output mem0_AWLOCK,
output[3:0] mem0_AWCACHE,
output[2:0] mem0_AWPROT,
output[3:0] mem0_AWQOS,
input mem0_WREADY,
output mem0_WVALID,
output[63:0] mem0_WDATA,
output[7:0] mem0_WSTRB,
output mem0_WLAST,
output mem0_BREADY,
input mem0_BVALID,
input [5:0] mem0_BID,
input [1:0] mem0_BRESP,
input mem0_ARREADY,
output mem0_ARVALID,
output[31:0] mem0_ARADDR,
output[2:0] mem0_ARSIZE,
output[7:0] mem0_ARLEN,
output[1:0] mem0_ARBURST,
output[5:0] mem0_ARID,
output mem0_ARLOCK,
output[3:0] mem0_ARCACHE,
output[2:0] mem0_ARPROT,
output[3:0] mem0_ARQOS,
output mem0_RREADY,
input mem0_RVALID,
input [63:0] mem0_RDATA,
input [5:0] mem0_RID,
input mem0_RLAST,
input [1:0] mem0_RRESP
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3_4_V
`define SKY130_FD_SC_HDLL__NAND3_4_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_4 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_HVL__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PS_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD1_1_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD1_1_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv5sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd1_1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkdlyinv5sd1 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd1_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkdlyinv5sd1 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD1_1_V
|
module bsg_rp_clk_gen_fine_delay_tuner
( input i
, input we_i
, input async_reset_neg_i
, input [1:0] sel_i
, output o
, output buf_o
);
wire [1:0] sel_r;
wire [1:0] mux_lo;
wire [3:0] ft;
wire i_inv;
// if wen, capture the select line shortly after a transition
// from 1 to 0 of the input i
// synopsys rp_group (bsg_clk_gen_fdt)
// synopsys rp_fill (0 0 UX)
// synopsys rp_fill (0 0 UX)
// synopsys rp_orient ({N FS} I2_1)
SC7P5T_CKINVX3_SSC14SL I2_1 ( .CLK(ft[1]), .Z() );
// synopsys rp_orient ({N FS} I3_1)
SC7P5T_CKINVX3_SSC14SL I3_1 ( .CLK(ft[2]), .Z() );
// synopsys rp_orient ({N FS} I3_2)
SC7P5T_CKINVX3_SSC14SL I3_2 ( .CLK(ft[2]), .Z() );
// synopsys rp_orient ({N FS} I4_1)
SC7P5T_CKINVX3_SSC14SL I4_1 ( .CLK(ft[3]), .Z() );
// synopsys rp_orient ({N FS} I4_2)
SC7P5T_CKINVX3_SSC14SL I4_2 ( .CLK(ft[3]), .Z() );
// synopsys rp_orient ({N FS} I4_3)
SC7P5T_CKINVX3_SSC14SL I4_3 ( .CLK(ft[3]), .Z() );
// same driver with different caps and thus different transition times
// synopsys rp_fill (1 0 UX)
SC7P5T_CKINVX4_SSC14SL I0 ( .CLK(i) , .Z(i_inv) ); // decouple load of FDT from previous stage; also makes this inverting
SC7P5T_CKINVX2_SSC14SL I1 ( .CLK(i_inv), .Z(ft[0]) );
SC7P5T_CKINVX2_SSC14SL I2 ( .CLK(i_inv), .Z(ft[1]) );
SC7P5T_CKINVX2_SSC14SL I3 ( .CLK(i_inv), .Z(ft[2]) );
SC7P5T_CKINVX2_SSC14SL I4 ( .CLK(i_inv), .Z(ft[3]) );
// flops catch on positive edge of inverted clock
// synopsys rp_fill (2 0 UX)
SC7P5T_MUX2X1_SSC14SL X1 ( .D0(sel_r[0]), .D1(sel_i[0]), .S(we_i), .Z(mux_lo[0]) );
SC7P5T_DFFRQX4_SSC14SL DFFR1 ( .D(mux_lo[0]), .CLK(o), .Q(sel_r[0]), .RESET(async_reset_neg_i) );
SC7P5T_MUXI4X4_SSC14SL M2 ( .D0(ft[3]), .D1(ft[2]), .D2(ft[1]), .D3(ft[0]), .S0(sel_r[0]), .S1(sel_r[1]), .Z(o) );
// capture on positive edge
SC7P5T_DFFRQX4_SSC14SL DFFR2 ( .D(mux_lo[1]), .CLK(o), .Q(sel_r[1]), .RESET(async_reset_neg_i) );
SC7P5T_MUX2X1_SSC14SL MX2 ( .D0(sel_r [1]), .D1(sel_i[1]), .S(we_i), .Z(mux_lo[1]) );
// synopsys rp_fill (3 2 UX)
SC7P5T_CKBUFX8_SSC14SL ICLK ( .CLK(o), .Z(buf_o) );
// synopsys rp_endgroup(bsg_clk_gen_fdt)
endmodule
`BSG_ABSTRACT_MODULE(bsg_rp_clk_gen_fine_delay_tuner)
|
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CRT Fifo
// File : crt_fifo_logic.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module consists of the crt fifo of size 40 wide
// and 32 deep. The data to the fifo is obtained from
// memory on m_t_mem_data[63:0] which is packed to
// m_t_mem_data[31:0] to write into the fifo.
//
// The output of the fifo which is m_att_data[39:0]
// is sent to the attribute module.
// The att_text_out [4:0] from the att_text_blk module
// is also written into the crt-fifo block.
//
// The crtfifo writes and reads are also generated here
// in this module.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module crt_fifo_logic
(
input sync_c_crt_line_end,
input hreset_n,
input mem_clk,
input t_crt_clk,
input c_dclk_en,
input crt_ff_write,
input c_crt_line_end,
input c_crt_ff_read,
input dum_ff_read,
input enrd_font_addr,
input text_mode,
input crt_ff_empty,
input crt_ff_rda,
input crt_ff_rdb,
input gr_ff_wra,
input gr_ff_wrb,
input tx_ff_wra_high,
input tx_ff_wra_low,
input tx_ff_wrb_high,
input tx_ff_wrb_low,
input [4:0] att_text_out,
input extend_font_addr,
input [31:0] m_t_mem_data_in,
output dum_ff_rd_cnt0,
output crt_frd0,
output crt_frd15,
output crt_frd16,
output crt_frd31,
output crt_fwr0,
output crt_fwr15,
output crt_fwr16,
output crt_fwr31,
output crt_fwr0_low,
output crt_fwr15_high,
output crt_fwr15_low,
output crt_fwr16_low,
output crt_fwr31_high,
output crt_fwr31_low,
output [36:0] m_att_data,
output [8:0] ff_asic_out,
output crt_fwr7_low,
output crt_fwr7_high,
output crt_fwr23_low,
output crt_fwr23_high,
output crt_frd1,
output crt_frd17
);
//
// Define Variables
//
reg [4:0] wr_cnt_value;
reg [4:0] rd_cnt_value;
reg [4:0] rd_cnt_value_a;
reg [4:0] dum_frd_value;
reg [4:0] dum_frd_value_a;
reg [8:0] store_asi_mc[31:0];
reg [8:0] store_asi_crt[31:0];
reg [12:0] store_att[31:0];
reg [15:0] store_font[31:0];
wire [39:0] int_m_att_data;
wire [31:0] wr_cnt_index_dec;
wire ff_wra_low;
wire ff_wra_high;
wire ff_wrb_low;
wire ff_wrb_high;
wire [15:0] wra_low;
wire [15:0] wra_high;
wire [31:16] wrb_low;
wire [31:16] wrb_high;
wire [31:0] rd_cnt_index_dec;
wire [31:0] dum_frd_index_dec;
wire [31:0] crt_fifo_wr_low;
wire [31:0] crt_fifo_wr_high;
wire [31:0] crt_fifo_rd;
wire [23:16] ff_data_in;
wire [31:0] ff_rda;
wire dum_index_7;
wire dum_index_15;
wire dum_index_23;
wire dum_index_31;
wire en_dum_fifo;
wire crt_ff_rdab;
wire [8:0] att_asic_data;
wire [12:0] ff_att_in;
wire [15:0] ff_att_out;
wire [15:0] ff_font_out;
wire [5:0] dumff_rd;
wire [31:0] asic_ff_read;
wire crt_ff_strobe;
wire [6:0] nc7_0;
//
// Begining of Generating crt fifo logic
// Expecting an 5-bit counter with write enable.
// When write enable is set to one, a value of 00000 is loaded into
// the register.
//
always @(posedge mem_clk or negedge hreset_n) begin
if (!hreset_n) wr_cnt_value <= 5'b0;
else if (sync_c_crt_line_end) wr_cnt_value <= 5'b0;
else if (crt_ff_write) wr_cnt_value <= wr_cnt_value + 1;
end
assign wr_cnt_index_dec = 1'b1 << wr_cnt_value;
assign ff_wra_low = gr_ff_wra | tx_ff_wra_low;
assign ff_wra_high = gr_ff_wra | tx_ff_wra_high;
assign ff_wrb_low = gr_ff_wrb | tx_ff_wrb_low;
assign ff_wrb_high = gr_ff_wrb | tx_ff_wrb_high;
//
// Decoding the write strobes for crt write fifo
//
assign crt_ff_strobe = crt_ff_write;
assign wra_low[7:0] = wr_cnt_index_dec[7:0] & {8{ff_wra_low & crt_ff_strobe}};
assign wra_low[15:8] = (wr_cnt_index_dec[15:8] | wr_cnt_index_dec[23:16]) & {8{ff_wra_low & crt_ff_strobe}};
assign wrb_low[23:16] = (wr_cnt_index_dec[7:0] | wr_cnt_index_dec[23:16] &{8{~text_mode}}) & {8{ff_wrb_low & crt_ff_strobe}};
assign wrb_low[31:24] = (wr_cnt_index_dec[23:16] & {8{text_mode}} | wr_cnt_index_dec[31:24]) & {8{ff_wrb_low & crt_ff_strobe}};
assign wra_high[7:0] = (wr_cnt_index_dec[15:8] & {8{text_mode}} | wr_cnt_index_dec[7:0]) & {8{ff_wra_high & crt_ff_strobe}};
assign wra_high[15:8] = (wr_cnt_index_dec[31:24] | wr_cnt_index_dec[15:8] &{8{~text_mode}})& {8{ff_wra_high & crt_ff_strobe}};
assign wrb_high[23:16] = (wr_cnt_index_dec[23:16] | wr_cnt_index_dec[15:8]) & {8{ff_wrb_high & crt_ff_strobe}};
assign wrb_high[31:24] = (wr_cnt_index_dec[31:24] & {8{ff_wrb_high & crt_ff_strobe}});
//
// Generation of write strobes for read of crt fifo
//
always @*
begin
if (c_dclk_en & c_crt_line_end) rd_cnt_value_a = 5'b00000;
else if (c_dclk_en & c_crt_ff_read) rd_cnt_value_a = rd_cnt_value + 1;
else rd_cnt_value_a = rd_cnt_value;
end
always @(posedge t_crt_clk or negedge hreset_n)
begin
if (!hreset_n) rd_cnt_value <= 5'b0;
else rd_cnt_value <= rd_cnt_value_a;
end
assign rd_cnt_index_dec = 1'b1 << rd_cnt_value;
assign crt_ff_rdab = crt_ff_rda | crt_ff_rdb;
assign ff_rda[0] = (rd_cnt_index_dec[0] );
assign ff_rda[30:1] = {30{crt_ff_rdab}} & rd_cnt_index_dec[30:1];
assign ff_rda[31] = (rd_cnt_index_dec[31]);
//
// Assigning different names to tap them as outputs.
//
assign crt_frd0 = ff_rda[0] & c_crt_ff_read;
assign crt_frd1 = ff_rda[1];
assign crt_frd16 = ff_rda[16];
assign crt_frd15 = ff_rda[15];
assign crt_frd17 = ff_rda[17];
assign crt_frd31 = ff_rda[31];
assign crt_fwr0 = wra_low[0] & wra_high[0];
assign crt_fwr15 = wra_low[15] & wra_high[15];
assign crt_fwr16 = wrb_low[16] & wrb_high[16];
assign crt_fwr31 = wrb_low[31] & wrb_high[31];
assign crt_fwr0_low = wra_low[0];
assign crt_fwr15_high = wra_high[15];
assign crt_fwr15_low = wra_low[15];
assign crt_fwr16_low = wrb_low[16];
assign crt_fwr31_high = wrb_high[31];
assign crt_fwr31_low = wrb_low[31];
assign crt_fwr7_low = wra_low[7];
assign crt_fwr7_high = wra_high[7];
assign crt_fwr23_low = wrb_low[23];
assign crt_fwr23_high = wrb_high[23];
//
// Generation of font fifo reads
//
always @*
begin
if (sync_c_crt_line_end) dum_frd_value_a = 5'b0;
else if (dum_ff_read) dum_frd_value_a = dum_frd_value + 1;
else dum_frd_value_a = dum_frd_value;
end
always @(posedge mem_clk or negedge hreset_n)
begin
if (!hreset_n) dum_frd_value <= 5'b0;
else dum_frd_value <= dum_frd_value_a;
end
assign en_dum_fifo = (extend_font_addr | dum_ff_read);
assign dum_frd_index_dec = (1'b1 << dum_frd_value);
assign dum_index_7 = dum_frd_index_dec[7];
assign dum_index_15 = dum_frd_index_dec[15];
assign dum_index_23 = dum_frd_index_dec[23];
assign dum_index_31 = dum_frd_index_dec[31];
//
// By adding with extend_font_addr which is active for state 4, state5 and
// state 5x
//
assign dum_ff_rd_cnt0 = ((dum_index_7 | dum_index_15 | dum_index_23 | dum_index_31) & extend_font_addr);
assign crt_fifo_wr_low = {wrb_low[31:16], wra_low[15:0]};
assign crt_fifo_wr_high = {wrb_high[31:16], wra_high[15:0]};
assign crt_fifo_rd = {ff_rda[31:0]};
//
// Instantiating an 9x32 fifo to store ascii data [7:0] and the
// mem_data[11] to be used for font generation.
// This fifo is read by the dum_read storbes generated from the sm_txt_sm.
// The writes to this fifo are the crt_fifo_write_low in text mode and in
// graphic mode normal write.
//
wire [4:0] adr_trans_asi_att = {ff_wrb_low,
(ff_wra_low & (wr_cnt_value[4] | wr_cnt_value[3])) |
(ff_wrb_low & wr_cnt_value[3]) |
(ff_wrb_low & text_mode & wr_cnt_value[4]),
wr_cnt_value[2:0]};
wire we_asi_att = crt_ff_write &
((ff_wra_low & ~(wr_cnt_value[4] & wr_cnt_value[3])) |
(ff_wrb_low & ~(~wr_cnt_value[4] & wr_cnt_value[3])));
// always @(posedge mem_clk) if (we_asi_att)
// store_asi_mc[adr_trans_asi_att] <= {m_t_mem_data_in[11], m_t_mem_data_in[7:0]};
// always @(posedge mem_clk) ff_asic_out <= store_asi_mc[dum_frd_value_a];
ram_9x32_2p u_asi_ram
(
.clock (mem_clk),
.wren (we_asi_att),
.wraddress (adr_trans_asi_att),
.data ({m_t_mem_data_in[11], m_t_mem_data_in[7:0]}),
.rdaddress (dum_frd_value_a),
.q (ff_asic_out)
);
// always @(posedge mem_clk) if (we_asi_att)
// store_asi_crt[adr_trans_asi_att] <= {m_t_mem_data_in[11], m_t_mem_data_in[7:0]};
// always @(posedge t_crt_clk) att_asic_data <= store_asi_crt[rd_cnt_value_a];
ram_32x32_dp u_asi_att_ram
(
.wrclock (mem_clk),
.wren (we_asi_att),
.wraddress (adr_trans_asi_att),
.data ({10'h0, att_text_out[4:0], m_t_mem_data_in[15:8], m_t_mem_data_in[11], m_t_mem_data_in[7:0]}),
.rdclock (t_crt_clk),
.rdaddress (rd_cnt_value_a),
.q ({nc7_0, ff_att_out, att_asic_data})
);
//
// If the font fifo is active then en_dum_fifo = 1 and ff_asic_out is
// the att_asic_data which is used to generate font address and if
// the en_dum_fifo = 0, then we force zero's to the att_asic_data
// which is also read on the m_att_data.
//
// Here in part of text mode when en_dum_fifo is set to one, then
// we force zero's on to the att_asic_data bus. Other wise the data
// from the fifo sent to the m_att_data.
//
//GateC assign att_asic_data = (~en_dum_fifo) ? ff_asic_out[8:0] : 8'b0;
// assign att_asic_data = ff_asic_out[8:0];
//
// Instantiating an 16x32 fifo to store attribute data [15:8],
// att_text_out [4:0] and force 3'b0 for future
// use.
// This fifo is read by the crt_fifo_read[31:0]
// The writes to this fifo are the crt_fifo_write_low in text mode and in
// graphic mode normal write.
//
// always @(posedge mem_clk) if (we_asi_att)
// store_att[adr_trans_asi_att] <= {att_text_out[4:0], m_t_mem_data_in[15:8]};
// always @(posedge t_crt_clk) ff_att_out <= {3'b0, store_att[rd_cnt_value_a]};
//
// Instantiating an 16x32 fifo to store font data [23:16], and [31:24]
// This fifo is read by the crt_fifo_read[31:0].
// The address for the memory is generated by the font address generator.
// The writes to this fifo are the crt_fifo_write_high in text mode and in graphic mode normal write.
//
wire [4:0] adr_trans_font = {ff_wrb_high,
(ff_wra_high & wr_cnt_value[4] & wr_cnt_value[3]) |
(ff_wra_high & ~text_mode & ~wr_cnt_value[4] & wr_cnt_value[3]) |
(ff_wrb_high & wr_cnt_value[4] & wr_cnt_value[3]), wr_cnt_value[2:0]};
wire we_font = crt_ff_write &
((ff_wra_high & ~(wr_cnt_value[4] & ~wr_cnt_value[3])) |
(ff_wrb_high & (wr_cnt_value[4] | wr_cnt_value[3])));
ram_16x32_dp u_font_ram
(
.wrclock (mem_clk),
.wren (we_font),
.wraddress (adr_trans_font),
.data (m_t_mem_data_in[31:16]),
.rdclock (t_crt_clk),
.rdaddress (rd_cnt_value_a),
.q (ff_font_out)
);
//
// m_att_data[39:0] is the concatation of the data coming out of the above
// three crt fifos.
//
assign int_m_att_data[39:0] = {ff_att_out[15:8], ff_font_out[15:0], ff_att_out[7:0], att_asic_data[7:0]};
assign m_att_data[36:0] = {int_m_att_data[36:0]};
endmodule
|
/*
DCPU16 Verilog Implementation
Copyright (C) 2012 Shawn Tan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version. This program is
distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU Lesser General Public
License along with this program. If not, see
<http://www.gnu.org/licenses/>. */
/*
DCPU16 PIPELINE
===============
Consists of the following stages:
- Fetch (FE): fetches instructions from the FBUS.
- Decode (DE): decodes instructions.
- EA A (EA) : calculates EA for A
- EA B (EB) : calculates EA for B
- Load A (LA): loads operand A from ABUS.
- Load B (LB): loads operand B from ABUS.
- Execute (EX): performs the ALU operation.
- Save A (SA): saves operand A to the FBUS.
0| 1| 2| 3| 0| 1| 2| 3| 0| 1| 2| 3
FE|DE|EA|EB|LA|LB|EX|SA
FE|DE|EA|EB|LA|LB|EX|SA
FE|DE|EA|EB|LA|LB|EX|SA
*/
// 775@155
// 692@159
// 685@160
// 603@138
// 573@138
// 508@141
// 502@149
// 712@153
// 679@162
module dcpu16_cpu (/*AUTOARG*/
// Outputs
g_wre, g_stb, g_dto, g_adr, f_wre, f_stb, f_dto, f_adr,
// Inputs
rst, g_dti, g_ack, f_dti, f_ack, clk
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [15:0] f_adr; // From m0 of dcpu16_mbus.v
output [15:0] f_dto; // From x0 of dcpu16_alu.v
output f_stb; // From m0 of dcpu16_mbus.v
output f_wre; // From m0 of dcpu16_mbus.v
output [15:0] g_adr; // From m0 of dcpu16_mbus.v
output [15:0] g_dto; // From x0 of dcpu16_alu.v
output g_stb; // From m0 of dcpu16_mbus.v
output g_wre; // From m0 of dcpu16_mbus.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To c0 of dcpu16_ctl.v, ...
input f_ack; // To c0 of dcpu16_ctl.v, ...
input [15:0] f_dti; // To c0 of dcpu16_ctl.v, ...
input g_ack; // To m0 of dcpu16_mbus.v
input [15:0] g_dti; // To m0 of dcpu16_mbus.v
input rst; // To c0 of dcpu16_ctl.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire CC; // From x0 of dcpu16_alu.v
wire bra; // From c0 of dcpu16_ctl.v
wire ena; // From m0 of dcpu16_mbus.v
wire [15:0] ireg; // From c0 of dcpu16_ctl.v
wire [3:0] opc; // From c0 of dcpu16_ctl.v
wire [1:0] pha; // From c0 of dcpu16_ctl.v
wire [15:0] regA; // From m0 of dcpu16_mbus.v
wire [15:0] regB; // From m0 of dcpu16_mbus.v
wire [15:0] regO; // From x0 of dcpu16_alu.v
wire [15:0] regR; // From x0 of dcpu16_alu.v
wire [2:0] rra; // From c0 of dcpu16_ctl.v
wire [15:0] rrd; // From r0 of dcpu16_regs.v
wire [2:0] rwa; // From c0 of dcpu16_ctl.v
wire [15:0] rwd; // From x0 of dcpu16_alu.v
wire rwe; // From c0 of dcpu16_ctl.v
wire wpc; // From m0 of dcpu16_mbus.v
// End of automatics
/*AUTOREG*/
dcpu16_ctl
c0 (/*AUTOINST*/
// Outputs
.ireg (ireg[15:0]),
.pha (pha[1:0]),
.opc (opc[3:0]),
.rra (rra[2:0]),
.rwa (rwa[2:0]),
.rwe (rwe),
.bra (bra),
// Inputs
.CC (CC),
.wpc (wpc),
.f_dti (f_dti[15:0]),
.f_ack (f_ack),
.clk (clk),
.ena (ena),
.rst (rst));
dcpu16_mbus
m0 (/*AUTOINST*/
// Outputs
.g_adr (g_adr[15:0]),
.g_stb (g_stb),
.g_wre (g_wre),
.f_adr (f_adr[15:0]),
.f_stb (f_stb),
.f_wre (f_wre),
.ena (ena),
.wpc (wpc),
.regA (regA[15:0]),
.regB (regB[15:0]),
// Inputs
.g_dti (g_dti[15:0]),
.g_ack (g_ack),
.f_dti (f_dti[15:0]),
.f_ack (f_ack),
.bra (bra),
.CC (CC),
.regR (regR[15:0]),
.rrd (rrd[15:0]),
.ireg (ireg[15:0]),
.regO (regO[15:0]),
.pha (pha[1:0]),
.clk (clk),
.rst (rst));
dcpu16_alu
x0 (/*AUTOINST*/
// Outputs
.f_dto (f_dto[15:0]),
.g_dto (g_dto[15:0]),
.rwd (rwd[15:0]),
.regR (regR[15:0]),
.regO (regO[15:0]),
.CC (CC),
// Inputs
.regA (regA[15:0]),
.regB (regB[15:0]),
.opc (opc[3:0]),
.clk (clk),
.rst (rst),
.ena (ena),
.pha (pha[1:0]));
dcpu16_regs
r0 (/*AUTOINST*/
// Outputs
.rrd (rrd[15:0]),
// Inputs
.rwd (rwd[15:0]),
.rra (rra[2:0]),
.rwa (rwa[2:0]),
.rwe (rwe),
.rst (rst),
.ena (ena),
.clk (clk));
endmodule // dcpu16
|
module opicorv32_memif_wrap (
mem_do_wdata,
mem_do_rdata,
mem_do_prefetch,
mem_wordsize,
mem_rdata,
mem_do_rinst,
mem_ready,
next_pc,
reg_op2,
reg_op1,
resetn,
clk,
mem_done,
mem_valid,
mem_instr,
mem_addr,
mem_wdata,
mem_wstrb,
mem_rdata_latched,
mem_rdata_q,
mem_rdata_word,
mem_la_read,
mem_la_write,
mem_la_addr,
mem_la_wdata,
mem_la_wstrb
);
input mem_do_wdata;
input mem_do_rdata;
input mem_do_prefetch;
input [1:0] mem_wordsize;
input [31:0] mem_rdata;
input mem_do_rinst;
input mem_ready;
input [31:0] next_pc;
input [31:0] reg_op2;
input [31:0] reg_op1;
input resetn;
input clk;
output mem_done;
output mem_valid;
output mem_instr;
output [31:0] mem_addr;
output [31:0] mem_wdata;
output [3:0] mem_wstrb;
output [31:0] mem_rdata_latched;
output [31:0] mem_rdata_q;
output [31:0] mem_rdata_word;
output mem_la_read;
output mem_la_write;
output [31:0] mem_la_addr;
output [31:0] mem_la_wdata;
output [3:0] mem_la_wstrb;
/* signal declarations */
wire [3:0] _1515;
wire [3:0] _1501;
wire [3:0] compare_mem_la_wstrb;
wire [3:0] _1517;
wire [31:0] _1518;
wire [31:0] _1502;
wire [31:0] compare_mem_la_wdata;
wire [31:0] _1520;
wire [31:0] _1521;
wire [31:0] _1503;
wire [31:0] compare_mem_la_addr;
wire [31:0] _1523;
wire _1524;
wire _1504;
wire compare_mem_la_write;
wire _1526;
wire _1527;
wire _1505;
wire compare_mem_la_read;
wire _1529;
wire [31:0] _1530;
wire [31:0] _1506;
wire [31:0] compare_mem_rdata_word;
wire [31:0] _1532;
wire [31:0] _1533;
wire [31:0] _1507;
wire [31:0] compare_mem_rdata_q;
wire [31:0] _1535;
wire [31:0] _1536;
wire [31:0] _1508;
wire [31:0] compare_mem_rdata_latched;
wire [31:0] _1538;
wire [3:0] _1539;
wire [3:0] _1509;
wire [3:0] compare_mem_wstrb;
wire [3:0] _1541;
wire [31:0] _1542;
wire [31:0] _1510;
wire [31:0] compare_mem_wdata;
wire [31:0] _1544;
wire [31:0] _1545;
wire [31:0] _1511;
wire [31:0] compare_mem_addr;
wire [31:0] _1547;
wire _1548;
wire _1512;
wire compare_mem_instr;
wire _1550;
wire _1551;
wire _1513;
wire compare_mem_valid;
wire _1553;
wire [236:0] _1498;
wire _1554;
wire [236:0] _1500;
wire _1514;
wire compare_mem_done;
wire _1556;
/* logic */
assign _1515 = _1498[236:233];
assign _1501 = _1500[236:233];
assign compare_mem_la_wstrb = _1501 ^ _1515;
assign _1517 = compare_mem_la_wstrb ^ _1515;
assign _1518 = _1498[232:201];
assign _1502 = _1500[232:201];
assign compare_mem_la_wdata = _1502 ^ _1518;
assign _1520 = compare_mem_la_wdata ^ _1518;
assign _1521 = _1498[200:169];
assign _1503 = _1500[200:169];
assign compare_mem_la_addr = _1503 ^ _1521;
assign _1523 = compare_mem_la_addr ^ _1521;
assign _1524 = _1498[168:168];
assign _1504 = _1500[168:168];
assign compare_mem_la_write = _1504 ^ _1524;
assign _1526 = compare_mem_la_write ^ _1524;
assign _1527 = _1498[167:167];
assign _1505 = _1500[167:167];
assign compare_mem_la_read = _1505 ^ _1527;
assign _1529 = compare_mem_la_read ^ _1527;
assign _1530 = _1498[166:135];
assign _1506 = _1500[166:135];
assign compare_mem_rdata_word = _1506 ^ _1530;
assign _1532 = compare_mem_rdata_word ^ _1530;
assign _1533 = _1498[134:103];
assign _1507 = _1500[134:103];
assign compare_mem_rdata_q = _1507 ^ _1533;
assign _1535 = compare_mem_rdata_q ^ _1533;
assign _1536 = _1498[102:71];
assign _1508 = _1500[102:71];
assign compare_mem_rdata_latched = _1508 ^ _1536;
assign _1538 = compare_mem_rdata_latched ^ _1536;
assign _1539 = _1498[70:67];
assign _1509 = _1500[70:67];
assign compare_mem_wstrb = _1509 ^ _1539;
assign _1541 = compare_mem_wstrb ^ _1539;
assign _1542 = _1498[66:35];
assign _1510 = _1500[66:35];
assign compare_mem_wdata = _1510 ^ _1542;
assign _1544 = compare_mem_wdata ^ _1542;
assign _1545 = _1498[34:3];
assign _1511 = _1500[34:3];
assign compare_mem_addr = _1511 ^ _1545;
assign _1547 = compare_mem_addr ^ _1545;
assign _1548 = _1498[2:2];
assign _1512 = _1500[2:2];
assign compare_mem_instr = _1512 ^ _1548;
assign _1550 = compare_mem_instr ^ _1548;
assign _1551 = _1498[1:1];
assign _1513 = _1500[1:1];
assign compare_mem_valid = _1513 ^ _1551;
assign _1553 = compare_mem_valid ^ _1551;
picorv32_memif
the_picorv32_memif
( .clk(clk), .resetn(resetn), .reg_op1(reg_op1), .reg_op2(reg_op2), .next_pc(next_pc), .mem_ready(mem_ready), .mem_do_rinst(mem_do_rinst), .mem_rdata(mem_rdata), .mem_wordsize(mem_wordsize), .mem_do_prefetch(mem_do_prefetch), .mem_do_rdata(mem_do_rdata), .mem_do_wdata(mem_do_wdata), .mem_la_wstrb(_1498[236:233]), .mem_la_wdata(_1498[232:201]), .mem_la_addr(_1498[200:169]), .mem_la_write(_1498[168:168]), .mem_la_read(_1498[167:167]), .mem_rdata_word(_1498[166:135]), .mem_rdata_q(_1498[134:103]), .mem_rdata_latched(_1498[102:71]), .mem_wstrb(_1498[70:67]), .mem_wdata(_1498[66:35]), .mem_addr(_1498[34:3]), .mem_instr(_1498[2:2]), .mem_valid(_1498[1:1]), .mem_done(_1498[0:0]) );
assign _1554 = _1498[0:0];
opicorv32_memif
the_opicorv32_memif
( .clk(clk), .resetn(resetn), .reg_op1(reg_op1), .reg_op2(reg_op2), .next_pc(next_pc), .mem_ready(mem_ready), .mem_do_rinst(mem_do_rinst), .mem_rdata(mem_rdata), .mem_wordsize(mem_wordsize), .mem_do_prefetch(mem_do_prefetch), .mem_do_rdata(mem_do_rdata), .mem_do_wdata(mem_do_wdata), .mem_la_wstrb(_1500[236:233]), .mem_la_wdata(_1500[232:201]), .mem_la_addr(_1500[200:169]), .mem_la_write(_1500[168:168]), .mem_la_read(_1500[167:167]), .mem_rdata_word(_1500[166:135]), .mem_rdata_q(_1500[134:103]), .mem_rdata_latched(_1500[102:71]), .mem_wstrb(_1500[70:67]), .mem_wdata(_1500[66:35]), .mem_addr(_1500[34:3]), .mem_instr(_1500[2:2]), .mem_valid(_1500[1:1]), .mem_done(_1500[0:0]) );
assign _1514 = _1500[0:0];
assign compare_mem_done = _1514 ^ _1554;
assign _1556 = compare_mem_done ^ _1554;
/* aliases */
/* output assignments */
assign mem_done = _1556;
assign mem_valid = _1553;
assign mem_instr = _1550;
assign mem_addr = _1547;
assign mem_wdata = _1544;
assign mem_wstrb = _1541;
assign mem_rdata_latched = _1538;
assign mem_rdata_q = _1535;
assign mem_rdata_word = _1532;
assign mem_la_read = _1529;
assign mem_la_write = _1526;
assign mem_la_addr = _1523;
assign mem_la_wdata = _1520;
assign mem_la_wstrb = _1517;
endmodule
|
`include "Nlut/alut.sim.v"
`include "Nlut/blut.sim.v"
`include "Nlut/clut.sim.v"
`include "Nlut/dlut.sim.v"
`include "muxes/f7amux/f7amux.sim.v"
`include "muxes/f7bmux/f7bmux.sim.v"
`include "muxes/f8mux/f8mux.sim.v"
`include "routing/affmux/affmux.sim.v"
`include "routing/bffmux/bffmux.sim.v"
`include "routing/cffmux/cffmux.sim.v"
`include "routing/dffmux/dffmux.sim.v"
`include "routing/aoutmux/aoutmux.sim.v"
`include "routing/boutmux/boutmux.sim.v"
`include "routing/coutmux/coutmux.sim.v"
`include "routing/doutmux/doutmux.sim.v"
`include "routing/precyinit_mux/precyinit_mux.sim.v"
`include "routing/coutused/coutused.sim.v"
`include "routing/srusedmux/srusedmux.sim.v"
`include "routing/ceusedmux/ceusedmux.sim.v"
`include "routing/N5ffmux/a5ffmux.sim.v"
`include "routing/N5ffmux/b5ffmux.sim.v"
`include "routing/N5ffmux/c5ffmux.sim.v"
`include "routing/N5ffmux/d5ffmux.sim.v"
`include "routing/Ncy0/acy0.sim.v"
`include "routing/Ncy0/bcy0.sim.v"
`include "routing/Ncy0/ccy0.sim.v"
`include "routing/Ncy0/dcy0.sim.v"
`include "routing/Nused/aused.sim.v"
`include "routing/Nused/bused.sim.v"
`include "routing/Nused/cused.sim.v"
`include "routing/Nused/dused.sim.v"
`include "carry/carry4_vpr.sim.v"
`include "routing/clkinv/clkinv.sim.v"
// Broken
module COMMON_SLICE(
DX, D1, D2, D3, D4, D5, D6, DMUX, D, DQ, // D port
CX, C1, C2, C3, C4, C5, C6, CMUX, C, CQ, // C port
BX, B1, B2, B3, B4, B5, B6, BMUX, B, BQ, // B port
AX, A1, A2, A3, A4, A5, A6, AMUX, A, AQ, // A port
SR, CE, CLK, // Flip flop signals
CIN, CYINIT, COUT, // Carry to/from adjacent slices
);
// D port
input wire DX;
input wire D1;
input wire D2;
input wire D3;
input wire D4;
input wire D5;
input wire D6;
output wire DMUX;
output wire D;
output wire DQ;
// D port flip-flop config
parameter D5FF_SRVAL = "SRLOW";
parameter D5FF_INIT = D5FF_SRVAL;
parameter DFF_SRVAL = "SRLOW";
parameter DFF_INIT = D5FF_SRVAL;
// C port
input wire CX;
input wire C1;
input wire C2;
input wire C3;
input wire C4;
input wire C5;
input wire C6;
output wire CMUX;
output wire C;
output wire CQ;
// B port
input wire BX;
input wire B1;
input wire B2;
input wire B3;
input wire B4;
input wire B5;
input wire B6;
output wire BMUX;
output wire B;
output wire BQ;
// A port
input wire AX;
input wire A1;
input wire A2;
input wire A3;
input wire A4;
input wire A5;
input wire A6;
output wire AMUX;
output wire A;
output wire AQ;
// Shared Flip flop signals
input wire CLK; // Clock
input wire SR; // Set/Reset
input wire CE; // Clock enable
// Reset type for all flip flops, can be;
// * None -- Ignore SR
// * Sync -- Reset occurs on clock edge
// * Async -- Reset occurs when ever
parameter SR_TYPE = "SYNC";
// The mode this unit operates in, can be;
// "FLIPFLOP" - Operate as a flip-flop (D->Q on clock low->high)
// "LATCH" - Operate as a latch (D->Q while CLK low)
parameter FF_MODE = "FLIPFLOP";
// Carry to/from adjacent slices
input wire CIN;
input wire CYINIT;
output wire COUT;
// Internal routing configuration
wire A5LUT_O5;
wire B5LUT_O5;
wire C5LUT_O5;
wire D5LUT_O5;
wire D6LUT_O6;
wire C6LUT_O6;
wire B6LUT_O6;
wire A6LUT_O6;
ALUT alut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .O6(A6LUT_O6), .O5(A5LUT_O5));
BLUT blut (.A1(B1), .A2(B2), .A3(B3), .A4(B4), .A5(B5), .A6(B6), .O6(B6LUT_O6), .O5(B5LUT_O5));
CLUT clut (.A1(C1), .A2(C2), .A3(C3), .A4(C4), .A5(C5), .A6(C6), .O6(C6LUT_O6), .O5(C5LUT_O5));
DLUT dlut (.A1(D1), .A2(D2), .A3(D3), .A4(D4), .A5(D5), .A6(D6), .O6(D6LUT_O6), .O5(D5LUT_O5));
wire F7AMUX_OUT;
wire F8MUX_OUT;
wire A5FFMUX_OUT;
wire B5FFMUX_OUT;
wire C5FFMUX_OUT;
wire D5FFMUX_OUT;
A5FFMUX a5ffmux (.IN_B(AX), .IN_A(A5LUT_O5), .O(A5FFMUX_OUT));
B5FFMUX b5ffmux (.IN_B(BX), .IN_A(B5LUT_O5), .O(B5FFMUX_OUT));
C5FFMUX c5ffmux (.IN_B(CX), .IN_A(C5LUT_O5), .O(C5FFMUX_OUT));
D5FFMUX d5ffmux (.IN_B(DX), .IN_A(D5LUT_O5), .O(D5FFMUX_OUT));
wire ACY0_OUT;
wire BCY0_OUT;
wire CCY0_OUT;
wire DCY0_OUT;
ACY0 acy0 (.O5(A5LUT_O5), .AX(AX), .O(ACY0_OUT));
BCY0 bcy0 (.O5(B5LUT_O5), .BX(BX), .O(BCY0_OUT));
CCY0 ccy0 (.O5(C5LUT_O5), .CX(CX), .O(CCY0_OUT));
DCY0 dcy0 (.O5(D5LUT_O5), .DX(DX), .O(DCY0_OUT));
wire F7BMUX_OUT;
F7BMUX f7bmux (.I0(D6LUT_O6), .I1(C6LUT_O6), .OUT(F7BMUX_OUT), .S0(CX));
wire F7AMUX_OUT;
F7BMUX f7amux (.I0(B6LUT_O6), .I1(A6LUT_O6), .OUT(F7AMUX_OUT), .S0(AX));
wire F8MUX_OUT;
F8MUX f8mux (.I0(F7BMUX_OUT), .I1(F7AMUX_OUT), .OUT(F8MUX_OUT), .S0(BX));
wire PRECYINIT_OUT;
PRECYINIT_MUX precyinit_mux (.C0(0), .C1(1), .CI(CIN), .CYINIT(CYINIT), .OUT(PRECYINIT_OUT));
wire [3:0] CARRY4_CO;
wire [3:0] CARRY4_O;
CARRY4_MODES carry4 (
.CO(CARRY4_CO),
.O(CARRY4_O),
.DI({ACY0_OUT, BCY0_OUT, CCY0_OUT, DCY0_OUT}),
.S({A6LUT_O6, B6LUT_O6, C6LUT_O6, D6LUT_O6}),
.CIN(PRECYINIT_OUT));
COUTUSED coutused (.IN(CARRY4_O[3]), .OUT(COUT));
wire A5FF_Q;
wire B5FF_Q;
wire C5FF_Q;
wire D5FF_Q;
AOUTMUX aoutmux (
.A5Q(A5FF_Q), .XOR(CARRY4_O[0]), .O6(A6LUT_O6), .O5(A5LUT_O5), .CY(CARRY4_CO[0]), .F7(F7AMUX_OUT),
.OUT(AMUX));
BOUTMUX boutmux (
.B5Q(B5FF_Q), .XOR(CARRY4_O[1]), .O6(B6LUT_O6), .O5(B5LUT_O5), .CY(CARRY4_CO[1]), .F8(F8MUX_OUT),
.OUT(BMUX));
COUTMUX coutmux (
.C5Q(C5FF_Q), .XOR(CARRY4_O[2]), .O6(C6LUT_O6), .O5(C5LUT_O5), .CY(CARRY4_CO[2]), .F7(F7BMUX_OUT),
.OUT(CMUX));
DOUTMUX doutmux (
.D5Q(D5FF_Q), .XOR(CARRY4_O[3]), .O6(D6LUT_O6), .O5(D5LUT_O5), .CY(CARRY4_CO[3]),
.OUT(DMUX));
wire AFFMUX_OUT;
wire BFFMUX_OUT;
wire CFFMUX_OUT;
wire DFFMUX_OUT;
AFFMUX affmux (
.AX(AX), .XOR(CARRY4_O[0]), .O6(A6LUT_O6), .O5(A5LUT_O5), .CY(CARRY4_CO[0]), .F7(F7AMUX_OUT),
.OUT(AFFMUX_OUT));
BFFMUX bffmux (
.BX(BX), .XOR(CARRY4_O[1]), .O6(B6LUT_O6), .O5(B5LUT_O5), .CY(CARRY4_CO[1]), .F8(F8MUX_OUT),
.OUT(BFFMUX_OUT));
CFFMUX cffmux (
.CX(CX), .XOR(CARRY4_O[2]), .O6(C6LUT_O6), .O5(C5LUT_O5), .CY(CARRY4_CO[2]), .F7(F7BMUX_OUT),
.OUT(CFFMUX_OUT));
DFFMUX dffmux (
.DX(DX), .XOR(CARRY4_O[3]), .O6(D6LUT_O6), .O5(D5LUT_O5), .CY(CARRY4_CO[3]),
.OUT(DFFMUX_OUT));
wire CEUSEDMUX_OUT;
wire SRUSEDMUX_OUT;
wire CLKINV_OUT;
CLKINV clkinv (.CLK(CLK), .OUT(CLKINV_OUT));
A5FF a5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(A5FFMUX_OUT), .Q(A5FF_Q));
B5FF b5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(B5FFMUX_OUT), .Q(B5FF_Q));
C5FF c5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(C5FFMUX_OUT), .Q(C5FF_Q));
D5FF d5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(D5FFMUX_OUT), .Q(D5FF_Q));
A5FF aff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(AFFMUX_OUT), .Q(AQ));
B5FF bff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(BFFMUX_OUT), .Q(BQ));
C5FF cff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(CFFMUX_OUT), .Q(CQ));
D5FF dff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(DFFMUX_OUT), .Q(DQ));
AUSED aused (.I0(A6LUT_O6), .O(A));
BUSED bused (.I0(B6LUT_O6), .O(B));
CUSED cused (.I0(C6LUT_O6), .O(C));
DUSED dused (.I0(D6LUT_O6), .O(D));
CEUSEDMUX ceusedmux (.IN(CE), .OUT(CEUSEDMUX_OUT));
SRUSEDMUX srusedmux (.IN(SR), .OUT(SRUSEDMUX_OUT));
endmodule
|
// nios_system_nios2_qsys_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2016.05.03.15:20:15
`timescale 1 ps / 1 ps
module nios_system_nios2_qsys_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [18:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [18:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_system_nios2_qsys_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
// psi2c.v
module psi2c
(
// avalon clock interface
input csi_clock_clk,
input csi_clock_reset,
// avalon mm slave
input [2:0]avs_ctrl_address,
input avs_ctrl_read,
output [31:0]avs_ctrl_readdata,
input avs_ctrl_write,
input [31:0]avs_ctrl_writedata,
// conduit
input sync,
input phase,
output send,
output sda,
input rda
);
wire go;
wire empty;
wire [11:0] dout;
wire [11:0] din;
wire full;
wire [31:0]rda_data;
wire wr;
wire rd;
wire tbm;
psi2c_bitsend bitsend(
.clk(csi_clock_clk),
.reset(csi_clock_reset),
.sync(sync),
.go(go),
.empty(empty),
.phase(phase),
.d(dout),
.rd(rd),
.busy(send),
.sda(sda)
);
psi2c_readback readback
(
.go(tbm & go),
.clk(csi_clock_clk),
.reset(csi_clock_reset),
.sync(sync),
.sync2(phase),
.rda(rda),
.i2c_send(send),
.d(rda_data)
);
i2c_control control
(
.clk(csi_clock_clk),
.reset(csi_clock_reset),
.busy(send),
.write(avs_ctrl_write),
.read(avs_ctrl_read),
.full(full),
.address(avs_ctrl_address),
.rda(rda_data),
.writedata(avs_ctrl_writedata),
.memw(wr),
.go(go),
.tbm(tbm),
.memd(din),
.readdata(avs_ctrl_readdata)
);
psi2c_fifo fifo
(
.clock (csi_clock_clk),
.aclr (csi_clock_reset),
.data (din),
.rdreq (rd),
.wrreq (wr),
.empty (empty),
.full (full),
.q (dout)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:53:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_stub.v
// Design : system_clk_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_0_0(clk_out1, resetn, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,resetn,locked,clk_in1" */;
output clk_out1;
input resetn;
output locked;
input clk_in1;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TX Engine takes unformatted request and completions,
// formats these packets into AXI packets for the Xilinx Core. These packets
// must meet max-request, max-payload, and payload termination requirements (see
// Read Completion Boundary). The TX Engine does not check these requirements
// during operation, but may do so during simulation.
//
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "ultrascale.vh"
module tx_engine_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
output TXC_SENT,
// Interface: RQ
input S_AXIS_RQ_TREADY,
output S_AXIS_RQ_TVALID,
output S_AXIS_RQ_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
output TXR_SENT
);
`include "functions.vh"
localparam C_DEPTH_PACKETS = 10;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
reg rTxcSent;
reg rTxrSent;
assign TXC_SENT = rTxcSent;
assign TXR_SENT = rTxrSent;
always @(posedge CLK) begin
rTxcSent <= S_AXIS_CC_TLAST & S_AXIS_CC_TVALID & S_AXIS_CC_TREADY;
rTxrSent <= S_AXIS_RQ_TLAST & S_AXIS_RQ_TVALID & S_AXIS_RQ_TREADY;
end
txr_engine_ultrascale
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txr_engine_inst
(/*AUTOINST*/
// Outputs
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
txc_engine_ultrascale
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txc_engine_inst
(/*AUTOINST*/
// Outputs
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
.TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_2_V
`define SKY130_FD_SC_HD__O2BB2AI_2_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 09:37:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_1_0/system_inverter_1_0_stub.v
// Design : system_inverter_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "inverter,Vivado 2016.4" *)
module system_inverter_1_0(x, x_not)
/* synthesis syn_black_box black_box_pad_pin="x,x_not" */;
input x;
output x_not;
endmodule
|
`include "seeed_tft_defines.v"
module seeed_tft_data_writer#(
parameter BUFFER_SIZE = 12
)(
input rst,
input clk,
output [31:0] debug,
input i_soft_tearing,
input [7:0] i_tearing_reg,
input i_tearing_polarity,
input [31:0] i_tearing_value,
input [31:0] i_tearing_count,
input [7:0] i_mem_write_cmd,
//Control
input i_enable,
input [31:0] i_num_pixels,
input i_enable_tearing,
//FIFO Signals
output [1:0] o_fifo_rdy,
input [1:0] i_fifo_act,
input i_fifo_stb,
output [23:0] o_fifo_size,
input [31:0] i_fifo_data,
//Physical Signals
input i_tearing_effect,
output o_chip_select,
output o_cmd_mode,
output [7:0] o_data_out,
input [7:0] i_data_in,
output o_write,
output o_read,
output o_data_out_en
);
//Local Parameters
localparam IDLE = 4'h0;
localparam WRITE_ADDRESS = 4'h1;
localparam WRITE_RED_START = 4'h2;
localparam WRITE_RED = 4'h3;
localparam WRITE_GREEN_START = 4'h4;
localparam WRITE_GREEN = 4'h5;
localparam WRITE_BLUE_START = 4'h6;
localparam WRITE_BLUE = 4'h7;
localparam TEARING_WRITE_DELAY = 4'h1;
localparam GET_TEARING = 4'h2;
localparam READ_TEAR_STATUS = 4'h3;
localparam TEARING_FINISHED = 4'h4;
//Registers/Wires
reg [3:0] state;
wire [7:0] w_red;
wire [7:0] w_green;
wire [7:0] w_blue;
reg r_read_stb;
wire w_read_rdy;
reg r_read_act;
wire [23:0] w_read_size;
wire [31:0] w_read_data;
wire w_hard_tear_ready;
reg [23:0] r_read_count;
reg [31:0] r_pixel_count;
reg [2:0] r_delay_count;
wire w_delayed;
//Tear Mode select
reg [3:0] tstate;
reg r_tmode;
reg r_write;
reg r_read;
reg r_chip_select;
reg r_cmd_mode;
reg r_data_out_en;
reg [7:0] r_data_out;
reg r_twrite;
reg r_tdata_out_en;
reg r_tread;
reg r_tchip_select;
reg r_tcmd_mode;
reg [1:0] r_tdata_count;
reg [7:0] r_tdata_out;
reg [31:0] r_tdata;
reg r_finished_image;
reg [2:0] r_tdelay_count;
wire w_tdelayed;
//Tear control
//Submodules
//generate a Ping Pong FIFO to cross the clock domain
ppfifo #(
.DATA_WIDTH (32 ),
`ifndef SIMULATION
.ADDRESS_WIDTH (BUFFER_SIZE )
`else
.ADDRESS_WIDTH (2 )
`endif
)ping_pong (
.reset (rst ),
//write
.write_clock (clk ),
.write_ready (o_fifo_rdy ),
.write_activate (i_fifo_act ),
.write_fifo_size (o_fifo_size ),
.write_strobe (i_fifo_stb ),
.write_data (i_fifo_data ),
//.starved (starved ),
//read
.read_clock (clk ),
.read_strobe (r_read_stb ),
.read_ready (w_read_rdy ),
.read_activate (r_read_act ),
.read_count (w_read_size ),
.read_data (w_read_data )
);
//Asynchronous Logic
//assign w_red = w_read_data[23:16];
//assign w_green = w_read_data[15:8];
//assign w_blue = w_read_data[7:0];
assign w_red = w_read_data[31:24];
assign w_green = w_read_data[23:16];
assign w_blue = w_read_data[15:8];
assign o_chip_select = (r_tmode) ? r_tchip_select : r_chip_select;
assign o_cmd_mode = (r_tmode) ? r_tcmd_mode : r_cmd_mode;
assign o_data_out = (r_tmode) ? r_tdata_out : r_data_out;
assign o_write = (r_tmode) ? r_twrite : r_write;
assign o_read = (r_tmode) ? r_tread : r_read;
assign o_data_out_en = (r_tmode) ? r_tdata_out_en : r_data_out_en;
assign w_hard_tear_ready = (i_enable_tearing && ! i_soft_tearing && (i_tearing_effect == i_tearing_polarity));
assign w_delayed = (r_delay_count >= `DELAY_COUNT);
assign w_tdelayed = (r_tdelay_count >= `DELAY_COUNT);
assign debug[0] = i_enable;
assign debug[1] = o_cmd_mode;
assign debug[2] = o_write;
assign debug[3] = o_read;
assign debug[11:4] = o_data_out_en ? o_data_out : i_data_in;
assign debug[12] = r_tmode;
assign debug[16:13] = state;
assign debug[20:17] = tstate;
assign debug[21] = o_data_out_en;
assign debug[31:22] = 10'b0;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
//Control of Physical lines
r_chip_select <= 0;
r_data_out <= 0;
r_write <= 0;
r_read <= 0;
r_cmd_mode <= 1;
r_data_out_en <= 1;
r_read_count <= 0;
r_read_stb <= 0;
r_read_act <= 0;
r_pixel_count <= 0;
r_finished_image <= 0;
r_delay_count <= 0;
end
else begin
//Strobes
r_finished_image <= 0;
r_read_stb <= 0;
//Get a ping pong FIFO
if (w_read_rdy && !r_read_act) begin
r_read_count <= 0;
r_read_act <= 1;
end
if (r_delay_count < `DELAY_COUNT) begin
r_delay_count <= r_delay_count + 1;
end
else begin
r_write <= 0;
r_cmd_mode <= 1;
end
case (state)
IDLE: begin
//Is there going to be some weird behavior with the state machine
if ((r_pixel_count >= i_num_pixels) || !i_enable) begin
r_pixel_count <= 0;
r_finished_image <= 1;
r_chip_select <= 0;
end
//Start a transaction
if (i_enable && r_read_act && (!r_tmode || w_hard_tear_ready)) begin
if (r_pixel_count == 0) begin
//We are at the beginning of a Frame, need to start writing to the
//first address
$display("initiate a LCD MEM write");
r_chip_select <= 1;
r_cmd_mode <= 0;
r_write <= 1;
r_data_out <= i_mem_write_cmd;
state <= WRITE_ADDRESS;
//r_read_stb <= 1;
r_delay_count <= 0;
end
else if (r_read_act) begin
state <= WRITE_RED_START;
r_delay_count <= 0;
end
end
//else begin
// r_chip_select <= 0;
//end
end
WRITE_ADDRESS: begin
if (w_delayed) begin
state <= WRITE_RED_START;
end
end
WRITE_RED_START: begin
r_write <= 1;
r_data_out <= {w_red[7:2], 2'b00};
state <= WRITE_RED;
r_delay_count <= 0;
end
WRITE_RED: begin
if (w_delayed) begin
state <= WRITE_GREEN_START;
end
end
WRITE_GREEN_START: begin
r_write <= 1;
r_data_out <= {w_green[7:2], 2'b00};
r_delay_count <= 0;
state <= WRITE_GREEN;
end
WRITE_GREEN: begin
if (w_delayed) begin
state <= WRITE_BLUE_START;
end
end
WRITE_BLUE_START: begin
if (r_read_count < w_read_size - 1) begin
r_read_stb <= 1;
end
r_write <= 1;
r_data_out <= {w_blue[7:2], 2'b00};
state <= WRITE_BLUE;
r_delay_count <= 0;
end
WRITE_BLUE: begin
if (w_delayed) begin
r_delay_count <= 0;
r_pixel_count <= r_pixel_count + 1;
if (r_read_count < w_read_size - 1) begin
r_read_count <= r_read_count + 1;
//r_read_stb <= 1;
state <= WRITE_RED_START;
end
else begin
//Hard tearing
if (i_enable_tearing && !i_soft_tearing && !w_hard_tear_ready) begin
//Wait for hard tearing to be deasserted
r_read_act <= 0;
state <= IDLE;
end
else if (!i_enable_tearing || i_soft_tearing) begin
//soft tearing
r_read_act <= 0;
state <= IDLE;
end
end
end
end
endcase
end
end
always @ (posedge clk) begin
if (rst || !i_enable) begin
tstate <= IDLE;
if (i_enable_tearing && i_soft_tearing) begin
r_tmode <= 1;
end
else begin
r_tmode <= 0;
end
r_tchip_select <= 0;
r_tcmd_mode <= 0;
r_twrite <= 0;
r_tread <= 0;
r_tdata_out_en <= 0;
r_tdata_out <= i_tearing_reg;
r_tdata_count <= 0;
end
else begin
r_twrite <= 0;
r_tread <= 0;
r_tcmd_mode <= 1; //Default to data mode
r_tdata_out_en <= 0;
r_tdata <= 0;
case (tstate)
IDLE: begin
if (i_enable_tearing && i_soft_tearing) begin
r_tmode <= 1;
end
else begin
r_tmode <= 0;
r_tchip_select <= 0;
end
r_tdata_count <= 0;
if (i_enable && r_read_act) begin
r_tchip_select <= 1;
r_tcmd_mode <= 0;
r_tdata_out_en <= 1;
r_tdata_out <= i_tearing_reg;
r_tdelay_count <= 0;
tstate <= TEARING_WRITE_DELAY;
//Output is always to get the tear status
r_twrite <= 1;
end
end
TEARING_WRITE_DELAY: begin
if (w_tdelayed) begin
tstate <= GET_TEARING;
end
end
GET_TEARING: begin
tstate <= READ_TEAR_STATUS;
r_tread <= 1;
end
READ_TEAR_STATUS: begin
if (w_tdelayed) begin
r_tdata <= {r_tdata[23:0], i_data_in};
if (r_tdata_count < i_tearing_count) begin
r_tdata_count <= r_tdata_count + 1;
tstate <= GET_TEARING;
r_tdelay_count <= 0;
end
else begin
tstate <= TEARING_FINISHED;
end
end
end
TEARING_FINISHED: begin
if (r_tdata == i_tearing_value) begin
r_tmode <= 0;
r_tchip_select <= 0;
if (r_finished_image) begin
tstate <= IDLE;
end
end
else begin
tstate <= IDLE;
end
end
endcase
end
end
endmodule
|
module testbench();
localparam width_p = 8;
logic [width_p-1:0] li;
logic [`BSG_SAFE_CLOG2(width_p)-1:0] addr_lo;
logic v_lo;
bsg_priority_encode #(
.width_p(8)
,.lo_to_hi_p(1)
) pe (
.i(li)
,.addr_o(addr_lo)
,.v_o(v_lo)
);
initial begin
li = 8'b0;
#(10);
assert(v_lo == 1'b0);
assert(addr_lo == 8'b0);
li = 8'b1;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'b0);
li = 8'b11;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'b0);
li = 8'b10;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'b1);
li = 8'b100;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd2);
li = 8'b1000;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd3);
li = 8'b1000_0000;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd7);
li = 8'b1010_0000;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd5);
li = 8'b1011_0000;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd4);
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_spi (
spi_cs0n,
spi_cs1n,
spi_clk,
spi_sd_en,
spi_sd_o,
spi_sd_i,
up_rstn,
up_clk,
up_spi_start,
up_spi_devsel,
up_spi_wdata,
up_spi_rdata,
up_spi_status,
debug_data,
debug_trigger);
output spi_cs0n;
output spi_cs1n;
output spi_clk;
output spi_sd_en;
output spi_sd_o;
input spi_sd_i;
input up_rstn;
input up_clk;
input up_spi_start;
input up_spi_devsel;
input [23:0] up_spi_wdata;
output [ 7:0] up_spi_rdata;
output up_spi_status;
output [63:0] debug_data;
output [ 7:0] debug_trigger;
reg spi_cs0n;
reg spi_cs1n;
reg spi_clk;
reg spi_sd_en;
reg spi_sd_o;
reg spi_count_5_d;
reg [ 2:0] spi_clk_count;
reg [ 5:0] spi_count;
reg spi_rwn;
reg [23:0] spi_data_out;
reg [ 7:0] spi_data_in;
reg up_spi_start_d;
reg up_spi_status;
reg [ 7:0] up_spi_rdata;
wire spi_cs_en_s;
assign debug_trigger[7] = spi_cs0n;
assign debug_trigger[6] = spi_cs1n;
assign debug_trigger[5] = spi_sd_en;
assign debug_trigger[4] = spi_count[5];
assign debug_trigger[3] = up_spi_devsel;
assign debug_trigger[2] = up_spi_start;
assign debug_trigger[1] = up_spi_start_d;
assign debug_trigger[0] = up_spi_status;
assign debug_data[63:62] = 'd0;
assign debug_data[61:61] = spi_cs_en_s;
assign debug_data[60:60] = up_spi_start_d;
assign debug_data[59:52] = up_spi_rdata;
assign debug_data[51:44] = spi_data_in;
assign debug_data[43:20] = spi_data_out;
assign debug_data[19:19] = spi_rwn;
assign debug_data[18:18] = spi_count_5_d;
assign debug_data[17:12] = spi_count;
assign debug_data[11: 9] = spi_clk_count;
assign debug_data[ 8: 8] = up_spi_status;
assign debug_data[ 7: 7] = up_spi_devsel;
assign debug_data[ 6: 6] = up_spi_start;
assign debug_data[ 5: 5] = spi_sd_i;
assign debug_data[ 4: 4] = spi_sd_o;
assign debug_data[ 3: 3] = spi_sd_en;
assign debug_data[ 2: 2] = spi_clk;
assign debug_data[ 1: 1] = spi_cs1n;
assign debug_data[ 0: 0] = spi_cs0n;
assign spi_cs_en_s = spi_count_5_d | spi_count[5];
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
spi_cs0n <= 'd1;
spi_cs1n <= 'd1;
spi_clk <= 'd0;
spi_sd_en <= 'd0;
spi_sd_o <= 'd0;
spi_count_5_d <= 'd0;
spi_clk_count <= 'd0;
spi_count <= 'd0;
spi_rwn <= 'd0;
spi_data_out <= 'd0;
spi_data_in <= 'd0;
up_spi_start_d <= 'd0;
up_spi_status <= 'd0;
up_spi_rdata <= 'd0;
end else begin
spi_cs0n <= up_spi_devsel | (~spi_cs_en_s);
spi_cs1n <= (~up_spi_devsel) | (~spi_cs_en_s);
spi_clk <= spi_clk_count[2] & spi_count[5];
spi_sd_en <= (spi_count[5:3] == 3'b111) ? spi_rwn : 1'b0;
spi_sd_o <= spi_data_out[23];
if (spi_clk_count == 3'b100) begin
spi_count_5_d <= spi_count[5];
end
spi_clk_count <= spi_clk_count + 1'b1;
if (spi_count[5] == 1'b1) begin
if (spi_clk_count == 3'b111) begin
spi_count <= spi_count + 1'b1;
end
spi_rwn <= spi_rwn;
if (spi_clk_count == 3'b111) begin
spi_data_out <= {spi_data_out[22:0], 1'b0};
end
if ((spi_clk_count == 3'b100) && (spi_rwn == 1'b1) && (spi_count[5:3] == 3'b111)) begin
spi_data_in <= {spi_data_in[6:0], spi_sd_i};
end
end else if ((spi_clk_count == 3'b111) && (up_spi_start == 1'b1) &&
(up_spi_start_d == 1'b0)) begin
spi_count <= 6'h28;
spi_rwn <= up_spi_wdata[23];
spi_data_out <= up_spi_wdata;
spi_data_in <= 8'd0;
end
if (spi_clk_count == 3'b111) begin
up_spi_start_d <= up_spi_start;
end
up_spi_status <= ~(spi_count[5] | (up_spi_start & ~up_spi_start_d));
up_spi_rdata <= spi_data_in;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
module i2s_clkctrl_apb (
input clk, // Interface clock
input reset_n, // asynchronous, active low
// APB
input [4:0] paddr, // apb address
input penable, // apb enable
input pwrite, // apb write strobe
input [31:0] pwdata, // apb data in
input psel, // apb select
output reg [31:0] prdata, // apb data out
output pready, // apb ready
// Clock inputs, synthesized in PLL or external TCXOs
input clk_48, // this clock, divided by mclk_devisor, should be 22.
input clk_44,
// In slave mode, an external master makes the clocks
input ext_bclk,
input ext_playback_lrclk,
input ext_capture_lrclk,
output master_slave_mode, // 1 = master, 0 (default) = slave
// Clock derived outputs
output clk_sel_48_44, // 1 = mclk derived from 44, 0 (default) mclk derived from 48
output mclk,
output bclk,
output playback_lrclk,
output capture_lrclk
);
/*
* Example: Input clock is 24.5760MHz
* mclk_divisor = 0 (divide by (0+1)*2=2) => mclk = 12.288MHz
* bclk_divisor = 3 (divide by (3+1)*2=8) => bclk = 3.072MHz
* lrclk_divisor = 15 (divide by (15*16+15+1)*2=512) => lrclk = 0.048MHz
*
* Example: Input clock is 33.8688MHz
* mclk_divisor = 0 (divide by (0+1)*2=2) => mclk = 16.9344MHz
* bclk_divisor = 5 (divide by (5+1)*2=12) => bclk = 2.8224MHz
* lrclk_divisor = 23 (divide by (23*16+15+1)*2=768 => lrclk = 0.0441MHz
*/
reg [31:0] cmd_reg1;
wire cmd_sel1 = psel && (paddr == 0);
reg [31:0] cmd_reg2;
wire cmd_sel2 = psel && (paddr == 4);
assign master_slave_mode = cmd_reg1[0]; // 1 = master, 0 (default) = slave
assign clk_sel_48_44 = cmd_reg1[1]; // 1 = mclk derived from 44, 0 (default) mclk derived from 48
wire cmd_reg2_wr = cmd_sel2 & pwrite & penable;
// Register access
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
cmd_reg1 <= 0;
cmd_reg2 <= 0;
end
else
begin
if (cmd_sel1 & pwrite & penable) // write cmd
cmd_reg1 <= pwdata;
else if (cmd_sel1 & ~pwrite & ~penable) // cmd readback
prdata <= cmd_reg1;
if (cmd_reg2_wr) // write cmd
cmd_reg2 <= pwdata;
else if (cmd_sel2 & ~pwrite & ~penable) // cmd readback
prdata <= cmd_reg2;
end
end
wire mclk48;
wire bclk48;
wire playback_lrclk48;
wire capture_lrclk48;
audio_clock_generator playback_gen48 (
.clk (clk_48),
.reset_n (reset_n),
.cmd_reg1 (cmd_reg1),
.cmd_reg2 (cmd_reg2),
.mclk (mclk48),
.bclk (bclk48),
.lrclk_clear(cmd_reg2_wr),
.lrclk1 (playback_lrclk48),
.lrclk2 (capture_lrclk48)
);
wire mclk44;
wire bclk44;
wire playback_lrclk44;
wire capture_lrclk44;
audio_clock_generator playback_gen44 (
.clk (clk_44),
.reset_n (reset_n & ~cmd_reg2_wr),
.cmd_reg1 (cmd_reg1),
.cmd_reg2 (cmd_reg2),
.mclk (mclk44),
.bclk (bclk44),
.lrclk_clear(cmd_reg2_wr),
.lrclk1 (playback_lrclk44),
.lrclk2 (capture_lrclk44)
);
// Output muxes
assign mclk = clk_sel_48_44 ? mclk44 : mclk48;
assign bclk = master_slave_mode
? (clk_sel_48_44 ? bclk44 : bclk48)
: ext_bclk;
assign playback_lrclk = master_slave_mode
? (clk_sel_48_44 ? playback_lrclk44 : playback_lrclk48)
: ext_playback_lrclk;
assign capture_lrclk = master_slave_mode
? (clk_sel_48_44 ? capture_lrclk44 : capture_lrclk48)
: ext_capture_lrclk;
// APB
assign pready = penable; // always ready (no wait states)
endmodule
module audio_clock_generator (
input clk,
input reset_n,
input [31:0] cmd_reg1,
input [31:0] cmd_reg2,
output mclk,
output bclk,
input lrclk_clear,
output lrclk1,
output lrclk2
);
wire [7:0] mclk_divisor = cmd_reg1[31:24]; // divide by (n + 1)*2
wire [7:0] bclk_divisor = cmd_reg1[23:16]; // divide by (n + 1)*2
wire [7:0] lrclk1_divisor = cmd_reg2[15:8]; // divide by (n + 1)*2*16
wire [7:0] lrclk2_divisor = cmd_reg2[7:0]; // divide by (n + 1)*2*16
clk_divider #(.N(8)) mclk_divider (
.clk (clk),
.reset_n (reset_n),
.max_count (mclk_divisor),
.q (mclk)
);
clk_divider #(.N(8)) bclk_divider (
.clk (clk),
.reset_n (reset_n),
.max_count (bclk_divisor),
.q (bclk)
);
clk_divider #(.N(12)) lrclk1_divider (
.clk (clk),
.reset_n (reset_n & ~lrclk),
.max_count ({lrclk1_divisor, 4'b1111}),
.q (lrclk1)
);
clk_divider #(.N(12)) lrclk2_divider (
.clk (clk),
.reset_n (reset_n & ~lrclk_clear),
.max_count ({lrclk2_divisor, 4'b1111}),
.q (lrclk2)
);
endmodule
module clk_divider #(parameter N = 8) (
input clk,
input reset_n,
input [N-1:0] max_count,
output reg q
);
reg [N-1:0] counter;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
q <= 0;
counter <= 0;
end
else
begin
if (counter == max_count)
begin
counter <= 0;
q <= ~q;
end
else
counter <= counter + 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_2_V
`define SKY130_FD_SC_LS__EBUFN_2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_2_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : mig_wrap_mig_7series_0_0_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_wrap_mig_7series_0_0_mig #
(
parameter RST_ACT_LOW = 1,
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DQ_CNT_WIDTH = 4,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 2,
// # of DM (data mask)
parameter DQ_WIDTH = 16,
// # of DQ (data)
parameter DQS_WIDTH = 2,
parameter DQS_CNT_WIDTH = 1,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter DATA_WIDTH = 16,
parameter ECC_TEST = "OFF",
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
//Possible Parameters
//1.BANK_ROW_COLUMN : Address mapping is
// in form of Bank Row Column.
//2.ROW_BANK_COLUMN : Address mapping is
// in the form of Row Bank Column.
//3.TG_TEST : Scrambles Address bits
// for distributed Addressing.
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ODT_WIDTH = 1,
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 1,
// # = 1, When Chip Select (CS#) output is enabled
// = 0, When Chip Select (CS#) output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
parameter PHY_CONTROL_MASTER_BANK = 0,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
parameter MEM_DENSITY = "1Gb",
// Indicates the density of the Memory part
// Added for the sake of Vivado simulations
parameter MEM_SPEEDGRADE = "25E",
// Indicates the Speed grade of Memory Part
// Added for the sake of Vivado simulations
parameter MEM_DEVICE_WIDTH = 16,
// Indicates the device width of the Memory Part
// Added for the sake of Vivado simulations
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 5,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter OUTPUT_DRV = "HIGH",
// Output Drive Strength (Extended Mode Register).
// # = "HIGH" - FULL,
// = "LOW" - REDUCED.
parameter RTT_NOM = "50",
// RTT (Nominal) (Extended Mode Register).
// = "150" - 150 Ohms,
// = "75" - 75 Ohms,
// = "50" - 50 Ohms.
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 4999,
// Input Clock Period
parameter CLKFBOUT_MULT = 6,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_PHASE = 0.0,
// Phase for PLL output clock (CLKOUT0)
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 4,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 64,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 8,
// VCO output divisor for PLL output clock (CLKOUT3)
parameter MMCM_VCO = 1200,
// Max Freq (MHz) of MMCM VCO
parameter MMCM_MULT_F = 7,
// write MMCM VCO multiplier
parameter MMCM_DIVCLK_DIVIDE = 1,
// write MMCM VCO divisor
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tCKE = 7500,
// memory tCKE paramter in pS
parameter tFAW = 45000,
// memory tRAW paramter in pS.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter in pS.
parameter tRAS = 40000,
// memory tRAS paramter in pS.
parameter tRCD = 15000,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 127500,
// memory tRFC paramter in pS.
parameter tRP = 12500,
// memory tRP paramter in pS.
parameter tRRD = 10000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
parameter SIMULATION = "TRUE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b0101,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'hFFC_3F7_FFF_3FE,
parameter PHY_1_BITLANES = 48'h000_000_000_000,
parameter PHY_2_BITLANES = 48'h000_000_000_000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_03,
parameter ADDR_MAP
= 192'h000_000_000_010_033_01A_019_032_03A_034_018_036_012_011_017_015,
parameter BANK_MAP = 36'h013_016_01B,
parameter CAS_MAP = 12'h039,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_038,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_035,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_037,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h014,
parameter WE_MAP = 12'h03B,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02_00,
parameter DATA0_MAP = 96'h008_004_009_007_005_001_006_003,
parameter DATA1_MAP = 96'h022_028_020_024_027_025_026_021,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_029_002,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter DATA_IO_IDLE_PWRDWN = "ON",
// # = "ON", "OFF"
parameter BANK_TYPE = "HR_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "HR_LP",
// # = "HP_LP", "HR_LP", "DEFAULT"
parameter CKE_ODT_AUX = "FALSE",
parameter USER_REFRESH = "OFF",
parameter WRLVL = "OFF",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "STRICT",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IODELAY_GRP0 = "MIG_WRAP_MIG_7SERIES_0_0_IODELAY_MIG0",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (200MHz).
parameter SYSCLK_TYPE = "NO_BUFFER",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "NO_BUFFER",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter CMD_PIPE_PLUS1 = "ON",
// add pipeline stage between MC and PHY
parameter DRAM_TYPE = "DDR2",
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 3333,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "TRUE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
parameter UI_EXTRA_CLOCKS = "FALSE",
// Generates extra clocks as
// 1/2, 1/4 and 1/8 of fabrick clock.
// Valid for DDR2/DDR3 AXI interfaces
// based on GUI selection
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_MEM_SIZE = "134217728",
// Address Space required for this component
parameter C_S_AXI_ADDR_WIDTH = 32,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_MC_nCK_PER_CLK = 2,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
// "WRITE_PRIORITY", "WRITE_PRIORITY_REG"
parameter C_S_AXI_REG_EN0 = 20'h00000,
// C_S_AXI_REG_EN0[00] = Reserved
// C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE
parameter C_S_AXI_REG_EN1 = 20'h00000,
// Instatiates register slices after the upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
// 7 => ADDRESS = Optimized for address channel
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Base address of AXI4 Memory Mapped bus.
parameter C_ECC_ONOFF_RESET_VALUE = 1,
// Controls ECC on/off value at startup/reset
parameter C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Temparature monitor parameter
//***************************************************************************
parameter TEMP_MON_CONTROL = "INTERNAL"
// # = "INTERNAL", "EXTERNAL"
// parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr2_dq,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
inout [DQS_WIDTH-1:0] ddr2_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr2_addr,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CK_WIDTH-1:0] ddr2_ck_p,
output [CK_WIDTH-1:0] ddr2_ck_n,
output [CKE_WIDTH-1:0] ddr2_cke,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n,
output [DM_WIDTH-1:0] ddr2_dm,
output [ODT_WIDTH-1:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output mmcm_locked,
input aresetn,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
localparam RANK_WIDTH = clogb2(RANKS);
localparam ECC_WIDTH = (ECC == "OFF")?
0 : (DATA_WIDTH <= 4)?
4 : (DATA_WIDTH <= 10)?
5 : (DATA_WIDTH <= 26)?
6 : (DATA_WIDTH <= 57)?
7 : (DATA_WIDTH <= 120)?
8 : (DATA_WIDTH <= 247)?
9 : 10;
localparam DATA_BUF_OFFSET_WIDTH = 1;
localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH
+ DATA_BUF_OFFSET_WIDTH;
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam TEMP_MON_EN = (SIMULATION == "TRUE") ? "ON" : "OFF";
// Enable or disable the temp monitor module
localparam tTEMPSAMPLE = 10000000; // sample every 10 us
localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock
localparam TAPSPERKCLK = 56;
// Wire declarations
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
wire clk;
wire [1:0] clk_ref;
wire [1:0] iodelay_ctrl_rdy;
wire clk_ref_in;
wire sys_rst_o;
wire clk_div2;
wire rst_div2;
wire freq_refclk ;
wire mem_refclk ;
wire pll_lock ;
wire sync_pulse;
wire mmcm_ps_clk;
wire poc_sample_pd;
wire psen;
wire psincdec;
wire psdone;
wire iddr_rst;
wire ref_dll_lock;
wire rst_phaser_ref;
wire pll_locked;
wire rst;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;
wire ddr2_reset_n;
wire ddr2_parity;
// AXI CTRL port
wire s_axi_ctrl_awvalid;
wire s_axi_ctrl_awready;
wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr;
// Slave Interface Write Data Ports
wire s_axi_ctrl_wvalid;
wire s_axi_ctrl_wready;
wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata;
// Slave Interface Write Response Ports
wire s_axi_ctrl_bvalid;
wire s_axi_ctrl_bready;
wire [1:0] s_axi_ctrl_bresp;
// Slave Interface Read Address Ports
wire s_axi_ctrl_arvalid;
wire s_axi_ctrl_arready;
wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr;
// Slave Interface Read Data Ports
wire s_axi_ctrl_rvalid;
wire s_axi_ctrl_rready;
wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata;
wire [1:0] s_axi_ctrl_rresp;
// Interrupt output
wire interrupt;
wire sys_clk_p;
wire sys_clk_n;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire [11:0] device_temp;
wire [11:0] device_temp_i;
// Debug port signals
wire dbg_idel_down_all;
wire dbg_idel_down_cpt;
wire dbg_idel_up_all;
wire dbg_idel_up_cpt;
wire dbg_sel_all_idel_cpt;
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
wire dbg_sel_pi_incdec;
wire [DQS_CNT_WIDTH:0] dbg_byte_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire [5:0] dbg_pi_counter_read_val;
wire [8:0] dbg_po_counter_read_val;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;
wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;
wire [255:0] dbg_calib_top;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;
wire [(6*RANKS)-1:0] dbg_rd_data_offset;
wire [255:0] dbg_phy_rdlvl;
wire [99:0] dbg_phy_wrcal;
wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;
wire [255:0] dbg_phy_wrlvl;
wire [255:0] dbg_phy_init;
wire [255:0] dbg_prbs_rdlvl;
wire [255:0] dbg_dqs_found_cal;
wire dbg_pi_phaselock_start;
wire dbg_pi_phaselocked_done;
wire dbg_pi_phaselock_err;
wire dbg_pi_dqsfound_start;
wire dbg_pi_dqsfound_done;
wire dbg_pi_dqsfound_err;
wire dbg_wrcal_start;
wire dbg_wrcal_done;
wire dbg_wrcal_err;
wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;
wire [11:0] dbg_pi_phase_locked_phy4lanes;
wire dbg_oclkdelay_calib_start;
wire dbg_oclkdelay_calib_done;
wire [255:0] dbg_phy_oclkdelay_cal;
wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;
wire dbg_rddata_valid;
wire [1:0] dbg_rdlvl_done;
wire [1:0] dbg_rdlvl_err;
wire [1:0] dbg_rdlvl_start;
wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;
wire [5:0] dbg_tap_cnt_during_wrlvl;
wire dbg_wl_edge_detect_valid;
wire dbg_wrlvl_done;
wire dbg_wrlvl_err;
wire dbg_wrlvl_start;
reg [63:0] dbg_rddata_r;
reg dbg_rddata_valid_r;
wire [53:0] ocal_tap_cnt;
wire [4:0] dbg_dqs;
wire [8:0] dbg_bit;
wire [8:0] rd_data_edge_detect_r;
wire [53:0] wl_po_fine_cnt;
wire [26:0] wl_po_coarse_cnt;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;
wire [5:0] dbg_data_offset;
wire [5:0] dbg_data_offset_1;
wire [5:0] dbg_data_offset_2;
wire [390:0] ddr2_ila_wrpath_int;
wire [1023:0] ddr2_ila_rdpath_int;
wire [119:0] ddr2_ila_basic_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;
//***************************************************************************
assign ui_clk = clk;
assign ui_clk_sync_rst = rst;
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
assign clk_ref_p = 1'b0;
assign clk_ref_n = 1'b0;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v4_0_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP0 (IODELAY_GRP0),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
.clk_ref (clk_ref),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.sys_rst (sys_rst)
);
mig_7series_v4_0_clk_ibuf #
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_ddr2_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
// Temperature monitoring logic
generate
if (TEMP_MON_EN == "ON") begin: temp_mon_enabled
mig_7series_v4_0_tempmon #
(
.TCQ (TCQ),
.TEMP_MON_CONTROL (TEMP_MON_CONTROL),
.XADC_CLK_PERIOD (XADC_CLK_PERIOD),
.tTEMPSAMPLE (tTEMPSAMPLE)
)
u_tempmon
(
.clk (clk),
.xadc_clk (clk_ref[0]),
.rst (rst),
.device_temp_i (device_temp_i),
.device_temp (device_temp)
);
end else begin: temp_mon_disabled
assign device_temp = 'b0;
end
endgenerate
mig_7series_v4_0_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.MMCM_VCO (MMCM_VCO),
.MMCM_MULT_F (MMCM_MULT_F),
.MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW),
.tCK (tCK),
.MEM_TYPE (DRAM_TYPE)
)
u_ddr2_infrastructure
(
// Outputs
.rstdiv0 (rst),
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
// .auxout_clk (),
.ui_addn_clk_0 (),
.ui_addn_clk_1 (),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.pll_locked (pll_locked),
.mmcm_locked (mmcm_locked),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.psen (psen),
.psincdec (psincdec),
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v4_0_memc_ui_top_axi #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.IODELAY_GRP0 (IODELAY_GRP0),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.CL (CL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.IDELAY_ADJ ("OFF"),
.FINE_PER_BIT ("OFF"),
.CENTER_COMP_MODE ("OFF"),
.PI_VAL_ADJ ("OFF"),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S_AXI_BASEADDR),
.C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE),
.C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB ("FALSE"),
.FPGA_VOLT_TYPE ("N")
)
u_memc_ui_top_axi
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_locked),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.psen (psen),
.psincdec (psincdec),
.rst (rst),
.rst_phaser_ref (rst_phaser_ref),
.ref_dll_lock (ref_dll_lock),
// Memory interface ports
.ddr_dq (ddr2_dq),
.ddr_dqs_n (ddr2_dqs_n),
.ddr_dqs (ddr2_dqs_p),
.ddr_addr (ddr2_addr),
.ddr_ba (ddr2_ba),
.ddr_cas_n (ddr2_cas_n),
.ddr_ck_n (ddr2_ck_n),
.ddr_ck (ddr2_ck_p),
.ddr_cke (ddr2_cke),
.ddr_cs_n (ddr2_cs_n),
.ddr_dm (ddr2_dm),
.ddr_odt (ddr2_odt),
.ddr_ras_n (ddr2_ras_n),
.ddr_reset_n (ddr2_reset_n),
.ddr_parity (ddr2_parity),
.ddr_we_n (ddr2_we_n),
.bank_mach_next (bank_mach_next),
// Application interface ports
.app_ecc_multiple_err_o (),
.app_ecc_single_err (),
.device_temp (device_temp),
.calib_tap_req (),
.calib_tap_load (1'b0),
.calib_tap_addr (7'b0),
.calib_tap_val (8'b0),
.calib_tap_load_done (1'b0),
// Debug logic ports
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.aresetn (aresetn),
.app_sr_req (1'b0),
.app_sr_active (app_sr_active),
.app_ref_req (1'b0),
.app_ref_ack (app_ref_ack),
.app_zq_req (1'b0),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// AXI CTRL port
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
.s_axi_ctrl_awready (s_axi_ctrl_awready),
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
// Slave Interface Write Data Ports
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
.s_axi_ctrl_wready (s_axi_ctrl_wready),
.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
// Slave Interface Write Response Ports
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
.s_axi_ctrl_bready (s_axi_ctrl_bready),
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),
// Slave Interface Read Address Ports
.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
.s_axi_ctrl_arready (s_axi_ctrl_arready),
.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
// Slave Interface Read Data Ports
.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
.s_axi_ctrl_rready (s_axi_ctrl_rready),
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
// Interrupt output
.interrupt (interrupt),
.init_calib_complete (init_calib_complete),
.dbg_poc (dbg_poc)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
assign dbg_byte_sel = 'd0;
assign dbg_sel_pi_incdec = 1'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
assign dbg_sel_po_incdec = 'b0;
endmodule
|
//==================================================================================================
// Filename : DECO_CORDIC_OP.v
// Created On : 2016-10-03 13:00:49
// Last Modified : 2016-10-28 23:06:30
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : DECODER TO TO SELECT THE THIRD MUX AND INVERT SIGN
//
//
//==================================================================================================
`timescale 1ns / 1ps
module DECO_CORDIC_EXT #(parameter W = 32)(
input wire [W-1:0] data_i,
input wire operation,
input wire [1:0] shift_region_flag,
output reg sel_mux_3,
output reg [W-1:0] data_out_CORDECO
);
always @(*) begin
if(operation == 1'b0)
begin //COSENO
case (shift_region_flag)
2'b00 : begin
sel_mux_3 = 1'b0;
data_out_CORDECO = data_i;
end
2'b01 : begin
sel_mux_3 = 1'b1;
data_out_CORDECO = {~data_i[W-1],data_i[W-2:0]};
end
2'b10 : begin
sel_mux_3 = 1'b1;
data_out_CORDECO = data_i;
end
2'b11 : begin
sel_mux_3 = 1'b0;
data_out_CORDECO = data_i;
end
endcase
end
else begin ///SENO
case (shift_region_flag)
2'b00 : begin
sel_mux_3 = 1'b1;
data_out_CORDECO = data_i;
end
2'b01 : begin
sel_mux_3 = 1'b0;
data_out_CORDECO = data_i;
end
2'b10 : begin
sel_mux_3 = 1'b0;
data_out_CORDECO = {~data_i[W-1],data_i[W-2:0]};;
end
2'b11 : begin
sel_mux_3 = 1'b1;
data_out_CORDECO = data_i;
end
endcase
end
end
endmodule
|
`timescale 1 ns /10 ps
`include "alu.v"
`include "componentes.v"
`include "cpu.v"
`include "e_s.v"
`include "memprog.v"
`include "memvga.v"
`include "microc.v"
`include "printvga.v"
`include "regtovga.v"
`include "uc.v"
`include "cpu_vga.v"
`include "vga.v"
`include "stack.v"
module cpu_tb;
reg clk, reset;
reg [7:0] e1,e2,e3,e4;
wire [7:0] s1,s2,s3,s4;
wire [5:0] opcode;
wire [2:0] operacion;
wire z;
reg vgae;
wire [7:0] vgax;
wire [7:0] vgay;
wire vgaw;
wire CLOCK;
wire [3:0] VGA_R;
wire [3:0] VGA_G;
wire [3:0] VGA_B;
wire VGA_VS;
wire VGA_HS;
wire VGA_BLANK;
wire VGA_SYNC;
wire VGA_CLK;
always
begin
clk = 1;
#20;
clk = 0;
#60;
end
initial
begin
$monitor("time: %0d, clk: %b, reset: %b", $time, clk, reset);
$dumpfile("cpu_tb.vcd");
$dumpvars;
e1 = 8'b00000100; //4
e2 = 8'b00000011; //3
e3 = 8'b00000000; //0
e4 = 8'b00000000; //0
vgae=0;
reset = 1;
#5
reset = 0;
#30000
$finish;
end
//cpu cpu_(clk,~reset,vgae,e1,e2,e3,e4,s1,s2,s3,s4,opcode,z);
cpu_vga cpu_vga_(clk,~reset,e1,e2,e3,CLOCK,s1,s2,s3,s4,opcode,z,VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS, VGA_BLANK,VGA_SYNC,VGA_CLK);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_macb_l.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_macb_l(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa,
data_prev_px_l, rclk, scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input [129:0] data_prev_px_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire [129:0] data_px_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
// Generate write selects
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
/*
mux2ds #(`PCX_WIDTH) mx2ds_pcx_datain_q0(
.dout (q0_datain_pa[`PCX_WIDTH-1:0]),
.in0 (q1_dataout[`PCX_WIDTH-1:0]),
.in1 (src_pcx_data_pa[`PCX_WIDTH-1:0]),
.sel0 (arb_pcxdp_shift_px),
.sel1 (arb_pcxdp_qsel0_pa));
*/
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
assign data_out_px_l[129:0] = data_px_l[129:0] & data_prev_px_l[129:0];
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:49:18 09/03/2013
// Design Name:
// Module Name: timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timer(clk, rst, start_timer, time_value, expired);
input clk;
input rst;
input start_timer;
input [3:0] time_value;
output expired;
reg cuenta_finalizada;
reg [3:0] contador;
//Reloj a 1Hz
wire div_clk;
initial
begin
contador <= 4'b0001;
cuenta_finalizada <= 0;
end
//Divisor de reloj
clock_divider mod_divider(clk,rst,div_clk);
//
assign expired = start_timer & cuenta_finalizada;
//
always @( posedge div_clk, negedge start_timer)
begin
if(~start_timer)
begin
cuenta_finalizada <= 0;
contador <= 4'b0001; //Reset
end
else
begin
if(contador == time_value)
begin
contador <= 4'b0001;
cuenta_finalizada <= 1;
end
else
contador <= contador + 1;
end
end
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007-2009 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
`include "../../soclib/pipeconnect.h"
module main
(input iSYS_CLK_100
,input iSYS_RST
,input iUART_RXD
,output oUART_TXD
);
parameter FREQ = 100_000_000; // match clock frequency
parameter BPS = 9_600; // Serial speed
// Copied from yari.v
parameter ID_DC = 2'd1;
parameter ID_IC = 2'd2;
parameter ID_FB = 2'd3;
wire clock; // The master clock
/*
wire video_clock;
wire clock_locked;
// Actually, just a 1-1 clock filter for c0
// and a 65 MHz for video_clock
pll pll_inst(.inclk0(iCLK_50)
,.c0(clock)
,.c2(video_clock)
,.locked(clock_locked));
reg iSW17_, iSW17, manual_reset;
*/
assign clock = iSYS_CLK_100;
wire reset = iSYS_RST;
wire [ 7:0] rs232out_transmit_data;
wire rs232out_write_enable;
wire rs232out_busy;
wire [ 7:0] rs232in_received_data;
wire rs232in_received_data_valid;
wire mem_waitrequest;
wire [1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [1:0] mem_readdataid;
wire yari_mem_waitrequest;
wire [1:0] yari_mem_id;
wire [29:0] yari_mem_address;
wire yari_mem_read;
wire yari_mem_write;
wire [31:0] yari_mem_writedata;
wire [3:0] yari_mem_writedatamask;
wire `REQ rs232_req;
wire `RES rs232_res;
yari yari_inst(
.clock(clock)
,.rst(reset)
// Inputs
,.mem_waitrequest (yari_mem_waitrequest)
,.mem_readdata (mem_readdata)
,.mem_readdataid (mem_readdataid)
// Outputs
,.mem_id (yari_mem_id)
,.mem_address (yari_mem_address)
,.mem_read (yari_mem_read)
,.mem_write (yari_mem_write)
,.mem_writedata (yari_mem_writedata)
,.mem_writedatamask(yari_mem_writedatamask)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
rs232out rs232out_inst
(.clock (clock),
.serial_out (oUART_TXD),
.transmit_data(rs232out_transmit_data),
.we (rs232out_write_enable),
.busy (rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock (clock),
.serial_in (iUART_RXD),
.received_data(rs232in_received_data),
.attention (rs232in_received_data_valid));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
wire [31:0] vsynccnt;
rs232 rs232_inst(.clk(clock),
.rst(reset),
.iKEY(0),
.vsynccnt(vsynccnt),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_received_data_valid),
.rs232in_data (rs232in_received_data),
.rs232out_busy(rs232out_busy),
.rs232out_w (rs232out_write_enable),
.rs232out_d (rs232out_transmit_data));
assign mem_id = yari_mem_id;
assign mem_address = yari_mem_address;
assign mem_read = yari_mem_read;
assign mem_write = yari_mem_write;
assign mem_writedata = yari_mem_writedata;
assign mem_writedatamask = yari_mem_writedatamask;
assign yari_mem_waitrequest = mem_waitrequest;
endmodule
|
// Polyphase filter bank for upsampling from 44100.0kHz to 48000.0kHz
// Depth: 32
module rom_firbank_441_480(
input wire clk,
input wire [11:0] addr,
output wire [23:0] data);
reg [23:0] data_ff;
assign data = data_ff;
always @(posedge clk) begin
case(addr)
0: data_ff <= 24'h005690; // 22160
1: data_ff <= 24'hFFC696; // -14698
2: data_ff <= 24'h002C4B; // 11339
3: data_ff <= 24'hFFDD3C; // -8900
4: data_ff <= 24'h001AC2; // 6850
5: data_ff <= 24'hFFEC21; // -5087
6: data_ff <= 24'h000E18; // 3608
7: data_ff <= 24'hFFF688; // -2424
8: data_ff <= 24'h0005F9; // 1529
9: data_ff <= 24'hFFFC81; // -895
10: data_ff <= 24'h0001DF; // 479
11: data_ff <= 24'hFFFF1A; // -230
12: data_ff <= 24'h00005F; // 95
13: data_ff <= 24'hFFFFE1; // -31
14: data_ff <= 24'h000006; // 6
15: data_ff <= 24'h000000; // 0
16: data_ff <= 24'h00BBFD; // 48125
17: data_ff <= 24'hFF9771; // -26767
18: data_ff <= 24'h004854; // 18516
19: data_ff <= 24'hFFCB52; // -13486
20: data_ff <= 24'h002665; // 9829
21: data_ff <= 24'hFFE4A7; // -7001
22: data_ff <= 24'h0012C6; // 4806
23: data_ff <= 24'hFFF3B8; // -3144
24: data_ff <= 24'h000794; // 1940
25: data_ff <= 24'hFFFBA5; // -1115
26: data_ff <= 24'h00024C; // 588
27: data_ff <= 24'hFFFEEA; // -278
28: data_ff <= 24'h000072; // 114
29: data_ff <= 24'hFFFFDB; // -37
30: data_ff <= 24'h000008; // 8
31: data_ff <= 24'h000000; // 0
32: data_ff <= 24'h0122B1; // 74417
33: data_ff <= 24'hFF67FC; // -38916
34: data_ff <= 24'h006480; // 25728
35: data_ff <= 24'hFFB954; // -18092
36: data_ff <= 24'h003213; // 12819
37: data_ff <= 24'hFFDD25; // -8923
38: data_ff <= 24'h001779; // 6009
39: data_ff <= 24'hFFF0E4; // -3868
40: data_ff <= 24'h000932; // 2354
41: data_ff <= 24'hFFFAC7; // -1337
42: data_ff <= 24'h0002BA; // 698
43: data_ff <= 24'hFFFEB8; // -328
44: data_ff <= 24'h000085; // 133
45: data_ff <= 24'hFFFFD5; // -43
46: data_ff <= 24'h000009; // 9
47: data_ff <= 24'h000000; // 0
48: data_ff <= 24'h018AA5; // 101029
49: data_ff <= 24'hFF383D; // -51139
50: data_ff <= 24'h0080CC; // 32972
51: data_ff <= 24'hFFA744; // -22716
52: data_ff <= 24'h003DCD; // 15821
53: data_ff <= 24'hFFD59B; // -10853
54: data_ff <= 24'h001C30; // 7216
55: data_ff <= 24'hFFEE0D; // -4595
56: data_ff <= 24'h000AD2; // 2770
57: data_ff <= 24'hFFF9E8; // -1560
58: data_ff <= 24'h000329; // 809
59: data_ff <= 24'hFFFE87; // -377
60: data_ff <= 24'h000098; // 152
61: data_ff <= 24'hFFFFCE; // -50
62: data_ff <= 24'h00000A; // 10
63: data_ff <= 24'h000000; // 0
64: data_ff <= 24'h01F3D8; // 127960
65: data_ff <= 24'hFF0836; // -63434
66: data_ff <= 24'h009D37; // 40247
67: data_ff <= 24'hFF9524; // -27356
68: data_ff <= 24'h004991; // 18833
69: data_ff <= 24'hFFCE0B; // -12789
70: data_ff <= 24'h0020ED; // 8429
71: data_ff <= 24'hFFEB33; // -5325
72: data_ff <= 24'h000C73; // 3187
73: data_ff <= 24'hFFF907; // -1785
74: data_ff <= 24'h000398; // 920
75: data_ff <= 24'hFFFE55; // -427
76: data_ff <= 24'h0000AC; // 172
77: data_ff <= 24'hFFFFC8; // -56
78: data_ff <= 24'h00000B; // 11
79: data_ff <= 24'hFFFFFF; // -1
80: data_ff <= 24'h025E43; // 155203
81: data_ff <= 24'hFED7EC; // -75796
82: data_ff <= 24'h00B9BC; // 47548
83: data_ff <= 24'hFF82F5; // -32011
84: data_ff <= 24'h00555F; // 21855
85: data_ff <= 24'hFFC674; // -14732
86: data_ff <= 24'h0025AD; // 9645
87: data_ff <= 24'hFFE856; // -6058
88: data_ff <= 24'h000E17; // 3607
89: data_ff <= 24'hFFF826; // -2010
90: data_ff <= 24'h000408; // 1032
91: data_ff <= 24'hFFFE23; // -477
92: data_ff <= 24'h0000C0; // 192
93: data_ff <= 24'hFFFFC2; // -62
94: data_ff <= 24'h00000D; // 13
95: data_ff <= 24'hFFFFFF; // -1
96: data_ff <= 24'h02C9E4; // 182756
97: data_ff <= 24'hFEA763; // -88221
98: data_ff <= 24'h00D65A; // 54874
99: data_ff <= 24'hFF70BA; // -36678
100: data_ff <= 24'h006134; // 24884
101: data_ff <= 24'hFFBED9; // -16679
102: data_ff <= 24'h002A71; // 10865
103: data_ff <= 24'hFFE577; // -6793
104: data_ff <= 24'h000FBC; // 4028
105: data_ff <= 24'hFFF743; // -2237
106: data_ff <= 24'h000479; // 1145
107: data_ff <= 24'hFFFDF0; // -528
108: data_ff <= 24'h0000D4; // 212
109: data_ff <= 24'hFFFFBB; // -69
110: data_ff <= 24'h00000E; // 14
111: data_ff <= 24'hFFFFFF; // -1
112: data_ff <= 24'h0336B5; // 210613
113: data_ff <= 24'hFE769F; // -100705
114: data_ff <= 24'h00F30F; // 62223
115: data_ff <= 24'hFF5E73; // -41357
116: data_ff <= 24'h006D0F; // 27919
117: data_ff <= 24'hFFB739; // -18631
118: data_ff <= 24'h002F39; // 12089
119: data_ff <= 24'hFFE296; // -7530
120: data_ff <= 24'h001163; // 4451
121: data_ff <= 24'hFFF660; // -2464
122: data_ff <= 24'h0004EA; // 1258
123: data_ff <= 24'hFFFDBD; // -579
124: data_ff <= 24'h0000E8; // 232
125: data_ff <= 24'hFFFFB5; // -75
126: data_ff <= 24'h000010; // 16
127: data_ff <= 24'hFFFFFF; // -1
128: data_ff <= 24'h03A4B3; // 238771
129: data_ff <= 24'hFE45A4; // -113244
130: data_ff <= 24'h010FD6; // 69590
131: data_ff <= 24'hFF4C23; // -46045
132: data_ff <= 24'h0078F0; // 30960
133: data_ff <= 24'hFFAF95; // -20587
134: data_ff <= 24'h003403; // 13315
135: data_ff <= 24'hFFDFB2; // -8270
136: data_ff <= 24'h00130B; // 4875
137: data_ff <= 24'hFFF57B; // -2693
138: data_ff <= 24'h00055B; // 1371
139: data_ff <= 24'hFFFD8A; // -630
140: data_ff <= 24'h0000FC; // 252
141: data_ff <= 24'hFFFFAE; // -82
142: data_ff <= 24'h000011; // 17
143: data_ff <= 24'hFFFFFF; // -1
144: data_ff <= 24'h0413D8; // 267224
145: data_ff <= 24'hFE1478; // -125832
146: data_ff <= 24'h012CAE; // 76974
147: data_ff <= 24'hFF39CC; // -50740
148: data_ff <= 24'h0084D6; // 34006
149: data_ff <= 24'hFFA7EE; // -22546
150: data_ff <= 24'h0038CF; // 14543
151: data_ff <= 24'hFFDCCD; // -9011
152: data_ff <= 24'h0014B4; // 5300
153: data_ff <= 24'hFFF496; // -2922
154: data_ff <= 24'h0005CE; // 1486
155: data_ff <= 24'hFFFD57; // -681
156: data_ff <= 24'h000110; // 272
157: data_ff <= 24'hFFFFA8; // -88
158: data_ff <= 24'h000012; // 18
159: data_ff <= 24'hFFFFFF; // -1
160: data_ff <= 24'h048421; // 295969
161: data_ff <= 24'hFDE31D; // -138467
162: data_ff <= 24'h014994; // 84372
163: data_ff <= 24'hFF276F; // -55441
164: data_ff <= 24'h0090BF; // 37055
165: data_ff <= 24'hFFA045; // -24507
166: data_ff <= 24'h003D9C; // 15772
167: data_ff <= 24'hFFD9E7; // -9753
168: data_ff <= 24'h00165F; // 5727
169: data_ff <= 24'hFFF3B0; // -3152
170: data_ff <= 24'h000640; // 1600
171: data_ff <= 24'hFFFD23; // -733
172: data_ff <= 24'h000125; // 293
173: data_ff <= 24'hFFFFA1; // -95
174: data_ff <= 24'h000014; // 20
175: data_ff <= 24'hFFFFFF; // -1
176: data_ff <= 24'h04F588; // 325000
177: data_ff <= 24'hFDB198; // -151144
178: data_ff <= 24'h016684; // 91780
179: data_ff <= 24'hFF150D; // -60147
180: data_ff <= 24'h009CAA; // 40106
181: data_ff <= 24'hFF989A; // -26470
182: data_ff <= 24'h00426C; // 17004
183: data_ff <= 24'hFFD700; // -10496
184: data_ff <= 24'h00180A; // 6154
185: data_ff <= 24'hFFF2CA; // -3382
186: data_ff <= 24'h0006B3; // 1715
187: data_ff <= 24'hFFFCEF; // -785
188: data_ff <= 24'h000139; // 313
189: data_ff <= 24'hFFFF9B; // -101
190: data_ff <= 24'h000015; // 21
191: data_ff <= 24'hFFFFFF; // -1
192: data_ff <= 24'h056808; // 354312
193: data_ff <= 24'hFD7FEF; // -163857
194: data_ff <= 24'h01837D; // 99197
195: data_ff <= 24'hFF02AA; // -64854
196: data_ff <= 24'h00A895; // 43157
197: data_ff <= 24'hFF90EF; // -28433
198: data_ff <= 24'h00473B; // 18235
199: data_ff <= 24'hFFD417; // -11241
200: data_ff <= 24'h0019B6; // 6582
201: data_ff <= 24'hFFF1E2; // -3614
202: data_ff <= 24'h000727; // 1831
203: data_ff <= 24'hFFFCBA; // -838
204: data_ff <= 24'h00014E; // 334
205: data_ff <= 24'hFFFF94; // -108
206: data_ff <= 24'h000017; // 23
207: data_ff <= 24'hFFFFFF; // -1
208: data_ff <= 24'h05DB9D; // 383901
209: data_ff <= 24'hFD4E24; // -176604
210: data_ff <= 24'h01A07B; // 106619
211: data_ff <= 24'hFEF047; // -69561
212: data_ff <= 24'h00B481; // 46209
213: data_ff <= 24'hFF8944; // -30396
214: data_ff <= 24'h004C0C; // 19468
215: data_ff <= 24'hFFD12F; // -11985
216: data_ff <= 24'h001B62; // 7010
217: data_ff <= 24'hFFF0FB; // -3845
218: data_ff <= 24'h00079B; // 1947
219: data_ff <= 24'hFFFC86; // -890
220: data_ff <= 24'h000163; // 355
221: data_ff <= 24'hFFFF8D; // -115
222: data_ff <= 24'h000018; // 24
223: data_ff <= 24'hFFFFFF; // -1
224: data_ff <= 24'h065042; // 413762
225: data_ff <= 24'hFD1C3E; // -189378
226: data_ff <= 24'h01BD7C; // 114044
227: data_ff <= 24'hFEDDE5; // -74267
228: data_ff <= 24'h00C06A; // 49258
229: data_ff <= 24'hFF819A; // -32358
230: data_ff <= 24'h0050DB; // 20699
231: data_ff <= 24'hFFCE46; // -12730
232: data_ff <= 24'h001D0F; // 7439
233: data_ff <= 24'hFFF013; // -4077
234: data_ff <= 24'h00080F; // 2063
235: data_ff <= 24'hFFFC51; // -943
236: data_ff <= 24'h000178; // 376
237: data_ff <= 24'hFFFF86; // -122
238: data_ff <= 24'h00001A; // 26
239: data_ff <= 24'hFFFFFE; // -2
240: data_ff <= 24'h06C5F2; // 443890
241: data_ff <= 24'hFCEA3F; // -202177
242: data_ff <= 24'h01DA7C; // 121468
243: data_ff <= 24'hFECB86; // -78970
244: data_ff <= 24'h00CC51; // 52305
245: data_ff <= 24'hFF79F1; // -34319
246: data_ff <= 24'h0055AB; // 21931
247: data_ff <= 24'hFFCB5D; // -13475
248: data_ff <= 24'h001EBB; // 7867
249: data_ff <= 24'hFFEF2B; // -4309
250: data_ff <= 24'h000883; // 2179
251: data_ff <= 24'hFFFC1C; // -996
252: data_ff <= 24'h00018D; // 397
253: data_ff <= 24'hFFFF7F; // -129
254: data_ff <= 24'h00001C; // 28
255: data_ff <= 24'hFFFFFE; // -2
256: data_ff <= 24'h073CA6; // 474278
257: data_ff <= 24'hFCB82E; // -214994
258: data_ff <= 24'h01F77A; // 128890
259: data_ff <= 24'hFEB92D; // -83667
260: data_ff <= 24'h00D834; // 55348
261: data_ff <= 24'hFF724B; // -36277
262: data_ff <= 24'h005A79; // 23161
263: data_ff <= 24'hFFC875; // -14219
264: data_ff <= 24'h002068; // 8296
265: data_ff <= 24'hFFEE43; // -4541
266: data_ff <= 24'h0008F8; // 2296
267: data_ff <= 24'hFFFBE7; // -1049
268: data_ff <= 24'h0001A2; // 418
269: data_ff <= 24'hFFFF78; // -136
270: data_ff <= 24'h00001D; // 29
271: data_ff <= 24'hFFFFFE; // -2
272: data_ff <= 24'h07B45B; // 504923
273: data_ff <= 24'hFC860E; // -227826
274: data_ff <= 24'h021471; // 136305
275: data_ff <= 24'hFEA6DB; // -88357
276: data_ff <= 24'h00E412; // 58386
277: data_ff <= 24'hFF6AA7; // -38233
278: data_ff <= 24'h005F45; // 24389
279: data_ff <= 24'hFFC58D; // -14963
280: data_ff <= 24'h002215; // 8725
281: data_ff <= 24'hFFED5A; // -4774
282: data_ff <= 24'h00096C; // 2412
283: data_ff <= 24'hFFFBB2; // -1102
284: data_ff <= 24'h0001B7; // 439
285: data_ff <= 24'hFFFF71; // -143
286: data_ff <= 24'h00001F; // 31
287: data_ff <= 24'hFFFFFE; // -2
288: data_ff <= 24'h082D0B; // 535819
289: data_ff <= 24'hFC53E4; // -240668
290: data_ff <= 24'h02315F; // 143711
291: data_ff <= 24'hFE9491; // -93039
292: data_ff <= 24'h00EFEA; // 61418
293: data_ff <= 24'hFF6308; // -40184
294: data_ff <= 24'h00640F; // 25615
295: data_ff <= 24'hFFC2A7; // -15705
296: data_ff <= 24'h0023C1; // 9153
297: data_ff <= 24'hFFEC72; // -5006
298: data_ff <= 24'h0009E1; // 2529
299: data_ff <= 24'hFFFB7D; // -1155
300: data_ff <= 24'h0001CD; // 461
301: data_ff <= 24'hFFFF6A; // -150
302: data_ff <= 24'h000021; // 33
303: data_ff <= 24'hFFFFFE; // -2
304: data_ff <= 24'h08A6B0; // 566960
305: data_ff <= 24'hFC21B5; // -253515
306: data_ff <= 24'h024E41; // 151105
307: data_ff <= 24'hFE8253; // -97709
308: data_ff <= 24'h00FBB9; // 64441
309: data_ff <= 24'hFF5B6E; // -42130
310: data_ff <= 24'h0068D7; // 26839
311: data_ff <= 24'hFFBFC1; // -16447
312: data_ff <= 24'h00256D; // 9581
313: data_ff <= 24'hFFEB8A; // -5238
314: data_ff <= 24'h000A56; // 2646
315: data_ff <= 24'hFFFB48; // -1208
316: data_ff <= 24'h0001E2; // 482
317: data_ff <= 24'hFFFF63; // -157
318: data_ff <= 24'h000022; // 34
319: data_ff <= 24'hFFFFFE; // -2
320: data_ff <= 24'h092144; // 598340
321: data_ff <= 24'hFBEF86; // -266362
322: data_ff <= 24'h026B15; // 158485
323: data_ff <= 24'hFE7021; // -102367
324: data_ff <= 24'h010780; // 67456
325: data_ff <= 24'hFF53D9; // -44071
326: data_ff <= 24'h006D9B; // 28059
327: data_ff <= 24'hFFBCDE; // -17186
328: data_ff <= 24'h002718; // 10008
329: data_ff <= 24'hFFEAA2; // -5470
330: data_ff <= 24'h000ACB; // 2763
331: data_ff <= 24'hFFFB12; // -1262
332: data_ff <= 24'h0001F8; // 504
333: data_ff <= 24'hFFFF5C; // -164
334: data_ff <= 24'h000024; // 36
335: data_ff <= 24'hFFFFFE; // -2
336: data_ff <= 24'h099CC3; // 629955
337: data_ff <= 24'hFBBD5B; // -279205
338: data_ff <= 24'h0287D7; // 165847
339: data_ff <= 24'hFE5DFE; // -107010
340: data_ff <= 24'h01133D; // 70461
341: data_ff <= 24'hFF4C4B; // -46005
342: data_ff <= 24'h00725C; // 29276
343: data_ff <= 24'hFFB9FC; // -17924
344: data_ff <= 24'h0028C2; // 10434
345: data_ff <= 24'hFFE9BA; // -5702
346: data_ff <= 24'h000B40; // 2880
347: data_ff <= 24'hFFFADD; // -1315
348: data_ff <= 24'h00020D; // 525
349: data_ff <= 24'hFFFF54; // -172
350: data_ff <= 24'h000026; // 38
351: data_ff <= 24'hFFFFFE; // -2
352: data_ff <= 24'h0A1926; // 661798
353: data_ff <= 24'hFB8B3A; // -292038
354: data_ff <= 24'h02A484; // 173188
355: data_ff <= 24'hFE4BEC; // -111636
356: data_ff <= 24'h011EEE; // 73454
357: data_ff <= 24'hFF44C4; // -47932
358: data_ff <= 24'h007718; // 30488
359: data_ff <= 24'hFFB71D; // -18659
360: data_ff <= 24'h002A6B; // 10859
361: data_ff <= 24'hFFE8D2; // -5934
362: data_ff <= 24'h000BB4; // 2996
363: data_ff <= 24'hFFFAA7; // -1369
364: data_ff <= 24'h000223; // 547
365: data_ff <= 24'hFFFF4D; // -179
366: data_ff <= 24'h000027; // 39
367: data_ff <= 24'hFFFFFD; // -3
368: data_ff <= 24'h0A9668; // 693864
369: data_ff <= 24'hFB5926; // -304858
370: data_ff <= 24'h02C11A; // 180506
371: data_ff <= 24'hFE39EB; // -116245
372: data_ff <= 24'h012A93; // 76435
373: data_ff <= 24'hFF3D44; // -49852
374: data_ff <= 24'h007BD0; // 31696
375: data_ff <= 24'hFFB440; // -19392
376: data_ff <= 24'h002C13; // 11283
377: data_ff <= 24'hFFE7EC; // -6164
378: data_ff <= 24'h000C29; // 3113
379: data_ff <= 24'hFFFA72; // -1422
380: data_ff <= 24'h000239; // 569
381: data_ff <= 24'hFFFF46; // -186
382: data_ff <= 24'h000029; // 41
383: data_ff <= 24'hFFFFFD; // -3
384: data_ff <= 24'h0B1483; // 726147
385: data_ff <= 24'hFB2725; // -317659
386: data_ff <= 24'h02DD95; // 187797
387: data_ff <= 24'hFE2800; // -120832
388: data_ff <= 24'h01362A; // 79402
389: data_ff <= 24'hFF35CE; // -51762
390: data_ff <= 24'h008082; // 32898
391: data_ff <= 24'hFFB166; // -20122
392: data_ff <= 24'h002DBA; // 11706
393: data_ff <= 24'hFFE705; // -6395
394: data_ff <= 24'h000C9D; // 3229
395: data_ff <= 24'hFFFA3C; // -1476
396: data_ff <= 24'h00024E; // 590
397: data_ff <= 24'hFFFF3E; // -194
398: data_ff <= 24'h00002B; // 43
399: data_ff <= 24'hFFFFFD; // -3
400: data_ff <= 24'h0B9370; // 758640
401: data_ff <= 24'hFAF53D; // -330435
402: data_ff <= 24'h02F9F3; // 195059
403: data_ff <= 24'hFE162A; // -125398
404: data_ff <= 24'h0141B2; // 82354
405: data_ff <= 24'hFF2E61; // -53663
406: data_ff <= 24'h00852F; // 34095
407: data_ff <= 24'hFFAE8F; // -20849
408: data_ff <= 24'h002F5F; // 12127
409: data_ff <= 24'hFFE620; // -6624
410: data_ff <= 24'h000D11; // 3345
411: data_ff <= 24'hFFFA07; // -1529
412: data_ff <= 24'h000264; // 612
413: data_ff <= 24'hFFFF37; // -201
414: data_ff <= 24'h00002D; // 45
415: data_ff <= 24'hFFFFFD; // -3
416: data_ff <= 24'h0C132B; // 791339
417: data_ff <= 24'hFAC371; // -343183
418: data_ff <= 24'h031630; // 202288
419: data_ff <= 24'hFE046C; // -129940
420: data_ff <= 24'h014D2A; // 85290
421: data_ff <= 24'hFF26FF; // -55553
422: data_ff <= 24'h0089D5; // 35285
423: data_ff <= 24'hFFABBC; // -21572
424: data_ff <= 24'h003102; // 12546
425: data_ff <= 24'hFFE53B; // -6853
426: data_ff <= 24'h000D85; // 3461
427: data_ff <= 24'hFFF9D2; // -1582
428: data_ff <= 24'h00027A; // 634
429: data_ff <= 24'hFFFF30; // -208
430: data_ff <= 24'h00002E; // 46
431: data_ff <= 24'hFFFFFD; // -3
432: data_ff <= 24'h0C93AC; // 824236
433: data_ff <= 24'hFA91C6; // -355898
434: data_ff <= 24'h03324A; // 209482
435: data_ff <= 24'hFDF2C9; // -134455
436: data_ff <= 24'h015890; // 88208
437: data_ff <= 24'hFF1FA8; // -57432
438: data_ff <= 24'h008E75; // 36469
439: data_ff <= 24'hFFA8EC; // -22292
440: data_ff <= 24'h0032A3; // 12963
441: data_ff <= 24'hFFE457; // -7081
442: data_ff <= 24'h000DF9; // 3577
443: data_ff <= 24'hFFF99C; // -1636
444: data_ff <= 24'h00028F; // 655
445: data_ff <= 24'hFFFF28; // -216
446: data_ff <= 24'h000030; // 48
447: data_ff <= 24'hFFFFFD; // -3
448: data_ff <= 24'h0D14ED; // 857325
449: data_ff <= 24'hFA6043; // -368573
450: data_ff <= 24'h034E3E; // 216638
451: data_ff <= 24'hFDE141; // -138943
452: data_ff <= 24'h0163E3; // 91107
453: data_ff <= 24'hFF185C; // -59300
454: data_ff <= 24'h00930D; // 37645
455: data_ff <= 24'hFFA621; // -23007
456: data_ff <= 24'h003442; // 13378
457: data_ff <= 24'hFFE375; // -7307
458: data_ff <= 24'h000E6C; // 3692
459: data_ff <= 24'hFFF967; // -1689
460: data_ff <= 24'h0002A5; // 677
461: data_ff <= 24'hFFFF21; // -223
462: data_ff <= 24'h000032; // 50
463: data_ff <= 24'hFFFFFC; // -4
464: data_ff <= 24'h0D96EA; // 890602
465: data_ff <= 24'hFA2EEB; // -381205
466: data_ff <= 24'h036A07; // 223751
467: data_ff <= 24'hFDCFD7; // -143401
468: data_ff <= 24'h016F22; // 93986
469: data_ff <= 24'hFF111E; // -61154
470: data_ff <= 24'h00979E; // 38814
471: data_ff <= 24'hFFA35A; // -23718
472: data_ff <= 24'h0035DE; // 13790
473: data_ff <= 24'hFFE293; // -7533
474: data_ff <= 24'h000EDE; // 3806
475: data_ff <= 24'hFFF932; // -1742
476: data_ff <= 24'h0002BB; // 699
477: data_ff <= 24'hFFFF19; // -231
478: data_ff <= 24'h000034; // 52
479: data_ff <= 24'hFFFFFC; // -4
480: data_ff <= 24'h0E199A; // 924058
481: data_ff <= 24'hF9FDC4; // -393788
482: data_ff <= 24'h0385A5; // 230821
483: data_ff <= 24'hFDBE8D; // -147827
484: data_ff <= 24'h017A4C; // 96844
485: data_ff <= 24'hFF09ED; // -62995
486: data_ff <= 24'h009C26; // 39974
487: data_ff <= 24'hFFA098; // -24424
488: data_ff <= 24'h003778; // 14200
489: data_ff <= 24'hFFE1B3; // -7757
490: data_ff <= 24'h000F51; // 3921
491: data_ff <= 24'hFFF8FD; // -1795
492: data_ff <= 24'h0002D0; // 720
493: data_ff <= 24'hFFFF12; // -238
494: data_ff <= 24'h000036; // 54
495: data_ff <= 24'hFFFFFC; // -4
496: data_ff <= 24'h0E9CF8; // 957688
497: data_ff <= 24'hF9CCD3; // -406317
498: data_ff <= 24'h03A113; // 237843
499: data_ff <= 24'hFDAD65; // -152219
500: data_ff <= 24'h018560; // 99680
501: data_ff <= 24'hFF02CB; // -64821
502: data_ff <= 24'h00A0A6; // 41126
503: data_ff <= 24'hFF9DDB; // -25125
504: data_ff <= 24'h003910; // 14608
505: data_ff <= 24'hFFE0D3; // -7981
506: data_ff <= 24'h000FC2; // 4034
507: data_ff <= 24'hFFF8C9; // -1847
508: data_ff <= 24'h0002E6; // 742
509: data_ff <= 24'hFFFF0B; // -245
510: data_ff <= 24'h000038; // 56
511: data_ff <= 24'hFFFFFC; // -4
512: data_ff <= 24'h0F20FD; // 991485
513: data_ff <= 24'hF99C1C; // -418788
514: data_ff <= 24'h03BC4F; // 244815
515: data_ff <= 24'hFD9C60; // -156576
516: data_ff <= 24'h01905C; // 102492
517: data_ff <= 24'hFEFBB8; // -66632
518: data_ff <= 24'h00A51C; // 42268
519: data_ff <= 24'hFF9B23; // -25821
520: data_ff <= 24'h003AA4; // 15012
521: data_ff <= 24'hFFDFF6; // -8202
522: data_ff <= 24'h001033; // 4147
523: data_ff <= 24'hFFF894; // -1900
524: data_ff <= 24'h0002FB; // 763
525: data_ff <= 24'hFFFF03; // -253
526: data_ff <= 24'h00003A; // 58
527: data_ff <= 24'hFFFFFC; // -4
528: data_ff <= 24'h0FA5A3; // 1025443
529: data_ff <= 24'hF96BA6; // -431194
530: data_ff <= 24'h03D755; // 251733
531: data_ff <= 24'hFD8B80; // -160896
532: data_ff <= 24'h019B3E; // 105278
533: data_ff <= 24'hFEF4B5; // -68427
534: data_ff <= 24'h00A988; // 43400
535: data_ff <= 24'hFF9871; // -26511
536: data_ff <= 24'h003C36; // 15414
537: data_ff <= 24'hFFDF19; // -8423
538: data_ff <= 24'h0010A3; // 4259
539: data_ff <= 24'hFFF860; // -1952
540: data_ff <= 24'h000311; // 785
541: data_ff <= 24'hFFFEFC; // -260
542: data_ff <= 24'h00003C; // 60
543: data_ff <= 24'hFFFFFC; // -4
544: data_ff <= 24'h102AE3; // 1059555
545: data_ff <= 24'hF93B75; // -443531
546: data_ff <= 24'h03F223; // 258595
547: data_ff <= 24'hFD7AC8; // -165176
548: data_ff <= 24'h01A607; // 108039
549: data_ff <= 24'hFEEDC3; // -70205
550: data_ff <= 24'h00ADEA; // 44522
551: data_ff <= 24'hFF95C5; // -27195
552: data_ff <= 24'h003DC4; // 15812
553: data_ff <= 24'hFFDE3F; // -8641
554: data_ff <= 24'h001113; // 4371
555: data_ff <= 24'hFFF82C; // -2004
556: data_ff <= 24'h000326; // 806
557: data_ff <= 24'hFFFEF4; // -268
558: data_ff <= 24'h00003D; // 61
559: data_ff <= 24'hFFFFFB; // -5
560: data_ff <= 24'h10B0B6; // 1093814
561: data_ff <= 24'hF90B8D; // -455795
562: data_ff <= 24'h040CB6; // 265398
563: data_ff <= 24'hFD6A38; // -169416
564: data_ff <= 24'h01B0B4; // 110772
565: data_ff <= 24'hFEE6E2; // -71966
566: data_ff <= 24'h00B241; // 45633
567: data_ff <= 24'hFF931F; // -27873
568: data_ff <= 24'h003F4F; // 16207
569: data_ff <= 24'hFFDD66; // -8858
570: data_ff <= 24'h001182; // 4482
571: data_ff <= 24'hFFF7F8; // -2056
572: data_ff <= 24'h00033C; // 828
573: data_ff <= 24'hFFFEED; // -275
574: data_ff <= 24'h00003F; // 63
575: data_ff <= 24'hFFFFFB; // -5
576: data_ff <= 24'h113717; // 1128215
577: data_ff <= 24'hF8DBF6; // -467978
578: data_ff <= 24'h04270A; // 272138
579: data_ff <= 24'hFD59D4; // -173612
580: data_ff <= 24'h01BB45; // 113477
581: data_ff <= 24'hFEE014; // -73708
582: data_ff <= 24'h00B68D; // 46733
583: data_ff <= 24'hFF9080; // -28544
584: data_ff <= 24'h0040D6; // 16598
585: data_ff <= 24'hFFDC8F; // -9073
586: data_ff <= 24'h0011F0; // 4592
587: data_ff <= 24'hFFF7C5; // -2107
588: data_ff <= 24'h000351; // 849
589: data_ff <= 24'hFFFEE5; // -283
590: data_ff <= 24'h000041; // 65
591: data_ff <= 24'hFFFFFB; // -5
592: data_ff <= 24'h11BDFE; // 1162750
593: data_ff <= 24'hF8ACB2; // -480078
594: data_ff <= 24'h04411D; // 278813
595: data_ff <= 24'hFD499D; // -177763
596: data_ff <= 24'h01C5B7; // 116151
597: data_ff <= 24'hFED959; // -75431
598: data_ff <= 24'h00BACD; // 47821
599: data_ff <= 24'hFF8DE8; // -29208
600: data_ff <= 24'h004259; // 16985
601: data_ff <= 24'hFFDBBA; // -9286
602: data_ff <= 24'h00125D; // 4701
603: data_ff <= 24'hFFF792; // -2158
604: data_ff <= 24'h000366; // 870
605: data_ff <= 24'hFFFEDE; // -290
606: data_ff <= 24'h000043; // 67
607: data_ff <= 24'hFFFFFB; // -5
608: data_ff <= 24'h124563; // 1197411
609: data_ff <= 24'hF87DC8; // -492088
610: data_ff <= 24'h045AEC; // 285420
611: data_ff <= 24'hFD3995; // -181867
612: data_ff <= 24'h01D00B; // 118795
613: data_ff <= 24'hFED2B2; // -77134
614: data_ff <= 24'h00BF01; // 48897
615: data_ff <= 24'hFF8B57; // -29865
616: data_ff <= 24'h0043D8; // 17368
617: data_ff <= 24'hFFDAE7; // -9497
618: data_ff <= 24'h0012C9; // 4809
619: data_ff <= 24'hFFF75F; // -2209
620: data_ff <= 24'h00037B; // 891
621: data_ff <= 24'hFFFED7; // -297
622: data_ff <= 24'h000045; // 69
623: data_ff <= 24'hFFFFFB; // -5
624: data_ff <= 24'h12CD42; // 1232194
625: data_ff <= 24'hF84F3D; // -504003
626: data_ff <= 24'h047474; // 291956
627: data_ff <= 24'hFD29BD; // -185923
628: data_ff <= 24'h01DA3E; // 121406
629: data_ff <= 24'hFECC20; // -78816
630: data_ff <= 24'h00C327; // 49959
631: data_ff <= 24'hFF88CE; // -30514
632: data_ff <= 24'h004553; // 17747
633: data_ff <= 24'hFFDA16; // -9706
634: data_ff <= 24'h001334; // 4916
635: data_ff <= 24'hFFF72D; // -2259
636: data_ff <= 24'h000390; // 912
637: data_ff <= 24'hFFFECF; // -305
638: data_ff <= 24'h000047; // 71
639: data_ff <= 24'hFFFFFA; // -6
640: data_ff <= 24'h135592; // 1267090
641: data_ff <= 24'hF82116; // -515818
642: data_ff <= 24'h048DB1; // 298417
643: data_ff <= 24'hFD1A17; // -189929
644: data_ff <= 24'h01E450; // 123984
645: data_ff <= 24'hFEC5A3; // -80477
646: data_ff <= 24'h00C741; // 51009
647: data_ff <= 24'hFF864D; // -31155
648: data_ff <= 24'h0046CA; // 18122
649: data_ff <= 24'hFFD947; // -9913
650: data_ff <= 24'h00139E; // 5022
651: data_ff <= 24'hFFF6FB; // -2309
652: data_ff <= 24'h0003A5; // 933
653: data_ff <= 24'hFFFEC8; // -312
654: data_ff <= 24'h000049; // 73
655: data_ff <= 24'hFFFFFA; // -6
656: data_ff <= 24'h13DE4C; // 1302092
657: data_ff <= 24'hF7F358; // -527528
658: data_ff <= 24'h04A6A2; // 304802
659: data_ff <= 24'hFD0AA6; // -193882
660: data_ff <= 24'h01EE3F; // 126527
661: data_ff <= 24'hFEBF3D; // -82115
662: data_ff <= 24'h00CB4C; // 52044
663: data_ff <= 24'hFF83D3; // -31789
664: data_ff <= 24'h00483C; // 18492
665: data_ff <= 24'hFFD87B; // -10117
666: data_ff <= 24'h001408; // 5128
667: data_ff <= 24'hFFF6CA; // -2358
668: data_ff <= 24'h0003B9; // 953
669: data_ff <= 24'hFFFEC1; // -319
670: data_ff <= 24'h00004B; // 75
671: data_ff <= 24'hFFFFFA; // -6
672: data_ff <= 24'h14676A; // 1337194
673: data_ff <= 24'hF7C608; // -539128
674: data_ff <= 24'h04BF42; // 311106
675: data_ff <= 24'hFCFB6C; // -197780
676: data_ff <= 24'h01F80A; // 129034
677: data_ff <= 24'hFEB8EE; // -83730
678: data_ff <= 24'h00CF49; // 53065
679: data_ff <= 24'hFF8163; // -32413
680: data_ff <= 24'h0049AA; // 18858
681: data_ff <= 24'hFFD7B1; // -10319
682: data_ff <= 24'h00146F; // 5231
683: data_ff <= 24'hFFF699; // -2407
684: data_ff <= 24'h0003CE; // 974
685: data_ff <= 24'hFFFEB9; // -327
686: data_ff <= 24'h00004D; // 77
687: data_ff <= 24'hFFFFFA; // -6
688: data_ff <= 24'h14F0E4; // 1372388
689: data_ff <= 24'hF7992C; // -550612
690: data_ff <= 24'h04D78F; // 317327
691: data_ff <= 24'hFCEC69; // -201623
692: data_ff <= 24'h0201B0; // 131504
693: data_ff <= 24'hFEB2B7; // -85321
694: data_ff <= 24'h00D337; // 54071
695: data_ff <= 24'hFF7EFB; // -33029
696: data_ff <= 24'h004B12; // 19218
697: data_ff <= 24'hFFD6E9; // -10519
698: data_ff <= 24'h0014D6; // 5334
699: data_ff <= 24'hFFF669; // -2455
700: data_ff <= 24'h0003E2; // 994
701: data_ff <= 24'hFFFEB2; // -334
702: data_ff <= 24'h00004F; // 79
703: data_ff <= 24'hFFFFFA; // -6
704: data_ff <= 24'h157AB4; // 1407668
705: data_ff <= 24'hF76CC8; // -561976
706: data_ff <= 24'h04EF87; // 323463
707: data_ff <= 24'hFCDDA0; // -205408
708: data_ff <= 24'h020B30; // 133936
709: data_ff <= 24'hFEAC98; // -86888
710: data_ff <= 24'h00D716; // 55062
711: data_ff <= 24'hFF7C9C; // -33636
712: data_ff <= 24'h004C75; // 19573
713: data_ff <= 24'hFFD624; // -10716
714: data_ff <= 24'h00153C; // 5436
715: data_ff <= 24'hFFF639; // -2503
716: data_ff <= 24'h0003F6; // 1014
717: data_ff <= 24'hFFFEAB; // -341
718: data_ff <= 24'h000051; // 81
719: data_ff <= 24'hFFFFF9; // -7
720: data_ff <= 24'h1604D2; // 1443026
721: data_ff <= 24'hF740E2; // -573214
722: data_ff <= 24'h050726; // 329510
723: data_ff <= 24'hFCCF12; // -209134
724: data_ff <= 24'h021488; // 136328
725: data_ff <= 24'hFEA693; // -88429
726: data_ff <= 24'h00DAE5; // 56037
727: data_ff <= 24'hFF7A47; // -34233
728: data_ff <= 24'h004DD4; // 19924
729: data_ff <= 24'hFFD562; // -10910
730: data_ff <= 24'h0015A0; // 5536
731: data_ff <= 24'hFFF609; // -2551
732: data_ff <= 24'h00040A; // 1034
733: data_ff <= 24'hFFFEA4; // -348
734: data_ff <= 24'h000053; // 83
735: data_ff <= 24'hFFFFF9; // -7
736: data_ff <= 24'h168F37; // 1478455
737: data_ff <= 24'hF7157F; // -584321
738: data_ff <= 24'h051E69; // 335465
739: data_ff <= 24'hFCC0C2; // -212798
740: data_ff <= 24'h021DB8; // 138680
741: data_ff <= 24'hFEA0A8; // -89944
742: data_ff <= 24'h00DEA4; // 56996
743: data_ff <= 24'hFF77FB; // -34821
744: data_ff <= 24'h004F2C; // 20268
745: data_ff <= 24'hFFD4A3; // -11101
746: data_ff <= 24'h001603; // 5635
747: data_ff <= 24'hFFF5DB; // -2597
748: data_ff <= 24'h00041E; // 1054
749: data_ff <= 24'hFFFE9D; // -355
750: data_ff <= 24'h000055; // 85
751: data_ff <= 24'hFFFFF9; // -7
752: data_ff <= 24'h1719DB; // 1513947
753: data_ff <= 24'hF6EAA4; // -595292
754: data_ff <= 24'h05354E; // 341326
755: data_ff <= 24'hFCB2B1; // -216399
756: data_ff <= 24'h0226BF; // 140991
757: data_ff <= 24'hFE9AD8; // -91432
758: data_ff <= 24'h00E252; // 57938
759: data_ff <= 24'hFF75B9; // -35399
760: data_ff <= 24'h00507F; // 20607
761: data_ff <= 24'hFFD3E7; // -11289
762: data_ff <= 24'h001664; // 5732
763: data_ff <= 24'hFFF5AC; // -2644
764: data_ff <= 24'h000432; // 1074
765: data_ff <= 24'hFFFE95; // -363
766: data_ff <= 24'h000057; // 87
767: data_ff <= 24'hFFFFF9; // -7
768: data_ff <= 24'h17A4B8; // 1549496
769: data_ff <= 24'hF6C057; // -606121
770: data_ff <= 24'h054BD2; // 347090
771: data_ff <= 24'hFCA4E1; // -219935
772: data_ff <= 24'h022F9A; // 143258
773: data_ff <= 24'hFE9524; // -92892
774: data_ff <= 24'h00E5EF; // 58863
775: data_ff <= 24'hFF7382; // -35966
776: data_ff <= 24'h0051CD; // 20941
777: data_ff <= 24'hFFD32E; // -11474
778: data_ff <= 24'h0016C4; // 5828
779: data_ff <= 24'hFFF57F; // -2689
780: data_ff <= 24'h000445; // 1093
781: data_ff <= 24'hFFFE8E; // -370
782: data_ff <= 24'h000059; // 89
783: data_ff <= 24'hFFFFF8; // -8
784: data_ff <= 24'h182FC6; // 1585094
785: data_ff <= 24'hF6969C; // -616804
786: data_ff <= 24'h0561F2; // 352754
787: data_ff <= 24'hFC9753; // -223405
788: data_ff <= 24'h02384A; // 145482
789: data_ff <= 24'hFE8F8C; // -94324
790: data_ff <= 24'h00E97A; // 59770
791: data_ff <= 24'hFF7155; // -36523
792: data_ff <= 24'h005314; // 21268
793: data_ff <= 24'hFFD278; // -11656
794: data_ff <= 24'h001723; // 5923
795: data_ff <= 24'hFFF552; // -2734
796: data_ff <= 24'h000458; // 1112
797: data_ff <= 24'hFFFE88; // -376
798: data_ff <= 24'h00005B; // 91
799: data_ff <= 24'hFFFFF8; // -8
800: data_ff <= 24'h18BAFE; // 1620734
801: data_ff <= 24'hF66D78; // -627336
802: data_ff <= 24'h0577AB; // 358315
803: data_ff <= 24'hFC8A09; // -226807
804: data_ff <= 24'h0240CC; // 147660
805: data_ff <= 24'hFE8A11; // -95727
806: data_ff <= 24'h00ECF2; // 60658
807: data_ff <= 24'hFF6F33; // -37069
808: data_ff <= 24'h005455; // 21589
809: data_ff <= 24'hFFD1C5; // -11835
810: data_ff <= 24'h001780; // 6016
811: data_ff <= 24'hFFF526; // -2778
812: data_ff <= 24'h00046B; // 1131
813: data_ff <= 24'hFFFE81; // -383
814: data_ff <= 24'h00005D; // 93
815: data_ff <= 24'hFFFFF8; // -8
816: data_ff <= 24'h194658; // 1656408
817: data_ff <= 24'hF644F2; // -637710
818: data_ff <= 24'h058CFA; // 363770
819: data_ff <= 24'hFC7D06; // -230138
820: data_ff <= 24'h024920; // 149792
821: data_ff <= 24'hFE84B4; // -97100
822: data_ff <= 24'h00F059; // 61529
823: data_ff <= 24'hFF6D1D; // -37603
824: data_ff <= 24'h005590; // 21904
825: data_ff <= 24'hFFD116; // -12010
826: data_ff <= 24'h0017DB; // 6107
827: data_ff <= 24'hFFF4FA; // -2822
828: data_ff <= 24'h00047E; // 1150
829: data_ff <= 24'hFFFE7A; // -390
830: data_ff <= 24'h00005F; // 95
831: data_ff <= 24'hFFFFF8; // -8
832: data_ff <= 24'h19D1CD; // 1692109
833: data_ff <= 24'hF61D0D; // -647923
834: data_ff <= 24'h05A1DD; // 369117
835: data_ff <= 24'hFC704A; // -233398
836: data_ff <= 24'h025146; // 151878
837: data_ff <= 24'hFE7F75; // -98443
838: data_ff <= 24'h00F3AB; // 62379
839: data_ff <= 24'hFF6B12; // -38126
840: data_ff <= 24'h0056C4; // 22212
841: data_ff <= 24'hFFD06A; // -12182
842: data_ff <= 24'h001835; // 6197
843: data_ff <= 24'hFFF4CF; // -2865
844: data_ff <= 24'h000490; // 1168
845: data_ff <= 24'hFFFE73; // -397
846: data_ff <= 24'h000060; // 96
847: data_ff <= 24'hFFFFF7; // -9
848: data_ff <= 24'h1A5D56; // 1727830
849: data_ff <= 24'hF5F5CF; // -657969
850: data_ff <= 24'h05B650; // 374352
851: data_ff <= 24'hFC63D8; // -236584
852: data_ff <= 24'h02593A; // 153914
853: data_ff <= 24'hFE7A56; // -99754
854: data_ff <= 24'h00F6EB; // 63211
855: data_ff <= 24'hFF6912; // -38638
856: data_ff <= 24'h0057F2; // 22514
857: data_ff <= 24'hFFCFC1; // -12351
858: data_ff <= 24'h00188C; // 6284
859: data_ff <= 24'hFFF4A5; // -2907
860: data_ff <= 24'h0004A2; // 1186
861: data_ff <= 24'hFFFE6D; // -403
862: data_ff <= 24'h000062; // 98
863: data_ff <= 24'hFFFFF7; // -9
864: data_ff <= 24'h1AE8EA; // 1763562
865: data_ff <= 24'hF5CF3D; // -667843
866: data_ff <= 24'h05CA52; // 379474
867: data_ff <= 24'hFC57B1; // -239695
868: data_ff <= 24'h0260FE; // 155902
869: data_ff <= 24'hFE7557; // -101033
870: data_ff <= 24'h00FA16; // 64022
871: data_ff <= 24'hFF671F; // -39137
872: data_ff <= 24'h005918; // 22808
873: data_ff <= 24'hFFCF1C; // -12516
874: data_ff <= 24'h0018E3; // 6371
875: data_ff <= 24'hFFF47C; // -2948
876: data_ff <= 24'h0004B4; // 1204
877: data_ff <= 24'hFFFE66; // -410
878: data_ff <= 24'h000064; // 100
879: data_ff <= 24'hFFFFF7; // -9
880: data_ff <= 24'h1B7484; // 1799300
881: data_ff <= 24'hF5A95D; // -677539
882: data_ff <= 24'h05DDE0; // 384480
883: data_ff <= 24'hFC4BD6; // -242730
884: data_ff <= 24'h02688F; // 157839
885: data_ff <= 24'hFE7078; // -102280
886: data_ff <= 24'h00FD2D; // 64813
887: data_ff <= 24'hFF6538; // -39624
888: data_ff <= 24'h005A38; // 23096
889: data_ff <= 24'hFFCE7B; // -12677
890: data_ff <= 24'h001937; // 6455
891: data_ff <= 24'hFFF453; // -2989
892: data_ff <= 24'h0004C5; // 1221
893: data_ff <= 24'hFFFE5F; // -417
894: data_ff <= 24'h000066; // 102
895: data_ff <= 24'hFFFFF7; // -9
896: data_ff <= 24'h1C001A; // 1835034
897: data_ff <= 24'hF58433; // -687053
898: data_ff <= 24'h05F0F6; // 389366
899: data_ff <= 24'hFC404A; // -245686
900: data_ff <= 24'h026FED; // 159725
901: data_ff <= 24'hFE6BBA; // -103494
902: data_ff <= 24'h01002F; // 65583
903: data_ff <= 24'hFF635D; // -40099
904: data_ff <= 24'h005B51; // 23377
905: data_ff <= 24'hFFCDDE; // -12834
906: data_ff <= 24'h001989; // 6537
907: data_ff <= 24'hFFF42B; // -3029
908: data_ff <= 24'h0004D6; // 1238
909: data_ff <= 24'hFFFE59; // -423
910: data_ff <= 24'h000068; // 104
911: data_ff <= 24'hFFFFF6; // -10
912: data_ff <= 24'h1C8BA5; // 1870757
913: data_ff <= 24'hF55FC3; // -696381
914: data_ff <= 24'h060393; // 394131
915: data_ff <= 24'hFC350D; // -248563
916: data_ff <= 24'h027716; // 161558
917: data_ff <= 24'hFE671F; // -104673
918: data_ff <= 24'h01031C; // 66332
919: data_ff <= 24'hFF618F; // -40561
920: data_ff <= 24'h005C62; // 23650
921: data_ff <= 24'hFFCD45; // -12987
922: data_ff <= 24'h0019DA; // 6618
923: data_ff <= 24'hFFF405; // -3067
924: data_ff <= 24'h0004E7; // 1255
925: data_ff <= 24'hFFFE53; // -429
926: data_ff <= 24'h00006A; // 106
927: data_ff <= 24'hFFFFF6; // -10
928: data_ff <= 24'h1D171E; // 1906462
929: data_ff <= 24'hF53C14; // -705516
930: data_ff <= 24'h0615B3; // 398771
931: data_ff <= 24'hFC2A22; // -251358
932: data_ff <= 24'h027E0A; // 163338
933: data_ff <= 24'hFE62A6; // -105818
934: data_ff <= 24'h0105F3; // 67059
935: data_ff <= 24'hFF5FCF; // -41009
936: data_ff <= 24'h005D6B; // 23915
937: data_ff <= 24'hFFCCB0; // -13136
938: data_ff <= 24'h001A28; // 6696
939: data_ff <= 24'hFFF3DF; // -3105
940: data_ff <= 24'h0004F8; // 1272
941: data_ff <= 24'hFFFE4D; // -435
942: data_ff <= 24'h00006C; // 108
943: data_ff <= 24'hFFFFF6; // -10
944: data_ff <= 24'h1DA27E; // 1942142
945: data_ff <= 24'hF5192B; // -714453
946: data_ff <= 24'h062755; // 403285
947: data_ff <= 24'hFC1F89; // -254071
948: data_ff <= 24'h0284C7; // 165063
949: data_ff <= 24'hFE5E50; // -106928
950: data_ff <= 24'h0108B4; // 67764
951: data_ff <= 24'hFF5E1C; // -41444
952: data_ff <= 24'h005E6D; // 24173
953: data_ff <= 24'hFFCC1F; // -13281
954: data_ff <= 24'h001A75; // 6773
955: data_ff <= 24'hFFF3BA; // -3142
956: data_ff <= 24'h000508; // 1288
957: data_ff <= 24'hFFFE47; // -441
958: data_ff <= 24'h00006E; // 110
959: data_ff <= 24'hFFFFF5; // -11
960: data_ff <= 24'h1E2DBC; // 1977788
961: data_ff <= 24'hF4F70B; // -723189
962: data_ff <= 24'h063875; // 407669
963: data_ff <= 24'hFC1545; // -256699
964: data_ff <= 24'h028B4D; // 166733
965: data_ff <= 24'hFE5A1E; // -108002
966: data_ff <= 24'h010B5E; // 68446
967: data_ff <= 24'hFF5C76; // -41866
968: data_ff <= 24'h005F68; // 24424
969: data_ff <= 24'hFFCB92; // -13422
970: data_ff <= 24'h001ABF; // 6847
971: data_ff <= 24'hFFF395; // -3179
972: data_ff <= 24'h000518; // 1304
973: data_ff <= 24'hFFFE41; // -447
974: data_ff <= 24'h00006F; // 111
975: data_ff <= 24'hFFFFF5; // -11
976: data_ff <= 24'h1EB8D2; // 2013394
977: data_ff <= 24'hF4D5BB; // -731717
978: data_ff <= 24'h064911; // 411921
979: data_ff <= 24'hFC0B57; // -259241
980: data_ff <= 24'h02919A; // 168346
981: data_ff <= 24'hFE5611; // -109039
982: data_ff <= 24'h010DF1; // 69105
983: data_ff <= 24'hFF5ADF; // -42273
984: data_ff <= 24'h00605A; // 24666
985: data_ff <= 24'hFFCB09; // -13559
986: data_ff <= 24'h001B07; // 6919
987: data_ff <= 24'hFFF372; // -3214
988: data_ff <= 24'h000527; // 1319
989: data_ff <= 24'hFFFE3B; // -453
990: data_ff <= 24'h000071; // 113
991: data_ff <= 24'hFFFFF5; // -11
992: data_ff <= 24'h1F43B6; // 2048950
993: data_ff <= 24'hF4B53F; // -740033
994: data_ff <= 24'h065927; // 416039
995: data_ff <= 24'hFC01C1; // -261695
996: data_ff <= 24'h0297AE; // 169902
997: data_ff <= 24'hFE5229; // -110039
998: data_ff <= 24'h01106D; // 69741
999: data_ff <= 24'hFF5955; // -42667
1000: data_ff <= 24'h006144; // 24900
1001: data_ff <= 24'hFFCA85; // -13691
1002: data_ff <= 24'h001B4D; // 6989
1003: data_ff <= 24'hFFF350; // -3248
1004: data_ff <= 24'h000536; // 1334
1005: data_ff <= 24'hFFFE35; // -459
1006: data_ff <= 24'h000073; // 115
1007: data_ff <= 24'hFFFFF5; // -11
1008: data_ff <= 24'h1FCE63; // 2084451
1009: data_ff <= 24'hF4959B; // -748133
1010: data_ff <= 24'h0668B5; // 420021
1011: data_ff <= 24'hFBF883; // -264061
1012: data_ff <= 24'h029D88; // 171400
1013: data_ff <= 24'hFE4E66; // -111002
1014: data_ff <= 24'h0112D1; // 70353
1015: data_ff <= 24'hFF57DA; // -43046
1016: data_ff <= 24'h006225; // 25125
1017: data_ff <= 24'hFFCA05; // -13819
1018: data_ff <= 24'h001B91; // 7057
1019: data_ff <= 24'hFFF32F; // -3281
1020: data_ff <= 24'h000545; // 1349
1021: data_ff <= 24'hFFFE2F; // -465
1022: data_ff <= 24'h000075; // 117
1023: data_ff <= 24'hFFFFF4; // -12
1024: data_ff <= 24'h2058CF; // 2119887
1025: data_ff <= 24'hF476D5; // -756011
1026: data_ff <= 24'h0677B7; // 423863
1027: data_ff <= 24'hFBEF9F; // -266337
1028: data_ff <= 24'h02A327; // 172839
1029: data_ff <= 24'hFE4ACA; // -111926
1030: data_ff <= 24'h01151D; // 70941
1031: data_ff <= 24'hFF566E; // -43410
1032: data_ff <= 24'h0062FF; // 25343
1033: data_ff <= 24'hFFC98A; // -13942
1034: data_ff <= 24'h001BD3; // 7123
1035: data_ff <= 24'hFFF30F; // -3313
1036: data_ff <= 24'h000553; // 1363
1037: data_ff <= 24'hFFFE2A; // -470
1038: data_ff <= 24'h000076; // 118
1039: data_ff <= 24'hFFFFF4; // -12
1040: data_ff <= 24'h20E2F4; // 2155252
1041: data_ff <= 24'hF458F2; // -763662
1042: data_ff <= 24'h06862B; // 427563
1043: data_ff <= 24'hFBE717; // -268521
1044: data_ff <= 24'h02A88A; // 174218
1045: data_ff <= 24'hFE4755; // -112811
1046: data_ff <= 24'h011750; // 71504
1047: data_ff <= 24'hFF5510; // -43760
1048: data_ff <= 24'h0063CF; // 25551
1049: data_ff <= 24'hFFC913; // -14061
1050: data_ff <= 24'h001C12; // 7186
1051: data_ff <= 24'hFFF2EF; // -3345
1052: data_ff <= 24'h000561; // 1377
1053: data_ff <= 24'hFFFE25; // -475
1054: data_ff <= 24'h000078; // 120
1055: data_ff <= 24'hFFFFF4; // -12
1056: data_ff <= 24'h216CCA; // 2190538
1057: data_ff <= 24'hF43BF6; // -771082
1058: data_ff <= 24'h069410; // 431120
1059: data_ff <= 24'hFBDEEC; // -270612
1060: data_ff <= 24'h02ADB0; // 175536
1061: data_ff <= 24'hFE4407; // -113657
1062: data_ff <= 24'h01196A; // 72042
1063: data_ff <= 24'hFF53C2; // -44094
1064: data_ff <= 24'h006497; // 25751
1065: data_ff <= 24'hFFC8A1; // -14175
1066: data_ff <= 24'h001C4F; // 7247
1067: data_ff <= 24'hFFF2D1; // -3375
1068: data_ff <= 24'h00056E; // 1390
1069: data_ff <= 24'hFFFE1F; // -481
1070: data_ff <= 24'h00007A; // 122
1071: data_ff <= 24'hFFFFF3; // -13
1072: data_ff <= 24'h21F649; // 2225737
1073: data_ff <= 24'hF41FE7; // -778265
1074: data_ff <= 24'h06A163; // 434531
1075: data_ff <= 24'hFBD71F; // -272609
1076: data_ff <= 24'h02B298; // 176792
1077: data_ff <= 24'hFE40E1; // -114463
1078: data_ff <= 24'h011B6C; // 72556
1079: data_ff <= 24'hFF5283; // -44413
1080: data_ff <= 24'h006556; // 25942
1081: data_ff <= 24'hFFC834; // -14284
1082: data_ff <= 24'h001C89; // 7305
1083: data_ff <= 24'hFFF2B4; // -3404
1084: data_ff <= 24'h00057B; // 1403
1085: data_ff <= 24'hFFFE1A; // -486
1086: data_ff <= 24'h00007B; // 123
1087: data_ff <= 24'hFFFFF3; // -13
1088: data_ff <= 24'h227F69; // 2260841
1089: data_ff <= 24'hF404C8; // -785208
1090: data_ff <= 24'h06AE22; // 437794
1091: data_ff <= 24'hFBCFB2; // -274510
1092: data_ff <= 24'h02B742; // 177986
1093: data_ff <= 24'hFE3DE4; // -115228
1094: data_ff <= 24'h011D53; // 73043
1095: data_ff <= 24'hFF5154; // -44716
1096: data_ff <= 24'h00660D; // 26125
1097: data_ff <= 24'hFFC7CC; // -14388
1098: data_ff <= 24'h001CC1; // 7361
1099: data_ff <= 24'hFFF299; // -3431
1100: data_ff <= 24'h000588; // 1416
1101: data_ff <= 24'hFFFE15; // -491
1102: data_ff <= 24'h00007D; // 125
1103: data_ff <= 24'hFFFFF3; // -13
1104: data_ff <= 24'h230824; // 2295844
1105: data_ff <= 24'hF3EA9E; // -791906
1106: data_ff <= 24'h06BA4A; // 440906
1107: data_ff <= 24'hFBC8A6; // -276314
1108: data_ff <= 24'h02BBAC; // 179116
1109: data_ff <= 24'hFE3B10; // -115952
1110: data_ff <= 24'h011F21; // 73505
1111: data_ff <= 24'hFF5034; // -45004
1112: data_ff <= 24'h0066B9; // 26297
1113: data_ff <= 24'hFFC769; // -14487
1114: data_ff <= 24'h001CF7; // 7415
1115: data_ff <= 24'hFFF27E; // -3458
1116: data_ff <= 24'h000594; // 1428
1117: data_ff <= 24'hFFFE10; // -496
1118: data_ff <= 24'h00007E; // 126
1119: data_ff <= 24'hFFFFF3; // -13
1120: data_ff <= 24'h239070; // 2330736
1121: data_ff <= 24'hF3D16E; // -798354
1122: data_ff <= 24'h06C5D9; // 443865
1123: data_ff <= 24'hFBC1FC; // -278020
1124: data_ff <= 24'h02BFD7; // 180183
1125: data_ff <= 24'hFE3865; // -116635
1126: data_ff <= 24'h0120D4; // 73940
1127: data_ff <= 24'hFF4F25; // -45275
1128: data_ff <= 24'h00675D; // 26461
1129: data_ff <= 24'hFFC70B; // -14581
1130: data_ff <= 24'h001D29; // 7465
1131: data_ff <= 24'hFFF264; // -3484
1132: data_ff <= 24'h00059F; // 1439
1133: data_ff <= 24'hFFFE0C; // -500
1134: data_ff <= 24'h000080; // 128
1135: data_ff <= 24'hFFFFF2; // -14
1136: data_ff <= 24'h241847; // 2365511
1137: data_ff <= 24'hF3B93D; // -804547
1138: data_ff <= 24'h06D0CE; // 446670
1139: data_ff <= 24'hFBBBB5; // -279627
1140: data_ff <= 24'h02C3C0; // 181184
1141: data_ff <= 24'hFE35E4; // -117276
1142: data_ff <= 24'h01226D; // 74349
1143: data_ff <= 24'hFF4E25; // -45531
1144: data_ff <= 24'h0067F7; // 26615
1145: data_ff <= 24'hFFC6B2; // -14670
1146: data_ff <= 24'h001D5A; // 7514
1147: data_ff <= 24'hFFF24C; // -3508
1148: data_ff <= 24'h0005AB; // 1451
1149: data_ff <= 24'hFFFE07; // -505
1150: data_ff <= 24'h000081; // 129
1151: data_ff <= 24'hFFFFF2; // -14
1152: data_ff <= 24'h249FA1; // 2400161
1153: data_ff <= 24'hF3A20F; // -810481
1154: data_ff <= 24'h06DB26; // 449318
1155: data_ff <= 24'hFBB5D2; // -281134
1156: data_ff <= 24'h02C767; // 182119
1157: data_ff <= 24'hFE338E; // -117874
1158: data_ff <= 24'h0123EA; // 74730
1159: data_ff <= 24'hFF4D36; // -45770
1160: data_ff <= 24'h006888; // 26760
1161: data_ff <= 24'hFFC65F; // -14753
1162: data_ff <= 24'h001D87; // 7559
1163: data_ff <= 24'hFFF235; // -3531
1164: data_ff <= 24'h0005B5; // 1461
1165: data_ff <= 24'hFFFE03; // -509
1166: data_ff <= 24'h000083; // 131
1167: data_ff <= 24'hFFFFF2; // -14
1168: data_ff <= 24'h252676; // 2434678
1169: data_ff <= 24'hF38BE8; // -816152
1170: data_ff <= 24'h06E4DF; // 451807
1171: data_ff <= 24'hFBB056; // -282538
1172: data_ff <= 24'h02CACD; // 182989
1173: data_ff <= 24'hFE3163; // -118429
1174: data_ff <= 24'h01254D; // 75085
1175: data_ff <= 24'hFF4C58; // -45992
1176: data_ff <= 24'h00690F; // 26895
1177: data_ff <= 24'hFFC610; // -14832
1178: data_ff <= 24'h001DB2; // 7602
1179: data_ff <= 24'hFFF21F; // -3553
1180: data_ff <= 24'h0005BF; // 1471
1181: data_ff <= 24'hFFFDFF; // -513
1182: data_ff <= 24'h000084; // 132
1183: data_ff <= 24'hFFFFF1; // -15
1184: data_ff <= 24'h25ACBF; // 2469055
1185: data_ff <= 24'hF376CE; // -821554
1186: data_ff <= 24'h06EDF8; // 454136
1187: data_ff <= 24'hFBAB40; // -283840
1188: data_ff <= 24'h02CDEF; // 183791
1189: data_ff <= 24'hFE2F64; // -118940
1190: data_ff <= 24'h012694; // 75412
1191: data_ff <= 24'hFF4B8B; // -46197
1192: data_ff <= 24'h00698C; // 27020
1193: data_ff <= 24'hFFC5C7; // -14905
1194: data_ff <= 24'h001DDB; // 7643
1195: data_ff <= 24'hFFF20A; // -3574
1196: data_ff <= 24'h0005C9; // 1481
1197: data_ff <= 24'hFFFDFB; // -517
1198: data_ff <= 24'h000086; // 134
1199: data_ff <= 24'hFFFFF1; // -15
1200: data_ff <= 24'h263274; // 2503284
1201: data_ff <= 24'hF362C4; // -826684
1202: data_ff <= 24'h06F66E; // 456302
1203: data_ff <= 24'hFBA691; // -285039
1204: data_ff <= 24'h02D0CE; // 184526
1205: data_ff <= 24'hFE2D91; // -119407
1206: data_ff <= 24'h0127BF; // 75711
1207: data_ff <= 24'hFF4ACE; // -46386
1208: data_ff <= 24'h0069FF; // 27135
1209: data_ff <= 24'hFFC584; // -14972
1210: data_ff <= 24'h001E00; // 7680
1211: data_ff <= 24'hFFF1F7; // -3593
1212: data_ff <= 24'h0005D2; // 1490
1213: data_ff <= 24'hFFFDF7; // -521
1214: data_ff <= 24'h000087; // 135
1215: data_ff <= 24'hFFFFF1; // -15
1216: data_ff <= 24'h26B78E; // 2537358
1217: data_ff <= 24'hF34FCE; // -831538
1218: data_ff <= 24'h06FE3F; // 458303
1219: data_ff <= 24'hFBA24C; // -286132
1220: data_ff <= 24'h02D368; // 185192
1221: data_ff <= 24'hFE2BE9; // -119831
1222: data_ff <= 24'h0128CD; // 75981
1223: data_ff <= 24'hFF4A23; // -46557
1224: data_ff <= 24'h006A68; // 27240
1225: data_ff <= 24'hFFC546; // -15034
1226: data_ff <= 24'h001E23; // 7715
1227: data_ff <= 24'hFFF1E5; // -3611
1228: data_ff <= 24'h0005DB; // 1499
1229: data_ff <= 24'hFFFDF3; // -525
1230: data_ff <= 24'h000088; // 136
1231: data_ff <= 24'hFFFFF1; // -15
1232: data_ff <= 24'h273C04; // 2571268
1233: data_ff <= 24'hF33DF1; // -836111
1234: data_ff <= 24'h07056A; // 460138
1235: data_ff <= 24'hFB9E70; // -287120
1236: data_ff <= 24'h02D5BD; // 185789
1237: data_ff <= 24'hFE2A6F; // -120209
1238: data_ff <= 24'h0129C0; // 76224
1239: data_ff <= 24'hFF4989; // -46711
1240: data_ff <= 24'h006AC7; // 27335
1241: data_ff <= 24'hFFC50D; // -15091
1242: data_ff <= 24'h001E43; // 7747
1243: data_ff <= 24'hFFF1D4; // -3628
1244: data_ff <= 24'h0005E3; // 1507
1245: data_ff <= 24'hFFFDF0; // -528
1246: data_ff <= 24'h00008A; // 138
1247: data_ff <= 24'hFFFFF0; // -16
1248: data_ff <= 24'h27BFD0; // 2605008
1249: data_ff <= 24'hF32D32; // -840398
1250: data_ff <= 24'h070BED; // 461805
1251: data_ff <= 24'hFB9B00; // -288000
1252: data_ff <= 24'h02D7CC; // 186316
1253: data_ff <= 24'hFE2922; // -120542
1254: data_ff <= 24'h012A96; // 76438
1255: data_ff <= 24'hFF4901; // -46847
1256: data_ff <= 24'h006B1C; // 27420
1257: data_ff <= 24'hFFC4DA; // -15142
1258: data_ff <= 24'h001E60; // 7776
1259: data_ff <= 24'hFFF1C5; // -3643
1260: data_ff <= 24'h0005EA; // 1514
1261: data_ff <= 24'hFFFDED; // -531
1262: data_ff <= 24'h00008B; // 139
1263: data_ff <= 24'hFFFFF0; // -16
1264: data_ff <= 24'h2842EA; // 2638570
1265: data_ff <= 24'hF31D94; // -844396
1266: data_ff <= 24'h0711C7; // 463303
1267: data_ff <= 24'hFB97FB; // -288773
1268: data_ff <= 24'h02D995; // 186773
1269: data_ff <= 24'hFE2802; // -120830
1270: data_ff <= 24'h012B4F; // 76623
1271: data_ff <= 24'hFF488B; // -46965
1272: data_ff <= 24'h006B67; // 27495
1273: data_ff <= 24'hFFC4AD; // -15187
1274: data_ff <= 24'h001E7A; // 7802
1275: data_ff <= 24'hFFF1B7; // -3657
1276: data_ff <= 24'h0005F1; // 1521
1277: data_ff <= 24'hFFFDEA; // -534
1278: data_ff <= 24'h00008C; // 140
1279: data_ff <= 24'hFFFFF0; // -16
1280: data_ff <= 24'h28C54B; // 2671947
1281: data_ff <= 24'hF30F1B; // -848101
1282: data_ff <= 24'h0716F4; // 464628
1283: data_ff <= 24'hFB9563; // -289437
1284: data_ff <= 24'h02DB18; // 187160
1285: data_ff <= 24'hFE2711; // -121071
1286: data_ff <= 24'h012BEA; // 76778
1287: data_ff <= 24'hFF4826; // -47066
1288: data_ff <= 24'h006BA7; // 27559
1289: data_ff <= 24'hFFC486; // -15226
1290: data_ff <= 24'h001E91; // 7825
1291: data_ff <= 24'hFFF1AA; // -3670
1292: data_ff <= 24'h0005F8; // 1528
1293: data_ff <= 24'hFFFDE7; // -537
1294: data_ff <= 24'h00008D; // 141
1295: data_ff <= 24'hFFFFEF; // -17
1296: data_ff <= 24'h2946EA; // 2705130
1297: data_ff <= 24'hF301CB; // -851509
1298: data_ff <= 24'h071B75; // 465781
1299: data_ff <= 24'hFB9338; // -289992
1300: data_ff <= 24'h02DC53; // 187475
1301: data_ff <= 24'hFE264D; // -121267
1302: data_ff <= 24'h012C69; // 76905
1303: data_ff <= 24'hFF47D3; // -47149
1304: data_ff <= 24'h006BDC; // 27612
1305: data_ff <= 24'hFFC464; // -15260
1306: data_ff <= 24'h001EA5; // 7845
1307: data_ff <= 24'hFFF19F; // -3681
1308: data_ff <= 24'h0005FD; // 1533
1309: data_ff <= 24'hFFFDE4; // -540
1310: data_ff <= 24'h00008E; // 142
1311: data_ff <= 24'hFFFFEF; // -17
1312: data_ff <= 24'h29C7C1; // 2738113
1313: data_ff <= 24'hF2F5A9; // -854615
1314: data_ff <= 24'h071F47; // 466759
1315: data_ff <= 24'hFB917C; // -290436
1316: data_ff <= 24'h02DD46; // 187718
1317: data_ff <= 24'hFE25B8; // -121416
1318: data_ff <= 24'h012CC9; // 77001
1319: data_ff <= 24'hFF4793; // -47213
1320: data_ff <= 24'h006C07; // 27655
1321: data_ff <= 24'hFFC449; // -15287
1322: data_ff <= 24'h001EB6; // 7862
1323: data_ff <= 24'hFFF195; // -3691
1324: data_ff <= 24'h000603; // 1539
1325: data_ff <= 24'hFFFDE2; // -542
1326: data_ff <= 24'h00008F; // 143
1327: data_ff <= 24'hFFFFEF; // -17
1328: data_ff <= 24'h2A47C8; // 2770888
1329: data_ff <= 24'hF2EAB9; // -857415
1330: data_ff <= 24'h072269; // 467561
1331: data_ff <= 24'hFB902F; // -290769
1332: data_ff <= 24'h02DDF1; // 187889
1333: data_ff <= 24'hFE2553; // -121517
1334: data_ff <= 24'h012D0C; // 77068
1335: data_ff <= 24'hFF4765; // -47259
1336: data_ff <= 24'h006C27; // 27687
1337: data_ff <= 24'hFFC433; // -15309
1338: data_ff <= 24'h001EC4; // 7876
1339: data_ff <= 24'hFFF18D; // -3699
1340: data_ff <= 24'h000607; // 1543
1341: data_ff <= 24'hFFFDDF; // -545
1342: data_ff <= 24'h000090; // 144
1343: data_ff <= 24'hFFFFEF; // -17
1344: data_ff <= 24'h2AC6F8; // 2803448
1345: data_ff <= 24'hF2E0FD; // -859907
1346: data_ff <= 24'h0724D9; // 468185
1347: data_ff <= 24'hFB8F51; // -290991
1348: data_ff <= 24'h02DE54; // 187988
1349: data_ff <= 24'hFE251C; // -121572
1350: data_ff <= 24'h012D31; // 77105
1351: data_ff <= 24'hFF4749; // -47287
1352: data_ff <= 24'h006C3C; // 27708
1353: data_ff <= 24'hFFC423; // -15325
1354: data_ff <= 24'h001ECF; // 7887
1355: data_ff <= 24'hFFF186; // -3706
1356: data_ff <= 24'h00060B; // 1547
1357: data_ff <= 24'hFFFDDD; // -547
1358: data_ff <= 24'h000091; // 145
1359: data_ff <= 24'hFFFFEE; // -18
1360: data_ff <= 24'h2B4549; // 2835785
1361: data_ff <= 24'hF2D87A; // -862086
1362: data_ff <= 24'h072697; // 468631
1363: data_ff <= 24'hFB8EE5; // -291099
1364: data_ff <= 24'h02DE6D; // 188013
1365: data_ff <= 24'hFE2515; // -121579
1366: data_ff <= 24'h012D37; // 77111
1367: data_ff <= 24'hFF4740; // -47296
1368: data_ff <= 24'h006C46; // 27718
1369: data_ff <= 24'hFFC41A; // -15334
1370: data_ff <= 24'h001ED6; // 7894
1371: data_ff <= 24'hFFF180; // -3712
1372: data_ff <= 24'h00060F; // 1551
1373: data_ff <= 24'hFFFDDC; // -548
1374: data_ff <= 24'h000092; // 146
1375: data_ff <= 24'hFFFFEE; // -18
1376: data_ff <= 24'h2BC2B5; // 2867893
1377: data_ff <= 24'hF2D134; // -863948
1378: data_ff <= 24'h0727A0; // 468896
1379: data_ff <= 24'hFB8EEA; // -291094
1380: data_ff <= 24'h02DE3D; // 187965
1381: data_ff <= 24'hFE253E; // -121538
1382: data_ff <= 24'h012D20; // 77088
1383: data_ff <= 24'hFF474A; // -47286
1384: data_ff <= 24'h006C45; // 27717
1385: data_ff <= 24'hFFC416; // -15338
1386: data_ff <= 24'h001EDB; // 7899
1387: data_ff <= 24'hFFF17C; // -3716
1388: data_ff <= 24'h000611; // 1553
1389: data_ff <= 24'hFFFDDA; // -550
1390: data_ff <= 24'h000093; // 147
1391: data_ff <= 24'hFFFFEE; // -18
1392: data_ff <= 24'h2C3F34; // 2899764
1393: data_ff <= 24'hF2CB2F; // -865489
1394: data_ff <= 24'h0727F3; // 468979
1395: data_ff <= 24'hFB8F60; // -290976
1396: data_ff <= 24'h02DDC2; // 187842
1397: data_ff <= 24'hFE2596; // -121450
1398: data_ff <= 24'h012CE9; // 77033
1399: data_ff <= 24'hFF4767; // -47257
1400: data_ff <= 24'h006C39; // 27705
1401: data_ff <= 24'hFFC419; // -15335
1402: data_ff <= 24'h001EDD; // 7901
1403: data_ff <= 24'hFFF17A; // -3718
1404: data_ff <= 24'h000614; // 1556
1405: data_ff <= 24'hFFFDD9; // -551
1406: data_ff <= 24'h000093; // 147
1407: data_ff <= 24'hFFFFEE; // -18
1408: data_ff <= 24'h2CBABE; // 2931390
1409: data_ff <= 24'hF2C66D; // -866707
1410: data_ff <= 24'h072790; // 468880
1411: data_ff <= 24'hFB9049; // -290743
1412: data_ff <= 24'h02DCFD; // 187645
1413: data_ff <= 24'hFE261F; // -121313
1414: data_ff <= 24'h012C94; // 76948
1415: data_ff <= 24'hFF4796; // -47210
1416: data_ff <= 24'h006C22; // 27682
1417: data_ff <= 24'hFFC422; // -15326
1418: data_ff <= 24'h001EDB; // 7899
1419: data_ff <= 24'hFFF179; // -3719
1420: data_ff <= 24'h000615; // 1557
1421: data_ff <= 24'hFFFDD7; // -553
1422: data_ff <= 24'h000094; // 148
1423: data_ff <= 24'hFFFFED; // -19
1424: data_ff <= 24'h2D354D; // 2962765
1425: data_ff <= 24'hF2C2F2; // -867598
1426: data_ff <= 24'h072675; // 468597
1427: data_ff <= 24'hFB91A6; // -290394
1428: data_ff <= 24'h02DBEE; // 187374
1429: data_ff <= 24'hFE26D9; // -121127
1430: data_ff <= 24'h012C20; // 76832
1431: data_ff <= 24'hFF47D9; // -47143
1432: data_ff <= 24'h006C00; // 27648
1433: data_ff <= 24'hFFC431; // -15311
1434: data_ff <= 24'h001ED6; // 7894
1435: data_ff <= 24'hFFF179; // -3719
1436: data_ff <= 24'h000616; // 1558
1437: data_ff <= 24'hFFFDD7; // -553
1438: data_ff <= 24'h000094; // 148
1439: data_ff <= 24'hFFFFED; // -19
1440: data_ff <= 24'h2DAEDA; // 2993882
1441: data_ff <= 24'hF2C0C3; // -868157
1442: data_ff <= 24'h0724A1; // 468129
1443: data_ff <= 24'hFB9375; // -289931
1444: data_ff <= 24'h02DA94; // 187028
1445: data_ff <= 24'hFE27C3; // -120893
1446: data_ff <= 24'h012B8D; // 76685
1447: data_ff <= 24'hFF482E; // -47058
1448: data_ff <= 24'h006BD3; // 27603
1449: data_ff <= 24'hFFC446; // -15290
1450: data_ff <= 24'h001ECD; // 7885
1451: data_ff <= 24'hFFF17B; // -3717
1452: data_ff <= 24'h000616; // 1558
1453: data_ff <= 24'hFFFDD6; // -554
1454: data_ff <= 24'h000095; // 149
1455: data_ff <= 24'hFFFFED; // -19
1456: data_ff <= 24'h2E275D; // 3024733
1457: data_ff <= 24'hF2BFE1; // -868383
1458: data_ff <= 24'h072213; // 467475
1459: data_ff <= 24'hFB95B9; // -289351
1460: data_ff <= 24'h02D8EE; // 186606
1461: data_ff <= 24'hFE28DD; // -120611
1462: data_ff <= 24'h012ADB; // 76507
1463: data_ff <= 24'hFF4897; // -46953
1464: data_ff <= 24'h006B9A; // 27546
1465: data_ff <= 24'hFFC462; // -15262
1466: data_ff <= 24'h001EC2; // 7874
1467: data_ff <= 24'hFFF17F; // -3713
1468: data_ff <= 24'h000616; // 1558
1469: data_ff <= 24'hFFFDD5; // -555
1470: data_ff <= 24'h000095; // 149
1471: data_ff <= 24'hFFFFED; // -19
1472: data_ff <= 24'h2E9ECF; // 3055311
1473: data_ff <= 24'hF2C051; // -868271
1474: data_ff <= 24'h071ECA; // 466634
1475: data_ff <= 24'hFB9872; // -288654
1476: data_ff <= 24'h02D6FD; // 186109
1477: data_ff <= 24'hFE2A29; // -120279
1478: data_ff <= 24'h012A09; // 76297
1479: data_ff <= 24'hFF4913; // -46829
1480: data_ff <= 24'h006B55; // 27477
1481: data_ff <= 24'hFFC484; // -15228
1482: data_ff <= 24'h001EB3; // 7859
1483: data_ff <= 24'hFFF184; // -3708
1484: data_ff <= 24'h000615; // 1557
1485: data_ff <= 24'hFFFDD5; // -555
1486: data_ff <= 24'h000096; // 150
1487: data_ff <= 24'hFFFFED; // -19
1488: data_ff <= 24'h2F152A; // 3085610
1489: data_ff <= 24'hF2C215; // -867819
1490: data_ff <= 24'h071AC5; // 465605
1491: data_ff <= 24'hFB9B9F; // -287841
1492: data_ff <= 24'h02D4C1; // 185537
1493: data_ff <= 24'hFE2BA6; // -119898
1494: data_ff <= 24'h012919; // 76057
1495: data_ff <= 24'hFF49A3; // -46685
1496: data_ff <= 24'h006B06; // 27398
1497: data_ff <= 24'hFFC4AD; // -15187
1498: data_ff <= 24'h001EA1; // 7841
1499: data_ff <= 24'hFFF18B; // -3701
1500: data_ff <= 24'h000613; // 1555
1501: data_ff <= 24'hFFFDD5; // -555
1502: data_ff <= 24'h000096; // 150
1503: data_ff <= 24'hFFFFEC; // -20
1504: data_ff <= 24'h2F8A66; // 3115622
1505: data_ff <= 24'hF2C532; // -867022
1506: data_ff <= 24'h071603; // 464387
1507: data_ff <= 24'hFB9F41; // -286911
1508: data_ff <= 24'h02D238; // 184888
1509: data_ff <= 24'hFE2D55; // -119467
1510: data_ff <= 24'h012808; // 75784
1511: data_ff <= 24'hFF4A46; // -46522
1512: data_ff <= 24'h006AAA; // 27306
1513: data_ff <= 24'hFFC4DC; // -15140
1514: data_ff <= 24'h001E8B; // 7819
1515: data_ff <= 24'hFFF193; // -3693
1516: data_ff <= 24'h000610; // 1552
1517: data_ff <= 24'hFFFDD6; // -554
1518: data_ff <= 24'h000096; // 150
1519: data_ff <= 24'hFFFFEC; // -20
1520: data_ff <= 24'h2FFE7D; // 3145341
1521: data_ff <= 24'hF2C9A9; // -865879
1522: data_ff <= 24'h071084; // 462980
1523: data_ff <= 24'hFBA359; // -285863
1524: data_ff <= 24'h02CF64; // 184164
1525: data_ff <= 24'hFE2F34; // -118988
1526: data_ff <= 24'h0126D9; // 75481
1527: data_ff <= 24'hFF4AFC; // -46340
1528: data_ff <= 24'h006A44; // 27204
1529: data_ff <= 24'hFFC511; // -15087
1530: data_ff <= 24'h001E72; // 7794
1531: data_ff <= 24'hFFF19E; // -3682
1532: data_ff <= 24'h00060D; // 1549
1533: data_ff <= 24'hFFFDD6; // -554
1534: data_ff <= 24'h000097; // 151
1535: data_ff <= 24'hFFFFEC; // -20
1536: data_ff <= 24'h307168; // 3174760
1537: data_ff <= 24'hF2CF7E; // -864386
1538: data_ff <= 24'h070A46; // 461382
1539: data_ff <= 24'hFBA7E7; // -284697
1540: data_ff <= 24'h02CC44; // 183364
1541: data_ff <= 24'hFE3145; // -118459
1542: data_ff <= 24'h012589; // 75145
1543: data_ff <= 24'hFF4BC6; // -46138
1544: data_ff <= 24'h0069D1; // 27089
1545: data_ff <= 24'hFFC54D; // -15027
1546: data_ff <= 24'h001E56; // 7766
1547: data_ff <= 24'hFFF1A9; // -3671
1548: data_ff <= 24'h000609; // 1545
1549: data_ff <= 24'hFFFDD7; // -553
1550: data_ff <= 24'h000097; // 151
1551: data_ff <= 24'hFFFFEC; // -20
1552: data_ff <= 24'h30E321; // 3203873
1553: data_ff <= 24'hF2D6B3; // -862541
1554: data_ff <= 24'h07034A; // 459594
1555: data_ff <= 24'hFBACEA; // -283414
1556: data_ff <= 24'h02C8D7; // 182487
1557: data_ff <= 24'hFE3388; // -117880
1558: data_ff <= 24'h01241B; // 74779
1559: data_ff <= 24'hFF4CA4; // -45916
1560: data_ff <= 24'h006953; // 26963
1561: data_ff <= 24'hFFC58F; // -14961
1562: data_ff <= 24'h001E36; // 7734
1563: data_ff <= 24'hFFF1B7; // -3657
1564: data_ff <= 24'h000605; // 1541
1565: data_ff <= 24'hFFFDD8; // -552
1566: data_ff <= 24'h000097; // 151
1567: data_ff <= 24'hFFFFEC; // -20
1568: data_ff <= 24'h31539F; // 3232671
1569: data_ff <= 24'hF2DF4C; // -860340
1570: data_ff <= 24'h06FB8E; // 457614
1571: data_ff <= 24'hFBB264; // -282012
1572: data_ff <= 24'h02C51E; // 181534
1573: data_ff <= 24'hFE35FC; // -117252
1574: data_ff <= 24'h01228C; // 74380
1575: data_ff <= 24'hFF4D95; // -45675
1576: data_ff <= 24'h0068C9; // 26825
1577: data_ff <= 24'hFFC5D8; // -14888
1578: data_ff <= 24'h001E13; // 7699
1579: data_ff <= 24'hFFF1C6; // -3642
1580: data_ff <= 24'h0005FF; // 1535
1581: data_ff <= 24'hFFFDD9; // -551
1582: data_ff <= 24'h000097; // 151
1583: data_ff <= 24'hFFFFEB; // -21
1584: data_ff <= 24'h31C2DE; // 3261150
1585: data_ff <= 24'hF2E94B; // -857781
1586: data_ff <= 24'h06F313; // 455443
1587: data_ff <= 24'hFBB854; // -280492
1588: data_ff <= 24'h02C119; // 180505
1589: data_ff <= 24'hFE38A1; // -116575
1590: data_ff <= 24'h0120DE; // 73950
1591: data_ff <= 24'hFF4E9A; // -45414
1592: data_ff <= 24'h006834; // 26676
1593: data_ff <= 24'hFFC628; // -14808
1594: data_ff <= 24'h001DEC; // 7660
1595: data_ff <= 24'hFFF1D6; // -3626
1596: data_ff <= 24'h0005F9; // 1529
1597: data_ff <= 24'hFFFDDB; // -549
1598: data_ff <= 24'h000097; // 151
1599: data_ff <= 24'hFFFFEB; // -21
1600: data_ff <= 24'h3230D6; // 3289302
1601: data_ff <= 24'hF2F4B3; // -854861
1602: data_ff <= 24'h06E9D6; // 453078
1603: data_ff <= 24'hFBBEBA; // -278854
1604: data_ff <= 24'h02BCC7; // 179399
1605: data_ff <= 24'hFE3B79; // -115847
1606: data_ff <= 24'h011F10; // 73488
1607: data_ff <= 24'hFF4FB3; // -45133
1608: data_ff <= 24'h006793; // 26515
1609: data_ff <= 24'hFFC67E; // -14722
1610: data_ff <= 24'h001DC2; // 7618
1611: data_ff <= 24'hFFF1E9; // -3607
1612: data_ff <= 24'h0005F3; // 1523
1613: data_ff <= 24'hFFFDDD; // -547
1614: data_ff <= 24'h000097; // 151
1615: data_ff <= 24'hFFFFEB; // -21
1616: data_ff <= 24'h329D81; // 3317121
1617: data_ff <= 24'hF30186; // -851578
1618: data_ff <= 24'h06DFDA; // 450522
1619: data_ff <= 24'hFBC596; // -277098
1620: data_ff <= 24'h02B829; // 178217
1621: data_ff <= 24'hFE3E81; // -115071
1622: data_ff <= 24'h011D22; // 72994
1623: data_ff <= 24'hFF50DF; // -44833
1624: data_ff <= 24'h0066E6; // 26342
1625: data_ff <= 24'hFFC6DB; // -14629
1626: data_ff <= 24'h001D94; // 7572
1627: data_ff <= 24'hFFF1FD; // -3587
1628: data_ff <= 24'h0005EB; // 1515
1629: data_ff <= 24'hFFFDDF; // -545
1630: data_ff <= 24'h000096; // 150
1631: data_ff <= 24'hFFFFEB; // -21
1632: data_ff <= 24'h3308D8; // 3344600
1633: data_ff <= 24'hF30FC8; // -847928
1634: data_ff <= 24'h06D51C; // 447772
1635: data_ff <= 24'hFBCCE9; // -275223
1636: data_ff <= 24'h02B33F; // 176959
1637: data_ff <= 24'hFE41BC; // -114244
1638: data_ff <= 24'h011B15; // 72469
1639: data_ff <= 24'hFF521F; // -44513
1640: data_ff <= 24'h00662E; // 26158
1641: data_ff <= 24'hFFC73E; // -14530
1642: data_ff <= 24'h001D63; // 7523
1643: data_ff <= 24'hFFF212; // -3566
1644: data_ff <= 24'h0005E3; // 1507
1645: data_ff <= 24'hFFFDE1; // -543
1646: data_ff <= 24'h000096; // 150
1647: data_ff <= 24'hFFFFEB; // -21
1648: data_ff <= 24'h3372D6; // 3371734
1649: data_ff <= 24'hF31F79; // -843911
1650: data_ff <= 24'h06C99D; // 444829
1651: data_ff <= 24'hFBD4B3; // -273229
1652: data_ff <= 24'h02AE09; // 175625
1653: data_ff <= 24'hFE4527; // -113369
1654: data_ff <= 24'h0118E8; // 71912
1655: data_ff <= 24'hFF5372; // -44174
1656: data_ff <= 24'h00656A; // 25962
1657: data_ff <= 24'hFFC7A8; // -14424
1658: data_ff <= 24'h001D2F; // 7471
1659: data_ff <= 24'hFFF22A; // -3542
1660: data_ff <= 24'h0005DA; // 1498
1661: data_ff <= 24'hFFFDE4; // -540
1662: data_ff <= 24'h000095; // 149
1663: data_ff <= 24'hFFFFEB; // -21
1664: data_ff <= 24'h33DB73; // 3398515
1665: data_ff <= 24'hF3309D; // -839523
1666: data_ff <= 24'h06BD5C; // 441692
1667: data_ff <= 24'hFBDCF2; // -271118
1668: data_ff <= 24'h02A886; // 174214
1669: data_ff <= 24'hFE48C4; // -112444
1670: data_ff <= 24'h01169B; // 71323
1671: data_ff <= 24'hFF54D9; // -43815
1672: data_ff <= 24'h00649A; // 25754
1673: data_ff <= 24'hFFC819; // -14311
1674: data_ff <= 24'h001CF6; // 7414
1675: data_ff <= 24'hFFF243; // -3517
1676: data_ff <= 24'h0005D0; // 1488
1677: data_ff <= 24'hFFFDE7; // -537
1678: data_ff <= 24'h000095; // 149
1679: data_ff <= 24'hFFFFEB; // -21
1680: data_ff <= 24'h3442AA; // 3424938
1681: data_ff <= 24'hF34335; // -834763
1682: data_ff <= 24'h06B05A; // 438362
1683: data_ff <= 24'hFBE5A7; // -268889
1684: data_ff <= 24'h02A2B8; // 172728
1685: data_ff <= 24'hFE4C93; // -111469
1686: data_ff <= 24'h01142F; // 70703
1687: data_ff <= 24'hFF5654; // -43436
1688: data_ff <= 24'h0063BE; // 25534
1689: data_ff <= 24'hFFC890; // -14192
1690: data_ff <= 24'h001CBB; // 7355
1691: data_ff <= 24'hFFF25E; // -3490
1692: data_ff <= 24'h0005C6; // 1478
1693: data_ff <= 24'hFFFDEA; // -534
1694: data_ff <= 24'h000094; // 148
1695: data_ff <= 24'hFFFFEB; // -21
1696: data_ff <= 24'h34A875; // 3450997
1697: data_ff <= 24'hF35744; // -829628
1698: data_ff <= 24'h06A296; // 434838
1699: data_ff <= 24'hFBEED2; // -266542
1700: data_ff <= 24'h029C9E; // 171166
1701: data_ff <= 24'hFE5092; // -110446
1702: data_ff <= 24'h0111A3; // 70051
1703: data_ff <= 24'hFF57E3; // -43037
1704: data_ff <= 24'h0062D7; // 25303
1705: data_ff <= 24'hFFC90E; // -14066
1706: data_ff <= 24'h001C7C; // 7292
1707: data_ff <= 24'hFFF27A; // -3462
1708: data_ff <= 24'h0005BB; // 1467
1709: data_ff <= 24'hFFFDEE; // -530
1710: data_ff <= 24'h000094; // 148
1711: data_ff <= 24'hFFFFEB; // -21
1712: data_ff <= 24'h350CCE; // 3476686
1713: data_ff <= 24'hF36CCC; // -824116
1714: data_ff <= 24'h069411; // 431121
1715: data_ff <= 24'hFBF873; // -264077
1716: data_ff <= 24'h029638; // 169528
1717: data_ff <= 24'hFE54C3; // -109373
1718: data_ff <= 24'h010EF8; // 69368
1719: data_ff <= 24'hFF5985; // -42619
1720: data_ff <= 24'h0061E4; // 25060
1721: data_ff <= 24'hFFC992; // -13934
1722: data_ff <= 24'h001C39; // 7225
1723: data_ff <= 24'hFFF298; // -3432
1724: data_ff <= 24'h0005AF; // 1455
1725: data_ff <= 24'hFFFDF1; // -527
1726: data_ff <= 24'h000093; // 147
1727: data_ff <= 24'hFFFFEB; // -21
1728: data_ff <= 24'h356FAD; // 3501997
1729: data_ff <= 24'hF383CE; // -818226
1730: data_ff <= 24'h0684CA; // 427210
1731: data_ff <= 24'hFC0289; // -261495
1732: data_ff <= 24'h028F87; // 167815
1733: data_ff <= 24'hFE5925; // -108251
1734: data_ff <= 24'h010C2E; // 68654
1735: data_ff <= 24'hFF5B3A; // -42182
1736: data_ff <= 24'h0060E5; // 24805
1737: data_ff <= 24'hFFCA1E; // -13794
1738: data_ff <= 24'h001BF3; // 7155
1739: data_ff <= 24'hFFF2B8; // -3400
1740: data_ff <= 24'h0005A2; // 1442
1741: data_ff <= 24'hFFFDF5; // -523
1742: data_ff <= 24'h000092; // 146
1743: data_ff <= 24'hFFFFEB; // -21
1744: data_ff <= 24'h35D10F; // 3526927
1745: data_ff <= 24'hF39C4D; // -811955
1746: data_ff <= 24'h0674C2; // 423106
1747: data_ff <= 24'hFC0D14; // -258796
1748: data_ff <= 24'h02888B; // 166027
1749: data_ff <= 24'hFE5DB7; // -107081
1750: data_ff <= 24'h010944; // 67908
1751: data_ff <= 24'hFF5D04; // -41724
1752: data_ff <= 24'h005FDB; // 24539
1753: data_ff <= 24'hFFCAAF; // -13649
1754: data_ff <= 24'h001BA9; // 7081
1755: data_ff <= 24'hFFF2DA; // -3366
1756: data_ff <= 24'h000595; // 1429
1757: data_ff <= 24'hFFFDFA; // -518
1758: data_ff <= 24'h000091; // 145
1759: data_ff <= 24'hFFFFEB; // -21
1760: data_ff <= 24'h3630ED; // 3551469
1761: data_ff <= 24'hF3B64A; // -805302
1762: data_ff <= 24'h0663F9; // 418809
1763: data_ff <= 24'hFC1814; // -255980
1764: data_ff <= 24'h028145; // 164165
1765: data_ff <= 24'hFE627A; // -105862
1766: data_ff <= 24'h01063B; // 67131
1767: data_ff <= 24'hFF5EE0; // -41248
1768: data_ff <= 24'h005EC5; // 24261
1769: data_ff <= 24'hFFCB48; // -13496
1770: data_ff <= 24'h001B5C; // 7004
1771: data_ff <= 24'hFFF2FD; // -3331
1772: data_ff <= 24'h000586; // 1414
1773: data_ff <= 24'hFFFDFE; // -514
1774: data_ff <= 24'h000090; // 144
1775: data_ff <= 24'hFFFFEB; // -21
1776: data_ff <= 24'h368F41; // 3575617
1777: data_ff <= 24'hF3D1C7; // -798265
1778: data_ff <= 24'h06526F; // 414319
1779: data_ff <= 24'hFC2387; // -253049
1780: data_ff <= 24'h0279B4; // 162228
1781: data_ff <= 24'hFE676D; // -104595
1782: data_ff <= 24'h010313; // 66323
1783: data_ff <= 24'hFF60D0; // -40752
1784: data_ff <= 24'h005DA3; // 23971
1785: data_ff <= 24'hFFCBE7; // -13337
1786: data_ff <= 24'h001B0B; // 6923
1787: data_ff <= 24'hFFF323; // -3293
1788: data_ff <= 24'h000577; // 1399
1789: data_ff <= 24'hFFFE03; // -509
1790: data_ff <= 24'h00008F; // 143
1791: data_ff <= 24'hFFFFEB; // -21
1792: data_ff <= 24'h36EC05; // 3599365
1793: data_ff <= 24'hF3EEC5; // -790843
1794: data_ff <= 24'h064026; // 409638
1795: data_ff <= 24'hFC2F6F; // -250001
1796: data_ff <= 24'h0271D8; // 160216
1797: data_ff <= 24'hFE6C90; // -103280
1798: data_ff <= 24'h00FFCC; // 65484
1799: data_ff <= 24'hFF62D3; // -40237
1800: data_ff <= 24'h005C76; // 23670
1801: data_ff <= 24'hFFCC8C; // -13172
1802: data_ff <= 24'h001AB7; // 6839
1803: data_ff <= 24'hFFF349; // -3255
1804: data_ff <= 24'h000568; // 1384
1805: data_ff <= 24'hFFFE09; // -503
1806: data_ff <= 24'h00008E; // 142
1807: data_ff <= 24'hFFFFEB; // -21
1808: data_ff <= 24'h374735; // 3622709
1809: data_ff <= 24'hF40D45; // -783035
1810: data_ff <= 24'h062D1C; // 404764
1811: data_ff <= 24'hFC3BC9; // -246839
1812: data_ff <= 24'h0269B4; // 158132
1813: data_ff <= 24'hFE71E3; // -101917
1814: data_ff <= 24'h00FC67; // 64615
1815: data_ff <= 24'hFF64E9; // -39703
1816: data_ff <= 24'h005B3D; // 23357
1817: data_ff <= 24'hFFCD39; // -12999
1818: data_ff <= 24'h001A5F; // 6751
1819: data_ff <= 24'hFFF372; // -3214
1820: data_ff <= 24'h000557; // 1367
1821: data_ff <= 24'hFFFE0E; // -498
1822: data_ff <= 24'h00008D; // 141
1823: data_ff <= 24'hFFFFEB; // -21
1824: data_ff <= 24'h37A0CA; // 3645642
1825: data_ff <= 24'hF42D4A; // -774838
1826: data_ff <= 24'h061953; // 399699
1827: data_ff <= 24'hFC4896; // -243562
1828: data_ff <= 24'h026145; // 155973
1829: data_ff <= 24'hFE7766; // -100506
1830: data_ff <= 24'h00F8E3; // 63715
1831: data_ff <= 24'hFF6713; // -39149
1832: data_ff <= 24'h0059F9; // 23033
1833: data_ff <= 24'hFFCDEB; // -12821
1834: data_ff <= 24'h001A04; // 6660
1835: data_ff <= 24'hFFF39C; // -3172
1836: data_ff <= 24'h000546; // 1350
1837: data_ff <= 24'hFFFE14; // -492
1838: data_ff <= 24'h00008B; // 139
1839: data_ff <= 24'hFFFFEB; // -21
1840: data_ff <= 24'h37F8C0; // 3668160
1841: data_ff <= 24'hF44ED4; // -766252
1842: data_ff <= 24'h0604CC; // 394444
1843: data_ff <= 24'hFC55D5; // -240171
1844: data_ff <= 24'h02588F; // 153743
1845: data_ff <= 24'hFE7D18; // -99048
1846: data_ff <= 24'h00F541; // 62785
1847: data_ff <= 24'hFF694F; // -38577
1848: data_ff <= 24'h0058A9; // 22697
1849: data_ff <= 24'hFFCEA5; // -12635
1850: data_ff <= 24'h0019A5; // 6565
1851: data_ff <= 24'hFFF3C9; // -3127
1852: data_ff <= 24'h000534; // 1332
1853: data_ff <= 24'hFFFE1A; // -486
1854: data_ff <= 24'h00008A; // 138
1855: data_ff <= 24'hFFFFEB; // -21
1856: data_ff <= 24'h384F10; // 3690256
1857: data_ff <= 24'hF471E5; // -757275
1858: data_ff <= 24'h05EF87; // 388999
1859: data_ff <= 24'hFC6385; // -236667
1860: data_ff <= 24'h024F8F; // 151439
1861: data_ff <= 24'hFE82F8; // -97544
1862: data_ff <= 24'h00F180; // 61824
1863: data_ff <= 24'hFF6B9F; // -37985
1864: data_ff <= 24'h00574E; // 22350
1865: data_ff <= 24'hFFCF64; // -12444
1866: data_ff <= 24'h001943; // 6467
1867: data_ff <= 24'hFFF3F6; // -3082
1868: data_ff <= 24'h000521; // 1313
1869: data_ff <= 24'hFFFE21; // -479
1870: data_ff <= 24'h000088; // 136
1871: data_ff <= 24'hFFFFEB; // -21
1872: data_ff <= 24'h38A3B7; // 3711927
1873: data_ff <= 24'hF4967C; // -747908
1874: data_ff <= 24'h05D984; // 383364
1875: data_ff <= 24'hFC71A6; // -233050
1876: data_ff <= 24'h024648; // 149064
1877: data_ff <= 24'hFE8908; // -95992
1878: data_ff <= 24'h00EDA2; // 60834
1879: data_ff <= 24'hFF6E01; // -37375
1880: data_ff <= 24'h0055E8; // 21992
1881: data_ff <= 24'hFFD02B; // -12245
1882: data_ff <= 24'h0018DD; // 6365
1883: data_ff <= 24'hFFF426; // -3034
1884: data_ff <= 24'h00050D; // 1293
1885: data_ff <= 24'hFFFE27; // -473
1886: data_ff <= 24'h000086; // 134
1887: data_ff <= 24'hFFFFEB; // -21
1888: data_ff <= 24'h38F6AE; // 3733166
1889: data_ff <= 24'hF4BC9C; // -738148
1890: data_ff <= 24'h05C2C6; // 377542
1891: data_ff <= 24'hFC8037; // -229321
1892: data_ff <= 24'h023CBA; // 146618
1893: data_ff <= 24'hFE8F45; // -94395
1894: data_ff <= 24'h00E9A5; // 59813
1895: data_ff <= 24'hFF7075; // -36747
1896: data_ff <= 24'h005476; // 21622
1897: data_ff <= 24'hFFD0F7; // -12041
1898: data_ff <= 24'h001874; // 6260
1899: data_ff <= 24'hFFF457; // -2985
1900: data_ff <= 24'h0004F9; // 1273
1901: data_ff <= 24'hFFFE2F; // -465
1902: data_ff <= 24'h000085; // 133
1903: data_ff <= 24'hFFFFEB; // -21
1904: data_ff <= 24'h3947F1; // 3753969
1905: data_ff <= 24'hF4E446; // -727994
1906: data_ff <= 24'h05AB4C; // 371532
1907: data_ff <= 24'hFC8F36; // -225482
1908: data_ff <= 24'h0232E5; // 144101
1909: data_ff <= 24'hFE95B1; // -92751
1910: data_ff <= 24'h00E58C; // 58764
1911: data_ff <= 24'hFF72FD; // -36099
1912: data_ff <= 24'h0052FA; // 21242
1913: data_ff <= 24'hFFD1CA; // -11830
1914: data_ff <= 24'h001807; // 6151
1915: data_ff <= 24'hFFF48A; // -2934
1916: data_ff <= 24'h0004E4; // 1252
1917: data_ff <= 24'hFFFE36; // -458
1918: data_ff <= 24'h000083; // 131
1919: data_ff <= 24'hFFFFEC; // -20
1920: data_ff <= 24'h39977C; // 3774332
1921: data_ff <= 24'hF50D79; // -717447
1922: data_ff <= 24'h059318; // 365336
1923: data_ff <= 24'hFC9EA4; // -221532
1924: data_ff <= 24'h0228CA; // 141514
1925: data_ff <= 24'hFE9C4A; // -91062
1926: data_ff <= 24'h00E155; // 57685
1927: data_ff <= 24'hFF7596; // -35434
1928: data_ff <= 24'h005172; // 20850
1929: data_ff <= 24'hFFD2A4; // -11612
1930: data_ff <= 24'h001797; // 6039
1931: data_ff <= 24'hFFF4BF; // -2881
1932: data_ff <= 24'h0004CE; // 1230
1933: data_ff <= 24'hFFFE3E; // -450
1934: data_ff <= 24'h000081; // 129
1935: data_ff <= 24'hFFFFEC; // -20
1936: data_ff <= 24'h39E548; // 3794248
1937: data_ff <= 24'hF53836; // -706506
1938: data_ff <= 24'h057A2A; // 358954
1939: data_ff <= 24'hFCAE7F; // -217473
1940: data_ff <= 24'h021E69; // 138857
1941: data_ff <= 24'hFEA310; // -89328
1942: data_ff <= 24'h00DD01; // 56577
1943: data_ff <= 24'hFF7842; // -34750
1944: data_ff <= 24'h004FDF; // 20447
1945: data_ff <= 24'hFFD384; // -11388
1946: data_ff <= 24'h001723; // 5923
1947: data_ff <= 24'hFFF4F5; // -2827
1948: data_ff <= 24'h0004B7; // 1207
1949: data_ff <= 24'hFFFE45; // -443
1950: data_ff <= 24'h00007F; // 127
1951: data_ff <= 24'hFFFFEC; // -20
1952: data_ff <= 24'h3A3152; // 3813714
1953: data_ff <= 24'hF5647E; // -695170
1954: data_ff <= 24'h056085; // 352389
1955: data_ff <= 24'hFCBEC6; // -213306
1956: data_ff <= 24'h0213C4; // 136132
1957: data_ff <= 24'hFEAA03; // -87549
1958: data_ff <= 24'h00D890; // 55440
1959: data_ff <= 24'hFF7B00; // -34048
1960: data_ff <= 24'h004E41; // 20033
1961: data_ff <= 24'hFFD46A; // -11158
1962: data_ff <= 24'h0016AC; // 5804
1963: data_ff <= 24'hFFF52D; // -2771
1964: data_ff <= 24'h0004A0; // 1184
1965: data_ff <= 24'hFFFE4E; // -434
1966: data_ff <= 24'h00007D; // 125
1967: data_ff <= 24'hFFFFEC; // -20
1968: data_ff <= 24'h3A7B95; // 3832725
1969: data_ff <= 24'hF59252; // -683438
1970: data_ff <= 24'h054628; // 345640
1971: data_ff <= 24'hFCCF78; // -209032
1972: data_ff <= 24'h0208DB; // 133339
1973: data_ff <= 24'hFEB121; // -85727
1974: data_ff <= 24'h00D403; // 54275
1975: data_ff <= 24'hFF7DD0; // -33328
1976: data_ff <= 24'h004C99; // 19609
1977: data_ff <= 24'hFFD556; // -10922
1978: data_ff <= 24'h001632; // 5682
1979: data_ff <= 24'hFFF567; // -2713
1980: data_ff <= 24'h000488; // 1160
1981: data_ff <= 24'hFFFE56; // -426
1982: data_ff <= 24'h00007A; // 122
1983: data_ff <= 24'hFFFFEC; // -20
1984: data_ff <= 24'h3AC40D; // 3851277
1985: data_ff <= 24'hF5C1B1; // -671311
1986: data_ff <= 24'h052B16; // 338710
1987: data_ff <= 24'hFCE095; // -204651
1988: data_ff <= 24'h01FDAE; // 130478
1989: data_ff <= 24'hFEB86C; // -83860
1990: data_ff <= 24'h00CF5A; // 53082
1991: data_ff <= 24'hFF80B1; // -32591
1992: data_ff <= 24'h004AE5; // 19173
1993: data_ff <= 24'hFFD649; // -10679
1994: data_ff <= 24'h0015B4; // 5556
1995: data_ff <= 24'hFFF5A3; // -2653
1996: data_ff <= 24'h00046F; // 1135
1997: data_ff <= 24'hFFFE5F; // -417
1998: data_ff <= 24'h000078; // 120
1999: data_ff <= 24'hFFFFED; // -19
2000: data_ff <= 24'h3B0AB4; // 3869364
2001: data_ff <= 24'hF5F29C; // -658788
2002: data_ff <= 24'h050F50; // 331600
2003: data_ff <= 24'hFCF21B; // -200165
2004: data_ff <= 24'h01F23E; // 127550
2005: data_ff <= 24'hFEBFE2; // -81950
2006: data_ff <= 24'h00CA94; // 51860
2007: data_ff <= 24'hFF83A4; // -31836
2008: data_ff <= 24'h004927; // 18727
2009: data_ff <= 24'hFFD741; // -10431
2010: data_ff <= 24'h001533; // 5427
2011: data_ff <= 24'hFFF5E0; // -2592
2012: data_ff <= 24'h000455; // 1109
2013: data_ff <= 24'hFFFE68; // -408
2014: data_ff <= 24'h000075; // 117
2015: data_ff <= 24'hFFFFED; // -19
2016: data_ff <= 24'h3B4F88; // 3886984
2017: data_ff <= 24'hF62513; // -645869
2018: data_ff <= 24'h04F2D7; // 324311
2019: data_ff <= 24'hFD0409; // -195575
2020: data_ff <= 24'h01E68D; // 124557
2021: data_ff <= 24'hFEC782; // -79998
2022: data_ff <= 24'h00C5B4; // 50612
2023: data_ff <= 24'hFF86A8; // -31064
2024: data_ff <= 24'h00475F; // 18271
2025: data_ff <= 24'hFFD840; // -10176
2026: data_ff <= 24'h0014AF; // 5295
2027: data_ff <= 24'hFFF61F; // -2529
2028: data_ff <= 24'h00043A; // 1082
2029: data_ff <= 24'hFFFE72; // -398
2030: data_ff <= 24'h000073; // 115
2031: data_ff <= 24'hFFFFED; // -19
2032: data_ff <= 24'h3B9283; // 3904131
2033: data_ff <= 24'hF65915; // -632555
2034: data_ff <= 24'h04D5AD; // 316845
2035: data_ff <= 24'hFD165D; // -190883
2036: data_ff <= 24'h01DA9B; // 121499
2037: data_ff <= 24'hFECF4C; // -78004
2038: data_ff <= 24'h00C0B8; // 49336
2039: data_ff <= 24'hFF89BE; // -30274
2040: data_ff <= 24'h00458C; // 17804
2041: data_ff <= 24'hFFD945; // -9915
2042: data_ff <= 24'h001427; // 5159
2043: data_ff <= 24'hFFF65F; // -2465
2044: data_ff <= 24'h00041F; // 1055
2045: data_ff <= 24'hFFFE7C; // -388
2046: data_ff <= 24'h000070; // 112
2047: data_ff <= 24'hFFFFEE; // -18
2048: data_ff <= 24'h3BD3A2; // 3920802
2049: data_ff <= 24'hF68EA4; // -618844
2050: data_ff <= 24'h04B7D3; // 309203
2051: data_ff <= 24'hFD2918; // -186088
2052: data_ff <= 24'h01CE68; // 118376
2053: data_ff <= 24'hFED740; // -75968
2054: data_ff <= 24'h00BBA1; // 48033
2055: data_ff <= 24'hFF8CE4; // -29468
2056: data_ff <= 24'h0043AF; // 17327
2057: data_ff <= 24'hFFDA50; // -9648
2058: data_ff <= 24'h00139C; // 5020
2059: data_ff <= 24'hFFF6A1; // -2399
2060: data_ff <= 24'h000403; // 1027
2061: data_ff <= 24'hFFFE86; // -378
2062: data_ff <= 24'h00006D; // 109
2063: data_ff <= 24'hFFFFEE; // -18
2064: data_ff <= 24'h3C12E1; // 3936993
2065: data_ff <= 24'hF6C5BD; // -604739
2066: data_ff <= 24'h04994B; // 301387
2067: data_ff <= 24'hFD3C36; // -181194
2068: data_ff <= 24'h01C1F6; // 115190
2069: data_ff <= 24'hFEDF5E; // -73890
2070: data_ff <= 24'h00B670; // 46704
2071: data_ff <= 24'hFF901B; // -28645
2072: data_ff <= 24'h0041C7; // 16839
2073: data_ff <= 24'hFFDB60; // -9376
2074: data_ff <= 24'h00130E; // 4878
2075: data_ff <= 24'hFFF6E5; // -2331
2076: data_ff <= 24'h0003E6; // 998
2077: data_ff <= 24'hFFFE90; // -368
2078: data_ff <= 24'h00006B; // 107
2079: data_ff <= 24'hFFFFEE; // -18
2080: data_ff <= 24'h3C503C; // 3952700
2081: data_ff <= 24'hF6FE62; // -590238
2082: data_ff <= 24'h047A17; // 293399
2083: data_ff <= 24'hFD4FB8; // -176200
2084: data_ff <= 24'h01B546; // 111942
2085: data_ff <= 24'hFEE7A3; // -71773
2086: data_ff <= 24'h00B125; // 45349
2087: data_ff <= 24'hFF9362; // -27806
2088: data_ff <= 24'h003FD6; // 16342
2089: data_ff <= 24'hFFDC77; // -9097
2090: data_ff <= 24'h00127C; // 4732
2091: data_ff <= 24'hFFF72B; // -2261
2092: data_ff <= 24'h0003C8; // 968
2093: data_ff <= 24'hFFFE9B; // -357
2094: data_ff <= 24'h000068; // 104
2095: data_ff <= 24'hFFFFEF; // -17
2096: data_ff <= 24'h3C8BAF; // 3967919
2097: data_ff <= 24'hF73891; // -575343
2098: data_ff <= 24'h045A39; // 285241
2099: data_ff <= 24'hFD639B; // -171109
2100: data_ff <= 24'h01A859; // 108633
2101: data_ff <= 24'hFEF010; // -69616
2102: data_ff <= 24'h00ABC0; // 43968
2103: data_ff <= 24'hFF96BA; // -26950
2104: data_ff <= 24'h003DDB; // 15835
2105: data_ff <= 24'hFFDD93; // -8813
2106: data_ff <= 24'h0011E8; // 4584
2107: data_ff <= 24'hFFF772; // -2190
2108: data_ff <= 24'h0003AA; // 938
2109: data_ff <= 24'hFFFEA6; // -346
2110: data_ff <= 24'h000065; // 101
2111: data_ff <= 24'hFFFFEF; // -17
2112: data_ff <= 24'h3CC537; // 3982647
2113: data_ff <= 24'hF7744A; // -560054
2114: data_ff <= 24'h0439B2; // 276914
2115: data_ff <= 24'hFD77DF; // -165921
2116: data_ff <= 24'h019B2E; // 105262
2117: data_ff <= 24'hFEF8A5; // -67419
2118: data_ff <= 24'h00A642; // 42562
2119: data_ff <= 24'hFF9A22; // -26078
2120: data_ff <= 24'h003BD6; // 15318
2121: data_ff <= 24'hFFDEB5; // -8523
2122: data_ff <= 24'h001150; // 4432
2123: data_ff <= 24'hFFF7BA; // -2118
2124: data_ff <= 24'h00038B; // 907
2125: data_ff <= 24'hFFFEB1; // -335
2126: data_ff <= 24'h000061; // 97
2127: data_ff <= 24'hFFFFF0; // -16
2128: data_ff <= 24'h3CFCD0; // 3996880
2129: data_ff <= 24'hF7B18D; // -544371
2130: data_ff <= 24'h041885; // 268421
2131: data_ff <= 24'hFD8C81; // -160639
2132: data_ff <= 24'h018DC9; // 101833
2133: data_ff <= 24'hFF0160; // -65184
2134: data_ff <= 24'h00A0AB; // 41131
2135: data_ff <= 24'hFF9D99; // -25191
2136: data_ff <= 24'h0039C7; // 14791
2137: data_ff <= 24'hFFDFDD; // -8227
2138: data_ff <= 24'h0010B5; // 4277
2139: data_ff <= 24'hFFF805; // -2043
2140: data_ff <= 24'h00036B; // 875
2141: data_ff <= 24'hFFFEBD; // -323
2142: data_ff <= 24'h00005E; // 94
2143: data_ff <= 24'hFFFFF0; // -16
2144: data_ff <= 24'h3D3277; // 4010615
2145: data_ff <= 24'hF7F058; // -528296
2146: data_ff <= 24'h03F6B3; // 259763
2147: data_ff <= 24'hFDA181; // -155263
2148: data_ff <= 24'h018029; // 98345
2149: data_ff <= 24'hFF0A41; // -62911
2150: data_ff <= 24'h009AFB; // 39675
2151: data_ff <= 24'hFFA120; // -24288
2152: data_ff <= 24'h0037AF; // 14255
2153: data_ff <= 24'hFFE10A; // -7926
2154: data_ff <= 24'h001018; // 4120
2155: data_ff <= 24'hFFF850; // -1968
2156: data_ff <= 24'h00034B; // 843
2157: data_ff <= 24'hFFFEC9; // -311
2158: data_ff <= 24'h00005B; // 91
2159: data_ff <= 24'hFFFFF1; // -15
2160: data_ff <= 24'h3D6629; // 4023849
2161: data_ff <= 24'hF830AA; // -511830
2162: data_ff <= 24'h03D43E; // 250942
2163: data_ff <= 24'hFDB6DC; // -149796
2164: data_ff <= 24'h01724F; // 94799
2165: data_ff <= 24'hFF1346; // -60602
2166: data_ff <= 24'h009534; // 38196
2167: data_ff <= 24'hFFA4B7; // -23369
2168: data_ff <= 24'h00358D; // 13709
2169: data_ff <= 24'hFFE23D; // -7619
2170: data_ff <= 24'h000F77; // 3959
2171: data_ff <= 24'hFFF89E; // -1890
2172: data_ff <= 24'h00032A; // 810
2173: data_ff <= 24'hFFFED5; // -299
2174: data_ff <= 24'h000057; // 87
2175: data_ff <= 24'hFFFFF1; // -15
2176: data_ff <= 24'h3D97E2; // 4036578
2177: data_ff <= 24'hF87283; // -494973
2178: data_ff <= 24'h03B12A; // 241962
2179: data_ff <= 24'hFDCC92; // -144238
2180: data_ff <= 24'h01643D; // 91197
2181: data_ff <= 24'hFF1C71; // -58255
2182: data_ff <= 24'h008F55; // 36693
2183: data_ff <= 24'hFFA85C; // -22436
2184: data_ff <= 24'h003362; // 13154
2185: data_ff <= 24'hFFE375; // -7307
2186: data_ff <= 24'h000ED3; // 3795
2187: data_ff <= 24'hFFF8ED; // -1811
2188: data_ff <= 24'h000308; // 776
2189: data_ff <= 24'hFFFEE2; // -286
2190: data_ff <= 24'h000054; // 84
2191: data_ff <= 24'hFFFFF2; // -14
2192: data_ff <= 24'h3DC7A0; // 4048800
2193: data_ff <= 24'hF8B5E1; // -477727
2194: data_ff <= 24'h038D77; // 232823
2195: data_ff <= 24'hFDE2A0; // -138592
2196: data_ff <= 24'h0155F4; // 87540
2197: data_ff <= 24'hFF25BF; // -55873
2198: data_ff <= 24'h00895F; // 35167
2199: data_ff <= 24'hFFAC10; // -21488
2200: data_ff <= 24'h00312F; // 12591
2201: data_ff <= 24'hFFE4B2; // -6990
2202: data_ff <= 24'h000E2C; // 3628
2203: data_ff <= 24'hFFF93D; // -1731
2204: data_ff <= 24'h0002E5; // 741
2205: data_ff <= 24'hFFFEEE; // -274
2206: data_ff <= 24'h000050; // 80
2207: data_ff <= 24'hFFFFF2; // -14
2208: data_ff <= 24'h3DF55F; // 4060511
2209: data_ff <= 24'hF8FAC4; // -460092
2210: data_ff <= 24'h036929; // 223529
2211: data_ff <= 24'hFDF905; // -132859
2212: data_ff <= 24'h014775; // 83829
2213: data_ff <= 24'hFF2F30; // -53456
2214: data_ff <= 24'h008352; // 33618
2215: data_ff <= 24'hFFAFD2; // -20526
2216: data_ff <= 24'h002EF2; // 12018
2217: data_ff <= 24'hFFE5F4; // -6668
2218: data_ff <= 24'h000D83; // 3459
2219: data_ff <= 24'hFFF98F; // -1649
2220: data_ff <= 24'h0002C2; // 706
2221: data_ff <= 24'hFFFEFC; // -260
2222: data_ff <= 24'h00004C; // 76
2223: data_ff <= 24'hFFFFF3; // -13
2224: data_ff <= 24'h3E211D; // 4071709
2225: data_ff <= 24'hF9412A; // -442070
2226: data_ff <= 24'h034442; // 214082
2227: data_ff <= 24'hFE0FBF; // -127041
2228: data_ff <= 24'h0138C0; // 80064
2229: data_ff <= 24'hFF38C3; // -51005
2230: data_ff <= 24'h007D2F; // 32047
2231: data_ff <= 24'hFFB3A2; // -19550
2232: data_ff <= 24'h002CAD; // 11437
2233: data_ff <= 24'hFFE73C; // -6340
2234: data_ff <= 24'h000CD6; // 3286
2235: data_ff <= 24'hFFF9E2; // -1566
2236: data_ff <= 24'h00029E; // 670
2237: data_ff <= 24'hFFFF09; // -247
2238: data_ff <= 24'h000048; // 72
2239: data_ff <= 24'hFFFFF4; // -12
2240: data_ff <= 24'h3E4AD7; // 4082391
2241: data_ff <= 24'hF98910; // -423664
2242: data_ff <= 24'h031EC4; // 204484
2243: data_ff <= 24'hFE26CC; // -121140
2244: data_ff <= 24'h0129D8; // 76248
2245: data_ff <= 24'hFF4278; // -48520
2246: data_ff <= 24'h0076F6; // 30454
2247: data_ff <= 24'hFFB780; // -18560
2248: data_ff <= 24'h002A5F; // 10847
2249: data_ff <= 24'hFFE889; // -6007
2250: data_ff <= 24'h000C27; // 3111
2251: data_ff <= 24'hFFFA37; // -1481
2252: data_ff <= 24'h000279; // 633
2253: data_ff <= 24'hFFFF17; // -233
2254: data_ff <= 24'h000044; // 68
2255: data_ff <= 24'hFFFFF4; // -12
2256: data_ff <= 24'h3E728B; // 4092555
2257: data_ff <= 24'hF9D277; // -404873
2258: data_ff <= 24'h02F8B1; // 194737
2259: data_ff <= 24'hFE3E2B; // -115157
2260: data_ff <= 24'h011ABD; // 72381
2261: data_ff <= 24'hFF4C4E; // -46002
2262: data_ff <= 24'h0070A8; // 28840
2263: data_ff <= 24'hFFBB6C; // -17556
2264: data_ff <= 24'h002809; // 10249
2265: data_ff <= 24'hFFE9DA; // -5670
2266: data_ff <= 24'h000B75; // 2933
2267: data_ff <= 24'hFFFA8D; // -1395
2268: data_ff <= 24'h000253; // 595
2269: data_ff <= 24'hFFFF25; // -219
2270: data_ff <= 24'h000040; // 64
2271: data_ff <= 24'hFFFFF5; // -11
2272: data_ff <= 24'h3E9836; // 4102198
2273: data_ff <= 24'hFA1D5B; // -385701
2274: data_ff <= 24'h02D20E; // 184846
2275: data_ff <= 24'hFE55DA; // -109094
2276: data_ff <= 24'h010B71; // 68465
2277: data_ff <= 24'hFF5643; // -43453
2278: data_ff <= 24'h006A46; // 27206
2279: data_ff <= 24'hFFBF65; // -16539
2280: data_ff <= 24'h0025AB; // 9643
2281: data_ff <= 24'hFFEB31; // -5327
2282: data_ff <= 24'h000AC0; // 2752
2283: data_ff <= 24'hFFFAE5; // -1307
2284: data_ff <= 24'h00022D; // 557
2285: data_ff <= 24'hFFFF33; // -205
2286: data_ff <= 24'h00003C; // 60
2287: data_ff <= 24'hFFFFF6; // -10
2288: data_ff <= 24'h3EBBD6; // 4111318
2289: data_ff <= 24'hFA69BC; // -366148
2290: data_ff <= 24'h02AADB; // 174811
2291: data_ff <= 24'hFE6DD7; // -102953
2292: data_ff <= 24'h00FBF5; // 64501
2293: data_ff <= 24'hFF6057; // -40873
2294: data_ff <= 24'h0063CF; // 25551
2295: data_ff <= 24'hFFC36A; // -15510
2296: data_ff <= 24'h002344; // 9028
2297: data_ff <= 24'hFFEC8C; // -4980
2298: data_ff <= 24'h000A09; // 2569
2299: data_ff <= 24'hFFFB3E; // -1218
2300: data_ff <= 24'h000207; // 519
2301: data_ff <= 24'hFFFF41; // -191
2302: data_ff <= 24'h000038; // 56
2303: data_ff <= 24'hFFFFF6; // -10
2304: data_ff <= 24'h3EDD68; // 4119912
2305: data_ff <= 24'hFAB798; // -346216
2306: data_ff <= 24'h02831C; // 164636
2307: data_ff <= 24'hFE8620; // -96736
2308: data_ff <= 24'h00EC4A; // 60490
2309: data_ff <= 24'hFF6A89; // -38263
2310: data_ff <= 24'h005D45; // 23877
2311: data_ff <= 24'hFFC77C; // -14468
2312: data_ff <= 24'h0020D6; // 8406
2313: data_ff <= 24'hFFEDEC; // -4628
2314: data_ff <= 24'h00094F; // 2383
2315: data_ff <= 24'hFFFB98; // -1128
2316: data_ff <= 24'h0001DF; // 479
2317: data_ff <= 24'hFFFF50; // -176
2318: data_ff <= 24'h000033; // 51
2319: data_ff <= 24'hFFFFF7; // -9
2320: data_ff <= 24'h3EFCEC; // 4127980
2321: data_ff <= 24'hFB06EB; // -325909
2322: data_ff <= 24'h025AD4; // 154324
2323: data_ff <= 24'hFE9EB2; // -90446
2324: data_ff <= 24'h00DC72; // 56434
2325: data_ff <= 24'hFF74D9; // -35623
2326: data_ff <= 24'h0056A8; // 22184
2327: data_ff <= 24'hFFCB9A; // -13414
2328: data_ff <= 24'h001E61; // 7777
2329: data_ff <= 24'hFFEF50; // -4272
2330: data_ff <= 24'h000892; // 2194
2331: data_ff <= 24'hFFFBF4; // -1036
2332: data_ff <= 24'h0001B7; // 439
2333: data_ff <= 24'hFFFF5F; // -161
2334: data_ff <= 24'h00002F; // 47
2335: data_ff <= 24'hFFFFF8; // -8
2336: data_ff <= 24'h3F1A5E; // 4135518
2337: data_ff <= 24'hFB57B5; // -305227
2338: data_ff <= 24'h023206; // 143878
2339: data_ff <= 24'hFEB78D; // -84083
2340: data_ff <= 24'h00CC6E; // 52334
2341: data_ff <= 24'hFF7F45; // -32955
2342: data_ff <= 24'h004FF8; // 20472
2343: data_ff <= 24'hFFCFC5; // -12347
2344: data_ff <= 24'h001BE4; // 7140
2345: data_ff <= 24'hFFF0B8; // -3912
2346: data_ff <= 24'h0007D3; // 2003
2347: data_ff <= 24'hFFFC51; // -943
2348: data_ff <= 24'h00018E; // 398
2349: data_ff <= 24'hFFFF6F; // -145
2350: data_ff <= 24'h00002A; // 42
2351: data_ff <= 24'hFFFFF9; // -7
2352: data_ff <= 24'h3F35BD; // 4142525
2353: data_ff <= 24'hFBA9F3; // -284173
2354: data_ff <= 24'h0208B4; // 133300
2355: data_ff <= 24'hFED0AD; // -77651
2356: data_ff <= 24'h00BC3E; // 48190
2357: data_ff <= 24'hFF89CD; // -30259
2358: data_ff <= 24'h004937; // 18743
2359: data_ff <= 24'hFFD3FA; // -11270
2360: data_ff <= 24'h001960; // 6496
2361: data_ff <= 24'hFFF225; // -3547
2362: data_ff <= 24'h000712; // 1810
2363: data_ff <= 24'hFFFCAF; // -849
2364: data_ff <= 24'h000165; // 357
2365: data_ff <= 24'hFFFF7E; // -130
2366: data_ff <= 24'h000025; // 37
2367: data_ff <= 24'hFFFFFA; // -6
2368: data_ff <= 24'h3F4F08; // 4149000
2369: data_ff <= 24'hFBFDA2; // -262750
2370: data_ff <= 24'h01DEE2; // 122594
2371: data_ff <= 24'hFEEA12; // -71150
2372: data_ff <= 24'h00ABE6; // 44006
2373: data_ff <= 24'hFF946F; // -27537
2374: data_ff <= 24'h004264; // 16996
2375: data_ff <= 24'hFFD83B; // -10181
2376: data_ff <= 24'h0016D5; // 5845
2377: data_ff <= 24'hFFF396; // -3178
2378: data_ff <= 24'h00064E; // 1614
2379: data_ff <= 24'hFFFD0F; // -753
2380: data_ff <= 24'h00013B; // 315
2381: data_ff <= 24'hFFFF8E; // -114
2382: data_ff <= 24'h000021; // 33
2383: data_ff <= 24'hFFFFFB; // -5
2384: data_ff <= 24'h3F663D; // 4154941
2385: data_ff <= 24'hFC52C1; // -240959
2386: data_ff <= 24'h01B493; // 111763
2387: data_ff <= 24'hFF03B8; // -64584
2388: data_ff <= 24'h009B65; // 39781
2389: data_ff <= 24'hFF9F2B; // -24789
2390: data_ff <= 24'h003B81; // 15233
2391: data_ff <= 24'hFFDC86; // -9082
2392: data_ff <= 24'h001443; // 5187
2393: data_ff <= 24'hFFF50B; // -2805
2394: data_ff <= 24'h000588; // 1416
2395: data_ff <= 24'hFFFD70; // -656
2396: data_ff <= 24'h000111; // 273
2397: data_ff <= 24'hFFFF9E; // -98
2398: data_ff <= 24'h00001C; // 28
2399: data_ff <= 24'hFFFFFC; // -4
2400: data_ff <= 24'h3F7B5A; // 4160346
2401: data_ff <= 24'hFCA94C; // -218804
2402: data_ff <= 24'h0189C9; // 100809
2403: data_ff <= 24'hFF1D9D; // -57955
2404: data_ff <= 24'h008ABE; // 35518
2405: data_ff <= 24'hFFA9FF; // -22017
2406: data_ff <= 24'h00348D; // 13453
2407: data_ff <= 24'hFFE0DC; // -7972
2408: data_ff <= 24'h0011AB; // 4523
2409: data_ff <= 24'hFFF684; // -2428
2410: data_ff <= 24'h0004C0; // 1216
2411: data_ff <= 24'hFFFDD2; // -558
2412: data_ff <= 24'h0000E6; // 230
2413: data_ff <= 24'hFFFFAF; // -81
2414: data_ff <= 24'h000017; // 23
2415: data_ff <= 24'hFFFFFC; // -4
2416: data_ff <= 24'h3F8E5E; // 4165214
2417: data_ff <= 24'hFD0141; // -196287
2418: data_ff <= 24'h015E89; // 89737
2419: data_ff <= 24'hFF37C0; // -51264
2420: data_ff <= 24'h0079F2; // 31218
2421: data_ff <= 24'hFFB4EB; // -19221
2422: data_ff <= 24'h002D8A; // 11658
2423: data_ff <= 24'hFFE53C; // -6852
2424: data_ff <= 24'h000F0D; // 3853
2425: data_ff <= 24'hFFF801; // -2047
2426: data_ff <= 24'h0003F5; // 1013
2427: data_ff <= 24'hFFFE35; // -459
2428: data_ff <= 24'h0000BA; // 186
2429: data_ff <= 24'hFFFFBF; // -65
2430: data_ff <= 24'h000012; // 18
2431: data_ff <= 24'hFFFFFD; // -3
2432: data_ff <= 24'h3F9F48; // 4169544
2433: data_ff <= 24'hFD5A9E; // -173410
2434: data_ff <= 24'h0132D5; // 78549
2435: data_ff <= 24'hFF521F; // -44513
2436: data_ff <= 24'h006902; // 26882
2437: data_ff <= 24'hFFBFEF; // -16401
2438: data_ff <= 24'h002678; // 9848
2439: data_ff <= 24'hFFE9A5; // -5723
2440: data_ff <= 24'h000C68; // 3176
2441: data_ff <= 24'hFFF982; // -1662
2442: data_ff <= 24'h000329; // 809
2443: data_ff <= 24'hFFFE99; // -359
2444: data_ff <= 24'h00008E; // 142
2445: data_ff <= 24'hFFFFD0; // -48
2446: data_ff <= 24'h00000C; // 12
2447: data_ff <= 24'hFFFFFE; // -2
2448: data_ff <= 24'h3FAE18; // 4173336
2449: data_ff <= 24'hFDB55E; // -150178
2450: data_ff <= 24'h0106B1; // 67249
2451: data_ff <= 24'hFF6CB6; // -37706
2452: data_ff <= 24'h0057F0; // 22512
2453: data_ff <= 24'hFFCB08; // -13560
2454: data_ff <= 24'h001F58; // 8024
2455: data_ff <= 24'hFFEE18; // -4584
2456: data_ff <= 24'h0009BE; // 2494
2457: data_ff <= 24'hFFFB06; // -1274
2458: data_ff <= 24'h00025A; // 602
2459: data_ff <= 24'hFFFEFE; // -258
2460: data_ff <= 24'h000061; // 97
2461: data_ff <= 24'hFFFFE1; // -31
2462: data_ff <= 24'h000007; // 7
2463: data_ff <= 24'hFFFFFF; // -1
2464: data_ff <= 24'h3FBACB; // 4176587
2465: data_ff <= 24'hFE1180; // -126592
2466: data_ff <= 24'h00DA20; // 55840
2467: data_ff <= 24'hFF8783; // -30845
2468: data_ff <= 24'h0046BE; // 18110
2469: data_ff <= 24'hFFD635; // -10699
2470: data_ff <= 24'h00182A; // 6186
2471: data_ff <= 24'hFFF293; // -3437
2472: data_ff <= 24'h00070E; // 1806
2473: data_ff <= 24'hFFFC8D; // -883
2474: data_ff <= 24'h000189; // 393
2475: data_ff <= 24'hFFFF65; // -155
2476: data_ff <= 24'h000034; // 52
2477: data_ff <= 24'hFFFFF3; // -13
2478: data_ff <= 24'h000002; // 2
2479: data_ff <= 24'h000000; // 0
2480: data_ff <= 24'h3FC561; // 4179297
2481: data_ff <= 24'hFE6F00; // -102656
2482: data_ff <= 24'h00AD25; // 44325
2483: data_ff <= 24'hFFA285; // -23931
2484: data_ff <= 24'h00356C; // 13676
2485: data_ff <= 24'hFFE177; // -7817
2486: data_ff <= 24'h0010F0; // 4336
2487: data_ff <= 24'hFFF717; // -2281
2488: data_ff <= 24'h000459; // 1113
2489: data_ff <= 24'hFFFE18; // -488
2490: data_ff <= 24'h0000B7; // 183
2491: data_ff <= 24'hFFFFCC; // -52
2492: data_ff <= 24'h000006; // 6
2493: data_ff <= 24'h000004; // 4
2494: data_ff <= 24'hFFFFFD; // -3
2495: data_ff <= 24'h000001; // 1
2496: data_ff <= 24'h3FCDDB; // 4181467
2497: data_ff <= 24'hFECDDB; // -78373
2498: data_ff <= 24'h007FC5; // 32709
2499: data_ff <= 24'hFFBDB9; // -16967
2500: data_ff <= 24'h0023FD; // 9213
2501: data_ff <= 24'hFFECCB; // -4917
2502: data_ff <= 24'h0009A9; // 2473
2503: data_ff <= 24'hFFFBA3; // -1117
2504: data_ff <= 24'h00019E; // 414
2505: data_ff <= 24'hFFFFA6; // -90
2506: data_ff <= 24'hFFFFE3; // -29
2507: data_ff <= 24'h000034; // 52
2508: data_ff <= 24'hFFFFD8; // -40
2509: data_ff <= 24'h000015; // 21
2510: data_ff <= 24'hFFFFF8; // -8
2511: data_ff <= 24'h000002; // 2
2512: data_ff <= 24'h3FD436; // 4183094
2513: data_ff <= 24'hFF2E0E; // -53746
2514: data_ff <= 24'h005203; // 20995
2515: data_ff <= 24'hFFD91D; // -9955
2516: data_ff <= 24'h001273; // 4723
2517: data_ff <= 24'hFFF831; // -1999
2518: data_ff <= 24'h000256; // 598
2519: data_ff <= 24'h000035; // 53
2520: data_ff <= 24'hFFFEE0; // -288
2521: data_ff <= 24'h000135; // 309
2522: data_ff <= 24'hFFFF0D; // -243
2523: data_ff <= 24'h00009D; // 157
2524: data_ff <= 24'hFFFFAA; // -86
2525: data_ff <= 24'h000027; // 39
2526: data_ff <= 24'hFFFFF2; // -14
2527: data_ff <= 24'h000003; // 3
2528: data_ff <= 24'h3FD873; // 4184179
2529: data_ff <= 24'hFF8F95; // -28779
2530: data_ff <= 24'h0023E3; // 9187
2531: data_ff <= 24'hFFF4AD; // -2899
2532: data_ff <= 24'h0000CD; // 205
2533: data_ff <= 24'h0003A7; // 935
2534: data_ff <= 24'hFFFAFA; // -1286
2535: data_ff <= 24'h0004CF; // 1231
2536: data_ff <= 24'hFFFC1C; // -996
2537: data_ff <= 24'h0002C9; // 713
2538: data_ff <= 24'hFFFE35; // -459
2539: data_ff <= 24'h000108; // 264
2540: data_ff <= 24'hFFFF7A; // -134
2541: data_ff <= 24'h00003A; // 58
2542: data_ff <= 24'hFFFFEC; // -20
2543: data_ff <= 24'h000004; // 4
2544: data_ff <= 24'h3FDA92; // 4184722
2545: data_ff <= 24'hFFF26C; // -3476
2546: data_ff <= 24'hFFF568; // -2712
2547: data_ff <= 24'h001067; // 4199
2548: data_ff <= 24'hFFEF11; // -4335
2549: data_ff <= 24'h000F2D; // 3885
2550: data_ff <= 24'hFFF392; // -3182
2551: data_ff <= 24'h000971; // 2417
2552: data_ff <= 24'hFFF954; // -1708
2553: data_ff <= 24'h000460; // 1120
2554: data_ff <= 24'hFFFD5C; // -676
2555: data_ff <= 24'h000173; // 371
2556: data_ff <= 24'hFFFF4A; // -182
2557: data_ff <= 24'h00004C; // 76
2558: data_ff <= 24'hFFFFE6; // -26
2559: data_ff <= 24'h000005; // 5
default: data_ff <= 0;
endcase
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
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// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
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// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_0_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:36:27 $
// \ \ / \ Date Created : Fri Jan 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : QDRII+ SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_0_mig #
(
parameter MEM_TYPE = "QDR2PLUS",
// # of CK/CK# outputs to memory.
parameter DATA_WIDTH = 36,
// # of DQ (data)
parameter BW_WIDTH = 4,
// # of byte writes (data_width/9)
parameter ADDR_WIDTH = 19,
// Address Width
parameter NUM_DEVICES = 1,
// # of memory components connected
parameter MEM_RD_LATENCY = 2.5,
// Value of Memory part read latency
parameter CPT_CLK_CQ_ONLY = "TRUE",
// whether CQ and its inverse are used for the data capture
parameter INTER_BANK_SKEW = 0,
// Clock skew between two adjacent banks
parameter PHY_CONTROL_MASTER_BANK = 1,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_LEN = 4,
// Burst Length of the design (4 or 2).
parameter FIXED_LATENCY_MODE = 0,
// Enable Fixed Latency
parameter PHY_LATENCY = 0,
// Value for Fixed Latency Mode
// Expected Latency
//***************************************************************************
// The following parameters are multiplier and divisor factors for MMCM.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 5000,
// Input Clock Period
parameter CLKFBOUT_MULT = 4,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 32,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 4,
// VCO output divisor for PLL output clock (CLKOUT3)
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b1100,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b1111,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b1111,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
// this parameter specifies the location of the capture clock with respect
// to read data.
// Each byte refers to the information needed for data capture in the corresponding byte lane
// Lower order nibble - is either 4'h1 or 4'h2. This refers to the capture clock in T1 or T2 byte lane
// Higher order nibble - 4'h0 refers to clock present in the bank below the read data,
// 4'h1 refers to clock present in the same bank as the read data,
// 4'h2 refers to clock present in the bank above the read data.
parameter CPT_CLK_SEL_B0 = 32'h11_11_11_11,
parameter CPT_CLK_SEL_B1 = 32'h00_00_00_00,
parameter CPT_CLK_SEL_B2 = 32'h00_00_00_00,
parameter PHY_0_BITLANES = 48'hFF8_FF1_D3F_EFC,
// The bits used inside the Bank0 out of 48 pins.
parameter PHY_1_BITLANES = 48'h3FE_FFE_CFF_FFC,
// The bits used inside the Bank1 out of 48 pins.
parameter PHY_2_BITLANES = 48'hEFE_FFD_000_000,
// The bits used inside the Bank2 out of 48 pins.
parameter PHY_3_BITLANES = 48'h000_000_000_000,
// The bits used inside the Bank3 out of 48 pins.
parameter PHY_4_BITLANES = 48'h000_000_000_000,
// The bits used inside the Bank4 out of 48 pins.
// Differentiates the INPUT and OUTPUT bytelates (1-input, 0-output)
parameter BYTE_GROUP_TYPE_B0 = 4'b1111,
parameter BYTE_GROUP_TYPE_B1 = 4'b0000,
parameter BYTE_GROUP_TYPE_B2 = 4'b0000,
parameter BYTE_GROUP_TYPE_B3 = 4'b0000,
parameter BYTE_GROUP_TYPE_B4 = 4'b0000,
// mapping for K/K# clocks. This parameter needs to have an 8-bit value per component
// since the phy drives a K/K# clock pair to each memory it interfaces to. A 3 component
// interface is supported for now. This parameter needs to be used in conjunction with
// NUM_DEVICES parameter which provides information on the number. of components being
// interfaced to.
// the 8 bit for each component is defined as follows:
// [7:4] - bank number ; [3:0] - byte lane number
parameter K_MAP = 48'h00_00_00_00_00_13,
// mapping for CQ/CQ# clocks. This parameter needs to have an 4-bit value per component
// since the phy drives a CQ/CQ# clock pair to each memory it interfaces to. A 3 component
// interface is supported for now. This parameter needs to be used in conjunction with
// NUM_DEVICES parameter which provides information on the number. of components being
// interfaced to.
// the 4 bit for each component is defined as follows:
// [3:0] - bank number
parameter CQ_MAP = 48'h00_00_00_00_00_01,
//**********************************************************************************************
// Each of the following parameter contains the byte_lane and bit position information for
// the address/control, data write and data read signals. Each bit has 12 bits and the details are
// [3:0] - Bit position within a byte lane .
// [7:4] - Byte lane position within a bank. [5:4] have the byte lane position and others reserved.
// [11:8] - Bank position. [10:8] have the bank position. [11] tied to zero .
//**********************************************************************************************
// Mapping for address and control signals.
parameter RD_MAP = 12'h220, // Mapping for read enable signal
parameter WR_MAP = 12'h222, // Mapping for write enable signal
// Mapping for address signals. Supports upto 22 bits of address bits (22*12)
parameter ADD_MAP = 264'h000_000_000_223_236_22B_23B_235_234_225_229_224_232_228_23A_231_237_239_233_227_22A_226,
// Mapping for the byte lanes used for address/control signals. Supports a maximum of 3 banks.
parameter ADDR_CTL_MAP = 32'h00_00_23_22,
// Mapping for data WRITE signals
// Mapping for data write bytes (9*12)
parameter D0_MAP = 108'h137_134_136_135_132_133_131_138_139, //byte 0
parameter D1_MAP = 108'h121_124_125_122_126_127_12A_123_12B, //byte 1
parameter D2_MAP = 108'h102_103_108_104_106_105_107_10A_10B, //byte 2
parameter D3_MAP = 108'h116_117_115_11A_114_113_111_112_110, //byte 3
parameter D4_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 4
parameter D5_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 5
parameter D6_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 6
parameter D7_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 7
// Mapping for byte write signals (8*12)
parameter BW_MAP = 84'h000_000_000_11B_109_128_129,
// Mapping for data READ signals
// Mapping for data read bytes (9*12)
parameter Q0_MAP = 108'h033_039_034_036_035_03A_03B_037_038, //byte 0
parameter Q1_MAP = 108'h029_020_028_026_027_02A_02B_024_025, //byte 1
parameter Q2_MAP = 108'h015_014_01A_01B_011_010_013_012_018, //byte 2
parameter Q3_MAP = 108'h00B_003_007_002_005_004_009_006_00A, //byte 3
parameter Q4_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 4
parameter Q5_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 5
parameter Q6_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 6
parameter Q7_MAP = 108'h000_000_000_000_000_000_000_000_000, //byte 7
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IODELAY_HP_MODE = "ON",
// to phy_top
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter TCQ = 100,
parameter IODELAY_GRP = "MIG_7SERIES_0_IODELAY_MIG",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
parameter SYSCLK_TYPE = "SINGLE_ENDED",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
// Number of taps in target IDELAY
parameter integer DEVICE_TAPS = 32,
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter CLK_PERIOD = 2500,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "FALSE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// Wait period for the read strobe (CQ) to become stable
//***************************************************************************
parameter CLK_STABLE = (20*1000*1000/(CLK_PERIOD*2)),
// Cycles till CQ/CQ# is stable
//***************************************************************************
// Debug parameter
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Single-ended system clock
input sys_clk_i,
input [NUM_DEVICES-1:0] qdriip_cq_p, //Memory Interface
input [NUM_DEVICES-1:0] qdriip_cq_n,
input [DATA_WIDTH-1:0] qdriip_q,
output wire [NUM_DEVICES-1:0] qdriip_k_p,
output wire [NUM_DEVICES-1:0] qdriip_k_n,
output wire [DATA_WIDTH-1:0] qdriip_d,
output wire [ADDR_WIDTH-1:0] qdriip_sa,
output wire qdriip_w_n,
output wire qdriip_r_n,
output wire [BW_WIDTH-1:0] qdriip_bw_n,
output wire qdriip_dll_off_n,
// User Interface signals of Channel-0
input app_wr_cmd0,
input [ADDR_WIDTH-1:0] app_wr_addr0,
input [(DATA_WIDTH*BURST_LEN)-1:0] app_wr_data0,
input [(BW_WIDTH*BURST_LEN)-1:0] app_wr_bw_n0,
input app_rd_cmd0,
input [ADDR_WIDTH-1:0] app_rd_addr0,
output wire app_rd_valid0,
output wire [(DATA_WIDTH*BURST_LEN)-1:0] app_rd_data0,
// User Interface signals of Channel-1. It is useful only for BL2 designs.
// All inputs of Channel-1 can be grounded for BL4 designs.
input app_wr_cmd1,
input [ADDR_WIDTH-1:0] app_wr_addr1,
input [(DATA_WIDTH*2)-1:0] app_wr_data1,
input [(BW_WIDTH*2)-1:0] app_wr_bw_n1,
input app_rd_cmd1,
input [ADDR_WIDTH-1:0] app_rd_addr1,
output wire app_rd_valid1,
output wire [(DATA_WIDTH*2)-1:0] app_rd_data1,
output wire clk,
output wire rst_clk,
output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
// clogb2 function - ceiling of log base 2
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
localparam integer N_DATA_LANES = DATA_WIDTH / 9;
// Number of bits needed to represent DEVICE_TAPS
localparam integer TAP_BITS = clogb2(DEVICE_TAPS - 1);
// Number of bits to represent number of cq/cq#'s
localparam integer CQ_BITS = clogb2(DATA_WIDTH/9 - 1);
// Number of bits needed to represent number of q's
localparam integer Q_BITS = clogb2(DATA_WIDTH - 1);
// Wire declarations
wire freq_refclk ;
wire mem_refclk ;
wire pll_locked ;
wire sync_pulse;
wire rst_wr_clk;
wire ref_dll_lock;
wire rst_phaser_ref;
wire cmp_err; // Reserve for ERROR from test bench
wire [CQ_BITS-1:0] dbg_byte_sel;
wire [Q_BITS-1:0] dbg_bit_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire dbg_po_f_inc;
wire dbg_po_f_dec;
wire dbg_idel_up_all;
wire dbg_idel_down_all;
wire dbg_idel_up;
wire dbg_idel_down;
wire [(TAP_BITS*DATA_WIDTH)-1:0] dbg_idel_tap_cnt;
wire [TAP_BITS-1:0] dbg_idel_tap_cnt_sel;
wire [2:0] dbg_select_rdata;
//wire [5:0] dbg_pi_tap_cnt;
//wire [5:0] dbg_po_tap_cnt;
//wire [(TAP_BITS*DATA_WIDTH)-1:0] dbg_cpt_first_edge_cnt;
//wire [(TAP_BITS*DATA_WIDTH)-1:0] dbg_cpt_second_edge_cnt;
//ChipScope Readpath Debug Signals
wire [1:0] dbg_phy_wr_cmd_n; //cs debug - wr command
wire [2:0] dbg_byte_sel_cnt;
wire [(ADDR_WIDTH*4)-1:0] dbg_phy_addr; //cs debug - address
wire [1:0] dbg_phy_rd_cmd_n; //cs debug - rd command
wire [(DATA_WIDTH*4)-1:0] dbg_phy_wr_data; //cs debug - wr data
wire dbg_phy_init_wr_only;
wire dbg_phy_init_rd_only;
wire [8:0] dbg_po_counter_read_val;
wire vio_sel_rise_chk;
wire [(TAP_BITS*N_DATA_LANES)-1:0] dbg_cq_tapcnt; // tap count for each cq
wire [(TAP_BITS*N_DATA_LANES)-1:0] dbg_cqn_tapcnt; // tap count for each cq#
wire [CQ_BITS-1:0] dbg_cq_num; // current cq/cq# being calibrated
wire [4:0] dbg_valid_lat; // latency of the system
wire [N_DATA_LANES-1:0] dbg_inc_latency; // increase latency for dcb
wire [(4*DATA_WIDTH)-1:0] dbg_dcb_din; // dcb data in
wire [(4*DATA_WIDTH)-1:0] dbg_dcb_dout; // dcb data out
wire [N_DATA_LANES-1:0] dbg_error_max_latency; // stage 2 cal max latency error
wire dbg_error_adj_latency; // stage 2 cal latency adjustment error
wire [DATA_WIDTH-1:0] dbg_align_rd0;
wire [DATA_WIDTH-1:0] dbg_align_rd1;
wire [DATA_WIDTH-1:0] dbg_align_fd0;
wire [DATA_WIDTH-1:0] dbg_align_fd1;
wire [8:0] dbg_align_rd0_r;
wire [8:0] dbg_align_rd1_r;
wire [8:0] dbg_align_fd0_r;
wire [8:0] dbg_align_fd1_r;
reg rd_valid0_r;
reg rd_valid1_r;
wire [7:0] dbg_phy_status;
wire dbg_SM_No_Pause;
wire dbg_SM_en;
//wire [(TAP_BITS*DATA_WIDTH)-1:0] dbg_q_tapcnt; // tap count for each q
//wire [Q_BITS-1:0] dbg_q_bit; // current q being calibrated
wire [(DATA_WIDTH*2)-1:0] mux_wr_data0;
wire [(DATA_WIDTH*2)-1:0] mux_wr_data1;
wire [(BW_WIDTH*2)-1:0] mux_wr_bw_n0;
wire [(BW_WIDTH*2)-1:0] mux_wr_bw_n1;
wire [(DATA_WIDTH*2)-1:0] rd_data0;
wire [(DATA_WIDTH*2)-1:0] rd_data1;
wire sys_clk_p;
wire sys_clk_n;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire clk_ref_i;
wire clk_ref_in;
wire iodelay_ctrl_rdy;
wire clk_ref;
wire sys_rst_o;
wire [5:0] dbg_pi_counter_read_val;
wire [255:0] dbg_rd_stage1_cal;
wire [127:0] dbg_stage2_cal;
wire [255:0] dbg_wr_init;
//***************************************************************************
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
assign clk_ref_i = 1'b0;
generate
if (BURST_LEN == 4) begin: mux_data_bl4
assign mux_wr_data0 = app_wr_data0[DATA_WIDTH*4-1:DATA_WIDTH*2];
assign mux_wr_bw_n0 = app_wr_bw_n0[BW_WIDTH*4-1:BW_WIDTH*2];
end else begin: mux_data_bl2
assign mux_wr_data0 = app_wr_data0;
assign mux_wr_bw_n0 = app_wr_bw_n0;
end
endgenerate
assign mux_wr_data1 = (BURST_LEN == 4) ? app_wr_data0[DATA_WIDTH*2-1:0] : app_wr_data1;
assign mux_wr_bw_n1 = (BURST_LEN == 4) ? app_wr_bw_n0[BW_WIDTH*2-1:0] : app_wr_bw_n1;
assign app_rd_data0 = (BURST_LEN == 4) ? {rd_data0, rd_data1} : rd_data0;
assign app_rd_data1 = rd_data1;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v2_0_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP (IODELAY_GRP),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.clk_ref (clk_ref),
.sys_rst (sys_rst)
);
mig_7series_v2_0_clk_ibuf#
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
mig_7series_v2_0_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_infrastructure
(
// Outputs
.rstdiv0 (rst_wr_clk),
.clk (clk),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.auxout_clk (),
.ui_addn_clk_0 (),
.ui_addn_clk_1 (),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.pll_locked (pll_locked),
.mmcm_locked (),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v2_0_qdr_phy_top #
(
.MEM_TYPE (MEM_TYPE), //Memory Type (QDR2PLUS, QDR2)
.CLK_PERIOD (CLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.RST_ACT_LOW (RST_ACT_LOW),
.CLK_STABLE (CLK_STABLE ), //Cycles till CQ/CQ# is stable
.ADDR_WIDTH (ADDR_WIDTH ), //Adress Width
.DATA_WIDTH (DATA_WIDTH ), //Data Width
.BW_WIDTH (BW_WIDTH), //Byte Write Width
.BURST_LEN (BURST_LEN), //Burst Length
.NUM_DEVICES (NUM_DEVICES), //Memory Devices
.N_DATA_LANES (N_DATA_LANES),
.FIXED_LATENCY_MODE (FIXED_LATENCY_MODE), //Fixed Latency for data reads
.PHY_LATENCY (PHY_LATENCY), //Value for Fixed Latency Mode
.MEM_RD_LATENCY (MEM_RD_LATENCY), //Value of Memory part read latency
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY), //Only CQ is used for data capture and no CQ#
.SIMULATION (SIMULATION), //TRUE during design simulation
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.PLL_LOC (PHY_CONTROL_MASTER_BANK),
.INTER_BANK_SKEW (INTER_BANK_SKEW),
.CQ_BITS (CQ_BITS), //clogb2(NUM_DEVICES - 1)
.Q_BITS (Q_BITS), //clogb2(DATA_WIDTH - 1)
.DEVICE_TAPS (DEVICE_TAPS), // Number of taps in the IDELAY chain
.TAP_BITS (TAP_BITS), // clogb2(DEVICE_TAPS - 1)
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE ), //Input buffer low power mode
.IODELAY_HP_MODE (IODELAY_HP_MODE), //IODELAY High Performance Mode
.DATA_CTL_B0 (DATA_CTL_B0), //Data write/read bits in all banks
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.ADDR_CTL_MAP (ADDR_CTL_MAP),
.BYTE_LANES_B0 (BYTE_LANES_B0), //Byte lanes used for the complete design
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.BYTE_GROUP_TYPE_B0 (BYTE_GROUP_TYPE_B0), //Differentiates data write and read byte lanes
.BYTE_GROUP_TYPE_B1 (BYTE_GROUP_TYPE_B1),
.BYTE_GROUP_TYPE_B2 (BYTE_GROUP_TYPE_B2),
.BYTE_GROUP_TYPE_B3 (BYTE_GROUP_TYPE_B3),
.BYTE_GROUP_TYPE_B4 (BYTE_GROUP_TYPE_B4),
.CPT_CLK_SEL_B0 (CPT_CLK_SEL_B0), //Capture clock placement parameters
.CPT_CLK_SEL_B1 (CPT_CLK_SEL_B1),
.CPT_CLK_SEL_B2 (CPT_CLK_SEL_B2),
.BIT_LANES_B0 (PHY_0_BITLANES), //Bits used for the complete design
.BIT_LANES_B1 (PHY_1_BITLANES),
.BIT_LANES_B2 (PHY_2_BITLANES),
.BIT_LANES_B3 (PHY_3_BITLANES),
.BIT_LANES_B4 (PHY_4_BITLANES),
.ADD_MAP (ADD_MAP), // Address bits mapping
.RD_MAP (RD_MAP),
.WR_MAP (WR_MAP),
.D0_MAP (D0_MAP), // Data write bits mapping
.D1_MAP (D1_MAP),
.D2_MAP (D2_MAP),
.D3_MAP (D3_MAP),
.D4_MAP (D4_MAP),
.D5_MAP (D5_MAP),
.D6_MAP (D6_MAP),
.D7_MAP (D7_MAP),
.BW_MAP (BW_MAP),
.K_MAP (K_MAP),
.Q0_MAP (Q0_MAP), // Data read bits mapping
.Q1_MAP (Q1_MAP),
.Q2_MAP (Q2_MAP),
.Q3_MAP (Q3_MAP),
.Q4_MAP (Q4_MAP),
.Q5_MAP (Q5_MAP),
.Q6_MAP (Q6_MAP),
.Q7_MAP (Q7_MAP),
.CQ_MAP (CQ_MAP),
.DEBUG_PORT (DEBUG_PORT), // Debug using Chipscope controls
.TCQ (TCQ) //Register Delay
)
u_qdr_phy_top
(
// clocking and reset
.clk (clk), //Fabric logic clock
.rst_wr_clk (rst_wr_clk), // fabric reset based on PLL lock and system input reset.
.clk_ref (clk_ref), // Idelay_ctrl reference clock
.clk_mem (mem_refclk), // Memory clock to hard PHY
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.pll_lock (pll_locked),
.rst_clk (rst_clk), //output generated based on read clocks being stable
.sys_rst (sys_rst_o), // input system reset
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
//PHY Write Path Interface
.wr_cmd0 (app_wr_cmd0), //wr command 0
.wr_cmd1 (app_wr_cmd1), //wr command 1
.wr_addr0 (app_wr_addr0), //wr address 0
.wr_addr1 (app_wr_addr1), //wr address 1
.rd_cmd0 (app_rd_cmd0), //rd command 0
.rd_cmd1 (app_rd_cmd1), //rd command 1
.rd_addr0 (app_rd_addr0), //rd address 0
.rd_addr1 (app_rd_addr1), //rd address 1
.wr_data0 (mux_wr_data0), //app write data 0
.wr_data1 (mux_wr_data1), //app write data 1
.wr_bw_n0 (mux_wr_bw_n0), //app byte writes 0
.wr_bw_n1 (mux_wr_bw_n1), //app byte writes 1
//PHY Read Path Interface
.init_calib_complete (init_calib_complete), //Calibration complete
.rd_valid0 (app_rd_valid0), //Read valid for rd_data0
.rd_valid1 (app_rd_valid1), //Read valid for rd_data1
.rd_data0 (rd_data0), //Read data 0
.rd_data1 (rd_data1), //Read data 1
//Memory Interface
.qdr_dll_off_n (qdriip_dll_off_n), //QDR - turn off dll in mem
.qdr_k_p (qdriip_k_p), //QDR clock K
.qdr_k_n (qdriip_k_n), //QDR clock K#
.qdr_sa (qdriip_sa), //QDR Memory Address
.qdr_w_n (qdriip_w_n), //QDR Write
.qdr_r_n (qdriip_r_n), //QDR Read
.qdr_bw_n (qdriip_bw_n), //QDR Byte Writes to Mem
.qdr_d (qdriip_d), //QDR Data to Memory
.qdr_q (qdriip_q), //QDR Data from Memory
.qdr_cq_p (qdriip_cq_p), //QDR echo clock CQ
.qdr_cq_n (qdriip_cq_n), //QDR echo clock CQ#
//Debug interface
.dbg_phy_status (dbg_phy_status),
//.dbg_SM_en (dbg_SM_en),
//.dbg_SM_No_Pause (dbg_SM_No_Pause),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_phy_init_wr_only (dbg_phy_init_wr_only),
.dbg_phy_init_rd_only (dbg_phy_init_rd_only),
.dbg_byte_sel (dbg_byte_sel),
.dbg_bit_sel (dbg_bit_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up (dbg_idel_up),
.dbg_idel_down (dbg_idel_down),
.dbg_idel_tap_cnt (dbg_idel_tap_cnt),
.dbg_idel_tap_cnt_sel (dbg_idel_tap_cnt_sel),
.dbg_select_rdata (dbg_select_rdata),
.dbg_align_rd0_r (dbg_align_rd0_r),
.dbg_align_rd1_r (dbg_align_rd1_r),
.dbg_align_fd0_r (dbg_align_fd0_r),
.dbg_align_fd1_r (dbg_align_fd1_r),
.dbg_align_rd0 (dbg_align_rd0),
.dbg_align_rd1 (dbg_align_rd1),
.dbg_align_fd0 (dbg_align_fd0),
.dbg_align_fd1 (dbg_align_fd1),
.dbg_byte_sel_cnt (dbg_byte_sel_cnt),
.dbg_phy_wr_cmd_n (dbg_phy_wr_cmd_n),
.dbg_phy_addr (dbg_phy_addr),
.dbg_phy_rd_cmd_n (dbg_phy_rd_cmd_n),
.dbg_phy_wr_data (dbg_phy_wr_data),
.dbg_wr_init (dbg_wr_init),
.dbg_rd_stage1_cal (dbg_rd_stage1_cal),
.dbg_stage2_cal (dbg_stage2_cal),
.dbg_valid_lat (dbg_valid_lat),
.dbg_inc_latency (dbg_inc_latency),
.dbg_error_max_latency (dbg_error_max_latency),
.error_adj_latency (dbg_error_adj_latency)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_phy_init_wr_only = 1'b0;
assign dbg_phy_init_rd_only = 1'b0;
assign dbg_byte_sel = 'b0;
assign dbg_bit_sel = 'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 1'b0;
assign dbg_po_f_dec = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_up = 1'b0;
assign dbg_idel_down = 1'b0;
assign dbg_SM_en = 1'b1;
assign dbg_SM_No_Pause = 1'b1;
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_babasu_DATA_I (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 8: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 8: 0] data_out;
wire [ 8: 0] out_port;
wire [ 8: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[8 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:20:57 09/06/2015
// Design Name:
// Module Name: FSM_Mult_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Mult_Function(
//INPUTS
input wire clk,
input wire rst,
input wire beg_FSM, //Be gin the multiply operation
input wire ack_FSM, //Is used in the last state, is an aknowledge signal
//ZERO PHASE EVALUATION SIGNALS
input wire zero_flag_i,
//Sgf_Operation *EVALUATION SIGNALS
input wire Mult_shift_i,
//round decoder EVALUATION SIGNALS
input wire round_flag_i,
//Adder round EV LUATION Signals
input wire Add_Overflow_i,
///////////////////////Load Signals/////////////////////////////////////7
//Oper Start_in load signal
output reg load_0_o,
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
output reg load_1_o,
//Exp operation result,
output reg load_2_o,
//Exp operation Overflow, Sgf operation second reg
output reg load_3_o,
//Adder round register
output reg load_4_o,
//Final result registers
output reg load_5_o,
//Barrel shifter registers
output reg load_6_o,
/////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
output reg ctrl_select_a_o,
output reg ctrl_select_b_o,
output reg [1:0] selector_b_o,
output reg ctrl_select_c_o,
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
output reg exp_op_o,
//Barrel shifter control signals
output reg shift_value_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
////////States///////////
//Zero Phase
parameter [3:0] start = 4'd0,//A
load_operands = 4'd1, //B) loads both operands to registers
extra64_1 = 4'd2,
add_exp = 4'd3, //C) Add both operands, evaluate underflow
subt_bias = 4'd4, //D) Subtract bias to the result, evaluate overflow, evaluate zero
mult_overf= 4'd5, //E) Evaluate overflow in Sgf multiplication for normalization case
mult_norn = 4'd6, //F) Overflow normalization, right shift significant and increment exponent
mult_no_norn = 4'd7, //G)No_normalization sgf
round_case = 4'd8, //H) Rounding evaluation. Positive= adder rounding, Negative,=Final load
adder_round = 4'd9, //I) add a 1 to the significand in case of rounding
round_norm = 4'd10, //J) Evaluate overflow in adder for normalization, Positive = normalization, same that F
final_load = 4'd11, //K) Load output registers
ready_flag = 4'd12; //L) Ready flag, wait for ack signal
//State registers
reg [3:0] state_reg, state_next;
//State registers reset and standby logic
always @(posedge clk, posedge rst)
if(rst)
state_reg <= start;
else
state_reg <= state_next;
//Transition and Output Logic
always @*
begin
//STATE DEFAULT BEHAVIOR
state_next = state_reg; //If no changes, keep the value of the register unaltered
load_0_o=0;
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
load_1_o=0;
//Exp operation result,
load_2_o=0;
//Exp operation Overflow, Sgf operation second reg
load_3_o=0;
//Adder round register
load_4_o=0;
//Final result registers
load_5_o=0;
load_6_o=0;
//////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
ctrl_select_a_o=0;
ctrl_select_b_o=0;
selector_b_o=2'b0;
ctrl_select_c_o=0;
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
exp_op_o=0;
//Barrel shifter control signals
shift_value_o=0;
//Internal reset signal
rst_int=0;
//Ready Signal
ready=0;
case(state_reg)
start:
begin
rst_int = 1;
if(beg_FSM)
state_next = load_operands; //Jump to the first state of the machine
end
//First Phase
load_operands:
begin
load_0_o = 1;
state_next = extra64_1;
end
extra64_1:
begin
state_next = add_exp;
end
//Zero Check
add_exp:
begin
load_1_o = 1;
load_2_o = 1;
ctrl_select_a_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = subt_bias;
end
subt_bias:
begin
load_2_o = 1;
load_3_o = 1;
exp_op_o = 1;
if(zero_flag_i)
state_next = ready_flag;
else
state_next = mult_overf;
end
mult_overf:
begin
if(Mult_shift_i) begin
ctrl_select_b_o =1;
selector_b_o =2'b10;
state_next = mult_norn;
end
else
state_next = mult_no_norn;
end
//Ninth Phase
mult_norn:
begin
shift_value_o =1;
load_6_o = 1;
load_2_o = 1;
load_3_o = 1;
//exp_op_o = 1;
state_next = round_case;
end
mult_no_norn:
begin
shift_value_o =0;
load_6_o = 1;
state_next = round_case;
end
round_case:
begin
if(round_flag_i) begin
ctrl_select_c_o =1;
state_next = adder_round;
end
else
state_next = final_load;
end
adder_round:
begin
load_4_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = round_norm;
end
round_norm:
begin
load_6_o = 1;
if(Add_Overflow_i)begin
shift_value_o =1;
load_2_o = 1;
load_3_o = 1;
state_next = final_load;
end
else begin
shift_value_o =0;
state_next = final_load;
end
end
final_load:
begin
load_5_o =1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(ack_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_4_V
`define SKY130_FD_SC_LP__O221A_4_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221a_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_4_V
|
/**************************************************************************
Async Fifo
-parameter N
Queue data vector width
Example : DATA[3:0] is N=4
-parameter DEPTH
Queue entry depth
Example DEPTH 16 is DEPTH=16
-parameter D_N
Queue entry depth n size
Example PARAMETER_DEPTH16 is 4
-SDF Settings
Asynchronus Clock : iWR_CLOCK - iRD_CLOCK
-Make : 2013/2/13
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032isa_async_fifo
#(
parameter N = 16,
parameter DEPTH = 4,
parameter D_N = 2
)
(
//System
input wire inRESET,
//Remove
input wire iREMOVE,
//WR
input wire iWR_CLOCK,
input wire iWR_EN,
input wire [N-1:0] iWR_DATA,
output wire oWR_FULL,
//RD
input wire iRD_CLOCK,
input wire iRD_EN,
output wire [N-1:0] oRD_DATA,
output wire oRD_EMPTY
);
//Full
wire [D_N:0] full_count;
wire full;
wire [D_N:0] empty_count;
wire empty;
//Memory
reg [N-1:0] b_memory[0:DEPTH-1];
//Counter
reg [D_N:0] b_wr_counter/* synthesis preserve = 1 */; //Altera QuartusII Option
reg [D_N:0] b_rd_counter/* synthesis preserve = 1 */; //Altera QuartusII Option
wire [D_N:0] gray_d_fifo_rd_counter;
wire [D_N:0] binary_d_fifo_rd_counter;
wire [D_N:0] gray_d_fifo_wr_counter;
wire [D_N:0] binary_d_fifo_wr_counter;
//Assign
assign full_count = b_wr_counter - binary_d_fifo_rd_counter;
assign full = full_count[D_N] || (full_count[D_N-1:0] == {D_N{1'b1}})? 1'b1 : 1'b0;
//Empty
assign empty_count = binary_d_fifo_wr_counter - (b_rd_counter);
assign empty = (empty_count == {D_N+1{1'b0}})? 1'b1 : 1'b0;
/***************************************************
Memory
***************************************************/
//Write
always@(posedge iWR_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_wr_counter <= {D_N{1'b0}};
end
else if(iREMOVE)begin
b_wr_counter <= {D_N{1'b0}};
end
else begin
if(iWR_EN && !full)begin
b_memory[b_wr_counter[D_N-1:0]] <= iWR_DATA;
b_wr_counter <= b_wr_counter + {{D_N-1{1'b0}}, 1'b1};
end
end
end
//Read Pointer
always@(posedge iRD_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_rd_counter <= {D_N{1'b0}};
end
else if(iREMOVE)begin
b_rd_counter <= {D_N{1'b0}};
end
else begin
if(iRD_EN && !empty)begin
b_rd_counter <= b_rd_counter + {{D_N-1{1'b0}}, 1'b1};
end
end
end
/***************************************************
Counter Buffer
***************************************************/
mist1032isa_async_fifo_double_flipflop #(D_N+1) D_FIFO_READ(
.iCLOCK(iWR_CLOCK),
.inRESET(inRESET),
.iREQ_DATA(bin2gray(b_rd_counter)),
.oOUT_DATA(gray_d_fifo_rd_counter)
);
assign binary_d_fifo_rd_counter = gray2bin(gray_d_fifo_rd_counter);
mist1032isa_async_fifo_double_flipflop #(D_N+1) D_FIFO_WRITE(
.iCLOCK(iRD_CLOCK),
.inRESET(inRESET),
.iREQ_DATA(bin2gray(b_wr_counter)),
.oOUT_DATA(gray_d_fifo_wr_counter)
);
assign binary_d_fifo_wr_counter = gray2bin(gray_d_fifo_wr_counter);
/***************************************************
Function
***************************************************/
function [D_N:0] bin2gray;
input [D_N:0] binary;
begin
bin2gray = binary ^ (binary >> 1'b1);
end
endfunction
function[D_N:0] gray2bin(input[D_N:0] gray);
integer i;
for(i=D_N; i>=0; i=i-1)begin
if(i==D_N)begin
gray2bin[i] = gray[i];
end
else begin
gray2bin[i] = gray[i] ^ gray2bin[i+1];
end
end
endfunction
/***************************************************
Output Assign
***************************************************/
assign oWR_FULL = full;
assign oRD_EMPTY = empty;
assign oRD_DATA = b_memory[b_rd_counter[D_N-1:0]];
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:12:50 07/09/2015
// Design Name:
// Module Name: CLOCK
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CLOCK
( input CLK32,
output PixelClk,
output PixelClk2,
output PixelClk10,
output SerDesStrobe
);
wire pll_fbout; // PLL Feedback
wire pll_clk10x; // From PLL to BUFPLL
wire pll_clk2x; // From PLL to BUFG
wire pll_clk1x; // From PLL to BUFG
wire pll_locked;
PLL_BASE #(.CLKOUT0_DIVIDE(2), // IO clock 416.000MHz (VCO / 2)
.CLKOUT1_DIVIDE(10), // Intermediate clock 83.200MHz (VCO / 10)
.CLKOUT2_DIVIDE(20), // Pixel Clock 41.600MHz (VCO / 20)
.CLKFBOUT_MULT(26), // VCO = 32.000MHz * 26 = 832.000MHz ...
.DIVCLK_DIVIDE(1), // ... 832.000MHz / 1 = 832.000MHz
.CLKIN_PERIOD(31.25) // 31.25ns = 32.000MHz
) ClockGenPLL(.CLKIN(CLK32),
.CLKFBIN(pll_fbout),
.RST(1'b0),
.CLKOUT0(pll_clk10x),
.CLKOUT1(pll_clk2x),
.CLKOUT2(pll_clk1x),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(pll_fbout),
.LOCKED(pll_locked));
BUFG Clk1x_buf(.I(pll_clk1x), .O(PixelClk));
BUFG Clk2x_buf(.I(pll_clk2x), .O(PixelClk2));
BUFPLL #(.DIVIDE(5),
.ENABLE_SYNC("TRUE")
) Clk10x_buf(.PLLIN(pll_clk10x),
.GCLK(PixelClk2),
.LOCKED(pll_locked),
.IOCLK(PixelClk10),
.SERDESSTROBE(SerDesStrobe),
.LOCK());
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O32A_BEHAVIORAL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_TB_V
`define SKY130_FD_SC_HD__AND3B_TB_V
/**
* and3b: 3-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_hd__and3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_TB_V
|
module DecodeUnit(
input [15:0] COMMAND,
output out,
output INPUT_MUX, writeEnable,
output [2:0] writeAddress,
output ADR_MUX, write, PC_load,
output SP_write, inc, dec,
output [2:0] cond, op2,
output SP_Sw, MAD_MUX, FLAG_WRITE, AR_MUX, BR_MUX,
output [3:0] S_ALU,
output SPC_MUX, MW_MUX, AB_MUX, signEx
);
reg [3:0] Select_ALU;
reg [2:0] condition;
reg [2:0] opera2;
localparam IADD = 4'b0000;
localparam ISUB = 4'b0001;
localparam IAND = 4'b0010;
localparam IOR = 4'b0011;
localparam IXOR = 4'b0100;
localparam ISLL = 4'b1000;
localparam ISLR = 4'b1001;
localparam ISRL = 4'b1010;
localparam ISRA = 4'b1011;
localparam IIDT = 4'b1100;
localparam INON = 4'b1111;
reg [2:0] wrAdr;
reg wr, pcl, in, adr, ar, br, se, wren, o, spc, ab, mw, sps, mad, i, d, spw, flw;
//FLAG_WRITE
always @ (COMMAND) begin
if ((COMMAND[15:14] == 2'b11 && COMMAND[7:4] >= 4'b0000 && COMMAND[7:4] <= 4'b1011 && COMMAND[7:4] != 4'b0111)
|| COMMAND[15:11] == 5'b10001)
flw <= 1'b1;
else
flw <= 1'b0;
end
//SPC_MUX
always @ (COMMAND) begin
if (COMMAND[15:11] == 5'b10011 || COMMAND[15:11] == 5'b10101)
spc <= 1'b1;
else
spc <= 1'b0;
end
//AB_MUX
always @ (COMMAND) begin
if (COMMAND[15:14] == 2'b01)
ab <= 1;
else
ab <= 0;
end
//MW_MUX
always @ (COMMAND) begin
if (COMMAND[15:8] == 8'b10111110)
mw <= 0;
else
mw <= 1;
end
//SP_Sw
always @ (COMMAND) begin
if (COMMAND[15:8] == 8'b10111111)
sps <= 0;
else
sps <= 1;
end
//MAD_MUX
always @ (COMMAND) begin
if (COMMAND[15:11] == 5'b10010 || COMMAND[15:9] == 7'b1011111)
mad <= 0;
else
mad <=1;
end
//inc
always @ (COMMAND) begin
if (COMMAND[15:8] == 8'b10111110 || COMMAND[15:11] == 5'b10010)
i <= 1;
else
i <= 0;
end
//dec
always @ (COMMAND) begin
if (COMMAND[15:8] == 8'b10111111 || COMMAND[15:11] == 5'b10011)
d <= 1;
else
d <= 0;
end
//spw
always @ (COMMAND) begin
if (COMMAND[15:11] == 5'b10011)
spw <= 1;
else
spw <= 0;
end
//wrAdr
always @ (COMMAND) begin
if (COMMAND[15:14] == 2'b00)
wrAdr <= COMMAND[13:11];
else
wrAdr <= COMMAND[10:8];
end
//cond
always @ (COMMAND) begin
condition <= COMMAND[10:8];
end
//op2
always @ (COMMAND) begin
opera2 <= COMMAND[13:11];
end
//wren
always @ (COMMAND) begin
if (COMMAND[15:14] == 2'b01 || COMMAND[15:11] == 5'b10010 || COMMAND[15:11] == 5'b10010 ||
COMMAND[15:11] == 5'b10110 || COMMAND[15:8] == 8'b10111110)
wren <= 1;
else
wren <= 0;
end
//signEx
always @ (COMMAND) begin
if (COMMAND[15:14] != 2'b11)
se <= 1;
else
se <= 0;
end
//out
always @ (COMMAND) begin
if (COMMAND[15:14] == 2'b11 && COMMAND[7:4] == 4'b1101)
o <= 1;
else
o <= 0;
end
//write
always @ (COMMAND) begin
if ((COMMAND[15:14] == 2'b11 && (COMMAND[7:4] <= 4'b1100 && COMMAND[7:4] != 4'b0101)) ||
COMMAND[15:14] == 2'b00 || //LD
COMMAND[15:12] == 4'b1000 || //LI, ADDI
COMMAND[15:11] == 5'b10011 || //POP
COMMAND[15:11] == 5'b10101) //GET
wr <= 1;
else
wr <=0;
end
//PC_load
always @ (COMMAND) begin
if (COMMAND[15:11] == 5'b10100 || COMMAND[15:11] == 5'b10111)
pcl <= 1;
else
pcl <= 0;
end
//INPUT_MUX
always @ (COMMAND) begin
if (COMMAND[15:14] == 2'b11 && COMMAND[7:4] == 4'b1100)
in <= 1;
else
in <= 0;
end
//ADR_MUX
always @ (COMMAND) begin
//if ((COMMAND[15:14] == 2'b11 && COMMAND[7:4] <= 4'b1011) || COMMAND[15:14] == 2'b10)
if ((COMMAND[15:14] == 2'b11 && COMMAND[7:4] <= 4'b1011) ||
(COMMAND[15:14] == 2'b10 && (COMMAND[13:11] <= 3'b100 && COMMAND[13:11] != 3'b011)) ||
(COMMAND[15:11] == 5'b10111 && COMMAND[10:8] != 3'b111))
adr <= 1;
else
adr <= 0;
end
//BR_MUX
always @ (COMMAND) begin
//(COMMAND[15:14] != 2'b10 || COMMAND[13] != 1'b1)
if (COMMAND[15:14] == 2'b11 || COMMAND[15:11] == 5'b10001 || COMMAND[15:14] == 2'b01 || COMMAND[15:14] == 2'b00)
br <= 1;
else
br <= 0;
end
//AR_MUX
always @ (COMMAND) begin
if (COMMAND[15:14] == 2'b11 && COMMAND[7:4] <= 4'b0110)
ar <= 1;
else
ar <= 0;
end
//各種演算命令
always @ (COMMAND) begin
if (COMMAND[15:14] == 2'b11)//演算命令
case (COMMAND[7:4])
4'b0101 : Select_ALU <= ISUB;//CMP
4'b0110 : Select_ALU <= IIDT;//MOV
default : Select_ALU <= COMMAND[7:4];
endcase // case (COMMAND[7:4])
else if (COMMAND[15] == 1'b0)//LD, ST
Select_ALU <= IADD;
else if (COMMAND[15:11] == 5'b10000)//LI
Select_ALU <= IIDT;
else if (COMMAND[15:11] == 5'b10001)//ADDI
Select_ALU <= IADD;
else if (COMMAND[15:11] == 5'b10101 || COMMAND[15:11] == 5'b10110)//GET; SET;
Select_ALU <= ISUB;
else if (COMMAND[15:11] == 5'b10100)//分岐
Select_ALU <= IADD;
else if (COMMAND[15:11] == 5'b10111)//条件分岐
Select_ALU <= IADD;
else if (COMMAND[15:11] == 5'b10011)//POP
Select_ALU <= IADD;
else//その他
Select_ALU <= INON;
end
assign op2 = opera2;
assign writeAddress = wrAdr;
assign S_ALU = Select_ALU;
assign cond = condition;
assign AR_MUX = ar;
assign BR_MUX = br;
assign write = wr;
assign PC_load = pcl;
assign INPUT_MUX = in;
assign ADR_MUX = adr;
assign signEx = se;
assign out = o;
assign writeEnable = wren;
assign SPC_MUX = spc;
assign AB_MUX = ab;
assign MW_MUX = mw;
assign SP_Sw = sps;
assign MAD_MUX = mad;
assign inc = i;
assign dec = d;
assign SP_write = spw;
assign FLAG_WRITE = flw;
endmodule // DecodeUnit
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_BLACKBOX_V
`define SKY130_FD_SC_HVL__XOR2_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: clock_generator_ddr_s8_diff.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: September 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: BUFIO2 Based DDR clock generator. Takes in a differential clock
// and instantiates two sets of 2 BUFIO2s, one for each half bank
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module clock_generator_ddr_s8_diff (clkin_p, clkin_n, ioclkap, ioclkan, serdesstrobea, ioclkbp, ioclkbn, serdesstrobeb, gclk) ;
parameter integer S = 8 ; // Parameter to set the serdes factor 1..8
parameter DIFF_TERM = "FALSE" ; // Parameter to enable internal differential termination
input clkin_p, clkin_n ; // differential clock input
output ioclkap ; // A P ioclock from BUFIO2
output ioclkan ; // A N ioclock from BUFIO2
output serdesstrobea ; // A serdes strobe from BUFIO2
output ioclkbp ; // B P ioclock from BUFIO2 - leave open if not required
output ioclkbn ; // B N ioclock from BUFIO2 - leave open if not required
output serdesstrobeb ; // B serdes strobe from BUFIO2 - leave open if not required
output gclk ; // global clock output from BUFIO2
wire clkint ; //
wire gclk_int ; //
wire freqgen_in_p ; //
wire tx_bufio2_x1 ; //
assign gclk = gclk_int ;
IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
clk_iob_in (
.I (clkin_p),
.IB (clkin_n),
.O (freqgen_in_p));
BUFIO2 #(
.DIVIDE (S), // The DIVCLK divider divide-by value; default 1
.I_INVERT ("FALSE"), //
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("TRUE"))
bufio2_inst1 (
.I (freqgen_in_p), // Input source clock 0 degrees
.IOCLK (ioclkap), // Output Clock for IO
.DIVCLK (tx_bufio2_x1), // Output Divided Clock
.SERDESSTROBE (serdesstrobea)) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.I_INVERT ("TRUE"),
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("FALSE")) //
bufio2_inst2 (
.I (freqgen_in_p), // N_clk input from IDELAY
.IOCLK (ioclkan), // Output Clock
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.DIVIDE (S), // The DIVCLK divider divide-by value; default 1
.I_INVERT ("FALSE"), //
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("TRUE")) //
bufio2_inst3 (
.I (freqgen_in_p), // Input source clock 0 degrees
.IOCLK (ioclkbp), // Output Clock for IO
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE (serdesstrobeb)) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.I_INVERT ("TRUE"),
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("FALSE")) //
bufio2_inst4 (
.I (freqgen_in_p), // N_clk input from IDELAY
.IOCLK (ioclkbn), // Output Clock
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
BUFG bufg_tx (.I (tx_bufio2_x1), .O (gclk_int)) ;
endmodule
|
// date:2016/3/11
// engineer:ZhaiShaoMin
// module name program counter module
module core_pc(//input
clk,
rst,
btb_target,
ras_target,
pc_go,
stall,
// from id module
good_target, // target from decode stage, correct target
id_pc_src, // if 1 ,meaning pc scoure is from decode ,0,otherwise
// from BTB module
btb_v,
btb_type,
//output
pc_out,
v_pc_out,
pc_plus4
);
//parameter
parameter initial_addr=32'h00040000;
// para used in btb
parameter br_type=2'b00;
parameter j_type=2'b01;
parameter jal_type=2'b10;
parameter jr_type=2'b11;
//input
input clk;
input rst;
input [31:0] btb_target;
input [31:0] ras_target;
input id_pc_src;
input stall;
input pc_go;
input [31:0] good_target;
input [1:0] btb_type;
input btb_v;
//output
output [31:0] pc_out;
output v_pc_out;
output [31:0] pc_plus4;
//figure out pc src sel
wire [1:0] pc_src;
wire [1:0] pc_src1;
assign pc_src1=(btb_v&&(btb_type==br_type||btb_type==j_type||btb_type==jal_type))?2'b11:(btb_v&&btb_type==jr_type)?2'b10:2'b01;
assign pc_src=(id_pc_src==1'b1)?2'b00:pc_src1;
reg [31:0] pc_temp;
always@(*)
begin
case(pc_src)
2'b00:pc_temp=good_target;
2'b01:pc_temp=pc_plus4;
2'b10:pc_temp=ras_target;
2'b11:pc_temp=btb_target;
default:pc_temp=pc_plus4;
endcase
end
//reg
reg [31:0] pc;
always@(posedge clk)
begin
if(rst)
pc<=32'h00040000;
else if(pc_go&&!stall)
begin
pc<=pc_temp;
end
end
assign pc_plus4=pc+4;
assign v_pc_out=(pc_go&&!stall);//?1'b0:1'b1;
assign pc_out=pc;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_SYMBOL_V
`define SKY130_FD_SC_LP__O31AI_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o31ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_SYMBOL_V
|
// P-R unit (registers)
module pr(
input clk_sys,
input blr, // A50 - BLokuj Rejestry
input lpc, // A94 - LPC instruction
input wa, // B94 - state WA
input rpc, // B03 - RPC instruction
input ra, // B48 - user register address
input rb, // B49 - user register address
input rc, // A49
input as2, // B43
input w_r, // B47
input strob1, // B32
input strob1b, // B32
input strob2, // B42
input strob2b, // B42
input [0:15] w, // B07, B12, B11, B10, B22, B24, B25, B23, B13, B19, B20, B21, B16, B08, B17, B18 - bus W
output [0:15] l, // A04, A03, A28, A27, A09, A10, A26, A25, A07, A08, A16, A17, A06, A05, A18, A19 - bus L
input bar_nb, // B83 - BAR->NB: output BAR register to system bus
input w_rbb, // A51 - RB[4:9] clock in
input w_rbc, // B46 - RB[0:3] clock in
input w_rba, // B50 - RB[10:15] clock in
output [0:3] dnb, // A86, A90, A87, B84 - DNB: NB system bus driver
input rpn, // B85
input bp_nb, // B86
input pn_nb, // A92
input q_nb, // B90
input w_bar, // B56 - W->BAR: send W bus to {BAR, Q, BS} registers
input zer_sp, // A89
input clm, // B93
input ustr0_fp, // A11
input ust_leg, // B39
input aryt, // B45
input zs, // A47
input carry, // A48
input s_1, // B44
output zgpn, // B88
output dpn, // B87 - PN system bus driver
output dqb, // B89 - Q system bus driver
output q, // A53 - Q: system flag
output zer, // A52
input ust_z, // B53
input ust_mc, // B55
input s0, // B92
input ust_v, // A93
input _0_v, // B91
output [0:8] r0, // A44, A46, A43, A42, A41, A45, A40, A39, B09 - CPU flags in R0 register
input exy, // A37
input ust_y, // B40
input exx, // A38
input ust_x, // B41
input kia, // B81
input kib, // A91
input [0:15] bus_rz, // B70, B76, B60, B66, A60, A64, A68, A56, B80, A80, A74, A84, A77, B74, A71, B57
// NOTE: rz[14] is rz30, rz[15] is rz31
input [0:15] zp, // B68, B72, B62, B64, A62, B63, A66, A58, B78, A82, A75, A85, A78, A83, A70, A54
input [0:9] rs, // B69, B75, B61, B65, A61, A63, A67, A57, B79, A81
output [0:15] bus_ki // B71, B77, B59, B67, A59, A65, A69, A55, B82, A79, A73, B73, A76, A88, A72, B58
);
parameter CPU_NUMBER;
parameter AWP_PRESENT;
wire strob_a = ~as2 & strob1;
wire strob_b = as2 & strob2;
wire sel_r1_r7 = rb | ra | rc; // r1-r7 selected
wire wr0 = ~sel_r1_r7; // R0 selected
wire M60_6 = ~(wa & rpc);
wire [0:15] R1_7;
regs USER_REGS(
.clk_sys(clk_sys),
.w(w),
.addr({rc, rb, ra}),
.we((strob_a | strob_b) & w_r & sel_r1_r7),
.l(R1_7)
);
l BUS_L(
.r0({r0, r0low}),
.rn(R1_7),
.sel({blr, sel_r1_r7 & M60_6}),
.l(l)
);
// RB register (binary load register)
wire [0:15] rRB;
rb REG_RB(
.clk_sys(clk_sys),
.w(w[10:15]),
.w_rba(w_rba),
.w_rbb(w_rbb),
.w_rbc(w_rbc),
.rb(rRB)
);
assign zgpn = rpn ^ ~CPU_NUMBER; // CPU number matches
wire M35_8 = CPU_NUMBER ^ bs;
wire M23_11 = CPU_NUMBER & pn_nb;
assign dpn = (M35_8 & bp_nb) | M23_11;
assign dqb = q_nb & q;
wire cnb0_3 = w_bar & strob1b;
assign zer = zer_sp | clm;
// NB (BAR) register and system bus drivers
// Q and BS flag registers and system bus drivers
wire [0:3] nb;
wire bs;
bar REG_BAR(
.clk_sys(clk_sys),
.w(w[10:15]),
.cnb(cnb0_3),
.clm(clm),
.zer_sp(zer_sp),
.bar({q, bs, nb})
);
assign dnb = nb & {4{bar_nb}};
wire M60_3 = strob_a & AWP_PRESENT & ustr0_fp;
wire M62_6 = strob_a & w_r & wr0 & ~q;
wire M62_8 = strob_b & w_r & wr0 & ~q;
wire M61_8 = strob_a & w_r & wr0;
wire M61_12 = strob_b & w_r & wr0;
wire lr0 = lpc & strob_a & wa;
wire w_zmvc = lr0 | M62_8 | M62_6 | M60_3;
wire w_legy = lr0 | M62_8 | M62_6;
wire lrp = lr0 | M61_8 | M61_12;
wire cleg = as2 & strob2b & ust_leg;
wire vg = (~aryt & ~(zs | ~carry)) | (~(zs | s_1) & aryt);
wire vl = (~aryt & ~carry) | (aryt & s_1);
// R0 register
wire [9:15] r0low;
r0 REG_R0(
.clk_sys(clk_sys),
.w(w),
.r0({r0, r0low}),
.zs(zs),
.s_1(s_1),
.s0(s0),
.carry(carry),
.vl(vl),
.vg(vg),
.exy(exy),
.exx(exx),
.strob1b(strob1b),
.ust_z(ust_z),
.ust_v(ust_v),
.ust_mc(ust_mc),
.ust_y(ust_y),
.ust_x(ust_x),
.cleg(cleg),
.w_zmvc(w_zmvc),
.w_legy(w_legy),
._0_v(_0_v),
.lrp(lrp),
.zer(zer)
);
// KI bus
bus_ki BUS_KI(
.kia(kia),
.kib(kib),
.rz(bus_rz),
.sr({rs[0:9], q, bs, nb[0:3]}),
.rb(rRB),
.zp(zp),
.ki(bus_ki)
);
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/*
* Titor - System - LED module
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_LED
`else
`define INC_LED
`timescale 1 ns / 100 ps
module LED(
dout,
din,
address,
size,
read_write,
enable,
lighting,
reset,
clk
);
`include "definition/Definition.v"
output reg [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output wire [WORD-1:0] lighting;
input reset;
input clk;
reg [WORD-1:0] hold;
assign lighting = hold;
always @(posedge clk) begin
if(reset) hold <= 0;
else if((enable==ENABLE) && (read_write==WRITE) && (address==0)) hold <= din;
end
always @(posedge clk) begin
if(reset) dout <= 0;
else if((enable==ENABLE) && (read_write==READ) && (address==0)) dout <= hold;
else dout <= 0;
end
endmodule
`endif
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module spimemio (
input clk, resetn,
input valid,
output ready,
input [23:0] addr,
output reg [31:0] rdata,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di,
input [3:0] cfgreg_we,
input [31:0] cfgreg_di,
output [31:0] cfgreg_do
);
reg xfer_resetn;
reg din_valid;
wire din_ready;
reg [7:0] din_data;
reg [3:0] din_tag;
reg din_cont;
reg din_qspi;
reg din_ddr;
reg din_rd;
wire dout_valid;
wire [7:0] dout_data;
wire [3:0] dout_tag;
reg [23:0] buffer;
reg [23:0] rd_addr;
reg rd_valid;
reg rd_wait;
reg rd_inc;
assign ready = valid && (addr == rd_addr) && rd_valid;
wire jump = valid && !ready && (addr != rd_addr+4) && rd_valid;
reg softreset;
reg config_en; // cfgreg[31]
reg config_ddr; // cfgreg[22]
reg config_qspi; // cfgreg[21]
reg config_cont; // cfgreg[20]
reg [3:0] config_dummy; // cfgreg[19:16]
reg [3:0] config_oe; // cfgreg[11:8]
reg config_csb; // cfgreg[5]
reg config_clk; // cfgref[4]
reg [3:0] config_do; // cfgreg[3:0]
assign cfgreg_do[31] = config_en;
assign cfgreg_do[30:23] = 0;
assign cfgreg_do[22] = config_ddr;
assign cfgreg_do[21] = config_qspi;
assign cfgreg_do[20] = config_cont;
assign cfgreg_do[19:16] = config_dummy;
assign cfgreg_do[15:12] = 0;
assign cfgreg_do[11:8] = {flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe};
assign cfgreg_do[7:6] = 0;
assign cfgreg_do[5] = flash_csb;
assign cfgreg_do[4] = flash_clk;
assign cfgreg_do[3:0] = {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
always @(posedge clk) begin
softreset <= !config_en || cfgreg_we;
if (!resetn) begin
softreset <= 1;
config_en <= 1;
config_csb <= 0;
config_clk <= 0;
config_oe <= 0;
config_do <= 0;
config_ddr <= 0;
config_qspi <= 0;
config_cont <= 0;
config_dummy <= 8;
end else begin
if (cfgreg_we[0]) begin
config_csb <= cfgreg_di[5];
config_clk <= cfgreg_di[4];
config_do <= cfgreg_di[3:0];
end
if (cfgreg_we[1]) begin
config_oe <= cfgreg_di[11:8];
end
if (cfgreg_we[2]) begin
config_ddr <= cfgreg_di[22];
config_qspi <= cfgreg_di[21];
config_cont <= cfgreg_di[20];
config_dummy <= cfgreg_di[19:16];
end
if (cfgreg_we[3]) begin
config_en <= cfgreg_di[31];
end
end
end
wire xfer_csb;
wire xfer_clk;
wire xfer_io0_oe;
wire xfer_io1_oe;
wire xfer_io2_oe;
wire xfer_io3_oe;
wire xfer_io0_do;
wire xfer_io1_do;
wire xfer_io2_do;
wire xfer_io3_do;
reg xfer_io0_90;
reg xfer_io1_90;
reg xfer_io2_90;
reg xfer_io3_90;
always @(negedge clk) begin
xfer_io0_90 <= xfer_io0_do;
xfer_io1_90 <= xfer_io1_do;
xfer_io2_90 <= xfer_io2_do;
xfer_io3_90 <= xfer_io3_do;
end
assign flash_csb = config_en ? xfer_csb : config_csb;
assign flash_clk = config_en ? xfer_clk : config_clk;
assign flash_io0_oe = config_en ? xfer_io0_oe : config_oe[0];
assign flash_io1_oe = config_en ? xfer_io1_oe : config_oe[1];
assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2];
assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3];
assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0];
assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];
assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
wire xfer_dspi = din_ddr && !din_qspi;
wire xfer_ddr = din_ddr && din_qspi;
spimemio_xfer xfer (
.clk (clk ),
.resetn (xfer_resetn ),
.din_valid (din_valid ),
.din_ready (din_ready ),
.din_data (din_data ),
.din_tag (din_tag ),
.din_cont (din_cont ),
.din_dspi (xfer_dspi ),
.din_qspi (din_qspi ),
.din_ddr (xfer_ddr ),
.din_rd (din_rd ),
.dout_valid (dout_valid ),
.dout_data (dout_data ),
.dout_tag (dout_tag ),
.flash_csb (xfer_csb ),
.flash_clk (xfer_clk ),
.flash_io0_oe (xfer_io0_oe ),
.flash_io1_oe (xfer_io1_oe ),
.flash_io2_oe (xfer_io2_oe ),
.flash_io3_oe (xfer_io3_oe ),
.flash_io0_do (xfer_io0_do ),
.flash_io1_do (xfer_io1_do ),
.flash_io2_do (xfer_io2_do ),
.flash_io3_do (xfer_io3_do ),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di)
);
reg [3:0] state;
always @(posedge clk) begin
xfer_resetn <= 1;
din_valid <= 0;
if (!resetn || softreset) begin
state <= 0;
xfer_resetn <= 0;
rd_valid <= 0;
din_tag <= 0;
din_cont <= 0;
din_qspi <= 0;
din_ddr <= 0;
din_rd <= 0;
end else begin
if (dout_valid && dout_tag == 1) buffer[ 7: 0] <= dout_data;
if (dout_valid && dout_tag == 2) buffer[15: 8] <= dout_data;
if (dout_valid && dout_tag == 3) buffer[23:16] <= dout_data;
if (dout_valid && dout_tag == 4) begin
rdata <= {dout_data, buffer};
rd_addr <= rd_inc ? rd_addr + 4 : addr;
rd_valid <= 1;
rd_wait <= rd_inc;
rd_inc <= 1;
end
if (valid)
rd_wait <= 0;
case (state)
0: begin
din_valid <= 1;
din_data <= 8'h ff;
din_tag <= 0;
if (din_ready) begin
din_valid <= 0;
state <= 1;
end
end
1: begin
if (dout_valid) begin
xfer_resetn <= 0;
state <= 2;
end
end
2: begin
din_valid <= 1;
din_data <= 8'h ab;
din_tag <= 0;
if (din_ready) begin
din_valid <= 0;
state <= 3;
end
end
3: begin
if (dout_valid) begin
xfer_resetn <= 0;
state <= 4;
end
end
4: begin
rd_inc <= 0;
din_valid <= 1;
din_tag <= 0;
case ({config_ddr, config_qspi})
2'b11: din_data <= 8'h ED;
2'b01: din_data <= 8'h EB;
2'b10: din_data <= 8'h BB;
2'b00: din_data <= 8'h 03;
endcase
if (din_ready) begin
din_valid <= 0;
state <= 5;
end
end
5: begin
if (valid && !ready) begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[23:16];
din_qspi <= config_qspi;
din_ddr <= config_ddr;
if (din_ready) begin
din_valid <= 0;
state <= 6;
end
end
end
6: begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[15:8];
if (din_ready) begin
din_valid <= 0;
state <= 7;
end
end
7: begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[7:0];
if (din_ready) begin
din_valid <= 0;
din_data <= 0;
state <= config_qspi || config_ddr ? 8 : 9;
end
end
8: begin
din_valid <= 1;
din_tag <= 0;
din_data <= config_cont ? 8'h A5 : 8'h FF;
if (din_ready) begin
din_rd <= 1;
din_data <= config_dummy;
din_valid <= 0;
state <= 9;
end
end
9: begin
din_valid <= 1;
din_tag <= 1;
if (din_ready) begin
din_valid <= 0;
state <= 10;
end
end
10: begin
din_valid <= 1;
din_data <= 8'h 00;
din_tag <= 2;
if (din_ready) begin
din_valid <= 0;
state <= 11;
end
end
11: begin
din_valid <= 1;
din_tag <= 3;
if (din_ready) begin
din_valid <= 0;
state <= 12;
end
end
12: begin
if (!rd_wait || valid) begin
din_valid <= 1;
din_tag <= 4;
if (din_ready) begin
din_valid <= 0;
state <= 9;
end
end
end
endcase
if (jump) begin
rd_inc <= 0;
rd_valid <= 0;
xfer_resetn <= 0;
if (config_cont) begin
state <= 5;
end else begin
state <= 4;
din_qspi <= 0;
din_ddr <= 0;
end
din_rd <= 0;
end
end
end
endmodule
module spimemio_xfer (
input clk, resetn,
input din_valid,
output din_ready,
input [7:0] din_data,
input [3:0] din_tag,
input din_cont,
input din_dspi,
input din_qspi,
input din_ddr,
input din_rd,
output dout_valid,
output [7:0] dout_data,
output [3:0] dout_tag,
output reg flash_csb,
output reg flash_clk,
output reg flash_io0_oe,
output reg flash_io1_oe,
output reg flash_io2_oe,
output reg flash_io3_oe,
output reg flash_io0_do,
output reg flash_io1_do,
output reg flash_io2_do,
output reg flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di
);
reg [7:0] obuffer;
reg [7:0] ibuffer;
reg [3:0] count;
reg [3:0] dummy_count;
reg xfer_cont;
reg xfer_dspi;
reg xfer_qspi;
reg xfer_ddr;
reg xfer_ddr_q;
reg xfer_rd;
reg [3:0] xfer_tag;
reg [3:0] xfer_tag_q;
reg [7:0] next_obuffer;
reg [7:0] next_ibuffer;
reg [3:0] next_count;
reg fetch;
reg next_fetch;
reg last_fetch;
always @(posedge clk) begin
xfer_ddr_q <= xfer_ddr;
xfer_tag_q <= xfer_tag;
end
assign din_ready = din_valid && resetn && next_fetch;
assign dout_valid = (xfer_ddr_q ? fetch && !last_fetch : next_fetch && !fetch) && resetn;
assign dout_data = ibuffer;
assign dout_tag = xfer_tag_q;
always @* begin
flash_io0_oe = 0;
flash_io1_oe = 0;
flash_io2_oe = 0;
flash_io3_oe = 0;
flash_io0_do = 0;
flash_io1_do = 0;
flash_io2_do = 0;
flash_io3_do = 0;
next_obuffer = obuffer;
next_ibuffer = ibuffer;
next_count = count;
next_fetch = 0;
if (dummy_count == 0) begin
casez ({xfer_ddr, xfer_qspi, xfer_dspi})
3'b 000: begin
flash_io0_oe = 1;
flash_io0_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[6:0], 1'b 0};
next_count = count - |count;
end else begin
next_ibuffer = {ibuffer[6:0], flash_io1_di};
end
next_fetch = (next_count == 0);
end
3'b 01?: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io2_oe = !xfer_rd;
flash_io3_oe = !xfer_rd;
flash_io0_do = obuffer[4];
flash_io1_do = obuffer[5];
flash_io2_do = obuffer[6];
flash_io3_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[3:0], 4'b 0000};
next_count = count - {|count, 2'b00};
end else begin
next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
end
next_fetch = (next_count == 0);
end
3'b 11?: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io2_oe = !xfer_rd;
flash_io3_oe = !xfer_rd;
flash_io0_do = obuffer[4];
flash_io1_do = obuffer[5];
flash_io2_do = obuffer[6];
flash_io3_do = obuffer[7];
next_obuffer = {obuffer[3:0], 4'b 0000};
next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
next_count = count - {|count, 2'b00};
next_fetch = (next_count == 0);
end
3'b ??1: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io0_do = obuffer[6];
flash_io1_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[5:0], 2'b 00};
next_count = count - {|count, 1'b0};
end else begin
next_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di};
end
next_fetch = (next_count == 0);
end
endcase
end
end
always @(posedge clk) begin
if (!resetn) begin
fetch <= 1;
last_fetch <= 1;
flash_csb <= 1;
flash_clk <= 0;
count <= 0;
dummy_count <= 0;
xfer_tag <= 0;
xfer_cont <= 0;
xfer_dspi <= 0;
xfer_qspi <= 0;
xfer_ddr <= 0;
xfer_rd <= 0;
end else begin
fetch <= next_fetch;
last_fetch <= xfer_ddr ? fetch : 1;
if (dummy_count) begin
flash_clk <= !flash_clk && !flash_csb;
dummy_count <= dummy_count - flash_clk;
end else
if (count) begin
flash_clk <= !flash_clk && !flash_csb;
obuffer <= next_obuffer;
ibuffer <= next_ibuffer;
count <= next_count;
end
if (din_valid && din_ready) begin
flash_csb <= 0;
flash_clk <= 0;
count <= 8;
dummy_count <= din_rd ? din_data : 0;
obuffer <= din_data;
xfer_tag <= din_tag;
xfer_cont <= din_cont;
xfer_dspi <= din_dspi;
xfer_qspi <= din_qspi;
xfer_ddr <= din_ddr;
xfer_rd <= din_rd;
end
end
end
endmodule
|
`include "bsg_defines.v"
`include "test_assembler_defines.v"
module test_bsg_comm_link;
`include "test_bsg_clock_params.v"
// number of bits width of a channel
// must be >= 3; with channel_width = 3
// calibration will be limited
localparam channel_width_lp = `CHANNEL_WIDTH;
localparam num_channels_lp = `NUM_CHANNELS;
// this is the number of bytes that a ring packet is
localparam ring_bytes_lp = `RING_BYTES;
localparam iterations_lp = `ITERATIONS;
localparam verbose_lp = 1;
// most flexible configuration for assembler
// any subset of channels (4,3,2,1) may be used
localparam channel_mask_lp = (1 << num_channels_lp) - 1;
genvar i,j;
// *************************************************
// independent clocks and reset
//
//
logic [1:0] core_clk;
logic [1:0] io_master_clk;
test_bsg_clock_gen #(.cycle_time_p(core_0_period_lp)) c0_clk (.o( core_clk[0]));
test_bsg_clock_gen #(.cycle_time_p(core_1_period_lp)) c1_clk (.o( core_clk[1]));
initial
$display("%m creating clocks",core_0_period_lp, core_1_period_lp, io_master_0_period_lp, io_master_1_period_lp);
test_bsg_clock_gen #(.cycle_time_p(io_master_0_period_lp)) i0_clk (.o(io_master_clk[0]));
test_bsg_clock_gen #(.cycle_time_p(io_master_1_period_lp)) i1_clk (.o(io_master_clk[1]));
logic async_reset;
localparam core_reset_cycles_hi_lp = 256;
localparam core_reset_cycles_lo_lp = 16;
test_bsg_reset_gen
#(.num_clocks_p(4)
,.reset_cycles_lo_p(core_reset_cycles_lo_lp)
,.reset_cycles_hi_p(core_reset_cycles_hi_lp)
) reset_gen
(.clk_i({ core_clk, io_master_clk })
,.async_reset_o(async_reset)
);
// Defines for Core Zero and One
wire [1:0] core_reset_in;
wire [1:0] core_calib_reset;
wire [1:0] core_valid_out;
wire [ring_bytes_lp*channel_width_lp-1:0] core_data_out [1:0];
wire [1:0] core_yumi_out;
wire [1:0] core_valid_in;
wire [ring_bytes_lp*channel_width_lp-1:0] core_data_in [1:0];
wire [1:0] core_ready_in;
//**********************************************************************
// CORE 0 (sender)
// ______ _____ ______ _______ _______ _______ ______ _____
// / _____) ___ \(_____ \(_______) (_______|_______|_____ \ / ___ \
// | / | | | |_____) )_____ __ _____ _____) ) | | |
// | | | | | (_____ (| ___) / / | ___) (_____ (| | | |
// | \____| |___| | | | |_____ / /____| |_____ | | |___| |
// \______)_____/ |_|_______) (_______)_______) |_|\_____/
//
//**********************************************************************
// CORE ZERO Send (speaking valid/ready protocol)
// core_ready signal will be held low by comm_link
// module until calibration is done.
assign core_valid_out[0] = ~core_reset_in[0];
test_bsg_data_gen #(.channel_width_p(channel_width_lp)
,.num_channels_p(ring_bytes_lp)
) tbdg_send
(.clk_i(core_clk[0] )
,.reset_i(core_reset_in[0]) // this is a core, so should be woken up
// when cores wakeup
,.yumi_i (core_yumi_out[0])
,.o (core_data_out[0])
);
// CORE ZERO Receive (speaking valid/yumi protocol)
//
// always eat the data
assign core_ready_in[0] = 1'b1;
//************************************************************
// CORE 1 (input side)
// ______ _____ ______ _______ _____ ______ _______
// / _____) ___ \(_____ \(_______) / ___ \| ___ \(_______)
// | / | | | |_____) )_____ | | | | | | |_____
// | | | | | (_____ (| ___) | | | | | | | ___)
// | \____| |___| | | | |_____ | |___| | | | | |_____
// \______)_____/ |_|_______) \_____/|_| |_|_______)
//
//************************************************************
logic [1:0] core_async_reset, core_async_reset_r;
bsg_two_fifo #( .width_p(channel_width_lp*ring_bytes_lp)) core_one_fifo
(.clk_i(core_clk[1])
,.reset_i(core_reset_in[1])
,.ready_o(core_ready_in[1])
,.v_i (core_valid_in[1])
,.data_i (core_data_in [1])
,.v_o (core_valid_out[1])
,.data_o(core_data_out [1])
,.yumi_i(core_yumi_out [1])
);
always @(posedge io_master_clk[1])
begin
core_async_reset_r[1] <= core_async_reset[1];
if (~core_async_reset[1] & core_async_reset_r[1])
begin
$display(" _ ");
$display(" (_) _ ");
$display(" _____ ___ _ ____ ____ _____ ___ _____ _| |_ ");
$display("(____ |/___) |/ ___) / ___) ___ |/___) ___ (_ _)");
$display("/ ___ |___ | ( (___ | | | ____|___ | ____| | |_ ");
$display("\\_____(___/|_|\\____) |_| |_____|___/|_____) \\__)");
$display(" ");
end
end
//************************************************************
// CORE 1 (input side)
// ______ _____ ______ _______ ______ __
// / _____) ___ \(_____ \(_______) / __ | _ / |
// | / | | | |_____) )_____ | | //| | _| |_ /_/ |
// | | | | | (_____ (| ___) | |// | | (_ _) | |
// | \____| |___| | | | |_____ | /__| | |_| | |
// \______)_____/ |_|_______) \_____/ |_|
//
//************************************************************
// external signals
logic [num_channels_lp-1:0] io_clk_tline [1:0], io_valid_tline [1:0];
logic [channel_width_lp-1:0] io_data_tline [1:0] [num_channels_lp-1:0];
logic [num_channels_lp-1:0] token_clk_tline [1:0];
wire [1:0] slave_reset_tline;
//************************************************************
// BREAK PCB WIRES HERE.
//
// modify these lines to test stuck-at faults due to assembly
// issues or just even bad silicon.
//
// watch this crazy thing adapt to faults!
//
// A. to FPGA
// always @(io_data_tline[1][0]) force io_data_tline[1][0][channel_width_lp-1] = 1; // 0
// always @(io_data_tline[1][0]) force io_data_tline[1][1][channel_width_lp-1] = 1; // 1
// always @(io_data_tline[1][0]) force io_data_tline[1][2][channel_width_lp-1] = 1; // 2
// always @(io_data_tline[1][0]) force io_data_tline[1][3][channel_width_lp-1] = 1; // 3
// always @(io_data_tline[1][0]) force io_data_tline[0][0][channel_width_lp-1] = 1;
// always @(io_data_tline[1][0]) force io_data_tline[0][1][channel_width_lp-1] = 1; // 1
// always @(io_data_tline[1][0]) force io_data_tline[0][2][channel_width_lp-2] = 1; // 2
// B. to ASIC
// also: test contamination of calibration code
// always @(io_data_tline[1][0]) force io_data_tline[0][3][channel_width_lp-1] = 0; // 3
// always @(io_data_tline[1][0]) force io_valid_tline[0][3] = 1; // 3
for (i = 0; i < 2; i++)
begin : core
wire [ring_bytes_lp*channel_width_lp-1:0] core_node_data_lo [0:0];
wire [ring_bytes_lp*channel_width_lp-1:0] core_node_data_li [0:0];
// type translation
assign core_data_in [i] = core_node_data_lo[0];
assign core_node_data_li[0] = core_data_out [i];
// convention: for signals going between cores
// the "from core" is used as the index.
bsg_comm_link #(.channel_width_p (channel_width_lp)
, .core_channels_p (ring_bytes_lp)
, .link_channels_p (num_channels_lp)
, .nodes_p(1)
, .channel_mask_p(channel_mask_lp)
, .master_p(!i)
, .master_to_slave_speedup_p(master_to_slave_speedup_lp)
, .snoop_vec_p(1'b1) // ignore packet formats
, .enabled_at_start_vec_p(1'b1) // enable at start
, .master_bypass_test_p(5'b1_1_1_1_1)
) comm_link
(.core_clk_i (core_clk [i] )
, .async_reset_i ( (i ? slave_reset_tline[0] : async_reset) )
, .core_calib_reset_r_o(core_calib_reset [i] )
, .io_master_clk_i (io_master_clk [i] )
// in from core
, .core_node_v_i(core_valid_out [i])
, .core_node_data_i(core_node_data_li)
, .core_node_yumi_o(core_yumi_out[i])
// out to core
, .core_node_v_o(core_valid_in [i])
, .core_node_data_o(core_node_data_lo)
, .core_node_ready_i(core_ready_in [i])
// ignore enable and reset.
, .core_node_en_r_o()
, .core_node_reset_r_o(core_reset_in[i])
// in from i/o
, .io_valid_tline_i( io_valid_tline [!i])
, .io_data_tline_i( io_data_tline [!i])
, .io_clk_tline_i( io_clk_tline [!i]) // clk
, .io_token_clk_tline_o( token_clk_tline [i] ) // clk
// out to i/o
, .im_valid_tline_o(io_valid_tline[i])
, .im_data_tline_o( io_data_tline[i])
, .im_clk_tline_o( io_clk_tline[i]) // clk
, .im_slave_reset_tline_r_o ( slave_reset_tline[i])
, .token_clk_tline_i(token_clk_tline[!i]) // clk
// use core_calib_reset instead!
, .core_async_reset_danger_o (core_async_reset [i] )
);
end
localparam cycle_counter_width_lp=32;
// create some counters to track the four clocks in the system
logic [cycle_counter_width_lp-1:0] core_ctr[1:0];
logic [cycle_counter_width_lp-1:0] io_ctr [1:0];
// valid only in testbench code: reset violation
for (i = 0; i < 2; i=i+1)
begin
bsg_cycle_counter #(.width_p(cycle_counter_width_lp))
my_core_ctr (.clk_i(core_clk[i]), .reset_i(core_calib_reset[i]), .ctr_r_o(core_ctr[i]));
bsg_cycle_counter #(.width_p(cycle_counter_width_lp))
my_io_ctr (.clk_i(io_master_clk[i]), .reset_i(core_calib_reset[i]), .ctr_r_o(io_ctr[i]));
test_bsg_comm_link_checker
#(.channel_width_p(channel_width_lp)
,.num_channels_p(num_channels_lp)
,.ring_bytes_p (ring_bytes_lp)
,.verbose_p (verbose_lp)
,.iterations_p (iterations_lp)
,.core_0_period_p(core_0_period_lp)
,.core_1_period_p(core_1_period_lp)
,.io_master_0_period_p(io_master_0_period_lp)
,.io_master_1_period_p(io_master_1_period_lp)
,.cycle_counter_width_p(cycle_counter_width_lp)
,.node_num_p(i)
) checker
(.clk (core_clk[i])
,.valid_in(core_valid_in[i])
,.ready_in(core_ready_in[i])
,.data_in (core_data_in[i] )
,.data_out(core_data_out[i])
,.yumi_out(core_yumi_out[i])
,.async_reset(core_async_reset[i])
,.slave_reset_tline(slave_reset_tline[i])
,.io_valid_tline(io_valid_tline[i])
,.io_data_tline (io_data_tline[i])
,.core_ctr(core_ctr)
,.io_ctr(io_ctr)
);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_SYMBOL_V
/**
* lpflow_bleeder: Current bleeder (weak pulldown to ground).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_bleeder (
//# {{power|Power}}
input SHORT
);
// Voltage supply signals
wire VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_gpio_ovtv2 ( IN, IN_H, TIE_HI_ESD, TIE_LO_ESD, AMUXBUS_A,
AMUXBUS_B, PAD, PAD_A_ESD_0_H, PAD_A_ESD_1_H, PAD_A_NOESD_H,
VCCD, VCCHIB,VDDA, VDDIO, VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH,
ANALOG_EN, ANALOG_POL, ANALOG_SEL, DM, ENABLE_H, ENABLE_INP_H, ENABLE_VDDA_H, ENABLE_VDDIO, ENABLE_VSWITCH_H, HLD_H_N,
HLD_OVR, IB_MODE_SEL, INP_DIS, OE_N, OUT, SLOW, SLEW_CTL, VTRIP_SEL, HYS_TRIM, VINREF );
input OUT;
input OE_N;
input HLD_H_N;
input ENABLE_H;
input ENABLE_INP_H;
input ENABLE_VDDA_H;
input ENABLE_VDDIO;
input ENABLE_VSWITCH_H;
input INP_DIS;
input VTRIP_SEL;
input HYS_TRIM;
input SLOW;
input [1:0] SLEW_CTL;
input HLD_OVR;
input ANALOG_EN;
input ANALOG_SEL;
input ANALOG_POL;
input [2:0] DM;
input [1:0] IB_MODE_SEL;
input VINREF;
inout VDDIO;
inout VDDIO_Q;
inout VDDA;
inout VCCD;
inout VSWITCH;
inout VCCHIB;
inout VSSA;
inout VSSD;
inout VSSIO_Q;
inout VSSIO;
inout PAD;
inout PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H;
inout AMUXBUS_A;
inout AMUXBUS_B;
output IN;
output IN_H;
output TIE_HI_ESD, TIE_LO_ESD;
wire hld_h_n_del;
wire hld_h_n_buf;
reg [2:0] dm_final;
reg [1:0] slew_ctl_final;
reg slow_final, vtrip_sel_final, inp_dis_final, out_final, oe_n_final, hld_ovr_final, hys_trim_final, analog_en_final,analog_en_vdda, analog_en_vswitch,analog_en_vddio_q;
reg [1:0] ib_mode_sel_final;
wire [2:0] dm_del;
wire [1:0] slew_ctl_del;
wire [1:0] ib_mode_sel_del;
wire slow_del, vtrip_sel_del, inp_dis_del, out_del, oe_n_del, hld_ovr_del, hys_trim_del;
wire [2:0] dm_buf;
wire [1:0] slew_ctl_buf;
wire [1:0] ib_mode_sel_buf;
wire slow_buf, vtrip_sel_buf, inp_dis_buf, out_buf, oe_n_buf, hld_ovr_buf, hys_trim_buf;
reg notifier_dm, notifier_slow, notifier_oe_n, notifier_out, notifier_vtrip_sel, notifier_hld_ovr, notifier_inp_dis;
reg notifier_slew_ctl, notifier_ib_mode_sel, notifier_hys_trim;
reg notifier_enable_h, notifier, dummy_notifier1;
assign hld_h_n_buf = HLD_H_N;
assign hld_ovr_buf = HLD_OVR;
assign dm_buf = DM;
assign inp_dis_buf = INP_DIS;
assign vtrip_sel_buf = VTRIP_SEL;
assign slow_buf = SLOW;
assign oe_n_buf = OE_N;
assign out_buf = OUT;
assign ib_mode_sel_buf = IB_MODE_SEL;
assign slew_ctl_buf = SLEW_CTL;
assign hys_trim_buf = HYS_TRIM;
wire pwr_good_amux = ((hld_h_n_buf===0 || ENABLE_H===0) ? 1:(VCCD===1)) && (VSSD===0) && (VSSA===0) && (VSSIO_Q===0);
wire pwr_good_output_driver = (VDDIO===1) && (VDDIO_Q===1)&& (VSSIO===0) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_hold_ovr_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCHIB===1);
wire pwr_good_active_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0);
wire pwr_good_active_mode_vdda = (VDDA===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode_vdda = (VDDA===1) && (VSSD===0);
wire pwr_good_inpbuff_hv = (VDDIO_Q===1) && (inp_dis_final===0 && dm_final!==3'b000 && ib_mode_sel_final===2'b01 ? VCCHIB===1 : 1) && (VSSD===0);
wire pwr_good_inpbuff_lv = (VDDIO_Q===1) && (VSSD===0) && (VCCHIB===1);
wire pwr_good_analog_en_vdda = (VDDA===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vddio_q = (VDDIO_Q ===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vswitch = (VSWITCH ===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_amux_vccd = ((hld_h_n_buf===0 || ENABLE_H===0) ? 1:(VCCD===1));
parameter MAX_WARNING_COUNT = 100;
wire pad_tristate = oe_n_final === 1 || dm_final === 3'b000 || dm_final === 3'b001;
wire x_on_pad = !pwr_good_output_driver
|| (dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'bx)
|| (^dm_final[2:0] === 1'bx && oe_n_final===1'b0)
|| (slow_final===1'bx && dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'b0)
|| (slow_final===1'b1 && ^slew_ctl_final[1:0] ===1'bx && dm_final === 3'b100 && oe_n_final===1'b0);
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLOW_BEHV
parameter SLOW_1_DELAY= 70 ;
parameter SLOW_0_DELAY= 40;
`else
parameter SLOW_1_DELAY= 0;
parameter SLOW_0_DELAY= 0;
`endif
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLEW_BEHV
parameter SLEW_00_DELAY= 127 ;
parameter SLEW_01_DELAY= 109;
parameter SLEW_10_DELAY= 193;
parameter SLEW_11_DELAY= 136;
`else
parameter SLEW_00_DELAY= 0 ;
parameter SLEW_01_DELAY= 0;
parameter SLEW_10_DELAY= 0;
parameter SLEW_11_DELAY= 0;
`endif
integer slow_1_delay,slow_0_delay,slow_delay,slew_00_delay,slew_01_delay,slew_10_delay,slew_11_delay;
initial slow_1_delay = SLOW_1_DELAY;
initial slow_0_delay = SLOW_0_DELAY;
initial slew_00_delay = SLEW_00_DELAY;
initial slew_01_delay = SLEW_01_DELAY;
initial slew_10_delay = SLEW_10_DELAY;
initial slew_11_delay = SLEW_11_DELAY;
always @(*)
begin
if (SLOW===1)
begin
if (DM[2]===1 && DM[1]===0 && DM[0]===0)
begin
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLEW_BEHV
if (SLEW_CTL[1] ===0 && SLEW_CTL[0] ===0)
slow_delay = slew_00_delay;
else if (SLEW_CTL[1] ===0 && SLEW_CTL[0] ===1)
slow_delay = slew_01_delay;
else if (SLEW_CTL[1] ===1 && SLEW_CTL[0] ===0)
slow_delay = slew_10_delay;
else if (SLEW_CTL[1] ===1 && SLEW_CTL[0] ===1)
slow_delay = slew_11_delay;
`else
slow_delay = slow_1_delay;
`endif
end
else
slow_delay = slow_1_delay;
end
else
slow_delay = slow_0_delay;
end
bufif1 (pull1, strong0) #slow_delay dm2 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b010));
bufif1 (strong1, pull0) #slow_delay dm3 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b011));
bufif1 (highz1, strong0) #slow_delay dm4 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b100));
bufif1 (strong1, highz0) #slow_delay dm5 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b101));
bufif1 (strong1, strong0) #slow_delay dm6 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b110));
bufif1 (pull1, pull0) #slow_delay dm7 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b111));
tran pad_esd_1 (PAD,PAD_A_NOESD_H);
tran pad_esd_2 (PAD,PAD_A_ESD_0_H);
tran pad_esd_3 (PAD,PAD_A_ESD_1_H);
wire x_on_in_hv = (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (^ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b00)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b01)
|| (ib_mode_sel_final[1]===1'b1 && VINREF !== 1'b1 && inp_dis_final===0 && dm_final !== 3'b000)
|| (ib_mode_sel_final[1]===1'b1 && hys_trim_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000);
wire x_on_in_lv = (ENABLE_H===0 && ^ENABLE_VDDIO===1'bx)
|| (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (^ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b00)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 )
|| (ib_mode_sel_final[1]===1'b1 && VINREF !== 1'b1 && inp_dis_final===0 && dm_final !== 3'b000)
|| (ib_mode_sel_final[1]===1'b1 && hys_trim_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000);
wire disable_inp_buff = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_INP_H===0;
assign IN_H = (x_on_in_hv===1 || pwr_good_inpbuff_hv===0) ? 1'bx : (disable_inp_buff===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
wire disable_inp_buff_lv = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_VDDIO===0;
assign IN = (x_on_in_lv ===1 || pwr_good_inpbuff_lv===0) ? 1'bx : (disable_inp_buff_lv===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
assign TIE_HI_ESD = VDDIO===1'b1 ? 1'b1 : 1'bx;
assign TIE_LO_ESD = VSSIO===1'b0 ? 1'b0 : 1'bx;
wire functional_mode_amux = (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_analog_en_vswitch ===1 );
wire x_on_analog_en_vdda = (pwr_good_analog_en_vdda !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VDDA_H ===1'bx) ));
wire zero_on_analog_en_vdda = ( (pwr_good_analog_en_vdda ===1 && ENABLE_VDDA_H ===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vddio_q = ( pwr_good_analog_en_vddio_q !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) ));
wire zero_on_analog_en_vddio_q = ( (pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vswitch = (pwr_good_analog_en_vswitch !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VSWITCH_H ===1'bx) ));
wire zero_on_analog_en_vswitch = ( (pwr_good_analog_en_vswitch ===1 && ENABLE_VSWITCH_H ===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
always @(*)
begin : LATCH_dm
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
dm_final <= 3'bxxx;
end
else if (ENABLE_H===0)
begin
dm_final <= 3'b000;
end
else if (hld_h_n_buf===1)
begin
dm_final <= (^dm_buf[2:0] === 1'bx || !pwr_good_active_mode) ? 3'bxxx : dm_buf;
end
end
always @(notifier_enable_h or notifier_dm)
begin
disable LATCH_dm; dm_final <= 3'bxxx;
end
always @(*)
begin : LATCH_inp_dis
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
inp_dis_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
inp_dis_final <= 1'b1;
end
else if (hld_h_n_buf===1)
begin
inp_dis_final <= (^inp_dis_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : inp_dis_buf;
end
end
always @(notifier_enable_h or notifier_inp_dis)
begin
disable LATCH_inp_dis; inp_dis_final <= 1'bx;
end
always @(*)
begin : LATCH_ib_mode_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
ib_mode_sel_final <= 2'bxx;
end
else if (ENABLE_H===0)
begin
ib_mode_sel_final <= 2'b00;
end
else if (hld_h_n_buf===1)
begin
ib_mode_sel_final <= (^ib_mode_sel_buf[1:0] === 1'bx || !pwr_good_active_mode) ? 2'bxx : ib_mode_sel_buf;
end
end
always @(notifier_enable_h or notifier_ib_mode_sel)
begin
disable LATCH_ib_mode_sel; ib_mode_sel_final <= 2'bxx;
end
always @(*)
begin : LATCH_slew_ctl_final
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slew_ctl_final <= 2'bxx;
end
else if (ENABLE_H===0)
begin
slew_ctl_final <= 2'b00;
end
else if (hld_h_n_buf===1)
begin
slew_ctl_final <= (^slew_ctl_buf[1:0] === 1'bx || !pwr_good_active_mode) ? 2'bxx : slew_ctl_buf;
end
end
always @(notifier_enable_h or notifier_slew_ctl)
begin
disable LATCH_slew_ctl_final; slew_ctl_final <= 2'bxx;
end
always @(*)
begin : LATCH_vtrip_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
vtrip_sel_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
vtrip_sel_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
vtrip_sel_final <= (^vtrip_sel_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : vtrip_sel_buf;
end
end
always @(notifier_enable_h or notifier_vtrip_sel)
begin
disable LATCH_vtrip_sel; vtrip_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_hys_trim
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hys_trim_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hys_trim_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hys_trim_final <= (^hys_trim_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hys_trim_buf;
end
end
always @(notifier_enable_h or notifier_hys_trim)
begin
disable LATCH_hys_trim; hys_trim_final <= 1'bx;
end
always @(*)
begin : LATCH_slow
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slow_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
slow_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
slow_final <= (^slow_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : slow_buf;
end
end
always @(notifier_enable_h or notifier_slow)
begin
disable LATCH_slow; slow_final <= 1'bx;
end
always @(*)
begin : LATCH_hld_ovr
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hld_ovr_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hld_ovr_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hld_ovr_final <= (^hld_ovr_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hld_ovr_buf;
end
end
always @(notifier_enable_h or notifier_hld_ovr)
begin
disable LATCH_hld_ovr; hld_ovr_final <= 1'bx;
end
always @(*)
begin : LATCH_oe_n
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx || (hld_h_n_buf===0 && hld_ovr_final===1'bx)|| (hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
oe_n_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
oe_n_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
oe_n_final <= (^oe_n_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : oe_n_buf;
end
end
always @(notifier_enable_h or notifier_oe_n)
begin
disable LATCH_oe_n; oe_n_final <= 1'bx;
end
always @(*)
begin : LATCH_out
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx ||(hld_h_n_buf===0 && hld_ovr_final===1'bx)||(hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
out_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
out_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
out_final <= (^out_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : out_buf;
end
end
always @(notifier_enable_h or notifier_out)
begin
disable LATCH_out; out_final <= 1'bx;
end
always @(*)
begin
if (x_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'bx;
end
else if ( zero_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'b0;
end
else if (x_on_analog_en_vdda !==1 && zero_on_analog_en_vdda !==1)
begin
analog_en_vdda <= ANALOG_EN;
end
if (x_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'bx;
end
else if ( zero_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'b0;
end
else if ( x_on_analog_en_vddio_q !==1 && zero_on_analog_en_vddio_q !==1)
begin
analog_en_vddio_q <= ANALOG_EN;
end
if (x_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'bx;
end
else if ( zero_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'b0;
end
else if (x_on_analog_en_vswitch !==1 && zero_on_analog_en_vswitch !==1)
begin
analog_en_vswitch <= ANALOG_EN;
end
if ( (analog_en_vswitch ===1'bx && analog_en_vdda ===1'bx) || (analog_en_vswitch ===1'bx && analog_en_vddio_q ===1'bx) || (analog_en_vddio_q ===1'bx && analog_en_vdda ===1'bx ) )
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vdda ===1'bx && (analog_en_vddio_q ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vddio_q ===1'bx && (analog_en_vdda ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vswitch===1'bx && (analog_en_vdda ===1 || analog_en_vddio_q ===1 ))
begin
analog_en_final <= 1'bx;
end
else if ((analog_en_vdda ===0 && analog_en_vddio_q ===0 )|| (analog_en_vdda ===0 && analog_en_vswitch===0 ) || (analog_en_vddio_q ===0 && analog_en_vswitch===0 ))
begin
analog_en_final <=0;
end
else if (analog_en_vdda ===1 && analog_en_vddio_q ===1 && analog_en_vswitch ===1)
begin
analog_en_final <=1;
end
end
wire [2:0] amux_select = {ANALOG_SEL, ANALOG_POL, out_buf};
wire invalid_controls_amux = (analog_en_final===1'bx && inp_dis_final===1)
|| !pwr_good_amux
|| (analog_en_final===1 && ^amux_select[2:0] === 1'bx && inp_dis_final===1);
wire enable_pad_amuxbus_a = invalid_controls_amux ? 1'bx : (amux_select===3'b001 || amux_select===3'b010) && (analog_en_final===1);
wire enable_pad_amuxbus_b = invalid_controls_amux ? 1'bx : (amux_select===3'b101 || amux_select===3'b110) && (analog_en_final===1);
wire enable_pad_vssio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b100 || amux_select===3'b000) && (analog_en_final===1);
wire enable_pad_vddio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b011 || amux_select===3'b111) && (analog_en_final===1);
tranif1 pad_amuxbus_a (PAD, AMUXBUS_A, enable_pad_amuxbus_a);
tranif1 pad_amuxbus_b (PAD, AMUXBUS_B, enable_pad_amuxbus_b);
bufif1 pad_vddio_q (PAD, VDDIO_Q, enable_pad_vddio_q);
bufif1 pad_vssio_q (PAD, VSSIO_Q, enable_pad_vssio_q);
reg dis_err_msgs;
integer msg_count_pad,msg_count_pad1,msg_count_pad2,msg_count_pad3,msg_count_pad4,msg_count_pad5,msg_count_pad6,msg_count_pad7,msg_count_pad8,msg_count_pad9,msg_count_pad10,msg_count_pad11,msg_count_pad12;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0;
msg_count_pad1 = 0;
msg_count_pad2 = 0;
msg_count_pad3 = 0;
msg_count_pad4 = 0;
msg_count_pad5 = 0;
msg_count_pad6 = 0;
msg_count_pad7 = 0;
msg_count_pad8 = 0;
msg_count_pad9 = 0;
msg_count_pad10 = 0;
msg_count_pad11 = 0;
msg_count_pad12 = 0;
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
wire #100 error_enable_vddio = (ENABLE_VDDIO===0 && ENABLE_H===1);
event event_error_enable_vddio;
always @(error_enable_vddio)
begin
if (!dis_err_msgs)
begin
if (error_enable_vddio===1)
begin
msg_count_pad = msg_count_pad + 1;
->event_error_enable_vddio;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : Enable_h (= %b) and ENABLE_VDDIO (= %b) are complement of each \other. This is an illegal combination as ENABLE_VDDIO and ENABLE_H are the same input signals IN different power \domains %m", ENABLE_H, ENABLE_VDDIO, $stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda = ( VDDA===1 && VDDIO_Q !==1 && ENABLE_VDDA_H===1 );
event event_error_vdda;
always @(error_vdda)
begin
if (!dis_err_msgs)
begin
if (error_vdda===1)
begin
msg_count_pad1 = msg_count_pad1 + 1;
->event_error_vdda;
if (msg_count_pad1 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VDDA_H (= %b) cannot be 1 when VDDA (= %b) and VDDIO_Q (= %b) %m",ENABLE_VDDA_H, VDDA,VDDIO_Q,$stime);
end
else
if (msg_count_pad1 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda2 = ( VDDA===1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && VCCD===1 && ANALOG_EN ===1 );
event event_error_vdda2;
always @(error_vdda2)
begin
if (!dis_err_msgs)
begin
if (error_vdda2===1)
begin
msg_count_pad2 = msg_count_pad2 + 1;
->event_error_vdda2;
if (msg_count_pad2 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b),hld_h_n_buf (= %b) and VCCD (= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad2 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda3 = ( VDDA===1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && VCCD !==1 );
event event_error_vdda3;
always @(error_vdda3)
begin
if (!dis_err_msgs)
begin
if (error_vdda3===1)
begin
msg_count_pad3 = msg_count_pad3 + 1;
->event_error_vdda3;
if (msg_count_pad3 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : VCCD (= %b) cannot be any value other than 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",VCCD,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad3 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch1 = (VDDA !==1 && VDDIO_Q !==1 && VSWITCH ===1 && (ENABLE_VSWITCH_H===1)) ;
event event_error_vswitch1;
always @(error_vswitch1)
begin
if (!dis_err_msgs)
begin
if (error_vswitch1===1)
begin
msg_count_pad4 = msg_count_pad4 + 1;
->event_error_vswitch1;
if (msg_count_pad4 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad4 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch2 = (VDDA !==1 && VDDIO_Q !==1 && VSWITCH ===1 && VCCD===1 && ANALOG_EN===1);
event event_error_vswitch2;
always @(error_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vswitch2===1)
begin
msg_count_pad5 = msg_count_pad5 + 1;
->event_error_vswitch2;
if (msg_count_pad5 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b) & VCCD(= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,VCCD,$stime);
end
else
if (msg_count_pad5 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch3 = (VDDA ===1 && VDDIO_Q !==1 && VSWITCH ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch3;
always @(error_vswitch3)
begin
if (!dis_err_msgs)
begin
if (error_vswitch3===1)
begin
msg_count_pad6 = msg_count_pad6 + 1;
->event_error_vswitch3;
if (msg_count_pad6 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad6 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch4 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch4;
always @(error_vswitch4)
begin
if (!dis_err_msgs)
begin
if (error_vswitch4===1)
begin
msg_count_pad7 = msg_count_pad7 + 1;
->event_error_vswitch4;
if (msg_count_pad7 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad7 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch5 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1);
event event_error_vswitch5;
always @(error_vswitch5)
begin
if (!dis_err_msgs)
begin
if (error_vswitch5===1)
begin
msg_count_pad8 = msg_count_pad8 + 1;
->event_error_vswitch5;
if (msg_count_pad8 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b),hld_h_n_buf (= %b) and VCCD (= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad8 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q1 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD!==1);
event event_error_vddio_q1;
always @(error_vddio_q1)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q1===1)
begin
msg_count_pad9 = msg_count_pad9 + 1;
->event_error_vddio_q1;
if (msg_count_pad9 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : VCCD(= %b) cannot be any value other than 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",VCCD,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad9 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q2 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1);
event event_error_vddio_q2;
always @(error_vddio_q2)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q2===1)
begin
msg_count_pad10 = msg_count_pad10 + 1;
->event_error_vddio_q2;
if (msg_count_pad10 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b) , hld_h_n_buf (= %b) && VCCD (= %b) %m",ANALOG_EN, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad10 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_supply_good = ( VDDA ===1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1 && ENABLE_VSWITCH_H !==1 && ENABLE_VSWITCH_H !==0 );
event event_error_supply_good;
always @(error_supply_good)
begin
if (!dis_err_msgs)
begin
if (error_supply_good===1)
begin
msg_count_pad11 = msg_count_pad11 + 1;
->event_error_supply_good;
if (msg_count_pad11 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) should be either 1 or 0 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,VCCD (= %b) and ANALOG_EN(= %b) %m",ENABLE_VSWITCH_H, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,ANALOG_EN,$stime);
end
else
if (msg_count_pad11 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda_vddioq_vswitch2 = ( VDDA ===1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1 && ENABLE_VDDA_H !==1 && ENABLE_VDDA_H !==0 );
event event_error_vdda_vddioq_vswitch2;
always @(error_vdda_vddioq_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vdda_vddioq_vswitch2===1)
begin
msg_count_pad12 = msg_count_pad12 + 1;
->event_error_vdda_vddioq_vswitch2;
if (msg_count_pad12 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VDDA_H(= %b) should be either 1 or 0 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,VCCD (= %b) and ANALOG_EN(= %b) %m",ENABLE_VDDA_H, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,ANALOG_EN,$stime);
end
else
if (msg_count_pad12 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
/**
* Copyright (C) 2009 Ubixum, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
**/
// Author: Lane Brooks
// Date: 10/31/2009
// Desc: Implements a low level SPI master interface. Set the
// DATA_WIDTH parameter at instatiation. Put the data you want
// to send on the 'datai' port and strobe the 'go' signal. The
// bits of 'datai' will get serially shifted out to the device
// and the bits coming back from the device will get serially
// shifted into the 'datao' register. Hook up the 'csb',
// 'sclk', 'din', and 'dout' wires to the device. 'busy' is
// high while the shift is running and goes low when the shift
// is complete.
//
// The NUM_PORTS parameter can be used when the 'csb' and 'sclk'
// lines are shared with multiple devices and the 'din' and 'dout'
// lines are unique. For example, if you have two devices, the
// specify NUM_PORTS=2 and 'din' and 'dout' become width 2 ports
// and 'datai' and 'datao' become DATA_WIDTH*NUM_PORTS wide.
//
// Set the CLK_DIVIDER_WIDTH at instantiation. The rate of
// 'sclk' to the device is then set by the input 'clk_divider'.
// 'clk_divider' must be at least 2.
//
// The clock polarity and phasing of this master is set via the
// CPOL and CPHA inputs. See
// http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
// a description of these conventions.
//
//
// Modifications:
// Author: Kurt Snieckus, Eventide Inc.
// Date: 07/01/2014
// Desc: Hacked-in control signal to limit number of clock cycles to half
// DATA_WIDTH for a system which required 16 bit reads and 8 bit reads
`define SYNC_RESET
module spi_master
#(parameter DATA_WIDTH=16,
NUM_PORTS=1,
CLK_DIVIDER_WIDTH=8
)
(input clk,
input resetb,
input CPOL,
input CPHA,
input half_cycle_n,
input [CLK_DIVIDER_WIDTH-1:0] clk_divider,
input go,
input [(NUM_PORTS*DATA_WIDTH)-1:0] datai,
output [(NUM_PORTS*DATA_WIDTH)-1:0] datao,
output reg busy,
output reg done,
input [NUM_PORTS-1:0] dout,
output [NUM_PORTS-1:0] din,
output reg csb,
output reg sclk
);
reg [NUM_PORTS-1:0] dout_s;
reg [CLK_DIVIDER_WIDTH-1:0] clk_count;
wire [CLK_DIVIDER_WIDTH-1:0] next_clk_count = clk_count + 1;
wire pulse = next_clk_count == (clk_divider >> 1);
reg state;
`ifdef verilator
localparam LOG2_DATA_WIDTH = $clog2(DATA_WIDTH+1);
`else
function integer log2;
input integer value;
integer count;
begin
value = value-1;
for (count=0; value>0; count=count+1)
value = value>>1;
log2=count;
end
endfunction
localparam LOG2_DATA_WIDTH = log2(DATA_WIDTH+1);
`endif
reg [LOG2_DATA_WIDTH:0] shift_count;
wire start = shift_count == 0;
/* verilator lint_off WIDTH */
wire [31:0] stop_detect = ((half_cycle_n)+1)*DATA_WIDTH-1;
wire stop = shift_count >= stop_detect;
/* verilator lint_on WIDTH */
localparam IDLE_STATE = 0,
RUN_STATE = 1;
sro #(.DATA_WIDTH(DATA_WIDTH)) sro[NUM_PORTS-1:0]
(.clk(clk),
.resetb(resetb),
.shift(pulse && !csb && (shift_count[0] == 0)),
.dout(dout),
.datao(datao));
sri #(.DATA_WIDTH(DATA_WIDTH)) sri[NUM_PORTS-1:0]
(.clk(clk),
.resetb(resetb),
.datai(half_cycle_n ? datai : {datai[DATA_WIDTH/2-1:0], {DATA_WIDTH/2{1'b0}}}),
.sample(go && (state == IDLE_STATE)), // we condition on state so that if the user holds 'go' high, this will sample only at the start of the transfer
.shift(pulse && !csb && (shift_count[0] == 1)),
.din(din));
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
clk_count <= 0;
shift_count <= 0;
sclk <= 1;
csb <= 1;
state <= IDLE_STATE;
busy <= 0;
done <= 0;
end else begin
// generate the pulse train
if(pulse) begin
clk_count <= 0;
end else begin
clk_count <= next_clk_count;
end
// generate csb
if(state == IDLE_STATE) begin
csb <= 1;
shift_count <= 0;
done <= 0;
if(go && !busy) begin // the !busy condition here allows the user to hold go high and this will then run transactions back-to-back at maximum speed where busy drops at for at least one clock cycle but we stay in this idle state for two clock cycles. Staying in idle state for two cycles probably isn't a big deal since the serial clock is running slower anyway.
state <= RUN_STATE;
busy <= 1;
end else begin
busy <= 0;
end
end else begin
if(pulse) begin
if(stop) begin
csb <= 1;
state <= IDLE_STATE;
done <= 1;
end else begin
csb <= 0;
if(!csb) begin
shift_count <= shift_count + 1;
end
end
end
end
// generate sclk
if(pulse) begin
if((CPHA==1 && state==RUN_STATE && !stop) ||
(CPHA==0 && !csb)) begin
sclk <= !sclk;
end else begin
sclk <= CPOL;
end
end
end
end
endmodule // spi_master
module sri
// This is a shift register that sends data out to the di lines of
// spi slaves.
#(parameter DATA_WIDTH=16)
(input clk,
input resetb,
input [DATA_WIDTH-1:0] datai,
input sample,
input shift,
output din
);
reg [DATA_WIDTH-1:0] sr_reg;
assign din = sr_reg[DATA_WIDTH-1];
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
sr_reg <= 0;
end else begin
if(sample) begin
sr_reg <= datai;
end else if(shift) begin
sr_reg <= sr_reg << 1;
end
end
end
endmodule
module sro
// This is a shift register that receives data on the dout lines
// from spi slaves.
#(parameter DATA_WIDTH=16)
(input clk,
input resetb,
input shift,
input dout,
output reg [DATA_WIDTH-1:0] datao
);
reg dout_s;
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
dout_s <= 0;
datao <= 0;
end else begin
dout_s <= dout;
if(shift) begin
datao <= { datao[DATA_WIDTH-2:0], dout_s };
end
end
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_never_unknown_async (reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NEVER_UNKNOWN_ASYNC";
`include "std_ovl_reset.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_never_unknown_async_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_never_unknown_async_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_never_unknown_async_psl_logic.v"
`else
`endmodule // ovl_never_unknown_async
`endif
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: dblfetch.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This is one step beyond the simplest instruction fetch,
// prefetch.v. dblfetch.v uses memory pipelining to fetch two
// instruction words in one cycle, figuring that the unpipelined CPU can't
// go through both at once, but yet recycles itself fast enough for the
// next instruction that would follow. It is designed to be a touch
// faster than the single instruction prefetch, although not as fast as
// the prefetch and cache found elsewhere.
//
// There are some gotcha's in this logic, however. For example, it's
// illegal to switch devices mid-transaction, since the second device
// might have different timing. I.e. the first device might take 8
// clocks to create an ACK, and the second device might take 2 clocks, the
// acks might therefore come on top of each other, or even out of order.
// But ... in order to keep logic down, we keep track of the PC in the
// o_wb_addr register. Hence, this register gets changed on any i_new_pc.
// The i_pc value associated with i_new_pc will only be valid for one
// clock, hence we can't wait to change. To keep from violating the WB
// rule, therefore, we *must* immediately stop requesting any transaction,
// and then terminate the bus request as soon as possible.
//
// This has consequences in terms of logic used, leaving this routine
// anything but simple--even though the number of wires affected by
// this is small (o_wb_cyc, o_wb_stb, and last_ack).
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module dblfetch(i_clk, i_rst, i_new_pc, i_clear_cache,
i_stall_n, i_pc, o_i, o_pc, o_v,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
o_illegal);
parameter ADDRESS_WIDTH=32, AUX_WIDTH = 1;
localparam AW=ADDRESS_WIDTH;
input wire i_clk, i_rst, i_new_pc, i_clear_cache,
i_stall_n;
input wire [(AW-1):0] i_pc;
output reg [31:0] o_i;
output reg [(AW-1):0] o_pc;
output wire o_v;
// Wishbone outputs
output reg o_wb_cyc, o_wb_stb;
output wire o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output wire [31:0] o_wb_data;
// And return inputs
input wire i_wb_ack, i_wb_stall, i_wb_err;
input wire [31:0] i_wb_data;
// And ... the result if we got an error
output reg o_illegal;
assign o_wb_we = 1'b0;
assign o_wb_data = 32'h0000;
reg last_ack, last_stb, invalid_bus_cycle;
reg [31:0] cache [0:1];
reg cache_read_addr, cache_write_addr;
reg [1:0] cache_valid;
initial o_wb_cyc = 1'b0;
initial o_wb_stb = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(i_wb_err))
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
end else if (o_wb_cyc)
begin
if ((o_wb_stb)&&(!i_wb_stall))
o_wb_stb <= !last_stb;
if ((i_new_pc)||(invalid_bus_cycle))
o_wb_stb <= 1'b0;
if ((i_wb_ack)&&(
// Relase the bus on the second ack
(last_ack)
// Or on the first ACK, if we've been told
// we have an invalid bus cycle
||((o_wb_stb)&&(i_wb_stall)&&(last_stb)&&(
(i_new_pc)||(invalid_bus_cycle)))
))
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
end
if ((!last_stb)&&(i_wb_stall)
&&((i_new_pc)||(invalid_bus_cycle)))
// Also release the bus with no acks on a new
// address request, if we haven't made any
// bus requests that need to be answered
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
end
end else if ((invalid_bus_cycle)
||((o_v)&&(i_stall_n)&&(cache_read_addr))) // Initiate a bus cycle
begin
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
// last_stb <= 1'b0;
// last_ack <= 1'b0;
end
initial last_stb = 1'b0;
always @(posedge i_clk)
if ((o_wb_cyc)&&(o_wb_stb)&&(!i_wb_stall))
last_stb <= 1'b1;
else if (!o_wb_cyc)
last_stb <= 1'b0;
initial last_ack = 1'b0;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
last_ack <= 1'b1;
else if ((o_wb_cyc)&&(o_wb_stb)&&(i_wb_stall)&&(
(i_new_pc)||(invalid_bus_cycle)))
last_ack <= 1'b1;
else if ((o_wb_cyc)&&(o_wb_stb)&&(!i_wb_stall)&&(!last_stb)&&(
(i_new_pc)||(invalid_bus_cycle)))
last_ack <= 1'b1;
else if (!o_wb_cyc)
last_ack <= 1'b0;
initial invalid_bus_cycle = 1'b0;
always @(posedge i_clk)
if (i_rst)
invalid_bus_cycle <= 1'b0;
else if ((i_new_pc)||(i_clear_cache))
invalid_bus_cycle <= 1'b1;
else if (!o_wb_cyc)
invalid_bus_cycle <= 1'b0;
initial o_wb_addr = {(AW){1'b1}};
always @(posedge i_clk)
if (i_new_pc)
o_wb_addr <= i_pc;
else if ((o_wb_stb)&&(!i_wb_stall)&&(!invalid_bus_cycle))
o_wb_addr <= o_wb_addr + 1'b1;
initial cache_write_addr = 1'b0;
always @(posedge i_clk)
if (!o_wb_cyc)
cache_write_addr <= 1'b0;
else if ((o_wb_cyc)&&(i_wb_ack))
cache_write_addr <= cache_write_addr + 1'b1;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
cache[cache_write_addr] <= i_wb_data;
initial cache_read_addr = 1'b0;
always @(posedge i_clk)
if ((i_new_pc)||(invalid_bus_cycle)
||((o_v)&&(cache_read_addr)&&(i_stall_n)))
cache_read_addr <= 1'b0;
else if ((o_v)&&(i_stall_n))
cache_read_addr <= 1'b1;
always @(posedge i_clk)
if ((i_new_pc)||(invalid_bus_cycle))
cache_valid <= 2'b00;
else begin
if ((o_v)&&(i_stall_n))
cache_valid[cache_read_addr] <= 1'b0;
if ((o_wb_cyc)&&(i_wb_ack))
cache_valid[cache_write_addr] <= 1'b1;
end
initial o_i = {(32){1'b1}};
always @(posedge i_clk)
if (((i_stall_n)||(!o_v))&&(o_wb_cyc)&&(i_wb_ack))
o_i <= i_wb_data;
else
o_i <= cache[cache_read_addr];
initial o_pc = 0;
always @(posedge i_clk)
if (i_new_pc)
o_pc <= i_pc;
else if ((o_v)&&(i_stall_n))
o_pc <= o_pc + 1'b1;
assign o_v = cache_valid[cache_read_addr];
initial o_illegal = 1'b0;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_err))
o_illegal <= 1'b1;
else if ((!o_wb_cyc)&&((i_new_pc)||(invalid_bus_cycle)))
o_illegal <= 1'b0;
endmodule
|
module primogen_bench;
reg clk = 0;
wire rst;
reg go = 0;
reg [31:0] clk_count = 0;
reg [31:0] res_count = 0;
reg overflow = 0;
wire [15:0] gen_res;
wire gen_ready;
wire gen_error;
por pos_inst(
.clk(clk),
.rst(rst));
primogen gen(
.clk(clk),
.go(go),
.rst(rst),
.res(gen_res),
.ready(gen_ready),
.error(gen_error));
always #1 clk = !clk;
always @(posedge clk)
clk_count = clk_count + 1;
initial begin
wait(!rst);
while (clk_count < 20000) begin
// Ask for next prime
@(negedge clk) go = 1;
@(posedge clk) @(negedge clk) go = 0;
// Wait until prime is computed
@(posedge gen_ready);
if (gen_error)
overflow = 1;
if (!overflow)
res_count = res_count + 1;
end
$display("primogen_bench SUCCEEDED: Computed %0d primes in %0d cycles, last prime is %d, %soverflow", res_count, clk_count, gen_res, overflow ? "" : "no ");
$finish;
end
// initial
// $monitor("%t: go = %b, ready = %b, error = %b, res = %h", $time, go, gen_ready, gen_error, gen_res);
endmodule
|
/*******************************************************************************
*
* NetFPGA-10G http://www.netfpga.org
*
* File:
* tx_queue.v
*
* Library:
* hw/osnt/pcores/osnt_10g_interface_v1_11_a
*
* Module:
* tx_queue
*
* Author:
* James Hongyi Zeng
*
* Description:
* AXI-MAC converter: TX side
*
* Copyright notice:
* Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford
* Junior University
*
* Licence:
* This file is part of the NetFPGA 10G development base package.
*
* This file is free code: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 2.1 as
* published by the Free Software Foundation.
*
* This package is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with the NetFPGA source package. If not, see
* http://www.gnu.org/licenses/.
*
*/
module tx_queue
#(
parameter AXI_DATA_WIDTH = 64 //Only 64 is supported right now.
)
(
// AXI side
input [AXI_DATA_WIDTH-1:0] tdata,
input [AXI_DATA_WIDTH/8-1:0] tstrb,
input tvalid,
input tlast,
output tready,
input clk,
input reset,
// MAC side
output [63:0] tx_data,
output reg [ 7:0] tx_data_valid,
output reg tx_start,
input tx_ack,
input clk156,
// Timestamp
input [63:0] stamp_counter
);
localparam IDLE = 0;
localparam WAIT_FOR_ACK = 1;
localparam SEND_PKT = 2;
localparam IFG = 3;
wire [3:0] tx_data_valid_encoded;
reg [7:0] tx_data_valid_decoded;
reg [3:0] tstrb_encoded;
wire eop_axi;
wire eop_mac;
wire fifo_almost_full;
wire fifo_empty, info_fifo_empty;
reg fifo_rd_en, info_fifo_rd_en;
reg info_fifo_wr_en;
reg [2:0] state, state_next;
reg eop_axi_delay, tlast_delay;
reg [4:0] word; // add for mario
reg [AXI_DATA_WIDTH-1:0] tdata_aux;
reg [AXI_DATA_WIDTH/8-1:0] tstrb_aux;
reg tvalid_aux;
reg tlast_aux;
reg [63:0] timestamp;
assign tready = ~fifo_almost_full;
assign eop_axi = tlast_aux;
// Instantiate clock domain crossing FIFO
FIFO36_72 #(
.SIM_MODE("FAST"),
.ALMOST_FULL_OFFSET(9'hA),
.ALMOST_EMPTY_OFFSET(9'hA),
.DO_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.EN_SYN("FALSE"),
.FIRST_WORD_FALL_THROUGH("TRUE")
) tx_fifo (
.ALMOSTEMPTY(),
.ALMOSTFULL(fifo_almost_full),
.DBITERR(),
.DO(tx_data),
.DOP({eop_mac, tx_data_valid_encoded}),
.ECCPARITY(),
.EMPTY(fifo_empty),
.FULL(),
.RDCOUNT(),
.RDERR(),
.SBITERR(),
.WRCOUNT(),
.WRERR(),
.DI(tdata_aux), // add for mario
/*.DI(tdata),*/
.DIP({eop_axi , tstrb_encoded}),
.RDCLK(clk156),
.RDEN(fifo_rd_en),
.RST(reset),
.WRCLK(clk),
.WREN(tvalid_aux & tready)
);
small_async_fifo
#(
.DSIZE (1),
.ASIZE (9),
.ALMOST_FULL_SIZE(500)
) tx_info_fifo
(
.wdata(1'b0),
.winc(info_fifo_wr_en), //Only 1 cycle per packet!
.wclk(clk),
.rdata(),
.rinc(info_fifo_rd_en),
.rclk(clk156),
.rempty(info_fifo_empty),
.r_almost_empty(),
.wfull(),
.w_almost_full(),
.rrst_n(~reset),
.wrst_n(~reset)
);
/* Add for Mario for include timestamp here*/
always @(posedge clk) begin
if (tvalid==1'b1) begin
if (word==5 && tdata[63:16]==48'hFFFFFFFFFFFF) begin
tdata_aux[63:56]<=timestamp[23:16]; //TS tx 6
tdata_aux[55:48]<=timestamp[31:24]; //TS tx 5
tdata_aux[47:40]<=timestamp[39:32]; //TS tx 4
tdata_aux[39:32]<=timestamp[47:40]; //TS tx 3
tdata_aux[31:24]<=timestamp[55:48]; //TS tx 2
tdata_aux[23:16]<=timestamp[63:53]; //TS tx 1*/
tdata_aux[15:0] <= tdata[15:0];
end
else if (word==6 && tdata[15:0]==16'hFFFF) begin
tdata_aux[63:16] <= tdata[63:16];
tdata_aux[15:8]<=timestamp[7:0]; //TS tx 8
tdata_aux[7:0]<=timestamp[15:8]; //TS tx 7
end
else begin
tdata_aux <= tdata;
end
word = word + 1;
end
if (tstrb !=8'hFF) begin
word = 0;
timestamp <=stamp_counter;
end
tstrb_aux <= tstrb;
tvalid_aux <=tvalid;
tlast_aux <=tlast;
end
/* End include for mario*/
// Encoder to map 8bit strobe to 4 bit
always @* begin
case (tx_data_valid_encoded)
4'h0: tx_data_valid_decoded = 8'h1;
4'h1: tx_data_valid_decoded = 8'h3;
4'h2: tx_data_valid_decoded = 8'h7;
4'h3: tx_data_valid_decoded = 8'hF;
4'h4: tx_data_valid_decoded = 8'h1F;
4'h5: tx_data_valid_decoded = 8'h3F;
4'h6: tx_data_valid_decoded = 8'h7F;
4'h7: tx_data_valid_decoded = 8'hFF;
default: tx_data_valid_decoded = 8'h0;
endcase
case (tstrb_aux)
8'h1: tstrb_encoded = 4'h0;
8'h3: tstrb_encoded = 4'h1;
8'h7: tstrb_encoded = 4'h2;
8'hF: tstrb_encoded = 4'h3;
8'h1F: tstrb_encoded = 4'h4;
8'h3F: tstrb_encoded = 4'h5;
8'h7F: tstrb_encoded = 4'h6;
8'hFF: tstrb_encoded = 4'h7;
default: tstrb_encoded = 4'h8;
endcase
end
always @* begin
state_next = state;
fifo_rd_en = 1'b0;
info_fifo_rd_en = 1'b0;
tx_start = 1'b0;
tx_data_valid = tx_data_valid_decoded;
case(state)
IDLE: begin
tx_data_valid = 8'b0;
if(~info_fifo_empty) begin
info_fifo_rd_en = 1'b1;
tx_start = 1'b1;
state_next = WAIT_FOR_ACK;
end
end
WAIT_FOR_ACK: begin
if(tx_ack) begin
fifo_rd_en = 1'b1;
state_next = SEND_PKT;
end
end
SEND_PKT: begin
fifo_rd_en = 1'b1;
if(eop_mac) begin
state_next = IDLE;
end
end
IFG: begin
state_next = IDLE;
tx_data_valid = 8'b0;
end
endcase
end
always @(posedge clk156) begin
if(reset) begin
state <= IDLE;
end
else begin
state <= state_next;
end
end
always @(posedge clk) begin
info_fifo_wr_en <= tlast_aux & tvalid_aux & tready;
end
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pll (
// inputs:
address,
chipselect,
clk,
read,
reset_n,
write,
writedata,
// outputs:
c0,
c1,
readdata,
resetrequest
)
;
output c0;
output c1;
output [ 15: 0] readdata;
output resetrequest;
input [ 2: 0] address;
input chipselect;
input clk;
input read;
input reset_n;
input write;
input [ 15: 0] writedata;
wire always_one;
wire areset_n;
wire c0;
wire c1;
wire control_reg_en;
wire [ 15: 0] control_reg_in;
reg [ 15: 0] control_reg_out;
reg count_done;
reg [ 5: 0] countup;
wire inclk0;
reg not_areset /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
wire [ 15: 0] readdata;
wire resetrequest;
wire [ 15: 0] status_reg_in;
reg [ 15: 0] status_reg_out;
initial
begin
countup = 1'b0;
count_done = 1'b0;
not_areset = 1'b0;
end
assign status_reg_in[15 : 1] = 15'b000000000000000;
assign resetrequest = ~count_done;
//Up counter that stops counting when it reaches max value
always @(posedge clk or negedge areset_n)
begin
if (areset_n == 0)
countup <= 0;
else if (count_done != 1'b1)
countup <= countup + 1;
end
//Count_done signal, which is also the resetrequest_n
always @(posedge clk or negedge areset_n)
begin
if (areset_n == 0)
count_done <= 0;
else if (countup == 6'b111111)
count_done <= 1'b1;
end
//Creates a reset generator that will reset internal counters that are independent of global system reset
always @(posedge clk or negedge 1'b1)
begin
if (1'b1 == 0)
not_areset <= 0;
else
not_areset <= always_one;
end
assign always_one = 1'b1;
assign status_reg_in[0] = 1'b0;
assign areset_n = not_areset;
assign inclk0 = clk;
//Mux status and control registers to the readdata output using address as select
assign readdata = (address[0] == 0)? status_reg_out :
({control_reg_out[15 : 2], ~control_reg_out[1], control_reg_out[0]} );
//Status register - Read-Only
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
status_reg_out <= 0;
else
status_reg_out <= status_reg_in;
end
//Control register - R/W
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg_out <= 0;
else if (control_reg_en)
control_reg_out <= {control_reg_in[15 : 2], ~control_reg_in[1], control_reg_in[0]};
end
assign control_reg_in = writedata;
assign control_reg_en = (address == 3'b001) && write && chipselect;
//s1, which is an e_avalon_slave
altpllpll the_pll
(
.c0 (c0),
.c1 (c1),
.inclk0 (inclk0)
);
endmodule
|
module alu_p #(parameter WIDTH=8)
(output reg [WIDTH:0] out,
input [WIDTH-1:0] a, b, input c_in, input [2:0]op);
parameter [2:0]
OP_ADD = 0,
OP_SUB = 1,
OP_SUBB = 2,
OP_OR = 3,
OP_AND = 4,
OP_NOT = 5,
OP_XOR = 6,
OP_XNOR = 7;
always @(a, b, op, c_in)
case (op)
OP_ADD: out <= a + b + c_in;
OP_SUB: out <= a + (~b) + c_in;
OP_SUBB:out <= b + (~a) + (~c_in);
OP_OR: out <= {1'b0, a | b};
OP_AND: out <= {1'b0, a & b};
OP_NOT: out <= {1'b0, (~a) & b};
OP_XOR: out <= {1'b0, a ^ b};
OP_XNOR:out <= {1'b0, a ~^ b};
endcase
endmodule
module reg_file #(parameter word_sz = 8, addr_sz = 5)
(output [word_sz-1:0] do_1, do_2, input [word_sz-1:0]di,
input [addr_sz-1:0] raddr_1, raddr_2, waddr,
input wr_enable, clk);
parameter reg_ct = 2**addr_sz;
reg [word_sz-1:0] file [reg_ct-1:0];
assign do_1 = file[raddr_1];
assign do_2 = file[raddr_2];
always @(posedge clk)
if (wr_enable)
file[waddr] <= di;
endmodule
module alu_reg #(parameter word_sz = 8, addr_sz = 5)
( output [word_sz:0] alu_out,
input [word_sz-1:0] di,
input [addr_sz-1:0] raddr_1, raddr_2, waddr,
input [2:0] opcode,
input c_in, wr_enable, clk);
wire [word_sz-1:0] do_1, do_2;
reg_file #(word_sz, addr_sz) rfile(do_1, do_2, di, raddr_1, raddr_2,
waddr, wr_enable, clk);
alu_p #(word_sz) alu(alu_out, do_1, do_2, c_in, opcode);
endmodule
module tb_reg_alu();
parameter word_sz = 8,
addr_sz = 5;
wire [word_sz:0] alu_out;
reg [word_sz-1:0] di;
reg [addr_sz-1:0] raddr_1, raddr_2, waddr;
reg [2:0] opcode;
reg c_in, wr_en, clk;
alu_reg #(word_sz, addr_sz) dev(alu_out, di, raddr_1, raddr_2,
waddr, opcode, c_in, wr_en, clk);
initial begin
#500 $finish();
end
initial begin
clk = 0;
forever clk = ~clk;
end
integer i;
initial begin
opcode = 0;
di = 1;
c_in = 0;
wr_en = 1;
waddr = 0;
raddr_1 = 0;
raddr_2 = 0;
$dumpfile("p28_b.vcd");
$dumpvars(0, tb_reg_alu);
for( i = 0; i < addr_sz; i = i + 1) begin
@(negedge clk) begin
waddr <= waddr + 1;
raddr_1 <= raddr_1 + 1;
raddr_2 <= raddr_2 + 1;
end
end
$finish();
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
// Date : Sat Apr 1 16:02:46 2017
// Host : g-tune2016 running 64-bit Ubuntu 16.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/minoru/FPGA/Zybo/Chapter9/vgagraph/vgagraph/src/vgagraph_fifo/vgagraph_fifo_stub.v
// Design : vgagraph_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)
module vgagraph_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[15:0],full,empty" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [15:0]dout;
output full;
output empty;
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY TX IF
*/
module eth_phy_10g_tx_if #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded interface
*/
input wire [DATA_WIDTH-1:0] encoded_tx_data,
input wire [HDR_WIDTH-1:0] encoded_tx_hdr,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
/*
* Configuration
*/
input wire tx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
wire [DATA_WIDTH-1:0] scrambled_data;
reg [30:0] prbs31_state_reg = 31'h7fffffff;
wire [30:0] prbs31_state;
wire [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data;
reg [DATA_WIDTH-1:0] serdes_tx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] serdes_tx_hdr_reg = {HDR_WIDTH{1'b0}};
wire [DATA_WIDTH-1:0] serdes_tx_data_int;
wire [HDR_WIDTH-1:0] serdes_tx_hdr_int;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_tx_data_int[n] = serdes_tx_data_reg[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_tx_hdr_int[n] = serdes_tx_hdr_reg[HDR_WIDTH-n-1];
end
end else begin
assign serdes_tx_data_int = serdes_tx_data_reg;
assign serdes_tx_hdr_int = serdes_tx_hdr_reg;
end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_WIDTH-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_WIDTH-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
for (n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_tx_data_pipe_reg[n] <= {DATA_WIDTH{1'b0}};
serdes_tx_hdr_pipe_reg[n] <= {HDR_WIDTH{1'b0}};
end
always @(posedge clk) begin
serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1];
serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1];
end
end
assign serdes_tx_data = serdes_tx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_hdr = serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_tx_data = serdes_tx_data_int;
assign serdes_tx_hdr = serdes_tx_hdr_int;
end
endgenerate
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
)
scrambler_inst (
.data_in(encoded_tx_data),
.state_in(scrambler_state_reg),
.data_out(scrambled_data),
.state_out(scrambler_state)
);
lfsr #(
.LFSR_WIDTH(31),
.LFSR_POLY(31'h10000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH+HDR_WIDTH),
.STYLE("AUTO")
)
prbs31_gen_inst (
.data_in({DATA_WIDTH+HDR_WIDTH{1'b0}}),
.state_in(prbs31_state_reg),
.data_out(prbs31_data),
.state_out(prbs31_state)
);
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
if (PRBS31_ENABLE && tx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
serdes_tx_data_reg <= ~prbs31_data[DATA_WIDTH+HDR_WIDTH-1:HDR_WIDTH];
serdes_tx_hdr_reg <= ~prbs31_data[HDR_WIDTH-1:0];
end else begin
serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data;
serdes_tx_hdr_reg <= encoded_tx_hdr;
end
end
endmodule
`resetall
|
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Module Description : top level testbench
`timescale 1ns/10ps
// DEFINES FOR TOP LEVEL TB
`define C_RAND_SEED 0
`define C_CLOCK_PERIOD 13
`define TB_ACTIVE_EDGE "rise"
`define TB_DRIVE_DELAY 2
`define TB_OUTPUT_FILE 0
`define C_CLOCK_PERIOD_AXI 10
`define C_S_AXI_CLK_FREQ_HZ 100000000
`define C_ACTIVE_COLS 1920
`define C_ACTIVE_ROWS 1080
`define C_ACTIVE_SIZE (`C_ACTIVE_ROWS<<16)+ `C_ACTIVE_COLS
`define C_HAS_INTC_IF 0
`define C_HAS_AXI4_LITE 0
`define C_AXI4LITE_AWIDTH 9
`define C_AXI4LITE_DWIDTH 32
`define C_AXIS_MST_TDATA_WIDTH 24
`define C_AXIS_SLV_TDATA_WIDTH 24
`define TB_STIMULI_TYPE 0 // 0 = RAMP DATA, 1 = CMODEL GENERATED FILE
`define STIMULI_FILE_NAME "EMPTY"
module tb_tutorial_v_rgb2ycrcb_0_0;
//REG & DRIVERS
reg tb_clk;
reg tb_sclr;
wire tb_sclr_n;
wire tb_ce;
reg tb_clk_axi;
reg tb_sclr_axi;
wire tb_sclr_n_axi;
wire tb_ce_axi;
reg EOS;
reg EOS_VIDEO;
reg EOS_AXI;
integer clock_period = `C_CLOCK_PERIOD;
integer clock_period_axi = `C_CLOCK_PERIOD_AXI;
integer rseed = `C_RAND_SEED;
integer total_errors = 0;
//AXI4-STREAM VIDEO MASTER WIRES
wire [`C_AXIS_MST_TDATA_WIDTH-1:0] m_video_data_w;
wire m_ready_w;
wire m_valid_w;
wire m_sof_w;
wire m_eol_w;
wire m_EOF_w;
wire [`C_AXIS_MST_TDATA_WIDTH/8-1:0] m_tstrb_w;
wire [`C_AXIS_MST_TDATA_WIDTH/8-1:0] m_tkeep_w;
wire m_tdest_w;
wire m_tid_w;
//AXI4-STREAM VIDEO SLAVE WIRES
wire [`C_AXIS_SLV_TDATA_WIDTH-1:0] s_video_data_w;
wire s_ready_w;
wire s_valid_w;
wire s_sof_w;
wire s_eol_w;
wire s_EOF_w;
wire [31:0] s_error_count_w;
//AXI4-LITE MASTER WIRES
wire m_awready_w;
wire m_awvalid_w;
wire [`C_AXI4LITE_AWIDTH-1:0] m_awaddr_w;
wire [2:0] m_awprot_w;
wire m_wready_w;
wire m_wvalid_w;
wire [`C_AXI4LITE_DWIDTH-1:0] m_wdata_w;
wire [(`C_AXI4LITE_DWIDTH/8)-1:0] m_wstrb_w;
wire m_bvalid_w;
wire [1:0] m_bresp_w;
wire m_bready_w;
wire m_arready_w;
wire m_arvalid_w;
wire [`C_AXI4LITE_AWIDTH-1:0] m_araddr_w;
wire [2:0] m_arprot_w;
wire m_rvalid_w;
wire [`C_AXI4LITE_DWIDTH-1:0] m_rdata_w;
wire [1:0] m_rresp_w;
wire m_rready_w;
reg [`C_AXI4LITE_DWIDTH-1:0] reg_data;
//INTERRUPT WIRE
wire irq_w;
//INTC_IF WIRE
wire [8:0] intc_if_w;
// uut INSTANCE
tutorial_v_rgb2ycrcb_0_0 uut
(
.aclk (tb_clk),
.aresetn (tb_sclr_n),
.aclken (tb_ce),
.s_axis_video_tready (m_ready_w),
.s_axis_video_tdata (m_video_data_w),
.s_axis_video_tvalid (m_valid_w),
.s_axis_video_tlast (m_eol_w),
.s_axis_video_tuser_sof (m_sof_w),
.m_axis_video_tready (s_ready_w),
.m_axis_video_tdata (s_video_data_w),
.m_axis_video_tvalid (s_valid_w),
.m_axis_video_tlast (s_eol_w),
.m_axis_video_tuser_sof (s_sof_w)
);
//CE (clock enable) GENERATOR INSTANCE
ce_gen CE_GEN
(
.clk_in (tb_clk),
.sclr_in (tb_sclr),
.ce_out (tb_ce)
);
//CE GENERATOR INSTANCE FOR AXI4LITE
ce_gen CE_GEN_AXI
(
.clk_in (tb_clk_axi),
.sclr_in (tb_sclr_axi),
//.ce_out (tb_ce_axi)
.ce_out ( )
);
assign tb_ce_axi = 1;
//AXI4-LITE MASTER INSTANCE
axi4lite_mst
#(
.module_id ("AXI4-LITE MASTER 1"),
.drive_edge (`TB_ACTIVE_EDGE),
.datawidth (`C_AXI4LITE_DWIDTH),
.addrwidth (`C_AXI4LITE_AWIDTH),
.drive_dly (`TB_DRIVE_DELAY)
) AXI4LITE_MST (
.aclk (tb_clk_axi),
.aclken (tb_ce_axi),
.aresetn (tb_sclr_n_axi),
.awready (m_awready_w),
.awvalid (m_awvalid_w),
.awaddr (m_awaddr_w),
.awprot (m_awprot_w),
.wready (m_wready_w),
.wvalid (m_wvalid_w),
.wdata (m_wdata_w),
.wstrb (m_wstrb_w),
.bvalid (m_bvalid_w),
.bresp (m_bresp_w),
.bready (m_bready_w),
.arready (m_arready_w),
.arvalid (m_arvalid_w),
.araddr (m_araddr_w),
.arprot (m_arprot_w),
.rvalid (m_rvalid_w),
.rdata (m_rdata_w),
.rresp (m_rresp_w),
.rready (m_rready_w)
);
//AXI4-STREAM VIDEO MASTER INSTANCE
axi4s_video_mst
#(
.module_id ("AXI-S Video Master 1"),
.drive_edge (`TB_ACTIVE_EDGE),
.datawidth (`C_AXIS_MST_TDATA_WIDTH),
.drive_dly (`TB_DRIVE_DELAY)
) MST (
.aclk (tb_clk),
.aclken (tb_ce),
.aresetn (tb_sclr_n),
.tready (m_ready_w),
.tdata (m_video_data_w),
.tvalid (m_valid_w),
.tstrb (m_tstrb_w),
.tkeep (m_tkeep_w),
.tdest (m_tdest_w),
.tid (m_tid_w),
.sof (m_sof_w),
.eol (m_eol_w),
.EOF (m_EOF_w)
);
//AXI4-STREAM VIDEO SLAVE INSTANCE
axi4s_video_slv
#(
.module_id ("AXI-S Video Slave 1"),
.drive_edge (`TB_ACTIVE_EDGE),
.datawidth (`C_AXIS_SLV_TDATA_WIDTH),
.output_file (`TB_OUTPUT_FILE),
.drive_dly (`TB_DRIVE_DELAY)
) SLV (
.aclk (tb_clk),
.aclken (tb_ce),
.aresetn (tb_sclr_n),
.tready (s_ready_w),
.tdata (s_video_data_w),
.tvalid (s_valid_w),
.sof (s_sof_w),
.eol (s_eol_w),
.error_count (s_error_count_w),
.EOF (s_EOF_w)
);
assign tb_sclr_n = ~tb_sclr;
assign tb_sclr_n_axi = ~tb_sclr_axi;
//================================================
// TESTBENCH TASK TO WAIT for "clk_period" CYCLES
//================================================
task wait_cycle;
input integer wait_length;
begin
#(clock_period * wait_length);
end
endtask
//======================
// TESTBENCH RESET TASK
//======================
task reset;
input integer reset_length;
begin
tb_sclr = 1'b1;
tb_sclr_axi = 1'b1;
$display("@%10t : TB_TOP : SYSTEM RESET ASSERTED!", $time);
wait_cycle(reset_length);
tb_sclr = 1'b0;
tb_sclr_axi = 1'b0;
$display("@%10t : TB_TOP : SYSTEM RESET DEASSERTED!", $time);
wait_cycle(1);
end
endtask
//==========================
// TESTBENCH CLK GENERATION
//==========================
initial
begin
tb_clk = 0;
tb_sclr = 0;
EOS = 0;
EOS_VIDEO = 0;
while (1)
begin
#(clock_period/2);
if((!EOS)&&(!EOS_VIDEO)) tb_clk = ~tb_clk;
end
end
initial
begin
tb_clk_axi = 0;
tb_sclr_axi = 0;
EOS_AXI = 0;
while (1)
begin
#(clock_period_axi/2);
if((!EOS)&&(!EOS_AXI)) tb_clk_axi = ~tb_clk_axi;
end
end
task test_summary;
begin
total_errors = total_errors + s_error_count_w;
if(total_errors > 0)
begin
$display("*******************************");
$display("** TEST FAILED !!!");
$display("** TOTAL ERRORS = %d", total_errors);
$display("*******************************");
end
else
begin
$display("\n***********************");
$display("** TEST PASSED **");
$display("***********************\n");
$display(" Test completed successfully \n");
end
EOS = 1;
$finish;
end
endtask
task test_sequence;
begin
reset(100);
wait_cycle(50);
// if (`TB_STIMULI_TYPE == 0)
// begin
MST.is_ramp_gen(`C_ACTIVE_ROWS, `C_ACTIVE_COLS, 2);
// end
// if (`TB_STIMULI_TYPE == 1)
// begin
// MST.use_file(`STIMULI_FILE_NAME);
// end
SLV.is_passive;
CE_GEN.start;
wait_cycle(50);
MST.start;
SLV.start;
wait(m_EOF_w ==1);
wait_cycle(10);
MST.stop;
SLV.stop;
wait_cycle(10);
$display("TEST END :");
end
endtask
//=========================
// TEST FLOW
//=========================
initial
begin
$display("TEST BEGIN :");
test_sequence;
test_summary;
$display("TEST END :");
end
endmodule //END OF TESTBENCH
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
//
// This module implements a complete brushed DC motor channel with 16 bit quadrature tach counter,
// tach filtering, tach phase inversion, 8 bit pwm with current limit, and pwm output polarity selection.
module bdcmotorchannel(
// Tach counter low byte
output [7:0] countl,
// Tach counter high byte
output [7:0] counth,
// Complmentary pwm signals out
output [1:0] pwmout,
// 4 bit pwm signals out
output [3:0] pwmout4,
// System clock in
input clk,
// Clock enable for tach filter shift register
input filterce,
// Freeze tach counter ( used during reads)
input freeze,
// Invert tach counter phase
input invphase,
// PWM count enable (used to control PWM frequency)
input pwmcntce,
// Load a PWM value on the wrtdata bus into the PWM logic
input pwmldce,
// Invert the PWM outputs
input invertpwm,
// Enable the PWM outputs
input enablepwm,
// Run or send the brake signal to the pwm outputs
input run,
// Force early termination of the PWM cycle
input currentlimit,
// Quadrature tach inputs
input [1:0] tach,
// Write data bus
input [7:0] wrtdata);
tachcounter tc(
.clk(clk),
.tach(tach),
.filterce(filterce),
.freeze(freeze),
.invphase(invphase),
.countl(countl),
.counth(counth));
pwm8 pwm(
.clk(clk),
.pwmcntce(pwmcntce),
.pwmldce(pwmldce),
.invertpwm(invertpwm),
.enablepwm(enablepwm),
.run(run),
.currentlimit(currentlimit),
.wrtdata(wrtdata),
.pwmout(pwmout),
.pwmout4(pwmout4));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_4_V
`define SKY130_FD_SC_LS__A2BB2OI_4_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_BLACKBOX_V
`define SKY130_FD_SC_HD__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_BLACKBOX_V
|
/*
-- ============================================================================
-- FILE NAME : cpu.v
-- DESCRIPTION : CPU¥È¥Ã¥×¥â¥¸¥å©`¥ë
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
`include "bus.h"
`include "spm.h"
/********** ¥â¥¸¥å©`¥ë **********/
module cpu (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire clk_, // ·´Ü¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
// IF Stage
input wire [`WordDataBus] if_bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire if_bus_rdy_, // ¥ì¥Ç¥£
input wire if_bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output wire if_bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output wire [`WordAddrBus] if_bus_addr, // ¥¢¥É¥ì¥¹
output wire if_bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire if_bus_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] if_bus_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
// MEM Stage
input wire [`WordDataBus] mem_bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire mem_bus_rdy_, // ¥ì¥Ç¥£
input wire mem_bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output wire mem_bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output wire [`WordAddrBus] mem_bus_addr, // ¥¢¥É¥ì¥¹
output wire mem_bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire mem_bus_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] mem_bus_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¸î¤êÞz¤ß **********/
input wire [`CPU_IRQ_CH-1:0] cpu_irq // ¸î¤êÞz¤ßÒªÇó
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
// IF/ID
wire [`WordAddrBus] if_pc; // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
wire [`WordDataBus] if_insn; // ÃüÁî
wire if_en; // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
// ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
wire [`WordAddrBus] id_pc; // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
wire id_en; // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
wire [`AluOpBus] id_alu_op; // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] id_alu_in_0; // ALUÈëÁ¦ 0
wire [`WordDataBus] id_alu_in_1; // ALUÈëÁ¦ 1
wire id_br_flag; // ·Ö᪥ե饰
wire [`MemOpBus] id_mem_op; // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] id_mem_wr_data; // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
wire [`CtrlOpBus] id_ctrl_op; // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`RegAddrBus] id_dst_addr; // GPRø¤Þz¤ß¥¢¥É¥ì¥¹
wire id_gpr_we_; // GPRø¤Þz¤ßÓп
wire [`IsaExpBus] id_exp_code; // ÀýÍ⥳©`¥É
// EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
wire [`WordAddrBus] ex_pc; // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
wire ex_en; // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
wire ex_br_flag; // ·Ö᪥ե饰
wire [`MemOpBus] ex_mem_op; // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] ex_mem_wr_data; // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
wire [`CtrlOpBus] ex_ctrl_op; // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`RegAddrBus] ex_dst_addr; // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
wire ex_gpr_we_; // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
wire [`IsaExpBus] ex_exp_code; // ÀýÍ⥳©`¥É
wire [`WordDataBus] ex_out; // IÀí½Y¹û
// MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
wire [`WordAddrBus] mem_pc; // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
wire mem_en; // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
wire mem_br_flag; // ·Ö᪥ե饰
wire [`CtrlOpBus] mem_ctrl_op; // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`RegAddrBus] mem_dst_addr; // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
wire mem_gpr_we_; // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
wire [`IsaExpBus] mem_exp_code; // ÀýÍ⥳©`¥É
wire [`WordDataBus] mem_out; // IÀí½Y¹û
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
// ¥¹¥È©`¥ëÐźÅ
wire if_stall; // IF¥¹¥Æ©`¥¸
wire id_stall; // ID¥¹¥Æ©`
wire ex_stall; // EX¥¹¥Æ©`¥¸
wire mem_stall; // MEM¥¹¥Æ©`¥¸
// ¥Õ¥é¥Ã¥·¥åÐźÅ
wire if_flush; // IF¥¹¥Æ©`¥¸
wire id_flush; // ID¥¹¥Æ©`¥¸
wire ex_flush; // EX¥¹¥Æ©`¥¸
wire mem_flush; // MEM¥¹¥Æ©`¥¸
// ¥Ó¥¸©`ÐźÅ
wire if_busy; // IF¥¹¥Æ©`¥¸
wire mem_busy; // MEM¥¹¥Æ©`¥¸
// ¤½¤ÎËû¤ÎÖÆÓùÐźÅ
wire [`WordAddrBus] new_pc; // Ф·¤¤PC
wire [`WordAddrBus] br_addr; // ·Ö᪥¢¥É¥ì¥¹
wire br_taken; // ·Ö᪤γÉÁ¢
wire ld_hazard; // ¥í©`¥É¥Ï¥¶©`¥É
/********** øÓå쥸¥¹¥¿ÐźŠ**********/
wire [`WordDataBus] gpr_rd_data_0; // Õi¤ß³ö¤·¥Ç©`¥¿ 0
wire [`WordDataBus] gpr_rd_data_1; // Õi¤ß³ö¤·¥Ç©`¥¿ 1
wire [`RegAddrBus] gpr_rd_addr_0; // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
wire [`RegAddrBus] gpr_rd_addr_1; // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ÖÆÓù¥ì¥¸¥¹¥¿ÐźŠ**********/
wire [`CpuExeModeBus] exe_mode; // gÐÐ¥â©`¥É
wire [`WordDataBus] creg_rd_data; // Õi¤ß³ö¤·¥Ç©`¥¿
wire [`RegAddrBus] creg_rd_addr; // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** Interrupt Request **********/
wire int_detect; // ¸î¤êÞz¤ßʳö
/********** ¥¹¥¯¥é¥Ã¥Á¥Ñ¥Ã¥É¥á¥â¥êÐźŠ**********/
// IF¥¹¥Æ©`¥¸
wire [`WordDataBus] if_spm_rd_data; // Õi¤ß³ö¤·¥Ç©`¥¿
wire [`WordAddrBus] if_spm_addr; // ¥¢¥É¥ì¥¹
wire if_spm_as_; // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
wire if_spm_rw; // Õi¤ß£¯ø¤
wire [`WordDataBus] if_spm_wr_data; // ø¤Þz¤ß¥Ç©`¥¿
// MEM¥¹¥Æ©`¥¸
wire [`WordDataBus] mem_spm_rd_data; // Õi¤ß³ö¤·¥Ç©`¥¿
wire [`WordAddrBus] mem_spm_addr; // ¥¢¥É¥ì¥¹
wire mem_spm_as_; // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
wire mem_spm_rw; // Õi¤ß£¯ø¤
wire [`WordDataBus] mem_spm_wr_data; // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°ÐźŠ**********/
wire [`WordDataBus] ex_fwd_data; // EX¥¹¥Æ©`¥¸
wire [`WordDataBus] mem_fwd_data; // MEM¥¹¥Æ©`¥¸
/********** IF¥¹¥Æ©`¥¸ **********/
if_stage if_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.spm_rd_data (if_spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.spm_addr (if_spm_addr), // ¥¢¥É¥ì¥¹
.spm_as_ (if_spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.spm_rw (if_spm_rw), // Õi¤ß£¯ø¤
.spm_wr_data (if_spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.bus_rd_data (if_bus_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.bus_rdy_ (if_bus_rdy_), // ¥ì¥Ç¥£
.bus_grnt_ (if_bus_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
.bus_req_ (if_bus_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.bus_addr (if_bus_addr), // ¥¢¥É¥ì¥¹
.bus_as_ (if_bus_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.bus_rw (if_bus_rw), // Õi¤ß£¯ø¤
.bus_wr_data (if_bus_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (if_stall), // ¥¹¥È©`¥ë
.flush (if_flush), // ¥Õ¥é¥Ã¥·¥å
.new_pc (new_pc), // Ф·¤¤PC
.br_taken (br_taken), // ·Ö᪤γÉÁ¢
.br_addr (br_addr), // ·ÖáªÏÈ¥¢¥É¥ì¥¹
.busy (if_busy), // ¥Ó¥¸©`ÐźÅ
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_insn (if_insn), // ÃüÁî
.if_en (if_en) // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
);
/********** ID¥¹¥Æ©`¥¸ **********/
id_stage id_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** GPR¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.gpr_rd_data_0 (gpr_rd_data_0), // Õi¤ß³ö¤·¥Ç©`¥¿ 0
.gpr_rd_data_1 (gpr_rd_data_1), // Õi¤ß³ö¤·¥Ç©`¥¿ 1
.gpr_rd_addr_0 (gpr_rd_addr_0), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
.gpr_rd_addr_1 (gpr_rd_addr_1), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
// EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_fwd_data (ex_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
.ex_dst_addr (ex_dst_addr), // ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // ø¤Þz¤ßÓп
// MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.mem_fwd_data (mem_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.exe_mode (exe_mode), // gÐÐ¥â©`¥É
.creg_rd_data (creg_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.creg_rd_addr (creg_rd_addr), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (id_stall), // ¥¹¥È©`¥ë
.flush (id_flush), // ¥Õ¥é¥Ã¥·¥å
.br_addr (br_addr), // ·Ö᪥¢¥É¥ì¥¹
.br_taken (br_taken), // ·Ö᪤γÉÁ¢
.ld_hazard (ld_hazard), // ¥í©`¥É¥Ï¥¶©`¥É
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_insn (if_insn), // ÃüÁî
.if_en (if_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_alu_op (id_alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_alu_in_0 (id_alu_in_0), // ALUÈëÁ¦ 0
.id_alu_in_1 (id_alu_in_1), // ALUÈëÁ¦ 1
.id_br_flag (id_br_flag), // ·Ö᪥ե饰
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_mem_wr_data (id_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.id_ctrl_op (id_ctrl_op), // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_dst_addr (id_dst_addr), // GPRø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // GPRø¤Þz¤ßÓп
.id_exp_code (id_exp_code) // ÀýÍ⥳©`¥É
);
/********** EX¥¹¥Æ©`¥¸ **********/
ex_stage ex_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (ex_stall), // ¥¹¥È©`¥ë
.flush (ex_flush), // ¥Õ¥é¥Ã¥·¥å
.int_detect (int_detect), // ¸î¤êÞz¤ßʳö
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
.fwd_data (ex_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_alu_op (id_alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_alu_in_0 (id_alu_in_0), // ALUÈëÁ¦ 0
.id_alu_in_1 (id_alu_in_1), // ALUÈëÁ¦ 1
.id_br_flag (id_br_flag), // ·Ö᪥ե饰
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_mem_wr_data (id_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.id_ctrl_op (id_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_dst_addr (id_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.id_exp_code (id_exp_code), // ÀýÍ⥳©`¥É
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_pc (ex_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_br_flag (ex_br_flag), // ·Ö᪥ե饰
.ex_mem_op (ex_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_mem_wr_data (ex_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ex_ctrl_op (ex_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_dst_addr (ex_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.ex_exp_code (ex_exp_code), // ÀýÍ⥳©`¥É
.ex_out (ex_out) // IÀí½Y¹û
);
/********** MEM¥¹¥Æ©`¥¸ **********/
mem_stage mem_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (mem_stall), // ¥¹¥È©`¥ë
.flush (mem_flush), // ¥Õ¥é¥Ã¥·¥å
.busy (mem_busy), // ¥Ó¥¸©`ÐźÅ
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
.fwd_data (mem_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.spm_rd_data (mem_spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.spm_addr (mem_spm_addr), // ¥¢¥É¥ì¥¹
.spm_as_ (mem_spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.spm_rw (mem_spm_rw), // Õi¤ß£¯ø¤
.spm_wr_data (mem_spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.bus_rd_data (mem_bus_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.bus_rdy_ (mem_bus_rdy_), // ¥ì¥Ç¥£
.bus_grnt_ (mem_bus_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
.bus_req_ (mem_bus_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.bus_addr (mem_bus_addr), // ¥¢¥É¥ì¥¹
.bus_as_ (mem_bus_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.bus_rw (mem_bus_rw), // Õi¤ß£¯ø¤
.bus_wr_data (mem_bus_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_pc (ex_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_br_flag (ex_br_flag), // ·Ö᪥ե饰
.ex_mem_op (ex_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_mem_wr_data (ex_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ex_ctrl_op (ex_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_dst_addr (ex_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.ex_exp_code (ex_exp_code), // ÀýÍ⥳©`¥É
.ex_out (ex_out), // IÀí½Y¹û
/********** MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.mem_pc (mem_pc), // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
.mem_en (mem_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.mem_br_flag (mem_br_flag), // ·Ö᪥ե饰
.mem_ctrl_op (mem_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_dst_addr (mem_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.mem_gpr_we_ (mem_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.mem_exp_code (mem_exp_code), // ÀýÍ⥳©`¥É
.mem_out (mem_out) // IÀí½Y¹û
);
/********** ÖÆÓù¥æ¥Ë¥Ã¥È **********/
ctrl ctrl (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.creg_rd_addr (creg_rd_addr), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
.creg_rd_data (creg_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.exe_mode (exe_mode), // gÐÐ¥â©`¥É
/********** ¸î¤êÞz¤ß **********/
.irq (cpu_irq), // ¸î¤êÞz¤ßÒªÇó
.int_detect (int_detect), // ¸î¤êÞz¤ßʳö
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
/********** MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.mem_pc (mem_pc), // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
.mem_en (mem_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.mem_br_flag (mem_br_flag), // ·Ö᪥ե饰
.mem_ctrl_op (mem_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_dst_addr (mem_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.mem_exp_code (mem_exp_code), // ÀýÍ⥳©`¥É
.mem_out (mem_out), // IÀí½Y¹û
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
// ¥Ñ¥¤¥×¥é¥¤¥ó¤Î×´B
.if_busy (if_busy), // IF¥¹¥Æ©`¥¸¥Ó¥¸©`
.ld_hazard (ld_hazard), // Load¥Ï¥¶©`¥É
.mem_busy (mem_busy), // MEM¥¹¥Æ©`¥¸¥Ó¥¸©`
// ¥¹¥È©`¥ëÐźÅ
.if_stall (if_stall), // IF¥¹¥Æ©`¥¸¥¹¥È©`¥ë
.id_stall (id_stall), // ID¥¹¥Æ©`¥¸¥¹¥È©`¥ë
.ex_stall (ex_stall), // EX¥¹¥Æ©`¥¸¥¹¥È©`¥ë
.mem_stall (mem_stall), // MEM¥¹¥Æ©`¥¸¥¹¥È©`¥ë
// ¥Õ¥é¥Ã¥·¥åÐźÅ
.if_flush (if_flush), // IF¥¹¥Æ©`¥¸¥Õ¥é¥Ã¥·¥å
.id_flush (id_flush), // ID¥¹¥Æ©`¥¸¥Õ¥é¥Ã¥·¥å
.ex_flush (ex_flush), // EX¥¹¥Æ©`¥¸¥Õ¥é¥Ã¥·¥å
.mem_flush (mem_flush), // MEM¥¹¥Æ©`¥¸¥Õ¥é¥Ã¥·¥å
// Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.new_pc (new_pc) // Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
);
/********** øÓå쥸¥¹¥¿ **********/
gpr gpr (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** Õi¤ß³ö¤·¥Ý©`¥È 0 **********/
.rd_addr_0 (gpr_rd_addr_0), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
.rd_data_0 (gpr_rd_data_0), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** Õi¤ß³ö¤·¥Ý©`¥È 1 **********/
.rd_addr_1 (gpr_rd_addr_1), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
.rd_data_1 (gpr_rd_data_1), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** ø¤Þz¤ß¥Ý©`¥È **********/
.we_ (mem_gpr_we_), // ø¤Þz¤ßÓп
.wr_addr (mem_dst_addr), // ø¤Þz¤ß¥¢¥É¥ì¥¹
.wr_data (mem_out) // ø¤Þz¤ß¥Ç©`¥¿
);
/********** ¥¹¥¯¥é¥Ã¥Á¥Ñ¥Ã¥É¥á¥â¥ê **********/
spm spm (
/********** ¥¯¥í¥Ã¥¯ **********/
.clk (clk_), // ¥¯¥í¥Ã¥¯
/********** ¥Ý©`¥ÈA : IF¥¹¥Æ©`¥¸ **********/
.if_spm_addr (if_spm_addr[`SpmAddrLoc]), // ¥¢¥É¥ì¥¹
.if_spm_as_ (if_spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.if_spm_rw (if_spm_rw), // Õi¤ß£¯ø¤
.if_spm_wr_data (if_spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.if_spm_rd_data (if_spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** ¥Ý©`¥ÈB : MEM¥¹¥Æ©`¥¸ **********/
.mem_spm_addr (mem_spm_addr[`SpmAddrLoc]), // ¥¢¥É¥ì¥¹
.mem_spm_as_ (mem_spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.mem_spm_rw (mem_spm_rw), // Õi¤ß£¯ø¤
.mem_spm_wr_data (mem_spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.mem_spm_rd_data (mem_spm_rd_data) // Õi¤ß³ö¤·¥Ç©`¥¿
);
endmodule
|
//-----------------------------------------------------------------------------
// system_axi4lite_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "axi_interconnect_v1_06_a" *)
module system_axi4lite_0_wrapper
(
INTERCONNECT_ACLK,
INTERCONNECT_ARESETN,
S_AXI_ARESET_OUT_N,
M_AXI_ARESET_OUT_N,
IRQ,
S_AXI_ACLK,
S_AXI_AWID,
S_AXI_AWADDR,
S_AXI_AWLEN,
S_AXI_AWSIZE,
S_AXI_AWBURST,
S_AXI_AWLOCK,
S_AXI_AWCACHE,
S_AXI_AWPROT,
S_AXI_AWQOS,
S_AXI_AWUSER,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WLAST,
S_AXI_WUSER,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BID,
S_AXI_BRESP,
S_AXI_BUSER,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARID,
S_AXI_ARADDR,
S_AXI_ARLEN,
S_AXI_ARSIZE,
S_AXI_ARBURST,
S_AXI_ARLOCK,
S_AXI_ARCACHE,
S_AXI_ARPROT,
S_AXI_ARQOS,
S_AXI_ARUSER,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RID,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RLAST,
S_AXI_RUSER,
S_AXI_RVALID,
S_AXI_RREADY,
M_AXI_ACLK,
M_AXI_AWID,
M_AXI_AWADDR,
M_AXI_AWLEN,
M_AXI_AWSIZE,
M_AXI_AWBURST,
M_AXI_AWLOCK,
M_AXI_AWCACHE,
M_AXI_AWPROT,
M_AXI_AWREGION,
M_AXI_AWQOS,
M_AXI_AWUSER,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WID,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WLAST,
M_AXI_WUSER,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BID,
M_AXI_BRESP,
M_AXI_BUSER,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARID,
M_AXI_ARADDR,
M_AXI_ARLEN,
M_AXI_ARSIZE,
M_AXI_ARBURST,
M_AXI_ARLOCK,
M_AXI_ARCACHE,
M_AXI_ARPROT,
M_AXI_ARREGION,
M_AXI_ARQOS,
M_AXI_ARUSER,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RID,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RLAST,
M_AXI_RUSER,
M_AXI_RVALID,
M_AXI_RREADY,
S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA,
S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY,
INTERCONNECT_ARESET_OUT_N,
DEBUG_AW_TRANS_SEQ,
DEBUG_AW_ARB_GRANT,
DEBUG_AR_TRANS_SEQ,
DEBUG_AR_ARB_GRANT,
DEBUG_AW_TRANS_QUAL,
DEBUG_AW_ACCEPT_CNT,
DEBUG_AW_ACTIVE_THREAD,
DEBUG_AW_ACTIVE_TARGET,
DEBUG_AW_ACTIVE_REGION,
DEBUG_AW_ERROR,
DEBUG_AW_TARGET,
DEBUG_AR_TRANS_QUAL,
DEBUG_AR_ACCEPT_CNT,
DEBUG_AR_ACTIVE_THREAD,
DEBUG_AR_ACTIVE_TARGET,
DEBUG_AR_ACTIVE_REGION,
DEBUG_AR_ERROR,
DEBUG_AR_TARGET,
DEBUG_B_TRANS_SEQ,
DEBUG_R_BEAT_CNT,
DEBUG_R_TRANS_SEQ,
DEBUG_AW_ISSUING_CNT,
DEBUG_AR_ISSUING_CNT,
DEBUG_W_BEAT_CNT,
DEBUG_W_TRANS_SEQ,
DEBUG_BID_TARGET,
DEBUG_BID_ERROR,
DEBUG_RID_TARGET,
DEBUG_RID_ERROR,
DEBUG_SR_SC_ARADDR,
DEBUG_SR_SC_ARADDRCONTROL,
DEBUG_SR_SC_AWADDR,
DEBUG_SR_SC_AWADDRCONTROL,
DEBUG_SR_SC_BRESP,
DEBUG_SR_SC_RDATA,
DEBUG_SR_SC_RDATACONTROL,
DEBUG_SR_SC_WDATA,
DEBUG_SR_SC_WDATACONTROL,
DEBUG_SC_SF_ARADDR,
DEBUG_SC_SF_ARADDRCONTROL,
DEBUG_SC_SF_AWADDR,
DEBUG_SC_SF_AWADDRCONTROL,
DEBUG_SC_SF_BRESP,
DEBUG_SC_SF_RDATA,
DEBUG_SC_SF_RDATACONTROL,
DEBUG_SC_SF_WDATA,
DEBUG_SC_SF_WDATACONTROL,
DEBUG_SF_CB_ARADDR,
DEBUG_SF_CB_ARADDRCONTROL,
DEBUG_SF_CB_AWADDR,
DEBUG_SF_CB_AWADDRCONTROL,
DEBUG_SF_CB_BRESP,
DEBUG_SF_CB_RDATA,
DEBUG_SF_CB_RDATACONTROL,
DEBUG_SF_CB_WDATA,
DEBUG_SF_CB_WDATACONTROL,
DEBUG_CB_MF_ARADDR,
DEBUG_CB_MF_ARADDRCONTROL,
DEBUG_CB_MF_AWADDR,
DEBUG_CB_MF_AWADDRCONTROL,
DEBUG_CB_MF_BRESP,
DEBUG_CB_MF_RDATA,
DEBUG_CB_MF_RDATACONTROL,
DEBUG_CB_MF_WDATA,
DEBUG_CB_MF_WDATACONTROL,
DEBUG_MF_MC_ARADDR,
DEBUG_MF_MC_ARADDRCONTROL,
DEBUG_MF_MC_AWADDR,
DEBUG_MF_MC_AWADDRCONTROL,
DEBUG_MF_MC_BRESP,
DEBUG_MF_MC_RDATA,
DEBUG_MF_MC_RDATACONTROL,
DEBUG_MF_MC_WDATA,
DEBUG_MF_MC_WDATACONTROL,
DEBUG_MC_MP_ARADDR,
DEBUG_MC_MP_ARADDRCONTROL,
DEBUG_MC_MP_AWADDR,
DEBUG_MC_MP_AWADDRCONTROL,
DEBUG_MC_MP_BRESP,
DEBUG_MC_MP_RDATA,
DEBUG_MC_MP_RDATACONTROL,
DEBUG_MC_MP_WDATA,
DEBUG_MC_MP_WDATACONTROL,
DEBUG_MP_MR_ARADDR,
DEBUG_MP_MR_ARADDRCONTROL,
DEBUG_MP_MR_AWADDR,
DEBUG_MP_MR_AWADDRCONTROL,
DEBUG_MP_MR_BRESP,
DEBUG_MP_MR_RDATA,
DEBUG_MP_MR_RDATACONTROL,
DEBUG_MP_MR_WDATA,
DEBUG_MP_MR_WDATACONTROL
);
input INTERCONNECT_ACLK;
input INTERCONNECT_ARESETN;
output [0:0] S_AXI_ARESET_OUT_N;
output [7:0] M_AXI_ARESET_OUT_N;
output IRQ;
input [0:0] S_AXI_ACLK;
input [11:0] S_AXI_AWID;
input [31:0] S_AXI_AWADDR;
input [7:0] S_AXI_AWLEN;
input [2:0] S_AXI_AWSIZE;
input [1:0] S_AXI_AWBURST;
input [1:0] S_AXI_AWLOCK;
input [3:0] S_AXI_AWCACHE;
input [2:0] S_AXI_AWPROT;
input [3:0] S_AXI_AWQOS;
input [0:0] S_AXI_AWUSER;
input [0:0] S_AXI_AWVALID;
output [0:0] S_AXI_AWREADY;
input [11:0] S_AXI_WID;
input [31:0] S_AXI_WDATA;
input [3:0] S_AXI_WSTRB;
input [0:0] S_AXI_WLAST;
input [0:0] S_AXI_WUSER;
input [0:0] S_AXI_WVALID;
output [0:0] S_AXI_WREADY;
output [11:0] S_AXI_BID;
output [1:0] S_AXI_BRESP;
output [0:0] S_AXI_BUSER;
output [0:0] S_AXI_BVALID;
input [0:0] S_AXI_BREADY;
input [11:0] S_AXI_ARID;
input [31:0] S_AXI_ARADDR;
input [7:0] S_AXI_ARLEN;
input [2:0] S_AXI_ARSIZE;
input [1:0] S_AXI_ARBURST;
input [1:0] S_AXI_ARLOCK;
input [3:0] S_AXI_ARCACHE;
input [2:0] S_AXI_ARPROT;
input [3:0] S_AXI_ARQOS;
input [0:0] S_AXI_ARUSER;
input [0:0] S_AXI_ARVALID;
output [0:0] S_AXI_ARREADY;
output [11:0] S_AXI_RID;
output [31:0] S_AXI_RDATA;
output [1:0] S_AXI_RRESP;
output [0:0] S_AXI_RLAST;
output [0:0] S_AXI_RUSER;
output [0:0] S_AXI_RVALID;
input [0:0] S_AXI_RREADY;
input [7:0] M_AXI_ACLK;
output [95:0] M_AXI_AWID;
output [255:0] M_AXI_AWADDR;
output [63:0] M_AXI_AWLEN;
output [23:0] M_AXI_AWSIZE;
output [15:0] M_AXI_AWBURST;
output [15:0] M_AXI_AWLOCK;
output [31:0] M_AXI_AWCACHE;
output [23:0] M_AXI_AWPROT;
output [31:0] M_AXI_AWREGION;
output [31:0] M_AXI_AWQOS;
output [7:0] M_AXI_AWUSER;
output [7:0] M_AXI_AWVALID;
input [7:0] M_AXI_AWREADY;
output [95:0] M_AXI_WID;
output [255:0] M_AXI_WDATA;
output [31:0] M_AXI_WSTRB;
output [7:0] M_AXI_WLAST;
output [7:0] M_AXI_WUSER;
output [7:0] M_AXI_WVALID;
input [7:0] M_AXI_WREADY;
input [95:0] M_AXI_BID;
input [15:0] M_AXI_BRESP;
input [7:0] M_AXI_BUSER;
input [7:0] M_AXI_BVALID;
output [7:0] M_AXI_BREADY;
output [95:0] M_AXI_ARID;
output [255:0] M_AXI_ARADDR;
output [63:0] M_AXI_ARLEN;
output [23:0] M_AXI_ARSIZE;
output [15:0] M_AXI_ARBURST;
output [15:0] M_AXI_ARLOCK;
output [31:0] M_AXI_ARCACHE;
output [23:0] M_AXI_ARPROT;
output [31:0] M_AXI_ARREGION;
output [31:0] M_AXI_ARQOS;
output [7:0] M_AXI_ARUSER;
output [7:0] M_AXI_ARVALID;
input [7:0] M_AXI_ARREADY;
input [95:0] M_AXI_RID;
input [255:0] M_AXI_RDATA;
input [15:0] M_AXI_RRESP;
input [7:0] M_AXI_RLAST;
input [7:0] M_AXI_RUSER;
input [7:0] M_AXI_RVALID;
output [7:0] M_AXI_RREADY;
input [31:0] S_AXI_CTRL_AWADDR;
input S_AXI_CTRL_AWVALID;
output S_AXI_CTRL_AWREADY;
input [31:0] S_AXI_CTRL_WDATA;
input S_AXI_CTRL_WVALID;
output S_AXI_CTRL_WREADY;
output [1:0] S_AXI_CTRL_BRESP;
output S_AXI_CTRL_BVALID;
input S_AXI_CTRL_BREADY;
input [31:0] S_AXI_CTRL_ARADDR;
input S_AXI_CTRL_ARVALID;
output S_AXI_CTRL_ARREADY;
output [31:0] S_AXI_CTRL_RDATA;
output [1:0] S_AXI_CTRL_RRESP;
output S_AXI_CTRL_RVALID;
input S_AXI_CTRL_RREADY;
output INTERCONNECT_ARESET_OUT_N;
output [7:0] DEBUG_AW_TRANS_SEQ;
output [7:0] DEBUG_AW_ARB_GRANT;
output [7:0] DEBUG_AR_TRANS_SEQ;
output [7:0] DEBUG_AR_ARB_GRANT;
output [0:0] DEBUG_AW_TRANS_QUAL;
output [7:0] DEBUG_AW_ACCEPT_CNT;
output [15:0] DEBUG_AW_ACTIVE_THREAD;
output [7:0] DEBUG_AW_ACTIVE_TARGET;
output [7:0] DEBUG_AW_ACTIVE_REGION;
output [7:0] DEBUG_AW_ERROR;
output [7:0] DEBUG_AW_TARGET;
output [0:0] DEBUG_AR_TRANS_QUAL;
output [7:0] DEBUG_AR_ACCEPT_CNT;
output [15:0] DEBUG_AR_ACTIVE_THREAD;
output [7:0] DEBUG_AR_ACTIVE_TARGET;
output [7:0] DEBUG_AR_ACTIVE_REGION;
output [7:0] DEBUG_AR_ERROR;
output [7:0] DEBUG_AR_TARGET;
output [7:0] DEBUG_B_TRANS_SEQ;
output [7:0] DEBUG_R_BEAT_CNT;
output [7:0] DEBUG_R_TRANS_SEQ;
output [7:0] DEBUG_AW_ISSUING_CNT;
output [7:0] DEBUG_AR_ISSUING_CNT;
output [7:0] DEBUG_W_BEAT_CNT;
output [7:0] DEBUG_W_TRANS_SEQ;
output [7:0] DEBUG_BID_TARGET;
output DEBUG_BID_ERROR;
output [7:0] DEBUG_RID_TARGET;
output DEBUG_RID_ERROR;
output [31:0] DEBUG_SR_SC_ARADDR;
output [34:0] DEBUG_SR_SC_ARADDRCONTROL;
output [31:0] DEBUG_SR_SC_AWADDR;
output [34:0] DEBUG_SR_SC_AWADDRCONTROL;
output [15:0] DEBUG_SR_SC_BRESP;
output [31:0] DEBUG_SR_SC_RDATA;
output [16:0] DEBUG_SR_SC_RDATACONTROL;
output [31:0] DEBUG_SR_SC_WDATA;
output [6:0] DEBUG_SR_SC_WDATACONTROL;
output [31:0] DEBUG_SC_SF_ARADDR;
output [34:0] DEBUG_SC_SF_ARADDRCONTROL;
output [31:0] DEBUG_SC_SF_AWADDR;
output [34:0] DEBUG_SC_SF_AWADDRCONTROL;
output [15:0] DEBUG_SC_SF_BRESP;
output [31:0] DEBUG_SC_SF_RDATA;
output [16:0] DEBUG_SC_SF_RDATACONTROL;
output [31:0] DEBUG_SC_SF_WDATA;
output [6:0] DEBUG_SC_SF_WDATACONTROL;
output [31:0] DEBUG_SF_CB_ARADDR;
output [34:0] DEBUG_SF_CB_ARADDRCONTROL;
output [31:0] DEBUG_SF_CB_AWADDR;
output [34:0] DEBUG_SF_CB_AWADDRCONTROL;
output [15:0] DEBUG_SF_CB_BRESP;
output [31:0] DEBUG_SF_CB_RDATA;
output [16:0] DEBUG_SF_CB_RDATACONTROL;
output [31:0] DEBUG_SF_CB_WDATA;
output [6:0] DEBUG_SF_CB_WDATACONTROL;
output [31:0] DEBUG_CB_MF_ARADDR;
output [34:0] DEBUG_CB_MF_ARADDRCONTROL;
output [31:0] DEBUG_CB_MF_AWADDR;
output [34:0] DEBUG_CB_MF_AWADDRCONTROL;
output [15:0] DEBUG_CB_MF_BRESP;
output [31:0] DEBUG_CB_MF_RDATA;
output [16:0] DEBUG_CB_MF_RDATACONTROL;
output [31:0] DEBUG_CB_MF_WDATA;
output [6:0] DEBUG_CB_MF_WDATACONTROL;
output [31:0] DEBUG_MF_MC_ARADDR;
output [34:0] DEBUG_MF_MC_ARADDRCONTROL;
output [31:0] DEBUG_MF_MC_AWADDR;
output [34:0] DEBUG_MF_MC_AWADDRCONTROL;
output [15:0] DEBUG_MF_MC_BRESP;
output [31:0] DEBUG_MF_MC_RDATA;
output [16:0] DEBUG_MF_MC_RDATACONTROL;
output [31:0] DEBUG_MF_MC_WDATA;
output [6:0] DEBUG_MF_MC_WDATACONTROL;
output [31:0] DEBUG_MC_MP_ARADDR;
output [34:0] DEBUG_MC_MP_ARADDRCONTROL;
output [31:0] DEBUG_MC_MP_AWADDR;
output [34:0] DEBUG_MC_MP_AWADDRCONTROL;
output [15:0] DEBUG_MC_MP_BRESP;
output [31:0] DEBUG_MC_MP_RDATA;
output [16:0] DEBUG_MC_MP_RDATACONTROL;
output [31:0] DEBUG_MC_MP_WDATA;
output [6:0] DEBUG_MC_MP_WDATACONTROL;
output [31:0] DEBUG_MP_MR_ARADDR;
output [34:0] DEBUG_MP_MR_ARADDRCONTROL;
output [31:0] DEBUG_MP_MR_AWADDR;
output [34:0] DEBUG_MP_MR_AWADDRCONTROL;
output [15:0] DEBUG_MP_MR_BRESP;
output [31:0] DEBUG_MP_MR_RDATA;
output [16:0] DEBUG_MP_MR_RDATACONTROL;
output [31:0] DEBUG_MP_MR_WDATA;
output [6:0] DEBUG_MP_MR_WDATACONTROL;
axi_interconnect
#(
.C_BASEFAMILY ( "zynq" ),
.C_NUM_SLAVE_SLOTS ( 1 ),
.C_NUM_MASTER_SLOTS ( 8 ),
.C_AXI_ID_WIDTH ( 12 ),
.C_AXI_ADDR_WIDTH ( 32 ),
.C_AXI_DATA_MAX_WIDTH ( 32 ),
.C_S_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_M_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_INTERCONNECT_DATA_WIDTH ( 32 ),
.C_S_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ),
.C_M_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000200000002000000020000000200000002000000020000000200000002 ),
.C_M_AXI_BASE_ADDR ( 16384'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076820000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076800000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000043000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041240000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041220000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000 ),
.C_M_AXI_HIGH_ADDR ( 16384'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007682ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007680ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007660ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004300ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004160ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004124ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004122ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff ),
.C_S_AXI_BASE_ID ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_THREAD_ID_WIDTH ( 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c ),
.C_S_AXI_IS_INTERCONNECT ( 16'b0000000000000000 ),
.C_S_AXI_ACLK_RATIO ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100 ),
.C_S_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_M_AXI_ACLK_RATIO ( 512'h000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e100 ),
.C_M_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_INTERCONNECT_ACLK_RATIO ( 100000000 ),
.C_S_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ),
.C_AXI_AWUSER_WIDTH ( 1 ),
.C_AXI_ARUSER_WIDTH ( 1 ),
.C_AXI_WUSER_WIDTH ( 1 ),
.C_AXI_RUSER_WIDTH ( 1 ),
.C_AXI_BUSER_WIDTH ( 1 ),
.C_AXI_CONNECTIVITY ( 512'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ),
.C_S_AXI_SINGLE_THREAD ( 16'b0000000000000000 ),
.C_M_AXI_SUPPORTS_REORDERING ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111110 ),
.C_M_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_S_AXI_READ_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_M_AXI_WRITE_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_M_AXI_READ_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_S_AXI_ARB_PRIORITY ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_SECURE ( 16'b0000000000000000 ),
.C_S_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_INTERCONNECT_R_REGISTER ( 0 ),
.C_INTERCONNECT_CONNECTIVITY_MODE ( 0 ),
.C_USE_CTRL_PORT ( 0 ),
.C_USE_INTERRUPT ( 1 ),
.C_RANGE_CHECK ( 1 ),
.C_S_AXI_CTRL_ADDR_WIDTH ( 32 ),
.C_S_AXI_CTRL_DATA_WIDTH ( 32 ),
.C_DEBUG ( 0 ),
.C_S_AXI_DEBUG_SLOT ( 0 ),
.C_M_AXI_DEBUG_SLOT ( 0 ),
.C_MAX_DEBUG_THREADS ( 1 )
)
axi4lite_0 (
.INTERCONNECT_ACLK ( INTERCONNECT_ACLK ),
.INTERCONNECT_ARESETN ( INTERCONNECT_ARESETN ),
.S_AXI_ARESET_OUT_N ( S_AXI_ARESET_OUT_N ),
.M_AXI_ARESET_OUT_N ( M_AXI_ARESET_OUT_N ),
.IRQ ( IRQ ),
.S_AXI_ACLK ( S_AXI_ACLK ),
.S_AXI_AWID ( S_AXI_AWID ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWLEN ( S_AXI_AWLEN ),
.S_AXI_AWSIZE ( S_AXI_AWSIZE ),
.S_AXI_AWBURST ( S_AXI_AWBURST ),
.S_AXI_AWLOCK ( S_AXI_AWLOCK ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWQOS ( S_AXI_AWQOS ),
.S_AXI_AWUSER ( S_AXI_AWUSER ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WID ( S_AXI_WID ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WLAST ( S_AXI_WLAST ),
.S_AXI_WUSER ( S_AXI_WUSER ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BID ( S_AXI_BID ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BUSER ( S_AXI_BUSER ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARID ( S_AXI_ARID ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARLEN ( S_AXI_ARLEN ),
.S_AXI_ARSIZE ( S_AXI_ARSIZE ),
.S_AXI_ARBURST ( S_AXI_ARBURST ),
.S_AXI_ARLOCK ( S_AXI_ARLOCK ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARQOS ( S_AXI_ARQOS ),
.S_AXI_ARUSER ( S_AXI_ARUSER ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RID ( S_AXI_RID ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RLAST ( S_AXI_RLAST ),
.S_AXI_RUSER ( S_AXI_RUSER ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.M_AXI_ACLK ( M_AXI_ACLK ),
.M_AXI_AWID ( M_AXI_AWID ),
.M_AXI_AWADDR ( M_AXI_AWADDR ),
.M_AXI_AWLEN ( M_AXI_AWLEN ),
.M_AXI_AWSIZE ( M_AXI_AWSIZE ),
.M_AXI_AWBURST ( M_AXI_AWBURST ),
.M_AXI_AWLOCK ( M_AXI_AWLOCK ),
.M_AXI_AWCACHE ( M_AXI_AWCACHE ),
.M_AXI_AWPROT ( M_AXI_AWPROT ),
.M_AXI_AWREGION ( M_AXI_AWREGION ),
.M_AXI_AWQOS ( M_AXI_AWQOS ),
.M_AXI_AWUSER ( M_AXI_AWUSER ),
.M_AXI_AWVALID ( M_AXI_AWVALID ),
.M_AXI_AWREADY ( M_AXI_AWREADY ),
.M_AXI_WID ( M_AXI_WID ),
.M_AXI_WDATA ( M_AXI_WDATA ),
.M_AXI_WSTRB ( M_AXI_WSTRB ),
.M_AXI_WLAST ( M_AXI_WLAST ),
.M_AXI_WUSER ( M_AXI_WUSER ),
.M_AXI_WVALID ( M_AXI_WVALID ),
.M_AXI_WREADY ( M_AXI_WREADY ),
.M_AXI_BID ( M_AXI_BID ),
.M_AXI_BRESP ( M_AXI_BRESP ),
.M_AXI_BUSER ( M_AXI_BUSER ),
.M_AXI_BVALID ( M_AXI_BVALID ),
.M_AXI_BREADY ( M_AXI_BREADY ),
.M_AXI_ARID ( M_AXI_ARID ),
.M_AXI_ARADDR ( M_AXI_ARADDR ),
.M_AXI_ARLEN ( M_AXI_ARLEN ),
.M_AXI_ARSIZE ( M_AXI_ARSIZE ),
.M_AXI_ARBURST ( M_AXI_ARBURST ),
.M_AXI_ARLOCK ( M_AXI_ARLOCK ),
.M_AXI_ARCACHE ( M_AXI_ARCACHE ),
.M_AXI_ARPROT ( M_AXI_ARPROT ),
.M_AXI_ARREGION ( M_AXI_ARREGION ),
.M_AXI_ARQOS ( M_AXI_ARQOS ),
.M_AXI_ARUSER ( M_AXI_ARUSER ),
.M_AXI_ARVALID ( M_AXI_ARVALID ),
.M_AXI_ARREADY ( M_AXI_ARREADY ),
.M_AXI_RID ( M_AXI_RID ),
.M_AXI_RDATA ( M_AXI_RDATA ),
.M_AXI_RRESP ( M_AXI_RRESP ),
.M_AXI_RLAST ( M_AXI_RLAST ),
.M_AXI_RUSER ( M_AXI_RUSER ),
.M_AXI_RVALID ( M_AXI_RVALID ),
.M_AXI_RREADY ( M_AXI_RREADY ),
.S_AXI_CTRL_AWADDR ( S_AXI_CTRL_AWADDR ),
.S_AXI_CTRL_AWVALID ( S_AXI_CTRL_AWVALID ),
.S_AXI_CTRL_AWREADY ( S_AXI_CTRL_AWREADY ),
.S_AXI_CTRL_WDATA ( S_AXI_CTRL_WDATA ),
.S_AXI_CTRL_WVALID ( S_AXI_CTRL_WVALID ),
.S_AXI_CTRL_WREADY ( S_AXI_CTRL_WREADY ),
.S_AXI_CTRL_BRESP ( S_AXI_CTRL_BRESP ),
.S_AXI_CTRL_BVALID ( S_AXI_CTRL_BVALID ),
.S_AXI_CTRL_BREADY ( S_AXI_CTRL_BREADY ),
.S_AXI_CTRL_ARADDR ( S_AXI_CTRL_ARADDR ),
.S_AXI_CTRL_ARVALID ( S_AXI_CTRL_ARVALID ),
.S_AXI_CTRL_ARREADY ( S_AXI_CTRL_ARREADY ),
.S_AXI_CTRL_RDATA ( S_AXI_CTRL_RDATA ),
.S_AXI_CTRL_RRESP ( S_AXI_CTRL_RRESP ),
.S_AXI_CTRL_RVALID ( S_AXI_CTRL_RVALID ),
.S_AXI_CTRL_RREADY ( S_AXI_CTRL_RREADY ),
.INTERCONNECT_ARESET_OUT_N ( INTERCONNECT_ARESET_OUT_N ),
.DEBUG_AW_TRANS_SEQ ( DEBUG_AW_TRANS_SEQ ),
.DEBUG_AW_ARB_GRANT ( DEBUG_AW_ARB_GRANT ),
.DEBUG_AR_TRANS_SEQ ( DEBUG_AR_TRANS_SEQ ),
.DEBUG_AR_ARB_GRANT ( DEBUG_AR_ARB_GRANT ),
.DEBUG_AW_TRANS_QUAL ( DEBUG_AW_TRANS_QUAL ),
.DEBUG_AW_ACCEPT_CNT ( DEBUG_AW_ACCEPT_CNT ),
.DEBUG_AW_ACTIVE_THREAD ( DEBUG_AW_ACTIVE_THREAD ),
.DEBUG_AW_ACTIVE_TARGET ( DEBUG_AW_ACTIVE_TARGET ),
.DEBUG_AW_ACTIVE_REGION ( DEBUG_AW_ACTIVE_REGION ),
.DEBUG_AW_ERROR ( DEBUG_AW_ERROR ),
.DEBUG_AW_TARGET ( DEBUG_AW_TARGET ),
.DEBUG_AR_TRANS_QUAL ( DEBUG_AR_TRANS_QUAL ),
.DEBUG_AR_ACCEPT_CNT ( DEBUG_AR_ACCEPT_CNT ),
.DEBUG_AR_ACTIVE_THREAD ( DEBUG_AR_ACTIVE_THREAD ),
.DEBUG_AR_ACTIVE_TARGET ( DEBUG_AR_ACTIVE_TARGET ),
.DEBUG_AR_ACTIVE_REGION ( DEBUG_AR_ACTIVE_REGION ),
.DEBUG_AR_ERROR ( DEBUG_AR_ERROR ),
.DEBUG_AR_TARGET ( DEBUG_AR_TARGET ),
.DEBUG_B_TRANS_SEQ ( DEBUG_B_TRANS_SEQ ),
.DEBUG_R_BEAT_CNT ( DEBUG_R_BEAT_CNT ),
.DEBUG_R_TRANS_SEQ ( DEBUG_R_TRANS_SEQ ),
.DEBUG_AW_ISSUING_CNT ( DEBUG_AW_ISSUING_CNT ),
.DEBUG_AR_ISSUING_CNT ( DEBUG_AR_ISSUING_CNT ),
.DEBUG_W_BEAT_CNT ( DEBUG_W_BEAT_CNT ),
.DEBUG_W_TRANS_SEQ ( DEBUG_W_TRANS_SEQ ),
.DEBUG_BID_TARGET ( DEBUG_BID_TARGET ),
.DEBUG_BID_ERROR ( DEBUG_BID_ERROR ),
.DEBUG_RID_TARGET ( DEBUG_RID_TARGET ),
.DEBUG_RID_ERROR ( DEBUG_RID_ERROR ),
.DEBUG_SR_SC_ARADDR ( DEBUG_SR_SC_ARADDR ),
.DEBUG_SR_SC_ARADDRCONTROL ( DEBUG_SR_SC_ARADDRCONTROL ),
.DEBUG_SR_SC_AWADDR ( DEBUG_SR_SC_AWADDR ),
.DEBUG_SR_SC_AWADDRCONTROL ( DEBUG_SR_SC_AWADDRCONTROL ),
.DEBUG_SR_SC_BRESP ( DEBUG_SR_SC_BRESP ),
.DEBUG_SR_SC_RDATA ( DEBUG_SR_SC_RDATA ),
.DEBUG_SR_SC_RDATACONTROL ( DEBUG_SR_SC_RDATACONTROL ),
.DEBUG_SR_SC_WDATA ( DEBUG_SR_SC_WDATA ),
.DEBUG_SR_SC_WDATACONTROL ( DEBUG_SR_SC_WDATACONTROL ),
.DEBUG_SC_SF_ARADDR ( DEBUG_SC_SF_ARADDR ),
.DEBUG_SC_SF_ARADDRCONTROL ( DEBUG_SC_SF_ARADDRCONTROL ),
.DEBUG_SC_SF_AWADDR ( DEBUG_SC_SF_AWADDR ),
.DEBUG_SC_SF_AWADDRCONTROL ( DEBUG_SC_SF_AWADDRCONTROL ),
.DEBUG_SC_SF_BRESP ( DEBUG_SC_SF_BRESP ),
.DEBUG_SC_SF_RDATA ( DEBUG_SC_SF_RDATA ),
.DEBUG_SC_SF_RDATACONTROL ( DEBUG_SC_SF_RDATACONTROL ),
.DEBUG_SC_SF_WDATA ( DEBUG_SC_SF_WDATA ),
.DEBUG_SC_SF_WDATACONTROL ( DEBUG_SC_SF_WDATACONTROL ),
.DEBUG_SF_CB_ARADDR ( DEBUG_SF_CB_ARADDR ),
.DEBUG_SF_CB_ARADDRCONTROL ( DEBUG_SF_CB_ARADDRCONTROL ),
.DEBUG_SF_CB_AWADDR ( DEBUG_SF_CB_AWADDR ),
.DEBUG_SF_CB_AWADDRCONTROL ( DEBUG_SF_CB_AWADDRCONTROL ),
.DEBUG_SF_CB_BRESP ( DEBUG_SF_CB_BRESP ),
.DEBUG_SF_CB_RDATA ( DEBUG_SF_CB_RDATA ),
.DEBUG_SF_CB_RDATACONTROL ( DEBUG_SF_CB_RDATACONTROL ),
.DEBUG_SF_CB_WDATA ( DEBUG_SF_CB_WDATA ),
.DEBUG_SF_CB_WDATACONTROL ( DEBUG_SF_CB_WDATACONTROL ),
.DEBUG_CB_MF_ARADDR ( DEBUG_CB_MF_ARADDR ),
.DEBUG_CB_MF_ARADDRCONTROL ( DEBUG_CB_MF_ARADDRCONTROL ),
.DEBUG_CB_MF_AWADDR ( DEBUG_CB_MF_AWADDR ),
.DEBUG_CB_MF_AWADDRCONTROL ( DEBUG_CB_MF_AWADDRCONTROL ),
.DEBUG_CB_MF_BRESP ( DEBUG_CB_MF_BRESP ),
.DEBUG_CB_MF_RDATA ( DEBUG_CB_MF_RDATA ),
.DEBUG_CB_MF_RDATACONTROL ( DEBUG_CB_MF_RDATACONTROL ),
.DEBUG_CB_MF_WDATA ( DEBUG_CB_MF_WDATA ),
.DEBUG_CB_MF_WDATACONTROL ( DEBUG_CB_MF_WDATACONTROL ),
.DEBUG_MF_MC_ARADDR ( DEBUG_MF_MC_ARADDR ),
.DEBUG_MF_MC_ARADDRCONTROL ( DEBUG_MF_MC_ARADDRCONTROL ),
.DEBUG_MF_MC_AWADDR ( DEBUG_MF_MC_AWADDR ),
.DEBUG_MF_MC_AWADDRCONTROL ( DEBUG_MF_MC_AWADDRCONTROL ),
.DEBUG_MF_MC_BRESP ( DEBUG_MF_MC_BRESP ),
.DEBUG_MF_MC_RDATA ( DEBUG_MF_MC_RDATA ),
.DEBUG_MF_MC_RDATACONTROL ( DEBUG_MF_MC_RDATACONTROL ),
.DEBUG_MF_MC_WDATA ( DEBUG_MF_MC_WDATA ),
.DEBUG_MF_MC_WDATACONTROL ( DEBUG_MF_MC_WDATACONTROL ),
.DEBUG_MC_MP_ARADDR ( DEBUG_MC_MP_ARADDR ),
.DEBUG_MC_MP_ARADDRCONTROL ( DEBUG_MC_MP_ARADDRCONTROL ),
.DEBUG_MC_MP_AWADDR ( DEBUG_MC_MP_AWADDR ),
.DEBUG_MC_MP_AWADDRCONTROL ( DEBUG_MC_MP_AWADDRCONTROL ),
.DEBUG_MC_MP_BRESP ( DEBUG_MC_MP_BRESP ),
.DEBUG_MC_MP_RDATA ( DEBUG_MC_MP_RDATA ),
.DEBUG_MC_MP_RDATACONTROL ( DEBUG_MC_MP_RDATACONTROL ),
.DEBUG_MC_MP_WDATA ( DEBUG_MC_MP_WDATA ),
.DEBUG_MC_MP_WDATACONTROL ( DEBUG_MC_MP_WDATACONTROL ),
.DEBUG_MP_MR_ARADDR ( DEBUG_MP_MR_ARADDR ),
.DEBUG_MP_MR_ARADDRCONTROL ( DEBUG_MP_MR_ARADDRCONTROL ),
.DEBUG_MP_MR_AWADDR ( DEBUG_MP_MR_AWADDR ),
.DEBUG_MP_MR_AWADDRCONTROL ( DEBUG_MP_MR_AWADDRCONTROL ),
.DEBUG_MP_MR_BRESP ( DEBUG_MP_MR_BRESP ),
.DEBUG_MP_MR_RDATA ( DEBUG_MP_MR_RDATA ),
.DEBUG_MP_MR_RDATACONTROL ( DEBUG_MP_MR_RDATACONTROL ),
.DEBUG_MP_MR_WDATA ( DEBUG_MP_MR_WDATA ),
.DEBUG_MP_MR_WDATACONTROL ( DEBUG_MP_MR_WDATACONTROL )
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
`ifdef MK3
`define MSU
`endif
`ifndef MSU
assign reg_data_out = 0;
assign status_out = 0;
assign volume_out = 0;
assign volume_latch_out = 0;
assign addr_out = 0;
assign track_out = 0;
assign DBG_msu_reg_oe_rising = 0;
assign DBG_msu_reg_oe_falling = 0;
assign DBG_msu_reg_we_rising = 0;
assign DBG_msu_address = 0;
assign DBG_msu_address_ext_write_rising = 0;
`else
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MK2
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b010};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
`endif
endmodule
|
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_addr_cmd_wrap
# ( parameter
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CKE_WIDTH = 2, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits
CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_LPDDR2_ENABLED = 1,
CFG_PORT_WIDTH_TYPE = 3,
CFG_DWIDTH_RATIO = 2,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_LOCAL_ID_WIDTH = 8,
CFG_DATA_ID_WIDTH = 4,
CFG_INT_SIZE_WIDTH = 4,
CFG_ODT_ENABLED = 1,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_PORT_WIDTH_CAS_WR_LAT = 5,
CFG_PORT_WIDTH_TCL = 5,
CFG_PORT_WIDTH_ADD_LAT = 5,
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
cfg_type,
cfg_tcl,
cfg_cas_wr_lat,
cfg_add_lat,
cfg_write_odt_chip,
cfg_read_odt_chip,
cfg_burst_length,
cfg_output_regd_for_afi_output,
// burst generator command signals
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_lmr_read,
bg_do_refresh_1bank,
bg_do_zq_cal,
bg_do_lmr,
bg_localid,
bg_dataid,
bg_size,
// burst generator address signals
bg_to_chip, // active high input (one hot)
bg_to_bank,
bg_to_row,
bg_to_col,
bg_to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_rst_n,
afi_odt
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam CFG_FR_DWIDTH_RATIO = 2;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk ;
input ctl_reset_n ;
input ctl_cal_success ;
//run-time csr chain input
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type ;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl ;
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat ;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat ;
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip ;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip ;
input [4:0] cfg_burst_length ;
//output regd signal from rdwr_tmg block
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
//command inputs
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col ;
input bg_do_lmr_read ;
input bg_do_refresh_1bank ;
input [2:0] bg_to_lmr ;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid ;
input [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid ;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size ;
input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode ;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// port type declaration
// -----------------------------
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
reg [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
reg [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// signal declaration
// -----------------------------
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_correct ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_partial ;
wire [CFG_MEM_IF_CKE_WIDTH - 1:0] int_afi_cke [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_CHIP- 1:0] int_afi_cs_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_ras_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_cas_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_we_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_BA_WIDTH - 1:0] int_afi_ba [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_ADDR_WIDTH-1:0] int_afi_addr [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rst_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_correct [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_partial [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_CKE_WIDTH - 1:0] int_afi_cke_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_CHIP- 1:0] int_afi_cs_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_ras_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_cas_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_we_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_BA_WIDTH - 1:0] int_afi_ba_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_ADDR_WIDTH-1:0] int_afi_addr_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rst_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rmw_correct_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rmw_partial_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cke ;
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cs_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_ras_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_cas_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_we_n ;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_ba ;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_addr ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rst_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_correct ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_partial ;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cs_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_ras_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_cas_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_ba;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_rst_n;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_write ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_read ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_chop ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_terminate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_auto_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_activate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct_r ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_precharge_all [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_self_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_power_down [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_deep_pdown [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_zq_cal [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_lmr ;
reg [CFG_MEM_IF_CHIP -1:0] int_bg_to_chip [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_col [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] int_bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_bg_size;
reg int_bg_do_lmr_read;
reg int_bg_do_refresh_1bank;
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] cfg_enable_chipsel_for_sideband;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh_r;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown_r;
wire one = 1'b1;
wire zero = 1'b0;
// -----------------------------
// module definition
// -----------------------------
genvar afi_j, afi_n;
generate
// map int_afi_* multi-dimensional array signals to afi_* output port signals
for (afi_n = 0; afi_n < (CFG_DWIDTH_RATIO/2); afi_n = afi_n + 1'b1)
begin : gen_afi_signals
always @ (*)
begin
if (cfg_output_regd_for_afi_output == 2)
begin
afi_cke [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)] = int_afi_cke_r [afi_n] ;
afi_cs_n [((afi_n+1) * CFG_MEM_IF_CHIP) -1 : (afi_n * CFG_MEM_IF_CHIP)] = int_afi_cs_n_r [afi_n] ;
afi_ras_n [afi_n] = int_afi_ras_n_r [afi_n] ;
afi_cas_n [afi_n] = int_afi_cas_n_r [afi_n] ;
afi_we_n [afi_n] = int_afi_we_n_r [afi_n] ;
afi_ba [((afi_n+1) * CFG_MEM_IF_BA_WIDTH) -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)] = int_afi_ba_r [afi_n] ;
afi_addr [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr_r [afi_n] ;
afi_rst_n [afi_n] = int_afi_rst_n_r [afi_n] ;
afi_rmw_correct [afi_n] = int_afi_rmw_correct_r [afi_n] ;
afi_rmw_partial [afi_n] = int_afi_rmw_partial_r [afi_n] ;
end
else
begin
afi_cke [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)] = int_afi_cke [afi_n] ;
afi_cs_n [((afi_n+1) * CFG_MEM_IF_CHIP) -1 : (afi_n * CFG_MEM_IF_CHIP)] = int_afi_cs_n [afi_n] ;
afi_ras_n [afi_n] = int_afi_ras_n [afi_n] ;
afi_cas_n [afi_n] = int_afi_cas_n [afi_n] ;
afi_we_n [afi_n] = int_afi_we_n [afi_n] ;
afi_ba [((afi_n+1) * CFG_MEM_IF_BA_WIDTH) -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)] = int_afi_ba [afi_n] ;
afi_addr [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr [afi_n] ;
afi_rst_n [afi_n] = int_afi_rst_n [afi_n] ;
afi_rmw_correct [afi_n] = int_afi_rmw_correct [afi_n] ;
afi_rmw_partial [afi_n] = int_afi_rmw_partial [afi_n] ;
end
end
end
// generate int_afi_* signals based on CFG_DWIDTH_RATIO & CFG_AFI_INTF_PHASE_NUM
if (CFG_DWIDTH_RATIO == 2)
begin
// full rate, with any phase
assign int_afi_cke [0] = fr_afi_cke ;
assign int_afi_cs_n [0] = fr_afi_cs_n ;
assign int_afi_ras_n [0] = fr_afi_ras_n ;
assign int_afi_cas_n [0] = fr_afi_cas_n ;
assign int_afi_we_n [0] = fr_afi_we_n ;
assign int_afi_ba [0] = fr_afi_ba ;
assign int_afi_addr [0] = fr_afi_addr ;
assign int_afi_rst_n [0] = fr_afi_rst_n ;
assign int_afi_rmw_correct [0] = fr_afi_rmw_correct ;
assign int_afi_rmw_partial [0] = fr_afi_rmw_partial ;
end
else if ((CFG_DWIDTH_RATIO/2) == CFG_AFI_INTF_PHASE_NUM)
begin
// map phase_afi_* signals to int_afi_* signals
// half rate , with phase=2
// quarter rate, with phase=4
for (afi_j = 0; afi_j < CFG_AFI_INTF_PHASE_NUM; afi_j = afi_j + 1'b1)
begin : gen_afi_signals_0
assign int_afi_cke [afi_j] = phase_afi_cke [afi_j] ;
assign int_afi_cs_n [afi_j] = phase_afi_cs_n [afi_j] ;
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j] ;
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j] ;
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j] ;
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j] ;
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j] ;
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j] ;
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j] ;
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j] ;
end
end
else // only supports case CFG_AFI_INTF_PHASE_NUM < (CFG_DWIDTH_RATIO/2)
begin
// map phase_afi_* signals to selected int_afi_* signals, and drive the rest to default values
// for cs_n signals:
// half rate , with phase=1, drives int_afi_* 1 only
// quarter rate , with phase=2, drives int_afi_* 1 & 3
// for other signals:
// half rate , with phase=1, drives int_afi_* 0 & 1 with the same value
// quarter rate , with phase=2, drives int_afi_* 0 & 1 or 2 & 3 with the same value
// Why? to improve timing margin on PHY side
for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1)
begin : gen_afi_signals_1
// Assign even phase with '1' because we only issue on odd phase (2T timing)
assign int_afi_cs_n [afi_j] = ((afi_j % CFG_AFI_INTF_PHASE_NUM) == 1) ? phase_afi_cs_n [afi_j / CFG_AFI_INTF_PHASE_NUM] : { CFG_MEM_IF_CHIP {1'b1} };
// Assign the last CKE with phase_afi_cs_n[1], the rest with phase_afi_cs_n[0]
assign int_afi_cke [afi_j] = (afi_j == ((CFG_DWIDTH_RATIO/2) - 1)) ? phase_afi_cke [1] : phase_afi_cke [0];
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j / CFG_AFI_INTF_PHASE_NUM];
end
end
for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1)
begin : gen_afi_signals_r
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_afi_cke_r [afi_j] <= 0;
int_afi_cs_n_r [afi_j] <= 0;
int_afi_ras_n_r [afi_j] <= 0;
int_afi_cas_n_r [afi_j] <= 0;
int_afi_we_n_r [afi_j] <= 0;
int_afi_ba_r [afi_j] <= 0;
int_afi_addr_r [afi_j] <= 0;
int_afi_rst_n_r [afi_j] <= 0;
int_afi_rmw_correct_r [afi_j] <= 0;
int_afi_rmw_partial_r [afi_j] <= 0;
end
else
begin
int_afi_cke_r [afi_j] <= int_afi_cke [afi_j];
int_afi_cs_n_r [afi_j] <= int_afi_cs_n [afi_j];
int_afi_ras_n_r [afi_j] <= int_afi_ras_n [afi_j];
int_afi_cas_n_r [afi_j] <= int_afi_cas_n [afi_j];
int_afi_we_n_r [afi_j] <= int_afi_we_n [afi_j];
int_afi_ba_r [afi_j] <= int_afi_ba [afi_j];
int_afi_addr_r [afi_j] <= int_afi_addr [afi_j];
int_afi_rst_n_r [afi_j] <= int_afi_rst_n [afi_j];
int_afi_rmw_correct_r [afi_j] <= int_afi_rmw_correct [afi_j];
int_afi_rmw_partial_r [afi_j] <= int_afi_rmw_partial [afi_j];
end
end
end
endgenerate
// phase_afi_* signal generation
// instantiates an alt_mem_ddrx_addr_cmd for every phase
// maps bg_* signals to the correct instantiation
genvar afi_k;
generate
for (afi_k = 0; afi_k < CFG_AFI_INTF_PHASE_NUM; afi_k = afi_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_write [afi_k] = bg_do_write [afi_k];
int_bg_do_read [afi_k] = bg_do_read [afi_k];
int_bg_do_burst_chop [afi_k] = bg_do_burst_chop [afi_k];
int_bg_do_burst_terminate [afi_k] = bg_do_burst_terminate [afi_k];
int_bg_do_auto_precharge [afi_k] = bg_do_auto_precharge [afi_k];
int_bg_do_rmw_correct [afi_k] = bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial [afi_k] = bg_do_rmw_partial [afi_k];
int_bg_do_activate [afi_k] = bg_do_activate [afi_k];
int_bg_do_precharge [afi_k] = bg_do_precharge [afi_k];
int_bg_to_chip [afi_k] = bg_to_chip [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_to_bank [afi_k] = bg_to_bank [(((afi_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(afi_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [afi_k] = bg_to_row [(((afi_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(afi_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_col [afi_k] = bg_to_col [(((afi_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(afi_k*CFG_MEM_IF_COL_WIDTH)];
end
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_refresh [afi_k] = bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_self_refresh [afi_k] = bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_deep_pdown [afi_k] = bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_zq_cal [afi_k] = bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_lmr [afi_k] = bg_do_lmr [afi_k];
end
always @ (*)
begin
cfg_enable_chipsel_for_sideband [afi_k] = one;
end
end
else // half and quarter rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_zq_cal [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_lmr [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_lmr [afi_k ] : 1'b0;
// We need to assign these command to all phase
// because these command might take one or more controller clock cycles
// and we want to prevent CKE from toggling due to prolong commands
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_self_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_self_refresh_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_deep_pdown [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_deep_pdown_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
end
always @ (*)
begin
// We need to disable one phase of chipsel logic for sideband in half/quarter rate
// in order to prevent CS_N from going low for 2 clock cycles (deep power down and self refresh only)
cfg_enable_chipsel_for_sideband [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? one : zero;
end
end
// addresss command block instantiated based on number of phases
alt_mem_ddrx_addr_cmd # (
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO ( CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_addr_cmd_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_cal_success ( ctl_cal_success ),
.cfg_type ( cfg_type ),
.cfg_output_regd ( cfg_output_regd_for_afi_output ),
.cfg_enable_chipsel_for_sideband ( cfg_enable_chipsel_for_sideband [afi_k] ),
.bg_do_write ( int_bg_do_write [afi_k] ),
.bg_do_read ( int_bg_do_read [afi_k] ),
.bg_do_auto_precharge ( int_bg_do_auto_precharge [afi_k] ),
.bg_do_burst_chop ( int_bg_do_burst_chop [afi_k] ),
.bg_do_activate ( int_bg_do_activate [afi_k] ),
.bg_do_precharge ( int_bg_do_precharge [afi_k] ),
.bg_do_refresh ( int_bg_do_refresh [afi_k] ),
.bg_do_power_down ( int_bg_do_power_down [afi_k] ),
.bg_do_self_refresh ( int_bg_do_self_refresh [afi_k] ),
.bg_do_lmr ( int_bg_do_lmr [afi_k] ),
.bg_do_precharge_all ( int_bg_do_precharge_all [afi_k] ),
.bg_do_zq_cal ( int_bg_do_zq_cal [afi_k] ),
.bg_do_deep_pdown ( int_bg_do_deep_pdown [afi_k] ),
.bg_do_burst_terminate ( int_bg_do_burst_terminate [afi_k] ),
.bg_to_chip ( int_bg_to_chip [afi_k] ),
.bg_to_bank ( int_bg_to_bank [afi_k] ),
.bg_to_row ( int_bg_to_row [afi_k] ),
.bg_to_col ( int_bg_to_col [afi_k] ),
.bg_to_lmr ( bg_to_lmr ),
.lmr_opcode ( lmr_opcode ),
.afi_cke ( int_ddrx_afi_cke [afi_k] ),
.afi_cs_n ( int_ddrx_afi_cs_n [afi_k] ),
.afi_ras_n ( int_ddrx_afi_ras_n [afi_k] ),
.afi_cas_n ( int_ddrx_afi_cas_n [afi_k] ),
.afi_we_n ( int_ddrx_afi_we_n [afi_k] ),
.afi_ba ( int_ddrx_afi_ba [afi_k] ),
.afi_addr ( int_ddrx_afi_addr [afi_k] ),
.afi_rst_n ( int_ddrx_afi_rst_n [afi_k] )
);
if (CFG_LPDDR2_ENABLED)
begin
alt_mem_ddrx_lpddr2_addr_cmd # (
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_lpddr2_addr_cmd_inst (
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.cfg_enable_chipsel_for_sideband (cfg_enable_chipsel_for_sideband [afi_k]),
.do_write (int_bg_do_write [afi_k]),
.do_read (int_bg_do_read [afi_k]),
.do_auto_precharge (int_bg_do_auto_precharge [afi_k]),
.do_activate (int_bg_do_activate [afi_k]),
.do_precharge (int_bg_do_precharge [afi_k]),
.do_refresh (int_bg_do_refresh [afi_k]),
.do_power_down (int_bg_do_power_down [afi_k]),
.do_self_refresh (int_bg_do_self_refresh [afi_k]),
.do_lmr (int_bg_do_lmr [afi_k]),
.do_precharge_all (int_bg_do_precharge_all [afi_k]),
.do_deep_pwrdwn (int_bg_do_deep_pdown [afi_k]),
.do_burst_terminate (int_bg_do_burst_terminate [afi_k]),
.do_lmr_read (int_bg_do_lmr_read ),
.do_refresh_1bank (int_bg_do_refresh_1bank ),
.to_chip (int_bg_to_chip [afi_k]),
.to_bank (int_bg_to_bank [afi_k]),
.to_row (int_bg_to_row [afi_k]),
.to_col (int_bg_to_col [afi_k]),
.to_lmr (bg_to_lmr ),
.lmr_opcode (lmr_opcode[7:0] ),
.afi_cke (int_lpddr2_afi_cke [afi_k]),
.afi_cs_n (int_lpddr2_afi_cs_n [afi_k]),
.afi_addr (int_lpddr2_afi_addr [afi_k]),
.afi_rst_n (int_lpddr2_afi_rst_n [afi_k])
);
end
else
begin
assign int_lpddr2_afi_cke [afi_k] = {(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_cs_n [afi_k] = {(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_addr [afi_k] = {(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_rst_n [afi_k] = { (CFG_FR_DWIDTH_RATIO/2) {1'b0}};
end
always @ (*)
begin
// Mux to select ddrx or lpddr2 addrcmd decoder blocks
if (cfg_type == `MMR_TYPE_LPDDR2)
begin
phase_afi_cke [afi_k] = int_lpddr2_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_lpddr2_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_cas_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_we_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_ba [afi_k] = {(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
phase_afi_addr [afi_k] = int_lpddr2_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_lpddr2_afi_rst_n[afi_k] ;
end
else
begin
phase_afi_cke [afi_k] = int_ddrx_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_ddrx_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = int_ddrx_afi_ras_n [afi_k] ;
phase_afi_cas_n [afi_k] = int_ddrx_afi_cas_n [afi_k] ;
phase_afi_we_n [afi_k] = int_ddrx_afi_we_n [afi_k] ;
phase_afi_ba [afi_k] = int_ddrx_afi_ba [afi_k] ;
phase_afi_addr [afi_k] = int_ddrx_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_ddrx_afi_rst_n [afi_k] ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_bg_do_rmw_correct_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
int_bg_do_rmw_partial_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
end
else
begin
int_bg_do_rmw_correct_r[afi_k] <= int_bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial_r[afi_k] <= int_bg_do_rmw_partial [afi_k];
end
end
always @ (*)
begin
if (cfg_output_regd_for_afi_output)
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct_r [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial_r [afi_k];
end
else
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial [afi_k];
end
end
alt_mem_ddrx_odt_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
odt_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.bg_do_read (int_bg_do_read [afi_k]),
.bg_do_write (int_bg_do_write [afi_k]),
.bg_do_burst_chop (int_bg_do_burst_chop [afi_k]),
.bg_to_chip (int_bg_to_chip [afi_k]),
.afi_odt (afi_odt_h_l [afi_k])
);
end
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
int_bg_do_lmr_read = bg_do_lmr_read;
int_bg_do_refresh_1bank = bg_do_refresh_1bank;
end
endgenerate
// ODT output generation
always @ (*)
begin
afi_odt = mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1];
end
// generate ODT output signal from odt_gen
assign mux_afi_odt_h_l [0] = afi_odt_h_l [0];
genvar afi_m;
generate
for (afi_m = 1; afi_m < CFG_AFI_INTF_PHASE_NUM; afi_m = afi_m + 1)
begin : mux_for_odt
assign mux_afi_odt_h_l [afi_m] = mux_afi_odt_h_l [afi_m-1] | afi_odt_h_l [afi_m];
end
endgenerate
// generate fr_* signals from phase_* signals
assign mux_afi_cke [0] = phase_afi_cke [0];
assign mux_afi_cs_n [0] = phase_afi_cs_n [0];
assign mux_afi_ras_n [0] = phase_afi_ras_n [0];
assign mux_afi_cas_n [0] = phase_afi_cas_n [0];
assign mux_afi_we_n [0] = phase_afi_we_n [0];
assign mux_afi_ba [0] = phase_afi_ba [0];
assign mux_afi_addr [0] = phase_afi_addr [0];
assign mux_afi_rst_n [0] = phase_afi_rst_n [0];
assign mux_afi_rmw_correct [0] = phase_afi_rmw_correct [0];
assign mux_afi_rmw_partial [0] = phase_afi_rmw_partial [0];
genvar afi_l;
generate
for (afi_l = 1; afi_l < CFG_AFI_INTF_PHASE_NUM; afi_l = afi_l + 1)
begin : gen_resolve_phase_for_fullrate
assign mux_afi_cke [afi_l] = mux_afi_cke [(afi_l-1)] & phase_afi_cke [afi_l];
assign mux_afi_cs_n [afi_l] = mux_afi_cs_n [(afi_l-1)] & phase_afi_cs_n [afi_l];
assign mux_afi_ras_n [afi_l] = mux_afi_ras_n [(afi_l-1)] & phase_afi_ras_n [afi_l];
assign mux_afi_cas_n [afi_l] = mux_afi_cas_n [(afi_l-1)] & phase_afi_cas_n [afi_l];
assign mux_afi_we_n [afi_l] = mux_afi_we_n [(afi_l-1)] & phase_afi_we_n [afi_l];
assign mux_afi_ba [afi_l] = mux_afi_ba [(afi_l-1)] | phase_afi_ba [afi_l];
assign mux_afi_addr [afi_l] = mux_afi_addr [(afi_l-1)] | phase_afi_addr [afi_l];
assign mux_afi_rst_n [afi_l] = mux_afi_rst_n [(afi_l-1)] | phase_afi_rst_n [afi_l];
assign mux_afi_rmw_correct [afi_l] = mux_afi_rmw_correct [(afi_l-1)] | phase_afi_rmw_correct [afi_l];
assign mux_afi_rmw_partial [afi_l] = mux_afi_rmw_partial [(afi_l-1)] | phase_afi_rmw_partial [afi_l];
end
endgenerate
assign fr_afi_cke = mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cs_n = mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ras_n = mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cas_n = mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_we_n = mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ba = mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_addr = mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rst_n = mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_correct = mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_partial = mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
// Registered version of self refresh and power down
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bg_do_self_refresh_r <= 0;
bg_do_deep_pdown_r <= 0;
end
else
begin
bg_do_self_refresh_r <= bg_do_self_refresh;
bg_do_deep_pdown_r <= bg_do_deep_pdown;
end
end
endmodule
|
// `define DEBUG
module resampler_core
#(
parameter NUM_CH = 8,
parameter NUM_CH_LOG2 = 3,
parameter HALFDEPTH = 16,
parameter HALFDEPTH_LOG2 = 4,
parameter NUM_FIR = 160,
parameter NUM_FIR_LOG2 = 8,
parameter DECIM = 147,
parameter BANK_WIDTH = NUM_FIR_LOG2+HALFDEPTH_LOG2,
parameter TIMESLICE = 64,
parameter TIMESLICE_LOG2 = 6
)(
input wire clk,
input wire rst,
// to firbank
output wire [(BANK_WIDTH-1):0] bank_addr_o,
input wire [23:0] bank_data_i,
// to ringbuf array
output wire [(NUM_CH-1):0] pop_o,
output wire [(HALFDEPTH_LOG2+1-1):0] offset_o,
input wire [(NUM_CH*24-1):0] data_i,
// data output wire
input wire [(NUM_CH-1):0] pop_i,
output wire [23:0] data_o,
output wire [(NUM_CH-1):0] ack_o);
// Latch pop_i request
wire [(NUM_CH-1):0] ack_pop_i;
wire [(NUM_CH-1):0] pop_i_latched;
genvar igl;
generate
for(igl = 0; igl < NUM_CH; igl = igl + 1) begin:g
pop_latch pop_latch(
.clk(clk), .rst(rst),
.pop_i(pop_i[igl]),
.ack_pop_i(ack_pop_i[igl]), .pop_latched_o(pop_i_latched[igl]));
end
endgenerate
// Fixed timeslice based scheduling and decide ch to process
reg [(NUM_CH_LOG2-1):0] processing_ch_ff;
reg rst_processing_ff;
reg [(TIMESLICE_LOG2-1):0] timeslice_counter;
wire timeslice_deadline = (timeslice_counter == TIMESLICE-1);
always @(posedge clk) begin
if (rst) begin
timeslice_counter <= 0;
processing_ch_ff <= 0;
rst_processing_ff <= 1;
end else begin
timeslice_counter <= timeslice_counter + 1;
if (timeslice_deadline) begin
timeslice_counter <= 0;
processing_ch_ff <= processing_ch_ff + 1;
rst_processing_ff <= 1;
end else
rst_processing_ff <= 0;
end
end
// Sequence management
reg [7:0] state_ff; // Note: bit width will be optimized anyway.
parameter MULT_LATENCY = 5;
parameter ST_READY = 0;
parameter ST_MULADD_RWING = 2; // HALFDEPTH clk
parameter ST_MULADD_LWING = 3; // HALFDEPTH clk
parameter ST_WAIT_RESULT = 4; // 1 + MULT_LATENCY clk
parameter ST_SATURATE = 5; // 1 clk
parameter ST_END_CYCLE = 6; // 1 clk
parameter ST_IDLE = 7;
reg [(NUM_CH-1):0] ack_pop_ff;
assign ack_pop_i = ack_pop_ff;
reg [HALFDEPTH_LOG2:0] muladd_wing_cycle_counter;
always @(posedge clk) begin
if (rst_processing_ff) begin
ack_pop_ff <= 1 << processing_ch_ff;
state_ff <= ST_READY;
end else begin
muladd_wing_cycle_counter <= muladd_wing_cycle_counter + 1;
ack_pop_ff <= 0;
case (state_ff)
ST_READY: begin
if (pop_i_latched[processing_ch_ff]) begin
state_ff <= ST_MULADD_RWING;
muladd_wing_cycle_counter <= 0;
end
end
ST_MULADD_RWING: begin
if (muladd_wing_cycle_counter == HALFDEPTH-1) begin
state_ff <= ST_MULADD_LWING;
muladd_wing_cycle_counter <= 0;
end
end
ST_MULADD_LWING: begin
if (muladd_wing_cycle_counter == HALFDEPTH-1) begin
state_ff <= ST_WAIT_RESULT;
muladd_wing_cycle_counter <= 0;
end
end
ST_WAIT_RESULT: begin
if (muladd_wing_cycle_counter == 1+MULT_LATENCY-1)
state_ff <= ST_SATURATE;
end
ST_SATURATE: begin
state_ff <= ST_END_CYCLE;
end
ST_END_CYCLE: begin
state_ff <= ST_IDLE;
end
ST_IDLE: begin end // NOP
endcase
end
end
// Compute polyphase FIR filter index
// OUTPUT:
reg [(NUM_FIR_LOG2-1):0] firidx_rwing_currch_ff;
reg [(NUM_FIR_LOG2-1):0] firidx_lwing_currch_ff;
reg [(NUM_CH-1):0] pop_o_ff;
assign pop_o = pop_o_ff;
reg [(NUM_FIR_LOG2-1):0] firidx_mem [(NUM_CH-1):0];
integer i;
always @(posedge clk) begin
pop_o_ff <= 0;
if (rst) begin
for (i = 0; i < NUM_CH; i = i + 1) begin
firidx_mem[i] <= 0;
end
firidx_lwing_currch_ff <= 0;
end else begin
case (state_ff)
ST_READY: begin
firidx_lwing_currch_ff <= firidx_mem[processing_ch_ff];
firidx_rwing_currch_ff <= NUM_FIR-1 - firidx_mem[processing_ch_ff];
end
ST_MULADD_RWING: begin
`ifdef DEBUG
if (muladd_wing_cycle_counter == 0)
$display("ch: %d. firidx_lwing: %d", processing_ch_ff, firidx_mem[processing_ch_ff]);
`endif
end
ST_END_CYCLE: begin
if (firidx_lwing_currch_ff >= NUM_FIR - DECIM) begin
firidx_mem[processing_ch_ff] <= firidx_lwing_currch_ff + DECIM - NUM_FIR;
pop_o_ff[processing_ch_ff] <= 1;
`ifdef DEBUG
$display("ch: %d. pop!", processing_ch_ff);
`endif
end else begin
firidx_mem[processing_ch_ff] <= firidx_lwing_currch_ff + DECIM;
end
end
endcase
end
end
// Supply mplier
// OUTPUT:
wire [23:0] mplier_o = bank_data_i;
wire mplier_lwing_active = state_ff == ST_MULADD_LWING ? 1'b1 : 1'b0;
wire [(NUM_FIR_LOG2-1):0] firidx = mplier_lwing_active ? firidx_lwing_currch_ff : firidx_rwing_currch_ff;
reg [(HALFDEPTH_LOG2-1):0] depthidx_ff;
assign bank_addr_o[(BANK_WIDTH-1):0] = {firidx, depthidx_ff}; // FIXME: HALFDEPTH must be power of 2
always @(posedge clk) begin
case (state_ff)
ST_READY:
depthidx_ff <= HALFDEPTH-1;
ST_MULADD_RWING:
if (depthidx_ff != 0)
depthidx_ff <= depthidx_ff - 1;
ST_MULADD_LWING:
depthidx_ff <= depthidx_ff + 1;
endcase
end
// Supply mpcand
// OUTPUT:
wire [23:0] mpcand_o;
reg [(HALFDEPTH_LOG2-1):0] offset_counter;
assign offset_o = {~mplier_lwing_active, offset_counter};
always @(posedge clk) begin
offset_counter <= offset_counter - 1;
if (state_ff == ST_READY)
offset_counter <= HALFDEPTH-1;
end
wire [23:0] data_i_ary [(NUM_CH-1):0];
genvar ig;
generate
for (ig = 0; ig < NUM_CH; ig = ig + 1) begin:data_i_to_ary
assign data_i_ary[ig] = data_i[(ig*24)+:24];
end
endgenerate
assign mpcand_o = data_i_ary[processing_ch_ff];
// Multiplier
wire [27:0] mprod_i;
mpemu mpemu(.clk(clk), .mpcand_i(mpcand_o), .mplier_i(mplier_o), .mprod_o(mprod_i));
parameter KILL_RESULT = MULT_LATENCY + 1; // 1 clk for rom/ringbuf latency
reg [(KILL_RESULT-1):0] kill_result_ff;
always @(posedge clk) begin
if (state_ff == ST_READY)
kill_result_ff <= 0;
else
kill_result_ff <= {1'b1, kill_result_ff[(KILL_RESULT-1):1]};
end
wire product_valid = kill_result_ff[0];
// Adder
reg [31:0] sum_ff;
function [31:0] saturated_add(
input [31:0] a,
input [31:0] b);
reg [32:0] aext;
reg [32:0] bext;
reg [32:0] sumext;
begin
aext = {a[31], a};
bext = {b[31], b};
sumext = $signed(aext) + $signed(bext);
case (sumext[32:31])
2'b00, 2'b11: // sum is in expressible range
saturated_add = sumext[31:0];
2'b01: // overflow
saturated_add = 32'h7fff_ffff;
2'b10: // underflow
saturated_add = 32'h8000_0000;
endcase
end
endfunction
always @(posedge clk) begin
if (!product_valid) begin
sum_ff <= 0;
end else begin
`ifdef DEBUG
if (ST_READY < state_ff && state_ff < ST_END_CYCLE)
$display("ch: %d curr_sum: %d shifted %d. mpcand %d * mplier %d = %d",
processing_ch_ff, $signed(sum_ff), $signed(sum_ff) >>> 3, $signed(mpemu.delayed_a), $signed(mpemu.delayed_b), $signed(mprod_i));
`endif
sum_ff <= saturated_add(sum_ff, {{4{mprod_i[27]}}, mprod_i});
end
end
// Result
reg [23:0] saturated_sum_ff;
always @(posedge clk) begin
if (sum_ff[31] == 1'b0) begin
// sum +
if (sum_ff[30:27] != 4'b0000)
saturated_sum_ff <= 24'h7f_ffff; // overflow
else
saturated_sum_ff <= {1'b0, sum_ff[26:3]}; // sum is in expressible range
end else begin
// sum -
if (sum_ff[30:27] != 4'b1111)
saturated_sum_ff <= 24'h80_0000; // underflow
else
saturated_sum_ff <= {1'b1, sum_ff[26:3]}; // sum is in expressible range
end
end
assign data_o = saturated_sum_ff;
assign ack_o = (state_ff == ST_END_CYCLE ? 1 : 0) << processing_ch_ff;
endmodule
module ringbuffered_resampler
#(
parameter NUM_CH = 8,
parameter NUM_CH_LOG2 = 3,
parameter HALFDEPTH = 16,
parameter HALFDEPTH_LOG2 = 4,
parameter NUM_FIR = 160,
parameter NUM_FIR_LOG2 = 8,
parameter DECIM = 147,
parameter BANK_WIDTH = NUM_FIR_LOG2+HALFDEPTH_LOG2,
parameter TIMESLICE = 64, // Not sure if this is OK.
parameter TIMESLICE_LOG2 = 6
)(
input wire clk,
input wire rst,
input wire [(NUM_CH-1):0] rst_ch,
// to firbank
output wire [(BANK_WIDTH-1):0] bank_addr_o,
input wire [23:0] bank_data_i,
// data input wire
input wire [(NUM_CH-1):0] ack_i,
input wire [(24*NUM_CH-1):0] data_i,
output wire [(NUM_CH-1):0] pop_o,
// data output wire
input wire [(NUM_CH-1):0] pop_i,
output wire [23:0] data_o,
output wire [(NUM_CH-1):0] ack_o);
wire [(NUM_CH-1):0] pop;
wire [(HALFDEPTH_LOG2+1-1):0] rb_offset;
wire [(NUM_CH*24-1):0] rb_data;
genvar ig;
generate
for (ig = 0; ig < NUM_CH; ig = ig + 1) begin:rbunit
ringbuf #(
.LEN(HALFDEPTH*4), // should work w/ *2, but buffer a little longer to address input wire jitter
.LEN_LOG2(HALFDEPTH_LOG2+2)
) rb(
.clk(clk), .rst(rst | rst_ch[ig]),
.data_i(data_i[(24*ig)+:24]), .we_i(ack_i[ig]),
.pop_i(pop[ig]), .offset_i({1'b0, rb_offset[HALFDEPTH_LOG2:0]}), .data_o(rb_data[(24*ig) +: 24]));
end
endgenerate
resampler_core #(
.NUM_CH(NUM_CH), .NUM_CH_LOG2(NUM_CH_LOG2),
.HALFDEPTH(HALFDEPTH), .HALFDEPTH_LOG2(HALFDEPTH_LOG2),
.NUM_FIR(NUM_FIR), .NUM_FIR_LOG2(NUM_FIR_LOG2), .DECIM(DECIM),
.TIMESLICE(TIMESLICE), .TIMESLICE_LOG2(TIMESLICE_LOG2)
) core(
.clk(clk), .rst(rst),
.bank_addr_o(bank_addr_o), .bank_data_i(bank_data_i),
.pop_o(pop), .offset_o(rb_offset), .data_i(rb_data),
.pop_i(pop_i), .data_o(data_o), .ack_o(ack_o)
);
assign pop_o = pop;
endmodule
|
(*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*)
Require Import String.
Require Import List.
Require Import Compare_dec.
Require Import Program.
Require Import Eqdep_dec.
Require Import Bool.
Require Import EquivDec.
Require Import Utils.
Require Import Types.
Require Import ForeignData.
Require Import DataModel.
Require Import Operators.
Require Import TData.
Require Import ForeignDataTyping.
Section TUtil.
(* Lemma/definitions over types involved in the inference *)
Context {fdata:foreign_data}.
Context {ftype:foreign_type}.
Context {m:brand_model}.
(* Useful function *)
Definition tdot {A} (l:list (string * A)) (a:string) : option A := edot l a.
(* Type deconstructors *)
Definition tuneither (τ:rtype) : option (rtype * rtype).
Proof.
destruct τ.
destruct x.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- refine (Some ((exist _ x1 _),(exist _ x2 _))).
+ simpl in e; rewrite andb_true_iff in e; tauto.
+ simpl in e; rewrite andb_true_iff in e; tauto.
- exact None.
- exact None.
- exact None.
Defined.
Definition tuncoll (τ:rtype) : option rtype.
Proof.
destruct τ.
destruct x.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact (Some (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) x e)).
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
Defined.
Lemma tuncoll_correct (τ τ':rtype) :
tuncoll τ = Some τ' ->
τ = Coll τ'.
Proof.
destruct τ using rtype_rect; try discriminate.
inversion 1; subst.
reflexivity.
Qed.
Definition tsingleton (τ:rtype) : option rtype.
Proof.
destruct τ.
destruct x.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact (Some (Option (exist (fun τ₀ : rtype₀ => wf_rtype₀ τ₀ = true) x e))).
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
Defined.
Lemma tsingleton_correct (τ τ':rtype) :
tsingleton τ = Some (Option τ') ->
τ = Coll τ'.
Proof.
destruct τ using rtype_rect; try discriminate.
inversion 1; subst.
rtype_equalizer; subst.
reflexivity.
Qed.
Definition tunrec (τ: rtype) : option (record_kind * (list (string * rtype))).
Proof.
destruct τ; destruct x.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- generalize (from_Rec₀ srl e); intros.
destruct H.
exact (Some (k,x)).
- exact None.
- exact None.
- exact None.
- exact None.
Defined.
Lemma tunrec_correct k (τ:rtype) {l} :
tunrec τ = Some (k,l) ->
{pf | τ = Rec k l pf}.
Proof.
destruct τ using rtype_rect; try discriminate.
inversion 1; subst.
match goal with
| [H:context
[match ?p with
| _ => _
end] |- _] => destruct p
end.
inversion H2; subst; clear H2.
destruct e as [? [??]].
rtype_equalizer; subst.
eauto.
Qed.
Definition trecConcat (τ₁ τ₂: rtype) : option rtype.
Proof.
destruct τ₁; destruct x.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- destruct τ₂; destruct x.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ generalize (from_Rec₀ srl e); intros.
generalize (from_Rec₀ srl0 e0); intros.
destruct H; destruct H0.
destruct k; destruct k0; simpl.
* exact None. (* Open record *)
* exact None. (* Open record *)
* exact None. (* Open record *)
* generalize (rec_concat_sort x x0); intros.
exact (RecMaybe Closed H).
+ exact None.
+ exact None.
+ exact None.
+ exact None.
- exact None.
- exact None.
- exact None.
- exact None.
Defined.
Definition trecConcatRight (τ₁ τ₂: rtype) : option rtype.
Proof.
destruct τ₁; destruct x.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- destruct τ₂; destruct x.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ generalize (from_Rec₀ srl e); intros.
generalize (from_Rec₀ srl0 e0); intros.
destruct H; destruct H0.
destruct k; destruct k0; simpl.
* exact None. (* Both open record *)
* generalize (rec_concat_sort x x0); intros. (* Left open record *)
exact (RecMaybe Open H).
* exact None. (* Right open record *)
* generalize (rec_concat_sort x x0); intros.
exact (RecMaybe Closed H).
+ exact None.
+ exact None.
+ exact None.
+ exact None.
- exact None.
- exact None.
- exact None.
- exact None.
Defined.
Definition tmergeConcat (τ₁ τ₂: rtype) : option rtype.
Proof.
destruct τ₁; destruct x.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- exact None.
- destruct τ₂; destruct x.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
+ generalize (from_Rec₀ srl e); intros.
generalize (from_Rec₀ srl0 e0); intros.
destruct H; destruct H0.
generalize (merge_bindings x x0); intros.
destruct H as [rSome|].
destruct k; destruct k0; simpl in *.
* exact (RecMaybe Open rSome).
* exact None.
* exact None.
* exact (RecMaybe Closed rSome).
* exact None.
+ exact None.
+ exact None.
+ exact None.
+ exact None.
- exact None.
- exact None.
- exact None.
- exact None.
Defined.
Definition tunrecdot (s:string) (τ:rtype) : option rtype.
Proof.
generalize (tunrec τ); intros.
case_eq H; intros.
- destruct p; simpl in *.
exact (tdot l s).
- exact None.
Defined.
Definition tunrecremove (s:string) (τ:rtype) : option rtype.
Proof.
generalize (tunrec τ); intros.
case_eq H; intros.
- destruct p; simpl in *.
exact (RecMaybe r (rremove l s)).
- exact None.
Defined.
Definition tunrecproject (sl:list string) (τ:rtype) : option rtype.
Proof.
generalize (tunrec τ); intros.
case_eq H; intros.
- destruct p; simpl in *.
destruct (sublist_dec sl (domain l)).
+ exact (RecMaybe Closed (rproject l sl)). (* This is always a closed record *)
+ exact None. (* It is only well typed when sl is a sublist of domain l *)
- exact None.
Defined.
(* Type inference for binary operators *)
Definition recConcat (τ₁ τ₂: rtype) : option rtype.
Proof.
generalize (tunrec τ₁); intros.
case_eq H; intros.
- generalize (tunrec τ₂); intros.
case_eq H1; intros.
destruct p; destruct p0; simpl in *.
+ generalize (rec_concat_sort l l0); intros.
destruct r; destruct r0; simpl in *.
* exact None.
* exact None.
* exact None.
* exact (RecMaybe Closed H3).
+ exact None.
- exact None.
Defined.
Definition mergeConcat (τ₁ τ₂: rtype) : option rtype.
Proof.
generalize (tunrec τ₁); generalize (tunrec τ₂); intros.
case_eq H; case_eq H0; intros.
destruct p; destruct p0; simpl in *.
generalize (merge_bindings l l0); intros.
- destruct H3 as [rSome|].
destruct r; destruct r0; simpl in *.
* exact (RecMaybe Open rSome).
* exact None.
* exact None.
* exact (RecMaybe Closed rSome).
* exact None.
- exact None.
- exact None.
- exact None.
Defined.
Lemma RecMaybe_rec_concat_sort k l1 l2 :
RecMaybe k (rec_concat_sort l1 l2) = Some (Rec k (rec_concat_sort l1 l2) (drec_concat_sort_sorted l1 l2)).
Proof.
apply (RecMaybe_pf_some _).
Qed.
Lemma Bottom_proj : Bottom₀ = ` Bottom.
Proof.
reflexivity.
Qed.
Lemma Top_proj : Top₀ = ` Top.
Proof.
reflexivity.
Qed.
Lemma Unit_proj : Unit₀ = ` Unit.
Proof.
reflexivity.
Qed.
Lemma Nat_proj : Nat₀ = ` Nat.
Proof.
reflexivity.
Qed.
Lemma Float_proj : Float₀ = ` Float.
Proof.
reflexivity.
Qed.
Lemma Bool_proj : Bool₀ = ` Bool.
Proof.
reflexivity.
Qed.
Lemma String_proj : String₀ = ` String.
Proof.
reflexivity.
Qed.
Lemma Brand_canon {b} {τ₁:rtype} :` τ₁ = Brand₀ b -> τ₁ = Brand b.
Proof.
destruct τ₁; simpl; intros; subst.
apply brand_ext.
Qed.
Lemma Bottom_canon {τ₁:rtype} :` τ₁ = Bottom₀ -> τ₁ = Bottom.
Proof.
destruct τ₁; simpl; intros; subst.
apply rtype_ext.
Qed.
Lemma Top_canon {τ₁:rtype} :` τ₁ = Top₀ -> τ₁ = Top.
Proof.
destruct τ₁; simpl; intros; subst.
apply rtype_ext.
Qed.
Lemma Unit_canon {τ₁:rtype} :` τ₁ = Unit₀ -> τ₁ = Unit.
Proof.
destruct τ₁; simpl; intros; subst.
apply rtype_ext.
Qed.
Lemma Nat_canon {τ₁:rtype} :` τ₁ = Nat₀ -> τ₁ = Nat.
Proof.
destruct τ₁; simpl; intros; subst.
apply rtype_ext.
Qed.
Lemma Float_canon {τ₁:rtype} :` τ₁ = Float₀ -> τ₁ = Float.
Proof.
destruct τ₁; simpl; intros; subst.
apply rtype_ext.
Qed.
Lemma Bool_canon {τ₁:rtype} :` τ₁ = Bool₀ -> τ₁ = Bool.
Proof.
destruct τ₁; simpl; intros; subst.
apply rtype_ext.
Qed.
Lemma String_canon {τ₁:rtype} :` τ₁ = String₀ -> τ₁ = String.
Proof.
destruct τ₁; simpl; intros; subst.
apply rtype_ext.
Qed.
Lemma Coll_canon {τ₁ τ₀:rtype} :` τ₁ = Coll₀ (` τ₀) -> τ₁ = Coll τ₀.
Proof.
destruct τ₁; simpl; intros; subst.
apply rtype_ext.
Qed.
Section lift_map.
Context {fdtyping:foreign_data_typing}.
Lemma omap_product_empty_right τ pf l:
Forall (fun d : data => d ▹ Rec Closed τ pf) l ->
(omap_product (fun _ : data => Some (dcoll (drec nil :: nil))) l) = Some l.
Proof.
intros.
induction l; simpl; unfold omap_product in *; simpl.
- reflexivity.
- inversion H; clear H; subst.
specialize (IHl H3); clear H3.
rewrite IHl.
inversion H2.
dtype_inverter. subst.
unfold rec_concat_sort.
rewrite app_nil_r.
assert (rec_sort dl = dl).
+ clear a e.
rewrite sort_sorted_is_id.
reflexivity.
rewrite (same_domain_same_sorted rl dl).
reflexivity.
clear pf' H0 H2 H4 H1 rl_sub IHl pf.
assert (domain dl = domain rl).
apply (sorted_forall_same_domain); assumption.
auto.
assumption.
+ rewrite H.
reflexivity.
Qed.
Lemma oproduct_empty_right τ pf l:
Forall (fun d : data => d ▹ Rec Closed τ pf) l ->
(oproduct l (drec nil :: nil)) = Some l.
Proof.
intros.
induction l; simpl; unfold omap_product in *; simpl.
- reflexivity.
- inversion H; clear H; subst.
specialize (IHl H3); clear H3.
unfold oproduct in *; simpl in *; rewrite IHl.
inversion H2.
dtype_inverter. subst.
unfold rec_concat_sort.
rewrite app_nil_r.
assert (rec_sort dl = dl).
+ clear a e.
rewrite sort_sorted_is_id.
reflexivity.
rewrite (same_domain_same_sorted rl dl).
reflexivity.
clear pf' H0 H2 H4 H1 rl_sub IHl pf.
assert (domain dl = domain rl).
apply (sorted_forall_same_domain); assumption.
auto.
assumption.
+ rewrite H.
reflexivity.
Qed.
Lemma omap_product_empty_left τ pf l:
Forall (fun d : data => d ▹ Rec Closed τ pf) l ->
(omap_product (fun _ : data => Some (dcoll l)) (drec nil::nil)) = Some l.
Proof.
intros.
induction l; simpl; unfold omap_product in *; simpl.
- reflexivity.
- inversion H; clear H; subst.
specialize (IHl H3); clear H3.
unfold lift_flat_map in IHl.
unfold oncoll_map_concat in *.
unfold omap_concat in *.
simpl in *.
inversion H2.
dtype_inverter. subst.
unfold rec_concat_sort in *.
rewrite app_nil_l in *.
assert (rec_sort dl = dl).
+ clear a e.
rewrite sort_sorted_is_id.
reflexivity.
rewrite (same_domain_same_sorted rl dl).
reflexivity.
clear pf' H0 H2 H4 H1 rl_sub IHl pf.
assert (domain dl = domain rl).
apply (sorted_forall_same_domain); assumption.
auto.
assumption.
+ destruct (lift_map
(fun x : data =>
match x with
| dunit => None
| dnat _ => None
| dfloat _ => None
| dbool _ => None
| dstring _ => None
| dcoll _ => None
| drec r1 => Some (drec (rec_sort (nil ++ r1)))
| dleft _ => None
| dright _ => None
| dbrand _ _ => None
| dforeign _ => None
end) l); simpl in *; congruence.
Qed.
Lemma oproduct_empty_left τ pf l:
Forall (fun d : data => d ▹ Rec Closed τ pf) l ->
(oproduct (drec nil::nil) l) = Some l.
Proof.
intros.
induction l; simpl; unfold omap_product in *; simpl.
- reflexivity.
- inversion H; clear H; subst.
specialize (IHl H3); clear H3.
simpl in *.
unfold oproduct in *; simpl in *.
unfold omap_concat in *.
simpl in *.
inversion H2.
dtype_inverter. subst.
unfold rec_concat_sort in *.
rewrite app_nil_l in *.
assert (rec_sort dl = dl).
+ clear a e.
rewrite sort_sorted_is_id.
reflexivity.
rewrite (same_domain_same_sorted rl dl).
reflexivity.
clear pf' H0 H2 H4 H1 rl_sub IHl pf.
assert (domain dl = domain rl).
apply (sorted_forall_same_domain); assumption.
auto.
assumption.
+ destruct (lift_map
(fun x : data =>
match x with
| dunit => None
| dnat _ => None
| dfloat _ => None
| dbool _ => None
| dstring _ => None
| dcoll _ => None
| drec r1 => Some (drec (rec_sort (nil ++ r1)))
| dleft _ => None
| dright _ => None
| dbrand _ _ => None
| dforeign _ => None
end) l); simpl in *; congruence.
Qed.
End lift_map.
Section bagops.
Context {fdtyping:foreign_data_typing}.
Lemma forall_typed_bunion {τ} d1 d2:
Forall (fun d : data => data_type d τ) d1 ->
Forall (fun d : data => data_type d τ) d2 ->
Forall (fun d : data => data_type d τ) (bunion d1 d2).
Proof.
intros; rewrite Forall_forall in *.
induction d1.
simpl in *; intros.
apply H0; assumption.
simpl in *; intros.
elim H1; intros; clear H1.
apply (H x).
left; assumption.
assert (forall x : data, In x d1 -> data_type x τ).
intros.
apply (H x0).
right; assumption.
apply IHd1; assumption.
Qed.
Lemma bminus_in_remove (x a:data) (d1 d2:list data) :
In x (bminus d1 (remove_one a d2)) -> In x (bminus d1 d2).
Proof.
revert d2.
induction d1; simpl; intros.
- induction d2; simpl in *.
assumption.
revert H.
elim (EquivDec.equiv_dec a a0); unfold EquivDec.equiv_dec; intros.
rewrite <- a1.
right; assumption.
simpl in H.
elim H; intros; clear H.
left; assumption.
right; apply (IHd2 H0).
- specialize (IHd1 (remove_one a0 d2)).
apply IHd1.
rewrite remove_one_comm; assumption.
Qed.
Lemma forall_typed_bminus {τ} d1 d2:
Forall (fun d : data => data_type d τ) d1 ->
Forall (fun d : data => data_type d τ) d2 ->
Forall (fun d : data => data_type d τ) (bminus d1 d2).
Proof.
intros; rewrite Forall_forall in *.
induction d1.
simpl in *; intros.
apply H0; assumption.
simpl in *; intros.
assert (forall x : data, In x d1 -> data_type x τ).
intros.
apply (H x0).
right; assumption.
assert (In x (bminus d1 d2))
by (apply bminus_in_remove with (a:=a); assumption).
apply IHd1; assumption.
Qed.
Lemma forall_typed_bmin {τ} d1 d2:
Forall (fun d : data => data_type d τ) d1 ->
Forall (fun d : data => data_type d τ) d2 ->
Forall (fun d : data => data_type d τ) (bmin d1 d2).
Proof.
intros.
unfold bmin.
assert (Forall (fun d : data => data_type d τ) (bminus d2 d1)).
apply forall_typed_bminus; assumption.
apply forall_typed_bminus; assumption.
Qed.
Lemma forall_typed_bmax {τ} d1 d2:
Forall (fun d : data => data_type d τ) d1 ->
Forall (fun d : data => data_type d τ) d2 ->
Forall (fun d : data => data_type d τ) (bmax d1 d2).
Proof.
intros.
unfold bmax.
assert (Forall (fun d : data => data_type d τ) (bminus d1 d2)).
apply forall_typed_bminus; assumption.
apply forall_typed_bunion; assumption.
Qed.
Lemma rec_concat_with_drec_concat_well_typed dl dl0 τ₁ τ₂:
is_list_sorted ODT_lt_dec (domain τ₁) = true ->
is_list_sorted ODT_lt_dec (domain τ₂) = true ->
is_list_sorted ODT_lt_dec (domain (rec_concat_sort τ₁ τ₂)) = true ->
Forall2
(fun (d : string * data) (r : string * rtype) =>
fst d = fst r /\ data_type (snd d) (snd r)) dl τ₁ ->
Forall2
(fun (d : string * data) (r : string * rtype) =>
fst d = fst r /\ data_type (snd d) (snd r)) dl0 τ₂ ->
Forall2
(fun (d : string * data) (r : string * rtype) =>
fst d = fst r /\ data_type (snd d) (snd r)) (rec_sort (dl ++ dl0))
(rec_concat_sort τ₁ τ₂).
Proof.
intros pf1 pf2 pf3 H H0.
assert (domain dl = domain τ₁)
by (apply (sorted_forall_same_domain); assumption).
assert (domain dl0 = domain τ₂)
by (apply (sorted_forall_same_domain); assumption).
assert (rec_sort dl = dl)
by (apply sort_sorted_is_id; rewrite H1; assumption).
assert (rec_sort dl0 = dl0)
by (apply sort_sorted_is_id; rewrite H2; assumption).
assert (rec_sort τ₂ = τ₂)
by (apply sort_sorted_is_id; assumption).
assert (rec_sort τ₁ = τ₁)
by (apply sort_sorted_is_id; assumption).
unfold rec_concat_sort.
induction H; simpl in *.
rewrite H4; rewrite H5.
assumption.
assert (is_list_sorted ODT_lt_dec (domain l') = true).
revert pf1.
destruct l'.
reflexivity.
simpl.
destruct (StringOrder.lt_dec (fst y) (fst p)); congruence.
assert (is_list_sorted ODT_lt_dec
(domain (rec_sort (l' ++ τ₂))) = true)
by (apply (@rec_sort_sorted string ODT_string) with (l1 := l' ++ τ₂); reflexivity).
specialize (IHForall2 H8 H9).
inversion H1.
specialize (IHForall2 H12).
assert (is_list_sorted ODT_lt_dec (domain l') = true).
revert pf1.
destruct l'; try reflexivity; simpl.
destruct (StringOrder.lt_dec (fst y) (fst p)); congruence.
assert (is_list_sorted ODT_lt_dec (domain l') = true)
by (apply (@rec_sorted_skip_first string ODT_string _ l' y); assumption).
assert (rec_sort l' = l')
by (apply rec_sorted_id; assumption).
assert (is_list_sorted ODT_lt_dec (domain l) = true)
by (apply (sorted_forall_sorted l l'); assumption).
assert (rec_sort l = l)
by (apply rec_sorted_id; assumption).
specialize (IHForall2 H16 H14).
clear H4 H5 H12 H10 H13 H14 H15 H16.
elim H; intros; clear H H4.
clear pf1 pf2.
assert (is_list_sorted
ODT_lt_dec
(domain
(insertion_sort_insert rec_field_lt_dec x (rec_sort (l ++ dl0)))) =
true).
apply (insert_and_foralls_mean_same_sort l dl0 l' τ₂ x y); assumption.
apply Forall2_cons_sorted; assumption.
Qed.
Lemma concat_well_typed {τ₁ τ₂ τ₃} d1 d2 pf1 pf2 pf3:
rec_concat_sort τ₁ τ₂ = τ₃ ->
data_type d1 (Rec Closed τ₁ pf1) ->
data_type d2 (Rec Closed τ₂ pf2) ->
exists dl dl0 d3,
d1 = drec dl /\
d2 = drec dl0 /\
((rec_sort (dl ++ dl0)) = d3) /\
data_type (drec d3) (Rec Closed τ₃ pf3).
Proof.
intros.
destruct (data_type_Rec_inv H0); subst.
destruct (data_type_Rec_inv H1); subst.
apply dtrec_closed_inv in H0.
apply dtrec_closed_inv in H1.
do 3 eexists; do 3 (split; try reflexivity).
apply dtrec_full.
apply rec_concat_with_drec_concat_well_typed; assumption.
Qed.
Lemma forall_typed_bdistinct {τ} d1:
Forall (fun d : data => data_type d τ) d1 ->
Forall (fun d : data => data_type d τ) (bdistinct d1).
Proof.
intros; rewrite Forall_forall in *.
intros.
induction d1.
simpl in *.
contradiction.
simpl in *.
assert (forall x : data, In x d1 -> data_type x τ)
by (apply (forall_in_weaken (fun x => a = x)); assumption).
destruct (mult (bdistinct d1) a).
elim H0; intros; clear H0.
rewrite <- H2 in *.
apply (H a).
left; reflexivity.
specialize (IHd1 H1 H2); assumption.
specialize (IHd1 H1 H0); assumption.
Qed.
Lemma rremove_well_typed τ s dl:
Forall2
(fun (d : string * data) (r : string * rtype) =>
fst d = fst r /\ data_type (snd d) (snd r)) dl τ ->
Forall2
(fun (d : string * data) (r : string * rtype) =>
fst d = fst r /\ data_type (snd d) (snd r)) (rremove dl s)
(rremove τ s).
Proof.
intros F2.
induction F2; simpl; trivial.
destruct H; simpl in *.
rewrite H.
match_destr.
auto.
Qed.
Lemma rproject_well_typed τ rl s dl:
Forall2
(fun (d : string * data) (r : string * rtype) =>
fst d = fst r /\ data_type (snd d) (snd r)) dl rl ->
sublist s (domain τ) ->
sublist τ rl ->
is_list_sorted ODT_lt_dec (domain τ) = true ->
is_list_sorted ODT_lt_dec (domain rl) = true ->
Forall2
(fun (d : string * data) (r : string * rtype) =>
fst d = fst r /\ data_type (snd d) (snd r)) (rproject dl s)
(rproject τ s).
Proof.
intros.
assert (sublist s (domain rl)) by
(apply (sublist_trans s (domain τ) (domain rl)); try assumption;
apply sublist_domain; assumption).
assert (NoDup (domain rl))
by (apply is_list_sorted_NoDup_strlt; assumption).
rewrite (rproject_sublist τ rl s H2 H3); try assumption.
clear H0 H1 H4 H2.
induction H.
- apply Forall2_nil.
- inversion H5; subst.
assert (is_list_sorted ODT_lt_dec (domain l') = true)
by (apply (@rec_sorted_skip_first string ODT_string _ l' y); assumption).
specialize (IHForall2 H1 H6).
elim H; intros.
simpl; rewrite H2.
destruct (in_dec string_dec (fst y) s).
apply Forall2_cons; try assumption; split; assumption.
assumption.
Qed.
End bagops.
End TUtil.
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9434_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// adc interface
input adc_clk;
input adc_rst;
input [47:0] adc_data;
input adc_or;
// channel interface
output [63:0] adc_dfmt_data;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire adc_pn_type_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// instantiations
axi_ad9434_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_type (adc_pn_type_s));
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*12+11:n*12]),
.valid_out (),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_pn_type (adc_pn_type_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
`include "def.v"
module Controller(clk, reset,
memdata, memaddr, ireg_d0_lsb,
instr0, instr1, current_state,
cr, pc,
pc_update_req, pc_update_addr);
//
input clk, reset;
input [31:0] memdata;
input ireg_d0_lsb;
input pc_update_req;
input [15:0] pc_update_addr;
output reg [15:0] memaddr;
output reg [31:0] instr0 = 0;
output reg [31:0] instr1 = 0;
output reg [3:0] current_state = 0;
output reg [7:0] cr = 0;
output reg [15:0] pc = 0;
//
reg [15:0] pc_next;
wire [ 7:0] cr_next;
reg [ 3:0] next_state;
always begin
case (current_state)
`STATE_FETCH0_0, `STATE_FETCH1_0: pc_next = pc + 1;
`STATE_EXEC_0: begin
if(pc_update_req) pc_next = pc_update_addr;
else pc_next = pc;
end
default: pc_next = pc;
endcase
#1;
end
//
wire [7:0] instr0_op;
wire [7:0] next_instr0_op;
assign instr0_op = instr0[31:24];
assign next_instr0_op = memdata[31:24];
//
reg cr_next_hlt;
reg cr_next_skip;
assign cr_next = {6'b0, cr_next_skip, cr_next_hlt};
always begin
// HLT bit
if(current_state == `STATE_EXEC_1 && instr0_op == `OP_HLT) begin
cr_next_hlt = 1;
end
else cr_next_hlt = cr[`BIT_CR_HLT];
// SKIP bit
case (current_state)
`STATE_FETCH0_1: begin
case(next_instr0_op)
`OP_LIMM32, `OP_LBSET: begin
cr_next_skip = cr[`BIT_CR_SKIP];
end
default: cr_next_skip = 0;
endcase
end
`STATE_FETCH1_1: begin
cr_next_skip = 0;
end
`STATE_EXEC_0: begin
cr_next_skip = 0;
end
`STATE_EXEC_1: begin
if(instr0_op == `OP_CND && ireg_d0_lsb == 0) begin
cr_next_skip = 1;
end
else cr_next_skip = 0;
end
default: cr_next_skip = cr[`BIT_CR_SKIP];
endcase #1;
end
//
always begin
case (current_state)
`STATE_FETCH0_0, `STATE_FETCH0_1: memaddr <= pc;
`STATE_FETCH1_0, `STATE_FETCH1_1: memaddr <= pc;
default: memaddr <= 0;
endcase
#1;
end
always @(negedge clk) begin
if(reset == 0 && cr[`BIT_CR_HLT] == 0) begin
if(current_state == `STATE_FETCH0_1) begin
instr0 <= memdata;
end
if(current_state == `STATE_FETCH1_1) begin
instr1 <= memdata;
end
end
end
always @(posedge clk) begin
if(reset == 1) begin
pc = 0;
current_state = `STATE_FETCH0_0;
cr = 0;
end
if(reset == 0 && cr[`BIT_CR_HLT] == 0) begin
current_state <= next_state;
pc <= pc_next;
cr <= cr_next;
end
end
// state transition
always begin
#1;
case (current_state)
`STATE_FETCH0_0:
next_state = `STATE_FETCH0_1;
`STATE_FETCH0_1: begin
case(next_instr0_op)
`OP_LIMM32, `OP_LBSET: begin
next_state = `STATE_FETCH1_0;
end
default: begin
if(cr[`BIT_CR_SKIP])
next_state = `STATE_FETCH0_0;
else
next_state = `STATE_EXEC_0;
end
endcase
end
`STATE_FETCH1_0:
next_state = `STATE_FETCH1_1;
`STATE_FETCH1_1: begin
if(cr[`BIT_CR_SKIP])
next_state = `STATE_FETCH0_0;
else
next_state = `STATE_EXEC_0;
end
`STATE_EXEC_0: begin
next_state = `STATE_EXEC_1;
end
`STATE_EXEC_1: begin
next_state = `STATE_STORE_0;
end
`STATE_STORE_0: begin
next_state = `STATE_STORE_1;
end
`STATE_STORE_1: begin
next_state = `STATE_FETCH0_0;
end
default: next_state = `STATE_HLT;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_nsr.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 SET = 1'b0;
#80 D = 1'b1;
#100 RESET = 1'b1;
#120 SET = 1'b1;
#140 D = 1'b0;
#160 RESET = 1'b0;
#180 SET = 1'b0;
#200 SET = 1'b1;
#220 RESET = 1'b1;
#240 D = 1'b1;
#260 SET = 1'bx;
#280 RESET = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ls__udp_dff$NSR dut (.SET(SET), .RESET(RESET), .D(D), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_TB_V
|
//Defines the top level CPU module
//This CPu is pipelined and has the following pipeline stages:
// 0. Fetch -- Instruction is read from the RAM buffer unless the CPU is executing a multi-cycle instruction.
// In that case, the next op will be 0.
// 1. Data dependency resolve -- All data is copied the appropriate shifter.
// 2. Execute
// 3. Writeback
// 4. (empty stage, used for various memory operations)
//
// As a bit of cover for the quality of this CPU core:
// "Software people design hardware as hardware people write software"
// Take that as you will.
module cpu(
CLK,
MEMD,
MEMRDY,
addr,
memDat,
memWrite
);
input CLK;
input [15:0] MEMD;
input MEMRDY;
output [31:0] addr;
output [15:0] memDat;
output memWrite;
reg halt;
wire clk;
assign clk=CLK&&~halt;
reg [15:0] memOut;
assign memDat=memOut;
reg memW;
assign memWrite=memW;
//This is the operation shifter that will allow the CPU to complete its tasks:
reg [15:0] opShifter[4:0]; //Five stages should be enough for anybody.
wire [6:0] op1;
wire [6:0] op2;
wire [6:0] op3;
wire [6:0] op4;
wire [6:0] op5;
wire [2:0] aSel2;
wire [2:0] aSel3;
wire [2:0] aSel4;
wire [2:0] bSel2;
wire [2:0] bSel3;
wire [2:0] bSel4;
wire [2:0] cSel2;
wire [2:0] cSel3;
wire [2:0] cSel4;
wire [14:0] literalValue;
pipeBreakU pbru(opShifter[0], opShifter[1], opShifter[2], opShifter[3], opShifter[4], op1, op2, op3, op4, op5, aSel2, aSel3, aSel4, bSel2, bSel3, bSel4, cSel2, cSel3, cSel4, literalValue);
reg [14:0] literalValueIntermediary;
wire [4:0] aluOp;
aluOpU aou(op1, op2, op3, op4, op5, aluOp);
reg [7:0] procFlags; //This generates the set of flags used by the processor.
//Declare the CPU's register file:
reg [15:0] registers[7:0]; //Registers are addressed with 3-bit literals.
//Define some wires so that we can keep track of each register:
wire [15:0] r0;
assign r0=registers[0];
wire [15:0] r1;
assign r1=registers[1];
wire [15:0] r2;
assign r2=registers[2];
wire [15:0] r3;
assign r3=registers[3];
wire [15:0] r4;
assign r4=registers[4];
wire [15:0] r5;
assign r5=registers[5];
wire [15:0] r6;
assign r6=registers[6];
wire [15:0] r7;
assign r7=registers[7];
reg [15:0] aShifter[0:3]; //Make it one shorter than the overall op register.
reg [15:0] bShifter[0:3];
//Again, some debugging values:
wire [15:0] as3;
assign as3=aShifter[3];
wire [15:0] as2;
assign as2=aShifter[2];
wire [15:0] as1;
assign as1=aShifter[1];
wire [15:0] as0;
assign as0=aShifter[0];
wire [15:0] bs3;
assign bs3=bShifter[3];
wire [15:0] bs2;
assign bs2=bShifter[2];
wire [15:0] bs1;
assign bs1=bShifter[1];
wire [15:0] bs0;
assign bs0=bShifter[0];
reg [31:0] abCombined;
//Ensure that the computer can actually compute:
wire [7:0] flagsOut; //This is mostly unused.
reg [7:0] flags;
wire [15:0] aluOut;
wire aluShouldWriteBack;
ALU alu(op3[3:0], procFlags, aShifter[0], bShifter[0], flagsOut, aluOut, aluShouldWriteBack);
reg [15:0] intermediateResult;
//Make some wires to break the contents of the flags register out:
wire z, c, o, n;
assign z=flags[0];
assign c=flags[1];
assign o=flags[2];
assign n=flags[3];
//Declare a comparator for the cmp instruction, since manipulating the ALU would be a spot difficult.
wire greater, less, same;
reg g, l, s;
comparator cmp(aShifter[0], bShifter[0], greater, less, same);
//Declare the CPU's program counter:
reg [31:0] pCtr;
//Declare the CPU's stack pointer:
reg [31:0] stackPointer;
//wire [15:0] memOutMux [1:0];
reg [1:0] addrMuxSelector;
wire [31:0] addrMux[2:0];
assign addrMux[0]=pCtr;
assign addrMux[1]=stackPointer;
assign addrMux[2]=abCombined;
assign addr=addrMux[addrMuxSelector];
//This wire blocks the pipeline from attempting to issue more instructions.
wire pipeBlocked;
pipeBlockedU pbu(opShifter[0], opShifter[1], opShifter[2], opShifter[3], opShifter[4], pipeBlocked);
reg [31:0] shadowPc; //Used during calls and rets to keep the registers coherent.
//Set aside a direct path internally so that data stays up to date:
wire [15:0] aDataMux[4:0];
assign aDataMux[0]=registers[aSel2];
assign aDataMux[1]=aluOut;
assign aDataMux[2]=literalValueIntermediary;
assign aDataMux[3]=stackPointer[15:0];
assign aDataMux[4][7:0]=flags;
assign aDataMux[4][15:8]=0;
reg [31:0] instructionsFetched; //This is a performance/debugging variable only.
always@(posedge clk) begin
if(op1==44) begin
$display("Call instruction at %d", $time);
end
if(op2!=0) begin
instructionsFetched<=instructionsFetched+1;
end
//Shift all of the ops down the pipe:
if(pipeBlocked) begin
opShifter[0]<=0; //Issue a NOP if the pipe's blocked.
end
else begin
opShifter[0]<=MEMD; //Else try to use the current bit of memory information.
pCtr<=pCtr+1;
end
//Ensure that the rest of the pipeline is up to date:
opShifter[1]<=opShifter[0];
opShifter[2]<=opShifter[1];
opShifter[3]<=opShifter[2];
opShifter[4]<=opShifter[3];
if(op3>63&&aSel2==7) begin //Data bypass for LDL; ||op4>63)
aShifter[0]<=aDataMux[2];
end
else if(op3==40&&cSel3==aSel2) begin
aShifter[0]<=aDataMux[3];
end
else if(op3==63&&cSel3==aSel2) begin
aShifter[0]<=aDataMux[4];
end
else if(cSel3==aSel2&&(op3>0&&op3<11)) begin //For int ops.
aShifter[0]<=aDataMux[1];
end
else if(cSel4==aSel2&&(op4>0&&op4<11)) begin //For int ops.
aShifter[0]<=intermediateResult;
end
else if((op4>63) && (aSel2==7)) begin
aShifter[0]<=aDataMux[2];
end
else begin
aShifter[0]<=registers[aSel2];//aDataMux[0];
end
aShifter[1]<=aShifter[0];
aShifter[2]<=aShifter[1];
aShifter[3]<=aShifter[2];
if((op3>63)&&bSel2==7) begin //Data bypass for LDL
bShifter[0]<=aDataMux[2];
end
else if(op3==40&&cSel3==bSel2) begin
bShifter[0]<=aDataMux[3];
end
else if(op3==63&&cSel3==bSel2) begin
bShifter[0]<=aDataMux[4];
end
//TODO: Ensure coherence for LDFLGS instruction.
else if(cSel3==bSel2&&(op3>0&&op3<11)) begin //For int ops.
bShifter[0]<=aDataMux[1];
end
else if(cSel4==bSel2&&(op4>0&&op4<11)) begin //For int ops, since the registers are not yet coherent.
bShifter[0]<=intermediateResult;
end
else if((op4>63) && (bSel2==7)) begin
bShifter[0]<=aDataMux[2];
end
else begin
bShifter[0]<=registers[bSel2];
end
bShifter[1]<=bShifter[0];
bShifter[2]<=bShifter[1];
bShifter[3]<=bShifter[2];
//Handle the writeback stage for normal ops.
//Everything else is handled for me along the normal integer pipeline.
if(op4<11 && op4>0) begin
registers[cSel4]<=intermediateResult;//aluOut;
flags<=flagsOut;
end
if(op3<11 && op3>0) begin
intermediateResult<=aluOut;
//registers[cSel4]<=aluOut;
//flags<=flagsOut;
end
//Handle non-normal operations:
//BEGIN 2ND PIPELINE STAGE LOGIC
if(op2>63) begin //Get the LDL instruction out of the way:
literalValueIntermediary<=literalValue;
end
else if(op2==40) begin //Store stack register
end
else if(op2==41) begin //Load stack register. Loads the stack register from A and B.
//abCombined[31:16]<=aShifter[0];//registers[aSel2];
//abCombined[15:0]<=bShifter[0];//[bSel2];
end
else if(op2==42) begin //Push.
addrMuxSelector<=1;
stackPointer<=stackPointer-1;
//memOut<=aShifter[1];//registers[aSel2];
end
else if(op2==43) begin //Pop
addrMuxSelector<=1;
//stackPointer<=stackPointer+1;
end
else if(op2==44) begin //Call
addrMuxSelector<=1;
//stackPointer<=stackPointer-1;
//pCtr<=pCtr+1; // So that ret doesn't recurse! NOTE: This is unncecessary due to the instruction's timing.
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
end
else if(op2==45) begin //Ret. AAAAUGH!
addrMuxSelector<=1;
//stackPointer<=stackPointer+1;
end
else if(op2==50) begin //CMP.
end
else if(op2>=51&&op2<=54) begin //Jmp instrs.
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
end
else if(op2==60) begin //Load
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
addrMuxSelector<=2;
end
else if(op2==61) begin //Store
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
addrMuxSelector<=2;
memOut<=registers[cSel2];//registers[cSel2];
end
else if(op2==62) begin //Loads flags from the lower 8 bits of register A.
end
else if(op2==63) begin //Stores flags to the lower 8 bits of register A.
end
//BEGIN 3RD PIPELINE STAGE LOGIC
if(op3>63) begin //Execute stage of the LDL instruction. Do nothing! Woo!
//registers[7][14:0]<=literalValueIntermediary;
//registers[7][15]<=0;
end
else if(op3==40) begin //Store stack register
end
else if(op3==41) begin //Load stack register. Loads the stack register from A and B.
end
else if(op3==42) begin //Push.
memW<=1;
memOut<=aShifter[0];
end
else if(op3==43) begin //pop
registers[cSel3]<=MEMD;
end
else if(op3==44) begin //Call
memOut<=pCtr[31:16];
memW<=1;
stackPointer<=stackPointer-1;
end
else if(op3==45) begin //Ret. AAAAUGH!
pCtr[15:0]<=MEMD;
stackPointer<=stackPointer+1;
end
else if(op3==50) begin //CMP.
g<=greater;
l<=less;
s<=same;
end
else if(op3>=51&&op3<=54) begin //Jmp instrs.
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
end
//else if(op3==52) begin //Jump on equal.
//
//end
else if(op3==60) begin //Load
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
addrMuxSelector<=2;
end
else if(op3==61) begin //Store
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
addrMuxSelector<=2;
if(op4>63&&cSel3==7) begin
memOut[14:0]<=literalValueIntermediary;
memOut[15]<=0;
end
else if(cSel4==cSel3) begin //Then it is most likely the product of an ALU action.
if(op4>0&&op4<11) begin
memOut<=intermediateResult;
end
else if(op4==41) begin
memOut<=stackPointer[15:0];
end
else begin //Hope for the best:
memOut<=registers[cSel3];
end
end
else begin
memOut<=registers[cSel3];
end
memW<=1;
end
else if(op3==62) begin //Load flags.
end
else if(op3==63) begin //Stores flags to the lower 8 bits of register A.
end
// BEGIN 4TH PIPELINE STAGE LOGIC
if(op4>63) begin //Writeback stage of the LDL instruction. Lovely!
registers[7][14:0]<=literalValueIntermediary;
registers[7][15]<=1'b0;
end
else if(op4==40) begin //Store stack register
registers[cSel4]<=stackPointer[15:0];
end
else if(op4==41) begin //Load stack register. Loads the stack register from A and B.
stackPointer[31:16]<=aShifter[1];
stackPointer[15:0]<=bShifter[1];
//stackPointer<=abCombined;
end
else if(op4==42) begin //Push
memW<=0;
//stackPointer<=stackPointer-1;
addrMuxSelector<=0;
end
else if(op4==43) begin //Pop
//registers[cSel4]<=MEMD;
stackPointer<=stackPointer+1;
addrMuxSelector<=0;
end
else if(op4==44) begin //Call
memOut<=pCtr[15:0];
stackPointer<=stackPointer-1;
shadowPc[31:16]<=registers[aSel4];
shadowPc[15:0]<=registers[bSel4];
end
else if(op4==45) begin //Ret. AAAAUGH!
pCtr[31:16]<=MEMD;
stackPointer<=stackPointer+1;
end
else if(op4==50) begin //CMP.
flags[7]<=g; //This sort of writeback allows for better debugging.
flags[6]<=l;
flags[5]<=s;
end
else if(op4==59) begin //Halt. Should I even bother?
halt<=1;
end
else if(op4==60) begin //Load
registers[cSel4]<=MEMD;
addrMuxSelector<=0;
end
else if(op4==51) begin //Jmp
//pCtr[31:16]<=//aShifter[2];
//pCtr[15:0]<=//bShifter[2];
pCtr<=abCombined;
end
else if(op4==52) begin //JE
if(s) begin
//pCtr[31:16]<=aShifter[2];//registers[aSel4];//aShifter[1];
//pCtr[15:0]<=bShifter[2];//registers[bSel4];//bShifter[1];
pCtr<=abCombined;
end
end
else if(op4==53) begin //Jump on positive (greater)
if(g) begin
pCtr[31:16]<=aShifter[2];//registers[aSel4];//aShifter[1];
pCtr[15:0]<=bShifter[2];//registers[bSel4];//bShifter[1];
end
end
else if(op4==54) begin //Jump on negative (less)
if(n) begin
pCtr[31:16]<=registers[aSel4];//aShifter[1];
pCtr[15:0]<=registers[bSel4];//bShifter[1];
end
end
else if(op4==61) begin //Store
memW<=0;
addrMuxSelector<=0;
end
else if(op4==62) begin //Load flags.
flags<=aShifter[2][7:0];
end
else if(op4==63) begin //Store flags.
registers[cSel4][7:0]<=flags;
end
// BEGIN 5TH PIPELINE STAGE LOGIC
if(op5==44) begin //Call
//pCtr[31:16]<=registers[cSel4];//Complete the jump
//pCtr[15:0]<=bShifter[2];
pCtr<=shadowPc;
memW<=0; //Stop writing to memory.
addrMuxSelector<=0; //Use the program counter for addressing.
//stackPointer<=stackPointer-1; //3 shifts prevents push from destroying the address.
end
else if(op5==45) begin //Ret. AAAAUGH!
addrMuxSelector<=0;
end
//Jmp placeholder.
end
initial begin
addrMuxSelector<=0;
abCombined<=0;
halt<=0;
pCtr<=0;
stackPointer<=0;
//Assign registers to 0:
registers[0]<=0;
registers[1]<=0;
registers[2]<=0;
registers[3]<=0;
registers[4]<=0;
registers[5]<=0;
registers[6]<=0;
registers[7]<=0;
memW<=0;
opShifter[0]<=0;
opShifter[1]<=0;
opShifter[2]<=0;
opShifter[3]<=0;
opShifter[4]<=0;
instructionsFetched<=0;
end
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-12-2018
*/
// Wrapper to output only combined channels. Defaults to YM2612 mode.
module jt12 (
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, if not needed leave as 1'b1
input [7:0] din,
input [1:0] addr,
input cs_n,
input wr_n,
output [7:0] dout,
output irq_n,
// configuration
input en_hifi_pcm,
// combined output
output signed [15:0] snd_right,
output signed [15:0] snd_left,
output snd_sample
);
// Default parameters for JT12 select a YM2612
jt12_top u_jt12(
.rst ( rst ), // rst should be at least 6 clk&cen cycles long
.clk ( clk ), // CPU clock
.cen ( cen ), // optional clock enable, it not needed leave as 1'b1
.din ( din ),
.addr ( addr ),
.cs_n ( cs_n ),
.wr_n ( wr_n ),
.dout ( dout ),
.irq_n ( irq_n ),
// configuration
.en_hifi_pcm ( en_hifi_pcm ),
// Unused ADPCM pins
.adpcma_addr ( ), // real hardware has 10 pins multiplexed through RMPX pin
.adpcma_bank ( ),
.adpcma_roe_n ( ), // ADPCM-A ROM output enable
.adpcma_data ( 8'd0 ), // Data from RAM
.adpcmb_addr ( ), // real hardware has 12 pins multiplexed through PMPX pin
.adpcmb_roe_n ( ), // ADPCM-B ROM output enable
// Separated output
.psg_A (),
.psg_B (),
.psg_C (),
.fm_snd_left (),
.fm_snd_right (),
// Unused YM2203
.IOA_in (),
.IOB_in (),
// combined output
.psg_snd (),
.snd_right ( snd_right ), // FM+PSG
.snd_left ( snd_left ), // FM+PSG
.snd_sample ( snd_sample ),
.debug_view ( )
);
endmodule // jt03
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* XY routing
*
* Routing Function
* ================
*
* Simple XY routing
* - Function updates flit with the output port required at next router
* and modifies displacement fields as head flit gets closer to
* destination.
*
* More complex routing algorithms may be implemented by making edits here
* and to the flit's control field defn.
*
* Valid Turn?
* ===========
*
* LAG_route_valid_turn(from, to)
*
* This function is associated with the routing algorithm and is used to
* optimize the synthesis of the implementation by indicating impossible
* turns - hence superfluous logic.
*
* Valid Input PL
* ==============
*
* Does a particular input PL exist. e.g. Tile input port may only contain
* one PL buffer.
*
*/
function automatic bit LAG_route_valid_input_pl;
input integer port;
input integer pl;
`include "parameters.v"
bit valid;
begin
valid=1'b1;
// if ((port==`TILE)&&(pl!=0)) valid=1'b0;
if (port==`TILE) begin
if (pl>=router_num_pls_on_entry) valid=1'b0;
end
LAG_route_valid_input_pl=valid;
end
endfunction
function automatic bit LAG_route_valid_turn;
input output_port_t from;
input output_port_t to;
bit valid;
begin
valid=1'b1;
// flits don't leave on the same port as they entered
if (from==to) valid=1'b0;
`ifdef OPT_MESHXYTURNS
// Optimise turns for XY routing in a mesh
if (((from==`NORTH)||(from==`SOUTH))&&((to==`EAST)||(to==`WEST))) valid=1'b0;
`endif
LAG_route_valid_turn=valid;
end
endfunction
module LAG_route (flit_in, flit_out, clk, rst_n);
input flit_t flit_in;
output flit_t flit_out;
input clk, rst_n;
function flit_t next_route;
input flit_t flit_in;
logic [4:0] route;
flit_t new_flit;
x_displ_t x_disp;
y_displ_t y_disp;
begin
new_flit = flit_in;
x_disp = x_displ_t ' (flit_in.data[router_radix + `X_ADDR_BITS : router_radix]);
y_disp = y_displ_t ' (flit_in.data[router_radix + `X_ADDR_BITS + `Y_ADDR_BITS + 1 : router_radix + `X_ADDR_BITS + 1]);
// Simple XY Routing
if (x_disp!=0) begin
if (x_disp>0) begin
route = `port5id_east;
x_disp--;
end else begin
route = `port5id_west;
x_disp++;
end
end else begin
if (y_disp==0) begin
route=`port5id_tile;
end else if (y_disp>0) begin
route=`port5id_south;
y_disp--;
end else begin
route=`port5id_north;
y_disp++;
end
end
new_flit.data[router_radix - 1 : 0] = route;
new_flit.data[router_radix + `X_ADDR_BITS : router_radix] = x_displ_t ' (x_disp);
new_flit.data[router_radix + `X_ADDR_BITS + `Y_ADDR_BITS + 1 : router_radix + `X_ADDR_BITS + 1] = y_displ_t ' (y_disp);
next_route = new_flit;
end
endfunction // flit_t
assign flit_out=next_route(flit_in);
endmodule // route
|
// testbench for the freecell player.
// This simple testbench presents one move to the freecell player at each
// clock cycle. The task "doMove" allows the user to specify the moves in
// standard notation.
//
// Each move consists of two characters: the first designates the source;
// the second designates the destination.
//
module testFreeCell;
reg [3:0] source;
reg [3:0] dest;
reg clock;
wire win;
// Convert the character notation into bit-level codes.
function [3:0] encode;
input [7:0] selector;
begin: dec
case (selector)
"1": encode = 4'd0; // column 1 of the tableau
"2": encode = 4'd1; // column 2 of the tableau
"3": encode = 4'd2; // column 3 of the tableau
"4": encode = 4'd3; // column 4 of the tableau
"5": encode = 4'd4; // column 5 of the tableau
"6": encode = 4'd5; // column 6 of the tableau
"7": encode = 4'd6; // column 7 of the tableau
"8": encode = 4'd7; // column 8 of the tableau
"a": encode = 4'd8; // free cell a
"b": encode = 4'd9; // free cell b
"c": encode = 4'd10; // free cell c
"d": encode = 4'd11; // free cell d
"h": encode = 4'd12; // home cells: the two LSBs are arbitrary
default: encode = 4'bx;
endcase // case (selector)
end // block: dec
endfunction // encode
// Present one move to the circuit and wait one clock cycle.
task doMove;
input [15:0] move;
begin: doTheMove
source = encode(move[15:8]);
dest = encode(move[7:0]);
#10;
end // block: doTheMove
endtask // doMove
// Play the game. Several illegal moves are interspersed with the
// legal ones.
initial begin
$monitor("%d %b %b %d %b",$time, source, dest, fc.mtype, win);
clock = 0;
doMove("1h"); // 1
doMove("1h"); // 2
doMove("2h"); // 3
doMove("3h"); // 4
doMove("4a"); // 5
doMove("47"); // 6
doMove("a7"); // 7
doMove("85"); // 8
doMove("45"); // 9
doMove("4a"); // 10
doMove("42"); // 11
doMove("4h"); // 12
doMove("6h"); // 13
doMove("4b"); // 14
doMove("2c"); // 15
doMove("24"); // 16
doMove("c4"); // 17
doMove("a2"); // 18
doMove("b2"); // 19
doMove("6h"); // 20
doMove("87"); // 21
doMove("86"); // 22
doMove("8a"); // 23
doMove("2h"); // 24
doMove("82"); // 25
doMove("a8"); // 26
doMove("5a"); // 27
doMove("5b"); // 28
doMove("58"); // 29
doMove("1h"); // 30
doMove("5h"); // 31
doMove("b8"); // 32
doMove("a8"); // 33
doMove("18"); // 34
doMove("12"); // illegal
doMove("2a"); // 35
doMove("28"); // 36
doMove("a8"); // 37
doMove("1a"); // 38
doMove("14"); // 39
doMove("1h"); // 40
doMove("3b"); // 41
doMove("3h"); // 42
doMove("37"); // 43
doMove("a1"); // 44
doMove("h4"); // illegal
doMove("31"); // 45
doMove("3a"); // 46
doMove("1c"); // 47
doMove("13"); // 48
doMove("c3"); // 49
doMove("2c"); // 50
doMove("8c"); // illegal
doMove("2d"); // 51
doMove("23"); // 52
doMove("24"); // 53
doMove("a3"); // 54
doMove("c3"); // 55
doMove("c2"); // illegal
doMove("2h"); // 56
doMove("6a"); // 57
doMove("64"); // 58
doMove("6h"); // 59
doMove("a4"); // 60
doMove("dh"); // 61
doMove("5h"); // 62
doMove("ah"); // illegal
doMove("62"); // 63
doMove("52"); // 64
doMove("52"); // 65
doMove("71"); // 66
doMove("74"); // 67
doMove("14"); // 68
doMove("64"); // 69
doMove("b6"); // 70
doMove("56"); // 71
doMove("7a"); // 72
doMove("7b"); // 73
doMove("72"); // 74
doMove("b2"); // 75
doMove("a2"); // 76
doMove("75"); // 77
doMove("72"); // 78
doMove("75"); // 79
doMove("7h"); // 80
doMove("7h"); // 81
doMove("8h"); // 82
doMove("8h"); // 83
doMove("4h"); // 84
doMove("4h"); // 85
doMove("3h"); // 86
doMove("4h"); // 87
doMove("8h"); // 88
doMove("2h"); // 89
doMove("3h"); // 90
doMove("4h"); // 91
doMove("3h"); // 92
doMove("3h"); // 93
doMove("8h"); // 94
doMove("2h"); // 95
doMove("8h"); // 96
doMove("4h"); // 97
doMove("2h"); // 98
doMove("8h"); // 99
doMove("2h"); // 100
doMove("3h"); // 101
doMove("4h"); // 102
doMove("8h"); // 103
doMove("2h"); // 104
doMove("3h"); // 105
doMove("4h"); // 106
doMove("8h"); // 107
doMove("2h"); // 108
doMove("4h"); // 109
doMove("8h"); // illegal
doMove("5h"); // 110
doMove("6h"); // 111
doMove("2h"); // 112
doMove("4h"); // 113
doMove("5h"); // 114
doMove("6h"); // 115
$finish;
end // initial begin
// Clock generator.
always
#5 clock = ~clock;
freecellPlayer fc(clock,source,dest,win);
endmodule // testFreeCell
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* IP arbitrated multiplexer
*/
module ip_arb_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* IP frame inputs
*/
input wire [S_COUNT-1:0] s_ip_hdr_valid,
output wire [S_COUNT-1:0] s_ip_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*4-1:0] s_ip_version,
input wire [S_COUNT*4-1:0] s_ip_ihl,
input wire [S_COUNT*6-1:0] s_ip_dscp,
input wire [S_COUNT*2-1:0] s_ip_ecn,
input wire [S_COUNT*16-1:0] s_ip_length,
input wire [S_COUNT*16-1:0] s_ip_identification,
input wire [S_COUNT*3-1:0] s_ip_flags,
input wire [S_COUNT*13-1:0] s_ip_fragment_offset,
input wire [S_COUNT*8-1:0] s_ip_ttl,
input wire [S_COUNT*8-1:0] s_ip_protocol,
input wire [S_COUNT*16-1:0] s_ip_header_checksum,
input wire [S_COUNT*32-1:0] s_ip_source_ip,
input wire [S_COUNT*32-1:0] s_ip_dest_ip,
input wire [S_COUNT*DATA_WIDTH-1:0] s_ip_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_ip_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_ip_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_ip_payload_axis_tready,
input wire [S_COUNT-1:0] s_ip_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_ip_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_ip_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_ip_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [DATA_WIDTH-1:0] m_ip_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_ip_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_ip_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_ip_payload_axis_tuser
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_ip_hdr_ready_reg = {S_COUNT{1'b0}}, s_ip_hdr_ready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg [3:0] m_ip_version_reg = 4'd0, m_ip_version_next;
reg [3:0] m_ip_ihl_reg = 4'd0, m_ip_ihl_next;
reg [5:0] m_ip_dscp_reg = 6'd0, m_ip_dscp_next;
reg [1:0] m_ip_ecn_reg = 2'd0, m_ip_ecn_next;
reg [15:0] m_ip_length_reg = 16'd0, m_ip_length_next;
reg [15:0] m_ip_identification_reg = 16'd0, m_ip_identification_next;
reg [2:0] m_ip_flags_reg = 3'd0, m_ip_flags_next;
reg [12:0] m_ip_fragment_offset_reg = 13'd0, m_ip_fragment_offset_next;
reg [7:0] m_ip_ttl_reg = 8'd0, m_ip_ttl_next;
reg [7:0] m_ip_protocol_reg = 8'd0, m_ip_protocol_next;
reg [15:0] m_ip_header_checksum_reg = 16'd0, m_ip_header_checksum_next;
reg [31:0] m_ip_source_ip_reg = 32'd0, m_ip_source_ip_next;
reg [31:0] m_ip_dest_ip_reg = 32'd0, m_ip_dest_ip_next;
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
// internal datapath
reg [DATA_WIDTH-1:0] m_ip_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_ip_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = (m_ip_payload_axis_tready_int_reg && grant_valid) << grant_encoded;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_ip_payload_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_ip_payload_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_ip_payload_axis_tvalid[grant_encoded];
wire current_s_tready = s_ip_payload_axis_tready[grant_encoded];
wire current_s_tlast = s_ip_payload_axis_tlast[grant_encoded];
wire [ID_WIDTH-1:0] current_s_tid = s_ip_payload_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_ip_payload_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_ip_payload_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
// arbiter instance
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = s_ip_hdr_valid & ~grant;
assign acknowledge = grant & s_ip_payload_axis_tvalid & s_ip_payload_axis_tready & s_ip_payload_axis_tlast;
always @* begin
frame_next = frame_reg;
s_ip_hdr_ready_next = {S_COUNT{1'b0}};
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
m_ip_version_next = m_ip_version_reg;
m_ip_ihl_next = m_ip_ihl_reg;
m_ip_dscp_next = m_ip_dscp_reg;
m_ip_ecn_next = m_ip_ecn_reg;
m_ip_length_next = m_ip_length_reg;
m_ip_identification_next = m_ip_identification_reg;
m_ip_flags_next = m_ip_flags_reg;
m_ip_fragment_offset_next = m_ip_fragment_offset_reg;
m_ip_ttl_next = m_ip_ttl_reg;
m_ip_protocol_next = m_ip_protocol_reg;
m_ip_header_checksum_next = m_ip_header_checksum_reg;
m_ip_source_ip_next = m_ip_source_ip_reg;
m_ip_dest_ip_next = m_ip_dest_ip_reg;
if (s_ip_payload_axis_tvalid[grant_encoded] && s_ip_payload_axis_tready[grant_encoded]) begin
// end of frame detection
if (s_ip_payload_axis_tlast[grant_encoded]) begin
frame_next = 1'b0;
end
end
if (!frame_reg && grant_valid && (m_ip_hdr_ready || !m_ip_hdr_valid)) begin
// start of frame
frame_next = 1'b1;
s_ip_hdr_ready_next = grant;
m_ip_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[grant_encoded*48 +: 48];
m_eth_type_next = s_eth_type[grant_encoded*16 +: 16];
m_ip_version_next = s_ip_version[grant_encoded*4 +: 4];
m_ip_ihl_next = s_ip_ihl[grant_encoded*4 +: 4];
m_ip_dscp_next = s_ip_dscp[grant_encoded*6 +: 6];
m_ip_ecn_next = s_ip_ecn[grant_encoded*2 +: 2];
m_ip_length_next = s_ip_length[grant_encoded*16 +: 16];
m_ip_identification_next = s_ip_identification[grant_encoded*16 +: 16];
m_ip_flags_next = s_ip_flags[grant_encoded*3 +: 3];
m_ip_fragment_offset_next = s_ip_fragment_offset[grant_encoded*13 +: 13];
m_ip_ttl_next = s_ip_ttl[grant_encoded*8 +: 8];
m_ip_protocol_next = s_ip_protocol[grant_encoded*8 +: 8];
m_ip_header_checksum_next = s_ip_header_checksum[grant_encoded*16 +: 16];
m_ip_source_ip_next = s_ip_source_ip[grant_encoded*32 +: 32];
m_ip_dest_ip_next = s_ip_dest_ip[grant_encoded*32 +: 32];
end
// pass through selected packet data
m_ip_payload_axis_tdata_int = current_s_tdata;
m_ip_payload_axis_tkeep_int = current_s_tkeep;
m_ip_payload_axis_tvalid_int = current_s_tvalid && m_ip_payload_axis_tready_int_reg && grant_valid;
m_ip_payload_axis_tlast_int = current_s_tlast;
m_ip_payload_axis_tid_int = current_s_tid;
m_ip_payload_axis_tdest_int = current_s_tdest;
m_ip_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
frame_reg <= frame_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
m_ip_version_reg <= m_ip_version_next;
m_ip_ihl_reg <= m_ip_ihl_next;
m_ip_dscp_reg <= m_ip_dscp_next;
m_ip_ecn_reg <= m_ip_ecn_next;
m_ip_length_reg <= m_ip_length_next;
m_ip_identification_reg <= m_ip_identification_next;
m_ip_flags_reg <= m_ip_flags_next;
m_ip_fragment_offset_reg <= m_ip_fragment_offset_next;
m_ip_ttl_reg <= m_ip_ttl_next;
m_ip_protocol_reg <= m_ip_protocol_next;
m_ip_header_checksum_reg <= m_ip_header_checksum_next;
m_ip_source_ip_reg <= m_ip_source_ip_next;
m_ip_dest_ip_reg <= m_ip_dest_ip_next;
if (rst) begin
frame_reg <= 1'b0;
s_ip_hdr_ready_reg <= {S_COUNT{1'b0}};
m_ip_hdr_valid_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_ip_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_ip_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_ip_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_ip_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_ip_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_ip_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_ip_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tkeep = KEEP_ENABLE ? m_ip_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tid = ID_ENABLE ? m_ip_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_ip_payload_axis_tdest = DEST_ENABLE ? m_ip_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_ip_payload_axis_tuser = USER_ENABLE ? m_ip_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tid_reg <= m_ip_payload_axis_tid_int;
m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tid_reg <= temp_m_ip_payload_axis_tid_reg;
m_ip_payload_axis_tdest_reg <= temp_m_ip_payload_axis_tdest_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tid_reg <= m_ip_payload_axis_tid_int;
temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's CPU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////
//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_cpu.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// Structure reordered and bugs fixed.
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_cpu(
// Clk & Rst
clk, rst,
// Insn interface
ic_en,
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
immu_en,
immu_sxe, immu_uxe,
// Debug unit
id_void, id_insn, ex_void,
ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
spr_dat_npc, rf_dataw, ex_flushpipe,
du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop,
du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
du_lsu_store_dat, du_lsu_load_dat,
abort_mvspr, abort_ex,
// Data interface
dc_en,
dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
sb_en, dmmu_en, dc_no_writethrough,
// SR Interface
boot_adr_sel_i,
// Interrupt & tick exceptions
sig_int, sig_tick,
// SPR interface
supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
parameter boot_adr = `OR1200_BOOT_ADR;
//
// I/O ports
//
//
// Clk & Rst
//
input clk;
input rst;
//
// Insn (IC) interface
//
output ic_en;
output [31:0] icpu_adr_o;
output icpu_cycstb_o;
output [3:0] icpu_sel_o;
output [3:0] icpu_tag_o;
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_rty_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Insn (IMMU) interface
//
output immu_en;
input immu_sxe;
input immu_uxe;
//
// Debug interface
//
output id_void;
output [31:0] id_insn;
output ex_void;
output [31:0] ex_insn;
output ex_freeze;
output [31:0] wb_insn;
output wb_freeze;
output [31:0] id_pc;
output [31:0] ex_pc;
output [31:0] wb_pc;
output ex_flushpipe;
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input du_stall;
input [dw-1:0] du_addr;
input [dw-1:0] du_dat_du;
input du_read;
input du_write;
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
input [24:0] du_dmr1;
input du_hwbkpt;
input du_hwbkpt_ls_r;
output [13:0] du_except_trig;
output [13:0] du_except_stop;
output [dw-1:0] du_dat_cpu;
output [dw-1:0] rf_dataw;
output [dw-1:0] du_lsu_store_dat;
output [dw-1:0] du_lsu_load_dat;
//
// Data (DC) interface
//
output [31:0] dcpu_adr_o;
output dcpu_cycstb_o;
output dcpu_we_o;
output [3:0] dcpu_sel_o;
output [3:0] dcpu_tag_o;
output [31:0] dcpu_dat_o;
input [31:0] dcpu_dat_i;
input dcpu_ack_i;
input dcpu_rty_i;
input dcpu_err_i;
input [3:0] dcpu_tag_i;
output dc_en;
output dc_no_writethrough;
//
// Data (DMMU) interface
//
output sb_en;
output dmmu_en;
output abort_ex;
output abort_mvspr;
//
// SR Interface
//
input boot_adr_sel_i;
//
// SPR interface
//
output supv;
input [dw-1:0] spr_dat_pic;
input [dw-1:0] spr_dat_tt;
input [dw-1:0] spr_dat_pm;
input [dw-1:0] spr_dat_dmmu;
input [dw-1:0] spr_dat_immu;
input [dw-1:0] spr_dat_du;
output [dw-1:0] spr_addr;
output [dw-1:0] spr_dat_cpu;
output [dw-1:0] spr_dat_npc;
output [31:0] spr_cs;
output spr_we;
input mtspr_dc_done;
//
// Interrupt exceptions
//
input sig_int;
input sig_tick;
//
// Internal wires
//
wire [31:0] if_insn;
wire saving_if_insn;
wire [31:0] if_pc;
wire [aw-1:0] rf_addrw;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrb;
wire rf_rda;
wire rf_rdb;
wire [dw-1:0] id_simm;
wire [dw-1:2] id_branch_addrtarget;
wire [dw-1:2] ex_branch_addrtarget;
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
wire [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
wire [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
wire genpc_freeze;
wire if_freeze;
wire id_freeze;
wire ex_freeze;
wire wb_freeze;
wire [`OR1200_SEL_WIDTH-1:0] sel_a;
wire [`OR1200_SEL_WIDTH-1:0] sel_b;
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
wire [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
wire [dw-1:0] rf_dataw;
wire [dw-1:0] rf_dataa;
wire [dw-1:0] rf_datab;
wire [dw-1:0] muxed_a;
wire [dw-1:0] muxed_b;
wire [dw-1:0] wb_forw;
wire wbforw_valid;
wire [dw-1:0] operand_a;
wire [dw-1:0] operand_b;
wire [dw-1:0] alu_dataout;
wire [dw-1:0] lsu_dataout;
wire [dw-1:0] sprs_dataout;
wire [dw-1:0] fpu_dataout;
wire fpu_done;
wire [31:0] ex_simm;
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
wire [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
wire [4:0] cust5_op;
wire [5:0] cust5_limm;
wire if_flushpipe;
wire id_flushpipe;
wire ex_flushpipe;
wire wb_flushpipe;
wire extend_flush;
wire ex_branch_taken;
wire flag;
wire flagforw;
wire flag_we;
wire flagforw_alu;
wire flag_we_alu;
wire flagforw_fpu;
wire flag_we_fpu;
wire carry;
wire cyforw;
wire cy_we_alu;
wire ovforw;
wire ov_we_alu;
wire ovforw_mult_mac;
wire ov_we_mult_mac;
wire cy_we_rf;
wire lsu_stall;
wire epcr_we;
wire eear_we;
wire esr_we;
wire sp_epcr_ghost_we;
wire sp_eear_ghost_we;
wire sp_esr_ghost_we;
wire pc_we;
wire [31:0] epcr;
wire [31:0] eear;
wire [`OR1200_SR_WIDTH-1:0] esr;
wire [31:0] sp_epcr_ghost;
wire [31:0] sp_eear_ghost;
wire [`OR1200_SR_WIDTH-1:0] sp_esr_ghost;
wire [`OR1200_FPCSR_WIDTH-1:0] fpcsr;
wire fpcsr_we;
wire sr_we;
wire [`OR1200_SR_WIDTH-1:0] to_sr;
wire [`OR1200_SR_WIDTH-1:0] sr;
wire except_flushpipe;
wire except_start;
wire except_started;
wire fpu_except_started;
wire [31:0] wb_insn;
wire sig_syscall;
wire sig_trap;
wire sig_range;
wire sig_fp;
wire [31:0] spr_dat_cfgr;
wire [31:0] spr_dat_rf;
wire [31:0] spr_dat_npc;
wire [31:0] spr_dat_ppc;
wire [31:0] spr_dat_mac;
wire [31:0] spr_dat_fpu;
wire mtspr_done;
wire force_dslot_fetch;
wire no_more_dslot;
wire ex_void;
wire ex_spr_read;
wire ex_spr_write;
wire if_stall;
wire id_macrc_op;
wire ex_macrc_op;
wire [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire [31:0] mult_mac_result;
wire mult_mac_stall;
wire [13:0] except_trig;
wire [13:0] except_stop;
wire genpc_refetch;
wire rfe;
wire lsu_unstall;
wire except_align;
wire except_dtlbmiss;
wire except_dmmufault;
wire except_illegal;
wire except_itlbmiss;
wire except_immufault;
wire except_ibuserr;
wire except_dbuserr;
wire abort_ex;
wire abort_mvspr;
wire gpr_written_to;
wire [4:0] gpr_written_addr;
wire [31:0] gpr_written_data;
// Wires needed to connect the processor to the fabric
wire [31:0] sp_address;
wire [31:0] sp_data;
wire [31:0] sp_strobe;
wire [31:0] sp_assertions_violated;
wire sp_assertion_violated = |sp_assertions_violated;
reg [31:0] sp_assertions_violated_reg;
reg sp_assertion_violated_reg;
reg sp_exception_hold;
wire sp_exceptionHandled;
wire sp_exceptionGated;
wire [31:0] sp_attack_enable;
always @(posedge clk)begin
sp_assertion_violated_reg <= 1'b0;
if(rst == `OR1200_RST_VALUE)begin
sp_assertions_violated_reg <= 1'b0;
sp_assertion_violated_reg <= 1'b0;
end
else if(sp_assertion_violated)begin
sp_assertions_violated_reg <= sp_assertions_violated;
sp_assertion_violated_reg <= sp_assertion_violated;
end
end
always @(posedge clk)begin
if(rst == `OR1200_RST_VALUE)
sp_exception_hold <= 1'b0;
else if(sp_exceptionHandled == 1'b1)
sp_exception_hold <= 1'b0;
else if(sp_assertion_violated == 1'b1)
sp_exception_hold <= 1'b1;
end
// Signals needed for exception processing
assign sp_exceptionHandled = (except_type == `OR1200_EXCEPT_ILLEGAL);
assign sp_exceptionGated = (sp_assertion_violated_reg | sp_exception_hold) & ~sp_exceptionHandled;
//
// Send exceptions to Debug Unit
//
assign du_except_trig = except_trig;
assign du_except_stop = except_stop;
assign du_lsu_store_dat = operand_b;
assign du_lsu_load_dat = lsu_dataout;
//
// Data cache enable
//
`ifdef OR1200_NO_DC
assign dc_en = 1'b0;
`else
assign dc_en = sr[`OR1200_SR_DCE];
`endif
//
// Instruction cache enable
//
`ifdef OR1200_NO_IC
assign ic_en = 1'b0;
`else
assign ic_en = sr[`OR1200_SR_ICE];
`endif
//
// SB enable
//
`ifdef OR1200_SB_IMPLEMENTED
//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined -- jb
`else
assign sb_en = 1'b0;
`endif
//
// DMMU enable
//
`ifdef OR1200_NO_DMMU
assign dmmu_en = 1'b0;
`else
assign dmmu_en = sr[`OR1200_SR_DME];
`endif
//
// IMMU enable
//
`ifdef OR1200_NO_IMMU
assign immu_en = 1'b0;
`else
assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
`endif
//
// SUPV bit
//
assign supv = sr[`OR1200_SR_SM];
//
// FLAG write enable
//
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
//
// Flag for any MTSPR instructions, that must block execution, to indicate done
//
assign mtspr_done = mtspr_dc_done;
//
// Range exception
//
assign sig_range = sr[`OR1200_SR_OV];
//
// Instantiation of instruction fetch block
//
or1200_genpc #(.boot_adr(boot_adr)) or1200_genpc(
.clk(clk),
.rst(rst),
.icpu_adr_o(icpu_adr_o),
.icpu_cycstb_o(icpu_cycstb_o),
.icpu_sel_o(icpu_sel_o),
.icpu_tag_o(icpu_tag_o),
.icpu_rty_i(icpu_rty_i),
.icpu_adr_i(icpu_adr_i),
.pre_branch_op(pre_branch_op),
.branch_op(branch_op),
.except_type(except_type),
.except_start(except_start),
.except_prefix(sr[`OR1200_SR_EPH]),
.id_branch_addrtarget(id_branch_addrtarget),
.ex_branch_addrtarget(ex_branch_addrtarget),
.muxed_b(muxed_b),
.operand_b(operand_b),
.flag(flag),
.flagforw(flagforw),
.ex_branch_taken(ex_branch_taken),
.epcr(epcr),
.spr_dat_i(spr_dat_cpu),
.spr_pc_we(pc_we),
.genpc_refetch(genpc_refetch),
.genpc_freeze(genpc_freeze),
.no_more_dslot(no_more_dslot),
.lsu_stall(lsu_stall),
.ex_pc(ex_pc),
.sp_epcr_ghost(sp_epcr_ghost)
, .sp_attack_enable(sp_attack_enable)
);
//
// Instantiation of instruction fetch block
//
or1200_if or1200_if(
.clk(clk),
.rst(rst),
.icpu_dat_i(icpu_dat_i),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.icpu_adr_i(icpu_adr_i),
.icpu_tag_i(icpu_tag_i),
.if_freeze(if_freeze),
.if_insn(if_insn),
.if_pc(if_pc),
.saving_if_insn(saving_if_insn),
.if_flushpipe(if_flushpipe),
.if_stall(if_stall),
.no_more_dslot(no_more_dslot),
.genpc_refetch(genpc_refetch),
.rfe(rfe),
.except_itlbmiss(except_itlbmiss),
.except_immufault(except_immufault),
.except_ibuserr(except_ibuserr)
);
//
// Instantiation of instruction decode/control logic
//
or1200_ctrl or1200_ctrl(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.if_flushpipe(if_flushpipe),
.id_flushpipe(id_flushpipe),
.ex_flushpipe(ex_flushpipe),
.wb_flushpipe(wb_flushpipe),
.extend_flush(extend_flush),
.except_flushpipe(except_flushpipe),
.abort_mvspr(abort_mvspr),
.if_insn(if_insn),
.id_insn(id_insn),
.ex_insn(ex_insn),
.id_branch_op(pre_branch_op),
.ex_branch_op(branch_op),
.ex_branch_taken(ex_branch_taken),
.rf_addra(rf_addra),
.rf_addrb(rf_addrb),
.rf_rda(rf_rda),
.rf_rdb(rf_rdb),
.alu_op(alu_op),
.alu_op2(alu_op2),
.mac_op(mac_op),
.comp_op(comp_op),
.rf_addrw(rf_addrw),
.rfwb_op(rfwb_op),
.fpu_op(fpu_op),
.pc_we(pc_we),
.wb_insn(wb_insn),
.id_simm(id_simm),
.id_branch_addrtarget(id_branch_addrtarget),
.ex_branch_addrtarget(ex_branch_addrtarget),
.ex_simm(ex_simm),
.sel_a(sel_a),
.sel_b(sel_b),
.id_lsu_op(id_lsu_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.id_pc(id_pc),
.ex_pc(ex_pc),
.multicycle(multicycle),
.wait_on(wait_on),
.wbforw_valid(wbforw_valid),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.force_dslot_fetch(force_dslot_fetch),
.no_more_dslot(no_more_dslot),
.id_void(id_void),
.ex_void(ex_void),
.ex_spr_read(ex_spr_read),
.ex_spr_write(ex_spr_write),
.id_mac_op(id_mac_op),
.id_macrc_op(id_macrc_op),
.ex_macrc_op(ex_macrc_op),
.rfe(rfe),
.du_hwbkpt(du_hwbkpt),
.except_illegal(except_illegal),
.dc_no_writethrough(dc_no_writethrough),
.sp_exception(sp_exceptionGated),
.sp_attack_enable(sp_attack_enable)
);
//
// Instantiation of register file
//
or1200_rf or1200_rf(
.clk(clk),
.rst(rst),
.cy_we_i(cy_we_alu),
.cy_we_o(cy_we_rf),
.supv(sr[`OR1200_SR_SM]),
.wb_freeze(wb_freeze),
.addrw(rf_addrw),
.dataw(rf_dataw),
.id_freeze(id_freeze),
.we(rfwb_op[0]),
.flushpipe(wb_flushpipe),
.addra(rf_addra),
.rda(rf_rda),
.dataa(rf_dataa),
.addrb(rf_addrb),
.rdb(rf_rdb),
.datab(rf_datab),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_rf),
.du_read(du_read)
, .sp_attack_enable(sp_attack_enable)
, .gpr_written_to(gpr_written_to)
, .gpr_written_addr(gpr_written_addr)
, .gpr_written_data(gpr_written_data)
, .sp_exception_comb(sp_assertion_violated | sp_exceptionGated)
);
//
// Instantiation of operand muxes
//
or1200_operandmuxes or1200_operandmuxes(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.rf_dataa(rf_dataa),
.rf_datab(rf_datab),
.ex_forw(rf_dataw),
.wb_forw(wb_forw),
.simm(id_simm),
.sel_a(sel_a),
.sel_b(sel_b),
.operand_a(operand_a),
.operand_b(operand_b),
.muxed_a(muxed_a),
.muxed_b(muxed_b)
);
//
// Instantiation of CPU's ALU
//
or1200_alu or1200_alu(
.a(operand_a),
.b(operand_b),
.mult_mac_result(mult_mac_result),
.macrc_op(ex_macrc_op),
.alu_op(alu_op),
.alu_op2(alu_op2),
.comp_op(comp_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.result(alu_dataout),
.flagforw(flagforw_alu),
.flag_we(flag_we_alu),
.cyforw(cyforw),
.cy_we(cy_we_alu),
.ovforw(ovforw),
.ov_we(ov_we_alu),
.flag(flag),
.carry(carry)
);
//
// FPU's exception is being dealt with
//
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
//
// Instantiation of FPU
//
or1200_fpu or1200_fpu(
.clk(clk),
.rst(rst),
.ex_freeze(ex_freeze),
.a(operand_a),
.b(operand_b),
.fpu_op(fpu_op),
.result(fpu_dataout),
.done(fpu_done),
.flagforw(flagforw_fpu),
.flag_we(flag_we_fpu),
.sig_fp(sig_fp),
.except_started(fpu_except_started),
.fpcsr_we(fpcsr_we),
.fpcsr(fpcsr),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_fpu)
);
//
// Instantiation of CPU's multiply unit
//
or1200_mult_mac or1200_mult_mac(
.clk(clk),
.rst(rst),
.ex_freeze(ex_freeze),
.id_macrc_op(id_macrc_op),
.macrc_op(ex_macrc_op),
.a(operand_a),
.b(operand_b),
.mac_op(mac_op),
.alu_op(alu_op),
.result(mult_mac_result),
.ovforw(ovforw_mult_mac),
.ov_we(ov_we_mult_mac),
.mult_mac_stall(mult_mac_stall),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_mac)
);
//
// Instantiation of CPU's SPRS block
//
or1200_sprs or1200_sprs(
.clk(clk),
.rst(rst),
.addrbase(operand_a),
.addrofs(ex_simm[15:0]),
.dat_i(operand_b),
.ex_spr_read(ex_spr_read),
.ex_spr_write(ex_spr_write),
.flagforw(flagforw),
.flag_we(flag_we),
.flag(flag),
.cyforw(cyforw),
.cy_we(cy_we_rf),
.carry(carry),
.ovforw(ovforw | ovforw_mult_mac),
.ov_we(ov_we_alu | ov_we_mult_mac),
.to_wbmux(sprs_dataout),
.du_addr(du_addr),
.du_dat_du(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_dat_cpu(du_dat_cpu),
.boot_adr_sel_i(boot_adr_sel_i),
.spr_addr(spr_addr),
.spr_dat_pic(spr_dat_pic),
.spr_dat_tt(spr_dat_tt),
.spr_dat_pm(spr_dat_pm),
.spr_dat_cfgr(spr_dat_cfgr),
.spr_dat_rf(spr_dat_rf),
.spr_dat_npc(spr_dat_npc),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_mac(spr_dat_mac),
.spr_dat_dmmu(spr_dat_dmmu),
.spr_dat_immu(spr_dat_immu),
.spr_dat_du(spr_dat_du),
.spr_dat_o(spr_dat_cpu),
.spr_cs(spr_cs),
.spr_we(spr_we),
.epcr_we(epcr_we),
.eear_we(eear_we),
.esr_we(esr_we),
.pc_we(pc_we),
.epcr(epcr),
.eear(eear),
.esr(esr),
.except_started(except_started),
.fpcsr(fpcsr),
.fpcsr_we(fpcsr_we),
.spr_dat_fpu(spr_dat_fpu),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.branch_op(branch_op),
.dsx(dsx)
, .ex_pc(ex_pc),
.ex_void(ex_void),
.except_illegal(except_illegal | sp_exceptionGated),
.sp_epcr_ghost_we(sp_epcr_ghost_we),
.sp_eear_ghost_we(sp_eear_ghost_we),
.sp_esr_ghost_we(sp_esr_ghost_we),
.sp_epcr_ghost(sp_epcr_ghost),
.sp_eear_ghost(sp_eear_ghost),
.sp_esr_ghost(sp_esr_ghost),
.sp_address(sp_address),
.sp_data(sp_data),
.sp_strobe(sp_strobe),
.sp_assertions_violated(sp_assertions_violated_reg),
.sp_assertion_violated(sp_assertion_violated),
.sp_attack_enable(sp_attack_enable)
);
//
// Instantiation of load/store unit
//
or1200_lsu or1200_lsu(
.clk(clk),
.rst(rst),
.id_addrbase(muxed_a),
.id_addrofs(id_simm),
.ex_addrbase(operand_a),
.ex_addrofs(ex_simm),
.id_lsu_op(id_lsu_op),
.lsu_datain(operand_b),
.lsu_dataout(lsu_dataout),
.lsu_stall(lsu_stall),
.lsu_unstall(lsu_unstall),
.du_stall(du_stall),
.except_align(except_align),
.except_dtlbmiss(except_dtlbmiss),
.except_dmmufault(except_dmmufault),
.except_dbuserr(except_dbuserr),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.flushpipe(ex_flushpipe),
.dcpu_adr_o(dcpu_adr_o),
.dcpu_cycstb_o(dcpu_cycstb_o),
.dcpu_we_o(dcpu_we_o),
.dcpu_sel_o(dcpu_sel_o),
.dcpu_tag_o(dcpu_tag_o),
.dcpu_dat_o(dcpu_dat_o),
.dcpu_dat_i(dcpu_dat_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_rty_i(dcpu_rty_i),
.dcpu_err_i(dcpu_err_i),
.dcpu_tag_i(dcpu_tag_i)
);
//
// Instantiation of write-back muxes
//
or1200_wbmux or1200_wbmux(
.clk(clk),
.rst(rst),
.wb_freeze(wb_freeze),
.rfwb_op(rfwb_op),
.muxin_a(alu_dataout),
.muxin_b(lsu_dataout),
.muxin_c(sprs_dataout),
.muxin_d(ex_pc),
.muxin_e(fpu_dataout),
.muxout(rf_dataw),
.muxreg(wb_forw),
.muxreg_valid(wbforw_valid)
);
//
// Instantiation of freeze logic
//
or1200_freeze or1200_freeze(
.clk(clk),
.rst(rst),
.multicycle(multicycle),
.wait_on(wait_on),
.fpu_done(fpu_done),
.mtspr_done(mtspr_done),
.flushpipe(wb_flushpipe),
.extend_flush(extend_flush),
.lsu_stall(lsu_stall),
.if_stall(if_stall),
.lsu_unstall(lsu_unstall),
.force_dslot_fetch(force_dslot_fetch),
.abort_ex(abort_ex),
.du_stall(du_stall),
.mac_stall(mult_mac_stall),
.saving_if_insn(saving_if_insn),
.genpc_freeze(genpc_freeze),
.if_freeze(if_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i)
);
//
// Instantiation of exception block
//
or1200_except or1200_except(
.clk(clk),
.rst(rst),
.sig_ibuserr(except_ibuserr),
.sig_dbuserr(except_dbuserr),
.sig_illegal(except_illegal | sp_exceptionGated),
.sig_align(except_align),
.sig_range(sig_range),
.sig_dtlbmiss(except_dtlbmiss),
.sig_dmmufault(except_dmmufault),
.sig_int(sig_int),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.sig_itlbmiss(except_itlbmiss),
.sig_immufault(except_immufault),
.sig_tick(sig_tick),
.sig_fp(sig_fp),
.fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
.ex_branch_taken(ex_branch_taken),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_err_i(dcpu_err_i),
.genpc_freeze(genpc_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.if_stall(if_stall),
.if_pc(if_pc),
.id_pc(id_pc),
.ex_pc(ex_pc),
.wb_pc(wb_pc),
.id_flushpipe(id_flushpipe),
.ex_flushpipe(ex_flushpipe),
.extend_flush(extend_flush),
.except_flushpipe(except_flushpipe),
.abort_mvspr(abort_mvspr),
.except_type(except_type),
.except_start(except_start),
.except_started(except_started),
.except_stop(except_stop),
.except_trig(except_trig),
.ex_void(ex_void),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_npc(spr_dat_npc),
.datain(spr_dat_cpu),
.branch_op(branch_op),
.du_dsr(du_dsr),
.du_dmr1(du_dmr1),
.du_hwbkpt(du_hwbkpt),
.du_hwbkpt_ls_r(du_hwbkpt_ls_r),
.epcr_we(epcr_we),
.eear_we(eear_we),
.esr_we(esr_we),
.pc_we(pc_we),
.epcr(epcr),
.eear(eear),
.esr(esr),
.sp_epcr_ghost_we(sp_epcr_ghost_we),
.sp_eear_ghost_we(sp_eear_ghost_we),
.sp_esr_ghost_we(sp_esr_ghost_we),
.sp_epcr_ghost(sp_epcr_ghost),
.sp_eear_ghost(sp_eear_ghost),
.sp_esr_ghost(sp_esr_ghost),
.sp_attack_enable(sp_attack_enable),
.lsu_addr(dcpu_adr_o),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.abort_ex(abort_ex),
.dsx(dsx)
);
//
// Instantiation of configuration registers
//
or1200_cfgr or1200_cfgr(
.spr_addr(spr_addr),
.spr_dat_o(spr_dat_cfgr)
);
wire [31:0] sp_assertions_violated_f;
wire [31:0] sp_assertions_violated_b;
wire insn_clk = ~ex_void & ~ex_freeze & (ex_pc[31:27] == 5'b0);
wire [543:0] sp_isa_state = {ex_pc, ex_insn, spr_dat_ppc, spr_dat_npc, eear, {15'b0, sr}, {15'b0, esr}, epcr, {31'b0, immu_sxe}, {31'b0, immu_uxe}, {31'b0, immu_en}, {31'b0, gpr_written_to}, {27'b0, gpr_written_addr}, gpr_written_data, dcpu_adr_o, dcpu_dat_i, operand_b};
// Connect the processor to the fabric
assertionFabricDriver assertionFabricDriver(
.clk(clk),
.rst(sp_exceptionGated | rst),
.enable(insn_clk),
.routingInput(sp_isa_state),
.bakedInAssertions(sp_assertions_violated_b),
.address(sp_address),
.data(sp_data),
.strobe(sp_strobe[0]),
.assertionViolated(),
.assertionsViolated(sp_assertions_violated_f)
);
BakedInAssertions bia(
.clk(clk),
.rst(sp_exceptionGated | rst),
.enable(insn_clk),
.ex_pc(ex_pc),
.ex_insn(ex_insn),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_npc(spr_dat_npc),
.eear(eear),
.sr(sr),
.esr(esr),
.epcr(epcr),
.immu_sxe(immu_sxe),
.immu_uxe(immu_uxe),
.immu_en(immu_en),
.gpr_written_to(gpr_written_to),
.gpr_written_addr(gpr_written_addr),
.gpr_written_data(gpr_written_data),
.dcpu_adr_o(dcpu_adr_o),
.dcpu_dat_i(dcpu_dat_i),
.operand_b(operand_b),
.checkersFired(sp_assertions_violated_b)
);
assign sp_assertions_violated = sp_assertions_violated_b | sp_assertions_violated_f;
endmodule
|
`timescale 1ns/1ns
`define DEFAULT_CYCLE_TIMEOUT 10000
`define INPUT_DELAY 0
`define OUTPUT_DELAY 0
`define CLOCK_PERIOD 10
`define THREADS 4
module core_testbench;
// Process command line options.
reg [31:0] max_cycles;
reg [511:0] ispmfile;
reg [511:0] dspmfile;
reg [511:0] vcdplusfile;
reg [31:0] vcdpluson;
reg [15:0] k;
initial begin
// Read command line arguments.
// Maximum number of cycles.
if(!$value$plusargs("maxcycles=%d", max_cycles))
max_cycles = `DEFAULT_CYCLE_TIMEOUT;
// Where to store VPD trace file.
if($value$plusargs("vcd=%s", vcdplusfile))
$vcdplusfile(vcdplusfile);
// When to turn on VCD tracing.
if(!$value$plusargs("vcdstart=%d", vcdpluson))
vcdpluson = 0;
// Enable warnings about comparisons with X's or Z's.
//$xzcheckon;
end
// Clock signal.
reg clk;
initial begin
clk <= 0;
forever #(`CLOCK_PERIOD/2.0) clk = ~clk;
end
// SPM
reg [31:0] ispm_init [4095:0];
reg [31:0] dspm_init [4095:0];
// Reset signal.
reg reset;
initial begin
reset <= 1'b1;
@(posedge clk);
@(negedge clk);
// Module
//$readmemh(ispmfile, core.imem.ispm);
//$readmemh(dspmfile, core.dmem.dspm);
// Blackbox
$readmemh(ispmfile, ispm_init);
$readmemh(dspmfile, dspm_init);
for(k = 0; k < 4096; k = k + 1) begin
core.imem.BRAMS[0].ispm[k] = ispm_init[k][3:0];
core.imem.BRAMS[1].ispm[k] = ispm_init[k][7:4];
core.imem.BRAMS[2].ispm[k] = ispm_init[k][11:8];
core.imem.BRAMS[3].ispm[k] = ispm_init[k][15:12];
core.imem.BRAMS[4].ispm[k] = ispm_init[k][19:16];
core.imem.BRAMS[5].ispm[k] = ispm_init[k][23:20];
core.imem.BRAMS[6].ispm[k] = ispm_init[k][27:24];
core.imem.BRAMS[7].ispm[k] = ispm_init[k][31:28];
core.dmem.BRAMS[0].dspm[k] = dspm_init[k][3:0];
core.dmem.BRAMS[1].dspm[k] = dspm_init[k][7:4];
core.dmem.BRAMS[2].dspm[k] = dspm_init[k][11:8];
core.dmem.BRAMS[3].dspm[k] = dspm_init[k][15:12];
core.dmem.BRAMS[4].dspm[k] = dspm_init[k][19:16];
core.dmem.BRAMS[5].dspm[k] = dspm_init[k][23:20];
core.dmem.BRAMS[6].dspm[k] = dspm_init[k][27:24];
core.dmem.BRAMS[7].dspm[k] = dspm_init[k][31:28];
end
reset = 1'b0;
end
// FlexPRET core.
wire [31:0] tohost;
Core core
(
.clk (clk),
.reset (reset),
.io_imem_addr(12'b0),
.io_imem_enable(1'b0),
.io_imem_write(1'b0),
.io_imem_data_in(32'b0),
.io_dmem_addr(12'b0),
.io_dmem_enable(1'b0),
.io_dmem_byte_write_3(1'b0),
.io_dmem_byte_write_2(1'b0),
.io_dmem_byte_write_1(1'b0),
.io_dmem_byte_write_0(1'b0),
.io_dmem_data_in(32'b0),
.io_bus_data_out(32'b0),
.io_host_to_host (tohost),
.io_gpio_in_3(1'b0),
.io_gpio_in_2(1'b0),
.io_gpio_in_1(1'b0),
.io_gpio_in_0(1'b0),
.io_int_exts_3(1'b0),
.io_int_exts_2(1'b0),
.io_int_exts_1(1'b0),
.io_int_exts_0(1'b0)
);
// Cycle counter.
reg [31:0] cycle_count = 32'd0;
always @(posedge clk)
begin
// Increment cycle.
cycle_count <= cycle_count + 1;
// Turn on vcdplus?
if(cycle_count == vcdpluson)
$vcdpluson(0);
end
// Check for completion.
always @(posedge clk)
begin
// Timeout.
if(cycle_count > max_cycles)
begin
$display("*** FAILED *** (Max cycles timeout)");
$finish;
end
// Test failed.
if(!reset && tohost[31:30] == 2'b0 && tohost > 1)
begin
$display("*** FAILED *** (test #%d)", tohost);
$finish;
end
// Test passed.
if(!reset && tohost == 1)
begin
$display("*** PASSED ***: %d", tohost);
$finish;
end
end
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Flow generator - generic packet generator module
*/
module fg_packet_gen #(
parameter DEST_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* Burst descriptor input
*/
input wire input_bd_valid,
output wire input_bd_ready,
input wire [DEST_WIDTH-1:0] input_bd_dest,
input wire [31:0] input_bd_burst_len,
/*
* Packet output
*/
output wire output_hdr_valid,
input wire output_hdr_ready,
output wire [DEST_WIDTH-1:0] output_hdr_dest,
output wire [15:0] output_hdr_len,
output wire [DATA_WIDTH-1:0] output_payload_tdata,
output wire [KEEP_WIDTH-1:0] output_payload_tkeep,
output wire output_payload_tvalid,
input wire output_payload_tready,
output wire output_payload_tlast,
output wire output_payload_tuser,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [15:0] payload_mtu
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_BURST = 2'd1,
STATE_FRAME = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [31:0] burst_len_reg = 0, burst_len_next;
reg [15:0] frame_len_reg = 0, frame_len_next;
reg input_bd_ready_reg = 0, input_bd_ready_next;
reg output_hdr_valid_reg = 0, output_hdr_valid_next;
reg [DEST_WIDTH-1:0] output_hdr_dest_reg = 0, output_hdr_dest_next;
reg [15:0] output_hdr_len_reg = 0, output_hdr_len_next;
reg busy_reg = 0;
// internal datapath
reg [DATA_WIDTH-1:0] output_payload_tdata_int;
reg [KEEP_WIDTH-1:0] output_payload_tkeep_int;
reg output_payload_tvalid_int;
reg output_payload_tready_int = 0;
reg output_payload_tlast_int;
reg output_payload_tuser_int;
wire output_payload_tready_int_early;
assign input_bd_ready = input_bd_ready_reg;
assign output_hdr_valid = output_hdr_valid_reg;
assign output_hdr_dest = output_hdr_dest_reg;
assign output_hdr_len = output_hdr_len_reg;
assign busy = busy_reg;
always @* begin
state_next = 0;
burst_len_next = burst_len_reg;
frame_len_next = frame_len_reg;
input_bd_ready_next = 0;
output_hdr_valid_next = output_hdr_valid_reg & ~output_hdr_ready;
output_hdr_dest_next = output_hdr_dest_reg;
output_hdr_len_next = output_hdr_len_reg;
output_payload_tdata_int = 0;
output_payload_tkeep_int = 0;
output_payload_tvalid_int = 0;
output_payload_tlast_int = 0;
output_payload_tuser_int = 0;
case (state_reg)
STATE_IDLE: begin
input_bd_ready_next = 1;
if (input_bd_ready & input_bd_valid) begin
output_hdr_dest_next = input_bd_dest;
burst_len_next = input_bd_burst_len;
state_next = STATE_BURST;
end else begin
state_next = STATE_IDLE;
end
end
STATE_BURST: begin
if (~output_hdr_valid_reg) begin
if (burst_len_reg > payload_mtu) begin
frame_len_next = payload_mtu;
burst_len_next = burst_len_reg - payload_mtu;
output_hdr_valid_next = 1;
output_hdr_len_next = payload_mtu;
end else begin
frame_len_next = burst_len_reg;
burst_len_next = 0;
output_hdr_valid_next = 1;
output_hdr_len_next = burst_len_reg;
end
state_next = STATE_FRAME;
end else begin
state_next = STATE_BURST;
end
end
STATE_FRAME: begin
if (output_payload_tready_int) begin
if (frame_len_reg > KEEP_WIDTH) begin
frame_len_next = frame_len_reg - KEEP_WIDTH;
output_payload_tkeep_int = {KEEP_WIDTH{1'b1}};
output_payload_tvalid_int = 1;
state_next = STATE_FRAME;
end else begin
frame_len_next = 0;
output_payload_tkeep_int = {KEEP_WIDTH{1'b1}} >> (KEEP_WIDTH - frame_len_reg);
output_payload_tvalid_int = 1;
output_payload_tlast_int = 1;
if (burst_len_reg > 0) begin
state_next = STATE_BURST;
end else begin
state_next = STATE_IDLE;
end
end
end else begin
state_next = STATE_FRAME;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
burst_len_reg <= 0;
frame_len_reg <= 0;
input_bd_ready_reg <= 0;
output_hdr_valid_reg <= 0;
output_hdr_dest_reg <= 0;
output_hdr_len_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
burst_len_reg <= burst_len_next;
frame_len_reg <= frame_len_next;
input_bd_ready_reg <= input_bd_ready_next;
output_hdr_valid_reg <= output_hdr_valid_next;
output_hdr_dest_reg <= output_hdr_dest_next;
output_hdr_len_reg <= output_hdr_len_next;
busy_reg <= state_next != STATE_IDLE;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_payload_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] output_payload_tkeep_reg = 0;
reg output_payload_tvalid_reg = 0;
reg output_payload_tlast_reg = 0;
reg output_payload_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_payload_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] temp_payload_tkeep_reg = 0;
reg temp_payload_tvalid_reg = 0;
reg temp_payload_tlast_reg = 0;
reg temp_payload_tuser_reg = 0;
assign output_payload_tdata = output_payload_tdata_reg;
assign output_payload_tkeep = output_payload_tkeep_reg;
assign output_payload_tvalid = output_payload_tvalid_reg;
assign output_payload_tlast = output_payload_tlast_reg;
assign output_payload_tuser = output_payload_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_payload_tready_int_early = output_payload_tready | (~temp_payload_tvalid_reg & ~output_payload_tvalid_reg) | (~temp_payload_tvalid_reg & ~output_payload_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_payload_tdata_reg <= 0;
output_payload_tkeep_reg <= 0;
output_payload_tvalid_reg <= 0;
output_payload_tlast_reg <= 0;
output_payload_tuser_reg <= 0;
output_payload_tready_int <= 0;
temp_payload_tdata_reg <= 0;
temp_payload_tkeep_reg <= 0;
temp_payload_tvalid_reg <= 0;
temp_payload_tlast_reg <= 0;
temp_payload_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_payload_tready_int <= output_payload_tready_int_early;
if (output_payload_tready_int) begin
// input is ready
if (output_payload_tready | ~output_payload_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_payload_tdata_reg <= output_payload_tdata_int;
output_payload_tkeep_reg <= output_payload_tkeep_int;
output_payload_tvalid_reg <= output_payload_tvalid_int;
output_payload_tlast_reg <= output_payload_tlast_int;
output_payload_tuser_reg <= output_payload_tuser_int;
end else begin
// output is not ready, store input in temp
temp_payload_tdata_reg <= output_payload_tdata_int;
temp_payload_tkeep_reg <= output_payload_tkeep_int;
temp_payload_tvalid_reg <= output_payload_tvalid_int;
temp_payload_tlast_reg <= output_payload_tlast_int;
temp_payload_tuser_reg <= output_payload_tuser_int;
end
end else if (output_payload_tready) begin
// input is not ready, but output is ready
output_payload_tdata_reg <= temp_payload_tdata_reg;
output_payload_tkeep_reg <= temp_payload_tkeep_reg;
output_payload_tvalid_reg <= temp_payload_tvalid_reg;
output_payload_tlast_reg <= temp_payload_tlast_reg;
output_payload_tuser_reg <= temp_payload_tuser_reg;
temp_payload_tdata_reg <= 0;
temp_payload_tkeep_reg <= 0;
temp_payload_tvalid_reg <= 0;
temp_payload_tlast_reg <= 0;
temp_payload_tuser_reg <= 0;
end
end
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the communication channel
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
/*
`include "viterbidec.v"
`include "cencoder.v"
`include "noisegen.v"
`include "xor2.v"
`include "pipe.v"
`include "pipe2.v"
*/
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_communication_channel();
/**
* Description of module to model a communication channel
*
* This includes 3 stages in the communications channel
* @stage 1: Data from the transmitter (TX) is encoded.
* @stage 2: Data is "transmitted" across the communication
* channel, and gets corrupted with noise.
* Noise in the communication channel is modeled
* by pseudo-random noise that corrupts some of
* the data bits
* @stage 3: Data is received at the receiver (RX), and is
* subsequently decoded.
*/
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the communication channel
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// ============================================================
// Declare "wire" signals: outputs from the DUT
// Outputs from the communication channel
wire d; // Output data signal
wire [1:0] c; // Encoded data
wire [1:0] cx; // Corrupted encoded data
wire b; // Original data
// -----------------------------------------------------------
// Encoded data output from the convolutional encoder
wire [1:0] r_c;
//wire [255:0] rf;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// ------------------------------------------------------------
// Inputs to the communication channel
//reg [255:0] r; // Original data: 256 stream of bits
reg r[0:255]; // Original data: 256 stream of bits
reg rr;
/**
* Randomly generated number to determine if data bit should
* be corrupted
*/
reg [7:0] e;
reg clock; // Clock input to all flip-flops
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 1st stage of the communication
* channel
*/
// Original data input & input to the convolutional encoder
reg r_b;
// Encoded data output from the convolutional encoder
// reg [1:0] r_c;
/**
* Propagated randomly generated number to determine if data
* bit should be corrupted - propagated value from the input
* to the communications channel
*/
reg [7:0] r_e;
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 2nd stage of the communication
* channel
*/
// Propagated values of the encoded data; also, input to XOR gate
reg [1:0] rr_c;
/**
* Further propagated randomly generated number to determine
* if data bit should be corrupted - propagated value from the
* input to the communications channel
*/
reg [7:0] r_e1;
/**
* Randomly generated error that determines the corruption of
* the data bits
*
* Random number will corrupt the encoded data bits based on
* the XOR operator - invert the bits of the encoded data if
* they are different from the random error bits
*
* Also, input to XOR gate to generated corrupted encoded bits
*/
wire [1:0] r_e2;
/**
* Corrupted encoded data bits - model corruption of data during
* transmission of the data in the communications channel
*/
wire [1:0] r_cx;
// Propagated original data input
reg r_b1;
/** ########################################################
#
# IMPORTANT!!!: MODIFY THE error_level HERE!!!
#
########################################################
***
*
* Error level that will be used to generate noise that will
* be used to corrupt encoded data bits
*
* Randomly generated error bits will be compared with this
* error level
*/
reg [7:0] error_level;
// ------------------------------------------------------------
// Inputs to the 3rd stage of the communication channel
// Further propagated values of the encoded data
reg [1:0] rr_c1;
// Propagated values of the corrupted encoded data
reg [1:0] r_cx1;
// Propagated original data input
reg r_b2;
// Reset signal for the flip-flops and registers
reg rset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 9'd256;
// ============================================================
// Declare and instantiate modules for the communication channel
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
d,r_cx1,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,r_b,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "ng"
*/
noise_generator ng (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_e1,r_e2,error_level);
// ------------------------------------------------------------
/**
* Instantiate an instance of the 2-bit 2-input XOR gate so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c,r_e2,r_cx);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_c"
*/
pipeline_buffer_2bit pipe_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c1,c,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_cx"
*/
pipeline_buffer_2bit pipe_cx (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_cx1,cx,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_b"
*/
pipeline_buffer pipe_b (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b2,b,clock,rset);
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, [email protected] ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
//
// Revision 2.1 2009/08/23 16:41:00 fajardo
// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY
// This actually models appropriately the behavior of the FPGA internal RAMs
//
// Revision 2.0 2009/09/10 11:30:00 fajardo
// Added tri-state buffering for altera output
// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY
//
// Revision 1.9 2009/08/18 15:15:00 fajardo
// Added tri-state buffering for xilinx and generic memory output
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "minsoc_defines.v"
module minsoc_onchip_ram(
`ifdef BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 8;
`ifdef BIST
//
// RAM BIST
//
input mbist_si_i;
input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Decide memory implementation for Xilinx FPGAs
//
`ifdef SPARTAN2
`define MINSOC_XILINX_RAMB4
`elsif VIRTEX
`define MINSOC_XILINX_RAMB4
`endif // !SPARTAN2/VIRTEX
`ifdef SPARTAN3
`define MINSOC_XILINX_RAMB16
`elsif SPARTAN6
`define MINSOC_XILINX_RAMB16
`elsif SPARTAN3E
`define MINSOC_XILINX_RAMB16
`elsif SPARTAN3A
`define MINSOC_XILINX_RAMB16
`elsif VIRTEX2
`define MINSOC_XILINX_RAMB16
`elsif VIRTEX4
`define MINSOC_XILINX_RAMB16
`elsif VIRTEX5
`define MINSOC_XILINX_RAMB16
`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5
//
// Internal wires and registers
//
`ifdef ARTISAN_SSP
`else
`ifdef VIRTUALSILICON_SSP
`else
`ifdef BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef GENERIC_MEMORY
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`elsif ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
`endif
`ifdef BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`elsif AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`elsif VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`elsif VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`elsif MINSOC_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// SPARTAN2/VIRTEX
//
wire [dw-1:0] doq_internal; // output data bus
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq_internal[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq_internal[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq_internal[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq_internal[7:6])
);
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
`elsif MINSOC_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// SPARTAN3/SPARTAN3E/VIRTEX2
// SPARTAN3A/VIRTEX4/VIRTEX5 are automatically reallocated by ISE
//
// Added By Nir Mor
//
wire [dw-1:0] doq_internal; // output data bus
RAMB16_S9 ramb16_s9(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq_internal),
.DOP()
);
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
`elsif ALTERA_FPGA
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
wire [dw-1:0] doq_internal; // output data bus
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.data(di),
.we(wr),
.q(doq_internal)
);
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`endif // !ALTERA_FPGA/MINCON_XILINX_RAMB16/MINCON_XILINX_RAMB4/VIRTUALSILICON_SSP/VIRAGE_SSP/AVANT_ATP/ARTISAN_SSP/GENERIC_MEMORY
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_gen_reset.v
*
* Date : 2012-11
*
* Description : Module that generates FPGA_RESETs and synchronizes RESETs to the
* respective clocks.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_gen_reset(
por_rst_n,
sys_rst_n,
rst_out_n,
m_axi_gp0_clk,
m_axi_gp1_clk,
s_axi_gp0_clk,
s_axi_gp1_clk,
s_axi_hp0_clk,
s_axi_hp1_clk,
s_axi_hp2_clk,
s_axi_hp3_clk,
s_axi_acp_clk,
m_axi_gp0_rstn,
m_axi_gp1_rstn,
s_axi_gp0_rstn,
s_axi_gp1_rstn,
s_axi_hp0_rstn,
s_axi_hp1_rstn,
s_axi_hp2_rstn,
s_axi_hp3_rstn,
s_axi_acp_rstn,
fclk_reset3_n,
fclk_reset2_n,
fclk_reset1_n,
fclk_reset0_n,
fpga_acp_reset_n,
fpga_gp_m0_reset_n,
fpga_gp_m1_reset_n,
fpga_gp_s0_reset_n,
fpga_gp_s1_reset_n,
fpga_hp_s0_reset_n,
fpga_hp_s1_reset_n,
fpga_hp_s2_reset_n,
fpga_hp_s3_reset_n
);
input por_rst_n;
input sys_rst_n;
input m_axi_gp0_clk;
input m_axi_gp1_clk;
input s_axi_gp0_clk;
input s_axi_gp1_clk;
input s_axi_hp0_clk;
input s_axi_hp1_clk;
input s_axi_hp2_clk;
input s_axi_hp3_clk;
input s_axi_acp_clk;
output reg m_axi_gp0_rstn;
output reg m_axi_gp1_rstn;
output reg s_axi_gp0_rstn;
output reg s_axi_gp1_rstn;
output reg s_axi_hp0_rstn;
output reg s_axi_hp1_rstn;
output reg s_axi_hp2_rstn;
output reg s_axi_hp3_rstn;
output reg s_axi_acp_rstn;
output rst_out_n;
output fclk_reset3_n;
output fclk_reset2_n;
output fclk_reset1_n;
output fclk_reset0_n;
output fpga_acp_reset_n;
output fpga_gp_m0_reset_n;
output fpga_gp_m1_reset_n;
output fpga_gp_s0_reset_n;
output fpga_gp_s1_reset_n;
output fpga_hp_s0_reset_n;
output fpga_hp_s1_reset_n;
output fpga_hp_s2_reset_n;
output fpga_hp_s3_reset_n;
reg [31:0] fabric_rst_n;
reg r_m_axi_gp0_rstn;
reg r_m_axi_gp1_rstn;
reg r_s_axi_gp0_rstn;
reg r_s_axi_gp1_rstn;
reg r_s_axi_hp0_rstn;
reg r_s_axi_hp1_rstn;
reg r_s_axi_hp2_rstn;
reg r_s_axi_hp3_rstn;
reg r_s_axi_acp_rstn;
assign rst_out_n = por_rst_n & sys_rst_n;
assign fclk_reset0_n = !fabric_rst_n[0];
assign fclk_reset1_n = !fabric_rst_n[1];
assign fclk_reset2_n = !fabric_rst_n[2];
assign fclk_reset3_n = !fabric_rst_n[3];
assign fpga_acp_reset_n = !fabric_rst_n[24];
assign fpga_hp_s3_reset_n = !fabric_rst_n[23];
assign fpga_hp_s2_reset_n = !fabric_rst_n[22];
assign fpga_hp_s1_reset_n = !fabric_rst_n[21];
assign fpga_hp_s0_reset_n = !fabric_rst_n[20];
assign fpga_gp_s1_reset_n = !fabric_rst_n[17];
assign fpga_gp_s0_reset_n = !fabric_rst_n[16];
assign fpga_gp_m1_reset_n = !fabric_rst_n[13];
assign fpga_gp_m0_reset_n = !fabric_rst_n[12];
task fpga_soft_reset;
input[31:0] reset_ctrl;
begin
fabric_rst_n[0] = reset_ctrl[0];
fabric_rst_n[1] = reset_ctrl[1];
fabric_rst_n[2] = reset_ctrl[2];
fabric_rst_n[3] = reset_ctrl[3];
fabric_rst_n[12] = reset_ctrl[12];
fabric_rst_n[13] = reset_ctrl[13];
fabric_rst_n[16] = reset_ctrl[16];
fabric_rst_n[17] = reset_ctrl[17];
fabric_rst_n[20] = reset_ctrl[20];
fabric_rst_n[21] = reset_ctrl[21];
fabric_rst_n[22] = reset_ctrl[22];
fabric_rst_n[23] = reset_ctrl[23];
fabric_rst_n[24] = reset_ctrl[24];
end
endtask
always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f;
always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp0_rstn = 1'b0;
else
m_axi_gp0_rstn = 1'b1;
end
always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp1_rstn = 1'b0;
else
m_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp0_rstn = 1'b0;
else
s_axi_gp0_rstn = 1'b1;
end
always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp1_rstn = 1'b0;
else
s_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp0_rstn = 1'b0;
else
s_axi_hp0_rstn = 1'b1;
end
always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp1_rstn = 1'b0;
else
s_axi_hp1_rstn = 1'b1;
end
always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp2_rstn = 1'b0;
else
s_axi_hp2_rstn = 1'b1;
end
always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp3_rstn = 1'b0;
else
s_axi_hp3_rstn = 1'b1;
end
always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_acp_rstn = 1'b0;
else
s_axi_acp_rstn = 1'b1;
end
always@(*) begin
if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin
$display(" Error:processing_system7_bfm_v2_0_gen_reset. PS_PORB and PS_SRSTB must be driven to known state");
$finish();
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFXTP_FUNCTIONAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_FUNCTIONAL_PP_V
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_mem1x
#(
parameter DEPTH_WORDS=1,
parameter WIDTH=32,
parameter MEM_LATENCY=3, // ONLY two values are allowed: 1 and 3
parameter RDW_MODE="DONT_CARE",
parameter RAM_OPERATION_MODE = "BIDIR_DUAL_PORT", // altsyncram's OPERATION_MODE parameter
parameter RAM_BLOCK_TYPE = "AUTO", // altsyncram's RAM_BLOCK_TYPE parameter
parameter INTENDED_DEVICE_FAMILY = "Stratix IV", // altsyncram's INTENDED_DEVICE_FAMILY parameter
parameter ENABLED = 0, //use enable inputs
parameter PREFERRED_WIDTH = 160
)
(
input wire clk,
input wire resetn,
input wire avs_port1_enable,
input wire avs_port2_enable,
input wire [WIDTH-1:0] avs_port1_writedata,
input wire [WIDTH-1:0] avs_port2_writedata,
input wire [WIDTH/8-1:0] avs_port1_byteenable,
input wire [WIDTH/8-1:0] avs_port2_byteenable,
input wire [$clog2(DEPTH_WORDS)-1:0] avs_port1_address,
input wire [$clog2(DEPTH_WORDS)-1:0] avs_port2_address,
input wire avs_port1_read,
input wire avs_port2_read,
input wire avs_port1_write,
input wire avs_port2_write,
output logic [WIDTH-1:0] avs_port1_readdata,
output logic [WIDTH-1:0] avs_port2_readdata,
output logic avs_port1_readdatavalid,
output logic avs_port2_readdatavalid,
output logic avs_port1_waitrequest,
output logic avs_port2_waitrequest
);
localparam LOG2DEPTH = $clog2( DEPTH_WORDS );
localparam LOW_LATENCY = MEM_LATENCY < 3 ? 1 : 0;
assign avs_port1_waitrequest=1'b0;
assign avs_port2_waitrequest=1'b0;
wire port1_enable;
wire port2_enable;
generate
if (ENABLED) begin
assign port1_enable = avs_port1_enable;
assign port2_enable = avs_port2_enable;
end else begin
assign port1_enable = 1'b1;
assign port2_enable = 1'b1;
end
endgenerate
generate
if (LOW_LATENCY)
begin
always @(posedge clk or negedge resetn)
begin
if (!resetn) begin
avs_port1_readdatavalid <= '0;
avs_port2_readdatavalid <= '0;
end else begin
if (port1_enable) begin
avs_port1_readdatavalid <= avs_port1_read;
end
if (port2_enable) begin
avs_port2_readdatavalid <= avs_port2_read;
end
end
end
end
else
begin
_acl_mem1x_shiftreg readatavalid_1(.D(avs_port1_read), .clock(clk), .resetn(resetn), .enable(port1_enable), .Q(avs_port1_readdatavalid));
defparam readatavalid_1.WIDTH = 1;
defparam readatavalid_1.DEPTH = 3;
_acl_mem1x_shiftreg readatavalid_2(.D(avs_port2_read), .clock(clk), .resetn(resetn), .enable(port2_enable), .Q(avs_port2_readdatavalid));
defparam readatavalid_2.WIDTH = 1;
defparam readatavalid_2.DEPTH = 3;
end
endgenerate
localparam NUM_RAMS=((WIDTH+PREFERRED_WIDTH-1)/PREFERRED_WIDTH);
genvar n;
generate
for(n=0; n<NUM_RAMS; n++)
begin : block_n
localparam MY_WIDTH=( (n==NUM_RAMS-1) ? (WIDTH-(NUM_RAMS-1)*PREFERRED_WIDTH) : PREFERRED_WIDTH );
localparam MY_WIDTH_BYTES = MY_WIDTH / 8;
reg [MY_WIDTH-1:0] r_port1_writedata /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] r_port2_writedata /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] r_port1_byteenable /* synthesis dont_merge */;
reg [MY_WIDTH/8-1:0] r_port2_byteenable /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] r_port1_address /* synthesis dont_merge */;
reg [LOG2DEPTH-1:0] r_port2_address /* synthesis dont_merge */;
reg r_port1_write /* synthesis dont_merge */;
reg r_port2_write /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] port1_readdata /* synthesis dont_merge */;
reg [MY_WIDTH-1:0] port2_readdata /* synthesis dont_merge */;
wire [MY_WIDTH-1:0] port1_readdata_mem;
wire [MY_WIDTH-1:0] port2_readdata_mem;
if (LOW_LATENCY)
begin
assign r_port1_writedata = avs_port1_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
assign r_port2_writedata = avs_port2_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
assign r_port1_byteenable = avs_port1_byteenable[n*PREFERRED_WIDTH/8 +: MY_WIDTH/8];
assign r_port2_byteenable = avs_port2_byteenable[n*PREFERRED_WIDTH/8 +: MY_WIDTH/8];
assign r_port1_address = avs_port1_address;
assign r_port2_address = avs_port2_address;
assign r_port1_write = avs_port1_write;
assign r_port2_write = avs_port2_write;
end
else
begin
always @(posedge clk or negedge resetn)
begin
if (!resetn)
begin
r_port1_writedata <= 'x;
r_port1_byteenable <= 'x;
r_port1_address <= 'x;
r_port1_write <= 1'b0;
end else if (port1_enable) begin
r_port1_writedata <= avs_port1_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
r_port1_byteenable <= avs_port1_byteenable[n*PREFERRED_WIDTH/8 +: MY_WIDTH/8];
r_port1_address <= avs_port1_address;
r_port1_write <= avs_port1_write;
end
end
always @(posedge clk or negedge resetn)
begin
if (!resetn)
begin
r_port2_writedata <= 'x;
r_port2_byteenable <= 'x;
r_port2_address <= 'x;
r_port2_write <= 1'b0;
end else if (port2_enable) begin
r_port2_writedata <= avs_port2_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
r_port2_byteenable <= avs_port2_byteenable[n*PREFERRED_WIDTH/8 +: MY_WIDTH/8];
r_port2_address <= avs_port2_address;
r_port2_write <= avs_port2_write;
end
end
end
assign avs_port1_readdata[n*PREFERRED_WIDTH +: MY_WIDTH] = port1_readdata;
assign avs_port2_readdata[n*PREFERRED_WIDTH +: MY_WIDTH] = port2_readdata;
altsyncram altsyncram_component (
.clock0 (clk),
.wren_a (r_port1_write & port1_enable),
.wren_b (r_port2_write & port2_enable),
.address_a (r_port1_address),
.address_b (r_port2_address),
.data_a (r_port1_writedata),
.data_b (r_port2_writedata),
.q_a (port1_readdata_mem),
.q_b (port2_readdata_mem),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (~port1_enable),
.addressstall_b (~port2_enable),
.byteena_a (r_port1_byteenable),
.byteena_b (r_port2_byteenable),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = INTENDED_DEVICE_FAMILY,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = DEPTH_WORDS,
altsyncram_component.numwords_b = DEPTH_WORDS,
altsyncram_component.operation_mode = RAM_OPERATION_MODE,
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = LOW_LATENCY ? "UNREGISTERED" : "CLOCK0",
altsyncram_component.outdata_reg_b = LOW_LATENCY ? "UNREGISTERED" : "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = RDW_MODE,
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_b = "DONT_CARE",
altsyncram_component.widthad_a = LOG2DEPTH,
altsyncram_component.widthad_b = LOG2DEPTH,
altsyncram_component.width_a = MY_WIDTH,
altsyncram_component.width_b = MY_WIDTH,
altsyncram_component.width_byteena_a = MY_WIDTH_BYTES,
altsyncram_component.width_byteena_b = MY_WIDTH_BYTES,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.ram_block_type = RAM_BLOCK_TYPE;
if (ENABLED) begin
// catch read output data if disabled
acl_mem_staging_reg #(
.WIDTH (MY_WIDTH),
.LOW_LATENCY (LOW_LATENCY)
) data_a_acl_mem_staging_reg (
.clk (clk),
.resetn (resetn),
.enable (port1_enable),
.rdata_in (port1_readdata_mem),
.rdata_out(port1_readdata)
);
acl_mem_staging_reg #(
.WIDTH(MY_WIDTH),
.LOW_LATENCY (LOW_LATENCY)
) data_b_acl_mem_staging_reg (
.clk (clk),
.resetn (resetn),
.enable (port2_enable),
.rdata_in (port2_readdata_mem),
.rdata_out(port2_readdata)
);
end else begin
assign port1_readdata = port1_readdata_mem;
assign port2_readdata = port2_readdata_mem;
end
end
endgenerate
endmodule
/*********************************************************************************
* Support components
*********************************************************************************/
module _acl_mem1x_shiftreg(D, clock, resetn, enable, Q);
parameter WIDTH = 32;
parameter DEPTH = 1;
input logic [WIDTH-1:0] D;
input logic clock, resetn, enable;
output logic [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
if (!resetn)
local_ffs <= '0;
else if (enable)
local_ffs <= {local_ffs[DEPTH-2:0], D};
assign Q = local_ffs[DEPTH-1];
endmodule
// vim:set filetype=verilog:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
module my_function (
input clk,
input rst
//output reg [7:0] o_reg_example
//input [7:0] i_reg_example
);
//local parameters
localparam PARAM1 = 32'h00000000;
//registes/wires
//submodules
//asynchronous logic
//synchronous logic
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_BLACKBOX_V
`define SKY130_FD_SC_HVL__EINVN_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_BLACKBOX_V
|
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