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//-----------------------------------------------------
// Design Name : hw2_B_testbench
// File Name : hw2_B_testbench.v
// Function : This program will test hw2_B.v
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
module hw2_B_testbench ;
reg in;
reg clk, rst_n;
wire out;
hw2_B B(
in,
clk,
rst_n,
out,
);
initial begin
#0 rst_n = 1'b0; clk = 1'b0;
#20 rst_n = 1'b1; in = 1'b0;
$display ("====================================================================");
$display ("Time %t", $time);
$display ("rst_n = %b\tin = %b\tout = %b",
rst_n, in, out);
$display ("====================================================================");
end
wire [17:0] inputArr = 18'b0111_0001_0011_1110_00; // Test pattern
integer i;
initial begin
#20 $display ("Simulate hw2_B");
for (i = 17; i >= 0; i = i - 1) begin
#20 in = inputArr[i];
$display ("====================================================================");
$display ("Time %t", $time);
$display ("rst_n = %b\tin = %b\tout = %b",
rst_n, in, out);
$display ("====================================================================");
end
#40 $finish;
end
always begin
#10 clk = ~clk;
end
initial begin
$fsdbDumpfile("hw2_B_testbench.fsdb");
$fsdbDumpvars;
end
endmodule // End of Module hw2_B_testbench
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_MM_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_MM_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_MM
);
localparam N = 6; // Para definir el número de bits del contador (hasta 59->6 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 6'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 2)
begin
if (enUP)
begin
if (q_act >= 6'd59) q_next = 6'd0;
else q_next = q_act + 6'd1;
end
else if (enDOWN)
begin
if (q_act == 6'd0) q_next = 6'd59;
else q_next = q_act - 6'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_MM = {digit1,digit0};
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file decryption_mem.v when simulating
// the core, decryption_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module decryption_mem(
clka,
wea,
addra,
dina,
clkb,
rstb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [14 : 0] addra;
input [7 : 0] dina;
input clkb;
input rstb;
input [14 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(1),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(1),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("decryption_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("SR"),
.C_RST_TYPE("ASYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.RSTB(rstb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
module decoder (cx,d);
output [6:0] d;
input [10:0] cx;
reg [6:0] d;
reg [6:0] s;
reg [10:0] cx1;
parameter s0 = 7'b1000;
parameter s1 = 7'b0100;
parameter s2 = 7'b0010;
parameter s3 = 7'b0001;
parameter s4 = 7'b0111;
parameter s5 = 7'b0101;
parameter s6 = 7'b0010;
parameter s7 = 7'b1001;
parameter s8 = 7'b0010;
parameter s9 = 7'b0111;
parameter s10 = 7'b0101;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
cx1[9] = cx[9];
cx1[10] = cx[10];
s[0]= cx[0]+ cx[7];
s[1]= cx[1]+ cx[4]+ cx[5]+ cx[9]+ cx[10];
s[2]= cx[2]+ cx[4]+ cx[6]+ cx[8]+ cx[9];
s[3]= cx[3]+ cx[4]+ cx[5]+ cx[7]+ cx[9]+ cx[10];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
s9:
begin
if(cx[9]==1'b0)
begin
cx1[9]=1'b1;
end
else
begin
cx1[9]=1'b0;
end
end
s10:
begin
if(cx[10]==1'b0)
begin
cx1[10]=1'b1;
end
else
begin
cx1[10]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
cx1[9]=cx[9];
cx1[10]=cx[10];
end
endcase
d[0] = cx1[4];
d[1] = cx1[5];
d[2] = cx1[6];
d[3] = cx1[7];
d[4] = cx1[8];
d[5] = cx1[9];
d[6] = cx1[10];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDFRTN_FUNCTIONAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrtn (
VPWR ,
VGND ,
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , mux_out, intclk, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTN_FUNCTIONAL_PP_V |
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course; Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| b and b
| not b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
Case "ANum". reflexivity.
Case "APlus". destruct a1.
SCase "a1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHa2.
SSCase "n <> 0". simpl. rewrite IHa2. reflexivity.
SCase "a1 = APlus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMinus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMult a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
Case "AMinus".
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
Case "AMult".
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
Tactic Notation "simpl_refl" tactic :=
simpl; try reflexivity.
Lemma plus_trivial : plus 0 1 = 1.
Proof. simpl_refl().
Qed.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BEq a1 a2 => BEq (optimize_0plus a1) (optimize_0plus a2)
| BLe a1 a2 => BLe (optimize_0plus a1) (optimize_0plus a2)
| BTrue => BTrue
| BFalse => BFalse
| BNot b1 => BNot (optimize_0plus_b b1)
| BAnd b1 b2 => BAnd (optimize_0plus_b b1) (optimize_0plus_b b2)
end.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue"
| Case_aux c "BFalse"
| Case_aux c "BEq"
| Case_aux c "BLe"
| Case_aux c "BNot"
| Case_aux c "BAnd"
].
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
intros b.
bexp_cases (induction b) Case;
try (simpl; repeat (rewrite optimize_0plus_sound); simpl; reflexivity).
Case "BNot".
simpl. rewrite IHb. reflexivity.
Case "BAnd".
simpl. rewrite IHb1. rewrite IHb2. reflexivity.
Qed.
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
*)
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Liebniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase;
simpl; try (rewrite IHaevalR1); try (rewrite IHaevalR2); reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst; constructor; try (apply IHa1); try (apply IHa2); try reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
Inductive bevalR: bexp -> bool -> Prop :=
| E_BTrue : bevalR BTrue true
| E_BFalse : bevalR BFalse false
| E_BEq : forall (aexp1 aexp2 : aexp) (n1 n2 : nat),
aexp1 || n1 -> aexp2 || n2 -> bevalR (BEq aexp1 aexp2) (beq_nat n1 n2)
| E_BLe : forall (aexp1 aexp2 : aexp) (n1 n2 : nat),
aexp1 || n1 -> aexp2 || n2 -> bevalR (BLe aexp1 aexp2) (ble_nat n1 n2)
| E_BNot : forall (bexp1 : bexp) (b : bool),
bevalR bexp1 b -> bevalR (BNot bexp1) (negb b)
| E_BAnd : forall (bexp1 bexp2 : bexp) (b1 b2 : bool),
bevalR bexp1 b1 -> bevalR bexp2 b2 -> bevalR (BAnd bexp1 bexp2) (andb b1 b2).
Theorem beval_iff_bevalR : forall be b,
bevalR be b <-> beval be = b.
Proof.
split.
Case "->".
intros H.
bexp_cases (induction H) SCase;
simpl; try (apply aeval_iff_aevalR in H); try (apply aeval_iff_aevalR in H0); subst; reflexivity.
Case "<-".
intros H. generalize dependent b. induction be;
intros; simpl in H; subst; constructor;
repeat (apply aeval_iff_aevalR; reflexivity);
try (apply IHbe); try (apply IHbe1); try (apply IHbe2); reflexivity.
Qed.
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
Case "n1 = n2".
left. rewrite Heq. reflexivity.
Case "n1 <> n2".
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
Case "x = x".
reflexivity.
Case "x <> x (impossible)".
apply ex_falso_quodlibet. apply n. reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
intros. destruct (eq_id_dec x y).
Case "x = y". apply H in e. inversion e.
Case "x <> y". reflexivity.
Qed.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of all the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them. *)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
intros. unfold update. apply eq_id.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
intros. unfold update. apply neq_id. assumption.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
intros. unfold update. apply neq_id. intro contra. inversion contra.
Qed.
(** [] *)
Theorem neq_symm : forall (x1:id) (x2:id), x1 <> x2 <-> x2 <> x1.
Proof.
split; intros; intro contra; apply H; symmetry; assumption.
Qed.
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
intros. unfold update at 1. destruct (eq_id_dec x1 x2).
Case "x1 = x2".
rewrite e. rewrite eq_id. unfold update. rewrite eq_id. reflexivity.
Case "x1 <> x2".
apply neq_symm in n;
try (rewrite neq_id; unfold update; repeat (rewrite neq_id); try reflexivity); try assumption.
Qed.
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
intros. unfold update. destruct (eq_id_dec x1 x2).
Case "x1=x2". rewrite <- e. symmetry. assumption. reflexivity.
Qed.
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
intros;
destruct (eq_id_dec x1 x3);
destruct (eq_id_dec x2 x3).
rewrite <- e in e0. apply H in e0. inversion e0.
rewrite e. rewrite update_eq. rewrite update_neq. rewrite update_eq. reflexivity. assumption.
rewrite e. rewrite update_eq. rewrite update_neq. rewrite update_eq. reflexivity. assumption.
repeat (rewrite update_neq). reflexivity. assumption. assumption. assumption. assumption.
Qed.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
For example, here's the factorial function in Imp.
Z ::= X;
Y ::= 1;
WHILE not (Z = 0) DO
Y ::= Y * Z;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** Loops: *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
apply E_Seq with (update empty_state X 0). apply E_Ass. reflexivity.
apply E_Seq with (update (update empty_state X 0) Y 1). apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(Y ::= ANum 0;;
WHILE BLe (ANum 1) (AId X)
DO
Y ::= APlus (AId Y) (AId X);;
X ::= AMinus (AId X) (ANum 1)
END).
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
apply E_Seq with (update (update empty_state X 2) Y 0). apply E_Ass. reflexivity.
apply E_WhileLoop with (st:=update (update empty_state X 2) Y 0)
(st':=update (update (update (update empty_state X 2) Y 0) Y 2) X 1)
(st'':=update (update (update (update (update (update empty_state X 2) Y 0) Y 2) X 1) Y 3) X 0).
reflexivity.
apply E_Seq with (update (update (update empty_state X 2) Y 0) Y 2). apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
apply E_WhileLoop with (st:=update (update (update (update empty_state X 2) Y 0) Y 2) X 1)
(st':=update (update (update (update (update (update empty_state X 2) Y 0) Y 2) X 1) Y 3) X 0).
reflexivity.
apply E_Seq with (update (update (update (update (update empty_state X 2) Y 0) Y 2) X 1) Y 3).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
apply E_WhileEnd. reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to false".
reflexivity.
SCase "b1 evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)). *)
Theorem XtimesYinZ_spec : forall st st' x y,
st X = x ->
st Y = y ->
XtimesYinZ / st || st' ->
st' Z = x * y.
Proof.
intros st st' x y HX HY Heval.
inversion Heval. subst. clear Heval. simpl. apply update_eq.
Qed.
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
ceval_cases (induction contra) Case;
try (inversion Heqloopdef).
Case "E_WhileEnd". rewrite H1 in H. simpl in H. inversion H.
Case "E_WhileLoop". apply IHcontra2. subst. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR : com -> Prop :=
| NW_Skip : no_whilesR CSkip
| NW_Ass : forall a x, no_whilesR (CAss x a)
| NW_Seq : forall c1 c2, no_whilesR c1 -> no_whilesR c2 -> no_whilesR (c1;;c2)
| NW_If : forall b c1 c2, no_whilesR c1 -> no_whilesR c2 -> no_whilesR (CIf b c1 c2)
.
Tactic Notation "no_whilesR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "NW_Skip" | Case_aux c "NW_Ass" | Case_aux c "NW_Seq" | Case_aux c "NW_If" ].
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
intros. split.
Case "->". intros. com_cases (induction c) SCase;
try constructor;
try (simpl in H; symmetry in H; apply andb_true_eq in H; inversion H; try (apply IHc1); try (apply IHc2); symmetry; assumption);
try (simpl in H; inversion H).
Case "<-". intros. induction H;
try constructor;
try (simpl; rewrite IHno_whilesR1; rewrite IHno_whilesR2; reflexivity).
Qed.
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
Theorem no_whiles_term:
forall c st, no_whilesR c -> exists st', c / st || st'.
Proof.
intros. generalize dependent st. no_whilesR_cases (induction H) Case.
Case "NW_Skip". intro st. exists st. constructor.
Case "NW_Ass". intro st. exists (update st x (aeval st a)). constructor. reflexivity.
Case "NW_Seq".
intro st. assert (exists st': state, c1 / st || st'). apply IHno_whilesR1. inversion H1.
assert (exists st'': state, c2 / x || st''). apply IHno_whilesR2. inversion H3.
exists x0. apply E_Seq with (st':=x). assumption. assumption.
Case "NW_If".
intro st. remember (beval st b) as bb. destruct bb.
assert (exists st1, c1 / st || st1). apply IHno_whilesR1. inversion H1. exists x. apply E_IfTrue. symmetry. assumption. assumption.
assert (exists st2, c2 / st || st2). apply IHno_whilesR2. inversion H1. exists x. apply E_IfFalse. symmetry. assumption. assumption.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
match prog with
| h :: t =>
match h with
| SPush n => s_execute st (n :: stack) t
| SLoad i => s_execute st (st i :: stack) t
| SPlus => match stack with
| e1 :: e2 :: rest => s_execute st (e2 + e1 :: rest) t
| _ => []
end
| SMinus => match stack with
| e1 :: e2 :: rest => s_execute st (e2 - e1 :: rest) t
| _ => []
end
| SMult => match stack with
| e1 :: e2 :: rest => s_execute st (e2 * e1 :: rest) t
| _ => []
end
end
| [] => stack
end.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
reflexivity.
Qed.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
reflexivity.
Qed.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
match e with
| ANum n => [SPush n]
| AId i => [SLoad i]
| APlus e1 e2 => s_compile e1 ++ s_compile e2 ++ [SPlus]
| AMinus e1 e2 => s_compile e1 ++ s_compile e2 ++ [SMinus]
| AMult e1 e2 => s_compile e1 ++ s_compile e2 ++ [SMult]
end.
(** After you've defined [s_compile], uncomment the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
calculator implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Lemma app_assoc_4 : forall (X:Type) (l m n o : list X),
(l ++ m ++ n) ++ o = l ++ m ++ n ++ o.
Proof.
intros.
rewrite <- app_assoc with (m:=m++n). rewrite <- app_assoc. reflexivity.
Qed.
Lemma s_execute_app : forall (st : state) (e : aexp) (prog : list sinstr) (stk : list nat),
s_execute st stk (s_compile e ++ prog) = s_execute st (aeval st e :: stk) prog.
Proof.
intros st e.
aexp_cases (induction e) Case;
try reflexivity;
intros; simpl;
rewrite app_assoc_4;
rewrite IHe1;
rewrite IHe2;
simpl;
reflexivity.
Qed.
Theorem s_compile_correct : forall (e : aexp) (st : state),
s_execute st [] (s_compile e) = [aeval st e].
Proof.
intros. assert (s_compile e = s_compile e ++ []). rewrite app_nil_r. reflexivity.
rewrite H. rewrite s_execute_app. simpl. reflexivity.
Qed.
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;
Y ::= 1;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;
X ::= 1;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
| E_Break : forall st,
CBreak / st || SBreak / st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || SContinue / (update st x n)
| E_SeqCont : forall c1 c2 st st1 st2 sig,
c1 / st || SContinue / st1 ->
c2 / st1 || sig / st2 ->
(c1 ; c2) / st || sig / st2
| E_SeqBreak : forall c1 c2 st st1 st2 sig,
c1 / st || SBreak / st1 ->
c2 / st1 || sig / st2 ->
(c1 ; c2) / st || SBreak / st1
| E_IfTrue : forall st st1 b c1 c2 sig1,
beval st b = true ->
c1 / st || sig1 / st1 ->
(IFB b THEN c1 ELSE c2 FI) / st || sig1 / st1
| E_IfFalse : forall st st2 b c1 c2 sig2,
beval st b = false ->
c2 / st || sig2 / st2 ->
(IFB b THEN c1 ELSE c2 FI) / st || sig2 / st2
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || SContinue / st
(* FIXME: think about these *)
| E_WhileLoopCont : forall st st' st'' b c,
beval st b = true ->
c / st || SContinue / st' ->
(WHILE b DO c END) / st' || SContinue / st'' ->
(WHILE b DO c END) / st || SContinue / st''
| E_WhileLoopBreak : forall st st' b c,
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip"
| Case_aux c "E_Break"
| Case_aux c "E_Ass"
| Case_aux c "E_SeqCont"
| Case_aux c "E_SeqBreak"
| Case_aux c "E_IfTrue"
| Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd"
| Case_aux c "E_WhileLoopCont"
| Case_aux c "E_WhileLoopBreak"
].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK; c) / st || s / st' ->
st = st'.
Proof.
intros c st st' s H. inversion H. subst. inversion H2. subst.
inversion H2. reflexivity.
Qed.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
intros. inversion H; repeat reflexivity.
Qed.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
intros. apply E_WhileLoopBreak. assumption. assumption.
Qed.
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
intros. remember (WHILE b DO c END) as loopdef eqn:Heqloopdef.
ceval_cases (induction H) Case; try (inversion Heqloopdef); try subst.
Case "E_WhileEnd".
rewrite H in H0. inversion H0.
Case "E_WhileLoopCont".
(* I have no idea why this case works ... *)
apply IHceval2. apply Heqloopdef. apply H0.
Case "E_WhileLoopBreak".
exists st. assumption.
Qed.
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
intros c st st1 st2 s1 s2 H. generalize dependent st2. generalize dependent s2.
ceval_cases (induction H) Case.
Case "E_Skip".
intros. inversion H. split. reflexivity. reflexivity.
Case "E_Break".
intros. inversion H. split. reflexivity. reflexivity.
Case "E_Ass".
intros. inversion H0. subst. split. reflexivity. reflexivity.
Case "E_SeqCont". intros. apply IHceval2. inversion H1. subst.
assert (st1 = st4 /\ SContinue = SContinue). apply IHceval1. assumption. inversion H2. subst. assumption.
(* absurd case *)
apply IHceval1 in H4. inversion H4. inversion H10.
Case "E_SeqBreak". intros. apply IHceval1. inversion H1. subst.
(* absurd case *)
apply IHceval1 in H4. inversion H4. inversion H3.
(* good case *)
subst. apply IHceval1 in H4. inversion H4. subst. assumption.
Case "E_IfTrue".
intros. inversion H1. subst. apply IHceval in H9. assumption. rewrite H8 in H. inversion H.
Case "E_IfFalse".
intros. inversion H1. subst. rewrite H8 in H. inversion H. subst. apply IHceval. assumption.
Case "E_WhileEnd".
intros. inversion H0.
split. reflexivity. reflexivity.
split. subst. rewrite H3 in H. inversion H. reflexivity. split. subst. rewrite H3 in H. inversion H. reflexivity.
Case "E_WhileLoopCont".
intros. inversion H2.
subst. rewrite H in H8. inversion H8. subst. apply IHceval1 in H6. inversion H6. rewrite <- H3 in H10. apply IHceval2 in H10. assumption.
subst. apply IHceval1 in H9. inversion H9. inversion H4.
Case "E_WhileLoopBreak".
intros. inversion H1. subst. rewrite H in H7. inversion H7.
subst. apply IHceval in H5. inversion H5. inversion H3. subst. split.
apply IHceval in H8. inversion H8. assumption. reflexivity.
Qed.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:54:24 05/17/2016
// Design Name:
// Module Name: Encryption
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Encryption(
input Clk,
input Ack,
//input [7:0]ID,
input [7:0]DataIn,
//input [7:0]SizeOfData,
input [7:0]key,
//input [7:0]NumberOfKeys,
output reg [7:0]DataOut,
output reg Ready // toggled 'low' to indicate start of encryption
// and toggled 'high' to indicate completion.
);
//reg [2:0]dataCount;
reg [3:0]count;
//reg [7:0]temp;
//parameter NumberOfbitsInByte = 8;
always @(posedge Clk) begin
if (Ack) begin
Ready <= 1'b0;
// count <= 1'b0;
// dataCount <= 0;
end
else begin
// if (dataCount < SizeOfData) begin
// for (count = 0; count < 8; count = count + 1'b1) begin
// temp <= DataIn[count] ^ key[count];
// DataOut[count] <= temp;
//// dataCount <= dataCount + 1'b1;
//// keyCount <= keyCount + 1'b1;
////
//// if (keyCount == NumberOfKeys)
//// keyCount <= 1'b0; // wrap around.
// end
// if (count == 8)
// temp <= DataIn ^ key;
DataOut <= DataIn ^ key;
Ready <= 1'b1; // to indicate that we completed encryption.
end
end
endmodule |
`default_nettype none
package testcase_pkg;
typedef int unsigned uint;
localparam uint SIZE = 8;
typedef enum {ENUM1, ENUM2} enum_t;
endpackage
module testcase_top
(
input testcase_pkg::enum_t top_enum,
input logic [testcase_pkg::SIZE-1:0] top_in,
output logic [testcase_pkg::SIZE-1:0] top_out
);
import testcase_pkg::*;
//enum_t sub_enum; // is not declared by AUTOWIRE
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
testcase_pkg::enum_t sub_enum; // From testcase_sub1 of testcase_sub1.v
logic [testcase_pkg::SIZE-1:0] sub_in; // From testcase_sub1 of testcase_sub1.v
logic [testcase_pkg::SIZE-1:0] sub_out; // From testcase_sub2 of testcase_sub2.v
// End of automatics
assign top_out = sub_out;
testcase_sub1 testcase_sub1 (.*,
// Outputs
.sub_enum (sub_enum), // Implicit .*
.sub_in (sub_in[testcase_pkg::SIZE-1:0]), // Implicit .*
// Inputs
.top_enum (top_enum)); // Implicit .*
testcase_sub2 testcase_sub2 (.*,
// Outputs
.sub_out (sub_out[testcase_pkg::SIZE-1:0]), // Implicit .*
// Inputs
.sub_enum (sub_enum), // Implicit .*
.sub_in (sub_in[testcase_pkg::SIZE-1:0])); // Implicit .*
endmodule
module testcase_sub1
(
input testcase_pkg::enum_t top_enum,
output testcase_pkg::enum_t sub_enum,
output logic [testcase_pkg::SIZE-1:0] sub_in
);
import testcase_pkg::*;
assign sub_enum = top_enum;
assign sub_in = '1;
endmodule
module testcase_sub2
(
input testcase_pkg::enum_t sub_enum,
input logic [testcase_pkg::SIZE-1:0] sub_in,
output logic [testcase_pkg::SIZE-1:0] sub_out
);
import testcase_pkg::*;
assign sub_out = (sub_enum==ENUM1) ? ~sub_in : sub_in;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// verilog-auto-star-save: t
// End:
|
//#############################################################################
//# Purpose: Clock divider with 2 outputs #
// Secondary clock must be multiple of first clock #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockdiv
(
//inputs
input clk, // main clock
input nreset, // async active low reset (from oh_rsync)
input clkchange, // indicates a parameter change
input clken, // clock enable
input [7:0] clkdiv, // [7:0]=period (0==bypass, 1=div/2, 2=div/3, etc)
input [15:0] clkphase0, // [7:0]=rising,[15:8]=falling
input [15:0] clkphase1, // [7:0]=rising,[15:8]=falling
//outputs
output clkout0, // primary output clock
output clkrise0, // rising edge match
output clkfall0, // falling edge match
output clkout1, // secondary output clock
output clkrise1, // rising edge match
output clkfall1, // falling edge match
output clkstable // clock is guaranteed to be stable
);
//regs
reg [7:0] counter;
reg clkout0_reg;
reg clkout1_reg;
reg clkout1_shift;
reg [2:0] period;
wire period_match;
wire [3:0] clk1_sel;
wire [3:0] clk1_sel_sh;
wire [1:0] clk0_sel;
wire [1:0] clk0_sel_sh;
//###########################################
//# CHANGE DETECT (count 8 periods)
//###########################################
always @ (posedge clk or negedge nreset)
if(!nreset)
period[2:0] <= 'b0;
else if (clkchange)
period[2:0] <='b0;
else if(period_match & ~clkstable)
period[2:0] <= period[2:0] +1'b1;
assign clkstable = (period[2:0]==3'b111);
//###########################################
//# CYCLE COUNTER
//###########################################
always @ (posedge clk or negedge nreset)
if (!nreset)
counter[7:0] <= 'b0;
else if(clken)
if(period_match)
counter[7:0] <= 'b0;
else
counter[7:0] <= counter[7:0] + 1'b1;
assign period_match = (counter[7:0]==clkdiv[7:0]);
//###########################################
//# RISING/FALLING EDGE SELECTORS
//###########################################
assign clkrise0 = (counter[7:0]==clkphase0[7:0]);
assign clkfall0 = (counter[7:0]==clkphase0[15:8]);
assign clkrise1 = (counter[7:0]==clkphase1[7:0]);
assign clkfall1 = (counter[7:0]==clkphase1[15:8]);
//###########################################
//# CLKOUT0
//###########################################
always @ (posedge clk or negedge nreset)
if(!nreset)
clkout0_reg <= 1'b0;
else if(clkrise0)
clkout0_reg <= 1'b1;
else if(clkfall0)
clkout0_reg <= 1'b0;
// clock mux
assign clk0_sel[1] = (clkdiv[7:0]==8'd0); // not implemented
assign clk0_sel[0] = ~(clkdiv[7:0]==8'd0);
// clock select needs to be stable high
oh_lat0 #(.DW(2))
latch_clk0 (.out (clk0_sel_sh[1:0]),
.clk (clk),
.in (clk0_sel[1:0]));
oh_clockmux #(.N(2))
oh_clockmux0 (.clkout(clkout0),
.en(clk0_sel[1:0]),
.clkin({clk, clkout0_reg}));
//###########################################
//# CLKOUT1
//###########################################
always @ (posedge clk or negedge nreset)
if(!nreset)
clkout1_reg <= 1'b0;
else if(clkrise1)
clkout1_reg <= 1'b1;
else if(clkfall1)
clkout1_reg <= 1'b0;
// creating divide by 2 shifted clock with negedge
always @ (negedge clk)
clkout1_shift <= clkout1_reg;
// clock mux
assign clk1_sel[3] = 1'b0; // not implemented
assign clk1_sel[2] = (clkdiv[7:0]==8'd0); // div1 (bypass)
assign clk1_sel[1] = (clkdiv[7:0]==8'd1); // div2 clock
assign clk1_sel[0] = |clkdiv[7:1]; // all others
// clock select needs to be stable high
oh_lat0 #(.DW(4))
latch_clk1 (.out (clk1_sel_sh[3:0]),
.clk (clk),
.in (clk1_sel[3:0]));
oh_clockmux #(.N(4))
oh_clockmux1 (.clkout(clkout1),
.en(clk1_sel[3:0]),
.clkin({1'b0, clk, clkout1_shift, clkout1_reg}));
endmodule // oh_clockdiv
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module fft16TB;
reg ED;
reg RST;
reg CLK;
reg START;
reg ifft;
wire [32-1:0] DIImag;
wire [32-1:0] DIReal;
wire [32+3:0] DOImag;
wire [32+3:0] DOReal;
wire RDY;
reg [4:0] count;
initial
begin
CLK = 1'b0;
forever #5 CLK = ~CLK;
end
initial
begin
ifft = 1'b0;
ED = 1'b1;
RST = 1'b0;
count = 0;
START = 1'b0;
#13 RST =1'b1;
#43 RST =1'b0;
#53 START =1'b1;
#12 START =1'b0;
end
reg [4:0] ct16;
always @(posedge CLK or posedge START)
if (ED) begin
if (START) ct16 = 7'b000_0000;
else ct16 = ct16+ 'd1;
end
wire [31:0] D_R,D_I;
READ_ROM32 UG( .ADDR(ct16) ,
.DATA_RE(D_R), .DATA_IM(D_I));
assign DIImag = D_I;
assign DIReal = D_R;
fft16 UUT(
.ED(ED),
.RST(RST),
.CLK(CLK),
.START(START),
.ifft(ifft),
.DIImag(DIImag),
.DIReal(DIReal),
.DOImag(DOImag),
.DOReal(DOReal),
.RDY(RDY));
always @(posedge RDY)
count <= 17;
always @(posedge CLK)
begin
if(count!=0)
begin
if(count!=17)
$display("count:%d result real:%d imag:%d",count,DOReal,DOImag);
count = count-1;
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: usb_rd_fifo_32x512.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module usb_rd_fifo_32x512 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
dcfifo_mixed_widths_component.lpm_numwords = 512,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 32,
dcfifo_mixed_widths_component.lpm_widthu = 9,
dcfifo_mixed_widths_component.lpm_widthu_r = 9,
dcfifo_mixed_widths_component.lpm_width_r = 32,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "ON",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL usb_rd_fifo_32x512.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL usb_rd_fifo_32x512.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL usb_rd_fifo_32x512.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL usb_rd_fifo_32x512.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL usb_rd_fifo_32x512_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL usb_rd_fifo_32x512_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This interface includes both the transmit and receive components -
// They both uses the same clock (sourced from the receiving side).
`timescale 1ns/100ps
module axi_ad9361_pnlb (
// device interface
clk,
adc_valid_in,
adc_data_in_i1,
adc_data_in_q1,
adc_data_in_i2,
adc_data_in_q2,
dac_valid_in,
dac_data_in_i1,
dac_data_in_q1,
dac_data_in_i2,
dac_data_in_q2,
// dac outputs
dac_valid,
dac_data_i1,
dac_data_q1,
dac_data_i2,
dac_data_q2,
// control signals
dac_lb_enb_i1,
dac_pn_enb_i1,
dac_lb_enb_q1,
dac_pn_enb_q1,
dac_lb_enb_i2,
dac_pn_enb_i2,
dac_lb_enb_q2,
dac_pn_enb_q2,
// status signals
adc_pn_oos_i1,
adc_pn_err_i1,
adc_pn_oos_q1,
adc_pn_err_q1,
adc_pn_oos_i2,
adc_pn_err_i2,
adc_pn_oos_q2,
adc_pn_err_q2);
// device interface
input clk;
input adc_valid_in;
input [11:0] adc_data_in_i1;
input [11:0] adc_data_in_q1;
input [11:0] adc_data_in_i2;
input [11:0] adc_data_in_q2;
input dac_valid_in;
input [11:0] dac_data_in_i1;
input [11:0] dac_data_in_q1;
input [11:0] dac_data_in_i2;
input [11:0] dac_data_in_q2;
// dac outputs
output dac_valid;
output [11:0] dac_data_i1;
output [11:0] dac_data_q1;
output [11:0] dac_data_i2;
output [11:0] dac_data_q2;
// control signals
input dac_lb_enb_i1;
input dac_pn_enb_i1;
input dac_lb_enb_q1;
input dac_pn_enb_q1;
input dac_lb_enb_i2;
input dac_pn_enb_i2;
input dac_lb_enb_q2;
input dac_pn_enb_q2;
// status signals
output adc_pn_oos_i1;
output adc_pn_err_i1;
output adc_pn_oos_q1;
output adc_pn_err_q1;
output adc_pn_oos_i2;
output adc_pn_err_i2;
output adc_pn_oos_q2;
output adc_pn_err_q2;
// internal registers
reg dac_valid_t = 'd0;
reg [23:0] dac_pn_i1 = 'd0;
reg [23:0] dac_pn_q1 = 'd0;
reg [23:0] dac_pn_i2 = 'd0;
reg [23:0] dac_pn_q2 = 'd0;
reg [11:0] dac_lb_i1 = 'd0;
reg [11:0] dac_lb_q1 = 'd0;
reg [11:0] dac_lb_i2 = 'd0;
reg [11:0] dac_lb_q2 = 'd0;
reg dac_valid = 'd0;
reg [11:0] dac_data_i1 = 'd0;
reg [11:0] dac_data_q1 = 'd0;
reg [11:0] dac_data_i2 = 'd0;
reg [11:0] dac_data_q2 = 'd0;
reg adc_valid_t = 'd0;
reg [11:0] adc_data_in_i1_d = 'd0;
reg [11:0] adc_data_in_q1_d = 'd0;
reg [11:0] adc_data_in_i2_d = 'd0;
reg [11:0] adc_data_in_q2_d = 'd0;
reg [23:0] adc_pn_data_i1 = 'd0;
reg [23:0] adc_pn_data_q1 = 'd0;
reg [23:0] adc_pn_data_i2 = 'd0;
reg [23:0] adc_pn_data_q2 = 'd0;
reg adc_pn_err_i1 = 'd0;
reg adc_pn_oos_i1 = 'd0;
reg [ 3:0] adc_pn_oos_count_i1 = 'd0;
reg adc_pn_err_q1 = 'd0;
reg adc_pn_oos_q1 = 'd0;
reg [ 3:0] adc_pn_oos_count_q1 = 'd0;
reg adc_pn_err_i2 = 'd0;
reg adc_pn_oos_i2 = 'd0;
reg [ 3:0] adc_pn_oos_count_i2 = 'd0;
reg adc_pn_err_q2 = 'd0;
reg adc_pn_oos_q2 = 'd0;
reg [ 3:0] adc_pn_oos_count_q2 = 'd0;
// internal signals
wire dac_valid_t_s;
wire adc_valid_t_s;
wire [23:0] adc_data_in_i1_s;
wire adc_pn_err_i1_s;
wire adc_pn_update_i1_s;
wire adc_pn_match_i1_s;
wire adc_pn_match_i1_z_s;
wire adc_pn_match_i1_d_s;
wire [23:0] adc_pn_data_i1_s;
wire [23:0] adc_data_in_q1_s;
wire adc_pn_err_q1_s;
wire adc_pn_update_q1_s;
wire adc_pn_match_q1_s;
wire adc_pn_match_q1_z_s;
wire adc_pn_match_q1_d_s;
wire [23:0] adc_pn_data_q1_s;
wire [23:0] adc_data_in_i2_s;
wire adc_pn_err_i2_s;
wire adc_pn_update_i2_s;
wire adc_pn_match_i2_s;
wire adc_pn_match_i2_z_s;
wire adc_pn_match_i2_d_s;
wire [23:0] adc_pn_data_i2_s;
wire [23:0] adc_data_in_q2_s;
wire adc_pn_err_q2_s;
wire adc_pn_update_q2_s;
wire adc_pn_match_q2_s;
wire adc_pn_match_q2_z_s;
wire adc_pn_match_q2_d_s;
wire [23:0] adc_pn_data_q2_s;
// prbs-9 function
function [23:0] pn09;
input [23:0] din;
reg [23:0] dout;
begin
dout[23] = din[ 8] ^ din[ 4];
dout[22] = din[ 7] ^ din[ 3];
dout[21] = din[ 6] ^ din[ 2];
dout[20] = din[ 5] ^ din[ 1];
dout[19] = din[ 4] ^ din[ 0];
dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[14] = din[ 8] ^ din[ 0];
dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
pn09 = dout;
end
endfunction
// prbs-11 function
function [23:0] pn11;
input [23:0] din;
reg [23:0] dout;
begin
dout[23] = din[10] ^ din[ 8];
dout[22] = din[ 9] ^ din[ 7];
dout[21] = din[ 8] ^ din[ 6];
dout[20] = din[ 7] ^ din[ 5];
dout[19] = din[ 6] ^ din[ 4];
dout[18] = din[ 5] ^ din[ 3];
dout[17] = din[ 4] ^ din[ 2];
dout[16] = din[ 3] ^ din[ 1];
dout[15] = din[ 2] ^ din[ 0];
dout[14] = din[ 1] ^ din[10] ^ din[ 8];
dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
dout[12] = din[10] ^ din[ 6];
dout[11] = din[ 9] ^ din[ 5];
dout[10] = din[ 8] ^ din[ 4];
dout[ 9] = din[ 7] ^ din[ 3];
dout[ 8] = din[ 6] ^ din[ 2];
dout[ 7] = din[ 5] ^ din[ 1];
dout[ 6] = din[ 4] ^ din[ 0];
dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
pn11 = dout;
end
endfunction
// prbs-15 function
function [23:0] pn15;
input [23:0] din;
reg [23:0] dout;
begin
dout[23] = din[14] ^ din[13];
dout[22] = din[13] ^ din[12];
dout[21] = din[12] ^ din[11];
dout[20] = din[11] ^ din[10];
dout[19] = din[10] ^ din[ 9];
dout[18] = din[ 9] ^ din[ 8];
dout[17] = din[ 8] ^ din[ 7];
dout[16] = din[ 7] ^ din[ 6];
dout[15] = din[ 6] ^ din[ 5];
dout[14] = din[ 5] ^ din[ 4];
dout[13] = din[ 4] ^ din[ 3];
dout[12] = din[ 3] ^ din[ 2];
dout[11] = din[ 2] ^ din[ 1];
dout[10] = din[ 1] ^ din[ 0];
dout[ 9] = din[ 0] ^ din[14] ^ din[13];
dout[ 8] = din[14] ^ din[12];
dout[ 7] = din[13] ^ din[11];
dout[ 6] = din[12] ^ din[10];
dout[ 5] = din[11] ^ din[ 9];
dout[ 4] = din[10] ^ din[ 8];
dout[ 3] = din[ 9] ^ din[ 7];
dout[ 2] = din[ 8] ^ din[ 6];
dout[ 1] = din[ 7] ^ din[ 5];
dout[ 0] = din[ 6] ^ din[ 4];
pn15 = dout;
end
endfunction
// prbs-20 function
function [23:0] pn20;
input [23:0] din;
reg [23:0] dout;
begin
dout[23] = din[19] ^ din[ 2];
dout[22] = din[18] ^ din[ 1];
dout[21] = din[17] ^ din[ 0];
dout[20] = din[16] ^ din[19] ^ din[ 2];
dout[19] = din[15] ^ din[18] ^ din[ 1];
dout[18] = din[14] ^ din[17] ^ din[ 0];
dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
pn20 = dout;
end
endfunction
// prbs generators run at 24bits wide
assign dac_valid_t_s = dac_valid_in & dac_valid_t;
always @(posedge clk) begin
if (dac_valid_in == 1'b1) begin
dac_valid_t <= ~dac_valid_t;
end
if (dac_pn_enb_i1 == 1'b0) begin
dac_pn_i1 <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn_i1 <= pn09(dac_pn_i1);
end
if (dac_pn_enb_q1 == 1'b0) begin
dac_pn_q1 <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn_q1 <= pn11(dac_pn_q1);
end
if (dac_pn_enb_i2 == 1'b0) begin
dac_pn_i2 <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn_i2 <= pn15(dac_pn_i2);
end
if (dac_pn_enb_q2 == 1'b0) begin
dac_pn_q2 <= 24'hffffff;
end else if (dac_valid_t_s == 1'b1) begin
dac_pn_q2 <= pn20(dac_pn_q2);
end
end
// hold adc data for loopback, it is assumed that there is a one to one mapping
// of receive and transmit (the rates are the same).
always @(posedge clk) begin
if (adc_valid_in == 1'b1) begin
dac_lb_i1 <= adc_data_in_i1;
dac_lb_q1 <= adc_data_in_q1;
dac_lb_i2 <= adc_data_in_i2;
dac_lb_q2 <= adc_data_in_q2;
end
end
// dac outputs-
always @(posedge clk) begin
dac_valid <= dac_valid_in;
if (dac_pn_enb_i1 == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data_i1 <= dac_pn_i1[11:0];
end else begin
dac_data_i1 <= dac_pn_i1[23:12];
end
end else if (dac_lb_enb_i1 == 1'b1) begin
dac_data_i1 <= dac_lb_i1;
end else begin
dac_data_i1 <= dac_data_in_i1;
end
if (dac_pn_enb_q1 == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data_q1 <= dac_pn_q1[11:0];
end else begin
dac_data_q1 <= dac_pn_q1[23:12];
end
end else if (dac_lb_enb_q1 == 1'b1) begin
dac_data_q1 <= dac_lb_q1;
end else begin
dac_data_q1 <= dac_data_in_q1;
end
if (dac_pn_enb_i2 == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data_i2 <= dac_pn_i2[11:0];
end else begin
dac_data_i2 <= dac_pn_i2[23:12];
end
end else if (dac_lb_enb_i2 == 1'b1) begin
dac_data_i2 <= dac_lb_i2;
end else begin
dac_data_i2 <= dac_data_in_i2;
end
if (dac_pn_enb_q2 == 1'b1) begin
if (dac_valid_t == 1'b1) begin
dac_data_q2 <= dac_pn_q2[11:0];
end else begin
dac_data_q2 <= dac_pn_q2[23:12];
end
end else if (dac_lb_enb_q2 == 1'b1) begin
dac_data_q2 <= dac_lb_q2;
end else begin
dac_data_q2 <= dac_data_in_q2;
end
end
// adc pn monitoring
assign adc_valid_t_s = adc_valid_in & adc_valid_t;
assign adc_data_in_i1_s = {adc_data_in_i1_d, adc_data_in_i1};
assign adc_pn_err_i1_s = ~(adc_pn_oos_i1 | adc_pn_match_i1_s);
assign adc_pn_update_i1_s = ~(adc_pn_oos_i1 ^ adc_pn_match_i1_s);
assign adc_pn_match_i1_s = adc_pn_match_i1_d_s & adc_pn_match_i1_z_s;
assign adc_pn_match_i1_z_s = (adc_data_in_i1_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_i1_d_s = (adc_data_in_i1_s == adc_pn_data_i1) ? 1'b1 : 1'b0;
assign adc_pn_data_i1_s = (adc_pn_oos_i1 == 1'b1) ? adc_data_in_i1_s : adc_pn_data_i1;
assign adc_data_in_q1_s = {adc_data_in_q1_d, adc_data_in_q1};
assign adc_pn_err_q1_s = ~(adc_pn_oos_q1 | adc_pn_match_q1_s);
assign adc_pn_update_q1_s = ~(adc_pn_oos_q1 ^ adc_pn_match_q1_s);
assign adc_pn_match_q1_s = adc_pn_match_q1_d_s & adc_pn_match_q1_z_s;
assign adc_pn_match_q1_z_s = (adc_data_in_q1_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_q1_d_s = (adc_data_in_q1_s == adc_pn_data_q1) ? 1'b1 : 1'b0;
assign adc_pn_data_q1_s = (adc_pn_oos_q1 == 1'b1) ? adc_data_in_q1_s : adc_pn_data_q1;
assign adc_data_in_i2_s = {adc_data_in_i2_d, adc_data_in_i2};
assign adc_pn_err_i2_s = ~(adc_pn_oos_i2 | adc_pn_match_i2_s);
assign adc_pn_update_i2_s = ~(adc_pn_oos_i2 ^ adc_pn_match_i2_s);
assign adc_pn_match_i2_s = adc_pn_match_i2_d_s & adc_pn_match_i2_z_s;
assign adc_pn_match_i2_z_s = (adc_data_in_i2_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_i2_d_s = (adc_data_in_i2_s == adc_pn_data_i2) ? 1'b1 : 1'b0;
assign adc_pn_data_i2_s = (adc_pn_oos_i2 == 1'b1) ? adc_data_in_i2_s : adc_pn_data_i2;
assign adc_data_in_q2_s = {adc_data_in_q2_d, adc_data_in_q2};
assign adc_pn_err_q2_s = ~(adc_pn_oos_q2 | adc_pn_match_q2_s);
assign adc_pn_update_q2_s = ~(adc_pn_oos_q2 ^ adc_pn_match_q2_s);
assign adc_pn_match_q2_s = adc_pn_match_q2_d_s & adc_pn_match_q2_z_s;
assign adc_pn_match_q2_z_s = (adc_data_in_q2_s == 24'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_q2_d_s = (adc_data_in_q2_s == adc_pn_data_q2) ? 1'b1 : 1'b0;
assign adc_pn_data_q2_s = (adc_pn_oos_q2 == 1'b1) ? adc_data_in_q2_s : adc_pn_data_q2;
// adc pn running sequence
always @(posedge clk) begin
if (adc_valid_in == 1'b1) begin
adc_valid_t <= ~adc_valid_t;
adc_data_in_i1_d <= adc_data_in_i1;
adc_data_in_q1_d <= adc_data_in_q1;
adc_data_in_i2_d <= adc_data_in_i2;
adc_data_in_q2_d <= adc_data_in_q2;
end
if (adc_valid_t_s == 1'b1) begin
adc_pn_data_i1 <= pn09(adc_pn_data_i1_s);
adc_pn_data_q1 <= pn11(adc_pn_data_q1_s);
adc_pn_data_i2 <= pn15(adc_pn_data_i2_s);
adc_pn_data_q2 <= pn20(adc_pn_data_q2_s);
end
end
// pn oos and counters (16 to clear and set).
always @(posedge clk) begin
if (adc_valid_t_s == 1'b1) begin
adc_pn_err_i1 <= adc_pn_err_i1_s;
if ((adc_pn_update_i1_s == 1'b1) && (adc_pn_oos_count_i1 >= 15)) begin
adc_pn_oos_i1 <= ~adc_pn_oos_i1;
end
if (adc_pn_update_i1_s == 1'b1) begin
adc_pn_oos_count_i1 <= adc_pn_oos_count_i1 + 1'b1;
end else begin
adc_pn_oos_count_i1 <= 'd0;
end
adc_pn_err_q1 <= adc_pn_err_q1_s;
if ((adc_pn_update_q1_s == 1'b1) && (adc_pn_oos_count_q1 >= 15)) begin
adc_pn_oos_q1 <= ~adc_pn_oos_q1;
end
if (adc_pn_update_q1_s == 1'b1) begin
adc_pn_oos_count_q1 <= adc_pn_oos_count_q1 + 1'b1;
end else begin
adc_pn_oos_count_q1 <= 'd0;
end
adc_pn_err_i2 <= adc_pn_err_i2_s;
if ((adc_pn_update_i2_s == 1'b1) && (adc_pn_oos_count_i2 >= 15)) begin
adc_pn_oos_i2 <= ~adc_pn_oos_i2;
end
if (adc_pn_update_i2_s == 1'b1) begin
adc_pn_oos_count_i2 <= adc_pn_oos_count_i2 + 1'b1;
end else begin
adc_pn_oos_count_i2 <= 'd0;
end
adc_pn_err_q2 <= adc_pn_err_q2_s;
if ((adc_pn_update_q2_s == 1'b1) && (adc_pn_oos_count_q2 >= 15)) begin
adc_pn_oos_q2 <= ~adc_pn_oos_q2;
end
if (adc_pn_update_q2_s == 1'b1) begin
adc_pn_oos_count_q2 <= adc_pn_oos_count_q2 + 1'b1;
end else begin
adc_pn_oos_count_q2 <= 'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -*- Mode: Verilog -*-
// Filename : uart_tasks.v
// Description : UART Tasks
// Author : Philip Tracton
// Created On : Mon Apr 20 16:12:43 2015
// Last Modified By: Philip Tracton
// Last Modified On: Mon Apr 20 16:12:43 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
`include "simulation_includes.vh"
module uart_tasks;
// Configure WB UART in testbench
// 115200, 8N1
//
task uart_config;
begin
$display("\033[93mTASK: UART Configure\033[0m");
@(posedge `UART_CLK);
//Turn on receive data interrupt
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00010000);
@(posedge `UART_CLK);
//FIFO Control, interrupt for each byte, clear fifos and enable
`UART_MASTER0.wb_wr1(32'hFFFF0002, 4'h2, 32'h00000700);
@(posedge `UART_CLK);
//Line Control, enable writting to the baud rate registers
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000080);
@(posedge `UART_CLK);
//Baud Rate LSB
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h0000001A); //115200bps from 50 MHz
@(posedge `UART_CLK);
//Baud Rate MSB
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00000000);
@(posedge `UART_CLK);
//Line Control, 8 bits data, 1 stop bit, no parity
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000003);
end
endtask // uart_config
//
// Write a character to WB UART and catch with FPGA UART
//
task uart_write_char;
input [7:0] char;
begin
//
// Write the character to the WB UART to send to FPGA UART
//
@(posedge `UART_CLK);
$display("TASK: UART Write = %c @ %d", char, $time);
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h8, {char, 24'h000000});
end
endtask // uart_write_char
//
// Read a character with WB UART that was sent from FPGA UART
//
task uart_read_char;
input [7:0] expected;
begin
$display("Reading 0x%x @ %d", expected, $time);
if (!testbench.uart0_int)
@(posedge testbench.uart0_int);
`UART_MASTER0.wb_rd1(32'hFFFF0000, 4'h8, testbench.read_word);
$display("TASK: UART Read = %c @ %d", testbench.read_word[31:24], $time);
if (testbench.read_word[31:24] !== expected)
begin
$display("\033[1;31mFAIL: UART Read = 0x%h NOT 0x%h @ %d\033[0m", testbench.read_word[31:24], expected, $time);
`TEST_FAILED <= 1;
end
@(posedge testbench.wb_clk);
end
endtask // uart_read_char
endmodule // uart_tasks
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLRTP_PP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTP_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: write_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of write path .
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
wr_data_gen #(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_SYMBOL_V
`define SKY130_FD_SC_HVL__DIODE_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_SYMBOL_V
|
module helloworld #(parameter CLOCK_FREQ = 12000000, parameter BAUD_RATE = 115200)
(
input ext_clock,
output uart_tx_pin,
output uart_tx_led,
output uart_clock_led);
wire reset;
wire [47:0] write_data;
/* ring buffer */
wire read_clock_enable;
wire write_clock_enable;
wire empty;
wire overflow;
/* mem2serial */
wire [47:0] read_data;
/* uart tx */
wire uart_ready;
wire [7:0] uart_data;
wire uart_clock_enable;
wire uart_clock;
wire [47:0] read_data_static;
wire empty_static;
power_on_reset POR(
.clock(ext_clock),
.reset(reset));
/* write hello world */
helloworldwriter HELLOWORLDWRITER(
.clock(ext_clock),
.reset(reset),
.overflow(overflow),
.out_data(write_data),
.out_clock_enable(write_clock_enable));
ringbuffer #(.AW(10), .DW(48))
RINGBUFFER (
.reset(reset),
.clock(ext_clock),
.write_clock_enable(write_clock_enable),
.read_clock_enable(read_clock_enable),
.read_data(read_data),
.write_data(write_data),
.empty(empty),
.overflow(overflow));
mem2serial MEM_SERIAL(
.reset(reset),
.clock(ext_clock),
.read_empty(empty),
.read_clock_enable(read_clock_enable),
.read_data(read_data),
.uart_clock_enable(uart_clock_enable),
.uart_ready(uart_ready),
.uart_data(uart_data));
uart_tx #(.CLOCK_FREQ(CLOCK_FREQ), .BAUD_RATE(BAUD_RATE))
SERIAL (.read_data(uart_data),
.read_clock_enable(uart_clock_enable),
.reset(reset),
.ready(uart_ready),
.tx(uart_tx_pin),
.clock(ext_clock),
.uart_clock(uart_clock));
assign uart_tx_led = uart_tx_pin;
assign uart_clock_led = uart_clock;
endmodule
|
module peripheral_audio(clk , rst , d_in , cs,wr,rd , addr, d_out, mclk, ledres, micLRSel,micData );
input clk;
input rst;
input [15:0] d_in;
input cs;
input wr;
input rd;
input [3:0]addr; // 4 LSB from j1_io_addr
output reg [15:0]d_out;
output ledres;
output mclk;
output micLRSel;
input micData;
wire doutmic;
wire full;
wire empty;
reg enable;
//------------------------------------ regs and wires-------------------------------
reg [2:0] s; //selector mux_4 and demux_4
//------------------------------------ regs and wires-------------------------------
microfono mic(.reset(rst),.clk(clk),.micLRSel(micLRSel),.empty(empty),.mclk(mclk),.micData(micData),.ledres(ledres),.enable(enable),.full(full));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 3'b001 : 3'b000 ;end //enable
4'h2:begin s = (cs && rd) ? 3'b010 : 3'b000 ;end //full
4'h4:begin s = (cs && rd) ? 3'b100 : 3'b000 ;end //empty
4'h8:begin s = (cs && rd) ? 3'b111 : 3'b000 ;end //dout
default:begin s=3'b000 ; end
endcase
end//-----------------address_decoder--------------------
always @(negedge clk) begin//-------------------- escritura de registros
if (s[0]==1) begin
enable=1;
end
else begin
enable=0;
end
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
3'b010: d_out[0]= full;
3'b100: d_out[0]= empty;
3'b111: d_out[0]= dout;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:46:53 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_1/system_ov7670_vga_0_1_sim_netlist.v
// Design : system_ov7670_vga_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_vga_0_1,ov7670_vga,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_vga,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_vga_0_1
(pclk,
data,
rgb);
input pclk;
input [7:0]data;
output [15:0]rgb;
wire [7:0]data;
wire pclk;
wire [15:0]rgb;
system_ov7670_vga_0_1_ov7670_vga U0
(.data(data),
.pclk(pclk),
.rgb(rgb));
endmodule
(* ORIG_REF_NAME = "ov7670_vga" *)
module system_ov7670_vga_0_1_ov7670_vga
(rgb,
pclk,
data);
output [15:0]rgb;
input pclk;
input [7:0]data;
wire cycle;
wire [7:0]data;
wire p_0_in0;
wire pclk;
wire [15:0]rgb;
FDRE #(
.INIT(1'b0))
cycle_reg
(.C(pclk),
.CE(1'b1),
.D(p_0_in0),
.Q(cycle),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\rgb[15]_i_1
(.I0(cycle),
.O(p_0_in0));
FDRE \rgb_reg[0]
(.C(pclk),
.CE(cycle),
.D(data[0]),
.Q(rgb[0]),
.R(1'b0));
FDRE \rgb_reg[10]
(.C(pclk),
.CE(p_0_in0),
.D(data[2]),
.Q(rgb[10]),
.R(1'b0));
FDRE \rgb_reg[11]
(.C(pclk),
.CE(p_0_in0),
.D(data[3]),
.Q(rgb[11]),
.R(1'b0));
FDRE \rgb_reg[12]
(.C(pclk),
.CE(p_0_in0),
.D(data[4]),
.Q(rgb[12]),
.R(1'b0));
FDRE \rgb_reg[13]
(.C(pclk),
.CE(p_0_in0),
.D(data[5]),
.Q(rgb[13]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(pclk),
.CE(p_0_in0),
.D(data[6]),
.Q(rgb[14]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(pclk),
.CE(p_0_in0),
.D(data[7]),
.Q(rgb[15]),
.R(1'b0));
FDRE \rgb_reg[1]
(.C(pclk),
.CE(cycle),
.D(data[1]),
.Q(rgb[1]),
.R(1'b0));
FDRE \rgb_reg[2]
(.C(pclk),
.CE(cycle),
.D(data[2]),
.Q(rgb[2]),
.R(1'b0));
FDRE \rgb_reg[3]
(.C(pclk),
.CE(cycle),
.D(data[3]),
.Q(rgb[3]),
.R(1'b0));
FDRE \rgb_reg[4]
(.C(pclk),
.CE(cycle),
.D(data[4]),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[5]
(.C(pclk),
.CE(cycle),
.D(data[5]),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[6]
(.C(pclk),
.CE(cycle),
.D(data[6]),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[7]
(.C(pclk),
.CE(cycle),
.D(data[7]),
.Q(rgb[7]),
.R(1'b0));
FDRE \rgb_reg[8]
(.C(pclk),
.CE(p_0_in0),
.D(data[0]),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[9]
(.C(pclk),
.CE(p_0_in0),
.D(data[1]),
.Q(rgb[9]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
-- ============================================================================
-- FILE NAME : uart.v
-- DESCRIPTION : Universal Asynchronous Receiver and Transmitter
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ???????
-- ============================================================================
*/
/********** ?????a???????? **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ???e??a???????? **********/
`include "uart.h"
/********** ????`?? **********/
module uart (
/********** ????a? & ???a? **********/
input wire clk, // ????a?
input wire reset, // ???????a?
/********** ?V?????????`?? **********/
input wire cs_, // ???a??????
input wire as_, // ??????????`??
input wire rw, // Read / Write
input wire [`UartAddrBus] addr, // ?????
input wire [`WordDataBus] wr_data, // ?????z???`??
output wire [`WordDataBus] rd_data, // ?i???????`??
output wire rdy_, // ????
/********** ????z?? **********/
output wire irq_rx, // ???????????z??
output wire irq_tx, // ???????????z??
/********** UART????????? **********/
input wire rx, // UART???????
output wire tx // UART???????
);
/********** ??????? **********/
// ????????
wire rx_busy; // ?????V??
wire rx_end; // ???????????
wire [`ByteDataBus] rx_data; // ?????`??
// ????????
wire tx_busy; // ?????V??
wire tx_end; // ???????????
wire tx_start; // ?????_????
wire [`ByteDataBus] tx_data; // ?????`??
/********** UART????????`?? **********/
uart_ctrl uart_ctrl (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** Host Interface **********/
.cs_ (cs_), // ???a??????
.as_ (as_), // ??????????`??
.rw (rw), // Read / Write
.addr (addr), // ?????
.wr_data (wr_data), // ?????z???`??
.rd_data (rd_data), // ?i???????`??
.rdy_ (rdy_), // ????
/********** Interrupt **********/
.irq_rx (irq_rx), // ???????????z??
.irq_tx (irq_tx), // ???????????z??
/********** ??????? **********/
// ????????
.rx_busy (rx_busy), // ?????V??
.rx_end (rx_end), // ???????????
.rx_data (rx_data), // ?????`??
// ????????
.tx_busy (tx_busy), // ?????V??
.tx_end (tx_end), // ???????????
.tx_start (tx_start), // ?????_????
.tx_data (tx_data) // ?????`??
);
/********** UART???????`?? **********/
uart_tx uart_tx (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** ??????? **********/
.tx_start (tx_start), // ?????_????
.tx_data (tx_data), // ?????`??
.tx_busy (tx_busy), // ?????V??
.tx_end (tx_end), // ???????????
/********** Transmit Signal **********/
.tx (tx) // UART???????
);
/********** UART???????`?? **********/
uart_rx uart_rx (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** ??????? **********/
.rx_busy (rx_busy), // ?????V??
.rx_end (rx_end), // ???????????
.rx_data (rx_data), // ?????`??
/********** Receive Signal **********/
.rx (rx) // UART???????
);
endmodule
|
/*
*******************************************************************************
* File Name : ada_iaif_stage.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 8th, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Pipeline register: from Instruction Address to Instruction
* Fetch
*******************************************************************************
*/
`include "ada_defines.v"
module ada_iaif_stage(
input clk, // main clock
input rst, // main reset
input [31:0] pc_in, // New PC.
input if_stall, // Stall signal
output reg [31:0] pc_out // PC to IF stage
);
//--------------------------------------------------------------------------
// A simple register
// Do not update PC if IF stage is stalled.
//--------------------------------------------------------------------------
always @(posedge clk ) begin
pc_out <= (rst) ? `ADA_RESET_DEFAULT : ((if_stall) ? pc_out : pc_in);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/10 16:14:27
// Design Name:
// Module Name: lab5_1_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab5_1_1(
input ain,clk,reset,
output reg [3:0] count,
output reg yout
);
reg [1:0] state,nextstate;
parameter S0 = 0,S1 = 1,S2 = 2,S3 = 3;
initial
begin
nextstate = S2;
end
always @(posedge clk)
begin
if(reset)
begin
count = 4'b0000;
state = S0;
end
else
begin
if(ain)
begin
if(count == 15)
begin
count = 0;
state = S0;
end
else
begin
count = count + 1;
state = nextstate;
end
end
end
end
always @(state or ain or reset)
begin
yout = 1'b0;
case(state)
S0: if((~ain) & (~reset))
yout = 1;
S1: if(ain & (~reset))
yout = 1;
default: yout = 1'b0;
endcase
end
always @(state or ain)
begin
case(state)
S0:
begin
if(ain)
nextstate = S2;
else
nextstate = S0;
end
S1:
begin
if(ain)
nextstate = S2;
else
nextstate = S1;
end
S2:
begin
if(ain)
nextstate = S3;
else
nextstate = S2;
end
S3:
begin
if(ain)
nextstate = S1;
else
nextstate = S3;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_2_V
`define SKY130_FD_SC_LS__NOR2_2_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_2_V
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pwm_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module pwm_pll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.030000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.03000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pwm_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5000"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_BEHAVIORAL_PP_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s50 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_BEHAVIORAL_PP_V |
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* #################################### *)
(** * Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
Y ::= ANum 0;;
WHILE BNot (BEq (AId X) (ANum 0)) DO
Y ::= APlus (AId Y) (AId X);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** * Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case;
try (exists 1; simpl; reflexivity).
Case "E_Ass".
exists 1. simpl. rewrite H. reflexivity.
Case "E_Seq".
inversion IHHce1 as [i1 H1].
inversion IHHce2 as [i2 H2].
exists (S (i1 + i2)).
simpl.
apply ceval_step_more with (i2:=i1 + i2) in H1.
apply ceval_step_more with (i2:=i1 + i2) in H2.
rewrite H1.
apply H2.
omega.
omega.
Case "E_IfTrue".
inversion IHHce as [i He].
exists (S i).
simpl. rewrite H. assumption.
Case "E_IfFalse".
inversion IHHce as [i He].
exists (S i).
simpl. rewrite H. assumption.
Case "E_WhileEnd".
exists 1. simpl. rewrite H. reflexivity.
Case "E_WhileLoop".
inversion IHHce1 as [i1 H1].
inversion IHHce2 as [i2 H2].
exists (S (i1 + i2)).
simpl.
rewrite H.
apply ceval_step_more with (i2:=i1+i2) in H1.
apply ceval_step_more with (i2:=i1+i2) in H2.
rewrite H1.
rewrite H2.
reflexivity.
omega.
omega.
Qed.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** * Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
output wire [95 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
output wire [11 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
input wire [95 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(3),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(192'H000000004280000000000000404000000000000043c00000),
.C_M_AXI_ADDR_WIDTH(96'H000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(96'H000000010000000100000001),
.C_M_AXI_READ_ISSUING(96'H000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(96'H000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(3'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(3'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(3'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(3'H7),
.m_axi_ruser(3'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
// Note; 1) Please include "+define+ OEb" in running script if you want to check
// timing in the case of OE_ being set.
// 2) Please specify access time by defining tAC_10 or tAC_12.
`define OEb
`define tAC_10 //tAC_10 or tAC_12 defines different parameters
`timescale 1ns/1ns
module IS61LV25616 (A, IO, CE_, OE_, WE_, LB_, UB_);
parameter dqbits = 16;
parameter memdepth = 262143;
parameter addbits = 18;
parameter Toha = 2;
parameter Tsa = 2;
`ifdef tAC_10 //if "`define tAC_10 " at beginning,sentences below are compiled
parameter Taa = 10,
Thzce = 3,
Thzwe = 5;
`endif
`ifdef tAC_12 //if "`define tAC_12 " at beginning,sentences below are compiled
parameter Taa = 12,
Thzce = 5,
Thzwe = 6;
`endif
input CE_, OE_, WE_, LB_, UB_;
input [(addbits - 1) : 0] A;
inout [(dqbits - 1) : 0] IO;
wire [(dqbits - 1) : 0] dout;
reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
//array to simulate SRAM
// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
wire r_en = WE_ & (~CE_) & (~OE_); //WE=1,CE=OE=0 Read
wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_)); //WE=CE=0,LB or UB="0",OE=x Write
assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
initial
$timeformat (-9, 0.1, " ns", 10); //show current simulation time
assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
always @(A or w_en)
begin
#Tsa //address setup time
if (w_en)
#Thzwe
begin
bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
end
end
// Timing Check
`ifdef tAC_10
specify //sepcify delay
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 10,
tPWE1 = 8,
tPBW = 8;
`else
`ifdef tAC_12
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 12,
tPWE1 = 8,
tPBW = 8;
`endif
`endif
$setup (A, negedge CE_, tSA);
$setup (A, posedge CE_, tAW);
$setup (IO, posedge CE_, tSD);
$setup (A, negedge WE_, tSA);
$setup (IO, posedge WE_, tSD);
$setup (A, negedge LB_, tSA);
$setup (A, negedge UB_, tSA);
$width (negedge CE_, tSCE);
$width (negedge LB_, tPBW);
$width (negedge UB_, tPBW);
`ifdef OEb
$width (negedge WE_, tPWE1);
`else
$width (negedge WE_, tPWE2);
`endif
endspecify
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_BLACKBOX_V
`define SKY130_FD_SC_HD__O311A_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_BLACKBOX_V
|
//# 3 inputs
//# 6 outputs
//# 14 D-type flipflops
//# 44 inverters
//# 75 gates (31 ANDs + 9 NANDs + 16 ORs + 19 NORs)
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule
module s298(GND,VDD,CK,G0,G1,G117,G118,G132,G133,G2,G66,G67);
input GND,VDD,CK,G0,G1,G2;
output G117,G132,G66,G118,G133,G67;
wire G10,G29,G11,G30,G12,G34,G13,G39,G14,G44,G15,G56,G16,G86,G17,G92,G18,G98,
G19,G102,G20,G107,G21,G113,G22,G119,G23,G125,G28,G130,G38,G40,G45,G46,G50,
G51,G54,G55,G59,G60,G64,II155,II158,G76,G82,G87,G91,G93,G96,G99,G103,G108,
G112,G114,II210,II213,G120,G124,G121,II221,G126,G131,G127,II229,II232,
II235,II238,G26,G27,G31,G32,G33,G35,G36,G37,G42,G41,G48,G47,G49,G52,G57,
G61,G58,G65,G62,G63,G74,G75,G88,G89,G90,G94,G95,G100,G105,G104,G110,G109,
G111,G115,G122,G123,G128,G129,G24,G25,G68,G69,G70,G71,G72,G73,G77,G78,G79,
G80,G81,G83,G84,G85,G43,G97,G101,G106,G116,G53;
dff DFF_0(CK,G10,G29);
dff DFF_1(CK,G11,G30);
dff DFF_2(CK,G12,G34);
dff DFF_3(CK,G13,G39);
dff DFF_4(CK,G14,G44);
dff DFF_5(CK,G15,G56);
dff DFF_6(CK,G16,G86);
dff DFF_7(CK,G17,G92);
dff DFF_8(CK,G18,G98);
dff DFF_9(CK,G19,G102);
dff DFF_10(CK,G20,G107);
dff DFF_11(CK,G21,G113);
dff DFF_12(CK,G22,G119);
dff DFF_13(CK,G23,G125);
not NOT_0(G28,G130);
not NOT_1(G38,G10);
not NOT_2(G40,G13);
not NOT_3(G45,G12);
not NOT_4(G46,G11);
not NOT_5(G50,G14);
not NOT_6(G51,G23);
not NOT_7(G54,G11);
not NOT_8(G55,G13);
not NOT_9(G59,G12);
not NOT_10(G60,G22);
not NOT_11(G64,G15);
not NOT_12(II155,G16);
not NOT_13(G66,II155);
not NOT_14(II158,G17);
not NOT_15(G67,II158);
not NOT_16(G76,G10);
not NOT_17(G82,G11);
not NOT_18(G87,G16);
not NOT_19(G91,G12);
not NOT_20(G93,G17);
not NOT_21(G96,G14);
not NOT_22(G99,G18);
not NOT_23(G103,G13);
not NOT_24(G108,G112);
not NOT_25(G114,G21);
not NOT_26(II210,G18);
not NOT_27(G117,II210);
not NOT_28(II213,G19);
not NOT_29(G118,II213);
not NOT_30(G120,G124);
not NOT_31(G121,G22);
not NOT_32(II221,G2);
not NOT_33(G124,II221);
not NOT_34(G126,G131);
not NOT_35(G127,G23);
not NOT_36(II229,G0);
not NOT_37(G130,II229);
not NOT_38(II232,G1);
not NOT_39(G131,II232);
not NOT_40(II235,G20);
not NOT_41(G132,II235);
not NOT_42(II238,G21);
not NOT_43(G133,II238);
and AND2_0(G26,G28,G50);
and AND2_1(G27,G51,G28);
and AND3_0(G31,G10,G45,G13);
and AND2_2(G32,G10,G11);
and AND2_3(G33,G38,G46);
and AND3_1(G35,G10,G11,G12);
and AND2_4(G36,G38,G45);
and AND2_5(G37,G46,G45);
and AND2_6(G42,G40,G41);
and AND4_0(G48,G45,G46,G10,G47);
and AND3_2(G49,G50,G51,G52);
and AND4_1(G57,G59,G11,G60,G61);
and AND2_7(G58,G64,G65);
and AND4_2(G62,G59,G11,G60,G61);
and AND2_8(G63,G64,G65);
and AND3_3(G74,G12,G14,G19);
and AND3_4(G75,G82,G91,G14);
and AND2_9(G88,G14,G87);
and AND2_10(G89,G103,G96);
and AND2_11(G90,G91,G103);
and AND2_12(G94,G93,G13);
and AND2_13(G95,G96,G13);
and AND3_5(G100,G99,G14,G12);
and AND3_6(G105,G103,G108,G104);
and AND2_14(G110,G108,G109);
and AND2_15(G111,G10,G112);
and AND2_16(G115,G114,G14);
and AND2_17(G122,G120,G121);
and AND2_18(G123,G124,G22);
and AND2_19(G128,G126,G127);
and AND2_20(G129,G131,G23);
or OR4_0(G24,G38,G46,G45,G40);
or OR3_0(G25,G38,G11,G12);
or OR4_1(G68,G11,G12,G13,G96);
or OR2_0(G69,G103,G18);
or OR2_1(G70,G103,G14);
or OR3_1(G71,G82,G12,G13);
or OR2_2(G72,G91,G20);
or OR2_3(G73,G103,G20);
or OR4_2(G77,G112,G103,G96,G19);
or OR2_4(G78,G108,G76);
or OR2_5(G79,G103,G14);
or OR2_6(G80,G11,G14);
or OR2_7(G81,G12,G13);
or OR4_3(G83,G11,G12,G13,G96);
or OR3_2(G84,G82,G91,G14);
or OR3_3(G85,G91,G96,G17);
nand NAND3_0(G41,G12,G11,G10);
nand NAND3_1(G43,G24,G25,G28);
nand NAND4_0(G52,G13,G45,G46,G10);
nand NAND4_1(G65,G59,G54,G22,G61);
nand NAND4_2(G97,G83,G84,G85,G108);
nand NAND4_3(G101,G68,G69,G70,G108);
nand NAND2_0(G106,G77,G78);
nand NAND4_4(G109,G71,G72,G73,G14);
nand NAND4_5(G116,G79,G80,G81,G108);
nor NOR2_0(G29,G10,G130);
nor NOR4_0(G30,G31,G32,G33,G130);
nor NOR4_1(G34,G35,G36,G37,G130);
nor NOR2_1(G39,G42,G43);
nor NOR3_0(G44,G48,G49,G53);
nor NOR2_2(G47,G50,G40);
nor NOR2_3(G53,G26,G27);
nor NOR3_1(G56,G57,G58,G130);
nor NOR2_4(G61,G14,G55);
nor NOR4_2(G86,G88,G89,G90,G112);
nor NOR3_2(G92,G94,G95,G97);
nor NOR2_5(G98,G100,G101);
nor NOR2_6(G102,G105,G106);
nor NOR2_7(G104,G74,G75);
nor NOR2_8(G107,G110,G111);
nor NOR2_9(G112,G62,G63);
nor NOR2_10(G113,G115,G116);
nor NOR3_3(G119,G122,G123,G130);
nor NOR3_4(G125,G128,G129,G130);
endmodule
|
/****************************************
Logic
- Logic Calcration Circuit
Make : 2010/@@/@@
Update :
****************************************/
`default_nettype none
module shift_n
#(
parameter N = 32
)
(
//Control
input [2:0] iCONTROL_MODE,
//iDATA
input [N-1:0] iDATA_0,
input [N-1:0] iDATA_1,
//oDATA
//output oVALID, //NEW
output [N-1:0] oDATA,
output oSF,
output oOF,
output oCF,
output oPF,
output oZF
);
genvar i;
wire [31:0] l_shift_input;
assign l_shift_input = iDATA_0;
wire [31:0] l_shift_out[0:63];
generate
for(i = 0; i < 64; i = i + 1)begin : L_SHIFTER
if(i < 32)begin
assign l_shift_out [i[5:0]] = l_shift_input << i[5:0];
end
else begin
assign l_shift_out [i[5:0]] = 32'h0;
end
end
endgenerate
wire [31:0] r_shift_input;
assign r_shift_input = iDATA_0;
wire [31:0] r_shift_out[0:63];
generate
for(i = 0; i < 64; i = i + 1)begin : R_SHIFTER
if(i < 32)begin
assign r_shift_out [i[5:0]] = r_shift_input >> i[5:0];
end
else begin
assign r_shift_out [i[5:0]] = 32'h0;
end
end
endgenerate
wire [31:0] r_al_shift_input;
assign r_al_shift_input = iDATA_0;
wire [31:0] r_al_shift_out[0:63];
generate
for(i = 0; i < 64; i = i + 1)begin : R_AL_SHIFTER
if(i == 0)begin
assign r_al_shift_out [i[5:0]] = r_al_shift_input;
end
else if(i < 32)begin
assign r_al_shift_out [i[5:0]] = {{i{r_al_shift_input[31]}}, r_al_shift_input[31:i]};
end
else begin
assign r_al_shift_out [i[5:0]] = {32{r_al_shift_input[31]}};
end
end
endgenerate
/*
function [31:0] func_rol;
input [31:0] func_rol_data;
input [5:0] func_rol_shift;
begin
case(func_rol_shift)
6'd0, 6'd32 : func_rol = func_rol_data;
6'd1, 6'd2 : func_rol = {func_rol_data[30:0], func_rol_data[31:31]};
6'd2, 6'd4 : func_rol = {func_rol_data[29:0], func_rol_data[31:30]};
6'd3, 6'd6 : func_rol = {func_rol_data[28:0], func_rol_data[31:29]};
6'd4, 6'd8 : func_rol = {func_rol_data[27:0], func_rol_data[31:28]};
6'd5, 6'd10 : func_rol = {func_rol_data[26:0], func_rol_data[31:27]};
6'd6, 6'd12 : func_rol = {func_rol_data[25:0], func_rol_data[31:26]};
6'd7, 6'd14 : func_rol = {func_rol_data[24:0], func_rol_data[31:25]};
6'd8, 6'd16 : func_rol = {func_rol_data[23:0], func_rol_data[31:24]};
6'd9, 6'd18 : func_rol = {func_rol_data[22:0], func_rol_data[31:23]};
6'd10, 6'd20 : func_rol = {func_rol_data[21:0], func_rol_data[31:22]};
6'd11, 6'd22 : func_rol = {func_rol_data[20:0], func_rol_data[31:21]};
6'd12, 6'd24 : func_rol = {func_rol_data[19:0], func_rol_data[31:20]};
6'd13, 6'd26 : func_rol = {func_rol_data[18:0], func_rol_data[31:19]};
6'd14, 6'd28 : func_rol = {func_rol_data[17:0], func_rol_data[31:18]};
6'd15, 6'd30 : func_rol = {func_rol_data[16:0], func_rol_data[31:17]};
6'd16, 6'd32 : func_rol = {func_rol_data[15:0], func_rol_data[31:16]};
6'd17, 6'd34 : func_rol = {func_rol_data[14:0], func_rol_data[31:15]};
6'd18, 6'd36 : func_rol = {func_rol_data[13:0], func_rol_data[31:14]};
6'd19, 6'd38 : func_rol = {func_rol_data[12:0], func_rol_data[31:13]};
6'd20, 6'd40 : func_rol = {func_rol_data[11:0], func_rol_data[31:12]};
6'd21, 6'd42 : func_rol = {func_rol_data[10:0], func_rol_data[31:11]};
6'd22, 6'd44 : func_rol = {func_rol_data[9:0], func_rol_data[31:10]};
6'd23, 6'd46 : func_rol = {func_rol_data[8:0], func_rol_data[31:9]};
6'd24, 6'd48 : func_rol = {func_rol_data[7:0], func_rol_data[31:8]};
6'd25, 6'd50 : func_rol = {func_rol_data[6:0], func_rol_data[31:7]};
6'd26, 6'd52 : func_rol = {func_rol_data[5:0], func_rol_data[31:6]};
6'd27, 6'd54 : func_rol = {func_rol_data[4:0], func_rol_data[31:5]};
6'd28, 6'd56 : func_rol = {func_rol_data[3:0], func_rol_data[31:4]};
6'd29, 6'd58 : func_rol = {func_rol_data[2:0], func_rol_data[31:3]};
6'd30, 6'd60 : func_rol = {func_rol_data[1:0], func_rol_data[31:2]};
6'd31, 6'd62 : func_rol = {func_rol_data[0:0], func_rol_data[31:1]};
endcase
end
endfunction
*/
/*
function [31:0] func_ror;
input [31:0] func_ror_data;
input [5:0] func_ror_shift;
begin
case(func_ror_shift)
6'd0, 6'd32 : func_ror = func_ror_data;
6'd1, 6'd2 : func_ror = {func_ror_data[0:0], func_ror_data[31:1]};
6'd2, 6'd4 : func_ror = {func_ror_data[1:0], func_ror_data[31:2]};
6'd3, 6'd6 : func_ror = {func_ror_data[2:0], func_ror_data[31:3]};
6'd4, 6'd8 : func_ror = {func_ror_data[3:0], func_ror_data[31:4]};
6'd5, 6'd10 : func_ror = {func_ror_data[4:0], func_ror_data[31:5]};
6'd6, 6'd12 : func_ror = {func_ror_data[5:0], func_ror_data[31:6]};
6'd7, 6'd14 : func_ror = {func_ror_data[6:0], func_ror_data[31:7]};
6'd8, 6'd16 : func_ror = {func_ror_data[7:0], func_ror_data[31:8]};
6'd9, 6'd18 : func_ror = {func_ror_data[8:0], func_ror_data[31:9]};
6'd10, 6'd20 : func_ror = {func_ror_data[9:0], func_ror_data[31:10]};
6'd11, 6'd22 : func_ror = {func_ror_data[10:0], func_ror_data[31:11]};
6'd12, 6'd24 : func_ror = {func_ror_data[11:0], func_ror_data[31:12]};
6'd13, 6'd26 : func_ror = {func_ror_data[12:0], func_ror_data[31:13]};
6'd14, 6'd28 : func_ror = {func_ror_data[13:0], func_ror_data[31:14]};
6'd15, 6'd30 : func_ror = {func_ror_data[14:0], func_ror_data[31:15]};
6'd16, 6'd32 : func_ror = {func_ror_data[15:0], func_ror_data[31:16]};
6'd17, 6'd34 : func_ror = {func_ror_data[16:0], func_ror_data[31:17]};
6'd18, 6'd36 : func_ror = {func_ror_data[17:0], func_ror_data[31:18]};
6'd19, 6'd38 : func_ror = {func_ror_data[18:0], func_ror_data[31:19]};
6'd20, 6'd40 : func_ror = {func_ror_data[19:0], func_ror_data[31:20]};
6'd21, 6'd42 : func_ror = {func_ror_data[20:0], func_ror_data[31:21]};
6'd22, 6'd44 : func_ror = {func_ror_data[21:0], func_ror_data[31:22]};
6'd23, 6'd46 : func_ror = {func_ror_data[22:0], func_ror_data[31:23]};
6'd24, 6'd48 : func_ror = {func_ror_data[23:0], func_ror_data[31:24]};
6'd25, 6'd50 : func_ror = {func_ror_data[24:0], func_ror_data[31:25]};
6'd26, 6'd52 : func_ror = {func_ror_data[25:0], func_ror_data[31:26]};
6'd27, 6'd54 : func_ror = {func_ror_data[26:0], func_ror_data[31:27]};
6'd28, 6'd56 : func_ror = {func_ror_data[27:0], func_ror_data[31:28]};
6'd29, 6'd58 : func_ror = {func_ror_data[28:0], func_ror_data[31:29]};
6'd30, 6'd60 : func_ror = {func_ror_data[29:0], func_ror_data[31:30]};
6'd31, 6'd62 : func_ror = {func_ror_data[30:0], func_ror_data[31:31]};
endcase
end
endfunction*/
function [31:0] func_rol;
input [31:0] func_rol_data;
input [5:0] func_rol_shift;
begin
case(func_rol_shift)
5'd0 : func_rol = func_rol_data;
5'd1 : func_rol = {func_rol_data[30:0], func_rol_data[31:31]};
5'd2 : func_rol = {func_rol_data[29:0], func_rol_data[31:30]};
5'd3 : func_rol = {func_rol_data[28:0], func_rol_data[31:29]};
5'd4 : func_rol = {func_rol_data[27:0], func_rol_data[31:28]};
5'd5 : func_rol = {func_rol_data[26:0], func_rol_data[31:27]};
5'd6 : func_rol = {func_rol_data[25:0], func_rol_data[31:26]};
5'd7 : func_rol = {func_rol_data[24:0], func_rol_data[31:25]};
5'd8 : func_rol = {func_rol_data[23:0], func_rol_data[31:24]};
5'd9 : func_rol = {func_rol_data[22:0], func_rol_data[31:23]};
5'd10 : func_rol = {func_rol_data[21:0], func_rol_data[31:22]};
5'd11 : func_rol = {func_rol_data[20:0], func_rol_data[31:21]};
5'd12 : func_rol = {func_rol_data[19:0], func_rol_data[31:20]};
5'd13 : func_rol = {func_rol_data[18:0], func_rol_data[31:19]};
5'd14 : func_rol = {func_rol_data[17:0], func_rol_data[31:18]};
5'd15 : func_rol = {func_rol_data[16:0], func_rol_data[31:17]};
5'd16 : func_rol = {func_rol_data[15:0], func_rol_data[31:16]};
5'd17 : func_rol = {func_rol_data[14:0], func_rol_data[31:15]};
5'd18 : func_rol = {func_rol_data[13:0], func_rol_data[31:14]};
5'd19 : func_rol = {func_rol_data[12:0], func_rol_data[31:13]};
5'd20 : func_rol = {func_rol_data[11:0], func_rol_data[31:12]};
5'd21 : func_rol = {func_rol_data[10:0], func_rol_data[31:11]};
5'd22 : func_rol = {func_rol_data[9:0], func_rol_data[31:10]};
5'd23 : func_rol = {func_rol_data[8:0], func_rol_data[31:9]};
5'd24 : func_rol = {func_rol_data[7:0], func_rol_data[31:8]};
5'd25 : func_rol = {func_rol_data[6:0], func_rol_data[31:7]};
5'd26 : func_rol = {func_rol_data[5:0], func_rol_data[31:6]};
5'd27 : func_rol = {func_rol_data[4:0], func_rol_data[31:5]};
5'd28 : func_rol = {func_rol_data[3:0], func_rol_data[31:4]};
5'd29 : func_rol = {func_rol_data[2:0], func_rol_data[31:3]};
5'd30 : func_rol = {func_rol_data[1:0], func_rol_data[31:2]};
5'd31 : func_rol = {func_rol_data[0:0], func_rol_data[31:1]};
endcase
end
endfunction
function [31:0] func_ror;
input [31:0] func_ror_data;
input [5:0] func_ror_shift;
begin
case(func_ror_shift)
5'd0 : func_ror = func_ror_data;
5'd1 : func_ror = {func_ror_data[0:0], func_ror_data[31:1]};
5'd2 : func_ror = {func_ror_data[1:0], func_ror_data[31:2]};
5'd3 : func_ror = {func_ror_data[2:0], func_ror_data[31:3]};
5'd4 : func_ror = {func_ror_data[3:0], func_ror_data[31:4]};
5'd5 : func_ror = {func_ror_data[4:0], func_ror_data[31:5]};
5'd6 : func_ror = {func_ror_data[5:0], func_ror_data[31:6]};
5'd7 : func_ror = {func_ror_data[6:0], func_ror_data[31:7]};
5'd8 : func_ror = {func_ror_data[7:0], func_ror_data[31:8]};
5'd9 : func_ror = {func_ror_data[8:0], func_ror_data[31:9]};
5'd10 : func_ror = {func_ror_data[9:0], func_ror_data[31:10]};
5'd11 : func_ror = {func_ror_data[10:0], func_ror_data[31:11]};
5'd12 : func_ror = {func_ror_data[11:0], func_ror_data[31:12]};
5'd13 : func_ror = {func_ror_data[12:0], func_ror_data[31:13]};
5'd14 : func_ror = {func_ror_data[13:0], func_ror_data[31:14]};
5'd15 : func_ror = {func_ror_data[14:0], func_ror_data[31:15]};
5'd16 : func_ror = {func_ror_data[15:0], func_ror_data[31:16]};
5'd17 : func_ror = {func_ror_data[16:0], func_ror_data[31:17]};
5'd18 : func_ror = {func_ror_data[17:0], func_ror_data[31:18]};
5'd19 : func_ror = {func_ror_data[18:0], func_ror_data[31:19]};
5'd20 : func_ror = {func_ror_data[19:0], func_ror_data[31:20]};
5'd21 : func_ror = {func_ror_data[20:0], func_ror_data[31:21]};
5'd22 : func_ror = {func_ror_data[21:0], func_ror_data[31:22]};
5'd23 : func_ror = {func_ror_data[22:0], func_ror_data[31:23]};
5'd24 : func_ror = {func_ror_data[23:0], func_ror_data[31:24]};
5'd25 : func_ror = {func_ror_data[24:0], func_ror_data[31:25]};
5'd26 : func_ror = {func_ror_data[25:0], func_ror_data[31:26]};
5'd27 : func_ror = {func_ror_data[26:0], func_ror_data[31:27]};
5'd28 : func_ror = {func_ror_data[27:0], func_ror_data[31:28]};
5'd29 : func_ror = {func_ror_data[28:0], func_ror_data[31:29]};
5'd30 : func_ror = {func_ror_data[29:0], func_ror_data[31:30]};
5'd31 : func_ror = {func_ror_data[30:0], func_ror_data[31:31]};
endcase
end
endfunction
//Output Selector
reg [31:0] data_out;
reg flag_cf;
always @* begin
case(iCONTROL_MODE)
3'h0 : //Buffer
begin
data_out = iDATA_0;
flag_cf = 1'b0;
end
3'h1 : //Logic Left
begin
data_out = l_shift_out[iDATA_1[5:0]];
if(iDATA_1[5:0] > 32 || iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else begin
flag_cf = iDATA_0[31-(iDATA_1[5:0]-1)];
end
end
3'h2 : //Logic Right
begin
data_out = r_shift_out[iDATA_1[5:0]];
if(iDATA_1[5:0] > 32 || iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else begin
flag_cf = iDATA_0[iDATA_1[5:0]-1];
end
end
3'h3 : //Arithmetic Right
begin
data_out = r_al_shift_out[iDATA_1[5:0]];
if(iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else if(iDATA_1[5:0] > 32)begin
flag_cf = iDATA_0[31];
end
else begin
flag_cf = iDATA_0[iDATA_1[5:0]-1];
end
end
3'h4 : //Rotate Left
begin
data_out = func_rol(iDATA_0, iDATA_1[4:0]);
if(iDATA_1[5:0] > 32 || iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else begin
flag_cf = iDATA_0[31-(iDATA_1[5:0]-1)];
end
end
3'h5 : //Rotate Right
begin
data_out = func_ror(iDATA_0, iDATA_1[4:0]);
if(iDATA_1[5:0] > 32 || iDATA_1[5:0] == 6'h0)begin
flag_cf = 1'b0;
end
else begin
flag_cf = iDATA_0[iDATA_1[5:0]-1];
end
end
default: //Reserved (Buffer)
begin
data_out = iDATA_0;
flag_cf = 1'b0;
end
endcase
end
assign oDATA = data_out;
assign oSF = data_out[N-1];
assign oOF = 1'b0;
assign oCF = flag_cf;
assign oPF = data_out[0];
assign oZF = (data_out == {32{1'b0}})? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_BEHAVIORAL_V
`define SKY130_FD_SC_MS__INV_BEHAVIORAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_scache.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_buf_scache(/*AUTOARG*/
// Outputs
pcx_scache_data_px, pcx_scache_data_rdy_px,
// Inputs
pcx_scache_data_px_l, pcx_scache_data_rdy_arb_px
);
output [`PCX_WIDTH-1:0]pcx_scache_data_px;
output pcx_scache_data_rdy_px;
input [`PCX_WIDTH-1:0]pcx_scache_data_px_l;
input pcx_scache_data_rdy_arb_px;
assign pcx_scache_data_px[`PCX_WIDTH-1:0] = ~pcx_scache_data_px_l[`PCX_WIDTH-1:0];
assign pcx_scache_data_rdy_px = pcx_scache_data_rdy_arb_px;
endmodule
|
/*
* Titor - System - Terminal Stub
* Copyright (C) 2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_TERMINAL
`else
`define INC_TERMINAL
`timescale 1 ns / 100 ps
module Terminal(
dout,
din,
address,
size,
read_write,
enable,
interrupt,
reset,
clk
);
`include "definition/Definition.v"
output wire [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output wire interrupt;
input reset;
input clk;
// this is a terminal stub, it does nothing in synthesis
// it is just a placeholder for the simulation-time terminal
assign dout = 0;
assign interrupt = 0;
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_SYMBOL_V
`define SKY130_FD_SC_HVL__PROBEC_P_SYMBOL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__probec_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc=0;
reg [31:0] loops;
reg [31:0] loops2;
integer i;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n",$time);
// Unwind <
loops = 0;
loops2 = 0;
for (i=0; i<16; i=i+1) begin
loops = loops + i; // surefire lint_off_line ASWEMB
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
end
if (i !== 16) $stop;
if (loops !== 120) $stop;
if (loops2 !== 120) $stop;
// Unwind <=
loops = 0;
for (i=0; i<=16; i=i+1) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Don't unwind breaked loops
loops = 0;
for (i=0; i<16; i=i+1) begin
loops = loops + 1;
if (i==7) i=99; // break out of loop
end
if (loops !== 8) $stop;
// Don't unwind large loops!
loops = 0;
for (i=0; i<100000; i=i+1) begin
loops = loops + 1;
end
if (loops !== 100000) $stop;
// Test post-increment
loops = 0;
for (i=0; i<=16; i++) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Test pre-increment
loops = 0;
for (i=0; i<=16; ++i) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Test post-decrement
loops = 0;
for (i=16; i>=0; i--) begin
loops = loops + 1;
end
if (i !== -1) $stop;
if (loops !== 17) $stop;
// Test pre-decrement
loops = 0;
for (i=16; i>=0; --i) begin
loops = loops + 1;
end
if (i !== -1) $stop;
if (loops !== 17) $stop;
//
// 1800-2017 optionals init/expr/incr
loops = 0;
i = 0;
for (; i<10; ++i) ++loops;
if (loops !== 10) $stop;
//
loops = 0;
i = 0;
for (i=0; i<10; ) begin ++loops; ++i; end
if (loops !== 10) $stop;
//
loops = 0;
i = 0;
for (; ; ++i) begin ++loops; break; end
if (loops !== 1) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_16x75k.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_16x75k (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [16:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.clocken0 (clken),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 76800,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 17,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "76800"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "17"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "76800"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 17 0 INPUT NODEFVAL "address[16..0]"
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 17 0 address 0 0 17 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x75k_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A41O_PP_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_PP_BLACKBOX_V
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
// altera message_off 10030
module jt12_exprom
(
input [7:0] addr,
input clk,
input clk_en /* synthesis direct_enable */,
output reg [9:0] exp
);
reg [9:0] explut_jt51[255:0];
initial
begin
explut_jt51[8'd000] = 10'd1018;
explut_jt51[8'd001] = 10'd1013;
explut_jt51[8'd002] = 10'd1007;
explut_jt51[8'd003] = 10'd1002;
explut_jt51[8'd004] = 10'd0996;
explut_jt51[8'd005] = 10'd0991;
explut_jt51[8'd006] = 10'd0986;
explut_jt51[8'd007] = 10'd0980;
explut_jt51[8'd008] = 10'd0975;
explut_jt51[8'd009] = 10'd0969;
explut_jt51[8'd010] = 10'd0964;
explut_jt51[8'd011] = 10'd0959;
explut_jt51[8'd012] = 10'd0953;
explut_jt51[8'd013] = 10'd0948;
explut_jt51[8'd014] = 10'd0942;
explut_jt51[8'd015] = 10'd0937;
explut_jt51[8'd016] = 10'd0932;
explut_jt51[8'd017] = 10'd0927;
explut_jt51[8'd018] = 10'd0921;
explut_jt51[8'd019] = 10'd0916;
explut_jt51[8'd020] = 10'd0911;
explut_jt51[8'd021] = 10'd0906;
explut_jt51[8'd022] = 10'd0900;
explut_jt51[8'd023] = 10'd0895;
explut_jt51[8'd024] = 10'd0890;
explut_jt51[8'd025] = 10'd0885;
explut_jt51[8'd026] = 10'd0880;
explut_jt51[8'd027] = 10'd0874;
explut_jt51[8'd028] = 10'd0869;
explut_jt51[8'd029] = 10'd0864;
explut_jt51[8'd030] = 10'd0859;
explut_jt51[8'd031] = 10'd0854;
explut_jt51[8'd032] = 10'd0849;
explut_jt51[8'd033] = 10'd0844;
explut_jt51[8'd034] = 10'd0839;
explut_jt51[8'd035] = 10'd0834;
explut_jt51[8'd036] = 10'd0829;
explut_jt51[8'd037] = 10'd0824;
explut_jt51[8'd038] = 10'd0819;
explut_jt51[8'd039] = 10'd0814;
explut_jt51[8'd040] = 10'd0809;
explut_jt51[8'd041] = 10'd0804;
explut_jt51[8'd042] = 10'd0799;
explut_jt51[8'd043] = 10'd0794;
explut_jt51[8'd044] = 10'd0789;
explut_jt51[8'd045] = 10'd0784;
explut_jt51[8'd046] = 10'd0779;
explut_jt51[8'd047] = 10'd0774;
explut_jt51[8'd048] = 10'd0770;
explut_jt51[8'd049] = 10'd0765;
explut_jt51[8'd050] = 10'd0760;
explut_jt51[8'd051] = 10'd0755;
explut_jt51[8'd052] = 10'd0750;
explut_jt51[8'd053] = 10'd0745;
explut_jt51[8'd054] = 10'd0741;
explut_jt51[8'd055] = 10'd0736;
explut_jt51[8'd056] = 10'd0731;
explut_jt51[8'd057] = 10'd0726;
explut_jt51[8'd058] = 10'd0722;
explut_jt51[8'd059] = 10'd0717;
explut_jt51[8'd060] = 10'd0712;
explut_jt51[8'd061] = 10'd0708;
explut_jt51[8'd062] = 10'd0703;
explut_jt51[8'd063] = 10'd0698;
explut_jt51[8'd064] = 10'd0693;
explut_jt51[8'd065] = 10'd0689;
explut_jt51[8'd066] = 10'd0684;
explut_jt51[8'd067] = 10'd0680;
explut_jt51[8'd068] = 10'd0675;
explut_jt51[8'd069] = 10'd0670;
explut_jt51[8'd070] = 10'd0666;
explut_jt51[8'd071] = 10'd0661;
explut_jt51[8'd072] = 10'd0657;
explut_jt51[8'd073] = 10'd0652;
explut_jt51[8'd074] = 10'd0648;
explut_jt51[8'd075] = 10'd0643;
explut_jt51[8'd076] = 10'd0639;
explut_jt51[8'd077] = 10'd0634;
explut_jt51[8'd078] = 10'd0630;
explut_jt51[8'd079] = 10'd0625;
explut_jt51[8'd080] = 10'd0621;
explut_jt51[8'd081] = 10'd0616;
explut_jt51[8'd082] = 10'd0612;
explut_jt51[8'd083] = 10'd0607;
explut_jt51[8'd084] = 10'd0603;
explut_jt51[8'd085] = 10'd0599;
explut_jt51[8'd086] = 10'd0594;
explut_jt51[8'd087] = 10'd0590;
explut_jt51[8'd088] = 10'd0585;
explut_jt51[8'd089] = 10'd0581;
explut_jt51[8'd090] = 10'd0577;
explut_jt51[8'd091] = 10'd0572;
explut_jt51[8'd092] = 10'd0568;
explut_jt51[8'd093] = 10'd0564;
explut_jt51[8'd094] = 10'd0560;
explut_jt51[8'd095] = 10'd0555;
explut_jt51[8'd096] = 10'd0551;
explut_jt51[8'd097] = 10'd0547;
explut_jt51[8'd098] = 10'd0542;
explut_jt51[8'd099] = 10'd0538;
explut_jt51[8'd100] = 10'd0534;
explut_jt51[8'd101] = 10'd0530;
explut_jt51[8'd102] = 10'd0526;
explut_jt51[8'd103] = 10'd0521;
explut_jt51[8'd104] = 10'd0517;
explut_jt51[8'd105] = 10'd0513;
explut_jt51[8'd106] = 10'd0509;
explut_jt51[8'd107] = 10'd0505;
explut_jt51[8'd108] = 10'd0501;
explut_jt51[8'd109] = 10'd0496;
explut_jt51[8'd110] = 10'd0492;
explut_jt51[8'd111] = 10'd0488;
explut_jt51[8'd112] = 10'd0484;
explut_jt51[8'd113] = 10'd0480;
explut_jt51[8'd114] = 10'd0476;
explut_jt51[8'd115] = 10'd0472;
explut_jt51[8'd116] = 10'd0468;
explut_jt51[8'd117] = 10'd0464;
explut_jt51[8'd118] = 10'd0460;
explut_jt51[8'd119] = 10'd0456;
explut_jt51[8'd120] = 10'd0452;
explut_jt51[8'd121] = 10'd0448;
explut_jt51[8'd122] = 10'd0444;
explut_jt51[8'd123] = 10'd0440;
explut_jt51[8'd124] = 10'd0436;
explut_jt51[8'd125] = 10'd0432;
explut_jt51[8'd126] = 10'd0428;
explut_jt51[8'd127] = 10'd0424;
explut_jt51[8'd128] = 10'd0420;
explut_jt51[8'd129] = 10'd0416;
explut_jt51[8'd130] = 10'd0412;
explut_jt51[8'd131] = 10'd0409;
explut_jt51[8'd132] = 10'd0405;
explut_jt51[8'd133] = 10'd0401;
explut_jt51[8'd134] = 10'd0397;
explut_jt51[8'd135] = 10'd0393;
explut_jt51[8'd136] = 10'd0389;
explut_jt51[8'd137] = 10'd0385;
explut_jt51[8'd138] = 10'd0382;
explut_jt51[8'd139] = 10'd0378;
explut_jt51[8'd140] = 10'd0374;
explut_jt51[8'd141] = 10'd0370;
explut_jt51[8'd142] = 10'd0367;
explut_jt51[8'd143] = 10'd0363;
explut_jt51[8'd144] = 10'd0359;
explut_jt51[8'd145] = 10'd0355;
explut_jt51[8'd146] = 10'd0352;
explut_jt51[8'd147] = 10'd0348;
explut_jt51[8'd148] = 10'd0344;
explut_jt51[8'd149] = 10'd0340;
explut_jt51[8'd150] = 10'd0337;
explut_jt51[8'd151] = 10'd0333;
explut_jt51[8'd152] = 10'd0329;
explut_jt51[8'd153] = 10'd0326;
explut_jt51[8'd154] = 10'd0322;
explut_jt51[8'd155] = 10'd0318;
explut_jt51[8'd156] = 10'd0315;
explut_jt51[8'd157] = 10'd0311;
explut_jt51[8'd158] = 10'd0308;
explut_jt51[8'd159] = 10'd0304;
explut_jt51[8'd160] = 10'd0300;
explut_jt51[8'd161] = 10'd0297;
explut_jt51[8'd162] = 10'd0293;
explut_jt51[8'd163] = 10'd0290;
explut_jt51[8'd164] = 10'd0286;
explut_jt51[8'd165] = 10'd0283;
explut_jt51[8'd166] = 10'd0279;
explut_jt51[8'd167] = 10'd0276;
explut_jt51[8'd168] = 10'd0272;
explut_jt51[8'd169] = 10'd0268;
explut_jt51[8'd170] = 10'd0265;
explut_jt51[8'd171] = 10'd0262;
explut_jt51[8'd172] = 10'd0258;
explut_jt51[8'd173] = 10'd0255;
explut_jt51[8'd174] = 10'd0251;
explut_jt51[8'd175] = 10'd0248;
explut_jt51[8'd176] = 10'd0244;
explut_jt51[8'd177] = 10'd0241;
explut_jt51[8'd178] = 10'd0237;
explut_jt51[8'd179] = 10'd0234;
explut_jt51[8'd180] = 10'd0231;
explut_jt51[8'd181] = 10'd0227;
explut_jt51[8'd182] = 10'd0224;
explut_jt51[8'd183] = 10'd0220;
explut_jt51[8'd184] = 10'd0217;
explut_jt51[8'd185] = 10'd0214;
explut_jt51[8'd186] = 10'd0210;
explut_jt51[8'd187] = 10'd0207;
explut_jt51[8'd188] = 10'd0204;
explut_jt51[8'd189] = 10'd0200;
explut_jt51[8'd190] = 10'd0197;
explut_jt51[8'd191] = 10'd0194;
explut_jt51[8'd192] = 10'd0190;
explut_jt51[8'd193] = 10'd0187;
explut_jt51[8'd194] = 10'd0184;
explut_jt51[8'd195] = 10'd0181;
explut_jt51[8'd196] = 10'd0177;
explut_jt51[8'd197] = 10'd0174;
explut_jt51[8'd198] = 10'd0171;
explut_jt51[8'd199] = 10'd0168;
explut_jt51[8'd200] = 10'd0164;
explut_jt51[8'd201] = 10'd0161;
explut_jt51[8'd202] = 10'd0158;
explut_jt51[8'd203] = 10'd0155;
explut_jt51[8'd204] = 10'd0152;
explut_jt51[8'd205] = 10'd0148;
explut_jt51[8'd206] = 10'd0145;
explut_jt51[8'd207] = 10'd0142;
explut_jt51[8'd208] = 10'd0139;
explut_jt51[8'd209] = 10'd0136;
explut_jt51[8'd210] = 10'd0133;
explut_jt51[8'd211] = 10'd0130;
explut_jt51[8'd212] = 10'd0126;
explut_jt51[8'd213] = 10'd0123;
explut_jt51[8'd214] = 10'd0120;
explut_jt51[8'd215] = 10'd0117;
explut_jt51[8'd216] = 10'd0114;
explut_jt51[8'd217] = 10'd0111;
explut_jt51[8'd218] = 10'd0108;
explut_jt51[8'd219] = 10'd0105;
explut_jt51[8'd220] = 10'd0102;
explut_jt51[8'd221] = 10'd0099;
explut_jt51[8'd222] = 10'd0096;
explut_jt51[8'd223] = 10'd0093;
explut_jt51[8'd224] = 10'd0090;
explut_jt51[8'd225] = 10'd0087;
explut_jt51[8'd226] = 10'd0084;
explut_jt51[8'd227] = 10'd0081;
explut_jt51[8'd228] = 10'd0078;
explut_jt51[8'd229] = 10'd0075;
explut_jt51[8'd230] = 10'd0072;
explut_jt51[8'd231] = 10'd0069;
explut_jt51[8'd232] = 10'd0066;
explut_jt51[8'd233] = 10'd0063;
explut_jt51[8'd234] = 10'd0060;
explut_jt51[8'd235] = 10'd0057;
explut_jt51[8'd236] = 10'd0054;
explut_jt51[8'd237] = 10'd0051;
explut_jt51[8'd238] = 10'd0048;
explut_jt51[8'd239] = 10'd0045;
explut_jt51[8'd240] = 10'd0042;
explut_jt51[8'd241] = 10'd0040;
explut_jt51[8'd242] = 10'd0037;
explut_jt51[8'd243] = 10'd0034;
explut_jt51[8'd244] = 10'd0031;
explut_jt51[8'd245] = 10'd0028;
explut_jt51[8'd246] = 10'd0025;
explut_jt51[8'd247] = 10'd0022;
explut_jt51[8'd248] = 10'd0020;
explut_jt51[8'd249] = 10'd0017;
explut_jt51[8'd250] = 10'd0014;
explut_jt51[8'd251] = 10'd0011;
explut_jt51[8'd252] = 10'd0008;
explut_jt51[8'd253] = 10'd0006;
explut_jt51[8'd254] = 10'd0003;
explut_jt51[8'd255] = 10'd0000;
end
always @ (posedge clk) if(clk_en)
exp <= explut_jt51[addr];
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Bluespec primitive module which generates a periodic clock
// This module is not synthesizable
module ClockGen(CLK_OUT);
parameter v1Width = 5;
parameter v2Width = 5;
parameter initDelay = 5;
parameter initValue = 1'b0;
parameter otherValue = 1'b1 ;
output CLK_OUT ;
reg CLK_OUT ;
// synopsys translate_off
// Clock is set to initValue for initDelay, and
// then repeats set to value1 for value1Width
initial
begin : clock_loop
#0 ;
CLK_OUT = initValue ;
# initDelay ;
forever
begin
CLK_OUT = otherValue ;
# v1Width ;
CLK_OUT = initValue ;
# v2Width ;
end // forever begin
end // initial begin
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if (! ( (( initValue == 1'b0 ) && ( otherValue == 1'b1 )) ||
(( initValue == 1'b1 ) && ( otherValue == 1'b0 )) ) )
begin
ok = 0;
$display ( "ERROR ClockGen.v: clock values must be complements" ) ;
end // if ( (( initValue != 0 ) && ( otherValue != 1 )) ||...
if ( ( v1Width <= 0 ) || ( v2Width <= 0 ))
begin
ok = 0;
$display( "ERROR ClockGen.v: duty cycle must be greater then 0") ;
end // if ( ( v1Width <= 0 ) || ( v2Width <= 0 ))
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule // ClockGen
`ifdef testBluespec
module testClockGen1() ;
wire clkout ;
ClockGen#(8,24,16,1'b1,1'b0) u1( clkout );
initial
begin
$dumpfile("ClockGen.dump");
$dumpvars(5) ;
$dumpon ;
#10000 $finish ;
end
endmodule // testClockGen
`endif
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mul.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mul (
clock,
dataa,
datab,
result);
input clock;
input [9:0] dataa;
input [17:0] datab;
output [9:0] result;
wire [9:0] sub_wire0;
wire [9:0] result = sub_wire0[9:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 10,
lpm_mult_component.lpm_widthb = 18,
lpm_mult_component.lpm_widthp = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "3"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "10"
// Retrieval info: PRIVATE: WidthB NUMERIC "18"
// Retrieval info: PRIVATE: WidthP NUMERIC "10"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "10"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "18"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "10"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
// Retrieval info: USED_PORT: datab 0 0 18 0 INPUT NODEFVAL "datab[17..0]"
// Retrieval info: USED_PORT: result 0 0 10 0 OUTPUT NODEFVAL "result[9..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
// Retrieval info: CONNECT: @datab 0 0 18 0 datab 0 0 18 0
// Retrieval info: CONNECT: result 0 0 10 0 @result 0 0 10 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mul.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mul.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mul.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mul.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mul_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mul_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_128x512a.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_128x512a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [127:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [127:0] q;
output rdempty;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [127:0] sub_wire1;
wire sub_wire2;
wire [9:0] sub_wire3;
wire wrfull = sub_wire0;
wire [127:0] q = sub_wire1[127:0];
wire rdempty = sub_wire2;
wire [9:0] wrusedw = sub_wire3[9:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.rdusedw (),
.wrempty ());
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 128,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "128"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "128"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom16x2048.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom16x2048 (
address,
clken,
clock,
q);
input [10:0] address;
input clken;
input clock;
output [15:0] q;
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef OPENMSP430_SIMULATION
altsyncram_component.init_file = "./pmem.mif",
`else
altsyncram_component.init_file = "../../software/memledtest/memledtest.mif",
`endif
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=ROM",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "ROM"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../software/memledtest/memledtest.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../software/memledtest/memledtest.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=ROM"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_V |
`timescale 1ns / 1ps
module flashLED(
output reg [7:0] oLED,
input iCLK_50,
input [3:0] iSW,
input in,
input reset
);
parameter cN = 24;
reg [1:0] speed;
reg direction;
reg enable, enable_cnt;
reg [cN:0] CLKs, CLKs_cnt;
wire edge_out;
reg [1:0] edge_in;
edge_detect ed(iCLK_50, reset, edge_in[1], edge_out);
always @(posedge iCLK_50)
begin
if (reset) begin
edge_in <= 2'b00;
end
else begin
edge_in[1] <= edge_in[0];
edge_in[0] <= in;
end
end
always @(posedge iCLK_50)
begin
if (reset) begin
CLKs <= 0;
CLKs_cnt <= 0;
enable <= 0;
end
else begin
CLKs <= CLKs + 1;
CLKs_cnt <= CLKs_cnt + 1;
if (enable)
enable <= 0;
else if ((speed == 2'b00 && CLKs >= (1 << cN))
|| (speed == 2'b01 && CLKs >= (1 << (cN-1)))
|| (speed >= 2'b10 && CLKs >= (1 << (cN-2)))) begin
enable <= 1;
CLKs <= 0;
end
if (enable_cnt)
enable_cnt <= 0;
else if (CLKs >= (1 << cN)) begin
enable_cnt <= 1;
CLKs_cnt <= 0;
end
end
end
always @(posedge iCLK_50)
begin
if (reset)
speed <= 2'b00;
else if (edge_out)
case (speed)
2'b00:
speed <= 2'b01;
2'b01:
speed <= 2'b10;
default:
speed <= 2'b00;
endcase
end
always @(posedge iCLK_50)
if (reset) begin
oLED <= 8'b00000000;
direction <= 0;
end
else if (iSW == 4'b0011)
if (iSW[0] && enable_cnt)
oLED <= oLED + 1;
else
oLED <= oLED;
else if (iSW[0] && enable) begin
case (iSW[3:1])
3'b100:
case ({oLED, direction})
9'b000000010: oLED <= 8'b00000010;
9'b000000100: oLED <= 8'b00000100;
9'b000001000: oLED <= 8'b00001000;
9'b000010000: oLED <= 8'b00010000;
9'b000100000: oLED <= 8'b00100000;
9'b001000000: oLED <= 8'b01000000;
9'b010000000: oLED <= 8'b10000000;
9'b100000000: {oLED, direction} <= 9'b010000001;
9'b010000001: oLED <= 8'b00100000;
9'b001000001: oLED <= 8'b00010000;
9'b000100001: oLED <= 8'b00001000;
9'b000010001: oLED <= 8'b00000100;
9'b000001001: oLED <= 8'b00000010;
9'b000000101: oLED <= 8'b00000001;
9'b000000011: {oLED, direction} <= 9'b000000100;
default: {oLED, direction} <= 9'b000000010;
endcase
3'b010:
case ({oLED, direction})
9'b100000010: oLED <= 8'b01000010;
9'b010000100: oLED <= 8'b00100100;
9'b001001000: oLED <= 8'b00011000;
9'b000110000: {oLED, direction} <= 9'b001001001;
9'b001001001: oLED <= 8'b01000010;
9'b010000101: oLED <= 8'b10000001;
9'b100000011: {oLED, direction} <= 9'b010000100;
default: {oLED, direction} <= 9'b100000010;
endcase
//3'b001: oLED <= oLED + 1;
3'b011:
case (oLED)
8'b01010101: oLED <= 8'b10101010;
8'b10101010: oLED <= 8'b01010101;
default: oLED <= 8'b01010101;
endcase
3'b101:
case ({oLED, direction})
9'b000000000: oLED <= 8'b11111111;
9'b111111110: {oLED, direction} <= 9'b000000001;
9'b000000001: oLED <= 8'b01000000;
9'b010000001: oLED <= 8'b00010000;
9'b000100001: oLED <= 8'b00000100;
9'b000001001: oLED <= 8'b00000001;
9'b000000011: oLED <= 8'b11000000;
9'b110000001: oLED <= 8'b00110000;
9'b001100001: oLED <= 8'b00001100;
9'b000011001: oLED <= 8'b00000011;
9'b000000111: oLED <= 8'b11100000;
9'b111000001: oLED <= 8'b00000111;
9'b000001111: oLED <= 8'b00111100;
9'b001111001: {oLED, direction} <= 9'b000000000;
default: {oLED, direction} <= 9'b000000000;
endcase
3'b110: oLED <= oLED * 7;
3'b111:
begin
oLED[7:4] <= oLED[7:4] - 1;
oLED[3:0] <= oLED[7:4] * 11;
end
default: {oLED, direction} <= 9'bxxxxxxxxx;
endcase
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [11 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [11 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [11 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [11 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(0),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Mon Oct 31 01:16:19 2016
/////////////////////////////////////////////////////////////
module FPU_Interface_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready;
wire NaN_reg, underflow_flag_mult, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_data_output2_31_,
FPSENCOS_sel_mux_3_reg, FPSENCOS_d_ff3_sign_out,
FPSENCOS_sel_mux_1_reg, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag,
FPADDSUB_sign_final_result, FPADDSUB_intAS, FPADDSUB_FSM_selector_A,
FPADDSUB_add_overflow_flag, FPADDSUB_FSM_selector_C,
FPSENCOS_cordic_FSM_state_next_1_, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1343, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1988,
n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998,
n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008,
n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018,
n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028,
n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038,
n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048,
n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058,
n2059, n2060, n2061, DP_OP_134J12_124_859_n22,
DP_OP_134J12_124_859_n21, DP_OP_134J12_124_859_n20,
DP_OP_134J12_124_859_n19, DP_OP_134J12_124_859_n18,
DP_OP_134J12_124_859_n17, DP_OP_134J12_124_859_n16,
DP_OP_134J12_124_859_n15, DP_OP_134J12_124_859_n9,
DP_OP_134J12_124_859_n8, DP_OP_134J12_124_859_n7,
DP_OP_134J12_124_859_n6, DP_OP_134J12_124_859_n5,
DP_OP_134J12_124_859_n4, DP_OP_134J12_124_859_n3,
DP_OP_134J12_124_859_n2, DP_OP_134J12_124_859_n1,
DP_OP_498J12_123_5135_n727, DP_OP_498J12_123_5135_n474,
DP_OP_498J12_123_5135_n473, DP_OP_498J12_123_5135_n472,
DP_OP_498J12_123_5135_n471, DP_OP_498J12_123_5135_n470,
DP_OP_498J12_123_5135_n469, DP_OP_498J12_123_5135_n468,
DP_OP_498J12_123_5135_n467, DP_OP_498J12_123_5135_n461,
DP_OP_498J12_123_5135_n460, DP_OP_498J12_123_5135_n459,
DP_OP_498J12_123_5135_n458, DP_OP_498J12_123_5135_n457,
DP_OP_498J12_123_5135_n456, DP_OP_498J12_123_5135_n455,
DP_OP_498J12_123_5135_n454, DP_OP_498J12_123_5135_n453,
DP_OP_498J12_123_5135_n452, DP_OP_498J12_123_5135_n448,
DP_OP_498J12_123_5135_n447, DP_OP_498J12_123_5135_n445,
DP_OP_498J12_123_5135_n444, DP_OP_498J12_123_5135_n443,
DP_OP_498J12_123_5135_n442, DP_OP_498J12_123_5135_n441,
DP_OP_498J12_123_5135_n440, DP_OP_498J12_123_5135_n439,
DP_OP_498J12_123_5135_n438, DP_OP_498J12_123_5135_n437,
DP_OP_498J12_123_5135_n436, DP_OP_498J12_123_5135_n435,
DP_OP_498J12_123_5135_n431, DP_OP_498J12_123_5135_n430,
DP_OP_498J12_123_5135_n429, DP_OP_498J12_123_5135_n428,
DP_OP_498J12_123_5135_n427, DP_OP_498J12_123_5135_n426,
DP_OP_498J12_123_5135_n425, DP_OP_498J12_123_5135_n424,
DP_OP_498J12_123_5135_n423, DP_OP_498J12_123_5135_n418,
DP_OP_498J12_123_5135_n417, DP_OP_498J12_123_5135_n415,
DP_OP_498J12_123_5135_n414, DP_OP_498J12_123_5135_n413,
DP_OP_498J12_123_5135_n412, DP_OP_498J12_123_5135_n411,
DP_OP_498J12_123_5135_n410, DP_OP_498J12_123_5135_n409,
DP_OP_498J12_123_5135_n408, DP_OP_498J12_123_5135_n407,
DP_OP_498J12_123_5135_n406, DP_OP_498J12_123_5135_n401,
DP_OP_498J12_123_5135_n400, DP_OP_498J12_123_5135_n399,
DP_OP_498J12_123_5135_n398, DP_OP_498J12_123_5135_n397,
DP_OP_498J12_123_5135_n396, DP_OP_498J12_123_5135_n395,
DP_OP_498J12_123_5135_n394, DP_OP_498J12_123_5135_n388,
DP_OP_498J12_123_5135_n387, DP_OP_498J12_123_5135_n385,
DP_OP_498J12_123_5135_n384, DP_OP_498J12_123_5135_n369,
DP_OP_498J12_123_5135_n366, DP_OP_498J12_123_5135_n365,
DP_OP_498J12_123_5135_n364, DP_OP_498J12_123_5135_n363,
DP_OP_498J12_123_5135_n362, DP_OP_498J12_123_5135_n361,
DP_OP_498J12_123_5135_n360, DP_OP_498J12_123_5135_n359,
DP_OP_498J12_123_5135_n358, DP_OP_498J12_123_5135_n356,
DP_OP_498J12_123_5135_n355, DP_OP_498J12_123_5135_n354,
DP_OP_498J12_123_5135_n352, DP_OP_498J12_123_5135_n351,
DP_OP_498J12_123_5135_n350, DP_OP_498J12_123_5135_n349,
DP_OP_498J12_123_5135_n348, DP_OP_498J12_123_5135_n347,
DP_OP_498J12_123_5135_n346, DP_OP_498J12_123_5135_n345,
DP_OP_498J12_123_5135_n344, DP_OP_498J12_123_5135_n343,
DP_OP_498J12_123_5135_n342, DP_OP_498J12_123_5135_n341,
DP_OP_498J12_123_5135_n340, DP_OP_498J12_123_5135_n339,
DP_OP_498J12_123_5135_n338, DP_OP_498J12_123_5135_n337,
DP_OP_498J12_123_5135_n336, DP_OP_498J12_123_5135_n335,
DP_OP_498J12_123_5135_n334, DP_OP_498J12_123_5135_n333,
DP_OP_498J12_123_5135_n332, DP_OP_498J12_123_5135_n330,
DP_OP_498J12_123_5135_n329, DP_OP_498J12_123_5135_n328,
DP_OP_498J12_123_5135_n327, DP_OP_498J12_123_5135_n326,
DP_OP_498J12_123_5135_n325, DP_OP_498J12_123_5135_n324,
DP_OP_498J12_123_5135_n323, DP_OP_498J12_123_5135_n322,
DP_OP_498J12_123_5135_n321, DP_OP_498J12_123_5135_n320,
DP_OP_498J12_123_5135_n319, DP_OP_498J12_123_5135_n318,
DP_OP_498J12_123_5135_n317, DP_OP_498J12_123_5135_n315,
DP_OP_498J12_123_5135_n313, DP_OP_498J12_123_5135_n312,
DP_OP_498J12_123_5135_n311, DP_OP_498J12_123_5135_n310,
DP_OP_498J12_123_5135_n309, DP_OP_498J12_123_5135_n308,
DP_OP_498J12_123_5135_n305, DP_OP_498J12_123_5135_n304,
DP_OP_498J12_123_5135_n303, DP_OP_498J12_123_5135_n302,
DP_OP_498J12_123_5135_n301, DP_OP_498J12_123_5135_n300,
DP_OP_498J12_123_5135_n299, DP_OP_498J12_123_5135_n298,
DP_OP_498J12_123_5135_n297, DP_OP_498J12_123_5135_n296,
DP_OP_498J12_123_5135_n295, DP_OP_498J12_123_5135_n294,
DP_OP_498J12_123_5135_n293, DP_OP_498J12_123_5135_n292,
DP_OP_498J12_123_5135_n291, DP_OP_498J12_123_5135_n290,
DP_OP_498J12_123_5135_n289, DP_OP_498J12_123_5135_n288,
DP_OP_498J12_123_5135_n287, DP_OP_498J12_123_5135_n286,
DP_OP_498J12_123_5135_n285, DP_OP_498J12_123_5135_n284,
DP_OP_498J12_123_5135_n283, DP_OP_498J12_123_5135_n282,
DP_OP_498J12_123_5135_n281, DP_OP_498J12_123_5135_n280,
DP_OP_498J12_123_5135_n279, DP_OP_498J12_123_5135_n278,
DP_OP_498J12_123_5135_n277, DP_OP_498J12_123_5135_n274,
DP_OP_498J12_123_5135_n273, DP_OP_498J12_123_5135_n272,
DP_OP_498J12_123_5135_n271, DP_OP_498J12_123_5135_n270,
DP_OP_498J12_123_5135_n269, DP_OP_498J12_123_5135_n268,
DP_OP_498J12_123_5135_n267, DP_OP_498J12_123_5135_n266,
DP_OP_498J12_123_5135_n265, DP_OP_498J12_123_5135_n264,
DP_OP_498J12_123_5135_n263, DP_OP_498J12_123_5135_n262,
DP_OP_498J12_123_5135_n261, DP_OP_498J12_123_5135_n260,
DP_OP_498J12_123_5135_n259, DP_OP_498J12_123_5135_n258,
DP_OP_498J12_123_5135_n257, mult_x_121_n355, mult_x_121_n351,
mult_x_121_n350, mult_x_121_n343, mult_x_121_n342, mult_x_121_n340,
mult_x_121_n339, mult_x_121_n338, mult_x_121_n337, mult_x_121_n336,
mult_x_121_n335, mult_x_121_n334, mult_x_121_n331, mult_x_121_n330,
mult_x_121_n329, mult_x_121_n327, mult_x_121_n326, mult_x_121_n325,
mult_x_121_n323, mult_x_121_n322, mult_x_121_n321, mult_x_121_n320,
mult_x_121_n319, mult_x_121_n318, mult_x_121_n317, mult_x_121_n315,
mult_x_121_n314, mult_x_121_n313, mult_x_121_n312, mult_x_121_n311,
mult_x_121_n310, mult_x_121_n309, mult_x_121_n308, mult_x_121_n306,
mult_x_121_n303, mult_x_121_n302, mult_x_121_n301, mult_x_121_n300,
mult_x_121_n299, mult_x_121_n298, mult_x_121_n297, mult_x_121_n296,
mult_x_121_n295, mult_x_121_n294, mult_x_121_n293, mult_x_121_n292,
mult_x_121_n291, mult_x_121_n285, mult_x_121_n284, mult_x_121_n281,
mult_x_121_n280, mult_x_121_n265, mult_x_121_n262, mult_x_121_n261,
mult_x_121_n260, mult_x_121_n259, mult_x_121_n258, mult_x_121_n257,
mult_x_121_n256, mult_x_121_n255, mult_x_121_n254, mult_x_121_n253,
mult_x_121_n252, mult_x_121_n251, mult_x_121_n250, mult_x_121_n249,
mult_x_121_n248, mult_x_121_n247, mult_x_121_n246, mult_x_121_n245,
mult_x_121_n244, mult_x_121_n243, mult_x_121_n242, mult_x_121_n241,
mult_x_121_n240, mult_x_121_n239, mult_x_121_n238, mult_x_121_n237,
mult_x_121_n236, mult_x_121_n235, mult_x_121_n234, mult_x_121_n233,
mult_x_121_n232, mult_x_121_n231, mult_x_121_n230, mult_x_121_n229,
mult_x_121_n228, mult_x_121_n227, mult_x_121_n226, mult_x_121_n225,
mult_x_121_n224, mult_x_121_n223, mult_x_121_n222, mult_x_121_n221,
mult_x_121_n219, mult_x_121_n218, mult_x_121_n217, mult_x_121_n216,
mult_x_121_n215, mult_x_121_n214, mult_x_121_n213, mult_x_121_n212,
mult_x_121_n209, mult_x_121_n208, mult_x_121_n207, mult_x_121_n206,
mult_x_121_n205, mult_x_121_n204, mult_x_121_n203, mult_x_121_n202,
mult_x_121_n201, mult_x_121_n200, mult_x_121_n199, mult_x_121_n198,
mult_x_121_n197, mult_x_121_n196, mult_x_121_n195, mult_x_121_n194,
mult_x_121_n191, mult_x_121_n190, mult_x_121_n189, mult_x_121_n188,
mult_x_121_n187, mult_x_121_n186, mult_x_121_n185, mult_x_121_n184,
mult_x_121_n183, mult_x_121_n182, mult_x_121_n181, mult_x_121_n180,
mult_x_121_n177, mult_x_121_n176, mult_x_121_n175, mult_x_121_n174,
mult_x_121_n173, mult_x_121_n172, mult_x_121_n171, mult_x_121_n170,
mult_x_121_n169, mult_x_121_n168, mult_x_121_n165, mult_x_121_n164,
mult_x_121_n163, mult_x_121_n162, mult_x_121_n161, mult_x_121_n160,
mult_x_159_n363, mult_x_159_n361, mult_x_159_n359, mult_x_159_n357,
mult_x_159_n351, mult_x_159_n350, mult_x_159_n348, mult_x_159_n347,
mult_x_159_n346, mult_x_159_n345, mult_x_159_n344, mult_x_159_n343,
mult_x_159_n342, mult_x_159_n339, mult_x_159_n338, mult_x_159_n337,
mult_x_159_n335, mult_x_159_n334, mult_x_159_n331, mult_x_159_n330,
mult_x_159_n329, mult_x_159_n328, mult_x_159_n327, mult_x_159_n326,
mult_x_159_n323, mult_x_159_n322, mult_x_159_n321, mult_x_159_n320,
mult_x_159_n317, mult_x_159_n316, mult_x_159_n314, mult_x_159_n311,
mult_x_159_n307, mult_x_159_n306, mult_x_159_n305, mult_x_159_n304,
mult_x_159_n301, mult_x_159_n300, mult_x_159_n299, mult_x_159_n298,
mult_x_159_n297, mult_x_159_n296, mult_x_159_n295, mult_x_159_n294,
mult_x_159_n293, mult_x_159_n292, mult_x_159_n291, mult_x_159_n290,
mult_x_159_n289, mult_x_159_n288, mult_x_159_n282, mult_x_159_n280,
mult_x_159_n273, mult_x_159_n267, mult_x_159_n264, mult_x_159_n263,
mult_x_159_n262, mult_x_159_n261, mult_x_159_n260, mult_x_159_n259,
mult_x_159_n258, mult_x_159_n257, mult_x_159_n256, mult_x_159_n255,
mult_x_159_n254, mult_x_159_n253, mult_x_159_n252, mult_x_159_n251,
mult_x_159_n250, mult_x_159_n249, mult_x_159_n248, mult_x_159_n247,
mult_x_159_n246, mult_x_159_n245, mult_x_159_n244, mult_x_159_n243,
mult_x_159_n242, mult_x_159_n241, mult_x_159_n240, mult_x_159_n239,
mult_x_159_n238, mult_x_159_n237, mult_x_159_n236, mult_x_159_n235,
mult_x_159_n234, mult_x_159_n233, mult_x_159_n232, mult_x_159_n231,
mult_x_159_n230, mult_x_159_n229, mult_x_159_n228, mult_x_159_n227,
mult_x_159_n226, mult_x_159_n225, mult_x_159_n224, mult_x_159_n223,
mult_x_159_n221, mult_x_159_n220, mult_x_159_n219, mult_x_159_n218,
mult_x_159_n217, mult_x_159_n216, mult_x_159_n215, mult_x_159_n214,
mult_x_159_n211, mult_x_159_n210, mult_x_159_n209, mult_x_159_n208,
mult_x_159_n207, mult_x_159_n206, mult_x_159_n205, mult_x_159_n204,
mult_x_159_n203, mult_x_159_n202, mult_x_159_n201, mult_x_159_n200,
mult_x_159_n199, mult_x_159_n198, mult_x_159_n197, mult_x_159_n196,
mult_x_159_n195, mult_x_159_n194, mult_x_159_n193, mult_x_159_n192,
mult_x_159_n191, mult_x_159_n190, mult_x_159_n189, mult_x_159_n188,
mult_x_159_n187, mult_x_159_n186, mult_x_159_n185, mult_x_159_n184,
mult_x_159_n183, mult_x_159_n182, mult_x_159_n179, mult_x_159_n178,
mult_x_159_n177, mult_x_159_n176, mult_x_159_n175, mult_x_159_n174,
mult_x_159_n173, mult_x_159_n172, mult_x_159_n171, mult_x_159_n170,
mult_x_159_n169, mult_x_159_n168, mult_x_159_n167, mult_x_159_n166,
mult_x_159_n165, mult_x_159_n164, mult_x_159_n163, mult_x_159_n162,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2172, n2173,
n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183,
n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193,
n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203,
n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213,
n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223,
n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233,
n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243,
n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253,
n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263,
n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273,
n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283,
n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293,
n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303,
n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313,
n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323,
n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333,
n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343,
n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273,
n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283,
n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293,
n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303,
n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313,
n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323,
n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353,
n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363,
n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373,
n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383,
n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393,
n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403,
n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413,
n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423,
n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433,
n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443,
n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453,
n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463,
n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473,
n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483,
n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493,
n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503,
n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513,
n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523,
n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533,
n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543,
n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553,
n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563,
n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573,
n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583,
n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593,
n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603,
n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613,
n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623,
n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633,
n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643,
n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723,
n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224,
n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234,
n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244,
n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344,
n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354,
n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364,
n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374,
n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384,
n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394,
n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404,
n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414,
n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424,
n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434,
n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444,
n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454,
n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464,
n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474,
n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484,
n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494,
n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504,
n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514,
n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524,
n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755,
n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765,
n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775,
n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785,
n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795,
n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035,
n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045,
n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105,
n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115,
n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125,
n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135,
n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145,
n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155,
n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165,
n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175,
n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185,
n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195,
n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205,
n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215,
n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225,
n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235,
n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245,
n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255,
n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265,
n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275,
n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285,
n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295,
n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305,
n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315,
n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325,
n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335,
n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345,
n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355,
n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365,
n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375,
n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385,
n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395,
n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405,
n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415,
n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425,
n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435,
n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445,
n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455,
n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465,
n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475,
n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485,
n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495,
n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505,
n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515,
n5516, n5517, n5519, n5520, n5521, n5522, n5523, n5524, n5525, n5526,
n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535, n5536,
n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545, n5546,
n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555, n5556,
n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565, n5566,
n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575, n5576,
n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585, n5586,
n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595, n5596,
n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605, n5606,
n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615, n5616,
n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625, n5626,
n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635, n5636,
n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645, n5646,
n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655, n5656,
n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665, n5666,
n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675, n5676,
n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685, n5686,
n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695, n5696,
n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705, n5706,
n5707, n5708, n5709, n5711, n5712, n5713, n5714, n5715, n5716, n5717,
n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725, n5726, n5727,
n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735, n5736, n5737,
n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745, n5746, n5747,
n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755, n5756, n5757,
n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765, n5766, n5767,
n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775, n5776, n5777,
n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785, n5786, n5787,
n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795, n5796, n5797,
n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805, n5806, n5807,
n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815, n5816, n5817,
n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826, n5827,
n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835, n5836, n5837,
n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845, n5846, n5847,
n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855, n5856, n5857,
n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865, n5866, n5867,
n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875, n5876, n5877,
n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885, n5886, n5887,
n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895, n5896, n5897,
n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905, n5906, n5907,
n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915, n5916, n5917,
n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, n5926, n5927,
n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935, n5936, n5937,
n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945, n5946, n5947,
n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955, n5956, n5957,
n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965, n5966, n5967,
n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975, n5976, n5977,
n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, n5986, n5987,
n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995, n5996, n5997,
n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005, n6006, n6007,
n6008, n6009;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [30:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_sign_inv_out;
wire [1:0] FPSENCOS_sel_mux_2_reg;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [3:0] FPSENCOS_cont_iter_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_Sgf_normalized_result;
wire [25:0] FPADDSUB_Add_Subt_result;
wire [4:0] FPADDSUB_LZA_output;
wire [7:0] FPADDSUB_exp_oper_result;
wire [30:0] FPADDSUB_DmP;
wire [30:0] FPADDSUB_DMP;
wire [31:0] FPADDSUB_intDY;
wire [31:0] FPADDSUB_intDX;
wire [1:0] FPADDSUB_FSM_selector_B;
wire [3:0] FPSENCOS_cordic_FSM_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [11:1] FPMULT_Sgf_operation_Result;
wire [25:0] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle;
wire [23:12] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right;
wire [23:0] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left;
wire [3:0] FPADDSUB_FS_Module_state_reg;
wire [51:0] FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n5916), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n5947), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n5915), .QN(
n2151) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n5914), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n5917), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n5917), .Q(
dataB[31]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n2038), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[16]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n2036), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[14]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n2032), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[10]), .QN(n2354) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n2030), .CK(clk),
.RN(n6002), .Q(n2129), .QN(n2331) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n2027), .CK(clk),
.RN(n6002), .Q(n2130), .QN(n2344) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n2025), .CK(clk),
.RN(n6002), .Q(FPMULT_Op_MX[3]), .QN(n2330) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n2006), .CK(clk),
.RN(n5997), .Q(n2125), .QN(n2345) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n2004), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[14]), .QN(n2269) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n2002), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[12]), .QN(n2299) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1996), .CK(clk),
.RN(n5996), .Q(FPMULT_Op_MY[6]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1995), .CK(clk),
.RN(n5996), .Q(FPMULT_Op_MY[5]), .QN(n2141) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1993), .CK(clk),
.RN(n5996), .Q(FPMULT_Op_MY[3]), .QN(n2138) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1990), .CK(clk),
.RN(n5996), .Q(FPMULT_Op_MY[0]), .QN(n2323) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_23_ ( .D(n1916),
.CK(clk), .RN(n5948), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1985), .CK(
clk), .RN(n5994), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1940), .CK(clk), .RN(n5992), .Q(mult_result[31]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1948), .CK(clk), .RN(n5992), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1947), .CK(clk), .RN(n5992), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1946), .CK(clk), .RN(n5991), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1945), .CK(clk), .RN(n5991), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1944), .CK(clk), .RN(n5991), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1943), .CK(clk), .RN(n5991), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1942), .CK(clk), .RN(n5991), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1941), .CK(clk), .RN(n5991), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1868), .CK(clk), .RN(n5991), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1867), .CK(clk), .RN(n5991), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1866), .CK(clk), .RN(n5991), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1865), .CK(clk), .RN(n5991), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1864), .CK(clk), .RN(n5990), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1863), .CK(clk), .RN(n5990), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1862), .CK(clk), .RN(n5990), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1861), .CK(clk), .RN(n5990), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1860), .CK(clk), .RN(n5990), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1859), .CK(clk), .RN(n5990), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1858), .CK(clk), .RN(n5990), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1857), .CK(clk), .RN(n5990), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1856), .CK(clk), .RN(n5990), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1855), .CK(clk), .RN(n5990), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1854), .CK(clk), .RN(n5989), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1853), .CK(clk), .RN(n5989), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1852), .CK(clk), .RN(n5989), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1851), .CK(clk), .RN(n5989), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1850), .CK(clk), .RN(n5989), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1849), .CK(clk), .RN(n5989), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1848), .CK(clk), .RN(n5989), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1847), .CK(clk), .RN(n5989), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1846), .CK(clk), .RN(n5989), .Q(mult_result[22]) );
DFFRXLTS FPSENCOS_cont_iter_count_reg_1_ ( .D(n1830), .CK(clk), .RN(n5968),
.Q(FPSENCOS_cont_iter_out[1]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n1828), .CK(clk), .RN(n5969),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n1826), .CK(clk), .RN(n5969), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n1825), .CK(clk), .RN(n5969), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n1824), .CK(clk), .RN(n5969), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n1823), .CK(clk), .RN(n5969), .QN(
n5889) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n1822), .CK(clk), .RN(n5969), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_22_ ( .D(n1821), .CK(clk), .RN(n5969), .Q(
FPSENCOS_d_ff3_LUT_out[22]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n1820), .CK(clk), .RN(n5969), .QN(
n2113) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_20_ ( .D(n1819), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[20]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n1818), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_18_ ( .D(n1817), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[18]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_17_ ( .D(n1816), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[17]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_16_ ( .D(n1815), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[16]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n1814), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_14_ ( .D(n1813), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[14]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n1812), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n1811), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_11_ ( .D(n1810), .CK(clk), .RN(n5970), .Q(
FPSENCOS_d_ff3_LUT_out[11]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n1809), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n1807), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n1806), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n1805), .CK(clk), .RN(n5971), .QN(
n2339) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n1804), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n1803), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n1802), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n1800), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n1799), .CK(clk), .RN(n5972), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1411), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1412), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1413), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1414), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1415), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1416), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1417), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1782), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1783), .CK(clk), .RN(n5973),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1784), .CK(clk), .RN(n5973),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1785), .CK(clk), .RN(n5973),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1786), .CK(clk), .RN(n5973),
.Q(FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1787), .CK(clk), .RN(n5973),
.Q(FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1788), .CK(clk), .RN(n5973),
.Q(FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n1735), .CK(clk), .RN(n5973), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n1734), .CK(clk), .RN(n5973), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n1733), .CK(clk), .RN(n5973), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n1732), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n1731), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n1730), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n1729), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n1728), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n1727), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n1726), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n1725), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n1724), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n1723), .CK(clk), .RN(n5974), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n1722), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n1721), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n1720), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n1719), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n1718), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n1717), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n1716), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n1715), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n1714), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n1713), .CK(clk), .RN(n5975), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n1712), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n1711), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n1710), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n1709), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n1708), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n1707), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n1706), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n1705), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n1704), .CK(clk), .RN(n5976), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n1737), .CK(clk), .RN(
n5977), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n1736), .CK(clk), .RN(n5977),
.Q(FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRX2TS FPADDSUB_FS_Module_state_reg_reg_3_ ( .D(n1838), .CK(clk), .RN(
n5940), .Q(FPADDSUB_FS_Module_state_reg[3]), .QN(n5775) );
DFFRXLTS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(
n1658), .CK(clk), .RN(n5918), .Q(FPADDSUB_LZA_output[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1798), .CK(clk), .RN(n5977),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1698), .CK(clk), .RN(n5978), .Q(
FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1409), .CK(clk), .RN(n5978),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1343), .CK(clk), .RN(n5978),
.Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n3889), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1627), .CK(clk), .RN(n3893), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1476), .CK(clk), .RN(
n3891), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1797), .CK(clk), .RN(
n3888), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_30_ ( .D(n1347), .CK(clk), .RN(n5986), .Q(
FPSENCOS_sign_inv_out[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1346), .CK(clk), .RN(n5987),
.Q(cordic_result[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1623), .CK(clk), .RN(n3888), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1477), .CK(clk), .RN(
n5986), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1622), .CK(clk), .RN(n5987), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_29_ ( .D(n1349), .CK(clk), .RN(n3888), .Q(
FPSENCOS_sign_inv_out[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1348), .CK(clk), .RN(n5986),
.Q(cordic_result[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1619), .CK(clk), .RN(n5987), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1478), .CK(clk), .RN(
n3888), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1618), .CK(clk), .RN(n5986), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_28_ ( .D(n1351), .CK(clk), .RN(n5987), .Q(
FPSENCOS_sign_inv_out[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1350), .CK(clk), .RN(n5985),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1615), .CK(clk), .RN(n5985), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1479), .CK(clk), .RN(
n5985), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_27_ ( .D(n1353), .CK(clk), .RN(n5985), .Q(
FPSENCOS_sign_inv_out[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1352), .CK(clk), .RN(n5985),
.Q(cordic_result[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1611), .CK(clk), .RN(n5985), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1480), .CK(clk), .RN(
n5984), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1610), .CK(clk), .RN(n5984), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_26_ ( .D(n1355), .CK(clk), .RN(n5984), .Q(
FPSENCOS_sign_inv_out[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1354), .CK(clk), .RN(n5984),
.Q(cordic_result[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1607), .CK(clk), .RN(n5984), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1481), .CK(clk), .RN(
n5984), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1606), .CK(clk), .RN(n5984), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_25_ ( .D(n1357), .CK(clk), .RN(n5983), .Q(
FPSENCOS_sign_inv_out[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1356), .CK(clk), .RN(n5983),
.Q(cordic_result[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1603), .CK(clk), .RN(n5983), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1482), .CK(clk), .RN(
n5983), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1602), .CK(clk), .RN(n5983), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_24_ ( .D(n1359), .CK(clk), .RN(n5982), .Q(
FPSENCOS_sign_inv_out[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1358), .CK(clk), .RN(n5982),
.Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1599), .CK(clk), .RN(n5982), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1483), .CK(clk), .RN(
n5982), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1598), .CK(clk), .RN(n5982), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_23_ ( .D(n1361), .CK(clk), .RN(n5981), .Q(
FPSENCOS_sign_inv_out[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1360), .CK(clk), .RN(n5981),
.Q(cordic_result[23]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1508), .CK(clk), .RN(n5929), .Q(result_add_subt[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n1507), .CK(clk), .RN(n5981), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1506), .CK(clk), .RN(
n5981), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n1473), .CK(clk), .RN(n5981), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk),
.RN(n5919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n1595), .CK(clk), .RN(n5981), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1484), .CK(clk), .RN(
n5981), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n1594), .CK(clk), .RN(n5981), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1427), .CK(clk), .RN(n5980),
.QN(n5890) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1781), .CK(clk), .RN(
n5980), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1780), .CK(clk), .RN(n5980),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1532), .CK(clk), .RN(n5933), .Q(result_add_subt[6]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n1531), .CK(clk), .RN(n5980), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1500), .CK(clk), .RN(
n5980), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n1530), .CK(clk), .RN(n5980), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1459), .CK(clk), .RN(n5980),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1749), .CK(clk), .RN(
n5979), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1748), .CK(clk), .RN(n5979),
.Q(FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1520), .CK(clk), .RN(n5932), .Q(result_add_subt[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n1519), .CK(clk), .RN(n5979), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1503), .CK(clk), .RN(
n5979), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n1518), .CK(clk), .RN(n5979), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1465), .CK(clk), .RN(n5979),
.QN(n5891) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1743), .CK(clk), .RN(
n5979), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1742), .CK(clk), .RN(n5979),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n1583), .CK(clk), .RN(n5978), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1487), .CK(clk), .RN(
n5978), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n1582), .CK(clk), .RN(n5978), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1433), .CK(clk), .RN(n5983),
.QN(n5892) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1775), .CK(clk), .RN(
n5949), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1774), .CK(clk), .RN(n5949),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_19_ ( .D(n1369), .CK(clk), .RN(n5949), .Q(
FPSENCOS_sign_inv_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1368), .CK(clk), .RN(n5949),
.Q(cordic_result[19]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1516), .CK(clk), .RN(n5931), .Q(result_add_subt[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n1515), .CK(clk), .RN(n5949), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1504), .CK(clk), .RN(
n5949), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n1514), .CK(clk), .RN(n5949), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1467), .CK(clk), .RN(n5949),
.QN(n5893) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n1741), .CK(clk), .RN(
n5950), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n1740), .CK(clk), .RN(n5950),
.Q(FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n1591), .CK(clk), .RN(n5950), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1485), .CK(clk), .RN(
n5950), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n1590), .CK(clk), .RN(n5950), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1429), .CK(clk), .RN(n5950),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1779), .CK(clk), .RN(
n5950), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1778), .CK(clk), .RN(n5951),
.Q(FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n1579), .CK(clk), .RN(n5951), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1488), .CK(clk), .RN(
n5951), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n1578), .CK(clk), .RN(n5951), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1435), .CK(clk), .RN(n5951),
.QN(n5894) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1773), .CK(clk), .RN(
n5951), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1772), .CK(clk), .RN(n5951),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_18_ ( .D(n1371), .CK(clk), .RN(n5951), .Q(
FPSENCOS_sign_inv_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1370), .CK(clk), .RN(n5952),
.Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n1567), .CK(clk), .RN(n5952), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1491), .CK(clk), .RN(
n5952), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n1566), .CK(clk), .RN(n5952), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1441), .CK(clk), .RN(n5952),
.QN(n5895) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1767), .CK(clk), .RN(
n5952), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1766), .CK(clk), .RN(n5952),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1540), .CK(clk), .RN(n5929), .Q(result_add_subt[8]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n1539), .CK(clk), .RN(n5952), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1498), .CK(clk), .RN(
n5953), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n1538), .CK(clk), .RN(n5953), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1455), .CK(clk), .RN(n5953),
.QN(n5896) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1753), .CK(clk), .RN(
n5953), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1752), .CK(clk), .RN(n5953),
.Q(FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1512), .CK(clk), .RN(n5930), .Q(result_add_subt[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n1511), .CK(clk), .RN(n5953), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1505), .CK(clk), .RN(
n5953), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n1510), .CK(clk), .RN(n5953), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1469), .CK(clk), .RN(n5954),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n1739), .CK(clk), .RN(
n5954), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n1738), .CK(clk), .RN(n5954),
.Q(FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n1587), .CK(clk), .RN(n5954), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1486), .CK(clk), .RN(
n5954), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n1586), .CK(clk), .RN(n5954), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1431), .CK(clk), .RN(n5954),
.QN(n5897) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1777), .CK(clk), .RN(
n5955), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1776), .CK(clk), .RN(n5955),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_20_ ( .D(n1367), .CK(clk), .RN(n5955), .Q(
FPSENCOS_sign_inv_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1366), .CK(clk), .RN(n5955),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n1559), .CK(clk), .RN(n5955), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1493), .CK(clk), .RN(
n5955), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n1558), .CK(clk), .RN(n5955), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1445), .CK(clk), .RN(n5955),
.QN(n5898) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1763), .CK(clk), .RN(
n5956), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1762), .CK(clk), .RN(n5956),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(n5956), .Q(
FPSENCOS_sign_inv_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1380), .CK(clk), .RN(n5956),
.Q(cordic_result[13]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1528), .CK(clk), .RN(n5928), .Q(result_add_subt[5]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n1527), .CK(clk), .RN(n5956), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1501), .CK(clk), .RN(
n5956), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n1526), .CK(clk), .RN(n5956), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1461), .CK(clk), .RN(n5956),
.QN(n5899) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1747), .CK(clk), .RN(
n5957), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1746), .CK(clk), .RN(n5957),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n1575), .CK(clk), .RN(n5957), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1489), .CK(clk), .RN(
n5957), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n1574), .CK(clk), .RN(n5957), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1437), .CK(clk), .RN(n5957),
.QN(n5900) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1771), .CK(clk), .RN(
n5957), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1770), .CK(clk), .RN(n5958),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_17_ ( .D(n1373), .CK(clk), .RN(n5958), .Q(
FPSENCOS_sign_inv_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1372), .CK(clk), .RN(n5958),
.Q(cordic_result[17]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1524), .CK(clk), .RN(n3897), .Q(result_add_subt[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n1523), .CK(clk), .RN(n5958), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1502), .CK(clk), .RN(
n5958), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n1522), .CK(clk), .RN(n5958), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1463), .CK(clk), .RN(n5958),
.QN(n5901) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1745), .CK(clk), .RN(
n5959), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1744), .CK(clk), .RN(n5959),
.Q(FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n1571), .CK(clk), .RN(n5959), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1490), .CK(clk), .RN(
n5959), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n1570), .CK(clk), .RN(n5959), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1439), .CK(clk), .RN(n5959),
.QN(n5902) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1769), .CK(clk), .RN(
n5959), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1768), .CK(clk), .RN(n5959),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_16_ ( .D(n1375), .CK(clk), .RN(n5960), .Q(
FPSENCOS_sign_inv_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1374), .CK(clk), .RN(n5960),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n1547), .CK(clk), .RN(n5960), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1496), .CK(clk), .RN(
n5960), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n1546), .CK(clk), .RN(n5960), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1451), .CK(clk), .RN(n5960),
.QN(n5903) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1757), .CK(clk), .RN(
n5960), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1756), .CK(clk), .RN(n5960),
.Q(FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n1563), .CK(clk), .RN(n5961), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1492), .CK(clk), .RN(
n5961), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n1562), .CK(clk), .RN(n5961), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1443), .CK(clk), .RN(n5961),
.QN(n5904) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1765), .CK(clk), .RN(
n5961), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1764), .CK(clk), .RN(n5961),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_14_ ( .D(n1379), .CK(clk), .RN(n5961), .Q(
FPSENCOS_sign_inv_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1378), .CK(clk), .RN(n5961),
.Q(cordic_result[14]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1536), .CK(clk), .RN(n5927), .Q(result_add_subt[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n1535), .CK(clk), .RN(n5962), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1499), .CK(clk), .RN(
n5962), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n1534), .CK(clk), .RN(n5962), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1457), .CK(clk), .RN(n5962),
.QN(n5905) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1751), .CK(clk), .RN(
n5962), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1750), .CK(clk), .RN(n5962),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n1551), .CK(clk), .RN(n5962), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1495), .CK(clk), .RN(
n5962), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n1550), .CK(clk), .RN(n5963), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1449), .CK(clk), .RN(n5963),
.QN(n5906) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1759), .CK(clk), .RN(
n5963), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1758), .CK(clk), .RN(n5963),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n1555), .CK(clk), .RN(n5963), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1494), .CK(clk), .RN(
n5963), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n1554), .CK(clk), .RN(n5963), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1447), .CK(clk), .RN(n5964),
.QN(n5907) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1761), .CK(clk), .RN(
n5964), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1760), .CK(clk), .RN(n5964),
.Q(FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_12_ ( .D(n1383), .CK(clk), .RN(n5964), .Q(
FPSENCOS_sign_inv_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1382), .CK(clk), .RN(n5964),
.Q(cordic_result[12]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1544), .CK(clk), .RN(n5930), .Q(result_add_subt[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n1543), .CK(clk), .RN(n5964), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1497), .CK(clk), .RN(
n5964), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n1542), .CK(clk), .RN(n5964), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1453), .CK(clk), .RN(n5965),
.QN(n5908) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1755), .CK(clk), .RN(
n5965), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1754), .CK(clk), .RN(n5965),
.Q(FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_9_ ( .D(n1389), .CK(clk), .RN(n5965), .Q(
FPSENCOS_sign_inv_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1388), .CK(clk), .RN(n5965),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_11_ ( .D(n1385), .CK(clk), .RN(n5965), .Q(
FPSENCOS_sign_inv_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1384), .CK(clk), .RN(n5965),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_7_ ( .D(n1393), .CK(clk), .RN(n5965), .Q(
FPSENCOS_sign_inv_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1392), .CK(clk), .RN(n5965),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_10_ ( .D(n1387), .CK(clk), .RN(n5966), .Q(
FPSENCOS_sign_inv_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1386), .CK(clk), .RN(n5966),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_4_ ( .D(n1399), .CK(clk), .RN(n5966), .Q(
FPSENCOS_sign_inv_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1398), .CK(clk), .RN(n5966),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_5_ ( .D(n1397), .CK(clk), .RN(n5966), .Q(
FPSENCOS_sign_inv_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1396), .CK(clk), .RN(n5966),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_1_ ( .D(n1405), .CK(clk), .RN(n5966), .Q(
FPSENCOS_sign_inv_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1404), .CK(clk), .RN(n5966),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_8_ ( .D(n1391), .CK(clk), .RN(n5966), .Q(
FPSENCOS_sign_inv_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1390), .CK(clk), .RN(n5966),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_15_ ( .D(n1377), .CK(clk), .RN(n5967), .Q(
FPSENCOS_sign_inv_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1376), .CK(clk), .RN(n5967),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_21_ ( .D(n1365), .CK(clk), .RN(n5967), .Q(
FPSENCOS_sign_inv_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1364), .CK(clk), .RN(n5967),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_2_ ( .D(n1403), .CK(clk), .RN(n5967), .Q(
FPSENCOS_sign_inv_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1402), .CK(clk), .RN(n5967),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_3_ ( .D(n1401), .CK(clk), .RN(n5967), .Q(
FPSENCOS_sign_inv_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1400), .CK(clk), .RN(n5967),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_6_ ( .D(n1395), .CK(clk), .RN(n5967), .Q(
FPSENCOS_sign_inv_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1394), .CK(clk), .RN(n5967),
.Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_22_ ( .D(n1363), .CK(clk), .RN(n5968), .Q(
FPSENCOS_sign_inv_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1362), .CK(clk), .RN(n5968),
.Q(cordic_result[22]) );
DFFRXLTS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk),
.RN(n5922), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1471), .CK(clk), .RN(n5968),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_0_ ( .D(n1407), .CK(clk), .RN(n5968), .Q(
FPSENCOS_sign_inv_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1406), .CK(clk), .RN(n5968),
.Q(cordic_result[0]) );
DFFHQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[18]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_24_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_25_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1325), .CK(
clk), .RN(n5939), .Q(FPADDSUB_DmP[30]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1322), .CK(
clk), .RN(n5939), .Q(FPADDSUB_DmP[29]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1319), .CK(
clk), .RN(n5939), .Q(FPADDSUB_DmP[28]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1316), .CK(
clk), .RN(n5939), .Q(FPADDSUB_DmP[27]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1313), .CK(
clk), .RN(n5938), .Q(FPADDSUB_DmP[26]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1310), .CK(
clk), .RN(n5938), .Q(FPADDSUB_DmP[25]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1307), .CK(
clk), .RN(n5938), .Q(FPADDSUB_DmP[24]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1304), .CK(
clk), .RN(n5938), .Q(FPADDSUB_DmP[23]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1295), .CK(
clk), .RN(n5924), .Q(FPADDSUB_DmP[6]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1289), .CK(
clk), .RN(n5924), .Q(FPADDSUB_DmP[19]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1285), .CK(
clk), .RN(n5925), .Q(FPADDSUB_DmP[2]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1279), .CK(
clk), .RN(n5925), .Q(FPADDSUB_DmP[18]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1275), .CK(
clk), .RN(n5925), .Q(FPADDSUB_DmP[15]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1272), .CK(
clk), .RN(n5926), .Q(FPADDSUB_DmP[8]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1251), .CK(
clk), .RN(n5928), .Q(FPADDSUB_DmP[4]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1248), .CK(
clk), .RN(n5933), .Q(FPADDSUB_DmP[16]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1244), .CK(
clk), .RN(n5932), .Q(FPADDSUB_DmP[10]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1241), .CK(
clk), .RN(n3894), .Q(FPADDSUB_DmP[14]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1237), .CK(
clk), .RN(n5928), .Q(FPADDSUB_DmP[7]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1234), .CK(
clk), .RN(n5948), .Q(FPADDSUB_DmP[11]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1231), .CK(
clk), .RN(n5929), .Q(FPADDSUB_DmP[12]) );
CMPR32X2TS DP_OP_134J12_124_859_U8 ( .A(DP_OP_134J12_124_859_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_134J12_124_859_n8), .CO(
DP_OP_134J12_124_859_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_134J12_124_859_U6 ( .A(DP_OP_134J12_124_859_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_134J12_124_859_n6), .CO(
DP_OP_134J12_124_859_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_134J12_124_859_U4 ( .A(DP_OP_134J12_124_859_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_134J12_124_859_n4), .CO(
DP_OP_134J12_124_859_n3), .S(FPMULT_Exp_module_Data_S[6]) );
DFFHQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1626), .CK(clk), .RN(n5987), .Q(
FPSENCOS_d_ff_Yn[30]), .QN(n5888) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1621), .CK(clk), .RN(n5986), .Q(
FPSENCOS_d_ff_Xn[29]), .QN(n5886) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n1509), .CK(clk), .RN(n5954), .Q(
FPSENCOS_d_ff_Xn[1]), .QN(n5885) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n1513), .CK(clk), .RN(n5950), .Q(
FPSENCOS_d_ff_Xn[2]), .QN(n5884) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n1517), .CK(clk), .RN(n5979), .Q(
FPSENCOS_d_ff_Xn[3]), .QN(n5883) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n1525), .CK(clk), .RN(n5957), .Q(
FPSENCOS_d_ff_Xn[5]), .QN(n5882) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n1529), .CK(clk), .RN(n5980), .Q(
FPSENCOS_d_ff_Xn[6]), .QN(n5881) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n1533), .CK(clk), .RN(n5962), .Q(
FPSENCOS_d_ff_Xn[7]), .QN(n5880) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n1545), .CK(clk), .RN(n5960), .Q(
FPSENCOS_d_ff_Xn[10]), .QN(n5879) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n1553), .CK(clk), .RN(n5964), .Q(
FPSENCOS_d_ff_Xn[12]), .QN(n5878) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n1557), .CK(clk), .RN(n5956), .Q(
FPSENCOS_d_ff_Xn[13]), .QN(n5877) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n1561), .CK(clk), .RN(n5961), .Q(
FPSENCOS_d_ff_Xn[14]), .QN(n5876) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n1569), .CK(clk), .RN(n5959), .Q(
FPSENCOS_d_ff_Xn[16]), .QN(n5875) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n1573), .CK(clk), .RN(n5957), .Q(
FPSENCOS_d_ff_Xn[17]), .QN(n5874) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n1581), .CK(clk), .RN(n5958), .Q(
FPSENCOS_d_ff_Xn[19]), .QN(n5873) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n1585), .CK(clk), .RN(n5955), .Q(
FPSENCOS_d_ff_Xn[20]), .QN(n5872) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1601), .CK(clk), .RN(n5982), .Q(
FPSENCOS_d_ff_Xn[24]), .QN(n5871) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1605), .CK(clk), .RN(n5983), .Q(
FPSENCOS_d_ff_Xn[25]), .QN(n5870) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1609), .CK(clk), .RN(n5984), .Q(
FPSENCOS_d_ff_Xn[26]), .QN(n5869) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1613), .CK(clk), .RN(n5985), .Q(
FPSENCOS_d_ff_Xn[27]), .QN(n5868) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1617), .CK(clk), .RN(n5988), .Q(
FPSENCOS_d_ff_Xn[28]), .QN(n5867) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1426), .CK(clk), .RN(
n5982), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n5866) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk),
.RN(n5921), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[35]), .QN(n5865) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk),
.RN(n5921), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[34]), .QN(n5864) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1876), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[7]), .QN(n5863) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1879), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n5862) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk),
.RN(n5947), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[49]), .QN(n5859) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk),
.RN(n5920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[48]), .QN(n5858) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk),
.RN(n5919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[47]), .QN(n5857) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk),
.RN(n5920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[44]), .QN(n5856) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk),
.RN(n5920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[45]), .QN(n5855) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1421), .CK(clk), .RN(
n5988), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n5853) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1790), .CK(clk), .RN(
n5982), .Q(FPSENCOS_d_ff2_X[23]), .QN(n5852) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk),
.RN(n5945), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[51]), .QN(n5848) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1875), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n5847) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1873), .CK(
clk), .RN(n5992), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n5846) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n1827), .CK(clk), .RN(n5969),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n5845) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_3_ ( .D(n1293), .CK(clk), .RN(n5924), .Q(
FPADDSUB_intDY[3]), .QN(n5843) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_8_ ( .D(n1273), .CK(clk), .RN(n5926), .Q(
FPADDSUB_intDY[8]), .QN(n5842) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1686), .CK(
clk), .RN(n5933), .Q(overflow_flag_addsubt), .QN(n5841) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_9_ ( .D(n1228), .CK(clk), .RN(n5932), .Q(
FPADDSUB_intDY[9]), .QN(n5840) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_2_ ( .D(n1286), .CK(clk), .RN(n5924), .Q(
FPADDSUB_intDY[2]), .QN(n5839) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_10_ ( .D(n1245), .CK(clk), .RN(n3894), .Q(
FPADDSUB_intDY[10]), .QN(n5838) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_4_ ( .D(n1252), .CK(clk), .RN(n5933), .Q(
FPADDSUB_intDY[4]), .QN(n5837) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_6_ ( .D(n1296), .CK(clk), .RN(n5924), .Q(
FPADDSUB_intDY[6]), .QN(n5836) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1600), .CK(clk), .RN(n5919), .Q(result_add_subt[23]), .QN(n5835) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1841), .CK(clk), .RN(n5918), .QN(n5834) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1552), .CK(clk), .RN(n5921), .QN(n5833) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1568), .CK(clk), .RN(n5916), .QN(n5832) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1580), .CK(clk), .RN(n5915), .QN(n5831) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1592), .CK(clk), .RN(n5916), .QN(n5830) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1596), .CK(clk), .RN(n5919), .QN(n5829) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_5_ ( .D(n1259), .CK(clk), .RN(n5948), .Q(
FPADDSUB_intDY[5]), .QN(n5824) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_7_ ( .D(n1238), .CK(clk), .RN(n5931), .Q(
FPADDSUB_intDY[7]), .QN(n5823) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1650),
.CK(clk), .RN(n5944), .Q(FPADDSUB_Sgf_normalized_result[21]), .QN(
n5822) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1651),
.CK(clk), .RN(n5944), .Q(FPADDSUB_Sgf_normalized_result[22]), .QN(
n5821) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n1667),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[7]), .QN(n5820) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n1662),
.CK(clk), .RN(n5938), .Q(FPADDSUB_Add_Subt_result[2]), .QN(n5819) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n1671),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[11]), .QN(n5818) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_23_ ( .D(n1331), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDY[23]), .QN(n5816) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(n5928), .Q(
FPADDSUB_intDX[16]), .QN(n5815) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_29_ ( .D(n1337), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDY[29]), .QN(n5814) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1648),
.CK(clk), .RN(n5944), .Q(FPADDSUB_Sgf_normalized_result[19]), .QN(
n5812) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_10_ ( .D(n1246), .CK(clk), .RN(n5927), .Q(
FPADDSUB_intDX[10]), .QN(n5809) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n1663),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[3]), .QN(n5806) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_26_ ( .D(n1334), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDY[26]), .QN(n5805) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_23_ ( .D(n1305), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[23]), .QN(n5803) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1425), .CK(clk), .RN(
n5983), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n5802) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_12_ ( .D(n1232), .CK(clk), .RN(n5931), .Q(
FPADDSUB_intDY[12]), .QN(n5801) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_11_ ( .D(n1236), .CK(clk), .RN(n5948), .Q(
FPADDSUB_intDX[11]), .QN(n5800) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_14_ ( .D(n1243), .CK(clk), .RN(n5933), .Q(
FPADDSUB_intDX[14]), .QN(n5799) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_19_ ( .D(n1291), .CK(clk), .RN(n5924), .Q(
FPADDSUB_intDX[19]), .QN(n5798) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_24_ ( .D(n1332), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDY[24]), .QN(n5797) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_17_ ( .D(n1257), .CK(clk), .RN(n5928), .Q(
FPADDSUB_intDX[17]), .QN(n5796) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_20_ ( .D(n1268), .CK(clk), .RN(n5926), .Q(
FPADDSUB_intDX[20]), .QN(n5795) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_18_ ( .D(n1281), .CK(clk), .RN(n5925), .Q(
FPADDSUB_intDX[18]), .QN(n5794) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_22_ ( .D(n1300), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[22]), .QN(n5793) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_28_ ( .D(n1336), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDY[28]), .QN(n5792) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_25_ ( .D(n1333), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDY[25]), .QN(n5791) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1644),
.CK(clk), .RN(n5943), .Q(FPADDSUB_Sgf_normalized_result[15]), .QN(
n5790) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1645),
.CK(clk), .RN(n5943), .Q(FPADDSUB_Sgf_normalized_result[16]), .QN(
n5789) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1874), .CK(
clk), .RN(n5992), .Q(FPMULT_Sgf_normalized_result[5]), .QN(n5788) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1878), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n5787) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_18_ ( .D(n1280), .CK(clk), .RN(n5925), .Q(
FPADDSUB_intDY[18]), .QN(n5785) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_17_ ( .D(n1256), .CK(clk), .RN(n5929), .Q(
FPADDSUB_intDY[17]), .QN(n5784) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1872), .CK(
clk), .RN(n5992), .Q(FPMULT_Sgf_normalized_result[3]), .QN(n5783) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_21_ ( .D(n1283), .CK(clk), .RN(n5925), .Q(
FPADDSUB_intDY[21]), .QN(n5782) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_13_ ( .D(n1263), .CK(clk), .RN(n5926), .Q(
FPADDSUB_intDY[13]), .QN(n5781) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_28_ ( .D(n1320), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[28]), .QN(n5780) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_20_ ( .D(n1267), .CK(clk), .RN(n5926), .Q(
FPADDSUB_intDY[20]), .QN(n5779) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_13_ ( .D(n1264), .CK(clk), .RN(n5926), .Q(
FPADDSUB_intDX[13]), .QN(n5778) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_21_ ( .D(n1284), .CK(clk), .RN(n5925), .Q(
FPADDSUB_intDX[21]), .QN(n5777) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1641),
.CK(clk), .RN(n5942), .Q(FPADDSUB_Sgf_normalized_result[12]), .QN(
n5774) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1643),
.CK(clk), .RN(n5943), .Q(FPADDSUB_Sgf_normalized_result[14]), .QN(
n5772) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_11_ ( .D(n1235), .CK(clk), .RN(n5932), .Q(
FPADDSUB_intDY[11]), .QN(n5769) );
DFFRX2TS FPSENCOS_cordic_FSM_state_reg_reg_2_ ( .D(n2060), .CK(clk), .RN(
n5917), .Q(FPSENCOS_cordic_FSM_state_reg[2]), .QN(n5767) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_14_ ( .D(n1242), .CK(clk), .RN(n5928), .Q(
FPADDSUB_intDY[14]), .QN(n5766) );
DFFRX2TS FPSENCOS_cordic_FSM_state_reg_reg_3_ ( .D(n2061), .CK(clk), .RN(
n5918), .Q(FPSENCOS_cordic_FSM_state_reg[3]), .QN(n5765) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1792), .CK(clk), .RN(
n5983), .Q(FPSENCOS_d_ff2_X[25]), .QN(n5763) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1793), .CK(clk), .RN(
n5984), .Q(FPSENCOS_d_ff2_X[26]), .QN(n5762) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1796), .CK(clk), .RN(
n5988), .Q(FPSENCOS_d_ff2_X[29]), .QN(n5761) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk),
.RN(n5933), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[50]), .QN(n5760) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1794), .CK(clk), .RN(
n5985), .Q(FPSENCOS_d_ff2_X[27]), .QN(n5758) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1628), .CK(clk), .RN(n5918), .Q(result_add_subt[30]), .QN(n5757) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1604), .CK(clk), .RN(n5919), .Q(result_add_subt[24]), .QN(n5756) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1608), .CK(clk), .RN(n5919), .Q(result_add_subt[25]), .QN(n5755) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1612), .CK(clk), .RN(n5919), .Q(result_add_subt[26]), .QN(n5754) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1616), .CK(clk), .RN(n5918), .Q(result_add_subt[27]), .QN(n5753) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1620), .CK(clk), .RN(n5918), .Q(result_add_subt[28]), .QN(n5752) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1624), .CK(clk), .RN(n5918), .Q(result_add_subt[29]), .QN(n5751) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1548), .CK(clk), .RN(n5921), .QN(n5750) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1556), .CK(clk), .RN(n5921), .QN(n5749) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1560), .CK(clk), .RN(n5920), .QN(n5748) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1564), .CK(clk), .RN(n5921), .QN(n5747) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1572), .CK(clk), .RN(n5920), .QN(n5746) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1576), .CK(clk), .RN(n5920), .QN(n5745) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1584), .CK(clk), .RN(n5914), .QN(n5744) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1588), .CK(clk), .RN(n5920), .QN(n5743) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1653),
.CK(clk), .RN(n5945), .Q(FPADDSUB_Sgf_normalized_result[24]), .QN(
n5742) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1959), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[8]), .QN(n5741) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1652),
.CK(clk), .RN(n5944), .Q(FPADDSUB_Sgf_normalized_result[23]), .QN(
n5740) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1791), .CK(clk), .RN(
n5982), .Q(FPSENCOS_d_ff2_X[24]), .QN(n5738) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1649),
.CK(clk), .RN(n5944), .Q(FPADDSUB_Sgf_normalized_result[20]), .QN(
n5737) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_30_ ( .D(n1338), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDY[30]), .QN(n5736) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_7_ ( .D(n1239), .CK(clk), .RN(n5946), .Q(
FPADDSUB_intDX[7]), .QN(n5735) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_5_ ( .D(n1260), .CK(clk), .RN(n5946), .Q(
FPADDSUB_intDX[5]), .QN(n5734) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_9_ ( .D(n1229), .CK(clk), .RN(n5946), .Q(
FPADDSUB_intDX[9]), .QN(n5733) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_8_ ( .D(n1274), .CK(clk), .RN(n5946), .Q(
FPADDSUB_intDX[8]), .QN(n5732) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n1702), .CK(clk), .RN(n5976),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n5731) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_0_ ( .D(n1339), .CK(clk), .RN(n5945), .Q(
FPADDSUB_intDY[0]), .QN(n5730) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_27_ ( .D(n1335), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDY[27]), .QN(n5729) );
DFFRX2TS FPSENCOS_cont_var_count_reg_1_ ( .D(n1833), .CK(clk), .RN(n5949),
.Q(FPSENCOS_cont_var_out[1]), .QN(n5728) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1642),
.CK(clk), .RN(n5942), .Q(FPADDSUB_Sgf_normalized_result[13]), .QN(
n5727) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1646),
.CK(clk), .RN(n5943), .Q(FPADDSUB_Sgf_normalized_result[17]), .QN(
n5726) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1877), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n5725) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_19_ ( .D(n1290), .CK(clk), .RN(n5924), .Q(
FPADDSUB_intDY[19]), .QN(n5723) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_22_ ( .D(n1299), .CK(clk), .RN(n5924), .Q(
FPADDSUB_intDY[22]), .QN(n5722) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_15_ ( .D(n1276), .CK(clk), .RN(n5925), .Q(
FPADDSUB_intDY[15]), .QN(n5718) );
DFFRX2TS FPSENCOS_cordic_FSM_state_reg_reg_0_ ( .D(n2059), .CK(clk), .RN(
n5917), .Q(FPSENCOS_cordic_FSM_state_reg[0]), .QN(n5717) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1795), .CK(clk), .RN(
n5988), .QN(n5716) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_4_ ( .D(n1253), .CK(clk), .RN(n5946), .Q(
FPADDSUB_intDX[4]), .QN(n5715) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_6_ ( .D(n1297), .CK(clk), .RN(n5946), .Q(
FPADDSUB_intDX[6]), .QN(n5714) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_15_ ( .D(n1277), .CK(clk), .RN(n5925), .Q(
FPADDSUB_intDX[15]), .QN(n5713) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n5917), .Q(NaN_flag)
);
DFFRX1TS FPADDSUB_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1327),
.CK(clk), .RN(n5940), .Q(FPADDSUB_sign_final_result), .QN(n5861) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk),
.RN(n5928), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[46]), .QN(n5860) );
DFFRX2TS FPSENCOS_cont_var_count_reg_0_ ( .D(n1834), .CK(clk), .RN(n5968),
.Q(FPSENCOS_cont_var_out[0]), .QN(n5804) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_2_ ( .D(n1287), .CK(clk), .RN(n5945), .Q(
FPADDSUB_intDX[2]), .QN(n5811) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_3_ ( .D(n1294), .CK(clk), .RN(n5945), .Q(
FPADDSUB_intDX[3]), .QN(n5786) );
DFFRX2TS FPSENCOS_cont_iter_count_reg_3_ ( .D(n1832), .CK(clk), .RN(n5969),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n5764) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[23]) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n1678),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[18]), .QN(n5720) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_1_ ( .D(n1270), .CK(clk), .RN(n5926), .Q(
FPADDSUB_intDY[1]), .QN(n5844) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1986), .CK(clk), .RN(n5995), .Q(
FPMULT_FSM_selector_B[1]), .QN(n5724) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_1_ ( .D(n1271), .CK(clk), .RN(n5945), .Q(
FPADDSUB_intDX[1]), .QN(n5810) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n1676),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[16]), .QN(n5739) );
CMPR42X1TS DP_OP_498J12_123_5135_U319 ( .A(DP_OP_498J12_123_5135_n447), .B(
DP_OP_498J12_123_5135_n363), .C(DP_OP_498J12_123_5135_n364), .D(
DP_OP_498J12_123_5135_n460), .ICI(DP_OP_498J12_123_5135_n473), .S(
DP_OP_498J12_123_5135_n361), .ICO(DP_OP_498J12_123_5135_n359), .CO(
DP_OP_498J12_123_5135_n360) );
CMPR42X2TS DP_OP_498J12_123_5135_U309 ( .A(DP_OP_498J12_123_5135_n456), .B(
DP_OP_498J12_123_5135_n469), .C(DP_OP_498J12_123_5135_n345), .D(
DP_OP_498J12_123_5135_n341), .ICI(DP_OP_498J12_123_5135_n338), .S(
DP_OP_498J12_123_5135_n335), .ICO(DP_OP_498J12_123_5135_n333), .CO(
DP_OP_498J12_123_5135_n334) );
CMPR42X1TS DP_OP_498J12_123_5135_U307 ( .A(DP_OP_498J12_123_5135_n339), .B(
DP_OP_498J12_123_5135_n332), .C(DP_OP_498J12_123_5135_n442), .D(
DP_OP_498J12_123_5135_n429), .ICI(DP_OP_498J12_123_5135_n455), .S(
DP_OP_498J12_123_5135_n330), .ICO(DP_OP_498J12_123_5135_n328), .CO(
DP_OP_498J12_123_5135_n329) );
CMPR42X2TS DP_OP_498J12_123_5135_U303 ( .A(DP_OP_498J12_123_5135_n441), .B(
DP_OP_498J12_123_5135_n454), .C(DP_OP_498J12_123_5135_n329), .D(
DP_OP_498J12_123_5135_n325), .ICI(DP_OP_498J12_123_5135_n322), .S(
DP_OP_498J12_123_5135_n319), .ICO(DP_OP_498J12_123_5135_n317), .CO(
DP_OP_498J12_123_5135_n318) );
CMPR42X2TS DP_OP_498J12_123_5135_U300 ( .A(DP_OP_498J12_123_5135_n315), .B(
DP_OP_498J12_123_5135_n427), .C(DP_OP_498J12_123_5135_n414), .D(
DP_OP_498J12_123_5135_n323), .ICI(DP_OP_498J12_123_5135_n320), .S(
DP_OP_498J12_123_5135_n313), .ICO(DP_OP_498J12_123_5135_n311), .CO(
DP_OP_498J12_123_5135_n312) );
CMPR42X2TS DP_OP_498J12_123_5135_U299 ( .A(DP_OP_498J12_123_5135_n453), .B(
DP_OP_498J12_123_5135_n440), .C(DP_OP_498J12_123_5135_n321), .D(
DP_OP_498J12_123_5135_n313), .ICI(DP_OP_498J12_123_5135_n317), .S(
DP_OP_498J12_123_5135_n310), .ICO(DP_OP_498J12_123_5135_n308), .CO(
DP_OP_498J12_123_5135_n309) );
CMPR42X2TS DP_OP_498J12_123_5135_U295 ( .A(DP_OP_498J12_123_5135_n426), .B(
DP_OP_498J12_123_5135_n439), .C(DP_OP_498J12_123_5135_n312), .D(
DP_OP_498J12_123_5135_n303), .ICI(DP_OP_498J12_123_5135_n308), .S(
DP_OP_498J12_123_5135_n300), .ICO(DP_OP_498J12_123_5135_n298), .CO(
DP_OP_498J12_123_5135_n299) );
CMPR42X1TS DP_OP_498J12_123_5135_U290 ( .A(DP_OP_498J12_123_5135_n388), .B(
DP_OP_498J12_123_5135_n290), .C(DP_OP_498J12_123_5135_n437), .D(
DP_OP_498J12_123_5135_n399), .ICI(DP_OP_498J12_123_5135_n294), .S(
DP_OP_498J12_123_5135_n288), .ICO(DP_OP_498J12_123_5135_n286), .CO(
DP_OP_498J12_123_5135_n287) );
CMPR42X2TS DP_OP_498J12_123_5135_U289 ( .A(DP_OP_498J12_123_5135_n411), .B(
DP_OP_498J12_123_5135_n424), .C(DP_OP_498J12_123_5135_n295), .D(
DP_OP_498J12_123_5135_n288), .ICI(DP_OP_498J12_123_5135_n291), .S(
DP_OP_498J12_123_5135_n285), .ICO(DP_OP_498J12_123_5135_n283), .CO(
DP_OP_498J12_123_5135_n284) );
CMPR42X1TS DP_OP_498J12_123_5135_U288 ( .A(DP_OP_498J12_123_5135_n436), .B(
DP_OP_498J12_123_5135_n289), .C(DP_OP_498J12_123_5135_n387), .D(
DP_OP_498J12_123_5135_n398), .ICI(DP_OP_498J12_123_5135_n423), .S(
DP_OP_498J12_123_5135_n282), .ICO(DP_OP_498J12_123_5135_n280), .CO(
DP_OP_498J12_123_5135_n281) );
CMPR42X2TS DP_OP_498J12_123_5135_U284 ( .A(DP_OP_498J12_123_5135_n397), .B(
DP_OP_498J12_123_5135_n409), .C(DP_OP_498J12_123_5135_n274), .D(
DP_OP_498J12_123_5135_n281), .ICI(DP_OP_498J12_123_5135_n277), .S(
DP_OP_498J12_123_5135_n272), .ICO(DP_OP_498J12_123_5135_n270), .CO(
DP_OP_498J12_123_5135_n271) );
CMPR42X1TS DP_OP_498J12_123_5135_U280 ( .A(DP_OP_498J12_123_5135_n264), .B(
DP_OP_498J12_123_5135_n385), .C(DP_OP_498J12_123_5135_n268), .D(
DP_OP_498J12_123_5135_n395), .ICI(DP_OP_498J12_123_5135_n265), .S(
DP_OP_498J12_123_5135_n262), .ICO(DP_OP_498J12_123_5135_n260), .CO(
DP_OP_498J12_123_5135_n261) );
CMPR42X2TS mult_x_121_U209 ( .A(mult_x_121_n350), .B(mult_x_121_n338), .C(
mult_x_121_n302), .D(mult_x_121_n236), .ICI(mult_x_121_n240), .S(
mult_x_121_n234), .ICO(mult_x_121_n232), .CO(mult_x_121_n233) );
CMPR42X1TS mult_x_121_U208 ( .A(mult_x_121_n326), .B(mult_x_121_n314), .C(
mult_x_121_n237), .D(mult_x_121_n241), .ICI(mult_x_121_n234), .S(
mult_x_121_n231), .ICO(mult_x_121_n229), .CO(mult_x_121_n230) );
CMPR42X2TS mult_x_121_U206 ( .A(mult_x_121_n313), .B(mult_x_121_n337), .C(
mult_x_121_n301), .D(mult_x_121_n235), .ICI(mult_x_121_n232), .S(
mult_x_121_n226), .ICO(mult_x_121_n224), .CO(mult_x_121_n225) );
CMPR42X2TS mult_x_121_U205 ( .A(mult_x_121_n325), .B(mult_x_121_n228), .C(
mult_x_121_n233), .D(mult_x_121_n226), .ICI(mult_x_121_n229), .S(
mult_x_121_n223), .ICO(mult_x_121_n221), .CO(mult_x_121_n222) );
CMPR42X2TS mult_x_121_U201 ( .A(mult_x_121_n227), .B(mult_x_121_n219), .C(
mult_x_121_n225), .D(mult_x_121_n217), .ICI(mult_x_121_n221), .S(
mult_x_121_n214), .ICO(mult_x_121_n212), .CO(mult_x_121_n213) );
CMPR42X1TS mult_x_121_U198 ( .A(mult_x_121_n311), .B(mult_x_121_n335), .C(
mult_x_121_n323), .D(mult_x_121_n209), .ICI(mult_x_121_n215), .S(
mult_x_121_n207), .ICO(mult_x_121_n205), .CO(mult_x_121_n206) );
CMPR42X1TS mult_x_121_U194 ( .A(mult_x_121_n298), .B(mult_x_121_n334), .C(
mult_x_121_n206), .D(mult_x_121_n199), .ICI(mult_x_121_n202), .S(
mult_x_121_n196), .ICO(mult_x_121_n194), .CO(mult_x_121_n195) );
CMPR42X2TS mult_x_121_U191 ( .A(mult_x_121_n200), .B(mult_x_121_n197), .C(
mult_x_121_n191), .D(mult_x_121_n198), .ICI(mult_x_121_n194), .S(
mult_x_121_n188), .ICO(mult_x_121_n186), .CO(mult_x_121_n187) );
CMPR42X1TS mult_x_121_U189 ( .A(mult_x_121_n320), .B(mult_x_121_n189), .C(
mult_x_121_n190), .D(mult_x_121_n185), .ICI(mult_x_121_n186), .S(
mult_x_121_n182), .ICO(mult_x_121_n180), .CO(mult_x_121_n181) );
CMPR42X1TS mult_x_159_U222 ( .A(mult_x_159_n327), .B(mult_x_159_n339), .C(
mult_x_159_n351), .D(mult_x_159_n363), .ICI(mult_x_159_n267), .S(
mult_x_159_n264), .ICO(mult_x_159_n262), .CO(mult_x_159_n263) );
CMPR42X2TS mult_x_159_U220 ( .A(mult_x_159_n350), .B(mult_x_159_n326), .C(
mult_x_159_n338), .D(mult_x_159_n261), .ICI(mult_x_159_n262), .S(
mult_x_159_n259), .ICO(mult_x_159_n257), .CO(mult_x_159_n258) );
CMPR42X2TS mult_x_159_U215 ( .A(mult_x_159_n348), .B(mult_x_159_n251), .C(
mult_x_159_n255), .D(mult_x_159_n249), .ICI(mult_x_159_n252), .S(
mult_x_159_n247), .ICO(mult_x_159_n245), .CO(mult_x_159_n246) );
CMPR42X1TS mult_x_159_U214 ( .A(mult_x_159_n299), .B(mult_x_159_n323), .C(
mult_x_159_n347), .D(mult_x_159_n311), .ICI(mult_x_159_n248), .S(
mult_x_159_n244), .ICO(mult_x_159_n242), .CO(mult_x_159_n243) );
CMPR42X2TS mult_x_159_U213 ( .A(mult_x_159_n335), .B(mult_x_159_n359), .C(
mult_x_159_n250), .D(mult_x_159_n245), .ICI(mult_x_159_n244), .S(
mult_x_159_n241), .ICO(mult_x_159_n239), .CO(mult_x_159_n240) );
CMPR42X1TS mult_x_159_U210 ( .A(mult_x_159_n346), .B(mult_x_159_n238), .C(
mult_x_159_n242), .D(mult_x_159_n243), .ICI(mult_x_159_n236), .S(
mult_x_159_n233), .ICO(mult_x_159_n231), .CO(mult_x_159_n232) );
CMPR42X1TS mult_x_159_U208 ( .A(mult_x_159_n321), .B(mult_x_159_n345), .C(
mult_x_159_n297), .D(mult_x_159_n357), .ICI(mult_x_159_n230), .S(
mult_x_159_n228), .ICO(mult_x_159_n226), .CO(mult_x_159_n227) );
CMPR42X2TS mult_x_159_U207 ( .A(mult_x_159_n237), .B(mult_x_159_n234), .C(
mult_x_159_n231), .D(mult_x_159_n235), .ICI(mult_x_159_n228), .S(
mult_x_159_n225), .ICO(mult_x_159_n223), .CO(mult_x_159_n224) );
CMPR42X1TS mult_x_159_U204 ( .A(mult_x_159_n320), .B(mult_x_159_n344), .C(
mult_x_159_n296), .D(n2336), .ICI(mult_x_159_n221), .S(mult_x_159_n219), .ICO(mult_x_159_n217), .CO(mult_x_159_n218) );
CMPR42X2TS mult_x_159_U203 ( .A(mult_x_159_n226), .B(mult_x_159_n229), .C(
mult_x_159_n227), .D(mult_x_159_n223), .ICI(mult_x_159_n219), .S(
mult_x_159_n216), .ICO(mult_x_159_n214), .CO(mult_x_159_n215) );
CMPR42X1TS mult_x_159_U200 ( .A(mult_x_159_n307), .B(mult_x_159_n343), .C(
mult_x_159_n331), .D(mult_x_159_n295), .ICI(mult_x_159_n220), .S(
mult_x_159_n209), .ICO(mult_x_159_n207), .CO(mult_x_159_n208) );
CMPR42X2TS mult_x_159_U199 ( .A(mult_x_159_n211), .B(mult_x_159_n217), .C(
mult_x_159_n218), .D(mult_x_159_n209), .ICI(mult_x_159_n214), .S(
mult_x_159_n206), .ICO(mult_x_159_n204), .CO(mult_x_159_n205) );
CMPR42X2TS mult_x_159_U197 ( .A(mult_x_159_n306), .B(mult_x_159_n330), .C(
mult_x_159_n294), .D(mult_x_159_n342), .ICI(mult_x_159_n207), .S(
mult_x_159_n201), .ICO(mult_x_159_n199), .CO(mult_x_159_n200) );
CMPR42X2TS mult_x_159_U196 ( .A(mult_x_159_n210), .B(mult_x_159_n203), .C(
mult_x_159_n208), .D(mult_x_159_n201), .ICI(mult_x_159_n204), .S(
mult_x_159_n198), .ICO(mult_x_159_n196), .CO(mult_x_159_n197) );
CMPR42X1TS mult_x_159_U194 ( .A(mult_x_159_n195), .B(mult_x_159_n329), .C(
mult_x_159_n317), .D(mult_x_159_n305), .ICI(mult_x_159_n202), .S(
mult_x_159_n193), .ICO(mult_x_159_n191), .CO(mult_x_159_n192) );
CMPR42X1TS mult_x_159_U192 ( .A(mult_x_159_n194), .B(mult_x_159_n282), .C(
mult_x_159_n316), .D(mult_x_159_n304), .ICI(mult_x_159_n328), .S(
mult_x_159_n187), .ICO(mult_x_159_n185), .CO(mult_x_159_n186) );
CMPR42X1TS mult_x_159_U191 ( .A(mult_x_159_n292), .B(mult_x_159_n191), .C(
mult_x_159_n187), .D(mult_x_159_n192), .ICI(mult_x_159_n188), .S(
mult_x_159_n184), .ICO(mult_x_159_n182), .CO(mult_x_159_n183) );
CMPR42X2TS DP_OP_498J12_123_5135_U292 ( .A(DP_OP_498J12_123_5135_n438), .B(
DP_OP_498J12_123_5135_n425), .C(DP_OP_498J12_123_5135_n302), .D(
DP_OP_498J12_123_5135_n296), .ICI(DP_OP_498J12_123_5135_n298), .S(
DP_OP_498J12_123_5135_n293), .ICO(DP_OP_498J12_123_5135_n291), .CO(
DP_OP_498J12_123_5135_n292) );
CMPR42X2TS mult_x_121_U197 ( .A(mult_x_121_n299), .B(mult_x_121_n218), .C(
mult_x_121_n216), .D(mult_x_121_n207), .ICI(mult_x_121_n212), .S(
mult_x_121_n204), .ICO(mult_x_121_n202), .CO(mult_x_121_n203) );
CMPR42X2TS DP_OP_498J12_123_5135_U317 ( .A(DP_OP_498J12_123_5135_n362), .B(
DP_OP_498J12_123_5135_n358), .C(DP_OP_498J12_123_5135_n472), .D(
DP_OP_498J12_123_5135_n459), .ICI(DP_OP_498J12_123_5135_n359), .S(
DP_OP_498J12_123_5135_n356), .ICO(DP_OP_498J12_123_5135_n354), .CO(
DP_OP_498J12_123_5135_n355) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n2000), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[10]) );
CMPR42X2TS DP_OP_498J12_123_5135_U287 ( .A(DP_OP_498J12_123_5135_n410), .B(
DP_OP_498J12_123_5135_n286), .C(DP_OP_498J12_123_5135_n282), .D(
DP_OP_498J12_123_5135_n287), .ICI(DP_OP_498J12_123_5135_n283), .S(
DP_OP_498J12_123_5135_n279), .ICO(DP_OP_498J12_123_5135_n277), .CO(
DP_OP_498J12_123_5135_n278) );
CMPR42X2TS DP_OP_498J12_123_5135_U293 ( .A(DP_OP_498J12_123_5135_n297), .B(
DP_OP_498J12_123_5135_n412), .C(DP_OP_498J12_123_5135_n400), .D(
DP_OP_498J12_123_5135_n304), .ICI(DP_OP_498J12_123_5135_n301), .S(
DP_OP_498J12_123_5135_n296), .ICO(DP_OP_498J12_123_5135_n294), .CO(
DP_OP_498J12_123_5135_n295) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n1659),
.CK(clk), .RN(n5945), .Q(FPADDSUB_Add_Subt_result[25]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n1682),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[22]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1998), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[8]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_0_ ( .D(n1302), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[0]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n2012), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[22]), .QN(n2334) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n2008), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[18]), .QN(n2337) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n2001), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[11]), .QN(DP_OP_498J12_123_5135_n727) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1999), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[9]), .QN(n2338) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(
n1844), .CK(clk), .RN(n5940), .Q(FPADDSUB_add_overflow_flag) );
DFFRX2TS FPADDSUB_Sel_B_Q_reg_0_ ( .D(n1695), .CK(clk), .RN(n1340), .Q(
FPADDSUB_FSM_selector_B[0]), .QN(n5770) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n2053), .CK(clk), .RN(n5989), .Q(
FPMULT_FSM_selector_A), .QN(n5850) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n2056), .CK(clk), .RN(n3897),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n5808) );
DFFRX2TS FPADDSUB_FS_Module_state_reg_reg_2_ ( .D(n1835), .CK(clk), .RN(
n5918), .Q(FPADDSUB_FS_Module_state_reg[2]), .QN(n5721) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n2054), .CK(clk), .RN(n5927),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n5854) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n2057), .CK(clk), .RN(n5935),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n5807) );
DFFRX2TS FPADDSUB_FS_Module_state_reg_reg_0_ ( .D(n1837), .CK(clk), .RN(
n5918), .Q(FPADDSUB_FS_Module_state_reg[0]), .QN(n5719) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n2022), .CK(clk),
.RN(n6002), .Q(FPMULT_Op_MX[0]), .QN(n2341) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[4]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]) );
DFFRX1TS FPADDSUB_ASRegister_Q_reg_0_ ( .D(n1328), .CK(clk), .RN(n5927), .Q(
FPADDSUB_intAS) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1614), .CK(clk), .RN(n5985), .Q(
FPSENCOS_d_ff_Yn[27]), .QN(n5887) );
MDFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_0_ ( .D0(
n2341), .D1(1'b1), .S0(n2323), .CK(clk), .Q(n5711) );
DFFRX2TS FPADDSUB_Sel_A_Q_reg_0_ ( .D(n1696), .CK(clk), .RN(n1340), .Q(
FPADDSUB_FSM_selector_A) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n2039), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[17]), .QN(n2359) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_25_ ( .D(n1311), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[25]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_30_ ( .D(n1326), .CK(clk), .RN(n5922), .Q(
FPADDSUB_intDX[30]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_29_ ( .D(n1323), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[29]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_26_ ( .D(n1314), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[26]) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n5930), .Q(
FPADDSUB_intDY[16]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_27_ ( .D(n1317), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[27]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_12_ ( .D(n1233), .CK(clk), .RN(n3894), .Q(
FPADDSUB_intDX[12]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n1670),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[10]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n1666),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[6]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n1661),
.CK(clk), .RN(n5938), .Q(FPADDSUB_Add_Subt_result[1]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1869), .CK(
clk), .RN(n5992), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n1664),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[4]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n1673),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[13]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n1674),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[14]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n1680),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[20]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n1683),
.CK(clk), .RN(n5938), .Q(FPADDSUB_Add_Subt_result[23]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1871), .CK(
clk), .RN(n5992), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n1672),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[12]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n1675),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[15]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n1668),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[8]) );
DFFRX2TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1422), .CK(clk), .RN(
n5985), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPADDSUB_Sel_B_Q_reg_1_ ( .D(n1843), .CK(clk), .RN(n1340), .Q(
FPADDSUB_FSM_selector_B[1]) );
DFFRX1TS FPSENCOS_reg_ch_mux_2_Q_reg_1_ ( .D(n1700), .CK(clk), .RN(n5977),
.Q(FPSENCOS_sel_mux_2_reg[1]) );
DFFRX1TS FPSENCOS_reg_ch_mux_1_Q_reg_0_ ( .D(n1703), .CK(clk), .RN(n5977),
.Q(FPSENCOS_sel_mux_1_reg) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk),
.RN(n5930), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk),
.RN(n5919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1420), .CK(clk), .RN(
n5988), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk),
.RN(n5921), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk),
.RN(n5946), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk),
.RN(n5921), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1630),
.CK(clk), .RN(n5940), .Q(FPADDSUB_Sgf_normalized_result[1]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1949), .CK(clk), .RN(
n5994), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1638),
.CK(clk), .RN(n5942), .Q(FPADDSUB_Sgf_normalized_result[9]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1637),
.CK(clk), .RN(n5941), .Q(FPADDSUB_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n2010), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[20]), .QN(n2360) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1631),
.CK(clk), .RN(n5940), .Q(FPADDSUB_Sgf_normalized_result[2]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1640),
.CK(clk), .RN(n5942), .Q(FPADDSUB_Sgf_normalized_result[11]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1639),
.CK(clk), .RN(n5942), .Q(FPADDSUB_Sgf_normalized_result[10]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1635),
.CK(clk), .RN(n5941), .Q(FPADDSUB_Sgf_normalized_result[6]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1636),
.CK(clk), .RN(n5941), .Q(FPADDSUB_Sgf_normalized_result[7]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1633),
.CK(clk), .RN(n5941), .Q(FPADDSUB_Sgf_normalized_result[4]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1880), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1882), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1884), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1886), .CK(
clk), .RN(n5994), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1888), .CK(
clk), .RN(n5994), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1890), .CK(
clk), .RN(n5994), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1881), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1883), .CK(
clk), .RN(n5993), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1885), .CK(
clk), .RN(n5994), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1887), .CK(
clk), .RN(n5994), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1889), .CK(
clk), .RN(n5994), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1891), .CK(
clk), .RN(n5994), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(
n1655), .CK(clk), .RN(n5939), .Q(FPADDSUB_LZA_output[3]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_47_ ( .D(n2058),
.CK(clk), .RN(n5927), .Q(FPMULT_P_Sgf[47]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n2049), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n2051), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(
n1654), .CK(clk), .RN(n5939), .Q(FPADDSUB_LZA_output[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1424), .CK(clk), .RN(
n5983), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1423), .CK(clk), .RN(
n5984), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n5915),
.Q(operation_reg[0]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n2046), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n2017), .CK(clk),
.RN(n5999), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1419), .CK(clk), .RN(
n5988), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1951), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1953), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1955), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1956), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1958), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n2013), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk),
.RN(n5921), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk),
.RN(n5920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk),
.RN(n5920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRX1TS FPSENCOS_reg_ch_mux_3_Q_reg_0_ ( .D(n1699), .CK(clk), .RN(n5977),
.Q(FPSENCOS_sel_mux_3_reg) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1840), .CK(clk), .RN(n5977), .Q(
FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n2020), .CK(clk),
.RN(n5999), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n1541), .CK(clk), .RN(n5965), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n1549), .CK(clk), .RN(n5963), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n1521), .CK(clk), .RN(n5958), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n1537), .CK(clk), .RN(n5953), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n1565), .CK(clk), .RN(n5952), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n1577), .CK(clk), .RN(n5951), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n1589), .CK(clk), .RN(n5950), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n1593), .CK(clk), .RN(n5980), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1597), .CK(clk), .RN(n5982), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1625), .CK(clk), .RN(n5988), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n1408), .CK(clk), .RN(n5977), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n2018), .CK(clk),
.RN(n5999), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(
n1657), .CK(clk), .RN(n5938), .Q(FPADDSUB_LZA_output[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1454), .CK(clk), .RN(
n5964), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1448), .CK(clk), .RN(
n5963), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1450), .CK(clk), .RN(
n5963), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1458), .CK(clk), .RN(
n5962), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1444), .CK(clk), .RN(
n5961), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1452), .CK(clk), .RN(
n5960), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1440), .CK(clk), .RN(
n5959), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1464), .CK(clk), .RN(
n5958), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1438), .CK(clk), .RN(
n5957), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1462), .CK(clk), .RN(
n5956), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1446), .CK(clk), .RN(
n5955), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1432), .CK(clk), .RN(
n5954), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1456), .CK(clk), .RN(
n5953), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1442), .CK(clk), .RN(
n5952), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1436), .CK(clk), .RN(
n5951), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1468), .CK(clk), .RN(
n5949), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1434), .CK(clk), .RN(
n5978), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1466), .CK(clk), .RN(
n5979), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1428), .CK(clk), .RN(
n5981), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1470), .CK(clk), .RN(
n5954), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1430), .CK(clk), .RN(
n5950), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1460), .CK(clk), .RN(
n5980), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1472), .CK(clk), .RN(
n5981), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1845),
.CK(clk), .RN(n5948), .Q(FPADDSUB_Sgf_normalized_result[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1410), .CK(clk), .RN(
n5978), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1475), .CK(clk), .RN(
n5968), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(
n1656), .CK(clk), .RN(n5940), .Q(FPADDSUB_LZA_output[2]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n2021), .CK(clk),
.RN(n6001), .Q(FPMULT_Op_MX[31]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_8_ ( .D(n1901),
.CK(clk), .RN(n3894), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_9_ ( .D(n1902),
.CK(clk), .RN(n5932), .Q(FPMULT_P_Sgf[9]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_20_ ( .D(n1913),
.CK(clk), .RN(n5929), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_22_ ( .D(n1915),
.CK(clk), .RN(n3897), .Q(FPMULT_P_Sgf[22]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n1669),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[9]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n5917), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n5914), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n5914), .Q(
dataA[29]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_1_ ( .D(n1894),
.CK(clk), .RN(n5930), .Q(FPMULT_P_Sgf[1]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_13_ ( .D(n1906),
.CK(clk), .RN(n5931), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n5916), .Q(
dataB[25]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1258), .CK(
clk), .RN(n5948), .Q(FPADDSUB_DmP[5]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1266), .CK(
clk), .RN(n5926), .Q(FPADDSUB_DmP[20]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1269), .CK(
clk), .RN(n5926), .Q(FPADDSUB_DmP[1]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1213), .CK(
clk), .RN(n5945), .Q(FPADDSUB_DMP[22]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1215), .CK(
clk), .RN(n5941), .Q(FPADDSUB_DMP[3]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1217), .CK(
clk), .RN(n5945), .Q(FPADDSUB_DMP[21]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1218), .CK(
clk), .RN(n5943), .Q(FPADDSUB_DMP[15]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1220), .CK(
clk), .RN(n5941), .Q(FPADDSUB_DMP[1]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1223), .CK(
clk), .RN(n5942), .Q(FPADDSUB_DMP[10]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1225), .CK(
clk), .RN(n5943), .Q(FPADDSUB_DMP[11]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1240), .CK(
clk), .RN(n5943), .Q(FPADDSUB_DMP[14]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1254), .CK(
clk), .RN(n5944), .Q(FPADDSUB_DMP[17]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1261), .CK(
clk), .RN(n5943), .Q(FPADDSUB_DMP[13]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1265), .CK(
clk), .RN(n5944), .Q(FPADDSUB_DMP[20]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1306), .CK(
clk), .RN(n5939), .Q(FPADDSUB_DMP[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n1801), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n1808), .CK(clk), .RN(n5971), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk),
.RN(n5921), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk),
.RN(n5920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk),
.RN(n5919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk),
.RN(n5919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n5917), .Q(
dataB[27]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_24_ ( .D(n1308), .CK(clk), .RN(n5923), .Q(
FPADDSUB_intDX[24]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n1660),
.CK(clk), .RN(n5945), .Q(FPADDSUB_Add_Subt_result[0]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1688), .CK(
clk), .RN(n5939), .Q(FPADDSUB_exp_oper_result[0]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1692), .CK(
clk), .RN(n5948), .Q(FPADDSUB_exp_oper_result[4]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1689), .CK(
clk), .RN(n5939), .Q(FPADDSUB_exp_oper_result[1]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1690), .CK(
clk), .RN(n5938), .Q(FPADDSUB_exp_oper_result[2]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1870), .CK(
clk), .RN(n5992), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1629),
.CK(clk), .RN(n5940), .Q(FPADDSUB_Sgf_normalized_result[0]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1961), .CK(clk),
.RN(n5999), .Q(FPMULT_Add_result[23]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_44_ ( .D(n1937),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[44]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1839), .CK(clk), .RN(
n5977), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n1665),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[5]), .QN(n5825) );
DFFRX4TS FPSENCOS_cordic_FSM_state_reg_reg_1_ ( .D(
FPSENCOS_cordic_FSM_state_next_1_), .CK(clk), .RN(n5918), .Q(
FPSENCOS_cordic_FSM_state_reg[1]), .QN(n5712) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_19_ ( .D(n1912),
.CK(clk), .RN(n5932), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_14_ ( .D(n1907),
.CK(clk), .RN(n5931), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_7_ ( .D(n1900),
.CK(clk), .RN(n5932), .Q(FPMULT_P_Sgf[7]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_0_ ( .D(n1893),
.CK(clk), .RN(n3897), .Q(FPMULT_P_Sgf[0]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_18_ ( .D(n1911),
.CK(clk), .RN(n3897), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_10_ ( .D(n1903),
.CK(clk), .RN(n5932), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_6_ ( .D(n1899),
.CK(clk), .RN(n3897), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_2_ ( .D(n1895),
.CK(clk), .RN(n3894), .Q(FPMULT_P_Sgf[2]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1988), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[31]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n5917), .Q(
dataB[28]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_21_ ( .D(n1914),
.CK(clk), .RN(n5931), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_12_ ( .D(n1905),
.CK(clk), .RN(n5930), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_11_ ( .D(n1904),
.CK(clk), .RN(n5931), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS FPSENCOS_reg_ch_mux_2_Q_reg_0_ ( .D(n1701), .CK(clk), .RN(n5977),
.Q(FPSENCOS_sel_mux_2_reg[0]), .QN(n5826) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1301), .CK(
clk), .RN(n5923), .Q(FPADDSUB_DmP[0]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1298), .CK(
clk), .RN(n5924), .Q(FPADDSUB_DmP[22]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1292), .CK(
clk), .RN(n5924), .Q(FPADDSUB_DmP[3]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1282), .CK(
clk), .RN(n5925), .Q(FPADDSUB_DmP[21]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1262), .CK(
clk), .RN(n5926), .Q(FPADDSUB_DmP[13]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1255), .CK(
clk), .RN(n3894), .Q(FPADDSUB_DmP[17]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1227), .CK(
clk), .RN(n5930), .Q(FPADDSUB_DmP[9]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1324), .CK(
clk), .RN(n5940), .Q(FPADDSUB_DMP[30]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1321), .CK(
clk), .RN(n5915), .Q(FPADDSUB_DMP[29]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1315), .CK(
clk), .RN(n5914), .Q(FPADDSUB_DMP[27]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1309), .CK(
clk), .RN(n5946), .Q(FPADDSUB_DMP[25]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1303), .CK(
clk), .RN(n5939), .Q(FPADDSUB_DMP[23]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1288), .CK(
clk), .RN(n5944), .Q(FPADDSUB_DMP[19]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1278), .CK(
clk), .RN(n5944), .Q(FPADDSUB_DMP[18]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1247), .CK(
clk), .RN(n5944), .Q(FPADDSUB_DMP[16]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1230), .CK(
clk), .RN(n5943), .Q(FPADDSUB_DMP[12]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1226), .CK(
clk), .RN(n5942), .Q(FPADDSUB_DMP[9]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1224), .CK(
clk), .RN(n5942), .Q(FPADDSUB_DMP[7]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1222), .CK(
clk), .RN(n5941), .Q(FPADDSUB_DMP[4]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1221), .CK(
clk), .RN(n5941), .Q(FPADDSUB_DMP[5]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1219), .CK(
clk), .RN(n5942), .Q(FPADDSUB_DMP[8]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1216), .CK(
clk), .RN(n5941), .Q(FPADDSUB_DMP[2]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1214), .CK(
clk), .RN(n5942), .Q(FPADDSUB_DMP[6]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1212), .CK(
clk), .RN(n5940), .Q(FPADDSUB_DMP[0]) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1418), .CK(clk), .RN(n5972),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRX1TS FPSENCOS_d_ff5_Q_reg_31_ ( .D(n1345), .CK(clk), .RN(n5978), .Q(
FPSENCOS_data_output2_31_) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_15_ ( .D(n1908),
.CK(clk), .RN(n5933), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_3_ ( .D(n1896),
.CK(clk), .RN(n5933), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_17_ ( .D(n1910),
.CK(clk), .RN(n5927), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_5_ ( .D(n1898),
.CK(clk), .RN(n5927), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n5916), .Q(
dataB[23]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_16_ ( .D(n1909),
.CK(clk), .RN(n5928), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_4_ ( .D(n1897),
.CK(clk), .RN(n5928), .Q(FPMULT_P_Sgf[4]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n5947), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n5914), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n5917), .Q(
dataB[26]) );
DFFRX1TS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1789), .CK(clk), .RN(n5973),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n5947), .Q(
dataA[23]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n5916), .Q(
dataB[24]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1474), .CK(clk), .RN(n5968), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk),
.RN(n5948), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk),
.RN(n5916), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1691), .CK(
clk), .RN(n5948), .Q(FPADDSUB_exp_oper_result[3]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n2047), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[25]) );
DFFSX1TS R_4 ( .D(n5912), .CK(clk), .SN(n5915), .Q(n6009) );
DFFSX1TS R_11 ( .D(n5911), .CK(clk), .SN(n5915), .Q(n6007) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n5915),
.Q(operation_reg[1]) );
DFFRX1TS R_12 ( .D(n5910), .CK(clk), .RN(n5915), .Q(n6006) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n2048), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n2052), .CK(clk),
.RN(n3892), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n2045), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n2050), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1983), .CK(clk), .RN(
n5999), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1982), .CK(clk), .RN(
n5999), .Q(FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1981), .CK(clk), .RN(
n5999), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1980), .CK(clk), .RN(
n6000), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1979), .CK(clk), .RN(
n6000), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1978), .CK(clk), .RN(
n6000), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1977), .CK(clk), .RN(
n6000), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1976), .CK(clk), .RN(
n6000), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1975), .CK(clk), .RN(
n6000), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1974), .CK(clk),
.RN(n6000), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1962), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1963), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1964), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1965), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1966), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1967), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1968), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1969), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1970), .CK(clk),
.RN(n6001), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1971), .CK(clk),
.RN(n6000), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1972), .CK(clk),
.RN(n6000), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1973), .CK(clk),
.RN(n6000), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n2019), .CK(clk),
.RN(n5999), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n2015), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1957), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1954), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1952), .CK(clk), .RN(
n5995), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1694), .CK(
clk), .RN(n5915), .Q(FPADDSUB_exp_oper_result[6]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1693), .CK(
clk), .RN(n5914), .Q(FPADDSUB_exp_oper_result[5]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1687), .CK(
clk), .RN(n5947), .Q(FPADDSUB_exp_oper_result[7]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n2016), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n2014), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_46_ ( .D(n1939),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[46]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_45_ ( .D(n1938),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_43_ ( .D(n1936),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_42_ ( .D(n1935),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_41_ ( .D(n1934),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_40_ ( .D(n1933),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_39_ ( .D(n1932),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_38_ ( .D(n1931),
.CK(clk), .RN(n5935), .Q(FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_37_ ( .D(n1930),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_36_ ( .D(n1929),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_35_ ( .D(n1928),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_34_ ( .D(n1927),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_33_ ( .D(n1926),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_32_ ( .D(n1925),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_31_ ( .D(n1924),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_30_ ( .D(n1923),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_29_ ( .D(n1922),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_28_ ( .D(n1921),
.CK(clk), .RN(n5934), .Q(FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_27_ ( .D(n1920),
.CK(clk), .RN(n5931), .Q(FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_26_ ( .D(n1919),
.CK(clk), .RN(n3897), .Q(FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_25_ ( .D(n1918),
.CK(clk), .RN(n5930), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_24_ ( .D(n1917),
.CK(clk), .RN(n5929), .Q(FPMULT_P_Sgf[24]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1984), .CK(clk), .RN(
n5999), .Q(FPMULT_Add_result[0]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n2037), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[15]), .QN(n2144) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n2034), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[12]), .QN(n2353) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n2007), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[17]), .QN(n2126) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n2041), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[19]), .QN(n2356) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n2026), .CK(clk),
.RN(n6002), .Q(FPMULT_Op_MX[4]), .QN(n2328) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n2023), .CK(clk),
.RN(n6002), .Q(n2124), .QN(n2324) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n2035), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[13]), .QN(n2348) );
DFFRX2TS FPSENCOS_cont_iter_count_reg_0_ ( .D(n1831), .CK(clk), .RN(n5978),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n5768) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n2009), .CK(clk),
.RN(n5998), .Q(n2122), .QN(n2128) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n2005), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[15]), .QN(n2127) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n2011), .CK(clk),
.RN(n5998), .Q(FPMULT_Op_MY[21]), .QN(n2123) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n2024), .CK(clk),
.RN(n6002), .Q(FPMULT_Op_MX[2]), .QN(n2351) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n2033), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[11]), .QN(n2322) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n2003), .CK(clk),
.RN(n5997), .Q(FPMULT_Op_MY[13]), .QN(n2343) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1992), .CK(clk),
.RN(n5996), .Q(FPMULT_Op_MY[2]) );
DFFRX2TS FPADDSUB_FS_Module_state_reg_reg_1_ ( .D(n1836), .CK(clk), .RN(
n5917), .Q(FPADDSUB_FS_Module_state_reg[1]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[14]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[1]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[5]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[7]) );
DFFHQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[8]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_31_ ( .D(n1330), .CK(clk), .RN(n5930), .Q(
FPADDSUB_intDY[31]) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_31_ ( .D(n1329), .CK(clk), .RN(n5929), .Q(
FPADDSUB_intDX[31]) );
DFFSX1TS R_3 ( .D(n5913), .CK(clk), .SN(n5914), .Q(n6008) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[22]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[21]) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1892), .CK(clk), .RN(n5994), .Q(
FPMULT_FSM_selector_C), .QN(n5828) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n1677),
.CK(clk), .RN(n5936), .Q(FPADDSUB_Add_Subt_result[17]), .QN(n5827) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1632),
.CK(clk), .RN(n5940), .Q(FPADDSUB_Sgf_normalized_result[3]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1634),
.CK(clk), .RN(n5941), .Q(FPADDSUB_Sgf_normalized_result[5]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]) );
DFFSX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n6005), .CK(clk), .SN(n5996), .Q(n5776),
.QN(FPMULT_FSM_selector_B[0]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1989), .CK(
clk), .RN(n5996), .Q(FPMULT_zero_flag), .QN(n5909) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n1679),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[19]), .QN(n5773) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1647),
.CK(clk), .RN(n5943), .Q(FPADDSUB_Sgf_normalized_result[18]), .QN(
n5813) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1950), .CK(clk), .RN(
n5992), .Q(underflow_flag_mult), .QN(n5849) );
DFFRXLTS FPADDSUB_Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n1842), .CK(
clk), .RN(n3897), .Q(underflow_flag_addsubt), .QN(n5759) );
DFFRXLTS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1960), .CK(clk),
.RN(n5999), .Q(FPMULT_FSM_add_overflow_flag), .QN(n5851) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n2044), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[22]), .QN(n2340) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n1684),
.CK(clk), .RN(n5938), .Q(FPADDSUB_Add_Subt_result[24]) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n2055), .CK(clk), .RN(n5927),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n2116) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n2029), .CK(clk),
.RN(n6002), .Q(FPMULT_Op_MX[7]), .QN(n2325) );
ADDFHX2TS DP_OP_134J12_124_859_U3 ( .A(DP_OP_134J12_124_859_n15), .B(
FPMULT_S_Oper_A_exp[7]), .CI(DP_OP_134J12_124_859_n3), .CO(
DP_OP_134J12_124_859_n2), .S(FPMULT_Exp_module_Data_S[7]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1997), .CK(clk),
.RN(n5996), .Q(FPMULT_Op_MY[7]), .QN(n2145) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n2042), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[20]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n2028), .CK(clk),
.RN(n6002), .Q(FPMULT_Op_MX[6]), .QN(n2143) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n2040), .CK(clk),
.RN(n6003), .Q(FPMULT_Op_MX[18]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n2043), .CK(clk),
.RN(n6004), .Q(FPMULT_Op_MX[21]), .QN(n2364) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n1681),
.CK(clk), .RN(n5937), .Q(FPADDSUB_Add_Subt_result[21]), .QN(n5817) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1994), .CK(clk),
.RN(n5996), .Q(FPMULT_Op_MY[4]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1991), .CK(clk),
.RN(n5996), .Q(FPMULT_Op_MY[1]), .QN(n2336) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n2031), .CK(clk),
.RN(n6002), .Q(FPMULT_Op_MX[9]), .QN(n2326) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1318), .CK(
clk), .RN(n5946), .Q(FPADDSUB_DMP[28]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1312), .CK(
clk), .RN(n5947), .Q(FPADDSUB_DMP[26]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[9]) );
DFFHQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[11]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[6]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[10]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_0_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[2]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_Data_S_o_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[3]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_0_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]) );
DFFQX4TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_Data_S_o_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[17]) );
DFFQX2TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[16]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_Data_S_o_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19), .CK(clk), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[19]) );
DFFRX2TS FPADDSUB_Sel_C_Q_reg_0_ ( .D(n1685), .CK(clk), .RN(n1340), .Q(
FPADDSUB_FSM_selector_C), .QN(n5771) );
CMPR42X1TS mult_x_121_U220 ( .A(mult_x_121_n319), .B(mult_x_121_n355), .C(
mult_x_121_n343), .D(mult_x_121_n331), .ICI(mult_x_121_n265), .S(
mult_x_121_n262), .ICO(mult_x_121_n260), .CO(mult_x_121_n261) );
CMPR42X1TS mult_x_121_U216 ( .A(mult_x_121_n329), .B(mult_x_121_n317), .C(
mult_x_121_n258), .D(mult_x_121_n255), .ICI(mult_x_121_n254), .S(
mult_x_121_n252), .ICO(mult_x_121_n250), .CO(mult_x_121_n251) );
CMPR42X1TS mult_x_121_U212 ( .A(mult_x_121_n291), .B(mult_x_121_n351), .C(
mult_x_121_n339), .D(mult_x_121_n327), .ICI(mult_x_121_n248), .S(
mult_x_121_n242), .ICO(mult_x_121_n240), .CO(mult_x_121_n241) );
CMPR42X1TS mult_x_121_U195 ( .A(mult_x_121_n310), .B(mult_x_121_n322), .C(
mult_x_121_n208), .D(mult_x_121_n201), .ICI(mult_x_121_n205), .S(
mult_x_121_n199), .ICO(mult_x_121_n197), .CO(mult_x_121_n198) );
CMPR42X1TS mult_x_121_U192 ( .A(n2345), .B(mult_x_121_n285), .C(
mult_x_121_n321), .D(mult_x_121_n297), .ICI(mult_x_121_n309), .S(
mult_x_121_n191), .ICO(mult_x_121_n189), .CO(mult_x_121_n190) );
CMPR32X2TS DP_OP_134J12_124_859_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n3034),
.C(DP_OP_134J12_124_859_n22), .CO(DP_OP_134J12_124_859_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
DFFRX2TS FPSENCOS_cont_iter_count_reg_2_ ( .D(n1829), .CK(clk), .RN(n5968),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n2329) );
CMPR32X2TS DP_OP_134J12_124_859_U9 ( .A(DP_OP_134J12_124_859_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_134J12_124_859_n9), .CO(
DP_OP_134J12_124_859_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR42X1TS mult_x_159_U188 ( .A(mult_x_159_n291), .B(mult_x_159_n185), .C(
mult_x_159_n179), .D(mult_x_159_n186), .ICI(mult_x_159_n182), .S(
mult_x_159_n177), .ICO(mult_x_159_n175), .CO(mult_x_159_n176) );
CMPR32X2TS DP_OP_134J12_124_859_U7 ( .A(DP_OP_134J12_124_859_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_134J12_124_859_n7), .CO(
DP_OP_134J12_124_859_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_134J12_124_859_U5 ( .A(DP_OP_134J12_124_859_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_134J12_124_859_n5), .CO(
DP_OP_134J12_124_859_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_134J12_124_859_U2 ( .A(n2272), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_134J12_124_859_n2), .CO(DP_OP_134J12_124_859_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
MX2X2TS U2212 ( .A(FPMULT_P_Sgf[47]), .B(n2666), .S0(n5413), .Y(n2058) );
XOR2X1TS U2213 ( .A(n3044), .B(n3043), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17) );
XOR2X2TS U2214 ( .A(n3016), .B(n3015), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21) );
AOI21X2TS U2215 ( .A0(n3756), .A1(n3513), .B0(n2820), .Y(n2823) );
AOI21X1TS U2216 ( .A0(n3532), .A1(n3516), .B0(n3515), .Y(n3521) );
AOI222X1TS U2217 ( .A0(n5675), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n4008), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n4007), .Y(n4009)
);
XNOR2X2TS U2218 ( .A(n5118), .B(n5117), .Y(n5119) );
AOI222X1TS U2219 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[12]), .C0(FPSENCOS_d_ff_Zn[12]), .C1(n4047), .Y(n4035) );
AOI222X1TS U2220 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[11]), .C0(FPSENCOS_d_ff_Zn[11]), .C1(n4047), .Y(n4036) );
AOI222X1TS U2221 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[14]), .C0(FPSENCOS_d_ff_Zn[14]), .C1(n4047), .Y(n4037) );
AOI222X1TS U2222 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[16]), .C0(FPSENCOS_d_ff_Zn[16]), .C1(n4047), .Y(n4026) );
AOI222X1TS U2223 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[17]), .C0(FPSENCOS_d_ff_Zn[17]), .C1(n4047), .Y(n4030) );
AOI222X1TS U2224 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[13]), .C0(FPSENCOS_d_ff_Zn[13]), .C1(n4047), .Y(n4050) );
AOI222X1TS U2225 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[20]), .C0(FPSENCOS_d_ff_Zn[20]), .C1(n4047), .Y(n4041) );
AOI222X1TS U2226 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[15]), .C0(FPSENCOS_d_ff_Zn[15]), .C1(n4047), .Y(n4032) );
AOI222X1TS U2227 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[18]), .C0(FPSENCOS_d_ff_Zn[18]), .C1(n4047), .Y(n4028) );
AOI222X1TS U2228 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[21]), .C0(FPSENCOS_d_ff_Zn[21]), .C1(n5572), .Y(n4029) );
AOI222X1TS U2229 ( .A0(n4049), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4048), .B1(
FPSENCOS_d_ff1_Z[19]), .C0(FPSENCOS_d_ff_Zn[19]), .C1(n4047), .Y(n4034) );
AOI222X1TS U2230 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[7]), .C0(FPSENCOS_d_ff_Zn[7]), .C1(n4043), .Y(n4046)
);
AOI222X1TS U2231 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[6]), .C0(FPSENCOS_d_ff_Zn[6]), .C1(n4043), .Y(n4042)
);
AOI222X1TS U2232 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[3]), .C0(FPSENCOS_d_ff_Zn[3]), .C1(n4043), .Y(n4040)
);
AOI222X1TS U2233 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[9]), .C0(FPSENCOS_d_ff_Zn[9]), .C1(n4043), .Y(n4039)
);
AOI222X1TS U2234 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[8]), .C0(FPSENCOS_d_ff_Zn[8]), .C1(n4043), .Y(n4038)
);
AOI222X1TS U2235 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[4]), .C0(FPSENCOS_d_ff_Zn[4]), .C1(n4043), .Y(n4033)
);
AOI222X1TS U2236 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[5]), .C0(FPSENCOS_d_ff_Zn[5]), .C1(n4043), .Y(n4031)
);
AOI222X1TS U2237 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[2]), .C0(FPSENCOS_d_ff_Zn[2]), .C1(n4043), .Y(n4027)
);
AOI222X1TS U2238 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n4044), .B1(
FPSENCOS_d_ff1_Z[10]), .C0(FPSENCOS_d_ff_Zn[10]), .C1(n4043), .Y(n4023) );
AOI222X1TS U2239 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[27]), .C0(FPSENCOS_d_ff_Zn[27]), .C1(n5572), .Y(n4055) );
AOI222X1TS U2240 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[29]), .C0(FPSENCOS_d_ff_Zn[29]), .C1(n4059), .Y(n4056) );
AOI222X1TS U2241 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[30]), .C0(FPSENCOS_d_ff_Zn[30]), .C1(n4059), .Y(n4052) );
AOI222X1TS U2242 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[22]), .C0(FPSENCOS_d_ff_Zn[22]), .C1(n5572), .Y(n4061) );
AOI222X1TS U2243 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[25]), .C0(FPSENCOS_d_ff_Zn[25]), .C1(n4059), .Y(n4054) );
AOI222X1TS U2244 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[26]), .C0(FPSENCOS_d_ff_Zn[26]), .C1(n5572), .Y(n4053) );
AOI222X1TS U2245 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[28]), .C0(FPSENCOS_d_ff_Zn[28]), .C1(n4059), .Y(n4051) );
AOI222X1TS U2246 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[24]), .C0(FPSENCOS_d_ff_Zn[24]), .C1(n5572), .Y(n4057) );
AOI222X1TS U2247 ( .A0(n4060), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[23]), .C0(FPSENCOS_d_ff_Zn[23]), .C1(n4059), .Y(n4058) );
CLKXOR2X2TS U2248 ( .A(n5053), .B(n5052), .Y(n5054) );
CLKBUFX2TS U2249 ( .A(n5475), .Y(n5477) );
OAI21X2TS U2250 ( .A0(n5129), .A1(n5125), .B0(n5126), .Y(n5118) );
INVX4TS U2251 ( .A(n3097), .Y(n3122) );
INVX2TS U2252 ( .A(n4481), .Y(n4504) );
NAND2X1TS U2253 ( .A(n3047), .B(n2957), .Y(n3750) );
OR2X2TS U2254 ( .A(n5587), .B(n5586), .Y(n5592) );
CMPR32X2TS U2255 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5764), .C(n5663), .CO(n5665), .S(n3926) );
NAND2X1TS U2256 ( .A(FPSENCOS_cont_iter_out[3]), .B(n5536), .Y(n5515) );
INVX2TS U2257 ( .A(n2366), .Y(n2234) );
CLKBUFX2TS U2258 ( .A(n4143), .Y(n4776) );
OAI21X1TS U2259 ( .A0(n3324), .A1(n3326), .B0(n3327), .Y(n2712) );
CMPR32X2TS U2260 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n5536), .C(n3925), .CO(n5663), .S(n3924) );
CMPR32X2TS U2261 ( .A(FPSENCOS_d_ff2_X[25]), .B(n5536), .C(n5535), .CO(n5538), .S(n5537) );
NOR2X2TS U2262 ( .A(DP_OP_498J12_123_5135_n279), .B(
DP_OP_498J12_123_5135_n284), .Y(n2956) );
NAND2X1TS U2263 ( .A(n3351), .B(n2708), .Y(n2710) );
NOR2X1TS U2264 ( .A(n3943), .B(n3929), .Y(n5486) );
NOR2X1TS U2265 ( .A(n4546), .B(n4545), .Y(n4579) );
NAND2X1TS U2266 ( .A(n3105), .B(n3110), .Y(n3099) );
CLKBUFX2TS U2267 ( .A(n5474), .Y(n5481) );
NOR2X1TS U2268 ( .A(n3949), .B(n4656), .Y(n3950) );
NAND2X1TS U2269 ( .A(DP_OP_498J12_123_5135_n258), .B(n3001), .Y(n3788) );
NAND2X1TS U2270 ( .A(n5767), .B(FPSENCOS_cordic_FSM_state_reg[1]), .Y(n3949)
);
NOR2X2TS U2271 ( .A(DP_OP_498J12_123_5135_n327), .B(
DP_OP_498J12_123_5135_n334), .Y(n3713) );
NOR2X1TS U2272 ( .A(n3148), .B(n3248), .Y(n2931) );
NOR2X1TS U2273 ( .A(n3374), .B(n3468), .Y(n2706) );
BUFX3TS U2274 ( .A(n2365), .Y(n5624) );
INVX2TS U2275 ( .A(n5657), .Y(n5658) );
NOR2X1TS U2276 ( .A(operation[1]), .B(n5704), .Y(n4002) );
OAI21X2TS U2277 ( .A0(n3138), .A1(n3143), .B0(n3139), .Y(n3124) );
NAND2X2TS U2278 ( .A(n4856), .B(n5825), .Y(n3021) );
AOI32X1TS U2279 ( .A0(n2888), .A1(n2887), .A2(n2886), .B0(n2885), .B1(n2888),
.Y(n2889) );
NAND2X1TS U2280 ( .A(mult_x_121_n231), .B(mult_x_121_n238), .Y(n3469) );
NAND2X2TS U2281 ( .A(n4512), .B(n4437), .Y(n4615) );
NAND2X1TS U2282 ( .A(FPSENCOS_cont_iter_out[2]), .B(
FPSENCOS_cont_iter_out[3]), .Y(n5503) );
INVX2TS U2283 ( .A(operation[1]), .Y(n4269) );
CMPR42X2TS U2284 ( .A(DP_OP_498J12_123_5135_n408), .B(
DP_OP_498J12_123_5135_n269), .C(DP_OP_498J12_123_5135_n396), .D(
DP_OP_498J12_123_5135_n273), .ICI(DP_OP_498J12_123_5135_n270), .S(
DP_OP_498J12_123_5135_n267), .ICO(DP_OP_498J12_123_5135_n265), .CO(
DP_OP_498J12_123_5135_n266) );
CMPR32X2TS U2285 ( .A(n3746), .B(n3745), .C(n3744), .CO(
DP_OP_498J12_123_5135_n268), .S(DP_OP_498J12_123_5135_n269) );
CMPR32X2TS U2286 ( .A(n2300), .B(n3424), .C(n3423), .CO(mult_x_121_n227),
.S(mult_x_121_n228) );
NAND2X4TS U2287 ( .A(n5101), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(n2660) );
CMPR32X2TS U2288 ( .A(FPMULT_Op_MY[14]), .B(n2343), .C(n3420), .CO(
mult_x_121_n208), .S(mult_x_121_n209) );
OAI21X2TS U2289 ( .A0(n3575), .A1(n3572), .B0(n3573), .Y(n3570) );
ADDHXLTS U2290 ( .A(n3313), .B(n3312), .CO(mult_x_159_n260), .S(
mult_x_159_n261) );
ADDHXLTS U2291 ( .A(n3496), .B(n3495), .CO(mult_x_121_n258), .S(
mult_x_121_n259) );
NOR2X1TS U2292 ( .A(n5394), .B(n5396), .Y(n2576) );
NOR2X1TS U2293 ( .A(n5188), .B(n5190), .Y(n5161) );
BUFX3TS U2294 ( .A(n3498), .Y(n2176) );
NOR2X6TS U2295 ( .A(n5125), .B(n5117), .Y(n2657) );
XNOR2X1TS U2296 ( .A(n3664), .B(n2292), .Y(n3774) );
NOR2X2TS U2297 ( .A(n5149), .B(n5137), .Y(n5116) );
OAI21X1TS U2298 ( .A0(n5222), .A1(n5233), .B0(n5223), .Y(n2589) );
CLKXOR2X4TS U2299 ( .A(n2979), .B(n2978), .Y(n2980) );
BUFX6TS U2300 ( .A(n2971), .Y(n2292) );
NAND2X1TS U2301 ( .A(n2580), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n5297) );
NOR2X1TS U2302 ( .A(n2647), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n5188) );
NOR2X1TS U2303 ( .A(n2581), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n5272) );
NAND2XLTS U2304 ( .A(n4928), .B(n4691), .Y(n4693) );
NOR2X1TS U2305 ( .A(n2571), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(n5366) );
AOI21X1TS U2306 ( .A0(n3624), .A1(n2992), .B0(n2991), .Y(n2993) );
AOI21X1TS U2307 ( .A0(n3624), .A1(n3622), .B0(n3614), .Y(n3619) );
NOR2X4TS U2308 ( .A(n5770), .B(FPADDSUB_FSM_selector_B[1]), .Y(n3812) );
NAND2X1TS U2309 ( .A(n5775), .B(FPADDSUB_FS_Module_state_reg[0]), .Y(n4443)
);
BUFX3TS U2310 ( .A(n3734), .Y(n2120) );
INVX4TS U2311 ( .A(n2137), .Y(n2291) );
NOR2X1TS U2312 ( .A(n5014), .B(n5027), .Y(n5002) );
OAI21X1TS U2313 ( .A0(n4914), .A1(n4911), .B0(n4915), .Y(n4927) );
XNOR2X1TS U2314 ( .A(n2614), .B(n2610), .Y(n2648) );
XNOR2X1TS U2315 ( .A(n2558), .B(n2557), .Y(n2571) );
BUFX3TS U2316 ( .A(n2786), .Y(n3665) );
INVX2TS U2317 ( .A(n2134), .Y(n2285) );
NAND2X1TS U2318 ( .A(n3072), .B(n3071), .Y(n2978) );
BUFX3TS U2319 ( .A(n2786), .Y(n2287) );
BUFX3TS U2320 ( .A(n3463), .Y(n3504) );
NAND2X1TS U2321 ( .A(n4705), .B(n4704), .Y(n4962) );
INVX2TS U2322 ( .A(n2354), .Y(n2121) );
INVX2TS U2323 ( .A(n2338), .Y(n2194) );
XOR2X1TS U2324 ( .A(n4696), .B(n4680), .Y(n4687) );
NOR2X2TS U2325 ( .A(n3599), .B(n3604), .Y(n2963) );
XOR2X1TS U2326 ( .A(n4696), .B(n4694), .Y(n4705) );
XOR2X2TS U2327 ( .A(n2738), .B(n2737), .Y(n2739) );
XOR2X1TS U2328 ( .A(n4752), .B(n4699), .Y(n4715) );
INVX2TS U2329 ( .A(n2336), .Y(n2187) );
NAND2XLTS U2330 ( .A(n3587), .B(n3586), .Y(n3588) );
NAND2X1TS U2331 ( .A(n2732), .B(n2731), .Y(n2733) );
XOR2X1TS U2332 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .Y(n2780) );
INVX2TS U2333 ( .A(n2331), .Y(n2161) );
INVX4TS U2334 ( .A(n2442), .Y(n2561) );
NAND2X1TS U2335 ( .A(n2463), .B(n2363), .Y(n2468) );
NOR2X1TS U2336 ( .A(n2560), .B(n2562), .Y(n2474) );
NAND2X2TS U2337 ( .A(n2415), .B(n2414), .Y(n2559) );
NOR2X2TS U2338 ( .A(n2429), .B(n2428), .Y(n2449) );
OAI21X1TS U2339 ( .A0(FPMULT_Op_MX[14]), .A1(FPMULT_Op_MX[2]), .B0(n2157),
.Y(n2751) );
XNOR2X1TS U2340 ( .A(n3720), .B(n2971), .Y(n3766) );
OR2X1TS U2341 ( .A(n2460), .B(n2459), .Y(n2363) );
CLKINVX3TS U2342 ( .A(n2114), .Y(n2232) );
NAND2X2TS U2343 ( .A(n2986), .B(n2303), .Y(n2994) );
OAI22X1TS U2344 ( .A0(n3498), .A1(FPMULT_Op_MY[15]), .B0(n2201), .B1(n2125),
.Y(n3420) );
NOR2XLTS U2345 ( .A(DP_OP_498J12_123_5135_n727), .B(n2351), .Y(n3267) );
NOR2XLTS U2346 ( .A(n2348), .B(n3501), .Y(n3423) );
OAI21X2TS U2347 ( .A0(n2487), .A1(n2448), .B0(n2447), .Y(n2500) );
OR2X1TS U2348 ( .A(n5711), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]), .Y(n2519) );
NOR2XLTS U2349 ( .A(n5737), .B(n4795), .Y(n4748) );
NOR2XLTS U2350 ( .A(n5813), .B(n4800), .Y(n4741) );
INVX6TS U2351 ( .A(n4848), .Y(n4752) );
INVX2TS U2352 ( .A(n2142), .Y(n2200) );
OAI211XLTS U2353 ( .A0(FPADDSUB_intDX[8]), .A1(n5842), .B0(n2850), .C0(n2853), .Y(n2864) );
BUFX3TS U2354 ( .A(n3710), .Y(n2191) );
CMPR42X1TS U2355 ( .A(DP_OP_498J12_123_5135_n467), .B(
DP_OP_498J12_123_5135_n415), .C(DP_OP_498J12_123_5135_n428), .D(
DP_OP_498J12_123_5135_n324), .ICI(DP_OP_498J12_123_5135_n328), .S(
DP_OP_498J12_123_5135_n322), .ICO(DP_OP_498J12_123_5135_n320), .CO(
DP_OP_498J12_123_5135_n321) );
INVX2TS U2356 ( .A(n3477), .Y(n2273) );
CLKXOR2X2TS U2357 ( .A(n2517), .B(n2516), .Y(n2522) );
AOI21X2TS U2358 ( .A0(n2992), .A1(n3624), .B0(n2968), .Y(n3061) );
CMPR42X1TS U2359 ( .A(n2125), .B(n2170), .C(mult_x_121_n284), .D(
mult_x_121_n308), .ICI(mult_x_121_n296), .S(mult_x_121_n185), .ICO(
mult_x_121_n183), .CO(mult_x_121_n184) );
CMPR42X1TS U2360 ( .A(mult_x_121_n315), .B(mult_x_121_n303), .C(
mult_x_121_n246), .D(mult_x_121_n243), .ICI(mult_x_121_n242), .S(
mult_x_121_n239), .ICO(mult_x_121_n237), .CO(mult_x_121_n238) );
NAND2X1TS U2361 ( .A(n2649), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n5177) );
NOR2X1TS U2362 ( .A(n4515), .B(n4514), .Y(n4516) );
OR2X1TS U2363 ( .A(n4409), .B(n4406), .Y(n2133) );
AOI21X1TS U2364 ( .A0(n4677), .A1(n4879), .B0(n4676), .Y(n4895) );
OAI21X1TS U2365 ( .A0(n4580), .A1(n4579), .B0(n4578), .Y(n4583) );
NOR2XLTS U2366 ( .A(n4346), .B(FPADDSUB_Add_Subt_result[0]), .Y(n4347) );
NAND2X1TS U2367 ( .A(FPADDSUB_FS_Module_state_reg[1]), .B(n5721), .Y(n4468)
);
OAI21XLTS U2368 ( .A0(n5312), .A1(n5308), .B0(n5309), .Y(n5300) );
OAI21XLTS U2369 ( .A0(n5395), .A1(n5394), .B0(n5393), .Y(n5400) );
CLKBUFX2TS U2370 ( .A(n3883), .Y(n4840) );
XNOR2X1TS U2371 ( .A(n4583), .B(n4582), .Y(n5339) );
OR2X2TS U2372 ( .A(DP_OP_498J12_123_5135_n271), .B(
DP_OP_498J12_123_5135_n267), .Y(n2957) );
AOI31XLTS U2373 ( .A0(n3027), .A1(FPADDSUB_Add_Subt_result[16]), .A2(n5827),
.B0(n3026), .Y(n3032) );
NAND2X1TS U2374 ( .A(n4194), .B(n5808), .Y(n3914) );
AOI21X1TS U2375 ( .A0(n3146), .A1(n3125), .B0(n3124), .Y(n3135) );
OAI21XLTS U2376 ( .A0(n3188), .A1(n3184), .B0(n3185), .Y(n3183) );
AOI21X1TS U2377 ( .A0(n3532), .A1(n3530), .B0(n3523), .Y(n3528) );
CLKINVX3TS U2378 ( .A(n2322), .Y(n2303) );
AOI211XLTS U2379 ( .A0(n2264), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]), .B0(n4833),
.C0(n3880), .Y(n3881) );
CLKINVX3TS U2380 ( .A(n4003), .Y(n5704) );
CLKINVX3TS U2381 ( .A(n4615), .Y(n4483) );
OAI211XLTS U2382 ( .A0(n4830), .A1(n5857), .B0(n4822), .C0(n4821), .Y(n4823)
);
OAI211XLTS U2383 ( .A0(n4409), .A1(n4459), .B0(n3833), .C0(n3832), .Y(n3834)
);
OAI211XLTS U2384 ( .A0(n4830), .A1(n5858), .B0(n4825), .C0(n4824), .Y(n4826)
);
OAI211XLTS U2385 ( .A0(n4830), .A1(n5855), .B0(n4816), .C0(n4815), .Y(n4817)
);
CLKINVX3TS U2386 ( .A(n4491), .Y(n4612) );
OAI21X2TS U2387 ( .A0(n3096), .A1(n3092), .B0(n3093), .Y(n3091) );
OR4X2TS U2388 ( .A(n5767), .B(n5717), .C(FPSENCOS_cordic_FSM_state_reg[1]),
.D(FPSENCOS_cordic_FSM_state_reg[3]), .Y(n2365) );
OAI31X1TS U2389 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(
FPMULT_FS_Module_state_reg[0]), .A2(n2116), .B0(n3917), .Y(n2055) );
OAI21XLTS U2390 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n5294), .B0(
n3935), .Y(n1984) );
OAI21XLTS U2391 ( .A0(n5677), .A1(n3953), .B0(n3954), .Y(n1345) );
OAI21XLTS U2392 ( .A0(n5801), .A1(n4612), .B0(n4603), .Y(n1230) );
OAI21XLTS U2393 ( .A0(n5777), .A1(n4638), .B0(n4628), .Y(n1282) );
OAI211XLTS U2394 ( .A0(n3957), .A1(n3956), .B0(n3955), .C0(n5490), .Y(
FPSENCOS_cordic_FSM_state_next_1_) );
OAI211XLTS U2395 ( .A0(n4230), .A1(n5738), .B0(n4083), .C0(n4082), .Y(n1308)
);
OAI21XLTS U2396 ( .A0(n4600), .A1(n5844), .B0(n4594), .Y(n1220) );
OAI211XLTS U2397 ( .A0(n4217), .A1(n4389), .B0(n4388), .C0(n4387), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
OAI211XLTS U2398 ( .A0(n4467), .A1(n5857), .B0(n4426), .C0(n4425), .Y(n1633)
);
OAI211XLTS U2399 ( .A0(n4159), .A1(n5559), .B0(n4077), .C0(n4076), .Y(n1233)
);
OAI211XLTS U2400 ( .A0(n5758), .A1(n4230), .B0(n4201), .C0(n4200), .Y(n1317)
);
AOI31XLTS U2401 ( .A0(n4330), .A1(n4474), .A2(n4329), .B0(n4440), .Y(n1837)
);
OAI211XLTS U2402 ( .A0(n4230), .A1(n5575), .B0(n4229), .C0(n4228), .Y(n1302)
);
OAI211XLTS U2403 ( .A0(n4405), .A1(n5443), .B0(n4404), .C0(n4403), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI211XLTS U2404 ( .A0(n4159), .A1(n5904), .B0(n4138), .C0(n4137), .Y(n1242)
);
OAI211XLTS U2405 ( .A0(n5716), .A1(n4230), .B0(n4095), .C0(n4094), .Y(n1320)
);
OAI211XLTS U2406 ( .A0(n4184), .A1(n5548), .B0(n4112), .C0(n4111), .Y(n1268)
);
OAI211XLTS U2407 ( .A0(n4237), .A1(n5554), .B0(n4161), .C0(n4160), .Y(n1250)
);
OAI211XLTS U2408 ( .A0(n2339), .A1(n4143), .B0(n4142), .C0(n4141), .Y(n1296)
);
OAI21XLTS U2409 ( .A0(n5801), .A1(n2236), .B0(n4500), .Y(n1231) );
OAI21XLTS U2410 ( .A0(n5799), .A1(n4642), .B0(n4626), .Y(n1241) );
XOR2X2TS U2411 ( .A(n3010), .B(n3009), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24) );
OAI21XLTS U2412 ( .A0(n5649), .A1(n4000), .B0(n3988), .Y(n1363) );
OAI21XLTS U2413 ( .A0(n5621), .A1(n3996), .B0(n3972), .Y(n1405) );
OAI21XLTS U2414 ( .A0(n5646), .A1(n4000), .B0(n3970), .Y(n1367) );
OAI21XLTS U2415 ( .A0(n5645), .A1(n3991), .B0(n3966), .Y(n1369) );
OAI21XLTS U2416 ( .A0(n4300), .A1(n5615), .B0(n4296), .Y(op_result[2]) );
OAI21XLTS U2417 ( .A0(n4300), .A1(n5745), .B0(n4310), .Y(op_result[17]) );
CLKXOR2X2TS U2418 ( .A(FPMULT_Op_MY[8]), .B(n2230), .Y(n2114) );
CLKXOR2X2TS U2419 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[20]), .Y(n3425) );
AND2X2TS U2420 ( .A(n3081), .B(n3080), .Y(n2115) );
INVX2TS U2421 ( .A(n5657), .Y(n2239) );
BUFX3TS U2422 ( .A(n3918), .Y(n5657) );
CLKMX2X2TS U2423 ( .A(FPMULT_P_Sgf[45]), .B(n5054), .S0(n5142), .Y(n1938) );
XOR2X1TS U2424 ( .A(n3521), .B(n3520), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16) );
XOR2X1TS U2425 ( .A(n3791), .B(n3790), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23) );
XOR2X1TS U2426 ( .A(n3528), .B(n3527), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15) );
NOR2X4TS U2427 ( .A(n5111), .B(n2659), .Y(n5102) );
NAND2X4TS U2428 ( .A(n5116), .B(n2657), .Y(n2659) );
INVX6TS U2429 ( .A(n5100), .Y(n5204) );
AO21X1TS U2430 ( .A0(n5342), .A1(underflow_flag_addsubt), .B0(n5341), .Y(
n1842) );
NOR4X2TS U2431 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n5328), .D(n5470), .Y(n5329) );
XNOR2X1TS U2432 ( .A(DP_OP_134J12_124_859_n1), .B(n5325), .Y(n5326) );
XOR2X1TS U2433 ( .A(n3158), .B(n3157), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10) );
INVX2TS U2434 ( .A(n3017), .Y(n3011) );
XOR2X1TS U2435 ( .A(n3568), .B(n3567), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5) );
XOR2X1TS U2436 ( .A(n3397), .B(n3396), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7) );
AO21XLTS U2437 ( .A0(n4421), .A1(n3817), .B0(n3823), .Y(n1845) );
INVX2TS U2438 ( .A(n5274), .Y(n5276) );
OAI21X1TS U2439 ( .A0(n5730), .A1(n2366), .B0(n4502), .Y(n1301) );
NAND4X1TS U2440 ( .A(n4844), .B(n4843), .C(n4842), .D(n4841), .Y(n1645) );
INVX2TS U2441 ( .A(n2318), .Y(n2355) );
INVX2TS U2442 ( .A(n3558), .Y(n3553) );
OAI21X1TS U2443 ( .A0(n5736), .A1(n2366), .B0(n4498), .Y(n1325) );
OAI21X1TS U2444 ( .A0(n5777), .A1(n2366), .B0(n4495), .Y(n1217) );
OAI21X1TS U2445 ( .A0(n5796), .A1(n2366), .B0(n4493), .Y(n1254) );
OAI21X1TS U2446 ( .A0(n5713), .A1(n2366), .B0(n4496), .Y(n1218) );
OAI21X1TS U2447 ( .A0(n5800), .A1(n2366), .B0(n4494), .Y(n1225) );
XOR2X1TS U2448 ( .A(n3172), .B(n3171), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7) );
NAND4X1TS U2449 ( .A(n4844), .B(n4837), .C(n4836), .D(n4835), .Y(n1646) );
INVX4TS U2450 ( .A(n2235), .Y(n4639) );
OR2X2TS U2451 ( .A(n3008), .B(n3007), .Y(n3050) );
XOR2X1TS U2452 ( .A(n3402), .B(n3401), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6) );
INVX4TS U2453 ( .A(n2235), .Y(n4598) );
XOR2X1TS U2454 ( .A(n3177), .B(n3176), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6) );
INVX4TS U2455 ( .A(n4504), .Y(n4642) );
INVX4TS U2456 ( .A(n4504), .Y(n4638) );
AO22X1TS U2457 ( .A0(n5674), .A1(n5673), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1411) );
OR2X2TS U2458 ( .A(mult_x_159_n176), .B(mult_x_159_n172), .Y(n3110) );
AO22X1TS U2459 ( .A0(n5630), .A1(n5547), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1782) );
INVX4TS U2460 ( .A(n4481), .Y(n4491) );
OAI211X1TS U2461 ( .A0(n5889), .A1(n4143), .B0(n4015), .C0(n4014), .Y(n1332)
);
OR2X2TS U2462 ( .A(mult_x_121_n174), .B(mult_x_121_n170), .Y(n3336) );
OAI211X1TS U2463 ( .A0(n2113), .A1(n4776), .B0(n4169), .C0(n4168), .Y(n1283)
);
OAI211X1TS U2464 ( .A0(n4776), .A1(n5502), .B0(n4019), .C0(n4018), .Y(n1331)
);
INVX4TS U2465 ( .A(n4776), .Y(n5698) );
INVX4TS U2466 ( .A(n4776), .Y(n4199) );
AO22X1TS U2467 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n5476), .B0(
mult_result[5]), .B1(n5478), .Y(n1863) );
AO22X1TS U2468 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n5476), .B0(
mult_result[4]), .B1(n5478), .Y(n1864) );
AO22X1TS U2469 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n5476), .B0(
mult_result[3]), .B1(n5478), .Y(n1865) );
AO22X1TS U2470 ( .A0(n5483), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n5478), .Y(n1866) );
AO22X1TS U2471 ( .A0(n5483), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n5478), .Y(n1867) );
OAI21X1TS U2472 ( .A0(n5666), .A1(n5853), .B0(n5669), .Y(n5668) );
AO22X1TS U2473 ( .A0(n5483), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n5478), .Y(n1868) );
AO22X1TS U2474 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n5479), .B0(
mult_result[15]), .B1(n5480), .Y(n1853) );
AO22X1TS U2475 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n5479), .B0(
mult_result[14]), .B1(n5480), .Y(n1854) );
AO22X1TS U2476 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n5483), .B0(
mult_result[16]), .B1(n5480), .Y(n1852) );
AO22X1TS U2477 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n5479), .B0(
mult_result[13]), .B1(n5480), .Y(n1855) );
AO22X1TS U2478 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n5483), .B0(
mult_result[17]), .B1(n5482), .Y(n1851) );
AO22X1TS U2479 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n5479), .B0(
mult_result[12]), .B1(n5480), .Y(n1856) );
AO22X1TS U2480 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n5483), .B0(
mult_result[19]), .B1(n5482), .Y(n1849) );
AO22X1TS U2481 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n5483), .B0(
mult_result[20]), .B1(n5482), .Y(n1848) );
AO22X1TS U2482 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n5483), .B0(
mult_result[21]), .B1(n5482), .Y(n1847) );
AO22X1TS U2483 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n5483), .B0(
mult_result[22]), .B1(n5482), .Y(n1846) );
AO22X1TS U2484 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n5479), .B0(
mult_result[11]), .B1(n5480), .Y(n1857) );
AO22X1TS U2485 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n5479), .B0(
mult_result[10]), .B1(n5480), .Y(n1858) );
AO22X1TS U2486 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n5479), .B0(
mult_result[9]), .B1(n5480), .Y(n1859) );
AO22X1TS U2487 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n5479), .B0(
mult_result[8]), .B1(n5480), .Y(n1860) );
AO22X1TS U2488 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n5479), .B0(
mult_result[7]), .B1(n5480), .Y(n1861) );
AO22X1TS U2489 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n5483), .B0(
mult_result[18]), .B1(n5482), .Y(n1850) );
AO22X1TS U2490 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n5479), .B0(
mult_result[6]), .B1(n5478), .Y(n1862) );
OR2X2TS U2491 ( .A(mult_x_121_n239), .B(mult_x_121_n244), .Y(n2347) );
INVX4TS U2492 ( .A(n4143), .Y(n4227) );
INVX4TS U2493 ( .A(n5659), .Y(n5567) );
OR2X2TS U2494 ( .A(mult_x_121_n245), .B(mult_x_121_n251), .Y(n2346) );
AOI221X1TS U2495 ( .A0(FPSENCOS_cont_var_out[1]), .A1(n4073), .B0(n5728),
.B1(n4072), .C0(n5529), .Y(n1833) );
INVX2TS U2496 ( .A(n4979), .Y(n4980) );
INVX4TS U2497 ( .A(n4143), .Y(n4234) );
NAND4BXLTS U2498 ( .AN(FPADDSUB_Add_Subt_result[9]), .B(n3029), .C(
FPADDSUB_Add_Subt_result[8]), .D(n4874), .Y(n3030) );
INVX2TS U2499 ( .A(n3690), .Y(n3743) );
OAI211XLTS U2500 ( .A0(n5529), .A1(n2113), .B0(n4066), .C0(n5513), .Y(n1820)
);
INVX4TS U2501 ( .A(n2115), .Y(n2117) );
AOI2BB1X1TS U2502 ( .A0N(n5630), .A1N(FPSENCOS_d_ff3_LUT_out[10]), .B0(n5534), .Y(n1809) );
INVX4TS U2503 ( .A(n2179), .Y(n2180) );
AOI211X1TS U2504 ( .A0(FPADDSUB_FS_Module_state_reg[1]), .A1(n4440), .B0(
n4439), .C0(n4438), .Y(n4441) );
NAND3BX1TS U2505 ( .AN(n3085), .B(n3086), .C(FPADDSUB_Add_Subt_result[14]),
.Y(n4871) );
INVX4TS U2506 ( .A(n2315), .Y(n2118) );
NAND4X1TS U2507 ( .A(n5507), .B(n5515), .C(n5520), .D(n5533), .Y(n5512) );
INVX4TS U2508 ( .A(n3302), .Y(n2282) );
OAI21X1TS U2509 ( .A0(n5888), .A1(n3953), .B0(n3952), .Y(n1347) );
INVX4TS U2510 ( .A(n4346), .Y(n4367) );
INVX4TS U2511 ( .A(n4483), .Y(n4630) );
AND2X4TS U2512 ( .A(n3212), .B(n2232), .Y(n3302) );
NAND3X1TS U2513 ( .A(n3942), .B(FPSENCOS_sel_mux_3_reg), .C(n5988), .Y(n3941) );
NAND2X4TS U2514 ( .A(n2891), .B(n2221), .Y(n3282) );
INVX2TS U2515 ( .A(n3597), .Y(n3600) );
INVX2TS U2516 ( .A(n2480), .Y(n2482) );
INVX2TS U2517 ( .A(n2508), .Y(n2510) );
INVX4TS U2518 ( .A(n5511), .Y(n5671) );
INVX1TS U2519 ( .A(n4864), .Y(n4865) );
NOR2X2TS U2520 ( .A(n3901), .B(FPMULT_FS_Module_state_reg[1]), .Y(n3034) );
INVX2TS U2521 ( .A(n3901), .Y(n3902) );
INVX4TS U2522 ( .A(n5098), .Y(n5315) );
INVX3TS U2523 ( .A(n2135), .Y(n2221) );
OR2X2TS U2524 ( .A(n2625), .B(n2624), .Y(n2629) );
OR2X2TS U2525 ( .A(n2640), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]), .Y(n2644) );
NOR2X1TS U2526 ( .A(n5317), .B(FPMULT_P_Sgf[47]), .Y(n5319) );
INVX4TS U2527 ( .A(n4332), .Y(n4324) );
NAND2BX1TS U2528 ( .AN(n4222), .B(n5034), .Y(n5317) );
NOR2X1TS U2529 ( .A(n2869), .B(FPADDSUB_intDY[16]), .Y(n2870) );
NOR2X1TS U2530 ( .A(n2848), .B(FPADDSUB_intDY[10]), .Y(n2849) );
NAND2X2TS U2531 ( .A(n2664), .B(FPMULT_FS_Module_state_reg[2]), .Y(n3901) );
NOR2X1TS U2532 ( .A(n5726), .B(n4795), .Y(n4737) );
OAI21X1TS U2533 ( .A0(n4443), .A1(n4511), .B0(n3898), .Y(n3819) );
NOR2X1TS U2534 ( .A(n5772), .B(n4795), .Y(n4703) );
OAI21X1TS U2535 ( .A0(FPADDSUB_intDX[15]), .A1(n5718), .B0(
FPADDSUB_intDX[14]), .Y(n2856) );
NAND2X2TS U2536 ( .A(n4269), .B(n5449), .Y(n4272) );
NAND2X6TS U2537 ( .A(n3809), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[20]), .Y(n5053) );
XOR2X2TS U2538 ( .A(n2823), .B(n2822), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19) );
MX2X2TS U2539 ( .A(FPADDSUB_add_overflow_flag), .B(n4850), .S0(n4909), .Y(
n1844) );
MX2X2TS U2540 ( .A(FPADDSUB_Add_Subt_result[25]), .B(n4806), .S0(n4909), .Y(
n1659) );
NAND2X2TS U2541 ( .A(n5102), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(n2661) );
XOR2X2TS U2542 ( .A(n3067), .B(n3066), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25) );
XOR2X2TS U2543 ( .A(n4849), .B(n4848), .Y(n4850) );
OAI21X1TS U2544 ( .A0(n5136), .A1(n5149), .B0(n5150), .Y(n5141) );
OAI21X1TS U2545 ( .A0(n3135), .A1(n3131), .B0(n3132), .Y(n3130) );
OAI21X1TS U2546 ( .A0(n3717), .A1(n3713), .B0(n3714), .Y(n3538) );
XOR2X1TS U2547 ( .A(n3717), .B(n3716), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12) );
XOR2X1TS U2548 ( .A(n3135), .B(n3134), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15) );
XOR2X1TS U2549 ( .A(n3544), .B(n3543), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11) );
XOR2X1TS U2550 ( .A(n3142), .B(n3141), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14) );
XOR2X1TS U2551 ( .A(n3096), .B(n3095), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21) );
AO22X1TS U2552 ( .A0(n4877), .A1(n4876), .B0(n4875), .B1(
FPADDSUB_LZA_output[1]), .Y(n1657) );
XOR2X1TS U2553 ( .A(n3368), .B(n3367), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14) );
XOR2X1TS U2554 ( .A(n3348), .B(n3347), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17) );
XOR2X1TS U2555 ( .A(n3322), .B(n3321), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21) );
XOR2X1TS U2556 ( .A(n3361), .B(n3360), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15) );
INVX3TS U2557 ( .A(n3046), .Y(n3000) );
OAI21X1TS U2558 ( .A0(n4586), .A1(n2306), .B0(n4585), .Y(n1686) );
OAI21X1TS U2559 ( .A0(n3252), .A1(n3248), .B0(n3249), .Y(n3152) );
XOR2X1TS U2560 ( .A(n3252), .B(n3251), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11) );
XOR2X1TS U2561 ( .A(n3557), .B(n3556), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8) );
OAI21X1TS U2562 ( .A0(FPADDSUB_Add_Subt_result[1]), .A1(
FPADDSUB_Add_Subt_result[0]), .B0(n4651), .Y(n4653) );
XOR2X1TS U2563 ( .A(n3383), .B(n3382), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10) );
OAI21X1TS U2564 ( .A0(n3472), .A1(n3468), .B0(n3469), .Y(n3378) );
XOR2X1TS U2565 ( .A(n3472), .B(n3471), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11) );
AOI211X1TS U2566 ( .A0(FPADDSUB_Add_Subt_result[1]), .A1(n4651), .B0(n4854),
.C0(n3083), .Y(n3084) );
NAND2X1TS U2567 ( .A(n3759), .B(n3758), .Y(n3760) );
OAI21X1TS U2568 ( .A0(n5735), .A1(n4642), .B0(n4621), .Y(n1237) );
OAI21X1TS U2569 ( .A0(n5803), .A1(n4612), .B0(n4601), .Y(n1304) );
INVX3TS U2570 ( .A(n4855), .Y(n4644) );
OAI21X1TS U2571 ( .A0(n5815), .A1(n4642), .B0(n2890), .Y(n1248) );
OAI21X1TS U2572 ( .A0(n4600), .A1(n5836), .B0(n4589), .Y(n1214) );
OAI21X1TS U2573 ( .A0(n5715), .A1(n4642), .B0(n4624), .Y(n1251) );
NOR2X4TS U2574 ( .A(DP_OP_498J12_123_5135_n266), .B(
DP_OP_498J12_123_5135_n262), .Y(n3752) );
OAI21X1TS U2575 ( .A0(n4600), .A1(n5843), .B0(n4599), .Y(n1215) );
OAI21X1TS U2576 ( .A0(n3126), .A1(n3132), .B0(n3127), .Y(n2932) );
OAI21X1TS U2577 ( .A0(n5792), .A1(n4612), .B0(n4609), .Y(n1318) );
OAI21X1TS U2578 ( .A0(n5714), .A1(n4638), .B0(n4627), .Y(n1295) );
OAI21X1TS U2579 ( .A0(n5797), .A1(n4612), .B0(n4608), .Y(n1306) );
OAI21X1TS U2580 ( .A0(n5798), .A1(n4638), .B0(n4629), .Y(n1289) );
OAI21X1TS U2581 ( .A0(n5811), .A1(n4638), .B0(n4623), .Y(n1285) );
OAI21X1TS U2582 ( .A0(n5713), .A1(n4638), .B0(n4637), .Y(n1275) );
OAI21X1TS U2583 ( .A0(n5732), .A1(n4642), .B0(n4622), .Y(n1272) );
OAI21X1TS U2584 ( .A0(n5794), .A1(n4638), .B0(n4632), .Y(n1279) );
OAI21X1TS U2585 ( .A0(n5810), .A1(n4481), .B0(n4613), .Y(n1269) );
OAI21X1TS U2586 ( .A0(n5734), .A1(n4642), .B0(n4618), .Y(n1258) );
OAI21X1TS U2587 ( .A0(n5809), .A1(n4642), .B0(n4631), .Y(n1244) );
OAI21X1TS U2588 ( .A0(n5791), .A1(n4612), .B0(n4604), .Y(n1309) );
OAI21X1TS U2589 ( .A0(n5805), .A1(n4612), .B0(n4605), .Y(n1312) );
OAI21X1TS U2590 ( .A0(n5729), .A1(n4612), .B0(n4611), .Y(n1315) );
OAI21X1TS U2591 ( .A0(n5814), .A1(n4612), .B0(n4606), .Y(n1321) );
OAI21X1TS U2592 ( .A0(n5736), .A1(n4638), .B0(n4617), .Y(n1324) );
OAI21X1TS U2593 ( .A0(n5796), .A1(n4642), .B0(n4633), .Y(n1255) );
OAI21X1TS U2594 ( .A0(n4612), .A1(n5730), .B0(n4596), .Y(n1212) );
OAI21X1TS U2595 ( .A0(n5778), .A1(n4642), .B0(n4625), .Y(n1262) );
OAI21X1TS U2596 ( .A0(n5786), .A1(n4638), .B0(n4620), .Y(n1292) );
OAI21X1TS U2597 ( .A0(n5793), .A1(n4638), .B0(n4636), .Y(n1298) );
OAI21X1TS U2598 ( .A0(n5795), .A1(n4642), .B0(n4641), .Y(n1266) );
OAI21X1TS U2599 ( .A0(n4600), .A1(n5842), .B0(n4595), .Y(n1219) );
OAI21X2TS U2600 ( .A0(n5246), .A1(n5257), .B0(n5247), .Y(n5217) );
OAI21X1TS U2601 ( .A0(n3397), .A1(n3393), .B0(n3394), .Y(n3392) );
OAI21X1TS U2602 ( .A0(n5816), .A1(n4612), .B0(n4602), .Y(n1303) );
NOR2X4TS U2603 ( .A(DP_OP_498J12_123_5135_n310), .B(
DP_OP_498J12_123_5135_n318), .Y(n3522) );
OAI21X1TS U2604 ( .A0(n5729), .A1(n2236), .B0(n4499), .Y(n1316) );
OAI21X1TS U2605 ( .A0(n3172), .A1(n3168), .B0(n3169), .Y(n3167) );
OAI211X1TS U2606 ( .A0(n4467), .A1(n5858), .B0(n4466), .C0(n4465), .Y(n1632)
);
OAI211X1TS U2607 ( .A0(n5855), .A1(n4467), .B0(n4411), .C0(n4410), .Y(n1635)
);
OAI211X1TS U2608 ( .A0(n4467), .A1(n5859), .B0(n4429), .C0(n4428), .Y(n1631)
);
OAI211X1TS U2609 ( .A0(n5856), .A1(n4467), .B0(n4417), .C0(n4416), .Y(n1636)
);
OAI21X1TS U2610 ( .A0(n5733), .A1(n4638), .B0(n4619), .Y(n1227) );
OAI21X1TS U2611 ( .A0(n5815), .A1(n2235), .B0(n4497), .Y(n1247) );
OAI21X1TS U2612 ( .A0(n5799), .A1(n2236), .B0(n4492), .Y(n1240) );
OAI211X1TS U2613 ( .A0(n4830), .A1(n5856), .B0(n4813), .C0(n4812), .Y(n4814)
);
OAI211X1TS U2614 ( .A0(n4810), .A1(n5865), .B0(n3827), .C0(n3826), .Y(n3828)
);
OAI211X1TS U2615 ( .A0(n4467), .A1(n5860), .B0(n4414), .C0(n4413), .Y(n1634)
);
OR2X2TS U2616 ( .A(DP_OP_498J12_123_5135_n349), .B(
DP_OP_498J12_123_5135_n355), .Y(n2808) );
NAND2X2TS U2617 ( .A(DP_OP_498J12_123_5135_n349), .B(
DP_OP_498J12_123_5135_n355), .Y(n3549) );
OAI211X1TS U2618 ( .A0(n4830), .A1(n5859), .B0(n4829), .C0(n4828), .Y(n4831)
);
OAI21X1TS U2619 ( .A0(n5376), .A1(n5375), .B0(n5374), .Y(n5381) );
OAI211X1TS U2620 ( .A0(n4830), .A1(n5860), .B0(n4819), .C0(n4818), .Y(n4820)
);
NOR2X2TS U2621 ( .A(n5272), .B(n5274), .Y(n2584) );
NAND2X2TS U2622 ( .A(n2585), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n5257) );
OAI211X1TS U2623 ( .A0(n4401), .A1(n4212), .B0(n4374), .C0(n4373), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND3X1TS U2624 ( .A(n5702), .B(n5701), .C(n5707), .Y(n1336) );
OAI211X1TS U2625 ( .A0(n4237), .A1(n5900), .B0(n4118), .C0(n4117), .Y(n1256)
);
OAI211X1TS U2626 ( .A0(n4174), .A1(n4149), .B0(n4148), .C0(n4147), .Y(n1284)
);
OAI21X1TS U2627 ( .A0(n5793), .A1(n2236), .B0(n4509), .Y(n1213) );
OAI211X1TS U2628 ( .A0(n4184), .A1(n5563), .B0(n4183), .C0(n4182), .Y(n1274)
);
OAI211X1TS U2629 ( .A0(n4159), .A1(n5562), .B0(n4081), .C0(n4080), .Y(n1229)
);
OAI211X1TS U2630 ( .A0(n4159), .A1(n5905), .B0(n4089), .C0(n4088), .Y(n1238)
);
OAI211X1TS U2631 ( .A0(n4401), .A1(n4336), .B0(n4221), .C0(n4220), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
OAI211X1TS U2632 ( .A0(n4159), .A1(n5560), .B0(n4079), .C0(n4078), .Y(n1236)
);
AOI211X1TS U2633 ( .A0(n2263), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]), .B0(n4833),
.C0(n3884), .Y(n3885) );
OAI211X1TS U2634 ( .A0(n4184), .A1(n5894), .B0(n4132), .C0(n4131), .Y(n1280)
);
NAND2X1TS U2635 ( .A(n2264), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n3833) );
OAI21X1TS U2636 ( .A0(n5792), .A1(n2236), .B0(n4486), .Y(n1319) );
NAND3X1TS U2637 ( .A(n5709), .B(n5708), .C(n5707), .Y(n1335) );
OAI211X1TS U2638 ( .A0(n4184), .A1(n5895), .B0(n4124), .C0(n4123), .Y(n1276)
);
OAI211X1TS U2639 ( .A0(n4174), .A1(n5551), .B0(n4108), .C0(n4107), .Y(n1281)
);
OAI211X1TS U2640 ( .A0(n4159), .A1(n5908), .B0(n4116), .C0(n4115), .Y(n1228)
);
NOR2BX2TS U2641 ( .AN(n2319), .B(DP_OP_498J12_123_5135_n361), .Y(n2318) );
OAI211X1TS U2642 ( .A0(n4159), .A1(n5907), .B0(n4085), .C0(n4084), .Y(n1232)
);
OAI211X1TS U2643 ( .A0(n4159), .A1(n5906), .B0(n4087), .C0(n4086), .Y(n1235)
);
OAI211X1TS U2644 ( .A0(n4174), .A1(n5892), .B0(n4120), .C0(n4119), .Y(n1290)
);
OAI211X1TS U2645 ( .A0(n4389), .A1(n4353), .B0(n4338), .C0(n4337), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
OAI211X1TS U2646 ( .A0(n4237), .A1(n5899), .B0(n4146), .C0(n4145), .Y(n1259)
);
OAI211X1TS U2647 ( .A0(n4174), .A1(n5893), .B0(n4122), .C0(n4121), .Y(n1286)
);
NAND2X2TS U2648 ( .A(DP_OP_498J12_123_5135_n356), .B(
DP_OP_498J12_123_5135_n360), .Y(n3554) );
NAND2BX2TS U2649 ( .AN(n2319), .B(DP_OP_498J12_123_5135_n361), .Y(n3558) );
OAI211X1TS U2650 ( .A0(n5546), .A1(n4230), .B0(n4186), .C0(n4185), .Y(n1326)
);
OAI211X1TS U2651 ( .A0(n5761), .A1(n4230), .B0(n4188), .C0(n4187), .Y(n1323)
);
OAI21X1TS U2652 ( .A0(n5795), .A1(n2235), .B0(n4485), .Y(n1265) );
OAI211X1TS U2653 ( .A0(n4217), .A1(n4383), .B0(n4382), .C0(n4381), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
OAI211X1TS U2654 ( .A0(n4237), .A1(n5561), .B0(n4114), .C0(n4113), .Y(n1246)
);
OAI211X1TS U2655 ( .A0(n4383), .A1(n4353), .B0(n4342), .C0(n4341), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
OAI21X1TS U2656 ( .A0(n5797), .A1(n2235), .B0(n4490), .Y(n1307) );
OAI211X1TS U2657 ( .A0(n4389), .A1(n4212), .B0(n4360), .C0(n4359), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
OAI211X1TS U2658 ( .A0(n4467), .A1(n5760), .B0(n4420), .C0(n4419), .Y(n1630)
);
OAI211X1TS U2659 ( .A0(n4389), .A1(n4336), .B0(n4258), .C0(n4257), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
OAI21X1TS U2660 ( .A0(n5778), .A1(n2236), .B0(n4482), .Y(n1261) );
OAI211X1TS U2661 ( .A0(n4383), .A1(n4336), .B0(n4268), .C0(n4267), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
OAI211X1TS U2662 ( .A0(n4395), .A1(n4353), .B0(n4340), .C0(n4339), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
OAI211X1TS U2663 ( .A0(n4217), .A1(n4401), .B0(n4400), .C0(n4399), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
OAI211X1TS U2664 ( .A0(n4377), .A1(n4212), .B0(n4362), .C0(n4361), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
NAND3X1TS U2665 ( .A(n5700), .B(n5699), .C(n5707), .Y(n1337) );
OAI211X1TS U2666 ( .A0(n4401), .A1(n4353), .B0(n4344), .C0(n4343), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
OAI21X1TS U2667 ( .A0(n4506), .A1(n4630), .B0(n2236), .Y(n4503) );
OAI211X1TS U2668 ( .A0(n4237), .A1(n5901), .B0(n4128), .C0(n4127), .Y(n1252)
);
OAI211X1TS U2669 ( .A0(n4395), .A1(n4212), .B0(n4358), .C0(n4357), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
OAI211X1TS U2670 ( .A0(n4395), .A1(n4336), .B0(n4247), .C0(n4246), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
OAI211X1TS U2671 ( .A0(n4217), .A1(n4395), .B0(n4394), .C0(n4393), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
OAI211X1TS U2672 ( .A0(n4383), .A1(n4212), .B0(n4364), .C0(n4363), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
OAI21X1TS U2673 ( .A0(n5805), .A1(n2236), .B0(n4488), .Y(n1313) );
OAI211X1TS U2674 ( .A0(n4184), .A1(n5897), .B0(n4130), .C0(n4129), .Y(n1267)
);
OAI21X1TS U2675 ( .A0(n5798), .A1(n2236), .B0(n4484), .Y(n1288) );
OAI21X1TS U2676 ( .A0(n5794), .A1(n2235), .B0(n4487), .Y(n1278) );
OAI211X1TS U2677 ( .A0(n4184), .A1(n5573), .B0(n4176), .C0(n4175), .Y(n1271)
);
OAI211X1TS U2678 ( .A0(n4184), .A1(n5898), .B0(n4136), .C0(n4135), .Y(n1263)
);
OAI211X1TS U2679 ( .A0(n4237), .A1(n5552), .B0(n4110), .C0(n4109), .Y(n1257)
);
OAI211X1TS U2680 ( .A0(n5495), .A1(n4143), .B0(n4021), .C0(n4020), .Y(n1334)
);
OAI21X1TS U2681 ( .A0(n4935), .A1(n4934), .B0(n4933), .Y(n4940) );
OAI211X1TS U2682 ( .A0(n4174), .A1(n5549), .B0(n4097), .C0(n4096), .Y(n1291)
);
OAI211X1TS U2683 ( .A0(n4217), .A1(n4377), .B0(n4376), .C0(n4375), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
INVX4TS U2684 ( .A(n2234), .Y(n2235) );
OAI21X1TS U2685 ( .A0(n4480), .A1(n4479), .B0(n4478), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI211X1TS U2686 ( .A0(n4159), .A1(n5557), .B0(n4102), .C0(n4101), .Y(n1243)
);
OAI211X1TS U2687 ( .A0(n4230), .A1(n5852), .B0(n4126), .C0(n4125), .Y(n1305)
);
OAI21X1TS U2688 ( .A0(n5001), .A1(n4963), .B0(n4962), .Y(n4968) );
OAI211X1TS U2689 ( .A0(n4377), .A1(n4353), .B0(n4352), .C0(n4351), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
OAI211X1TS U2690 ( .A0(n5527), .A1(n4143), .B0(n4179), .C0(n4178), .Y(n1270)
);
OAI211X1TS U2691 ( .A0(n5848), .A1(n4467), .B0(n4423), .C0(n4422), .Y(n1629)
);
OAI211X1TS U2692 ( .A0(n4174), .A1(n5890), .B0(n4140), .C0(n4139), .Y(n1299)
);
OAI211X1TS U2693 ( .A0(n4377), .A1(n4336), .B0(n4284), .C0(n4283), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
OAI211X1TS U2694 ( .A0(n4810), .A1(n5856), .B0(n4433), .C0(n4432), .Y(n1644)
);
OAI211X1TS U2695 ( .A0(n4174), .A1(n5566), .B0(n4106), .C0(n4105), .Y(n1297)
);
OAI211X1TS U2696 ( .A0(n4810), .A1(n5855), .B0(n4436), .C0(n4435), .Y(n1643)
);
OAI211X1TS U2697 ( .A0(n4184), .A1(n5558), .B0(n4151), .C0(n4150), .Y(n1264)
);
OAI211X1TS U2698 ( .A0(n4230), .A1(n5763), .B0(n4093), .C0(n4092), .Y(n1311)
);
OAI211X1TS U2699 ( .A0(n4174), .A1(n5891), .B0(n4165), .C0(n4164), .Y(n1293)
);
OAI211X1TS U2700 ( .A0(n4230), .A1(n5762), .B0(n4091), .C0(n4090), .Y(n1314)
);
OAI211X1TS U2701 ( .A0(n4237), .A1(n5902), .B0(n4236), .C0(n4235), .Y(n1249)
);
OAI211X1TS U2702 ( .A0(n4237), .A1(n5569), .B0(n4104), .C0(n4103), .Y(n1253)
);
OAI211X1TS U2703 ( .A0(n5848), .A1(n4810), .B0(n4454), .C0(n4453), .Y(n1637)
);
OAI211X1TS U2704 ( .A0(n4237), .A1(n5903), .B0(n4134), .C0(n4133), .Y(n1245)
);
OAI211X1TS U2705 ( .A0(n4810), .A1(n5760), .B0(n4446), .C0(n4445), .Y(n1638)
);
OAI211X1TS U2706 ( .A0(n4174), .A1(n5570), .B0(n4167), .C0(n4166), .Y(n1294)
);
OAI211X1TS U2707 ( .A0(n4184), .A1(n5896), .B0(n4163), .C0(n4162), .Y(n1273)
);
OAI211X1TS U2708 ( .A0(n4237), .A1(n5568), .B0(n4156), .C0(n4155), .Y(n1260)
);
OAI211X1TS U2709 ( .A0(n4230), .A1(n4100), .B0(n4099), .C0(n4098), .Y(n1300)
);
OAI211X1TS U2710 ( .A0(n4143), .A1(n5498), .B0(n4017), .C0(n4016), .Y(n1333)
);
OAI211X1TS U2711 ( .A0(n5531), .A1(n4143), .B0(n4075), .C0(n4074), .Y(n1339)
);
OAI211X1TS U2712 ( .A0(n4159), .A1(n5564), .B0(n4158), .C0(n4157), .Y(n1239)
);
OAI211X1TS U2713 ( .A0(n4460), .A1(n4459), .B0(n4458), .C0(n4457), .Y(n1642)
);
OAI211X1TS U2714 ( .A0(n4174), .A1(n5571), .B0(n4173), .C0(n4172), .Y(n1287)
);
OAI211X1TS U2715 ( .A0(n4184), .A1(n5555), .B0(n4153), .C0(n4152), .Y(n1277)
);
OAI31XLTS U2716 ( .A0(n4269), .A1(n4005), .A2(n5704), .B0(n4004), .Y(n1328)
);
AOI32X2TS U2717 ( .A0(n4211), .A1(n5446), .A2(n4210), .B0(n4241), .B1(n5443),
.Y(n4365) );
CLKINVX2TS U2718 ( .A(n3744), .Y(n3609) );
NOR2X1TS U2719 ( .A(n4888), .B(n4887), .Y(n4893) );
AND2X2TS U2720 ( .A(n4456), .B(n4447), .Y(n3883) );
NOR2X1TS U2721 ( .A(n5443), .B(n2245), .Y(n5438) );
AOI21X2TS U2722 ( .A0(n4528), .A1(n4527), .B0(n4526), .Y(n4564) );
OR2X2TS U2723 ( .A(n2265), .B(n4407), .Y(n4450) );
OAI21X1TS U2724 ( .A0(n5635), .A1(n3991), .B0(n3971), .Y(n1387) );
OAI21X1TS U2725 ( .A0(n5654), .A1(n4000), .B0(n3968), .Y(n1357) );
OAI21X1TS U2726 ( .A0(n5653), .A1(n4000), .B0(n3980), .Y(n1359) );
INVX2TS U2727 ( .A(n4025), .Y(n4047) );
OAI21X1TS U2728 ( .A0(n5631), .A1(n3996), .B0(n3977), .Y(n1393) );
OAI21X1TS U2729 ( .A0(n5633), .A1(n3996), .B0(n3987), .Y(n1389) );
OAI21X1TS U2730 ( .A0(n5652), .A1(n4000), .B0(n3999), .Y(n1361) );
OR2X2TS U2731 ( .A(n4460), .B(n4406), .Y(n2146) );
OAI21X1TS U2732 ( .A0(n5636), .A1(n3991), .B0(n3990), .Y(n1385) );
INVX4TS U2733 ( .A(n4011), .Y(n4143) );
OAI21X1TS U2734 ( .A0(n5642), .A1(n3991), .B0(n3965), .Y(n1373) );
INVX3TS U2735 ( .A(n4025), .Y(n5572) );
OAI21X1TS U2736 ( .A0(n5638), .A1(n3991), .B0(n3967), .Y(n1381) );
OAI21X1TS U2737 ( .A0(n5660), .A1(n4000), .B0(n3969), .Y(n1349) );
OAI21X1TS U2738 ( .A0(n5887), .A1(n4000), .B0(n3961), .Y(n1353) );
OAI21X1TS U2739 ( .A0(n5641), .A1(n3991), .B0(n3964), .Y(n1375) );
INVX1TS U2740 ( .A(n4879), .Y(n4888) );
OAI21X1TS U2741 ( .A0(n5620), .A1(n3996), .B0(n3983), .Y(n1407) );
OAI21X1TS U2742 ( .A0(n5655), .A1(n4000), .B0(n3962), .Y(n1355) );
OAI21X1TS U2743 ( .A0(n5656), .A1(n4000), .B0(n3979), .Y(n1351) );
INVX3TS U2744 ( .A(n4025), .Y(n4059) );
OAI21X1TS U2745 ( .A0(n5628), .A1(n3996), .B0(n3975), .Y(n1395) );
AO22XLTS U2746 ( .A0(n2249), .A1(FPADDSUB_Add_Subt_result[9]), .B0(
FPADDSUB_DmP[14]), .B1(n4254), .Y(n4255) );
OAI21X1TS U2747 ( .A0(n5639), .A1(n3991), .B0(n3963), .Y(n1379) );
OAI21X1TS U2748 ( .A0(n5623), .A1(n3996), .B0(n3974), .Y(n1401) );
OAI21X1TS U2749 ( .A0(n5622), .A1(n3996), .B0(n3976), .Y(n1403) );
OAI21X1TS U2750 ( .A0(n5648), .A1(n4000), .B0(n3986), .Y(n1365) );
OAI21X1TS U2751 ( .A0(n5644), .A1(n3991), .B0(n3984), .Y(n1371) );
OAI21X1TS U2752 ( .A0(n5640), .A1(n3991), .B0(n3981), .Y(n1377) );
OAI21X1TS U2753 ( .A0(n5632), .A1(n3996), .B0(n3995), .Y(n1391) );
NOR2X1TS U2754 ( .A(n5443), .B(n4217), .Y(n4808) );
OAI21X1TS U2755 ( .A0(n5627), .A1(n3996), .B0(n3978), .Y(n1397) );
OAI21X1TS U2756 ( .A0(n5625), .A1(n3996), .B0(n3992), .Y(n1399) );
OAI21X1TS U2757 ( .A0(n5637), .A1(n3991), .B0(n3973), .Y(n1383) );
OAI32X1TS U2758 ( .A0(n3947), .A1(n3886), .A2(n5826), .B0(n5587), .B1(n3948),
.Y(n1701) );
OAI21X1TS U2759 ( .A0(n2553), .A1(n2552), .B0(n2551), .Y(n2558) );
INVX6TS U2760 ( .A(n3302), .Y(n2283) );
INVX3TS U2761 ( .A(n4217), .Y(n2244) );
INVX3TS U2762 ( .A(n4217), .Y(n2243) );
AND2X2TS U2763 ( .A(n4010), .B(FPSENCOS_sel_mux_2_reg[1]), .Y(n4011) );
NAND2X6TS U2764 ( .A(n2981), .B(n2980), .Y(n3771) );
INVX3TS U2765 ( .A(n4336), .Y(n2261) );
OAI21X1TS U2766 ( .A0(n5852), .A1(n5504), .B0(n4068), .Y(n1789) );
OAI21X1TS U2767 ( .A0(n5866), .A1(n5504), .B0(n4070), .Y(n1418) );
NOR2X4TS U2768 ( .A(n5412), .B(n5472), .Y(n5322) );
OAI211X1TS U2769 ( .A0(n4475), .A1(n4474), .B0(n4473), .C0(n4472), .Y(n1838)
);
AO22XLTS U2770 ( .A0(n4367), .A1(FPADDSUB_Add_Subt_result[13]), .B0(
FPADDSUB_DmP[10]), .B1(n4254), .Y(n4244) );
OR2X2TS U2771 ( .A(FPMULT_FSM_selector_C), .B(n3904), .Y(n2150) );
NAND3X1TS U2772 ( .A(n5496), .B(n5507), .C(n5515), .Y(n4064) );
AOI31X2TS U2773 ( .A0(n2183), .A1(n5536), .A2(n5764), .B0(n5505), .Y(n5526)
);
INVX4TS U2774 ( .A(n2315), .Y(n2119) );
OAI211X1TS U2775 ( .A0(n5321), .A1(n5807), .B0(n4196), .C0(n4195), .Y(n2057)
);
NAND2X2TS U2776 ( .A(n5657), .B(FPSENCOS_sel_mux_1_reg), .Y(n4025) );
NAND3BX4TS U2777 ( .AN(n5586), .B(n3929), .C(n5492), .Y(n3930) );
NAND2X4TS U2778 ( .A(n4216), .B(n4215), .Y(n4217) );
OAI211X1TS U2779 ( .A0(n5321), .A1(n5854), .B0(n4223), .C0(n5317), .Y(n2054)
);
OR2X2TS U2780 ( .A(n4216), .B(n4215), .Y(n4212) );
OAI21X1TS U2781 ( .A0(n4300), .A1(n5752), .B0(n4318), .Y(op_result[28]) );
OAI21X1TS U2782 ( .A0(n2163), .A1(n5747), .B0(n4295), .Y(op_result[14]) );
OAI21X1TS U2783 ( .A0(n4324), .A1(n5749), .B0(n4285), .Y(op_result[12]) );
OAI21X1TS U2784 ( .A0(n2163), .A1(n5832), .B0(n4302), .Y(op_result[15]) );
OAI21X1TS U2785 ( .A0(n4300), .A1(n5754), .B0(n4317), .Y(op_result[26]) );
OAI21X1TS U2786 ( .A0(n2163), .A1(n5751), .B0(n4320), .Y(op_result[29]) );
OAI21X1TS U2787 ( .A0(n4324), .A1(n5748), .B0(n4293), .Y(op_result[13]) );
OAI21X1TS U2788 ( .A0(n2163), .A1(n5753), .B0(n4319), .Y(op_result[27]) );
OAI21X1TS U2789 ( .A0(n4300), .A1(n5835), .B0(n4315), .Y(op_result[23]) );
OAI21X1TS U2790 ( .A0(n4300), .A1(n5829), .B0(n4311), .Y(op_result[22]) );
OAI21X1TS U2791 ( .A0(n4300), .A1(n5834), .B0(n4306), .Y(op_result[31]) );
OAI21X1TS U2792 ( .A0(n4272), .A1(n5744), .B0(n4308), .Y(op_result[19]) );
OAI21X1TS U2793 ( .A0(n4272), .A1(n5830), .B0(n4309), .Y(op_result[21]) );
OAI21X1TS U2794 ( .A0(n4324), .A1(n5831), .B0(n4314), .Y(op_result[18]) );
OAI21X1TS U2795 ( .A0(n4324), .A1(n5743), .B0(n4307), .Y(op_result[20]) );
OAI21X1TS U2796 ( .A0(n4300), .A1(n5756), .B0(n4316), .Y(op_result[24]) );
OAI21X1TS U2797 ( .A0(n4300), .A1(n5757), .B0(n4304), .Y(op_result[30]) );
OAI21X1TS U2798 ( .A0(n4324), .A1(n5755), .B0(n4323), .Y(op_result[25]) );
OAI21X1TS U2799 ( .A0(n4324), .A1(n5746), .B0(n4301), .Y(op_result[16]) );
BUFX8TS U2800 ( .A(n3590), .Y(n3740) );
INVX3TS U2801 ( .A(n4003), .Y(n4232) );
XNOR2X4TS U2802 ( .A(n2986), .B(FPMULT_Op_MX[11]), .Y(n2971) );
INVX3TS U2803 ( .A(n4003), .Y(n4780) );
INVX3TS U2804 ( .A(n4003), .Y(n4180) );
BUFX6TS U2805 ( .A(n2739), .Y(n3709) );
INVX3TS U2806 ( .A(n4003), .Y(n4225) );
OAI21X2TS U2807 ( .A0(n2990), .A1(n2989), .B0(n2988), .Y(n2991) );
NAND2X2TS U2808 ( .A(n2474), .B(n2423), .Y(n2444) );
NOR2X4TS U2809 ( .A(n5048), .B(n5828), .Y(n5060) );
INVX3TS U2810 ( .A(n4483), .Y(n4597) );
OR2X2TS U2811 ( .A(n5048), .B(FPMULT_FSM_selector_C), .Y(n5304) );
NOR2X4TS U2812 ( .A(n4452), .B(n4346), .Y(n3817) );
INVX3TS U2813 ( .A(n4003), .Y(n4198) );
INVX3TS U2814 ( .A(n4483), .Y(n4607) );
INVX3TS U2815 ( .A(n4003), .Y(n4170) );
INVX3TS U2816 ( .A(n4483), .Y(n4610) );
INVX3TS U2817 ( .A(n4483), .Y(n4635) );
NAND2X2TS U2818 ( .A(n2445), .B(n2433), .Y(n2435) );
INVX3TS U2819 ( .A(n4483), .Y(n4640) );
AOI21X2TS U2820 ( .A0(n2502), .A1(n2396), .B0(n2395), .Y(n2397) );
OAI21X1TS U2821 ( .A0(n4324), .A1(n5750), .B0(n4297), .Y(op_result[10]) );
OAI21X1TS U2822 ( .A0(n2163), .A1(n5604), .B0(n4294), .Y(op_result[7]) );
OAI21X1TS U2823 ( .A0(n2163), .A1(n5605), .B0(n4286), .Y(op_result[6]) );
OAI21X1TS U2824 ( .A0(n2163), .A1(n5610), .B0(n4291), .Y(op_result[3]) );
OAI21X1TS U2825 ( .A0(n4324), .A1(n5606), .B0(n4292), .Y(op_result[5]) );
OAI21X1TS U2826 ( .A0(n4324), .A1(n5609), .B0(n4287), .Y(op_result[4]) );
OAI21X1TS U2827 ( .A0(n2163), .A1(n5601), .B0(n4299), .Y(op_result[9]) );
OAI21X1TS U2828 ( .A0(n4324), .A1(n5603), .B0(n4290), .Y(op_result[8]) );
NOR2X2TS U2829 ( .A(FPSENCOS_sel_mux_3_reg), .B(n3982), .Y(n3951) );
INVX3TS U2830 ( .A(n5036), .Y(n5037) );
INVX3TS U2831 ( .A(n5036), .Y(n5040) );
INVX2TS U2832 ( .A(n5036), .Y(n5035) );
INVX3TS U2833 ( .A(n5036), .Y(n5323) );
AND3X2TS U2834 ( .A(n5599), .B(n5759), .C(n5841), .Y(n5600) );
NAND3X1TS U2835 ( .A(n2183), .B(n5506), .C(n5768), .Y(n5533) );
OAI2BB2XLTS U2836 ( .B0(n2855), .B1(n2862), .A0N(n2854), .A1N(n2853), .Y(
n2858) );
OAI211X1TS U2837 ( .A0(n2828), .A1(n2884), .B0(n2827), .C0(n2826), .Y(n2833)
);
INVX3TS U2838 ( .A(n5511), .Y(n5529) );
NAND2X2TS U2839 ( .A(n3595), .B(n2963), .Y(n2965) );
AO22X1TS U2840 ( .A0(FPADDSUB_LZA_output[3]), .A1(n3812), .B0(n2164), .B1(
FPADDSUB_exp_oper_result[3]), .Y(n2147) );
AND2X2TS U2841 ( .A(n3900), .B(FPMULT_FS_Module_state_reg[1]), .Y(n4193) );
NAND2X2TS U2842 ( .A(n2763), .B(n2762), .Y(n2317) );
NOR2X1TS U2843 ( .A(FPADDSUB_LZA_output[4]), .B(n4876), .Y(n4652) );
INVX2TS U2844 ( .A(n2552), .Y(n2504) );
OAI31XLTS U2845 ( .A0(n4335), .A1(n5683), .A2(n4334), .B0(n4333), .Y(
operation_ready) );
OAI21X1TS U2846 ( .A0(n2163), .A1(n5833), .B0(n4289), .Y(op_result[11]) );
OAI21X2TS U2847 ( .A0(n2961), .A1(n2960), .B0(n2959), .Y(n3597) );
NAND2X2TS U2848 ( .A(n3950), .B(FPSENCOS_sel_mux_3_reg), .Y(n3953) );
BUFX3TS U2849 ( .A(n5687), .Y(n5692) );
NOR2X2TS U2850 ( .A(n2419), .B(n2418), .Y(n2478) );
INVX3TS U2851 ( .A(n5589), .Y(n5597) );
INVX3TS U2852 ( .A(n2182), .Y(n5508) );
NAND2X2TS U2853 ( .A(n2374), .B(n2373), .Y(n2532) );
AND2X4TS U2854 ( .A(n4515), .B(n4001), .Y(n4003) );
INVX1TS U2855 ( .A(n3914), .Y(n3916) );
NAND2X2TS U2856 ( .A(n2392), .B(n2391), .Y(n2551) );
AND2X2TS U2857 ( .A(n4194), .B(n3936), .Y(n5474) );
NAND2X2TS U2858 ( .A(n2419), .B(n2418), .Y(n2567) );
OAI21X1TS U2859 ( .A0(r_mode[1]), .A1(FPADDSUB_sign_final_result), .B0(n3959), .Y(n3960) );
NOR2X1TS U2860 ( .A(n5042), .B(n5788), .Y(n5044) );
NOR2X1TS U2861 ( .A(n5042), .B(n5210), .Y(n5043) );
INVX1TS U2862 ( .A(n3932), .Y(n3841) );
INVX3TS U2863 ( .A(n2181), .Y(n2183) );
INVX3TS U2864 ( .A(FPSENCOS_cont_iter_out[2]), .Y(n5536) );
NAND2BX1TS U2865 ( .AN(FPADDSUB_Sgf_normalized_result[25]), .B(n4800), .Y(
n4846) );
NOR2X1TS U2866 ( .A(n4795), .B(n5774), .Y(n4701) );
NOR2X1TS U2867 ( .A(n5727), .B(n4795), .Y(n4702) );
NOR2X1TS U2868 ( .A(n5742), .B(n4795), .Y(n4796) );
AND2X4TS U2869 ( .A(n5034), .B(n5033), .Y(n5036) );
NOR2X1TS U2870 ( .A(n5740), .B(n4795), .Y(n4760) );
NOR2X1TS U2871 ( .A(n5821), .B(n4800), .Y(n4757) );
NOR2X1TS U2872 ( .A(n5822), .B(n4795), .Y(n4751) );
AND2X2TS U2873 ( .A(n4194), .B(n5034), .Y(n5098) );
NOR2X4TS U2874 ( .A(n4513), .B(FPADDSUB_FS_Module_state_reg[3]), .Y(n4919)
);
NOR2X1TS U2875 ( .A(n5812), .B(n4800), .Y(n4744) );
XNOR2X2TS U2876 ( .A(n2761), .B(n2780), .Y(n2316) );
NAND3X1TS U2877 ( .A(n3958), .B(r_mode[1]), .C(n3909), .Y(n3797) );
NAND3X1TS U2878 ( .A(n5805), .B(n2825), .C(FPADDSUB_intDX[26]), .Y(n2827) );
NOR2X1TS U2879 ( .A(n2883), .B(FPADDSUB_intDY[24]), .Y(n2824) );
NOR2X1TS U2880 ( .A(n5790), .B(n4800), .Y(n4728) );
OAI211X2TS U2881 ( .A0(FPADDSUB_intDX[12]), .A1(n5801), .B0(n2860), .C0(
n2846), .Y(n2862) );
INVX1TS U2882 ( .A(n4194), .Y(n4195) );
NOR2X1TS U2883 ( .A(DP_OP_498J12_123_5135_n727), .B(n2330), .Y(n3262) );
INVX1TS U2884 ( .A(n4512), .Y(n4326) );
OAI211X2TS U2885 ( .A0(FPADDSUB_intDX[20]), .A1(n5779), .B0(n2880), .C0(
n2865), .Y(n2874) );
NOR2X1TS U2886 ( .A(n5789), .B(n4800), .Y(n4729) );
CLKINVX2TS U2887 ( .A(n3949), .Y(n4664) );
INVX4TS U2888 ( .A(n4191), .Y(n4288) );
NAND3X1TS U2889 ( .A(n5420), .B(n5419), .C(n5418), .Y(n5910) );
OAI21X1TS U2890 ( .A0(FPADDSUB_intDX[23]), .A1(n5816), .B0(
FPADDSUB_intDX[22]), .Y(n2876) );
NAND2BX1TS U2891 ( .AN(FPADDSUB_intDX[21]), .B(FPADDSUB_intDY[21]), .Y(n2865) );
NAND2BX1TS U2892 ( .AN(FPADDSUB_intDY[27]), .B(FPADDSUB_intDX[27]), .Y(n2826) );
NAND2BX1TS U2893 ( .AN(FPADDSUB_intDX[27]), .B(FPADDSUB_intDY[27]), .Y(n2825) );
NAND2BX1TS U2894 ( .AN(FPADDSUB_intDX[24]), .B(FPADDSUB_intDY[24]), .Y(n2881) );
INVX3TS U2895 ( .A(n2364), .Y(n2237) );
NOR2X1TS U2896 ( .A(FPADDSUB_Add_Subt_result[9]), .B(
FPADDSUB_Add_Subt_result[8]), .Y(n4643) );
NAND2BX1TS U2897 ( .AN(FPADDSUB_intDX[9]), .B(FPADDSUB_intDY[9]), .Y(n2850)
);
NAND2BX1TS U2898 ( .AN(FPADDSUB_intDX[13]), .B(FPADDSUB_intDY[13]), .Y(n2846) );
NOR2X1TS U2899 ( .A(n5741), .B(n5850), .Y(FPMULT_S_Oper_A_exp[8]) );
INVX3TS U2900 ( .A(n2356), .Y(n2199) );
NAND2BX1TS U2901 ( .AN(FPADDSUB_intDX[19]), .B(FPADDSUB_intDY[19]), .Y(n2871) );
INVX3TS U2902 ( .A(n2126), .Y(n2170) );
OR2X2TS U2903 ( .A(FPADDSUB_FSM_selector_B[0]), .B(
FPADDSUB_FSM_selector_B[1]), .Y(n3813) );
CLKAND2X2TS U2904 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[12]), .Y(n2726) );
INVX3TS U2905 ( .A(n2359), .Y(n2197) );
INVX3TS U2906 ( .A(n2336), .Y(n2188) );
NAND2X2TS U2907 ( .A(n4269), .B(operation[2]), .Y(n4191) );
NAND3X1TS U2908 ( .A(n3803), .B(n3802), .C(n3801), .Y(n3804) );
ADDHX1TS U2909 ( .A(n3782), .B(n3781), .CO(DP_OP_498J12_123_5135_n369), .S(
n2801) );
CMPR42X2TS U2910 ( .A(mult_x_159_n337), .B(mult_x_159_n361), .C(
mult_x_159_n260), .D(mult_x_159_n257), .ICI(mult_x_159_n256), .S(
mult_x_159_n254), .ICO(mult_x_159_n252), .CO(mult_x_159_n253) );
NOR2XLTS U2911 ( .A(n2972), .B(n2975), .Y(n2973) );
XNOR2X2TS U2912 ( .A(n2975), .B(n2974), .Y(n2979) );
CMPR42X2TS U2913 ( .A(DP_OP_498J12_123_5135_n417), .B(
DP_OP_498J12_123_5135_n340), .C(DP_OP_498J12_123_5135_n344), .D(
DP_OP_498J12_123_5135_n430), .ICI(DP_OP_498J12_123_5135_n443), .S(
DP_OP_498J12_123_5135_n338), .ICO(DP_OP_498J12_123_5135_n336), .CO(
DP_OP_498J12_123_5135_n337) );
XNOR2X2TS U2914 ( .A(n2370), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]), .Y(n2369) );
INVX2TS U2915 ( .A(FPMULT_Sgf_operation_Result[1]), .Y(n2370) );
OAI21X2TS U2916 ( .A0(n5296), .A1(n5309), .B0(n5297), .Y(n5269) );
CMPR42X2TS U2917 ( .A(DP_OP_498J12_123_5135_n406), .B(
DP_OP_498J12_123_5135_n418), .C(DP_OP_498J12_123_5135_n431), .D(
DP_OP_498J12_123_5135_n352), .ICI(DP_OP_498J12_123_5135_n457), .S(
DP_OP_498J12_123_5135_n346), .ICO(DP_OP_498J12_123_5135_n344), .CO(
DP_OP_498J12_123_5135_n345) );
AOI21X4TS U2918 ( .A0(n2998), .A1(n3011), .B0(n2997), .Y(n3054) );
NOR2X4TS U2919 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n2961) );
OAI21X4TS U2920 ( .A0(n2622), .A1(n2621), .B0(n2620), .Y(n2630) );
ADDFHX2TS U2921 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]), .B(
n2411), .CI(n2410), .CO(n2424), .S(n2421) );
NOR2X2TS U2922 ( .A(n3752), .B(n3757), .Y(n2998) );
OAI21X2TS U2923 ( .A0(n3751), .A1(n3757), .B0(n3758), .Y(n2997) );
OAI21X1TS U2924 ( .A0(n3600), .A1(n3599), .B0(n3598), .Y(n3601) );
OAI21X2TS U2925 ( .A0(n3604), .A1(n3598), .B0(n3605), .Y(n2962) );
OAI21X2TS U2926 ( .A0(n4556), .A1(n4552), .B0(n4553), .Y(n4551) );
OAI21X2TS U2927 ( .A0(n3567), .A1(n3564), .B0(n3565), .Y(n3562) );
NOR2X2TS U2928 ( .A(n5126), .B(n5117), .Y(n2656) );
AOI21X4TS U2929 ( .A0(n2598), .A1(n2597), .B0(n2596), .Y(n2606) );
AOI211XLTS U2930 ( .A0(n4650), .A1(n4649), .B0(n4648), .C0(n4867), .Y(n4654)
);
ADDFX2TS U2931 ( .A(n2923), .B(n2922), .CI(n2921), .CO(n2924), .S(n2918) );
ADDHX1TS U2932 ( .A(n2955), .B(n2954), .CO(mult_x_159_n267), .S(n2921) );
OAI21X2TS U2933 ( .A0(n3374), .A1(n3469), .B0(n3375), .Y(n2705) );
OAI21X1TS U2934 ( .A0(n3361), .A1(n3357), .B0(n3358), .Y(n3356) );
NAND2X4TS U2935 ( .A(n2889), .B(n4483), .Y(n2366) );
OAI211X1TS U2936 ( .A0(n4810), .A1(n5864), .B0(n3822), .C0(n3826), .Y(n3823)
);
AOI21X4TS U2937 ( .A0(n2523), .A1(n2378), .B0(n2377), .Y(n2501) );
ADDFHX2TS U2938 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]), .B(
n2380), .CI(n2379), .CO(n2387), .S(n2376) );
OAI22X2TS U2939 ( .A0(n3772), .A1(n2980), .B0(n3771), .B1(n3766), .Y(n3776)
);
OAI21X4TS U2940 ( .A0(n2606), .A1(n2605), .B0(n2604), .Y(n2614) );
NAND2X2TS U2941 ( .A(n2970), .B(n2969), .Y(n2986) );
ADDFHX2TS U2942 ( .A(n3749), .B(n3748), .CI(n3747), .CO(
DP_OP_498J12_123_5135_n289), .S(DP_OP_498J12_123_5135_n297) );
OAI22X2TS U2943 ( .A0(n3068), .A1(n2179), .B0(n3770), .B1(n2994), .Y(n3749)
);
INVX2TS U2944 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n2520) );
AOI21X2TS U2945 ( .A0(n2519), .A1(n2520), .B0(n2367), .Y(n2516) );
XOR2X4TS U2946 ( .A(n3761), .B(n3760), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22) );
AOI21X2TS U2947 ( .A0(n3756), .A1(n3755), .B0(n3754), .Y(n3761) );
OAI21X2TS U2948 ( .A0(n2161), .A1(FPMULT_Op_MX[20]), .B0(FPMULT_Op_MX[7]),
.Y(n2977) );
INVX4TS U2949 ( .A(n2139), .Y(n2212) );
NAND2X4TS U2950 ( .A(n3216), .B(n2212), .Y(n3308) );
XOR2X2TS U2951 ( .A(FPMULT_Op_MY[6]), .B(n2228), .Y(n2139) );
AOI21X2TS U2952 ( .A0(n3124), .A1(n2933), .B0(n2932), .Y(n2934) );
NOR2X2TS U2953 ( .A(n2449), .B(n2451), .Y(n2433) );
AOI21X4TS U2954 ( .A0(n2446), .A1(n2433), .B0(n2432), .Y(n2434) );
ADDFHX2TS U2955 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]), .B(
n2386), .CI(n2385), .CO(n2393), .S(n2392) );
AOI21X2TS U2956 ( .A0(n3787), .A1(n2361), .B0(n2362), .Y(n3067) );
CMPR42X2TS U2957 ( .A(DP_OP_498J12_123_5135_n336), .B(
DP_OP_498J12_123_5135_n468), .C(DP_OP_498J12_123_5135_n337), .D(
DP_OP_498J12_123_5135_n333), .ICI(DP_OP_498J12_123_5135_n330), .S(
DP_OP_498J12_123_5135_n327), .ICO(DP_OP_498J12_123_5135_n325), .CO(
DP_OP_498J12_123_5135_n326) );
AOI21X2TS U2958 ( .A0(n5115), .A1(n2657), .B0(n2656), .Y(n2658) );
ADDFHX2TS U2959 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]), .B(
n2413), .CI(n2412), .CO(n2420), .S(n2419) );
AOI21X2TS U2960 ( .A0(n3787), .A1(n3786), .B0(n3785), .Y(n3791) );
NAND2X4TS U2961 ( .A(DP_OP_498J12_123_5135_n293), .B(
DP_OP_498J12_123_5135_n299), .Y(n3518) );
XOR2X4TS U2962 ( .A(n4506), .B(FPADDSUB_intDX[31]), .Y(n4667) );
INVX6TS U2963 ( .A(n4848), .Y(n4696) );
AOI21X2TS U2964 ( .A0(n5387), .A1(n2576), .B0(n2575), .Y(n2577) );
OAI21X1TS U2965 ( .A0(n5396), .A1(n5393), .B0(n5397), .Y(n2575) );
OAI21X2TS U2966 ( .A0(n5368), .A1(n5383), .B0(n5369), .Y(n5387) );
NOR2X8TS U2967 ( .A(n5053), .B(n5052), .Y(n3806) );
XNOR2X2TS U2968 ( .A(n2630), .B(n2626), .Y(n2650) );
NOR2X2TS U2969 ( .A(n4675), .B(n4674), .Y(n4889) );
NAND2X4TS U2970 ( .A(DP_OP_498J12_123_5135_n310), .B(
DP_OP_498J12_123_5135_n318), .Y(n3529) );
AOI21X2TS U2971 ( .A0(n5217), .A1(n2590), .B0(n2589), .Y(n2591) );
ADDFHX2TS U2972 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]), .B(
n2372), .CI(n2371), .CO(n2375), .S(n2374) );
CMPR42X2TS U2973 ( .A(DP_OP_498J12_123_5135_n444), .B(
DP_OP_498J12_123_5135_n350), .C(DP_OP_498J12_123_5135_n470), .D(
DP_OP_498J12_123_5135_n346), .ICI(DP_OP_498J12_123_5135_n347), .S(
DP_OP_498J12_123_5135_n343), .ICO(DP_OP_498J12_123_5135_n341), .CO(
DP_OP_498J12_123_5135_n342) );
XNOR2X2TS U2974 ( .A(n3720), .B(n2288), .Y(n3731) );
XOR2X4TS U2975 ( .A(n3582), .B(n3580), .Y(n2136) );
CMPR42X2TS U2976 ( .A(DP_OP_498J12_123_5135_n445), .B(
DP_OP_498J12_123_5135_n458), .C(DP_OP_498J12_123_5135_n351), .D(
DP_OP_498J12_123_5135_n471), .ICI(DP_OP_498J12_123_5135_n354), .S(
DP_OP_498J12_123_5135_n349), .ICO(DP_OP_498J12_123_5135_n347), .CO(
DP_OP_498J12_123_5135_n348) );
NAND2X8TS U2977 ( .A(n5075), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[18]), .Y(n5067) );
AOI21X4TS U2978 ( .A0(n2630), .A1(n2629), .B0(n2628), .Y(n2638) );
OAI21X4TS U2979 ( .A0(n2638), .A1(n2637), .B0(n2636), .Y(n2645) );
NOR2X1TS U2980 ( .A(n4572), .B(n4565), .Y(n4528) );
OAI21X1TS U2981 ( .A0(n4565), .A1(n4573), .B0(n4566), .Y(n4526) );
XOR2X1TS U2982 ( .A(FPMULT_Op_MY[8]), .B(n2194), .Y(n3212) );
INVX2TS U2983 ( .A(n4557), .Y(n4536) );
AOI222X1TS U2984 ( .A0(FPADDSUB_intDY[4]), .A1(n5715), .B0(n2841), .B1(n2840), .C0(FPADDSUB_intDY[5]), .C1(n5734), .Y(n2843) );
AOI2BB2XLTS U2985 ( .B0(FPADDSUB_intDX[3]), .B1(n5843), .A0N(
FPADDSUB_intDY[2]), .A1N(n2839), .Y(n2840) );
OAI21XLTS U2986 ( .A0(FPADDSUB_intDX[3]), .A1(n5843), .B0(FPADDSUB_intDX[2]),
.Y(n2839) );
OAI21X2TS U2987 ( .A0(n2492), .A1(n2488), .B0(n2493), .Y(n2446) );
AO21XLTS U2988 ( .A0(n3282), .A1(n2221), .B0(n2138), .Y(mult_x_159_n342) );
AOI21X1TS U2989 ( .A0(n5044), .A1(n5209), .B0(n5043), .Y(n5172) );
NAND2X1TS U2990 ( .A(n3815), .B(n3838), .Y(n4430) );
AOI21X2TS U2991 ( .A0(n4551), .A1(n2148), .B0(n4543), .Y(n4580) );
INVX2TS U2992 ( .A(n4549), .Y(n4543) );
BUFX3TS U2993 ( .A(n3237), .Y(n3311) );
AO21X2TS U2994 ( .A0(n2987), .A1(n2983), .B0(n2967), .Y(n2968) );
AO21XLTS U2995 ( .A0(n2276), .A1(n2219), .B0(n2359), .Y(mult_x_121_n320) );
NAND2X1TS U2996 ( .A(n4574), .B(n4573), .Y(n4575) );
CLKXOR2X2TS U2997 ( .A(n4564), .B(n4563), .Y(n5334) );
NAND2X1TS U2998 ( .A(n4562), .B(n4561), .Y(n4563) );
XNOR2X2TS U2999 ( .A(n4569), .B(n4568), .Y(n5332) );
NAND2X1TS U3000 ( .A(n4567), .B(n4566), .Y(n4568) );
MX2X1TS U3001 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U3002 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
CLKXOR2X2TS U3003 ( .A(n4556), .B(n4555), .Y(n5336) );
NAND2X1TS U3004 ( .A(n4554), .B(n4553), .Y(n4555) );
XNOR2X2TS U3005 ( .A(n4559), .B(n4558), .Y(n5335) );
NAND2X1TS U3006 ( .A(n2149), .B(n4557), .Y(n4558) );
XNOR2X2TS U3007 ( .A(n4551), .B(n4550), .Y(n5337) );
NAND2X1TS U3008 ( .A(n2148), .B(n4549), .Y(n4550) );
CLKXOR2X2TS U3009 ( .A(n4580), .B(n4548), .Y(n5338) );
NAND2X1TS U3010 ( .A(n4547), .B(n4578), .Y(n4548) );
INVX2TS U3011 ( .A(n4579), .Y(n4547) );
AO22XLTS U3012 ( .A0(FPSENCOS_d_ff_Yn[30]), .A1(n5662), .B0(n5661), .B1(
FPSENCOS_d_ff2_Y[30]), .Y(n1419) );
NOR2X4TS U3013 ( .A(n2168), .B(FPMULT_Op_MY[3]), .Y(n2768) );
OAI21X2TS U3014 ( .A0(n2443), .A1(n2435), .B0(n2434), .Y(n2436) );
NOR2X1TS U3015 ( .A(DP_OP_498J12_123_5135_n727), .B(n2328), .Y(
mult_x_159_n194) );
NAND2BXLTS U3016 ( .AN(n2298), .B(n2203), .Y(n3198) );
CLKINVX6TS U3017 ( .A(n2137), .Y(n2290) );
INVX2TS U3018 ( .A(n3615), .Y(n3617) );
INVX2TS U3019 ( .A(n2491), .Y(n2487) );
OAI21X2TS U3020 ( .A0(n2561), .A1(n2444), .B0(n2443), .Y(n2491) );
OR2X1TS U3021 ( .A(n2472), .B(n2471), .Y(n2597) );
NAND2BXLTS U3022 ( .AN(n3306), .B(n2231), .Y(n3307) );
NAND2X4TS U3023 ( .A(n2893), .B(n3288), .Y(n3290) );
INVX4TS U3024 ( .A(n2115), .Y(n2193) );
BUFX3TS U3025 ( .A(n2739), .Y(n2293) );
OAI21X1TS U3026 ( .A0(n5284), .A1(n5783), .B0(n5041), .Y(n5209) );
MX2X1TS U3027 ( .A(FPADDSUB_DMP[7]), .B(FPADDSUB_Sgf_normalized_result[9]),
.S0(n4700), .Y(n4708) );
MX2X1TS U3028 ( .A(FPADDSUB_DMP[6]), .B(FPADDSUB_Sgf_normalized_result[8]),
.S0(n4700), .Y(n4706) );
MX2X1TS U3029 ( .A(FPADDSUB_DMP[10]), .B(FPADDSUB_Sgf_normalized_result[12]),
.S0(n4753), .Y(n4716) );
MX2X1TS U3030 ( .A(FPADDSUB_DMP[12]), .B(FPADDSUB_Sgf_normalized_result[14]),
.S0(n4753), .Y(n4720) );
MX2X1TS U3031 ( .A(FPADDSUB_DMP[11]), .B(FPADDSUB_Sgf_normalized_result[13]),
.S0(n4753), .Y(n4718) );
MX2X1TS U3032 ( .A(FPADDSUB_DMP[2]), .B(FPADDSUB_Sgf_normalized_result[4]),
.S0(n4700), .Y(n4684) );
MX2X1TS U3033 ( .A(FPADDSUB_DMP[3]), .B(FPADDSUB_Sgf_normalized_result[5]),
.S0(n4700), .Y(n4686) );
MX2X1TS U3034 ( .A(FPADDSUB_DMP[4]), .B(FPADDSUB_Sgf_normalized_result[6]),
.S0(n4700), .Y(n4688) );
MX2X1TS U3035 ( .A(FPADDSUB_DMP[8]), .B(FPADDSUB_Sgf_normalized_result[10]),
.S0(n4700), .Y(n4710) );
NAND2X1TS U3036 ( .A(n4207), .B(n4206), .Y(n4520) );
MX2X1TS U3037 ( .A(FPADDSUB_DMP[17]), .B(FPADDSUB_Sgf_normalized_result[19]),
.S0(n4753), .Y(n4745) );
MX2X1TS U3038 ( .A(FPADDSUB_DMP[13]), .B(FPADDSUB_Sgf_normalized_result[15]),
.S0(n4753), .Y(n4730) );
MX2X1TS U3039 ( .A(FPADDSUB_DMP[14]), .B(FPADDSUB_Sgf_normalized_result[16]),
.S0(n4753), .Y(n4732) );
AOI21X2TS U3040 ( .A0(n4953), .A1(n4727), .B0(n4726), .Y(n4970) );
MX2X1TS U3041 ( .A(FPADDSUB_DMP[15]), .B(FPADDSUB_Sgf_normalized_result[17]),
.S0(n4753), .Y(n4738) );
MX2X1TS U3042 ( .A(FPADDSUB_DMP[16]), .B(FPADDSUB_Sgf_normalized_result[18]),
.S0(n4753), .Y(n4742) );
MX2X1TS U3043 ( .A(FPADDSUB_DMP[1]), .B(FPADDSUB_Sgf_normalized_result[3]),
.S0(n4700), .Y(n4682) );
MX2X1TS U3044 ( .A(FPADDSUB_DMP[9]), .B(FPADDSUB_Sgf_normalized_result[11]),
.S0(n4700), .Y(n4714) );
MX2X1TS U3045 ( .A(FPADDSUB_DMP[0]), .B(FPADDSUB_Sgf_normalized_result[2]),
.S0(n4700), .Y(n4674) );
MX2X1TS U3046 ( .A(FPADDSUB_DMP[5]), .B(FPADDSUB_Sgf_normalized_result[7]),
.S0(n4700), .Y(n4704) );
AO22XLTS U3047 ( .A0(n4367), .A1(FPADDSUB_Add_Subt_result[4]), .B0(
FPADDSUB_DmP[19]), .B1(n4511), .Y(n4278) );
AO22XLTS U3048 ( .A0(n4367), .A1(FPADDSUB_Add_Subt_result[16]), .B0(
FPADDSUB_DmP[7]), .B1(n4511), .Y(n4242) );
AO21XLTS U3049 ( .A0(n2278), .A1(n2217), .B0(n2364), .Y(mult_x_121_n292) );
AO21XLTS U3050 ( .A0(n2277), .A1(n2208), .B0(n2356), .Y(mult_x_121_n306) );
AO21XLTS U3051 ( .A0(n2283), .A1(n2233), .B0(n2338), .Y(mult_x_159_n300) );
AO21XLTS U3052 ( .A0(n2281), .A1(n2213), .B0(n2145), .Y(mult_x_159_n314) );
NOR2X1TS U3053 ( .A(n3138), .B(n3136), .Y(n3125) );
NOR2X1TS U3054 ( .A(mult_x_159_n216), .B(mult_x_159_n224), .Y(n3136) );
AO21XLTS U3055 ( .A0(n2274), .A1(n2223), .B0(n2144), .Y(mult_x_121_n334) );
NOR2X1TS U3056 ( .A(n3362), .B(n3364), .Y(n3351) );
NOR2X1TS U3057 ( .A(mult_x_121_n214), .B(mult_x_121_n222), .Y(n3362) );
CMPR42X1TS U3058 ( .A(mult_x_121_n342), .B(mult_x_121_n318), .C(
mult_x_121_n330), .D(mult_x_121_n259), .ICI(mult_x_121_n260), .S(
mult_x_121_n257), .ICO(mult_x_121_n255), .CO(mult_x_121_n256) );
AO22XLTS U3059 ( .A0(n2249), .A1(FPADDSUB_Add_Subt_result[17]), .B0(
FPADDSUB_DmP[6]), .B1(n4511), .Y(n4214) );
NAND2X4TS U3060 ( .A(n4643), .B(n4650), .Y(n4646) );
AOI21X1TS U3061 ( .A0(n5204), .A1(n5161), .B0(n5160), .Y(n5180) );
INVX2TS U3062 ( .A(n5172), .Y(n5199) );
INVX2TS U3063 ( .A(n5209), .Y(n5255) );
CLKAND2X2TS U3064 ( .A(n4797), .B(FPADDSUB_Sgf_normalized_result[0]), .Y(
n4672) );
NOR2X2TS U3065 ( .A(FPADDSUB_Add_Subt_result[22]), .B(
FPADDSUB_Add_Subt_result[23]), .Y(n4863) );
NOR2X2TS U3066 ( .A(FPADDSUB_Add_Subt_result[25]), .B(
FPADDSUB_Add_Subt_result[24]), .Y(n4870) );
NAND3XLTS U3067 ( .A(n5827), .B(n5739), .C(FPADDSUB_Add_Subt_result[15]),
.Y(n4866) );
OR2X1TS U3068 ( .A(n4762), .B(n4761), .Y(n4793) );
NAND2BXLTS U3069 ( .AN(n3505), .B(n2178), .Y(n2668) );
MX2X1TS U3070 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U3071 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U3072 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
OR2X1TS U3073 ( .A(n4755), .B(n4754), .Y(n4906) );
OR2X1TS U3074 ( .A(n4746), .B(n4745), .Y(n4943) );
OR2X1TS U3075 ( .A(n4733), .B(n4732), .Y(n4973) );
CLKAND2X2TS U3076 ( .A(n2176), .B(n2200), .Y(n2716) );
NAND3XLTS U3077 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n5431) );
AOI31XLTS U3078 ( .A0(n5429), .A1(n5428), .A2(n5427), .B0(n5434), .Y(n5432)
);
CLKAND2X2TS U3079 ( .A(n4801), .B(FPADDSUB_Sgf_normalized_result[1]), .Y(
n4668) );
NAND4XLTS U3080 ( .A(n3796), .B(n3795), .C(n3794), .D(n3793), .Y(n3799) );
OR2X1TS U3081 ( .A(mult_x_121_n161), .B(n2714), .Y(n3315) );
BUFX3TS U3082 ( .A(n4491), .Y(n4501) );
XOR3X1TS U3083 ( .A(n2947), .B(n2946), .C(n2945), .Y(n2948) );
AO21XLTS U3084 ( .A0(n2186), .A1(n2215), .B0(n2204), .Y(n2945) );
OR2X1TS U3085 ( .A(n2949), .B(n2948), .Y(n2951) );
OR2X1TS U3086 ( .A(n2907), .B(n2906), .Y(n3195) );
NAND2BXLTS U3087 ( .AN(n3306), .B(n2188), .Y(n2905) );
AO21XLTS U3088 ( .A0(n2189), .A1(n2297), .B0(n3719), .Y(n3060) );
OR2X1TS U3089 ( .A(n3061), .B(n2180), .Y(n3062) );
OR2X1TS U3090 ( .A(n3063), .B(n3062), .Y(n3065) );
BUFX16TS U3091 ( .A(n3787), .Y(n3756) );
NAND2X2TS U3092 ( .A(mult_x_121_n182), .B(mult_x_121_n187), .Y(n3345) );
AOI21X2TS U3093 ( .A0(n3405), .A1(n2342), .B0(n2695), .Y(n3401) );
NOR2X1TS U3094 ( .A(mult_x_121_n262), .B(n2699), .Y(n3398) );
AOI2BB2XLTS U3095 ( .B0(FPADDSUB_sign_final_result), .B1(n3958), .A0N(
FPADDSUB_Sgf_normalized_result[0]), .A1N(
FPADDSUB_Sgf_normalized_result[1]), .Y(n3959) );
INVX2TS U3096 ( .A(n5481), .Y(n5478) );
NAND3XLTS U3097 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(n5712), .C(n5767),
.Y(n3957) );
MX2X1TS U3098 ( .A(n5046), .B(FPMULT_Add_result[23]), .S0(n5294), .Y(n1961)
);
AO22XLTS U3099 ( .A0(FPSENCOS_d_ff_Yn[27]), .A1(n5662), .B0(n5661), .B1(
FPSENCOS_d_ff2_Y[27]), .Y(n1422) );
NOR2XLTS U3100 ( .A(n4470), .B(n4328), .Y(n4330) );
MX2X1TS U3101 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n5322), .Y(n1959) );
OAI2BB2XLTS U3102 ( .B0(FPADDSUB_intDY[0]), .B1(n2836), .A0N(
FPADDSUB_intDX[1]), .A1N(n5844), .Y(n2838) );
OAI21XLTS U3103 ( .A0(FPADDSUB_intDX[1]), .A1(n5844), .B0(FPADDSUB_intDX[0]),
.Y(n2836) );
NAND2BXLTS U3104 ( .AN(FPADDSUB_intDX[2]), .B(FPADDSUB_intDY[2]), .Y(n2837)
);
NAND2BXLTS U3105 ( .AN(FPADDSUB_intDY[9]), .B(FPADDSUB_intDX[9]), .Y(n2852)
);
NAND3XLTS U3106 ( .A(n5842), .B(n2850), .C(FPADDSUB_intDX[8]), .Y(n2851) );
INVX2TS U3107 ( .A(n2145), .Y(n2230) );
NAND2X1TS U3108 ( .A(n3077), .B(n3076), .Y(n3580) );
XOR2X1TS U3109 ( .A(n2161), .B(FPMULT_Op_MX[20]), .Y(n3075) );
NAND2BXLTS U3110 ( .AN(n2241), .B(n2971), .Y(n3718) );
INVX2TS U3111 ( .A(n3621), .Y(n3614) );
NAND2X1TS U3112 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n3598) );
XOR2X1TS U3113 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .Y(n3585) );
INVX2TS U3114 ( .A(n2344), .Y(n2159) );
AOI21X2TS U3115 ( .A0(n2475), .A1(n2423), .B0(n2422), .Y(n2443) );
OAI21X1TS U3116 ( .A0(n2535), .A1(n2532), .B0(n2536), .Y(n2377) );
NOR2X1TS U3117 ( .A(n2533), .B(n2535), .Y(n2378) );
OR2X1TS U3118 ( .A(n2370), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]), .Y(n2373) );
NOR2X1TS U3119 ( .A(n2204), .B(n2143), .Y(n3305) );
NOR2X1TS U3120 ( .A(DP_OP_498J12_123_5135_n727), .B(n2324), .Y(n3263) );
NAND2BXLTS U3121 ( .AN(n3306), .B(n2195), .Y(n3254) );
NAND2X1TS U3122 ( .A(n2977), .B(n2976), .Y(n3071) );
XOR2X1TS U3123 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .Y(n2975) );
NOR2X1TS U3124 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n2989) );
NOR2X2TS U3125 ( .A(n2166), .B(FPMULT_Op_MY[9]), .Y(n3615) );
NOR2X1TS U3126 ( .A(n3613), .B(n3615), .Y(n2982) );
NOR2X2TS U3127 ( .A(n2167), .B(FPMULT_Op_MY[7]), .Y(n3604) );
NOR2X2TS U3128 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n3599) );
OAI22X1TS U3129 ( .A0(n3635), .A1(n2980), .B0(n3774), .B1(n3771), .Y(n3611)
);
CLKINVX3TS U3130 ( .A(n2136), .Y(n2288) );
NAND2BXLTS U3131 ( .AN(n2241), .B(n2288), .Y(n3704) );
NAND2X2TS U3132 ( .A(n3591), .B(n3740), .Y(n3741) );
NAND2X1TS U3133 ( .A(n2793), .B(n2960), .Y(n2772) );
NAND2X1TS U3134 ( .A(n2755), .B(n2766), .Y(n2756) );
INVX2TS U3135 ( .A(n2324), .Y(n2157) );
INVX4TS U3136 ( .A(n2142), .Y(n2201) );
INVX2TS U3137 ( .A(n2359), .Y(n2196) );
INVX2TS U3138 ( .A(n2127), .Y(n2168) );
NAND2X1TS U3139 ( .A(n2429), .B(n2428), .Y(n2497) );
NOR2X1TS U3140 ( .A(n2601), .B(n2600), .Y(n2605) );
OR2X1TS U3141 ( .A(n2609), .B(n2608), .Y(n2613) );
NOR2X1TS U3142 ( .A(n5220), .B(n5222), .Y(n2590) );
NOR2X2TS U3143 ( .A(n2376), .B(n2375), .Y(n2535) );
NAND2X1TS U3144 ( .A(n2376), .B(n2375), .Y(n2536) );
INVX2TS U3145 ( .A(n2501), .Y(n2531) );
AOI21X1TS U3146 ( .A0(n2531), .A1(n2503), .B0(n2502), .Y(n2553) );
NOR2X1TS U3147 ( .A(n2369), .B(n2368), .Y(n2513) );
NAND2X1TS U3148 ( .A(n2369), .B(n2368), .Y(n2514) );
NOR2X1TS U3149 ( .A(n4982), .B(n4989), .Y(n4713) );
XOR2X1TS U3150 ( .A(n4529), .B(n4581), .Y(n4531) );
AO22XLTS U3151 ( .A0(FPADDSUB_LZA_output[3]), .A1(n3812), .B0(n2165), .B1(
FPADDSUB_DmP[26]), .Y(n4529) );
MX2X1TS U3152 ( .A(FPADDSUB_DMP[26]), .B(FPADDSUB_exp_oper_result[3]), .S0(
n4797), .Y(n4530) );
CLKXOR2X2TS U3153 ( .A(n4518), .B(n4581), .Y(n4523) );
AO22XLTS U3154 ( .A0(FPADDSUB_LZA_output[1]), .A1(n3812), .B0(n2164), .B1(
FPADDSUB_DmP[24]), .Y(n4518) );
MX2X1TS U3155 ( .A(FPADDSUB_DMP[24]), .B(FPADDSUB_exp_oper_result[1]), .S0(
n4797), .Y(n4522) );
XOR2X1TS U3156 ( .A(n4519), .B(n4581), .Y(n4525) );
AO22XLTS U3157 ( .A0(FPADDSUB_LZA_output[2]), .A1(n3812), .B0(n2164), .B1(
FPADDSUB_DmP[25]), .Y(n4519) );
MX2X1TS U3158 ( .A(FPADDSUB_DMP[25]), .B(FPADDSUB_exp_oper_result[2]), .S0(
n4797), .Y(n4524) );
NOR2X1TS U3159 ( .A(n5006), .B(n5008), .Y(n4723) );
NOR2X1TS U3160 ( .A(n4934), .B(n4936), .Y(n4691) );
NAND2X1TS U3161 ( .A(n2265), .B(n3829), .Y(n4406) );
XOR2X1TS U3162 ( .A(n4581), .B(n4537), .Y(n4539) );
CLKAND2X2TS U3163 ( .A(n2165), .B(FPADDSUB_DmP[28]), .Y(n4537) );
MX2X1TS U3164 ( .A(FPADDSUB_DMP[28]), .B(FPADDSUB_exp_oper_result[5]), .S0(
n4797), .Y(n4538) );
XOR2X1TS U3165 ( .A(n4533), .B(n4581), .Y(n4535) );
AO22XLTS U3166 ( .A0(FPADDSUB_LZA_output[4]), .A1(n3812), .B0(n2165), .B1(
FPADDSUB_DmP[27]), .Y(n4533) );
MX2X1TS U3167 ( .A(FPADDSUB_DMP[27]), .B(FPADDSUB_exp_oper_result[4]), .S0(
n4797), .Y(n4534) );
XOR2X1TS U3168 ( .A(n4581), .B(n4540), .Y(n4542) );
CLKAND2X2TS U3169 ( .A(n2165), .B(FPADDSUB_DmP[29]), .Y(n4540) );
MX2X1TS U3170 ( .A(FPADDSUB_DMP[29]), .B(FPADDSUB_exp_oper_result[6]), .S0(
n4797), .Y(n4541) );
XOR2X1TS U3171 ( .A(n4581), .B(n4544), .Y(n4546) );
CLKAND2X2TS U3172 ( .A(n2165), .B(FPADDSUB_DmP[30]), .Y(n4544) );
MX2X1TS U3173 ( .A(FPADDSUB_DMP[30]), .B(FPADDSUB_exp_oper_result[7]), .S0(
n4797), .Y(n4545) );
OAI21XLTS U3174 ( .A0(FPADDSUB_intDX[21]), .A1(n5782), .B0(
FPADDSUB_intDX[20]), .Y(n2868) );
NAND3BX1TS U3175 ( .AN(n2869), .B(n2867), .C(n2866), .Y(n2887) );
AO21XLTS U3176 ( .A0(n3290), .A1(n2211), .B0(n3222), .Y(mult_x_159_n328) );
OAI22X1TS U3177 ( .A0(n2185), .A1(n3208), .B0(n2216), .B1(n3207), .Y(
mult_x_159_n296) );
CMPR42X1TS U3178 ( .A(mult_x_159_n322), .B(mult_x_159_n334), .C(
mult_x_159_n273), .D(mult_x_159_n298), .ICI(mult_x_159_n239), .S(
mult_x_159_n236), .ICO(mult_x_159_n234), .CO(mult_x_159_n235) );
NAND2BXLTS U3179 ( .AN(n3306), .B(n2228), .Y(n2895) );
NAND2BXLTS U3180 ( .AN(n3306), .B(n2227), .Y(n2901) );
NAND2X1TS U3181 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n2988) );
OAI21X2TS U3182 ( .A0(n3615), .A1(n3621), .B0(n3616), .Y(n2987) );
CLKAND2X2TS U3183 ( .A(n2982), .B(n2983), .Y(n2992) );
AO21XLTS U3184 ( .A0(n2118), .A1(n3734), .B0(n3655), .Y(
DP_OP_498J12_123_5135_n436) );
BUFX3TS U3185 ( .A(n3590), .Y(n2294) );
XNOR2X2TS U3186 ( .A(n2157), .B(FPMULT_Op_MX[13]), .Y(n2736) );
NAND2BXLTS U3187 ( .AN(n3505), .B(n2237), .Y(n3506) );
NAND2BXLTS U3188 ( .AN(n3505), .B(n2199), .Y(n3493) );
NAND2BXLTS U3189 ( .AN(n3505), .B(n2197), .Y(n2689) );
NOR2X1TS U3190 ( .A(n5308), .B(n5296), .Y(n5268) );
NOR2X1TS U3191 ( .A(n5246), .B(n5243), .Y(n5216) );
NAND2X1TS U3192 ( .A(n5711), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]), .Y(n2518) );
MX2X1TS U3193 ( .A(FPADDSUB_DMP[22]), .B(FPADDSUB_Sgf_normalized_result[24]),
.S0(n4797), .Y(n4798) );
NAND2X1TS U3194 ( .A(n4863), .B(n4870), .Y(n4851) );
AO22XLTS U3195 ( .A0(n4367), .A1(FPADDSUB_Add_Subt_result[8]), .B0(
FPADDSUB_DmP[15]), .B1(n4254), .Y(n4253) );
MX2X1TS U3196 ( .A(FPADDSUB_DMP[21]), .B(FPADDSUB_Sgf_normalized_result[23]),
.S0(FPADDSUB_FSM_selector_A), .Y(n4761) );
MX2X1TS U3197 ( .A(FPADDSUB_DMP[18]), .B(FPADDSUB_Sgf_normalized_result[20]),
.S0(n4753), .Y(n4749) );
NOR2X1TS U3198 ( .A(n4963), .B(n4964), .Y(n4978) );
NOR2X1TS U3199 ( .A(n4531), .B(n4530), .Y(n4560) );
NAND2X1TS U3200 ( .A(n4531), .B(n4530), .Y(n4561) );
NOR2X2TS U3201 ( .A(n4525), .B(n4524), .Y(n4565) );
NOR2X2TS U3202 ( .A(n4523), .B(n4522), .Y(n4572) );
NAND2X2TS U3203 ( .A(n4523), .B(n4522), .Y(n4573) );
NAND2X1TS U3204 ( .A(n4525), .B(n4524), .Y(n4566) );
MX2X1TS U3205 ( .A(FPADDSUB_DMP[19]), .B(FPADDSUB_Sgf_normalized_result[21]),
.S0(n4753), .Y(n4754) );
BUFX3TS U3206 ( .A(FPADDSUB_FSM_selector_A), .Y(n4795) );
MX2X1TS U3207 ( .A(FPADDSUB_DMP[20]), .B(FPADDSUB_Sgf_normalized_result[22]),
.S0(n4800), .Y(n4758) );
NAND2X1TS U3208 ( .A(n4539), .B(n4538), .Y(n4553) );
NOR2X1TS U3209 ( .A(n4539), .B(n4538), .Y(n4552) );
NAND2X1TS U3210 ( .A(n4535), .B(n4534), .Y(n4557) );
NAND2X1TS U3211 ( .A(n4542), .B(n4541), .Y(n4549) );
NAND2X1TS U3212 ( .A(n4546), .B(n4545), .Y(n4578) );
CMPR42X1TS U3213 ( .A(mult_x_159_n293), .B(mult_x_159_n199), .C(
mult_x_159_n200), .D(mult_x_159_n193), .ICI(mult_x_159_n196), .S(
mult_x_159_n190), .ICO(mult_x_159_n188), .CO(mult_x_159_n189) );
INVX2TS U3214 ( .A(n2971), .Y(n3719) );
OAI21X1TS U3215 ( .A0(n3040), .A1(n3518), .B0(n3041), .Y(n2816) );
NAND2X1TS U3216 ( .A(n3789), .B(n3050), .Y(n3053) );
AO21XLTS U3217 ( .A0(n2193), .A1(n2296), .B0(n3727), .Y(
DP_OP_498J12_123_5135_n407) );
ADDHX1TS U3218 ( .A(n2775), .B(n2774), .CO(n2776), .S(n2760) );
XOR2X1TS U3219 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[12]), .Y(n2728) );
CMPR42X1TS U3220 ( .A(mult_x_121_n295), .B(mult_x_121_n183), .C(
mult_x_121_n177), .D(mult_x_121_n184), .ICI(mult_x_121_n180), .S(
mult_x_121_n175), .ICO(mult_x_121_n173), .CO(mult_x_121_n174) );
NAND2BXLTS U3221 ( .AN(n3505), .B(n2225), .Y(n2674) );
AO22XLTS U3222 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[19]), .B0(
FPADDSUB_DmP[4]), .B1(n4511), .Y(n4209) );
NOR3BX2TS U3223 ( .AN(n3086), .B(n3085), .C(FPADDSUB_Add_Subt_result[14]),
.Y(n3082) );
INVX2TS U3224 ( .A(n5162), .Y(n5164) );
NOR2X1TS U3225 ( .A(n5172), .B(n5045), .Y(n5158) );
AOI31X1TS U3226 ( .A0(n5506), .A1(n5508), .A2(n5768), .B0(n4062), .Y(n5519)
);
NOR2XLTS U3227 ( .A(FPSENCOS_cont_iter_out[2]), .B(n4356), .Y(n4062) );
MX2X1TS U3228 ( .A(FPADDSUB_DMP[23]), .B(FPADDSUB_exp_oper_result[0]), .S0(
n4797), .Y(n4571) );
XOR2X1TS U3229 ( .A(n4521), .B(n4581), .Y(n4570) );
AO21XLTS U3230 ( .A0(FPADDSUB_DmP[23]), .A1(n5770), .B0(n4520), .Y(n4521) );
MX2X1TS U3231 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U3232 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
NAND2BXLTS U3233 ( .AN(n3898), .B(n4437), .Y(n4329) );
OR2X4TS U3234 ( .A(n4667), .B(n4795), .Y(n4848) );
NAND3BXLTS U3235 ( .AN(n4222), .B(n5034), .C(FPMULT_P_Sgf[47]), .Y(n3937) );
NAND4XLTS U3236 ( .A(n3877), .B(n3876), .C(n3875), .D(n3874), .Y(n4505) );
NOR2X2TS U3237 ( .A(DP_OP_498J12_123_5135_n259), .B(
DP_OP_498J12_123_5135_n261), .Y(n3757) );
OAI21X1TS U3238 ( .A0(n3753), .A1(n3752), .B0(n3751), .Y(n3754) );
NOR2X1TS U3239 ( .A(n3750), .B(n3752), .Y(n3755) );
NAND2X1TS U3240 ( .A(n2676), .B(n2675), .Y(n3411) );
AO22XLTS U3241 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[21]), .B0(
FPADDSUB_DmP[2]), .B1(n4511), .Y(n4213) );
INVX2TS U3242 ( .A(FPSENCOS_d_ff2_X[9]), .Y(n5562) );
INVX2TS U3243 ( .A(FPSENCOS_d_ff_Yn[9]), .Y(n5633) );
INVX2TS U3244 ( .A(FPSENCOS_d_ff2_X[11]), .Y(n5560) );
INVX2TS U3245 ( .A(FPSENCOS_d_ff_Yn[7]), .Y(n5631) );
INVX2TS U3246 ( .A(FPSENCOS_d_ff_Yn[14]), .Y(n5639) );
INVX2TS U3247 ( .A(FPSENCOS_d_ff2_X[4]), .Y(n5569) );
INVX2TS U3248 ( .A(FPSENCOS_d_ff_Yn[4]), .Y(n5625) );
INVX2TS U3249 ( .A(FPSENCOS_d_ff_Yn[17]), .Y(n5642) );
INVX2TS U3250 ( .A(FPSENCOS_d_ff_Yn[5]), .Y(n5627) );
INVX2TS U3251 ( .A(FPSENCOS_d_ff2_X[13]), .Y(n5558) );
INVX2TS U3252 ( .A(FPSENCOS_d_ff_Yn[20]), .Y(n5646) );
INVX2TS U3253 ( .A(FPSENCOS_d_ff_Yn[1]), .Y(n5621) );
INVX2TS U3254 ( .A(FPSENCOS_d_ff2_X[8]), .Y(n5563) );
INVX2TS U3255 ( .A(FPSENCOS_d_ff_Yn[15]), .Y(n5640) );
INVX2TS U3256 ( .A(FPSENCOS_d_ff2_X[18]), .Y(n5551) );
INVX2TS U3257 ( .A(FPSENCOS_d_ff_Yn[18]), .Y(n5644) );
INVX2TS U3258 ( .A(FPSENCOS_d_ff2_X[21]), .Y(n4149) );
INVX2TS U3259 ( .A(FPSENCOS_d_ff_Yn[21]), .Y(n5648) );
INVX2TS U3260 ( .A(FPSENCOS_d_ff_Yn[2]), .Y(n5622) );
INVX2TS U3261 ( .A(FPSENCOS_d_ff_Yn[19]), .Y(n5645) );
INVX2TS U3262 ( .A(FPSENCOS_d_ff_Yn[3]), .Y(n5623) );
INVX2TS U3263 ( .A(FPSENCOS_d_ff2_X[22]), .Y(n4100) );
INVX2TS U3264 ( .A(n5592), .Y(n5595) );
INVX2TS U3265 ( .A(FPSENCOS_d_ff_Yn[22]), .Y(n5649) );
INVX2TS U3266 ( .A(FPSENCOS_d_ff_Yn[28]), .Y(n5656) );
INVX2TS U3267 ( .A(FPSENCOS_d_ff_Yn[31]), .Y(n5677) );
NOR2XLTS U3268 ( .A(n3025), .B(FPADDSUB_Add_Subt_result[25]), .Y(n3026) );
AOI2BB1XLTS U3269 ( .A0N(n3024), .A1N(FPADDSUB_Add_Subt_result[23]), .B0(
FPADDSUB_Add_Subt_result[24]), .Y(n3025) );
NAND2BXLTS U3270 ( .AN(FPADDSUB_Add_Subt_result[1]), .B(
FPADDSUB_Add_Subt_result[0]), .Y(n3022) );
INVX2TS U3271 ( .A(n4646), .Y(n3028) );
NAND2X1TS U3272 ( .A(n4001), .B(n3841), .Y(n4474) );
INVX2TS U3273 ( .A(FPSENCOS_d_ff2_X[0]), .Y(n5575) );
CLKINVX3TS U3274 ( .A(rst), .Y(n3895) );
INVX2TS U3275 ( .A(n5036), .Y(n5324) );
INVX2TS U3276 ( .A(n5036), .Y(n5473) );
INVX2TS U3277 ( .A(n5036), .Y(n5038) );
OAI21XLTS U3278 ( .A0(n4272), .A1(n5616), .B0(n4271), .Y(op_result[1]) );
MX2X1TS U3279 ( .A(Data_1[7]), .B(n2160), .S0(n5035), .Y(n2029) );
MX2X1TS U3280 ( .A(Data_1[2]), .B(n2268), .S0(n5473), .Y(n2024) );
MX2X1TS U3281 ( .A(Data_2[21]), .B(FPMULT_Op_MY[21]), .S0(n5040), .Y(n2011)
);
MX2X1TS U3282 ( .A(Data_2[15]), .B(FPMULT_Op_MY[15]), .S0(n5323), .Y(n2005)
);
MX2X1TS U3283 ( .A(Data_2[19]), .B(n2122), .S0(n5040), .Y(n2009) );
MX2X1TS U3284 ( .A(Data_1[13]), .B(FPMULT_Op_MX[13]), .S0(n5473), .Y(n2035)
);
MX2X1TS U3285 ( .A(Data_2[1]), .B(FPMULT_Op_MY[1]), .S0(n5040), .Y(n1991) );
MX2X1TS U3286 ( .A(Data_1[1]), .B(n2124), .S0(n5037), .Y(n2023) );
MX2X1TS U3287 ( .A(Data_1[9]), .B(n2162), .S0(n5035), .Y(n2031) );
MX2X1TS U3288 ( .A(Data_1[4]), .B(n2158), .S0(n5035), .Y(n2026) );
MX2X1TS U3289 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n5037), .Y(n2041)
);
MX2X1TS U3290 ( .A(Data_2[17]), .B(n2170), .S0(n5323), .Y(n2007) );
MX2X1TS U3291 ( .A(Data_1[12]), .B(FPMULT_Op_MX[12]), .S0(n5324), .Y(n2034)
);
MX2X1TS U3292 ( .A(Data_1[6]), .B(n5462), .S0(n5035), .Y(n2028) );
MX2X1TS U3293 ( .A(Data_1[15]), .B(FPMULT_Op_MX[15]), .S0(n5037), .Y(n2037)
);
MX2X1TS U3294 ( .A(FPMULT_P_Sgf[24]), .B(n5301), .S0(n5413), .Y(n1917) );
MX2X1TS U3295 ( .A(FPMULT_P_Sgf[25]), .B(n5290), .S0(n5413), .Y(n1918) );
MX2X1TS U3296 ( .A(FPMULT_P_Sgf[26]), .B(n5280), .S0(n5279), .Y(n1919) );
MX2X1TS U3297 ( .A(FPMULT_P_Sgf[27]), .B(n5261), .S0(n5279), .Y(n1920) );
MX2X1TS U3298 ( .A(FPMULT_P_Sgf[28]), .B(n5251), .S0(n5279), .Y(n1921) );
MX2X1TS U3299 ( .A(FPMULT_P_Sgf[29]), .B(n5237), .S0(n5279), .Y(n1922) );
MX2X1TS U3300 ( .A(FPMULT_P_Sgf[30]), .B(n5227), .S0(n5279), .Y(n1923) );
MX2X1TS U3301 ( .A(FPMULT_P_Sgf[31]), .B(n5205), .S0(n5279), .Y(n1924) );
MX2X1TS U3302 ( .A(FPMULT_P_Sgf[32]), .B(n5195), .S0(n5279), .Y(n1925) );
MX2X1TS U3303 ( .A(FPMULT_P_Sgf[33]), .B(n5181), .S0(n5279), .Y(n1926) );
MX2X1TS U3304 ( .A(FPMULT_P_Sgf[35]), .B(n5154), .S0(n5279), .Y(n1928) );
MX2X1TS U3305 ( .A(FPMULT_P_Sgf[36]), .B(n5143), .S0(n5142), .Y(n1929) );
MX2X1TS U3306 ( .A(FPMULT_P_Sgf[37]), .B(n5130), .S0(n5142), .Y(n1930) );
MX2X1TS U3307 ( .A(FPMULT_P_Sgf[38]), .B(n5119), .S0(n5142), .Y(n1931) );
MX2X1TS U3308 ( .A(FPMULT_P_Sgf[39]), .B(n5105), .S0(n5142), .Y(n1932) );
MX2X1TS U3309 ( .A(FPMULT_P_Sgf[40]), .B(n5093), .S0(n5142), .Y(n1933) );
MX2X1TS U3310 ( .A(FPMULT_P_Sgf[41]), .B(n5084), .S0(n5142), .Y(n1934) );
MX2X1TS U3311 ( .A(FPMULT_P_Sgf[42]), .B(n5076), .S0(n5142), .Y(n1935) );
MX2X1TS U3312 ( .A(FPMULT_P_Sgf[43]), .B(n5068), .S0(n5142), .Y(n1936) );
MX2X1TS U3313 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n5038), .Y(n2014)
);
MX2X1TS U3314 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n5324), .Y(n2016)
);
MX2X1TS U3315 ( .A(n5338), .B(FPADDSUB_exp_oper_result[7]), .S0(n2306), .Y(
n1687) );
MX2X1TS U3316 ( .A(n5336), .B(FPADDSUB_exp_oper_result[5]), .S0(n2306), .Y(
n1693) );
MX2X1TS U3317 ( .A(n5337), .B(FPADDSUB_exp_oper_result[6]), .S0(n2306), .Y(
n1694) );
MX2X1TS U3318 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n5322), .Y(n1952) );
MX2X1TS U3319 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n5322), .Y(n1954) );
MX2X1TS U3320 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n5322), .Y(n1957) );
MX2X1TS U3321 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n5038), .Y(n2015)
);
MX2X1TS U3322 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n5473), .Y(n2019)
);
MX2X1TS U3323 ( .A(n5159), .B(FPMULT_Add_result[11]), .S0(n5315), .Y(n1973)
);
MX2X1TS U3324 ( .A(n5148), .B(FPMULT_Add_result[12]), .S0(n5315), .Y(n1972)
);
MX2X1TS U3325 ( .A(n5135), .B(FPMULT_Add_result[13]), .S0(n5089), .Y(n1971)
);
MX2X1TS U3326 ( .A(n5124), .B(FPMULT_Add_result[14]), .S0(n5315), .Y(n1970)
);
MX2X1TS U3327 ( .A(n5110), .B(FPMULT_Add_result[15]), .S0(n5315), .Y(n1969)
);
MX2X1TS U3328 ( .A(n5099), .B(FPMULT_Add_result[16]), .S0(n5089), .Y(n1968)
);
MX2X1TS U3329 ( .A(n5090), .B(FPMULT_Add_result[17]), .S0(n5315), .Y(n1967)
);
MX2X1TS U3330 ( .A(n5081), .B(FPMULT_Add_result[18]), .S0(n5315), .Y(n1966)
);
MX2X1TS U3331 ( .A(n5073), .B(FPMULT_Add_result[19]), .S0(n5089), .Y(n1965)
);
MX2X1TS U3332 ( .A(n5065), .B(FPMULT_Add_result[20]), .S0(n5315), .Y(n1964)
);
MX2X1TS U3333 ( .A(n5059), .B(FPMULT_Add_result[21]), .S0(n5089), .Y(n1963)
);
MX2X1TS U3334 ( .A(n5051), .B(FPMULT_Add_result[22]), .S0(n5315), .Y(n1962)
);
MX2X1TS U3335 ( .A(n5175), .B(FPMULT_Add_result[10]), .S0(n5089), .Y(n1974)
);
MX2X1TS U3336 ( .A(n5187), .B(FPMULT_Add_result[9]), .S0(n5315), .Y(n1975)
);
MX2X1TS U3337 ( .A(n5200), .B(FPMULT_Add_result[8]), .S0(n5315), .Y(n1976)
);
MX2X1TS U3338 ( .A(n5212), .B(FPMULT_Add_result[7]), .S0(n5294), .Y(n1977)
);
MX2X1TS U3339 ( .A(n5232), .B(FPMULT_Add_result[6]), .S0(n5294), .Y(n1978)
);
MX2X1TS U3340 ( .A(n5242), .B(FPMULT_Add_result[5]), .S0(n5294), .Y(n1979)
);
MX2X1TS U3341 ( .A(n5256), .B(FPMULT_Add_result[4]), .S0(n5294), .Y(n1980)
);
MX2X1TS U3342 ( .A(n5267), .B(FPMULT_Add_result[3]), .S0(n5294), .Y(n1981)
);
INVX2TS U3343 ( .A(n5284), .Y(n5265) );
MX2X1TS U3344 ( .A(n5285), .B(FPMULT_Add_result[2]), .S0(n5089), .Y(n1982)
);
MX2X1TS U3345 ( .A(n5295), .B(FPMULT_Add_result[1]), .S0(n5089), .Y(n1983)
);
MX2X1TS U3346 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n5323), .Y(n2050)
);
MX2X1TS U3347 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n5038), .Y(n2045)
);
MX2X1TS U3348 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n5323), .Y(n2052)
);
MX2X1TS U3349 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n5473), .Y(n2048)
);
MX2X1TS U3350 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n5324), .Y(n2047)
);
MX2X1TS U3351 ( .A(n5334), .B(FPADDSUB_exp_oper_result[3]), .S0(n4878), .Y(
n1691) );
MX2X1TS U3352 ( .A(FPSENCOS_d_ff2_Z[31]), .B(FPSENCOS_d_ff3_sign_out), .S0(
n5532), .Y(n1474) );
MX2X1TS U3353 ( .A(FPMULT_P_Sgf[4]), .B(FPMULT_Sgf_operation_Result[4]),
.S0(n5410), .Y(n1897) );
MX2X1TS U3354 ( .A(FPMULT_P_Sgf[16]), .B(n5364), .S0(n5410), .Y(n1909) );
MX2X1TS U3355 ( .A(FPMULT_P_Sgf[5]), .B(FPMULT_Sgf_operation_Result[5]),
.S0(n5410), .Y(n1898) );
MX2X1TS U3356 ( .A(FPMULT_P_Sgf[17]), .B(n5353), .S0(n5413), .Y(n1910) );
MX2X1TS U3357 ( .A(FPMULT_P_Sgf[3]), .B(FPMULT_Sgf_operation_Result[3]),
.S0(n5410), .Y(n1896) );
MX2X1TS U3358 ( .A(FPMULT_P_Sgf[15]), .B(n5357), .S0(n5413), .Y(n1908) );
MX2X1TS U3359 ( .A(FPMULT_P_Sgf[11]), .B(FPMULT_Sgf_operation_Result[11]),
.S0(n5413), .Y(n1904) );
MX2X1TS U3360 ( .A(FPMULT_P_Sgf[12]), .B(n5411), .S0(n5410), .Y(n1905) );
MX2X1TS U3361 ( .A(FPMULT_P_Sgf[21]), .B(n5392), .S0(n5410), .Y(n1914) );
AO22XLTS U3362 ( .A0(n5036), .A1(Data_2[31]), .B0(n5473), .B1(
FPMULT_Op_MY[31]), .Y(n1988) );
MX2X1TS U3363 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_Sgf_operation_Result[2]),
.S0(n5412), .Y(n1895) );
MX2X1TS U3364 ( .A(FPMULT_P_Sgf[6]), .B(FPMULT_Sgf_operation_Result[6]),
.S0(n5412), .Y(n1899) );
MX2X1TS U3365 ( .A(FPMULT_P_Sgf[10]), .B(FPMULT_Sgf_operation_Result[10]),
.S0(n5412), .Y(n1903) );
MX2X1TS U3366 ( .A(FPMULT_P_Sgf[18]), .B(n5382), .S0(n5410), .Y(n1911) );
MX2X1TS U3367 ( .A(FPMULT_P_Sgf[0]), .B(n5402), .S0(n5412), .Y(n1893) );
MX2X1TS U3368 ( .A(FPMULT_P_Sgf[7]), .B(FPMULT_Sgf_operation_Result[7]),
.S0(n5412), .Y(n1900) );
MX2X1TS U3369 ( .A(FPMULT_P_Sgf[14]), .B(n5406), .S0(n5412), .Y(n1907) );
MX2X1TS U3370 ( .A(FPMULT_P_Sgf[19]), .B(n5386), .S0(n5410), .Y(n1912) );
MX2X1TS U3371 ( .A(FPADDSUB_Add_Subt_result[5]), .B(n4932), .S0(n4976), .Y(
n1665) );
AO22XLTS U3372 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n5662), .B0(
FPSENCOS_d_ff2_X[31]), .B1(n5658), .Y(n1839) );
MX2X1TS U3373 ( .A(FPMULT_P_Sgf[44]), .B(n3810), .S0(n5142), .Y(n1937) );
MX2X1TS U3374 ( .A(n5332), .B(FPADDSUB_exp_oper_result[2]), .S0(n4878), .Y(
n1690) );
MX2X1TS U3375 ( .A(n5330), .B(FPADDSUB_exp_oper_result[1]), .S0(n4878), .Y(
n1689) );
MX2X1TS U3376 ( .A(n5335), .B(FPADDSUB_exp_oper_result[4]), .S0(n4878), .Y(
n1692) );
MX2X1TS U3377 ( .A(n5331), .B(FPADDSUB_exp_oper_result[0]), .S0(n4878), .Y(
n1688) );
MX2X1TS U3378 ( .A(FPADDSUB_Add_Subt_result[0]), .B(n4790), .S0(n4909), .Y(
n1660) );
MX2X1TS U3379 ( .A(FPADDSUB_Add_Subt_result[24]), .B(n4886), .S0(n4909), .Y(
n1684) );
OAI31X1TS U3380 ( .A0(n2183), .A1(n5536), .A2(n4066), .B0(n4063), .Y(n1801)
);
AOI2BB2XLTS U3381 ( .B0(FPSENCOS_d_ff3_LUT_out[2]), .B1(n5532), .A0N(n5624),
.A1N(n5519), .Y(n4063) );
MX2X1TS U3382 ( .A(FPMULT_P_Sgf[13]), .B(n5349), .S0(n5413), .Y(n1906) );
MX2X1TS U3383 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_Sgf_operation_Result[1]),
.S0(n5413), .Y(n1894) );
MX2X1TS U3384 ( .A(FPADDSUB_Add_Subt_result[9]), .B(n4984), .S0(n4919), .Y(
n1669) );
MX2X1TS U3385 ( .A(FPMULT_P_Sgf[22]), .B(n5401), .S0(n5410), .Y(n1915) );
MX2X1TS U3386 ( .A(FPMULT_P_Sgf[20]), .B(n5373), .S0(n5410), .Y(n1913) );
MX2X1TS U3387 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_Sgf_operation_Result[9]),
.S0(n5412), .Y(n1902) );
MX2X1TS U3388 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_Sgf_operation_Result[8]),
.S0(n5412), .Y(n1901) );
AO22XLTS U3389 ( .A0(n5036), .A1(Data_1[31]), .B0(n5473), .B1(
FPMULT_Op_MX[31]), .Y(n2021) );
OAI211XLTS U3390 ( .A0(n4874), .A1(n4873), .B0(n4872), .C0(n4871), .Y(n4877)
);
INVX2TS U3391 ( .A(n4863), .Y(n4869) );
MX2X1TS U3392 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n5324), .Y(n2018)
);
MX2X1TS U3393 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n5473), .Y(n2020)
);
MX2X1TS U3394 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n5324), .Y(n2013)
);
MX2X1TS U3395 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n5322), .Y(n1958) );
MX2X1TS U3396 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n5322), .Y(n1956) );
MX2X1TS U3397 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n5322), .Y(n1955) );
MX2X1TS U3398 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n5322), .Y(n1953) );
MX2X1TS U3399 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n5322), .Y(n1951) );
MX2X1TS U3400 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n5038), .Y(n2017)
);
MX2X1TS U3401 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n5038), .Y(n2046)
);
AOI31XLTS U3402 ( .A0(n4654), .A1(n4876), .A2(n4653), .B0(n4652), .Y(n1654)
);
MX2X1TS U3403 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n5323), .Y(n2051)
);
MX2X1TS U3404 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n5323), .Y(n2049)
);
AO21XLTS U3405 ( .A0(FPADDSUB_Sgf_normalized_result[4]), .A1(n4462), .B0(
n4461), .Y(n4424) );
AO21XLTS U3406 ( .A0(FPADDSUB_Sgf_normalized_result[7]), .A1(n4462), .B0(
n4461), .Y(n4415) );
AO21XLTS U3407 ( .A0(FPADDSUB_Sgf_normalized_result[6]), .A1(n4462), .B0(
n4461), .Y(n4408) );
AO22XLTS U3408 ( .A0(n4840), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(
FPADDSUB_Sgf_normalized_result[10]), .B1(n4452), .Y(n3880) );
AO22XLTS U3409 ( .A0(n4840), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
FPADDSUB_Sgf_normalized_result[11]), .B1(n4452), .Y(n3884) );
AO21XLTS U3410 ( .A0(FPADDSUB_Sgf_normalized_result[2]), .A1(n4462), .B0(
n4461), .Y(n4427) );
MX2X1TS U3411 ( .A(Data_2[20]), .B(n2307), .S0(n5040), .Y(n2010) );
NAND3XLTS U3412 ( .A(n3945), .B(FPSENCOS_sel_mux_1_reg), .C(n5988), .Y(n3944) );
NAND3XLTS U3413 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(n4664), .C(n5765),
.Y(n3945) );
MX2X1TS U3414 ( .A(FPADDSUB_Add_Subt_result[8]), .B(n4969), .S0(n4976), .Y(
n1668) );
MX2X1TS U3415 ( .A(FPADDSUB_Add_Subt_result[15]), .B(n4998), .S0(n4919), .Y(
n1675) );
MX2X1TS U3416 ( .A(FPADDSUB_Add_Subt_result[12]), .B(n5032), .S0(n4919), .Y(
n1672) );
MX2X1TS U3417 ( .A(FPADDSUB_Add_Subt_result[23]), .B(n4764), .S0(n4909), .Y(
n1683) );
MX2X1TS U3418 ( .A(FPADDSUB_Add_Subt_result[20]), .B(n4926), .S0(n4976), .Y(
n1680) );
MX2X1TS U3419 ( .A(FPADDSUB_Add_Subt_result[14]), .B(n5013), .S0(n4919), .Y(
n1674) );
MX2X1TS U3420 ( .A(FPADDSUB_Add_Subt_result[13]), .B(n5022), .S0(n4919), .Y(
n1673) );
MX2X1TS U3421 ( .A(FPADDSUB_Add_Subt_result[4]), .B(n4920), .S0(n4976), .Y(
n1664) );
MX2X1TS U3422 ( .A(FPADDSUB_Add_Subt_result[1]), .B(n4880), .S0(n4909), .Y(
n1661) );
MX2X1TS U3423 ( .A(FPADDSUB_Add_Subt_result[6]), .B(n4941), .S0(n4976), .Y(
n1666) );
MX2X1TS U3424 ( .A(FPADDSUB_Add_Subt_result[10]), .B(n4994), .S0(n4919), .Y(
n1670) );
MX2X1TS U3425 ( .A(Data_1[22]), .B(FPMULT_Op_MX[22]), .S0(n5037), .Y(n2044)
);
MX2X1TS U3426 ( .A(Data_1[17]), .B(FPMULT_Op_MX[17]), .S0(n5037), .Y(n2039)
);
OR2X1TS U3427 ( .A(n4439), .B(n4801), .Y(n1696) );
OAI21XLTS U3428 ( .A0(n3122), .A1(n3118), .B0(n3119), .Y(n3117) );
XOR2XLTS U3429 ( .A(n3188), .B(n3187), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4) );
CLKAND2X2TS U3430 ( .A(n3467), .B(n3466), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1) );
MX2X1TS U3431 ( .A(Data_1[0]), .B(FPMULT_Op_MX[0]), .S0(n5037), .Y(n2022) );
MX2X1TS U3432 ( .A(n5316), .B(FPMULT_FSM_add_overflow_flag), .S0(n5089), .Y(
n1960) );
MX2X1TS U3433 ( .A(FPADDSUB_Add_Subt_result[21]), .B(n4910), .S0(n4909), .Y(
n1681) );
AO21XLTS U3434 ( .A0(n4832), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n4831),
.Y(n1647) );
AOI31XLTS U3435 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(
FPMULT_FS_Module_state_reg[0]), .A2(n5854), .B0(n2272), .Y(n4223) );
MX2X1TS U3436 ( .A(FPADDSUB_Add_Subt_result[19]), .B(n4946), .S0(n4976), .Y(
n1679) );
AO22XLTS U3437 ( .A0(n5472), .A1(n5471), .B0(n5470), .B1(FPMULT_zero_flag),
.Y(n1989) );
MX2X1TS U3438 ( .A(Data_2[9]), .B(n2195), .S0(n5473), .Y(n1999) );
MX2X1TS U3439 ( .A(Data_2[11]), .B(FPMULT_Op_MY[11]), .S0(n5324), .Y(n2001)
);
MX2X1TS U3440 ( .A(Data_2[18]), .B(FPMULT_Op_MY[18]), .S0(n5040), .Y(n2008)
);
MX2X1TS U3441 ( .A(Data_2[22]), .B(n5039), .S0(n5040), .Y(n2012) );
AOI211XLTS U3442 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n3937), .B0(n5098),
.C0(n5472), .Y(n6005) );
AO21XLTS U3443 ( .A0(FPADDSUB_Sgf_normalized_result[5]), .A1(n4462), .B0(
n4461), .Y(n4412) );
MX2X1TS U3444 ( .A(Data_2[8]), .B(FPMULT_Op_MY[8]), .S0(n5324), .Y(n1998) );
MX2X1TS U3445 ( .A(FPADDSUB_Add_Subt_result[22]), .B(n4904), .S0(n4909), .Y(
n1682) );
MX2X1TS U3446 ( .A(Data_2[10]), .B(FPMULT_Op_MY[10]), .S0(n5038), .Y(n2000)
);
AO21XLTS U3447 ( .A0(FPADDSUB_Sgf_normalized_result[3]), .A1(n4462), .B0(
n4461), .Y(n4463) );
MX2X1TS U3448 ( .A(FPADDSUB_Add_Subt_result[16]), .B(n4977), .S0(n4976), .Y(
n1676) );
MX2X1TS U3449 ( .A(FPADDSUB_Add_Subt_result[17]), .B(n4961), .S0(n4976), .Y(
n1677) );
OAI21XLTS U3450 ( .A0(n4326), .A1(n4513), .B0(n4254), .Y(n1685) );
MX2X1TS U3451 ( .A(FPADDSUB_Add_Subt_result[18]), .B(n4952), .S0(n4976), .Y(
n1678) );
OR2X1TS U3452 ( .A(n2718), .B(n2717), .Y(n2720) );
NOR3XLTS U3453 ( .A(n5529), .B(n4073), .C(n4071), .Y(n1834) );
NAND4XLTS U3454 ( .A(n6009), .B(n6008), .C(n6007), .D(n5433), .Y(n5435) );
OAI32X1TS U3455 ( .A0(n4661), .A1(FPSENCOS_cordic_FSM_state_reg[2]), .A2(
n4660), .B0(n5717), .B1(n4661), .Y(n4666) );
AO21XLTS U3456 ( .A0(n4832), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n4823),
.Y(n1649) );
AO21XLTS U3457 ( .A0(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(n4832), .B0(n4814), .Y(n1652) );
AO21XLTS U3458 ( .A0(n4418), .A1(n3817), .B0(n3828), .Y(n1653) );
AO21XLTS U3459 ( .A0(n4455), .A1(n3817), .B0(n3834), .Y(n1641) );
MX2X1TS U3460 ( .A(FPADDSUB_Add_Subt_result[3]), .B(n4898), .S0(n4909), .Y(
n1663) );
AO21XLTS U3461 ( .A0(n4832), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(n4826),
.Y(n1648) );
MX2X1TS U3462 ( .A(FPADDSUB_Add_Subt_result[11]), .B(n5017), .S0(n4919), .Y(
n1671) );
MX2X1TS U3463 ( .A(FPADDSUB_Add_Subt_result[2]), .B(n4894), .S0(n4909), .Y(
n1662) );
MX2X1TS U3464 ( .A(FPADDSUB_Add_Subt_result[7]), .B(n4956), .S0(n4976), .Y(
n1667) );
AO21XLTS U3465 ( .A0(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(n4832), .B0(n4817), .Y(n1651) );
AO21XLTS U3466 ( .A0(n4832), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]), .B0(n4820),
.Y(n1650) );
OAI21XLTS U3467 ( .A0(n5597), .A1(n5834), .B0(n3934), .Y(n1841) );
OAI21XLTS U3468 ( .A0(n5800), .A1(n4481), .B0(n4614), .Y(n1234) );
OAI21XLTS U3469 ( .A0(n5791), .A1(n2366), .B0(n4489), .Y(n1310) );
OAI21XLTS U3470 ( .A0(n5814), .A1(n2366), .B0(n4510), .Y(n1322) );
AO22XLTS U3471 ( .A0(Data_2[31]), .A1(n4781), .B0(FPADDSUB_intDY[31]), .B1(
n4780), .Y(n4782) );
XOR2X1TS U3472 ( .A(n2953), .B(n2952), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23) );
OAI21XLTS U3473 ( .A0(n3122), .A1(n3099), .B0(n3098), .Y(n3104) );
OAI21XLTS U3474 ( .A0(n3122), .A1(n3108), .B0(n3107), .Y(n3112) );
XOR2XLTS U3475 ( .A(n3122), .B(n3121), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17) );
XOR2XLTS U3476 ( .A(n3193), .B(n3192), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3) );
CLKAND2X2TS U3477 ( .A(n3241), .B(n3240), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1) );
NOR2X1TS U3478 ( .A(n3783), .B(n3045), .Y(n3003) );
NAND2X1TS U3479 ( .A(n3014), .B(n3751), .Y(n3015) );
AOI21X2TS U3480 ( .A0(n3756), .A1(n3013), .B0(n3012), .Y(n3016) );
XOR2X2TS U3481 ( .A(n3019), .B(n3018), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20) );
NAND2X1TS U3482 ( .A(n2957), .B(n3017), .Y(n3018) );
NAND2X1TS U3483 ( .A(n2821), .B(n2995), .Y(n2822) );
XOR2XLTS U3484 ( .A(n3576), .B(n3575), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3) );
INVX2TS U3485 ( .A(n3572), .Y(n3574) );
CLKAND2X2TS U3486 ( .A(n3703), .B(n3702), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1) );
XOR2XLTS U3487 ( .A(n3410), .B(n3409), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4) );
AO22XLTS U3488 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[0]), .B0(n5692), .B1(
cordic_result[0]), .Y(n1406) );
AO22XLTS U3489 ( .A0(n5630), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1471) );
AO22XLTS U3490 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[22]), .B0(n5687),
.B1(cordic_result[22]), .Y(n1362) );
AO22XLTS U3491 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[6]), .B0(n5688), .B1(
cordic_result[6]), .Y(n1394) );
AO22XLTS U3492 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[3]), .B0(n5688), .B1(
cordic_result[3]), .Y(n1400) );
AO22XLTS U3493 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[2]), .B0(n5688), .B1(
cordic_result[2]), .Y(n1402) );
AO22XLTS U3494 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[21]), .B0(n5687),
.B1(cordic_result[21]), .Y(n1364) );
AO22XLTS U3495 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[15]), .B0(n5685),
.B1(cordic_result[15]), .Y(n1376) );
AO22XLTS U3496 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[8]), .B0(n5685), .B1(
cordic_result[8]), .Y(n1390) );
AO22XLTS U3497 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[1]), .B0(n5688), .B1(
cordic_result[1]), .Y(n1404) );
AO22XLTS U3498 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[5]), .B0(n5688), .B1(
cordic_result[5]), .Y(n1396) );
AO22XLTS U3499 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[4]), .B0(n5688), .B1(
cordic_result[4]), .Y(n1398) );
AO22XLTS U3500 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[10]), .B0(n5685),
.B1(cordic_result[10]), .Y(n1386) );
AO22XLTS U3501 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[7]), .B0(n5688), .B1(
cordic_result[7]), .Y(n1392) );
AO22XLTS U3502 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[11]), .B0(n5685),
.B1(cordic_result[11]), .Y(n1384) );
AO22XLTS U3503 ( .A0(n5684), .A1(FPSENCOS_sign_inv_out[9]), .B0(n5685), .B1(
cordic_result[9]), .Y(n1388) );
AO22XLTS U3504 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[12]), .B0(n5685),
.B1(cordic_result[12]), .Y(n1382) );
AO22XLTS U3505 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[14]), .B0(n5685),
.B1(cordic_result[14]), .Y(n1378) );
AO22XLTS U3506 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[16]), .B0(n5685),
.B1(cordic_result[16]), .Y(n1374) );
AO22XLTS U3507 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[17]), .B0(n5685),
.B1(cordic_result[17]), .Y(n1372) );
AO22XLTS U3508 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[13]), .B0(n5685),
.B1(cordic_result[13]), .Y(n1380) );
AO22XLTS U3509 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[20]), .B0(n5687),
.B1(cordic_result[20]), .Y(n1366) );
AO22XLTS U3510 ( .A0(n5630), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1469) );
AO22XLTS U3511 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[18]), .B0(n5687),
.B1(cordic_result[18]), .Y(n1370) );
AO22XLTS U3512 ( .A0(n5679), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1429) );
AO22XLTS U3513 ( .A0(n5686), .A1(FPSENCOS_sign_inv_out[19]), .B0(n5687),
.B1(cordic_result[19]), .Y(n1368) );
AO22XLTS U3514 ( .A0(n5630), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n5629), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1459) );
AO22XLTS U3515 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[23]), .B0(n5687),
.B1(cordic_result[23]), .Y(n1360) );
AO22XLTS U3516 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[24]), .B0(n5687),
.B1(cordic_result[24]), .Y(n1358) );
AO22XLTS U3517 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[25]), .B0(n5687),
.B1(cordic_result[25]), .Y(n1356) );
AO22XLTS U3518 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[26]), .B0(n5692),
.B1(cordic_result[26]), .Y(n1354) );
AO22XLTS U3519 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[27]), .B0(n5688),
.B1(cordic_result[27]), .Y(n1352) );
AO22XLTS U3520 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[28]), .B0(n5688),
.B1(cordic_result[28]), .Y(n1350) );
AO22XLTS U3521 ( .A0(n5689), .A1(FPSENCOS_sign_inv_out[29]), .B0(n5692),
.B1(cordic_result[29]), .Y(n1348) );
AO22XLTS U3522 ( .A0(n5694), .A1(FPSENCOS_sign_inv_out[30]), .B0(n5692),
.B1(cordic_result[30]), .Y(n1346) );
AO22XLTS U3523 ( .A0(n5694), .A1(n5693), .B0(n5692), .B1(cordic_result[31]),
.Y(n1343) );
AO22XLTS U3524 ( .A0(n5679), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1409) );
AO22XLTS U3525 ( .A0(n5630), .A1(FPSENCOS_d_ff2_X[31]), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1798) );
AO22XLTS U3526 ( .A0(n5585), .A1(Data_1[31]), .B0(n5584), .B1(
FPSENCOS_d_ff1_Z[31]), .Y(n1704) );
AO22XLTS U3527 ( .A0(n5583), .A1(Data_1[0]), .B0(n5584), .B1(
FPSENCOS_d_ff1_Z[0]), .Y(n1705) );
AO22XLTS U3528 ( .A0(n5583), .A1(Data_1[1]), .B0(n5584), .B1(
FPSENCOS_d_ff1_Z[1]), .Y(n1706) );
AO22XLTS U3529 ( .A0(n5583), .A1(Data_1[2]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[2]), .Y(n1707) );
AO22XLTS U3530 ( .A0(n5583), .A1(Data_1[3]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[3]), .Y(n1708) );
AO22XLTS U3531 ( .A0(n5583), .A1(Data_1[4]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[4]), .Y(n1709) );
AO22XLTS U3532 ( .A0(n5585), .A1(Data_1[5]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[5]), .Y(n1710) );
AO22XLTS U3533 ( .A0(n5581), .A1(Data_1[6]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[6]), .Y(n1711) );
AO22XLTS U3534 ( .A0(n5585), .A1(Data_1[7]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[7]), .Y(n1712) );
AO22XLTS U3535 ( .A0(n5585), .A1(Data_1[8]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[8]), .Y(n1713) );
AO22XLTS U3536 ( .A0(n5585), .A1(Data_1[9]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[9]), .Y(n1714) );
AO22XLTS U3537 ( .A0(n5585), .A1(Data_1[10]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[10]), .Y(n1715) );
AO22XLTS U3538 ( .A0(n5585), .A1(Data_1[11]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[11]), .Y(n1716) );
AO22XLTS U3539 ( .A0(n5585), .A1(Data_1[12]), .B0(n5582), .B1(
FPSENCOS_d_ff1_Z[12]), .Y(n1717) );
AO22XLTS U3540 ( .A0(n5585), .A1(Data_1[13]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[13]), .Y(n1718) );
AO22XLTS U3541 ( .A0(n5585), .A1(Data_1[14]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[14]), .Y(n1719) );
AO22XLTS U3542 ( .A0(n5581), .A1(Data_1[15]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[15]), .Y(n1720) );
AO22XLTS U3543 ( .A0(n5581), .A1(Data_1[16]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[16]), .Y(n1721) );
AO22XLTS U3544 ( .A0(n5581), .A1(Data_1[17]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[17]), .Y(n1722) );
AO22XLTS U3545 ( .A0(n5581), .A1(Data_1[18]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[18]), .Y(n1723) );
AO22XLTS U3546 ( .A0(n5581), .A1(Data_1[19]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[19]), .Y(n1724) );
AO22XLTS U3547 ( .A0(n5581), .A1(Data_1[20]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[20]), .Y(n1725) );
AO22XLTS U3548 ( .A0(n5581), .A1(Data_1[21]), .B0(n5580), .B1(
FPSENCOS_d_ff1_Z[21]), .Y(n1726) );
AO22XLTS U3549 ( .A0(n5581), .A1(Data_1[22]), .B0(n5578), .B1(
FPSENCOS_d_ff1_Z[22]), .Y(n1727) );
AO22XLTS U3550 ( .A0(n5581), .A1(Data_1[23]), .B0(n5578), .B1(
FPSENCOS_d_ff1_Z[23]), .Y(n1728) );
AO22XLTS U3551 ( .A0(n5577), .A1(Data_1[24]), .B0(n5578), .B1(
FPSENCOS_d_ff1_Z[24]), .Y(n1729) );
AO22XLTS U3552 ( .A0(n5577), .A1(Data_1[25]), .B0(n5578), .B1(
FPSENCOS_d_ff1_Z[25]), .Y(n1730) );
AO22XLTS U3553 ( .A0(n5577), .A1(Data_1[26]), .B0(n5578), .B1(
FPSENCOS_d_ff1_Z[26]), .Y(n1731) );
AO22XLTS U3554 ( .A0(n5577), .A1(Data_1[27]), .B0(n5578), .B1(
FPSENCOS_d_ff1_Z[27]), .Y(n1732) );
AO22XLTS U3555 ( .A0(n5577), .A1(Data_1[28]), .B0(n5578), .B1(
FPSENCOS_d_ff1_Z[28]), .Y(n1733) );
AO22XLTS U3556 ( .A0(n5577), .A1(Data_1[29]), .B0(n5578), .B1(
FPSENCOS_d_ff1_Z[29]), .Y(n1734) );
AO22XLTS U3557 ( .A0(n5577), .A1(Data_1[30]), .B0(n5579), .B1(
FPSENCOS_d_ff1_Z[30]), .Y(n1735) );
AO22XLTS U3558 ( .A0(n5679), .A1(n3920), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_x_out[24]), .Y(n1788) );
AO22XLTS U3559 ( .A0(n5630), .A1(n5537), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_x_out[25]), .Y(n1787) );
AO22XLTS U3560 ( .A0(n5679), .A1(n3928), .B0(n5574), .B1(
FPSENCOS_d_ff3_sh_x_out[26]), .Y(n1786) );
AOI2BB2XLTS U3561 ( .B0(n5671), .B1(n5539), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n5674), .Y(n1785) );
AO22XLTS U3562 ( .A0(n5679), .A1(n5542), .B0(n5629), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1784) );
OAI21XLTS U3563 ( .A0(n5541), .A1(n5716), .B0(n5543), .Y(n5542) );
AOI2BB2XLTS U3564 ( .B0(n5671), .B1(n5544), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n5674), .Y(n1783) );
AO22XLTS U3565 ( .A0(n5679), .A1(n3922), .B0(n5678), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1417) );
AO22XLTS U3566 ( .A0(n5679), .A1(n3924), .B0(n5511), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1416) );
AO22XLTS U3567 ( .A0(n5679), .A1(n3926), .B0(n5574), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1415) );
AOI2BB2XLTS U3568 ( .B0(n5671), .B1(n5664), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n5674), .Y(n1414) );
AO22XLTS U3569 ( .A0(n5679), .A1(n5668), .B0(n5667), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1413) );
AOI2BB2XLTS U3570 ( .B0(n5671), .B1(n5670), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n5674), .Y(n1412) );
AO21XLTS U3571 ( .A0(FPSENCOS_d_ff3_LUT_out[3]), .A1(n5550), .B0(n5526), .Y(
n1802) );
AO21XLTS U3572 ( .A0(FPSENCOS_d_ff3_LUT_out[7]), .A1(n5550), .B0(n5517), .Y(
n1806) );
AO21XLTS U3573 ( .A0(FPSENCOS_d_ff3_LUT_out[11]), .A1(n5550), .B0(n5517),
.Y(n1810) );
AO22XLTS U3574 ( .A0(n5679), .A1(n5512), .B0(n5629), .B1(
FPSENCOS_d_ff3_LUT_out[12]), .Y(n1811) );
AO21XLTS U3575 ( .A0(FPSENCOS_d_ff3_LUT_out[13]), .A1(n5550), .B0(n5510),
.Y(n1812) );
AO21XLTS U3576 ( .A0(FPSENCOS_d_ff3_LUT_out[16]), .A1(n5624), .B0(n5526),
.Y(n1815) );
AO21XLTS U3577 ( .A0(FPSENCOS_d_ff3_LUT_out[18]), .A1(n2365), .B0(n5510),
.Y(n1817) );
OAI21XLTS U3578 ( .A0(n5536), .A1(n5764), .B0(FPSENCOS_cont_iter_out[0]),
.Y(n5500) );
OAI211XLTS U3579 ( .A0(n4443), .A1(n4513), .B0(n4442), .C0(n4441), .Y(n1836)
);
AO22XLTS U3580 ( .A0(n3911), .A1(n3910), .B0(mult_result[31]), .B1(n5478),
.Y(n1940) );
AO21XLTS U3581 ( .A0(FPMULT_Sgf_normalized_result[23]), .A1(n5182), .B0(
n5049), .Y(n1985) );
MX2X1TS U3582 ( .A(FPMULT_P_Sgf[23]), .B(n5313), .S0(n5413), .Y(n1916) );
MX2X1TS U3583 ( .A(Data_2[0]), .B(FPMULT_Op_MY[0]), .S0(n5040), .Y(n1990) );
MX2X1TS U3584 ( .A(Data_2[2]), .B(FPMULT_Op_MY[2]), .S0(n5040), .Y(n1992) );
MX2X1TS U3585 ( .A(Data_2[3]), .B(n2227), .S0(n5040), .Y(n1993) );
MX2X1TS U3586 ( .A(Data_2[4]), .B(FPMULT_Op_MY[4]), .S0(n5040), .Y(n1994) );
MX2X1TS U3587 ( .A(Data_2[5]), .B(FPMULT_Op_MY[5]), .S0(n5324), .Y(n1995) );
MX2X1TS U3588 ( .A(Data_2[6]), .B(FPMULT_Op_MY[6]), .S0(n5473), .Y(n1996) );
MX2X1TS U3589 ( .A(Data_2[7]), .B(FPMULT_Op_MY[7]), .S0(n5038), .Y(n1997) );
MX2X1TS U3590 ( .A(Data_2[12]), .B(FPMULT_Op_MY[12]), .S0(n5323), .Y(n2002)
);
MX2X1TS U3591 ( .A(Data_2[13]), .B(FPMULT_Op_MY[13]), .S0(n5323), .Y(n2003)
);
MX2X1TS U3592 ( .A(Data_2[14]), .B(n2270), .S0(n5323), .Y(n2004) );
MX2X1TS U3593 ( .A(Data_2[16]), .B(n2125), .S0(n5323), .Y(n2006) );
MX2X1TS U3594 ( .A(Data_1[3]), .B(FPMULT_Op_MX[3]), .S0(n5035), .Y(n2025) );
MX2X1TS U3595 ( .A(Data_1[5]), .B(n2130), .S0(n5035), .Y(n2027) );
MX2X1TS U3596 ( .A(Data_1[8]), .B(n2129), .S0(n5035), .Y(n2030) );
MX2X1TS U3597 ( .A(Data_1[10]), .B(n2121), .S0(n5035), .Y(n2032) );
MX2X1TS U3598 ( .A(Data_1[11]), .B(n2303), .S0(n5038), .Y(n2033) );
MX2X1TS U3599 ( .A(Data_1[14]), .B(FPMULT_Op_MX[14]), .S0(n5035), .Y(n2036)
);
MX2X1TS U3600 ( .A(Data_1[16]), .B(FPMULT_Op_MX[16]), .S0(n5037), .Y(n2038)
);
MX2X1TS U3601 ( .A(Data_1[18]), .B(FPMULT_Op_MX[18]), .S0(n5037), .Y(n2040)
);
MX2X1TS U3602 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n5037), .Y(n2042)
);
MX2X1TS U3603 ( .A(Data_1[21]), .B(n2237), .S0(n5037), .Y(n2043) );
BUFX3TS U3604 ( .A(n5930), .Y(n5916) );
NOR2X4TS U3605 ( .A(mult_x_159_n183), .B(mult_x_159_n177), .Y(n3113) );
AOI21X2TS U3606 ( .A0(n3332), .A1(n3336), .B0(n2711), .Y(n3324) );
INVX2TS U3607 ( .A(n3332), .Y(n3333) );
OAI21X2TS U3608 ( .A0(n3349), .A1(n2710), .B0(n2709), .Y(n3323) );
NOR2X2TS U3609 ( .A(n3357), .B(n3352), .Y(n2708) );
INVX4TS U3610 ( .A(n2141), .Y(n2228) );
NAND2X2TS U3611 ( .A(n2201), .B(n2340), .Y(n3498) );
NAND2X1TS U3612 ( .A(n2352), .B(n2734), .Y(n3769) );
INVX2TS U3613 ( .A(n3581), .Y(n2207) );
INVX2TS U3614 ( .A(n2747), .Y(n2222) );
OR2X1TS U3615 ( .A(n2303), .B(FPMULT_Op_MX[10]), .Y(n2131) );
OR2X1TS U3616 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[6]), .Y(n2132) );
CLKXOR2X2TS U3617 ( .A(n2763), .B(n2762), .Y(n2134) );
CLKXOR2X2TS U3618 ( .A(n2187), .B(FPMULT_Op_MY[2]), .Y(n2135) );
CLKXOR2X2TS U3619 ( .A(n3072), .B(n3071), .Y(n2137) );
AND2X2TS U3620 ( .A(n2940), .B(n3211), .Y(n2140) );
CLKXOR2X2TS U3621 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[18]), .Y(n3581) );
CMPR42X1TS U3622 ( .A(DP_OP_498J12_123_5135_n435), .B(
DP_OP_498J12_123_5135_n448), .C(DP_OP_498J12_123_5135_n461), .D(
DP_OP_498J12_123_5135_n369), .ICI(DP_OP_498J12_123_5135_n474), .S(
DP_OP_498J12_123_5135_n366), .ICO(DP_OP_498J12_123_5135_n364), .CO(
DP_OP_498J12_123_5135_n365) );
INVX2TS U3623 ( .A(DP_OP_498J12_123_5135_n365), .Y(n2319) );
NAND2X2TS U3624 ( .A(n2749), .B(n3709), .Y(n3710) );
CLKXOR2X2TS U3625 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[14]), .Y(n2747) );
INVX2TS U3626 ( .A(n3288), .Y(n2209) );
CLKBUFX2TS U3627 ( .A(n2892), .Y(n3288) );
CLKXOR2X2TS U3628 ( .A(n2238), .B(FPMULT_Op_MX[22]), .Y(n2142) );
INVX2TS U3629 ( .A(n4345), .Y(n4368) );
INVX2TS U3630 ( .A(n3211), .Y(n2214) );
CLKBUFX2TS U3631 ( .A(n2939), .Y(n3211) );
INVX2TS U3632 ( .A(FPMULT_Op_MX[12]), .Y(n3501) );
CLKBUFX2TS U3633 ( .A(n4012), .Y(n5706) );
INVX2TS U3634 ( .A(n2994), .Y(n2179) );
OR2X1TS U3635 ( .A(n4542), .B(n4541), .Y(n2148) );
OR2X1TS U3636 ( .A(n4535), .B(n4534), .Y(n2149) );
OR2X1TS U3637 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[2]), .Y(n2152) );
OR2X1TS U3638 ( .A(n2160), .B(FPMULT_Op_MX[0]), .Y(n2153) );
NOR2XLTS U3639 ( .A(n2132), .B(n2152), .Y(n2154) );
NOR2XLTS U3640 ( .A(n2131), .B(n2153), .Y(n2155) );
OR4X2TS U3641 ( .A(FPSENCOS_cordic_FSM_state_reg[3]), .B(n5767), .C(n5712),
.D(n5717), .Y(n2156) );
NAND2X2TS U3642 ( .A(mult_x_121_n196), .B(mult_x_121_n203), .Y(n3358) );
OAI21X4TS U3643 ( .A0(n2807), .A1(n3552), .B0(n2806), .Y(n3551) );
ADDFX2TS U3644 ( .A(n2802), .B(n2801), .CI(n2800), .CO(n2803), .S(n2799) );
CMPR42X2TS U3645 ( .A(DP_OP_498J12_123_5135_n452), .B(
DP_OP_498J12_123_5135_n401), .C(DP_OP_498J12_123_5135_n413), .D(
DP_OP_498J12_123_5135_n305), .ICI(DP_OP_498J12_123_5135_n311), .S(
DP_OP_498J12_123_5135_n303), .ICO(DP_OP_498J12_123_5135_n301), .CO(
DP_OP_498J12_123_5135_n302) );
NOR2X4TS U3646 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n2765) );
OAI22X2TS U3647 ( .A0(n4647), .A1(n4646), .B0(n4645), .B1(n4644), .Y(n4867)
);
NAND2X4TS U3648 ( .A(n3027), .B(n5720), .Y(n3085) );
NOR3X2TS U3649 ( .A(FPADDSUB_Add_Subt_result[3]), .B(
FPADDSUB_Add_Subt_result[2]), .C(n4644), .Y(n4651) );
NOR2X4TS U3650 ( .A(n4409), .B(n4451), .Y(n4464) );
ADDHX1TS U3651 ( .A(n2682), .B(n2681), .CO(n2683), .S(n2676) );
INVX2TS U3652 ( .A(n2328), .Y(n2158) );
INVX2TS U3653 ( .A(n2325), .Y(n2160) );
INVX2TS U3654 ( .A(n2326), .Y(n2162) );
INVX2TS U3655 ( .A(n4332), .Y(n2163) );
INVX2TS U3656 ( .A(n3813), .Y(n2164) );
INVX2TS U3657 ( .A(n3813), .Y(n2165) );
INVX2TS U3658 ( .A(n2123), .Y(n2166) );
INVX2TS U3659 ( .A(n2128), .Y(n2167) );
INVX2TS U3660 ( .A(n2345), .Y(n2169) );
INVX2TS U3661 ( .A(n5060), .Y(n2172) );
INVX2TS U3662 ( .A(n2172), .Y(n2173) );
INVX2TS U3663 ( .A(n2172), .Y(n2174) );
INVX2TS U3664 ( .A(FPSENCOS_cont_iter_out[0]), .Y(n2175) );
INVX2TS U3665 ( .A(n2348), .Y(n2177) );
INVX2TS U3666 ( .A(n2348), .Y(n2178) );
INVX2TS U3667 ( .A(FPSENCOS_cont_iter_out[1]), .Y(n2181) );
INVX2TS U3668 ( .A(n2181), .Y(n2182) );
INVX2TS U3669 ( .A(FPMULT_Op_MY[0]), .Y(n2184) );
INVX2TS U3670 ( .A(n2140), .Y(n2185) );
INVX2TS U3671 ( .A(n2140), .Y(n2186) );
CLKBUFX2TS U3672 ( .A(n3771), .Y(n2189) );
NAND2X4TS U3673 ( .A(n3591), .B(n3740), .Y(n2190) );
CLKXOR2X2TS U3674 ( .A(n3583), .B(n3582), .Y(n3591) );
INVX2TS U3675 ( .A(n2115), .Y(n2192) );
INVX2TS U3676 ( .A(n2338), .Y(n2195) );
INVX2TS U3677 ( .A(n2356), .Y(n2198) );
INVX2TS U3678 ( .A(DP_OP_498J12_123_5135_n727), .Y(n2202) );
INVX2TS U3679 ( .A(DP_OP_498J12_123_5135_n727), .Y(n2203) );
INVX2TS U3680 ( .A(FPMULT_Op_MY[11]), .Y(n2204) );
INVX2TS U3681 ( .A(n5706), .Y(n2205) );
INVX2TS U3682 ( .A(n2205), .Y(n2206) );
INVX2TS U3683 ( .A(n3581), .Y(n2208) );
INVX2TS U3684 ( .A(n2209), .Y(n2210) );
INVX2TS U3685 ( .A(n2209), .Y(n2211) );
INVX2TS U3686 ( .A(n2139), .Y(n2213) );
INVX2TS U3687 ( .A(n2214), .Y(n2215) );
INVX2TS U3688 ( .A(n2214), .Y(n2216) );
INVX2TS U3689 ( .A(n3425), .Y(n2217) );
INVX2TS U3690 ( .A(n2678), .Y(n2218) );
INVX2TS U3691 ( .A(n2218), .Y(n2219) );
INVX2TS U3692 ( .A(n2135), .Y(n2220) );
INVX2TS U3693 ( .A(n2747), .Y(n2223) );
INVX2TS U3694 ( .A(n2144), .Y(n2224) );
INVX2TS U3695 ( .A(n2144), .Y(n2225) );
INVX2TS U3696 ( .A(n2138), .Y(n2226) );
INVX2TS U3697 ( .A(n2138), .Y(n2227) );
INVX2TS U3698 ( .A(n2141), .Y(n2229) );
INVX2TS U3699 ( .A(n2145), .Y(n2231) );
INVX2TS U3700 ( .A(n2114), .Y(n2233) );
INVX2TS U3701 ( .A(n2234), .Y(n2236) );
INVX4TS U3702 ( .A(n2364), .Y(n2238) );
INVX2TS U3703 ( .A(n2239), .Y(n2240) );
INVX2TS U3704 ( .A(n3769), .Y(n2241) );
INVX2TS U3705 ( .A(n3769), .Y(n2242) );
INVX2TS U3706 ( .A(n4212), .Y(n2245) );
INVX2TS U3707 ( .A(n4212), .Y(n2246) );
INVX2TS U3708 ( .A(n4212), .Y(n2247) );
INVX2TS U3709 ( .A(n4367), .Y(n2248) );
INVX2TS U3710 ( .A(n2248), .Y(n2249) );
INVX2TS U3711 ( .A(n2248), .Y(n2250) );
INVX2TS U3712 ( .A(n4345), .Y(n2251) );
INVX2TS U3713 ( .A(n4345), .Y(n2252) );
INVX2TS U3714 ( .A(n2146), .Y(n2253) );
INVX2TS U3715 ( .A(n2146), .Y(n2254) );
INVX2TS U3716 ( .A(n4334), .Y(n4321) );
INVX2TS U3717 ( .A(n4334), .Y(n4298) );
INVX2TS U3718 ( .A(n2150), .Y(n2255) );
INVX2TS U3719 ( .A(n2150), .Y(n2256) );
INVX2TS U3720 ( .A(n2150), .Y(n2257) );
BUFX3TS U3721 ( .A(n5947), .Y(n5915) );
AOI22X2TS U3722 ( .A0(n4807), .A1(n4239), .B0(n4260), .B1(n5443), .Y(n4395)
);
AOI22X2TS U3723 ( .A0(n4807), .A1(n4241), .B0(n4262), .B1(n4479), .Y(n4398)
);
AOI22X2TS U3724 ( .A0(n4371), .A1(n4262), .B0(n4261), .B1(n4279), .Y(n4392)
);
AOI22X2TS U3725 ( .A0(n4371), .A1(n4264), .B0(n4263), .B1(n4279), .Y(n4390)
);
AOI22X2TS U3726 ( .A0(n2266), .A1(n4243), .B0(n4264), .B1(n4479), .Y(n4396)
);
AOI22X2TS U3727 ( .A0(n2266), .A1(n4245), .B0(n4266), .B1(n4279), .Y(n4391)
);
AOI22X2TS U3728 ( .A0(n4807), .A1(n4369), .B0(n4245), .B1(n4479), .Y(n4397)
);
INVX2TS U3729 ( .A(n2151), .Y(n2258) );
OAI32X1TS U3730 ( .A0(FPSENCOS_cordic_FSM_state_reg[2]), .A1(n4659), .A2(
n5717), .B0(n4658), .B1(n5767), .Y(n2060) );
OAI211X4TS U3731 ( .A0(FPSENCOS_cordic_FSM_state_reg[1]), .A1(n4666), .B0(
n4665), .C0(n5489), .Y(n2059) );
INVX2TS U3732 ( .A(n2156), .Y(n2259) );
INVX2TS U3733 ( .A(n4336), .Y(n2260) );
INVX2TS U3734 ( .A(n2133), .Y(n2262) );
INVX2TS U3735 ( .A(n2133), .Y(n2263) );
INVX2TS U3736 ( .A(n2133), .Y(n2264) );
CMPR42X1TS U3737 ( .A(mult_x_121_n340), .B(mult_x_121_n249), .C(
mult_x_121_n253), .D(mult_x_121_n247), .ICI(mult_x_121_n250), .S(
mult_x_121_n245), .ICO(mult_x_121_n243), .CO(mult_x_121_n244) );
ADDHX1TS U3738 ( .A(n3509), .B(n3508), .CO(mult_x_121_n248), .S(
mult_x_121_n249) );
NOR4X1TS U3739 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[0]), .C(
FPMULT_Op_MY[13]), .D(FPMULT_Op_MY[9]), .Y(n5456) );
NAND4X2TS U3740 ( .A(n4660), .B(n3940), .C(n5712), .D(n5767), .Y(n5586) );
NOR2X2TS U3741 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(n5765), .Y(n3940)
);
BUFX3TS U3742 ( .A(n5928), .Y(n5947) );
INVX2TS U3743 ( .A(n2147), .Y(n2265) );
OR2X2TS U3744 ( .A(n2889), .B(n4630), .Y(n4481) );
BUFX3TS U3745 ( .A(n5916), .Y(n5914) );
NAND3X2TS U3746 ( .A(n5536), .B(n5768), .C(n2183), .Y(n5520) );
INVX2TS U3747 ( .A(n4204), .Y(n2266) );
AOI22X2TS U3748 ( .A0(n4807), .A1(n4259), .B0(n4275), .B1(n4279), .Y(n4389)
);
AOI22X2TS U3749 ( .A0(n2266), .A1(n4260), .B0(n4259), .B1(n4279), .Y(n4383)
);
AOI22X2TS U3750 ( .A0(n2266), .A1(n4261), .B0(n4277), .B1(n4279), .Y(n4380)
);
AOI22X2TS U3751 ( .A0(n4371), .A1(n4263), .B0(n4280), .B1(n4279), .Y(n4378)
);
AOI22X2TS U3752 ( .A0(n4807), .A1(n4280), .B0(n4350), .B1(n4279), .Y(n4384)
);
AOI22X2TS U3753 ( .A0(n2266), .A1(n4266), .B0(n4265), .B1(n4279), .Y(n4379)
);
AOI22X2TS U3754 ( .A0(n4371), .A1(n4265), .B0(n4282), .B1(n4279), .Y(n4385)
);
AOI22X2TS U3755 ( .A0(n4807), .A1(n4350), .B0(n4349), .B1(n4479), .Y(n4477)
);
BUFX3TS U3756 ( .A(n5948), .Y(n5946) );
AOI222X4TS U3757 ( .A0(n4045), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4008), .B1(
FPSENCOS_d_ff1_Z[1]), .C0(FPSENCOS_d_ff_Zn[1]), .C1(n4043), .Y(n4006)
);
BUFX3TS U3758 ( .A(n3895), .Y(n5948) );
NOR2X4TS U3759 ( .A(FPADDSUB_FS_Module_state_reg[0]), .B(
FPADDSUB_FS_Module_state_reg[3]), .Y(n4512) );
NOR2X4TS U3760 ( .A(FPADDSUB_FS_Module_state_reg[1]), .B(n4862), .Y(n4876)
);
AOI32X1TS U3761 ( .A0(n5446), .A1(n2245), .A2(n5441), .B0(n4476), .B1(n2247),
.Y(n4375) );
NOR2X2TS U3762 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n5284) );
AO22X2TS U3763 ( .A0(FPADDSUB_LZA_output[2]), .A1(n3812), .B0(
FPADDSUB_exp_oper_result[2]), .B1(n2164), .Y(n4204) );
OAI221XLTS U3764 ( .A0(n5791), .A1(FPADDSUB_intDX[25]), .B0(n5797), .B1(
FPADDSUB_intDX[24]), .C0(n3861), .Y(n3862) );
INVX2TS U3765 ( .A(n2330), .Y(n2267) );
INVX2TS U3766 ( .A(n2351), .Y(n2268) );
INVX2TS U3767 ( .A(n2269), .Y(n2270) );
INVX2TS U3768 ( .A(n2994), .Y(n2271) );
BUFX3TS U3769 ( .A(n3034), .Y(n2272) );
AND2X4TS U3770 ( .A(n2672), .B(n2222), .Y(n3477) );
INVX2TS U3771 ( .A(n3477), .Y(n2274) );
INVX2TS U3772 ( .A(n3681), .Y(n2275) );
BUFX3TS U3773 ( .A(n2727), .Y(n3692) );
CLKBUFX2TS U3774 ( .A(n3487), .Y(n2276) );
NAND2X4TS U3775 ( .A(n2686), .B(n2678), .Y(n3487) );
CLKBUFX2TS U3776 ( .A(n3494), .Y(n2277) );
CLKBUFX2TS U3777 ( .A(n3507), .Y(n2278) );
NAND2X4TS U3778 ( .A(n3427), .B(n3426), .Y(n3507) );
BUFX3TS U3779 ( .A(n3282), .Y(n2279) );
CLKBUFX2TS U3780 ( .A(n3290), .Y(n2280) );
BUFX3TS U3781 ( .A(n3308), .Y(n2281) );
INVX2TS U3782 ( .A(n2728), .Y(n2284) );
OAI22X1TS U3783 ( .A0(n3697), .A1(n2242), .B0(n2741), .B1(n3699), .Y(n3701)
);
INVX2TS U3784 ( .A(n2728), .Y(n3699) );
INVX2TS U3785 ( .A(n2134), .Y(n2286) );
INVX2TS U3786 ( .A(n2136), .Y(n2289) );
XNOR2X1TS U3787 ( .A(n3684), .B(n2292), .Y(n3630) );
XNOR2X1TS U3788 ( .A(n3682), .B(n2292), .Y(n3629) );
CLKXOR2X2TS U3789 ( .A(n3589), .B(n3588), .Y(n3590) );
BUFX3TS U3790 ( .A(n3080), .Y(n2295) );
BUFX3TS U3791 ( .A(n3080), .Y(n2296) );
CLKXOR2X2TS U3792 ( .A(n3079), .B(n3078), .Y(n3080) );
BUFX3TS U3793 ( .A(n2980), .Y(n2297) );
INVX2TS U3794 ( .A(n2341), .Y(n2298) );
BUFX3TS U3795 ( .A(FPMULT_Op_MX[0]), .Y(n3306) );
INVX2TS U3796 ( .A(n2299), .Y(n2300) );
BUFX3TS U3797 ( .A(FPMULT_Op_MY[12]), .Y(n3505) );
BUFX3TS U3798 ( .A(n5487), .Y(n2301) );
BUFX3TS U3799 ( .A(n5487), .Y(n2302) );
NOR3X2TS U3800 ( .A(n5486), .B(n5485), .C(n5586), .Y(n5487) );
OAI221X1TS U3801 ( .A0(n5809), .A1(FPADDSUB_intDY[10]), .B0(n5811), .B1(
FPADDSUB_intDY[2]), .C0(n3844), .Y(n3847) );
AOI21X2TS U3802 ( .A0(n2920), .A1(n3178), .B0(n2919), .Y(n3176) );
AOI31XLTS U3803 ( .A0(n5425), .A1(n5424), .A2(n5423), .B0(dataB[27]), .Y(
n5436) );
OAI221X1TS U3804 ( .A0(n5735), .A1(FPADDSUB_intDY[7]), .B0(n5799), .B1(
FPADDSUB_intDY[14]), .C0(n3850), .Y(n3857) );
CLKXOR2X2TS U3805 ( .A(n4576), .B(n4575), .Y(n5330) );
OAI21X1TS U3806 ( .A0(n4576), .A1(n4572), .B0(n4573), .Y(n4569) );
INVX2TS U3807 ( .A(n4576), .Y(n4527) );
OAI21XLTS U3808 ( .A0(n5520), .A1(n5576), .B0(n4273), .Y(n1808) );
CLKBUFX3TS U3809 ( .A(n3931), .Y(n3888) );
AOI21X1TS U3810 ( .A0(n3350), .A1(n2708), .B0(n2707), .Y(n2709) );
AOI2BB2X1TS U3811 ( .B0(n2833), .B1(n2882), .A0N(n2832), .A1N(n2831), .Y(
n2888) );
AO22X1TS U3812 ( .A0(n4876), .A1(n3033), .B0(n4875), .B1(
FPADDSUB_LZA_output[0]), .Y(n1658) );
NOR4X1TS U3813 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5913) );
NOR4X1TS U3814 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5912) );
NOR4X1TS U3815 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n3804),
.Y(n5911) );
NAND3X2TS U3816 ( .A(n5033), .B(n5808), .C(n2116), .Y(n3892) );
NOR2X2TS U3817 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n5033) );
INVX2TS U3818 ( .A(n3938), .Y(n4663) );
NAND2X2TS U3819 ( .A(n5717), .B(n5765), .Y(n3938) );
NOR4X1TS U3820 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[19]), .C(
FPMULT_Op_MX[17]), .D(FPMULT_Op_MX[15]), .Y(n5459) );
OAI22X1TS U3821 ( .A0(n2185), .A1(n3206), .B0(n2215), .B1(n3205), .Y(
mult_x_159_n294) );
OAI33X1TS U3822 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n5690), .B0(n5731), .B1(
n5845), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n5691) );
NOR4X1TS U3823 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[5]), .C(
FPMULT_Op_MY[3]), .D(FPMULT_Op_MY[1]), .Y(n5457) );
NOR2X2TS U3824 ( .A(n5446), .B(n5444), .Y(n4476) );
OAI21XLTS U3825 ( .A0(n4600), .A1(n5839), .B0(n4593), .Y(n1216) );
OAI21XLTS U3826 ( .A0(n4600), .A1(n5838), .B0(n4592), .Y(n1223) );
OAI21XLTS U3827 ( .A0(n4600), .A1(n5837), .B0(n4591), .Y(n1222) );
OAI21XLTS U3828 ( .A0(n4600), .A1(n5840), .B0(n4590), .Y(n1226) );
OAI21XLTS U3829 ( .A0(n4600), .A1(n5824), .B0(n4588), .Y(n1221) );
OAI21XLTS U3830 ( .A0(n4600), .A1(n5823), .B0(n4587), .Y(n1224) );
NOR2X2TS U3831 ( .A(FPSENCOS_d_ff2_Y[23]), .B(n2175), .Y(n4069) );
NOR2X2TS U3832 ( .A(FPSENCOS_d_ff2_X[23]), .B(n2175), .Y(n4067) );
BUFX3TS U3833 ( .A(n5579), .Y(n5578) );
NAND2X2TS U3834 ( .A(n5671), .B(n5503), .Y(n5505) );
AOI2BB2X2TS U3835 ( .B0(n4512), .B1(n3820), .A0N(n4468), .A1N(n3932), .Y(
n5342) );
NOR2X1TS U3836 ( .A(n3933), .B(n4254), .Y(n3820) );
AOI211X1TS U3837 ( .A0(FPADDSUB_intDY[16]), .A1(n5815), .B0(n2874), .C0(
n2875), .Y(n2866) );
XNOR2X2TS U3838 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n3909) );
NOR2XLTS U3839 ( .A(n5768), .B(n5490), .Y(n5491) );
NAND4X2TS U3840 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(
FPSENCOS_cordic_FSM_state_reg[3]), .C(n5712), .D(n5767), .Y(n5490) );
NOR2XLTS U3841 ( .A(FPADDSUB_Add_Subt_result[3]), .B(
FPADDSUB_Add_Subt_result[2]), .Y(n4645) );
BUFX3TS U3842 ( .A(n3895), .Y(n3897) );
AOI22X2TS U3843 ( .A0(FPADDSUB_LZA_output[1]), .A1(n3812), .B0(n2165), .B1(
FPADDSUB_exp_oper_result[1]), .Y(n4216) );
NOR4X1TS U3844 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[30]), .C(
FPMULT_Op_MY[29]), .D(FPMULT_Op_MY[28]), .Y(n5451) );
NOR2XLTS U3845 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n4772) );
NOR3XLTS U3846 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[12]), .C(
FPMULT_Op_MY[23]), .Y(n5455) );
NOR3XLTS U3847 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[13]), .C(
FPMULT_Op_MX[24]), .Y(n5463) );
AO22X1TS U3848 ( .A0(n3087), .A1(n4876), .B0(n4875), .B1(
FPADDSUB_LZA_output[3]), .Y(n1655) );
AOI22X2TS U3849 ( .A0(n2266), .A1(n4205), .B0(n4239), .B1(n4479), .Y(n4401)
);
BUFX3TS U3850 ( .A(n4208), .Y(n2304) );
BUFX3TS U3851 ( .A(n4208), .Y(n2305) );
NOR2X2TS U3852 ( .A(n4215), .B(n4785), .Y(n4208) );
CLKBUFX2TS U3853 ( .A(n4878), .Y(n2306) );
INVX2TS U3854 ( .A(n2360), .Y(n2307) );
NOR2X1TS U3855 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n3613) );
NAND2X1TS U3856 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n3621) );
OAI21XLTS U3857 ( .A0(n5514), .A1(n3945), .B0(n3944), .Y(n1703) );
BUFX3TS U3858 ( .A(n3905), .Y(n2308) );
BUFX3TS U3859 ( .A(n3905), .Y(n5306) );
NOR2X2TS U3860 ( .A(n5828), .B(n3904), .Y(n3905) );
INVX2TS U3861 ( .A(n5304), .Y(n2309) );
INVX2TS U3862 ( .A(n5304), .Y(n2310) );
INVX2TS U3863 ( .A(n5304), .Y(n2311) );
AND2X2TS U3864 ( .A(n3734), .B(n2783), .Y(n2315) );
CLKXOR2X4TS U3865 ( .A(n2317), .B(n2316), .Y(n3734) );
INVX2TS U3866 ( .A(n5600), .Y(n2312) );
INVX2TS U3867 ( .A(n5600), .Y(n2313) );
INVX2TS U3868 ( .A(n5600), .Y(n2314) );
AOI32X1TS U3869 ( .A0(FPADDSUB_Add_Subt_result[10]), .A1(n3029), .A2(n5818),
.B0(FPADDSUB_Add_Subt_result[12]), .B1(n3029), .Y(n4857) );
NAND2BX1TS U3870 ( .AN(FPADDSUB_Add_Subt_result[12]), .B(n3029), .Y(n4873)
);
NAND2X1TS U3871 ( .A(FPMULT_Sgf_normalized_result[3]), .B(
FPMULT_Sgf_normalized_result[2]), .Y(n5041) );
NOR2XLTS U3872 ( .A(n5265), .B(FPMULT_Sgf_normalized_result[2]), .Y(n5266)
);
NOR2X1TS U3873 ( .A(FPADDSUB_Add_Subt_result[21]), .B(
FPADDSUB_Add_Subt_result[20]), .Y(n4852) );
NOR2BX2TS U3874 ( .AN(n3082), .B(FPADDSUB_Add_Subt_result[13]), .Y(n3029) );
NOR2X2TS U3875 ( .A(n3021), .B(FPADDSUB_Add_Subt_result[4]), .Y(n4855) );
AOI31XLTS U3876 ( .A0(FPADDSUB_Add_Subt_result[6]), .A1(n3028), .A2(n5820),
.B0(n3083), .Y(n3031) );
NOR2XLTS U3877 ( .A(FPADDSUB_Add_Subt_result[7]), .B(
FPADDSUB_Add_Subt_result[6]), .Y(n4647) );
OAI221XLTS U3878 ( .A0(n5793), .A1(FPADDSUB_intDY[22]), .B0(n5801), .B1(
FPADDSUB_intDX[12]), .C0(n3869), .Y(n3870) );
OAI221X1TS U3879 ( .A0(n5729), .A1(FPADDSUB_intDX[27]), .B0(n5798), .B1(
FPADDSUB_intDY[19]), .C0(n3860), .Y(n3863) );
OAI221X1TS U3880 ( .A0(n5796), .A1(FPADDSUB_intDY[17]), .B0(n5815), .B1(
FPADDSUB_intDY[16]), .C0(n3868), .Y(n3871) );
OAI221X1TS U3881 ( .A0(n5786), .A1(FPADDSUB_intDY[3]), .B0(n5805), .B1(
FPADDSUB_intDX[26]), .C0(n3852), .Y(n3855) );
NOR2X1TS U3882 ( .A(n5814), .B(FPADDSUB_intDX[29]), .Y(n2829) );
AOI221X1TS U3883 ( .A0(FPADDSUB_intDX[30]), .A1(n5736), .B0(
FPADDSUB_intDX[29]), .B1(n5814), .C0(n2830), .Y(n2832) );
OAI221X1TS U3884 ( .A0(n5794), .A1(FPADDSUB_intDY[18]), .B0(n5814), .B1(
FPADDSUB_intDX[29]), .C0(n3859), .Y(n3864) );
NOR2X1TS U3885 ( .A(n5736), .B(FPADDSUB_intDX[30]), .Y(n2831) );
OAI221X1TS U3886 ( .A0(n5795), .A1(FPADDSUB_intDY[20]), .B0(n5736), .B1(
FPADDSUB_intDX[30]), .C0(n3866), .Y(n3873) );
NOR2X1TS U3887 ( .A(n5791), .B(FPADDSUB_intDX[25]), .Y(n2883) );
NOR2X2TS U3888 ( .A(n2522), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(n5345) );
NAND2X4TS U3889 ( .A(n4517), .B(n4516), .Y(n4581) );
OR2X1TS U3890 ( .A(n2540), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(n2320) );
OR2X1TS U3891 ( .A(n2541), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(n2321) );
OR2X1TS U3892 ( .A(mult_x_159_n247), .B(mult_x_159_n253), .Y(n2327) );
OR2X1TS U3893 ( .A(n2676), .B(n2675), .Y(n2332) );
OR2X1TS U3894 ( .A(n2744), .B(n2743), .Y(n2333) );
BUFX3TS U3895 ( .A(FPMULT_Op_MY[22]), .Y(n5039) );
OR2X1TS U3896 ( .A(n4731), .B(n4730), .Y(n2335) );
OR2X1TS U3897 ( .A(n2694), .B(n2693), .Y(n2342) );
INVX2TS U3898 ( .A(n5711), .Y(n5402) );
OR2X2TS U3899 ( .A(FPMULT_FSM_selector_B[1]), .B(n5776), .Y(n2349) );
OR2X1TS U3900 ( .A(n2526), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(n2350) );
OR2X1TS U3901 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n2352) );
OR2X1TS U3902 ( .A(n2777), .B(n2776), .Y(n2357) );
OR2X1TS U3903 ( .A(DP_OP_498J12_123_5135_n366), .B(n2803), .Y(n2358) );
AND2X2TS U3904 ( .A(n3047), .B(n3056), .Y(n2361) );
AO21X1TS U3905 ( .A0(n3057), .A1(n3056), .B0(n3055), .Y(n2362) );
OAI21XLTS U3906 ( .A0(FPADDSUB_intDX[13]), .A1(n5781), .B0(
FPADDSUB_intDX[12]), .Y(n2847) );
NAND2X1TS U3907 ( .A(n3582), .B(n3580), .Y(n3078) );
AOI21X1TS U3908 ( .A0(n3624), .A1(n2982), .B0(n2987), .Y(n2985) );
XOR2X1TS U3909 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2746) );
NOR2X2TS U3910 ( .A(n2431), .B(n2430), .Y(n2451) );
INVX2TS U3911 ( .A(n2554), .Y(n2556) );
INVX2TS U3912 ( .A(n2492), .Y(n2494) );
OR2X1TS U3913 ( .A(n2440), .B(n2439), .Y(n2463) );
AO21X1TS U3914 ( .A0(n2190), .A1(n2294), .B0(n3739), .Y(n3746) );
ADDFX2TS U3915 ( .A(n3612), .B(n3070), .CI(n3069), .CO(
DP_OP_498J12_123_5135_n304), .S(DP_OP_498J12_123_5135_n305) );
ADDFX2TS U3916 ( .A(n3777), .B(n3776), .CI(n3775), .CO(n3778), .S(
DP_OP_498J12_123_5135_n332) );
NAND2X4TS U3917 ( .A(n3437), .B(n2207), .Y(n3494) );
OAI21X1TS U3918 ( .A0(n2561), .A1(n2477), .B0(n2476), .Y(n2570) );
BUFX3TS U3919 ( .A(FPMULT_Op_MY[18]), .Y(n5450) );
CMPR42X1TS U3920 ( .A(mult_x_121_n312), .B(mult_x_121_n336), .C(
mult_x_121_n300), .D(n2348), .ICI(mult_x_121_n224), .S(mult_x_121_n217), .ICO(mult_x_121_n215), .CO(mult_x_121_n216) );
NOR2X1TS U3921 ( .A(n4715), .B(n4714), .Y(n5014) );
NOR2X1TS U3922 ( .A(n5000), .B(n4725), .Y(n4727) );
NOR2X2TS U3923 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .B(
n2654), .Y(n5137) );
OR2X1TS U3924 ( .A(n4739), .B(n4738), .Y(n4958) );
OAI21X2TS U3925 ( .A0(n4895), .A1(n4693), .B0(n4692), .Y(n4953) );
OAI21X2TS U3926 ( .A0(n3119), .A1(n3113), .B0(n3114), .Y(n3106) );
AOI31XLTS U3927 ( .A0(n5773), .A1(n5720), .A2(n4866), .B0(n4865), .Y(n4868)
);
INVX2TS U3928 ( .A(n4552), .Y(n4554) );
INVX2TS U3929 ( .A(n4911), .Y(n4912) );
INVX2TS U3930 ( .A(n5396), .Y(n5398) );
INVX2TS U3931 ( .A(n5190), .Y(n5192) );
OAI21XLTS U3932 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4772), .B0(n2349), .Y(
n4773) );
NOR3XLTS U3933 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n5416) );
OR2X1TS U3934 ( .A(mult_x_159_n163), .B(n2941), .Y(n3089) );
NAND2X1TS U3935 ( .A(mult_x_159_n216), .B(mult_x_159_n224), .Y(n3143) );
AOI21X2TS U3936 ( .A0(n2926), .A1(n3162), .B0(n2925), .Y(n3153) );
NAND2X2TS U3937 ( .A(DP_OP_498J12_123_5135_n279), .B(
DP_OP_498J12_123_5135_n284), .Y(n3512) );
AOI211X1TS U3938 ( .A0(n3027), .A1(FPADDSUB_Add_Subt_result[18]), .B0(n4648),
.C0(n3023), .Y(n4860) );
BUFX3TS U3939 ( .A(n4430), .Y(n4452) );
BUFX3TS U3940 ( .A(n4288), .Y(n4303) );
NOR2XLTS U3941 ( .A(n5443), .B(n4785), .Y(n4786) );
AOI21X1TS U3942 ( .A0(n3091), .A1(n3089), .B0(n2942), .Y(n2953) );
OR2X1TS U3943 ( .A(n3239), .B(n3238), .Y(n3241) );
OR2X1TS U3944 ( .A(n3701), .B(n3700), .Y(n3703) );
INVX2TS U3945 ( .A(n3349), .Y(n3372) );
OAI21X1TS U3946 ( .A0(n3409), .A1(n3406), .B0(n3407), .Y(n3405) );
INVX2TS U3947 ( .A(FPSENCOS_d_ff2_X[12]), .Y(n5559) );
INVX2TS U3948 ( .A(FPSENCOS_d_ff2_X[14]), .Y(n5557) );
INVX2TS U3949 ( .A(FPSENCOS_d_ff_Yn[16]), .Y(n5641) );
INVX2TS U3950 ( .A(FPSENCOS_d_ff2_X[15]), .Y(n5555) );
INVX2TS U3951 ( .A(FPSENCOS_d_ff2_X[2]), .Y(n5571) );
INVX2TS U3952 ( .A(FPSENCOS_d_ff_Yn[23]), .Y(n5652) );
INVX2TS U3953 ( .A(FPSENCOS_d_ff2_X[30]), .Y(n5546) );
BUFX3TS U3954 ( .A(n5658), .Y(n5675) );
OAI21XLTS U3955 ( .A0(n3943), .A1(n3942), .B0(n3941), .Y(n1699) );
OAI21XLTS U3956 ( .A0(n4272), .A1(n5681), .B0(n4270), .Y(op_result[0]) );
INVX2TS U3958 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n2368) );
INVX2TS U3959 ( .A(n2518), .Y(n2367) );
OAI21X2TS U3960 ( .A0(n2513), .A1(n2516), .B0(n2514), .Y(n2523) );
INVX2TS U3961 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n2372) );
INVX2TS U3962 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n2371) );
NOR2X2TS U3963 ( .A(n2374), .B(n2373), .Y(n2533) );
INVX2TS U3964 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n2380) );
INVX2TS U3965 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n2379) );
INVX2TS U3966 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n2382) );
INVX2TS U3967 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n2381) );
NOR2X2TS U3968 ( .A(n2388), .B(n2387), .Y(n2506) );
INVX2TS U3969 ( .A(FPMULT_Sgf_operation_Result[5]), .Y(n2384) );
INVX2TS U3970 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n2383) );
CMPR32X2TS U3971 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]), .B(
n2382), .C(n2381), .CO(n2389), .S(n2388) );
NOR2X2TS U3972 ( .A(n2390), .B(n2389), .Y(n2508) );
NOR2X2TS U3973 ( .A(n2506), .B(n2508), .Y(n2503) );
INVX2TS U3974 ( .A(FPMULT_Sgf_operation_Result[6]), .Y(n2386) );
INVX2TS U3975 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n2385) );
CMPR32X2TS U3976 ( .A(n2384), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]), .C(n2383), .CO(
n2391), .S(n2390) );
NOR2X2TS U3977 ( .A(n2392), .B(n2391), .Y(n2552) );
INVX2TS U3978 ( .A(FPMULT_Sgf_operation_Result[7]), .Y(n2405) );
INVX2TS U3979 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n2404) );
NOR2X2TS U3980 ( .A(n2394), .B(n2393), .Y(n2554) );
NOR2X2TS U3981 ( .A(n2552), .B(n2554), .Y(n2396) );
NAND2X2TS U3982 ( .A(n2503), .B(n2396), .Y(n2398) );
NAND2X2TS U3983 ( .A(n2388), .B(n2387), .Y(n2528) );
NAND2X1TS U3984 ( .A(n2390), .B(n2389), .Y(n2509) );
OAI21X2TS U3985 ( .A0(n2508), .A1(n2528), .B0(n2509), .Y(n2502) );
NAND2X1TS U3986 ( .A(n2394), .B(n2393), .Y(n2555) );
OAI21X1TS U3987 ( .A0(n2554), .A1(n2551), .B0(n2555), .Y(n2395) );
OAI21X4TS U3988 ( .A0(n2501), .A1(n2398), .B0(n2397), .Y(n2442) );
INVX2TS U3989 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .Y(
n2400) );
INVX2TS U3990 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(
n2399) );
INVX2TS U3991 ( .A(FPMULT_Sgf_operation_Result[11]), .Y(n2411) );
INVX2TS U3992 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(
n2410) );
NOR2X2TS U3993 ( .A(n2425), .B(n2424), .Y(n2485) );
INVX2TS U3994 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(
n2402) );
INVX2TS U3995 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(
n2401) );
CMPR32X2TS U3996 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]),
.B(n2400), .C(n2399), .CO(n2426), .S(n2425) );
NOR2X2TS U3997 ( .A(n2427), .B(n2426), .Y(n2492) );
NOR2X2TS U3998 ( .A(n2485), .B(n2492), .Y(n2445) );
INVX4TS U3999 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[14]), .Y(
n5117) );
INVX2TS U4000 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(
n2403) );
CMPR32X2TS U4001 ( .A(n2402), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]), .C(n2401), .CO(
n2428), .S(n2427) );
INVX2TS U4002 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(
n2438) );
INVX2TS U4003 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(
n5103) );
CMPR32X2TS U4004 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]),
.B(n5117), .C(n2403), .CO(n2430), .S(n2429) );
INVX2TS U4005 ( .A(FPMULT_Sgf_operation_Result[8]), .Y(n2407) );
INVX2TS U4006 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n2406) );
CMPR32X2TS U4007 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]), .B(
n2405), .C(n2404), .CO(n2414), .S(n2394) );
NOR2X2TS U4008 ( .A(n2415), .B(n2414), .Y(n2560) );
INVX2TS U4009 ( .A(FPMULT_Sgf_operation_Result[9]), .Y(n2409) );
INVX2TS U4010 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n2408) );
CMPR32X2TS U4011 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]), .B(
n2407), .C(n2406), .CO(n2416), .S(n2415) );
NOR2X2TS U4012 ( .A(n2417), .B(n2416), .Y(n2562) );
INVX2TS U4013 ( .A(FPMULT_Sgf_operation_Result[10]), .Y(n2413) );
INVX2TS U4014 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(
n2412) );
CMPR32X2TS U4015 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]), .B(
n2409), .C(n2408), .CO(n2418), .S(n2417) );
NOR2X2TS U4016 ( .A(n2421), .B(n2420), .Y(n2480) );
NOR2X2TS U4017 ( .A(n2478), .B(n2480), .Y(n2423) );
NOR2X2TS U4018 ( .A(n2435), .B(n2444), .Y(n2437) );
NAND2X1TS U4019 ( .A(n2417), .B(n2416), .Y(n2563) );
OAI21X2TS U4020 ( .A0(n2562), .A1(n2559), .B0(n2563), .Y(n2475) );
NAND2X1TS U4021 ( .A(n2421), .B(n2420), .Y(n2481) );
OAI21X1TS U4022 ( .A0(n2480), .A1(n2567), .B0(n2481), .Y(n2422) );
NAND2X2TS U4023 ( .A(n2425), .B(n2424), .Y(n2488) );
NAND2X1TS U4024 ( .A(n2427), .B(n2426), .Y(n2493) );
NAND2X1TS U4025 ( .A(n2431), .B(n2430), .Y(n2452) );
OAI21X2TS U4026 ( .A0(n2451), .A1(n2497), .B0(n2452), .Y(n2432) );
AOI21X4TS U4027 ( .A0(n2442), .A1(n2437), .B0(n2436), .Y(n2469) );
INVX2TS U4028 ( .A(n2469), .Y(n2457) );
INVX2TS U4029 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[16]), .Y(
n5091) );
INVX2TS U4030 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(
n2458) );
CMPR32X2TS U4031 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]),
.B(n2438), .C(n5103), .CO(n2439), .S(n2431) );
NAND2X1TS U4032 ( .A(n2440), .B(n2439), .Y(n2456) );
NAND2X1TS U4033 ( .A(n2463), .B(n2456), .Y(n2441) );
XNOR2X1TS U4034 ( .A(n2457), .B(n2441), .Y(n2586) );
NOR2X2TS U4035 ( .A(n2586), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n5246) );
INVX2TS U4036 ( .A(n2445), .Y(n2448) );
INVX2TS U4037 ( .A(n2446), .Y(n2447) );
INVX2TS U4038 ( .A(n2449), .Y(n2498) );
INVX2TS U4039 ( .A(n2497), .Y(n2450) );
AOI21X1TS U4040 ( .A0(n2500), .A1(n2498), .B0(n2450), .Y(n2455) );
INVX2TS U4041 ( .A(n2451), .Y(n2453) );
NAND2X1TS U4042 ( .A(n2453), .B(n2452), .Y(n2454) );
CLKXOR2X2TS U4043 ( .A(n2455), .B(n2454), .Y(n2585) );
NOR2X2TS U4044 ( .A(n2585), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n5243) );
INVX2TS U4045 ( .A(n2456), .Y(n2466) );
AOI21X1TS U4046 ( .A0(n2457), .A1(n2463), .B0(n2466), .Y(n2462) );
INVX2TS U4047 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .Y(
n5082) );
INVX2TS U4048 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(
n2470) );
CMPR32X2TS U4049 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]),
.B(n5091), .C(n2458), .CO(n2459), .S(n2440) );
NAND2X1TS U4050 ( .A(n2460), .B(n2459), .Y(n2464) );
NAND2X1TS U4051 ( .A(n2363), .B(n2464), .Y(n2461) );
XOR2X1TS U4052 ( .A(n2462), .B(n2461), .Y(n2587) );
NOR2X2TS U4053 ( .A(n2587), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n5220) );
INVX2TS U4054 ( .A(n2464), .Y(n2465) );
AOI21X1TS U4055 ( .A0(n2363), .A1(n2466), .B0(n2465), .Y(n2467) );
OAI21X4TS U4056 ( .A0(n2469), .A1(n2468), .B0(n2467), .Y(n2598) );
INVX2TS U4057 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[18]), .Y(
n5074) );
INVX2TS U4058 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(
n2599) );
CMPR32X2TS U4059 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]),
.B(n5082), .C(n2470), .CO(n2471), .S(n2460) );
NAND2X1TS U4060 ( .A(n2472), .B(n2471), .Y(n2595) );
NAND2X1TS U4061 ( .A(n2597), .B(n2595), .Y(n2473) );
XNOR2X1TS U4062 ( .A(n2598), .B(n2473), .Y(n2588) );
NOR2X2TS U4063 ( .A(n2588), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n5222) );
NAND2X2TS U4064 ( .A(n5216), .B(n2590), .Y(n2592) );
INVX2TS U4065 ( .A(n2474), .Y(n2477) );
INVX2TS U4066 ( .A(n2475), .Y(n2476) );
INVX2TS U4067 ( .A(n2478), .Y(n2568) );
INVX2TS U4068 ( .A(n2567), .Y(n2479) );
AOI21X1TS U4069 ( .A0(n2570), .A1(n2568), .B0(n2479), .Y(n2484) );
NAND2X1TS U4070 ( .A(n2482), .B(n2481), .Y(n2483) );
CLKXOR2X2TS U4071 ( .A(n2484), .B(n2483), .Y(n2579) );
NOR2X2TS U4072 ( .A(n2579), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .Y(n5308) );
INVX2TS U4073 ( .A(n2485), .Y(n2490) );
NAND2X1TS U4074 ( .A(n2490), .B(n2488), .Y(n2486) );
XOR2X1TS U4075 ( .A(n2487), .B(n2486), .Y(n2580) );
NOR2X2TS U4076 ( .A(n2580), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n5296) );
INVX2TS U4077 ( .A(n2488), .Y(n2489) );
AOI21X1TS U4078 ( .A0(n2491), .A1(n2490), .B0(n2489), .Y(n2496) );
NAND2X1TS U4079 ( .A(n2494), .B(n2493), .Y(n2495) );
XOR2X1TS U4080 ( .A(n2496), .B(n2495), .Y(n2581) );
NAND2X1TS U4081 ( .A(n2498), .B(n2497), .Y(n2499) );
XNOR2X1TS U4082 ( .A(n2500), .B(n2499), .Y(n2582) );
NOR2X2TS U4083 ( .A(n2582), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n5274) );
NAND2X2TS U4084 ( .A(n5268), .B(n2584), .Y(n5215) );
NOR2X2TS U4085 ( .A(n2592), .B(n5215), .Y(n2594) );
NAND2X1TS U4086 ( .A(n2504), .B(n2551), .Y(n2505) );
XOR2X1TS U4087 ( .A(n2553), .B(n2505), .Y(n2546) );
NOR2X2TS U4088 ( .A(n2546), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(n5377) );
INVX2TS U4089 ( .A(n2506), .Y(n2529) );
INVX2TS U4090 ( .A(n2528), .Y(n2507) );
AOI21X1TS U4091 ( .A0(n2531), .A1(n2529), .B0(n2507), .Y(n2512) );
NAND2X1TS U4092 ( .A(n2510), .B(n2509), .Y(n2511) );
XOR2X1TS U4093 ( .A(n2512), .B(n2511), .Y(n2545) );
NOR2X2TS U4094 ( .A(n2545), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(n5375) );
NOR2X1TS U4095 ( .A(n5377), .B(n5375), .Y(n2548) );
INVX1TS U4096 ( .A(n2513), .Y(n2515) );
NAND2X1TS U4097 ( .A(n2515), .B(n2514), .Y(n2517) );
NAND2X1TS U4098 ( .A(n2519), .B(n2518), .Y(n2521) );
XNOR2X1TS U4099 ( .A(n2521), .B(n2520), .Y(n5407) );
NAND2X1TS U4100 ( .A(n5407), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(n5408) );
NAND2X1TS U4101 ( .A(n2522), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(n5346) );
OAI21X1TS U4102 ( .A0(n5345), .A1(n5408), .B0(n5346), .Y(n5404) );
INVX2TS U4103 ( .A(n2523), .Y(n2534) );
INVX2TS U4104 ( .A(n2533), .Y(n2524) );
NAND2X1TS U4105 ( .A(n2524), .B(n2532), .Y(n2525) );
XOR2X1TS U4106 ( .A(n2534), .B(n2525), .Y(n2526) );
NAND2X1TS U4107 ( .A(n2526), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(n5403) );
INVX2TS U4108 ( .A(n5403), .Y(n2527) );
AOI21X1TS U4109 ( .A0(n5404), .A1(n2350), .B0(n2527), .Y(n5354) );
NAND2X1TS U4110 ( .A(n2529), .B(n2528), .Y(n2530) );
XNOR2X1TS U4111 ( .A(n2531), .B(n2530), .Y(n2541) );
OAI21X1TS U4112 ( .A0(n2534), .A1(n2533), .B0(n2532), .Y(n2539) );
INVX2TS U4113 ( .A(n2535), .Y(n2537) );
NAND2X1TS U4114 ( .A(n2537), .B(n2536), .Y(n2538) );
XNOR2X1TS U4115 ( .A(n2539), .B(n2538), .Y(n2540) );
NAND2X1TS U4116 ( .A(n2321), .B(n2320), .Y(n2544) );
NAND2X1TS U4117 ( .A(n2540), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(n5355) );
INVX2TS U4118 ( .A(n5355), .Y(n5358) );
NAND2X1TS U4119 ( .A(n2541), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(n5360) );
INVX2TS U4120 ( .A(n5360), .Y(n2542) );
AOI21X1TS U4121 ( .A0(n2321), .A1(n5358), .B0(n2542), .Y(n2543) );
OAI21X1TS U4122 ( .A0(n5354), .A1(n2544), .B0(n2543), .Y(n5350) );
NAND2X1TS U4123 ( .A(n2545), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(n5374) );
NAND2X1TS U4124 ( .A(n2546), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(n5378) );
OAI21X1TS U4125 ( .A0(n5377), .A1(n5374), .B0(n5378), .Y(n2547) );
AOI21X2TS U4126 ( .A0(n2548), .A1(n5350), .B0(n2547), .Y(n5365) );
INVX2TS U4127 ( .A(n2560), .Y(n2549) );
NAND2X1TS U4128 ( .A(n2549), .B(n2559), .Y(n2550) );
XOR2X1TS U4129 ( .A(n2561), .B(n2550), .Y(n2572) );
NOR2X2TS U4130 ( .A(n2572), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(n5368) );
NAND2X1TS U4131 ( .A(n2556), .B(n2555), .Y(n2557) );
NOR2X2TS U4132 ( .A(n5368), .B(n5366), .Y(n5388) );
OAI21X1TS U4133 ( .A0(n2561), .A1(n2560), .B0(n2559), .Y(n2566) );
CLKINVX1TS U4134 ( .A(n2562), .Y(n2564) );
NAND2X1TS U4135 ( .A(n2564), .B(n2563), .Y(n2565) );
XNOR2X1TS U4136 ( .A(n2566), .B(n2565), .Y(n2573) );
NOR2X2TS U4137 ( .A(n2573), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(n5394) );
NAND2X1TS U4138 ( .A(n2568), .B(n2567), .Y(n2569) );
XNOR2X1TS U4139 ( .A(n2570), .B(n2569), .Y(n2574) );
NOR2X2TS U4140 ( .A(n2574), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(n5396) );
NAND2X2TS U4141 ( .A(n5388), .B(n2576), .Y(n2578) );
NAND2X2TS U4142 ( .A(n2571), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(n5383) );
NAND2X1TS U4143 ( .A(n2572), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(n5369) );
NAND2X1TS U4144 ( .A(n2573), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(n5393) );
NAND2X1TS U4145 ( .A(n2574), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(n5397) );
OAI21X4TS U4146 ( .A0(n5365), .A1(n2578), .B0(n2577), .Y(n5213) );
NAND2X2TS U4147 ( .A(n2579), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .Y(n5309) );
NAND2X1TS U4148 ( .A(n2581), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n5286) );
NAND2X1TS U4149 ( .A(n2582), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n5275) );
OAI21X1TS U4150 ( .A0(n5274), .A1(n5286), .B0(n5275), .Y(n2583) );
AOI21X2TS U4151 ( .A0(n5269), .A1(n2584), .B0(n2583), .Y(n5214) );
NAND2X1TS U4152 ( .A(n2586), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n5247) );
NAND2X1TS U4153 ( .A(n2587), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n5233) );
NAND2X1TS U4154 ( .A(n2588), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n5223) );
OAI21X2TS U4155 ( .A0(n2592), .A1(n5214), .B0(n2591), .Y(n2593) );
AOI21X4TS U4156 ( .A0(n2594), .A1(n5213), .B0(n2593), .Y(n5100) );
INVX2TS U4157 ( .A(n2595), .Y(n2596) );
INVX2TS U4158 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .Y(
n5066) );
INVX2TS U4159 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(
n2607) );
CMPR32X2TS U4160 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]),
.B(n5074), .C(n2599), .CO(n2600), .S(n2472) );
INVX2TS U4161 ( .A(n2605), .Y(n2602) );
NAND2X1TS U4162 ( .A(n2601), .B(n2600), .Y(n2604) );
NAND2X1TS U4163 ( .A(n2602), .B(n2604), .Y(n2603) );
XOR2X1TS U4164 ( .A(n2606), .B(n2603), .Y(n2647) );
INVX2TS U4165 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[20]), .Y(
n3808) );
INVX2TS U4166 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(
n2615) );
CMPR32X2TS U4167 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]),
.B(n5066), .C(n2607), .CO(n2608), .S(n2601) );
NAND2X1TS U4168 ( .A(n2609), .B(n2608), .Y(n2611) );
NAND2X1TS U4169 ( .A(n2613), .B(n2611), .Y(n2610) );
NOR2X2TS U4170 ( .A(n2648), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n5190) );
INVX2TS U4171 ( .A(n2611), .Y(n2612) );
AOI21X4TS U4172 ( .A0(n2614), .A1(n2613), .B0(n2612), .Y(n2622) );
INVX2TS U4173 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .Y(
n5052) );
INVX2TS U4174 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(
n2623) );
CMPR32X2TS U4175 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]),
.B(n3808), .C(n2615), .CO(n2616), .S(n2609) );
NOR2X1TS U4176 ( .A(n2617), .B(n2616), .Y(n2621) );
INVX2TS U4177 ( .A(n2621), .Y(n2618) );
NAND2X1TS U4178 ( .A(n2617), .B(n2616), .Y(n2620) );
NAND2X1TS U4179 ( .A(n2618), .B(n2620), .Y(n2619) );
CLKXOR2X2TS U4180 ( .A(n2622), .B(n2619), .Y(n2649) );
NOR2X2TS U4181 ( .A(n2649), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n5176) );
INVX2TS U4182 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[22]), .Y(
n3805) );
INVX2TS U4183 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(
n2631) );
CMPR32X2TS U4184 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]),
.B(n5052), .C(n2623), .CO(n2624), .S(n2617) );
NAND2X1TS U4185 ( .A(n2625), .B(n2624), .Y(n2627) );
NAND2X1TS U4186 ( .A(n2629), .B(n2627), .Y(n2626) );
NOR2X2TS U4187 ( .A(n2650), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(n5162) );
NOR2X2TS U4188 ( .A(n5176), .B(n5162), .Y(n2652) );
NAND2X2TS U4189 ( .A(n5161), .B(n2652), .Y(n5111) );
INVX2TS U4190 ( .A(n2627), .Y(n2628) );
INVX2TS U4191 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[23]), .Y(
n2662) );
INVX2TS U4192 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .Y(
n2639) );
CMPR32X2TS U4193 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]),
.B(n3805), .C(n2631), .CO(n2632), .S(n2625) );
NOR2X1TS U4194 ( .A(n2633), .B(n2632), .Y(n2637) );
INVX2TS U4195 ( .A(n2637), .Y(n2634) );
NAND2X1TS U4196 ( .A(n2633), .B(n2632), .Y(n2636) );
NAND2X1TS U4197 ( .A(n2634), .B(n2636), .Y(n2635) );
CLKXOR2X2TS U4198 ( .A(n2638), .B(n2635), .Y(n2653) );
NOR2X2TS U4199 ( .A(n2653), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(n5149) );
CMPR32X2TS U4200 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]),
.B(n2662), .C(n2639), .CO(n2640), .S(n2633) );
NAND2X1TS U4201 ( .A(n2640), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]), .Y(n2642) );
NAND2X1TS U4202 ( .A(n2644), .B(n2642), .Y(n2641) );
XNOR2X4TS U4203 ( .A(n2645), .B(n2641), .Y(n2654) );
INVX2TS U4204 ( .A(n2642), .Y(n2643) );
AOI21X2TS U4205 ( .A0(n2645), .A1(n2644), .B0(n2643), .Y(n2646) );
XOR2X4TS U4206 ( .A(n2646), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]), .Y(n2655) );
NOR2X4TS U4207 ( .A(n2655), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(n5125) );
NAND2X2TS U4208 ( .A(n2647), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n5201) );
NAND2X1TS U4209 ( .A(n2648), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n5191) );
OAI21X1TS U4210 ( .A0(n5190), .A1(n5201), .B0(n5191), .Y(n5160) );
NAND2X1TS U4211 ( .A(n2650), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(n5163) );
OAI21X1TS U4212 ( .A0(n5162), .A1(n5177), .B0(n5163), .Y(n2651) );
AOI21X2TS U4213 ( .A0(n5160), .A1(n2652), .B0(n2651), .Y(n5112) );
NAND2X2TS U4214 ( .A(n2653), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(n5150) );
NAND2X1TS U4215 ( .A(n2654), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .Y(n5138) );
OAI21X2TS U4216 ( .A0(n5137), .A1(n5150), .B0(n5138), .Y(n5115) );
NAND2X2TS U4217 ( .A(n2655), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(n5126) );
OAI21X4TS U4218 ( .A0(n5112), .A1(n2659), .B0(n2658), .Y(n5101) );
OAI21X4TS U4219 ( .A0(n5100), .A1(n2661), .B0(n2660), .Y(n5092) );
NAND2X6TS U4220 ( .A(n5092), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[16]), .Y(n5083) );
NOR2X8TS U4221 ( .A(n5083), .B(n5082), .Y(n5075) );
NOR2X6TS U4222 ( .A(n5067), .B(n5066), .Y(n3809) );
NAND2X4TS U4223 ( .A(n3806), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[22]), .Y(n2663) );
XOR2X4TS U4224 ( .A(n2663), .B(n2662), .Y(n2666) );
NOR2X2TS U4225 ( .A(n5807), .B(FPMULT_FS_Module_state_reg[2]), .Y(n4194) );
NOR2X1TS U4226 ( .A(n3914), .B(n5851), .Y(n3903) );
NAND2X1TS U4227 ( .A(n3903), .B(FPMULT_FS_Module_state_reg[1]), .Y(n2665) );
NOR2X1TS U4228 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[0]), .Y(n2664) );
NAND2X2TS U4229 ( .A(n2665), .B(n3901), .Y(n5363) );
BUFX3TS U4230 ( .A(n5363), .Y(n5413) );
NOR2X2TS U4231 ( .A(mult_x_121_n223), .B(mult_x_121_n230), .Y(n3374) );
NOR2X2TS U4232 ( .A(mult_x_121_n231), .B(mult_x_121_n238), .Y(n3468) );
NOR2X2TS U4233 ( .A(mult_x_121_n252), .B(mult_x_121_n256), .Y(n3388) );
NOR2X2TS U4234 ( .A(mult_x_121_n257), .B(mult_x_121_n261), .Y(n3393) );
NOR2X1TS U4235 ( .A(n3388), .B(n3393), .Y(n2701) );
NAND2X2TS U4236 ( .A(n2177), .B(n3501), .Y(n3463) );
BUFX3TS U4237 ( .A(FPMULT_Op_MY[13]), .Y(n3497) );
XNOR2X1TS U4238 ( .A(n2177), .B(n3497), .Y(n2667) );
XNOR2X1TS U4239 ( .A(n2177), .B(FPMULT_Op_MY[14]), .Y(n2671) );
OAI22X1TS U4240 ( .A0(n3504), .A1(n2667), .B0(n2671), .B1(n2353), .Y(n2670)
);
NOR2BX1TS U4241 ( .AN(n3505), .B(n2223), .Y(n2669) );
NOR2X1TS U4242 ( .A(n2670), .B(n2669), .Y(n3414) );
OAI22X1TS U4243 ( .A0(n3504), .A1(n3505), .B0(n2667), .B1(n3501), .Y(n3465)
);
NAND2X1TS U4244 ( .A(n2668), .B(n3504), .Y(n3464) );
NAND2X1TS U4245 ( .A(n3465), .B(n3464), .Y(n3466) );
NAND2X1TS U4246 ( .A(n2670), .B(n2669), .Y(n3415) );
OAI21X1TS U4247 ( .A0(n3414), .A1(n3466), .B0(n3415), .Y(n3412) );
XNOR2X1TS U4248 ( .A(n2177), .B(n2168), .Y(n2679) );
OAI22X1TS U4249 ( .A0(n3504), .A1(n2671), .B0(n2679), .B1(n3501), .Y(n2682)
);
XOR2X1TS U4250 ( .A(n2224), .B(FPMULT_Op_MX[14]), .Y(n2672) );
XNOR2X1TS U4251 ( .A(n2224), .B(n3505), .Y(n2673) );
XNOR2X1TS U4252 ( .A(n2224), .B(n3497), .Y(n2680) );
OAI22X1TS U4253 ( .A0(n2273), .A1(n2673), .B0(n2680), .B1(n2222), .Y(n2681)
);
OAI22X1TS U4254 ( .A0(n2273), .A1(n2144), .B0(n2222), .B1(n2674), .Y(n2675)
);
INVX2TS U4255 ( .A(n3411), .Y(n2677) );
AOI21X1TS U4256 ( .A0(n3412), .A1(n2332), .B0(n2677), .Y(n3409) );
XOR2X1TS U4257 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[16]), .Y(n2781) );
INVX2TS U4258 ( .A(n2781), .Y(n2678) );
NOR2BX1TS U4259 ( .AN(n2300), .B(n2219), .Y(n2692) );
XNOR2X1TS U4260 ( .A(n2178), .B(n2125), .Y(n2688) );
OAI22X1TS U4261 ( .A0(n3463), .A1(n2679), .B0(n2688), .B1(n2353), .Y(n2691)
);
XNOR2X1TS U4262 ( .A(n2225), .B(FPMULT_Op_MY[14]), .Y(n2685) );
OAI22X1TS U4263 ( .A0(n2274), .A1(n2680), .B0(n2685), .B1(n2223), .Y(n2690)
);
NOR2X1TS U4264 ( .A(n2684), .B(n2683), .Y(n3406) );
NAND2X1TS U4265 ( .A(n2684), .B(n2683), .Y(n3407) );
XNOR2X1TS U4266 ( .A(n2224), .B(FPMULT_Op_MY[15]), .Y(n3460) );
OAI22X1TS U4267 ( .A0(n2274), .A1(n2685), .B0(n3460), .B1(n2222), .Y(n2698)
);
XOR2X1TS U4268 ( .A(n2196), .B(FPMULT_Op_MX[16]), .Y(n2686) );
XNOR2X1TS U4269 ( .A(n2197), .B(n2300), .Y(n2687) );
XNOR2X1TS U4270 ( .A(n2197), .B(n3497), .Y(n3454) );
OAI22X1TS U4271 ( .A0(n2276), .A1(n2687), .B0(n3454), .B1(n2219), .Y(n2697)
);
XNOR2X1TS U4272 ( .A(n2178), .B(n2170), .Y(n3462) );
OAI22X1TS U4273 ( .A0(n3504), .A1(n2688), .B0(n3462), .B1(n2353), .Y(n3511)
);
OAI22X1TS U4274 ( .A0(n3487), .A1(n2359), .B0(n2219), .B1(n2689), .Y(n3510)
);
CMPR32X2TS U4275 ( .A(n2692), .B(n2691), .C(n2690), .CO(n2693), .S(n2684) );
NAND2X1TS U4276 ( .A(n2694), .B(n2693), .Y(n3403) );
INVX2TS U4277 ( .A(n3403), .Y(n2695) );
CMPR32X2TS U4278 ( .A(n2698), .B(n2697), .C(n2696), .CO(n2699), .S(n2694) );
NAND2X1TS U4279 ( .A(mult_x_121_n262), .B(n2699), .Y(n3399) );
OAI21X4TS U4280 ( .A0(n3401), .A1(n3398), .B0(n3399), .Y(n3387) );
NAND2X1TS U4281 ( .A(mult_x_121_n257), .B(mult_x_121_n261), .Y(n3394) );
NAND2X1TS U4282 ( .A(mult_x_121_n252), .B(mult_x_121_n256), .Y(n3389) );
OAI21X1TS U4283 ( .A0(n3388), .A1(n3394), .B0(n3389), .Y(n2700) );
AOI21X4TS U4284 ( .A0(n2701), .A1(n3387), .B0(n2700), .Y(n3379) );
NAND2X1TS U4285 ( .A(n2347), .B(n2346), .Y(n2704) );
NAND2X1TS U4286 ( .A(mult_x_121_n245), .B(mult_x_121_n251), .Y(n3384) );
INVX2TS U4287 ( .A(n3384), .Y(n3380) );
NAND2X1TS U4288 ( .A(mult_x_121_n239), .B(mult_x_121_n244), .Y(n3381) );
INVX2TS U4289 ( .A(n3381), .Y(n2702) );
AOI21X1TS U4290 ( .A0(n2347), .A1(n3380), .B0(n2702), .Y(n2703) );
OAI21X4TS U4291 ( .A0(n3379), .A1(n2704), .B0(n2703), .Y(n3373) );
NAND2X1TS U4292 ( .A(mult_x_121_n223), .B(mult_x_121_n230), .Y(n3375) );
AOI21X4TS U4293 ( .A0(n2706), .A1(n3373), .B0(n2705), .Y(n3349) );
NOR2X2TS U4294 ( .A(mult_x_121_n204), .B(mult_x_121_n213), .Y(n3364) );
NOR2X2TS U4295 ( .A(mult_x_121_n196), .B(mult_x_121_n203), .Y(n3357) );
NOR2X2TS U4296 ( .A(mult_x_121_n188), .B(mult_x_121_n195), .Y(n3352) );
NAND2X2TS U4297 ( .A(mult_x_121_n214), .B(mult_x_121_n222), .Y(n3369) );
NAND2X1TS U4298 ( .A(mult_x_121_n204), .B(mult_x_121_n213), .Y(n3365) );
OAI21X1TS U4299 ( .A0(n3364), .A1(n3369), .B0(n3365), .Y(n3350) );
NAND2X1TS U4300 ( .A(mult_x_121_n188), .B(mult_x_121_n195), .Y(n3353) );
OAI21X1TS U4301 ( .A0(n3352), .A1(n3358), .B0(n3353), .Y(n2707) );
NOR2X2TS U4302 ( .A(mult_x_121_n182), .B(mult_x_121_n187), .Y(n3344) );
NOR2X2TS U4303 ( .A(mult_x_121_n181), .B(mult_x_121_n175), .Y(n3339) );
NOR2X2TS U4304 ( .A(n3344), .B(n3339), .Y(n3331) );
NAND2X2TS U4305 ( .A(n3331), .B(n3336), .Y(n3325) );
NOR2X2TS U4306 ( .A(mult_x_121_n169), .B(mult_x_121_n165), .Y(n3326) );
NOR2X1TS U4307 ( .A(n3325), .B(n3326), .Y(n2713) );
NAND2X1TS U4308 ( .A(mult_x_121_n181), .B(mult_x_121_n175), .Y(n3340) );
OAI21X2TS U4309 ( .A0(n3345), .A1(n3339), .B0(n3340), .Y(n3332) );
NAND2X1TS U4310 ( .A(mult_x_121_n174), .B(mult_x_121_n170), .Y(n3335) );
INVX2TS U4311 ( .A(n3335), .Y(n2711) );
NAND2X1TS U4312 ( .A(mult_x_121_n169), .B(mult_x_121_n165), .Y(n3327) );
AOI21X4TS U4313 ( .A0(n3323), .A1(n2713), .B0(n2712), .Y(n3322) );
NOR2X1TS U4314 ( .A(mult_x_121_n162), .B(mult_x_121_n164), .Y(n3318) );
NAND2X1TS U4315 ( .A(mult_x_121_n162), .B(mult_x_121_n164), .Y(n3319) );
OAI21X4TS U4316 ( .A0(n3322), .A1(n3318), .B0(n3319), .Y(n3317) );
NAND2X1TS U4317 ( .A(mult_x_121_n161), .B(n2714), .Y(n3314) );
INVX2TS U4318 ( .A(n3314), .Y(n2715) );
AOI21X4TS U4319 ( .A0(n3317), .A1(n3315), .B0(n2715), .Y(n2722) );
CMPR32X2TS U4320 ( .A(n2334), .B(n2142), .C(mult_x_121_n160), .CO(n2718),
.S(n2714) );
XNOR2X1TS U4321 ( .A(n2716), .B(n5039), .Y(n2717) );
NAND2X1TS U4322 ( .A(n2718), .B(n2717), .Y(n2719) );
NAND2X1TS U4323 ( .A(n2720), .B(n2719), .Y(n2721) );
XOR2X2TS U4324 ( .A(n2722), .B(n2721), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23) );
NOR2X2TS U4325 ( .A(DP_OP_498J12_123_5135_n356), .B(
DP_OP_498J12_123_5135_n360), .Y(n2723) );
INVX2TS U4326 ( .A(n2723), .Y(n3555) );
NAND2X2TS U4327 ( .A(n3555), .B(n2355), .Y(n2807) );
NOR2X2TS U4328 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[1]), .Y(n2730) );
NAND2X2TS U4329 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n2734) );
NAND2X2TS U4330 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[1]), .Y(n2731) );
OAI21X4TS U4331 ( .A0(n2730), .A1(n2734), .B0(n2731), .Y(n2771) );
INVX2TS U4332 ( .A(n2771), .Y(n2754) );
INVX2TS U4333 ( .A(n2765), .Y(n2724) );
NAND2X2TS U4334 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n2767) );
NAND2X1TS U4335 ( .A(n2724), .B(n2767), .Y(n2725) );
CLKXOR2X4TS U4336 ( .A(n2754), .B(n2725), .Y(n3765) );
XNOR2X1TS U4337 ( .A(n2736), .B(n2726), .Y(n2727) );
XNOR2X1TS U4338 ( .A(n3765), .B(n3692), .Y(n2758) );
XOR2X1TS U4339 ( .A(n2353), .B(n2736), .Y(n2729) );
AND2X2TS U4340 ( .A(n2729), .B(n3699), .Y(n2740) );
INVX2TS U4341 ( .A(n2740), .Y(n3695) );
INVX2TS U4342 ( .A(n2730), .Y(n2732) );
CLKXOR2X4TS U4343 ( .A(n2733), .B(n2734), .Y(n3720) );
XNOR2X1TS U4344 ( .A(n3720), .B(n3692), .Y(n2741) );
OAI22X1TS U4345 ( .A0(n2758), .A1(n3699), .B0(n3695), .B1(n2741), .Y(n2744)
);
NOR2X1TS U4346 ( .A(n2157), .B(FPMULT_Op_MX[13]), .Y(n2735) );
XNOR2X1TS U4347 ( .A(n2746), .B(n2735), .Y(n2738) );
NAND2X1TS U4348 ( .A(n2736), .B(n2726), .Y(n2737) );
NOR2BX1TS U4349 ( .AN(n2241), .B(n3709), .Y(n2743) );
INVX2TS U4350 ( .A(n2740), .Y(n3697) );
NAND2BX1TS U4351 ( .AN(n2242), .B(n3692), .Y(n2742) );
NAND2X1TS U4352 ( .A(n2742), .B(n3697), .Y(n3700) );
NAND2X1TS U4353 ( .A(n3701), .B(n3700), .Y(n3702) );
INVX2TS U4354 ( .A(n3702), .Y(n3578) );
NAND2X1TS U4355 ( .A(n2744), .B(n2743), .Y(n3577) );
INVX2TS U4356 ( .A(n3577), .Y(n2745) );
AOI21X2TS U4357 ( .A0(n2333), .A1(n3578), .B0(n2745), .Y(n3575) );
NOR2X1TS U4358 ( .A(n2747), .B(n2746), .Y(n2748) );
XNOR2X2TS U4359 ( .A(FPMULT_Op_MX[15]), .B(n2267), .Y(n2763) );
XOR2X1TS U4360 ( .A(n2748), .B(n2763), .Y(n2749) );
NAND2X1TS U4361 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2750) );
NAND2X2TS U4362 ( .A(n2751), .B(n2750), .Y(n2762) );
INVX2TS U4363 ( .A(n2285), .Y(n3708) );
NAND2BX1TS U4364 ( .AN(n2242), .B(n2285), .Y(n2752) );
OAI22X1TS U4365 ( .A0(n3710), .A1(n3708), .B0(n3709), .B1(n2752), .Y(n2775)
);
XNOR2X1TS U4366 ( .A(n2286), .B(n2242), .Y(n2753) );
XNOR2X1TS U4367 ( .A(n3720), .B(n2285), .Y(n2764) );
OAI22X1TS U4368 ( .A0(n3710), .A1(n2753), .B0(n2764), .B1(n2293), .Y(n2774)
);
OAI21X1TS U4369 ( .A0(n2754), .A1(n2765), .B0(n2767), .Y(n2757) );
INVX2TS U4370 ( .A(n2768), .Y(n2755) );
NAND2X2TS U4371 ( .A(n2168), .B(FPMULT_Op_MY[3]), .Y(n2766) );
XNOR2X4TS U4372 ( .A(n2757), .B(n2756), .Y(n3664) );
XNOR2X1TS U4373 ( .A(n3664), .B(n3692), .Y(n2773) );
OAI22X1TS U4374 ( .A0(n2773), .A1(n3699), .B0(n2758), .B1(n3697), .Y(n2759)
);
NOR2X1TS U4375 ( .A(n2760), .B(n2759), .Y(n3572) );
NAND2X1TS U4376 ( .A(n2760), .B(n2759), .Y(n3573) );
NOR2X1TS U4377 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[3]), .Y(n2761) );
NOR2BX1TS U4378 ( .AN(n2241), .B(n3734), .Y(n2791) );
XNOR2X1TS U4379 ( .A(n3765), .B(n2285), .Y(n2779) );
OAI22X1TS U4380 ( .A0(n2779), .A1(n3709), .B0(n3710), .B1(n2764), .Y(n2790)
);
NOR2X2TS U4381 ( .A(n2765), .B(n2768), .Y(n2770) );
OAI21X2TS U4382 ( .A0(n2768), .A1(n2767), .B0(n2766), .Y(n2769) );
AOI21X4TS U4383 ( .A0(n2771), .A1(n2770), .B0(n2769), .Y(n2966) );
INVX4TS U4384 ( .A(n2966), .Y(n3603) );
NOR2X2TS U4385 ( .A(n2169), .B(FPMULT_Op_MY[4]), .Y(n2958) );
INVX2TS U4386 ( .A(n2958), .Y(n2793) );
NAND2X2TS U4387 ( .A(n2169), .B(FPMULT_Op_MY[4]), .Y(n2960) );
XNOR2X4TS U4388 ( .A(n3603), .B(n2772), .Y(n3676) );
XNOR2X1TS U4389 ( .A(n3676), .B(n3692), .Y(n2797) );
OAI22X1TS U4390 ( .A0(n2797), .A1(n3699), .B0(n2773), .B1(n3697), .Y(n2789)
);
NAND2X1TS U4391 ( .A(n2777), .B(n2776), .Y(n3569) );
INVX2TS U4392 ( .A(n3569), .Y(n2778) );
AOI21X4TS U4393 ( .A0(n3570), .A1(n2357), .B0(n2778), .Y(n3567) );
XNOR2X1TS U4394 ( .A(n3664), .B(n2285), .Y(n3678) );
OAI22X1TS U4395 ( .A0(n3678), .A1(n3709), .B0(n2779), .B1(n2191), .Y(n2802)
);
NOR2X1TS U4396 ( .A(n2781), .B(n2780), .Y(n2782) );
XNOR2X2TS U4397 ( .A(FPMULT_Op_MX[17]), .B(n2159), .Y(n3587) );
XOR2X1TS U4398 ( .A(n2782), .B(n3587), .Y(n2783) );
OAI21X1TS U4399 ( .A0(FPMULT_Op_MX[4]), .A1(FPMULT_Op_MX[16]), .B0(
FPMULT_Op_MX[3]), .Y(n2785) );
NAND2X1TS U4400 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .Y(n2784) );
NAND2X2TS U4401 ( .A(n2785), .B(n2784), .Y(n3586) );
XNOR2X1TS U4402 ( .A(n3587), .B(n3586), .Y(n2786) );
INVX2TS U4403 ( .A(n2287), .Y(n3655) );
NAND2BX1TS U4404 ( .AN(n2242), .B(n2287), .Y(n2787) );
OAI22X1TS U4405 ( .A0(n2119), .A1(n3655), .B0(n3734), .B1(n2787), .Y(n3782)
);
XNOR2X1TS U4406 ( .A(n3665), .B(n2241), .Y(n2788) );
XNOR2X1TS U4407 ( .A(n3720), .B(n3665), .Y(n3666) );
OAI22X1TS U4408 ( .A0(n2118), .A1(n2788), .B0(n3666), .B1(n3734), .Y(n3781)
);
CMPR32X2TS U4409 ( .A(n2791), .B(n2790), .C(n2789), .CO(n2800), .S(n2777) );
INVX2TS U4410 ( .A(n2960), .Y(n2792) );
AOI21X1TS U4411 ( .A0(n3603), .A1(n2793), .B0(n2792), .Y(n2796) );
INVX2TS U4412 ( .A(n2961), .Y(n2794) );
NAND2X1TS U4413 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n2959) );
NAND2X1TS U4414 ( .A(n2794), .B(n2959), .Y(n2795) );
CLKXOR2X4TS U4415 ( .A(n2796), .B(n2795), .Y(n3674) );
XNOR2X1TS U4416 ( .A(n3674), .B(n2275), .Y(n3698) );
OAI22X1TS U4417 ( .A0(n3698), .A1(n2284), .B0(n2797), .B1(n3695), .Y(n2798)
);
NOR2X2TS U4418 ( .A(n2799), .B(n2798), .Y(n3564) );
NAND2X1TS U4419 ( .A(n2799), .B(n2798), .Y(n3565) );
NAND2X1TS U4420 ( .A(DP_OP_498J12_123_5135_n366), .B(n2803), .Y(n3561) );
INVX2TS U4421 ( .A(n3561), .Y(n2804) );
AOI21X4TS U4422 ( .A0(n3562), .A1(n2358), .B0(n2804), .Y(n3552) );
INVX2TS U4423 ( .A(n3554), .Y(n2805) );
AOI21X4TS U4424 ( .A0(n3555), .A1(n3553), .B0(n2805), .Y(n2806) );
INVX2TS U4425 ( .A(n3549), .Y(n2809) );
AOI21X4TS U4426 ( .A0(n3551), .A1(n2808), .B0(n2809), .Y(n3539) );
OR2X4TS U4427 ( .A(DP_OP_498J12_123_5135_n335), .B(
DP_OP_498J12_123_5135_n342), .Y(n3542) );
NOR2X2TS U4428 ( .A(DP_OP_498J12_123_5135_n343), .B(
DP_OP_498J12_123_5135_n348), .Y(n2810) );
INVX2TS U4429 ( .A(n2810), .Y(n3546) );
NAND2X2TS U4430 ( .A(n3542), .B(n3546), .Y(n2813) );
NAND2X2TS U4431 ( .A(DP_OP_498J12_123_5135_n343), .B(
DP_OP_498J12_123_5135_n348), .Y(n3545) );
INVX2TS U4432 ( .A(n3545), .Y(n3540) );
NAND2X2TS U4433 ( .A(DP_OP_498J12_123_5135_n335), .B(
DP_OP_498J12_123_5135_n342), .Y(n3541) );
INVX2TS U4434 ( .A(n3541), .Y(n2811) );
AOI21X2TS U4435 ( .A0(n3542), .A1(n3540), .B0(n2811), .Y(n2812) );
OAI21X4TS U4436 ( .A0(n3539), .A1(n2813), .B0(n2812), .Y(n3533) );
NOR2X4TS U4437 ( .A(DP_OP_498J12_123_5135_n319), .B(
DP_OP_498J12_123_5135_n326), .Y(n3534) );
NOR2X2TS U4438 ( .A(n3534), .B(n3713), .Y(n2815) );
NAND2X2TS U4439 ( .A(DP_OP_498J12_123_5135_n327), .B(
DP_OP_498J12_123_5135_n334), .Y(n3714) );
NAND2X2TS U4440 ( .A(DP_OP_498J12_123_5135_n319), .B(
DP_OP_498J12_123_5135_n326), .Y(n3535) );
OAI21X2TS U4441 ( .A0(n3534), .A1(n3714), .B0(n3535), .Y(n2814) );
AOI21X4TS U4442 ( .A0(n3533), .A1(n2815), .B0(n2814), .Y(n3035) );
NOR2X6TS U4443 ( .A(DP_OP_498J12_123_5135_n300), .B(
DP_OP_498J12_123_5135_n309), .Y(n3524) );
NOR2X4TS U4444 ( .A(n3524), .B(n3522), .Y(n3516) );
NOR2X4TS U4445 ( .A(DP_OP_498J12_123_5135_n293), .B(
DP_OP_498J12_123_5135_n299), .Y(n3517) );
NOR2X4TS U4446 ( .A(DP_OP_498J12_123_5135_n285), .B(
DP_OP_498J12_123_5135_n292), .Y(n3040) );
NOR2X4TS U4447 ( .A(n3517), .B(n3040), .Y(n2817) );
NAND2X2TS U4448 ( .A(n3516), .B(n2817), .Y(n2819) );
NAND2X2TS U4449 ( .A(DP_OP_498J12_123_5135_n300), .B(
DP_OP_498J12_123_5135_n309), .Y(n3525) );
OAI21X4TS U4450 ( .A0(n3524), .A1(n3529), .B0(n3525), .Y(n3515) );
NAND2X2TS U4451 ( .A(DP_OP_498J12_123_5135_n285), .B(
DP_OP_498J12_123_5135_n292), .Y(n3041) );
AOI21X4TS U4452 ( .A0(n3515), .A1(n2817), .B0(n2816), .Y(n2818) );
OAI21X4TS U4453 ( .A0(n3035), .A1(n2819), .B0(n2818), .Y(n3787) );
INVX2TS U4454 ( .A(n2956), .Y(n3513) );
INVX2TS U4455 ( .A(n3512), .Y(n2820) );
NOR2X4TS U4456 ( .A(DP_OP_498J12_123_5135_n278), .B(
DP_OP_498J12_123_5135_n272), .Y(n2996) );
INVX2TS U4457 ( .A(n2996), .Y(n2821) );
NAND2X2TS U4458 ( .A(DP_OP_498J12_123_5135_n278), .B(
DP_OP_498J12_123_5135_n272), .Y(n2995) );
AOI22X1TS U4459 ( .A0(FPADDSUB_intDX[25]), .A1(n5791), .B0(
FPADDSUB_intDX[24]), .B1(n2824), .Y(n2828) );
OAI21X1TS U4460 ( .A0(FPADDSUB_intDX[26]), .A1(n5805), .B0(n2825), .Y(n2884)
);
AOI211X1TS U4461 ( .A0(FPADDSUB_intDY[28]), .A1(n5780), .B0(n2831), .C0(
n2829), .Y(n2882) );
NOR3X1TS U4462 ( .A(n5780), .B(n2829), .C(FPADDSUB_intDY[28]), .Y(n2830) );
NOR2X1TS U4463 ( .A(n5784), .B(FPADDSUB_intDX[17]), .Y(n2869) );
NOR2X1TS U4464 ( .A(n5769), .B(FPADDSUB_intDX[11]), .Y(n2848) );
AOI21X1TS U4465 ( .A0(FPADDSUB_intDY[10]), .A1(n5809), .B0(n2848), .Y(n2853)
);
OAI2BB1X1TS U4466 ( .A0N(n5734), .A1N(FPADDSUB_intDY[5]), .B0(
FPADDSUB_intDX[4]), .Y(n2834) );
OAI22X1TS U4467 ( .A0(FPADDSUB_intDY[4]), .A1(n2834), .B0(n5734), .B1(
FPADDSUB_intDY[5]), .Y(n2845) );
OAI2BB1X1TS U4468 ( .A0N(n5735), .A1N(FPADDSUB_intDY[7]), .B0(
FPADDSUB_intDX[6]), .Y(n2835) );
OAI22X1TS U4469 ( .A0(FPADDSUB_intDY[6]), .A1(n2835), .B0(n5735), .B1(
FPADDSUB_intDY[7]), .Y(n2844) );
OAI211X1TS U4470 ( .A0(n5843), .A1(FPADDSUB_intDX[3]), .B0(n2838), .C0(n2837), .Y(n2841) );
AOI22X1TS U4471 ( .A0(FPADDSUB_intDY[7]), .A1(n5735), .B0(FPADDSUB_intDY[6]),
.B1(n5714), .Y(n2842) );
OAI32X1TS U4472 ( .A0(n2845), .A1(n2844), .A2(n2843), .B0(n2842), .B1(n2844),
.Y(n2863) );
OA22X1TS U4473 ( .A0(n5766), .A1(FPADDSUB_intDX[14]), .B0(n5718), .B1(
FPADDSUB_intDX[15]), .Y(n2860) );
OAI2BB2XLTS U4474 ( .B0(FPADDSUB_intDY[12]), .B1(n2847), .A0N(
FPADDSUB_intDX[13]), .A1N(n5781), .Y(n2859) );
AOI22X1TS U4475 ( .A0(FPADDSUB_intDX[11]), .A1(n5769), .B0(
FPADDSUB_intDX[10]), .B1(n2849), .Y(n2855) );
AOI21X1TS U4476 ( .A0(n2852), .A1(n2851), .B0(n2862), .Y(n2854) );
OAI2BB2XLTS U4477 ( .B0(FPADDSUB_intDY[14]), .B1(n2856), .A0N(
FPADDSUB_intDX[15]), .A1N(n5718), .Y(n2857) );
AOI211X1TS U4478 ( .A0(n2860), .A1(n2859), .B0(n2858), .C0(n2857), .Y(n2861)
);
OAI31X1TS U4479 ( .A0(n2864), .A1(n2863), .A2(n2862), .B0(n2861), .Y(n2867)
);
OA22X1TS U4480 ( .A0(n5722), .A1(FPADDSUB_intDX[22]), .B0(n5816), .B1(
FPADDSUB_intDX[23]), .Y(n2880) );
OAI21X1TS U4481 ( .A0(FPADDSUB_intDX[18]), .A1(n5785), .B0(n2871), .Y(n2875)
);
OAI2BB2XLTS U4482 ( .B0(FPADDSUB_intDY[20]), .B1(n2868), .A0N(
FPADDSUB_intDX[21]), .A1N(n5782), .Y(n2879) );
AOI22X1TS U4483 ( .A0(FPADDSUB_intDX[17]), .A1(n5784), .B0(
FPADDSUB_intDX[16]), .B1(n2870), .Y(n2873) );
AOI32X1TS U4484 ( .A0(n5785), .A1(n2871), .A2(FPADDSUB_intDX[18]), .B0(
FPADDSUB_intDX[19]), .B1(n5723), .Y(n2872) );
OAI32X1TS U4485 ( .A0(n2875), .A1(n2874), .A2(n2873), .B0(n2872), .B1(n2874),
.Y(n2878) );
OAI2BB2XLTS U4486 ( .B0(FPADDSUB_intDY[22]), .B1(n2876), .A0N(
FPADDSUB_intDX[23]), .A1N(n5816), .Y(n2877) );
AOI211X1TS U4487 ( .A0(n2880), .A1(n2879), .B0(n2878), .C0(n2877), .Y(n2886)
);
NAND4BBX1TS U4488 ( .AN(n2884), .BN(n2883), .C(n2882), .D(n2881), .Y(n2885)
);
INVX2TS U4489 ( .A(n4468), .Y(n4437) );
INVX4TS U4490 ( .A(n2235), .Y(n4634) );
AOI22X1TS U4491 ( .A0(FPADDSUB_DmP[16]), .A1(n4640), .B0(FPADDSUB_intDY[16]),
.B1(n4634), .Y(n2890) );
NOR2X2TS U4492 ( .A(mult_x_159_n206), .B(mult_x_159_n215), .Y(n3138) );
NOR2X2TS U4493 ( .A(mult_x_159_n198), .B(mult_x_159_n205), .Y(n3131) );
NOR2X2TS U4494 ( .A(mult_x_159_n190), .B(mult_x_159_n197), .Y(n3126) );
NOR2X2TS U4495 ( .A(n3131), .B(n3126), .Y(n2933) );
NAND2X2TS U4496 ( .A(n3125), .B(n2933), .Y(n2935) );
OR2X2TS U4497 ( .A(mult_x_159_n241), .B(mult_x_159_n246), .Y(n3156) );
NAND2X1TS U4498 ( .A(n3156), .B(n2327), .Y(n2929) );
NOR2X2TS U4499 ( .A(mult_x_159_n254), .B(mult_x_159_n258), .Y(n3163) );
NOR2X2TS U4500 ( .A(mult_x_159_n259), .B(mult_x_159_n263), .Y(n3168) );
NOR2X1TS U4501 ( .A(n3163), .B(n3168), .Y(n2926) );
XOR2X1TS U4502 ( .A(FPMULT_Op_MY[2]), .B(n2226), .Y(n2891) );
XNOR2X1TS U4503 ( .A(n2227), .B(FPMULT_Op_MX[2]), .Y(n2896) );
XNOR2X1TS U4504 ( .A(n2227), .B(FPMULT_Op_MX[3]), .Y(n3235) );
OAI22X1TS U4505 ( .A0(n2279), .A1(n2896), .B0(n2220), .B1(n3235), .Y(n2923)
);
XOR2X1TS U4506 ( .A(FPMULT_Op_MY[4]), .B(n2228), .Y(n2893) );
XNOR2X1TS U4507 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[3]), .Y(n2892) );
XNOR2X1TS U4508 ( .A(n2228), .B(n3306), .Y(n2894) );
XNOR2X1TS U4509 ( .A(n2229), .B(n2124), .Y(n3228) );
OAI22X1TS U4510 ( .A0(n3290), .A1(n2894), .B0(n2211), .B1(n3228), .Y(n2922)
);
INVX2TS U4511 ( .A(n2228), .Y(n3222) );
OAI22X1TS U4512 ( .A0(n3290), .A1(n3222), .B0(n2211), .B1(n2895), .Y(n2955)
);
NAND2X2TS U4513 ( .A(n2187), .B(n2323), .Y(n3237) );
XNOR2X1TS U4514 ( .A(n2188), .B(n2158), .Y(n2897) );
XNOR2X1TS U4515 ( .A(n2188), .B(n2130), .Y(n3236) );
OAI22X1TS U4516 ( .A0(n3311), .A1(n2897), .B0(n3236), .B1(n2184), .Y(n2954)
);
NOR2BX1TS U4517 ( .AN(n2298), .B(n2211), .Y(n2900) );
XNOR2X1TS U4518 ( .A(n2227), .B(n2124), .Y(n2902) );
OAI22X1TS U4519 ( .A0(n3282), .A1(n2902), .B0(n2221), .B1(n2896), .Y(n2899)
);
XNOR2X1TS U4520 ( .A(n2188), .B(FPMULT_Op_MX[3]), .Y(n2911) );
OAI22X1TS U4521 ( .A0(n3311), .A1(n2911), .B0(n2897), .B1(n2184), .Y(n2898)
);
NOR2X4TS U4522 ( .A(n2918), .B(n2917), .Y(n3179) );
CMPR32X2TS U4523 ( .A(n2900), .B(n2899), .C(n2898), .CO(n2917), .S(n2916) );
OAI22X1TS U4524 ( .A0(n3282), .A1(n2138), .B0(n2221), .B1(n2901), .Y(n2910)
);
XNOR2X1TS U4525 ( .A(n2226), .B(n3306), .Y(n2903) );
OAI22X1TS U4526 ( .A0(n3282), .A1(n2903), .B0(n2220), .B1(n2902), .Y(n2909)
);
NOR2X2TS U4527 ( .A(n2916), .B(n2915), .Y(n3184) );
NOR2X1TS U4528 ( .A(n3179), .B(n3184), .Y(n2920) );
XNOR2X1TS U4529 ( .A(n2187), .B(n2124), .Y(n2904) );
XNOR2X1TS U4530 ( .A(n2187), .B(FPMULT_Op_MX[2]), .Y(n2912) );
OAI22X1TS U4531 ( .A0(n3237), .A1(n2904), .B0(n2912), .B1(n2323), .Y(n2907)
);
NOR2BX1TS U4532 ( .AN(n3306), .B(n2220), .Y(n2906) );
OAI22X1TS U4533 ( .A0(n3311), .A1(n3306), .B0(n2904), .B1(n2323), .Y(n3239)
);
NAND2X1TS U4534 ( .A(n2905), .B(n3311), .Y(n3238) );
NAND2X1TS U4535 ( .A(n3239), .B(n3238), .Y(n3240) );
INVX2TS U4536 ( .A(n3240), .Y(n3196) );
NAND2X1TS U4537 ( .A(n2907), .B(n2906), .Y(n3194) );
INVX2TS U4538 ( .A(n3194), .Y(n2908) );
AOI21X1TS U4539 ( .A0(n3195), .A1(n3196), .B0(n2908), .Y(n3192) );
ADDHX1TS U4540 ( .A(n2910), .B(n2909), .CO(n2915), .S(n2914) );
OAI22X1TS U4541 ( .A0(n3311), .A1(n2912), .B0(n2911), .B1(n2184), .Y(n2913)
);
NOR2X1TS U4542 ( .A(n2914), .B(n2913), .Y(n3189) );
NAND2X1TS U4543 ( .A(n2914), .B(n2913), .Y(n3190) );
OAI21X1TS U4544 ( .A0(n3192), .A1(n3189), .B0(n3190), .Y(n3178) );
NAND2X1TS U4545 ( .A(n2916), .B(n2915), .Y(n3185) );
NAND2X1TS U4546 ( .A(n2918), .B(n2917), .Y(n3180) );
OAI21X1TS U4547 ( .A0(n3179), .A1(n3185), .B0(n3180), .Y(n2919) );
NOR2X1TS U4548 ( .A(mult_x_159_n264), .B(n2924), .Y(n3173) );
NAND2X1TS U4549 ( .A(mult_x_159_n264), .B(n2924), .Y(n3174) );
OAI21X2TS U4550 ( .A0(n3176), .A1(n3173), .B0(n3174), .Y(n3162) );
NAND2X1TS U4551 ( .A(mult_x_159_n259), .B(mult_x_159_n263), .Y(n3169) );
NAND2X1TS U4552 ( .A(mult_x_159_n254), .B(mult_x_159_n258), .Y(n3164) );
OAI21X1TS U4553 ( .A0(n3163), .A1(n3169), .B0(n3164), .Y(n2925) );
NAND2X1TS U4554 ( .A(mult_x_159_n247), .B(mult_x_159_n253), .Y(n3159) );
INVX2TS U4555 ( .A(n3159), .Y(n3154) );
NAND2X1TS U4556 ( .A(mult_x_159_n241), .B(mult_x_159_n246), .Y(n3155) );
INVX2TS U4557 ( .A(n3155), .Y(n2927) );
AOI21X1TS U4558 ( .A0(n3156), .A1(n3154), .B0(n2927), .Y(n2928) );
OAI21X2TS U4559 ( .A0(n2929), .A1(n3153), .B0(n2928), .Y(n3147) );
NOR2X2TS U4560 ( .A(mult_x_159_n225), .B(mult_x_159_n232), .Y(n3148) );
NOR2X2TS U4561 ( .A(mult_x_159_n233), .B(mult_x_159_n240), .Y(n3248) );
NAND2X2TS U4562 ( .A(mult_x_159_n233), .B(mult_x_159_n240), .Y(n3249) );
NAND2X1TS U4563 ( .A(mult_x_159_n225), .B(mult_x_159_n232), .Y(n3149) );
OAI21X1TS U4564 ( .A0(n3148), .A1(n3249), .B0(n3149), .Y(n2930) );
AOI21X4TS U4565 ( .A0(n3147), .A1(n2931), .B0(n2930), .Y(n3123) );
NAND2X1TS U4566 ( .A(mult_x_159_n206), .B(mult_x_159_n215), .Y(n3139) );
NAND2X1TS U4567 ( .A(mult_x_159_n198), .B(mult_x_159_n205), .Y(n3132) );
NAND2X1TS U4568 ( .A(mult_x_159_n190), .B(mult_x_159_n197), .Y(n3127) );
OAI21X4TS U4569 ( .A0(n2935), .A1(n3123), .B0(n2934), .Y(n3097) );
NOR2X2TS U4570 ( .A(mult_x_159_n184), .B(mult_x_159_n189), .Y(n3118) );
NOR2X2TS U4571 ( .A(n3118), .B(n3113), .Y(n3105) );
NOR2X2TS U4572 ( .A(mult_x_159_n171), .B(mult_x_159_n167), .Y(n3100) );
NOR2X1TS U4573 ( .A(n3099), .B(n3100), .Y(n2938) );
NAND2X2TS U4574 ( .A(mult_x_159_n184), .B(mult_x_159_n189), .Y(n3119) );
NAND2X1TS U4575 ( .A(mult_x_159_n183), .B(mult_x_159_n177), .Y(n3114) );
NAND2X1TS U4576 ( .A(mult_x_159_n176), .B(mult_x_159_n172), .Y(n3109) );
INVX2TS U4577 ( .A(n3109), .Y(n2936) );
AOI21X1TS U4578 ( .A0(n3106), .A1(n3110), .B0(n2936), .Y(n3098) );
NAND2X1TS U4579 ( .A(mult_x_159_n171), .B(mult_x_159_n167), .Y(n3101) );
OAI21X2TS U4580 ( .A0(n3098), .A1(n3100), .B0(n3101), .Y(n2937) );
AOI21X4TS U4581 ( .A0(n3097), .A1(n2938), .B0(n2937), .Y(n3096) );
NOR2X1TS U4582 ( .A(mult_x_159_n166), .B(mult_x_159_n164), .Y(n3092) );
NAND2X1TS U4583 ( .A(mult_x_159_n166), .B(mult_x_159_n164), .Y(n3093) );
NOR2X1TS U4584 ( .A(n2204), .B(n2354), .Y(n2947) );
INVX2TS U4585 ( .A(n2947), .Y(n2944) );
XOR2X1TS U4586 ( .A(FPMULT_Op_MY[10]), .B(n2202), .Y(n2940) );
XNOR2X1TS U4587 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[9]), .Y(n2939) );
XNOR2X1TS U4588 ( .A(n2203), .B(n2303), .Y(n3199) );
OAI22X1TS U4589 ( .A0(n2186), .A1(n3199), .B0(n2216), .B1(n2204), .Y(n2943)
);
NAND2X1TS U4590 ( .A(mult_x_159_n163), .B(n2941), .Y(n3088) );
INVX2TS U4591 ( .A(n3088), .Y(n2942) );
CMPR32X2TS U4592 ( .A(n2944), .B(n2943), .C(mult_x_159_n162), .CO(n2949),
.S(n2941) );
NOR2X1TS U4593 ( .A(n2204), .B(n2322), .Y(n2946) );
NAND2X1TS U4594 ( .A(n2949), .B(n2948), .Y(n2950) );
NAND2X1TS U4595 ( .A(n2951), .B(n2950), .Y(n2952) );
NOR2X4TS U4596 ( .A(n2956), .B(n2996), .Y(n3047) );
NAND2X2TS U4597 ( .A(n2998), .B(n2957), .Y(n3046) );
NAND2X2TS U4598 ( .A(n3047), .B(n3000), .Y(n3783) );
INVX2TS U4599 ( .A(n2989), .Y(n2983) );
NOR2X2TS U4600 ( .A(n2958), .B(n2961), .Y(n3595) );
NAND2X1TS U4601 ( .A(n2167), .B(FPMULT_Op_MY[7]), .Y(n3605) );
AOI21X2TS U4602 ( .A0(n3597), .A1(n2963), .B0(n2962), .Y(n2964) );
OAI21X4TS U4603 ( .A0(n2966), .A1(n2965), .B0(n2964), .Y(n3624) );
NAND2X1TS U4604 ( .A(n2166), .B(FPMULT_Op_MY[9]), .Y(n3616) );
NAND2X1TS U4605 ( .A(n2988), .B(DP_OP_498J12_123_5135_n727), .Y(n2967) );
INVX6TS U4606 ( .A(n3061), .Y(n3680) );
OAI21X1TS U4607 ( .A0(FPMULT_Op_MX[10]), .A1(FPMULT_Op_MX[22]), .B0(
FPMULT_Op_MX[9]), .Y(n2970) );
NAND2X1TS U4608 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .Y(n2969) );
XNOR2X1TS U4609 ( .A(n3680), .B(n2292), .Y(n3628) );
XOR2X1TS U4610 ( .A(FPMULT_Op_MX[21]), .B(n2121), .Y(n2972) );
XOR2X1TS U4611 ( .A(n2973), .B(n2303), .Y(n2981) );
NOR2X1TS U4612 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .Y(n2974) );
XNOR2X2TS U4613 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .Y(n3072) );
NAND2X1TS U4614 ( .A(n2161), .B(FPMULT_Op_MX[20]), .Y(n2976) );
OAI22X1TS U4615 ( .A0(n3628), .A1(n3771), .B0(n2297), .B1(n3719), .Y(n3059)
);
INVX2TS U4616 ( .A(n3059), .Y(n3005) );
NAND2X1TS U4617 ( .A(n2983), .B(n2988), .Y(n2984) );
CLKXOR2X4TS U4618 ( .A(n2985), .B(n2984), .Y(n3684) );
INVX2TS U4619 ( .A(n3684), .Y(n3620) );
INVX2TS U4620 ( .A(n2987), .Y(n2990) );
CLKXOR2X4TS U4621 ( .A(n2993), .B(FPMULT_Op_MY[11]), .Y(n3682) );
INVX2TS U4622 ( .A(n3682), .Y(n3006) );
OAI22X1TS U4623 ( .A0(n3620), .A1(n2180), .B0(n3006), .B1(n2271), .Y(n3004)
);
NOR2X2TS U4624 ( .A(DP_OP_498J12_123_5135_n258), .B(n3001), .Y(n3045) );
OAI21X4TS U4625 ( .A0(n3512), .A1(n2996), .B0(n2995), .Y(n3057) );
NAND2X2TS U4626 ( .A(DP_OP_498J12_123_5135_n271), .B(
DP_OP_498J12_123_5135_n267), .Y(n3017) );
NAND2X2TS U4627 ( .A(DP_OP_498J12_123_5135_n266), .B(
DP_OP_498J12_123_5135_n262), .Y(n3751) );
NAND2X1TS U4628 ( .A(DP_OP_498J12_123_5135_n259), .B(
DP_OP_498J12_123_5135_n261), .Y(n3758) );
INVX2TS U4629 ( .A(n3054), .Y(n2999) );
AOI21X4TS U4630 ( .A0(n3057), .A1(n3000), .B0(n2999), .Y(n3784) );
OAI21X1TS U4631 ( .A0(n3784), .A1(n3045), .B0(n3788), .Y(n3002) );
AOI21X2TS U4632 ( .A0(n3756), .A1(n3003), .B0(n3002), .Y(n3010) );
CMPR32X2TS U4633 ( .A(n3005), .B(n3004), .C(DP_OP_498J12_123_5135_n257),
.CO(n3008), .S(n3001) );
OAI22X1TS U4634 ( .A0(n3006), .A1(n2180), .B0(n3061), .B1(n2271), .Y(n3058)
);
NAND2X1TS U4635 ( .A(n3008), .B(n3007), .Y(n3048) );
NAND2X1TS U4636 ( .A(n3050), .B(n3048), .Y(n3009) );
INVX2TS U4637 ( .A(n3750), .Y(n3013) );
AOI21X2TS U4638 ( .A0(n3057), .A1(n2957), .B0(n3011), .Y(n3753) );
INVX2TS U4639 ( .A(n3753), .Y(n3012) );
INVX2TS U4640 ( .A(n3752), .Y(n3014) );
AOI21X2TS U4641 ( .A0(n3756), .A1(n3047), .B0(n3057), .Y(n3019) );
NAND2X2TS U4642 ( .A(FPADDSUB_FS_Module_state_reg[3]), .B(n5719), .Y(n3898)
);
OR2X2TS U4643 ( .A(n3898), .B(FPADDSUB_FS_Module_state_reg[2]), .Y(n4862) );
INVX2TS U4644 ( .A(n4852), .Y(n3020) );
NOR2X2TS U4645 ( .A(n4851), .B(n3020), .Y(n4864) );
AND2X4TS U4646 ( .A(n4864), .B(n5773), .Y(n3027) );
NOR3X2TS U4647 ( .A(FPADDSUB_Add_Subt_result[17]), .B(
FPADDSUB_Add_Subt_result[16]), .C(FPADDSUB_Add_Subt_result[15]), .Y(
n3086) );
NOR3X2TS U4648 ( .A(FPADDSUB_Add_Subt_result[11]), .B(
FPADDSUB_Add_Subt_result[10]), .C(n4873), .Y(n4650) );
NOR3X2TS U4649 ( .A(FPADDSUB_Add_Subt_result[7]), .B(
FPADDSUB_Add_Subt_result[6]), .C(n4646), .Y(n4856) );
NOR2BX1TS U4650 ( .AN(FPADDSUB_Add_Subt_result[4]), .B(n3021), .Y(n4648) );
AOI211X1TS U4651 ( .A0(n5819), .A1(n3022), .B0(FPADDSUB_Add_Subt_result[3]),
.C0(n4644), .Y(n3023) );
AOI21X1TS U4652 ( .A0(n5817), .A1(FPADDSUB_Add_Subt_result[20]), .B0(
FPADDSUB_Add_Subt_result[22]), .Y(n3024) );
NAND2X1TS U4653 ( .A(n4871), .B(n4857), .Y(n3083) );
NOR2X1TS U4654 ( .A(FPADDSUB_Add_Subt_result[11]), .B(
FPADDSUB_Add_Subt_result[10]), .Y(n4874) );
NAND4X1TS U4655 ( .A(n4860), .B(n3032), .C(n3031), .D(n3030), .Y(n3033) );
INVX2TS U4656 ( .A(n4876), .Y(n4875) );
XNOR2X1TS U4657 ( .A(n2202), .B(n2268), .Y(n3208) );
XNOR2X1TS U4658 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[3]), .Y(n3207) );
INVX4TS U4659 ( .A(n3035), .Y(n3532) );
INVX2TS U4660 ( .A(n3516), .Y(n3036) );
NOR2X1TS U4661 ( .A(n3036), .B(n3517), .Y(n3039) );
INVX2TS U4662 ( .A(n3515), .Y(n3037) );
OAI21X1TS U4663 ( .A0(n3037), .A1(n3517), .B0(n3518), .Y(n3038) );
AOI21X1TS U4664 ( .A0(n3532), .A1(n3039), .B0(n3038), .Y(n3044) );
INVX2TS U4665 ( .A(n3040), .Y(n3042) );
NAND2X1TS U4666 ( .A(n3042), .B(n3041), .Y(n3043) );
INVX2TS U4667 ( .A(n3045), .Y(n3789) );
NOR2X2TS U4668 ( .A(n3046), .B(n3053), .Y(n3056) );
INVX2TS U4669 ( .A(n3788), .Y(n3051) );
INVX2TS U4670 ( .A(n3048), .Y(n3049) );
AOI21X1TS U4671 ( .A0(n3051), .A1(n3050), .B0(n3049), .Y(n3052) );
OAI21X1TS U4672 ( .A0(n3054), .A1(n3053), .B0(n3052), .Y(n3055) );
CMPR32X2TS U4673 ( .A(n3060), .B(n3059), .C(n3058), .CO(n3063), .S(n3007) );
NAND2X1TS U4674 ( .A(n3063), .B(n3062), .Y(n3064) );
NAND2X1TS U4675 ( .A(n3065), .B(n3064), .Y(n3066) );
INVX2TS U4676 ( .A(n3765), .Y(n3068) );
INVX2TS U4677 ( .A(n3720), .Y(n3770) );
INVX2TS U4678 ( .A(n3749), .Y(n3612) );
INVX2TS U4679 ( .A(n3664), .Y(n3711) );
OAI22X1TS U4680 ( .A0(n3711), .A1(n2271), .B0(n3068), .B1(n2994), .Y(n3070)
);
INVX2TS U4681 ( .A(n3692), .Y(n3681) );
XNOR2X1TS U4682 ( .A(n3676), .B(n2292), .Y(n3635) );
XNOR2X1TS U4683 ( .A(n3680), .B(n2291), .Y(n3637) );
NOR2X1TS U4684 ( .A(n3425), .B(n3075), .Y(n3073) );
XOR2X1TS U4685 ( .A(n3073), .B(n3072), .Y(n3081) );
NOR2X1TS U4686 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .Y(n3074) );
XNOR2X1TS U4687 ( .A(n3075), .B(n3074), .Y(n3079) );
XNOR2X2TS U4688 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .Y(n3582) );
OAI21X1TS U4689 ( .A0(FPMULT_Op_MX[6]), .A1(FPMULT_Op_MX[18]), .B0(n2159),
.Y(n3077) );
NAND2X1TS U4690 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .Y(n3076) );
INVX2TS U4691 ( .A(n2290), .Y(n3727) );
OAI22X2TS U4692 ( .A0(n3637), .A1(n2193), .B0(n2295), .B1(n3727), .Y(
DP_OP_498J12_123_5135_n263) );
XNOR2X1TS U4693 ( .A(n2203), .B(n2158), .Y(n3206) );
XNOR2X1TS U4694 ( .A(FPMULT_Op_MY[11]), .B(n2130), .Y(n3205) );
OA21XLTS U4695 ( .A0(FPADDSUB_Add_Subt_result[11]), .A1(
FPADDSUB_Add_Subt_result[13]), .B0(n3082), .Y(n4854) );
OAI21X1TS U4696 ( .A0(n3086), .A1(n3085), .B0(n3084), .Y(n3087) );
NAND2X1TS U4697 ( .A(n3089), .B(n3088), .Y(n3090) );
XNOR2X1TS U4698 ( .A(n3091), .B(n3090), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22) );
INVX2TS U4699 ( .A(n3092), .Y(n3094) );
NAND2X1TS U4700 ( .A(n3094), .B(n3093), .Y(n3095) );
INVX2TS U4701 ( .A(n3100), .Y(n3102) );
NAND2X1TS U4702 ( .A(n3102), .B(n3101), .Y(n3103) );
XNOR2X1TS U4703 ( .A(n3104), .B(n3103), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20) );
INVX2TS U4704 ( .A(n3105), .Y(n3108) );
INVX2TS U4705 ( .A(n3106), .Y(n3107) );
NAND2X1TS U4706 ( .A(n3110), .B(n3109), .Y(n3111) );
XNOR2X1TS U4707 ( .A(n3112), .B(n3111), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19) );
INVX2TS U4708 ( .A(n3113), .Y(n3115) );
NAND2X1TS U4709 ( .A(n3115), .B(n3114), .Y(n3116) );
XNOR2X1TS U4710 ( .A(n3117), .B(n3116), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18) );
INVX2TS U4711 ( .A(n3118), .Y(n3120) );
NAND2X1TS U4712 ( .A(n3120), .B(n3119), .Y(n3121) );
INVX4TS U4713 ( .A(n3123), .Y(n3146) );
INVX2TS U4714 ( .A(n3126), .Y(n3128) );
NAND2X1TS U4715 ( .A(n3128), .B(n3127), .Y(n3129) );
XNOR2X1TS U4716 ( .A(n3130), .B(n3129), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16) );
INVX2TS U4717 ( .A(n3131), .Y(n3133) );
NAND2X1TS U4718 ( .A(n3133), .B(n3132), .Y(n3134) );
INVX2TS U4719 ( .A(n3136), .Y(n3144) );
INVX2TS U4720 ( .A(n3143), .Y(n3137) );
AOI21X1TS U4721 ( .A0(n3146), .A1(n3144), .B0(n3137), .Y(n3142) );
INVX2TS U4722 ( .A(n3138), .Y(n3140) );
NAND2X1TS U4723 ( .A(n3140), .B(n3139), .Y(n3141) );
NAND2X1TS U4724 ( .A(n3144), .B(n3143), .Y(n3145) );
XNOR2X1TS U4725 ( .A(n3146), .B(n3145), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13) );
INVX2TS U4726 ( .A(n3147), .Y(n3252) );
INVX2TS U4727 ( .A(n3148), .Y(n3150) );
NAND2X1TS U4728 ( .A(n3150), .B(n3149), .Y(n3151) );
XNOR2X1TS U4729 ( .A(n3152), .B(n3151), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12) );
INVX2TS U4730 ( .A(n3153), .Y(n3161) );
AOI21X1TS U4731 ( .A0(n3161), .A1(n2327), .B0(n3154), .Y(n3158) );
NAND2X1TS U4732 ( .A(n3156), .B(n3155), .Y(n3157) );
NAND2X1TS U4733 ( .A(n2327), .B(n3159), .Y(n3160) );
XNOR2X1TS U4734 ( .A(n3161), .B(n3160), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9) );
INVX2TS U4735 ( .A(n3162), .Y(n3172) );
INVX2TS U4736 ( .A(n3163), .Y(n3165) );
NAND2X1TS U4737 ( .A(n3165), .B(n3164), .Y(n3166) );
XNOR2X1TS U4738 ( .A(n3167), .B(n3166), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8) );
INVX2TS U4739 ( .A(n3168), .Y(n3170) );
NAND2X1TS U4740 ( .A(n3170), .B(n3169), .Y(n3171) );
INVX2TS U4741 ( .A(n3173), .Y(n3175) );
NAND2X1TS U4742 ( .A(n3175), .B(n3174), .Y(n3177) );
INVX2TS U4743 ( .A(n3178), .Y(n3188) );
INVX2TS U4744 ( .A(n3179), .Y(n3181) );
NAND2X1TS U4745 ( .A(n3181), .B(n3180), .Y(n3182) );
XNOR2X1TS U4746 ( .A(n3183), .B(n3182), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5) );
INVX2TS U4747 ( .A(n3184), .Y(n3186) );
NAND2X1TS U4748 ( .A(n3186), .B(n3185), .Y(n3187) );
INVX2TS U4749 ( .A(n3189), .Y(n3191) );
NAND2X1TS U4750 ( .A(n3191), .B(n3190), .Y(n3193) );
NAND2X1TS U4751 ( .A(n3195), .B(n3194), .Y(n3197) );
XNOR2X1TS U4752 ( .A(n3197), .B(n3196), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2) );
OAI22X1TS U4753 ( .A0(n2185), .A1(n2204), .B0(n2215), .B1(n3198), .Y(
mult_x_159_n273) );
XNOR2X1TS U4754 ( .A(n2203), .B(n2121), .Y(n3200) );
OAI22X1TS U4755 ( .A0(n2186), .A1(n3200), .B0(n2215), .B1(n3199), .Y(
mult_x_159_n288) );
XNOR2X1TS U4756 ( .A(n2203), .B(n2162), .Y(n3201) );
OAI22X1TS U4757 ( .A0(n2186), .A1(n3201), .B0(n2216), .B1(n3200), .Y(
mult_x_159_n289) );
XNOR2X1TS U4758 ( .A(n2203), .B(n2129), .Y(n3202) );
OAI22X1TS U4759 ( .A0(n2186), .A1(n3202), .B0(n2216), .B1(n3201), .Y(
mult_x_159_n290) );
XNOR2X1TS U4760 ( .A(n2203), .B(n2160), .Y(n3203) );
OAI22X1TS U4761 ( .A0(n2186), .A1(n3203), .B0(n2215), .B1(n3202), .Y(
mult_x_159_n291) );
BUFX3TS U4762 ( .A(FPMULT_Op_MX[6]), .Y(n5462) );
XNOR2X1TS U4763 ( .A(FPMULT_Op_MY[11]), .B(n5462), .Y(n3204) );
OAI22X1TS U4764 ( .A0(n2186), .A1(n3204), .B0(n2215), .B1(n3203), .Y(
mult_x_159_n292) );
OAI22X1TS U4765 ( .A0(n2186), .A1(n3205), .B0(n2215), .B1(n3204), .Y(
mult_x_159_n293) );
OAI22X1TS U4766 ( .A0(n2185), .A1(n3207), .B0(n2216), .B1(n3206), .Y(
mult_x_159_n295) );
XNOR2X1TS U4767 ( .A(n2203), .B(n2124), .Y(n3209) );
OAI22X1TS U4768 ( .A0(n2185), .A1(n3209), .B0(n2216), .B1(n3208), .Y(
mult_x_159_n297) );
XNOR2X1TS U4769 ( .A(n2203), .B(n2298), .Y(n3210) );
OAI22X1TS U4770 ( .A0(n2186), .A1(n3210), .B0(n2216), .B1(n3209), .Y(
mult_x_159_n298) );
NOR2BX1TS U4771 ( .AN(n2298), .B(n2939), .Y(mult_x_159_n299) );
XNOR2X1TS U4772 ( .A(n2195), .B(n2303), .Y(n3300) );
OAI22X1TS U4773 ( .A0(n2283), .A1(n3300), .B0(n2233), .B1(n2338), .Y(
mult_x_159_n301) );
XNOR2X1TS U4774 ( .A(n2194), .B(n2129), .Y(n3213) );
XNOR2X1TS U4775 ( .A(n2194), .B(n2162), .Y(n3273) );
OAI22X1TS U4776 ( .A0(n2282), .A1(n3213), .B0(n2232), .B1(n3273), .Y(
mult_x_159_n304) );
XNOR2X1TS U4777 ( .A(n2195), .B(n2160), .Y(n3214) );
OAI22X1TS U4778 ( .A0(n2283), .A1(n3214), .B0(n2233), .B1(n3213), .Y(
mult_x_159_n305) );
XNOR2X1TS U4779 ( .A(n2194), .B(n5462), .Y(n3215) );
OAI22X1TS U4780 ( .A0(n2283), .A1(n3215), .B0(n2232), .B1(n3214), .Y(
mult_x_159_n306) );
XNOR2X1TS U4781 ( .A(n2194), .B(n2130), .Y(n3268) );
OAI22X1TS U4782 ( .A0(n2282), .A1(n3268), .B0(n2232), .B1(n3215), .Y(
mult_x_159_n307) );
XNOR2X1TS U4783 ( .A(n2195), .B(n2124), .Y(n3242) );
XNOR2X1TS U4784 ( .A(n2195), .B(FPMULT_Op_MX[2]), .Y(n3295) );
OAI22X1TS U4785 ( .A0(n2283), .A1(n3242), .B0(n2233), .B1(n3295), .Y(
mult_x_159_n311) );
XOR2X1TS U4786 ( .A(FPMULT_Op_MY[6]), .B(n2230), .Y(n3216) );
XNOR2X1TS U4787 ( .A(n2231), .B(n2121), .Y(n3217) );
XNOR2X1TS U4788 ( .A(n2230), .B(n2303), .Y(n3274) );
OAI22X1TS U4789 ( .A0(n3308), .A1(n3217), .B0(n2212), .B1(n3274), .Y(
mult_x_159_n316) );
XNOR2X1TS U4790 ( .A(n2231), .B(n2162), .Y(n3260) );
OAI22X1TS U4791 ( .A0(n3308), .A1(n3260), .B0(n2213), .B1(n3217), .Y(
mult_x_159_n317) );
XNOR2X1TS U4792 ( .A(n2231), .B(n5462), .Y(n3218) );
XNOR2X1TS U4793 ( .A(n2231), .B(n2160), .Y(n3265) );
OAI22X1TS U4794 ( .A0(n3308), .A1(n3218), .B0(n2213), .B1(n3265), .Y(
mult_x_159_n320) );
XNOR2X1TS U4795 ( .A(FPMULT_Op_MY[7]), .B(n2130), .Y(n3219) );
OAI22X1TS U4796 ( .A0(n3308), .A1(n3219), .B0(n2212), .B1(n3218), .Y(
mult_x_159_n321) );
XNOR2X1TS U4797 ( .A(n2231), .B(n2158), .Y(n3220) );
OAI22X1TS U4798 ( .A0(n2281), .A1(n3220), .B0(n2212), .B1(n3219), .Y(
mult_x_159_n322) );
XNOR2X1TS U4799 ( .A(n2231), .B(FPMULT_Op_MX[3]), .Y(n3253) );
OAI22X1TS U4800 ( .A0(n3308), .A1(n3253), .B0(n2213), .B1(n3220), .Y(
mult_x_159_n323) );
XNOR2X1TS U4801 ( .A(n2231), .B(n2298), .Y(n3221) );
XNOR2X1TS U4802 ( .A(FPMULT_Op_MY[7]), .B(n2124), .Y(n3279) );
OAI22X1TS U4803 ( .A0(n2281), .A1(n3221), .B0(n2212), .B1(n3279), .Y(
mult_x_159_n326) );
NOR2BX1TS U4804 ( .AN(n2298), .B(n2213), .Y(mult_x_159_n327) );
XNOR2X1TS U4805 ( .A(n2228), .B(n2303), .Y(n3223) );
OAI22X1TS U4806 ( .A0(n3290), .A1(n3223), .B0(n2210), .B1(n3222), .Y(
mult_x_159_n329) );
XNOR2X1TS U4807 ( .A(n2229), .B(n2121), .Y(n3224) );
OAI22X1TS U4808 ( .A0(n3290), .A1(n3224), .B0(n2210), .B1(n3223), .Y(
mult_x_159_n330) );
XNOR2X1TS U4809 ( .A(n2229), .B(n2162), .Y(n3269) );
OAI22X1TS U4810 ( .A0(n3290), .A1(n3269), .B0(n2210), .B1(n3224), .Y(
mult_x_159_n331) );
XNOR2X1TS U4811 ( .A(n2229), .B(n5462), .Y(n3225) );
XNOR2X1TS U4812 ( .A(n2229), .B(n2160), .Y(n3289) );
OAI22X1TS U4813 ( .A0(n2280), .A1(n3225), .B0(n2210), .B1(n3289), .Y(
mult_x_159_n334) );
XNOR2X1TS U4814 ( .A(n2229), .B(n2130), .Y(n3255) );
OAI22X1TS U4815 ( .A0(n2280), .A1(n3255), .B0(n2210), .B1(n3225), .Y(
mult_x_159_n335) );
XNOR2X1TS U4816 ( .A(n2229), .B(FPMULT_Op_MX[3]), .Y(n3226) );
XNOR2X1TS U4817 ( .A(n2228), .B(n2158), .Y(n3256) );
OAI22X1TS U4818 ( .A0(n2280), .A1(n3226), .B0(n2211), .B1(n3256), .Y(
mult_x_159_n337) );
XNOR2X1TS U4819 ( .A(n2229), .B(n2268), .Y(n3227) );
OAI22X1TS U4820 ( .A0(n2280), .A1(n3227), .B0(n2210), .B1(n3226), .Y(
mult_x_159_n338) );
OAI22X1TS U4821 ( .A0(n3290), .A1(n3228), .B0(n2211), .B1(n3227), .Y(
mult_x_159_n339) );
XNOR2X1TS U4822 ( .A(n2227), .B(n2303), .Y(n3229) );
OAI22X1TS U4823 ( .A0(n3282), .A1(n3229), .B0(n2220), .B1(n2138), .Y(
mult_x_159_n343) );
XNOR2X1TS U4824 ( .A(n2226), .B(FPMULT_Op_MX[10]), .Y(n3230) );
OAI22X1TS U4825 ( .A0(n3282), .A1(n3230), .B0(n2220), .B1(n3229), .Y(
mult_x_159_n344) );
XNOR2X1TS U4826 ( .A(n2227), .B(n2162), .Y(n3231) );
OAI22X1TS U4827 ( .A0(n3282), .A1(n3231), .B0(n2220), .B1(n3230), .Y(
mult_x_159_n345) );
XNOR2X1TS U4828 ( .A(n2226), .B(n2129), .Y(n3232) );
OAI22X1TS U4829 ( .A0(n2279), .A1(n3232), .B0(n2221), .B1(n3231), .Y(
mult_x_159_n346) );
XNOR2X1TS U4830 ( .A(n2227), .B(n2160), .Y(n3233) );
OAI22X1TS U4831 ( .A0(n3282), .A1(n3233), .B0(n2221), .B1(n3232), .Y(
mult_x_159_n347) );
XNOR2X1TS U4832 ( .A(n2226), .B(n5462), .Y(n3280) );
OAI22X1TS U4833 ( .A0(n2279), .A1(n3280), .B0(n2220), .B1(n3233), .Y(
mult_x_159_n348) );
XNOR2X1TS U4834 ( .A(n2227), .B(n2158), .Y(n3234) );
XNOR2X1TS U4835 ( .A(n2226), .B(n2130), .Y(n3281) );
OAI22X1TS U4836 ( .A0(n2279), .A1(n3234), .B0(n2220), .B1(n3281), .Y(
mult_x_159_n350) );
OAI22X1TS U4837 ( .A0(n3282), .A1(n3235), .B0(n2221), .B1(n3234), .Y(
mult_x_159_n351) );
XNOR2X1TS U4838 ( .A(n2188), .B(n2303), .Y(n3296) );
OAI22X1TS U4839 ( .A0(n3237), .A1(n3296), .B0(n2184), .B1(n2336), .Y(
mult_x_159_n357) );
XNOR2X1TS U4840 ( .A(n2188), .B(n2162), .Y(n3244) );
XNOR2X1TS U4841 ( .A(n2188), .B(n2121), .Y(n3297) );
OAI22X1TS U4842 ( .A0(n3311), .A1(n3244), .B0(n3297), .B1(n2184), .Y(
mult_x_159_n359) );
XNOR2X1TS U4843 ( .A(n2188), .B(n2160), .Y(n3309) );
XNOR2X1TS U4844 ( .A(n2188), .B(n2129), .Y(n3245) );
OAI22X1TS U4845 ( .A0(n3311), .A1(n3309), .B0(n3245), .B1(n2184), .Y(
mult_x_159_n361) );
XNOR2X1TS U4846 ( .A(n2188), .B(n5462), .Y(n3310) );
OAI22X1TS U4847 ( .A0(n3237), .A1(n3236), .B0(n3310), .B1(n2184), .Y(
mult_x_159_n363) );
XNOR2X1TS U4848 ( .A(n2195), .B(n2298), .Y(n3243) );
OAI22X1TS U4849 ( .A0(n2283), .A1(n3243), .B0(n2233), .B1(n3242), .Y(n3247)
);
OAI22X1TS U4850 ( .A0(n3311), .A1(n3245), .B0(n3244), .B1(n2323), .Y(n3246)
);
ADDHX1TS U4851 ( .A(n3247), .B(n3246), .CO(mult_x_159_n250), .S(
mult_x_159_n251) );
NOR2X1TS U4852 ( .A(DP_OP_498J12_123_5135_n727), .B(n2344), .Y(
mult_x_159_n282) );
INVX2TS U4853 ( .A(n3248), .Y(n3250) );
NAND2X1TS U4854 ( .A(n3250), .B(n3249), .Y(n3251) );
NOR2X1TS U4855 ( .A(n2204), .B(n2326), .Y(mult_x_159_n280) );
INVX2TS U4856 ( .A(mult_x_159_n194), .Y(mult_x_159_n195) );
NOR2X1TS U4857 ( .A(n2204), .B(n2331), .Y(mult_x_159_n168) );
INVX2TS U4858 ( .A(mult_x_159_n168), .Y(mult_x_159_n169) );
XNOR2X1TS U4859 ( .A(n2231), .B(FPMULT_Op_MX[2]), .Y(n3278) );
OAI22X1TS U4860 ( .A0(n3308), .A1(n3278), .B0(n2213), .B1(n3253), .Y(n3259)
);
OAI22X1TS U4861 ( .A0(n2283), .A1(n2338), .B0(n2233), .B1(n3254), .Y(n3258)
);
OAI22X1TS U4862 ( .A0(n2280), .A1(n3256), .B0(n2211), .B1(n3255), .Y(n3257)
);
CMPR32X2TS U4863 ( .A(n3259), .B(n3258), .C(n3257), .CO(mult_x_159_n248),
.S(mult_x_159_n249) );
XNOR2X1TS U4864 ( .A(FPMULT_Op_MY[7]), .B(n2129), .Y(n3264) );
OAI22X1TS U4865 ( .A0(n3308), .A1(n3264), .B0(n2212), .B1(n3260), .Y(n3261)
);
CMPR32X2TS U4866 ( .A(n3263), .B(n3262), .C(n3261), .CO(mult_x_159_n202),
.S(mult_x_159_n203) );
INVX2TS U4867 ( .A(n3263), .Y(n3272) );
OAI22X1TS U4868 ( .A0(n2281), .A1(n3265), .B0(n2212), .B1(n3264), .Y(n3266)
);
CMPR32X2TS U4869 ( .A(n3267), .B(n3272), .C(n3266), .CO(mult_x_159_n210),
.S(mult_x_159_n211) );
XNOR2X1TS U4870 ( .A(n2194), .B(n2158), .Y(n3286) );
OAI22X1TS U4871 ( .A0(n2282), .A1(n3286), .B0(n2232), .B1(n3268), .Y(n3271)
);
XNOR2X1TS U4872 ( .A(n2229), .B(n2129), .Y(n3287) );
OAI22X1TS U4873 ( .A0(n3290), .A1(n3287), .B0(n2210), .B1(n3269), .Y(n3270)
);
CMPR32X2TS U4874 ( .A(n3272), .B(n3271), .C(n3270), .CO(mult_x_159_n220),
.S(mult_x_159_n221) );
INVX2TS U4875 ( .A(n3305), .Y(n3277) );
XNOR2X1TS U4876 ( .A(n2195), .B(FPMULT_Op_MX[10]), .Y(n3301) );
OAI22X1TS U4877 ( .A0(n2283), .A1(n3273), .B0(n2233), .B1(n3301), .Y(n3276)
);
OAI22X1TS U4878 ( .A0(n2281), .A1(n3274), .B0(n2213), .B1(n2145), .Y(n3275)
);
CMPR32X2TS U4879 ( .A(n3277), .B(n3276), .C(n3275), .CO(mult_x_159_n178),
.S(mult_x_159_n179) );
NOR2BX1TS U4880 ( .AN(n2298), .B(n2233), .Y(n3285) );
OAI22X1TS U4881 ( .A0(n3308), .A1(n3279), .B0(n2213), .B1(n3278), .Y(n3284)
);
OAI22X1TS U4882 ( .A0(n2279), .A1(n3281), .B0(n2221), .B1(n3280), .Y(n3283)
);
CMPR32X2TS U4883 ( .A(n3285), .B(n3284), .C(n3283), .CO(mult_x_159_n255),
.S(mult_x_159_n256) );
NOR2BX1TS U4884 ( .AN(n3306), .B(DP_OP_498J12_123_5135_n727), .Y(n3293) );
XNOR2X1TS U4885 ( .A(n2194), .B(FPMULT_Op_MX[3]), .Y(n3294) );
OAI22X1TS U4886 ( .A0(n2282), .A1(n3294), .B0(n2232), .B1(n3286), .Y(n3292)
);
OAI22X1TS U4887 ( .A0(n3290), .A1(n3289), .B0(n2210), .B1(n3287), .Y(n3291)
);
CMPR32X2TS U4888 ( .A(n3293), .B(n3292), .C(n3291), .CO(mult_x_159_n229),
.S(mult_x_159_n230) );
OAI22X1TS U4889 ( .A0(n2282), .A1(n3295), .B0(n2232), .B1(n3294), .Y(n3299)
);
OAI22X1TS U4890 ( .A0(n3311), .A1(n3297), .B0(n3296), .B1(n2184), .Y(n3298)
);
ADDHX1TS U4891 ( .A(n3299), .B(n3298), .CO(mult_x_159_n237), .S(
mult_x_159_n238) );
NOR2X1TS U4892 ( .A(n2204), .B(n2325), .Y(n3304) );
OAI22X1TS U4893 ( .A0(n2283), .A1(n3301), .B0(n2233), .B1(n3300), .Y(n3303)
);
CMPR32X2TS U4894 ( .A(n3305), .B(n3304), .C(n3303), .CO(mult_x_159_n173),
.S(mult_x_159_n174) );
OAI22X1TS U4895 ( .A0(n3308), .A1(n2145), .B0(n2213), .B1(n3307), .Y(n3313)
);
OAI22X1TS U4896 ( .A0(n3311), .A1(n3310), .B0(n3309), .B1(n2184), .Y(n3312)
);
NAND2X1TS U4897 ( .A(n3315), .B(n3314), .Y(n3316) );
XNOR2X1TS U4898 ( .A(n3317), .B(n3316), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22) );
INVX2TS U4899 ( .A(n3318), .Y(n3320) );
NAND2X1TS U4900 ( .A(n3320), .B(n3319), .Y(n3321) );
INVX4TS U4901 ( .A(n3323), .Y(n3348) );
OAI21X1TS U4902 ( .A0(n3348), .A1(n3325), .B0(n3324), .Y(n3330) );
INVX2TS U4903 ( .A(n3326), .Y(n3328) );
NAND2X1TS U4904 ( .A(n3328), .B(n3327), .Y(n3329) );
XNOR2X1TS U4905 ( .A(n3330), .B(n3329), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20) );
INVX2TS U4906 ( .A(n3331), .Y(n3334) );
OAI21X1TS U4907 ( .A0(n3348), .A1(n3334), .B0(n3333), .Y(n3338) );
NAND2X1TS U4908 ( .A(n3336), .B(n3335), .Y(n3337) );
XNOR2X1TS U4909 ( .A(n3338), .B(n3337), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19) );
OAI21X1TS U4910 ( .A0(n3348), .A1(n3344), .B0(n3345), .Y(n3343) );
INVX2TS U4911 ( .A(n3339), .Y(n3341) );
NAND2X1TS U4912 ( .A(n3341), .B(n3340), .Y(n3342) );
XNOR2X1TS U4913 ( .A(n3343), .B(n3342), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18) );
INVX2TS U4914 ( .A(n3344), .Y(n3346) );
NAND2X1TS U4915 ( .A(n3346), .B(n3345), .Y(n3347) );
AOI21X2TS U4916 ( .A0(n3372), .A1(n3351), .B0(n3350), .Y(n3361) );
INVX2TS U4917 ( .A(n3352), .Y(n3354) );
NAND2X1TS U4918 ( .A(n3354), .B(n3353), .Y(n3355) );
XNOR2X1TS U4919 ( .A(n3356), .B(n3355), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16) );
INVX2TS U4920 ( .A(n3357), .Y(n3359) );
NAND2X1TS U4921 ( .A(n3359), .B(n3358), .Y(n3360) );
INVX2TS U4922 ( .A(n3362), .Y(n3370) );
INVX2TS U4923 ( .A(n3369), .Y(n3363) );
AOI21X1TS U4924 ( .A0(n3372), .A1(n3370), .B0(n3363), .Y(n3368) );
INVX2TS U4925 ( .A(n3364), .Y(n3366) );
NAND2X1TS U4926 ( .A(n3366), .B(n3365), .Y(n3367) );
NAND2X1TS U4927 ( .A(n3370), .B(n3369), .Y(n3371) );
XNOR2X1TS U4928 ( .A(n3372), .B(n3371), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13) );
INVX2TS U4929 ( .A(n3373), .Y(n3472) );
INVX2TS U4930 ( .A(n3374), .Y(n3376) );
NAND2X1TS U4931 ( .A(n3376), .B(n3375), .Y(n3377) );
XNOR2X1TS U4932 ( .A(n3378), .B(n3377), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12) );
INVX2TS U4933 ( .A(n3379), .Y(n3386) );
AOI21X1TS U4934 ( .A0(n3386), .A1(n2346), .B0(n3380), .Y(n3383) );
NAND2X1TS U4935 ( .A(n2347), .B(n3381), .Y(n3382) );
NAND2X1TS U4936 ( .A(n2346), .B(n3384), .Y(n3385) );
XNOR2X1TS U4937 ( .A(n3386), .B(n3385), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9) );
INVX2TS U4938 ( .A(n3387), .Y(n3397) );
INVX2TS U4939 ( .A(n3388), .Y(n3390) );
NAND2X1TS U4940 ( .A(n3390), .B(n3389), .Y(n3391) );
XNOR2X1TS U4941 ( .A(n3392), .B(n3391), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8) );
INVX2TS U4942 ( .A(n3393), .Y(n3395) );
NAND2X1TS U4943 ( .A(n3395), .B(n3394), .Y(n3396) );
INVX2TS U4944 ( .A(n3398), .Y(n3400) );
NAND2X1TS U4945 ( .A(n3400), .B(n3399), .Y(n3402) );
NAND2X1TS U4946 ( .A(n2342), .B(n3403), .Y(n3404) );
XNOR2X1TS U4947 ( .A(n3405), .B(n3404), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5) );
INVX2TS U4948 ( .A(n3406), .Y(n3408) );
NAND2X1TS U4949 ( .A(n3408), .B(n3407), .Y(n3410) );
NAND2X1TS U4950 ( .A(n2332), .B(n3411), .Y(n3413) );
XNOR2X1TS U4951 ( .A(n3413), .B(n3412), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3) );
INVX2TS U4952 ( .A(n3414), .Y(n3416) );
NAND2X1TS U4953 ( .A(n3416), .B(n3415), .Y(n3417) );
XOR2X1TS U4954 ( .A(n3417), .B(n3466), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2) );
OAI22X1TS U4955 ( .A0(n2176), .A1(n2307), .B0(n2200), .B1(FPMULT_Op_MY[21]),
.Y(n3418) );
CMPR32X2TS U4956 ( .A(n5450), .B(n2122), .C(n3418), .CO(mult_x_121_n171),
.S(mult_x_121_n172) );
OAI22X1TS U4957 ( .A0(n3498), .A1(n2125), .B0(n2201), .B1(n2170), .Y(n3419)
);
CMPR32X2TS U4958 ( .A(n3497), .B(FPMULT_Op_MY[15]), .C(n3419), .CO(
mult_x_121_n200), .S(mult_x_121_n201) );
OAI22X1TS U4959 ( .A0(n2176), .A1(FPMULT_Op_MY[14]), .B0(n2200), .B1(
FPMULT_Op_MY[15]), .Y(n3422) );
XNOR2X1TS U4960 ( .A(n2197), .B(n2307), .Y(n3449) );
XNOR2X1TS U4961 ( .A(n2196), .B(n2166), .Y(n3448) );
OAI22X1TS U4962 ( .A0(n3487), .A1(n3449), .B0(n3448), .B1(n2678), .Y(n3421)
);
CMPR32X2TS U4963 ( .A(n2343), .B(n3422), .C(n3421), .CO(mult_x_121_n218),
.S(mult_x_121_n219) );
OAI22X1TS U4964 ( .A0(n2176), .A1(n3497), .B0(n2200), .B1(n2270), .Y(n3424)
);
OAI22X1TS U4965 ( .A0(n2176), .A1(FPMULT_Op_MY[21]), .B0(n2200), .B1(n5039),
.Y(mult_x_121_n281) );
OAI22X1TS U4966 ( .A0(n2176), .A1(n5450), .B0(n2200), .B1(n2122), .Y(
mult_x_121_n284) );
OAI22X1TS U4967 ( .A0(n2176), .A1(n2170), .B0(n2201), .B1(n5450), .Y(
mult_x_121_n285) );
NOR2BX1TS U4968 ( .AN(n2300), .B(n2200), .Y(mult_x_121_n291) );
XOR2X1TS U4969 ( .A(n2238), .B(FPMULT_Op_MX[20]), .Y(n3427) );
INVX2TS U4970 ( .A(n3425), .Y(n3426) );
OAI22X1TS U4971 ( .A0(n2278), .A1(n2237), .B0(n3426), .B1(n2364), .Y(
mult_x_121_n293) );
XNOR2X1TS U4972 ( .A(n2237), .B(n5039), .Y(n3428) );
OAI22X1TS U4973 ( .A0(n2278), .A1(n3428), .B0(n3426), .B1(n2237), .Y(
mult_x_121_n294) );
XNOR2X1TS U4974 ( .A(n2237), .B(FPMULT_Op_MY[21]), .Y(n3429) );
OAI22X1TS U4975 ( .A0(n2278), .A1(n3429), .B0(n3428), .B1(n3426), .Y(
mult_x_121_n295) );
XNOR2X1TS U4976 ( .A(n2237), .B(n2307), .Y(n3430) );
OAI22X1TS U4977 ( .A0(n3507), .A1(n3430), .B0(n3429), .B1(n2217), .Y(
mult_x_121_n296) );
XNOR2X1TS U4978 ( .A(n2237), .B(n2122), .Y(n3431) );
OAI22X1TS U4979 ( .A0(n3507), .A1(n3431), .B0(n3430), .B1(n2217), .Y(
mult_x_121_n297) );
XNOR2X1TS U4980 ( .A(n2237), .B(n5450), .Y(n3432) );
OAI22X1TS U4981 ( .A0(n2278), .A1(n3432), .B0(n3431), .B1(n2217), .Y(
mult_x_121_n298) );
XNOR2X1TS U4982 ( .A(n2238), .B(n2170), .Y(n3433) );
OAI22X1TS U4983 ( .A0(n2278), .A1(n3433), .B0(n3432), .B1(n2217), .Y(
mult_x_121_n299) );
XNOR2X1TS U4984 ( .A(n2238), .B(n2169), .Y(n3434) );
OAI22X1TS U4985 ( .A0(n3507), .A1(n3434), .B0(n3433), .B1(n2217), .Y(
mult_x_121_n300) );
XNOR2X1TS U4986 ( .A(n2238), .B(FPMULT_Op_MY[15]), .Y(n3435) );
OAI22X1TS U4987 ( .A0(n3507), .A1(n3435), .B0(n3434), .B1(n2217), .Y(
mult_x_121_n301) );
XNOR2X1TS U4988 ( .A(n2237), .B(FPMULT_Op_MY[14]), .Y(n3436) );
OAI22X1TS U4989 ( .A0(n3507), .A1(n3436), .B0(n3435), .B1(n2217), .Y(
mult_x_121_n302) );
XNOR2X1TS U4990 ( .A(n2238), .B(n3497), .Y(n3483) );
OAI22X1TS U4991 ( .A0(n3507), .A1(n3483), .B0(n3436), .B1(n3426), .Y(
mult_x_121_n303) );
XOR2X1TS U4992 ( .A(n2198), .B(FPMULT_Op_MX[18]), .Y(n3437) );
XNOR2X1TS U4993 ( .A(n2199), .B(FPMULT_Op_MY[22]), .Y(n3438) );
OAI22X1TS U4994 ( .A0(n3494), .A1(n3438), .B0(n2208), .B1(n2199), .Y(
mult_x_121_n308) );
XNOR2X1TS U4995 ( .A(n2198), .B(n2166), .Y(n3439) );
OAI22X1TS U4996 ( .A0(n2277), .A1(n3439), .B0(n3438), .B1(n2208), .Y(
mult_x_121_n309) );
XNOR2X1TS U4997 ( .A(n2198), .B(FPMULT_Op_MY[20]), .Y(n3440) );
OAI22X1TS U4998 ( .A0(n3494), .A1(n3440), .B0(n3439), .B1(n2207), .Y(
mult_x_121_n310) );
XNOR2X1TS U4999 ( .A(n2198), .B(n2167), .Y(n3441) );
OAI22X1TS U5000 ( .A0(n3494), .A1(n3441), .B0(n3440), .B1(n2207), .Y(
mult_x_121_n311) );
XNOR2X1TS U5001 ( .A(n2198), .B(n5450), .Y(n3442) );
OAI22X1TS U5002 ( .A0(n3494), .A1(n3442), .B0(n3441), .B1(n2208), .Y(
mult_x_121_n312) );
XNOR2X1TS U5003 ( .A(n2199), .B(n2170), .Y(n3443) );
OAI22X1TS U5004 ( .A0(n3494), .A1(n3443), .B0(n3442), .B1(n2208), .Y(
mult_x_121_n313) );
XNOR2X1TS U5005 ( .A(n2199), .B(n2125), .Y(n3444) );
OAI22X1TS U5006 ( .A0(n2277), .A1(n3444), .B0(n3443), .B1(n2207), .Y(
mult_x_121_n314) );
XNOR2X1TS U5007 ( .A(n2199), .B(n2168), .Y(n3481) );
OAI22X1TS U5008 ( .A0(n3494), .A1(n3481), .B0(n3444), .B1(n2207), .Y(
mult_x_121_n315) );
XNOR2X1TS U5009 ( .A(n2199), .B(n3497), .Y(n3445) );
XNOR2X1TS U5010 ( .A(n2199), .B(FPMULT_Op_MY[14]), .Y(n3482) );
OAI22X1TS U5011 ( .A0(n2277), .A1(n3445), .B0(n3482), .B1(n2207), .Y(
mult_x_121_n317) );
XNOR2X1TS U5012 ( .A(n2199), .B(n2300), .Y(n3446) );
OAI22X1TS U5013 ( .A0(n3494), .A1(n3446), .B0(n3445), .B1(n2207), .Y(
mult_x_121_n318) );
NOR2BX1TS U5014 ( .AN(n2300), .B(n2208), .Y(mult_x_121_n319) );
OAI22X1TS U5015 ( .A0(n3487), .A1(n2197), .B0(n2219), .B1(n2359), .Y(
mult_x_121_n321) );
XNOR2X1TS U5016 ( .A(n2196), .B(n5039), .Y(n3447) );
OAI22X1TS U5017 ( .A0(n3487), .A1(n3447), .B0(n2678), .B1(n2197), .Y(
mult_x_121_n322) );
OAI22X1TS U5018 ( .A0(n3487), .A1(n3448), .B0(n3447), .B1(n2678), .Y(
mult_x_121_n323) );
XNOR2X1TS U5019 ( .A(n2197), .B(n2122), .Y(n3450) );
OAI22X1TS U5020 ( .A0(n2276), .A1(n3450), .B0(n3449), .B1(n2219), .Y(
mult_x_121_n325) );
XNOR2X1TS U5021 ( .A(n2197), .B(n5450), .Y(n3451) );
OAI22X1TS U5022 ( .A0(n2276), .A1(n3451), .B0(n3450), .B1(n2678), .Y(
mult_x_121_n326) );
XNOR2X1TS U5023 ( .A(n2196), .B(n2170), .Y(n3485) );
OAI22X1TS U5024 ( .A0(n3487), .A1(n3485), .B0(n3451), .B1(n2219), .Y(
mult_x_121_n327) );
XNOR2X1TS U5025 ( .A(n2197), .B(FPMULT_Op_MY[15]), .Y(n3452) );
XNOR2X1TS U5026 ( .A(n2196), .B(n2125), .Y(n3486) );
OAI22X1TS U5027 ( .A0(n3487), .A1(n3452), .B0(n3486), .B1(n2678), .Y(
mult_x_121_n329) );
XNOR2X1TS U5028 ( .A(n2197), .B(FPMULT_Op_MY[14]), .Y(n3453) );
OAI22X1TS U5029 ( .A0(n3487), .A1(n3453), .B0(n3452), .B1(n2219), .Y(
mult_x_121_n330) );
OAI22X1TS U5030 ( .A0(n2276), .A1(n3454), .B0(n3453), .B1(n2678), .Y(
mult_x_121_n331) );
OAI22X1TS U5031 ( .A0(n2273), .A1(n2224), .B0(n2222), .B1(n2144), .Y(
mult_x_121_n335) );
XNOR2X1TS U5032 ( .A(n2225), .B(n5039), .Y(n3455) );
OAI22X1TS U5033 ( .A0(n2273), .A1(n3455), .B0(n2223), .B1(n2225), .Y(
mult_x_121_n336) );
XNOR2X1TS U5034 ( .A(n2225), .B(FPMULT_Op_MY[21]), .Y(n3456) );
OAI22X1TS U5035 ( .A0(n2274), .A1(n3456), .B0(n3455), .B1(n2223), .Y(
mult_x_121_n337) );
XNOR2X1TS U5036 ( .A(n2225), .B(n2307), .Y(n3457) );
OAI22X1TS U5037 ( .A0(n2274), .A1(n3457), .B0(n3456), .B1(n2223), .Y(
mult_x_121_n338) );
XNOR2X1TS U5038 ( .A(n2224), .B(n2122), .Y(n3458) );
OAI22X1TS U5039 ( .A0(n2274), .A1(n3458), .B0(n3457), .B1(n2223), .Y(
mult_x_121_n339) );
XNOR2X1TS U5040 ( .A(n2225), .B(n5450), .Y(n3475) );
OAI22X1TS U5041 ( .A0(n2274), .A1(n3475), .B0(n3458), .B1(n2222), .Y(
mult_x_121_n340) );
XNOR2X1TS U5042 ( .A(n2225), .B(n2125), .Y(n3459) );
XNOR2X1TS U5043 ( .A(n2225), .B(n2170), .Y(n3476) );
OAI22X1TS U5044 ( .A0(n2274), .A1(n3459), .B0(n3476), .B1(n2222), .Y(
mult_x_121_n342) );
OAI22X1TS U5045 ( .A0(n2274), .A1(n3460), .B0(n3459), .B1(n2223), .Y(
mult_x_121_n343) );
XNOR2X1TS U5046 ( .A(n2178), .B(n5039), .Y(n3461) );
OAI22X1TS U5047 ( .A0(n3504), .A1(n3461), .B0(n2353), .B1(n2178), .Y(
mult_x_121_n350) );
XNOR2X1TS U5048 ( .A(n2178), .B(FPMULT_Op_MY[21]), .Y(n3502) );
OAI22X1TS U5049 ( .A0(n3504), .A1(n3502), .B0(n3461), .B1(n2353), .Y(
mult_x_121_n351) );
XNOR2X1TS U5050 ( .A(n2178), .B(n5450), .Y(n3492) );
OAI22X1TS U5051 ( .A0(n3463), .A1(n3462), .B0(n3492), .B1(n2353), .Y(
mult_x_121_n355) );
NOR2BX1TS U5052 ( .AN(n2300), .B(n3501), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0) );
OR2X1TS U5053 ( .A(n3465), .B(n3464), .Y(n3467) );
INVX2TS U5054 ( .A(n3468), .Y(n3470) );
NAND2X1TS U5055 ( .A(n3470), .B(n3469), .Y(n3471) );
NOR2X1TS U5056 ( .A(n2176), .B(n5039), .Y(mult_x_121_n280) );
OAI22X1TS U5057 ( .A0(n2176), .A1(n2122), .B0(n2200), .B1(n2307), .Y(n3474)
);
OAI22X1TS U5058 ( .A0(n2277), .A1(n2199), .B0(n2208), .B1(n2356), .Y(n3473)
);
CMPR32X2TS U5059 ( .A(n2337), .B(n3474), .C(n3473), .CO(mult_x_121_n176),
.S(mult_x_121_n177) );
NOR2BX1TS U5060 ( .AN(n3505), .B(n3426), .Y(n3480) );
XNOR2X1TS U5061 ( .A(n2178), .B(n2122), .Y(n3491) );
XNOR2X1TS U5062 ( .A(n2178), .B(FPMULT_Op_MY[20]), .Y(n3503) );
OAI22X1TS U5063 ( .A0(n3504), .A1(n3491), .B0(n3503), .B1(n2353), .Y(n3479)
);
OAI22X1TS U5064 ( .A0(n2273), .A1(n3476), .B0(n3475), .B1(n2223), .Y(n3478)
);
CMPR32X2TS U5065 ( .A(n3480), .B(n3479), .C(n3478), .CO(mult_x_121_n253),
.S(mult_x_121_n254) );
OAI22X1TS U5066 ( .A0(n3494), .A1(n3482), .B0(n3481), .B1(n2208), .Y(n3490)
);
XNOR2X1TS U5067 ( .A(n2238), .B(n3505), .Y(n3484) );
OAI22X1TS U5068 ( .A0(n3507), .A1(n3484), .B0(n3483), .B1(n3426), .Y(n3489)
);
OAI22X1TS U5069 ( .A0(n3487), .A1(n3486), .B0(n3485), .B1(n2219), .Y(n3488)
);
CMPR32X2TS U5070 ( .A(n3490), .B(n3489), .C(n3488), .CO(mult_x_121_n246),
.S(mult_x_121_n247) );
OAI22X1TS U5071 ( .A0(n3504), .A1(n3492), .B0(n3491), .B1(n3501), .Y(n3496)
);
OAI22X1TS U5072 ( .A0(n3494), .A1(n2356), .B0(n2208), .B1(n3493), .Y(n3495)
);
OAI21X1TS U5073 ( .A0(n2200), .A1(n2300), .B0(n2176), .Y(n3500) );
OAI22X1TS U5074 ( .A0(n3498), .A1(n2300), .B0(n2201), .B1(n3497), .Y(n3499)
);
ADDHX1TS U5075 ( .A(n3500), .B(n3499), .CO(mult_x_121_n235), .S(
mult_x_121_n236) );
OAI22X1TS U5076 ( .A0(n3504), .A1(n3503), .B0(n3502), .B1(n2353), .Y(n3509)
);
OAI22X1TS U5077 ( .A0(n3507), .A1(n2364), .B0(n2217), .B1(n3506), .Y(n3508)
);
ADDHXLTS U5078 ( .A(n3511), .B(n3510), .CO(mult_x_121_n265), .S(n2696) );
NAND2X1TS U5079 ( .A(n3513), .B(n3512), .Y(n3514) );
XNOR2X1TS U5080 ( .A(n3756), .B(n3514), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18) );
INVX2TS U5081 ( .A(n3517), .Y(n3519) );
NAND2X1TS U5082 ( .A(n3519), .B(n3518), .Y(n3520) );
INVX2TS U5083 ( .A(n3522), .Y(n3530) );
INVX2TS U5084 ( .A(n3529), .Y(n3523) );
INVX2TS U5085 ( .A(n3524), .Y(n3526) );
NAND2X1TS U5086 ( .A(n3526), .B(n3525), .Y(n3527) );
NAND2X1TS U5087 ( .A(n3530), .B(n3529), .Y(n3531) );
XNOR2X1TS U5088 ( .A(n3532), .B(n3531), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14) );
INVX2TS U5089 ( .A(n3533), .Y(n3717) );
INVX2TS U5090 ( .A(n3534), .Y(n3536) );
NAND2X1TS U5091 ( .A(n3536), .B(n3535), .Y(n3537) );
XNOR2X1TS U5092 ( .A(n3538), .B(n3537), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13) );
INVX2TS U5093 ( .A(n3539), .Y(n3548) );
AOI21X1TS U5094 ( .A0(n3548), .A1(n3546), .B0(n3540), .Y(n3544) );
NAND2X1TS U5095 ( .A(n3542), .B(n3541), .Y(n3543) );
NAND2X1TS U5096 ( .A(n3546), .B(n3545), .Y(n3547) );
XNOR2X1TS U5097 ( .A(n3548), .B(n3547), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10) );
NAND2X1TS U5098 ( .A(n2808), .B(n3549), .Y(n3550) );
XNOR2X1TS U5099 ( .A(n3551), .B(n3550), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9) );
INVX2TS U5100 ( .A(n3552), .Y(n3559) );
AOI21X1TS U5101 ( .A0(n2355), .A1(n3559), .B0(n3553), .Y(n3557) );
NAND2X1TS U5102 ( .A(n3555), .B(n3554), .Y(n3556) );
NAND2X1TS U5103 ( .A(n2355), .B(n3558), .Y(n3560) );
XNOR2X1TS U5104 ( .A(n3560), .B(n3559), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7) );
NAND2X1TS U5105 ( .A(n2358), .B(n3561), .Y(n3563) );
XNOR2X1TS U5106 ( .A(n3563), .B(n3562), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6) );
INVX2TS U5107 ( .A(n3564), .Y(n3566) );
NAND2X1TS U5108 ( .A(n3566), .B(n3565), .Y(n3568) );
NAND2X1TS U5109 ( .A(n2357), .B(n3569), .Y(n3571) );
XNOR2X1TS U5110 ( .A(n3571), .B(n3570), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4) );
NAND2X1TS U5111 ( .A(n3574), .B(n3573), .Y(n3576) );
NAND2X1TS U5112 ( .A(n2333), .B(n3577), .Y(n3579) );
XNOR2X1TS U5113 ( .A(n3579), .B(n3578), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2) );
XNOR2X1TS U5114 ( .A(n3680), .B(n2289), .Y(n3646) );
NOR2X1TS U5115 ( .A(n3581), .B(n3585), .Y(n3583) );
NOR2X1TS U5116 ( .A(FPMULT_Op_MX[17]), .B(n2159), .Y(n3584) );
XNOR2X1TS U5117 ( .A(n3585), .B(n3584), .Y(n3589) );
INVX2TS U5118 ( .A(n2289), .Y(n3739) );
OAI22X1TS U5119 ( .A0(n3646), .A1(n2190), .B0(n3740), .B1(n3739), .Y(n3610)
);
AOI21X1TS U5120 ( .A0(n3603), .A1(n3595), .B0(n3597), .Y(n3594) );
INVX2TS U5121 ( .A(n3599), .Y(n3592) );
NAND2X1TS U5122 ( .A(n3592), .B(n3598), .Y(n3593) );
CLKXOR2X4TS U5123 ( .A(n3594), .B(n3593), .Y(n3693) );
INVX2TS U5124 ( .A(n3693), .Y(n3626) );
INVX2TS U5125 ( .A(n3595), .Y(n3596) );
NOR2X1TS U5126 ( .A(n3596), .B(n3599), .Y(n3602) );
AOI21X1TS U5127 ( .A0(n3603), .A1(n3602), .B0(n3601), .Y(n3608) );
INVX2TS U5128 ( .A(n3604), .Y(n3606) );
NAND2X1TS U5129 ( .A(n3606), .B(n3605), .Y(n3607) );
CLKXOR2X4TS U5130 ( .A(n3608), .B(n3607), .Y(n3690) );
OAI22X1TS U5131 ( .A0(n3626), .A1(n2180), .B0(n3743), .B1(n2271), .Y(n3744)
);
CMPR32X2TS U5132 ( .A(n3610), .B(n3609), .C(DP_OP_498J12_123_5135_n280),
.CO(DP_OP_498J12_123_5135_n273), .S(DP_OP_498J12_123_5135_n274) );
CMPR32X2TS U5133 ( .A(n3612), .B(n3681), .C(n3611), .CO(n3069), .S(
DP_OP_498J12_123_5135_n315) );
INVX2TS U5134 ( .A(n3613), .Y(n3622) );
NAND2X1TS U5135 ( .A(n3617), .B(n3616), .Y(n3618) );
CLKXOR2X4TS U5136 ( .A(n3619), .B(n3618), .Y(n3686) );
INVX2TS U5137 ( .A(n3686), .Y(n3625) );
OAI22X1TS U5138 ( .A0(n3625), .A1(n2180), .B0(n3620), .B1(n2271), .Y(
DP_OP_498J12_123_5135_n384) );
NAND2X1TS U5139 ( .A(n3622), .B(n3621), .Y(n3623) );
XNOR2X4TS U5140 ( .A(n3624), .B(n3623), .Y(n3688) );
INVX2TS U5141 ( .A(n3688), .Y(n3742) );
OAI22X1TS U5142 ( .A0(n3625), .A1(n2271), .B0(n3742), .B1(n2180), .Y(
DP_OP_498J12_123_5135_n385) );
INVX2TS U5143 ( .A(n3674), .Y(n3627) );
OAI22X1TS U5144 ( .A0(n3627), .A1(n2180), .B0(n3626), .B1(n2179), .Y(
DP_OP_498J12_123_5135_n387) );
INVX2TS U5145 ( .A(n3676), .Y(n3712) );
OAI22X1TS U5146 ( .A0(n3627), .A1(n2179), .B0(n3712), .B1(n2180), .Y(
DP_OP_498J12_123_5135_n388) );
OAI22X1TS U5147 ( .A0(n3629), .A1(n2189), .B0(n3628), .B1(n2297), .Y(
DP_OP_498J12_123_5135_n394) );
OAI22X1TS U5148 ( .A0(n3630), .A1(n2189), .B0(n3629), .B1(n2297), .Y(
DP_OP_498J12_123_5135_n395) );
XNOR2X1TS U5149 ( .A(n3686), .B(n2292), .Y(n3631) );
OAI22X1TS U5150 ( .A0(n3631), .A1(n2189), .B0(n3630), .B1(n2297), .Y(
DP_OP_498J12_123_5135_n396) );
XNOR2X1TS U5151 ( .A(n3688), .B(n2292), .Y(n3632) );
OAI22X1TS U5152 ( .A0(n3631), .A1(n2297), .B0(n3632), .B1(n2189), .Y(
DP_OP_498J12_123_5135_n397) );
XNOR2X1TS U5153 ( .A(n3690), .B(n2292), .Y(n3633) );
OAI22X1TS U5154 ( .A0(n3633), .A1(n3771), .B0(n3632), .B1(n2297), .Y(
DP_OP_498J12_123_5135_n398) );
XNOR2X1TS U5155 ( .A(n3693), .B(n2292), .Y(n3634) );
OAI22X1TS U5156 ( .A0(n3634), .A1(n3771), .B0(n3633), .B1(n2297), .Y(
DP_OP_498J12_123_5135_n399) );
XNOR2X1TS U5157 ( .A(n3674), .B(n2292), .Y(n3636) );
OAI22X1TS U5158 ( .A0(n3636), .A1(n2189), .B0(n3634), .B1(n2297), .Y(
DP_OP_498J12_123_5135_n400) );
OAI22X1TS U5159 ( .A0(n3636), .A1(n2297), .B0(n3635), .B1(n3771), .Y(
DP_OP_498J12_123_5135_n401) );
NOR2BX1TS U5160 ( .AN(n2242), .B(n2980), .Y(DP_OP_498J12_123_5135_n406) );
XNOR2X1TS U5161 ( .A(n3682), .B(n2291), .Y(n3638) );
OAI22X1TS U5162 ( .A0(n3638), .A1(n2192), .B0(n3637), .B1(n2295), .Y(
DP_OP_498J12_123_5135_n408) );
XNOR2X1TS U5163 ( .A(n3684), .B(n2291), .Y(n3639) );
OAI22X1TS U5164 ( .A0(n3639), .A1(n2193), .B0(n3638), .B1(n2296), .Y(
DP_OP_498J12_123_5135_n409) );
XNOR2X1TS U5165 ( .A(n3686), .B(n2291), .Y(n3640) );
OAI22X1TS U5166 ( .A0(n3640), .A1(n2117), .B0(n3639), .B1(n2296), .Y(
DP_OP_498J12_123_5135_n410) );
XNOR2X1TS U5167 ( .A(n3688), .B(n2291), .Y(n3641) );
OAI22X1TS U5168 ( .A0(n3640), .A1(n2295), .B0(n3641), .B1(n2192), .Y(
DP_OP_498J12_123_5135_n411) );
XNOR2X1TS U5169 ( .A(n3690), .B(n2291), .Y(n3642) );
OAI22X1TS U5170 ( .A0(n3642), .A1(n2117), .B0(n3641), .B1(n2295), .Y(
DP_OP_498J12_123_5135_n412) );
XNOR2X1TS U5171 ( .A(n3693), .B(n2291), .Y(n3643) );
OAI22X1TS U5172 ( .A0(n3643), .A1(n2192), .B0(n3642), .B1(n2295), .Y(
DP_OP_498J12_123_5135_n413) );
XNOR2X1TS U5173 ( .A(n3674), .B(n2291), .Y(n3644) );
OAI22X1TS U5174 ( .A0(n3644), .A1(n2117), .B0(n3643), .B1(n2296), .Y(
DP_OP_498J12_123_5135_n414) );
XNOR2X1TS U5175 ( .A(n3676), .B(n2290), .Y(n3768) );
OAI22X1TS U5176 ( .A0(n3644), .A1(n2295), .B0(n3768), .B1(n2192), .Y(
DP_OP_498J12_123_5135_n415) );
XNOR2X1TS U5177 ( .A(n3664), .B(n2290), .Y(n3767) );
XNOR2X1TS U5178 ( .A(n3765), .B(n2290), .Y(n3645) );
OAI22X1TS U5179 ( .A0(n3767), .A1(n2296), .B0(n3645), .B1(n2117), .Y(
DP_OP_498J12_123_5135_n417) );
XNOR2X1TS U5180 ( .A(n3720), .B(n2290), .Y(n3724) );
OAI22X1TS U5181 ( .A0(n3645), .A1(n2295), .B0(n2117), .B1(n3724), .Y(
DP_OP_498J12_123_5135_n418) );
XNOR2X1TS U5182 ( .A(n3682), .B(n2289), .Y(n3647) );
OAI22X1TS U5183 ( .A0(n3647), .A1(n2190), .B0(n3646), .B1(n2294), .Y(
DP_OP_498J12_123_5135_n423) );
XNOR2X1TS U5184 ( .A(n3684), .B(n2289), .Y(n3648) );
OAI22X1TS U5185 ( .A0(n3648), .A1(n2190), .B0(n3647), .B1(n3740), .Y(
DP_OP_498J12_123_5135_n424) );
XNOR2X1TS U5186 ( .A(n3686), .B(n2289), .Y(n3649) );
OAI22X1TS U5187 ( .A0(n3649), .A1(n2190), .B0(n3648), .B1(n2294), .Y(
DP_OP_498J12_123_5135_n425) );
XNOR2X1TS U5188 ( .A(n3688), .B(n2289), .Y(n3650) );
OAI22X1TS U5189 ( .A0(n3649), .A1(n3740), .B0(n3650), .B1(n2190), .Y(
DP_OP_498J12_123_5135_n426) );
XNOR2X1TS U5190 ( .A(n3690), .B(n2289), .Y(n3651) );
OAI22X1TS U5191 ( .A0(n3651), .A1(n2190), .B0(n3650), .B1(n2294), .Y(
DP_OP_498J12_123_5135_n427) );
XNOR2X1TS U5192 ( .A(n3693), .B(n2289), .Y(n3652) );
OAI22X1TS U5193 ( .A0(n3652), .A1(n2190), .B0(n3651), .B1(n2294), .Y(
DP_OP_498J12_123_5135_n428) );
XNOR2X1TS U5194 ( .A(n3674), .B(n2289), .Y(n3653) );
OAI22X1TS U5195 ( .A0(n3653), .A1(n2190), .B0(n3652), .B1(n3740), .Y(
DP_OP_498J12_123_5135_n429) );
XNOR2X1TS U5196 ( .A(n3676), .B(n2288), .Y(n3654) );
OAI22X1TS U5197 ( .A0(n3653), .A1(n3740), .B0(n3654), .B1(n2190), .Y(
DP_OP_498J12_123_5135_n430) );
XNOR2X1TS U5198 ( .A(n3664), .B(n2288), .Y(n3728) );
OAI22X1TS U5199 ( .A0(n3654), .A1(n2294), .B0(n3728), .B1(n3741), .Y(
DP_OP_498J12_123_5135_n431) );
NOR2BX1TS U5200 ( .AN(n2242), .B(n2294), .Y(DP_OP_498J12_123_5135_n435) );
XNOR2X1TS U5201 ( .A(n3680), .B(n2287), .Y(n3656) );
OAI22X1TS U5202 ( .A0(n3656), .A1(n2119), .B0(n3734), .B1(n3655), .Y(
DP_OP_498J12_123_5135_n437) );
XNOR2X1TS U5203 ( .A(n3682), .B(n2287), .Y(n3657) );
OAI22X1TS U5204 ( .A0(n3657), .A1(n2119), .B0(n3656), .B1(n2120), .Y(
DP_OP_498J12_123_5135_n438) );
XNOR2X1TS U5205 ( .A(n3684), .B(n2287), .Y(n3658) );
OAI22X1TS U5206 ( .A0(n3658), .A1(n2118), .B0(n3657), .B1(n2120), .Y(
DP_OP_498J12_123_5135_n439) );
XNOR2X1TS U5207 ( .A(n3686), .B(n2287), .Y(n3659) );
OAI22X1TS U5208 ( .A0(n3659), .A1(n2118), .B0(n3658), .B1(n2120), .Y(
DP_OP_498J12_123_5135_n440) );
XNOR2X1TS U5209 ( .A(n3688), .B(n2287), .Y(n3660) );
OAI22X1TS U5210 ( .A0(n3659), .A1(n2120), .B0(n3660), .B1(n2118), .Y(
DP_OP_498J12_123_5135_n441) );
XNOR2X1TS U5211 ( .A(n3690), .B(n2287), .Y(n3661) );
OAI22X1TS U5212 ( .A0(n3661), .A1(n2118), .B0(n3660), .B1(n3734), .Y(
DP_OP_498J12_123_5135_n442) );
XNOR2X1TS U5213 ( .A(n3693), .B(n2287), .Y(n3662) );
OAI22X1TS U5214 ( .A0(n3662), .A1(n2119), .B0(n3661), .B1(n2120), .Y(
DP_OP_498J12_123_5135_n443) );
XNOR2X1TS U5215 ( .A(n3674), .B(n2287), .Y(n3663) );
OAI22X1TS U5216 ( .A0(n3663), .A1(n2118), .B0(n3662), .B1(n3734), .Y(
DP_OP_498J12_123_5135_n444) );
XNOR2X1TS U5217 ( .A(n3676), .B(n3665), .Y(n3735) );
OAI22X1TS U5218 ( .A0(n3663), .A1(n2120), .B0(n3735), .B1(n2118), .Y(
DP_OP_498J12_123_5135_n445) );
XNOR2X1TS U5219 ( .A(n3664), .B(n3665), .Y(n3733) );
XNOR2X1TS U5220 ( .A(n3765), .B(n3665), .Y(n3667) );
OAI22X1TS U5221 ( .A0(n3733), .A1(n2120), .B0(n3667), .B1(n2119), .Y(
DP_OP_498J12_123_5135_n447) );
OAI22X1TS U5222 ( .A0(n3667), .A1(n2120), .B0(n2119), .B1(n3666), .Y(
DP_OP_498J12_123_5135_n448) );
XNOR2X1TS U5223 ( .A(n3680), .B(n2286), .Y(n3668) );
OAI22X1TS U5224 ( .A0(n3668), .A1(n2191), .B0(n2293), .B1(n3708), .Y(
DP_OP_498J12_123_5135_n452) );
XNOR2X1TS U5225 ( .A(n3682), .B(n2286), .Y(n3669) );
OAI22X1TS U5226 ( .A0(n3669), .A1(n2191), .B0(n3709), .B1(n3668), .Y(
DP_OP_498J12_123_5135_n453) );
XNOR2X1TS U5227 ( .A(n3684), .B(n2286), .Y(n3670) );
OAI22X1TS U5228 ( .A0(n3670), .A1(n2191), .B0(n3669), .B1(n2293), .Y(
DP_OP_498J12_123_5135_n454) );
XNOR2X1TS U5229 ( .A(n3686), .B(n2286), .Y(n3671) );
OAI22X1TS U5230 ( .A0(n3671), .A1(n2191), .B0(n3670), .B1(n3709), .Y(
DP_OP_498J12_123_5135_n455) );
XNOR2X1TS U5231 ( .A(n3688), .B(n2286), .Y(n3672) );
OAI22X1TS U5232 ( .A0(n3671), .A1(n2293), .B0(n3672), .B1(n2191), .Y(
DP_OP_498J12_123_5135_n456) );
XNOR2X1TS U5233 ( .A(n3690), .B(n2286), .Y(n3673) );
OAI22X1TS U5234 ( .A0(n3673), .A1(n2191), .B0(n3672), .B1(n2293), .Y(
DP_OP_498J12_123_5135_n457) );
XNOR2X1TS U5235 ( .A(n3693), .B(n2286), .Y(n3675) );
OAI22X1TS U5236 ( .A0(n3675), .A1(n2191), .B0(n3673), .B1(n3709), .Y(
DP_OP_498J12_123_5135_n458) );
XNOR2X1TS U5237 ( .A(n3674), .B(n2286), .Y(n3677) );
OAI22X1TS U5238 ( .A0(n3677), .A1(n2191), .B0(n3675), .B1(n2293), .Y(
DP_OP_498J12_123_5135_n459) );
XNOR2X1TS U5239 ( .A(n3676), .B(n2285), .Y(n3679) );
OAI22X1TS U5240 ( .A0(n3677), .A1(n3709), .B0(n3679), .B1(n2191), .Y(
DP_OP_498J12_123_5135_n460) );
OAI22X1TS U5241 ( .A0(n3679), .A1(n2293), .B0(n3678), .B1(n3710), .Y(
DP_OP_498J12_123_5135_n461) );
XNOR2X1TS U5242 ( .A(n3680), .B(n3692), .Y(n3683) );
OAI22X1TS U5243 ( .A0(n3683), .A1(n3697), .B0(n3681), .B1(n3699), .Y(
DP_OP_498J12_123_5135_n467) );
XNOR2X1TS U5244 ( .A(n3682), .B(n2275), .Y(n3685) );
OAI22X1TS U5245 ( .A0(n3685), .A1(n3695), .B0(n3683), .B1(n2284), .Y(
DP_OP_498J12_123_5135_n468) );
XNOR2X1TS U5246 ( .A(n3684), .B(n3692), .Y(n3687) );
OAI22X1TS U5247 ( .A0(n3687), .A1(n3695), .B0(n3685), .B1(n3699), .Y(
DP_OP_498J12_123_5135_n469) );
XNOR2X1TS U5248 ( .A(n3686), .B(n2275), .Y(n3689) );
OAI22X1TS U5249 ( .A0(n3689), .A1(n3697), .B0(n3687), .B1(n3699), .Y(
DP_OP_498J12_123_5135_n470) );
XNOR2X1TS U5250 ( .A(n3688), .B(n3692), .Y(n3691) );
OAI22X1TS U5251 ( .A0(n3689), .A1(n2284), .B0(n3691), .B1(n3695), .Y(
DP_OP_498J12_123_5135_n471) );
XNOR2X1TS U5252 ( .A(n3690), .B(n3692), .Y(n3694) );
OAI22X1TS U5253 ( .A0(n3694), .A1(n3697), .B0(n3691), .B1(n3699), .Y(
DP_OP_498J12_123_5135_n472) );
XNOR2X1TS U5254 ( .A(n3693), .B(n2275), .Y(n3696) );
OAI22X1TS U5255 ( .A0(n3696), .A1(n3695), .B0(n3694), .B1(n2284), .Y(
DP_OP_498J12_123_5135_n473) );
OAI22X1TS U5256 ( .A0(n3698), .A1(n3697), .B0(n3696), .B1(n2284), .Y(
DP_OP_498J12_123_5135_n474) );
NOR2BX1TS U5257 ( .AN(n2241), .B(n2284), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0) );
OAI22X1TS U5258 ( .A0(n3741), .A1(n3739), .B0(n3740), .B1(n3704), .Y(n3707)
);
XNOR2X1TS U5259 ( .A(n2288), .B(n2242), .Y(n3705) );
OAI22X1TS U5260 ( .A0(n3741), .A1(n3705), .B0(n3731), .B1(n3740), .Y(n3706)
);
ADDHX1TS U5261 ( .A(n3707), .B(n3706), .CO(DP_OP_498J12_123_5135_n362), .S(
DP_OP_498J12_123_5135_n363) );
INVX2TS U5262 ( .A(DP_OP_498J12_123_5135_n263), .Y(
DP_OP_498J12_123_5135_n264) );
AO21X4TS U5263 ( .A0(n3710), .A1(n2293), .B0(n3708), .Y(n3748) );
OAI22X1TS U5264 ( .A0(n3712), .A1(n2271), .B0(n3711), .B1(n2994), .Y(n3747)
);
INVX2TS U5265 ( .A(DP_OP_498J12_123_5135_n289), .Y(
DP_OP_498J12_123_5135_n290) );
INVX2TS U5266 ( .A(n3713), .Y(n3715) );
NAND2X1TS U5267 ( .A(n3715), .B(n3714), .Y(n3716) );
OAI22X1TS U5268 ( .A0(n3771), .A1(n3719), .B0(n2980), .B1(n3718), .Y(n3723)
);
XNOR2X1TS U5269 ( .A(n2971), .B(n2241), .Y(n3721) );
OAI22X1TS U5270 ( .A0(n3771), .A1(n3721), .B0(n3766), .B1(n2980), .Y(n3722)
);
ADDHX1TS U5271 ( .A(n3723), .B(n3722), .CO(DP_OP_498J12_123_5135_n339), .S(
DP_OP_498J12_123_5135_n340) );
XNOR2X1TS U5272 ( .A(n2290), .B(n2241), .Y(n3725) );
OAI22X1TS U5273 ( .A0(n2117), .A1(n3725), .B0(n3724), .B1(n2295), .Y(n3730)
);
NAND2BX1TS U5274 ( .AN(n2241), .B(n2291), .Y(n3726) );
OAI22X1TS U5275 ( .A0(n2117), .A1(n3727), .B0(n2296), .B1(n3726), .Y(n3729)
);
XNOR2X1TS U5276 ( .A(n3765), .B(n2288), .Y(n3732) );
OAI22X1TS U5277 ( .A0(n3728), .A1(n3740), .B0(n3741), .B1(n3732), .Y(n3738)
);
ADDHX1TS U5278 ( .A(n3730), .B(n3729), .CO(DP_OP_498J12_123_5135_n352), .S(
n3737) );
NOR2BX1TS U5279 ( .AN(n2242), .B(n2296), .Y(n3764) );
OAI22X1TS U5280 ( .A0(n3732), .A1(n2294), .B0(n3741), .B1(n3731), .Y(n3763)
);
OAI22X1TS U5281 ( .A0(n3735), .A1(n2120), .B0(n3733), .B1(n2119), .Y(n3762)
);
CMPR32X2TS U5282 ( .A(n3738), .B(n3737), .C(n3736), .CO(
DP_OP_498J12_123_5135_n350), .S(DP_OP_498J12_123_5135_n351) );
OAI22X1TS U5283 ( .A0(n3743), .A1(n2180), .B0(n3742), .B1(n2179), .Y(n3745)
);
INVX2TS U5284 ( .A(n3757), .Y(n3759) );
CMPR32X2TS U5285 ( .A(n3764), .B(n3763), .C(n3762), .CO(n3736), .S(
DP_OP_498J12_123_5135_n358) );
NOR2BX1TS U5286 ( .AN(n2242), .B(n2271), .Y(n3777) );
XNOR2X1TS U5287 ( .A(n3765), .B(n2971), .Y(n3772) );
OAI22X1TS U5288 ( .A0(n3768), .A1(n2296), .B0(n3767), .B1(n2193), .Y(n3775)
);
OAI22X1TS U5289 ( .A0(n3770), .A1(n2271), .B0(n2180), .B1(n3769), .Y(n3780)
);
OAI22X1TS U5290 ( .A0(n3774), .A1(n2980), .B0(n3772), .B1(n3771), .Y(n3779)
);
CMPR32X2TS U5291 ( .A(n3780), .B(n3779), .C(n3778), .CO(
DP_OP_498J12_123_5135_n323), .S(DP_OP_498J12_123_5135_n324) );
INVX2TS U5292 ( .A(n3783), .Y(n3786) );
INVX2TS U5293 ( .A(n3784), .Y(n3785) );
NAND2X1TS U5294 ( .A(n3789), .B(n3788), .Y(n3790) );
OR4X2TS U5295 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[17]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[16]), .Y(n3800) );
NOR4X1TS U5296 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[18]), .C(
FPMULT_P_Sgf[19]), .D(FPMULT_P_Sgf[21]), .Y(n3796) );
OR4X2TS U5297 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[5]), .C(FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n3792) );
NOR4X1TS U5298 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[2]), .C(
FPMULT_P_Sgf[0]), .D(n3792), .Y(n3795) );
NOR4X1TS U5299 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_P_Sgf[10]), .C(
FPMULT_P_Sgf[14]), .D(FPMULT_P_Sgf[12]), .Y(n3794) );
NOR4X1TS U5300 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[6]), .C(
FPMULT_P_Sgf[7]), .D(FPMULT_P_Sgf[11]), .Y(n3793) );
INVX2TS U5301 ( .A(r_mode[0]), .Y(n3958) );
OAI31X1TS U5302 ( .A0(n3958), .A1(r_mode[1]), .A2(n3909), .B0(n3797), .Y(
n3798) );
OAI21X1TS U5303 ( .A0(n3800), .A1(n3799), .B0(n3798), .Y(n3915) );
OAI31XLTS U5304 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(n3914), .A2(n3915),
.B0(n5828), .Y(n1892) );
NOR4X1TS U5305 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n3803) );
NOR4X1TS U5306 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n3802) );
NOR4X1TS U5307 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n3801) );
XNOR2X4TS U5308 ( .A(n3806), .B(n3805), .Y(n3807) );
BUFX3TS U5309 ( .A(n5363), .Y(n5412) );
CLKMX2X2TS U5310 ( .A(FPMULT_P_Sgf[46]), .B(n3807), .S0(n5412), .Y(n1939) );
XNOR2X1TS U5311 ( .A(n3809), .B(n3808), .Y(n3810) );
BUFX3TS U5312 ( .A(n5363), .Y(n5142) );
NAND3X1TS U5313 ( .A(FPSENCOS_cordic_FSM_state_reg[1]), .B(
FPSENCOS_cordic_FSM_state_reg[2]), .C(n4663), .Y(n3948) );
INVX2TS U5314 ( .A(n3948), .Y(n3947) );
NOR3X1TS U5315 ( .A(n3938), .B(FPSENCOS_cordic_FSM_state_reg[1]), .C(
FPSENCOS_cordic_FSM_state_reg[2]), .Y(n3886) );
NAND2X2TS U5316 ( .A(n2182), .B(FPSENCOS_cont_iter_out[0]), .Y(n4356) );
NOR2X4TS U5317 ( .A(n4356), .B(n5503), .Y(n5484) );
INVX2TS U5318 ( .A(n5484), .Y(n3929) );
CLKINVX1TS U5319 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n5690) );
XOR2X1TS U5320 ( .A(n5731), .B(FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(
n3811) );
XNOR2X1TS U5321 ( .A(n5690), .B(n3811), .Y(n3943) );
AOI21X1TS U5322 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n3929), .B0(n5486), .Y(
n5587) );
AOI22X2TS U5323 ( .A0(FPADDSUB_LZA_output[4]), .A1(n3812), .B0(n2165), .B1(
FPADDSUB_exp_oper_result[4]), .Y(n3829) );
NOR2X1TS U5324 ( .A(n3829), .B(n2265), .Y(n3825) );
INVX2TS U5325 ( .A(n4406), .Y(n4448) );
INVX2TS U5326 ( .A(n3829), .Y(n3818) );
NAND2X2TS U5327 ( .A(n2265), .B(n3818), .Y(n4451) );
INVX2TS U5328 ( .A(n4451), .Y(n4811) );
AOI22X1TS U5329 ( .A0(n4448), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[26]), .B0(n4811),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n3814) );
OAI2BB1X1TS U5330 ( .A0N(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1N(n3825),
.B0(n3814), .Y(n4421) );
NAND2X1TS U5331 ( .A(n4443), .B(n3898), .Y(n3815) );
OR2X2TS U5332 ( .A(FPADDSUB_FS_Module_state_reg[1]), .B(n5721), .Y(n3933) );
INVX2TS U5333 ( .A(n3933), .Y(n3838) );
BUFX3TS U5334 ( .A(n5771), .Y(n4254) );
NOR2BX1TS U5335 ( .AN(n3820), .B(FPADDSUB_add_overflow_flag), .Y(n3816) );
NAND2X4TS U5336 ( .A(n5775), .B(n3816), .Y(n4346) );
NOR2X4TS U5337 ( .A(n2265), .B(n3818), .Y(n4447) );
NAND2X2TS U5338 ( .A(n3817), .B(n4447), .Y(n4810) );
NOR2X4TS U5339 ( .A(n4452), .B(n2249), .Y(n4456) );
INVX2TS U5340 ( .A(n4456), .Y(n4409) );
BUFX3TS U5341 ( .A(n4430), .Y(n4462) );
AOI22X1TS U5342 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(n2264),
.B0(FPADDSUB_Sgf_normalized_result[25]), .B1(n4462), .Y(n3822) );
BUFX3TS U5343 ( .A(n5771), .Y(n4511) );
NAND2X1TS U5344 ( .A(n3819), .B(n3838), .Y(n4325) );
NAND2X1TS U5345 ( .A(FPADDSUB_FS_Module_state_reg[0]), .B(
FPADDSUB_FS_Module_state_reg[3]), .Y(n3932) );
NAND2X1TS U5346 ( .A(n4325), .B(n5342), .Y(n3821) );
NAND2X2TS U5347 ( .A(n3821), .B(FPADDSUB_add_overflow_flag), .Y(n5444) );
NOR3X4TS U5348 ( .A(n4462), .B(n5444), .C(n4448), .Y(n4827) );
INVX2TS U5349 ( .A(n4827), .Y(n3826) );
AOI22X1TS U5350 ( .A0(n4448), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[27]), .B0(n4811),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n3824) );
OAI2BB1X1TS U5351 ( .A0N(n3825), .A1N(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(n3824),
.Y(n4418) );
AOI22X1TS U5352 ( .A0(n2262), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(
FPADDSUB_Sgf_normalized_result[24]), .B1(n4462), .Y(n3827) );
AOI22X1TS U5353 ( .A0(n4448), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n4447),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n3830) );
NOR2X1TS U5354 ( .A(n5444), .B(n3829), .Y(n3831) );
INVX2TS U5355 ( .A(n3831), .Y(n4407) );
NAND2X1TS U5356 ( .A(n3830), .B(n4407), .Y(n4455) );
AOI21X1TS U5357 ( .A0(n4447), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n3831),
.Y(n4459) );
NAND2X1TS U5358 ( .A(n4452), .B(FPADDSUB_Sgf_normalized_result[12]), .Y(
n3832) );
NOR2X2TS U5359 ( .A(FPADDSUB_FS_Module_state_reg[2]), .B(
FPADDSUB_FS_Module_state_reg[1]), .Y(n4001) );
NAND2X2TS U5360 ( .A(n4512), .B(n4001), .Y(n1340) );
NAND2X2TS U5361 ( .A(FPADDSUB_FS_Module_state_reg[1]), .B(
FPADDSUB_FS_Module_state_reg[2]), .Y(n4513) );
NOR2X2TS U5362 ( .A(n3898), .B(n4513), .Y(n4660) );
INVX2TS U5363 ( .A(operation[2]), .Y(n5449) );
INVX2TS U5364 ( .A(ack_operation), .Y(n4190) );
OA22X1TS U5365 ( .A0(n4272), .A1(n4190), .B0(n5490), .B1(n4269), .Y(n3837)
);
INVX2TS U5366 ( .A(n1340), .Y(n3836) );
INVX2TS U5367 ( .A(n4272), .Y(n4332) );
AOI22X1TS U5368 ( .A0(operation[1]), .A1(n2259), .B0(n4332), .B1(
begin_operation), .Y(n3835) );
AOI22X1TS U5369 ( .A0(n4660), .A1(n3837), .B0(n3836), .B1(n3835), .Y(n4469)
);
INVX2TS U5370 ( .A(n4469), .Y(n4440) );
AOI211X1TS U5371 ( .A0(FPADDSUB_FSM_selector_C), .A1(n5775), .B0(n5719),
.C0(n3933), .Y(n4438) );
NAND2X1TS U5372 ( .A(n4512), .B(n3838), .Y(n3840) );
NAND2X1TS U5373 ( .A(FPADDSUB_FS_Module_state_reg[0]), .B(n4437), .Y(n3839)
);
AND2X2TS U5374 ( .A(n3840), .B(n3839), .Y(n4878) );
OAI211XLTS U5375 ( .A0(FPADDSUB_FS_Module_state_reg[1]), .A1(n3898), .B0(
n4878), .C0(n4474), .Y(n3842) );
AOI211X1TS U5376 ( .A0(FPADDSUB_FS_Module_state_reg[2]), .A1(n4440), .B0(
n4438), .C0(n3842), .Y(n3878) );
XNOR2X2TS U5377 ( .A(FPADDSUB_intDY[31]), .B(FPADDSUB_intAS), .Y(n4506) );
AOI22X1TS U5378 ( .A0(FPADDSUB_intDY[23]), .A1(FPADDSUB_intDX[23]), .B0(
n5803), .B1(n5816), .Y(n3849) );
AOI22X1TS U5379 ( .A0(n5713), .A1(FPADDSUB_intDY[15]), .B0(n5778), .B1(
FPADDSUB_intDY[13]), .Y(n3843) );
OAI221XLTS U5380 ( .A0(n5713), .A1(FPADDSUB_intDY[15]), .B0(n5778), .B1(
FPADDSUB_intDY[13]), .C0(n3843), .Y(n3848) );
AOI22X1TS U5381 ( .A0(n5809), .A1(FPADDSUB_intDY[10]), .B0(n5811), .B1(
FPADDSUB_intDY[2]), .Y(n3844) );
AOI22X1TS U5382 ( .A0(n5733), .A1(FPADDSUB_intDY[9]), .B0(n5800), .B1(
FPADDSUB_intDY[11]), .Y(n3845) );
OAI221XLTS U5383 ( .A0(n5733), .A1(FPADDSUB_intDY[9]), .B0(n5800), .B1(
FPADDSUB_intDY[11]), .C0(n3845), .Y(n3846) );
NOR4X1TS U5384 ( .A(n3849), .B(n3848), .C(n3847), .D(n3846), .Y(n3877) );
AOI22X1TS U5385 ( .A0(n5735), .A1(FPADDSUB_intDY[7]), .B0(n5799), .B1(
FPADDSUB_intDY[14]), .Y(n3850) );
AOI22X1TS U5386 ( .A0(n5734), .A1(FPADDSUB_intDY[5]), .B0(n5715), .B1(
FPADDSUB_intDY[4]), .Y(n3851) );
OAI221XLTS U5387 ( .A0(n5734), .A1(FPADDSUB_intDY[5]), .B0(n5715), .B1(
FPADDSUB_intDY[4]), .C0(n3851), .Y(n3856) );
AOI22X1TS U5388 ( .A0(n5786), .A1(FPADDSUB_intDY[3]), .B0(n5805), .B1(
FPADDSUB_intDX[26]), .Y(n3852) );
AOI22X1TS U5389 ( .A0(n5810), .A1(FPADDSUB_intDY[1]), .B0(n5730), .B1(
FPADDSUB_intDX[0]), .Y(n3853) );
OAI221XLTS U5390 ( .A0(n5810), .A1(FPADDSUB_intDY[1]), .B0(n5730), .B1(
FPADDSUB_intDX[0]), .C0(n3853), .Y(n3854) );
NOR4X1TS U5391 ( .A(n3857), .B(n3856), .C(n3855), .D(n3854), .Y(n3876) );
AOI22X1TS U5392 ( .A0(n5792), .A1(FPADDSUB_intDX[28]), .B0(n5714), .B1(
FPADDSUB_intDY[6]), .Y(n3858) );
OAI221XLTS U5393 ( .A0(n5792), .A1(FPADDSUB_intDX[28]), .B0(n5714), .B1(
FPADDSUB_intDY[6]), .C0(n3858), .Y(n3865) );
AOI22X1TS U5394 ( .A0(n5794), .A1(FPADDSUB_intDY[18]), .B0(n5814), .B1(
FPADDSUB_intDX[29]), .Y(n3859) );
AOI22X1TS U5395 ( .A0(n5729), .A1(FPADDSUB_intDX[27]), .B0(n5798), .B1(
FPADDSUB_intDY[19]), .Y(n3860) );
AOI22X1TS U5396 ( .A0(n5791), .A1(FPADDSUB_intDX[25]), .B0(n5797), .B1(
FPADDSUB_intDX[24]), .Y(n3861) );
NOR4X1TS U5397 ( .A(n3864), .B(n3865), .C(n3863), .D(n3862), .Y(n3875) );
AOI22X1TS U5398 ( .A0(n5795), .A1(FPADDSUB_intDY[20]), .B0(n5736), .B1(
FPADDSUB_intDX[30]), .Y(n3866) );
AOI22X1TS U5399 ( .A0(n5732), .A1(FPADDSUB_intDY[8]), .B0(n5777), .B1(
FPADDSUB_intDY[21]), .Y(n3867) );
OAI221XLTS U5400 ( .A0(n5732), .A1(FPADDSUB_intDY[8]), .B0(n5777), .B1(
FPADDSUB_intDY[21]), .C0(n3867), .Y(n3872) );
AOI22X1TS U5401 ( .A0(n5796), .A1(FPADDSUB_intDY[17]), .B0(n5815), .B1(
FPADDSUB_intDY[16]), .Y(n3868) );
AOI22X1TS U5402 ( .A0(n5793), .A1(FPADDSUB_intDY[22]), .B0(n5801), .B1(
FPADDSUB_intDX[12]), .Y(n3869) );
NOR4X1TS U5403 ( .A(n3873), .B(n3872), .C(n3871), .D(n3870), .Y(n3874) );
NOR2X1TS U5404 ( .A(n4667), .B(n4505), .Y(n4327) );
NAND2X1TS U5405 ( .A(n4327), .B(n4483), .Y(n4472) );
NAND2X1TS U5406 ( .A(n3878), .B(n4472), .Y(n1835) );
AOI22X1TS U5407 ( .A0(n4448), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n4447),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(n3879) );
NAND2X1TS U5408 ( .A(n3879), .B(n4407), .Y(n4431) );
NOR2X2TS U5409 ( .A(n4407), .B(n4409), .Y(n4833) );
OAI2BB1X1TS U5410 ( .A0N(n3817), .A1N(n4431), .B0(n3881), .Y(n1639) );
AOI22X1TS U5411 ( .A0(n4448), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(n4447),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(n3882) );
NAND2X1TS U5412 ( .A(n3882), .B(n4407), .Y(n4434) );
OAI2BB1X1TS U5413 ( .A0N(n3817), .A1N(n4434), .B0(n3885), .Y(n1640) );
INVX2TS U5414 ( .A(n3886), .Y(n3931) );
CLKBUFX2TS U5415 ( .A(n3931), .Y(n3889) );
BUFX3TS U5416 ( .A(n3888), .Y(n5967) );
BUFX3TS U5417 ( .A(n3888), .Y(n5966) );
BUFX3TS U5418 ( .A(n3887), .Y(n5965) );
BUFX3TS U5419 ( .A(n3887), .Y(n5970) );
BUFX3TS U5420 ( .A(n5987), .Y(n5963) );
BUFX3TS U5421 ( .A(n5987), .Y(n5971) );
BUFX3TS U5422 ( .A(n5986), .Y(n5960) );
BUFX3TS U5423 ( .A(n3889), .Y(n5962) );
CLKBUFX2TS U5424 ( .A(n3892), .Y(n3896) );
BUFX3TS U5425 ( .A(n3896), .Y(n5991) );
BUFX3TS U5426 ( .A(n3896), .Y(n5990) );
BUFX3TS U5427 ( .A(n5986), .Y(n5964) );
CLKBUFX2TS U5428 ( .A(n3931), .Y(n3891) );
BUFX3TS U5429 ( .A(n3888), .Y(n5980) );
BUFX3TS U5430 ( .A(n3887), .Y(n5981) );
CLKBUFX2TS U5431 ( .A(n3931), .Y(n3893) );
BUFX3TS U5432 ( .A(n3888), .Y(n5975) );
BUFX3TS U5433 ( .A(n5931), .Y(n5939) );
BUFX3TS U5434 ( .A(n3887), .Y(n5977) );
BUFX3TS U5435 ( .A(n3893), .Y(n5972) );
CLKBUFX2TS U5436 ( .A(n3931), .Y(n3887) );
BUFX3TS U5437 ( .A(n3888), .Y(n5954) );
BUFX3TS U5438 ( .A(n3887), .Y(n5953) );
BUFX3TS U5439 ( .A(n5986), .Y(n5952) );
BUFX3TS U5440 ( .A(n5987), .Y(n5951) );
BUFX3TS U5441 ( .A(n5987), .Y(n5973) );
BUFX3TS U5442 ( .A(n3893), .Y(n5950) );
BUFX3TS U5443 ( .A(n5929), .Y(n5941) );
BUFX3TS U5444 ( .A(n3889), .Y(n5974) );
BUFX3TS U5445 ( .A(n5987), .Y(n5979) );
BUFX3TS U5446 ( .A(n3892), .Y(n5999) );
CLKBUFX2TS U5447 ( .A(n3896), .Y(n3890) );
BUFX3TS U5448 ( .A(n3890), .Y(n5998) );
BUFX3TS U5449 ( .A(n3890), .Y(n5996) );
CLKBUFX2TS U5450 ( .A(n3895), .Y(n3894) );
BUFX3TS U5451 ( .A(n5916), .Y(n5934) );
BUFX3TS U5452 ( .A(n5986), .Y(n5978) );
BUFX3TS U5453 ( .A(n3891), .Y(n5968) );
BUFX3TS U5454 ( .A(n5927), .Y(n5940) );
BUFX3TS U5455 ( .A(n3892), .Y(n5995) );
BUFX3TS U5456 ( .A(n3895), .Y(n5932) );
BUFX3TS U5457 ( .A(n5929), .Y(n5925) );
BUFX3TS U5458 ( .A(n5933), .Y(n5943) );
BUFX3TS U5459 ( .A(n3897), .Y(n5942) );
BUFX3TS U5460 ( .A(n3891), .Y(n5949) );
BUFX3TS U5461 ( .A(n3931), .Y(n5988) );
BUFX3TS U5462 ( .A(n3888), .Y(n5956) );
BUFX3TS U5463 ( .A(n3893), .Y(n5961) );
BUFX3TS U5464 ( .A(n3893), .Y(n5959) );
BUFX3TS U5465 ( .A(n3895), .Y(n5931) );
BUFX3TS U5466 ( .A(n3889), .Y(n5957) );
BUFX3TS U5467 ( .A(n3889), .Y(n5958) );
BUFX3TS U5468 ( .A(n3891), .Y(n5955) );
BUFX3TS U5469 ( .A(n5986), .Y(n5984) );
BUFX3TS U5470 ( .A(n3887), .Y(n5985) );
BUFX3TS U5471 ( .A(n5929), .Y(n5917) );
BUFX3TS U5472 ( .A(n3890), .Y(n5997) );
BUFX3TS U5473 ( .A(n5927), .Y(n5920) );
BUFX3TS U5474 ( .A(n3893), .Y(n5982) );
BUFX3TS U5475 ( .A(n5947), .Y(n5945) );
BUFX3TS U5476 ( .A(n3896), .Y(n5993) );
BUFX3TS U5477 ( .A(n3890), .Y(n5992) );
BUFX3TS U5478 ( .A(n3889), .Y(n5969) );
BUFX3TS U5479 ( .A(n5932), .Y(n5926) );
BUFX3TS U5480 ( .A(n3890), .Y(n6004) );
BUFX3TS U5481 ( .A(n5947), .Y(n5924) );
BUFX3TS U5482 ( .A(n5933), .Y(n5918) );
BUFX3TS U5483 ( .A(n5916), .Y(n5921) );
BUFX3TS U5484 ( .A(n3897), .Y(n5919) );
BUFX3TS U5485 ( .A(n3890), .Y(n5994) );
BUFX3TS U5486 ( .A(n3892), .Y(n5989) );
BUFX3TS U5487 ( .A(n3896), .Y(n6000) );
BUFX3TS U5488 ( .A(n3891), .Y(n5983) );
BUFX3TS U5489 ( .A(n5946), .Y(n5923) );
BUFX3TS U5490 ( .A(n5915), .Y(n5938) );
BUFX3TS U5491 ( .A(n3896), .Y(n6003) );
BUFX3TS U5492 ( .A(n3895), .Y(n5930) );
BUFX3TS U5493 ( .A(n5947), .Y(n5944) );
BUFX3TS U5494 ( .A(n3895), .Y(n5929) );
BUFX3TS U5495 ( .A(n5914), .Y(n5937) );
BUFX3TS U5496 ( .A(n3892), .Y(n6001) );
BUFX3TS U5497 ( .A(n5914), .Y(n5922) );
BUFX3TS U5498 ( .A(n3891), .Y(n5976) );
BUFX3TS U5499 ( .A(n3895), .Y(n5927) );
BUFX3TS U5500 ( .A(n5932), .Y(n5935) );
BUFX3TS U5501 ( .A(n3895), .Y(n5933) );
BUFX3TS U5502 ( .A(n3895), .Y(n5928) );
BUFX3TS U5503 ( .A(n3896), .Y(n6002) );
BUFX3TS U5504 ( .A(n5931), .Y(n5936) );
AOI22X1TS U5505 ( .A0(FPADDSUB_FSM_selector_B[1]), .A1(n4862), .B0(
FPADDSUB_add_overflow_flag), .B1(n4876), .Y(n3899) );
NAND2X1TS U5506 ( .A(n3899), .B(n4329), .Y(n1843) );
NAND2X1TS U5507 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n5807), .Y(n4222) );
NAND2X1TS U5508 ( .A(n3914), .B(n4222), .Y(n3900) );
OAI21X2TS U5509 ( .A0(n3903), .A1(n3902), .B0(FPMULT_FS_Module_state_reg[1]),
.Y(n5048) );
NAND2X1TS U5510 ( .A(n4193), .B(n5048), .Y(n3904) );
INVX2TS U5511 ( .A(n4193), .Y(n5182) );
BUFX3TS U5512 ( .A(n5182), .Y(n5168) );
AOI22X1TS U5513 ( .A0(n2173), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n5168), .Y(n3906) );
OAI2BB1X1TS U5514 ( .A0N(n2311), .A1N(FPMULT_P_Sgf[24]), .B0(n3906), .Y(
n3907) );
AOI21X1TS U5515 ( .A0(n2308), .A1(FPMULT_Add_result[0]), .B0(n3907), .Y(
n3908) );
OAI2BB1X1TS U5516 ( .A0N(FPMULT_P_Sgf[23]), .A1N(n2257), .B0(n3908), .Y(
n1869) );
INVX2TS U5517 ( .A(n5624), .Y(n5674) );
OR2X1TS U5518 ( .A(FPSENCOS_d_ff3_LUT_out[27]), .B(n5674), .Y(n1826) );
NOR2X1TS U5519 ( .A(n2116), .B(n5808), .Y(n3936) );
NOR3XLTS U5520 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n5478), .Y(n3911) );
NAND2X1TS U5521 ( .A(n3909), .B(n5849), .Y(n3910) );
NAND2X1TS U5522 ( .A(FPSENCOS_cordic_FSM_state_reg[2]), .B(
FPSENCOS_cordic_FSM_state_reg[3]), .Y(n5683) );
AOI211X1TS U5523 ( .A0(operation[1]), .A1(ack_operation), .B0(
FPSENCOS_cordic_FSM_state_reg[1]), .C0(n5683), .Y(n4662) );
AOI211X1TS U5524 ( .A0(n3940), .A1(n5712), .B0(n4662), .C0(n2259), .Y(n3913)
);
OAI211XLTS U5525 ( .A0(FPSENCOS_cordic_FSM_state_reg[1]), .A1(n5484), .B0(
FPSENCOS_cordic_FSM_state_reg[3]), .C0(n5767), .Y(n3912) );
NAND2X1TS U5526 ( .A(n3913), .B(n3912), .Y(n2061) );
NOR2X2TS U5527 ( .A(n5808), .B(FPMULT_FS_Module_state_reg[1]), .Y(n5034) );
NAND2X1TS U5528 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .Y(n4189) );
AOI22X1TS U5529 ( .A0(n3916), .A1(n3915), .B0(n5034), .B1(n4189), .Y(n3917)
);
NOR3X1TS U5530 ( .A(n5767), .B(n3938), .C(FPSENCOS_cordic_FSM_state_reg[1]),
.Y(n3918) );
BUFX3TS U5531 ( .A(n4025), .Y(n5634) );
INVX2TS U5532 ( .A(n5634), .Y(n5662) );
OAI2BB2XLTS U5533 ( .B0(n5546), .B1(n2240), .A0N(FPSENCOS_d_ff_Xn[30]),
.A1N(n5662), .Y(n1797) );
OAI2BB2XLTS U5534 ( .B0(n5852), .B1(n5657), .A0N(FPSENCOS_d_ff_Xn[23]),
.A1N(n5662), .Y(n1790) );
INVX2TS U5535 ( .A(n5634), .Y(n4007) );
OAI2BB2XLTS U5536 ( .B0(n4100), .B1(n5657), .A0N(FPSENCOS_d_ff_Xn[22]),
.A1N(n4007), .Y(n1781) );
OAI2BB2XLTS U5537 ( .B0(n5563), .B1(n2240), .A0N(FPSENCOS_d_ff_Xn[8]), .A1N(
n4007), .Y(n1753) );
OAI2BB2XLTS U5538 ( .B0(n5569), .B1(n2240), .A0N(FPSENCOS_d_ff_Xn[4]), .A1N(
n4007), .Y(n1745) );
OAI2BB2XLTS U5539 ( .B0(n5575), .B1(n2240), .A0N(FPSENCOS_d_ff_Xn[0]), .A1N(
n4007), .Y(n1737) );
OAI2BB2XLTS U5540 ( .B0(n4149), .B1(n2240), .A0N(FPSENCOS_d_ff_Xn[21]),
.A1N(n4007), .Y(n1779) );
OAI2BB2XLTS U5541 ( .B0(n5560), .B1(n2240), .A0N(FPSENCOS_d_ff_Xn[11]),
.A1N(n4007), .Y(n1759) );
OAI2BB2XLTS U5542 ( .B0(n5555), .B1(n5657), .A0N(FPSENCOS_d_ff_Xn[15]),
.A1N(n4007), .Y(n1767) );
OAI2BB2XLTS U5543 ( .B0(n5562), .B1(n2240), .A0N(FPSENCOS_d_ff_Xn[9]), .A1N(
n4007), .Y(n1755) );
OAI2BB2XLTS U5544 ( .B0(n5551), .B1(n5657), .A0N(FPSENCOS_d_ff_Xn[18]),
.A1N(n4007), .Y(n1773) );
BUFX3TS U5545 ( .A(n5624), .Y(n5576) );
BUFX3TS U5546 ( .A(n5576), .Y(n5667) );
INVX2TS U5547 ( .A(n5667), .Y(n5679) );
AOI22X1TS U5548 ( .A0(n2183), .A1(n5738), .B0(FPSENCOS_d_ff2_X[24]), .B1(
n5508), .Y(n3919) );
XNOR2X1TS U5549 ( .A(n4067), .B(n3919), .Y(n3920) );
BUFX3TS U5550 ( .A(n5624), .Y(n5511) );
BUFX3TS U5551 ( .A(n5511), .Y(n5678) );
AOI22X1TS U5552 ( .A0(n2183), .A1(n5802), .B0(FPSENCOS_d_ff2_Y[24]), .B1(
n5508), .Y(n3921) );
XNOR2X1TS U5553 ( .A(n4069), .B(n3921), .Y(n3922) );
NAND2X1TS U5554 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n5508), .Y(n3923) );
AOI22X1TS U5555 ( .A0(n2183), .A1(n5802), .B0(n4069), .B1(n3923), .Y(n3925)
);
BUFX3TS U5556 ( .A(n5624), .Y(n5550) );
OAI2BB2XLTS U5557 ( .B0(n5576), .B1(n4149), .A0N(n5550), .A1N(
FPSENCOS_d_ff3_sh_x_out[21]), .Y(n1778) );
BUFX3TS U5558 ( .A(n5624), .Y(n5574) );
NAND2X1TS U5559 ( .A(FPSENCOS_d_ff2_X[24]), .B(n5508), .Y(n3927) );
AOI22X1TS U5560 ( .A0(n2182), .A1(n5738), .B0(n4067), .B1(n3927), .Y(n5535)
);
INVX2TS U5561 ( .A(n5576), .Y(n5650) );
NAND2X1TS U5562 ( .A(n5764), .B(FPSENCOS_cont_iter_out[2]), .Y(n5528) );
INVX2TS U5563 ( .A(n5528), .Y(n5506) );
NOR3X2TS U5564 ( .A(FPSENCOS_cont_iter_out[3]), .B(n2175), .C(n5508), .Y(
n5516) );
AOI22X1TS U5565 ( .A0(n5506), .A1(n4356), .B0(n5516), .B1(n5536), .Y(n5496)
);
NAND2X1TS U5566 ( .A(FPSENCOS_cont_iter_out[2]), .B(n5516), .Y(n5507) );
NAND3X1TS U5567 ( .A(FPSENCOS_cont_iter_out[0]), .B(n5671), .C(n5764), .Y(
n4066) );
OAI2BB1X1TS U5568 ( .A0N(n5650), .A1N(n4064), .B0(n4066), .Y(n5510) );
BUFX3TS U5569 ( .A(n5667), .Y(n5532) );
INVX2TS U5570 ( .A(FPSENCOS_d_ff2_X[19]), .Y(n5549) );
OAI2BB2XLTS U5571 ( .B0(n5624), .B1(n5549), .A0N(n5550), .A1N(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1774) );
INVX2TS U5572 ( .A(FPSENCOS_d_ff2_X[20]), .Y(n5548) );
OAI2BB2XLTS U5573 ( .B0(n2365), .B1(n5548), .A0N(n5550), .A1N(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1776) );
OAI2BB2XLTS U5574 ( .B0(n2365), .B1(n4100), .A0N(n5550), .A1N(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1780) );
NOR2X2TS U5575 ( .A(FPSENCOS_cont_var_out[0]), .B(n5728), .Y(n5492) );
BUFX3TS U5576 ( .A(n3930), .Y(n5594) );
OAI2BB2XLTS U5577 ( .B0(n5594), .B1(n5834), .A0N(n3930), .A1N(
FPSENCOS_d_ff_Zn[31]), .Y(n1697) );
BUFX3TS U5578 ( .A(n3930), .Y(n5612) );
INVX2TS U5579 ( .A(result_add_subt[1]), .Y(n5616) );
OAI2BB2XLTS U5580 ( .B0(n5612), .B1(n5616), .A0N(n3930), .A1N(
FPSENCOS_d_ff_Zn[1]), .Y(n1511) );
BUFX3TS U5581 ( .A(n3930), .Y(n5598) );
INVX2TS U5582 ( .A(result_add_subt[0]), .Y(n5681) );
OAI2BB2XLTS U5583 ( .B0(n5598), .B1(n5681), .A0N(n3930), .A1N(
FPSENCOS_d_ff_Zn[0]), .Y(n1507) );
BUFX3TS U5584 ( .A(n3930), .Y(n5593) );
OAI2BB2XLTS U5585 ( .B0(n5593), .B1(n5757), .A0N(n3930), .A1N(
FPSENCOS_d_ff_Zn[30]), .Y(n1627) );
BUFX3TS U5586 ( .A(n3931), .Y(n5987) );
BUFX3TS U5587 ( .A(n3931), .Y(n5986) );
OR2X2TS U5588 ( .A(n3933), .B(n3932), .Y(n5589) );
OAI211XLTS U5589 ( .A0(FPADDSUB_sign_final_result), .A1(
underflow_flag_addsubt), .B0(n5590), .C0(n5841), .Y(n3934) );
INVX2TS U5590 ( .A(n5098), .Y(n5294) );
NAND2X1TS U5591 ( .A(n5294), .B(FPMULT_Add_result[0]), .Y(n3935) );
NAND2X2TS U5592 ( .A(n3936), .B(n5033), .Y(n5470) );
INVX2TS U5593 ( .A(n5470), .Y(n5472) );
OAI31X1TS U5594 ( .A0(n5098), .A1(n5472), .A2(n5724), .B0(n3937), .Y(n1986)
);
OR2X2TS U5595 ( .A(n3949), .B(n3938), .Y(n5579) );
BUFX3TS U5596 ( .A(n5579), .Y(n5584) );
INVX2TS U5597 ( .A(n5584), .Y(n5583) );
AOI32X1TS U5598 ( .A0(n5583), .A1(operation[1]), .A2(operation[0]), .B0(
n5584), .B1(FPSENCOS_d_ff1_operation_out), .Y(n3939) );
INVX2TS U5599 ( .A(n3939), .Y(n1702) );
NAND2X1TS U5600 ( .A(n4664), .B(n3940), .Y(n3942) );
NOR4X2TS U5601 ( .A(FPSENCOS_cont_iter_out[2]), .B(n2183), .C(
FPSENCOS_cont_iter_out[0]), .D(FPSENCOS_cont_iter_out[3]), .Y(n5514)
);
NAND2X1TS U5602 ( .A(FPSENCOS_sel_mux_2_reg[1]), .B(n5988), .Y(n3946) );
OAI32X1TS U5603 ( .A0(n3948), .A1(n5484), .A2(n5728), .B0(n3947), .B1(n3946),
.Y(n1700) );
NAND2X1TS U5604 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(
FPSENCOS_cordic_FSM_state_reg[3]), .Y(n4656) );
INVX2TS U5605 ( .A(n3950), .Y(n3982) );
BUFX3TS U5606 ( .A(n3982), .Y(n3997) );
AOI22X1TS U5607 ( .A0(FPSENCOS_d_ff_Xn[30]), .A1(n3951), .B0(
FPSENCOS_sign_inv_out[30]), .B1(n3997), .Y(n3952) );
AOI22X1TS U5608 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n3951), .B0(
FPSENCOS_data_output2_31_), .B1(n3997), .Y(n3954) );
NAND2X1TS U5609 ( .A(operation[1]), .B(begin_operation), .Y(n3956) );
AOI31XLTS U5610 ( .A0(FPSENCOS_cordic_FSM_state_reg[1]), .A1(n5717), .A2(
n5683), .B0(n5671), .Y(n3955) );
AOI21X1TS U5611 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n3960), .Y(n4475) );
NOR2BX1TS U5612 ( .AN(n4475), .B(n4474), .Y(n4439) );
BUFX3TS U5613 ( .A(FPADDSUB_FSM_selector_A), .Y(n4801) );
BUFX3TS U5614 ( .A(n3953), .Y(n4000) );
BUFX3TS U5615 ( .A(n3951), .Y(n3998) );
AOI22X1TS U5616 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[27]), .B1(n3997), .Y(n3961) );
INVX2TS U5617 ( .A(FPSENCOS_d_ff_Yn[26]), .Y(n5655) );
AOI22X1TS U5618 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[26]), .B1(n3997), .Y(n3962) );
BUFX3TS U5619 ( .A(n3953), .Y(n3991) );
BUFX3TS U5620 ( .A(n3951), .Y(n3989) );
BUFX3TS U5621 ( .A(n3982), .Y(n3985) );
AOI22X1TS U5622 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[14]), .B1(n3985), .Y(n3963) );
AOI22X1TS U5623 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[16]), .B1(n3985), .Y(n3964) );
AOI22X1TS U5624 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[17]), .B1(n3985), .Y(n3965) );
AOI22X1TS U5625 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[19]), .B1(n3985), .Y(n3966) );
INVX2TS U5626 ( .A(FPSENCOS_d_ff_Yn[13]), .Y(n5638) );
AOI22X1TS U5627 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[13]), .B1(n3985), .Y(n3967) );
INVX2TS U5628 ( .A(FPSENCOS_d_ff_Yn[25]), .Y(n5654) );
AOI22X1TS U5629 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[25]), .B1(n3997), .Y(n3968) );
INVX2TS U5630 ( .A(FPSENCOS_d_ff_Yn[29]), .Y(n5660) );
AOI22X1TS U5631 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[29]), .B1(n3997), .Y(n3969) );
AOI22X1TS U5632 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[20]), .B1(n3985), .Y(n3970) );
INVX2TS U5633 ( .A(FPSENCOS_d_ff_Yn[10]), .Y(n5635) );
BUFX3TS U5634 ( .A(n3982), .Y(n3993) );
AOI22X1TS U5635 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[10]), .B1(n3993), .Y(n3971) );
BUFX3TS U5636 ( .A(n3953), .Y(n3996) );
BUFX3TS U5637 ( .A(n3951), .Y(n3994) );
AOI22X1TS U5638 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[1]), .B1(n3982), .Y(n3972) );
INVX2TS U5639 ( .A(FPSENCOS_d_ff_Yn[12]), .Y(n5637) );
AOI22X1TS U5640 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[12]), .B1(n3985), .Y(n3973) );
AOI22X1TS U5641 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[3]), .B1(n3993), .Y(n3974) );
INVX2TS U5642 ( .A(FPSENCOS_d_ff_Yn[6]), .Y(n5628) );
AOI22X1TS U5643 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[6]), .B1(n3993), .Y(n3975) );
AOI22X1TS U5644 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[2]), .B1(n3993), .Y(n3976) );
AOI22X1TS U5645 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[7]), .B1(n3993), .Y(n3977) );
AOI22X1TS U5646 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[5]), .B1(n3993), .Y(n3978) );
AOI22X1TS U5647 ( .A0(FPSENCOS_d_ff_Xn[28]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[28]), .B1(n3997), .Y(n3979) );
INVX2TS U5648 ( .A(FPSENCOS_d_ff_Yn[24]), .Y(n5653) );
AOI22X1TS U5649 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[24]), .B1(n3997), .Y(n3980) );
AOI22X1TS U5650 ( .A0(FPSENCOS_d_ff_Xn[15]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[15]), .B1(n3985), .Y(n3981) );
INVX2TS U5651 ( .A(FPSENCOS_d_ff_Yn[0]), .Y(n5620) );
AOI22X1TS U5652 ( .A0(FPSENCOS_d_ff_Xn[0]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[0]), .B1(n3982), .Y(n3983) );
AOI22X1TS U5653 ( .A0(FPSENCOS_d_ff_Xn[18]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[18]), .B1(n3985), .Y(n3984) );
AOI22X1TS U5654 ( .A0(FPSENCOS_d_ff_Xn[21]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[21]), .B1(n3985), .Y(n3986) );
AOI22X1TS U5655 ( .A0(FPSENCOS_d_ff_Xn[9]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[9]), .B1(n3993), .Y(n3987) );
AOI22X1TS U5656 ( .A0(FPSENCOS_d_ff_Xn[22]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[22]), .B1(n3997), .Y(n3988) );
INVX2TS U5657 ( .A(FPSENCOS_d_ff_Yn[11]), .Y(n5636) );
AOI22X1TS U5658 ( .A0(FPSENCOS_d_ff_Xn[11]), .A1(n3989), .B0(
FPSENCOS_sign_inv_out[11]), .B1(n3993), .Y(n3990) );
AOI22X1TS U5659 ( .A0(FPSENCOS_d_ff_Xn[4]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[4]), .B1(n3993), .Y(n3992) );
INVX2TS U5660 ( .A(FPSENCOS_d_ff_Yn[8]), .Y(n5632) );
AOI22X1TS U5661 ( .A0(FPSENCOS_d_ff_Xn[8]), .A1(n3994), .B0(
FPSENCOS_sign_inv_out[8]), .B1(n3993), .Y(n3995) );
AOI22X1TS U5662 ( .A0(FPSENCOS_d_ff_Xn[23]), .A1(n3998), .B0(
FPSENCOS_sign_inv_out[23]), .B1(n3997), .Y(n3999) );
XOR2XLTS U5663 ( .A(FPSENCOS_cont_var_out[0]), .B(FPSENCOS_d_ff3_sign_out),
.Y(n4005) );
INVX2TS U5664 ( .A(n4443), .Y(n4515) );
BUFX3TS U5665 ( .A(n4002), .Y(n5703) );
BUFX3TS U5666 ( .A(n5703), .Y(n4781) );
AOI22X1TS U5667 ( .A0(operation[0]), .A1(n4781), .B0(FPADDSUB_intAS), .B1(
n4780), .Y(n4004) );
CLKBUFX2TS U5668 ( .A(n5658), .Y(n4024) );
BUFX3TS U5669 ( .A(n4024), .Y(n4045) );
NOR2X1TS U5670 ( .A(FPSENCOS_sel_mux_1_reg), .B(n5675), .Y(n4022) );
CLKBUFX2TS U5671 ( .A(n4022), .Y(n4008) );
INVX2TS U5672 ( .A(n5634), .Y(n4043) );
INVX2TS U5673 ( .A(n4006), .Y(n1505) );
INVX2TS U5674 ( .A(n4009), .Y(n1506) );
NOR3X1TS U5675 ( .A(FPSENCOS_sel_mux_2_reg[0]), .B(n5704), .C(n4269), .Y(
n4010) );
BUFX3TS U5676 ( .A(n5703), .Y(n4197) );
AOI22X1TS U5677 ( .A0(FPADDSUB_intDY[24]), .A1(n4198), .B0(n4197), .B1(
Data_2[24]), .Y(n4015) );
NOR4X1TS U5678 ( .A(FPSENCOS_sel_mux_2_reg[1]), .B(FPSENCOS_sel_mux_2_reg[0]), .C(n5704), .D(n4269), .Y(n4012) );
NOR4X1TS U5679 ( .A(n5826), .B(FPSENCOS_sel_mux_2_reg[1]), .C(n5704), .D(
n4269), .Y(n4013) );
BUFX3TS U5680 ( .A(n4013), .Y(n5705) );
BUFX3TS U5681 ( .A(n5705), .Y(n4226) );
AOI22X1TS U5682 ( .A0(n5706), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n4226),
.B1(FPSENCOS_d_ff3_sh_x_out[24]), .Y(n4014) );
INVX2TS U5683 ( .A(FPSENCOS_d_ff3_LUT_out[25]), .Y(n5498) );
AOI22X1TS U5684 ( .A0(FPADDSUB_intDY[25]), .A1(n4198), .B0(n4197), .B1(
Data_2[25]), .Y(n4017) );
AOI22X1TS U5685 ( .A0(n2206), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n4226),
.B1(FPSENCOS_d_ff3_sh_x_out[25]), .Y(n4016) );
INVX2TS U5686 ( .A(FPSENCOS_d_ff3_LUT_out[23]), .Y(n5502) );
AOI22X1TS U5687 ( .A0(FPADDSUB_intDY[23]), .A1(n4198), .B0(n4197), .B1(
Data_2[23]), .Y(n4019) );
AOI22X1TS U5688 ( .A0(n2206), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n4226),
.B1(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n4018) );
INVX2TS U5689 ( .A(FPSENCOS_d_ff3_LUT_out[26]), .Y(n5495) );
BUFX3TS U5690 ( .A(n5703), .Y(n5697) );
AOI22X1TS U5691 ( .A0(FPADDSUB_intDY[26]), .A1(n4198), .B0(n5697), .B1(
Data_2[26]), .Y(n4021) );
AOI22X1TS U5692 ( .A0(n2206), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n4226),
.B1(FPSENCOS_d_ff3_sh_x_out[26]), .Y(n4020) );
BUFX3TS U5693 ( .A(n4008), .Y(n4044) );
INVX2TS U5694 ( .A(n4023), .Y(n1496) );
BUFX3TS U5695 ( .A(n4024), .Y(n4049) );
BUFX3TS U5696 ( .A(n4008), .Y(n4048) );
INVX2TS U5697 ( .A(n4026), .Y(n1490) );
INVX2TS U5698 ( .A(n4027), .Y(n1504) );
INVX2TS U5699 ( .A(n4028), .Y(n1488) );
CLKBUFX2TS U5700 ( .A(n5658), .Y(n5556) );
BUFX3TS U5701 ( .A(n5556), .Y(n4060) );
INVX2TS U5702 ( .A(n4029), .Y(n1485) );
INVX2TS U5703 ( .A(n4030), .Y(n1489) );
INVX2TS U5704 ( .A(n4031), .Y(n1501) );
INVX2TS U5705 ( .A(n4032), .Y(n1491) );
INVX2TS U5706 ( .A(n4033), .Y(n1502) );
INVX2TS U5707 ( .A(n4034), .Y(n1487) );
INVX2TS U5708 ( .A(n4035), .Y(n1494) );
INVX2TS U5709 ( .A(n4036), .Y(n1495) );
INVX2TS U5710 ( .A(n4037), .Y(n1492) );
INVX2TS U5711 ( .A(n4038), .Y(n1498) );
INVX2TS U5712 ( .A(n4039), .Y(n1497) );
INVX2TS U5713 ( .A(n4040), .Y(n1503) );
INVX2TS U5714 ( .A(n4041), .Y(n1486) );
INVX2TS U5715 ( .A(n4042), .Y(n1500) );
INVX2TS U5716 ( .A(n4046), .Y(n1499) );
INVX2TS U5717 ( .A(n4050), .Y(n1493) );
BUFX3TS U5718 ( .A(n4022), .Y(n4774) );
INVX2TS U5719 ( .A(n4051), .Y(n1478) );
INVX2TS U5720 ( .A(n4052), .Y(n1476) );
INVX2TS U5721 ( .A(n4053), .Y(n1480) );
INVX2TS U5722 ( .A(n4054), .Y(n1481) );
INVX2TS U5723 ( .A(n4055), .Y(n1479) );
INVX2TS U5724 ( .A(n4056), .Y(n1477) );
INVX2TS U5725 ( .A(n4057), .Y(n1482) );
INVX2TS U5726 ( .A(n4058), .Y(n1483) );
INVX2TS U5727 ( .A(n4061), .Y(n1484) );
INVX2TS U5728 ( .A(n5520), .Y(n4065) );
OAI21X2TS U5729 ( .A0(n4065), .A1(n4064), .B0(n5671), .Y(n5513) );
INVX2TS U5730 ( .A(n5511), .Y(n5651) );
NAND2X1TS U5731 ( .A(n5651), .B(n5768), .Y(n5504) );
AOI22X1TS U5732 ( .A0(n5529), .A1(n4067), .B0(FPSENCOS_d_ff3_sh_x_out[23]),
.B1(n5532), .Y(n4068) );
AOI22X1TS U5733 ( .A0(n5529), .A1(n4069), .B0(FPSENCOS_d_ff3_sh_y_out[23]),
.B1(n5532), .Y(n4070) );
NOR2X2TS U5734 ( .A(n5484), .B(n5490), .Y(n4354) );
NAND2X1TS U5735 ( .A(FPSENCOS_cont_var_out[0]), .B(n4354), .Y(n4072) );
INVX2TS U5736 ( .A(n4072), .Y(n4073) );
AOI21X1TS U5737 ( .A0(n4354), .A1(n5728), .B0(FPSENCOS_cont_var_out[0]), .Y(
n4071) );
INVX2TS U5738 ( .A(FPSENCOS_d_ff3_LUT_out[0]), .Y(n5531) );
BUFX3TS U5739 ( .A(n5705), .Y(n4783) );
AOI22X1TS U5740 ( .A0(n2206), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4783),
.B1(FPSENCOS_d_ff3_sh_x_out[0]), .Y(n4075) );
AOI22X1TS U5741 ( .A0(FPADDSUB_intDY[0]), .A1(n5704), .B0(n4781), .B1(
Data_2[0]), .Y(n4074) );
BUFX3TS U5742 ( .A(n2205), .Y(n4159) );
AOI22X1TS U5743 ( .A0(FPADDSUB_intDX[12]), .A1(n4780), .B0(n4781), .B1(
Data_1[12]), .Y(n4077) );
INVX2TS U5744 ( .A(n4776), .Y(n4144) );
AOI22X1TS U5745 ( .A0(n4199), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4783), .B1(
FPSENCOS_d_ff2_Y[12]), .Y(n4076) );
AOI22X1TS U5746 ( .A0(FPADDSUB_intDX[11]), .A1(n4780), .B0(n4781), .B1(
Data_1[11]), .Y(n4079) );
AOI22X1TS U5747 ( .A0(n5698), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4783), .B1(
FPSENCOS_d_ff2_Y[11]), .Y(n4078) );
AOI22X1TS U5748 ( .A0(FPADDSUB_intDX[9]), .A1(n4780), .B0(n4781), .B1(
Data_1[9]), .Y(n4081) );
AOI22X1TS U5749 ( .A0(n4199), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4783), .B1(
FPSENCOS_d_ff2_Y[9]), .Y(n4080) );
BUFX3TS U5750 ( .A(n2205), .Y(n4230) );
AOI22X1TS U5751 ( .A0(FPADDSUB_intDX[24]), .A1(n4225), .B0(n4197), .B1(
Data_1[24]), .Y(n4083) );
AOI22X1TS U5752 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n4226), .B1(
FPSENCOS_d_ff2_Y[24]), .Y(n4082) );
AOI22X1TS U5753 ( .A0(FPADDSUB_intDY[12]), .A1(n4780), .B0(n4781), .B1(
Data_2[12]), .Y(n4085) );
BUFX3TS U5754 ( .A(n5705), .Y(n4233) );
AOI22X1TS U5755 ( .A0(FPSENCOS_d_ff3_LUT_out[12]), .A1(n4199), .B0(n4233),
.B1(FPSENCOS_d_ff3_sh_x_out[12]), .Y(n4084) );
AOI22X1TS U5756 ( .A0(FPADDSUB_intDY[11]), .A1(n4780), .B0(n4781), .B1(
Data_2[11]), .Y(n4087) );
AOI22X1TS U5757 ( .A0(FPSENCOS_d_ff3_LUT_out[11]), .A1(n4199), .B0(n4233),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n4086) );
AOI22X1TS U5758 ( .A0(FPADDSUB_intDY[7]), .A1(n4780), .B0(n4781), .B1(
Data_2[7]), .Y(n4089) );
AOI22X1TS U5759 ( .A0(FPSENCOS_d_ff3_LUT_out[7]), .A1(n5698), .B0(n4233),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n4088) );
AOI22X1TS U5760 ( .A0(FPADDSUB_intDX[26]), .A1(n4198), .B0(n4197), .B1(
Data_1[26]), .Y(n4091) );
AOI22X1TS U5761 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n4226), .B1(
FPSENCOS_d_ff2_Y[26]), .Y(n4090) );
AOI22X1TS U5762 ( .A0(FPADDSUB_intDX[25]), .A1(n4198), .B0(n4197), .B1(
Data_1[25]), .Y(n4093) );
AOI22X1TS U5763 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n4226), .B1(
FPSENCOS_d_ff2_Y[25]), .Y(n4092) );
AOI22X1TS U5764 ( .A0(FPADDSUB_intDX[28]), .A1(n4198), .B0(n4197), .B1(
Data_1[28]), .Y(n4095) );
AOI22X1TS U5765 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n4783), .B0(n4144), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n4094) );
BUFX3TS U5766 ( .A(n2205), .Y(n4174) );
BUFX3TS U5767 ( .A(n5697), .Y(n4224) );
AOI22X1TS U5768 ( .A0(FPADDSUB_intDX[19]), .A1(n4225), .B0(n4224), .B1(
Data_1[19]), .Y(n4097) );
BUFX3TS U5769 ( .A(n5705), .Y(n4171) );
AOI22X1TS U5770 ( .A0(n4234), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4171), .B1(
FPSENCOS_d_ff2_Y[19]), .Y(n4096) );
AOI22X1TS U5771 ( .A0(FPADDSUB_intDX[22]), .A1(n4225), .B0(n4224), .B1(
Data_1[22]), .Y(n4099) );
AOI22X1TS U5772 ( .A0(n4234), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n4226), .B1(
FPSENCOS_d_ff2_Y[22]), .Y(n4098) );
BUFX3TS U5773 ( .A(n5697), .Y(n4231) );
AOI22X1TS U5774 ( .A0(FPADDSUB_intDX[14]), .A1(n4232), .B0(n4231), .B1(
Data_1[14]), .Y(n4102) );
AOI22X1TS U5775 ( .A0(n4234), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4233), .B1(
FPSENCOS_d_ff2_Y[14]), .Y(n4101) );
BUFX3TS U5776 ( .A(n2205), .Y(n4237) );
AOI22X1TS U5777 ( .A0(FPADDSUB_intDX[4]), .A1(n4232), .B0(n4231), .B1(
Data_1[4]), .Y(n4104) );
BUFX3TS U5778 ( .A(n5705), .Y(n4154) );
AOI22X1TS U5779 ( .A0(n4234), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4154), .B1(
FPSENCOS_d_ff2_Y[4]), .Y(n4103) );
INVX2TS U5780 ( .A(FPSENCOS_d_ff2_X[6]), .Y(n5566) );
AOI22X1TS U5781 ( .A0(FPADDSUB_intDX[6]), .A1(n4225), .B0(n4224), .B1(
Data_1[6]), .Y(n4106) );
AOI22X1TS U5782 ( .A0(n4234), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4171), .B1(
FPSENCOS_d_ff2_Y[6]), .Y(n4105) );
AOI22X1TS U5783 ( .A0(FPADDSUB_intDX[18]), .A1(n4170), .B0(n5697), .B1(
Data_1[18]), .Y(n4108) );
BUFX3TS U5784 ( .A(n5705), .Y(n4181) );
AOI22X1TS U5785 ( .A0(n5698), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4181), .B1(
FPSENCOS_d_ff2_Y[18]), .Y(n4107) );
INVX2TS U5786 ( .A(FPSENCOS_d_ff2_X[17]), .Y(n5552) );
BUFX3TS U5787 ( .A(n5697), .Y(n4177) );
AOI22X1TS U5788 ( .A0(FPADDSUB_intDX[17]), .A1(n4232), .B0(n4177), .B1(
Data_1[17]), .Y(n4110) );
AOI22X1TS U5789 ( .A0(n4234), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4154), .B1(
FPSENCOS_d_ff2_Y[17]), .Y(n4109) );
BUFX3TS U5790 ( .A(n2205), .Y(n4184) );
AOI22X1TS U5791 ( .A0(FPADDSUB_intDX[20]), .A1(n4180), .B0(n4177), .B1(
Data_1[20]), .Y(n4112) );
AOI22X1TS U5792 ( .A0(n5698), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4154), .B1(
FPSENCOS_d_ff2_Y[20]), .Y(n4111) );
INVX2TS U5793 ( .A(FPSENCOS_d_ff2_X[10]), .Y(n5561) );
AOI22X1TS U5794 ( .A0(FPADDSUB_intDX[10]), .A1(n4232), .B0(n4231), .B1(
Data_1[10]), .Y(n4114) );
AOI22X1TS U5795 ( .A0(n4199), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n4233), .B1(
FPSENCOS_d_ff2_Y[10]), .Y(n4113) );
AOI22X1TS U5796 ( .A0(FPADDSUB_intDY[9]), .A1(n4170), .B0(n5703), .B1(
Data_2[9]), .Y(n4116) );
AOI22X1TS U5797 ( .A0(n5698), .A1(FPSENCOS_d_ff3_LUT_out[9]), .B0(n4181),
.B1(FPSENCOS_d_ff3_sh_x_out[9]), .Y(n4115) );
AOI22X1TS U5798 ( .A0(FPADDSUB_intDY[17]), .A1(n4232), .B0(n4231), .B1(
Data_2[17]), .Y(n4118) );
AOI22X1TS U5799 ( .A0(FPSENCOS_d_ff3_LUT_out[17]), .A1(n5698), .B0(n4154),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4117) );
AOI22X1TS U5800 ( .A0(FPADDSUB_intDY[19]), .A1(n4170), .B0(n4224), .B1(
Data_2[19]), .Y(n4120) );
AOI22X1TS U5801 ( .A0(n5698), .A1(FPSENCOS_d_ff3_LUT_out[19]), .B0(n4171),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n4119) );
AOI22X1TS U5802 ( .A0(FPADDSUB_intDY[2]), .A1(n4170), .B0(n5703), .B1(
Data_2[2]), .Y(n4122) );
AOI22X1TS U5803 ( .A0(n4199), .A1(FPSENCOS_d_ff3_LUT_out[2]), .B0(n4171),
.B1(FPSENCOS_d_ff3_sh_x_out[2]), .Y(n4121) );
AOI22X1TS U5804 ( .A0(FPADDSUB_intDY[15]), .A1(n4170), .B0(n5703), .B1(
Data_2[15]), .Y(n4124) );
AOI22X1TS U5805 ( .A0(FPSENCOS_d_ff3_LUT_out[15]), .A1(n4199), .B0(n4181),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4123) );
AOI22X1TS U5806 ( .A0(FPADDSUB_intDX[23]), .A1(n4225), .B0(n4224), .B1(
Data_1[23]), .Y(n4126) );
AOI22X1TS U5807 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n4226), .B1(
FPSENCOS_d_ff2_Y[23]), .Y(n4125) );
AOI22X1TS U5808 ( .A0(FPADDSUB_intDY[4]), .A1(n4232), .B0(n4231), .B1(
Data_2[4]), .Y(n4128) );
AOI22X1TS U5809 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n5698), .B0(n4154),
.B1(FPSENCOS_d_ff3_sh_x_out[4]), .Y(n4127) );
AOI22X1TS U5810 ( .A0(FPADDSUB_intDY[20]), .A1(n4180), .B0(n4177), .B1(
Data_2[20]), .Y(n4130) );
AOI22X1TS U5811 ( .A0(FPSENCOS_d_ff3_LUT_out[20]), .A1(n5698), .B0(n4154),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4129) );
AOI22X1TS U5812 ( .A0(FPADDSUB_intDY[18]), .A1(n4170), .B0(n5703), .B1(
Data_2[18]), .Y(n4132) );
AOI22X1TS U5813 ( .A0(FPSENCOS_d_ff3_LUT_out[18]), .A1(n4144), .B0(n4181),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4131) );
AOI22X1TS U5814 ( .A0(FPADDSUB_intDY[10]), .A1(n4232), .B0(n4231), .B1(
Data_2[10]), .Y(n4134) );
AOI22X1TS U5815 ( .A0(n4234), .A1(FPSENCOS_d_ff3_LUT_out[10]), .B0(n4233),
.B1(FPSENCOS_d_ff3_sh_x_out[10]), .Y(n4133) );
AOI22X1TS U5816 ( .A0(FPADDSUB_intDY[13]), .A1(n4180), .B0(n4177), .B1(
Data_2[13]), .Y(n4136) );
AOI22X1TS U5817 ( .A0(FPSENCOS_d_ff3_LUT_out[13]), .A1(n4144), .B0(n4154),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n4135) );
AOI22X1TS U5818 ( .A0(FPADDSUB_intDY[14]), .A1(n4232), .B0(n4231), .B1(
Data_2[14]), .Y(n4138) );
AOI22X1TS U5819 ( .A0(FPSENCOS_d_ff3_LUT_out[14]), .A1(n4144), .B0(n4233),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n4137) );
AOI22X1TS U5820 ( .A0(FPADDSUB_intDY[22]), .A1(n4225), .B0(n4224), .B1(
Data_2[22]), .Y(n4140) );
AOI22X1TS U5821 ( .A0(n4227), .A1(FPSENCOS_d_ff3_LUT_out[22]), .B0(n4171),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n4139) );
AOI22X1TS U5822 ( .A0(FPADDSUB_intDY[6]), .A1(n4225), .B0(n4224), .B1(
Data_2[6]), .Y(n4142) );
AOI22X1TS U5823 ( .A0(n5706), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n4171),
.B1(FPSENCOS_d_ff3_sh_x_out[6]), .Y(n4141) );
AOI22X1TS U5824 ( .A0(FPADDSUB_intDY[5]), .A1(n4180), .B0(n4177), .B1(
Data_2[5]), .Y(n4146) );
AOI22X1TS U5825 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n4199), .B0(n4154),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4145) );
AOI22X1TS U5826 ( .A0(FPADDSUB_intDX[21]), .A1(n4170), .B0(n5697), .B1(
Data_1[21]), .Y(n4148) );
AOI22X1TS U5827 ( .A0(n5698), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n4171), .B1(
FPSENCOS_d_ff2_Y[21]), .Y(n4147) );
AOI22X1TS U5828 ( .A0(FPADDSUB_intDX[13]), .A1(n4180), .B0(n4177), .B1(
Data_1[13]), .Y(n4151) );
AOI22X1TS U5829 ( .A0(n4234), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4154), .B1(
FPSENCOS_d_ff2_Y[13]), .Y(n4150) );
AOI22X1TS U5830 ( .A0(FPADDSUB_intDX[15]), .A1(n4170), .B0(n5697), .B1(
Data_1[15]), .Y(n4153) );
AOI22X1TS U5831 ( .A0(n4011), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4181), .B1(
FPSENCOS_d_ff2_Y[15]), .Y(n4152) );
INVX2TS U5832 ( .A(FPSENCOS_d_ff2_X[5]), .Y(n5568) );
AOI22X1TS U5833 ( .A0(FPADDSUB_intDX[5]), .A1(n4180), .B0(n4177), .B1(
Data_1[5]), .Y(n4156) );
AOI22X1TS U5834 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4154), .B1(
FPSENCOS_d_ff2_Y[5]), .Y(n4155) );
INVX2TS U5835 ( .A(FPSENCOS_d_ff2_X[7]), .Y(n5564) );
AOI22X1TS U5836 ( .A0(FPADDSUB_intDX[7]), .A1(n4780), .B0(n4231), .B1(
Data_1[7]), .Y(n4158) );
AOI22X1TS U5837 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4233), .B1(
FPSENCOS_d_ff2_Y[7]), .Y(n4157) );
INVX2TS U5838 ( .A(FPSENCOS_d_ff2_X[16]), .Y(n5554) );
AOI22X1TS U5839 ( .A0(FPADDSUB_intDX[16]), .A1(n4232), .B0(n4231), .B1(
Data_1[16]), .Y(n4161) );
AOI22X1TS U5840 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4233), .B1(
FPSENCOS_d_ff2_Y[16]), .Y(n4160) );
AOI22X1TS U5841 ( .A0(FPADDSUB_intDY[8]), .A1(n4180), .B0(n4177), .B1(
Data_2[8]), .Y(n4163) );
AOI22X1TS U5842 ( .A0(n4011), .A1(FPSENCOS_d_ff3_LUT_out[8]), .B0(n4181),
.B1(FPSENCOS_d_ff3_sh_x_out[8]), .Y(n4162) );
AOI22X1TS U5843 ( .A0(FPADDSUB_intDY[3]), .A1(n4225), .B0(n4224), .B1(
Data_2[3]), .Y(n4165) );
AOI22X1TS U5844 ( .A0(n4234), .A1(FPSENCOS_d_ff3_LUT_out[3]), .B0(n4171),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4164) );
INVX2TS U5845 ( .A(FPSENCOS_d_ff2_X[3]), .Y(n5570) );
AOI22X1TS U5846 ( .A0(FPADDSUB_intDX[3]), .A1(n4225), .B0(n4224), .B1(
Data_1[3]), .Y(n4167) );
AOI22X1TS U5847 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4171), .B1(
FPSENCOS_d_ff2_Y[3]), .Y(n4166) );
AOI22X1TS U5848 ( .A0(FPADDSUB_intDY[21]), .A1(n4170), .B0(n5697), .B1(
Data_2[21]), .Y(n4169) );
AOI22X1TS U5849 ( .A0(n2206), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4181),
.B1(FPSENCOS_d_ff3_sh_x_out[21]), .Y(n4168) );
AOI22X1TS U5850 ( .A0(FPADDSUB_intDX[2]), .A1(n4170), .B0(n5697), .B1(
Data_1[2]), .Y(n4173) );
AOI22X1TS U5851 ( .A0(n4011), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4171), .B1(
FPSENCOS_d_ff2_Y[2]), .Y(n4172) );
INVX2TS U5852 ( .A(FPSENCOS_d_ff2_X[1]), .Y(n5573) );
AOI22X1TS U5853 ( .A0(FPADDSUB_intDX[1]), .A1(n4180), .B0(n4177), .B1(
Data_1[1]), .Y(n4176) );
AOI22X1TS U5854 ( .A0(n4199), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4181), .B1(
FPSENCOS_d_ff2_Y[1]), .Y(n4175) );
INVX2TS U5855 ( .A(FPSENCOS_d_ff3_LUT_out[1]), .Y(n5527) );
AOI22X1TS U5856 ( .A0(FPADDSUB_intDY[1]), .A1(n4180), .B0(n4177), .B1(
Data_2[1]), .Y(n4179) );
AOI22X1TS U5857 ( .A0(n2206), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n4181),
.B1(FPSENCOS_d_ff3_sh_x_out[1]), .Y(n4178) );
AOI22X1TS U5858 ( .A0(FPADDSUB_intDX[8]), .A1(n4180), .B0(n4002), .B1(
Data_1[8]), .Y(n4183) );
AOI22X1TS U5859 ( .A0(n4199), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4181), .B1(
FPSENCOS_d_ff2_Y[8]), .Y(n4182) );
AOI22X1TS U5860 ( .A0(FPADDSUB_intDX[30]), .A1(n4198), .B0(n4197), .B1(
Data_1[30]), .Y(n4186) );
AOI22X1TS U5861 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n4783), .B0(n4144), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n4185) );
AOI22X1TS U5862 ( .A0(FPADDSUB_intDX[29]), .A1(n4198), .B0(n4197), .B1(
Data_1[29]), .Y(n4188) );
AOI22X1TS U5863 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4783), .B0(n4144), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n4187) );
AOI21X1TS U5864 ( .A0(begin_operation), .A1(n4288), .B0(n3892), .Y(n4192) );
NOR3X1TS U5865 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[0]), .C(n4189), .Y(n4331) );
OAI32X4TS U5866 ( .A0(n4192), .A1(n4191), .A2(n4190), .B0(n4331), .B1(n4192),
.Y(n5321) );
AOI21X1TS U5867 ( .A0(FPMULT_zero_flag), .A1(n2272), .B0(n4193), .Y(n4196)
);
AOI22X1TS U5868 ( .A0(FPADDSUB_intDX[27]), .A1(n4198), .B0(n4197), .B1(
Data_1[27]), .Y(n4201) );
AOI22X1TS U5869 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n4783), .B0(n4144), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n4200) );
INVX2TS U5870 ( .A(n4204), .Y(n4807) );
NAND2X2TS U5871 ( .A(n4346), .B(FPADDSUB_FSM_selector_C), .Y(n4345) );
AOI22X1TS U5872 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[22]), .B0(
FPADDSUB_DmP[1]), .B1(n5771), .Y(n4202) );
OAI21X1TS U5873 ( .A0(n5806), .A1(n4345), .B0(n4202), .Y(n4205) );
AOI22X1TS U5874 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[18]), .B0(
FPADDSUB_DmP[5]), .B1(n4254), .Y(n4203) );
OAI21X1TS U5875 ( .A0(n5820), .A1(n4345), .B0(n4203), .Y(n4239) );
BUFX3TS U5876 ( .A(n4204), .Y(n5443) );
BUFX3TS U5877 ( .A(n5443), .Y(n4479) );
INVX2TS U5878 ( .A(n4216), .Y(n4785) );
NAND2X1TS U5879 ( .A(n3812), .B(FPADDSUB_LZA_output[0]), .Y(n4207) );
NAND2X1TS U5880 ( .A(n5770), .B(FPADDSUB_FSM_selector_B[1]), .Y(n4206) );
AOI21X2TS U5881 ( .A0(FPADDSUB_exp_oper_result[0]), .A1(n5770), .B0(n4520),
.Y(n4215) );
NAND2X2TS U5882 ( .A(n4785), .B(n4215), .Y(n4336) );
AOI22X1TS U5883 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[23]), .B0(
FPADDSUB_DmP[0]), .B1(n5771), .Y(n4211) );
INVX2TS U5884 ( .A(n4479), .Y(n5446) );
NAND2X1TS U5885 ( .A(FPADDSUB_Add_Subt_result[2]), .B(n4368), .Y(n4210) );
AOI21X1TS U5886 ( .A0(n4368), .A1(FPADDSUB_Add_Subt_result[6]), .B0(n4209),
.Y(n4241) );
AOI21X1TS U5887 ( .A0(FPADDSUB_Add_Subt_result[4]), .A1(n2251), .B0(n4213),
.Y(n4369) );
AOI21X1TS U5888 ( .A0(n4368), .A1(FPADDSUB_Add_Subt_result[8]), .B0(n4214),
.Y(n4245) );
AOI22X1TS U5889 ( .A0(n2305), .A1(n4365), .B0(n2246), .B1(n4397), .Y(n4221)
);
AOI22X1TS U5890 ( .A0(n2252), .A1(FPADDSUB_Add_Subt_result[1]), .B0(n4367),
.B1(FPADDSUB_Add_Subt_result[24]), .Y(n4219) );
AOI22X1TS U5891 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[20]), .B0(
FPADDSUB_DmP[3]), .B1(n4254), .Y(n4218) );
OA21XLTS U5892 ( .A0(n4345), .A1(n5825), .B0(n4218), .Y(n4243) );
AOI22X1TS U5893 ( .A0(n4371), .A1(n4219), .B0(n4243), .B1(n4479), .Y(n4366)
);
NAND2X1TS U5894 ( .A(n2243), .B(n4366), .Y(n4220) );
AOI22X1TS U5895 ( .A0(FPADDSUB_intDX[0]), .A1(n4225), .B0(n4224), .B1(
Data_1[0]), .Y(n4229) );
AOI22X1TS U5896 ( .A0(n4227), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n4226), .B1(
FPSENCOS_d_ff2_Y[0]), .Y(n4228) );
AOI22X1TS U5897 ( .A0(FPADDSUB_intDY[16]), .A1(n4232), .B0(n4231), .B1(
Data_2[16]), .Y(n4236) );
AOI22X1TS U5898 ( .A0(n4234), .A1(FPSENCOS_d_ff3_LUT_out[16]), .B0(n4233),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4235) );
AOI22X1TS U5899 ( .A0(n4367), .A1(FPADDSUB_Add_Subt_result[14]), .B0(
FPADDSUB_DmP[9]), .B1(n5771), .Y(n4238) );
OAI21X1TS U5900 ( .A0(n5818), .A1(n4345), .B0(n4238), .Y(n4260) );
AO22X1TS U5901 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[15]), .B0(
FPADDSUB_DmP[8]), .B1(n4254), .Y(n4240) );
AOI21X1TS U5902 ( .A0(n4368), .A1(FPADDSUB_Add_Subt_result[10]), .B0(n4240),
.Y(n4262) );
AOI21X1TS U5903 ( .A0(n2252), .A1(FPADDSUB_Add_Subt_result[9]), .B0(n4242),
.Y(n4264) );
AOI22X1TS U5904 ( .A0(n2305), .A1(n4398), .B0(n2244), .B1(n4396), .Y(n4247)
);
AOI21X1TS U5905 ( .A0(n4368), .A1(FPADDSUB_Add_Subt_result[12]), .B0(n4244),
.Y(n4266) );
BUFX3TS U5906 ( .A(n4204), .Y(n4279) );
NAND2X1TS U5907 ( .A(n2247), .B(n4391), .Y(n4246) );
INVX2TS U5908 ( .A(n4204), .Y(n4371) );
AOI22X1TS U5909 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[10]), .B0(
FPADDSUB_DmP[13]), .B1(n5771), .Y(n4248) );
OAI2BB1X1TS U5910 ( .A0N(FPADDSUB_Add_Subt_result[15]), .A1N(n2252), .B0(
n4248), .Y(n4259) );
AOI22X1TS U5911 ( .A0(n4367), .A1(FPADDSUB_Add_Subt_result[6]), .B0(
FPADDSUB_DmP[17]), .B1(n5771), .Y(n4249) );
OAI2BB1X1TS U5912 ( .A0N(FPADDSUB_Add_Subt_result[19]), .A1N(n2252), .B0(
n4249), .Y(n4275) );
OAI2BB2XLTS U5913 ( .B0(n4346), .B1(n5818), .A0N(FPADDSUB_DmP[12]), .A1N(
n4511), .Y(n4250) );
AOI21X1TS U5914 ( .A0(n2252), .A1(FPADDSUB_Add_Subt_result[14]), .B0(n4250),
.Y(n4261) );
OAI2BB2XLTS U5915 ( .B0(n4346), .B1(n5820), .A0N(FPADDSUB_DmP[16]), .A1N(
n4511), .Y(n4251) );
AOI21X1TS U5916 ( .A0(n2252), .A1(FPADDSUB_Add_Subt_result[18]), .B0(n4251),
.Y(n4277) );
AO22X1TS U5917 ( .A0(n2250), .A1(FPADDSUB_Add_Subt_result[12]), .B0(
FPADDSUB_DmP[11]), .B1(n4254), .Y(n4252) );
AOI21X1TS U5918 ( .A0(n4368), .A1(FPADDSUB_Add_Subt_result[13]), .B0(n4252),
.Y(n4263) );
AOI21X1TS U5919 ( .A0(n2251), .A1(FPADDSUB_Add_Subt_result[17]), .B0(n4253),
.Y(n4280) );
AOI22X1TS U5920 ( .A0(n2304), .A1(n4380), .B0(n2244), .B1(n4378), .Y(n4258)
);
AOI21X1TS U5921 ( .A0(n2252), .A1(FPADDSUB_Add_Subt_result[16]), .B0(n4255),
.Y(n4265) );
OAI2BB2XLTS U5922 ( .B0(n4346), .B1(n5825), .A0N(FPADDSUB_DmP[18]), .A1N(
n4511), .Y(n4256) );
AOI21X1TS U5923 ( .A0(n2252), .A1(FPADDSUB_Add_Subt_result[20]), .B0(n4256),
.Y(n4282) );
NAND2X1TS U5924 ( .A(n2246), .B(n4385), .Y(n4257) );
AOI22X1TS U5925 ( .A0(n2304), .A1(n4392), .B0(n2244), .B1(n4390), .Y(n4268)
);
NAND2X1TS U5926 ( .A(n2246), .B(n4379), .Y(n4267) );
OR2X2TS U5927 ( .A(n4269), .B(operation[2]), .Y(n4334) );
AOI22X1TS U5928 ( .A0(n4288), .A1(mult_result[0]), .B0(n4312), .B1(
cordic_result[0]), .Y(n4270) );
AOI22X1TS U5929 ( .A0(n4288), .A1(mult_result[1]), .B0(n4312), .B1(
cordic_result[1]), .Y(n4271) );
AOI21X1TS U5930 ( .A0(FPSENCOS_d_ff3_LUT_out[9]), .A1(n5576), .B0(n5526),
.Y(n4273) );
AOI22X1TS U5931 ( .A0(n2251), .A1(FPADDSUB_Add_Subt_result[23]), .B0(
FPADDSUB_DmP[21]), .B1(n5771), .Y(n4274) );
OAI21X2TS U5932 ( .A0(n5819), .A1(n4346), .B0(n4274), .Y(n5440) );
AOI22X2TS U5933 ( .A0(n4371), .A1(n4275), .B0(n5440), .B1(n4479), .Y(n4377)
);
AOI22X1TS U5934 ( .A0(n2251), .A1(FPADDSUB_Add_Subt_result[22]), .B0(
FPADDSUB_DmP[20]), .B1(n4254), .Y(n4276) );
OAI21X2TS U5935 ( .A0(n5806), .A1(n4346), .B0(n4276), .Y(n5441) );
AOI2BB2X2TS U5936 ( .B0(n5446), .B1(n4277), .A0N(n5441), .A1N(n5446), .Y(
n4386) );
AOI21X1TS U5937 ( .A0(n2251), .A1(FPADDSUB_Add_Subt_result[21]), .B0(n4278),
.Y(n4350) );
AOI22X1TS U5938 ( .A0(n2304), .A1(n4386), .B0(n2244), .B1(n4384), .Y(n4284)
);
AOI22X1TS U5939 ( .A0(n4367), .A1(FPADDSUB_Add_Subt_result[1]), .B0(
FPADDSUB_DmP[22]), .B1(n5771), .Y(n4281) );
OAI2BB1X2TS U5940 ( .A0N(FPADDSUB_Add_Subt_result[24]), .A1N(n2252), .B0(
n4281), .Y(n5439) );
AOI2BB2X2TS U5941 ( .B0(n5446), .B1(n4282), .A0N(n5439), .A1N(n5446), .Y(
n4402) );
NAND2X1TS U5942 ( .A(n2247), .B(n4402), .Y(n4283) );
BUFX3TS U5943 ( .A(n4303), .Y(n4313) );
INVX2TS U5944 ( .A(n4334), .Y(n4312) );
AOI22X1TS U5945 ( .A0(n4313), .A1(mult_result[12]), .B0(n4298), .B1(
cordic_result[12]), .Y(n4285) );
INVX2TS U5946 ( .A(n4332), .Y(n4300) );
INVX2TS U5947 ( .A(result_add_subt[6]), .Y(n5605) );
AOI22X1TS U5948 ( .A0(n4303), .A1(mult_result[6]), .B0(n4321), .B1(
cordic_result[6]), .Y(n4286) );
INVX2TS U5949 ( .A(result_add_subt[4]), .Y(n5609) );
AOI22X1TS U5950 ( .A0(n4303), .A1(mult_result[4]), .B0(n4298), .B1(
cordic_result[4]), .Y(n4287) );
AOI22X1TS U5951 ( .A0(n4288), .A1(mult_result[11]), .B0(n4305), .B1(
cordic_result[11]), .Y(n4289) );
INVX2TS U5952 ( .A(result_add_subt[8]), .Y(n5603) );
AOI22X1TS U5953 ( .A0(n4303), .A1(mult_result[8]), .B0(n4305), .B1(
cordic_result[8]), .Y(n4290) );
INVX2TS U5954 ( .A(result_add_subt[3]), .Y(n5610) );
AOI22X1TS U5955 ( .A0(n4303), .A1(mult_result[3]), .B0(n4305), .B1(
cordic_result[3]), .Y(n4291) );
INVX2TS U5956 ( .A(result_add_subt[5]), .Y(n5606) );
AOI22X1TS U5957 ( .A0(n4303), .A1(mult_result[5]), .B0(n4321), .B1(
cordic_result[5]), .Y(n4292) );
AOI22X1TS U5958 ( .A0(n4313), .A1(mult_result[13]), .B0(n4321), .B1(
cordic_result[13]), .Y(n4293) );
INVX2TS U5959 ( .A(result_add_subt[7]), .Y(n5604) );
AOI22X1TS U5960 ( .A0(n4303), .A1(mult_result[7]), .B0(n4298), .B1(
cordic_result[7]), .Y(n4294) );
AOI22X1TS U5961 ( .A0(n4313), .A1(mult_result[14]), .B0(n4298), .B1(
cordic_result[14]), .Y(n4295) );
INVX2TS U5962 ( .A(result_add_subt[2]), .Y(n5615) );
AOI22X1TS U5963 ( .A0(n4288), .A1(mult_result[2]), .B0(n4312), .B1(
cordic_result[2]), .Y(n4296) );
AOI22X1TS U5964 ( .A0(n4303), .A1(mult_result[10]), .B0(n4305), .B1(
cordic_result[10]), .Y(n4297) );
INVX2TS U5965 ( .A(result_add_subt[9]), .Y(n5601) );
AOI22X1TS U5966 ( .A0(n4303), .A1(mult_result[9]), .B0(n4305), .B1(
cordic_result[9]), .Y(n4299) );
AOI22X1TS U5967 ( .A0(n4313), .A1(mult_result[16]), .B0(n4321), .B1(
cordic_result[16]), .Y(n4301) );
AOI22X1TS U5968 ( .A0(n4313), .A1(mult_result[15]), .B0(n4298), .B1(
cordic_result[15]), .Y(n4302) );
BUFX3TS U5969 ( .A(n4303), .Y(n4322) );
INVX2TS U5970 ( .A(n4334), .Y(n4305) );
AOI22X1TS U5971 ( .A0(n4322), .A1(mult_result[30]), .B0(n4305), .B1(
cordic_result[30]), .Y(n4304) );
AOI22X1TS U5972 ( .A0(n4322), .A1(mult_result[31]), .B0(cordic_result[31]),
.B1(n4298), .Y(n4306) );
AOI22X1TS U5973 ( .A0(n4313), .A1(mult_result[20]), .B0(n4312), .B1(
cordic_result[20]), .Y(n4307) );
AOI22X1TS U5974 ( .A0(n4313), .A1(mult_result[19]), .B0(n4305), .B1(
cordic_result[19]), .Y(n4308) );
AOI22X1TS U5975 ( .A0(n4313), .A1(mult_result[21]), .B0(n4298), .B1(
cordic_result[21]), .Y(n4309) );
AOI22X1TS U5976 ( .A0(n4313), .A1(mult_result[17]), .B0(n4321), .B1(
cordic_result[17]), .Y(n4310) );
AOI22X1TS U5977 ( .A0(n4322), .A1(mult_result[22]), .B0(n4312), .B1(
cordic_result[22]), .Y(n4311) );
AOI22X1TS U5978 ( .A0(n4313), .A1(mult_result[18]), .B0(n4321), .B1(
cordic_result[18]), .Y(n4314) );
AOI22X1TS U5979 ( .A0(n4322), .A1(mult_result[23]), .B0(n4312), .B1(
cordic_result[23]), .Y(n4315) );
AOI22X1TS U5980 ( .A0(n4322), .A1(mult_result[24]), .B0(n4312), .B1(
cordic_result[24]), .Y(n4316) );
AOI22X1TS U5981 ( .A0(n4322), .A1(mult_result[26]), .B0(n4312), .B1(
cordic_result[26]), .Y(n4317) );
AOI22X1TS U5982 ( .A0(n4322), .A1(mult_result[28]), .B0(n4305), .B1(
cordic_result[28]), .Y(n4318) );
AOI22X1TS U5983 ( .A0(n4322), .A1(mult_result[27]), .B0(n4321), .B1(
cordic_result[27]), .Y(n4319) );
AOI22X1TS U5984 ( .A0(n4322), .A1(mult_result[29]), .B0(n4298), .B1(
cordic_result[29]), .Y(n4320) );
AOI22X1TS U5985 ( .A0(n4322), .A1(mult_result[25]), .B0(n4305), .B1(
cordic_result[25]), .Y(n4323) );
INVX2TS U5986 ( .A(n4325), .Y(n4470) );
OAI22X1TS U5987 ( .A0(n4327), .A1(n4597), .B0(
FPADDSUB_FS_Module_state_reg[1]), .B1(n4326), .Y(n4328) );
NAND2X1TS U5988 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(n5712), .Y(n4335)
);
AOI22X1TS U5989 ( .A0(n4660), .A1(n4332), .B0(n4288), .B1(n4331), .Y(n4333)
);
INVX2TS U5990 ( .A(n4208), .Y(n4353) );
AOI22X1TS U5991 ( .A0(n2260), .A1(n4385), .B0(n2243), .B1(n4380), .Y(n4338)
);
NAND2X1TS U5992 ( .A(n2246), .B(n4384), .Y(n4337) );
AOI22X1TS U5993 ( .A0(n2260), .A1(n4391), .B0(n2243), .B1(n4398), .Y(n4340)
);
NAND2X1TS U5994 ( .A(n2247), .B(n4390), .Y(n4339) );
AOI22X1TS U5995 ( .A0(n2260), .A1(n4379), .B0(n2243), .B1(n4392), .Y(n4342)
);
NAND2X1TS U5996 ( .A(n2246), .B(n4378), .Y(n4341) );
AOI22X1TS U5997 ( .A0(n2260), .A1(n4397), .B0(n2243), .B1(n4365), .Y(n4344)
);
NAND2X1TS U5998 ( .A(n2247), .B(n4396), .Y(n4343) );
AOI22X1TS U5999 ( .A0(n2261), .A1(n4402), .B0(n2244), .B1(n4386), .Y(n4352)
);
NOR2X1TS U6000 ( .A(n4345), .B(FPADDSUB_Add_Subt_result[25]), .Y(n4348) );
NOR2X2TS U6001 ( .A(n4348), .B(n4347), .Y(n5442) );
INVX2TS U6002 ( .A(n5442), .Y(n4349) );
NAND2X1TS U6003 ( .A(n2247), .B(n4477), .Y(n4351) );
NAND2X2TS U6004 ( .A(n5492), .B(n4354), .Y(n5489) );
NAND2X1TS U6005 ( .A(n5584), .B(n5489), .Y(n5493) );
INVX2TS U6006 ( .A(n5493), .Y(n4355) );
AOI21X1TS U6007 ( .A0(n5584), .A1(n4356), .B0(n4355), .Y(n5488) );
OAI32X1TS U6008 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n4356), .A2(n5489),
.B0(n5488), .B1(n5536), .Y(n1829) );
AOI22X1TS U6009 ( .A0(n2305), .A1(n4396), .B0(n2243), .B1(n4397), .Y(n4358)
);
NAND2X1TS U6010 ( .A(n2261), .B(n4398), .Y(n4357) );
AOI22X1TS U6011 ( .A0(n2304), .A1(n4378), .B0(n2244), .B1(n4379), .Y(n4360)
);
NAND2X1TS U6012 ( .A(n2261), .B(n4380), .Y(n4359) );
AOI22X1TS U6013 ( .A0(n2304), .A1(n4384), .B0(n2243), .B1(n4385), .Y(n4362)
);
NAND2X1TS U6014 ( .A(n2261), .B(n4386), .Y(n4361) );
AOI22X1TS U6015 ( .A0(n2304), .A1(n4390), .B0(n2244), .B1(n4391), .Y(n4364)
);
NAND2X1TS U6016 ( .A(n2261), .B(n4392), .Y(n4363) );
AOI22X1TS U6017 ( .A0(n2304), .A1(n4366), .B0(n2261), .B1(n4365), .Y(n4374)
);
AOI22X1TS U6018 ( .A0(n4368), .A1(FPADDSUB_Add_Subt_result[0]), .B0(
FPADDSUB_Add_Subt_result[25]), .B1(n4367), .Y(n4370) );
AOI22X1TS U6019 ( .A0(n4807), .A1(n4370), .B0(n4369), .B1(n4479), .Y(n4372)
);
NAND2X1TS U6020 ( .A(n2243), .B(n4372), .Y(n4373) );
AOI22X1TS U6021 ( .A0(n2305), .A1(n4402), .B0(n2260), .B1(n4477), .Y(n4376)
);
AOI22X1TS U6022 ( .A0(n2305), .A1(n4379), .B0(n2260), .B1(n4378), .Y(n4382)
);
NAND2X1TS U6023 ( .A(n2247), .B(n4380), .Y(n4381) );
AOI22X1TS U6024 ( .A0(n2305), .A1(n4385), .B0(n2260), .B1(n4384), .Y(n4388)
);
NAND2X1TS U6025 ( .A(n2246), .B(n4386), .Y(n4387) );
AOI22X1TS U6026 ( .A0(n2305), .A1(n4391), .B0(n2261), .B1(n4390), .Y(n4394)
);
NAND2X1TS U6027 ( .A(n2246), .B(n4392), .Y(n4393) );
AOI22X1TS U6028 ( .A0(n2305), .A1(n4397), .B0(n2261), .B1(n4396), .Y(n4400)
);
NAND2X1TS U6029 ( .A(n2247), .B(n4398), .Y(n4399) );
AOI22X1TS U6030 ( .A0(n2260), .A1(n5441), .B0(n2245), .B1(n5440), .Y(n4405)
);
AOI22X1TS U6031 ( .A0(n2304), .A1(n4477), .B0(n2243), .B1(n4402), .Y(n4404)
);
NAND2X1TS U6032 ( .A(n4476), .B(n4785), .Y(n4403) );
INVX2TS U6033 ( .A(n3817), .Y(n4460) );
INVX2TS U6034 ( .A(n2253), .Y(n4467) );
NOR2X2TS U6035 ( .A(n4409), .B(n4450), .Y(n4461) );
AOI21X1TS U6036 ( .A0(n2263), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(n4408),
.Y(n4411) );
AOI22X1TS U6037 ( .A0(n4464), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n4840),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n4410) );
AOI21X1TS U6038 ( .A0(n2263), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(n4412),
.Y(n4414) );
AOI22X1TS U6039 ( .A0(n4464), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n3883),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n4413) );
AOI21X1TS U6040 ( .A0(n2264), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[33]), .B0(n4415),
.Y(n4417) );
AOI22X1TS U6041 ( .A0(n4464), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n3883),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n4416) );
NAND2X1TS U6042 ( .A(n4418), .B(n4456), .Y(n4420) );
AOI22X1TS U6043 ( .A0(n4840), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(
FPADDSUB_Sgf_normalized_result[1]), .B1(n4452), .Y(n4419) );
NAND2X1TS U6044 ( .A(n4421), .B(n4456), .Y(n4423) );
AOI22X1TS U6045 ( .A0(n3883), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(
FPADDSUB_Sgf_normalized_result[0]), .B1(n4452), .Y(n4422) );
AOI21X1TS U6046 ( .A0(n2264), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(n4424),
.Y(n4426) );
AOI22X1TS U6047 ( .A0(n4464), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n4840),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n4425) );
AOI21X1TS U6048 ( .A0(n2263), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n4427),
.Y(n4429) );
AOI22X1TS U6049 ( .A0(n4464), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n3883),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n4428) );
NAND2X1TS U6050 ( .A(n2254), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n4433) );
BUFX3TS U6051 ( .A(n4430), .Y(n4839) );
AOI22X1TS U6052 ( .A0(n4456), .A1(n4431), .B0(
FPADDSUB_Sgf_normalized_result[15]), .B1(n4839), .Y(n4432) );
NAND2X1TS U6053 ( .A(n2254), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n4436) );
AOI22X1TS U6054 ( .A0(n4456), .A1(n4434), .B0(
FPADDSUB_Sgf_normalized_result[14]), .B1(n4839), .Y(n4435) );
AOI21X1TS U6055 ( .A0(n4437), .A1(n5719), .B0(n4003), .Y(n4442) );
NAND2X1TS U6056 ( .A(n2254), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n4446) );
AOI22X1TS U6057 ( .A0(n4448), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n4447),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n4444) );
OAI211X1TS U6058 ( .A0(n5848), .A1(n4451), .B0(n4450), .C0(n4444), .Y(n4838)
);
AOI22X1TS U6059 ( .A0(n4456), .A1(n4838), .B0(
FPADDSUB_Sgf_normalized_result[9]), .B1(n4452), .Y(n4445) );
NAND2X1TS U6060 ( .A(n2254), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n4454) );
AOI22X1TS U6061 ( .A0(n4448), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(n4447),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n4449) );
OAI211X1TS U6062 ( .A0(n5760), .A1(n4451), .B0(n4450), .C0(n4449), .Y(n4834)
);
AOI22X1TS U6063 ( .A0(n4456), .A1(n4834), .B0(
FPADDSUB_Sgf_normalized_result[8]), .B1(n4452), .Y(n4453) );
NAND2X1TS U6064 ( .A(n2254), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n4458) );
AOI22X1TS U6065 ( .A0(n4456), .A1(n4455), .B0(
FPADDSUB_Sgf_normalized_result[13]), .B1(n4462), .Y(n4457) );
AOI21X1TS U6066 ( .A0(n2264), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n4463),
.Y(n4466) );
AOI22X1TS U6067 ( .A0(n4464), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]), .B1(n4840),
.Y(n4465) );
INVX2TS U6068 ( .A(n5589), .Y(n5599) );
AOI21X1TS U6069 ( .A0(n4469), .A1(n4468), .B0(n5775), .Y(n4471) );
NOR4X1TS U6070 ( .A(n5599), .B(n4471), .C(n4919), .D(n4470), .Y(n4473) );
AOI222X1TS U6071 ( .A0(n5441), .A1(n2304), .B0(n5439), .B1(n2247), .C0(n5440), .C1(n2260), .Y(n4480) );
AOI22X1TS U6072 ( .A0(n2244), .A1(n4477), .B0(n4476), .B1(n4217), .Y(n4478)
);
AOI22X1TS U6073 ( .A0(n4491), .A1(FPADDSUB_intDY[13]), .B0(FPADDSUB_DMP[13]),
.B1(n4607), .Y(n4482) );
AOI22X1TS U6074 ( .A0(n4491), .A1(FPADDSUB_intDY[19]), .B0(FPADDSUB_DMP[19]),
.B1(n4635), .Y(n4484) );
AOI22X1TS U6075 ( .A0(n4491), .A1(FPADDSUB_intDY[20]), .B0(FPADDSUB_DMP[20]),
.B1(n4607), .Y(n4485) );
AOI22X1TS U6076 ( .A0(n4491), .A1(FPADDSUB_intDX[28]), .B0(FPADDSUB_DmP[28]),
.B1(n4610), .Y(n4486) );
AOI22X1TS U6077 ( .A0(n4491), .A1(FPADDSUB_intDY[18]), .B0(FPADDSUB_DMP[18]),
.B1(n4635), .Y(n4487) );
AOI22X1TS U6078 ( .A0(n4491), .A1(FPADDSUB_intDX[26]), .B0(FPADDSUB_DmP[26]),
.B1(n4610), .Y(n4488) );
AOI22X1TS U6079 ( .A0(n4491), .A1(FPADDSUB_intDX[25]), .B0(FPADDSUB_DmP[25]),
.B1(n4607), .Y(n4489) );
AOI22X1TS U6080 ( .A0(n4491), .A1(FPADDSUB_intDX[24]), .B0(FPADDSUB_DmP[24]),
.B1(n4607), .Y(n4490) );
AOI22X1TS U6081 ( .A0(n4501), .A1(FPADDSUB_intDY[14]), .B0(FPADDSUB_DMP[14]),
.B1(n4610), .Y(n4492) );
AOI22X1TS U6082 ( .A0(n4501), .A1(FPADDSUB_intDY[17]), .B0(FPADDSUB_DMP[17]),
.B1(n4607), .Y(n4493) );
AOI22X1TS U6083 ( .A0(n4501), .A1(FPADDSUB_intDY[11]), .B0(FPADDSUB_DMP[11]),
.B1(n4615), .Y(n4494) );
AOI22X1TS U6084 ( .A0(n4501), .A1(FPADDSUB_intDY[21]), .B0(FPADDSUB_DMP[21]),
.B1(n4615), .Y(n4495) );
AOI22X1TS U6085 ( .A0(n4501), .A1(FPADDSUB_intDY[15]), .B0(FPADDSUB_DMP[15]),
.B1(n4615), .Y(n4496) );
AOI22X1TS U6086 ( .A0(n4501), .A1(FPADDSUB_intDY[16]), .B0(FPADDSUB_DMP[16]),
.B1(n4610), .Y(n4497) );
AOI22X1TS U6087 ( .A0(n4501), .A1(FPADDSUB_intDX[30]), .B0(FPADDSUB_DmP[30]),
.B1(n4615), .Y(n4498) );
AOI22X1TS U6088 ( .A0(n4501), .A1(FPADDSUB_intDX[27]), .B0(FPADDSUB_DmP[27]),
.B1(n4597), .Y(n4499) );
AOI22X1TS U6089 ( .A0(FPADDSUB_DmP[12]), .A1(n4630), .B0(FPADDSUB_intDX[12]),
.B1(n4501), .Y(n4500) );
AOI22X1TS U6090 ( .A0(FPADDSUB_DmP[0]), .A1(n4635), .B0(FPADDSUB_intDX[0]),
.B1(n4501), .Y(n4502) );
NAND2X1TS U6091 ( .A(n4503), .B(FPADDSUB_intDX[31]), .Y(n4508) );
NAND3BX1TS U6092 ( .AN(n4506), .B(n4504), .C(n4505), .Y(n4507) );
OAI211X1TS U6093 ( .A0(n4483), .A1(n5861), .B0(n4508), .C0(n4507), .Y(n1327)
);
AOI22X1TS U6094 ( .A0(n4504), .A1(FPADDSUB_intDY[22]), .B0(FPADDSUB_DMP[22]),
.B1(n4607), .Y(n4509) );
AOI22X1TS U6095 ( .A0(n4504), .A1(FPADDSUB_intDX[29]), .B0(FPADDSUB_DmP[29]),
.B1(n4610), .Y(n4510) );
NAND2X1TS U6096 ( .A(n4512), .B(n4511), .Y(n4517) );
NAND3X1TS U6097 ( .A(n4513), .B(n4862), .C(FPADDSUB_add_overflow_flag), .Y(
n4514) );
BUFX3TS U6098 ( .A(FPADDSUB_FSM_selector_A), .Y(n4797) );
OAI21X4TS U6099 ( .A0(n4564), .A1(n4560), .B0(n4561), .Y(n4559) );
AOI21X4TS U6100 ( .A0(n4559), .A1(n2149), .B0(n4536), .Y(n4556) );
INVX2TS U6101 ( .A(n4560), .Y(n4562) );
INVX2TS U6102 ( .A(n4565), .Y(n4567) );
AFHCONX2TS U6103 ( .A(n4571), .B(n4581), .CI(n4570), .CON(n4576), .S(n5331)
);
INVX2TS U6104 ( .A(n4572), .Y(n4574) );
AND4X1TS U6105 ( .A(n5334), .B(n5332), .C(n5331), .D(n5330), .Y(n4577) );
AND4X1TS U6106 ( .A(n5337), .B(n5336), .C(n5335), .D(n4577), .Y(n4584) );
INVX2TS U6107 ( .A(n4581), .Y(n4582) );
AOI21X1TS U6108 ( .A0(n5338), .A1(n4584), .B0(n5339), .Y(n4586) );
NAND2X1TS U6109 ( .A(n4878), .B(overflow_flag_addsubt), .Y(n4585) );
INVX2TS U6110 ( .A(n4504), .Y(n4600) );
AOI22X1TS U6111 ( .A0(n4598), .A1(FPADDSUB_intDX[7]), .B0(FPADDSUB_DMP[7]),
.B1(n4597), .Y(n4587) );
AOI22X1TS U6112 ( .A0(n4598), .A1(FPADDSUB_intDX[5]), .B0(FPADDSUB_DMP[5]),
.B1(n4597), .Y(n4588) );
AOI22X1TS U6113 ( .A0(n4598), .A1(FPADDSUB_intDX[6]), .B0(FPADDSUB_DMP[6]),
.B1(n4597), .Y(n4589) );
AOI22X1TS U6114 ( .A0(n4598), .A1(FPADDSUB_intDX[9]), .B0(FPADDSUB_DMP[9]),
.B1(n4597), .Y(n4590) );
AOI22X1TS U6115 ( .A0(n4598), .A1(FPADDSUB_intDX[4]), .B0(FPADDSUB_DMP[4]),
.B1(n4597), .Y(n4591) );
AOI22X1TS U6116 ( .A0(n4598), .A1(FPADDSUB_intDX[10]), .B0(FPADDSUB_DMP[10]),
.B1(n4597), .Y(n4592) );
AOI22X1TS U6117 ( .A0(n4598), .A1(FPADDSUB_intDX[2]), .B0(FPADDSUB_DMP[2]),
.B1(n4630), .Y(n4593) );
AOI22X1TS U6118 ( .A0(n4598), .A1(FPADDSUB_intDX[1]), .B0(FPADDSUB_DMP[1]),
.B1(n4610), .Y(n4594) );
AOI22X1TS U6119 ( .A0(n4598), .A1(FPADDSUB_intDX[8]), .B0(FPADDSUB_DMP[8]),
.B1(n4597), .Y(n4595) );
INVX4TS U6120 ( .A(n2235), .Y(n4616) );
AOI22X1TS U6121 ( .A0(n4616), .A1(FPADDSUB_intDX[0]), .B0(FPADDSUB_DMP[0]),
.B1(n4630), .Y(n4596) );
AOI22X1TS U6122 ( .A0(n4598), .A1(FPADDSUB_intDX[3]), .B0(FPADDSUB_DMP[3]),
.B1(n4610), .Y(n4599) );
AOI22X1TS U6123 ( .A0(n4616), .A1(FPADDSUB_intDY[23]), .B0(FPADDSUB_DmP[23]),
.B1(n4607), .Y(n4601) );
AOI22X1TS U6124 ( .A0(n4616), .A1(FPADDSUB_intDX[23]), .B0(FPADDSUB_DMP[23]),
.B1(n4635), .Y(n4602) );
AOI22X1TS U6125 ( .A0(n4639), .A1(FPADDSUB_intDX[12]), .B0(FPADDSUB_DMP[12]),
.B1(n4597), .Y(n4603) );
AOI22X1TS U6126 ( .A0(n4616), .A1(FPADDSUB_intDX[25]), .B0(FPADDSUB_DMP[25]),
.B1(n4607), .Y(n4604) );
AOI22X1TS U6127 ( .A0(n4616), .A1(FPADDSUB_intDX[26]), .B0(FPADDSUB_DMP[26]),
.B1(n4607), .Y(n4605) );
AOI22X1TS U6128 ( .A0(n4616), .A1(FPADDSUB_intDX[29]), .B0(FPADDSUB_DMP[29]),
.B1(n4610), .Y(n4606) );
AOI22X1TS U6129 ( .A0(n4616), .A1(FPADDSUB_intDX[24]), .B0(FPADDSUB_DMP[24]),
.B1(n4607), .Y(n4608) );
AOI22X1TS U6130 ( .A0(n4616), .A1(FPADDSUB_intDX[28]), .B0(FPADDSUB_DMP[28]),
.B1(n4610), .Y(n4609) );
AOI22X1TS U6131 ( .A0(n4616), .A1(FPADDSUB_intDX[27]), .B0(FPADDSUB_DMP[27]),
.B1(n4610), .Y(n4611) );
AOI22X1TS U6132 ( .A0(FPADDSUB_DmP[1]), .A1(n4640), .B0(FPADDSUB_intDY[1]),
.B1(n4639), .Y(n4613) );
AOI22X1TS U6133 ( .A0(FPADDSUB_DmP[11]), .A1(n4630), .B0(FPADDSUB_intDY[11]),
.B1(n2234), .Y(n4614) );
AOI22X1TS U6134 ( .A0(n4616), .A1(FPADDSUB_intDX[30]), .B0(FPADDSUB_DMP[30]),
.B1(n4615), .Y(n4617) );
AOI22X1TS U6135 ( .A0(FPADDSUB_DmP[5]), .A1(n4640), .B0(FPADDSUB_intDY[5]),
.B1(n4639), .Y(n4618) );
AOI22X1TS U6136 ( .A0(FPADDSUB_DmP[9]), .A1(n4630), .B0(FPADDSUB_intDY[9]),
.B1(n2234), .Y(n4619) );
AOI22X1TS U6137 ( .A0(FPADDSUB_DmP[3]), .A1(n4635), .B0(FPADDSUB_intDY[3]),
.B1(n4634), .Y(n4620) );
AOI22X1TS U6138 ( .A0(FPADDSUB_DmP[7]), .A1(n4630), .B0(FPADDSUB_intDY[7]),
.B1(n4634), .Y(n4621) );
AOI22X1TS U6139 ( .A0(FPADDSUB_DmP[8]), .A1(n4640), .B0(FPADDSUB_intDY[8]),
.B1(n4639), .Y(n4622) );
AOI22X1TS U6140 ( .A0(FPADDSUB_DmP[2]), .A1(n4635), .B0(FPADDSUB_intDY[2]),
.B1(n4639), .Y(n4623) );
AOI22X1TS U6141 ( .A0(FPADDSUB_DmP[4]), .A1(n4640), .B0(FPADDSUB_intDY[4]),
.B1(n4634), .Y(n4624) );
AOI22X1TS U6142 ( .A0(FPADDSUB_DmP[13]), .A1(n4640), .B0(FPADDSUB_intDY[13]),
.B1(n4639), .Y(n4625) );
AOI22X1TS U6143 ( .A0(FPADDSUB_DmP[14]), .A1(n4630), .B0(FPADDSUB_intDY[14]),
.B1(n4634), .Y(n4626) );
AOI22X1TS U6144 ( .A0(FPADDSUB_DmP[6]), .A1(n4635), .B0(FPADDSUB_intDY[6]),
.B1(n4634), .Y(n4627) );
AOI22X1TS U6145 ( .A0(FPADDSUB_DmP[21]), .A1(n4640), .B0(FPADDSUB_intDY[21]),
.B1(n4639), .Y(n4628) );
AOI22X1TS U6146 ( .A0(FPADDSUB_DmP[19]), .A1(n4635), .B0(FPADDSUB_intDY[19]),
.B1(n4634), .Y(n4629) );
AOI22X1TS U6147 ( .A0(FPADDSUB_DmP[10]), .A1(n4630), .B0(FPADDSUB_intDY[10]),
.B1(n4634), .Y(n4631) );
AOI22X1TS U6148 ( .A0(FPADDSUB_DmP[18]), .A1(n4640), .B0(FPADDSUB_intDY[18]),
.B1(n4639), .Y(n4632) );
AOI22X1TS U6149 ( .A0(FPADDSUB_DmP[17]), .A1(n4635), .B0(FPADDSUB_intDY[17]),
.B1(n4634), .Y(n4633) );
AOI22X1TS U6150 ( .A0(FPADDSUB_DmP[22]), .A1(n4635), .B0(FPADDSUB_intDY[22]),
.B1(n4634), .Y(n4636) );
AOI22X1TS U6151 ( .A0(FPADDSUB_DmP[15]), .A1(n4640), .B0(FPADDSUB_intDY[15]),
.B1(n4639), .Y(n4637) );
AOI22X1TS U6152 ( .A0(FPADDSUB_DmP[20]), .A1(n4640), .B0(FPADDSUB_intDY[20]),
.B1(n4639), .Y(n4641) );
NAND2X1TS U6153 ( .A(n4643), .B(n5825), .Y(n4649) );
OAI31X1TS U6154 ( .A0(n5765), .A1(n5492), .A2(n5484), .B0(n5712), .Y(n4655)
);
INVX2TS U6155 ( .A(n4655), .Y(n4659) );
NAND2X1TS U6156 ( .A(operation[1]), .B(ack_operation), .Y(n4657) );
OAI32X1TS U6157 ( .A0(n4663), .A1(n4657), .A2(n4656), .B0(n5712), .B1(n4663),
.Y(n4658) );
AOI211X1TS U6158 ( .A0(operation[1]), .A1(begin_operation), .B0(
FPSENCOS_cordic_FSM_state_reg[2]), .C0(
FPSENCOS_cordic_FSM_state_reg[3]), .Y(n4661) );
AOI211XLTS U6159 ( .A0(n4664), .A1(n5717), .B0(n4663), .C0(n4662), .Y(n4665)
);
XOR2X1TS U6160 ( .A(n4696), .B(FPADDSUB_Sgf_normalized_result[1]), .Y(n4669)
);
NOR2X2TS U6161 ( .A(n4669), .B(n4668), .Y(n4887) );
OR2X1TS U6162 ( .A(n4795), .B(FPADDSUB_Sgf_normalized_result[2]), .Y(n4670)
);
XOR2X1TS U6163 ( .A(n4696), .B(n4670), .Y(n4675) );
BUFX3TS U6164 ( .A(FPADDSUB_FSM_selector_A), .Y(n4700) );
NOR2X1TS U6165 ( .A(n4887), .B(n4889), .Y(n4677) );
INVX4TS U6166 ( .A(n4848), .Y(n4803) );
BUFX3TS U6167 ( .A(FPADDSUB_FSM_selector_A), .Y(n4800) );
NOR2BX1TS U6168 ( .AN(FPADDSUB_Sgf_normalized_result[0]), .B(n4800), .Y(
n4671) );
XOR2X1TS U6169 ( .A(n4803), .B(n4671), .Y(n4788) );
INVX2TS U6170 ( .A(n4788), .Y(n4673) );
NOR2X1TS U6171 ( .A(n4803), .B(n4672), .Y(n4789) );
NOR2X1TS U6172 ( .A(n4673), .B(n4789), .Y(n4879) );
NAND2X1TS U6173 ( .A(n4675), .B(n4674), .Y(n4890) );
INVX2TS U6174 ( .A(n4890), .Y(n4676) );
NOR2BX1TS U6175 ( .AN(FPADDSUB_Sgf_normalized_result[3]), .B(n4801), .Y(
n4678) );
XOR2X1TS U6176 ( .A(n4696), .B(n4678), .Y(n4683) );
NOR2X1TS U6177 ( .A(n4683), .B(n4682), .Y(n4896) );
NOR2BX1TS U6178 ( .AN(FPADDSUB_Sgf_normalized_result[4]), .B(n4800), .Y(
n4679) );
XOR2X1TS U6179 ( .A(n4696), .B(n4679), .Y(n4685) );
NOR2X2TS U6180 ( .A(n4685), .B(n4684), .Y(n4914) );
NOR2X1TS U6181 ( .A(n4896), .B(n4914), .Y(n4928) );
NOR2BX1TS U6182 ( .AN(FPADDSUB_Sgf_normalized_result[5]), .B(n4800), .Y(
n4680) );
NOR2X2TS U6183 ( .A(n4687), .B(n4686), .Y(n4934) );
NOR2BX1TS U6184 ( .AN(FPADDSUB_Sgf_normalized_result[6]), .B(n4801), .Y(
n4681) );
XOR2X1TS U6185 ( .A(n4696), .B(n4681), .Y(n4689) );
NOR2X2TS U6186 ( .A(n4689), .B(n4688), .Y(n4936) );
NAND2X1TS U6187 ( .A(n4683), .B(n4682), .Y(n4911) );
NAND2X1TS U6188 ( .A(n4685), .B(n4684), .Y(n4915) );
NAND2X1TS U6189 ( .A(n4687), .B(n4686), .Y(n4933) );
NAND2X1TS U6190 ( .A(n4689), .B(n4688), .Y(n4937) );
OAI21X1TS U6191 ( .A0(n4936), .A1(n4933), .B0(n4937), .Y(n4690) );
AOI21X2TS U6192 ( .A0(n4927), .A1(n4691), .B0(n4690), .Y(n4692) );
NOR2BX1TS U6193 ( .AN(FPADDSUB_Sgf_normalized_result[7]), .B(n4801), .Y(
n4694) );
NOR2X2TS U6194 ( .A(n4705), .B(n4704), .Y(n4963) );
NOR2BX1TS U6195 ( .AN(FPADDSUB_Sgf_normalized_result[8]), .B(n4801), .Y(
n4695) );
XOR2X1TS U6196 ( .A(n4696), .B(n4695), .Y(n4707) );
NOR2X2TS U6197 ( .A(n4707), .B(n4706), .Y(n4964) );
NOR2BX1TS U6198 ( .AN(FPADDSUB_Sgf_normalized_result[9]), .B(n4801), .Y(
n4697) );
XOR2X1TS U6199 ( .A(n4752), .B(n4697), .Y(n4709) );
NOR2X1TS U6200 ( .A(n4709), .B(n4708), .Y(n4982) );
NOR2BX1TS U6201 ( .AN(FPADDSUB_Sgf_normalized_result[10]), .B(n4801), .Y(
n4698) );
XOR2X1TS U6202 ( .A(n4752), .B(n4698), .Y(n4711) );
NOR2X2TS U6203 ( .A(n4711), .B(n4710), .Y(n4989) );
NAND2X2TS U6204 ( .A(n4978), .B(n4713), .Y(n5000) );
NOR2BX1TS U6205 ( .AN(FPADDSUB_Sgf_normalized_result[11]), .B(n4801), .Y(
n4699) );
XOR2X1TS U6206 ( .A(n4752), .B(n4701), .Y(n4717) );
BUFX3TS U6207 ( .A(FPADDSUB_FSM_selector_A), .Y(n4753) );
NOR2X2TS U6208 ( .A(n4717), .B(n4716), .Y(n5027) );
XOR2X1TS U6209 ( .A(n4752), .B(n4702), .Y(n4719) );
NOR2X1TS U6210 ( .A(n4719), .B(n4718), .Y(n5006) );
XOR2X1TS U6211 ( .A(n4752), .B(n4703), .Y(n4721) );
NOR2X2TS U6212 ( .A(n4721), .B(n4720), .Y(n5008) );
NAND2X2TS U6213 ( .A(n5002), .B(n4723), .Y(n4725) );
NAND2X1TS U6214 ( .A(n4707), .B(n4706), .Y(n4965) );
OAI21X1TS U6215 ( .A0(n4964), .A1(n4962), .B0(n4965), .Y(n4979) );
NAND2X1TS U6216 ( .A(n4709), .B(n4708), .Y(n4985) );
NAND2X1TS U6217 ( .A(n4711), .B(n4710), .Y(n4990) );
OAI21X1TS U6218 ( .A0(n4989), .A1(n4985), .B0(n4990), .Y(n4712) );
AOI21X2TS U6219 ( .A0(n4979), .A1(n4713), .B0(n4712), .Y(n4999) );
NAND2X2TS U6220 ( .A(n4715), .B(n4714), .Y(n5023) );
NAND2X1TS U6221 ( .A(n4717), .B(n4716), .Y(n5028) );
OAI21X1TS U6222 ( .A0(n5027), .A1(n5023), .B0(n5028), .Y(n5003) );
NAND2X1TS U6223 ( .A(n4719), .B(n4718), .Y(n5018) );
NAND2X1TS U6224 ( .A(n4721), .B(n4720), .Y(n5009) );
OAI21X1TS U6225 ( .A0(n5008), .A1(n5018), .B0(n5009), .Y(n4722) );
AOI21X1TS U6226 ( .A0(n5003), .A1(n4723), .B0(n4722), .Y(n4724) );
OAI21X2TS U6227 ( .A0(n4999), .A1(n4725), .B0(n4724), .Y(n4726) );
XOR2X1TS U6228 ( .A(n4752), .B(n4728), .Y(n4731) );
XOR2X1TS U6229 ( .A(n4752), .B(n4729), .Y(n4733) );
NAND2X1TS U6230 ( .A(n2335), .B(n4973), .Y(n4736) );
NAND2X1TS U6231 ( .A(n4731), .B(n4730), .Y(n4995) );
INVX2TS U6232 ( .A(n4995), .Y(n4971) );
NAND2X1TS U6233 ( .A(n4733), .B(n4732), .Y(n4972) );
INVX2TS U6234 ( .A(n4972), .Y(n4734) );
AOI21X1TS U6235 ( .A0(n4973), .A1(n4971), .B0(n4734), .Y(n4735) );
OAI21X4TS U6236 ( .A0(n4970), .A1(n4736), .B0(n4735), .Y(n4960) );
XOR2X1TS U6237 ( .A(n4752), .B(n4737), .Y(n4739) );
NAND2X1TS U6238 ( .A(n4739), .B(n4738), .Y(n4957) );
INVX2TS U6239 ( .A(n4957), .Y(n4740) );
AOI21X4TS U6240 ( .A0(n4960), .A1(n4958), .B0(n4740), .Y(n4951) );
XOR2X1TS U6241 ( .A(n4803), .B(n4741), .Y(n4743) );
NOR2X1TS U6242 ( .A(n4743), .B(n4742), .Y(n4947) );
NAND2X1TS U6243 ( .A(n4743), .B(n4742), .Y(n4948) );
OAI21X4TS U6244 ( .A0(n4951), .A1(n4947), .B0(n4948), .Y(n4945) );
XOR2X1TS U6245 ( .A(n4803), .B(n4744), .Y(n4746) );
NAND2X1TS U6246 ( .A(n4746), .B(n4745), .Y(n4942) );
INVX2TS U6247 ( .A(n4942), .Y(n4747) );
AOI21X4TS U6248 ( .A0(n4945), .A1(n4943), .B0(n4747), .Y(n4925) );
XOR2X1TS U6249 ( .A(n4803), .B(n4748), .Y(n4750) );
NOR2X1TS U6250 ( .A(n4750), .B(n4749), .Y(n4921) );
NAND2X1TS U6251 ( .A(n4750), .B(n4749), .Y(n4922) );
OAI21X4TS U6252 ( .A0(n4925), .A1(n4921), .B0(n4922), .Y(n4908) );
XOR2X1TS U6253 ( .A(n4752), .B(n4751), .Y(n4755) );
NAND2X1TS U6254 ( .A(n4755), .B(n4754), .Y(n4905) );
INVX2TS U6255 ( .A(n4905), .Y(n4756) );
AOI21X4TS U6256 ( .A0(n4908), .A1(n4906), .B0(n4756), .Y(n4903) );
XOR2X1TS U6257 ( .A(n4803), .B(n4757), .Y(n4759) );
NOR2X1TS U6258 ( .A(n4759), .B(n4758), .Y(n4899) );
NAND2X1TS U6259 ( .A(n4759), .B(n4758), .Y(n4900) );
OAI21X4TS U6260 ( .A0(n4903), .A1(n4899), .B0(n4900), .Y(n4794) );
XOR2X1TS U6261 ( .A(n4803), .B(n4760), .Y(n4762) );
NAND2X1TS U6262 ( .A(n4762), .B(n4761), .Y(n4791) );
NAND2X1TS U6263 ( .A(n4793), .B(n4791), .Y(n4763) );
XNOR2X1TS U6264 ( .A(n4794), .B(n4763), .Y(n4764) );
BUFX3TS U6265 ( .A(n4919), .Y(n4909) );
NOR3BX1TS U6266 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n4765) );
XOR2X1TS U6267 ( .A(n2272), .B(n4765), .Y(DP_OP_134J12_124_859_n15) );
OAI2BB1X1TS U6268 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5724), .B0(n2349), .Y(
n4766) );
XOR2X1TS U6269 ( .A(n2272), .B(n4766), .Y(DP_OP_134J12_124_859_n16) );
OAI2BB1X1TS U6270 ( .A0N(FPMULT_Op_MY[28]), .A1N(n5724), .B0(n2349), .Y(
n4767) );
XOR2X1TS U6271 ( .A(n2272), .B(n4767), .Y(DP_OP_134J12_124_859_n17) );
OAI2BB1X1TS U6272 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5724), .B0(n2349), .Y(
n4768) );
XOR2X1TS U6273 ( .A(n2272), .B(n4768), .Y(DP_OP_134J12_124_859_n18) );
OAI2BB1X1TS U6274 ( .A0N(FPMULT_Op_MY[26]), .A1N(n5724), .B0(n2349), .Y(
n4769) );
XOR2X1TS U6275 ( .A(n2272), .B(n4769), .Y(DP_OP_134J12_124_859_n19) );
OAI2BB1X1TS U6276 ( .A0N(FPMULT_Op_MY[25]), .A1N(n5724), .B0(n2349), .Y(
n4770) );
XOR2X1TS U6277 ( .A(n3034), .B(n4770), .Y(DP_OP_134J12_124_859_n20) );
OAI2BB1X1TS U6278 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5724), .B0(n2349), .Y(
n4771) );
XOR2X1TS U6279 ( .A(n3034), .B(n4771), .Y(DP_OP_134J12_124_859_n21) );
XOR2X1TS U6280 ( .A(n3034), .B(n4773), .Y(DP_OP_134J12_124_859_n22) );
AOI22X1TS U6281 ( .A0(FPSENCOS_d_ff_Zn[31]), .A1(n4059), .B0(n4774), .B1(
FPSENCOS_d_ff1_Z[31]), .Y(n4775) );
OAI2BB1X1TS U6282 ( .A0N(FPSENCOS_d_ff2_Z[31]), .A1N(n5658), .B0(n4775), .Y(
n1475) );
AOI22X1TS U6283 ( .A0(Data_1[31]), .A1(n4781), .B0(FPADDSUB_intDX[31]), .B1(
n4780), .Y(n4777) );
OAI2BB1X1TS U6284 ( .A0N(FPSENCOS_d_ff2_Z[31]), .A1N(n4144), .B0(n4777), .Y(
n4778) );
AOI21X1TS U6285 ( .A0(n4783), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n4778), .Y(
n4779) );
OAI2BB1X1TS U6286 ( .A0N(n5706), .A1N(FPSENCOS_d_ff2_X[31]), .B0(n4779), .Y(
n1329) );
AOI21X1TS U6287 ( .A0(n4783), .A1(FPSENCOS_d_ff3_sh_x_out[31]), .B0(n4782),
.Y(n4784) );
OAI2BB1X1TS U6288 ( .A0N(n2206), .A1N(FPSENCOS_d_ff3_sh_y_out[31]), .B0(
n4784), .Y(n1330) );
AOI22X1TS U6289 ( .A0(n2305), .A1(n5442), .B0(n2244), .B1(n5439), .Y(n4787)
);
OAI22X1TS U6290 ( .A0(n4787), .A1(n5443), .B0(n4786), .B1(n5444), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
XNOR2X1TS U6291 ( .A(n4789), .B(n4788), .Y(n4790) );
INVX2TS U6292 ( .A(n4791), .Y(n4792) );
AOI21X4TS U6293 ( .A0(n4794), .A1(n4793), .B0(n4792), .Y(n4885) );
XOR2X1TS U6294 ( .A(n4803), .B(n4796), .Y(n4799) );
NOR2X1TS U6295 ( .A(n4799), .B(n4798), .Y(n4881) );
NAND2X1TS U6296 ( .A(n4799), .B(n4798), .Y(n4882) );
OAI21X4TS U6297 ( .A0(n4885), .A1(n4881), .B0(n4882), .Y(n4847) );
NOR2BX1TS U6298 ( .AN(FPADDSUB_Sgf_normalized_result[25]), .B(n4801), .Y(
n4802) );
XOR2X1TS U6299 ( .A(n4803), .B(n4802), .Y(n4845) );
INVX2TS U6300 ( .A(n4845), .Y(n4804) );
NAND2X1TS U6301 ( .A(n4846), .B(n4804), .Y(n4805) );
XNOR2X1TS U6302 ( .A(n4847), .B(n4805), .Y(n4806) );
NAND2X1TS U6303 ( .A(n5442), .B(n4371), .Y(n4809) );
OAI22X1TS U6304 ( .A0(n4217), .A1(n4809), .B0(n4808), .B1(n5444), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[25]) );
INVX2TS U6305 ( .A(n4810), .Y(n4832) );
NAND2X2TS U6306 ( .A(n3817), .B(n4811), .Y(n4830) );
AOI21X1TS U6307 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[28]), .A1(n2254),
.B0(n4827), .Y(n4813) );
AOI22X1TS U6308 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[49]), .A1(n2262),
.B0(FPADDSUB_Sgf_normalized_result[23]), .B1(n4839), .Y(n4812) );
AOI21X1TS U6309 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(n2254),
.B0(n4827), .Y(n4816) );
AOI22X1TS U6310 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(n2262),
.B0(FPADDSUB_Sgf_normalized_result[22]), .B1(n4839), .Y(n4815) );
AOI21X1TS U6311 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[30]), .A1(n2254),
.B0(n4827), .Y(n4819) );
AOI22X1TS U6312 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(n2262),
.B0(FPADDSUB_Sgf_normalized_result[21]), .B1(n4839), .Y(n4818) );
AOI21X1TS U6313 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(n2253),
.B0(n4827), .Y(n4822) );
AOI22X1TS U6314 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(n2262),
.B0(FPADDSUB_Sgf_normalized_result[20]), .B1(n4839), .Y(n4821) );
AOI21X1TS U6315 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[32]), .A1(n2253),
.B0(n4827), .Y(n4825) );
AOI22X1TS U6316 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(n2262),
.B0(FPADDSUB_Sgf_normalized_result[19]), .B1(n4839), .Y(n4824) );
AOI21X1TS U6317 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(n2263),
.B0(n4827), .Y(n4829) );
AOI22X1TS U6318 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(n2253),
.B0(FPADDSUB_Sgf_normalized_result[18]), .B1(n4839), .Y(n4828) );
INVX2TS U6319 ( .A(n4833), .Y(n4844) );
NAND2X1TS U6320 ( .A(n3817), .B(n4834), .Y(n4837) );
AOI22X1TS U6321 ( .A0(n2264), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]), .B0(
FPADDSUB_Sgf_normalized_result[17]), .B1(n4839), .Y(n4836) );
NAND2X1TS U6322 ( .A(n3883), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[51]), .Y(n4835) );
NAND2X1TS U6323 ( .A(n3817), .B(n4838), .Y(n4843) );
AOI22X1TS U6324 ( .A0(n2263), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
FPADDSUB_Sgf_normalized_result[16]), .B1(n4839), .Y(n4842) );
NAND2X1TS U6325 ( .A(n4840), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[50]), .Y(n4841) );
AOI21X2TS U6326 ( .A0(n4847), .A1(n4846), .B0(n4845), .Y(n4849) );
AOI21X1TS U6327 ( .A0(n4852), .A1(n5773), .B0(n4851), .Y(n4853) );
NOR2X1TS U6328 ( .A(n4854), .B(n4853), .Y(n4859) );
AOI22X1TS U6329 ( .A0(FPADDSUB_Add_Subt_result[5]), .A1(n4856), .B0(
FPADDSUB_Add_Subt_result[3]), .B1(n4855), .Y(n4858) );
NAND4X1TS U6330 ( .A(n4860), .B(n4859), .C(n4858), .D(n4857), .Y(n4861) );
AO22X1TS U6331 ( .A0(n4861), .A1(n4876), .B0(FPADDSUB_LZA_output[2]), .B1(
n4875), .Y(n1656) );
MXI2X1TS U6332 ( .A(FPADDSUB_add_overflow_flag), .B(n5770), .S0(n4862), .Y(
n1695) );
AOI211X1TS U6333 ( .A0(n4870), .A1(n4869), .B0(n4868), .C0(n4867), .Y(n4872)
);
XOR2X1TS U6334 ( .A(n4887), .B(n4888), .Y(n4880) );
INVX2TS U6335 ( .A(n4881), .Y(n4883) );
NAND2X1TS U6336 ( .A(n4883), .B(n4882), .Y(n4884) );
XOR2X1TS U6337 ( .A(n4885), .B(n4884), .Y(n4886) );
INVX2TS U6338 ( .A(n4889), .Y(n4891) );
NAND2X1TS U6339 ( .A(n4891), .B(n4890), .Y(n4892) );
XNOR2X1TS U6340 ( .A(n4893), .B(n4892), .Y(n4894) );
INVX2TS U6341 ( .A(n4895), .Y(n4929) );
INVX2TS U6342 ( .A(n4896), .Y(n4913) );
NAND2X1TS U6343 ( .A(n4913), .B(n4911), .Y(n4897) );
XNOR2X1TS U6344 ( .A(n4929), .B(n4897), .Y(n4898) );
INVX2TS U6345 ( .A(n4899), .Y(n4901) );
NAND2X1TS U6346 ( .A(n4901), .B(n4900), .Y(n4902) );
XOR2X1TS U6347 ( .A(n4903), .B(n4902), .Y(n4904) );
NAND2X1TS U6348 ( .A(n4906), .B(n4905), .Y(n4907) );
XNOR2X1TS U6349 ( .A(n4908), .B(n4907), .Y(n4910) );
AOI21X1TS U6350 ( .A0(n4929), .A1(n4913), .B0(n4912), .Y(n4918) );
INVX2TS U6351 ( .A(n4914), .Y(n4916) );
NAND2X1TS U6352 ( .A(n4916), .B(n4915), .Y(n4917) );
XOR2X1TS U6353 ( .A(n4918), .B(n4917), .Y(n4920) );
BUFX3TS U6354 ( .A(n4919), .Y(n4976) );
INVX2TS U6355 ( .A(n4921), .Y(n4923) );
NAND2X1TS U6356 ( .A(n4923), .B(n4922), .Y(n4924) );
XOR2X1TS U6357 ( .A(n4925), .B(n4924), .Y(n4926) );
AOI21X1TS U6358 ( .A0(n4929), .A1(n4928), .B0(n4927), .Y(n4935) );
INVX2TS U6359 ( .A(n4934), .Y(n4930) );
NAND2X1TS U6360 ( .A(n4930), .B(n4933), .Y(n4931) );
XOR2X1TS U6361 ( .A(n4935), .B(n4931), .Y(n4932) );
INVX2TS U6362 ( .A(n4936), .Y(n4938) );
NAND2X1TS U6363 ( .A(n4938), .B(n4937), .Y(n4939) );
XNOR2X1TS U6364 ( .A(n4940), .B(n4939), .Y(n4941) );
NAND2X1TS U6365 ( .A(n4943), .B(n4942), .Y(n4944) );
XNOR2X1TS U6366 ( .A(n4945), .B(n4944), .Y(n4946) );
INVX2TS U6367 ( .A(n4947), .Y(n4949) );
NAND2X1TS U6368 ( .A(n4949), .B(n4948), .Y(n4950) );
XOR2X1TS U6369 ( .A(n4951), .B(n4950), .Y(n4952) );
INVX2TS U6370 ( .A(n4953), .Y(n5001) );
INVX2TS U6371 ( .A(n4963), .Y(n4954) );
NAND2X1TS U6372 ( .A(n4954), .B(n4962), .Y(n4955) );
XOR2X1TS U6373 ( .A(n5001), .B(n4955), .Y(n4956) );
NAND2X1TS U6374 ( .A(n4958), .B(n4957), .Y(n4959) );
XNOR2X1TS U6375 ( .A(n4960), .B(n4959), .Y(n4961) );
INVX2TS U6376 ( .A(n4964), .Y(n4966) );
NAND2X1TS U6377 ( .A(n4966), .B(n4965), .Y(n4967) );
XNOR2X1TS U6378 ( .A(n4968), .B(n4967), .Y(n4969) );
INVX2TS U6379 ( .A(n4970), .Y(n4997) );
AOI21X1TS U6380 ( .A0(n4997), .A1(n2335), .B0(n4971), .Y(n4975) );
NAND2X1TS U6381 ( .A(n4973), .B(n4972), .Y(n4974) );
XOR2X1TS U6382 ( .A(n4975), .B(n4974), .Y(n4977) );
INVX2TS U6383 ( .A(n4978), .Y(n4981) );
OAI21X1TS U6384 ( .A0(n5001), .A1(n4981), .B0(n4980), .Y(n4988) );
INVX2TS U6385 ( .A(n4982), .Y(n4987) );
NAND2X1TS U6386 ( .A(n4987), .B(n4985), .Y(n4983) );
XNOR2X1TS U6387 ( .A(n4988), .B(n4983), .Y(n4984) );
INVX2TS U6388 ( .A(n4985), .Y(n4986) );
AOI21X1TS U6389 ( .A0(n4988), .A1(n4987), .B0(n4986), .Y(n4993) );
INVX2TS U6390 ( .A(n4989), .Y(n4991) );
NAND2X1TS U6391 ( .A(n4991), .B(n4990), .Y(n4992) );
XOR2X1TS U6392 ( .A(n4993), .B(n4992), .Y(n4994) );
NAND2X1TS U6393 ( .A(n2335), .B(n4995), .Y(n4996) );
XNOR2X1TS U6394 ( .A(n4997), .B(n4996), .Y(n4998) );
OAI21X1TS U6395 ( .A0(n5001), .A1(n5000), .B0(n4999), .Y(n5026) );
INVX2TS U6396 ( .A(n5026), .Y(n5016) );
INVX2TS U6397 ( .A(n5002), .Y(n5005) );
INVX2TS U6398 ( .A(n5003), .Y(n5004) );
OAI21X1TS U6399 ( .A0(n5016), .A1(n5005), .B0(n5004), .Y(n5021) );
INVX2TS U6400 ( .A(n5006), .Y(n5019) );
INVX2TS U6401 ( .A(n5018), .Y(n5007) );
AOI21X1TS U6402 ( .A0(n5021), .A1(n5019), .B0(n5007), .Y(n5012) );
INVX2TS U6403 ( .A(n5008), .Y(n5010) );
NAND2X1TS U6404 ( .A(n5010), .B(n5009), .Y(n5011) );
XOR2X1TS U6405 ( .A(n5012), .B(n5011), .Y(n5013) );
INVX2TS U6406 ( .A(n5014), .Y(n5025) );
NAND2X1TS U6407 ( .A(n5025), .B(n5023), .Y(n5015) );
XOR2X1TS U6408 ( .A(n5016), .B(n5015), .Y(n5017) );
NAND2X1TS U6409 ( .A(n5019), .B(n5018), .Y(n5020) );
XNOR2X1TS U6410 ( .A(n5021), .B(n5020), .Y(n5022) );
INVX2TS U6411 ( .A(n5023), .Y(n5024) );
AOI21X1TS U6412 ( .A0(n5026), .A1(n5025), .B0(n5024), .Y(n5031) );
INVX2TS U6413 ( .A(n5027), .Y(n5029) );
NAND2X1TS U6414 ( .A(n5029), .B(n5028), .Y(n5030) );
XOR2X1TS U6415 ( .A(n5031), .B(n5030), .Y(n5032) );
NAND2X1TS U6416 ( .A(FPMULT_Sgf_normalized_result[6]), .B(
FPMULT_Sgf_normalized_result[7]), .Y(n5042) );
NAND2X1TS U6417 ( .A(FPMULT_Sgf_normalized_result[5]), .B(
FPMULT_Sgf_normalized_result[4]), .Y(n5210) );
NOR2X1TS U6418 ( .A(n5725), .B(n5787), .Y(n5173) );
NAND2X1TS U6419 ( .A(n5173), .B(FPMULT_Sgf_normalized_result[10]), .Y(n5045)
);
MXI2X1TS U6420 ( .A(FPMULT_P_Sgf[46]), .B(FPMULT_Add_result[23]), .S0(
FPMULT_FSM_selector_C), .Y(n5047) );
AOI21X1TS U6421 ( .A0(n5048), .A1(n5047), .B0(n5182), .Y(n5049) );
AHHCINX2TS U6422 ( .A(FPMULT_Sgf_normalized_result[22]), .CIN(n5050), .S(
n5051), .CO(n5314) );
INVX2TS U6423 ( .A(n5098), .Y(n5089) );
AOI22X1TS U6424 ( .A0(n2174), .A1(FPMULT_Add_result[23]), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n5182), .Y(n5055) );
OAI2BB1X1TS U6425 ( .A0N(FPMULT_P_Sgf[46]), .A1N(n2310), .B0(n5055), .Y(
n5056) );
AOI21X1TS U6426 ( .A0(n5306), .A1(FPMULT_Add_result[22]), .B0(n5056), .Y(
n5057) );
OAI2BB1X1TS U6427 ( .A0N(n2255), .A1N(FPMULT_P_Sgf[45]), .B0(n5057), .Y(
n1891) );
AHHCONX2TS U6428 ( .A(FPMULT_Sgf_normalized_result[21]), .CI(n5058), .CON(
n5050), .S(n5059) );
AOI22X1TS U6429 ( .A0(n5060), .A1(FPMULT_Add_result[22]), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n5182), .Y(n5061) );
OAI2BB1X1TS U6430 ( .A0N(FPMULT_P_Sgf[45]), .A1N(n2309), .B0(n5061), .Y(
n5062) );
AOI21X1TS U6431 ( .A0(n2308), .A1(FPMULT_Add_result[21]), .B0(n5062), .Y(
n5063) );
OAI2BB1X1TS U6432 ( .A0N(n2255), .A1N(FPMULT_P_Sgf[44]), .B0(n5063), .Y(
n1890) );
AHHCINX2TS U6433 ( .A(FPMULT_Sgf_normalized_result[20]), .CIN(n5064), .S(
n5065), .CO(n5058) );
XOR2X1TS U6434 ( .A(n5067), .B(n5066), .Y(n5068) );
AOI22X1TS U6435 ( .A0(n2173), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n5182), .Y(n5069) );
OAI2BB1X1TS U6436 ( .A0N(n2310), .A1N(FPMULT_P_Sgf[44]), .B0(n5069), .Y(
n5070) );
AOI21X1TS U6437 ( .A0(n2308), .A1(FPMULT_Add_result[20]), .B0(n5070), .Y(
n5071) );
OAI2BB1X1TS U6438 ( .A0N(n2255), .A1N(FPMULT_P_Sgf[43]), .B0(n5071), .Y(
n1889) );
AHHCONX2TS U6439 ( .A(FPMULT_Sgf_normalized_result[19]), .CI(n5072), .CON(
n5064), .S(n5073) );
XNOR2X1TS U6440 ( .A(n5075), .B(n5074), .Y(n5076) );
AOI22X1TS U6441 ( .A0(n2174), .A1(FPMULT_Add_result[20]), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n5168), .Y(n5077) );
OAI2BB1X1TS U6442 ( .A0N(n2311), .A1N(FPMULT_P_Sgf[43]), .B0(n5077), .Y(
n5078) );
AOI21X1TS U6443 ( .A0(n2308), .A1(FPMULT_Add_result[19]), .B0(n5078), .Y(
n5079) );
OAI2BB1X1TS U6444 ( .A0N(n2255), .A1N(FPMULT_P_Sgf[42]), .B0(n5079), .Y(
n1888) );
AHHCINX2TS U6445 ( .A(FPMULT_Sgf_normalized_result[18]), .CIN(n5080), .S(
n5081), .CO(n5072) );
XOR2X1TS U6446 ( .A(n5083), .B(n5082), .Y(n5084) );
AOI22X1TS U6447 ( .A0(n2174), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n5168), .Y(n5085) );
OAI2BB1X1TS U6448 ( .A0N(n2311), .A1N(FPMULT_P_Sgf[42]), .B0(n5085), .Y(
n5086) );
AOI21X1TS U6449 ( .A0(n3905), .A1(FPMULT_Add_result[18]), .B0(n5086), .Y(
n5087) );
OAI2BB1X1TS U6450 ( .A0N(n2255), .A1N(FPMULT_P_Sgf[41]), .B0(n5087), .Y(
n1887) );
AHHCONX2TS U6451 ( .A(FPMULT_Sgf_normalized_result[17]), .CI(n5088), .CON(
n5080), .S(n5090) );
XNOR2X1TS U6452 ( .A(n5092), .B(n5091), .Y(n5093) );
AOI22X1TS U6453 ( .A0(n2173), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n5168), .Y(n5094) );
OAI2BB1X1TS U6454 ( .A0N(n2309), .A1N(FPMULT_P_Sgf[41]), .B0(n5094), .Y(
n5095) );
AOI21X1TS U6455 ( .A0(n2308), .A1(FPMULT_Add_result[17]), .B0(n5095), .Y(
n5096) );
OAI2BB1X1TS U6456 ( .A0N(n2255), .A1N(FPMULT_P_Sgf[40]), .B0(n5096), .Y(
n1886) );
AHHCINX2TS U6457 ( .A(FPMULT_Sgf_normalized_result[16]), .CIN(n5097), .S(
n5099), .CO(n5088) );
AOI21X1TS U6458 ( .A0(n5204), .A1(n5102), .B0(n5101), .Y(n5104) );
XOR2X1TS U6459 ( .A(n5104), .B(n5103), .Y(n5105) );
AOI22X1TS U6460 ( .A0(n2173), .A1(FPMULT_Add_result[17]), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n5168), .Y(n5106) );
OAI2BB1X1TS U6461 ( .A0N(n2309), .A1N(FPMULT_P_Sgf[40]), .B0(n5106), .Y(
n5107) );
AOI21X1TS U6462 ( .A0(n2308), .A1(FPMULT_Add_result[16]), .B0(n5107), .Y(
n5108) );
OAI2BB1X1TS U6463 ( .A0N(n2256), .A1N(FPMULT_P_Sgf[39]), .B0(n5108), .Y(
n1885) );
AHHCONX2TS U6464 ( .A(FPMULT_Sgf_normalized_result[15]), .CI(n5109), .CON(
n5097), .S(n5110) );
INVX2TS U6465 ( .A(n5111), .Y(n5114) );
INVX2TS U6466 ( .A(n5112), .Y(n5113) );
AOI21X4TS U6467 ( .A0(n5204), .A1(n5114), .B0(n5113), .Y(n5136) );
INVX2TS U6468 ( .A(n5136), .Y(n5153) );
AOI21X2TS U6469 ( .A0(n5153), .A1(n5116), .B0(n5115), .Y(n5129) );
AOI22X1TS U6470 ( .A0(n5060), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n5168), .Y(n5120) );
OAI2BB1X1TS U6471 ( .A0N(n2310), .A1N(FPMULT_P_Sgf[39]), .B0(n5120), .Y(
n5121) );
AOI21X1TS U6472 ( .A0(n2308), .A1(FPMULT_Add_result[15]), .B0(n5121), .Y(
n5122) );
OAI2BB1X1TS U6473 ( .A0N(n2257), .A1N(FPMULT_P_Sgf[38]), .B0(n5122), .Y(
n1884) );
AHHCINX2TS U6474 ( .A(FPMULT_Sgf_normalized_result[14]), .CIN(n5123), .S(
n5124), .CO(n5109) );
INVX2TS U6475 ( .A(n5125), .Y(n5127) );
NAND2X1TS U6476 ( .A(n5127), .B(n5126), .Y(n5128) );
XOR2X1TS U6477 ( .A(n5129), .B(n5128), .Y(n5130) );
AOI22X1TS U6478 ( .A0(n2173), .A1(FPMULT_Add_result[15]), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n5168), .Y(n5131) );
OAI2BB1X1TS U6479 ( .A0N(n2310), .A1N(FPMULT_P_Sgf[38]), .B0(n5131), .Y(
n5132) );
AOI21X1TS U6480 ( .A0(n3905), .A1(FPMULT_Add_result[14]), .B0(n5132), .Y(
n5133) );
OAI2BB1X1TS U6481 ( .A0N(n2256), .A1N(FPMULT_P_Sgf[37]), .B0(n5133), .Y(
n1883) );
AHHCONX2TS U6482 ( .A(FPMULT_Sgf_normalized_result[13]), .CI(n5134), .CON(
n5123), .S(n5135) );
INVX2TS U6483 ( .A(n5137), .Y(n5139) );
NAND2X1TS U6484 ( .A(n5139), .B(n5138), .Y(n5140) );
XNOR2X1TS U6485 ( .A(n5141), .B(n5140), .Y(n5143) );
AOI22X1TS U6486 ( .A0(n2173), .A1(FPMULT_Add_result[14]), .B0(
FPMULT_Sgf_normalized_result[13]), .B1(n5168), .Y(n5144) );
OAI2BB1X1TS U6487 ( .A0N(n2311), .A1N(FPMULT_P_Sgf[37]), .B0(n5144), .Y(
n5145) );
AOI21X1TS U6488 ( .A0(n2308), .A1(FPMULT_Add_result[13]), .B0(n5145), .Y(
n5146) );
OAI2BB1X1TS U6489 ( .A0N(n2257), .A1N(FPMULT_P_Sgf[36]), .B0(n5146), .Y(
n1882) );
AHHCINX2TS U6490 ( .A(FPMULT_Sgf_normalized_result[12]), .CIN(n5147), .S(
n5148), .CO(n5134) );
INVX2TS U6491 ( .A(n5149), .Y(n5151) );
NAND2X1TS U6492 ( .A(n5151), .B(n5150), .Y(n5152) );
XNOR2X1TS U6493 ( .A(n5153), .B(n5152), .Y(n5154) );
BUFX3TS U6494 ( .A(n5363), .Y(n5279) );
AOI22X1TS U6495 ( .A0(n2174), .A1(FPMULT_Add_result[13]), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n5168), .Y(n5155) );
OAI2BB1X1TS U6496 ( .A0N(n2311), .A1N(FPMULT_P_Sgf[36]), .B0(n5155), .Y(
n5156) );
AOI21X1TS U6497 ( .A0(n3905), .A1(FPMULT_Add_result[12]), .B0(n5156), .Y(
n5157) );
OAI2BB1X1TS U6498 ( .A0N(n2256), .A1N(FPMULT_P_Sgf[35]), .B0(n5157), .Y(
n1881) );
AHHCONX2TS U6499 ( .A(FPMULT_Sgf_normalized_result[11]), .CI(n5158), .CON(
n5147), .S(n5159) );
OAI21X1TS U6500 ( .A0(n5180), .A1(n5176), .B0(n5177), .Y(n5166) );
NAND2X1TS U6501 ( .A(n5164), .B(n5163), .Y(n5165) );
XNOR2X1TS U6502 ( .A(n5166), .B(n5165), .Y(n5167) );
CLKMX2X2TS U6503 ( .A(FPMULT_P_Sgf[34]), .B(n5167), .S0(n5279), .Y(n1927) );
AOI22X1TS U6504 ( .A0(n2174), .A1(FPMULT_Add_result[12]), .B0(
FPMULT_Sgf_normalized_result[11]), .B1(n5168), .Y(n5169) );
OAI2BB1X1TS U6505 ( .A0N(n2309), .A1N(FPMULT_P_Sgf[35]), .B0(n5169), .Y(
n5170) );
AOI21X1TS U6506 ( .A0(n2308), .A1(FPMULT_Add_result[11]), .B0(n5170), .Y(
n5171) );
OAI2BB1X1TS U6507 ( .A0N(n2257), .A1N(FPMULT_P_Sgf[34]), .B0(n5171), .Y(
n1880) );
NAND2X1TS U6508 ( .A(n5199), .B(n5173), .Y(n5174) );
XOR2X1TS U6509 ( .A(n5174), .B(n5862), .Y(n5175) );
INVX2TS U6510 ( .A(n5176), .Y(n5178) );
NAND2X1TS U6511 ( .A(n5178), .B(n5177), .Y(n5179) );
XOR2X1TS U6512 ( .A(n5180), .B(n5179), .Y(n5181) );
BUFX3TS U6513 ( .A(n5182), .Y(n5302) );
AOI22X1TS U6514 ( .A0(n2173), .A1(FPMULT_Add_result[11]), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n5302), .Y(n5183) );
OAI2BB1X1TS U6515 ( .A0N(n2309), .A1N(FPMULT_P_Sgf[34]), .B0(n5183), .Y(
n5184) );
AOI21X1TS U6516 ( .A0(n5306), .A1(FPMULT_Add_result[10]), .B0(n5184), .Y(
n5185) );
OAI2BB1X1TS U6517 ( .A0N(n2256), .A1N(FPMULT_P_Sgf[33]), .B0(n5185), .Y(
n1879) );
NAND2X1TS U6518 ( .A(n5199), .B(FPMULT_Sgf_normalized_result[8]), .Y(n5186)
);
XOR2X1TS U6519 ( .A(n5186), .B(n5787), .Y(n5187) );
INVX2TS U6520 ( .A(n5188), .Y(n5202) );
INVX2TS U6521 ( .A(n5201), .Y(n5189) );
AOI21X1TS U6522 ( .A0(n5204), .A1(n5202), .B0(n5189), .Y(n5194) );
NAND2X1TS U6523 ( .A(n5192), .B(n5191), .Y(n5193) );
XOR2X1TS U6524 ( .A(n5194), .B(n5193), .Y(n5195) );
AOI22X1TS U6525 ( .A0(n5060), .A1(FPMULT_Add_result[10]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n5302), .Y(n5196) );
OAI2BB1X1TS U6526 ( .A0N(n2310), .A1N(FPMULT_P_Sgf[33]), .B0(n5196), .Y(
n5197) );
AOI21X1TS U6527 ( .A0(n5306), .A1(FPMULT_Add_result[9]), .B0(n5197), .Y(
n5198) );
OAI2BB1X1TS U6528 ( .A0N(n2257), .A1N(FPMULT_P_Sgf[32]), .B0(n5198), .Y(
n1878) );
XNOR2X1TS U6529 ( .A(n5199), .B(n5725), .Y(n5200) );
NAND2X1TS U6530 ( .A(n5202), .B(n5201), .Y(n5203) );
XNOR2X1TS U6531 ( .A(n5204), .B(n5203), .Y(n5205) );
AOI22X1TS U6532 ( .A0(n2174), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n5302), .Y(n5206) );
OAI2BB1X1TS U6533 ( .A0N(n2311), .A1N(FPMULT_P_Sgf[32]), .B0(n5206), .Y(
n5207) );
AOI21X1TS U6534 ( .A0(n5306), .A1(FPMULT_Add_result[8]), .B0(n5207), .Y(
n5208) );
OAI2BB1X1TS U6535 ( .A0N(n2256), .A1N(FPMULT_P_Sgf[31]), .B0(n5208), .Y(
n1877) );
OAI21X1TS U6536 ( .A0(n5255), .A1(n5788), .B0(n5210), .Y(n5231) );
NAND2X1TS U6537 ( .A(n5231), .B(FPMULT_Sgf_normalized_result[6]), .Y(n5211)
);
XOR2X1TS U6538 ( .A(n5211), .B(n5863), .Y(n5212) );
INVX4TS U6539 ( .A(n5213), .Y(n5312) );
OAI21X2TS U6540 ( .A0(n5312), .A1(n5215), .B0(n5214), .Y(n5245) );
INVX2TS U6541 ( .A(n5245), .Y(n5260) );
INVX2TS U6542 ( .A(n5216), .Y(n5219) );
INVX2TS U6543 ( .A(n5217), .Y(n5218) );
OAI21X2TS U6544 ( .A0(n5260), .A1(n5219), .B0(n5218), .Y(n5236) );
INVX2TS U6545 ( .A(n5220), .Y(n5234) );
INVX2TS U6546 ( .A(n5233), .Y(n5221) );
AOI21X1TS U6547 ( .A0(n5236), .A1(n5234), .B0(n5221), .Y(n5226) );
INVX2TS U6548 ( .A(n5222), .Y(n5224) );
NAND2X1TS U6549 ( .A(n5224), .B(n5223), .Y(n5225) );
XOR2X1TS U6550 ( .A(n5226), .B(n5225), .Y(n5227) );
AOI22X1TS U6551 ( .A0(n5060), .A1(FPMULT_Add_result[8]), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n5302), .Y(n5228) );
OAI2BB1X1TS U6552 ( .A0N(n2309), .A1N(FPMULT_P_Sgf[31]), .B0(n5228), .Y(
n5229) );
AOI21X1TS U6553 ( .A0(n5306), .A1(FPMULT_Add_result[7]), .B0(n5229), .Y(
n5230) );
OAI2BB1X1TS U6554 ( .A0N(n2257), .A1N(FPMULT_P_Sgf[30]), .B0(n5230), .Y(
n1876) );
XNOR2X1TS U6555 ( .A(n5231), .B(n5847), .Y(n5232) );
NAND2X1TS U6556 ( .A(n5234), .B(n5233), .Y(n5235) );
XNOR2X1TS U6557 ( .A(n5236), .B(n5235), .Y(n5237) );
AOI22X1TS U6558 ( .A0(n2174), .A1(FPMULT_Add_result[7]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n5302), .Y(n5238) );
OAI2BB1X1TS U6559 ( .A0N(n2310), .A1N(FPMULT_P_Sgf[30]), .B0(n5238), .Y(
n5239) );
AOI21X1TS U6560 ( .A0(n5306), .A1(FPMULT_Add_result[6]), .B0(n5239), .Y(
n5240) );
OAI2BB1X1TS U6561 ( .A0N(n2256), .A1N(FPMULT_P_Sgf[29]), .B0(n5240), .Y(
n1875) );
NAND2X1TS U6562 ( .A(n5255), .B(n5846), .Y(n5241) );
XNOR2X1TS U6563 ( .A(n5241), .B(n5788), .Y(n5242) );
INVX2TS U6564 ( .A(n5243), .Y(n5258) );
INVX2TS U6565 ( .A(n5257), .Y(n5244) );
AOI21X1TS U6566 ( .A0(n5245), .A1(n5258), .B0(n5244), .Y(n5250) );
INVX2TS U6567 ( .A(n5246), .Y(n5248) );
NAND2X1TS U6568 ( .A(n5248), .B(n5247), .Y(n5249) );
XOR2X1TS U6569 ( .A(n5250), .B(n5249), .Y(n5251) );
AOI22X1TS U6570 ( .A0(n2174), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n5302), .Y(n5252) );
OAI2BB1X1TS U6571 ( .A0N(n2311), .A1N(FPMULT_P_Sgf[29]), .B0(n5252), .Y(
n5253) );
AOI21X1TS U6572 ( .A0(n5306), .A1(FPMULT_Add_result[5]), .B0(n5253), .Y(
n5254) );
OAI2BB1X1TS U6573 ( .A0N(n2257), .A1N(FPMULT_P_Sgf[28]), .B0(n5254), .Y(
n1874) );
XOR2X1TS U6574 ( .A(n5255), .B(FPMULT_Sgf_normalized_result[4]), .Y(n5256)
);
NAND2X1TS U6575 ( .A(n5258), .B(n5257), .Y(n5259) );
XOR2X1TS U6576 ( .A(n5260), .B(n5259), .Y(n5261) );
AOI22X1TS U6577 ( .A0(n2174), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n5302), .Y(n5262) );
OAI2BB1X1TS U6578 ( .A0N(n2309), .A1N(FPMULT_P_Sgf[28]), .B0(n5262), .Y(
n5263) );
AOI21X1TS U6579 ( .A0(n5306), .A1(FPMULT_Add_result[4]), .B0(n5263), .Y(
n5264) );
OAI2BB1X1TS U6580 ( .A0N(n2256), .A1N(FPMULT_P_Sgf[27]), .B0(n5264), .Y(
n1873) );
XOR2X1TS U6581 ( .A(n5266), .B(n5783), .Y(n5267) );
INVX2TS U6582 ( .A(n5268), .Y(n5271) );
INVX2TS U6583 ( .A(n5269), .Y(n5270) );
OAI21X1TS U6584 ( .A0(n5312), .A1(n5271), .B0(n5270), .Y(n5289) );
INVX2TS U6585 ( .A(n5272), .Y(n5287) );
INVX2TS U6586 ( .A(n5286), .Y(n5273) );
AOI21X1TS U6587 ( .A0(n5289), .A1(n5287), .B0(n5273), .Y(n5278) );
NAND2X1TS U6588 ( .A(n5276), .B(n5275), .Y(n5277) );
XOR2X1TS U6589 ( .A(n5278), .B(n5277), .Y(n5280) );
AOI22X1TS U6590 ( .A0(n5060), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n5302), .Y(n5281) );
OAI2BB1X1TS U6591 ( .A0N(n2310), .A1N(FPMULT_P_Sgf[27]), .B0(n5281), .Y(
n5282) );
AOI21X1TS U6592 ( .A0(n5306), .A1(FPMULT_Add_result[3]), .B0(n5282), .Y(
n5283) );
OAI2BB1X1TS U6593 ( .A0N(n2257), .A1N(FPMULT_P_Sgf[26]), .B0(n5283), .Y(
n1872) );
XOR2X1TS U6594 ( .A(n5284), .B(FPMULT_Sgf_normalized_result[2]), .Y(n5285)
);
NAND2X1TS U6595 ( .A(n5287), .B(n5286), .Y(n5288) );
XNOR2X1TS U6596 ( .A(n5289), .B(n5288), .Y(n5290) );
AOI22X1TS U6597 ( .A0(n2173), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n5302), .Y(n5291) );
OAI2BB1X1TS U6598 ( .A0N(n2309), .A1N(FPMULT_P_Sgf[26]), .B0(n5291), .Y(
n5292) );
AOI21X1TS U6599 ( .A0(n5306), .A1(FPMULT_Add_result[2]), .B0(n5292), .Y(
n5293) );
OAI2BB1X1TS U6600 ( .A0N(n2255), .A1N(FPMULT_P_Sgf[25]), .B0(n5293), .Y(
n1871) );
XNOR2X1TS U6601 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n5295) );
INVX2TS U6602 ( .A(n5296), .Y(n5298) );
NAND2X1TS U6603 ( .A(n5298), .B(n5297), .Y(n5299) );
XNOR2X1TS U6604 ( .A(n5300), .B(n5299), .Y(n5301) );
AOI22X1TS U6605 ( .A0(n5060), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n5302), .Y(n5303) );
OAI2BB1X1TS U6606 ( .A0N(n2310), .A1N(FPMULT_P_Sgf[25]), .B0(n5303), .Y(
n5305) );
AOI21X1TS U6607 ( .A0(n2308), .A1(FPMULT_Add_result[1]), .B0(n5305), .Y(
n5307) );
OAI2BB1X1TS U6608 ( .A0N(n2256), .A1N(FPMULT_P_Sgf[24]), .B0(n5307), .Y(
n1870) );
INVX2TS U6609 ( .A(n5308), .Y(n5310) );
NAND2X1TS U6610 ( .A(n5310), .B(n5309), .Y(n5311) );
XOR2X1TS U6611 ( .A(n5312), .B(n5311), .Y(n5313) );
ADDHXLTS U6612 ( .A(FPMULT_Sgf_normalized_result[23]), .B(n5314), .CO(n5316),
.S(n5046) );
NOR2XLTS U6613 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[0]), .Y(n5318) );
AOI211X1TS U6614 ( .A0(n2272), .A1(n5909), .B0(n5319), .C0(n5318), .Y(n5320)
);
NOR2BX1TS U6615 ( .AN(n5321), .B(n5320), .Y(n2056) );
NAND2X1TS U6616 ( .A(n5470), .B(n5850), .Y(n2053) );
CLKMX2X2TS U6617 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
INVX2TS U6618 ( .A(n2272), .Y(n5325) );
CLKMX2X2TS U6619 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(n5326), .S0(
n5413), .Y(n1949) );
AND4X1TS U6620 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n5327) );
AND4X1TS U6621 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n5327), .Y(n5328) );
AO21X1TS U6622 ( .A0(underflow_flag_mult), .A1(n5470), .B0(n5329), .Y(n1950)
);
OR4X2TS U6623 ( .A(n5332), .B(n5331), .C(n5330), .D(n5342), .Y(n5333) );
NOR4X1TS U6624 ( .A(n5336), .B(n5335), .C(n5334), .D(n5333), .Y(n5340) );
NOR4BX1TS U6625 ( .AN(n5340), .B(n5339), .C(n5338), .D(n5337), .Y(n5341) );
INVX2TS U6626 ( .A(n5589), .Y(n5344) );
INVX2TS U6627 ( .A(n2312), .Y(n5343) );
OAI2BB2XLTS U6628 ( .B0(n5599), .B1(n5601), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[11]), .Y(n1544) );
OAI2BB2XLTS U6629 ( .B0(n5599), .B1(n5603), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[10]), .Y(n1540) );
OAI2BB2XLTS U6630 ( .B0(n5599), .B1(n5604), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[9]), .Y(n1536) );
OAI2BB2XLTS U6631 ( .B0(n5599), .B1(n5605), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[8]), .Y(n1532) );
OAI2BB2XLTS U6632 ( .B0(n5599), .B1(n5606), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[7]), .Y(n1528) );
OAI2BB2XLTS U6633 ( .B0(n5590), .B1(n5609), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[6]), .Y(n1524) );
OAI2BB2XLTS U6634 ( .B0(n5344), .B1(n5610), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[5]), .Y(n1520) );
OR4X2TS U6635 ( .A(n5478), .B(FPMULT_Exp_module_Overflow_flag_A), .C(
FPMULT_exp_oper_result[8]), .D(underflow_flag_mult), .Y(n5475) );
INVX2TS U6636 ( .A(n5477), .Y(n5483) );
OAI2BB2XLTS U6637 ( .B0(n5344), .B1(n5615), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[4]), .Y(n1516) );
OAI2BB2XLTS U6638 ( .B0(n5590), .B1(n5616), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[3]), .Y(n1512) );
OAI2BB2XLTS U6639 ( .B0(n5344), .B1(n5681), .A0N(n5343), .A1N(
FPADDSUB_Sgf_normalized_result[2]), .Y(n1508) );
INVX2TS U6640 ( .A(n5345), .Y(n5347) );
NAND2X1TS U6641 ( .A(n5347), .B(n5346), .Y(n5348) );
XOR2X1TS U6642 ( .A(n5348), .B(n5408), .Y(n5349) );
INVX2TS U6643 ( .A(n5350), .Y(n5376) );
INVX2TS U6644 ( .A(n5375), .Y(n5351) );
NAND2X1TS U6645 ( .A(n5351), .B(n5374), .Y(n5352) );
XOR2X1TS U6646 ( .A(n5376), .B(n5352), .Y(n5353) );
INVX2TS U6647 ( .A(n5354), .Y(n5359) );
NAND2X1TS U6648 ( .A(n2320), .B(n5355), .Y(n5356) );
XNOR2X1TS U6649 ( .A(n5359), .B(n5356), .Y(n5357) );
AOI21X1TS U6650 ( .A0(n5359), .A1(n2320), .B0(n5358), .Y(n5362) );
NAND2X1TS U6651 ( .A(n2321), .B(n5360), .Y(n5361) );
XOR2X1TS U6652 ( .A(n5362), .B(n5361), .Y(n5364) );
BUFX3TS U6653 ( .A(n5363), .Y(n5410) );
INVX2TS U6654 ( .A(n5365), .Y(n5389) );
INVX2TS U6655 ( .A(n5366), .Y(n5384) );
INVX2TS U6656 ( .A(n5383), .Y(n5367) );
AOI21X1TS U6657 ( .A0(n5389), .A1(n5384), .B0(n5367), .Y(n5372) );
INVX2TS U6658 ( .A(n5368), .Y(n5370) );
NAND2X1TS U6659 ( .A(n5370), .B(n5369), .Y(n5371) );
XOR2X1TS U6660 ( .A(n5372), .B(n5371), .Y(n5373) );
INVX2TS U6661 ( .A(n5377), .Y(n5379) );
NAND2X1TS U6662 ( .A(n5379), .B(n5378), .Y(n5380) );
XNOR2X1TS U6663 ( .A(n5381), .B(n5380), .Y(n5382) );
NAND2X1TS U6664 ( .A(n5384), .B(n5383), .Y(n5385) );
XNOR2X1TS U6665 ( .A(n5389), .B(n5385), .Y(n5386) );
AOI21X1TS U6666 ( .A0(n5389), .A1(n5388), .B0(n5387), .Y(n5395) );
INVX2TS U6667 ( .A(n5394), .Y(n5390) );
NAND2X1TS U6668 ( .A(n5390), .B(n5393), .Y(n5391) );
XOR2X1TS U6669 ( .A(n5395), .B(n5391), .Y(n5392) );
NAND2X1TS U6670 ( .A(n5398), .B(n5397), .Y(n5399) );
XNOR2X1TS U6671 ( .A(n5400), .B(n5399), .Y(n5401) );
NAND2X1TS U6672 ( .A(n2350), .B(n5403), .Y(n5405) );
XNOR2X1TS U6673 ( .A(n5405), .B(n5404), .Y(n5406) );
OR2X1TS U6674 ( .A(n5407), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(n5409) );
CLKAND2X2TS U6675 ( .A(n5409), .B(n5408), .Y(n5411) );
NOR4X1TS U6676 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n5420) );
NOR4X1TS U6677 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n5419) );
NOR4X1TS U6678 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n5417) );
NOR4X1TS U6679 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n5415) );
NOR4X1TS U6680 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n5414) );
AND4X1TS U6681 ( .A(n5417), .B(n5416), .C(n5415), .D(n5414), .Y(n5418) );
NOR4BX1TS U6682 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n5425) );
NOR4X1TS U6683 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n5424) );
NAND4XLTS U6684 ( .A(dataA[30]), .B(n2258), .C(dataA[28]), .D(dataA[26]),
.Y(n5422) );
NAND4XLTS U6685 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n5421) );
OR3X1TS U6686 ( .A(n6006), .B(n5422), .C(n5421), .Y(n5426) );
NOR3X1TS U6687 ( .A(dataB[25]), .B(dataB[31]), .C(n5426), .Y(n5423) );
NOR4X1TS U6688 ( .A(dataA[30]), .B(n2258), .C(dataA[28]), .D(dataA[26]), .Y(
n5429) );
NOR4X1TS U6689 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n5428) );
NOR4BX1TS U6690 ( .AN(operation_reg[1]), .B(dataA[31]), .C(operation_reg[0]),
.D(n6006), .Y(n5427) );
NOR2X1TS U6691 ( .A(operation_reg[1]), .B(n5426), .Y(n5434) );
NAND4XLTS U6692 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n5430) );
OAI31X1TS U6693 ( .A0(n5432), .A1(n5431), .A2(n5430), .B0(dataB[27]), .Y(
n5433) );
OAI2BB2XLTS U6694 ( .B0(n5436), .B1(n5435), .A0N(n5434), .A1N(
operation_reg[0]), .Y(NaN_reg) );
AOI222X1TS U6695 ( .A0(n5439), .A1(n2305), .B0(n5442), .B1(n2261), .C0(n5440), .C1(n2243), .Y(n5437) );
OAI22X1TS U6696 ( .A0(n5444), .A1(n5438), .B0(n5437), .B1(n5443), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U6697 ( .A0(n2304), .A1(n5440), .B0(n2261), .B1(n5439), .Y(n5447)
);
AOI22X1TS U6698 ( .A0(n5442), .A1(n2246), .B0(n2244), .B1(n5441), .Y(n5445)
);
AOI32X1TS U6699 ( .A0(n5447), .A1(n5446), .A2(n5445), .B0(n5444), .B1(n5443),
.Y(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
NOR2XLTS U6700 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n5448) );
AOI22X1TS U6701 ( .A0(operation[2]), .A1(n5448), .B0(n5841), .B1(n5449), .Y(
overflow_flag) );
AOI22X1TS U6702 ( .A0(operation[2]), .A1(n5849), .B0(n5759), .B1(n5449), .Y(
underflow_flag) );
NOR4X1TS U6703 ( .A(FPMULT_Op_MY[27]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[25]), .D(FPMULT_Op_MY[24]), .Y(n5454) );
NOR4X1TS U6704 ( .A(n2307), .B(n5450), .C(FPMULT_Op_MY[15]), .D(n2125), .Y(
n5453) );
NOR4X1TS U6705 ( .A(FPMULT_Op_MY[21]), .B(n2170), .C(FPMULT_Op_MY[14]), .D(
n2122), .Y(n5452) );
NAND4XLTS U6706 ( .A(n5454), .B(n5453), .C(n5452), .D(n5451), .Y(n5469) );
NAND4XLTS U6707 ( .A(n5457), .B(n2154), .C(n5456), .D(n5455), .Y(n5468) );
NOR4X1TS U6708 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[25]), .D(FPMULT_Op_MX[23]), .Y(n5461) );
NOR4X1TS U6709 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[18]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[14]), .Y(n5460) );
NOR4X1TS U6710 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[28]), .Y(n5458) );
NAND4XLTS U6711 ( .A(n5461), .B(n5460), .C(n5459), .D(n5458), .Y(n5467) );
NOR4X1TS U6712 ( .A(n2162), .B(n2130), .C(FPMULT_Op_MX[3]), .D(n2124), .Y(
n5465) );
NOR4X1TS U6713 ( .A(n2129), .B(n5462), .C(n2158), .D(n2268), .Y(n5464) );
NAND4XLTS U6714 ( .A(n5465), .B(n5464), .C(n2155), .D(n5463), .Y(n5466) );
OAI22X1TS U6715 ( .A0(n5469), .A1(n5468), .B0(n5467), .B1(n5466), .Y(n5471)
);
OA22X1TS U6716 ( .A0(n5481), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n5477), .Y(n1948) );
OA22X1TS U6717 ( .A0(n5481), .A1(mult_result[24]), .B0(
FPMULT_exp_oper_result[1]), .B1(n5475), .Y(n1947) );
OA22X1TS U6718 ( .A0(n5474), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n5475), .Y(n1946) );
OA22X1TS U6719 ( .A0(n5474), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n5475), .Y(n1945) );
OA22X1TS U6720 ( .A0(n5474), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n5475), .Y(n1944) );
OA22X1TS U6721 ( .A0(n5474), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n5475), .Y(n1943) );
OA22X1TS U6722 ( .A0(n5474), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n5475), .Y(n1942) );
OA22X1TS U6723 ( .A0(n5481), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n5475), .Y(n1941) );
INVX2TS U6724 ( .A(n5477), .Y(n5476) );
INVX2TS U6725 ( .A(n5477), .Y(n5479) );
INVX2TS U6726 ( .A(n5481), .Y(n5480) );
INVX2TS U6727 ( .A(n5481), .Y(n5482) );
AOI21X1TS U6728 ( .A0(n5804), .A1(n5728), .B0(n5484), .Y(n5485) );
INVX2TS U6729 ( .A(n5487), .Y(n5680) );
BUFX3TS U6730 ( .A(n5680), .Y(n5608) );
OAI2BB2XLTS U6731 ( .B0(n5608), .B1(n5834), .A0N(n5680), .A1N(
FPSENCOS_d_ff_Xn[31]), .Y(n1840) );
OAI222X1TS U6732 ( .A0(n5489), .A1(n5507), .B0(n5515), .B1(n5583), .C0(n5764), .C1(n5488), .Y(n1832) );
AOI22X1TS U6733 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5493), .B0(n5489),
.B1(n5768), .Y(n1831) );
AOI32X1TS U6734 ( .A0(n5492), .A1(n5508), .A2(n5491), .B0(n2183), .B1(n5768),
.Y(n5494) );
OAI22X1TS U6735 ( .A0(n5583), .A1(n5494), .B0(n5508), .B1(n5493), .Y(n1830)
);
INVX2TS U6736 ( .A(n5584), .Y(n5577) );
OAI2BB2XLTS U6737 ( .B0(n5583), .B1(n5690), .A0N(n5577), .A1N(region_flag[0]), .Y(n1828) );
OAI2BB2XLTS U6738 ( .B0(n5583), .B1(n5845), .A0N(n5577), .A1N(region_flag[1]), .Y(n1827) );
OAI21X1TS U6739 ( .A0(n5508), .A1(n5768), .B0(n5536), .Y(n5499) );
OAI21X1TS U6740 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n5499), .B0(n5671),
.Y(n5524) );
INVX2TS U6741 ( .A(n5524), .Y(n5497) );
AOI22X1TS U6742 ( .A0(n5497), .A1(n5496), .B0(n5532), .B1(n5495), .Y(n1825)
);
AOI32X1TS U6743 ( .A0(n5499), .A1(n5529), .A2(n5507), .B0(n5498), .B1(n5532),
.Y(n1824) );
INVX2TS U6744 ( .A(n5667), .Y(n5630) );
XOR2X1TS U6745 ( .A(n2183), .B(n5500), .Y(n5501) );
OAI2BB2XLTS U6746 ( .B0(n5630), .B1(n5889), .A0N(n5650), .A1N(n5501), .Y(
n1823) );
OAI222X1TS U6747 ( .A0(n5504), .A1(n5503), .B0(n5502), .B1(n5529), .C0(n2175), .C1(n5505), .Y(n1822) );
OAI2BB1X1TS U6748 ( .A0N(FPSENCOS_d_ff3_LUT_out[22]), .A1N(n5576), .B0(n5505), .Y(n1821) );
OAI2BB1X1TS U6749 ( .A0N(FPSENCOS_d_ff3_LUT_out[20]), .A1N(n2365), .B0(n5513), .Y(n1819) );
OAI2BB1X1TS U6750 ( .A0N(FPSENCOS_d_ff3_LUT_out[19]), .A1N(n5576), .B0(n5505), .Y(n1818) );
OAI2BB1X1TS U6751 ( .A0N(FPSENCOS_d_ff3_LUT_out[17]), .A1N(n2365), .B0(n5513), .Y(n1816) );
OAI2BB1X1TS U6752 ( .A0N(FPSENCOS_d_ff3_LUT_out[15]), .A1N(n5576), .B0(n5513), .Y(n1814) );
NOR2XLTS U6753 ( .A(FPSENCOS_cont_iter_out[3]), .B(n5768), .Y(n5509) );
AOI32X1TS U6754 ( .A0(n5509), .A1(n5529), .A2(n5508), .B0(n5512), .B1(n5529),
.Y(n5523) );
OAI2BB1X1TS U6755 ( .A0N(FPSENCOS_d_ff3_LUT_out[14]), .A1N(n5511), .B0(n5523), .Y(n1813) );
BUFX3TS U6756 ( .A(n5511), .Y(n5629) );
NAND2X1TS U6757 ( .A(n5671), .B(n5514), .Y(n5521) );
NAND2X1TS U6758 ( .A(n5521), .B(n5513), .Y(n5517) );
NOR2BX1TS U6759 ( .AN(n5515), .B(n5514), .Y(n5530) );
NOR3BX1TS U6760 ( .AN(n5530), .B(n5516), .C(n5532), .Y(n5534) );
OAI2BB2XLTS U6761 ( .B0(n5667), .B1(FPSENCOS_cont_iter_out[2]), .A0N(n5550),
.A1N(FPSENCOS_d_ff3_LUT_out[8]), .Y(n1807) );
OAI21X1TS U6762 ( .A0(n5764), .A1(n5520), .B0(n5519), .Y(n5525) );
AOI31XLTS U6763 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n2329), .B0(n5525), .Y(n5522) );
OAI221XLTS U6764 ( .A0(n5651), .A1(n2339), .B0(n5667), .B1(n5522), .C0(n5521), .Y(n1805) );
OAI2BB1X1TS U6765 ( .A0N(FPSENCOS_d_ff3_LUT_out[5]), .A1N(n5511), .B0(n5523),
.Y(n1804) );
OA22X1TS U6766 ( .A0(n5525), .A1(n5524), .B0(n5630), .B1(
FPSENCOS_d_ff3_LUT_out[4]), .Y(n1803) );
AOI32X1TS U6767 ( .A0(n5530), .A1(n5529), .A2(n5528), .B0(n5527), .B1(n5532),
.Y(n1800) );
AOI22X1TS U6768 ( .A0(n5534), .A1(n5533), .B0(n5532), .B1(n5531), .Y(n1799)
);
BUFX3TS U6769 ( .A(n5556), .Y(n5553) );
AOI32X1TS U6770 ( .A0(FPSENCOS_sel_mux_1_reg), .A1(n5657), .A2(n5886), .B0(
n5761), .B1(n5553), .Y(n1796) );
BUFX3TS U6771 ( .A(n4025), .Y(n5659) );
AOI22X1TS U6772 ( .A0(n5567), .A1(n5867), .B0(n5716), .B1(n5553), .Y(n1795)
);
AOI22X1TS U6773 ( .A0(n5567), .A1(n5868), .B0(n5758), .B1(n5553), .Y(n1794)
);
AOI22X1TS U6774 ( .A0(n5567), .A1(n5869), .B0(n5762), .B1(n5553), .Y(n1793)
);
AOI22X1TS U6775 ( .A0(n5567), .A1(n5870), .B0(n5763), .B1(n5553), .Y(n1792)
);
AOI22X1TS U6776 ( .A0(n5567), .A1(n5871), .B0(n5738), .B1(n5553), .Y(n1791)
);
CMPR32X2TS U6777 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5764), .C(n5538), .CO(n5540), .S(n3928) );
NOR2X1TS U6778 ( .A(FPSENCOS_d_ff2_X[27]), .B(n5540), .Y(n5541) );
AOI21X1TS U6779 ( .A0(n5540), .A1(FPSENCOS_d_ff2_X[27]), .B0(n5541), .Y(
n5539) );
NAND3BX1TS U6780 ( .AN(n5540), .B(n5716), .C(n5758), .Y(n5543) );
NOR2X1TS U6781 ( .A(FPSENCOS_d_ff2_X[29]), .B(n5543), .Y(n5545) );
AOI21X1TS U6782 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n5543), .B0(n5545), .Y(
n5544) );
XNOR2X1TS U6783 ( .A(n5546), .B(n5545), .Y(n5547) );
AOI22X1TS U6784 ( .A0(n5567), .A1(n5872), .B0(n5548), .B1(n5553), .Y(n1777)
);
AOI22X1TS U6785 ( .A0(n5572), .A1(n5873), .B0(n5549), .B1(n5553), .Y(n1775)
);
OAI2BB2XLTS U6786 ( .B0(n5667), .B1(n5551), .A0N(n5550), .A1N(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1772) );
AOI22X1TS U6787 ( .A0(n5567), .A1(n5874), .B0(n5552), .B1(n5553), .Y(n1771)
);
BUFX3TS U6788 ( .A(n5624), .Y(n5565) );
OAI2BB2XLTS U6789 ( .B0(n2365), .B1(n5552), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1770) );
AOI22X1TS U6790 ( .A0(n5572), .A1(n5875), .B0(n5554), .B1(n5553), .Y(n1769)
);
OAI2BB2XLTS U6791 ( .B0(n5576), .B1(n5554), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1768) );
OAI2BB2XLTS U6792 ( .B0(n5667), .B1(n5555), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1766) );
AOI22X1TS U6793 ( .A0(n5567), .A1(n5876), .B0(n5557), .B1(n5556), .Y(n1765)
);
OAI2BB2XLTS U6794 ( .B0(n5511), .B1(n5557), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1764) );
AOI22X1TS U6795 ( .A0(n4059), .A1(n5877), .B0(n5558), .B1(n2239), .Y(n1763)
);
OAI2BB2XLTS U6796 ( .B0(n2365), .B1(n5558), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1762) );
AOI22X1TS U6797 ( .A0(n4059), .A1(n5878), .B0(n5559), .B1(n2239), .Y(n1761)
);
OAI2BB2XLTS U6798 ( .B0(n5511), .B1(n5559), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[12]), .Y(n1760) );
OAI2BB2XLTS U6799 ( .B0(n2365), .B1(n5560), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1758) );
AOI22X1TS U6800 ( .A0(n5572), .A1(n5879), .B0(n5561), .B1(n2239), .Y(n1757)
);
OAI2BB2XLTS U6801 ( .B0(n5629), .B1(n5561), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[10]), .Y(n1756) );
OAI2BB2XLTS U6802 ( .B0(n2365), .B1(n5562), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[9]), .Y(n1754) );
OAI2BB2XLTS U6803 ( .B0(n5629), .B1(n5563), .A0N(n5574), .A1N(
FPSENCOS_d_ff3_sh_x_out[8]), .Y(n1752) );
AOI22X1TS U6804 ( .A0(n4059), .A1(n5880), .B0(n5564), .B1(n2239), .Y(n1751)
);
OAI2BB2XLTS U6805 ( .B0(n5629), .B1(n5564), .A0N(n5574), .A1N(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1750) );
AOI22X1TS U6806 ( .A0(n5567), .A1(n5881), .B0(n5566), .B1(n5658), .Y(n1749)
);
OAI2BB2XLTS U6807 ( .B0(n5629), .B1(n5566), .A0N(n5565), .A1N(
FPSENCOS_d_ff3_sh_x_out[6]), .Y(n1748) );
AOI22X1TS U6808 ( .A0(n5567), .A1(n5882), .B0(n5568), .B1(n5658), .Y(n1747)
);
OAI2BB2XLTS U6809 ( .B0(n5629), .B1(n5568), .A0N(n5574), .A1N(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1746) );
OAI2BB2XLTS U6810 ( .B0(n5629), .B1(n5569), .A0N(n5574), .A1N(
FPSENCOS_d_ff3_sh_x_out[4]), .Y(n1744) );
AOI22X1TS U6811 ( .A0(n5572), .A1(n5883), .B0(n5570), .B1(n2239), .Y(n1743)
);
OAI2BB2XLTS U6812 ( .B0(n5629), .B1(n5570), .A0N(n5574), .A1N(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1742) );
AOI22X1TS U6813 ( .A0(n4059), .A1(n5884), .B0(n5571), .B1(n2239), .Y(n1741)
);
OAI2BB2XLTS U6814 ( .B0(n5532), .B1(n5571), .A0N(n5574), .A1N(
FPSENCOS_d_ff3_sh_x_out[2]), .Y(n1740) );
AOI22X1TS U6815 ( .A0(n5572), .A1(n5885), .B0(n5573), .B1(n2239), .Y(n1739)
);
OAI2BB2XLTS U6816 ( .B0(n5667), .B1(n5573), .A0N(n5574), .A1N(
FPSENCOS_d_ff3_sh_x_out[1]), .Y(n1738) );
OAI2BB2XLTS U6817 ( .B0(n5576), .B1(n5575), .A0N(n5574), .A1N(
FPSENCOS_d_ff3_sh_x_out[0]), .Y(n1736) );
INVX2TS U6818 ( .A(n5584), .Y(n5581) );
BUFX3TS U6819 ( .A(n5579), .Y(n5580) );
INVX2TS U6820 ( .A(n5584), .Y(n5585) );
BUFX3TS U6821 ( .A(n5579), .Y(n5582) );
CLKBUFX2TS U6822 ( .A(n5592), .Y(n5588) );
BUFX3TS U6823 ( .A(n5588), .Y(n5596) );
INVX2TS U6824 ( .A(n5592), .Y(n5591) );
OAI22X1TS U6825 ( .A0(n5596), .A1(n5834), .B0(n5618), .B1(n5677), .Y(n1698)
);
INVX2TS U6826 ( .A(n5589), .Y(n5590) );
OA22X1TS U6827 ( .A0(n5597), .A1(result_add_subt[30]), .B0(
FPADDSUB_exp_oper_result[7]), .B1(n2313), .Y(n1628) );
OAI22X1TS U6828 ( .A0(n5596), .A1(n5757), .B0(n5595), .B1(n5888), .Y(n1626)
);
OAI2BB2XLTS U6829 ( .B0(n5608), .B1(n5757), .A0N(n5680), .A1N(
FPSENCOS_d_ff_Xn[30]), .Y(n1625) );
OA22X1TS U6830 ( .A0(n5344), .A1(result_add_subt[29]), .B0(
FPADDSUB_exp_oper_result[6]), .B1(n2314), .Y(n1624) );
BUFX3TS U6831 ( .A(n3930), .Y(n5611) );
OAI2BB2XLTS U6832 ( .B0(n5594), .B1(n5751), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[29]), .Y(n1623) );
OAI22X1TS U6833 ( .A0(n5596), .A1(n5751), .B0(n5613), .B1(n5660), .Y(n1622)
);
BUFX3TS U6834 ( .A(n5680), .Y(n5617) );
OAI22X1TS U6835 ( .A0(n5617), .A1(n5751), .B0(n2302), .B1(n5886), .Y(n1621)
);
OA22X1TS U6836 ( .A0(n5590), .A1(result_add_subt[28]), .B0(
FPADDSUB_exp_oper_result[5]), .B1(n2312), .Y(n1620) );
OAI2BB2XLTS U6837 ( .B0(n5593), .B1(n5752), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[28]), .Y(n1619) );
OAI22X1TS U6838 ( .A0(n5592), .A1(n5752), .B0(n5591), .B1(n5656), .Y(n1618)
);
OAI22X1TS U6839 ( .A0(n5617), .A1(n5752), .B0(n2301), .B1(n5867), .Y(n1617)
);
OA22X1TS U6840 ( .A0(n5597), .A1(result_add_subt[27]), .B0(
FPADDSUB_exp_oper_result[4]), .B1(n2313), .Y(n1616) );
OAI2BB2XLTS U6841 ( .B0(n5593), .B1(n5753), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[27]), .Y(n1615) );
OAI22X1TS U6842 ( .A0(n5592), .A1(n5753), .B0(n5595), .B1(n5887), .Y(n1614)
);
OAI22X1TS U6843 ( .A0(n5617), .A1(n5753), .B0(n2302), .B1(n5868), .Y(n1613)
);
OA22X1TS U6844 ( .A0(n5597), .A1(result_add_subt[26]), .B0(
FPADDSUB_exp_oper_result[3]), .B1(n2314), .Y(n1612) );
BUFX3TS U6845 ( .A(n3930), .Y(n5602) );
OAI2BB2XLTS U6846 ( .B0(n5593), .B1(n5754), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[26]), .Y(n1611) );
OAI22X1TS U6847 ( .A0(n5619), .A1(n5754), .B0(n5618), .B1(n5655), .Y(n1610)
);
OAI22X1TS U6848 ( .A0(n5617), .A1(n5754), .B0(n2301), .B1(n5869), .Y(n1609)
);
OA22X1TS U6849 ( .A0(n5590), .A1(result_add_subt[25]), .B0(
FPADDSUB_exp_oper_result[2]), .B1(n2312), .Y(n1608) );
OAI2BB2XLTS U6850 ( .B0(n5593), .B1(n5755), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[25]), .Y(n1607) );
OAI22X1TS U6851 ( .A0(n5588), .A1(n5755), .B0(n5591), .B1(n5654), .Y(n1606)
);
OAI22X1TS U6852 ( .A0(n5617), .A1(n5755), .B0(n2302), .B1(n5870), .Y(n1605)
);
OA22X1TS U6853 ( .A0(n5344), .A1(result_add_subt[24]), .B0(
FPADDSUB_exp_oper_result[1]), .B1(n2313), .Y(n1604) );
OAI2BB2XLTS U6854 ( .B0(n5593), .B1(n5756), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[24]), .Y(n1603) );
OAI22X1TS U6855 ( .A0(n5588), .A1(n5756), .B0(n5613), .B1(n5653), .Y(n1602)
);
OAI22X1TS U6856 ( .A0(n5617), .A1(n5756), .B0(n2301), .B1(n5871), .Y(n1601)
);
OA22X1TS U6857 ( .A0(n5590), .A1(result_add_subt[23]), .B0(
FPADDSUB_exp_oper_result[0]), .B1(n2314), .Y(n1600) );
OAI2BB2XLTS U6858 ( .B0(n5593), .B1(n5835), .A0N(n5594), .A1N(
FPSENCOS_d_ff_Zn[23]), .Y(n1599) );
OAI22X1TS U6859 ( .A0(n5588), .A1(n5835), .B0(n5591), .B1(n5652), .Y(n1598)
);
BUFX3TS U6860 ( .A(n5680), .Y(n5682) );
OAI2BB2XLTS U6861 ( .B0(n5682), .B1(n5835), .A0N(n5680), .A1N(
FPSENCOS_d_ff_Xn[23]), .Y(n1597) );
OAI22X1TS U6862 ( .A0(n2312), .A1(n5742), .B0(n5829), .B1(n5344), .Y(n1596)
);
OAI2BB2XLTS U6863 ( .B0(n5593), .B1(n5829), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[22]), .Y(n1595) );
OAI22X1TS U6864 ( .A0(n5588), .A1(n5829), .B0(n5595), .B1(n5649), .Y(n1594)
);
OAI2BB2XLTS U6865 ( .B0(n5682), .B1(n5829), .A0N(n5608), .A1N(
FPSENCOS_d_ff_Xn[22]), .Y(n1593) );
OAI22X1TS U6866 ( .A0(n2313), .A1(n5740), .B0(n5830), .B1(n5597), .Y(n1592)
);
OAI2BB2XLTS U6867 ( .B0(n5593), .B1(n5830), .A0N(n5594), .A1N(
FPSENCOS_d_ff_Zn[21]), .Y(n1591) );
BUFX3TS U6868 ( .A(n5592), .Y(n5614) );
OAI22X1TS U6869 ( .A0(n5614), .A1(n5830), .B0(n5613), .B1(n5648), .Y(n1590)
);
OAI2BB2XLTS U6870 ( .B0(n5682), .B1(n5830), .A0N(n5608), .A1N(
FPSENCOS_d_ff_Xn[21]), .Y(n1589) );
OAI22X1TS U6871 ( .A0(n2314), .A1(n5821), .B0(n5743), .B1(n5597), .Y(n1588)
);
OAI2BB2XLTS U6872 ( .B0(n5598), .B1(n5743), .A0N(n5594), .A1N(
FPSENCOS_d_ff_Zn[20]), .Y(n1587) );
OAI22X1TS U6873 ( .A0(n5614), .A1(n5743), .B0(n5591), .B1(n5646), .Y(n1586)
);
BUFX3TS U6874 ( .A(n5680), .Y(n5607) );
OAI22X1TS U6875 ( .A0(n5607), .A1(n5743), .B0(n2302), .B1(n5872), .Y(n1585)
);
OAI22X1TS U6876 ( .A0(n2312), .A1(n5822), .B0(n5744), .B1(n5590), .Y(n1584)
);
OAI2BB2XLTS U6877 ( .B0(n5598), .B1(n5744), .A0N(n5594), .A1N(
FPSENCOS_d_ff_Zn[19]), .Y(n1583) );
OAI22X1TS U6878 ( .A0(n5614), .A1(n5744), .B0(n5595), .B1(n5645), .Y(n1582)
);
OAI22X1TS U6879 ( .A0(n5607), .A1(n5744), .B0(n2301), .B1(n5873), .Y(n1581)
);
OAI22X1TS U6880 ( .A0(n2313), .A1(n5737), .B0(n5831), .B1(n5344), .Y(n1580)
);
OAI2BB2XLTS U6881 ( .B0(n5598), .B1(n5831), .A0N(n5594), .A1N(
FPSENCOS_d_ff_Zn[18]), .Y(n1579) );
OAI22X1TS U6882 ( .A0(n5596), .A1(n5831), .B0(n5618), .B1(n5644), .Y(n1578)
);
OAI2BB2XLTS U6883 ( .B0(n5682), .B1(n5831), .A0N(n5608), .A1N(
FPSENCOS_d_ff_Xn[18]), .Y(n1577) );
OAI22X1TS U6884 ( .A0(n2314), .A1(n5812), .B0(n5745), .B1(n5344), .Y(n1576)
);
OAI2BB2XLTS U6885 ( .B0(n5598), .B1(n5745), .A0N(n5594), .A1N(
FPSENCOS_d_ff_Zn[17]), .Y(n1575) );
OAI22X1TS U6886 ( .A0(n5596), .A1(n5745), .B0(n5613), .B1(n5642), .Y(n1574)
);
OAI22X1TS U6887 ( .A0(n5607), .A1(n5745), .B0(n2302), .B1(n5874), .Y(n1573)
);
OAI22X1TS U6888 ( .A0(n2312), .A1(n5813), .B0(n5746), .B1(n5590), .Y(n1572)
);
OAI2BB2XLTS U6889 ( .B0(n5593), .B1(n5746), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[16]), .Y(n1571) );
OAI22X1TS U6890 ( .A0(n5596), .A1(n5746), .B0(n5591), .B1(n5641), .Y(n1570)
);
OAI22X1TS U6891 ( .A0(n5607), .A1(n5746), .B0(n2301), .B1(n5875), .Y(n1569)
);
OAI22X1TS U6892 ( .A0(n5726), .A1(n2312), .B0(n5832), .B1(n5597), .Y(n1568)
);
OAI2BB2XLTS U6893 ( .B0(n5598), .B1(n5832), .A0N(n5594), .A1N(
FPSENCOS_d_ff_Zn[15]), .Y(n1567) );
OAI22X1TS U6894 ( .A0(n5596), .A1(n5832), .B0(n5595), .B1(n5640), .Y(n1566)
);
OAI2BB2XLTS U6895 ( .B0(n5682), .B1(n5832), .A0N(n5608), .A1N(
FPSENCOS_d_ff_Xn[15]), .Y(n1565) );
OAI22X1TS U6896 ( .A0(n5789), .A1(n2313), .B0(n5747), .B1(n5597), .Y(n1564)
);
OAI2BB2XLTS U6897 ( .B0(n5598), .B1(n5747), .A0N(n5594), .A1N(
FPSENCOS_d_ff_Zn[14]), .Y(n1563) );
OAI22X1TS U6898 ( .A0(n5596), .A1(n5747), .B0(n5618), .B1(n5639), .Y(n1562)
);
OAI22X1TS U6899 ( .A0(n5617), .A1(n5747), .B0(n2302), .B1(n5876), .Y(n1561)
);
OAI22X1TS U6900 ( .A0(n5790), .A1(n2314), .B0(n5748), .B1(n5344), .Y(n1560)
);
OAI2BB2XLTS U6901 ( .B0(n5598), .B1(n5748), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[13]), .Y(n1559) );
OAI22X1TS U6902 ( .A0(n5596), .A1(n5748), .B0(n5613), .B1(n5638), .Y(n1558)
);
OAI22X1TS U6903 ( .A0(n5607), .A1(n5748), .B0(n2301), .B1(n5877), .Y(n1557)
);
OAI22X1TS U6904 ( .A0(n5772), .A1(n2312), .B0(n5749), .B1(n5590), .Y(n1556)
);
OAI2BB2XLTS U6905 ( .B0(n5598), .B1(n5749), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[12]), .Y(n1555) );
OAI22X1TS U6906 ( .A0(n5596), .A1(n5749), .B0(n5591), .B1(n5637), .Y(n1554)
);
OAI22X1TS U6907 ( .A0(n5607), .A1(n5749), .B0(n2302), .B1(n5878), .Y(n1553)
);
OAI22X1TS U6908 ( .A0(n5727), .A1(n2313), .B0(n5833), .B1(n5597), .Y(n1552)
);
OAI2BB2XLTS U6909 ( .B0(n5598), .B1(n5833), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[11]), .Y(n1551) );
CLKBUFX2TS U6910 ( .A(n5592), .Y(n5619) );
INVX2TS U6911 ( .A(n5592), .Y(n5613) );
OAI22X1TS U6912 ( .A0(n5619), .A1(n5833), .B0(n5618), .B1(n5636), .Y(n1550)
);
OAI2BB2XLTS U6913 ( .B0(n5682), .B1(n5833), .A0N(n5608), .A1N(
FPSENCOS_d_ff_Xn[11]), .Y(n1549) );
OAI22X1TS U6914 ( .A0(n5774), .A1(n2314), .B0(n5750), .B1(n5597), .Y(n1548)
);
OAI2BB2XLTS U6915 ( .B0(n5612), .B1(n5750), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[10]), .Y(n1547) );
OAI22X1TS U6916 ( .A0(n5619), .A1(n5750), .B0(n5613), .B1(n5635), .Y(n1546)
);
OAI22X1TS U6917 ( .A0(n5607), .A1(n5750), .B0(n2301), .B1(n5879), .Y(n1545)
);
OAI2BB2XLTS U6918 ( .B0(n5612), .B1(n5601), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[9]), .Y(n1543) );
OAI22X1TS U6919 ( .A0(n5619), .A1(n5601), .B0(n5591), .B1(n5633), .Y(n1542)
);
OAI2BB2XLTS U6920 ( .B0(n5682), .B1(n5601), .A0N(n5608), .A1N(
FPSENCOS_d_ff_Xn[9]), .Y(n1541) );
OAI2BB2XLTS U6921 ( .B0(n5612), .B1(n5603), .A0N(n5602), .A1N(
FPSENCOS_d_ff_Zn[8]), .Y(n1539) );
OAI22X1TS U6922 ( .A0(n5614), .A1(n5603), .B0(n5595), .B1(n5632), .Y(n1538)
);
OAI2BB2XLTS U6923 ( .B0(n5682), .B1(n5603), .A0N(n5608), .A1N(
FPSENCOS_d_ff_Xn[8]), .Y(n1537) );
OAI2BB2XLTS U6924 ( .B0(n5612), .B1(n5604), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[7]), .Y(n1535) );
OAI22X1TS U6925 ( .A0(n5614), .A1(n5604), .B0(n5618), .B1(n5631), .Y(n1534)
);
OAI22X1TS U6926 ( .A0(n5607), .A1(n5604), .B0(n2302), .B1(n5880), .Y(n1533)
);
OAI2BB2XLTS U6927 ( .B0(n5612), .B1(n5605), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[6]), .Y(n1531) );
OAI22X1TS U6928 ( .A0(n5614), .A1(n5605), .B0(n5613), .B1(n5628), .Y(n1530)
);
OAI22X1TS U6929 ( .A0(n5607), .A1(n5605), .B0(n2301), .B1(n5881), .Y(n1529)
);
OAI2BB2XLTS U6930 ( .B0(n5612), .B1(n5606), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[5]), .Y(n1527) );
OAI22X1TS U6931 ( .A0(n5614), .A1(n5606), .B0(n5591), .B1(n5627), .Y(n1526)
);
OAI22X1TS U6932 ( .A0(n5607), .A1(n5606), .B0(n2302), .B1(n5882), .Y(n1525)
);
OAI2BB2XLTS U6933 ( .B0(n5612), .B1(n5609), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[4]), .Y(n1523) );
OAI22X1TS U6934 ( .A0(n5614), .A1(n5609), .B0(n5595), .B1(n5625), .Y(n1522)
);
OAI2BB2XLTS U6935 ( .B0(n5682), .B1(n5609), .A0N(n5608), .A1N(
FPSENCOS_d_ff_Xn[4]), .Y(n1521) );
OAI2BB2XLTS U6936 ( .B0(n5612), .B1(n5610), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[3]), .Y(n1519) );
OAI22X1TS U6937 ( .A0(n5614), .A1(n5610), .B0(n5618), .B1(n5623), .Y(n1518)
);
OAI22X1TS U6938 ( .A0(n5617), .A1(n5610), .B0(n2301), .B1(n5883), .Y(n1517)
);
OAI2BB2XLTS U6939 ( .B0(n5612), .B1(n5615), .A0N(n5611), .A1N(
FPSENCOS_d_ff_Zn[2]), .Y(n1515) );
OAI22X1TS U6940 ( .A0(n5614), .A1(n5615), .B0(n5613), .B1(n5622), .Y(n1514)
);
OAI22X1TS U6941 ( .A0(n5617), .A1(n5615), .B0(n2302), .B1(n5884), .Y(n1513)
);
INVX2TS U6942 ( .A(n5592), .Y(n5618) );
OAI22X1TS U6943 ( .A0(n5619), .A1(n5616), .B0(n5595), .B1(n5621), .Y(n1510)
);
OAI22X1TS U6944 ( .A0(n5617), .A1(n5616), .B0(n2301), .B1(n5885), .Y(n1509)
);
OAI22X1TS U6945 ( .A0(n5619), .A1(n5681), .B0(n5618), .B1(n5620), .Y(n1473)
);
OAI2BB2XLTS U6946 ( .B0(n5620), .B1(n5659), .A0N(FPSENCOS_d_ff2_Y[0]), .A1N(
n5675), .Y(n1472) );
CLKBUFX2TS U6947 ( .A(n5634), .Y(n5626) );
OAI2BB2XLTS U6948 ( .B0(n5621), .B1(n5626), .A0N(FPSENCOS_d_ff2_Y[1]), .A1N(
n5675), .Y(n1470) );
OAI2BB2XLTS U6949 ( .B0(n5622), .B1(n5626), .A0N(FPSENCOS_d_ff2_Y[2]), .A1N(
n5675), .Y(n1468) );
OAI2BB2XLTS U6950 ( .B0(n5630), .B1(n5893), .A0N(n5650), .A1N(
FPSENCOS_d_ff2_Y[2]), .Y(n1467) );
OAI2BB2XLTS U6951 ( .B0(n5623), .B1(n5626), .A0N(FPSENCOS_d_ff2_Y[3]), .A1N(
n5675), .Y(n1466) );
INVX2TS U6952 ( .A(n5667), .Y(n5643) );
INVX2TS U6953 ( .A(n5624), .Y(n5647) );
OAI2BB2XLTS U6954 ( .B0(n5643), .B1(n5891), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[3]), .Y(n1465) );
OAI2BB2XLTS U6955 ( .B0(n5625), .B1(n5626), .A0N(FPSENCOS_d_ff2_Y[4]), .A1N(
n5675), .Y(n1464) );
OAI2BB2XLTS U6956 ( .B0(n5643), .B1(n5901), .A0N(n5674), .A1N(
FPSENCOS_d_ff2_Y[4]), .Y(n1463) );
OAI2BB2XLTS U6957 ( .B0(n5627), .B1(n5626), .A0N(FPSENCOS_d_ff2_Y[5]), .A1N(
n5675), .Y(n1462) );
OAI2BB2XLTS U6958 ( .B0(n5643), .B1(n5899), .A0N(n5650), .A1N(
FPSENCOS_d_ff2_Y[5]), .Y(n1461) );
OAI2BB2XLTS U6959 ( .B0(n5628), .B1(n5659), .A0N(FPSENCOS_d_ff2_Y[6]), .A1N(
n5675), .Y(n1460) );
OAI2BB2XLTS U6960 ( .B0(n5631), .B1(n5634), .A0N(FPSENCOS_d_ff2_Y[7]), .A1N(
n5658), .Y(n1458) );
OAI2BB2XLTS U6961 ( .B0(n5643), .B1(n5905), .A0N(n5674), .A1N(
FPSENCOS_d_ff2_Y[7]), .Y(n1457) );
OAI2BB2XLTS U6962 ( .B0(n5632), .B1(n5634), .A0N(FPSENCOS_d_ff2_Y[8]), .A1N(
n4024), .Y(n1456) );
OAI2BB2XLTS U6963 ( .B0(n5643), .B1(n5896), .A0N(n5674), .A1N(
FPSENCOS_d_ff2_Y[8]), .Y(n1455) );
OAI2BB2XLTS U6964 ( .B0(n5633), .B1(n5634), .A0N(FPSENCOS_d_ff2_Y[9]), .A1N(
n4024), .Y(n1454) );
OAI2BB2XLTS U6965 ( .B0(n5643), .B1(n5908), .A0N(n5674), .A1N(
FPSENCOS_d_ff2_Y[9]), .Y(n1453) );
OAI2BB2XLTS U6966 ( .B0(n5635), .B1(n5634), .A0N(FPSENCOS_d_ff2_Y[10]),
.A1N(n5556), .Y(n1452) );
OAI2BB2XLTS U6967 ( .B0(n5643), .B1(n5903), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[10]), .Y(n1451) );
OAI2BB2XLTS U6968 ( .B0(n5636), .B1(n4025), .A0N(FPSENCOS_d_ff2_Y[11]),
.A1N(n5556), .Y(n1450) );
OAI2BB2XLTS U6969 ( .B0(n5643), .B1(n5906), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[11]), .Y(n1449) );
OAI2BB2XLTS U6970 ( .B0(n5637), .B1(n5634), .A0N(FPSENCOS_d_ff2_Y[12]),
.A1N(n4024), .Y(n1448) );
OAI2BB2XLTS U6971 ( .B0(n5651), .B1(n5907), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[12]), .Y(n1447) );
OAI2BB2XLTS U6972 ( .B0(n5638), .B1(n5659), .A0N(FPSENCOS_d_ff2_Y[13]),
.A1N(n5556), .Y(n1446) );
OAI2BB2XLTS U6973 ( .B0(n5651), .B1(n5898), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[13]), .Y(n1445) );
BUFX3TS U6974 ( .A(n5634), .Y(n5676) );
OAI2BB2XLTS U6975 ( .B0(n5639), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[14]),
.A1N(n4024), .Y(n1444) );
OAI2BB2XLTS U6976 ( .B0(n5643), .B1(n5904), .A0N(n5650), .A1N(
FPSENCOS_d_ff2_Y[14]), .Y(n1443) );
OAI2BB2XLTS U6977 ( .B0(n5640), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[15]),
.A1N(n5556), .Y(n1442) );
OAI2BB2XLTS U6978 ( .B0(n5651), .B1(n5895), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[15]), .Y(n1441) );
OAI2BB2XLTS U6979 ( .B0(n5641), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[16]),
.A1N(n4024), .Y(n1440) );
OAI2BB2XLTS U6980 ( .B0(n5651), .B1(n5902), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[16]), .Y(n1439) );
BUFX3TS U6981 ( .A(n5658), .Y(n5661) );
OAI2BB2XLTS U6982 ( .B0(n5642), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[17]),
.A1N(n5661), .Y(n1438) );
OAI2BB2XLTS U6983 ( .B0(n5643), .B1(n5900), .A0N(n5650), .A1N(
FPSENCOS_d_ff2_Y[17]), .Y(n1437) );
OAI2BB2XLTS U6984 ( .B0(n5644), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[18]),
.A1N(n5661), .Y(n1436) );
OAI2BB2XLTS U6985 ( .B0(n5651), .B1(n5894), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[18]), .Y(n1435) );
OAI2BB2XLTS U6986 ( .B0(n5645), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[19]),
.A1N(n5661), .Y(n1434) );
OAI2BB2XLTS U6987 ( .B0(n5651), .B1(n5892), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[19]), .Y(n1433) );
OAI2BB2XLTS U6988 ( .B0(n5646), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[20]),
.A1N(n5661), .Y(n1432) );
OAI2BB2XLTS U6989 ( .B0(n5651), .B1(n5897), .A0N(n5647), .A1N(
FPSENCOS_d_ff2_Y[20]), .Y(n1431) );
OAI2BB2XLTS U6990 ( .B0(n5648), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[21]),
.A1N(n5661), .Y(n1430) );
OAI2BB2XLTS U6991 ( .B0(n5649), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[22]),
.A1N(n5661), .Y(n1428) );
OAI2BB2XLTS U6992 ( .B0(n5651), .B1(n5890), .A0N(n5650), .A1N(
FPSENCOS_d_ff2_Y[22]), .Y(n1427) );
OAI22X1TS U6993 ( .A0(n5657), .A1(n5866), .B0(n5652), .B1(n5659), .Y(n1426)
);
OAI22X1TS U6994 ( .A0(n2240), .A1(n5802), .B0(n5653), .B1(n5659), .Y(n1425)
);
OAI2BB2XLTS U6995 ( .B0(n5654), .B1(n5659), .A0N(FPSENCOS_d_ff2_Y[25]),
.A1N(n5661), .Y(n1424) );
OAI2BB2XLTS U6996 ( .B0(n5655), .B1(n5659), .A0N(FPSENCOS_d_ff2_Y[26]),
.A1N(n5661), .Y(n1423) );
OAI22X1TS U6997 ( .A0(n2240), .A1(n5853), .B0(n5656), .B1(n5659), .Y(n1421)
);
OAI2BB2XLTS U6998 ( .B0(n5660), .B1(n5659), .A0N(n5658), .A1N(
FPSENCOS_d_ff2_Y[29]), .Y(n1420) );
NOR2X1TS U6999 ( .A(FPSENCOS_d_ff2_Y[27]), .B(n5665), .Y(n5666) );
AOI21X1TS U7000 ( .A0(n5665), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n5666), .Y(
n5664) );
OR3X1TS U7001 ( .A(n5665), .B(FPSENCOS_d_ff2_Y[28]), .C(FPSENCOS_d_ff2_Y[27]), .Y(n5669) );
NOR2X1TS U7002 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n5669), .Y(n5672) );
AOI21X1TS U7003 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n5669), .B0(n5672), .Y(
n5670) );
XOR2X1TS U7004 ( .A(FPSENCOS_d_ff2_Y[30]), .B(n5672), .Y(n5673) );
OAI2BB2XLTS U7005 ( .B0(n5677), .B1(n5676), .A0N(FPSENCOS_d_ff2_Y[31]),
.A1N(n5675), .Y(n1410) );
OAI2BB2XLTS U7006 ( .B0(n5682), .B1(n5681), .A0N(n5680), .A1N(
FPSENCOS_d_ff_Xn[0]), .Y(n1408) );
OR3X2TS U7007 ( .A(FPSENCOS_cordic_FSM_state_reg[1]), .B(
FPSENCOS_cordic_FSM_state_reg[0]), .C(n5683), .Y(n5687) );
BUFX3TS U7008 ( .A(n5692), .Y(n5688) );
INVX2TS U7009 ( .A(n5688), .Y(n5684) );
BUFX3TS U7010 ( .A(n5687), .Y(n5685) );
INVX2TS U7011 ( .A(n5692), .Y(n5686) );
INVX2TS U7012 ( .A(n5692), .Y(n5689) );
INVX2TS U7013 ( .A(n5692), .Y(n5694) );
XOR2X1TS U7014 ( .A(FPSENCOS_data_output2_31_), .B(n5691), .Y(n5693) );
AOI22X1TS U7015 ( .A0(FPSENCOS_d_ff3_sh_y_out[30]), .A1(n2206), .B0(n5703),
.B1(Data_2[30]), .Y(n5696) );
AOI22X1TS U7016 ( .A0(FPADDSUB_intDY[30]), .A1(n5704), .B0(
FPSENCOS_d_ff3_sh_x_out[30]), .B1(n5705), .Y(n5695) );
NAND2X1TS U7017 ( .A(n5696), .B(n5695), .Y(n1338) );
AOI22X1TS U7018 ( .A0(FPADDSUB_intDY[29]), .A1(n5704), .B0(n5697), .B1(
Data_2[29]), .Y(n5700) );
AOI22X1TS U7019 ( .A0(n2206), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n5705),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n5699) );
NAND2X1TS U7020 ( .A(n4144), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n5707) );
AOI22X1TS U7021 ( .A0(FPADDSUB_intDY[28]), .A1(n5704), .B0(n5703), .B1(
Data_2[28]), .Y(n5702) );
AOI22X1TS U7022 ( .A0(n5706), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n5705),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n5701) );
AOI22X1TS U7023 ( .A0(FPADDSUB_intDY[27]), .A1(n5704), .B0(n5703), .B1(
Data_2[27]), .Y(n5709) );
AOI22X1TS U7024 ( .A0(n5706), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n5705),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n5708) );
CMPR42X1TS U7025 ( .A(mult_x_159_n168), .B(mult_x_159_n280), .C(
mult_x_159_n288), .D(mult_x_159_n300), .ICI(mult_x_159_n165), .S(
mult_x_159_n164), .ICO(mult_x_159_n162), .CO(mult_x_159_n163) );
CMPR42X1TS U7026 ( .A(mult_x_159_n169), .B(mult_x_159_n301), .C(
mult_x_159_n289), .D(mult_x_159_n173), .ICI(mult_x_159_n170), .S(
mult_x_159_n167), .ICO(mult_x_159_n165), .CO(mult_x_159_n166) );
CMPR42X1TS U7027 ( .A(mult_x_159_n290), .B(mult_x_159_n314), .C(
mult_x_159_n174), .D(mult_x_159_n178), .ICI(mult_x_159_n175), .S(
mult_x_159_n172), .ICO(mult_x_159_n170), .CO(mult_x_159_n171) );
CMPR42X1TS U7028 ( .A(n2307), .B(FPMULT_Op_MY[21]), .C(mult_x_121_n280), .D(
mult_x_121_n292), .ICI(mult_x_121_n163), .S(mult_x_121_n162), .ICO(
mult_x_121_n160), .CO(mult_x_121_n161) );
CMPR42X1TS U7029 ( .A(n2360), .B(mult_x_121_n281), .C(mult_x_121_n293), .D(
mult_x_121_n171), .ICI(mult_x_121_n168), .S(mult_x_121_n165), .ICO(
mult_x_121_n163), .CO(mult_x_121_n164) );
CMPR42X1TS U7030 ( .A(mult_x_121_n294), .B(mult_x_121_n306), .C(
mult_x_121_n172), .D(mult_x_121_n176), .ICI(mult_x_121_n173), .S(
mult_x_121_n170), .ICO(mult_x_121_n168), .CO(mult_x_121_n169) );
CMPR42X1TS U7031 ( .A(DP_OP_498J12_123_5135_n407), .B(
DP_OP_498J12_123_5135_n263), .C(DP_OP_498J12_123_5135_n384), .D(
DP_OP_498J12_123_5135_n394), .ICI(DP_OP_498J12_123_5135_n260), .S(
DP_OP_498J12_123_5135_n259), .ICO(DP_OP_498J12_123_5135_n257), .CO(
DP_OP_498J12_123_5135_n258) );
initial $sdf_annotate("FPU_Interface_syn.sdf");
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2011 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_system_1.v
//
// *Module Description:
// openMSP430 System 0.
// This core is dedicated to communication and
// display (i.e. UART, LEDs and 7-segment modport)
// It can also read the switches value.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
`include "openmsp430/openMSP430_defines.v"
module omsp_system_0 (
// Clock & Reset
dco_clk, // Fast oscillator (fast clock)
reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
// Serial Debug Interface (I2C)
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
// Data Memory
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
dmem_dout, // Data Memory data output
// Program Memory
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
pmem_dout, // Program Memory data output
// UART
uart_rxd, // UART Data Receive (RXD)
uart_txd, // UART Data Transmit (TXD)
// Switches & LEDs
switch, // Input switches
led // LEDs
);
// Clock & Reset
input dco_clk; // Fast oscillator (fast clock)
input reset_n; // Reset Pin (low active, asynchronous and non-glitchy)
// Serial Debug Interface (I2C)
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
// Data Memory
input [15:0] dmem_dout; // Data Memory data output
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
// Program Memory
input [15:0] pmem_dout; // Program Memory data output
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
// UART
input uart_rxd; // UART Data Receive (RXD)
output uart_txd; // UART Data Transmit (TXD)
// Switches & LEDs
input [3:0] switch; // Input switches
output [1:0] led; // LEDs
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
// Clock & Reset
wire mclk;
wire aclk_en;
wire smclk_en;
wire puc_rst;
// Debug interface
wire dbg_freeze;
// Data memory
wire [`DMEM_MSB:0] dmem_addr;
wire dmem_cen;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [15:0] dmem_dout;
// Program memory
wire [`PMEM_MSB:0] pmem_addr;
wire pmem_cen;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [15:0] pmem_dout;
// Peripheral bus
wire [13:0] per_addr;
wire [15:0] per_din;
wire [1:0] per_we;
wire per_en;
wire [15:0] per_dout;
// Interrupts
wire [13:0] irq_acc;
wire [13:0] irq_bus;
wire nmi;
// GPIO
wire [7:0] p1_din;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_din;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [15:0] per_dout_gpio;
// Timer A
wire [15:0] per_dout_tA;
// Hardware UART
wire [15:0] per_dout_uart;
//=============================================================================
// 2) OPENMSP430 CORE
//=============================================================================
openMSP430 #(.INST_NR (0),
.TOTAL_NR(1)) openMSP430_0 (
// OUTPUTs
.aclk (), // ASIC ONLY: ACLK
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_uart_txd (), // Debug interface: UART TXD
.dco_enable (), // ASIC ONLY: Fast oscillator enable
.dco_wkup (), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.lfxt_enable (), // ASIC ONLY: Low frequency oscillator enable
.lfxt_wkup (), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
.mclk (mclk), // Main system clock
.dma_dout (), // Direct Memory Access data output
.dma_ready (), // Direct Memory Access is complete
.dma_resp (), // Direct Memory Access response (0:Okay / 1:Error)
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc_rst (puc_rst), // Main system reset
.smclk (), // ASIC ONLY: SMCLK
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
// INPUTs
.cpu_en (1'b1), // Enable CPU code execution (asynchronous and non-glitchy)
.dbg_en (1'b1), // Debug interface enable (asynchronous and non-glitchy)
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_uart_rxd (1'b1), // Debug interface: UART RXD (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_bus), // Maskable interrupts
.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
.dma_addr (15'h0000), // Direct Memory Access address
.dma_din (16'h0000), // Direct Memory Access data input
.dma_en (1'b0), // Direct Memory Access enable (high active)
.dma_priority (1'b0), // Direct Memory Access priority (0:low / 1:high)
.dma_we (2'b00), // Direct Memory Access write byte enable (high active)
.dma_wkup (1'b0), // ASIC ONLY: DMA Sub-System Wake-up (asynchronous and non-glitchy)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n), // Reset Pin (low active, asynchronous and non-glitchy)
.scan_enable (1'b0), // ASIC ONLY: Scan enable (active during scan shifting)
.scan_mode (1'b0), // ASIC ONLY: Scan mode
.wkup (1'b0) // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
);
//=============================================================================
// 3) OPENMSP430 PERIPHERALS
//=============================================================================
//
// Digital I/O
//-------------------------------
omsp_gpio #(.P1_EN(1),
.P2_EN(1),
.P3_EN(0),
.P4_EN(0),
.P5_EN(0),
.P6_EN(0)) gpio_0 (
// OUTPUTs
.irq_port1 (irq_port1), // Port 1 interrupt
.irq_port2 (irq_port2), // Port 2 interrupt
.p1_dout (p1_dout), // Port 1 data output
.p1_dout_en (p1_dout_en), // Port 1 data output enable
.p1_sel (p1_sel), // Port 1 function select
.p2_dout (p2_dout), // Port 2 data output
.p2_dout_en (p2_dout_en), // Port 2 data output enable
.p2_sel (p2_sel), // Port 2 function select
.p3_dout (), // Port 3 data output
.p3_dout_en (), // Port 3 data output enable
.p3_sel (), // Port 3 function select
.p4_dout (), // Port 4 data output
.p4_dout_en (), // Port 4 data output enable
.p4_sel (), // Port 4 function select
.p5_dout (), // Port 5 data output
.p5_dout_en (), // Port 5 data output enable
.p5_sel (), // Port 5 function select
.p6_dout (), // Port 6 data output
.p6_dout_en (), // Port 6 data output enable
.p6_sel (), // Port 6 function select
.per_dout (per_dout_gpio), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.p1_din (p1_din), // Port 1 data input
.p2_din (p2_din), // Port 2 data input
.p3_din (8'h00), // Port 3 data input
.p4_din (8'h00), // Port 4 data input
.p5_din (8'h00), // Port 5 data input
.p6_din (8'h00), // Port 6 data input
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst) // Main system reset
);
// Assign LEDs
assign led = p2_dout[1:0] & p2_dout_en[1:0];
// Assign Switches
assign p1_din[7:4] = 4'h0;
assign p1_din[3:0] = switch;
//
// Timer A
//----------------------------------------------
omsp_timerA timerA_0 (
// OUTPUTs
.irq_ta0 (irq_ta0), // Timer A interrupt: TACCR0
.irq_ta1 (irq_ta1), // Timer A interrupt: TAIV, TACCR1, TACCR2
.per_dout (per_dout_tA), // Peripheral data output
.ta_out0 (), // Timer A output 0
.ta_out0_en (), // Timer A output 0 enable
.ta_out1 (), // Timer A output 1
.ta_out1_en (), // Timer A output 1 enable
.ta_out2 (), // Timer A output 2
.ta_out2_en (), // Timer A output 2 enable
// INPUTs
.aclk_en (aclk_en), // ACLK enable (from CPU)
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
.inclk (1'b0), // INCLK external timer clock (SLOW)
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.ta_cci0a (1'b0), // Timer A capture 0 input A
.ta_cci0b (1'b0), // Timer A capture 0 input B
.ta_cci1a (1'b0), // Timer A capture 1 input A
.ta_cci1b (1'b0), // Timer A capture 1 input B
.ta_cci2a (1'b0), // Timer A capture 2 input A
.ta_cci2b (1'b0), // Timer A capture 2 input B
.taclk (1'b0) // TACLK external timer clock (SLOW)
);
//
// Hardware UART
//----------------------------------------------
omsp_uart uart_0 (
// OUTPUTs
.irq_uart_rx (irq_uart_rx), // UART receive interrupt
.irq_uart_tx (irq_uart_tx), // UART transmit interrupt
.per_dout (per_dout_uart), // Peripheral data output
.uart_txd (uart_txd), // UART Data Transmit (TXD)
// INPUTs
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.smclk_en (smclk_en), // SMCLK enable (from CPU)
.uart_rxd (uart_rxd) // UART Data Receive (RXD)
);
//
// Combine peripheral data buses
//-------------------------------
assign per_dout = per_dout_gpio |
per_dout_uart |
per_dout_tA;
//
// Assign interrupts
//-------------------------------
assign nmi = 1'b0;
assign irq_bus = {1'b0, // Vector 13 (0xFFFA)
1'b0, // Vector 12 (0xFFF8)
1'b0, // Vector 11 (0xFFF6)
1'b0, // Vector 10 (0xFFF4) - Watchdog -
irq_ta0, // Vector 9 (0xFFF2)
irq_ta1, // Vector 8 (0xFFF0)
irq_uart_rx, // Vector 7 (0xFFEE)
irq_uart_tx, // Vector 6 (0xFFEC)
1'b0, // Vector 5 (0xFFEA) - Reserved (Timer-A 0 from system 1)
1'b0, // Vector 4 (0xFFE8) - Reserved (Timer-A 1 from system 1)
irq_port2, // Vector 3 (0xFFE6)
irq_port1, // Vector 2 (0xFFE4)
1'b0, // Vector 1 (0xFFE2) - Reserved (Port 2 from system 1)
1'b0}; // Vector 0 (0xFFE0) - Reserved (Port 1 from system 1)
endmodule // omsp_system_0
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_receiveFIFODataOut (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 8: 0] in_port;
input reset_n;
wire clk_en;
wire [ 8: 0] data_in;
wire [ 8: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
Components for aligning colored pixels to memory and the inverse
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
module color_to_memory(color_depth_i, color_i, x_lsb_i,
mem_o, sel_o);
input [1:0] color_depth_i;
input [31:0] color_i;
input [1:0] x_lsb_i;
output [31:0] mem_o;
output [3:0] sel_o;
assign sel_o = (color_depth_i == 2'b00) && (x_lsb_i == 2'b00) ? 4'b1000 : // 8-bit
(color_depth_i == 2'b00) && (x_lsb_i == 2'b01) ? 4'b0100 : // 8-bit
(color_depth_i == 2'b00) && (x_lsb_i == 2'b10) ? 4'b0010 : // 8-bit
(color_depth_i == 2'b00) && (x_lsb_i == 2'b11) ? 4'b0001 : // 8-bit
(color_depth_i == 2'b01) && (x_lsb_i[0] == 1'b0) ? 4'b1100 : // 16-bit, high word
(color_depth_i == 2'b01) && (x_lsb_i[0] == 1'b1) ? 4'b0011 : // 16-bit, low word
4'b1111; // 32-bit
assign mem_o = (color_depth_i == 2'b00) && (x_lsb_i == 2'b00) ? {color_i[7:0], 24'h000000} : // 8-bit
(color_depth_i == 2'b00) && (x_lsb_i == 2'b01) ? {color_i[7:0], 16'h0000} : // 8-bit
(color_depth_i == 2'b00) && (x_lsb_i == 2'b10) ? {color_i[7:0], 8'h00} : // 8-bit
(color_depth_i == 2'b00) && (x_lsb_i == 2'b11) ? {color_i[7:0]} : // 8-bit
(color_depth_i == 2'b01) && (x_lsb_i[0] == 1'b0) ? {color_i[15:0], 16'h0000} : // 16-bit, high word
(color_depth_i == 2'b01) && (x_lsb_i[0] == 1'b1) ? {color_i[15:0]} : // 16-bit, low word
color_i; // 32-bit
endmodule
module memory_to_color(color_depth_i, mem_i, mem_lsb_i,
color_o, sel_o);
input [1:0] color_depth_i;
input [31:0] mem_i;
input [1:0] mem_lsb_i;
output [31:0] color_o;
output [3:0] sel_o;
assign sel_o = color_depth_i == 2'b00 ? 4'b0001 : // 8-bit
color_depth_i == 2'b01 ? 4'b0011 : // 16-bit, low word
4'b1111; // 32-bit
assign color_o = (color_depth_i == 2'b00) && (mem_lsb_i == 2'b00) ? {mem_i[31:24]} : // 8-bit
(color_depth_i == 2'b00) && (mem_lsb_i == 2'b01) ? {mem_i[23:16]} : // 8-bit
(color_depth_i == 2'b00) && (mem_lsb_i == 2'b10) ? {mem_i[15:8]} : // 8-bit
(color_depth_i == 2'b00) && (mem_lsb_i == 2'b11) ? {mem_i[7:0]} : // 8-bit
(color_depth_i == 2'b01) && (mem_lsb_i[0] == 1'b0) ? {mem_i[31:16]} : // 16-bit, high word
(color_depth_i == 2'b01) && (mem_lsb_i[0] == 1'b1) ? {mem_i[15:0]} : // 16-bit, low word
mem_i; // 32-bit
endmodule
|
//IEEE Floating Point Adder (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Divider (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
//
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Multiplier (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Divider (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
//
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [108:0] quotient, divisor, dividend, remainder;
reg [6:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 1024) && (b_e == 1024)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 56;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[108];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 107) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[55:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Multiplier (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-10
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [107:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[107:55];
guard <= product[54];
round_bit <= product[53];
sticky <= (product[52:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[11:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Adder (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [63:0] a, b, z;
reg [55:0] a_m, b_m;
reg [52:0] z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [56:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[51 : 0], 3'd0};
b_m <= {b[51 : 0], 3'd0};
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -1023) && (a_m == 0)) && (($signed(b_e) == -1023) && (b_m == 0))) begin
z[63] <= a_s & b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s;
z[62:52] <= a_e[10:0] + 1023;
z[51:0] <= a_m[55:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[55] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[55] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= {1'd0, a_m} + b_m;
z_s <= a_s;
end else begin
if (a_m > b_m) begin
sum <= {1'd0, a_m} - b_m;
z_s <= a_s;
end else begin
sum <= {1'd0, b_m} - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[56]) begin
z_m <= sum[56:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[55:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [31:0] a, z, value;
reg [23:0] z_m;
reg [7:0] z_r;
reg [7:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -127;
state <= pack;
end else begin
value <= a[31] ? -a : a;
z_s <= a[31];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 31;
z_m <= value[31:8];
z_r <= value[7:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[23]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[7];
z_r <= z_r << 1;
end else begin
guard <= z_r[7];
round_bit <= z_r[6];
sticky <= z_r[5:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e + 127;
z[31] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [63:0] a, z, value;
reg [52:0] z_m;
reg [10:0] z_r;
reg [10:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -1023;
state <= pack;
end else begin
value <= a[63] ? -a : a;
z_s <= a[63];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 63;
z_m <= value[63:11];
z_r <= value[10:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[52]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[10];
z_r <= z_r << 1;
end else begin
guard <= z_r[10];
round_bit <= z_r[9];
sticky <= z_r[8:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e + 1023;
z[63] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [63:0] a_m, a, z;
reg [11:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[63:11] <= {1'b1, a[51 : 0]};
a_m[10:0] <= 0;
a_e <= a[62 : 52] - 1023;
a_s <= a[63];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -1023) begin
//zero
z <= 0;
state <= put_z;
end else if ($signed(a_e) == 1024 && a[51:0] != 0) begin
//nan
z <= 64'h8000000000000000;
state <= put_z;
end else if ($signed(a_e) > 63) begin
//too big
if (a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= 64'h0000000000000000;
end
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 63 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[63] && a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [1:0] state;
parameter get_a = 3'd0,
unpack = 3'd1,
denormalise = 3'd2,
put_z = 3'd3;
reg [63:0] a;
reg [31:0] z;
reg [10:0] z_e;
reg [23:0] z_m;
reg guard;
reg round;
reg sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
z[31] <= a[63];
state <= put_z;
if (a[62:52] == 0) begin
z[30:23] <= 0;
z[22:0] <= 0;
end else if (a[62:52] < 897) begin
z[30:23] <= 0;
z_m <= {1'd1, a[51:29]};
z_e <= a[62:52];
guard <= a[28];
round <= a[27];
sticky <= a[26:0] != 0;
state <= denormalise;
end else if (a[62:52] == 2047) begin
z[30:23] <= 255;
z[22:0] <= 0;
if (a[51:0]) begin
z[22] <= 1;
end
end else if (a[62:52] > 1150) begin
z[30:23] <= 255;
z[22:0] <= 0;
end else begin
z[30:23] <= (a[62:52] - 1023) + 127;
if (a[28] && (a[27] || a[26:0])) begin
z[22:0] <= a[51:29] + 1;
end else begin
z[22:0] <= a[51:29];
end
end
end
denormalise:
begin
if (z_e == 897 || (z_m == 0 && guard == 0)) begin
state <= put_z;
z[22:0] <= z_m;
if (guard && (round || sticky)) begin
z[22:0] <= z_m + 1;
end
end else begin
z_e <= z_e + 1;
z_m <= {1'd0, z_m[23:1]};
guard <= z_m[0];
round <= guard;
sticky <= sticky | round;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
module station_management
#(
parameter STATE_IDLE = 4'd0,
parameter STATE_PREAMBLE = 4'd1,
parameter STATE_START_OF_FRAME = 4'd2,
parameter STATE_OPCODE = 4'd3,
parameter STATE_PHY_ADDRESS = 4'd4,
parameter STATE_REG_ADDRESS = 4'd5,
parameter STATE_TURNAROUND = 4'd6,
parameter STATE_DATA = 4'd7,
parameter STATE_OK = 4'd8,
parameter READ = 1'b0,
parameter WRITE = 1'b1
)(
input wire reset,
input wire clock,
output wire mdc,
inout wire mdio,
input wire mode,
input wire begin_transaction,
input wire [4:0] phy_address,
input wire [4:0] reg_address,
input wire [15:0] data_in,
output reg [15:0] data_out
);
localparam start_of_frame = 2'b01;
localparam turnaround = 2'b10;
reg [3:0] state;
reg [3:0] next_state;
reg mdio_data;
reg writing;
reg [1:0] opcode;
reg [15:0] data_read;
reg [4:0] preamble_counter;
reg start_of_frame_counter;
reg opcode_counter;
reg [2:0] phy_address_counter;
reg [2:0] reg_address_counter;
reg turnaround_counter;
reg [3:0] data_counter;
// MDC
assign mdc = clock;
// MDIO - if reading present high impedance.
assign mdio = (writing) ? mdio_data : 1'bz;
// State Update
always @(posedge mdc)
if (reset)
state <= STATE_IDLE;
else
state <= next_state;
// State Machine
always @(*)
case(state)
STATE_IDLE:
if ( begin_transaction )
next_state <= STATE_PREAMBLE;
else
next_state <= STATE_IDLE;
STATE_PREAMBLE:
if (preamble_counter == 5'b0)
next_state <= STATE_START_OF_FRAME;
else
next_state <= STATE_PREAMBLE;
STATE_START_OF_FRAME:
if (start_of_frame_counter == 0)
next_state <= STATE_OPCODE;
else
next_state <= STATE_START_OF_FRAME;
STATE_OPCODE:
if (opcode_counter == 0)
next_state <= STATE_PHY_ADDRESS;
else
next_state <= STATE_OPCODE;
STATE_PHY_ADDRESS:
if (phy_address_counter == 0)
next_state <= STATE_REG_ADDRESS;
else
next_state <= STATE_PHY_ADDRESS;
STATE_REG_ADDRESS:
if (reg_address_counter == 0)
next_state <= STATE_TURNAROUND;
else
next_state <= STATE_REG_ADDRESS;
STATE_TURNAROUND:
if (turnaround_counter == 0)
next_state <= STATE_DATA;
else
next_state <= STATE_TURNAROUND;
STATE_DATA:
if (data_counter == 0)
next_state <= STATE_OK;
else
next_state <= STATE_DATA;
STATE_OK:
next_state <= STATE_IDLE;
default:
next_state <= STATE_IDLE;
endcase
// State Outputs
always @(*)
case(state)
STATE_IDLE:
mdio_data <= 0;
STATE_PREAMBLE:
mdio_data <= 1;
STATE_START_OF_FRAME:
mdio_data <= start_of_frame[start_of_frame_counter-:1];
STATE_OPCODE:
mdio_data <= opcode[opcode_counter-:1];
STATE_PHY_ADDRESS:
mdio_data <= phy_address[phy_address_counter-:1];
STATE_REG_ADDRESS:
mdio_data <= reg_address[reg_address_counter-:1];
STATE_TURNAROUND:
mdio_data <= turnaround[turnaround_counter-:1];
STATE_DATA:
mdio_data <= data_in[data_counter-:1];
default:
mdio_data <= 0;
endcase
always @(posedge mdc)
if (state == STATE_DATA && mode == READ)
data_read[data_counter-:1] <= mdio;
always @(*)
if (state == STATE_OK)
begin
data_out <= data_read;
end
always @(*)
if ((state == STATE_TURNAROUND && mode == READ) ||
(state == STATE_DATA && mode == READ))
writing <= 0;
else
writing <= 1;
always @(*)
if (mode == READ)
opcode <= 2'b10;
else
opcode <= 2'b01;
// Counters
// Preamble
always @(posedge mdc)
if (reset)
preamble_counter <= 5'd31;
else if (state == STATE_PREAMBLE)
preamble_counter <= preamble_counter - 1;
else
preamble_counter <= 5'd31;
// Start of Frame
always @(posedge mdc)
if (reset)
start_of_frame_counter <= 1'b1;
else if (state == STATE_START_OF_FRAME)
start_of_frame_counter <= 1'b0;
else
start_of_frame_counter <= 1'b1;
// Opcode
always @(posedge mdc)
if (reset)
opcode_counter <= 1'b1;
else if (state == STATE_OPCODE)
opcode_counter <= 1'b0;
else
opcode_counter <= 1'b1;
// PHY Address
always @(posedge mdc)
if (reset)
phy_address_counter <= 3'd4;
else if (state == STATE_PHY_ADDRESS)
phy_address_counter <= phy_address_counter - 1;
else
phy_address_counter <= 3'd4;
// Register Address
always @(posedge mdc)
if (reset)
reg_address_counter <= 3'd4;
else if (state == STATE_REG_ADDRESS)
reg_address_counter <= reg_address_counter - 1;
else
reg_address_counter <= 3'd4;
// Turnaround
always @(posedge mdc)
if (reset)
turnaround_counter <= 1'b1;
else if (state == STATE_TURNAROUND)
turnaround_counter <= 1'b0;
else
turnaround_counter <= 1'b1;
// Data
always @(posedge mdc)
if (reset)
data_counter <= 4'd15;
else if (state == STATE_DATA)
data_counter <= data_counter - 1;
else
data_counter <= 4'd15;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Fri Jul 15 16:37:20 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.4 2005/11/30 14:04:17 wig Exp $
// $Date: 2005/11/30 14:04:17 $
// $Log: ent_ba.v,v $
// Revision 1.4 2005/11/30 14:04:17 wig
// Updated testcase references
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Color Space Conversion, adder. This is a simple adder, but had to be
// pipe-lined for faster clock rates. The delay input is delay-matched to
// the sum pipe-line stages
`timescale 1ps/1ps
module ad_csc_1_add #(
parameter DELAY_DATA_WIDTH = 16) (
// all signed
input clk,
input [24:0] data_1,
input [24:0] data_2,
input [24:0] data_3,
input [24:0] data_4,
output reg [ 7:0] data_p,
// delay match
input [DW:0] ddata_in,
output reg [DW:0] ddata_out);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [24:0] p1_data_1 = 'd0;
reg [24:0] p1_data_2 = 'd0;
reg [24:0] p1_data_3 = 'd0;
reg [24:0] p1_data_4 = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [24:0] p2_data_0 = 'd0;
reg [24:0] p2_data_1 = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [24:0] p3_data = 'd0;
// internal signals
wire [24:0] p1_data_1_p_s;
wire [24:0] p1_data_1_n_s;
wire [24:0] p1_data_1_s;
wire [24:0] p1_data_2_p_s;
wire [24:0] p1_data_2_n_s;
wire [24:0] p1_data_2_s;
wire [24:0] p1_data_3_p_s;
wire [24:0] p1_data_3_n_s;
wire [24:0] p1_data_3_s;
wire [24:0] p1_data_4_p_s;
wire [24:0] p1_data_4_n_s;
wire [24:0] p1_data_4_s;
// pipe line stage 1, get the two's complement versions
assign p1_data_1_p_s = {1'b0, data_1[23:0]};
assign p1_data_1_n_s = ~p1_data_1_p_s + 1'b1;
assign p1_data_1_s = (data_1[24] == 1'b1) ? p1_data_1_n_s : p1_data_1_p_s;
assign p1_data_2_p_s = {1'b0, data_2[23:0]};
assign p1_data_2_n_s = ~p1_data_2_p_s + 1'b1;
assign p1_data_2_s = (data_2[24] == 1'b1) ? p1_data_2_n_s : p1_data_2_p_s;
assign p1_data_3_p_s = {1'b0, data_3[23:0]};
assign p1_data_3_n_s = ~p1_data_3_p_s + 1'b1;
assign p1_data_3_s = (data_3[24] == 1'b1) ? p1_data_3_n_s : p1_data_3_p_s;
assign p1_data_4_p_s = {1'b0, data_4[23:0]};
assign p1_data_4_n_s = ~p1_data_4_p_s + 1'b1;
assign p1_data_4_s = (data_4[24] == 1'b1) ? p1_data_4_n_s : p1_data_4_p_s;
always @(posedge clk) begin
p1_ddata <= ddata_in;
p1_data_1 <= p1_data_1_s;
p1_data_2 <= p1_data_2_s;
p1_data_3 <= p1_data_3_s;
p1_data_4 <= p1_data_4_s;
end
// pipe line stage 2, get the sum (intermediate, 4->2)
always @(posedge clk) begin
p2_ddata <= p1_ddata;
p2_data_0 <= p1_data_1 + p1_data_2;
p2_data_1 <= p1_data_3 + p1_data_4;
end
// pipe line stage 3, get the sum (final, 2->1)
always @(posedge clk) begin
p3_ddata <= p2_ddata;
p3_data <= p2_data_0 + p2_data_1;
end
// output registers, output is unsigned (0 if sum is < 0) and saturated.
// the inputs are expected to be 1.4.20 format (output is 8bits).
always @(posedge clk) begin
ddata_out <= p3_ddata;
if (p3_data[24] == 1'b1) begin
data_p <= 8'h00;
end else if (p3_data[23:20] == 'd0) begin
data_p <= p3_data[19:12];
end else begin
data_p <= 8'hff;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//deps: register_unit.v
`timescale 1ns/1ps
module register_unit_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] rD_data_out; // From ru of register_unit.v
wire [15:0] rS_data_out; // From ru of register_unit.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To ru of register_unit.v
reg en; // To ru of register_unit.v
reg [15:0] rD_data_in; // To ru of register_unit.v
reg [2:0] rD_sel; // To ru of register_unit.v
reg [15:0] rS_data_in; // To ru of register_unit.v
reg [2:0] rS_sel; // To ru of register_unit.v
reg rS_wr_en; // To ru of register_unit.v
reg wr_en; // To ru of register_unit.v
// End of automatics
register_unit ru (/*AUTOINST*/
// Outputs
.rD_data_out (rD_data_out[15:0]),
.rS_data_out (rS_data_out[15:0]),
// Inputs
.clk (clk),
.en (en),
.wr_en (wr_en),
.rS_wr_en (rS_wr_en),
.rD_sel (rD_sel[2:0]),
.rS_sel (rS_sel[2:0]),
.rD_data_in (rD_data_in[15:0]),
.rS_data_in (rS_data_in[15:0]));
initial begin
clk <= 0;
rD_sel <= 0;
en <= 0;
rS_sel <= 0;
wr_en <= 0;
rS_wr_en <= 0;
rD_data_in <= 0;
rS_data_in <= 0;
$dumpfile("dump.vcd");
$dumpvars;
end
always #5 clk <= ~clk;
initial begin
#20
en <= 1;
rD_sel <= 1;
rD_data_in <= 16'hfeed;
wr_en <= 1;
#10
rD_sel <= 0;
rD_data_in <= 16'hbeef;
wr_en <= 1;
#10
rD_sel <= 0;
rS_sel <= 1;
wr_en <= 0;
#10
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_1_V
`define SKY130_FD_SC_LS__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_1_V
|
/**
* bsg_fifo_reorder.v
*
*/
`include "bsg_defines.v"
module bsg_fifo_reorder
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter lg_els_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input clk_i
, input reset_i
// FIFO allocates the next available addr
, output fifo_alloc_v_o
, output [lg_els_lp-1:0] fifo_alloc_id_o
, input fifo_alloc_yumi_i
// random access write
// data can be written out of order
, input write_v_i
, input [lg_els_lp-1:0] write_id_i
, input [width_p-1:0] write_data_i
// dequeue written items in order
, output fifo_deq_v_o
, output [width_p-1:0] fifo_deq_data_o
// id of the currently dequeueing fifo entry. This can be used to select
// metadata from a separate memory storage, written at a different time
, output [lg_els_lp-1:0] fifo_deq_id_o
, input fifo_deq_yumi_i
// this signals that the FIFO is empty
// i.e. there is no reserved spot for returning data,
// and all valid data in the FIFO has been consumed.
, output logic empty_o
);
// fifo tracker
// enque when id is allocated.
// deque when data is dequeued.
logic [lg_els_lp-1:0] wptr_r, rptr_r;
logic full, empty;
logic enq, deq;
bsg_fifo_tracker #(
.els_p(els_p)
) tracker0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.enq_i(enq)
,.deq_i(deq)
,.wptr_r_o(wptr_r)
,.rptr_r_o(rptr_r)
,.rptr_n_o()
,.full_o(full)
,.empty_o(empty)
);
assign fifo_alloc_v_o = ~full;
assign enq = ~full & fifo_alloc_yumi_i;
assign fifo_alloc_id_o = wptr_r;
assign empty_o = empty;
// valid bit for each entry
// this valid bit is cleared, when the valid data is dequeued.
// this valid bit is set, when the valid data is written.
logic [els_p-1:0] valid_r;
logic [els_p-1:0] set_valid;
logic [els_p-1:0] clear_valid;
bsg_decode_with_v #(
.num_out_p(els_p)
) set_demux0 (
.i(write_id_i)
,.v_i(write_v_i)
,.o(set_valid)
);
bsg_decode_with_v #(
.num_out_p(els_p)
) clear_demux0 (
.i(rptr_r)
,.v_i(deq)
,.o(clear_valid)
);
bsg_dff_reset_set_clear #(
.width_p(els_p)
) dff_valid0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.set_i(set_valid)
,.clear_i(clear_valid)
,.data_o(valid_r)
);
// deque logic
wire fifo_deq_v_lo = valid_r[rptr_r] & ~empty;
assign fifo_deq_v_o = fifo_deq_v_lo;
assign deq = fifo_deq_yumi_i;
// data storage
bsg_mem_1r1w #(
.width_p(width_p)
,.els_p(els_p)
) mem0 (
.w_clk_i(clk_i)
,.w_reset_i(reset_i)
,.w_v_i(write_v_i)
,.w_addr_i(write_id_i)
,.w_data_i(write_data_i)
,.r_v_i(fifo_deq_v_lo)
,.r_addr_i(rptr_r)
,.r_data_o(fifo_deq_data_o)
);
assign fifo_deq_id_o = rptr_r;
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (fifo_alloc_yumi_i)
assert(fifo_alloc_v_o) else $error("Handshaking error. fifo_alloc_yumi_i raised without fifo_alloc_v_o.");
if (fifo_deq_yumi_i)
assert(fifo_deq_v_o) else $error("Handshaking error. fifo_deq_yumi_i raised without fifo_deq_v_o.");
if (write_v_i)
assert(~valid_r[write_id_i]) else $error("Cannot write to an already valid data.");
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_reorder)
|
/* S-box using all normal bases */
/* case # 4 : [d^16, d], [alpha^8, alpha^2], [Omega^2, Omega] */
/* beta^8 = N^2*alpha^2, N = w^2 */
/* optimized using OR gates and NAND gates */
/* square in GF(2^2), using normal basis [Omega^2,Omega] */
/* inverse is the same as square in GF(2^2), using any normal basis */
module GF_SQ_2 ( A, Q );
input [1:0] A;
output [1:0] Q;
assign Q = { A[0], A[1] };
endmodule
/* multiply in GF(2^2), shared factors, using normal basis [Omega^2,Omega] */
module GF_MULS_2 ( A, ab, B, cd, Y );
input [1:0] A;
input ab;
input [1:0] B;
input cd;
output [1:0] Y;
wire abcd, p, q;
assign abcd = ~(ab & cd); /* note: ~& syntax for NAND won¡¯t compile */
assign p = (~(A[1] & B[1])) ^ abcd;
assign q = (~(A[0] & B[0])) ^ abcd;
assign Y = { p, q };
endmodule
/* multiply & scale by N in GF(2^2), shared factors, basis [Omega^2,Omega] */
module GF_MULS_SCL_2 ( A, ab, B, cd, Y );
input [1:0] A;
input ab;
input [1:0] B;
input cd;
output [1:0] Y;
wire t, p, q;
assign t = ~(A[0] & B[0]); /* note: ~& syntax for NAND won¡¯t compile */
assign p = (~(ab & cd)) ^ t;
assign q = (~(A[1] & B[1])) ^ t;
assign Y = { p, q };
endmodule
/* inverse in GF(2^4)/GF(2^2), using normal basis [alpha^8, alpha^2] */
module GF_INV_4 ( X, Y );
input [3:0] X;
output [3:0] Y;
wire [1:0] a, b, c, d, p, q;
wire sa, sb, sd; /* for shared factors in multipliers */
assign a = X[3:2];
assign b = X[1:0];
assign sa = a[1] ^ a[0];
assign sb = b[1] ^ b[0];
/* optimize this section as shown below
GF_MULS_2 abmul(a, sa, b, sb, ab);
GF_SQ_2 absq( (a ^ b), ab2);
GF_SCLW2_2 absclN( ab2, ab2N);
GF_SQ_2 dinv( (ab ^ ab2N), d);
*/
assign c = { /* note: ~| syntax for NOR won¡¯t compile */
~(a[1] | b[1]) ^ (~(sa & sb)) ,
~(sa | sb) ^ (~(a[0] & b[0])) };
GF_SQ_2 dinv( c, d);
/* end of optimization */
assign sd = d[1] ^ d[0];
GF_MULS_2 pmul(d, sd, b, sb, p);
GF_MULS_2 qmul(d, sd, a, sa, q);
assign Y = { p, q };
endmodule
/* multiply in GF(2^4)/GF(2^2), shared factors, basis [alpha^8, alpha^2] */
module GF_MULS_4 ( A, a1, Al, Ah, aa, B, b1, Bl, Bh, bb, Q );
input [3:0] A;
input [1:0] a1;
input Al;
input Ah;
input aa;
input [3:0] B;
input [1:0] b1;
input Bl;
input Bh;
input bb;
output [3:0] Q;
wire [1:0] ph, pl, p;
GF_MULS_2 himul(A[3:2], Ah, B[3:2], Bh, ph);
GF_MULS_2 lomul(A[1:0], Al, B[1:0], Bl, pl);
GF_MULS_SCL_2 summul( a1, aa, b1, bb, p);
assign Q = { (ph ^ p), (pl ^ p) };
endmodule
/* inverse in GF(2^8)/GF(2^4), using normal basis [d^16, d] */
module GF_INV_8 ( X, Y );
input [7:0] X;
output [7:0] Y;
wire [3:0] a, b, c, d, p, q;
wire [1:0] sa, sb, sd; /* for shared factors in multipliers */
wire al, ah, aa, bl, bh, bb, dl, dh, dd; /* for shared factors */
wire c1, c2, c3; /* for temp var */
assign a = X[7:4];
assign b = X[3:0];
assign sa = a[3:2] ^ a[1:0];
assign sb = b[3:2] ^ b[1:0];
assign al = a[1] ^ a[0];
assign ah = a[3] ^ a[2];
assign aa = sa[1] ^ sa[0];
assign bl = b[1] ^ b[0];
assign bh = b[3] ^ b[2];
assign bb = sb[1] ^ sb[0];
// optimize this section as shown below
/*GF_MULS_4 abmul(a, sa, al, ah, aa, b, sb, bl, bh, bb, ab);
GF_SQ_SCL_4 absq( (a ^ b), ab2);
GF_INV_4 dinv( (ab ^ ab2), d);*/
assign c1 = ~(ah & bh);
assign c2 = ~(sa[0] & sb[0]);
assign c3 = ~(aa & bb);
assign c = {
(~(sa[0] | sb[0]) ^ (~(a[3] & b[3]))) ^ c1 ^ c3 ,
(~(sa[1] | sb[1]) ^ (~(a[2] & b[2]))) ^ c1 ^ c2 ,
(~(al | bl) ^ (~(a[1] & b[1]))) ^ c2 ^ c3 ,
(~(a[0] | b[0]) ^ (~(al & bl))) ^ (~(sa[1] & sb[1])) ^ c2 };
GF_INV_4 dinv( c, d);
/* end of optimization */
assign sd = d[3:2] ^ d[1:0];
assign dl = d[1] ^ d[0];
assign dh = d[3] ^ d[2];
assign dd = sd[1] ^ sd[0];
GF_MULS_4 pmul(d, sd, dl, dh, dd, b, sb, bl, bh, bb, p);
GF_MULS_4 qmul(d, sd, dl, dh, dd, a, sa, al, ah, aa, q);
assign Y = { p, q };
endmodule
/* find either Sbox or its inverse in GF(2^8), by Canright Algorithm */
module bSbox ( A, Q );
input [7:0] A;
output [7:0] Q;
wire [7:0] B, C;
wire R1, R2, R3, R4, R5, R6, R7, R8, R9;
wire T1, T2, T3, T4, T5, T6, T7, T8, T9;
/* change basis from GF(2^8) to GF(2^8)/GF(2^4)/GF(2^2) */
/* combine with bit inverse matrix multiply of Sbox */
assign R1 = A[7] ^ A[5] ;
assign R2 = A[7] ^ A[4] ;
assign R3 = A[6] ^ A[0] ;
assign R4 = A[5] ^ R3 ;
assign R5 = A[4] ^ R4 ;
assign R6 = A[3] ^ A[0] ;
assign R7 = A[2] ^ R1 ;
assign R8 = A[1] ^ R3 ;
assign R9 = A[3] ^ R8 ;
assign B[7] = R7 ^ R8 ;
assign B[6] = R5 ;
assign B[5] = A[1] ^ R4 ;
assign B[4] = R1 ^ R3 ;
assign B[3] = A[1] ^ R2 ^ R6 ;
assign B[2] = A[0] ;
assign B[1] = R4 ;
assign B[0] = A[2] ^ R9 ;
GF_INV_8 inv( B, C );
/* change basis back from GF(2^8)/GF(2^4)/GF(2^2) to GF(2^8) */
assign T1 = C[7] ^ C[3] ;
assign T2 = C[6] ^ C[4] ;
assign T3 = C[6] ^ C[0] ;
assign T4 = C[5] ^ C[3] ;
assign T5 = C[5] ^ T1 ;
assign T6 = C[5] ^ C[1] ;
assign T7 = C[4] ^ T6 ;
assign T8 = C[2] ^ T4 ;
assign T9 = C[1] ^ T2 ;
assign Q[7] = T4 ;
assign Q[6] = ~T1 ;
assign Q[5] = ~T3 ;
assign Q[4] = T5 ;
assign Q[3] = T2 ^ T5 ;
assign Q[2] = T3 ^ T8 ;
assign Q[1] = ~T7 ;
assign Q[0] = ~T9 ;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ADM7V3_Gen3x4If128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx 7V3 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module ADM7V3_Gen3x4If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 4,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 6)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [5:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
OBUF
#()
led_2_obuf
(.O(LED[2]),
.I(cfg_ltssm_state[2]));
OBUF
#()
led_3_obuf
(.O(LED[3]),
.I(cfg_ltssm_state[3]));
OBUF
#()
led_4_obuf
(.O(LED[4]),
.I(cfg_ltssm_state[4]));
OBUF
#()
led_5_obuf
(.O(LED[5]),
.I(cfg_ltssm_state[5]));
OBUF
#()
led_6_obuf
(.O(LED[6]),
.I(pcie_reset_n));
OBUF
#()
led_7_obuf
(.O(LED[7]),
.I(rst_out));
// Core Top Level Wrapper
PCIeGen3x4If128
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_adm7V3
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])
/*AUTOINST*/);
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
/*AUTOINST*/);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("../../../../riffa_hdl/" "../../")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_BLACKBOX_V
`define SKY130_FD_SC_LS__A222O_BLACKBOX_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_BLACKBOX_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*
* Chuck Benz, Hollis, NH Copyright (c)2002
*
* The information and description contained herein is the
* property of Chuck Benz.
*
* Permission is granted for any reuse of this information
* and description as long as this copyright notice is
* preserved. Modifications may be made as long as this
* notice is preserved.
* per Widmer and Franaszek
*/
`timescale 1ps/1ps
`default_nettype none
module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err);
input wire [9:0] datain;
input wire dispin;
output wire [8:0] dataout;
output wire dispout;
output wire code_err;
output wire disp_err;
wire ai = datain[0];
wire bi = datain[1];
wire ci = datain[2];
wire di = datain[3];
wire ei = datain[4];
wire ii = datain[5];
wire fi = datain[6];
wire gi = datain[7];
wire hi = datain[8];
wire ji = datain[9];
wire aeqb = (ai & bi) | (!ai & !bi);
wire ceqd = (ci & di) | (!ci & !di);
wire p22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd);
wire p13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi);
wire p31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi);
wire p40 = ai & bi & ci & di;
wire p04 = !ai & !bi & !ci & !di;
wire disp6a = p31 | (p22 & dispin); // pos disp if p22 and was pos, or p31.
wire disp6a2 = p31 & dispin; // disp is ++ after 4 bits
wire disp6a0 = p13 & ! dispin; // -- disp after 4 bits
wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 |
(ei & ii & di)) & (ei | ii | di));
// The 5B/6B decoding special cases where ABCDE != abcde
wire p22bceeqi = p22 & bi & ci & (ei == ii);
wire p22bncneeqi = p22 & !bi & !ci & (ei == ii);
wire p13in = p13 & !ii;
wire p31i = p31 & ii;
wire p13dei = p13 & di & ei & ii;
wire p22aceeqi = p22 & ai & ci & (ei == ii);
wire p22ancneeqi = p22 & !ai & !ci & (ei == ii);
wire p13en = p13 & !ei;
wire anbnenin = !ai & !bi & !ei & !ii;
wire abei = ai & bi & ei & ii;
wire cdei = ci & di & ei & ii;
wire cndnenin = !ci & !di & !ei & !ii;
// non-zero disparity cases:
wire p22enin = p22 & !ei & !ii;
wire p22ei = p22 & ei & ii;
//wire p13in = p12 & !ii;
//wire p31i = p31 & ii;
wire p31dnenin = p31 & !di & !ei & !ii;
//wire p13dei = p13 & di & ei & ii;
wire p31e = p31 & ei;
wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi |
p13en | abei | cndnenin;
wire compb = p22bceeqi | p31i | p13dei | p22aceeqi |
p13en | abei | cndnenin;
wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi |
p13en | anbnenin | cndnenin;
wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi |
p13en | abei | cndnenin;
wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi |
p13en | anbnenin | cndnenin;
wire ao = ai ^ compa;
wire bo = bi ^ compb;
wire co = ci ^ compc;
wire do_ = di ^ compd;
wire eo = ei ^ compe;
wire feqg = (fi & gi) | (!fi & !gi);
wire heqj = (hi & ji) | (!hi & !ji);
wire fghj22 = (fi & gi & !hi & !ji) |
(!fi & !gi & hi & ji) |
( !feqg & !heqj);
wire fghjp13 = ( !feqg & !hi & !ji) |
( !heqj & !fi & !gi);
wire fghjp31 = ( (!feqg) & hi & ji) |
( !heqj & fi & gi);
assign dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji);
wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) |
(p13 & !ei & ii & gi & hi & ji) |
(p31 & ei & !ii & !gi & !hi & !ji));
wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1
((dispin & ci & di & !ei & !ii) | ko |
(dispin & !ci & di & !ei & !ii))) |
(!fi & gi & hi & // 0111 cases, where disp6b is 0
(( !dispin & !ci & !di & ei & ii) | ko |
( !dispin & ci & !di & ei & ii)));
wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii);
// k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
wire k28p = ! (ci | di | ei | ii);
wire fo = (ji & !fi & (hi | !gi | k28p)) |
(fi & !ji & (!hi | gi | !k28p)) |
(k28p & gi & hi) |
(!k28p & !gi & !hi);
wire go = (ji & !fi & (hi | !gi | !k28p)) |
(fi & !ji & (!hi | gi |k28p)) |
(!k28p & gi & hi) |
(k28p & !gi & !hi);
wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) |
(fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) |
(!fi & gi & hi & ji) | (fi & !gi & !hi & !ji);
wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii);
wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii);
wire disp4p = fghjp31;
wire disp4n = fghjp13;
assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) |
(p13 & !ei & !ii) | (p31 & ei & ii) |
(ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) |
(ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) |
(!p31 & ei & !ii & !gi & !hi & !ji) |
(!p13 & !ei & ii & gi & hi & ji) |
(((ei & ii & !gi & !hi & !ji) |
(!ei & !ii & gi & hi & ji)) &
! ((ci & di & ei) | (!ci & !di & !ei))) |
(disp6p & disp4p) | (disp6n & disp4n) |
(ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) |
(!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) |
(fi & gi & !hi & !ji & disp6p) |
(!fi & !gi & hi & ji & disp6n) |
(ci & di & ei & ii & !fi & !gi & !hi) |
(!ci & !di & !ei & !ii & fi & gi & hi);
assign dataout = {ko, ho, go, fo, eo, do_, co, bo, ao};
// my disp err fires for any legal codes that violate disparity, may fire for illegal codes
assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) |
(dispin & !disp6n & fi & gi) |
(dispin & ai & bi & ci) |
(dispin & !disp6n & disp4p) |
(!dispin & !disp6p & !fi & !gi) |
(!dispin & !ai & !bi & !ci) |
(!dispin & !disp6p & disp4n) |
(disp6p & disp4p) | (disp6n & disp4n));
endmodule
|
// -*- mode: Verilog; verilog-auto-lineup-declaration: nil; -*-
//-----------------------------------------------------------------------------
// Title : Synchronous FIFO
// Project : Common
//-----------------------------------------------------------------------------
// File : sync_fifo.v
//-----------------------------------------------------------------------------
// Description : Synchronous FIFO using BRAM.
//
// Implements a variable width/depth synchronous FIFO. The synthesis
// tool may choose to implement the memory as a block RAM.
//-----------------------------------------------------------------------------
// Copyright 1994-2009 Beyond Circuits. All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE BEYOND CIRCUITS ``AS IS'' AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
// SHALL BEYOND CIRCUITS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//------------------------------------------------------------------------------
`timescale 1ns/1ns
module sync_fifo
#(
parameter depth = 32,
parameter width = 32,
// Need the log of the parameters as parameters also due to an XST bug.
parameter log2_depth = log2(depth),
parameter log2_depthp1 = log2(depth+1)
)
(
input clk,
input reset,
input wr_enable,
input rd_enable,
output reg empty,
output reg full,
output [width-1:0] rd_data,
input [width-1:0] wr_data,
output reg [log2_depthp1-1:0] count
);
// log2 -- return the log base 2 of value.
function integer log2;
input [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
// increment -- add one to value modulo depth.
function [log2_depth-1:0] increment;
input [log2_depth-1:0] value;
begin
if (value == depth-1)
increment = 0;
else
increment = value+1;
end
endfunction
// writing -- true when we write to the RAM.
wire writing = wr_enable && (rd_enable || !full);
// reading -- true when we are reading from the RAM.
wire reading = rd_enable && !empty;
// rd_ptr -- the read pointer.
reg [log2_depth-1:0] rd_ptr;
// next_rd_ptr -- the next value for the read pointer.
// We need to name this combinational value because it
// is needed to use the write-before-read style RAM.
reg [log2_depth-1:0] next_rd_ptr;
always @(*)
if (reset)
next_rd_ptr = 0;
else if (reading)
next_rd_ptr = increment(rd_ptr);
else
next_rd_ptr = rd_ptr;
always @(posedge clk)
rd_ptr <= next_rd_ptr;
// wr_ptr -- the write pointer
reg [log2_depth-1:0] wr_ptr;
// next_wr_ptr -- the next value for the write pointer.
reg [log2_depth-1:0] next_wr_ptr;
always @(*)
if (reset)
next_wr_ptr = 0;
else if (writing)
next_wr_ptr = increment(wr_ptr);
else
next_wr_ptr = wr_ptr;
always @(posedge clk)
wr_ptr <= next_wr_ptr;
// count -- the number of valid entries in the FIFO.
always @(posedge clk)
if (reset)
count <= 0;
else if (writing && !reading)
count <= count+1;
else if (reading && !writing)
count <= count-1;
// empty -- true if the FIFO is empty.
// Note that this doesn't depend on count so if the count
// output is unused the logic for computing the count can
// be optimized away.
always @(posedge clk)
if (reset)
empty <= 1;
else if (reading && next_wr_ptr == next_rd_ptr && !full)
empty <= 1;
else
if (writing && !reading)
empty <= 0;
// full -- true if the FIFO is full.
// Again, this is not dependent on count.
always @(posedge clk)
if (reset)
full <= 0;
else if (writing && next_wr_ptr == next_rd_ptr)
full <= 1;
else if (reading && !writing)
full <= 0;
// We need to infer a write first style RAM so that when
// the FIFO is empty the write data can flow through to
// the read side and be available the next clock cycle.
reg [width-1:0] mem [depth-1:0];
always @(posedge clk)
begin
if (writing)
mem[wr_ptr] <= wr_data;
rd_ptr <= next_rd_ptr;
end
assign rd_data = mem[rd_ptr];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_1_V
`define SKY130_FD_SC_LS__A211OI_1_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211oi_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O221AI_PP_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_2TO1_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_MUX_2TO1_BLACKBOX_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_mux_2to1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_2TO1_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXTP_PP_BLACKBOX_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTP_PP_BLACKBOX_V
|
module counter_26bit (En, Clk, Clr, Q);
input En, Clk, Clr;
output [25:0] Q;
wire [25:0] T, Qs;
t_flipflop T0 (En, Clk, Clr, Qs[0]);
assign T[0] = En & Qs[0];
t_flipflop T1 (T[0], Clk, Clr, Qs[1]);
assign T[1] = T[0] & Qs[1];
t_flipflop T2 (T[1], Clk, Clr, Qs[2]);
assign T[2] = T[1] & Qs[2];
t_flipflop T3 (T[2], Clk, Clr, Qs[3]);
assign T[3] = T[2] & Qs[3];
t_flipflop T4 (T[3], Clk, Clr, Qs[4]);
assign T[4] = T[3] & Qs[4];
t_flipflop T5 (T[4], Clk, Clr, Qs[5]);
assign T[5] = T[4] & Qs[5];
t_flipflop T6 (T[5], Clk, Clr, Qs[6]);
assign T[6] = T[5] & Qs[6];
t_flipflop T7 (T[6], Clk, Clr, Qs[7]);
assign T[7] = T[6] & Qs[7];
t_flipflop T8 (T[7], Clk, Clr, Qs[8]);
assign T[8] = T[7] & Qs[8];
t_flipflop T9 (T[8], Clk, Clr, Qs[9]);
assign T[9] = T[8] & Qs[9];
t_flipflop T10 (T[9], Clk, Clr, Qs[10]);
assign T[10] = T[9] & Qs[10];
t_flipflop T11 (T[10], Clk, Clr, Qs[11]);
assign T[11] = T[10] & Qs[11];
t_flipflop T12 (T[11], Clk, Clr, Qs[12]);
assign T[12] = T[11] & Qs[12];
t_flipflop T13 (T[12], Clk, Clr, Qs[13]);
assign T[13] = T[12] & Qs[13];
t_flipflop T14 (T[13], Clk, Clr, Qs[14]);
assign T[14] = T[13] & Qs[14];
t_flipflop T15 (T[14], Clk, Clr, Qs[15]);
assign T[15] = T[14] & Qs[15];
t_flipflop T16 (T[15], Clk, Clr, Qs[16]);
assign T[16] = T[15] & Qs[16];
t_flipflop T17 (T[16], Clk, Clr, Qs[17]);
assign T[17] = T[16] & Qs[17];
t_flipflop T18 (T[17], Clk, Clr, Qs[18]);
assign T[18] = T[17] & Qs[18];
t_flipflop T19 (T[18], Clk, Clr, Qs[19]);
assign T[19] = T[18] & Qs[19];
t_flipflop T20 (T[19], Clk, Clr, Qs[20]);
assign T[20] = T[19] & Qs[20];
t_flipflop T21 (T[20], Clk, Clr, Qs[21]);
assign T[21] = T[20] & Qs[21];
t_flipflop T22 (T[21], Clk, Clr, Qs[22]);
assign T[22] = T[21] & Qs[22];
t_flipflop T23 (T[22], Clk, Clr, Qs[23]);
assign T[23] = T[22] & Qs[23];
t_flipflop T24 (T[23], Clk, Clr, Qs[24]);
assign T[24] = T[23] & Qs[24];
t_flipflop T25 (T[24], Clk, Clr, Qs[25]);
assign T[25] = T[24] & Qs[25];
assign Q = Qs;
endmodule
|
(** * BasicTactics: Additional Basic Coq Tactics *)
Require Export Poly.
(** This chapter introduces several more proof strategies and
tactics that, together, allow us to prove theorems about the
functional programs we have been writing. In particular, we'll
reason about functions that work with natural numbers and
lists. We will see:
- how to use auxiliary lemmas, in both forwards and backwards reasoning;
- how to reason about data constructors, which are injective and disjoint;
- how to create a strong induction hypothesis (and when
strengthening is required); and
- how to reason by case analysis.
*)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros. rewrite H0. apply H.
Qed.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
(* FILL IN HERE *) Admitted.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* Hint: use the plus_n_Sm lemma *)
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
- (* n = O *) simpl. intros eq. destruct m as [| m'].
+ (* m = O *) reflexivity.
+ (* m = S m' *) inversion eq.
- (* n = S n' *) intros eq. destruct m as [| m'].
+ (* m = O *) inversion eq.
+ (* m = S m' *) apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _these particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
- (* n = O *) simpl. intros m eq. destruct m as [| m'].
+ (* m = O *) reflexivity.
+ (* m = S m' *) inversion eq.
- (* n = S n' *)
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
+ (* m = O *)
(* The 0 case is trivial *)
inversion eq.
+ (* m = S m' *)
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* FILL IN HERE *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
- (* m = O *) simpl. intros eq. destruct n as [| n'].
+ (* n = O *) reflexivity.
+ (* n = S n' *) inversion eq.
- (* m = S m' *) intros eq. destruct n as [| n'].
+ (* n = O *) inversion eq.
+ (* n = S n' *) apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
- (* m = O *) simpl. intros n eq. destruct n as [| n'].
+ (* n = O *) reflexivity.
+ (* n = S n' *) inversion eq.
- (* m = S m' *) intros n eq. destruct n as [| n'].
+ (* n = O *) inversion eq.
+ (* n = S n' *) apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
- (* l = [] *)
intros n eq. rewrite <- eq. reflexivity.
- (* l = v' :: l' *)
intros n eq. simpl. destruct n as [| n'].
+ (* n = 0 *) inversion eq.
+ (* n = S n' *)
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
- (* l = [] *)
rewrite <- eq. reflexivity.
- (* l = v' :: l' *)
simpl. destruct n as [| n'].
+ (* n = 0 *) inversion eq.
+ (* n = S n' *)
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]
from [Lists]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using [app_length] from [Lists]. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
intros P POO PmO POn Pmn m n.
induction m.
- induction n.
+ apply POO.
+ apply POn. apply IHn.
- induction n.
+ apply PmO. apply IHm.
+ apply Pmn. admit.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
- (* beq_nat n 3 = true *) reflexivity.
- (* beq_nat n 3 = false *) destruct (beq_nat n 5).
+ (* beq_nat n 5 = true *) reflexivity.
+ (* beq_nat n 5 = false *) reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
- (* e3 = true *) apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
- (* e3 = false *)
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
+ (* e5 = true *)
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
+ (* e5 = false *) inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]? When is this property true?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem split_combine : split_combine_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
intros X test x l lf.
induction l.
+ intros. unfold filter in H. inversion H.
+ intros.
destruct (test x0) eqn: testH.
- unfold filter in H. rewrite testH in H. fold (filter test) in H. inversion H. rewrite <- H1. apply testH.
- unfold filter in H. rewrite testH in H. fold (filter test) in H. apply IHl. apply H.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove theorem [existsb_existsb'] that [existsb'] and [existsb] have
the same behavior.
*)
Fixpoint forallb {X : Type} (p : X -> bool) (l : list X) :=
match l with
| [] => true
| x :: l' => if p x then forallb p l' else false
end.
Fixpoint existsb {X : Type} (p : X -> bool) (l : list X) :=
match l with
| [] => false
| x :: l' => if p x then true else existsb p l'
end.
Definition existsb' {X : Type} (p : X -> bool) (l : list X) :=
negb (forallb (fun x => negb (p x)) l).
Theorem existsb_existsb': forall (X : Type) (p : X -> bool)
(l : list X),
existsb p l = existsb' p l.
Proof.
intros.
induction l.
- simpl. unfold existsb'. unfold forallb. simpl. reflexivity.
- destruct (p x) eqn: Hpx.
+ simpl.
unfold existsb'. unfold forallb.
rewrite Hpx. simpl. reflexivity.
+ simpl. unfold existsb'. unfold forallb. rewrite Hpx.
simpl. fold (forallb (fun x0 : X => negb (p x0))).
unfold existsb' in IHl. rewrite IHl. reflexivity.
Qed.
(* FILL IN HERE *)
(** [] *)
(** $Date: 2015-08-11 03:46:09 +0200 (Tue, 11 Aug 2015) $ *)
|
//--------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementation and creation of design files
//-- limited to Xilinx devices or technologies. Use with non-Xilinx
//-- devices or technologies is expressly prohibited and immediately
//-- terminates your license.
//--
//-- Xilinx products are not intended for use in life support
//-- appliances, devices, or systems. Use in such applications is
//-- expressly prohibited.
//--
//-- **************************************
//-- ** Copyright (C) 2005, Xilinx, Inc. **
//-- ** All Rights Reserved. **
//-- **************************************
//--
//--------------------------------------------------------------------------------
//-- Filename: BMD.v
//--
//-- Description: Bus Master Device (BMD) Module
//--
//-- The module designed to operate with 32 bit and 64 bit interfaces.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module BMD #
(
parameter INTERFACE_WIDTH = 128,
parameter INTERFACE_TYPE = 4'b0010,
parameter FPGA_FAMILY = 8'h14
)
(
trn_clk,
trn_reset_n,
trn_lnk_up_n,
en,
bar0_addr_o,
bar0_wr_en_o,
bar0_wr_be_o,
bar0_busy_i,
bar0_rd_d_i,
bar0_rd_be_o,
bar0_wr_d_o,
bar1_wr_en1_i,
bar1_addr1_i,
bar1_be1_i,
bar1_wr_d1_i,
bar1_wr_ack1_n_o,
bar1_wr_en2_i,
bar1_addr2_i,
bar1_be2_i,
bar1_wr_d2_i,
bar1_wr_ack2_n_o,
bar1_wr_en3_i,
bar1_addr3_i,
bar1_be3_i,
bar1_wr_d3_i,
bar1_wr_ack3_n_o,
bar1_arbiter_busy_o,
bar1_wr_busy_o,
rdata_o,
rdata_rd_en_i,
rdata_fifo_empty_o,
tdata_i,
tdata_wr_en_i,
tdata_fifo_full_o,
mwr_start_o,
mwr_done_o,
mrd_start_o,
mrd_done_o,
req_compl_o,
compl_done_o,
cpld_malformed_o,
cpld_rcv_data_size_i,
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_tsrc_rdy_n,
trn_tsrc_dsc_n,
trn_tdst_rdy_n,
trn_tdst_dsc_n,
trn_tbuf_av,
trn_rd,
trn_rrem_n,
trn_rsof_n,
trn_reof_n,
trn_rsrc_rdy_n,
trn_rsrc_dsc_n,
trn_rdst_rdy_n,
trn_rbar_hit_n,
trn_rnp_ok_n,
trn_rcpl_streaming_n, //only for Block Plus
cfg_to_turnoff_n,
cfg_turnoff_ok_n,
cfg_interrupt_n,
cfg_interrupt_rdy_n,
cfg_interrupt_assert_n,
cfg_interrupt_di,
cfg_interrupt_do,
cfg_interrupt_mmenable,
cfg_interrupt_msienable,
cfg_neg_max_lnk_width,
cfg_neg_max_lnk_speed,
cfg_prg_max_payload_size,
cfg_max_rd_req_size,
cfg_rd_comp_bound,
cfg_phant_func_en,
cfg_phant_func_supported,
cfg_dwaddr,
cfg_rd_en_n,
cfg_do,
cfg_rd_wr_done_n,
trn_tstr_n, //only for V6/S6
`ifdef PCIE2_0
pl_directed_link_change,
pl_ltssm_state,
pl_directed_link_width,
pl_directed_link_speed,
pl_directed_link_auton,
pl_upstream_preemph_src,
pl_sel_link_width,
pl_sel_link_rate,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_initial_link_width,
pl_link_upcfg_capable,
pl_lane_reversal_mode,
`endif
cfg_completer_id,
cfg_ext_tag_en,
cfg_bus_mstr_enable,
/*************ouyang***************/
//response queue interface
response_queue_empty_i,
response_queue_data_i,
response_queue_rd_en_o ,//read enable signal for response queue
//msix interface
msg_lower_addr_i,
msg_upper_addr_i,
msg_data_i,
// the base addr for response queue
response_queue_addr_i,
//count enable for response queue offset
response_queue_addr_offset_cnt_en_o,
interrupt_block_i,
response_queue_cur_offset_reg_i,
response_queue_addr_offset_i
/**********************************/
); // synthesis syn_hier = "hard"
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
/*************ouyang***************/
//response queue interface
input response_queue_empty_i;
input [31:0] response_queue_data_i;
output response_queue_rd_en_o ;//read enable signal for response queue
//msix interface
input [31:0] msg_lower_addr_i;
input [31:0] msg_upper_addr_i;
input [31:0] msg_data_i;
// the base addr for response queue
input [31:0] response_queue_addr_i;
//count enable for response queue offset
output response_queue_addr_offset_cnt_en_o;
input interrupt_block_i;
input [31:0] response_queue_cur_offset_reg_i;
input [10:0] response_queue_addr_offset_i;
/**********************************/
input trn_clk;
input trn_reset_n;
input trn_lnk_up_n;
input en;
output [6:0] bar0_addr_o;
output bar0_wr_en_o;
output [7:0] bar0_wr_be_o;
input bar0_busy_i;
input [31:0] bar0_rd_d_i;
output [3:0] bar0_rd_be_o;
output [31:0] bar0_wr_d_o;
input bar1_wr_en1_i;
input [6:0] bar1_addr1_i;
input [3:0] bar1_be1_i;
input [31:0] bar1_wr_d1_i;
output bar1_wr_ack1_n_o;
input bar1_wr_en2_i;
input [6:0] bar1_addr2_i;
input [3:0] bar1_be2_i;
input [31:0] bar1_wr_d2_i;
output bar1_wr_ack2_n_o;
input bar1_wr_en3_i;
input [6:0] bar1_addr3_i;
input [3:0] bar1_be3_i;
input [31:0] bar1_wr_d3_i;
output bar1_wr_ack3_n_o;
output bar1_arbiter_busy_o;
output bar1_wr_busy_o;
output [127:0] rdata_o;
input rdata_rd_en_i;
output rdata_fifo_empty_o;
input [127:0] tdata_i;
input tdata_wr_en_i;
output tdata_fifo_full_o;
output mwr_start_o;
output mwr_done_o;
output mrd_start_o;
output mrd_done_o;
output req_compl_o;
output compl_done_o;
output cpld_malformed_o;
input [31:0] cpld_rcv_data_size_i;
output [INTERFACE_WIDTH-1:0] trn_td;
output [(INTERFACE_WIDTH/8)-1:0] trn_trem_n;
output trn_tsof_n;
output trn_teof_n;
output trn_tsrc_rdy_n;
output trn_tsrc_dsc_n;
input trn_tdst_rdy_n;
input trn_tdst_dsc_n;
input [5:0] trn_tbuf_av;
output trn_tstr_n;
input [INTERFACE_WIDTH-1:0] trn_rd;
input [(INTERFACE_WIDTH/8)-1:0] trn_rrem_n;
input trn_rsof_n;
input trn_reof_n;
input trn_rsrc_rdy_n;
input trn_rsrc_dsc_n;
output trn_rdst_rdy_n;
input [6:0] trn_rbar_hit_n;
output trn_rnp_ok_n;
output trn_rcpl_streaming_n;
input cfg_to_turnoff_n;
output cfg_turnoff_ok_n;
output cfg_interrupt_n;
input cfg_interrupt_rdy_n;
output cfg_interrupt_assert_n;
output [7:0] cfg_interrupt_di;
input [7:0] cfg_interrupt_do;
input [2:0] cfg_interrupt_mmenable;
input cfg_interrupt_msienable;
input [15:0] cfg_completer_id;
input cfg_ext_tag_en;
input cfg_bus_mstr_enable;
input [5:0] cfg_neg_max_lnk_width;
input [3:0] cfg_neg_max_lnk_speed;
input [2:0] cfg_prg_max_payload_size;
input [2:0] cfg_max_rd_req_size;
input cfg_rd_comp_bound;
input cfg_phant_func_en;
input [1:0] cfg_phant_func_supported;
output [9:0] cfg_dwaddr;
output cfg_rd_en_n;
input [31:0] cfg_do;
input cfg_rd_wr_done_n;
`ifdef PCIE2_0
output [1:0] pl_directed_link_change;
input [5:0] pl_ltssm_state;
output [1:0] pl_directed_link_width;
output pl_directed_link_speed;
output pl_directed_link_auton;
output pl_upstream_preemph_src;
input [1:0] pl_sel_link_width;
input pl_sel_link_rate;
input pl_link_gen2_capable;
input pl_link_partner_gen2_supported;
input [2:0] pl_initial_link_width;
input pl_link_upcfg_capable;
input [1:0] pl_lane_reversal_mode;
`endif
// Local wires
wire req_compl;
wire compl_done;
wire bmd_reset_n = trn_reset_n & ~trn_lnk_up_n;
wire [5:0] cfg_cap_max_lnk_width;
wire [3:0] cfg_cap_max_lnk_speed;
wire [2:0] cfg_cap_max_payload_size;
assign compl_done_o = compl_done;
assign req_compl_o = req_compl;
BMD_EP#
(
.INTERFACE_WIDTH(INTERFACE_WIDTH),
.INTERFACE_TYPE(INTERFACE_TYPE),
.FPGA_FAMILY(FPGA_FAMILY)
)
BMD_EP (
.clk ( trn_clk ), // I
.rst_n ( bmd_reset_n ), // I
.en( en ),
.bar0_addr_o( bar0_addr_o ),
.bar0_wr_en_o( bar0_wr_en_o ),
.bar0_wr_be_o( bar0_wr_be_o ),
.bar0_busy_i( bar0_busy_i ),
.bar0_rd_d_i( bar0_rd_d_i ),
.bar0_rd_be_o( bar0_rd_be_o ),
.bar0_wr_d_o( bar0_wr_d_o ),
.bar1_wr_en1_i( bar1_wr_en1_i ),
.bar1_addr1_i( bar1_addr1_i ),
.bar1_be1_i( bar1_be1_i ),
.bar1_wr_d1_i( bar1_wr_d1_i ),
.bar1_wr_ack1_n_o( bar1_wr_ack1_n_o ),
.bar1_wr_en2_i( bar1_wr_en2_i ),
.bar1_addr2_i( bar1_addr2_i ),
.bar1_be2_i( bar1_be2_i ),
.bar1_wr_d2_i( bar1_wr_d2_i ),
.bar1_wr_ack2_n_o( bar1_wr_ack2_n_o ),
.bar1_wr_en3_i( bar1_wr_en3_i ),
.bar1_addr3_i( bar1_addr3_i ),
.bar1_be3_i( bar1_be3_i ),
.bar1_wr_d3_i( bar1_wr_d3_i ),
.bar1_wr_ack3_n_o( bar1_wr_ack3_n_o ),
.bar1_arbiter_busy_o( bar1_arbiter_busy_o ),
.bar1_wr_busy_o( bar1_wr_busy_o ),
.rdata_o( rdata_o ),
.rdata_rd_en_i( rdata_rd_en_i ),
.rdata_fifo_empty_o( rdata_fifo_empty_o ),
.tdata_i( tdata_i ),
.tdata_wr_en_i( tdata_wr_en_i ),
.tdata_fifo_full_o( tdata_fifo_full_o ),
.mwr_start_o( mwr_start_o ),
.mwr_done_o( mwr_done_o ),
.mrd_start_o( mrd_start_o ),
.mrd_done_o( mrd_done_o ),
.cpld_malformed_o( cpld_malformed_o ),
.cpld_rcv_data_size_i(cpld_rcv_data_size_i),
.trn_td ( trn_td ), // O [63/31:0]
.trn_trem_n ( trn_trem_n ), // O [7:0]
.trn_tsof_n ( trn_tsof_n ), // O
.trn_teof_n ( trn_teof_n ), // O
.trn_tsrc_rdy_n ( trn_tsrc_rdy_n ), // O
.trn_tsrc_dsc_n ( trn_tsrc_dsc_n ), // O
.trn_tdst_rdy_n ( trn_tdst_rdy_n ), // I
.trn_tdst_dsc_n ( trn_tdst_dsc_n ), // I
.trn_tbuf_av ( trn_tbuf_av ), // I [5:0]
.trn_tstr_n ( trn_tstr_n ), // O
.trn_rd ( trn_rd ), // I [63/31:0]
.trn_rrem_n ( trn_rrem_n ), // I
.trn_rsof_n ( trn_rsof_n ), // I
.trn_reof_n ( trn_reof_n ), // I
.trn_rsrc_rdy_n ( trn_rsrc_rdy_n ), // I
.trn_rsrc_dsc_n ( trn_rsrc_dsc_n ), // I
.trn_rdst_rdy_n ( trn_rdst_rdy_n ), // O
.trn_rbar_hit_n (7'b1111110/* trn_rbar_hit_n */), // I [6:0]
.trn_rnp_ok_n ( trn_rnp_ok_n ), // O
.trn_rcpl_streaming_n( trn_rcpl_streaming_n ), // O
`ifdef PCIE2_0
.pl_directed_link_change( pl_directed_link_change ),
.pl_ltssm_state( pl_ltssm_state ),
.pl_directed_link_width( pl_directed_link_width ),
.pl_directed_link_speed( pl_directed_link_speed ),
.pl_directed_link_auton( pl_directed_link_auton ),
.pl_upstream_preemph_src( pl_upstream_preemph_src ),
.pl_sel_link_width( pl_sel_link_width ),
.pl_sel_link_rate( pl_sel_link_rate ),
.pl_link_gen2_capable( pl_link_gen2_capable ),
.pl_link_partner_gen2_supported( pl_link_partner_gen2_supported ),
.pl_initial_link_width( pl_initial_link_width ),
.pl_link_upcfg_capable( pl_link_upcfg_capable ),
.pl_lane_reversal_mode( pl_lane_reversal_mode ),
`endif
.req_compl_o(req_compl), // O
.compl_done_o(compl_done), // O
.cfg_interrupt_n(cfg_interrupt_n), // O
.cfg_interrupt_rdy_n(cfg_interrupt_rdy_n), // I
.cfg_interrupt_assert_n(cfg_interrupt_assert_n), // O
.cfg_interrupt_di ( cfg_interrupt_di ), // O
.cfg_interrupt_do ( cfg_interrupt_do ), // I
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ), // I
.cfg_interrupt_msienable ( cfg_interrupt_msienable ), // I
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_ext_tag_en ( cfg_ext_tag_en ), // I
.cfg_cap_max_lnk_width( cfg_cap_max_lnk_width ), // I [5:0]
.cfg_neg_max_lnk_width( cfg_neg_max_lnk_width ), // I [5:0]
.cfg_cap_max_lnk_speed(cfg_cap_max_lnk_speed),
.cfg_neg_max_lnk_speed(cfg_neg_max_lnk_speed),
.cfg_cap_max_payload_size( cfg_cap_max_payload_size ), // I [2:0]
.cfg_prg_max_payload_size( cfg_prg_max_payload_size ), // I [2:0]
.cfg_max_rd_req_size( cfg_max_rd_req_size ), // I [2:0]
.cfg_msi_enable(cfg_interrupt_msienable), // I
.cfg_rd_comp_bound( cfg_rd_comp_bound ), // I
.cfg_phant_func_en(cfg_phant_func_en), // I
.cfg_phant_func_supported(cfg_phant_func_supported), // I [1:0]
.cfg_bus_mstr_enable ( cfg_bus_mstr_enable ), // I
/*************ouyang***************/
//response queue interface
.response_queue_empty_i(response_queue_empty_i),
.response_queue_data_i(response_queue_data_i),
.response_queue_rd_en_o(response_queue_rd_en_o) ,//read enable signal for response queue
//msix interface
.msg_lower_addr_i(msg_lower_addr_i),
.msg_upper_addr_i(msg_upper_addr_i),
.msg_data_i(msg_data_i),
// the base addr for response queue
.response_queue_addr_i(response_queue_addr_i),
//count enable for response queue offset
.response_queue_addr_offset_cnt_en_o(response_queue_addr_offset_cnt_en_o),
.interrupt_block_i(interrupt_block_i),
.response_queue_cur_offset_reg_i(response_queue_cur_offset_reg_i),
.response_queue_addr_offset_i(response_queue_addr_offset_i)
/**********************************/
);
BMD_TO_CTRL BMD_TO (
.clk( trn_clk ), // I
.rst_n( bmd_reset_n ), // I
.req_compl_i( req_compl ), // I
.compl_done_i( compl_done ), // I
.cfg_to_turnoff_n( cfg_to_turnoff_n ), // I
.cfg_turnoff_ok_n( cfg_turnoff_ok_n ) // O
);
BMD_CFG_CTRL BMD_CF (
.clk( trn_clk ), // I
.rst_n( bmd_reset_n ), // I
.cfg_bus_mstr_enable( cfg_bus_mstr_enable ), // I
.cfg_dwaddr( cfg_dwaddr ), // O [9:0]
.cfg_rd_en_n( cfg_rd_en_n ), // O
.cfg_do( cfg_do ), // I [31:0]
.cfg_rd_wr_done_n( cfg_rd_wr_done_n ), // I
.cfg_cap_max_lnk_width( cfg_cap_max_lnk_width ), // O [5:0]
.cfg_cap_max_lnk_speed( cfg_cap_max_lnk_speed ),
.cfg_cap_max_payload_size( cfg_cap_max_payload_size ) // O [2:0]
// .cfg_msi_enable(cfg_msi_enable) // O
);
endmodule // BMD
|
// zhiyang ong
// andrew mattheisen
module mux(ina, inb, out, sel);
//INPUTS
input [0:127] ina, inb;
input sel;
// OUTPUTS
output [0:127] out;
// REGISTERS
reg [0:127] out;
always @ (ina or inb or sel)
begin
out<= sel ? ina : inb;
end // always @ (ina or inb or sel)
endmodule
`include control.h
`include mux.v
`include alu.v
`include reg
module cpu(Clk,
Reset,
Instruction, // 32 bit instruction
ProgramCounter, // 32 bit program counter
DataIn, // 128 bit data from dmem
DataOut, // 128 bit data to dmem
MemAddr, // 21 bit immediate address, only 8 bits are used
MemWrEn, // dmem write enable
MemEn // dmeme enable (to avoid spurious reads)
);
//INPUTS
input Clk, Reset;
input [0:31] Instruction, // 32 bit instruction
ProgramCounter; // 32 bit program counter
input [0:127] DataIn; // 128 bit data from dmem
//OUTPUTS
output
reg
DataOut, // 128 bit data to dmem
MemAddr, // 21 bit immediate address, only 8 bits are used
MemWrEn, // dmem write enable
MemEn // dmeme enable (to avoid spurious reads)
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S4_altera_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module RAMB16_S4_altera_new (
address,
clken,
clock,
data,
wren,
q);
input [7:0] address;
input clken;
input clock;
input [11:0] data;
input wren;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "lr_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "lr_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__BUFINV_FUNCTIONAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_FUNCTIONAL_PP_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_enable,
src_adc_valid,
src_adc_data,
dst_adc_enable,
dst_adc_valid,
dst_adc_data
);
localparam RP_ID = 8'hA0;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_enable;
input src_adc_valid;
input [15:0] src_adc_data;
output dst_adc_enable;
output dst_adc_valid;
output [15:0] dst_adc_data;
reg dst_adc_enable;
reg dst_adc_valid;
reg [15:0] dst_adc_data;
assign status = {24'h0, RP_ID};
always @(posedge clk) begin
dst_adc_enable <= src_adc_enable;
dst_adc_valid <= src_adc_valid;
dst_adc_data <= src_adc_data;
end
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : GTPE2_CHANNEL.uniprim.v
// \ \ / \
// \__\/\__ \
//
// 11/8/12 - 686589 - YML default changes
// 01/18/13 - 695630 - added drp monitor
// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK*
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTPE2_CHANNEL (
DMONITOROUT,
DRPDO,
DRPRDY,
EYESCANDATAERROR,
GTPTXN,
GTPTXP,
PCSRSVDOUT,
PHYSTATUS,
PMARSVDOUT0,
PMARSVDOUT1,
RXBUFSTATUS,
RXBYTEISALIGNED,
RXBYTEREALIGN,
RXCDRLOCK,
RXCHANBONDSEQ,
RXCHANISALIGNED,
RXCHANREALIGN,
RXCHARISCOMMA,
RXCHARISK,
RXCHBONDO,
RXCLKCORCNT,
RXCOMINITDET,
RXCOMMADET,
RXCOMSASDET,
RXCOMWAKEDET,
RXDATA,
RXDATAVALID,
RXDISPERR,
RXDLYSRESETDONE,
RXELECIDLE,
RXHEADER,
RXHEADERVALID,
RXNOTINTABLE,
RXOSINTDONE,
RXOSINTSTARTED,
RXOSINTSTROBEDONE,
RXOSINTSTROBESTARTED,
RXOUTCLK,
RXOUTCLKFABRIC,
RXOUTCLKPCS,
RXPHALIGNDONE,
RXPHMONITOR,
RXPHSLIPMONITOR,
RXPMARESETDONE,
RXPRBSERR,
RXRATEDONE,
RXRESETDONE,
RXSTARTOFSEQ,
RXSTATUS,
RXSYNCDONE,
RXSYNCOUT,
RXVALID,
TXBUFSTATUS,
TXCOMFINISH,
TXDLYSRESETDONE,
TXGEARBOXREADY,
TXOUTCLK,
TXOUTCLKFABRIC,
TXOUTCLKPCS,
TXPHALIGNDONE,
TXPHINITDONE,
TXPMARESETDONE,
TXRATEDONE,
TXRESETDONE,
TXSYNCDONE,
TXSYNCOUT,
CFGRESET,
CLKRSVD0,
CLKRSVD1,
DMONFIFORESET,
DMONITORCLK,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
EYESCANMODE,
EYESCANRESET,
EYESCANTRIGGER,
GTPRXN,
GTPRXP,
GTRESETSEL,
GTRSVD,
GTRXRESET,
GTTXRESET,
LOOPBACK,
PCSRSVDIN,
PLL0CLK,
PLL0REFCLK,
PLL1CLK,
PLL1REFCLK,
PMARSVDIN0,
PMARSVDIN1,
PMARSVDIN2,
PMARSVDIN3,
PMARSVDIN4,
RESETOVRD,
RX8B10BEN,
RXADAPTSELTEST,
RXBUFRESET,
RXCDRFREQRESET,
RXCDRHOLD,
RXCDROVRDEN,
RXCDRRESET,
RXCDRRESETRSV,
RXCHBONDEN,
RXCHBONDI,
RXCHBONDLEVEL,
RXCHBONDMASTER,
RXCHBONDSLAVE,
RXCOMMADETEN,
RXDDIEN,
RXDFEXYDEN,
RXDLYBYPASS,
RXDLYEN,
RXDLYOVRDEN,
RXDLYSRESET,
RXELECIDLEMODE,
RXGEARBOXSLIP,
RXLPMHFHOLD,
RXLPMHFOVRDEN,
RXLPMLFHOLD,
RXLPMLFOVRDEN,
RXLPMOSINTNTRLEN,
RXLPMRESET,
RXMCOMMAALIGNEN,
RXOOBRESET,
RXOSCALRESET,
RXOSHOLD,
RXOSINTCFG,
RXOSINTEN,
RXOSINTHOLD,
RXOSINTID0,
RXOSINTNTRLEN,
RXOSINTOVRDEN,
RXOSINTPD,
RXOSINTSTROBE,
RXOSINTTESTOVRDEN,
RXOSOVRDEN,
RXOUTCLKSEL,
RXPCOMMAALIGNEN,
RXPCSRESET,
RXPD,
RXPHALIGN,
RXPHALIGNEN,
RXPHDLYPD,
RXPHDLYRESET,
RXPHOVRDEN,
RXPMARESET,
RXPOLARITY,
RXPRBSCNTRESET,
RXPRBSSEL,
RXRATE,
RXRATEMODE,
RXSLIDE,
RXSYNCALLIN,
RXSYNCIN,
RXSYNCMODE,
RXSYSCLKSEL,
RXUSERRDY,
RXUSRCLK,
RXUSRCLK2,
SETERRSTATUS,
SIGVALIDCLK,
TSTIN,
TX8B10BBYPASS,
TX8B10BEN,
TXBUFDIFFCTRL,
TXCHARDISPMODE,
TXCHARDISPVAL,
TXCHARISK,
TXCOMINIT,
TXCOMSAS,
TXCOMWAKE,
TXDATA,
TXDEEMPH,
TXDETECTRX,
TXDIFFCTRL,
TXDIFFPD,
TXDLYBYPASS,
TXDLYEN,
TXDLYHOLD,
TXDLYOVRDEN,
TXDLYSRESET,
TXDLYUPDOWN,
TXELECIDLE,
TXHEADER,
TXINHIBIT,
TXMAINCURSOR,
TXMARGIN,
TXOUTCLKSEL,
TXPCSRESET,
TXPD,
TXPDELECIDLEMODE,
TXPHALIGN,
TXPHALIGNEN,
TXPHDLYPD,
TXPHDLYRESET,
TXPHDLYTSTCLK,
TXPHINIT,
TXPHOVRDEN,
TXPIPPMEN,
TXPIPPMOVRDEN,
TXPIPPMPD,
TXPIPPMSEL,
TXPIPPMSTEPSIZE,
TXPISOPD,
TXPMARESET,
TXPOLARITY,
TXPOSTCURSOR,
TXPOSTCURSORINV,
TXPRBSFORCEERR,
TXPRBSSEL,
TXPRECURSOR,
TXPRECURSORINV,
TXRATE,
TXRATEMODE,
TXSEQUENCE,
TXSTARTSEQ,
TXSWING,
TXSYNCALLIN,
TXSYNCIN,
TXSYNCMODE,
TXSYSCLKSEL,
TXUSERRDY,
TXUSRCLK,
TXUSRCLK2
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
parameter [0:0] ACJTAG_MODE = 1'b0;
parameter [0:0] ACJTAG_RESET = 1'b0;
parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
parameter integer ALIGN_COMMA_WORD = 1;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000;
parameter [6:0] CFOK_CFG2 = 7'b0100000;
parameter [6:0] CFOK_CFG3 = 7'b0100000;
parameter [0:0] CFOK_CFG4 = 1'b0;
parameter [1:0] CFOK_CFG5 = 2'b00;
parameter [3:0] CFOK_CFG6 = 4'b0000;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter integer CHAN_BOND_MAX_SKEW = 7;
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter [0:0] CLK_COMMON_SWING = 1'b0;
parameter CLK_CORRECT_USE = "TRUE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 20;
parameter integer CLK_COR_MIN_LAT = 18;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter integer CLK_COR_REPEAT_WAIT = 0;
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter [23:0] DMONITOR_CFG = 24'h000A00;
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
parameter [5:0] ES_CONTROL = 6'b000000;
parameter ES_ERRDET_EN = "FALSE";
parameter ES_EYE_SCAN_EN = "FALSE";
parameter [11:0] ES_HORZ_OFFSET = 12'h010;
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
parameter [4:0] ES_PRESCALE = 5'b00000;
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter [2:0] GEARBOX_MODE = 3'b000;
parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
parameter [0:0] LOOPBACK_CFG = 1'b0;
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
parameter PCS_PCIE_EN = "FALSE";
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
parameter [0:0] PMA_LOOPBACK_CFG = 1'b0;
parameter [31:0] PMA_RSV = 32'h00000333;
parameter [31:0] PMA_RSV2 = 32'h00002050;
parameter [1:0] PMA_RSV3 = 2'b00;
parameter [3:0] PMA_RSV4 = 4'b0000;
parameter [0:0] PMA_RSV5 = 1'b0;
parameter [0:0] PMA_RSV6 = 1'b0;
parameter [0:0] PMA_RSV7 = 1'b0;
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
parameter RXBUF_ADDR_MODE = "FULL";
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
parameter RXBUF_EN = "TRUE";
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter integer RXBUF_THRESH_OVFLW = 61;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter integer RXBUF_THRESH_UNDFLW = 4;
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010;
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
parameter [15:0] RXDLY_CFG = 16'h0010;
parameter [8:0] RXDLY_LCFG = 9'h020;
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
parameter RXGEARBOX_EN = "FALSE";
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
parameter [6:0] RXLPMRESET_TIME = 7'b0001111;
parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0;
parameter [3:0] RXLPM_CFG = 4'b0110;
parameter [0:0] RXLPM_CFG1 = 1'b0;
parameter [0:0] RXLPM_CM_CFG = 1'b0;
parameter [8:0] RXLPM_GC_CFG = 9'b111100010;
parameter [2:0] RXLPM_GC_CFG2 = 3'b001;
parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000;
parameter [4:0] RXLPM_HF_CFG2 = 5'b01010;
parameter [3:0] RXLPM_HF_CFG3 = 4'b0000;
parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0;
parameter [0:0] RXLPM_INCM_CFG = 1'b0;
parameter [0:0] RXLPM_IPCM_CFG = 1'b0;
parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000;
parameter [4:0] RXLPM_LF_CFG2 = 5'b01010;
parameter [2:0] RXLPM_OSINT_CFG = 3'b100;
parameter [6:0] RXOOB_CFG = 7'b0000110;
parameter RXOOB_CLK_CFG = "PMA";
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
parameter integer RXOUT_DIV = 2;
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
parameter [23:0] RXPHDLY_CFG = 24'h084000;
parameter [23:0] RXPH_CFG = 24'hC00002;
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
parameter [2:0] RXPI_CFG0 = 3'b000;
parameter [0:0] RXPI_CFG1 = 1'b0;
parameter [0:0] RXPI_CFG2 = 1'b0;
parameter [4:0] RXPMARESET_TIME = 5'b00011;
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
parameter integer RXSLIDE_AUTO_WAIT = 7;
parameter RXSLIDE_MODE = "OFF";
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
parameter [0:0] RXSYNC_OVRD = 1'b0;
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011;
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
parameter integer RX_CLK25_DIV = 7;
parameter [0:0] RX_CLKMUX_EN = 1'b1;
parameter [1:0] RX_CM_SEL = 2'b11;
parameter [3:0] RX_CM_TRIM = 4'b0100;
parameter integer RX_DATA_WIDTH = 20;
parameter [5:0] RX_DDI_SEL = 6'b000000;
parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter [12:0] RX_OS_CFG = 13'b0001111110000;
parameter integer RX_SIG_VALID_DLY = 10;
parameter RX_XCLK_SEL = "RXREC";
parameter integer SAS_MAX_COM = 64;
parameter integer SAS_MIN_COM = 36;
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter [2:0] SATA_BURST_VAL = 3'b100;
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
parameter integer SATA_MAX_BURST = 8;
parameter integer SATA_MAX_INIT = 21;
parameter integer SATA_MAX_WAKE = 7;
parameter integer SATA_MIN_BURST = 4;
parameter integer SATA_MIN_INIT = 12;
parameter integer SATA_MIN_WAKE = 4;
parameter SATA_PLL_CFG = "VCO_3000MHZ";
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
parameter [31:0] TST_RSV = 32'h00000000;
parameter TXBUF_EN = "TRUE";
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
parameter [15:0] TXDLY_CFG = 16'h0010;
parameter [8:0] TXDLY_LCFG = 9'h020;
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
parameter TXGEARBOX_EN = "FALSE";
parameter [0:0] TXOOB_CFG = 1'b0;
parameter integer TXOUT_DIV = 2;
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
parameter [23:0] TXPHDLY_CFG = 24'h084000;
parameter [15:0] TXPH_CFG = 16'h0400;
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
parameter [1:0] TXPI_CFG0 = 2'b00;
parameter [1:0] TXPI_CFG1 = 2'b00;
parameter [1:0] TXPI_CFG2 = 2'b00;
parameter [0:0] TXPI_CFG3 = 1'b0;
parameter [0:0] TXPI_CFG4 = 1'b0;
parameter [2:0] TXPI_CFG5 = 3'b000;
parameter [0:0] TXPI_GREY_SEL = 1'b0;
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
parameter [4:0] TXPMARESET_TIME = 5'b00001;
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
parameter [0:0] TXSYNC_OVRD = 1'b0;
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
parameter integer TX_CLK25_DIV = 7;
parameter [0:0] TX_CLKMUX_EN = 1'b1;
parameter integer TX_DATA_WIDTH = 20;
parameter [5:0] TX_DEEMPH0 = 6'b000000;
parameter [5:0] TX_DEEMPH1 = 6'b000000;
parameter TX_DRIVE_MODE = "DIRECT";
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
parameter [2:0] TX_RXDETECT_REF = 3'b100;
parameter TX_XCLK_SEL = "TXUSR";
parameter [0:0] UCODEER_CLR = 1'b0;
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output DRPRDY;
output EYESCANDATAERROR;
output GTPTXN;
output GTPTXP;
output PHYSTATUS;
output PMARSVDOUT0;
output PMARSVDOUT1;
output RXBYTEISALIGNED;
output RXBYTEREALIGN;
output RXCDRLOCK;
output RXCHANBONDSEQ;
output RXCHANISALIGNED;
output RXCHANREALIGN;
output RXCOMINITDET;
output RXCOMMADET;
output RXCOMSASDET;
output RXCOMWAKEDET;
output RXDLYSRESETDONE;
output RXELECIDLE;
output RXHEADERVALID;
output RXOSINTDONE;
output RXOSINTSTARTED;
output RXOSINTSTROBEDONE;
output RXOSINTSTROBESTARTED;
output RXOUTCLK;
output RXOUTCLKFABRIC;
output RXOUTCLKPCS;
output RXPHALIGNDONE;
output RXPMARESETDONE;
output RXPRBSERR;
output RXRATEDONE;
output RXRESETDONE;
output RXSYNCDONE;
output RXSYNCOUT;
output RXVALID;
output TXCOMFINISH;
output TXDLYSRESETDONE;
output TXGEARBOXREADY;
output TXOUTCLK;
output TXOUTCLKFABRIC;
output TXOUTCLKPCS;
output TXPHALIGNDONE;
output TXPHINITDONE;
output TXPMARESETDONE;
output TXRATEDONE;
output TXRESETDONE;
output TXSYNCDONE;
output TXSYNCOUT;
output [14:0] DMONITOROUT;
output [15:0] DRPDO;
output [15:0] PCSRSVDOUT;
output [1:0] RXCLKCORCNT;
output [1:0] RXDATAVALID;
output [1:0] RXSTARTOFSEQ;
output [1:0] TXBUFSTATUS;
output [2:0] RXBUFSTATUS;
output [2:0] RXHEADER;
output [2:0] RXSTATUS;
output [31:0] RXDATA;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [3:0] RXCHBONDO;
output [3:0] RXDISPERR;
output [3:0] RXNOTINTABLE;
output [4:0] RXPHMONITOR;
output [4:0] RXPHSLIPMONITOR;
input CFGRESET;
input CLKRSVD0;
input CLKRSVD1;
input DMONFIFORESET;
input DMONITORCLK;
input DRPCLK;
input DRPEN;
input DRPWE;
input EYESCANMODE;
input EYESCANRESET;
input EYESCANTRIGGER;
input GTPRXN;
input GTPRXP;
input GTRESETSEL;
input GTRXRESET;
input GTTXRESET;
input PLL0CLK;
input PLL0REFCLK;
input PLL1CLK;
input PLL1REFCLK;
input PMARSVDIN0;
input PMARSVDIN1;
input PMARSVDIN2;
input PMARSVDIN3;
input PMARSVDIN4;
input RESETOVRD;
input RX8B10BEN;
input RXBUFRESET;
input RXCDRFREQRESET;
input RXCDRHOLD;
input RXCDROVRDEN;
input RXCDRRESET;
input RXCDRRESETRSV;
input RXCHBONDEN;
input RXCHBONDMASTER;
input RXCHBONDSLAVE;
input RXCOMMADETEN;
input RXDDIEN;
input RXDFEXYDEN;
input RXDLYBYPASS;
input RXDLYEN;
input RXDLYOVRDEN;
input RXDLYSRESET;
input RXGEARBOXSLIP;
input RXLPMHFHOLD;
input RXLPMHFOVRDEN;
input RXLPMLFHOLD;
input RXLPMLFOVRDEN;
input RXLPMOSINTNTRLEN;
input RXLPMRESET;
input RXMCOMMAALIGNEN;
input RXOOBRESET;
input RXOSCALRESET;
input RXOSHOLD;
input RXOSINTEN;
input RXOSINTHOLD;
input RXOSINTNTRLEN;
input RXOSINTOVRDEN;
input RXOSINTPD;
input RXOSINTSTROBE;
input RXOSINTTESTOVRDEN;
input RXOSOVRDEN;
input RXPCOMMAALIGNEN;
input RXPCSRESET;
input RXPHALIGN;
input RXPHALIGNEN;
input RXPHDLYPD;
input RXPHDLYRESET;
input RXPHOVRDEN;
input RXPMARESET;
input RXPOLARITY;
input RXPRBSCNTRESET;
input RXRATEMODE;
input RXSLIDE;
input RXSYNCALLIN;
input RXSYNCIN;
input RXSYNCMODE;
input RXUSERRDY;
input RXUSRCLK2;
input RXUSRCLK;
input SETERRSTATUS;
input SIGVALIDCLK;
input TX8B10BEN;
input TXCOMINIT;
input TXCOMSAS;
input TXCOMWAKE;
input TXDEEMPH;
input TXDETECTRX;
input TXDIFFPD;
input TXDLYBYPASS;
input TXDLYEN;
input TXDLYHOLD;
input TXDLYOVRDEN;
input TXDLYSRESET;
input TXDLYUPDOWN;
input TXELECIDLE;
input TXINHIBIT;
input TXPCSRESET;
input TXPDELECIDLEMODE;
input TXPHALIGN;
input TXPHALIGNEN;
input TXPHDLYPD;
input TXPHDLYRESET;
input TXPHDLYTSTCLK;
input TXPHINIT;
input TXPHOVRDEN;
input TXPIPPMEN;
input TXPIPPMOVRDEN;
input TXPIPPMPD;
input TXPIPPMSEL;
input TXPISOPD;
input TXPMARESET;
input TXPOLARITY;
input TXPOSTCURSORINV;
input TXPRBSFORCEERR;
input TXPRECURSORINV;
input TXRATEMODE;
input TXSTARTSEQ;
input TXSWING;
input TXSYNCALLIN;
input TXSYNCIN;
input TXSYNCMODE;
input TXUSERRDY;
input TXUSRCLK2;
input TXUSRCLK;
input [13:0] RXADAPTSELTEST;
input [15:0] DRPDI;
input [15:0] GTRSVD;
input [15:0] PCSRSVDIN;
input [19:0] TSTIN;
input [1:0] RXELECIDLEMODE;
input [1:0] RXPD;
input [1:0] RXSYSCLKSEL;
input [1:0] TXPD;
input [1:0] TXSYSCLKSEL;
input [2:0] LOOPBACK;
input [2:0] RXCHBONDLEVEL;
input [2:0] RXOUTCLKSEL;
input [2:0] RXPRBSSEL;
input [2:0] RXRATE;
input [2:0] TXBUFDIFFCTRL;
input [2:0] TXHEADER;
input [2:0] TXMARGIN;
input [2:0] TXOUTCLKSEL;
input [2:0] TXPRBSSEL;
input [2:0] TXRATE;
input [31:0] TXDATA;
input [3:0] RXCHBONDI;
input [3:0] RXOSINTCFG;
input [3:0] RXOSINTID0;
input [3:0] TX8B10BBYPASS;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [3:0] TXDIFFCTRL;
input [4:0] TXPIPPMSTEPSIZE;
input [4:0] TXPOSTCURSOR;
input [4:0] TXPRECURSOR;
input [6:0] TXMAINCURSOR;
input [6:0] TXSEQUENCE;
input [8:0] DRPADDR;
reg SIM_RECEIVER_DETECT_PASS_BINARY;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_TX_EIDLE_DRIVE_LEVEL_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] ACJTAG_DEBUG_MODE_BINARY;
reg [0:0] ACJTAG_MODE_BINARY;
reg [0:0] ACJTAG_RESET_BINARY;
reg [0:0] ALIGN_COMMA_DOUBLE_BINARY;
reg [0:0] ALIGN_MCOMMA_DET_BINARY;
reg [0:0] ALIGN_PCOMMA_DET_BINARY;
reg [0:0] CBCC_DATA_SOURCE_SEL_BINARY;
reg [0:0] CFOK_CFG4_BINARY;
reg [0:0] CHAN_BOND_KEEP_ALIGN_BINARY;
reg [0:0] CHAN_BOND_SEQ_2_USE_BINARY;
reg [0:0] CLK_COMMON_SWING_BINARY;
reg [0:0] CLK_CORRECT_USE_BINARY;
reg [0:0] CLK_COR_KEEP_IDLE_BINARY;
reg [0:0] CLK_COR_PRECEDENCE_BINARY;
reg [0:0] CLK_COR_SEQ_2_USE_BINARY;
reg [0:0] DEC_MCOMMA_DETECT_BINARY;
reg [0:0] DEC_PCOMMA_DETECT_BINARY;
reg [0:0] DEC_VALID_COMMA_ONLY_BINARY;
reg [0:0] ES_CLK_PHASE_SEL_BINARY;
reg [0:0] ES_ERRDET_EN_BINARY;
reg [0:0] ES_EYE_SCAN_EN_BINARY;
reg [0:0] FTS_LANE_DESKEW_EN_BINARY;
reg [0:0] LOOPBACK_CFG_BINARY;
reg [0:0] PCS_PCIE_EN_BINARY;
reg [0:0] PMA_LOOPBACK_CFG_BINARY;
reg [0:0] PMA_RSV5_BINARY;
reg [0:0] PMA_RSV6_BINARY;
reg [0:0] PMA_RSV7_BINARY;
reg [0:0] RXBUF_ADDR_MODE_BINARY;
reg [0:0] RXBUF_EN_BINARY;
reg [0:0] RXBUF_RESET_ON_CB_CHANGE_BINARY;
reg [0:0] RXBUF_RESET_ON_COMMAALIGN_BINARY;
reg [0:0] RXBUF_RESET_ON_EIDLE_BINARY;
reg [0:0] RXBUF_RESET_ON_RATE_CHANGE_BINARY;
reg [0:0] RXBUF_THRESH_OVRD_BINARY;
reg [0:0] RXCDR_FR_RESET_ON_EIDLE_BINARY;
reg [0:0] RXCDR_HOLD_DURING_EIDLE_BINARY;
reg [0:0] RXCDR_PH_RESET_ON_EIDLE_BINARY;
reg [0:0] RXGEARBOX_EN_BINARY;
reg [0:0] RXLPM_BIAS_STARTUP_DISABLE_BINARY;
reg [0:0] RXLPM_CFG1_BINARY;
reg [0:0] RXLPM_CM_CFG_BINARY;
reg [0:0] RXLPM_HOLD_DURING_EIDLE_BINARY;
reg [0:0] RXLPM_INCM_CFG_BINARY;
reg [0:0] RXLPM_IPCM_CFG_BINARY;
reg [0:0] RXOOB_CLK_CFG_BINARY;
reg [0:0] RXPI_CFG1_BINARY;
reg [0:0] RXPI_CFG2_BINARY;
reg [0:0] RXPRBS_ERR_LOOPBACK_BINARY;
reg [0:0] RXSYNC_MULTILANE_BINARY;
reg [0:0] RXSYNC_OVRD_BINARY;
reg [0:0] RXSYNC_SKIP_DA_BINARY;
reg [0:0] RX_CLKMUX_EN_BINARY;
reg [0:0] RX_DEFER_RESET_BUF_EN_BINARY;
reg [0:0] RX_DISPERR_SEQ_MATCH_BINARY;
reg [0:0] RX_XCLK_SEL_BINARY;
reg [0:0] SHOW_REALIGN_COMMA_BINARY;
reg [0:0] TXBUF_EN_BINARY;
reg [0:0] TXBUF_RESET_ON_RATE_CHANGE_BINARY;
reg [0:0] TXGEARBOX_EN_BINARY;
reg [0:0] TXOOB_CFG_BINARY;
reg [0:0] TXPI_CFG3_BINARY;
reg [0:0] TXPI_CFG4_BINARY;
reg [0:0] TXPI_GREY_SEL_BINARY;
reg [0:0] TXPI_INVSTROBE_SEL_BINARY;
reg [0:0] TXPI_PPMCLK_SEL_BINARY;
reg [0:0] TXSYNC_MULTILANE_BINARY;
reg [0:0] TXSYNC_OVRD_BINARY;
reg [0:0] TXSYNC_SKIP_DA_BINARY;
reg [0:0] TX_CLKMUX_EN_BINARY;
reg [0:0] TX_LOOPBACK_DRIVE_HIZ_BINARY;
reg [0:0] TX_MAINCURSOR_SEL_BINARY;
reg [0:0] TX_PREDRIVER_MODE_BINARY;
reg [0:0] TX_XCLK_SEL_BINARY;
reg [0:0] UCODEER_CLR_BINARY;
reg [0:0] USE_PCS_CLK_PHASE_SEL_BINARY;
reg [12:0] RX_OS_CFG_BINARY;
reg [13:0] RXLPM_HF_CFG_BINARY;
reg [13:0] RX_DEBUG_CFG_BINARY;
reg [14:0] TERM_RCAL_CFG_BINARY;
reg [15:0] RX_BIAS_CFG_BINARY;
reg [17:0] RXLPM_LF_CFG_BINARY;
reg [19:0] ADAPT_CFG0_BINARY;
reg [1:0] ALIGN_COMMA_WORD_BINARY;
reg [1:0] CFOK_CFG5_BINARY;
reg [1:0] CHAN_BOND_SEQ_LEN_BINARY;
reg [1:0] CLK_COR_SEQ_LEN_BINARY;
reg [1:0] OUTREFCLK_SEL_INV_BINARY;
reg [1:0] PMA_RSV3_BINARY;
reg [1:0] RXSLIDE_MODE_BINARY;
reg [1:0] RX_CM_SEL_BINARY;
reg [1:0] SATA_PLL_CFG_BINARY;
reg [1:0] TXPI_CFG0_BINARY;
reg [1:0] TXPI_CFG1_BINARY;
reg [1:0] TXPI_CFG2_BINARY;
reg [2:0] GEARBOX_MODE_BINARY;
reg [2:0] RXLPM_GC_CFG2_BINARY;
reg [2:0] RXLPM_OSINT_CFG_BINARY;
reg [2:0] RXOUT_DIV_BINARY;
reg [2:0] RXPI_CFG0_BINARY;
reg [2:0] RX_DATA_WIDTH_BINARY;
reg [2:0] SATA_BURST_VAL_BINARY;
reg [2:0] SATA_EIDLE_VAL_BINARY;
reg [2:0] TERM_RCAL_OVRD_BINARY;
reg [2:0] TXOUT_DIV_BINARY;
reg [2:0] TXPI_CFG5_BINARY;
reg [2:0] TXPI_SYNFREQ_PPM_BINARY;
reg [2:0] TX_DATA_WIDTH_BINARY;
reg [2:0] TX_EIDLE_ASSERT_DELAY_BINARY;
reg [2:0] TX_EIDLE_DEASSERT_DELAY_BINARY;
reg [2:0] TX_RXDETECT_REF_BINARY;
reg [3:0] CFOK_CFG6_BINARY;
reg [3:0] CHAN_BOND_MAX_SKEW_BINARY;
reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY;
reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY;
reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY;
reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY;
reg [3:0] FTS_DESKEW_SEQ_ENABLE_BINARY;
reg [3:0] FTS_LANE_DESKEW_CFG_BINARY;
reg [3:0] PMA_RSV4_BINARY;
reg [3:0] RXBUF_EIDLE_HI_CNT_BINARY;
reg [3:0] RXBUF_EIDLE_LO_CNT_BINARY;
reg [3:0] RXLPM_CFG_BINARY;
reg [3:0] RXLPM_HF_CFG3_BINARY;
reg [3:0] RXSLIDE_AUTO_WAIT_BINARY;
reg [3:0] RX_CM_TRIM_BINARY;
reg [3:0] SATA_BURST_SEQ_LEN_BINARY;
reg [42:0] CFOK_CFG_BINARY;
reg [4:0] CLK_COR_REPEAT_WAIT_BINARY;
reg [4:0] ES_PRESCALE_BINARY;
reg [4:0] RXBUFRESET_TIME_BINARY;
reg [4:0] RXCDRFREQRESET_TIME_BINARY;
reg [4:0] RXCDRPHRESET_TIME_BINARY;
reg [4:0] RXISCANRESET_TIME_BINARY;
reg [4:0] RXLPM_HF_CFG2_BINARY;
reg [4:0] RXLPM_LF_CFG2_BINARY;
reg [4:0] RXOSCALRESET_TIMEOUT_BINARY;
reg [4:0] RXOSCALRESET_TIME_BINARY;
reg [4:0] RXPCSRESET_TIME_BINARY;
reg [4:0] RXPH_MONITOR_SEL_BINARY;
reg [4:0] RXPMARESET_TIME_BINARY;
reg [4:0] RX_CLK25_DIV_BINARY;
reg [4:0] RX_SIG_VALID_DLY_BINARY;
reg [4:0] TXPCSRESET_TIME_BINARY;
reg [4:0] TXPH_MONITOR_SEL_BINARY;
reg [4:0] TXPMARESET_TIME_BINARY;
reg [4:0] TX_CLK25_DIV_BINARY;
reg [4:0] TX_DRIVE_MODE_BINARY;
reg [5:0] CLK_COR_MAX_LAT_BINARY;
reg [5:0] CLK_COR_MIN_LAT_BINARY;
reg [5:0] ES_CONTROL_BINARY;
reg [5:0] RXBUF_THRESH_OVFLW_BINARY;
reg [5:0] RXBUF_THRESH_UNDFLW_BINARY;
reg [5:0] RXCDR_LOCK_CFG_BINARY;
reg [5:0] RX_BUFFER_CFG_BINARY;
reg [5:0] RX_DDI_SEL_BINARY;
reg [5:0] SAS_MIN_COM_BINARY;
reg [5:0] SATA_MAX_BURST_BINARY;
reg [5:0] SATA_MAX_INIT_BINARY;
reg [5:0] SATA_MAX_WAKE_BINARY;
reg [5:0] SATA_MIN_BURST_BINARY;
reg [5:0] SATA_MIN_INIT_BINARY;
reg [5:0] SATA_MIN_WAKE_BINARY;
reg [5:0] TX_DEEMPH0_BINARY;
reg [5:0] TX_DEEMPH1_BINARY;
reg [6:0] CFOK_CFG2_BINARY;
reg [6:0] CFOK_CFG3_BINARY;
reg [6:0] RXLPMRESET_TIME_BINARY;
reg [6:0] RXOOB_CFG_BINARY;
reg [6:0] SAS_MAX_COM_BINARY;
reg [6:0] TX_MARGIN_FULL_0_BINARY;
reg [6:0] TX_MARGIN_FULL_1_BINARY;
reg [6:0] TX_MARGIN_FULL_2_BINARY;
reg [6:0] TX_MARGIN_FULL_3_BINARY;
reg [6:0] TX_MARGIN_FULL_4_BINARY;
reg [6:0] TX_MARGIN_LOW_0_BINARY;
reg [6:0] TX_MARGIN_LOW_1_BINARY;
reg [6:0] TX_MARGIN_LOW_2_BINARY;
reg [6:0] TX_MARGIN_LOW_3_BINARY;
reg [6:0] TX_MARGIN_LOW_4_BINARY;
reg [7:0] TXPI_PPM_CFG_BINARY;
reg [8:0] ES_VERT_OFFSET_BINARY;
reg [8:0] RXLPM_GC_CFG_BINARY;
reg [9:0] ALIGN_COMMA_ENABLE_BINARY;
reg [9:0] ALIGN_MCOMMA_VALUE_BINARY;
reg [9:0] ALIGN_PCOMMA_VALUE_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_1_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_2_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_3_BINARY;
reg [9:0] CHAN_BOND_SEQ_1_4_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_1_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_2_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_3_BINARY;
reg [9:0] CHAN_BOND_SEQ_2_4_BINARY;
reg [9:0] CLK_COR_SEQ_1_1_BINARY;
reg [9:0] CLK_COR_SEQ_1_2_BINARY;
reg [9:0] CLK_COR_SEQ_1_3_BINARY;
reg [9:0] CLK_COR_SEQ_1_4_BINARY;
reg [9:0] CLK_COR_SEQ_2_1_BINARY;
reg [9:0] CLK_COR_SEQ_2_2_BINARY;
reg [9:0] CLK_COR_SEQ_2_3_BINARY;
reg [9:0] CLK_COR_SEQ_2_4_BINARY;
reg [9:0] ES_PMA_CFG_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (ALIGN_COMMA_DOUBLE)
"FALSE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b0;
"TRUE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_DOUBLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALIGN_COMMA_DOUBLE);
#1 $finish;
end
endcase
case (ALIGN_MCOMMA_DET)
"TRUE" : ALIGN_MCOMMA_DET_BINARY = 1'b1;
"FALSE" : ALIGN_MCOMMA_DET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_DET on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_MCOMMA_DET);
#1 $finish;
end
endcase
case (ALIGN_PCOMMA_DET)
"TRUE" : ALIGN_PCOMMA_DET_BINARY = 1'b1;
"FALSE" : ALIGN_PCOMMA_DET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_DET on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_PCOMMA_DET);
#1 $finish;
end
endcase
case (CBCC_DATA_SOURCE_SEL)
"DECODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b1;
"ENCODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CBCC_DATA_SOURCE_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DECODED, or ENCODED.", CBCC_DATA_SOURCE_SEL);
#1 $finish;
end
endcase
case (CHAN_BOND_KEEP_ALIGN)
"FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0;
"TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_KEEP_ALIGN);
#1 $finish;
end
endcase
case (CHAN_BOND_SEQ_2_USE)
"FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0;
"TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_SEQ_2_USE);
#1 $finish;
end
endcase
case (CHAN_BOND_SEQ_LEN)
1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00;
2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01;
3 : CHAN_BOND_SEQ_LEN_BINARY = 2'b10;
4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1);
#1 $finish;
end
endcase
case (CLK_CORRECT_USE)
"TRUE" : CLK_CORRECT_USE_BINARY = 1'b1;
"FALSE" : CLK_CORRECT_USE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_CORRECT_USE);
#1 $finish;
end
endcase
case (CLK_COR_KEEP_IDLE)
"FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0;
"TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_KEEP_IDLE);
#1 $finish;
end
endcase
case (CLK_COR_PRECEDENCE)
"TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1;
"FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_COR_PRECEDENCE);
#1 $finish;
end
endcase
case (CLK_COR_SEQ_2_USE)
"FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0;
"TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_SEQ_2_USE);
#1 $finish;
end
endcase
case (CLK_COR_SEQ_LEN)
1 : CLK_COR_SEQ_LEN_BINARY = 2'b00;
2 : CLK_COR_SEQ_LEN_BINARY = 2'b01;
3 : CLK_COR_SEQ_LEN_BINARY = 2'b10;
4 : CLK_COR_SEQ_LEN_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_SEQ_LEN, 1);
#1 $finish;
end
endcase
case (DEC_MCOMMA_DETECT)
"TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1;
"FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_MCOMMA_DETECT);
#1 $finish;
end
endcase
case (DEC_PCOMMA_DETECT)
"TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1;
"FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_PCOMMA_DETECT);
#1 $finish;
end
endcase
case (DEC_VALID_COMMA_ONLY)
"TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1;
"FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_VALID_COMMA_ONLY);
#1 $finish;
end
endcase
case (ES_ERRDET_EN)
"FALSE" : ES_ERRDET_EN_BINARY = 1'b0;
"TRUE" : ES_ERRDET_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ES_ERRDET_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_ERRDET_EN);
#1 $finish;
end
endcase
case (ES_EYE_SCAN_EN)
"FALSE" : ES_EYE_SCAN_EN_BINARY = 1'b0;
"TRUE" : ES_EYE_SCAN_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ES_EYE_SCAN_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_EYE_SCAN_EN);
#1 $finish;
end
endcase
case (FTS_LANE_DESKEW_EN)
"FALSE" : FTS_LANE_DESKEW_EN_BINARY = 1'b0;
"TRUE" : FTS_LANE_DESKEW_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", FTS_LANE_DESKEW_EN);
#1 $finish;
end
endcase
case (PCS_PCIE_EN)
"FALSE" : PCS_PCIE_EN_BINARY = 1'b0;
"TRUE" : PCS_PCIE_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PCS_PCIE_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCS_PCIE_EN);
#1 $finish;
end
endcase
case (RXBUF_ADDR_MODE)
"FULL" : RXBUF_ADDR_MODE_BINARY = 1'b0;
"FAST" : RXBUF_ADDR_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_ADDR_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RXBUF_ADDR_MODE);
#1 $finish;
end
endcase
case (RXBUF_EN)
"TRUE" : RXBUF_EN_BINARY = 1'b1;
"FALSE" : RXBUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_EN);
#1 $finish;
end
endcase
case (RXBUF_RESET_ON_CB_CHANGE)
"TRUE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b1;
"FALSE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_CB_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_CB_CHANGE);
#1 $finish;
end
endcase
case (RXBUF_RESET_ON_COMMAALIGN)
"FALSE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b0;
"TRUE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_COMMAALIGN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_COMMAALIGN);
#1 $finish;
end
endcase
case (RXBUF_RESET_ON_EIDLE)
"FALSE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b0;
"TRUE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_EIDLE);
#1 $finish;
end
endcase
case (RXBUF_RESET_ON_RATE_CHANGE)
"TRUE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1;
"FALSE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_RATE_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_RATE_CHANGE);
#1 $finish;
end
endcase
case (RXBUF_THRESH_OVRD)
"FALSE" : RXBUF_THRESH_OVRD_BINARY = 1'b0;
"TRUE" : RXBUF_THRESH_OVRD_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVRD on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_THRESH_OVRD);
#1 $finish;
end
endcase
case (RXGEARBOX_EN)
"FALSE" : RXGEARBOX_EN_BINARY = 1'b0;
"TRUE" : RXGEARBOX_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXGEARBOX_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXGEARBOX_EN);
#1 $finish;
end
endcase
case (RXOOB_CLK_CFG)
"PMA" : RXOOB_CLK_CFG_BINARY = 1'b0;
"FABRIC" : RXOOB_CLK_CFG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RXOOB_CLK_CFG on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are PMA, or FABRIC.", RXOOB_CLK_CFG);
#1 $finish;
end
endcase
case (RXOUT_DIV)
2 : RXOUT_DIV_BINARY = 3'b001;
1 : RXOUT_DIV_BINARY = 3'b000;
4 : RXOUT_DIV_BINARY = 3'b010;
8 : RXOUT_DIV_BINARY = 3'b011;
16 : RXOUT_DIV_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute RXOUT_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", RXOUT_DIV, 2);
#1 $finish;
end
endcase
case (RXSLIDE_MODE)
"OFF" : RXSLIDE_MODE_BINARY = 2'b00;
"AUTO" : RXSLIDE_MODE_BINARY = 2'b01;
"PCS" : RXSLIDE_MODE_BINARY = 2'b10;
"PMA" : RXSLIDE_MODE_BINARY = 2'b11;
default : begin
$display("Attribute Syntax Error : The Attribute RXSLIDE_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RXSLIDE_MODE);
#1 $finish;
end
endcase
case (RX_CLK25_DIV)
7 : RX_CLK25_DIV_BINARY = 5'b00110;
1 : RX_CLK25_DIV_BINARY = 5'b00000;
2 : RX_CLK25_DIV_BINARY = 5'b00001;
3 : RX_CLK25_DIV_BINARY = 5'b00010;
4 : RX_CLK25_DIV_BINARY = 5'b00011;
5 : RX_CLK25_DIV_BINARY = 5'b00100;
6 : RX_CLK25_DIV_BINARY = 5'b00101;
8 : RX_CLK25_DIV_BINARY = 5'b00111;
9 : RX_CLK25_DIV_BINARY = 5'b01000;
10 : RX_CLK25_DIV_BINARY = 5'b01001;
11 : RX_CLK25_DIV_BINARY = 5'b01010;
12 : RX_CLK25_DIV_BINARY = 5'b01011;
13 : RX_CLK25_DIV_BINARY = 5'b01100;
14 : RX_CLK25_DIV_BINARY = 5'b01101;
15 : RX_CLK25_DIV_BINARY = 5'b01110;
16 : RX_CLK25_DIV_BINARY = 5'b01111;
17 : RX_CLK25_DIV_BINARY = 5'b10000;
18 : RX_CLK25_DIV_BINARY = 5'b10001;
19 : RX_CLK25_DIV_BINARY = 5'b10010;
20 : RX_CLK25_DIV_BINARY = 5'b10011;
21 : RX_CLK25_DIV_BINARY = 5'b10100;
22 : RX_CLK25_DIV_BINARY = 5'b10101;
23 : RX_CLK25_DIV_BINARY = 5'b10110;
24 : RX_CLK25_DIV_BINARY = 5'b10111;
25 : RX_CLK25_DIV_BINARY = 5'b11000;
26 : RX_CLK25_DIV_BINARY = 5'b11001;
27 : RX_CLK25_DIV_BINARY = 5'b11010;
28 : RX_CLK25_DIV_BINARY = 5'b11011;
29 : RX_CLK25_DIV_BINARY = 5'b11100;
30 : RX_CLK25_DIV_BINARY = 5'b11101;
31 : RX_CLK25_DIV_BINARY = 5'b11110;
32 : RX_CLK25_DIV_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_CLK25_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIV, 7);
#1 $finish;
end
endcase
case (RX_DATA_WIDTH)
20 : RX_DATA_WIDTH_BINARY = 3'b011;
16 : RX_DATA_WIDTH_BINARY = 3'b010;
32 : RX_DATA_WIDTH_BINARY = 3'b100;
40 : RX_DATA_WIDTH_BINARY = 3'b101;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 40.", RX_DATA_WIDTH, 20);
#1 $finish;
end
endcase
case (RX_DEFER_RESET_BUF_EN)
"TRUE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b1;
"FALSE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DEFER_RESET_BUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DEFER_RESET_BUF_EN);
#1 $finish;
end
endcase
case (RX_DISPERR_SEQ_MATCH)
"TRUE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b1;
"FALSE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute RX_DISPERR_SEQ_MATCH on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DISPERR_SEQ_MATCH);
#1 $finish;
end
endcase
case (RX_SIG_VALID_DLY)
10 : RX_SIG_VALID_DLY_BINARY = 5'b01001;
1 : RX_SIG_VALID_DLY_BINARY = 5'b00000;
2 : RX_SIG_VALID_DLY_BINARY = 5'b00001;
3 : RX_SIG_VALID_DLY_BINARY = 5'b00010;
4 : RX_SIG_VALID_DLY_BINARY = 5'b00011;
5 : RX_SIG_VALID_DLY_BINARY = 5'b00100;
6 : RX_SIG_VALID_DLY_BINARY = 5'b00101;
7 : RX_SIG_VALID_DLY_BINARY = 5'b00110;
8 : RX_SIG_VALID_DLY_BINARY = 5'b00111;
9 : RX_SIG_VALID_DLY_BINARY = 5'b01000;
11 : RX_SIG_VALID_DLY_BINARY = 5'b01010;
12 : RX_SIG_VALID_DLY_BINARY = 5'b01011;
13 : RX_SIG_VALID_DLY_BINARY = 5'b01100;
14 : RX_SIG_VALID_DLY_BINARY = 5'b01101;
15 : RX_SIG_VALID_DLY_BINARY = 5'b01110;
16 : RX_SIG_VALID_DLY_BINARY = 5'b01111;
17 : RX_SIG_VALID_DLY_BINARY = 5'b10000;
18 : RX_SIG_VALID_DLY_BINARY = 5'b10001;
19 : RX_SIG_VALID_DLY_BINARY = 5'b10010;
20 : RX_SIG_VALID_DLY_BINARY = 5'b10011;
21 : RX_SIG_VALID_DLY_BINARY = 5'b10100;
22 : RX_SIG_VALID_DLY_BINARY = 5'b10101;
23 : RX_SIG_VALID_DLY_BINARY = 5'b10110;
24 : RX_SIG_VALID_DLY_BINARY = 5'b10111;
25 : RX_SIG_VALID_DLY_BINARY = 5'b11000;
26 : RX_SIG_VALID_DLY_BINARY = 5'b11001;
27 : RX_SIG_VALID_DLY_BINARY = 5'b11010;
28 : RX_SIG_VALID_DLY_BINARY = 5'b11011;
29 : RX_SIG_VALID_DLY_BINARY = 5'b11100;
30 : RX_SIG_VALID_DLY_BINARY = 5'b11101;
31 : RX_SIG_VALID_DLY_BINARY = 5'b11110;
32 : RX_SIG_VALID_DLY_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute RX_SIG_VALID_DLY on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_SIG_VALID_DLY, 10);
#1 $finish;
end
endcase
case (RX_XCLK_SEL)
"RXREC" : RX_XCLK_SEL_BINARY = 1'b0;
"RXUSR" : RX_XCLK_SEL_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL);
#1 $finish;
end
endcase
case (SATA_PLL_CFG)
"VCO_3000MHZ" : SATA_PLL_CFG_BINARY = 2'b00;
"VCO_750MHZ" : SATA_PLL_CFG_BINARY = 2'b10;
"VCO_1500MHZ" : SATA_PLL_CFG_BINARY = 2'b01;
default : begin
$display("Attribute Syntax Error : The Attribute SATA_PLL_CFG on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, or VCO_1500MHZ.", SATA_PLL_CFG);
#1 $finish;
end
endcase
case (SHOW_REALIGN_COMMA)
"TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1;
"FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SHOW_REALIGN_COMMA);
#1 $finish;
end
endcase
case (SIM_RECEIVER_DETECT_PASS)
"TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0;
"FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RECEIVER_DETECT_PASS);
#1 $finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
#1 $finish;
end
endcase
case (SIM_TX_EIDLE_DRIVE_LEVEL)
"X" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"0" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"1" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
"Z" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_TX_EIDLE_DRIVE_LEVEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", SIM_TX_EIDLE_DRIVE_LEVEL);
#1 $finish;
end
endcase
case (SIM_VERSION)
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, or 2.0.", SIM_VERSION);
#1 $finish;
end
endcase
case (TXBUF_EN)
"TRUE" : TXBUF_EN_BINARY = 1'b1;
"FALSE" : TXBUF_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TXBUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TXBUF_EN);
#1 $finish;
end
endcase
case (TXBUF_RESET_ON_RATE_CHANGE)
"FALSE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0;
"TRUE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TXBUF_RESET_ON_RATE_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXBUF_RESET_ON_RATE_CHANGE);
#1 $finish;
end
endcase
case (TXGEARBOX_EN)
"FALSE" : TXGEARBOX_EN_BINARY = 1'b0;
"TRUE" : TXGEARBOX_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TXGEARBOX_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXGEARBOX_EN);
#1 $finish;
end
endcase
case (TXOUT_DIV)
2 : TXOUT_DIV_BINARY = 3'b001;
1 : TXOUT_DIV_BINARY = 3'b000;
4 : TXOUT_DIV_BINARY = 3'b010;
8 : TXOUT_DIV_BINARY = 3'b011;
16 : TXOUT_DIV_BINARY = 3'b100;
default : begin
$display("Attribute Syntax Error : The Attribute TXOUT_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", TXOUT_DIV, 2);
#1 $finish;
end
endcase
case (TXPI_PPMCLK_SEL)
"TXUSRCLK2" : TXPI_PPMCLK_SEL_BINARY = 1'b1;
"TXUSRCLK" : TXPI_PPMCLK_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TXPI_PPMCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSRCLK2, or TXUSRCLK.", TXPI_PPMCLK_SEL);
#1 $finish;
end
endcase
case (TX_CLK25_DIV)
7 : TX_CLK25_DIV_BINARY = 5'b00110;
1 : TX_CLK25_DIV_BINARY = 5'b00000;
2 : TX_CLK25_DIV_BINARY = 5'b00001;
3 : TX_CLK25_DIV_BINARY = 5'b00010;
4 : TX_CLK25_DIV_BINARY = 5'b00011;
5 : TX_CLK25_DIV_BINARY = 5'b00100;
6 : TX_CLK25_DIV_BINARY = 5'b00101;
8 : TX_CLK25_DIV_BINARY = 5'b00111;
9 : TX_CLK25_DIV_BINARY = 5'b01000;
10 : TX_CLK25_DIV_BINARY = 5'b01001;
11 : TX_CLK25_DIV_BINARY = 5'b01010;
12 : TX_CLK25_DIV_BINARY = 5'b01011;
13 : TX_CLK25_DIV_BINARY = 5'b01100;
14 : TX_CLK25_DIV_BINARY = 5'b01101;
15 : TX_CLK25_DIV_BINARY = 5'b01110;
16 : TX_CLK25_DIV_BINARY = 5'b01111;
17 : TX_CLK25_DIV_BINARY = 5'b10000;
18 : TX_CLK25_DIV_BINARY = 5'b10001;
19 : TX_CLK25_DIV_BINARY = 5'b10010;
20 : TX_CLK25_DIV_BINARY = 5'b10011;
21 : TX_CLK25_DIV_BINARY = 5'b10100;
22 : TX_CLK25_DIV_BINARY = 5'b10101;
23 : TX_CLK25_DIV_BINARY = 5'b10110;
24 : TX_CLK25_DIV_BINARY = 5'b10111;
25 : TX_CLK25_DIV_BINARY = 5'b11000;
26 : TX_CLK25_DIV_BINARY = 5'b11001;
27 : TX_CLK25_DIV_BINARY = 5'b11010;
28 : TX_CLK25_DIV_BINARY = 5'b11011;
29 : TX_CLK25_DIV_BINARY = 5'b11100;
30 : TX_CLK25_DIV_BINARY = 5'b11101;
31 : TX_CLK25_DIV_BINARY = 5'b11110;
32 : TX_CLK25_DIV_BINARY = 5'b11111;
default : begin
$display("Attribute Syntax Error : The Attribute TX_CLK25_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIV, 7);
#1 $finish;
end
endcase
case (TX_DATA_WIDTH)
20 : TX_DATA_WIDTH_BINARY = 3'b011;
16 : TX_DATA_WIDTH_BINARY = 3'b010;
32 : TX_DATA_WIDTH_BINARY = 3'b100;
40 : TX_DATA_WIDTH_BINARY = 3'b101;
default : begin
$display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 40.", TX_DATA_WIDTH, 20);
#1 $finish;
end
endcase
case (TX_DRIVE_MODE)
"DIRECT" : TX_DRIVE_MODE_BINARY = 5'b00000;
"PIPE" : TX_DRIVE_MODE_BINARY = 5'b00001;
"PIPEGEN3" : TX_DRIVE_MODE_BINARY = 5'b00010;
default : begin
$display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE, or PIPEGEN3.", TX_DRIVE_MODE);
#1 $finish;
end
endcase
case (TX_LOOPBACK_DRIVE_HIZ)
"FALSE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b0;
"TRUE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TX_LOOPBACK_DRIVE_HIZ on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TX_LOOPBACK_DRIVE_HIZ);
#1 $finish;
end
endcase
case (TX_XCLK_SEL)
"TXUSR" : TX_XCLK_SEL_BINARY = 1'b1;
"TXOUT" : TX_XCLK_SEL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL);
#1 $finish;
end
endcase
if ((ACJTAG_DEBUG_MODE >= 1'b0) && (ACJTAG_DEBUG_MODE <= 1'b1))
ACJTAG_DEBUG_MODE_BINARY = ACJTAG_DEBUG_MODE;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_DEBUG_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_DEBUG_MODE);
#1 $finish;
end
if ((ACJTAG_MODE >= 1'b0) && (ACJTAG_MODE <= 1'b1))
ACJTAG_MODE_BINARY = ACJTAG_MODE;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_MODE);
#1 $finish;
end
if ((ACJTAG_RESET >= 1'b0) && (ACJTAG_RESET <= 1'b1))
ACJTAG_RESET_BINARY = ACJTAG_RESET;
else begin
$display("Attribute Syntax Error : The Attribute ACJTAG_RESET on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_RESET);
#1 $finish;
end
if ((ADAPT_CFG0 >= 20'b00000000000000000000) && (ADAPT_CFG0 <= 20'b11111111111111111111))
ADAPT_CFG0_BINARY = ADAPT_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute ADAPT_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 20'b00000000000000000000 to 20'b11111111111111111111.", ADAPT_CFG0);
#1 $finish;
end
if ((ALIGN_COMMA_ENABLE >= 10'b0000000000) && (ALIGN_COMMA_ENABLE <= 10'b1111111111))
ALIGN_COMMA_ENABLE_BINARY = ALIGN_COMMA_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_COMMA_ENABLE);
#1 $finish;
end
if ((ALIGN_COMMA_WORD >= 1) && (ALIGN_COMMA_WORD <= 2))
ALIGN_COMMA_WORD_BINARY = ALIGN_COMMA_WORD;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 2.", ALIGN_COMMA_WORD);
#1 $finish;
end
if ((ALIGN_MCOMMA_VALUE >= 10'b0000000000) && (ALIGN_MCOMMA_VALUE <= 10'b1111111111))
ALIGN_MCOMMA_VALUE_BINARY = ALIGN_MCOMMA_VALUE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_VALUE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_MCOMMA_VALUE);
#1 $finish;
end
if ((ALIGN_PCOMMA_VALUE >= 10'b0000000000) && (ALIGN_PCOMMA_VALUE <= 10'b1111111111))
ALIGN_PCOMMA_VALUE_BINARY = ALIGN_PCOMMA_VALUE;
else begin
$display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_VALUE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_PCOMMA_VALUE);
#1 $finish;
end
if ((CFOK_CFG >= 43'b0000000000000000000000000000000000000000000) && (CFOK_CFG <= 43'b1111111111111111111111111111111111111111111))
CFOK_CFG_BINARY = CFOK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 43'b0000000000000000000000000000000000000000000 to 43'b1111111111111111111111111111111111111111111.", CFOK_CFG);
#1 $finish;
end
if ((CFOK_CFG2 >= 7'b0000000) && (CFOK_CFG2 <= 7'b1111111))
CFOK_CFG2_BINARY = CFOK_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", CFOK_CFG2);
#1 $finish;
end
if ((CFOK_CFG3 >= 7'b0000000) && (CFOK_CFG3 <= 7'b1111111))
CFOK_CFG3_BINARY = CFOK_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", CFOK_CFG3);
#1 $finish;
end
if ((CFOK_CFG4 >= 1'b0) && (CFOK_CFG4 <= 1'b1))
CFOK_CFG4_BINARY = CFOK_CFG4;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", CFOK_CFG4);
#1 $finish;
end
if ((CFOK_CFG5 >= 2'b00) && (CFOK_CFG5 <= 2'b11))
CFOK_CFG5_BINARY = CFOK_CFG5;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", CFOK_CFG5);
#1 $finish;
end
if ((CFOK_CFG6 >= 4'b0000) && (CFOK_CFG6 <= 4'b1111))
CFOK_CFG6_BINARY = CFOK_CFG6;
else begin
$display("Attribute Syntax Error : The Attribute CFOK_CFG6 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CFOK_CFG6);
#1 $finish;
end
if ((CHAN_BOND_MAX_SKEW >= 1) && (CHAN_BOND_MAX_SKEW <= 14))
CHAN_BOND_MAX_SKEW_BINARY = CHAN_BOND_MAX_SKEW;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_MAX_SKEW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_MAX_SKEW);
#1 $finish;
end
if ((CHAN_BOND_SEQ_1_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_1 <= 10'b1111111111))
CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_1);
#1 $finish;
end
if ((CHAN_BOND_SEQ_1_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_2 <= 10'b1111111111))
CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_2);
#1 $finish;
end
if ((CHAN_BOND_SEQ_1_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_3 <= 10'b1111111111))
CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_3);
#1 $finish;
end
if ((CHAN_BOND_SEQ_1_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_4 <= 10'b1111111111))
CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_4);
#1 $finish;
end
if ((CHAN_BOND_SEQ_1_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_1_ENABLE <= 4'b1111))
CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_1_ENABLE);
#1 $finish;
end
if ((CHAN_BOND_SEQ_2_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_1 <= 10'b1111111111))
CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_1);
#1 $finish;
end
if ((CHAN_BOND_SEQ_2_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_2 <= 10'b1111111111))
CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_2);
#1 $finish;
end
if ((CHAN_BOND_SEQ_2_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_3 <= 10'b1111111111))
CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_3);
#1 $finish;
end
if ((CHAN_BOND_SEQ_2_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_4 <= 10'b1111111111))
CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_4);
#1 $finish;
end
if ((CHAN_BOND_SEQ_2_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_2_ENABLE <= 4'b1111))
CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_2_ENABLE);
#1 $finish;
end
if ((CLK_COMMON_SWING >= 1'b0) && (CLK_COMMON_SWING <= 1'b1))
CLK_COMMON_SWING_BINARY = CLK_COMMON_SWING;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COMMON_SWING on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", CLK_COMMON_SWING);
#1 $finish;
end
if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 60))
CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MAX_LAT);
#1 $finish;
end
if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 60))
CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MIN_LAT);
#1 $finish;
end
if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31))
CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT);
#1 $finish;
end
if ((CLK_COR_SEQ_1_1 >= 10'b0000000000) && (CLK_COR_SEQ_1_1 <= 10'b1111111111))
CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_1);
#1 $finish;
end
if ((CLK_COR_SEQ_1_2 >= 10'b0000000000) && (CLK_COR_SEQ_1_2 <= 10'b1111111111))
CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_2);
#1 $finish;
end
if ((CLK_COR_SEQ_1_3 >= 10'b0000000000) && (CLK_COR_SEQ_1_3 <= 10'b1111111111))
CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_3);
#1 $finish;
end
if ((CLK_COR_SEQ_1_4 >= 10'b0000000000) && (CLK_COR_SEQ_1_4 <= 10'b1111111111))
CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_4);
#1 $finish;
end
if ((CLK_COR_SEQ_1_ENABLE >= 4'b0000) && (CLK_COR_SEQ_1_ENABLE <= 4'b1111))
CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_1_ENABLE);
#1 $finish;
end
if ((CLK_COR_SEQ_2_1 >= 10'b0000000000) && (CLK_COR_SEQ_2_1 <= 10'b1111111111))
CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_1);
#1 $finish;
end
if ((CLK_COR_SEQ_2_2 >= 10'b0000000000) && (CLK_COR_SEQ_2_2 <= 10'b1111111111))
CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_2);
#1 $finish;
end
if ((CLK_COR_SEQ_2_3 >= 10'b0000000000) && (CLK_COR_SEQ_2_3 <= 10'b1111111111))
CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_3);
#1 $finish;
end
if ((CLK_COR_SEQ_2_4 >= 10'b0000000000) && (CLK_COR_SEQ_2_4 <= 10'b1111111111))
CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_4);
#1 $finish;
end
if ((CLK_COR_SEQ_2_ENABLE >= 4'b0000) && (CLK_COR_SEQ_2_ENABLE <= 4'b1111))
CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_2_ENABLE);
#1 $finish;
end
if ((ES_CLK_PHASE_SEL >= 1'b0) && (ES_CLK_PHASE_SEL <= 1'b1))
ES_CLK_PHASE_SEL_BINARY = ES_CLK_PHASE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute ES_CLK_PHASE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ES_CLK_PHASE_SEL);
#1 $finish;
end
if ((ES_CONTROL >= 6'b000000) && (ES_CONTROL <= 6'b111111))
ES_CONTROL_BINARY = ES_CONTROL;
else begin
$display("Attribute Syntax Error : The Attribute ES_CONTROL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", ES_CONTROL);
#1 $finish;
end
if ((ES_PMA_CFG >= 10'b0000000000) && (ES_PMA_CFG <= 10'b1111111111))
ES_PMA_CFG_BINARY = ES_PMA_CFG;
else begin
$display("Attribute Syntax Error : The Attribute ES_PMA_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ES_PMA_CFG);
#1 $finish;
end
if ((ES_PRESCALE >= 5'b00000) && (ES_PRESCALE <= 5'b11111))
ES_PRESCALE_BINARY = ES_PRESCALE;
else begin
$display("Attribute Syntax Error : The Attribute ES_PRESCALE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", ES_PRESCALE);
#1 $finish;
end
if ((ES_VERT_OFFSET >= 9'b000000000) && (ES_VERT_OFFSET <= 9'b111111111))
ES_VERT_OFFSET_BINARY = ES_VERT_OFFSET;
else begin
$display("Attribute Syntax Error : The Attribute ES_VERT_OFFSET on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", ES_VERT_OFFSET);
#1 $finish;
end
if ((FTS_DESKEW_SEQ_ENABLE >= 4'b0000) && (FTS_DESKEW_SEQ_ENABLE <= 4'b1111))
FTS_DESKEW_SEQ_ENABLE_BINARY = FTS_DESKEW_SEQ_ENABLE;
else begin
$display("Attribute Syntax Error : The Attribute FTS_DESKEW_SEQ_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_DESKEW_SEQ_ENABLE);
#1 $finish;
end
if ((FTS_LANE_DESKEW_CFG >= 4'b0000) && (FTS_LANE_DESKEW_CFG <= 4'b1111))
FTS_LANE_DESKEW_CFG_BINARY = FTS_LANE_DESKEW_CFG;
else begin
$display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_LANE_DESKEW_CFG);
#1 $finish;
end
if ((GEARBOX_MODE >= 3'b000) && (GEARBOX_MODE <= 3'b111))
GEARBOX_MODE_BINARY = GEARBOX_MODE;
else begin
$display("Attribute Syntax Error : The Attribute GEARBOX_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", GEARBOX_MODE);
#1 $finish;
end
if ((LOOPBACK_CFG >= 1'b0) && (LOOPBACK_CFG <= 1'b1))
LOOPBACK_CFG_BINARY = LOOPBACK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute LOOPBACK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", LOOPBACK_CFG);
#1 $finish;
end
if ((OUTREFCLK_SEL_INV >= 2'b00) && (OUTREFCLK_SEL_INV <= 2'b11))
OUTREFCLK_SEL_INV_BINARY = OUTREFCLK_SEL_INV;
else begin
$display("Attribute Syntax Error : The Attribute OUTREFCLK_SEL_INV on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", OUTREFCLK_SEL_INV);
#1 $finish;
end
if ((PMA_LOOPBACK_CFG >= 1'b0) && (PMA_LOOPBACK_CFG <= 1'b1))
PMA_LOOPBACK_CFG_BINARY = PMA_LOOPBACK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute PMA_LOOPBACK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_LOOPBACK_CFG);
#1 $finish;
end
if ((PMA_RSV3 >= 2'b00) && (PMA_RSV3 <= 2'b11))
PMA_RSV3_BINARY = PMA_RSV3;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", PMA_RSV3);
#1 $finish;
end
if ((PMA_RSV4 >= 4'b0000) && (PMA_RSV4 <= 4'b1111))
PMA_RSV4_BINARY = PMA_RSV4;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", PMA_RSV4);
#1 $finish;
end
if ((PMA_RSV5 >= 1'b0) && (PMA_RSV5 <= 1'b1))
PMA_RSV5_BINARY = PMA_RSV5;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV5);
#1 $finish;
end
if ((PMA_RSV6 >= 1'b0) && (PMA_RSV6 <= 1'b1))
PMA_RSV6_BINARY = PMA_RSV6;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV6 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV6);
#1 $finish;
end
if ((PMA_RSV7 >= 1'b0) && (PMA_RSV7 <= 1'b1))
PMA_RSV7_BINARY = PMA_RSV7;
else begin
$display("Attribute Syntax Error : The Attribute PMA_RSV7 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV7);
#1 $finish;
end
if ((RXBUFRESET_TIME >= 5'b00000) && (RXBUFRESET_TIME <= 5'b11111))
RXBUFRESET_TIME_BINARY = RXBUFRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXBUFRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXBUFRESET_TIME);
#1 $finish;
end
if ((RXBUF_EIDLE_HI_CNT >= 4'b0000) && (RXBUF_EIDLE_HI_CNT <= 4'b1111))
RXBUF_EIDLE_HI_CNT_BINARY = RXBUF_EIDLE_HI_CNT;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_HI_CNT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_HI_CNT);
#1 $finish;
end
if ((RXBUF_EIDLE_LO_CNT >= 4'b0000) && (RXBUF_EIDLE_LO_CNT <= 4'b1111))
RXBUF_EIDLE_LO_CNT_BINARY = RXBUF_EIDLE_LO_CNT;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_LO_CNT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_LO_CNT);
#1 $finish;
end
if ((RXBUF_THRESH_OVFLW >= 0) && (RXBUF_THRESH_OVFLW <= 63))
RXBUF_THRESH_OVFLW_BINARY = RXBUF_THRESH_OVFLW;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVFLW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_OVFLW);
#1 $finish;
end
if ((RXBUF_THRESH_UNDFLW >= 0) && (RXBUF_THRESH_UNDFLW <= 63))
RXBUF_THRESH_UNDFLW_BINARY = RXBUF_THRESH_UNDFLW;
else begin
$display("Attribute Syntax Error : The Attribute RXBUF_THRESH_UNDFLW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_UNDFLW);
#1 $finish;
end
if ((RXCDRFREQRESET_TIME >= 5'b00000) && (RXCDRFREQRESET_TIME <= 5'b11111))
RXCDRFREQRESET_TIME_BINARY = RXCDRFREQRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXCDRFREQRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRFREQRESET_TIME);
#1 $finish;
end
if ((RXCDRPHRESET_TIME >= 5'b00000) && (RXCDRPHRESET_TIME <= 5'b11111))
RXCDRPHRESET_TIME_BINARY = RXCDRPHRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXCDRPHRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRPHRESET_TIME);
#1 $finish;
end
if ((RXCDR_FR_RESET_ON_EIDLE >= 1'b0) && (RXCDR_FR_RESET_ON_EIDLE <= 1'b1))
RXCDR_FR_RESET_ON_EIDLE_BINARY = RXCDR_FR_RESET_ON_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_FR_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_FR_RESET_ON_EIDLE);
#1 $finish;
end
if ((RXCDR_HOLD_DURING_EIDLE >= 1'b0) && (RXCDR_HOLD_DURING_EIDLE <= 1'b1))
RXCDR_HOLD_DURING_EIDLE_BINARY = RXCDR_HOLD_DURING_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_HOLD_DURING_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_HOLD_DURING_EIDLE);
#1 $finish;
end
if ((RXCDR_LOCK_CFG >= 6'b000000) && (RXCDR_LOCK_CFG <= 6'b111111))
RXCDR_LOCK_CFG_BINARY = RXCDR_LOCK_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_LOCK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RXCDR_LOCK_CFG);
#1 $finish;
end
if ((RXCDR_PH_RESET_ON_EIDLE >= 1'b0) && (RXCDR_PH_RESET_ON_EIDLE <= 1'b1))
RXCDR_PH_RESET_ON_EIDLE_BINARY = RXCDR_PH_RESET_ON_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXCDR_PH_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_PH_RESET_ON_EIDLE);
#1 $finish;
end
if ((RXISCANRESET_TIME >= 5'b00000) && (RXISCANRESET_TIME <= 5'b11111))
RXISCANRESET_TIME_BINARY = RXISCANRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXISCANRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXISCANRESET_TIME);
#1 $finish;
end
if ((RXLPMRESET_TIME >= 7'b0000000) && (RXLPMRESET_TIME <= 7'b1111111))
RXLPMRESET_TIME_BINARY = RXLPMRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXLPMRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXLPMRESET_TIME);
#1 $finish;
end
if ((RXLPM_BIAS_STARTUP_DISABLE >= 1'b0) && (RXLPM_BIAS_STARTUP_DISABLE <= 1'b1))
RXLPM_BIAS_STARTUP_DISABLE_BINARY = RXLPM_BIAS_STARTUP_DISABLE;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_BIAS_STARTUP_DISABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_BIAS_STARTUP_DISABLE);
#1 $finish;
end
if ((RXLPM_CFG >= 4'b0000) && (RXLPM_CFG <= 4'b1111))
RXLPM_CFG_BINARY = RXLPM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXLPM_CFG);
#1 $finish;
end
if ((RXLPM_CFG1 >= 1'b0) && (RXLPM_CFG1 <= 1'b1))
RXLPM_CFG1_BINARY = RXLPM_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_CFG1);
#1 $finish;
end
if ((RXLPM_CM_CFG >= 1'b0) && (RXLPM_CM_CFG <= 1'b1))
RXLPM_CM_CFG_BINARY = RXLPM_CM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_CM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_CM_CFG);
#1 $finish;
end
if ((RXLPM_GC_CFG >= 9'b000000000) && (RXLPM_GC_CFG <= 9'b111111111))
RXLPM_GC_CFG_BINARY = RXLPM_GC_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_GC_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", RXLPM_GC_CFG);
#1 $finish;
end
if ((RXLPM_GC_CFG2 >= 3'b000) && (RXLPM_GC_CFG2 <= 3'b111))
RXLPM_GC_CFG2_BINARY = RXLPM_GC_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_GC_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXLPM_GC_CFG2);
#1 $finish;
end
if ((RXLPM_HF_CFG >= 14'b00000000000000) && (RXLPM_HF_CFG <= 14'b11111111111111))
RXLPM_HF_CFG_BINARY = RXLPM_HF_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_HF_CFG);
#1 $finish;
end
if ((RXLPM_HF_CFG2 >= 5'b00000) && (RXLPM_HF_CFG2 <= 5'b11111))
RXLPM_HF_CFG2_BINARY = RXLPM_HF_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXLPM_HF_CFG2);
#1 $finish;
end
if ((RXLPM_HF_CFG3 >= 4'b0000) && (RXLPM_HF_CFG3 <= 4'b1111))
RXLPM_HF_CFG3_BINARY = RXLPM_HF_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXLPM_HF_CFG3);
#1 $finish;
end
if ((RXLPM_HOLD_DURING_EIDLE >= 1'b0) && (RXLPM_HOLD_DURING_EIDLE <= 1'b1))
RXLPM_HOLD_DURING_EIDLE_BINARY = RXLPM_HOLD_DURING_EIDLE;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_HOLD_DURING_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_HOLD_DURING_EIDLE);
#1 $finish;
end
if ((RXLPM_INCM_CFG >= 1'b0) && (RXLPM_INCM_CFG <= 1'b1))
RXLPM_INCM_CFG_BINARY = RXLPM_INCM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_INCM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_INCM_CFG);
#1 $finish;
end
if ((RXLPM_IPCM_CFG >= 1'b0) && (RXLPM_IPCM_CFG <= 1'b1))
RXLPM_IPCM_CFG_BINARY = RXLPM_IPCM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_IPCM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_IPCM_CFG);
#1 $finish;
end
if ((RXLPM_LF_CFG >= 18'b000000000000000000) && (RXLPM_LF_CFG <= 18'b111111111111111111))
RXLPM_LF_CFG_BINARY = RXLPM_LF_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 18'b000000000000000000 to 18'b111111111111111111.", RXLPM_LF_CFG);
#1 $finish;
end
if ((RXLPM_LF_CFG2 >= 5'b00000) && (RXLPM_LF_CFG2 <= 5'b11111))
RXLPM_LF_CFG2_BINARY = RXLPM_LF_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXLPM_LF_CFG2);
#1 $finish;
end
if ((RXLPM_OSINT_CFG >= 3'b000) && (RXLPM_OSINT_CFG <= 3'b111))
RXLPM_OSINT_CFG_BINARY = RXLPM_OSINT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXLPM_OSINT_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXLPM_OSINT_CFG);
#1 $finish;
end
if ((RXOOB_CFG >= 7'b0000000) && (RXOOB_CFG <= 7'b1111111))
RXOOB_CFG_BINARY = RXOOB_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RXOOB_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXOOB_CFG);
#1 $finish;
end
if ((RXOSCALRESET_TIME >= 5'b00000) && (RXOSCALRESET_TIME <= 5'b11111))
RXOSCALRESET_TIME_BINARY = RXOSCALRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIME);
#1 $finish;
end
if ((RXOSCALRESET_TIMEOUT >= 5'b00000) && (RXOSCALRESET_TIMEOUT <= 5'b11111))
RXOSCALRESET_TIMEOUT_BINARY = RXOSCALRESET_TIMEOUT;
else begin
$display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIMEOUT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIMEOUT);
#1 $finish;
end
if ((RXPCSRESET_TIME >= 5'b00000) && (RXPCSRESET_TIME <= 5'b11111))
RXPCSRESET_TIME_BINARY = RXPCSRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXPCSRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPCSRESET_TIME);
#1 $finish;
end
if ((RXPH_MONITOR_SEL >= 5'b00000) && (RXPH_MONITOR_SEL <= 5'b11111))
RXPH_MONITOR_SEL_BINARY = RXPH_MONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RXPH_MONITOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPH_MONITOR_SEL);
#1 $finish;
end
if ((RXPI_CFG0 >= 3'b000) && (RXPI_CFG0 <= 3'b111))
RXPI_CFG0_BINARY = RXPI_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXPI_CFG0);
#1 $finish;
end
if ((RXPI_CFG1 >= 1'b0) && (RXPI_CFG1 <= 1'b1))
RXPI_CFG1_BINARY = RXPI_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG1);
#1 $finish;
end
if ((RXPI_CFG2 >= 1'b0) && (RXPI_CFG2 <= 1'b1))
RXPI_CFG2_BINARY = RXPI_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute RXPI_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG2);
#1 $finish;
end
if ((RXPMARESET_TIME >= 5'b00000) && (RXPMARESET_TIME <= 5'b11111))
RXPMARESET_TIME_BINARY = RXPMARESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute RXPMARESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPMARESET_TIME);
#1 $finish;
end
if ((RXPRBS_ERR_LOOPBACK >= 1'b0) && (RXPRBS_ERR_LOOPBACK <= 1'b1))
RXPRBS_ERR_LOOPBACK_BINARY = RXPRBS_ERR_LOOPBACK;
else begin
$display("Attribute Syntax Error : The Attribute RXPRBS_ERR_LOOPBACK on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPRBS_ERR_LOOPBACK);
#1 $finish;
end
if ((RXSLIDE_AUTO_WAIT >= 0) && (RXSLIDE_AUTO_WAIT <= 15))
RXSLIDE_AUTO_WAIT_BINARY = RXSLIDE_AUTO_WAIT;
else begin
$display("Attribute Syntax Error : The Attribute RXSLIDE_AUTO_WAIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 15.", RXSLIDE_AUTO_WAIT);
#1 $finish;
end
if ((RXSYNC_MULTILANE >= 1'b0) && (RXSYNC_MULTILANE <= 1'b1))
RXSYNC_MULTILANE_BINARY = RXSYNC_MULTILANE;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_MULTILANE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_MULTILANE);
#1 $finish;
end
if ((RXSYNC_OVRD >= 1'b0) && (RXSYNC_OVRD <= 1'b1))
RXSYNC_OVRD_BINARY = RXSYNC_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_OVRD);
#1 $finish;
end
if ((RXSYNC_SKIP_DA >= 1'b0) && (RXSYNC_SKIP_DA <= 1'b1))
RXSYNC_SKIP_DA_BINARY = RXSYNC_SKIP_DA;
else begin
$display("Attribute Syntax Error : The Attribute RXSYNC_SKIP_DA on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_SKIP_DA);
#1 $finish;
end
if ((RX_BIAS_CFG >= 16'b0000000000000000) && (RX_BIAS_CFG <= 16'b1111111111111111))
RX_BIAS_CFG_BINARY = RX_BIAS_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_BIAS_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", RX_BIAS_CFG);
#1 $finish;
end
if ((RX_BUFFER_CFG >= 6'b000000) && (RX_BUFFER_CFG <= 6'b111111))
RX_BUFFER_CFG_BINARY = RX_BUFFER_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_BUFFER_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_BUFFER_CFG);
#1 $finish;
end
if ((RX_CLKMUX_EN >= 1'b0) && (RX_CLKMUX_EN <= 1'b1))
RX_CLKMUX_EN_BINARY = RX_CLKMUX_EN;
else begin
$display("Attribute Syntax Error : The Attribute RX_CLKMUX_EN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_CLKMUX_EN);
#1 $finish;
end
if ((RX_CM_SEL >= 2'b00) && (RX_CM_SEL <= 2'b11))
RX_CM_SEL_BINARY = RX_CM_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RX_CM_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_CM_SEL);
#1 $finish;
end
if ((RX_CM_TRIM >= 4'b0000) && (RX_CM_TRIM <= 4'b1111))
RX_CM_TRIM_BINARY = RX_CM_TRIM;
else begin
$display("Attribute Syntax Error : The Attribute RX_CM_TRIM on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_CM_TRIM);
#1 $finish;
end
if ((RX_DDI_SEL >= 6'b000000) && (RX_DDI_SEL <= 6'b111111))
RX_DDI_SEL_BINARY = RX_DDI_SEL;
else begin
$display("Attribute Syntax Error : The Attribute RX_DDI_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_DDI_SEL);
#1 $finish;
end
if ((RX_DEBUG_CFG >= 14'b00000000000000) && (RX_DEBUG_CFG <= 14'b11111111111111))
RX_DEBUG_CFG_BINARY = RX_DEBUG_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_DEBUG_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RX_DEBUG_CFG);
#1 $finish;
end
if ((RX_OS_CFG >= 13'b0000000000000) && (RX_OS_CFG <= 13'b1111111111111))
RX_OS_CFG_BINARY = RX_OS_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RX_OS_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_OS_CFG);
#1 $finish;
end
if ((SAS_MAX_COM >= 1) && (SAS_MAX_COM <= 127))
SAS_MAX_COM_BINARY = SAS_MAX_COM;
else begin
$display("Attribute Syntax Error : The Attribute SAS_MAX_COM on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 127.", SAS_MAX_COM);
#1 $finish;
end
if ((SAS_MIN_COM >= 1) && (SAS_MIN_COM <= 63))
SAS_MIN_COM_BINARY = SAS_MIN_COM;
else begin
$display("Attribute Syntax Error : The Attribute SAS_MIN_COM on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SAS_MIN_COM);
#1 $finish;
end
if ((SATA_BURST_SEQ_LEN >= 4'b0000) && (SATA_BURST_SEQ_LEN <= 4'b1111))
SATA_BURST_SEQ_LEN_BINARY = SATA_BURST_SEQ_LEN;
else begin
$display("Attribute Syntax Error : The Attribute SATA_BURST_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", SATA_BURST_SEQ_LEN);
#1 $finish;
end
if ((SATA_BURST_VAL >= 3'b000) && (SATA_BURST_VAL <= 3'b111))
SATA_BURST_VAL_BINARY = SATA_BURST_VAL;
else begin
$display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_BURST_VAL);
#1 $finish;
end
if ((SATA_EIDLE_VAL >= 3'b000) && (SATA_EIDLE_VAL <= 3'b111))
SATA_EIDLE_VAL_BINARY = SATA_EIDLE_VAL;
else begin
$display("Attribute Syntax Error : The Attribute SATA_EIDLE_VAL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_EIDLE_VAL);
#1 $finish;
end
if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 63))
SATA_MAX_BURST_BINARY = SATA_MAX_BURST;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_BURST);
#1 $finish;
end
if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 63))
SATA_MAX_INIT_BINARY = SATA_MAX_INIT;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_INIT);
#1 $finish;
end
if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 63))
SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_WAKE);
#1 $finish;
end
if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61))
SATA_MIN_BURST_BINARY = SATA_MIN_BURST;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST);
#1 $finish;
end
if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 63))
SATA_MIN_INIT_BINARY = SATA_MIN_INIT;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_INIT);
#1 $finish;
end
if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 63))
SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE;
else begin
$display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_WAKE);
#1 $finish;
end
if ((TERM_RCAL_CFG >= 15'b000000000000000) && (TERM_RCAL_CFG <= 15'b111111111111111))
TERM_RCAL_CFG_BINARY = TERM_RCAL_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TERM_RCAL_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", TERM_RCAL_CFG);
#1 $finish;
end
if ((TERM_RCAL_OVRD >= 3'b000) && (TERM_RCAL_OVRD <= 3'b111))
TERM_RCAL_OVRD_BINARY = TERM_RCAL_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute TERM_RCAL_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TERM_RCAL_OVRD);
#1 $finish;
end
if ((TXOOB_CFG >= 1'b0) && (TXOOB_CFG <= 1'b1))
TXOOB_CFG_BINARY = TXOOB_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TXOOB_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXOOB_CFG);
#1 $finish;
end
if ((TXPCSRESET_TIME >= 5'b00000) && (TXPCSRESET_TIME <= 5'b11111))
TXPCSRESET_TIME_BINARY = TXPCSRESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute TXPCSRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPCSRESET_TIME);
#1 $finish;
end
if ((TXPH_MONITOR_SEL >= 5'b00000) && (TXPH_MONITOR_SEL <= 5'b11111))
TXPH_MONITOR_SEL_BINARY = TXPH_MONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPH_MONITOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPH_MONITOR_SEL);
#1 $finish;
end
if ((TXPI_CFG0 >= 2'b00) && (TXPI_CFG0 <= 2'b11))
TXPI_CFG0_BINARY = TXPI_CFG0;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG0);
#1 $finish;
end
if ((TXPI_CFG1 >= 2'b00) && (TXPI_CFG1 <= 2'b11))
TXPI_CFG1_BINARY = TXPI_CFG1;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG1);
#1 $finish;
end
if ((TXPI_CFG2 >= 2'b00) && (TXPI_CFG2 <= 2'b11))
TXPI_CFG2_BINARY = TXPI_CFG2;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG2);
#1 $finish;
end
if ((TXPI_CFG3 >= 1'b0) && (TXPI_CFG3 <= 1'b1))
TXPI_CFG3_BINARY = TXPI_CFG3;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG3);
#1 $finish;
end
if ((TXPI_CFG4 >= 1'b0) && (TXPI_CFG4 <= 1'b1))
TXPI_CFG4_BINARY = TXPI_CFG4;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG4);
#1 $finish;
end
if ((TXPI_CFG5 >= 3'b000) && (TXPI_CFG5 <= 3'b111))
TXPI_CFG5_BINARY = TXPI_CFG5;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_CFG5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_CFG5);
#1 $finish;
end
if ((TXPI_GREY_SEL >= 1'b0) && (TXPI_GREY_SEL <= 1'b1))
TXPI_GREY_SEL_BINARY = TXPI_GREY_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_GREY_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_GREY_SEL);
#1 $finish;
end
if ((TXPI_INVSTROBE_SEL >= 1'b0) && (TXPI_INVSTROBE_SEL <= 1'b1))
TXPI_INVSTROBE_SEL_BINARY = TXPI_INVSTROBE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_INVSTROBE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_INVSTROBE_SEL);
#1 $finish;
end
if ((TXPI_PPM_CFG >= 8'b00000000) && (TXPI_PPM_CFG <= 8'b11111111))
TXPI_PPM_CFG_BINARY = TXPI_PPM_CFG;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_PPM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", TXPI_PPM_CFG);
#1 $finish;
end
if ((TXPI_SYNFREQ_PPM >= 3'b000) && (TXPI_SYNFREQ_PPM <= 3'b111))
TXPI_SYNFREQ_PPM_BINARY = TXPI_SYNFREQ_PPM;
else begin
$display("Attribute Syntax Error : The Attribute TXPI_SYNFREQ_PPM on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_SYNFREQ_PPM);
#1 $finish;
end
if ((TXPMARESET_TIME >= 5'b00000) && (TXPMARESET_TIME <= 5'b11111))
TXPMARESET_TIME_BINARY = TXPMARESET_TIME;
else begin
$display("Attribute Syntax Error : The Attribute TXPMARESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPMARESET_TIME);
#1 $finish;
end
if ((TXSYNC_MULTILANE >= 1'b0) && (TXSYNC_MULTILANE <= 1'b1))
TXSYNC_MULTILANE_BINARY = TXSYNC_MULTILANE;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_MULTILANE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_MULTILANE);
#1 $finish;
end
if ((TXSYNC_OVRD >= 1'b0) && (TXSYNC_OVRD <= 1'b1))
TXSYNC_OVRD_BINARY = TXSYNC_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_OVRD);
#1 $finish;
end
if ((TXSYNC_SKIP_DA >= 1'b0) && (TXSYNC_SKIP_DA <= 1'b1))
TXSYNC_SKIP_DA_BINARY = TXSYNC_SKIP_DA;
else begin
$display("Attribute Syntax Error : The Attribute TXSYNC_SKIP_DA on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_SKIP_DA);
#1 $finish;
end
if ((TX_CLKMUX_EN >= 1'b0) && (TX_CLKMUX_EN <= 1'b1))
TX_CLKMUX_EN_BINARY = TX_CLKMUX_EN;
else begin
$display("Attribute Syntax Error : The Attribute TX_CLKMUX_EN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_CLKMUX_EN);
#1 $finish;
end
if ((TX_DEEMPH0 >= 6'b000000) && (TX_DEEMPH0 <= 6'b111111))
TX_DEEMPH0_BINARY = TX_DEEMPH0;
else begin
$display("Attribute Syntax Error : The Attribute TX_DEEMPH0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH0);
#1 $finish;
end
if ((TX_DEEMPH1 >= 6'b000000) && (TX_DEEMPH1 <= 6'b111111))
TX_DEEMPH1_BINARY = TX_DEEMPH1;
else begin
$display("Attribute Syntax Error : The Attribute TX_DEEMPH1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH1);
#1 $finish;
end
if ((TX_EIDLE_ASSERT_DELAY >= 3'b000) && (TX_EIDLE_ASSERT_DELAY <= 3'b111))
TX_EIDLE_ASSERT_DELAY_BINARY = TX_EIDLE_ASSERT_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute TX_EIDLE_ASSERT_DELAY on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_ASSERT_DELAY);
#1 $finish;
end
if ((TX_EIDLE_DEASSERT_DELAY >= 3'b000) && (TX_EIDLE_DEASSERT_DELAY <= 3'b111))
TX_EIDLE_DEASSERT_DELAY_BINARY = TX_EIDLE_DEASSERT_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute TX_EIDLE_DEASSERT_DELAY on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_DEASSERT_DELAY);
#1 $finish;
end
if ((TX_MAINCURSOR_SEL >= 1'b0) && (TX_MAINCURSOR_SEL <= 1'b1))
TX_MAINCURSOR_SEL_BINARY = TX_MAINCURSOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute TX_MAINCURSOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_MAINCURSOR_SEL);
#1 $finish;
end
if ((TX_MARGIN_FULL_0 >= 7'b0000000) && (TX_MARGIN_FULL_0 <= 7'b1111111))
TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_0);
#1 $finish;
end
if ((TX_MARGIN_FULL_1 >= 7'b0000000) && (TX_MARGIN_FULL_1 <= 7'b1111111))
TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_1);
#1 $finish;
end
if ((TX_MARGIN_FULL_2 >= 7'b0000000) && (TX_MARGIN_FULL_2 <= 7'b1111111))
TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_2);
#1 $finish;
end
if ((TX_MARGIN_FULL_3 >= 7'b0000000) && (TX_MARGIN_FULL_3 <= 7'b1111111))
TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_3);
#1 $finish;
end
if ((TX_MARGIN_FULL_4 >= 7'b0000000) && (TX_MARGIN_FULL_4 <= 7'b1111111))
TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_4);
#1 $finish;
end
if ((TX_MARGIN_LOW_0 >= 7'b0000000) && (TX_MARGIN_LOW_0 <= 7'b1111111))
TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_0);
#1 $finish;
end
if ((TX_MARGIN_LOW_1 >= 7'b0000000) && (TX_MARGIN_LOW_1 <= 7'b1111111))
TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_1);
#1 $finish;
end
if ((TX_MARGIN_LOW_2 >= 7'b0000000) && (TX_MARGIN_LOW_2 <= 7'b1111111))
TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_2);
#1 $finish;
end
if ((TX_MARGIN_LOW_3 >= 7'b0000000) && (TX_MARGIN_LOW_3 <= 7'b1111111))
TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_3);
#1 $finish;
end
if ((TX_MARGIN_LOW_4 >= 7'b0000000) && (TX_MARGIN_LOW_4 <= 7'b1111111))
TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4;
else begin
$display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_4);
#1 $finish;
end
if ((TX_PREDRIVER_MODE >= 1'b0) && (TX_PREDRIVER_MODE <= 1'b1))
TX_PREDRIVER_MODE_BINARY = TX_PREDRIVER_MODE;
else begin
$display("Attribute Syntax Error : The Attribute TX_PREDRIVER_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_PREDRIVER_MODE);
#1 $finish;
end
if ((TX_RXDETECT_REF >= 3'b000) && (TX_RXDETECT_REF <= 3'b111))
TX_RXDETECT_REF_BINARY = TX_RXDETECT_REF;
else begin
$display("Attribute Syntax Error : The Attribute TX_RXDETECT_REF on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_RXDETECT_REF);
#1 $finish;
end
if ((UCODEER_CLR >= 1'b0) && (UCODEER_CLR <= 1'b1))
UCODEER_CLR_BINARY = UCODEER_CLR;
else begin
$display("Attribute Syntax Error : The Attribute UCODEER_CLR on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", UCODEER_CLR);
#1 $finish;
end
if ((USE_PCS_CLK_PHASE_SEL >= 1'b0) && (USE_PCS_CLK_PHASE_SEL <= 1'b1))
USE_PCS_CLK_PHASE_SEL_BINARY = USE_PCS_CLK_PHASE_SEL;
else begin
$display("Attribute Syntax Error : The Attribute USE_PCS_CLK_PHASE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", USE_PCS_CLK_PHASE_SEL);
#1 $finish;
end
end
wire [14:0] delay_DMONITOROUT;
wire [15:0] delay_DRPDO;
wire [15:0] delay_PCSRSVDOUT;
wire [1:0] delay_RXCLKCORCNT;
wire [1:0] delay_RXDATAVALID;
wire [1:0] delay_RXSTARTOFSEQ;
wire [1:0] delay_TXBUFSTATUS;
wire [2:0] delay_RXBUFSTATUS;
wire [2:0] delay_RXHEADER;
wire [2:0] delay_RXSTATUS;
wire [31:0] delay_RXDATA;
wire [3:0] delay_RXCHARISCOMMA;
wire [3:0] delay_RXCHARISK;
wire [3:0] delay_RXCHBONDO;
wire [3:0] delay_RXDISPERR;
wire [3:0] delay_RXNOTINTABLE;
wire [4:0] delay_RXPHMONITOR;
wire [4:0] delay_RXPHSLIPMONITOR;
wire delay_DRPRDY;
wire delay_EYESCANDATAERROR;
wire delay_GTPTXN;
wire delay_GTPTXP;
wire delay_PHYSTATUS;
wire delay_PMARSVDOUT0;
wire delay_PMARSVDOUT1;
wire delay_RXBYTEISALIGNED;
wire delay_RXBYTEREALIGN;
wire delay_RXCDRLOCK;
wire delay_RXCHANBONDSEQ;
wire delay_RXCHANISALIGNED;
wire delay_RXCHANREALIGN;
wire delay_RXCOMINITDET;
wire delay_RXCOMMADET;
wire delay_RXCOMSASDET;
wire delay_RXCOMWAKEDET;
wire delay_RXDLYSRESETDONE;
wire delay_RXELECIDLE;
wire delay_RXHEADERVALID;
wire delay_RXOSINTDONE;
wire delay_RXOSINTSTARTED;
wire delay_RXOSINTSTROBEDONE;
wire delay_RXOSINTSTROBESTARTED;
wire delay_RXOUTCLK;
wire delay_RXOUTCLKFABRIC;
wire delay_RXOUTCLKPCS;
wire delay_RXPHALIGNDONE;
wire delay_RXPMARESETDONE;
wire delay_RXPRBSERR;
wire delay_RXRATEDONE;
wire delay_RXRESETDONE;
wire delay_RXSYNCDONE;
wire delay_RXSYNCOUT;
wire delay_RXVALID;
wire delay_TXCOMFINISH;
wire delay_TXDLYSRESETDONE;
wire delay_TXGEARBOXREADY;
wire delay_TXOUTCLK;
wire delay_TXOUTCLKFABRIC;
wire delay_TXOUTCLKPCS;
wire delay_TXPHALIGNDONE;
wire delay_TXPHINITDONE;
wire delay_TXPMARESETDONE;
wire delay_TXRATEDONE;
wire delay_TXRESETDONE;
wire delay_TXSYNCDONE;
wire delay_TXSYNCOUT;
wire [13:0] delay_RXADAPTSELTEST;
wire [15:0] delay_DRPDI;
wire [15:0] delay_GTRSVD;
wire [15:0] delay_PCSRSVDIN;
wire [19:0] delay_TSTIN;
wire [1:0] delay_RXELECIDLEMODE;
wire [1:0] delay_RXPD;
wire [1:0] delay_RXSYSCLKSEL;
wire [1:0] delay_TXPD;
wire [1:0] delay_TXSYSCLKSEL;
wire [2:0] delay_LOOPBACK;
wire [2:0] delay_RXCHBONDLEVEL;
wire [2:0] delay_RXOUTCLKSEL;
wire [2:0] delay_RXPRBSSEL;
wire [2:0] delay_RXRATE;
wire [2:0] delay_TXBUFDIFFCTRL;
wire [2:0] delay_TXHEADER;
wire [2:0] delay_TXMARGIN;
wire [2:0] delay_TXOUTCLKSEL;
wire [2:0] delay_TXPRBSSEL;
wire [2:0] delay_TXRATE;
wire [31:0] delay_TXDATA;
wire [3:0] delay_RXCHBONDI;
wire [3:0] delay_RXOSINTCFG;
wire [3:0] delay_RXOSINTID0;
wire [3:0] delay_TX8B10BBYPASS;
wire [3:0] delay_TXCHARDISPMODE;
wire [3:0] delay_TXCHARDISPVAL;
wire [3:0] delay_TXCHARISK;
wire [3:0] delay_TXDIFFCTRL;
wire [4:0] delay_TXPIPPMSTEPSIZE;
wire [4:0] delay_TXPOSTCURSOR;
wire [4:0] delay_TXPRECURSOR;
wire [6:0] delay_TXMAINCURSOR;
wire [6:0] delay_TXSEQUENCE;
wire [8:0] delay_DRPADDR;
wire delay_CFGRESET;
wire delay_CLKRSVD0;
wire delay_CLKRSVD1;
wire delay_DMONFIFORESET;
wire delay_DMONITORCLK;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_EYESCANMODE;
wire delay_EYESCANRESET;
wire delay_EYESCANTRIGGER;
wire delay_GTPRXN;
wire delay_GTPRXP;
wire delay_GTRESETSEL;
wire delay_GTRXRESET;
wire delay_GTTXRESET;
wire delay_PLL0CLK;
wire delay_PLL0REFCLK;
wire delay_PLL1CLK;
wire delay_PLL1REFCLK;
wire delay_PMARSVDIN0;
wire delay_PMARSVDIN1;
wire delay_PMARSVDIN2;
wire delay_PMARSVDIN3;
wire delay_PMARSVDIN4;
wire delay_RESETOVRD;
wire delay_RX8B10BEN;
wire delay_RXBUFRESET;
wire delay_RXCDRFREQRESET;
wire delay_RXCDRHOLD;
wire delay_RXCDROVRDEN;
wire delay_RXCDRRESET;
wire delay_RXCDRRESETRSV;
wire delay_RXCHBONDEN;
wire delay_RXCHBONDMASTER;
wire delay_RXCHBONDSLAVE;
wire delay_RXCOMMADETEN;
wire delay_RXDDIEN;
wire delay_RXDFEXYDEN;
wire delay_RXDLYBYPASS;
wire delay_RXDLYEN;
wire delay_RXDLYOVRDEN;
wire delay_RXDLYSRESET;
wire delay_RXGEARBOXSLIP;
wire delay_RXLPMHFHOLD;
wire delay_RXLPMHFOVRDEN;
wire delay_RXLPMLFHOLD;
wire delay_RXLPMLFOVRDEN;
wire delay_RXLPMOSINTNTRLEN;
wire delay_RXLPMRESET;
wire delay_RXMCOMMAALIGNEN;
wire delay_RXOOBRESET;
wire delay_RXOSCALRESET;
wire delay_RXOSHOLD;
wire delay_RXOSINTEN;
wire delay_RXOSINTHOLD;
wire delay_RXOSINTNTRLEN;
wire delay_RXOSINTOVRDEN;
wire delay_RXOSINTPD;
wire delay_RXOSINTSTROBE;
wire delay_RXOSINTTESTOVRDEN;
wire delay_RXOSOVRDEN;
wire delay_RXPCOMMAALIGNEN;
wire delay_RXPCSRESET;
wire delay_RXPHALIGN;
wire delay_RXPHALIGNEN;
wire delay_RXPHDLYPD;
wire delay_RXPHDLYRESET;
wire delay_RXPHOVRDEN;
wire delay_RXPMARESET;
wire delay_RXPOLARITY;
wire delay_RXPRBSCNTRESET;
wire delay_RXRATEMODE;
wire delay_RXSLIDE;
wire delay_RXSYNCALLIN;
wire delay_RXSYNCIN;
wire delay_RXSYNCMODE;
wire delay_RXUSERRDY;
wire delay_RXUSRCLK2;
wire delay_RXUSRCLK;
wire delay_SETERRSTATUS;
wire delay_SIGVALIDCLK;
wire delay_TX8B10BEN;
wire delay_TXCOMINIT;
wire delay_TXCOMSAS;
wire delay_TXCOMWAKE;
wire delay_TXDEEMPH;
wire delay_TXDETECTRX;
wire delay_TXDIFFPD;
wire delay_TXDLYBYPASS;
wire delay_TXDLYEN;
wire delay_TXDLYHOLD;
wire delay_TXDLYOVRDEN;
wire delay_TXDLYSRESET;
wire delay_TXDLYUPDOWN;
wire delay_TXELECIDLE;
wire delay_TXINHIBIT;
wire delay_TXPCSRESET;
wire delay_TXPDELECIDLEMODE;
wire delay_TXPHALIGN;
wire delay_TXPHALIGNEN;
wire delay_TXPHDLYPD;
wire delay_TXPHDLYRESET;
wire delay_TXPHDLYTSTCLK;
wire delay_TXPHINIT;
wire delay_TXPHOVRDEN;
wire delay_TXPIPPMEN;
wire delay_TXPIPPMOVRDEN;
wire delay_TXPIPPMPD;
wire delay_TXPIPPMSEL;
wire delay_TXPISOPD;
wire delay_TXPMARESET;
wire delay_TXPOLARITY;
wire delay_TXPOSTCURSORINV;
wire delay_TXPRBSFORCEERR;
wire delay_TXPRECURSORINV;
wire delay_TXRATEMODE;
wire delay_TXSTARTSEQ;
wire delay_TXSWING;
wire delay_TXSYNCALLIN;
wire delay_TXSYNCIN;
wire delay_TXSYNCMODE;
wire delay_TXUSERRDY;
wire delay_TXUSRCLK2;
wire delay_TXUSRCLK;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= DRPEN;
drpwe_r1 <= DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((DRPWE === 1'b1) && (DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge DRPCLK)
//end drp monitor
reg [0:0] IS_CLKRSVD0_INVERTED_REG = IS_CLKRSVD0_INVERTED;
reg [0:0] IS_CLKRSVD1_INVERTED_REG = IS_CLKRSVD1_INVERTED;
reg [0:0] IS_DMONITORCLK_INVERTED_REG = IS_DMONITORCLK_INVERTED;
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_RXUSRCLK2_INVERTED_REG = IS_RXUSRCLK2_INVERTED;
reg [0:0] IS_RXUSRCLK_INVERTED_REG = IS_RXUSRCLK_INVERTED;
reg [0:0] IS_SIGVALIDCLK_INVERTED_REG = IS_SIGVALIDCLK_INVERTED;
reg [0:0] IS_TXPHDLYTSTCLK_INVERTED_REG = IS_TXPHDLYTSTCLK_INVERTED;
reg [0:0] IS_TXUSRCLK2_INVERTED_REG = IS_TXUSRCLK2_INVERTED;
reg [0:0] IS_TXUSRCLK_INVERTED_REG = IS_TXUSRCLK_INVERTED;
assign #(OUTCLK_DELAY) RXOUTCLK = delay_RXOUTCLK;
assign #(OUTCLK_DELAY) TXOUTCLK = delay_TXOUTCLK;
assign #(out_delay) DMONITOROUT = delay_DMONITOROUT;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) EYESCANDATAERROR = delay_EYESCANDATAERROR;
assign #(out_delay) GTPTXN = delay_GTPTXN;
assign #(out_delay) GTPTXP = delay_GTPTXP;
assign #(out_delay) PCSRSVDOUT = delay_PCSRSVDOUT;
assign #(out_delay) PHYSTATUS = delay_PHYSTATUS;
assign #(out_delay) PMARSVDOUT0 = delay_PMARSVDOUT0;
assign #(out_delay) PMARSVDOUT1 = delay_PMARSVDOUT1;
assign #(out_delay) RXBUFSTATUS = delay_RXBUFSTATUS;
assign #(out_delay) RXBYTEISALIGNED = delay_RXBYTEISALIGNED;
assign #(out_delay) RXBYTEREALIGN = delay_RXBYTEREALIGN;
assign #(out_delay) RXCDRLOCK = delay_RXCDRLOCK;
assign #(out_delay) RXCHANBONDSEQ = delay_RXCHANBONDSEQ;
assign #(out_delay) RXCHANISALIGNED = delay_RXCHANISALIGNED;
assign #(out_delay) RXCHANREALIGN = delay_RXCHANREALIGN;
assign #(out_delay) RXCHARISCOMMA = delay_RXCHARISCOMMA;
assign #(out_delay) RXCHARISK = delay_RXCHARISK;
assign #(out_delay) RXCHBONDO = delay_RXCHBONDO;
assign #(out_delay) RXCLKCORCNT = delay_RXCLKCORCNT;
assign #(out_delay) RXCOMINITDET = delay_RXCOMINITDET;
assign #(out_delay) RXCOMMADET = delay_RXCOMMADET;
assign #(out_delay) RXCOMSASDET = delay_RXCOMSASDET;
assign #(out_delay) RXCOMWAKEDET = delay_RXCOMWAKEDET;
assign #(out_delay) RXDATA = delay_RXDATA;
assign #(out_delay) RXDATAVALID = delay_RXDATAVALID;
assign #(out_delay) RXDISPERR = delay_RXDISPERR;
assign #(out_delay) RXDLYSRESETDONE = delay_RXDLYSRESETDONE;
assign #(out_delay) RXELECIDLE = delay_RXELECIDLE;
assign #(out_delay) RXHEADER = delay_RXHEADER;
assign #(out_delay) RXHEADERVALID = delay_RXHEADERVALID;
assign #(out_delay) RXNOTINTABLE = delay_RXNOTINTABLE;
assign #(out_delay) RXOSINTDONE = delay_RXOSINTDONE;
assign #(out_delay) RXOSINTSTARTED = delay_RXOSINTSTARTED;
assign #(out_delay) RXOSINTSTROBEDONE = delay_RXOSINTSTROBEDONE;
assign #(out_delay) RXOSINTSTROBESTARTED = delay_RXOSINTSTROBESTARTED;
assign #(out_delay) RXOUTCLKFABRIC = delay_RXOUTCLKFABRIC;
assign #(out_delay) RXOUTCLKPCS = delay_RXOUTCLKPCS;
assign #(out_delay) RXPHALIGNDONE = delay_RXPHALIGNDONE;
assign #(out_delay) RXPHMONITOR = delay_RXPHMONITOR;
assign #(out_delay) RXPHSLIPMONITOR = delay_RXPHSLIPMONITOR;
assign #(out_delay) RXPMARESETDONE = delay_RXPMARESETDONE;
assign #(out_delay) RXPRBSERR = delay_RXPRBSERR;
assign #(out_delay) RXRATEDONE = delay_RXRATEDONE;
assign #(out_delay) RXRESETDONE = delay_RXRESETDONE;
assign #(out_delay) RXSTARTOFSEQ = delay_RXSTARTOFSEQ;
assign #(out_delay) RXSTATUS = delay_RXSTATUS;
assign #(out_delay) RXSYNCDONE = delay_RXSYNCDONE;
assign #(out_delay) RXSYNCOUT = delay_RXSYNCOUT;
assign #(out_delay) RXVALID = delay_RXVALID;
assign #(out_delay) TXBUFSTATUS = delay_TXBUFSTATUS;
assign #(out_delay) TXCOMFINISH = delay_TXCOMFINISH;
assign #(out_delay) TXDLYSRESETDONE = delay_TXDLYSRESETDONE;
assign #(out_delay) TXGEARBOXREADY = delay_TXGEARBOXREADY;
assign #(out_delay) TXOUTCLKFABRIC = delay_TXOUTCLKFABRIC;
assign #(out_delay) TXOUTCLKPCS = delay_TXOUTCLKPCS;
assign #(out_delay) TXPHALIGNDONE = delay_TXPHALIGNDONE;
assign #(out_delay) TXPHINITDONE = delay_TXPHINITDONE;
assign #(out_delay) TXPMARESETDONE = delay_TXPMARESETDONE;
assign #(out_delay) TXRATEDONE = delay_TXRATEDONE;
assign #(out_delay) TXRESETDONE = delay_TXRESETDONE;
assign #(out_delay) TXSYNCDONE = delay_TXSYNCDONE;
assign #(out_delay) TXSYNCOUT = delay_TXSYNCOUT;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_CLKRSVD0 = CLKRSVD0 ^ IS_CLKRSVD0_INVERTED_REG;
assign #(INCLK_DELAY) delay_CLKRSVD1 = CLKRSVD1 ^ IS_CLKRSVD1_INVERTED_REG;
assign #(INCLK_DELAY) delay_DMONITORCLK = DMONITORCLK ^ IS_DMONITORCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_PLL0CLK = PLL0CLK;
assign #(INCLK_DELAY) delay_PLL1CLK = PLL1CLK;
assign #(INCLK_DELAY) delay_RXUSRCLK = RXUSRCLK ^ IS_RXUSRCLK2_INVERTED_REG;
assign #(INCLK_DELAY) delay_RXUSRCLK2 = RXUSRCLK2 ^ IS_RXUSRCLK2_INVERTED_REG;
assign #(INCLK_DELAY) delay_SIGVALIDCLK = SIGVALIDCLK^ IS_SIGVALIDCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXPHDLYTSTCLK = TXPHDLYTSTCLK ^ IS_TXPHDLYTSTCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_TXUSRCLK = TXUSRCLK;
assign #(INCLK_DELAY) delay_TXUSRCLK2 = TXUSRCLK2;
assign #(in_delay) delay_CFGRESET = CFGRESET;
assign #(in_delay) delay_DMONFIFORESET = DMONFIFORESET;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_EYESCANMODE = EYESCANMODE;
assign #(in_delay) delay_EYESCANRESET = EYESCANRESET;
assign #(in_delay) delay_EYESCANTRIGGER = EYESCANTRIGGER;
assign #(in_delay) delay_GTPRXN = GTPRXN;
assign #(in_delay) delay_GTPRXP = GTPRXP;
assign #(in_delay) delay_GTRESETSEL = GTRESETSEL;
assign #(in_delay) delay_GTRSVD = GTRSVD;
assign #(in_delay) delay_GTRXRESET = GTRXRESET;
assign #(in_delay) delay_GTTXRESET = GTTXRESET;
assign #(in_delay) delay_LOOPBACK = LOOPBACK;
assign #(in_delay) delay_PCSRSVDIN = PCSRSVDIN;
assign #(in_delay) delay_PLL0REFCLK = PLL0REFCLK;
assign #(in_delay) delay_PLL1REFCLK = PLL1REFCLK;
assign #(in_delay) delay_PMARSVDIN0 = PMARSVDIN0;
assign #(in_delay) delay_PMARSVDIN1 = PMARSVDIN1;
assign #(in_delay) delay_PMARSVDIN2 = PMARSVDIN2;
assign #(in_delay) delay_PMARSVDIN3 = PMARSVDIN3;
assign #(in_delay) delay_PMARSVDIN4 = PMARSVDIN4;
assign #(in_delay) delay_RESETOVRD = RESETOVRD;
assign #(in_delay) delay_RX8B10BEN = RX8B10BEN;
assign #(in_delay) delay_RXADAPTSELTEST = RXADAPTSELTEST;
assign #(in_delay) delay_RXBUFRESET = RXBUFRESET;
assign #(in_delay) delay_RXCDRFREQRESET = RXCDRFREQRESET;
assign #(in_delay) delay_RXCDRHOLD = RXCDRHOLD;
assign #(in_delay) delay_RXCDROVRDEN = RXCDROVRDEN;
assign #(in_delay) delay_RXCDRRESET = RXCDRRESET;
assign #(in_delay) delay_RXCDRRESETRSV = RXCDRRESETRSV;
assign #(in_delay) delay_RXCHBONDEN = RXCHBONDEN;
assign #(in_delay) delay_RXCHBONDI = RXCHBONDI;
assign #(in_delay) delay_RXCHBONDLEVEL = RXCHBONDLEVEL;
assign #(in_delay) delay_RXCHBONDMASTER = RXCHBONDMASTER;
assign #(in_delay) delay_RXCHBONDSLAVE = RXCHBONDSLAVE;
assign #(in_delay) delay_RXCOMMADETEN = RXCOMMADETEN;
assign #(in_delay) delay_RXDDIEN = RXDDIEN;
assign #(in_delay) delay_RXDFEXYDEN = RXDFEXYDEN;
assign #(in_delay) delay_RXDLYBYPASS = RXDLYBYPASS;
assign #(in_delay) delay_RXDLYEN = RXDLYEN;
assign #(in_delay) delay_RXDLYOVRDEN = RXDLYOVRDEN;
assign #(in_delay) delay_RXDLYSRESET = RXDLYSRESET;
assign #(in_delay) delay_RXELECIDLEMODE = RXELECIDLEMODE;
assign #(in_delay) delay_RXGEARBOXSLIP = RXGEARBOXSLIP;
assign #(in_delay) delay_RXLPMHFHOLD = RXLPMHFHOLD;
assign #(in_delay) delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN;
assign #(in_delay) delay_RXLPMLFHOLD = RXLPMLFHOLD;
assign #(in_delay) delay_RXLPMLFOVRDEN = RXLPMLFOVRDEN;
assign #(in_delay) delay_RXLPMOSINTNTRLEN = RXLPMOSINTNTRLEN;
assign #(in_delay) delay_RXLPMRESET = RXLPMRESET;
assign #(in_delay) delay_RXMCOMMAALIGNEN = RXMCOMMAALIGNEN;
assign #(in_delay) delay_RXOOBRESET = RXOOBRESET;
assign #(in_delay) delay_RXOSCALRESET = RXOSCALRESET;
assign #(in_delay) delay_RXOSHOLD = RXOSHOLD;
assign #(in_delay) delay_RXOSINTCFG = RXOSINTCFG;
assign #(in_delay) delay_RXOSINTEN = RXOSINTEN;
assign #(in_delay) delay_RXOSINTHOLD = RXOSINTHOLD;
assign #(in_delay) delay_RXOSINTID0 = RXOSINTID0;
assign #(in_delay) delay_RXOSINTNTRLEN = RXOSINTNTRLEN;
assign #(in_delay) delay_RXOSINTOVRDEN = RXOSINTOVRDEN;
assign #(in_delay) delay_RXOSINTPD = RXOSINTPD;
assign #(in_delay) delay_RXOSINTSTROBE = RXOSINTSTROBE;
assign #(in_delay) delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN;
assign #(in_delay) delay_RXOSOVRDEN = RXOSOVRDEN;
assign #(in_delay) delay_RXOUTCLKSEL = RXOUTCLKSEL;
assign #(in_delay) delay_RXPCOMMAALIGNEN = RXPCOMMAALIGNEN;
assign #(in_delay) delay_RXPCSRESET = RXPCSRESET;
assign #(in_delay) delay_RXPD = RXPD;
assign #(in_delay) delay_RXPHALIGN = RXPHALIGN;
assign #(in_delay) delay_RXPHALIGNEN = RXPHALIGNEN;
assign #(in_delay) delay_RXPHDLYPD = RXPHDLYPD;
assign #(in_delay) delay_RXPHDLYRESET = RXPHDLYRESET;
assign #(in_delay) delay_RXPHOVRDEN = RXPHOVRDEN;
assign #(in_delay) delay_RXPMARESET = RXPMARESET;
assign #(in_delay) delay_RXPOLARITY = RXPOLARITY;
assign #(in_delay) delay_RXPRBSCNTRESET = RXPRBSCNTRESET;
assign #(in_delay) delay_RXPRBSSEL = RXPRBSSEL;
assign #(in_delay) delay_RXRATE = RXRATE;
assign #(in_delay) delay_RXRATEMODE = RXRATEMODE;
assign #(in_delay) delay_RXSLIDE = RXSLIDE;
assign #(in_delay) delay_RXSYNCALLIN = RXSYNCALLIN;
assign #(in_delay) delay_RXSYNCIN = RXSYNCIN;
assign #(in_delay) delay_RXSYNCMODE = RXSYNCMODE;
assign #(in_delay) delay_RXSYSCLKSEL = RXSYSCLKSEL;
assign #(in_delay) delay_RXUSERRDY = RXUSERRDY;
assign #(in_delay) delay_SETERRSTATUS = SETERRSTATUS;
assign #(in_delay) delay_TSTIN = TSTIN;
assign #(in_delay) delay_TX8B10BBYPASS = TX8B10BBYPASS;
assign #(in_delay) delay_TX8B10BEN = TX8B10BEN;
assign #(in_delay) delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL;
assign #(in_delay) delay_TXCHARDISPMODE = TXCHARDISPMODE;
assign #(in_delay) delay_TXCHARDISPVAL = TXCHARDISPVAL;
assign #(in_delay) delay_TXCHARISK = TXCHARISK;
assign #(in_delay) delay_TXCOMINIT = TXCOMINIT;
assign #(in_delay) delay_TXCOMSAS = TXCOMSAS;
assign #(in_delay) delay_TXCOMWAKE = TXCOMWAKE;
assign #(in_delay) delay_TXDATA = TXDATA;
assign #(in_delay) delay_TXDEEMPH = TXDEEMPH;
assign #(in_delay) delay_TXDETECTRX = TXDETECTRX;
assign #(in_delay) delay_TXDIFFCTRL = TXDIFFCTRL;
assign #(in_delay) delay_TXDIFFPD = TXDIFFPD;
assign #(in_delay) delay_TXDLYBYPASS = TXDLYBYPASS;
assign #(in_delay) delay_TXDLYEN = TXDLYEN;
assign #(in_delay) delay_TXDLYHOLD = TXDLYHOLD;
assign #(in_delay) delay_TXDLYOVRDEN = TXDLYOVRDEN;
assign #(in_delay) delay_TXDLYSRESET = TXDLYSRESET;
assign #(in_delay) delay_TXDLYUPDOWN = TXDLYUPDOWN;
assign #(in_delay) delay_TXELECIDLE = TXELECIDLE;
assign #(in_delay) delay_TXHEADER = TXHEADER;
assign #(in_delay) delay_TXINHIBIT = TXINHIBIT;
assign #(in_delay) delay_TXMAINCURSOR = TXMAINCURSOR;
assign #(in_delay) delay_TXMARGIN = TXMARGIN;
assign #(in_delay) delay_TXOUTCLKSEL = TXOUTCLKSEL;
assign #(in_delay) delay_TXPCSRESET = TXPCSRESET;
assign #(in_delay) delay_TXPD = TXPD;
assign #(in_delay) delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE;
assign #(in_delay) delay_TXPHALIGN = TXPHALIGN;
assign #(in_delay) delay_TXPHALIGNEN = TXPHALIGNEN;
assign #(in_delay) delay_TXPHDLYPD = TXPHDLYPD;
assign #(in_delay) delay_TXPHDLYRESET = TXPHDLYRESET;
assign #(in_delay) delay_TXPHINIT = TXPHINIT;
assign #(in_delay) delay_TXPHOVRDEN = TXPHOVRDEN;
assign #(in_delay) delay_TXPIPPMEN = TXPIPPMEN;
assign #(in_delay) delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN;
assign #(in_delay) delay_TXPIPPMPD = TXPIPPMPD;
assign #(in_delay) delay_TXPIPPMSEL = TXPIPPMSEL;
assign #(in_delay) delay_TXPIPPMSTEPSIZE = TXPIPPMSTEPSIZE;
assign #(in_delay) delay_TXPISOPD = TXPISOPD;
assign #(in_delay) delay_TXPMARESET = TXPMARESET;
assign #(in_delay) delay_TXPOLARITY = TXPOLARITY;
assign #(in_delay) delay_TXPOSTCURSOR = TXPOSTCURSOR;
assign #(in_delay) delay_TXPOSTCURSORINV = TXPOSTCURSORINV;
assign #(in_delay) delay_TXPRBSFORCEERR = TXPRBSFORCEERR;
assign #(in_delay) delay_TXPRBSSEL = TXPRBSSEL;
assign #(in_delay) delay_TXPRECURSOR = TXPRECURSOR;
assign #(in_delay) delay_TXPRECURSORINV = TXPRECURSORINV;
assign #(in_delay) delay_TXRATE = TXRATE;
assign #(in_delay) delay_TXRATEMODE = TXRATEMODE;
assign #(in_delay) delay_TXSEQUENCE = TXSEQUENCE;
assign #(in_delay) delay_TXSTARTSEQ = TXSTARTSEQ;
assign #(in_delay) delay_TXSWING = TXSWING;
assign #(in_delay) delay_TXSYNCALLIN = TXSYNCALLIN;
assign #(in_delay) delay_TXSYNCIN = TXSYNCIN;
assign #(in_delay) delay_TXSYNCMODE = TXSYNCMODE;
assign #(in_delay) delay_TXSYSCLKSEL = TXSYSCLKSEL;
assign #(in_delay) delay_TXUSERRDY = TXUSERRDY;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_CFGRESET = CFGRESET;
assign delay_CLKRSVD0 = CLKRSVD0;
assign delay_CLKRSVD1 = CLKRSVD1;
assign delay_DMONFIFORESET = DMONFIFORESET;
assign delay_DMONITORCLK = DMONITORCLK;
assign delay_EYESCANMODE = EYESCANMODE;
assign delay_EYESCANRESET = EYESCANRESET;
assign delay_EYESCANTRIGGER = EYESCANTRIGGER;
assign delay_GTPRXN = GTPRXN;
assign delay_GTPRXP = GTPRXP;
assign delay_GTRESETSEL = GTRESETSEL;
assign delay_GTRSVD = GTRSVD;
assign delay_GTRXRESET = GTRXRESET;
assign delay_GTTXRESET = GTTXRESET;
assign delay_LOOPBACK = LOOPBACK;
assign delay_PCSRSVDIN = PCSRSVDIN;
assign delay_PLL0CLK = PLL0CLK;
assign delay_PLL0REFCLK = PLL0REFCLK;
assign delay_PLL1CLK = PLL1CLK;
assign delay_PLL1REFCLK = PLL1REFCLK;
assign delay_PMARSVDIN0 = PMARSVDIN0;
assign delay_PMARSVDIN1 = PMARSVDIN1;
assign delay_PMARSVDIN2 = PMARSVDIN2;
assign delay_PMARSVDIN3 = PMARSVDIN3;
assign delay_PMARSVDIN4 = PMARSVDIN4;
assign delay_RESETOVRD = RESETOVRD;
assign delay_RXADAPTSELTEST = RXADAPTSELTEST;
assign delay_RXBUFRESET = RXBUFRESET;
assign delay_RXCDRFREQRESET = RXCDRFREQRESET;
assign delay_RXCDRHOLD = RXCDRHOLD;
assign delay_RXCDROVRDEN = RXCDROVRDEN;
assign delay_RXCDRRESET = RXCDRRESET;
assign delay_RXCDRRESETRSV = RXCDRRESETRSV;
assign delay_RXCHBONDI = RXCHBONDI;
assign delay_RXDDIEN = RXDDIEN;
assign delay_RXDFEXYDEN = RXDFEXYDEN;
assign delay_RXDLYBYPASS = RXDLYBYPASS;
assign delay_RXDLYEN = RXDLYEN;
assign delay_RXDLYOVRDEN = RXDLYOVRDEN;
assign delay_RXDLYSRESET = RXDLYSRESET;
assign delay_RXELECIDLEMODE = RXELECIDLEMODE;
assign delay_RXLPMHFHOLD = RXLPMHFHOLD;
assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN;
assign delay_RXLPMLFHOLD = RXLPMLFHOLD;
assign delay_RXLPMLFOVRDEN = RXLPMLFOVRDEN;
assign delay_RXLPMOSINTNTRLEN = RXLPMOSINTNTRLEN;
assign delay_RXLPMRESET = RXLPMRESET;
assign delay_RXOOBRESET = RXOOBRESET;
assign delay_RXOSCALRESET = RXOSCALRESET;
assign delay_RXOSHOLD = RXOSHOLD;
assign delay_RXOSINTCFG = RXOSINTCFG;
assign delay_RXOSINTEN = RXOSINTEN;
assign delay_RXOSINTHOLD = RXOSINTHOLD;
assign delay_RXOSINTID0 = RXOSINTID0;
assign delay_RXOSINTNTRLEN = RXOSINTNTRLEN;
assign delay_RXOSINTOVRDEN = RXOSINTOVRDEN;
assign delay_RXOSINTPD = RXOSINTPD;
assign delay_RXOSINTSTROBE = RXOSINTSTROBE;
assign delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN;
assign delay_RXOSOVRDEN = RXOSOVRDEN;
assign delay_RXOUTCLKSEL = RXOUTCLKSEL;
assign delay_RXPCSRESET = RXPCSRESET;
assign delay_RXPD = RXPD;
assign delay_RXPHALIGN = RXPHALIGN;
assign delay_RXPHALIGNEN = RXPHALIGNEN;
assign delay_RXPHDLYPD = RXPHDLYPD;
assign delay_RXPHDLYRESET = RXPHDLYRESET;
assign delay_RXPHOVRDEN = RXPHOVRDEN;
assign delay_RXPMARESET = RXPMARESET;
assign delay_RXRATEMODE = RXRATEMODE;
assign delay_RXSYNCALLIN = RXSYNCALLIN;
assign delay_RXSYNCIN = RXSYNCIN;
assign delay_RXSYNCMODE = RXSYNCMODE;
assign delay_RXSYSCLKSEL = RXSYSCLKSEL;
assign delay_RXUSERRDY = RXUSERRDY;
assign delay_SIGVALIDCLK = SIGVALIDCLK;
assign delay_TSTIN = TSTIN;
assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL;
assign delay_TXDEEMPH = TXDEEMPH;
assign delay_TXDIFFCTRL = TXDIFFCTRL;
assign delay_TXDIFFPD = TXDIFFPD;
assign delay_TXDLYBYPASS = TXDLYBYPASS;
assign delay_TXDLYEN = TXDLYEN;
assign delay_TXDLYOVRDEN = TXDLYOVRDEN;
assign delay_TXDLYSRESET = TXDLYSRESET;
assign delay_TXMAINCURSOR = TXMAINCURSOR;
assign delay_TXMARGIN = TXMARGIN;
assign delay_TXOUTCLKSEL = TXOUTCLKSEL;
assign delay_TXPCSRESET = TXPCSRESET;
assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE;
assign delay_TXPHALIGN = TXPHALIGN;
assign delay_TXPHALIGNEN = TXPHALIGNEN;
assign delay_TXPHDLYPD = TXPHDLYPD;
assign delay_TXPHDLYRESET = TXPHDLYRESET;
assign delay_TXPHINIT = TXPHINIT;
assign delay_TXPHOVRDEN = TXPHOVRDEN;
assign delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN;
assign delay_TXPIPPMPD = TXPIPPMPD;
assign delay_TXPIPPMSEL = TXPIPPMSEL;
assign delay_TXPISOPD = TXPISOPD;
assign delay_TXPMARESET = TXPMARESET;
assign delay_TXPOSTCURSOR = TXPOSTCURSOR;
assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV;
assign delay_TXPRECURSOR = TXPRECURSOR;
assign delay_TXPRECURSORINV = TXPRECURSORINV;
assign delay_TXRATEMODE = TXRATEMODE;
assign delay_TXSWING = TXSWING;
assign delay_TXSYNCALLIN = TXSYNCALLIN;
assign delay_TXSYNCIN = TXSYNCIN;
assign delay_TXSYNCMODE = TXSYNCMODE;
assign delay_TXSYSCLKSEL = TXSYSCLKSEL;
assign delay_TXUSERRDY = TXUSERRDY;
wire drpclk_en_p;
wire drpclk_en_n;
wire rxusrclk2_en_p;
wire rxusrclk2_en_n;
wire rxusrclk_en_p;
wire rxusrclk_en_n;
wire txphdlytstclk_en_p;
wire txphdlytstclk_en_n;
wire txusrclk2_en_p;
wire txusrclk2_en_n;
wire txusrclk_en_p;
wire txusrclk_en_n;
assign drpclk_en_p = ~IS_DRPCLK_INVERTED;
assign drpclk_en_n = IS_DRPCLK_INVERTED;
assign rxusrclk2_en_p = ~IS_RXUSRCLK2_INVERTED;
assign rxusrclk2_en_n = IS_RXUSRCLK2_INVERTED;
assign rxusrclk_en_p = ~IS_RXUSRCLK_INVERTED;
assign rxusrclk_en_n = IS_RXUSRCLK_INVERTED;
assign txphdlytstclk_en_p = ~IS_TXPHDLYTSTCLK_INVERTED;
assign txphdlytstclk_en_n = IS_TXPHDLYTSTCLK_INVERTED;
assign txusrclk2_en_p = ~IS_TXUSRCLK2_INVERTED;
assign txusrclk2_en_n = IS_TXUSRCLK2_INVERTED;
assign txusrclk_en_p = ~IS_TXUSRCLK_INVERTED;
assign txusrclk_en_n = IS_TXUSRCLK_INVERTED;
`endif
B_GTPE2_CHANNEL #(
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE),
.ACJTAG_MODE (ACJTAG_MODE),
.ACJTAG_RESET (ACJTAG_RESET),
.ADAPT_CFG0 (ADAPT_CFG0),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
.CFOK_CFG (CFOK_CFG),
.CFOK_CFG2 (CFOK_CFG2),
.CFOK_CFG3 (CFOK_CFG3),
.CFOK_CFG4 (CFOK_CFG4),
.CFOK_CFG5 (CFOK_CFG5),
.CFOK_CFG6 (CFOK_CFG6),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN),
.CLK_COMMON_SWING (CLK_COMMON_SWING),
.CLK_CORRECT_USE (CLK_CORRECT_USE),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY),
.DMONITOR_CFG (DMONITOR_CFG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL),
.ES_CONTROL (ES_CONTROL),
.ES_ERRDET_EN (ES_ERRDET_EN),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET),
.ES_PMA_CFG (ES_PMA_CFG),
.ES_PRESCALE (ES_PRESCALE),
.ES_QUALIFIER (ES_QUALIFIER),
.ES_QUAL_MASK (ES_QUAL_MASK),
.ES_SDATA_MASK (ES_SDATA_MASK),
.ES_VERT_OFFSET (ES_VERT_OFFSET),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN),
.GEARBOX_MODE (GEARBOX_MODE),
.LOOPBACK_CFG (LOOPBACK_CFG),
.OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV),
.PCS_PCIE_EN (PCS_PCIE_EN),
.PCS_RSVD_ATTR (PCS_RSVD_ATTR),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2),
.PMA_LOOPBACK_CFG (PMA_LOOPBACK_CFG),
.PMA_RSV (PMA_RSV),
.PMA_RSV2 (PMA_RSV2),
.PMA_RSV3 (PMA_RSV3),
.PMA_RSV4 (PMA_RSV4),
.PMA_RSV5 (PMA_RSV5),
.PMA_RSV6 (PMA_RSV6),
.PMA_RSV7 (PMA_RSV7),
.RXBUFRESET_TIME (RXBUFRESET_TIME),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT),
.RXBUF_EN (RXBUF_EN),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDR_CFG (RXCDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE),
.RXCDR_LOCK_CFG (RXCDR_LOCK_CFG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE),
.RXDLY_CFG (RXDLY_CFG),
.RXDLY_LCFG (RXDLY_LCFG),
.RXDLY_TAP_CFG (RXDLY_TAP_CFG),
.RXGEARBOX_EN (RXGEARBOX_EN),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXLPMRESET_TIME (RXLPMRESET_TIME),
.RXLPM_BIAS_STARTUP_DISABLE (RXLPM_BIAS_STARTUP_DISABLE),
.RXLPM_CFG (RXLPM_CFG),
.RXLPM_CFG1 (RXLPM_CFG1),
.RXLPM_CM_CFG (RXLPM_CM_CFG),
.RXLPM_GC_CFG (RXLPM_GC_CFG),
.RXLPM_GC_CFG2 (RXLPM_GC_CFG2),
.RXLPM_HF_CFG (RXLPM_HF_CFG),
.RXLPM_HF_CFG2 (RXLPM_HF_CFG2),
.RXLPM_HF_CFG3 (RXLPM_HF_CFG3),
.RXLPM_HOLD_DURING_EIDLE (RXLPM_HOLD_DURING_EIDLE),
.RXLPM_INCM_CFG (RXLPM_INCM_CFG),
.RXLPM_IPCM_CFG (RXLPM_IPCM_CFG),
.RXLPM_LF_CFG (RXLPM_LF_CFG),
.RXLPM_LF_CFG2 (RXLPM_LF_CFG2),
.RXLPM_OSINT_CFG (RXLPM_OSINT_CFG),
.RXOOB_CFG (RXOOB_CFG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME),
.RXOSCALRESET_TIMEOUT (RXOSCALRESET_TIMEOUT),
.RXOUT_DIV (RXOUT_DIV),
.RXPCSRESET_TIME (RXPCSRESET_TIME),
.RXPHDLY_CFG (RXPHDLY_CFG),
.RXPH_CFG (RXPH_CFG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RXPI_CFG2 (RXPI_CFG2),
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RXSLIDE_MODE (RXSLIDE_MODE),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE),
.RXSYNC_OVRD (RXSYNC_OVRD),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA),
.RX_BIAS_CFG (RX_BIAS_CFG),
.RX_BUFFER_CFG (RX_BUFFER_CFG),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (RX_CLKMUX_EN),
.RX_CM_SEL (RX_CM_SEL),
.RX_CM_TRIM (RX_CM_TRIM),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_DDI_SEL (RX_DDI_SEL),
.RX_DEBUG_CFG (RX_DEBUG_CFG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH),
.RX_OS_CFG (RX_OS_CFG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY),
.RX_XCLK_SEL (RX_XCLK_SEL),
.SAS_MAX_COM (SAS_MAX_COM),
.SAS_MIN_COM (SAS_MIN_COM),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_BURST_VAL (SATA_BURST_VAL),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL),
.SATA_MAX_BURST (SATA_MAX_BURST),
.SATA_MAX_INIT (SATA_MAX_INIT),
.SATA_MAX_WAKE (SATA_MAX_WAKE),
.SATA_MIN_BURST (SATA_MIN_BURST),
.SATA_MIN_INIT (SATA_MIN_INIT),
.SATA_MIN_WAKE (SATA_MIN_WAKE),
.SATA_PLL_CFG (SATA_PLL_CFG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION),
.TERM_RCAL_CFG (TERM_RCAL_CFG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD),
.TRANS_TIME_RATE (TRANS_TIME_RATE),
.TST_RSV (TST_RSV),
.TXBUF_EN (TXBUF_EN),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE),
.TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG),
.TXGEARBOX_EN (TXGEARBOX_EN),
.TXOOB_CFG (TXOOB_CFG),
.TXOUT_DIV (TXOUT_DIV),
.TXPCSRESET_TIME (TXPCSRESET_TIME),
.TXPHDLY_CFG (TXPHDLY_CFG),
.TXPH_CFG (TXPH_CFG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL),
.TXPI_CFG0 (TXPI_CFG0),
.TXPI_CFG1 (TXPI_CFG1),
.TXPI_CFG2 (TXPI_CFG2),
.TXPI_CFG3 (TXPI_CFG3),
.TXPI_CFG4 (TXPI_CFG4),
.TXPI_CFG5 (TXPI_CFG5),
.TXPI_GREY_SEL (TXPI_GREY_SEL),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL),
.TXPI_PPM_CFG (TXPI_PPM_CFG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM),
.TXPMARESET_TIME (TXPMARESET_TIME),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE),
.TXSYNC_OVRD (TXSYNC_OVRD),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (TX_CLKMUX_EN),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_DEEMPH0 (TX_DEEMPH0),
.TX_DEEMPH1 (TX_DEEMPH1),
.TX_DRIVE_MODE (TX_DRIVE_MODE),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.TX_PREDRIVER_MODE (TX_PREDRIVER_MODE),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
.TX_RXDETECT_REF (TX_RXDETECT_REF),
.TX_XCLK_SEL (TX_XCLK_SEL),
.UCODEER_CLR (UCODEER_CLR),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL))
B_GTPE2_CHANNEL_INST (
.DMONITOROUT (delay_DMONITOROUT),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.EYESCANDATAERROR (delay_EYESCANDATAERROR),
.GTPTXN (delay_GTPTXN),
.GTPTXP (delay_GTPTXP),
.PCSRSVDOUT (delay_PCSRSVDOUT),
.PHYSTATUS (delay_PHYSTATUS),
.PMARSVDOUT0 (delay_PMARSVDOUT0),
.PMARSVDOUT1 (delay_PMARSVDOUT1),
.RXBUFSTATUS (delay_RXBUFSTATUS),
.RXBYTEISALIGNED (delay_RXBYTEISALIGNED),
.RXBYTEREALIGN (delay_RXBYTEREALIGN),
.RXCDRLOCK (delay_RXCDRLOCK),
.RXCHANBONDSEQ (delay_RXCHANBONDSEQ),
.RXCHANISALIGNED (delay_RXCHANISALIGNED),
.RXCHANREALIGN (delay_RXCHANREALIGN),
.RXCHARISCOMMA (delay_RXCHARISCOMMA),
.RXCHARISK (delay_RXCHARISK),
.RXCHBONDO (delay_RXCHBONDO),
.RXCLKCORCNT (delay_RXCLKCORCNT),
.RXCOMINITDET (delay_RXCOMINITDET),
.RXCOMMADET (delay_RXCOMMADET),
.RXCOMSASDET (delay_RXCOMSASDET),
.RXCOMWAKEDET (delay_RXCOMWAKEDET),
.RXDATA (delay_RXDATA),
.RXDATAVALID (delay_RXDATAVALID),
.RXDISPERR (delay_RXDISPERR),
.RXDLYSRESETDONE (delay_RXDLYSRESETDONE),
.RXELECIDLE (delay_RXELECIDLE),
.RXHEADER (delay_RXHEADER),
.RXHEADERVALID (delay_RXHEADERVALID),
.RXNOTINTABLE (delay_RXNOTINTABLE),
.RXOSINTDONE (delay_RXOSINTDONE),
.RXOSINTSTARTED (delay_RXOSINTSTARTED),
.RXOSINTSTROBEDONE (delay_RXOSINTSTROBEDONE),
.RXOSINTSTROBESTARTED (delay_RXOSINTSTROBESTARTED),
.RXOUTCLK (delay_RXOUTCLK),
.RXOUTCLKFABRIC (delay_RXOUTCLKFABRIC),
.RXOUTCLKPCS (delay_RXOUTCLKPCS),
.RXPHALIGNDONE (delay_RXPHALIGNDONE),
.RXPHMONITOR (delay_RXPHMONITOR),
.RXPHSLIPMONITOR (delay_RXPHSLIPMONITOR),
.RXPMARESETDONE (delay_RXPMARESETDONE),
.RXPRBSERR (delay_RXPRBSERR),
.RXRATEDONE (delay_RXRATEDONE),
.RXRESETDONE (delay_RXRESETDONE),
.RXSTARTOFSEQ (delay_RXSTARTOFSEQ),
.RXSTATUS (delay_RXSTATUS),
.RXSYNCDONE (delay_RXSYNCDONE),
.RXSYNCOUT (delay_RXSYNCOUT),
.RXVALID (delay_RXVALID),
.TXBUFSTATUS (delay_TXBUFSTATUS),
.TXCOMFINISH (delay_TXCOMFINISH),
.TXDLYSRESETDONE (delay_TXDLYSRESETDONE),
.TXGEARBOXREADY (delay_TXGEARBOXREADY),
.TXOUTCLK (delay_TXOUTCLK),
.TXOUTCLKFABRIC (delay_TXOUTCLKFABRIC),
.TXOUTCLKPCS (delay_TXOUTCLKPCS),
.TXPHALIGNDONE (delay_TXPHALIGNDONE),
.TXPHINITDONE (delay_TXPHINITDONE),
.TXPMARESETDONE (delay_TXPMARESETDONE),
.TXRATEDONE (delay_TXRATEDONE),
.TXRESETDONE (delay_TXRESETDONE),
.TXSYNCDONE (delay_TXSYNCDONE),
.TXSYNCOUT (delay_TXSYNCOUT),
.CFGRESET (delay_CFGRESET),
.CLKRSVD0 (delay_CLKRSVD0),
.CLKRSVD1 (delay_CLKRSVD1),
.DMONFIFORESET (delay_DMONFIFORESET),
.DMONITORCLK (delay_DMONITORCLK),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.EYESCANMODE (delay_EYESCANMODE),
.EYESCANRESET (delay_EYESCANRESET),
.EYESCANTRIGGER (delay_EYESCANTRIGGER),
.GTPRXN (delay_GTPRXN),
.GTPRXP (delay_GTPRXP),
.GTRESETSEL (delay_GTRESETSEL),
.GTRSVD (delay_GTRSVD),
.GTRXRESET (delay_GTRXRESET),
.GTTXRESET (delay_GTTXRESET),
.LOOPBACK (delay_LOOPBACK),
.PCSRSVDIN (delay_PCSRSVDIN),
.PLL0CLK (delay_PLL0CLK),
.PLL0REFCLK (delay_PLL0REFCLK),
.PLL1CLK (delay_PLL1CLK),
.PLL1REFCLK (delay_PLL1REFCLK),
.PMARSVDIN0 (delay_PMARSVDIN0),
.PMARSVDIN1 (delay_PMARSVDIN1),
.PMARSVDIN2 (delay_PMARSVDIN2),
.PMARSVDIN3 (delay_PMARSVDIN3),
.PMARSVDIN4 (delay_PMARSVDIN4),
.RESETOVRD (delay_RESETOVRD),
.RX8B10BEN (delay_RX8B10BEN),
.RXADAPTSELTEST (delay_RXADAPTSELTEST),
.RXBUFRESET (delay_RXBUFRESET),
.RXCDRFREQRESET (delay_RXCDRFREQRESET),
.RXCDRHOLD (delay_RXCDRHOLD),
.RXCDROVRDEN (delay_RXCDROVRDEN),
.RXCDRRESET (delay_RXCDRRESET),
.RXCDRRESETRSV (delay_RXCDRRESETRSV),
.RXCHBONDEN (delay_RXCHBONDEN),
.RXCHBONDI (delay_RXCHBONDI),
.RXCHBONDLEVEL (delay_RXCHBONDLEVEL),
.RXCHBONDMASTER (delay_RXCHBONDMASTER),
.RXCHBONDSLAVE (delay_RXCHBONDSLAVE),
.RXCOMMADETEN (delay_RXCOMMADETEN),
.RXDDIEN (delay_RXDDIEN),
.RXDFEXYDEN (delay_RXDFEXYDEN),
.RXDLYBYPASS (delay_RXDLYBYPASS),
.RXDLYEN (delay_RXDLYEN),
.RXDLYOVRDEN (delay_RXDLYOVRDEN),
.RXDLYSRESET (delay_RXDLYSRESET),
.RXELECIDLEMODE (delay_RXELECIDLEMODE),
.RXGEARBOXSLIP (delay_RXGEARBOXSLIP),
.RXLPMHFHOLD (delay_RXLPMHFHOLD),
.RXLPMHFOVRDEN (delay_RXLPMHFOVRDEN),
.RXLPMLFHOLD (delay_RXLPMLFHOLD),
.RXLPMLFOVRDEN (delay_RXLPMLFOVRDEN),
.RXLPMOSINTNTRLEN (delay_RXLPMOSINTNTRLEN),
.RXLPMRESET (delay_RXLPMRESET),
.RXMCOMMAALIGNEN (delay_RXMCOMMAALIGNEN),
.RXOOBRESET (delay_RXOOBRESET),
.RXOSCALRESET (delay_RXOSCALRESET),
.RXOSHOLD (delay_RXOSHOLD),
.RXOSINTCFG (delay_RXOSINTCFG),
.RXOSINTEN (delay_RXOSINTEN),
.RXOSINTHOLD (delay_RXOSINTHOLD),
.RXOSINTID0 (delay_RXOSINTID0),
.RXOSINTNTRLEN (delay_RXOSINTNTRLEN),
.RXOSINTOVRDEN (delay_RXOSINTOVRDEN),
.RXOSINTPD (delay_RXOSINTPD),
.RXOSINTSTROBE (delay_RXOSINTSTROBE),
.RXOSINTTESTOVRDEN (delay_RXOSINTTESTOVRDEN),
.RXOSOVRDEN (delay_RXOSOVRDEN),
.RXOUTCLKSEL (delay_RXOUTCLKSEL),
.RXPCOMMAALIGNEN (delay_RXPCOMMAALIGNEN),
.RXPCSRESET (delay_RXPCSRESET),
.RXPD (delay_RXPD),
.RXPHALIGN (delay_RXPHALIGN),
.RXPHALIGNEN (delay_RXPHALIGNEN),
.RXPHDLYPD (delay_RXPHDLYPD),
.RXPHDLYRESET (delay_RXPHDLYRESET),
.RXPHOVRDEN (delay_RXPHOVRDEN),
.RXPMARESET (delay_RXPMARESET),
.RXPOLARITY (delay_RXPOLARITY),
.RXPRBSCNTRESET (delay_RXPRBSCNTRESET),
.RXPRBSSEL (delay_RXPRBSSEL),
.RXRATE (delay_RXRATE),
.RXRATEMODE (delay_RXRATEMODE),
.RXSLIDE (delay_RXSLIDE),
.RXSYNCALLIN (delay_RXSYNCALLIN),
.RXSYNCIN (delay_RXSYNCIN),
.RXSYNCMODE (delay_RXSYNCMODE),
.RXSYSCLKSEL (delay_RXSYSCLKSEL),
.RXUSERRDY (delay_RXUSERRDY),
.RXUSRCLK (delay_RXUSRCLK),
.RXUSRCLK2 (delay_RXUSRCLK2),
.SETERRSTATUS (delay_SETERRSTATUS),
.SIGVALIDCLK (delay_SIGVALIDCLK),
.TSTIN (delay_TSTIN),
.TX8B10BBYPASS (delay_TX8B10BBYPASS),
.TX8B10BEN (delay_TX8B10BEN),
.TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL),
.TXCHARDISPMODE (delay_TXCHARDISPMODE),
.TXCHARDISPVAL (delay_TXCHARDISPVAL),
.TXCHARISK (delay_TXCHARISK),
.TXCOMINIT (delay_TXCOMINIT),
.TXCOMSAS (delay_TXCOMSAS),
.TXCOMWAKE (delay_TXCOMWAKE),
.TXDATA (delay_TXDATA),
.TXDEEMPH (delay_TXDEEMPH),
.TXDETECTRX (delay_TXDETECTRX),
.TXDIFFCTRL (delay_TXDIFFCTRL),
.TXDIFFPD (delay_TXDIFFPD),
.TXDLYBYPASS (delay_TXDLYBYPASS),
.TXDLYEN (delay_TXDLYEN),
.TXDLYHOLD (delay_TXDLYHOLD),
.TXDLYOVRDEN (delay_TXDLYOVRDEN),
.TXDLYSRESET (delay_TXDLYSRESET),
.TXDLYUPDOWN (delay_TXDLYUPDOWN),
.TXELECIDLE (delay_TXELECIDLE),
.TXHEADER (delay_TXHEADER),
.TXINHIBIT (delay_TXINHIBIT),
.TXMAINCURSOR (delay_TXMAINCURSOR),
.TXMARGIN (delay_TXMARGIN),
.TXOUTCLKSEL (delay_TXOUTCLKSEL),
.TXPCSRESET (delay_TXPCSRESET),
.TXPD (delay_TXPD),
.TXPDELECIDLEMODE (delay_TXPDELECIDLEMODE),
.TXPHALIGN (delay_TXPHALIGN),
.TXPHALIGNEN (delay_TXPHALIGNEN),
.TXPHDLYPD (delay_TXPHDLYPD),
.TXPHDLYRESET (delay_TXPHDLYRESET),
.TXPHDLYTSTCLK (delay_TXPHDLYTSTCLK),
.TXPHINIT (delay_TXPHINIT),
.TXPHOVRDEN (delay_TXPHOVRDEN),
.TXPIPPMEN (delay_TXPIPPMEN),
.TXPIPPMOVRDEN (delay_TXPIPPMOVRDEN),
.TXPIPPMPD (delay_TXPIPPMPD),
.TXPIPPMSEL (delay_TXPIPPMSEL),
.TXPIPPMSTEPSIZE (delay_TXPIPPMSTEPSIZE),
.TXPISOPD (delay_TXPISOPD),
.TXPMARESET (delay_TXPMARESET),
.TXPOLARITY (delay_TXPOLARITY),
.TXPOSTCURSOR (delay_TXPOSTCURSOR),
.TXPOSTCURSORINV (delay_TXPOSTCURSORINV),
.TXPRBSFORCEERR (delay_TXPRBSFORCEERR),
.TXPRBSSEL (delay_TXPRBSSEL),
.TXPRECURSOR (delay_TXPRECURSOR),
.TXPRECURSORINV (delay_TXPRECURSORINV),
.TXRATE (delay_TXRATE),
.TXRATEMODE (delay_TXRATEMODE),
.TXSEQUENCE (delay_TXSEQUENCE),
.TXSTARTSEQ (delay_TXSTARTSEQ),
.TXSWING (delay_TXSWING),
.TXSYNCALLIN (delay_TXSYNCALLIN),
.TXSYNCIN (delay_TXSYNCIN),
.TXSYNCMODE (delay_TXSYNCMODE),
.TXSYSCLKSEL (delay_TXSYSCLKSEL),
.TXUSERRDY (delay_TXUSERRDY),
.TXUSRCLK (delay_TXUSRCLK),
.TXUSRCLK2 (delay_TXUSRCLK2),
.GSR (GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge CLKRSVD0, 0:0:0, notifier);
$period (negedge CLKRSVD0, 0:0:0, notifier);
$period (posedge CLKRSVD1, 0:0:0, notifier);
$period (negedge CLKRSVD1, 0:0:0, notifier);
$period (posedge DMONITORCLK, 0:0:0, notifier);
$period (negedge DMONITORCLK, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$period (negedge DRPCLK, 0:0:0, notifier);
$period (posedge PLL0CLK, 0:0:0, notifier);
$period (posedge PLL1CLK, 0:0:0, notifier);
$period (posedge RXOUTCLK, 0:0:0, notifier);
$period (posedge RXOUTCLKFABRIC, 0:0:0, notifier);
$period (posedge RXOUTCLKPCS, 0:0:0, notifier);
$period (posedge RXUSRCLK, 0:0:0, notifier);
$period (negedge RXUSRCLK, 0:0:0, notifier);
$period (posedge RXUSRCLK2, 0:0:0, notifier);
$period (negedge RXUSRCLK2, 0:0:0, notifier);
$period (posedge SIGVALIDCLK, 0:0:0, notifier);
$period (negedge SIGVALIDCLK, 0:0:0, notifier);
$period (posedge TXOUTCLK, 0:0:0, notifier);
$period (posedge TXOUTCLKFABRIC, 0:0:0, notifier);
$period (posedge TXOUTCLKPCS, 0:0:0, notifier);
$period (posedge TXPHDLYTSTCLK, 0:0:0, notifier);
$period (negedge TXPHDLYTSTCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK, 0:0:0, notifier);
$period (negedge TXUSRCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK2, 0:0:0, notifier);
$period (negedge TXUSRCLK2, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE);
$setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR);
$setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI);
$setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN);
$setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE);
$setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR);
$setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI);
$setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN);
$setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_p, rxusrclk_en_p, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_p, rxusrclk_en_p, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (negedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_n, rxusrclk_en_n, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (negedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk_en_n, rxusrclk_en_n, delay_RXUSRCLK, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (posedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (posedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_p, rxusrclk2_en_p, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (negedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (negedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDI);
$setuphold (negedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (negedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (negedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (negedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (negedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (negedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (negedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (negedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (negedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (negedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (negedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (negedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (negedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (negedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (negedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (negedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RX8B10BEN);
$setuphold (negedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDEN);
$setuphold (negedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDLEVEL);
$setuphold (negedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDMASTER);
$setuphold (negedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCHBONDSLAVE);
$setuphold (negedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXCOMMADETEN);
$setuphold (negedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXGEARBOXSLIP);
$setuphold (negedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN);
$setuphold (negedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN);
$setuphold (negedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPOLARITY);
$setuphold (negedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSCNTRESET);
$setuphold (negedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXPRBSSEL);
$setuphold (negedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXRATE);
$setuphold (negedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_RXSLIDE);
$setuphold (negedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier, rxusrclk2_en_n, rxusrclk2_en_n, delay_RXUSRCLK2, delay_SETERRSTATUS);
$setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_p, txphdlytstclk_en_p, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD);
$setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier, txphdlytstclk_en_n, txphdlytstclk_en_n, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_p, txusrclk_en_p, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE);
$setuphold (negedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMEN);
$setuphold (negedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE);
$setuphold (negedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMEN);
$setuphold (negedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk_en_n, txusrclk_en_n, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (posedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (posedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (posedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPD);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (posedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSTARTSEQ);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (posedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (posedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (posedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPD);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMEN);
$setuphold (posedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (posedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_p, txusrclk2_en_p, delay_TXUSRCLK2, delay_TXSTARTSEQ);
$setuphold (negedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (negedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (negedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (negedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (negedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (negedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (negedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (negedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (negedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (negedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (negedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (negedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (negedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (negedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPD);
$setuphold (negedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMEN);
$setuphold (negedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE);
$setuphold (negedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (negedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (negedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (negedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (negedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (negedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSTARTSEQ);
$setuphold (negedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BBYPASS);
$setuphold (negedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TX8B10BEN);
$setuphold (negedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPMODE);
$setuphold (negedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARDISPVAL);
$setuphold (negedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCHARISK);
$setuphold (negedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMINIT);
$setuphold (negedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMSAS);
$setuphold (negedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXCOMWAKE);
$setuphold (negedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDATA);
$setuphold (negedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXDETECTRX);
$setuphold (negedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXELECIDLE);
$setuphold (negedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXHEADER);
$setuphold (negedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXINHIBIT);
$setuphold (negedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPD);
$setuphold (negedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMEN);
$setuphold (negedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE);
$setuphold (negedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPOLARITY);
$setuphold (negedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSFORCEERR);
$setuphold (negedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXPRBSSEL);
$setuphold (negedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXRATE);
$setuphold (negedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSEQUENCE);
$setuphold (negedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier, txusrclk2_en_n, txusrclk2_en_n, delay_TXUSRCLK2, delay_TXSTARTSEQ);
`endif
( DMONITORCLK *> DMONITOROUT) = (0, 0);
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( RXUSRCLK2 *> PHYSTATUS) = (0, 0);
( RXUSRCLK2 *> RXBUFSTATUS) = (0, 0);
( RXUSRCLK2 *> RXBYTEISALIGNED) = (0, 0);
( RXUSRCLK2 *> RXBYTEREALIGN) = (0, 0);
( RXUSRCLK2 *> RXCHANBONDSEQ) = (0, 0);
( RXUSRCLK2 *> RXCHANISALIGNED) = (0, 0);
( RXUSRCLK2 *> RXCHANREALIGN) = (0, 0);
( RXUSRCLK2 *> RXCHARISCOMMA) = (0, 0);
( RXUSRCLK2 *> RXCHARISK) = (0, 0);
( RXUSRCLK2 *> RXCHBONDO) = (0, 0);
( RXUSRCLK *> RXCHBONDO) = (0, 0);
( RXUSRCLK2 *> RXCLKCORCNT) = (0, 0);
( RXUSRCLK2 *> RXCOMINITDET) = (0, 0);
( RXUSRCLK2 *> RXCOMMADET) = (0, 0);
( RXUSRCLK2 *> RXCOMSASDET) = (0, 0);
( RXUSRCLK2 *> RXCOMWAKEDET) = (0, 0);
( RXUSRCLK2 *> RXDATA) = (0, 0);
( RXUSRCLK2 *> RXDATAVALID) = (0, 0);
( RXUSRCLK2 *> RXDISPERR) = (0, 0);
( RXUSRCLK2 *> RXHEADER) = (0, 0);
( RXUSRCLK2 *> RXHEADERVALID) = (0, 0);
( RXUSRCLK2 *> RXNOTINTABLE) = (0, 0);
( RXUSRCLK2 *> RXPRBSERR) = (0, 0);
( RXUSRCLK2 *> RXRATEDONE) = (0, 0);
( RXUSRCLK2 *> RXRESETDONE) = (0, 0);
( RXUSRCLK2 *> RXSTARTOFSEQ) = (0, 0);
( RXUSRCLK2 *> RXSTATUS) = (0, 0);
( RXUSRCLK2 *> RXVALID) = (0, 0);
( TXUSRCLK2 *> TXBUFSTATUS) = (0, 0);
( TXUSRCLK2 *> TXCOMFINISH) = (0, 0);
( TXUSRCLK2 *> TXGEARBOXREADY) = (0, 0);
( TXUSRCLK2 *> TXRATEDONE) = (0, 0);
( TXUSRCLK2 *> TXRESETDONE) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFRBP_PP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_PP_SYMBOL_V
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
module ovl_always_on_edge_wrapped(
clk,
rst,
enable,
sampling_event,
test_expr,
prevConfigInvalid,
out
);
input clk;
input rst;
input enable;
input sampling_event;
input test_expr;
input prevConfigInvalid;
output out;
wire [2:0] result_3bit;
wire [2:0] result_3bit_comb;
ovl_always_on_edge ovl_always_on_edge(
.clock(clk),
.reset(rst),
.enable(enable),
.sampling_event(sampling_event),
.test_expr(test_expr),
.fire(result_3bit),
.fire_comb(result_3bit_comb)
);
assign out = result_3bit_comb[0] & ~prevConfigInvalid;
endmodule
|
/*
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| eg_comb/ | | 49/49 | 0/0 | 153/153 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_comb |
| eg_comb/ | | 42/42 | 0/0 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_comb |
| eg_comb/ | | 39/39 | 0/0 | 129/129 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_comb |
| eg_comb/ | | 43/43 | 0/0 | 122/122 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_comb |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
This module represents all the envelope generator calculations.
Everything is combinational. The testbench ver/eg2 checks the
functionality of this module.
*/
module eg_comb(
input attack,
input [ 4:0] base_rate,
input [ 4:0] keycode,
input [14:0] eg_cnt,
input cnt_in,
input [ 1:0] ks,
input [ 9:0] eg_in,
input [ 6:0] lfo_mod,
input amsen,
input [ 1:0] ams,
input [ 6:0] tl,
output cnt_lsb,
output reg [9:0] eg_limited,
output reg [9:0] eg_pure
);
reg [6:0] pre_rate;
reg [5:0] rate;
always @(*) begin : pre_rate_calc
if( base_rate == 5'd0 )
pre_rate = 7'd0;
else
case( ks )
2'd3: pre_rate = { base_rate, 1'b0 } + { 1'b0, keycode };
2'd2: pre_rate = { base_rate, 1'b0 } + { 2'b0, keycode[4:1] };
2'd1: pre_rate = { base_rate, 1'b0 } + { 3'b0, keycode[4:2] };
2'd0: pre_rate = { base_rate, 1'b0 } + { 4'b0, keycode[4:3] };
endcase
end
always @(*)
rate = pre_rate[6] ? 6'd63 : pre_rate[5:0];
reg [2:0] cnt;
reg [4:0] mux_sel;
always @(*) begin
mux_sel = attack ? (rate[5:2]+4'd1): {1'b0,rate[5:2]};
end // always @(*)
always @(*)
case( mux_sel )
5'h0: cnt = eg_cnt[14:12];
5'h1: cnt = eg_cnt[13:11];
5'h2: cnt = eg_cnt[12:10];
5'h3: cnt = eg_cnt[11: 9];
5'h4: cnt = eg_cnt[10: 8];
5'h5: cnt = eg_cnt[ 9: 7];
5'h6: cnt = eg_cnt[ 8: 6];
5'h7: cnt = eg_cnt[ 7: 5];
5'h8: cnt = eg_cnt[ 6: 4];
5'h9: cnt = eg_cnt[ 5: 3];
5'ha: cnt = eg_cnt[ 4: 2];
5'hb: cnt = eg_cnt[ 3: 1];
default: cnt = eg_cnt[ 2: 0];
endcase
////////////////////////////////
reg step;
reg [7:0] step_idx;
always @(*) begin : rate_step
if( rate[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate[5:2]==4'hf && attack)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
case( rate[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate[5:2]==4'd0 && !attack)
step_idx = 8'b11111110; // limit slowest decay rate
else
case( rate[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate of zero keeps the level still
step = rate[5:1]==5'd0 ? 1'b0 : step_idx[ cnt ];
end
reg sum_up;
assign cnt_lsb = cnt[0];
always @(*) begin
sum_up = cnt[0] != cnt_in;
end
//////////////////////////////////////////////////////////////
// cnt/cnt_lsb/cnt_in not used below this point
reg [3:0] dr_sum;
reg [10:0] dr_result;
always @(*) begin
case( rate[5:2] )
4'b1100: dr_sum = { 2'b0, step, ~step }; // 12
4'b1101: dr_sum = { 1'b0, step, ~step, 1'b0 }; // 13
4'b1110: dr_sum = { step, ~step, 2'b0 }; // 14
4'b1111: dr_sum = 4'd8;// 15
default: dr_sum = { 2'b0, step, 1'b0 };
endcase
dr_result = {6'd0, dr_sum} + eg_in;
end
reg [ 7:0] ar_sum0;
reg [ 8:0] ar_sum1;
reg [10:0] ar_result;
reg [ 9:0] ar_sum;
always @(*) begin : ar_calculation
casez( rate[5:2] )
default: ar_sum0 = {2'd0, eg_in[9:4]};
4'b1101: ar_sum0 = {1'd0, eg_in[9:3]};
4'b111?: ar_sum0 = eg_in[9:2];
endcase
ar_sum1 = ar_sum0+9'd1;
if( rate[5:4] == 2'b11 )
ar_sum = step ? { ar_sum1, 1'b0 } : { 1'b0, ar_sum1 };
else
ar_sum = step ? { 1'b0, ar_sum1 } : 10'd0;
ar_result = rate[5:1]==5'h1F ? 11'd0 : eg_in-ar_sum;
end
///////////////////////////////////////////////////////////
// rate not used below this point
always @(*) begin
if(sum_up) begin
if( attack )
eg_pure = ar_result[10] ? 10'd0: ar_result[9:0];
else
eg_pure = dr_result[10] ? 10'h3FF : dr_result[9:0];
end
else eg_pure = eg_in;
end
//////////////////////////////////////////////////////////////
reg [ 8:0] am_final;
reg [10:0] sum_eg_tl;
reg [11:0] sum_eg_tl_am;
reg [ 5:0] am_inverted;
always @(*) begin
am_inverted = lfo_mod[6] ? ~lfo_mod[5:0] : lfo_mod[5:0];
end
always @(*) begin
casez( {amsen, ams } )
default: am_final = 9'd0;
3'b1_01: am_final = { 5'd0, am_inverted[5:2] };
3'b1_10: am_final = { 3'd0, am_inverted };
3'b1_11: am_final = { 2'd0, am_inverted, 1'b0 };
endcase
sum_eg_tl = { tl, 3'd0 } + eg_pure;
sum_eg_tl_am = sum_eg_tl + { 3'd0, am_final };
end
always @(*)
eg_limited = sum_eg_tl_am[11:10]==2'd0 ? sum_eg_tl_am[9:0] : 10'h3ff;
endmodule // eg_comb |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_rd (
// request and synchronization
dma_xfer_req,
// read interface
axi_rd_req,
axi_rd_addr,
// axi interface
axi_clk,
axi_resetn,
axi_arvalid,
axi_arid,
axi_arburst,
axi_arlock,
axi_arcache,
axi_arprot,
axi_arqos,
axi_aruser,
axi_arlen,
axi_arsize,
axi_araddr,
axi_arready,
axi_rvalid,
axi_rid,
axi_ruser,
axi_rresp,
axi_rlast,
axi_rdata,
axi_rready,
// axi status
axi_rerror,
// fifo interface
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
// request and synchronization
input dma_xfer_req;
// read interface
input axi_rd_req;
input [ 31:0] axi_rd_addr;
// axi interface
input axi_clk;
input axi_resetn;
output axi_arvalid;
output [ 3:0] axi_arid;
output [ 1:0] axi_arburst;
output axi_arlock;
output [ 3:0] axi_arcache;
output [ 2:0] axi_arprot;
output [ 3:0] axi_arqos;
output [ 3:0] axi_aruser;
output [ 7:0] axi_arlen;
output [ 2:0] axi_arsize;
output [ 31:0] axi_araddr;
input axi_arready;
input axi_rvalid;
input [ 3:0] axi_rid;
input [ 3:0] axi_ruser;
input [ 1:0] axi_rresp;
input axi_rlast;
input [AXI_DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// axi status
output axi_rerror;
// fifo interface
output axi_drst;
output axi_dvalid;
output [AXI_DATA_WIDTH-1:0] axi_ddata;
input axi_dready;
// internal registers
reg [ 31:0] axi_rd_addr_h = 'd0;
reg axi_rd = 'd0;
reg axi_rd_active = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg axi_xfer_enable = 'd0;
reg axi_arvalid = 'd0;
reg [ 31:0] axi_araddr = 'd0;
reg axi_drst = 'd0;
reg axi_dvalid = 'd0;
reg [AXI_DATA_WIDTH-1:0] axi_ddata = 'd0;
reg axi_rready = 'd0;
reg axi_rerror = 'd0;
// internal signals
wire axi_ready_s;
// read is way too slow- buffer mode
assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_addr_h <= 'd0;
axi_rd <= 'd0;
axi_rd_active <= 'd0;
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
axi_xfer_enable <= 'd0;
end else begin
if (axi_xfer_init == 1'b1) begin
axi_rd_addr_h <= AXI_ADDRESS;
end else if (axi_rd_req == 1'b1) begin
axi_rd_addr_h <= axi_rd_addr;
end
if (axi_rd_active == 1'b1) begin
axi_rd <= 1'b0;
if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
axi_rd_active <= 1'b0;
end
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
axi_rd <= axi_xfer_enable;
axi_rd_active <= axi_xfer_enable;
end
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
axi_xfer_enable <= axi_xfer_req_m[2];
end
end
// address channel
assign axi_arid = 4'b0000;
assign axi_arburst = 2'b01;
assign axi_arlock = 1'b0;
assign axi_arcache = 4'b0010;
assign axi_arprot = 3'b000;
assign axi_arqos = 4'b0000;
assign axi_aruser = 4'b0001;
assign axi_arlen = AXI_LENGTH - 1;
assign axi_arsize = AXI_SIZE;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_arvalid <= 'd0;
axi_araddr <= 'd0;
end else begin
if (axi_arvalid == 1'b1) begin
if (axi_arready == 1'b1) begin
axi_arvalid <= 1'b0;
end
end else begin
if (axi_rd == 1'b1) begin
axi_arvalid <= 1'b1;
end
end
if (axi_xfer_init == 1'b1) begin
axi_araddr <= AXI_ADDRESS;
end else if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin
axi_araddr <= axi_araddr + AXI_AWINCR;
end
end
end
// read data channel
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_drst <= 'd1;
axi_dvalid <= 'd0;
axi_ddata <= 'd0;
axi_rready <= 'd0;
end else begin
axi_drst <= ~axi_xfer_req_m[1];
axi_dvalid <= axi_rvalid;
axi_ddata <= axi_rdata;
axi_rready <= 1'b1;
end
end
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rerror <= 'd0;
end else begin
axi_rerror <= axi_rvalid & axi_rresp[1];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_no_pg/sky130_fd_sc_hs__u_df_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfxtp (
VPWR,
VGND,
Q ,
CLK ,
D ,
SCD ,
SCE
);
// Module ports
input VPWR;
input VGND;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
,VCCD, VCCHIB, VDDA, VDDIO,VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH
);
output XRES_H_N;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout PAD;
input DISABLE_PULLUP_H;
input ENABLE_H;
input EN_VDDIO_SIG_H;
input INP_SEL_H;
input FILT_IN_H;
inout PULLUP_H;
input ENABLE_VDDIO;
input VCCD;
input VCCHIB;
input VDDA;
input VDDIO;
input VDDIO_Q;
input VSSA;
input VSSD;
input VSSIO;
input VSSIO_Q;
input VSWITCH;
wire mode_vcchib;
wire pwr_good_xres_tmp = (VDDIO===1) && (VDDIO_Q===1) && ((mode_vcchib && ENABLE_VDDIO)===1 ? VCCHIB===1 : 1'b1) && (VSSIO===0) && (VSSD===0);
wire pwr_good_xres_h_n = (VDDIO_Q===1) && (VSSD===0);
wire pwr_good_pullup = (VDDIO===1) && (VSSD===0);
inout PAD_A_ESD_H;
output TIE_HI_ESD;
output TIE_LO_ESD;
inout TIE_WEAK_HI_H;
wire tmp1;
pullup (pull1) p1 (tmp1); tranif1 x_pull_1 (TIE_WEAK_HI_H, tmp1, pwr_good_pullup===0 ? 1'bx : 1);
tran p2 (PAD, PAD_A_ESD_H);
buf p4 (TIE_HI_ESD, VDDIO);
buf p5 (TIE_LO_ESD, VSSIO);
wire tmp;
pullup (pull1) p3 (tmp); tranif0 x_pull (PULLUP_H, tmp, pwr_good_pullup===0 || ^DISABLE_PULLUP_H===1'bx ? 1'bx : DISABLE_PULLUP_H);
parameter MAX_WARNING_COUNT = 100;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
parameter MIN_DELAY = 0;
parameter MAX_DELAY = 0;
`else
parameter MIN_DELAY = 50;
parameter MAX_DELAY = 600;
`endif
integer min_delay, max_delay;
initial begin
min_delay = MIN_DELAY;
max_delay = MAX_DELAY;
end
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_ENABLE_VDDIO_CHANGE_X
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 1;
`else
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 0;
`endif
integer disable_enable_vddio_change_x = DISABLE_ENABLE_VDDIO_CHANGE_X;
reg notifier_enable_h;
specify
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
specparam DELAY = 0;
`else
specparam DELAY = 50;
`endif
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==1) (FILT_IN_H => XRES_H_N) = (0:0:0 , 0:0:0);
specparam tsetup = 0;
specparam thold = 5;
endspecify
reg corrupt_enable;
always @(notifier_enable_h)
begin
corrupt_enable <= 1'bx;
end
initial
begin
corrupt_enable = 1'b0;
end
always @(PAD or ENABLE_H or EN_VDDIO_SIG_H or ENABLE_VDDIO or INP_SEL_H or FILT_IN_H or pwr_good_xres_tmp or DISABLE_PULLUP_H or PULLUP_H or TIE_WEAK_HI_H)
begin
corrupt_enable <= 1'b0;
end
assign mode_vcchib = ENABLE_H && !EN_VDDIO_SIG_H;
wire xres_tmp = (pwr_good_xres_tmp===0 || ^PAD===1'bx || (mode_vcchib===1'bx ) ||(mode_vcchib!==1'b0 && ^ENABLE_VDDIO===1'bx) || (corrupt_enable===1'bx) ||
(mode_vcchib===1'b1 && ENABLE_VDDIO===0 && (disable_enable_vddio_change_x===0)))
? 1'bx : PAD;
wire x_on_xres_h_n = (pwr_good_xres_h_n===0
|| ^INP_SEL_H===1'bx
|| INP_SEL_H===1 && ^FILT_IN_H===1'bx
|| INP_SEL_H===0 && xres_tmp===1'bx);
assign #1 XRES_H_N = x_on_xres_h_n===1 ? 1'bx : (INP_SEL_H===1 ? FILT_IN_H : xres_tmp);
realtime t_pad_current_transition,t_pad_prev_transition;
realtime t_filt_in_h_current_transition,t_filt_in_h_prev_transition;
realtime pad_pulse_width, filt_in_h_pulse_width;
always @(PAD)
begin
if (^PAD !== 1'bx)
begin
t_pad_prev_transition = t_pad_current_transition;
t_pad_current_transition = $realtime;
pad_pulse_width = t_pad_current_transition - t_pad_prev_transition;
end
else
begin
t_pad_prev_transition = 0;
t_pad_current_transition = 0;
pad_pulse_width = 0;
end
end
always @(FILT_IN_H)
begin
if (^FILT_IN_H !== 1'bx)
begin
t_filt_in_h_prev_transition = t_filt_in_h_current_transition;
t_filt_in_h_current_transition = $realtime;
filt_in_h_pulse_width = t_filt_in_h_current_transition - t_filt_in_h_prev_transition;
end
else
begin
t_filt_in_h_prev_transition = 0;
t_filt_in_h_current_transition = 0;
filt_in_h_pulse_width = 0;
end
end
reg dis_err_msgs;
integer msg_count_pad, msg_count_filt_in_h;
event event_errflag_pad_pulse_width, event_errflag_filt_in_h_pulse_width;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0; msg_count_filt_in_h = 0;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
always @(pad_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===0 && (pad_pulse_width > min_delay) && (pad_pulse_width < max_delay))
begin
msg_count_pad = msg_count_pad + 1;
->event_errflag_pad_pulse_width;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for PAD input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",pad_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
always @(filt_in_h_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===1 && (filt_in_h_pulse_width > min_delay) && (filt_in_h_pulse_width < max_delay))
begin
msg_count_filt_in_h = msg_count_filt_in_h + 1;
->event_errflag_filt_in_h_pulse_width;
if (msg_count_filt_in_h <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for FILT_IN_H input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",filt_in_h_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_filt_in_h == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
// file: pll_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
reg COUNTER_RESET = 0;
wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
pll_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__XNOR3_BEHAVIORAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR3_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V |
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
output wire VGA_HSYNC,
output wire VGA_VSYNC,
output wire VGA_RED,
output wire VGA_GREEN,
output wire VGA_BLUE
);
wire [15:0] wIP,wIP_temp,wIP_return;
reg rWriteEnable,rBranchTaken,rReturn,rCall;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestinationPrev;
wire [15:0] wSourceData0,wSourceData1,wSourceData0_RAM,wSourceData1_RAM,wResultPrev,wIPInitialValue,wDestinationJump,wImmediateValue;
wire wHazard0, wHazard1, wWriteEnablePrev, wIsImmediate,wPushAddr;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0_RAM ),
.oDataOut1( wSourceData1_RAM )
);
assign wDestinationJump = (rReturn) ? wIP_return : wDestination;
assign wIPInitialValue = (Reset) ? 8'b0 : wDestinationJump;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 16'd1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1[7:0] ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
/////////////////////////////////
// Data Hazards en el pipeline //
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD41
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wDestination),
.Q(wDestinationPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDRES
(
.Clock(Clock),
.Reset(Reset),
.Enable(rWriteEnable),
.D(rResult),
.Q(wResultPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDWRITE
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D( {rWriteEnable} ),
.Q( {wWriteEnablePrev} )
);
assign wIsImmediate = wOperation[3] && wOperation[2];
assign wHazard0 = ((wDestinationPrev == wSourceAddr0) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wHazard1 = ((wDestinationPrev == wSourceAddr1) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wSourceData0 = (wHazard0) ? wResultPrev : wSourceData0_RAM;
assign wSourceData1 = (wHazard1) ? wResultPrev : wSourceData1_RAM;
// //
/////////////////////////////////
/////////////////////////////////
// CALL RET //
// assign wPushAddr = (wInstruction[27:24] == `CALL);
//assign wPushAddr = (wOperation == `CALL);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FF_RET
(
.Clock(~Clock),
.Reset(Reset),
.Enable( rCall ),
.D( wIP_temp ),
.Q( wIP_return )
);
// //
/////////////////////////////////
//////////////////////////////
// VGA Controler and Memory //
VGA_Controller vga (
.Clock(Clock),
.Enable(1'b1),
.Reset(Reset),
.iPixel(`RED),
.oHorizontalSync(VGA_HSYNC),
.oVerticalSync(VGA_VSYNC),
.oRed(VGA_RED),
.oGreen(VGA_GREEN),
.oBlue(VGA_BLUE)
);
// Instanciar memoria aqui
// //
//////////////////////////////
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`CALL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b1;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b1;
rCall <= 1'b0;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
`WRITE_ROM :
begin
if (row <= 200){
}else if(row <= 400){
}else if (row <= 600) {
}else if(row <= 800) {}
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 18:14:28 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/About/About_stub.v
// Design : About
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *)
module About(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[799:0]" */;
input clka;
input [9:0]addra;
output [799:0]douta;
endmodule
|
module testbench;
localparam integer PERIOD = 12000000 / 9600;
reg CLK;
always #5 CLK = (CLK === 1'b0);
reg RX = 1;
wire TX;
wire LED1;
wire LED2;
wire LED3;
wire LED4;
wire LED5;
top uut (
.CLK (CLK ),
.RX (RX ),
.TX (TX ),
.LED1(LED1),
.LED2(LED2),
.LED3(LED3),
.LED4(LED4),
.LED5(LED5)
);
task send_byte;
input [7:0] c;
integer i;
begin
RX <= 0;
repeat (PERIOD) @(posedge CLK);
for (i = 0; i < 8; i = i+1) begin
RX <= c[i];
repeat (PERIOD) @(posedge CLK);
end
RX <= 1;
repeat (PERIOD) @(posedge CLK);
end
endtask
reg [4095:0] vcdfile;
initial begin
if ($value$plusargs("vcd=%s", vcdfile)) begin
$dumpfile(vcdfile);
$dumpvars(0, testbench);
end
repeat (10 * PERIOD) @(posedge CLK);
// turn all LEDs on
send_byte("1");
send_byte("2");
send_byte("3");
send_byte("4");
send_byte("5");
// turn all LEDs off
send_byte("1");
send_byte("2");
send_byte("3");
send_byte("4");
send_byte("5");
repeat (10 * PERIOD) @(posedge CLK);
$finish;
end
endmodule
|
/*main function
1)receiving packet from inputctrl module,and forwarding packets to classification module and offset module
*/
module INGRESS_CTRL(
input clk,
input reset,
input in_inputctrl_pkt_wr,// the packet write request of input_ctrl moudle to inputctrl module
input [133:0] in_inputctrl_pkt,// the packet of input_ctrl moudle to inputctrl module
input in_inputctrl_valid_wr,//the valid flag write request of input_ctrl moudle to inputctrl module
input in_inputctrl_valid,// the valid flag of input_ctrl moudle to inputctrl module
output out_inputctrl_pkt_almostfull,
output reg out_class_key_wr,// the packet write request of input_ctrl moudle to classification module
output reg [133:0] out_class_key,// the packet of input_ctrl moudle to classification module
input in_class_key_almostfull,
output reg out_class_valid,// the valid flag of input_ctrl moudle to classification module
output reg out_class_valid_wr,//the valid flag write request of input_ctrl moudle to classification module
output reg out_offset_pkt_wr,// the packet write request of input_ctrl moudle to offset module
output reg [133:0] out_offset_pkt,// the packet of input_ctrl moudle to offset module
output reg out_offset_valid,// the valid flag of input_ctrl moudle to offset module
output reg out_offset_valid_wr,//the valid flag write request of iinput_ctrl moudle to offset module
input in_offset_pkt_almostfull
);
reg [2:0] current_state;
reg [2:0] counter;
wire in_inputctrl_valid_q;
wire in_inputctrl_valid_empty;
reg out_inputctrl_valid_rd;
wire [7:0] out_inputctrl_pkt_usedw;
assign out_inputctrl_pkt_almostfull = out_inputctrl_pkt_usedw[7];
reg out_inputctrl_pkt_rd;
wire [133:0]in_inputctrl_pkt_q;
parameter idle_s = 3'd0,
send_meta1_s = 3'd1,
send_meta2_s = 3'd2,
send_key_s = 3'd3,
send_data_s = 3'd4,
discard_s=3'd5;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_class_key_wr<=1'b0;
out_class_key<=134'b0;
out_class_valid<=1'b1;
out_class_valid_wr<=1'b0;
out_offset_pkt_wr<=1'b0;
out_offset_pkt<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_inputctrl_valid_rd<=1'b0;
out_inputctrl_pkt_rd<=1'b0;
counter<=3'b0;
current_state<=idle_s;
end
else begin
case(current_state)
idle_s:begin
counter<=3'b0;
out_class_key_wr<=1'b0;
out_class_valid_wr<=1'b0;
out_offset_pkt_wr<=1'b0;
out_offset_valid_wr<=1'b0;
out_offset_valid<=1'b0;
if((in_offset_pkt_almostfull==1'b0) && (in_inputctrl_valid_empty==1'b0) && (in_class_key_almostfull==1'b0))begin
if(in_inputctrl_valid_q==1'b1)begin
out_inputctrl_valid_rd<=1'b1;
out_inputctrl_pkt_rd<=1'b1;
current_state<=send_meta1_s;
end
else begin
out_inputctrl_valid_rd<=1'b1;
out_inputctrl_pkt_rd<=1'b1;
current_state<=discard_s;
end
end
else begin
out_inputctrl_valid_rd<=1'b0;
out_inputctrl_pkt_rd<=1'b0;
current_state<=idle_s;
end
end
send_meta1_s:begin//forward to first pat metadata
out_inputctrl_valid_rd<=1'b0;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_meta2_s;
end
send_meta2_s:begin//forward to second pat metadata
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_key_s;
end
send_key_s:begin//forward to first pat packet
out_offset_pkt_wr<=1'b1;
out_class_key_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
out_class_key<=in_inputctrl_pkt_q;
counter<=counter+1'b1;//the number of forward to packet
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
out_offset_valid_wr<=1'b1;
out_offset_valid<=1'b1;
out_class_valid_wr<=1'b1;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
out_offset_valid_wr<=1'b0;
out_offset_valid<=1'b0;
if(counter<3'd3)begin //four packets forward to inputctrl
out_class_valid_wr<=1'b0;
current_state<=send_key_s;
end
else begin
out_class_valid_wr<=1'b1;
current_state<=send_data_s;
end
end
end
send_data_s:begin//forward other packets to offset module
out_class_key_wr<=1'b0;
out_class_valid_wr<=1'b0;
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
out_offset_valid_wr<=1'b1;
out_offset_valid<=1'b1;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_data_s;
end
end
discard_s:begin
out_inputctrl_valid_rd<=1'b0;
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
current_state<=discard_s;
end
end
default:;
endcase
end
end
fifo_64_1 FIFO_VALID_input_ctrl (
.aclr(!reset),
.data(in_inputctrl_valid),
.clock(clk),
.rdreq(out_inputctrl_valid_rd),
.wrreq(in_inputctrl_valid_wr),
.q(in_inputctrl_valid_q),
.empty(in_inputctrl_valid_empty)
);
fifo_256_134 FIFO_PKT_input_ctrl (
.aclr(!reset),
.data(in_inputctrl_pkt),
.clock(clk),
.rdreq(out_inputctrl_pkt_rd),
.wrreq(in_inputctrl_pkt_wr),
.q(in_inputctrl_pkt_q),
.usedw(out_inputctrl_pkt_usedw)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__BUF_PP_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// ////
//// To Do: ////
//// - add support for other RAM's ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_128x32.v,v $
// Revision 1.3 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_spram_128x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 7;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({1'b0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({1'b0, addr}),
.DI(di[31:16]),
.EN(ce),
.WE(we),
.DO(doq[31:16])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({2'b00, addr}),
.DI(di),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO(doq),
.DOP()
);
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_BLACKBOX_V
`define SKY130_FD_SC_LP__SREGSBP_BLACKBOX_V
/**
* sregsbp: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_BLACKBOX_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tutorial_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001d),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000100000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000002),
.C_M_AXI_READ_CONNECTIVITY(32'H00000003),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000200000004),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000200000002),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`include "senior_defines.vh"
module agu_rf
#(parameter nat_w = `SENIOR_NATIVE_WIDTH,
parameter adr_w = 2,
parameter other_value = 0)
(
input wire clk_i,
input wire [adr_w-1:0] adr_a_i,
input wire [adr_w-1:0] adr_b_i,
output reg [nat_w-1:0] dat_a_o,
output reg [nat_w-1:0] dat_b_o,
input wire spr_wren_i,
input wire spr_read_i,
input wire [adr_w-1:0] spr_sel_i,
input wire [nat_w-1:0] spr_dat_i);
reg [nat_w-1:0] rf [1:0];
wire [adr_w-1:0] adr_a;
wire [nat_w-1:0] dat_a;
assign adr_a = (spr_wren_i | spr_read_i) ? spr_sel_i : adr_a_i;
always@(posedge clk_i) begin
if(spr_wren_i) begin
rf[adr_a[0]] = spr_dat_i;
end
end
//Need to do like this to be able to synthesize, bug in xst
wire [nat_w-1:0] rf_adr_a_0;
wire [nat_w-1:0] rf_adr_b_i_0;
assign rf_adr_a_0 = rf[adr_a[0]];
assign rf_adr_b_i_0 = rf[adr_b_i[0]];
always@* begin
casex(adr_a)
2'b1x: begin
dat_a_o = other_value;
end
2'b0x: begin
dat_a_o = rf_adr_a_0; //rf[adr_a[0]];
end
endcase
casex(adr_b_i)
2'b1x: begin
dat_b_o = other_value;
end
2'b0x: begin
dat_b_o = rf_adr_b_i_0; //rf[adr_b_i[0]];
end
endcase
end
endmodule
|
`timescale 1ns/1ns
module usb_tx_ack
(input c,
input start,
output [7:0] sie_d,
output sie_dv);
`include "usb_pids.v"
localparam ST_IDLE = 3'd0;
localparam ST_SYNC = 3'd1;
localparam ST_PID = 3'd2;
localparam SW=4, CW=2;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire sie_d_sel;
wire [7:0] sie_mux_z;
gmux #(.DWIDTH(8), .SELWIDTH(1)) sie_d_gmux
(.d({PID_ACK, 8'b10000000}), .sel(sie_d_sel), .z(sie_mux_z));
wire [7:0] sie_d_i = sie_dv_i ? sie_mux_z : 8'h0;
always @* begin
case (state)
ST_IDLE:
if (start) ctrl = { ST_SYNC , 2'b01 };
else ctrl = { ST_IDLE , 2'b00 };
ST_SYNC: ctrl = { ST_PID , 2'b11 };
ST_PID: ctrl = { ST_IDLE , 2'b00 };
default: ctrl = { ST_IDLE , 2'b00 };
endcase
end
wire sie_dv_i = ctrl[0];
assign sie_d_sel = ctrl[1];
// help timing a bit
d1 #(8) sie_d1_d_r (.c(c), .d(sie_d_i ), .q(sie_d ));
d1 sie_d1_dv_r(.c(c), .d(sie_dv_i), .q(sie_dv));
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
//
//
// Owner: Jayant Mittal
// Revision: $Id: qdr_rld_byte_group_io.v,v 1.2 2012/05/08 01:03:44 rodrigoa Exp $
// $Author: rodrigoa $
// $DateTime: 2010/09/27 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a paramertizable I/O termination for
// the single byte lane.
// to create a N byte-lane wide phy.
//
// History:
// Date Engineer Description
// 09/13/2010 J. Mittal Initial Checkin.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_rld_byte_group_io #(
parameter MEMORY_TYPE = "SRAM",
parameter DATA_CTL_N = 1,
parameter OSERDES_DATA_RATE = "DDR",
parameter BITLANES_IN = 12'b0000_0000_0000,
parameter BITLANES_OUT = 12'b0000_0000_0000,
parameter CK_P_OUT = 12'b0000_0000_0000,
parameter CK_VALUE_D1 = 1'b0,
parameter BUS_WIDTH = 12,
parameter ABCD = "A",
parameter BYTE_GROUP_TYPE = "IN",
parameter BUFG_FOR_OUTPUTS = "OFF",
parameter IODELAY_GRP = "IODELAY_MIG", //May be assigned unique name
// when mult IP cores in design
parameter IODELAY_HP_MODE = "ON", //IODELAY High Performance Mode
parameter REFCLK_FREQ = 200.0,
parameter ODELAY_90_SHIFT = 0
)
(
output wire [BUS_WIDTH-1:0] O,
input [11:0] I,
output wire [BUS_WIDTH-1:0] mem_dq_ts,
input phy_clk,
output wire [(4*12)-1:0] iserdes_q, // 2 extra 12-bit lanes not used
input iserdes_clk,
input iserdes_clkb,
input iserdes_clkdiv,
input oserdes_rst,
input iserdes_rst,
input [(4*BUS_WIDTH)-1:0] oserdes_d,
input [1:0] oserdes_dqts_in,
input oserdes_clk,
input oserdes_clkdiv,
input idelay_ld,
input [BUS_WIDTH-1:0] idelay_ce,
input [BUS_WIDTH-1:0] idelay_inc,
input [5*12-1:0] idelay_cnt_in,
output wire [5*12-1:0] idelay_cnt_out
);
wire [BUS_WIDTH-1:0] data_in_dly;
wire tbyte_out;
wire tbyte_out_uni;
wire [1:0] oserdes_dqts;
wire [BUS_WIDTH-1:0] oserdes_data_out;
wire [BUS_WIDTH-1:0] oserdes_data_delay_out;
wire [BUS_WIDTH-1:0] ddr_ck_out_q;
wire [11:0] data_in;
wire [11:0] iserdes_r0;
wire [11:0] iserdes_f0;
wire [11:0] iserdes_r1;
wire [11:0] iserdes_f1;
reg iserdes_clk_d;
reg iserdes_clkb_d;
// Function to check for empty data byte lane (no tri-state)
function [11:0] calc_byte_group_type;
input [11:0] bitlanes_in;
input [11:0] bitlanes_out;
integer x;
begin
calc_byte_group_type = 'b0;
for (x = 0; x < 12; x = x + 1)
if (bitlanes_in[x] && bitlanes_out[x]) //bidirectional bit
calc_byte_group_type = 1; //if we see one bidirectional bit, the byte lane
//is bidrectional and needs a tri-state
else //not bidirectional, hold previous value
calc_byte_group_type = calc_byte_group_type;
end
endfunction
localparam BYTE_GROUP_TYPE_CALC =
(calc_byte_group_type(BITLANES_IN, BITLANES_OUT) == 0 ) ?
"OUT" : BYTE_GROUP_TYPE;
localparam BYTE_TYPE = (BYTE_GROUP_TYPE == "BIDIR") ?
BYTE_GROUP_TYPE_CALC : BYTE_GROUP_TYPE;
/// INSTANCES
localparam ISERDES_Q_DATA_RATE = "DDR";
localparam ISERDES_Q_DATA_WIDTH = 4;
localparam ISERDES_Q_DYN_CLKDIV_INV_EN = "FALSE";
localparam ISERDES_Q_DYN_CLK_INV_EN = "FALSE";
localparam ISERDES_Q_INIT_Q1 = 1'b0;
localparam ISERDES_Q_INIT_Q2 = 1'b0;
localparam ISERDES_Q_INIT_Q3 = 1'b0;
localparam ISERDES_Q_INIT_Q4 = 1'b0;
localparam ISERDES_Q_INTERFACE_TYPE = "MEMORY_DDR3";
localparam ISERDES_NUM_CE = 2;
localparam ISERDES_Q_IOBDELAY = "IFD";
localparam ISERDES_Q_OFB_USED = "FALSE";
localparam ISERDES_Q_SERDES_MODE = "MASTER";
localparam ISERDES_Q_SRVAL_Q1 = 1'b0;
localparam ISERDES_Q_SRVAL_Q2 = 1'b0;
localparam ISERDES_Q_SRVAL_Q3 = 1'b0;
localparam ISERDES_Q_SRVAL_Q4 = 1'b0;
always @(*) begin
iserdes_clk_d = iserdes_clk;
iserdes_clkb_d = iserdes_clkb;
end
generate
genvar rd_i;
for (rd_i=0; rd_i <12; rd_i= rd_i+1) begin : gen_iserdes_q
assign iserdes_q[4*rd_i] = iserdes_r0[rd_i];
assign iserdes_q[4*rd_i+1] = iserdes_f0[rd_i];
assign iserdes_q[4*rd_i+2] = iserdes_r1[rd_i];
assign iserdes_q[4*rd_i+3] = iserdes_f1[rd_i];
end
endgenerate
generate
genvar j;
for ( j = 0; j != 12; j=j+1)
begin : i_serdesq_
if (BITLANES_IN[j]) begin : gen_iserdes
//`UNISIM_ISERDESE2 #(
ISERDESE2 #(
.DATA_RATE ( ISERDES_Q_DATA_RATE),
.DATA_WIDTH ( ISERDES_Q_DATA_WIDTH),
.DYN_CLKDIV_INV_EN ( ISERDES_Q_DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN ( ISERDES_Q_DYN_CLK_INV_EN),
.INIT_Q1 ( ISERDES_Q_INIT_Q1),
.INIT_Q2 ( ISERDES_Q_INIT_Q2),
.INIT_Q3 ( ISERDES_Q_INIT_Q3),
.INIT_Q4 ( ISERDES_Q_INIT_Q4),
.INTERFACE_TYPE ( ISERDES_Q_INTERFACE_TYPE),
.NUM_CE ( ISERDES_NUM_CE),
.IOBDELAY ( ISERDES_Q_IOBDELAY),
.OFB_USED ( ISERDES_Q_OFB_USED),
.SERDES_MODE ( ISERDES_Q_SERDES_MODE),
.SRVAL_Q1 ( ISERDES_Q_SRVAL_Q1),
.SRVAL_Q2 ( ISERDES_Q_SRVAL_Q2),
.SRVAL_Q3 ( ISERDES_Q_SRVAL_Q3),
.SRVAL_Q4 ( ISERDES_Q_SRVAL_Q4)
)
iserdesq
(
.O (),
.Q1 (iserdes_f1[j]),
.Q2 (iserdes_r1[j]),
.Q3 (iserdes_f0[j]),
.Q4 (iserdes_r0[j]),
.Q5 (),
.Q6 (),
.Q7 (),
.Q8 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iserdes_clk_d),
.CLKB (iserdes_clkb_d), //(!iserdes_clk_d),
//`ifdef SKIPME
//`ifdef FUJI_UNISIMS
.CLKDIVP (iserdes_clkdiv),
//`endif
//`endif
.CLKDIV (),
.DDLY (data_in_dly[j]),
//.D (data_in[j]),
.D (),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OCLK (),
.OCLKB (),
.OFB (),
//.RST (iserdes_rst),
.RST (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
localparam IDELAYE2_CINVCTRL_SEL = "FALSE";
localparam IDELAYE2_DELAY_SRC = "IDATAIN";
localparam IDELAYE2_HIGH_PERFORMANCE_MODE = (IODELAY_HP_MODE=="ON") ? "TRUE":
"FALSE";
localparam IDELAYE2_IDELAY_TYPE = "VAR_LOAD";
localparam IDELAYE2_IDELAY_VALUE = 0;
localparam IDELAYE2_PIPE_SEL = "FALSE";
localparam IDELAYE2_ODELAY_TYPE = "FIXED";
localparam IDELAYE2_REFCLK_FREQUENCY = REFCLK_FREQ;
localparam IDELAYE2_SIGNAL_PATTERN = "DATA";
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2 #(
.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
.DELAY_SRC ( IDELAYE2_DELAY_SRC),
.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
.PIPE_SEL ( IDELAYE2_PIPE_SEL),
.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
)
idelaye2
(
.CNTVALUEOUT (idelay_cnt_out[j*5+4:j*5]),
.DATAOUT (data_in_dly[j]),
.C (phy_clk), //iserdes_clkdiv), // automatically wired by ISE
.CE (idelay_ce[j]),
.CINVCTRL (),
.CNTVALUEIN (idelay_cnt_in[j*5+4:j*5]), // 5-bit loadable delay tap number
.DATAIN (1'b0),
.IDATAIN (data_in[j]),
.INC (idelay_inc[j]),
.LD (idelay_ld),
.LDPIPEEN (1'b0),
.REGRST (iserdes_rst)
);
assign data_in[j] = I[j];
end // if block
end // for loop
endgenerate // iserdes_q_
localparam OSERDES_D_DATA_RATE_OQ = OSERDES_DATA_RATE;
localparam OSERDES_D_DATA_RATE_TQ = OSERDES_D_DATA_RATE_OQ;
localparam OSERDES_D_DATA_WIDTH = 4;
localparam OSERDES_D_DDR3_DATA = 0;
localparam OSERDES_D_INIT_OQ = 1'b1;
localparam OSERDES_D_INIT_TQ = 1'b1;
localparam OSERDES_D_INTERFACE_TYPE = "DEFAULT";
localparam OSERDES_D_ODELAY_USED = 0;
localparam OSERDES_D_SERDES_MODE = "MASTER";
localparam OSERDES_D_SRVAL_OQ = 1'b1;
localparam OSERDES_D_SRVAL_TQ = 1'b1;
localparam OSERDES_D_TRISTATE_WIDTH = (OSERDES_D_DATA_RATE_OQ == "DDR") ? 4 : 1;
//Tri-state location in a given byte lane
localparam TRI_STATE_LOC = 10;
localparam TRI_STATE_LOC_DOWN = 5; //location in OUT_FIFO
localparam BITLANES_TRI_STATE = 12'b0100_0000_0000;
//For now assume we will always have to generate a spare OSERDES for the tri-
//state for RLDRAM III
localparam EMPTY_TRI_STATE = (BITLANES_OUT[TRI_STATE_LOC] &&
BITLANES_TRI_STATE[TRI_STATE_LOC] &&
MEMORY_TYPE != "RLD3") ?
"FALSE" : "TRUE";
//Depending on the byte lane, if we are sharing the tri-state with another
//output-only OSERDES then we expect the tri-state to come from a certain byte
//lane from the OUT_FIFO
localparam SHIFT_TRI_STATE_MAP_UP = (EMPTY_TRI_STATE == "FALSE" &&
(ABCD == "A" || ABCD == "B")) ?
"TRUE" : "FALSE";
localparam SHIFT_TRI_STATE_MAP_DOWN = (EMPTY_TRI_STATE == "FALSE" &&
(ABCD == "C" || ABCD == "D")) ?
"TRUE" : "FALSE";
generate
//Tri-state signal comes from location next door (if used for other signal)
//else it comes from the regular location
if ( BYTE_TYPE == "BIDIR" && DATA_CTL_N == 1 ) begin : gen_tri_state
if (MEMORY_TYPE == "RLD3") begin : gen_rld3_tri_state
//Tri-state comes from the PHASER_OUT for the byte lane
assign oserdes_dqts = oserdes_dqts_in;
end else begin: gen_rld2_tri_state
assign oserdes_dqts = (SHIFT_TRI_STATE_MAP_UP == "TRUE") ?
oserdes_d[((TRI_STATE_LOC+1)*4)+:4] :
((SHIFT_TRI_STATE_MAP_DOWN == "TRUE") ?
oserdes_d[((TRI_STATE_LOC_DOWN)*4)+:4] :
oserdes_d[((TRI_STATE_LOC)*4)+:4]); //default location
end
end else begin: gen_tri_state_low
assign oserdes_dqts = 2'b0; //0 means data always driven out
end
// Generate a slave OSERDES to drive the tri-state
// Needs to be LOC'd in UCF
if ( BYTE_TYPE == "BIDIR" &&
DATA_CTL_N == 1 &&
EMPTY_TRI_STATE == "TRUE" ) begin : slave_ts
OSERDESE2 #(
//`UNISIM_OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_D_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_D_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_D_DATA_WIDTH),
.INIT_OQ (OSERDES_D_INIT_OQ),
.INIT_TQ (OSERDES_D_INIT_TQ),
.SERDES_MODE (OSERDES_D_SERDES_MODE),
.SRVAL_OQ (OSERDES_D_SRVAL_OQ),
.SRVAL_TQ (OSERDES_D_SRVAL_TQ),
.TBYTE_CTL ("TRUE"),
.TBYTE_SRC ("TRUE"),
.TRISTATE_WIDTH (OSERDES_D_TRISTATE_WIDTH)
//`ifdef FUJI_UNISIMS
//`else
// ,.DDR3_DATA (OSERDES_D_DDR3_DATA),
// .INTERFACE_TYPE (OSERDES_D_INTERFACE_TYPE),
// .ODELAY_USED (OSERDES_D_ODELAY_USED)
//`endif
)
oserdes_slave_ts
(
//-------------------------------------------------------------
// Outputs:
//-------------------------------------------------------------
// OQ: Data output
// TQ: Output of tristate mux
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// OFB: O Feedback output
// TFB: T Feedback output
//
//-------------------------------------------------------------
// Inputs:
//-------------------------------------------------------------
//
// Inputs:
// CLK: High speed clock from DCM
// CLKB: Inverted High speed clock from DCM
// CLKDIV: Low speed divided clock from DCM
// CLKPERF: Performance Path clock
// CLKPERFDELAY: delayed Performance Path clock
// D1, D2, D3, D4, D5, D6 : Data inputs
// OCE: Clock enable for output data flops
// ODV: ODELAY value > 140 degrees
// RST: Reset control
// T1, T2, T3, T4: tristate inputs
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
// TCE: Tristate clock enable
// WC: Write command given by memory controller
.OFB (),
.OQ (),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TBYTEOUT (tbyte_out),
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (),
.D2 (),
.D3 (),
.D4 (),
.D5 (1'b0),
.D6 (1'b0),
.D7 (1'b0),
.D8 (1'b0),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (1'b0), // not extended
.SHIFTIN2 (1'b0), // not extended
.T1 (oserdes_dqts[0]),
.T2 (oserdes_dqts[0]),
.T3 (oserdes_dqts[1]),
.T4 (oserdes_dqts[1]),
.TBYTEIN (tbyte_out),
.TCE (1'b1)
//`ifdef FUJI_UNISIMS
//`else
// ,.ODV (),
// .OCBEXTEND (), // ddr3 mode only
// .CLKPERF (), // ddr3 mode only
// .CLKPERFDELAY (), // ddr3 mode only
// .WC (1'b0) // ddr3 mode only
//`endif
);
end
genvar i;
for (i = 0; i != BUS_WIDTH; i=i+1) begin:o_serdesd_
assign O[i] = (BUFG_FOR_OUTPUTS == "ON") ? oserdes_data_delay_out[i] :
oserdes_data_out[i];
//Unidirectional Pin
if (!BITLANES_IN[i] && BITLANES_OUT[i] ) begin : gen_oserdes_uni
//check for OSERDES combined with tri-state control
if (BYTE_GROUP_TYPE == "BIDIR" && EMPTY_TRI_STATE == "FALSE" &&
BITLANES_TRI_STATE[i]) begin : gen_oserdes_uni_tri
OSERDESE2 #(
//`UNISIM_OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_D_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_D_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_D_DATA_WIDTH),
.INIT_OQ (OSERDES_D_INIT_OQ),
.INIT_TQ (OSERDES_D_INIT_TQ),
.SERDES_MODE (OSERDES_D_SERDES_MODE),
.SRVAL_OQ (OSERDES_D_SRVAL_OQ),
.SRVAL_TQ (OSERDES_D_SRVAL_TQ),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("TRUE"),
.TRISTATE_WIDTH (OSERDES_D_TRISTATE_WIDTH)
//`ifdef FUJI_UNISIMS
//`else
// ,.DDR3_DATA (OSERDES_D_DDR3_DATA),
// .INTERFACE_TYPE (OSERDES_D_INTERFACE_TYPE),
// .ODELAY_USED (OSERDES_D_ODELAY_USED)
//`endif
)
oserdes_d_i
(
//-------------------------------------------------------------
// Outputs:
//-------------------------------------------------------------
// OQ: Data output
// TQ: Output of tristate mux
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// OFB: O Feedback output
// TFB: T Feedback output
//
//-------------------------------------------------------------
// Inputs:
//-------------------------------------------------------------
//
// Inputs:
// CLK: High speed clock from DCM
// CLKB: Inverted High speed clock from DCM
// CLKDIV: Low speed divided clock from DCM
// CLKPERF: Performance Path clock
// CLKPERFDELAY: delayed Performance Path clock
// D1, D2, D3, D4, D5, D6 : Data inputs
// OCE: Clock enable for output data flops
// ODV: ODELAY value > 140 degrees
// RST: Reset control
// T1, T2, T3, T4: tristate inputs
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
// TCE: Tristate clock enable
// WC: Write command given by memory controller
.OFB (),
.OQ (oserdes_data_out[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TBYTEOUT (tbyte_out_uni),
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_d[4 * i + 0]),
.D2 (oserdes_d[4 * i + 1]),
.D3 (oserdes_d[4 * i + 2]),
.D4 (oserdes_d[4 * i + 3]),
.D5 (1'b0),
.D6 (1'b0),
.D7 (1'b0),
.D8 (1'b0),
.OCE (1'b1),
.RST (oserdes_rst),//fabric_oserdes_rst
.SHIFTIN1 (1'b0), // not extended
.SHIFTIN2 (1'b0), // not extended
.T1 (oserdes_dqts[0]),
.T2 (oserdes_dqts[0]),
.T3 (oserdes_dqts[1]),
.T4 (oserdes_dqts[1]),
.TBYTEIN (),
.TCE (1'b1)
//`ifdef FUJI_UNISIMS
//`else
// ,.ODV (),
// .OCBEXTEND (), // ddr3 mode only
// .CLKPERF (), // ddr3 mode only
// .CLKPERFDELAY (), // ddr3 mode only
// .WC (1'b0) // ddr3 mode only
//`endif
);
assign tbyte_out = tbyte_out_uni;
end else begin : gen_oserdes_uni_notri
OSERDESE2 #(
//`UNISIM_OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_D_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_D_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_D_DATA_WIDTH),
.INIT_OQ (OSERDES_D_INIT_OQ),
.INIT_TQ (OSERDES_D_INIT_TQ),
.SERDES_MODE (OSERDES_D_SERDES_MODE),
.SRVAL_OQ (OSERDES_D_SRVAL_OQ),
.SRVAL_TQ (OSERDES_D_SRVAL_TQ),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("FALSE"),
.TRISTATE_WIDTH (OSERDES_D_TRISTATE_WIDTH)
//`ifdef FUJI_UNISIMS
//`else
// ,.DDR3_DATA (OSERDES_D_DDR3_DATA),
// .INTERFACE_TYPE (OSERDES_D_INTERFACE_TYPE),
// .ODELAY_USED (OSERDES_D_ODELAY_USED)
//`endif
)
oserdes_d_i
(
//-------------------------------------------------------------
// Outputs:
//-------------------------------------------------------------
// OQ: Data output
// TQ: Output of tristate mux
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// OFB: O Feedback output
// TFB: T Feedback output
//
//-------------------------------------------------------------
// Inputs:
//-------------------------------------------------------------
//
// Inputs:
// CLK: High speed clock from DCM
// CLKB: Inverted High speed clock from DCM
// CLKDIV: Low speed divided clock from DCM
// CLKPERF: Performance Path clock
// CLKPERFDELAY: delayed Performance Path clock
// D1, D2, D3, D4, D5, D6 : Data inputs
// OCE: Clock enable for output data flops
// ODV: ODELAY value > 140 degrees
// RST: Reset control
// T1, T2, T3, T4: tristate inputs
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
// TCE: Tristate clock enable
// WC: Write command given by memory controller
.OFB (),
.OQ (oserdes_data_out[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TBYTEOUT (),
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_d[4 * i + 0]),
.D2 (oserdes_d[4 * i + 1]),
.D3 (oserdes_d[4 * i + 2]),
.D4 (oserdes_d[4 * i + 3]),
.D5 (1'b0),
.D6 (1'b0),
.D7 (1'b0),
.D8 (1'b0),
.OCE (1'b1),
.RST (oserdes_rst),//fabric_oserdes_rst
.SHIFTIN1 (1'b0), // not extended
.SHIFTIN2 (1'b0), // not extended
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TBYTEIN (),
.TCE (1'b1)
//`ifdef FUJI_UNISIMS
//`else
// ,.ODV (),
// .OCBEXTEND (), // ddr3 mode only
// .CLKPERF (), // ddr3 mode only
// .CLKPERFDELAY (), // ddr3 mode only
// .WC (1'b0) // ddr3 mode only
//`endif
);
end
end else if (BITLANES_IN[i] && BITLANES_OUT[i]) begin : gen_oserdes_bidir
OSERDESE2 #(
//`UNISIM_OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_D_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_D_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_D_DATA_WIDTH),
.INIT_OQ (OSERDES_D_INIT_OQ),
.INIT_TQ (OSERDES_D_INIT_TQ),
.SERDES_MODE (OSERDES_D_SERDES_MODE),
.SRVAL_OQ (OSERDES_D_SRVAL_OQ),
.SRVAL_TQ (OSERDES_D_SRVAL_TQ),
.TBYTE_CTL ("TRUE"),
.TBYTE_SRC ("FALSE"),
.TRISTATE_WIDTH (OSERDES_D_TRISTATE_WIDTH)
//`ifdef FUJI_UNISIMS
//`else
// ,.DDR3_DATA (OSERDES_D_DDR3_DATA),
// .INTERFACE_TYPE (OSERDES_D_INTERFACE_TYPE),
// .ODELAY_USED (OSERDES_D_ODELAY_USED)
//`endif
)
oserdes_d_i
(
//-------------------------------------------------------------
// Outputs:
//-------------------------------------------------------------
// OQ: Data output
// TQ: Output of tristate mux
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// OFB: O Feedback output
// TFB: T Feedback output
//
//-------------------------------------------------------------
// Inputs:
//-------------------------------------------------------------
//
// Inputs:
// CLK: High speed clock from DCM
// CLKB: Inverted High speed clock from DCM
// CLKDIV: Low speed divided clock from DCM
// CLKPERF: Performance Path clock
// CLKPERFDELAY: delayed Performance Path clock
// D1, D2, D3, D4, D5, D6 : Data inputs
// OCE: Clock enable for output data flops
// ODV: ODELAY value > 140 degrees
// RST: Reset control
// T1, T2, T3, T4: tristate inputs
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
// TCE: Tristate clock enable
// WC: Write command given by memory controller
.OFB (),
.OQ (oserdes_data_out[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TBYTEOUT (),
.TFB (),
.TQ (mem_dq_ts[i]), //(O) tristate enable
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_d[4 * i + 0]),
.D2 (oserdes_d[4 * i + 1]),
.D3 (oserdes_d[4 * i + 2]),
.D4 (oserdes_d[4 * i + 3]),
.D5 (1'b0),
.D6 (1'b0),
.D7 (1'b0),
.D8 (1'b0),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (1'b0), // not extended
.SHIFTIN2 (1'b0), // not extended
.T1 (oserdes_dqts[0]),
.T2 (oserdes_dqts[0]),
.T3 (oserdes_dqts[1]),
.T4 (oserdes_dqts[1]),
.TBYTEIN (tbyte_out),
.TCE (1'b1)
//`ifdef FUJI_UNISIMS
//`else
// ,.ODV (),
// .OCBEXTEND (), // ddr3 mode only
// .CLKPERF (), // ddr3 mode only
// .CLKPERFDELAY (), // ddr3 mode only
// .WC (1'b0) // ddr3 mode only
//`endif
);
end// conditional generate
if (BUFG_FOR_OUTPUTS == "ON") begin : gen_odelay
(* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2 #(
.CINVCTRL_SEL ( "FALSE"),
.DELAY_SRC ( "ODATAIN"), //ODATAIN or CLKIN
.HIGH_PERFORMANCE_MODE ((IODELAY_HP_MODE=="ON") ? "TRUE": "FALSE"),
.ODELAY_TYPE ( "FIXED"),
.ODELAY_VALUE ( (DATA_CTL_N == 1) ? 0 : ODELAY_90_SHIFT ),
.PIPE_SEL ( "FALSE"),
.REFCLK_FREQUENCY ( REFCLK_FREQ ),
.SIGNAL_PATTERN ( "DATA")
)
u_odelaye2_i
(
.CNTVALUEOUT (),
.DATAOUT (oserdes_data_delay_out[i]), //delayed signal
.C (oserdes_clkdiv),
.CE (1'b0),
.CINVCTRL (1'b0),
.CLKIN (), //clock delay input
.CNTVALUEIN (5'b0),
.INC (1'b0),
.LD (1'b0),
.LDPIPEEN (1'b0),
.ODATAIN (oserdes_data_out[i]),//output delay data input
.REGRST (oserdes_rst)
);
end
//Used for RLDRAM III where the clock is placed on a non-dqs pin pair
//Since it's a differential pair we generate an OBUFDS and send out N-side
//as well. As long as there is no mistake in the mapping this should work fine
if (DATA_CTL_N == 0 && CK_P_OUT[i]) begin : gen_ck
ODDR #
(
.DDR_CLK_EDGE ("SAME_EDGE")
)
ddr_ck (
.C (oserdes_clk),
.R (oserdes_rst),
.S (),
.D1 (CK_VALUE_D1),
.D2 (~CK_VALUE_D1),
.CE (1'b1),
.Q (ddr_ck_out_q[i])
);
OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]),
.O(oserdes_data_out[i]), .OB(oserdes_data_out[i-1]));
end
end // o_serdes_d_ for loop
endgenerate
endmodule // qdr_rld_byte_group_io
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_1_V
`define SKY130_FD_SC_HVL__MUX4_1_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// both inputs are considered unsigned 16 bits-
// ddata is delay matched generic data
`timescale 1ps/1ps
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
// delay interface
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg [DW:0] ddata_in_d = 'd0;
reg [16:0] data_a_p = 'd0;
reg [16:0] data_a_n = 'd0;
reg [15:0] data_b_d = 'd0;
reg [DW:0] p1_ddata = 'd0;
reg [31:0] p1_data_p_0 = 'd0;
reg [31:0] p1_data_p_1 = 'd0;
reg [31:0] p1_data_p_2 = 'd0;
reg [31:0] p1_data_p_3 = 'd0;
reg [31:0] p1_data_p_4 = 'd0;
reg [31:0] p1_data_p_5 = 'd0;
reg [31:0] p1_data_p_6 = 'd0;
reg [31:0] p1_data_p_7 = 'd0;
reg [31:0] p1_data_p_8 = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [31:0] p2_data_p_0 = 'd0;
reg [31:0] p2_data_p_1 = 'd0;
reg [31:0] p2_data_p_2 = 'd0;
reg [31:0] p2_data_p_3 = 'd0;
reg [31:0] p2_data_p_4 = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [31:0] p3_data_p_0 = 'd0;
reg [31:0] p3_data_p_1 = 'd0;
reg [31:0] p3_data_p_2 = 'd0;
reg [DW:0] p4_ddata = 'd0;
reg [31:0] p4_data_p_0 = 'd0;
reg [31:0] p4_data_p_1 = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [31:0] data_p = 'd0;
// internal signals
wire [16:0] data_a_p_17_s;
wire [16:0] data_a_n_17_s;
wire [31:0] p1_data_a_1p_s;
wire [31:0] p1_data_a_1n_s;
wire [31:0] p1_data_a_2p_s;
wire [31:0] p1_data_a_2n_s;
// pipe line stage 0, get the two's complement versions
assign data_a_p_17_s = {1'b0, data_a};
assign data_a_n_17_s = ~data_a_p_17_s + 1'b1;
always @(posedge clk) begin
ddata_in_d <= ddata_in;
data_a_p <= data_a_p_17_s;
data_a_n <= data_a_n_17_s;
data_b_d <= data_b;
end
// pipe line stage 1, get the partial products
assign p1_data_a_1p_s = {{15{data_a_p[16]}}, data_a_p};
assign p1_data_a_1n_s = {{15{data_a_n[16]}}, data_a_n};
assign p1_data_a_2p_s = {{14{data_a_p[16]}}, data_a_p, 1'b0};
assign p1_data_a_2n_s = {{14{data_a_n[16]}}, data_a_n, 1'b0};
always @(posedge clk) begin
p1_ddata <= ddata_in_d;
case (data_b_d[1:0])
2'b11: p1_data_p_0 <= p1_data_a_1n_s;
2'b10: p1_data_p_0 <= p1_data_a_2n_s;
2'b01: p1_data_p_0 <= p1_data_a_1p_s;
default: p1_data_p_0 <= 32'd0;
endcase
case (data_b_d[3:1])
3'b011: p1_data_p_1 <= {p1_data_a_2p_s[29:0], 2'd0};
3'b100: p1_data_p_1 <= {p1_data_a_2n_s[29:0], 2'd0};
3'b001: p1_data_p_1 <= {p1_data_a_1p_s[29:0], 2'd0};
3'b010: p1_data_p_1 <= {p1_data_a_1p_s[29:0], 2'd0};
3'b101: p1_data_p_1 <= {p1_data_a_1n_s[29:0], 2'd0};
3'b110: p1_data_p_1 <= {p1_data_a_1n_s[29:0], 2'd0};
default: p1_data_p_1 <= 32'd0;
endcase
case (data_b_d[5:3])
3'b011: p1_data_p_2 <= {p1_data_a_2p_s[27:0], 4'd0};
3'b100: p1_data_p_2 <= {p1_data_a_2n_s[27:0], 4'd0};
3'b001: p1_data_p_2 <= {p1_data_a_1p_s[27:0], 4'd0};
3'b010: p1_data_p_2 <= {p1_data_a_1p_s[27:0], 4'd0};
3'b101: p1_data_p_2 <= {p1_data_a_1n_s[27:0], 4'd0};
3'b110: p1_data_p_2 <= {p1_data_a_1n_s[27:0], 4'd0};
default: p1_data_p_2 <= 32'd0;
endcase
case (data_b_d[7:5])
3'b011: p1_data_p_3 <= {p1_data_a_2p_s[25:0], 6'd0};
3'b100: p1_data_p_3 <= {p1_data_a_2n_s[25:0], 6'd0};
3'b001: p1_data_p_3 <= {p1_data_a_1p_s[25:0], 6'd0};
3'b010: p1_data_p_3 <= {p1_data_a_1p_s[25:0], 6'd0};
3'b101: p1_data_p_3 <= {p1_data_a_1n_s[25:0], 6'd0};
3'b110: p1_data_p_3 <= {p1_data_a_1n_s[25:0], 6'd0};
default: p1_data_p_3 <= 32'd0;
endcase
case (data_b_d[9:7])
3'b011: p1_data_p_4 <= {p1_data_a_2p_s[23:0], 8'd0};
3'b100: p1_data_p_4 <= {p1_data_a_2n_s[23:0], 8'd0};
3'b001: p1_data_p_4 <= {p1_data_a_1p_s[23:0], 8'd0};
3'b010: p1_data_p_4 <= {p1_data_a_1p_s[23:0], 8'd0};
3'b101: p1_data_p_4 <= {p1_data_a_1n_s[23:0], 8'd0};
3'b110: p1_data_p_4 <= {p1_data_a_1n_s[23:0], 8'd0};
default: p1_data_p_4 <= 32'd0;
endcase
case (data_b_d[11:9])
3'b011: p1_data_p_5 <= {p1_data_a_2p_s[21:0], 10'd0};
3'b100: p1_data_p_5 <= {p1_data_a_2n_s[21:0], 10'd0};
3'b001: p1_data_p_5 <= {p1_data_a_1p_s[21:0], 10'd0};
3'b010: p1_data_p_5 <= {p1_data_a_1p_s[21:0], 10'd0};
3'b101: p1_data_p_5 <= {p1_data_a_1n_s[21:0], 10'd0};
3'b110: p1_data_p_5 <= {p1_data_a_1n_s[21:0], 10'd0};
default: p1_data_p_5 <= 32'd0;
endcase
case (data_b_d[13:11])
3'b011: p1_data_p_6 <= {p1_data_a_2p_s[19:0], 12'd0};
3'b100: p1_data_p_6 <= {p1_data_a_2n_s[19:0], 12'd0};
3'b001: p1_data_p_6 <= {p1_data_a_1p_s[19:0], 12'd0};
3'b010: p1_data_p_6 <= {p1_data_a_1p_s[19:0], 12'd0};
3'b101: p1_data_p_6 <= {p1_data_a_1n_s[19:0], 12'd0};
3'b110: p1_data_p_6 <= {p1_data_a_1n_s[19:0], 12'd0};
default: p1_data_p_6 <= 32'd0;
endcase
case (data_b_d[15:13])
3'b011: p1_data_p_7 <= {p1_data_a_2p_s[17:0], 14'd0};
3'b100: p1_data_p_7 <= {p1_data_a_2n_s[17:0], 14'd0};
3'b001: p1_data_p_7 <= {p1_data_a_1p_s[17:0], 14'd0};
3'b010: p1_data_p_7 <= {p1_data_a_1p_s[17:0], 14'd0};
3'b101: p1_data_p_7 <= {p1_data_a_1n_s[17:0], 14'd0};
3'b110: p1_data_p_7 <= {p1_data_a_1n_s[17:0], 14'd0};
default: p1_data_p_7 <= 32'd0;
endcase
case (data_b_d[15])
1'b1: p1_data_p_8 <= {p1_data_a_1p_s[15:0], 16'd0};
default: p1_data_p_8 <= 32'd0;
endcase
end
// pipe line stage 2, sum (intermediate 9 -> 5)
always @(posedge clk) begin
p2_ddata <= p1_ddata;
p2_data_p_0 <= p1_data_p_0 + p1_data_p_1;
p2_data_p_1 <= p1_data_p_2 + p1_data_p_3;
p2_data_p_2 <= p1_data_p_4 + p1_data_p_5;
p2_data_p_3 <= p1_data_p_6 + p1_data_p_7;
p2_data_p_4 <= p1_data_p_8;
end
// pipe line stage 3, sum (intermediate 5 -> 3)
always @(posedge clk) begin
p3_ddata <= p2_ddata;
p3_data_p_0 <= p2_data_p_0 + p2_data_p_4;
p3_data_p_1 <= p2_data_p_1 + p2_data_p_2;
p3_data_p_2 <= p2_data_p_3;
end
// pipe line stage 4, sum (intermediate 3 -> 2)
always @(posedge clk) begin
p4_ddata <= p3_ddata;
p4_data_p_0 <= p3_data_p_0 + p3_data_p_2;
p4_data_p_1 <= p3_data_p_1;
end
// piple line stage 5, output registers
always @(posedge clk) begin
ddata_out <= p4_ddata;
data_p <= p4_data_p_0 + p4_data_p_1;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_tdd_cntrl #(
parameter ID = 0) (
input clk,
input rst,
//rf tdd interface control
output tdd_enable,
output tdd_secondary,
output tdd_rx_only,
output tdd_tx_only,
output tdd_gated_rx_dmapath,
output tdd_gated_tx_dmapath,
output [ 7:0] tdd_burst_count,
output [23:0] tdd_counter_init,
output [23:0] tdd_frame_length,
output tdd_terminal_type,
output [23:0] tdd_vco_rx_on_1,
output [23:0] tdd_vco_rx_off_1,
output [23:0] tdd_vco_tx_on_1,
output [23:0] tdd_vco_tx_off_1,
output [23:0] tdd_rx_on_1,
output [23:0] tdd_rx_off_1,
output [23:0] tdd_rx_dp_on_1,
output [23:0] tdd_rx_dp_off_1,
output [23:0] tdd_tx_on_1,
output [23:0] tdd_tx_off_1,
output [23:0] tdd_tx_dp_on_1,
output [23:0] tdd_tx_dp_off_1,
output [23:0] tdd_vco_rx_on_2,
output [23:0] tdd_vco_rx_off_2,
output [23:0] tdd_vco_tx_on_2,
output [23:0] tdd_vco_tx_off_2,
output [23:0] tdd_rx_on_2,
output [23:0] tdd_rx_off_2,
output [23:0] tdd_rx_dp_on_2,
output [23:0] tdd_rx_dp_off_2,
output [23:0] tdd_tx_on_2,
output [23:0] tdd_tx_off_2,
output [23:0] tdd_tx_dp_on_2,
output [23:0] tdd_tx_dp_off_2,
input [ 7:0] tdd_status,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
localparam PCORE_VERSION = 32'h00010061;
// internal registers
reg [31:0] up_scratch = 32'h0;
reg up_tdd_enable = 1'h0;
reg up_tdd_secondary = 1'h0;
reg up_tdd_rx_only = 1'h0;
reg up_tdd_tx_only = 1'h0;
reg up_tdd_gated_tx_dmapath = 1'h0;
reg up_tdd_gated_rx_dmapath = 1'h0;
reg up_tdd_terminal_type = 1'h0;
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
reg [23:0] up_tdd_frame_length = 24'h0;
reg [23:0] up_tdd_vco_rx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_on_1 = 24'h0;
reg [23:0] up_tdd_rx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_rx_dp_off_1 = 24'h0;
reg [23:0] up_tdd_tx_on_1 = 24'h0;
reg [23:0] up_tdd_tx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_on_2 = 24'h0;
reg [23:0] up_tdd_rx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_rx_dp_off_2 = 24'h0;
reg [23:0] up_tdd_tx_on_2 = 24'h0;
reg [23:0] up_tdd_tx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_2 = 24'h0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 7:0] up_tdd_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
up_tdd_rx_only <= 1'h0;
up_tdd_tx_only <= 1'h0;
up_tdd_gated_tx_dmapath <= 1'h0;
up_tdd_gated_rx_dmapath <= 1'h0;
up_tdd_terminal_type <= 1'h0;
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
up_tdd_vco_rx_on_1 <= 24'h0;
up_tdd_vco_rx_off_1 <= 24'h0;
up_tdd_vco_tx_on_1 <= 24'h0;
up_tdd_vco_tx_off_1 <= 24'h0;
up_tdd_rx_on_1 <= 24'h0;
up_tdd_rx_off_1 <= 24'h0;
up_tdd_rx_dp_on_1 <= 24'h0;
up_tdd_rx_dp_off_1 <= 24'h0;
up_tdd_tx_on_1 <= 24'h0;
up_tdd_tx_off_1 <= 24'h0;
up_tdd_tx_dp_on_1 <= 24'h0;
up_tdd_tx_dp_off_1 <= 24'h0;
up_tdd_vco_rx_on_2 <= 24'h0;
up_tdd_vco_rx_off_2 <= 24'h0;
up_tdd_vco_tx_on_2 <= 24'h0;
up_tdd_vco_tx_off_2 <= 24'h0;
up_tdd_rx_on_2 <= 24'h0;
up_tdd_rx_off_2 <= 24'h0;
up_tdd_rx_dp_on_2 <= 24'h0;
up_tdd_rx_dp_off_2 <= 24'h0;
up_tdd_tx_on_2 <= 24'h0;
up_tdd_tx_off_2 <= 24'h0;
up_tdd_tx_dp_on_2 <= 24'h0;
up_tdd_tx_dp_off_2 <= 24'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_tdd_enable <= up_wdata[0];
up_tdd_secondary <= up_wdata[1];
up_tdd_rx_only <= up_wdata[2];
up_tdd_tx_only <= up_wdata[3];
up_tdd_gated_rx_dmapath <= up_wdata[4];
up_tdd_gated_tx_dmapath <= up_wdata[5];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_burst_count <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_tdd_counter_init <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_tdd_frame_length <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_tdd_terminal_type <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tdd_vco_rx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_tdd_rx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin
up_tdd_rx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin
up_tdd_tx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin
up_tdd_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_tdd_rx_dp_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_tdd_rx_dp_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin
up_tdd_tx_dp_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin
up_tdd_tx_dp_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
up_tdd_vco_rx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin
up_tdd_vco_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
up_tdd_vco_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
up_tdd_vco_tx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin
up_tdd_rx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin
up_tdd_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin
up_tdd_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
up_tdd_tx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
up_tdd_rx_dp_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
up_tdd_rx_dp_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin
up_tdd_tx_dp_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3b)) begin
up_tdd_tx_dp_off_2 <= up_wdata[23:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 1'b0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath,
up_tdd_gated_rx_dmapath,
up_tdd_tx_only,
up_tdd_rx_only,
up_tdd_secondary,
up_tdd_enable};
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
8'h14: up_rdata <= {31'h0, up_tdd_terminal_type};
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
8'h22: up_rdata <= { 8'h0, up_tdd_vco_tx_on_1};
8'h23: up_rdata <= { 8'h0, up_tdd_vco_tx_off_1};
8'h24: up_rdata <= { 8'h0, up_tdd_rx_on_1};
8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1};
8'h28: up_rdata <= { 8'h0, up_tdd_rx_dp_on_1};
8'h29: up_rdata <= { 8'h0, up_tdd_rx_dp_off_1};
8'h2a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
8'h2b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2};
8'h33: up_rdata <= { 8'h0, up_tdd_vco_tx_off_2};
8'h34: up_rdata <= { 8'h0, up_tdd_rx_on_2};
8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2};
8'h38: up_rdata <= { 8'h0, up_tdd_rx_dp_on_2};
8'h39: up_rdata <= { 8'h0, up_tdd_rx_dp_off_2};
8'h3a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
8'h3b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
default: up_rdata <= 32'h0;
endcase
end
end
end
// rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_tdd_control (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_secondary,
up_tdd_rx_only,
up_tdd_tx_only,
up_tdd_gated_rx_dmapath,
up_tdd_gated_tx_dmapath,
up_tdd_burst_count,
up_tdd_terminal_type
}),
.up_xfer_done(),
.d_rst(rst),
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_secondary,
tdd_rx_only,
tdd_tx_only,
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
tdd_burst_count,
tdd_terminal_type
}));
up_xfer_cntrl #(.DATA_WIDTH(624)) i_xfer_tdd_counter_values (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init,
up_tdd_frame_length,
up_tdd_vco_rx_on_1,
up_tdd_vco_rx_off_1,
up_tdd_vco_tx_on_1,
up_tdd_vco_tx_off_1,
up_tdd_rx_on_1,
up_tdd_rx_off_1,
up_tdd_tx_on_1,
up_tdd_tx_off_1,
up_tdd_rx_dp_on_1,
up_tdd_rx_dp_off_1,
up_tdd_tx_dp_on_1,
up_tdd_tx_dp_off_1,
up_tdd_vco_rx_on_2,
up_tdd_vco_rx_off_2,
up_tdd_vco_tx_on_2,
up_tdd_vco_tx_off_2,
up_tdd_rx_on_2,
up_tdd_rx_off_2,
up_tdd_tx_on_2,
up_tdd_tx_off_2,
up_tdd_rx_dp_on_2,
up_tdd_rx_dp_off_2,
up_tdd_tx_dp_on_2,
up_tdd_tx_dp_off_2
}),
.up_xfer_done(),
.d_rst(rst),
.d_clk(clk),
.d_data_cntrl({tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_rx_dp_on_1,
tdd_rx_dp_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_rx_dp_on_2,
tdd_rx_dp_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2
}));
up_xfer_status #(.DATA_WIDTH(8)) i_xfer_tdd_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_tdd_status_s),
.d_rst (rst),
.d_clk (clk),
.d_data_status (tdd_status));
endmodule
// ***************************************************************************
// ***************************************************************************
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