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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: California State University, Fullerton
// Engineer: Lucas Magasweran, Alan Nguyen
//
// Create Date: 17:31:25 11/16/2011
// Design Name: 8x8 Robertson's Multiplier
// Module Name: toprobertsons
// Project Name: EE557 Homework #4
// Target Devices: Simululator (xc3sd1800a-4fg676)
// Tool versions: Xilinx ISE 13.1
// Description:
// This multiplier implements the Robertson's algorithm (that was discussed
// in class) for the multiplication of two signed binary numbers in 2's
// complement format. In your design, the multiplicand must be placed in a
// register called Y. Two more registers, A and X, must also be used in your
// design. The register A is initially loaded with all 0s and the register X is
// initially loaded with the multiplier. A and X, combined, acts as a shift
// register (A:X). You may use additional hardware structures as necessary to
// complete your design. The final product must be stored in the shift register
// A:X.
// Dependencies: none.
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module toprobertsons(
input clk, reset,
input [7:0] multiplier, // 8-bit data input to multiplier unit
input [7:0] multiplicand, // 8-bit data input to multiplier unit
output [15:0] product, // 16-bit data output of multiplier unit
output done // flag to signal multiplication is complete to testbench
);
// instantiate Robertson's Multiplier
robsmult mult(clk, reset, multiplier, multiplicand, product, done);
// instantiate signed multipler (used for testing testbench)
//signed_mult mult(product, clk, multiplier, multiplicand);
endmodule
|
module uniphy_status
#(
parameter WIDTH=32,
parameter NUM_UNIPHYS=2
)
(
input clk,
input resetn,
// Slave port
input slave_read,
output [WIDTH-1:0] slave_readdata,
// hw.tcl won't let me index into a bit vector :(
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
input mem2_local_cal_success,
input mem2_local_cal_fail,
input mem2_local_init_done,
input mem3_local_cal_success,
input mem3_local_cal_fail,
input mem3_local_init_done,
input mem4_local_cal_success,
input mem4_local_cal_fail,
input mem4_local_init_done,
input mem5_local_cal_success,
input mem5_local_cal_fail,
input mem5_local_init_done,
input mem6_local_cal_success,
input mem6_local_cal_fail,
input mem6_local_init_done,
input mem7_local_cal_success,
input mem7_local_cal_fail,
input mem7_local_init_done,
output export_local_cal_success,
output export_local_cal_fail,
output export_local_init_done
);
reg [WIDTH-1:0] aggregate_uniphy_status;
wire local_cal_success;
wire local_cal_fail;
wire local_init_done;
wire [NUM_UNIPHYS-1:0] not_init_done;
wire [7:0] mask;
assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS);
assign local_cal_success = &( ~mask | {mem7_local_cal_success,
mem6_local_cal_success,
mem5_local_cal_success,
mem4_local_cal_success,
mem3_local_cal_success,
mem2_local_cal_success,
mem1_local_cal_success,
mem0_local_cal_success});
assign local_cal_fail = mem0_local_cal_fail |
mem1_local_cal_fail |
mem2_local_cal_fail |
mem3_local_cal_fail |
mem4_local_cal_fail |
mem5_local_cal_fail |
mem6_local_cal_fail |
mem7_local_cal_fail;
assign local_init_done = &( ~mask |{mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done});
assign not_init_done = mask & ~{ mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done};
// Desire status==0 to imply success - may cause false positives, but the
// alternative is headaches for non-uniphy memories.
// Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone
always@(posedge clk or negedge resetn)
if (!resetn)
aggregate_uniphy_status <= {WIDTH{1'b0}};
else
aggregate_uniphy_status <= { not_init_done, 1'b0,
{~local_cal_success,local_cal_fail,~local_init_done}
};
assign slave_readdata = aggregate_uniphy_status;
assign export_local_cal_success = local_cal_success;
assign export_local_cal_fail = local_cal_fail;
assign export_local_init_done = local_init_done;
endmodule
|
`timescale 1ns/10ps
/*
功能：生成SPI控制信号
输入：nrst, clk, bitcnt
输出：sig_last, sig_tc
*/
module sspi_sig(nrst, clk, bitcnt, sig_last, sig_tc);
input nrst;
input clk;
input [2:0] bitcnt;
output sig_last;
output sig_tc;
reg bits7_r;
wire bits7;
assign bits7 = (bitcnt == 3'b111);
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
bits7_r <= 1'b0;
end else begin
bits7_r <= bits7;
end
end
assign sig_tc = ({bits7_r, bits7} == 2'b10);
assign sig_last = ({bits7_r, bits7} == 2'b01);
endmodule
/*
功能：同步SPI输入信号
输入：nrst, clk, cs, sck, si
输出：cs_s, sck_p, sck_n, si_s
*/
module sspi_sync(nrst, clk, cs, sck, si, cs_s, sck_p, sck_n, si_s);
input nrst;
input clk;
input cs;
input sck;
input si;
output cs_s;
output sck_p;
output sck_n;
output si_s;
reg [1:0] cs_r;
reg [1:0] si_r;
reg [2:0] sck_r;
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
sck_r <= 3'b111;
cs_r <= 2'b11;
si_r <= 2'b00;
end else begin
sck_r <= {sck_r[1:0], sck};
cs_r <= {cs_r[0], cs};
si_r <= {si_r[0], si};
end
end
assign sck_p = (sck_r[2:1] == 2'b01);
assign sck_n = (sck_r[2:1] == 2'b10);
assign cs_s = cs_r[1];
assign si_s = si_r[1];
endmodule
/*
功能：串并转换
输入：nrst-0复位
clk-时钟
en-1使能
si-串行输入
load-1并行加载
pi-并行输入
输出：po-并行输出
*/
module s2p(nrst, clk, en, si, load, pi, po);
parameter width = 8;
input nrst;
input clk;
input en;
input si;
input load;
input [width-1:0] pi;
output [width-1:0] po;
reg [width-1:0] po;
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
po <= 0;
end else if (load) begin
po <= pi;
end else if (en) begin
po <= {po[width-2:0], si};
end
end
endmodule
/*
功能：SPI从接口
极性：SPI模式3，SCLK空闲状态为高电平，在上升沿采样（第二个边沿）
协议：首字节bit[7:1]为地址，bit[0]为读(0)/写(1)，后续字节为数据
读格式：MOSI: 地址[7]|0[1]|dummy[n*8]
MISO: 0[8]|读出的数据[n*8]
写格式：MOSI: 地址[7]|1[1]|要写入的数据[n*8]
MISO: 0[8]|原始值[8]|被写入的数据[(n-1)*8]
输入：nrst, clk, cs, sck, si, din
输出：so, addr, dout, rd, we
修改：eleqian 2016-01-9
*/
module sspi(nrst, clk, cs, sck, si, so, addr, din, dout, rd, we);
input nrst;
input clk;
input cs;
input sck;
input si;
output so;
output [6:0] addr;
input [7:0] din;
output [7:0] dout;
output rd;
output we;
//reg so;
reg [6:0] addr;
reg d_na; // 1-dat/0-addr
reg w_nr; // 1-write/0-read
wire cs_s;
wire sck_p;
wire sck_n;
wire si_s;
wire [7:0] data;
wire [2:0] bitcnt;
wire sig_tc;
wire sig_last;
// 同步输入信号
sspi_sync u_sync(.nrst(nrst), .clk(clk), .cs(cs), .sck(sck), .si(si),
.cs_s(cs_s), .sck_p(sck_p), .sck_n(sck_n), .si_s(si_s));
// bit计数
cntn #(3) u_cnt(.nrst(nrst), .clk(clk), .en(sck_p), .step(1), .load(cs_s), .cin(0), .cnt(bitcnt));
// 产生传输完成信号
sspi_sig u_sig(.nrst(nrst), .clk(clk), .bitcnt(bitcnt), .sig_last(sig_last), .sig_tc(sig_tc));
// 产生数据读写信号
assign we = w_nr && sig_tc;
assign rd = ~w_nr && sig_tc;
// 接收数据
s2p u_s2p(.nrst(nrst), .clk(clk), .en(sck_p), .si(si_s),
.load(rd), .pi(din), .po(data));
assign dout = data;
// 发送数据
/*always @(negedge sck or negedge nrst) begin
if (~nrst) begin
so <= 1'b0;
end else begin
so <= data[7];
end
end*/
// 为提高sck速率，miso不由sck下降沿同步，否则可能建立时间不满足
// 因为对sck同步已延迟2~3个clk，通常满足miso保持时间
assign so = data[7];
// 地址/数据状态转换
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
d_na <= 1'b0;
end else if (cs_s) begin
d_na <= 1'b0;
end else if (sig_tc) begin
d_na <= 1'b1;
end
end
// 接收读写标志
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
w_nr <= 1'b0;
end else if (cs_s) begin
w_nr <= 1'b0;
end else if (~d_na && sig_tc) begin
w_nr <= data[0];
end
end
// 接收地址
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
addr <= 7'b0;
end else if (~d_na && sig_last) begin
addr <= data[6:0];
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : rotating unit, stays between 2 stages of FFT pipeline
// FUNCTION: complex multiplication to the twiddle factors proper to the 64 point FFT
// for any type FPGAs and ASIC.
// FILES: ROTATOR256_v.v - this file,
// WROM256.v - ROM of twiddle factors.
// PROPERTIES: 1) Has 256-clock cycle period starting with the START impulse
// and continuing forever
// 2) rounding is not used
// 3)intended for synthesizing
//
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1ns / 1ps
`include "FFT256_CONFIG.inc"
module ROTATOR64 (CLK ,RST,ED,START, DR,DI, DOR, DOI,RDY );
`FFT256paramnb
`FFT256paramnw
input RST ;
wire RST ;
input CLK ;
wire CLK ;
input ED ; //operation enable
input [nb-1:0] DI; //Imaginary part of data
wire [nb-1:0] DI ;
input [nb-1:0] DR ; //Real part of data
input START ; //1-st Data is entered after this impulse
wire START ;
output [nb-1:0] DOI ; //Imaginary part of data
wire [nb-1:0] DOI ;
output [nb-1:0] DOR ; //Real part of data
wire [nb-1:0] DOR ;
output RDY ; //repeats START impulse following the output data
reg RDY ;
reg [7:0] addrw;
reg sd1,sd2;
always @( posedge CLK) //address counter for twiddle factors
begin
if (RST) begin
addrw<=0;
sd1<=0;
sd2<=0;
end
else if (START && ED) begin
addrw[7:0]<=0;
sd1<=START;
sd2<=0;
end
else if (ED) begin
addrw<=addrw+1;
sd1<=START;
sd2<=sd1;
RDY<=sd2;
end
end
wire signed [nw-1:0] wr,wi; //twiddle factor coefficients
//twiddle factor ROM
WROM256 UROM( .ADDR(addrw), .WR(wr),.WI(wi) );
reg signed [nb-1 : 0] drd,did;
reg signed [nw-1 : 0] wrd,wid;
wire signed [nw+nb-1 : 0] drri,drii,diri,diii;
reg signed [nb:0] drr,dri,dir,dii,dwr,dwi;
assign drri=drd*wrd;
assign diri=did*wrd;
assign drii=drd*wid;
assign diii=did*wid;
always @(posedge CLK) //complex multiplier
begin
if (ED) begin
drd<=DR;
did<=DI;
wrd<=wr;
wid<=wi;
drr<=drri[nw+nb-1 :nw-1]; //msbs of multiplications are stored
dri<=drii[nw+nb-1 : nw-1];
dir<=diri[nw+nb-1 : nw-1];
dii<=diii[nw+nb-1 : nw-1];
dwr<=drr - dii;
dwi<=dri + dir;
end
end
assign DOR=dwr[nb:1];
assign DOI=dwi[nb:1];
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:53:17 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/system_rgb565_to_rgb888_1_0_sim_netlist.v
// Design : system_rgb565_to_rgb888_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rgb565_to_rgb888_1_0,rgb565_to_rgb888,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb565_to_rgb888_1_0
(rgb_565,
rgb_888);
input [15:0]rgb_565;
output [23:0]rgb_888;
wire \<const0> ;
wire [15:0]rgb_565;
assign rgb_888[23:19] = rgb_565[15:11];
assign rgb_888[18:16] = rgb_565[15:13];
assign rgb_888[15:10] = rgb_565[10:5];
assign rgb_888[9:8] = rgb_565[10:9];
assign rgb_888[7:3] = rgb_565[4:0];
assign rgb_888[2] = \<const0> ;
assign rgb_888[1] = \<const0> ;
assign rgb_888[0] = \<const0> ;
GND GND
(.G(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//==========================================
// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
// Coder : Alex Claros F.
// Date : 15/May/2005.
// Notes : This implementation is based on the article
// 'Asynchronous FIFO in Virtex-II FPGAs'
// writen by Peter Alfke. This TechXclusive
// article can be downloaded from the
// Xilinx website. It has some minor modifications.
//=========================================
`timescale 1ns / 1ps
module vgafb_asfifo
#(parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH))
//Reading port
(output wire [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Writing port.
input wire [DATA_WIDTH-1:0] Data_in,
output reg Full_out,
input wire WriteEn_in,
input wire WClk,
input wire Clear_in);
/////Internal connections & variables//////
reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0];
wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
wire EqualAddresses;
wire NextWriteAddressEn, NextReadAddressEn;
wire Set_Status, Rst_Status;
reg Status;
wire PresetFull, PresetEmpty;
//////////////Code///////////////
//Data ports logic:
//(Uses a dual-port RAM).
//'Data_out' logic:
assign Data_out = Mem[pNextWordToRead];
// always @ (posedge RClk)
// if (!PresetEmpty)
// Data_out <= Mem[pNextWordToRead];
// if (ReadEn_in & !Empty_out)
//'Data_in' logic:
always @ (posedge WClk)
if (WriteEn_in & !Full_out)
Mem[pNextWordToWrite] <= Data_in;
//Fifo addresses support logic:
//'Next Addresses' enable logic:
assign NextWriteAddressEn = WriteEn_in & ~Full_out;
assign NextReadAddressEn = ReadEn_in & ~Empty_out;
//Addreses (Gray counters) logic:
vgafb_graycounter #(
.COUNTER_WIDTH( ADDRESS_WIDTH )
) GrayCounter_pWr (
.GrayCount_out(pNextWordToWrite),
.Enable_in(NextWriteAddressEn),
.Clear_in(Clear_in),
.Clk(WClk)
);
vgafb_graycounter #(
.COUNTER_WIDTH( ADDRESS_WIDTH )
) GrayCounter_pRd (
.GrayCount_out(pNextWordToRead),
.Enable_in(NextReadAddressEn),
.Clear_in(Clear_in),
.Clk(RClk)
);
//'EqualAddresses' logic:
assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
//'Quadrant selectors' logic:
assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
//'Status' latch logic:
always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status | Clear_in)
Status = 0; //Going 'Empty'.
else if (Set_Status)
Status = 1; //Going 'Full'.
//'Full_out' logic for the writing port:
assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
if (PresetFull)
Full_out <= 1;
else
Full_out <= 0;
//'Empty_out' logic for the reading port:
assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty)
Empty_out <= 1;
else
Empty_out <= 0;
endmodule
|
// Copyright 2006, 2007 Dennis van Weeren
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// This is the Minimig PS/2 keyboard handler
//
// 19-11-2006 -started coding
// 20-11-2006 -more coding
// 21-11-2006 -finished PS/2 state machine, added keymap
// 29-11-2006 -keymap is now blockram, saves almost 80 slices!
// 04-12-2006 -added keyack signal
// 05-12-2006 -more work; cleaning up, optimizing
// -added on-screen-display control
// 01-01-2007 -added extra key for on-screen-display control
// 11-02-2007 -reset is now ctrl-alt-alt (as in Amiga OS4) instead of ctrl-lgui-rgui
// this is the ps2 keyboard module itself
// every time a new key is decoded, keystrobe is asserted.
// keydat is only valid when keystrobe is asserted
// after keystrobe, keyboard controller waits for keyack or timeout
// kbdrst is asserted when the control, left gui and right gui keys are hold down together
// leda and ledb control the numlock and scrolllock leds
// JB:
// added support for prtscr and ctrlbrk keys
// verilog 2001 style module declaration
// osd_ctrl is 8-bit wide
//
// 2009-05-24 - clean-up & renaming
// 2010-08-18 - joystick emulation
// SB:
// 2011-04-09 - added autofire lock function using capslock
// 2011-07-21 - changed '#' key scan code, thanks Chris
module ciaa_ps2keyboard
(
input clk, //bus clock
input clk7_en,
input reset, //reset (system reset in)
inout ps2kdat, //keyboard PS/2 data
inout ps2kclk, //keyboard PS/2 clk
input leda, //keyboard led a in
input ledb, //keyboard led b in
output aflock, // auto fire toggle
output kbdrst, //keyboard reset out
output [7:0] keydat, //keyboard data out
output reg keystrobe, //keyboard data out strobe
input keyack, //keyboard data out acknowledge
output [7:0] osd_ctrl, //on-screen-display controll
output _lmb, //emulated left mouse button
output _rmb, //emulated right mouse button
output [5:0] _joy2, //joystick emulation
output freeze, //Action Replay freeze button
output [5:0] mou_emu,
output [5:0] joy_emu
);
//local signals
reg pclkout; //ps2 clk out
wire pdatout; //ps2 data out
wire pclkneg; //negative edge of ps2 clock strobe
reg pdatb,pclkb,pclkc; //input synchronization
reg [11:0] preceive; //ps2 receive register
reg [11:0] psend; //ps2 send register
reg [19:0] ptimer; //ps2 timer
reg [2:0] kstate; //keyboard controller current state
reg [2:0] knext; //keyboard controller next state
reg capslock; //capslock status
wire numlock;
reg prreset; //ps2 receive reset
wire prbusy; //ps2 receive busy
reg ptreset; //ps2 reset timer
wire pto1; //ps2 timer timeout 1
wire pto2; //ps2 timer timeout 2
reg psled1; //ps2 send led code 1
reg psled2; //ps2 send led code 2
wire psready; //ps2 send ready
wire valid; //valid amiga key code at keymap output
//bidirectional open collector IO buffers
assign ps2kclk = pclkout ? 1'bz : 1'b0;
assign ps2kdat = pdatout ? 1'bz : 1'b0;
//input synchronization of external signals
always @(posedge clk) begin
if (clk7_en) begin
pdatb <= ps2kdat;
pclkb <= ps2kclk;
pclkc <= pclkb;
end
end
//detect ps2 clock negative edge
assign pclkneg = pclkc & ~pclkb;
//PS2 input shifter
wire prready;
always @(posedge clk)
if (clk7_en) begin
if (prreset || prready)
preceive[11:0] <= 12'b111111111111;
else if (pclkneg)
preceive[11:0] <= {1'b0,pdatb,preceive[10:1]};
end
assign prready = ~preceive[0];
assign prbusy = ~preceive[11];
//PS2 timer
always @(posedge clk)
if (clk7_en) begin
if (ptreset)
ptimer[19:0] <= 20'd0;
else if (!pto2)
ptimer[19:0] <= ptimer[19:0] + 20'd1;
end
assign pto1 = ptimer[15];//4.6ms @ 7.09Mhz
assign pto2 = ptimer[19];//74ms @ 7.09Mhz
//PS2 send shifter
always @(posedge clk)
if (clk7_en) begin
if (psled1)
psend[11:0] <= 12'b111111011010;//$ED
else if (psled2)
psend[11:0] <= {2'b11,~(capslock^numlock^ledb),5'b00000,capslock,numlock,ledb,1'b0};//led status
else if (!psready && pclkneg)
psend[11:0] <= {1'b0,psend[11:1]};
end
assign psready = (psend[11:0]==12'b000000000001) ? 1'd1 : 1'd0;
assign pdatout = psend[0];
//keyboard state machine
always @(posedge clk)
if (clk7_en) begin
if (reset)//master reset
kstate <= 3'd0;
else
kstate <= knext;
end
always @(*)
begin
case(kstate)
0://reset timer
begin
prreset = 1'd1;
ptreset = 1'd1;
pclkout = 1'd0;
psled1 = 1'd0;
psled2 = 1'd0;
knext = 3'd1;
end
1://"request-to-send" for led1 code
begin
prreset = 1'd1;
ptreset = 1'd0;
pclkout = 1'd0;
psled1 = 1'd1;
psled2 = 1'd0;
if (pto1)
knext = 3'd2;
else
knext = 3'd1;
end
2://wait for led1 code to be sent and acknowledge received
begin
prreset = ~psready;
ptreset = 1'd1;
pclkout = 1'd1;
psled1 = 1'd0;
psled2 = 1'd0;
if (prready)
knext = 3'd3;
else
knext = 3'd2;
end
3://"request-to-send" for led2 code
begin
prreset = 1'd1;
ptreset = 1'd0;
pclkout = 1'd0;
psled1 = 1'd0;
psled2 = 1'd1;
if (pto1)
knext = 3'd4;
else
knext = 3'd3;
end
4://wait for led2 code to be sent
begin
prreset = ~psready;
ptreset = 1'd1;
pclkout = 1'd1;
psled1 = 1'd0;
psled2 = 1'd0;
if (prready)
knext = 3'd5;
else
knext = 3'd4;
end
5://wait for valid amiga key code
begin
prreset = 1'd0;
ptreset = keystrobe;
pclkout = 1'd1;
psled1 = 1'd0;
psled2 = 1'd0;
if (keystrobe)//valid amiga key decoded
knext = 3'd6;
else if (!prbusy && pto2)//timeout, update leds
knext = 3'd0;
else//stay here
knext = 3'd5;
end
6://hold of ps2 keyboard and wait for keyack or timeout
begin
prreset = 1'd0;
ptreset = keyack;
pclkout = 1'd0;
psled1 = 1'd0;
psled2 = 1'd0;
if (keyack || pto2)//keyack or timeout
knext = 3'd5;
else//stay here
knext = 3'd6;
end
default://we should never come here
begin
prreset = 1'd0;//ps2 receiver reset
ptreset = 1'd0;//ps2 timer reset
pclkout = 1'd1;//ps2 clock override
psled1 = 1'd0;//ps2 send led code 1
psled2 = 1'd0;//ps2 send led code 2
knext = 3'd0;//go to reset state
end
endcase
end
//instantiate keymap to convert ps2 scan codes to amiga raw key codes
wire ctrl,aleft,aright,caps;
ciaa_ps2keyboard_map km1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(reset),
.enable(prready),
.ps2key(preceive[8:1]),
.valid(valid),
.akey(keydat[7:0]),
.ctrl(ctrl),
.aleft(aleft),
.aright(aright),
.caps(caps),
.numlock(numlock),
.osd_ctrl(osd_ctrl),
._lmb(_lmb),
._rmb(_rmb),
._joy2(_joy2),
.freeze(freeze),
.mou_emu(mou_emu),
.joy_emu(joy_emu)
);
//Duplicate key filter and caps lock handling.
//A ps/2 keyboard has a future called "typematic".
//This means that the last key downstroke event
//is repeated (at approx 2Hz default).
//An Amiga keyboard does not do this so this filter removes
//all duplicate downstroke events:
//When a duplicate downstroke event is detected, keystrobe is not asserted.
//When the event is unique (no duplicate), keystrobe is asserted when valid is asserted.
//
//Capslock on amiga is "remembered" by keyboard. A ps/2 keyboard doesn't do this
//therefore, amiga-like caps lock behaviour is simulated here
wire keyequal;
reg [7:0]keydat2;
assign keyequal = keydat2[6:0]==keydat[6:0] ? 1'd1 : 1'd0; //detect if latched key equals new key
//latch last key downstroke event
always @(posedge clk)
if (clk7_en) begin
if (reset)
keydat2[7:0] <= 8'd0;
else if (valid && !keydat[7])//latch downstroke event for last key pressed
keydat2[7:0] <= keydat[7:0];
else if (valid && keydat[7] && keyequal)//upstroke event for latched key received
keydat2[7:0] <= keydat[7:0];
end
//toggle capslock status on capslock downstroke event
always @(posedge clk)
if (clk7_en) begin
if (reset)
capslock <= 1'd0;
else if (valid && !keydat[7] && caps && !(keyequal && (keydat[7]==keydat2[7])))
capslock <= ~capslock;
end
assign aflock = capslock;
//generate keystrobe to indicate valid keycode
always @(*)
if (capslock && caps)//filter out capslock downstroke && capslock upstroke events if capslock is set
keystrobe = 1'd0;
else if (keyequal && (keydat[7]==keydat2[7]))//filter out duplicate events
keystrobe = 1'd0;
else if (valid)//valid amiga keycode, assert strobe
keystrobe = 1'd1;
else
keystrobe = 1'd0;
//Keyboard reset detector.
//Reset is accomplished by holding down the
//ctrl or caps, left alt and right alt keys all at the same time
reg [2:0]kbdrststatus;
always @(posedge clk) begin
if (clk7_en) begin
//latch status of control key
if (reset)
kbdrststatus[2] <= 1'd1;
else if (valid && (ctrl || caps))
kbdrststatus[2] <= keydat[7];
//latch status of left alt key
if (reset)
kbdrststatus[1] <= 1'd1;
else if (valid && aleft)
kbdrststatus[1] <= keydat[7];
//latch status of right alt key
if (reset)
kbdrststatus[0] <= 1'd1;
else if (valid && aright)
kbdrststatus[0] <= keydat[7];
end
end
assign kbdrst = ~(kbdrststatus[2] | kbdrststatus[1] | kbdrststatus[0]);//reset if all 3 keys down
endmodule
|
/*
-- ============================================================================
-- FILE NAME : decoder.v
-- DESCRIPTION : ½ßfR[_
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "isa.h"
`include "cpu.h"
/********** W
[ **********/
module decoder (
/********** IF/IDpCvCWX^ **********/
input wire [`WordAddrBus] if_pc, // vOJE^
input wire [`WordDataBus] if_insn, // ½ß
input wire if_en, // pCvCf[^ÌLø
/********** GPRC^tF[X **********/
input wire [`WordDataBus] gpr_rd_data_0, // ÇÝoµf[^ 0
input wire [`WordDataBus] gpr_rd_data_1, // ÇÝoµf[^ 1
output wire [`RegAddrBus] gpr_rd_addr_0, // ÇÝoµAhX 0
output wire [`RegAddrBus] gpr_rd_addr_1, // ÇÝoµAhX 1
/********** tH[fBO **********/
// IDXe[W©çÌtH[fBO
input wire id_en, // pCvCf[^ÌLø
input wire [`RegAddrBus] id_dst_addr, // «ÝAhX
input wire id_gpr_we_, // «ÝLø
input wire [`MemOpBus] id_mem_op, // Iy[V
// EXXe[W©çÌtH[fBO
input wire ex_en, // pCvCf[^ÌLø
input wire [`RegAddrBus] ex_dst_addr, // «ÝAhX
input wire ex_gpr_we_, // «ÝLø
input wire [`WordDataBus] ex_fwd_data, // tH[fBOf[^
// MEMXe[W©çÌtH[fBO
input wire [`WordDataBus] mem_fwd_data, // tH[fBOf[^
/********** §äWX^C^tF[X **********/
input wire [`CpuExeModeBus] exe_mode, // Às[h
input wire [`WordDataBus] creg_rd_data, // ÇÝoµf[^
output wire [`RegAddrBus] creg_rd_addr, // ÇÝoµAhX
/********** fR[hÊ **********/
output reg [`AluOpBus] alu_op, // ALUIy[V
output reg [`WordDataBus] alu_in_0, // ALUüÍ 0
output reg [`WordDataBus] alu_in_1, // ALUüÍ 1
output reg [`WordAddrBus] br_addr, // ªòAhX
output reg br_taken, // ªò̬§
output reg br_flag, // ªòtO
output reg [`MemOpBus] mem_op, // Iy[V
output wire [`WordDataBus] mem_wr_data, // «Ýf[^
output reg [`CtrlOpBus] ctrl_op, // §äIy[V
output reg [`RegAddrBus] dst_addr, // ÄpWX^«ÝAhX
output reg gpr_we_, // ÄpWX^«ÝLø
output reg [`IsaExpBus] exp_code, // áOR[h
output reg ld_hazard // [hnU[h
);
/********** ½ßtB[h **********/
wire [`IsaOpBus] op = if_insn[`IsaOpLoc]; // IyR[h
wire [`RegAddrBus] ra_addr = if_insn[`IsaRaAddrLoc]; // RaAhX
wire [`RegAddrBus] rb_addr = if_insn[`IsaRbAddrLoc]; // RbAhX
wire [`RegAddrBus] rc_addr = if_insn[`IsaRcAddrLoc]; // RcAhX
wire [`IsaImmBus] imm = if_insn[`IsaImmLoc]; // ¦l
/********** ¦l **********/
// g£
wire [`WordDataBus] imm_s = {{`ISA_EXT_W{imm[`ISA_IMM_MSB]}}, imm};
// [g£
wire [`WordDataBus] imm_u = {{`ISA_EXT_W{1'b0}}, imm};
/********** WX^ÌÇÝoµAhX **********/
assign gpr_rd_addr_0 = ra_addr; // ÄpWX^ÇÝoµAhX 0
assign gpr_rd_addr_1 = rb_addr; // ÄpWX^ÇÝoµAhX 1
assign creg_rd_addr = ra_addr; // §äWX^ÇÝoµAhX
/********** ÄpWX^ÌÇÝoµf[^ **********/
reg [`WordDataBus] ra_data; // ȵRa
wire signed [`WordDataBus] s_ra_data = $signed(ra_data); // t«Ra
reg [`WordDataBus] rb_data; // ȵRb
wire signed [`WordDataBus] s_rb_data = $signed(rb_data); // t«Rb
assign mem_wr_data = rb_data; // «Ýf[^
/********** AhX **********/
wire [`WordAddrBus] ret_addr = if_pc + 1'b1; // ßèÔn
wire [`WordAddrBus] br_target = if_pc + imm_s[`WORD_ADDR_MSB:0]; // ªòæ
wire [`WordAddrBus] jr_target = ra_data[`WordAddrLoc]; // Wvæ
/********** tH[fBO **********/
always @(*) begin
/* RaWX^ */
if ((id_en == `ENABLE) && (id_gpr_we_ == `ENABLE_) &&
(id_dst_addr == ra_addr)) begin
ra_data = ex_fwd_data; // EXXe[W©çÌtH[fBO
end else if ((ex_en == `ENABLE) && (ex_gpr_we_ == `ENABLE_) &&
(ex_dst_addr == ra_addr)) begin
ra_data = mem_fwd_data; // MEMXe[W©çÌtH[fBO
end else begin
ra_data = gpr_rd_data_0; // WX^t@C©çÌÇÝoµ
end
/* RbWX^ */
if ((id_en == `ENABLE) && (id_gpr_we_ == `ENABLE_) &&
(id_dst_addr == rb_addr)) begin
rb_data = ex_fwd_data; // EXXe[W©çÌtH[fBO
end else if ((ex_en == `ENABLE) && (ex_gpr_we_ == `ENABLE_) &&
(ex_dst_addr == rb_addr)) begin
rb_data = mem_fwd_data; // MEMXe[W©çÌtH[fBO
end else begin
rb_data = gpr_rd_data_1; // WX^t@C©çÌÇÝoµ
end
end
/********** [hnU[hÌo **********/
always @(*) begin
if ((id_en == `ENABLE) && (id_mem_op == `MEM_OP_LDW) &&
((id_dst_addr == ra_addr) || (id_dst_addr == rb_addr))) begin
ld_hazard = `ENABLE; // [hnU[h
end else begin
ld_hazard = `DISABLE; // nU[hȵ
end
end
/********** ½ßÌfR[h **********/
always @(*) begin
/* ftHgl */
alu_op = `ALU_OP_NOP;
alu_in_0 = ra_data;
alu_in_1 = rb_data;
br_taken = `DISABLE;
br_flag = `DISABLE;
br_addr = {`WORD_ADDR_W{1'b0}};
mem_op = `MEM_OP_NOP;
ctrl_op = `CTRL_OP_NOP;
dst_addr = rb_addr;
gpr_we_ = `DISABLE_;
exp_code = `ISA_EXP_NO_EXP;
/* IyR[hÌ»è */
if (if_en == `ENABLE) begin
case (op)
/* _Z½ß */
`ISA_OP_ANDR : begin // WX^¯mÌ_Ï
alu_op = `ALU_OP_AND;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ANDI : begin // WX^ƦlÌ_Ï
alu_op = `ALU_OP_AND;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ORR : begin // WX^¯mÌ_a
alu_op = `ALU_OP_OR;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ORI : begin // WX^ƦlÌ_a
alu_op = `ALU_OP_OR;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_XORR : begin // WX^¯mÌr¼I_a
alu_op = `ALU_OP_XOR;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_XORI : begin // WX^ƦlÌr¼I_a
alu_op = `ALU_OP_XOR;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
/* ZpZ½ß */
`ISA_OP_ADDSR : begin // WX^¯mÌt«ÁZ
alu_op = `ALU_OP_ADDS;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDSI : begin // WX^ƦlÌt«ÁZ
alu_op = `ALU_OP_ADDS;
alu_in_1 = imm_s;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDUR : begin // WX^¯mÌȵÁZ
alu_op = `ALU_OP_ADDU;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDUI : begin // WX^ƦlÌȵÁZ
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SUBSR : begin // WX^¯mÌt«¸Z
alu_op = `ALU_OP_SUBS;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SUBUR : begin // WX^¯mÌȵ¸Z
alu_op = `ALU_OP_SUBU;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
/* Vtg½ß */
`ISA_OP_SHRLR : begin // WX^¯mÌ_EVtg
alu_op = `ALU_OP_SHRL;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHRLI : begin // WX^ƦlÌ_EVtg
alu_op = `ALU_OP_SHRL;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHLLR : begin // WX^¯mÌ_¶Vtg
alu_op = `ALU_OP_SHLL;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHLLI : begin // WX^ƦlÌ_¶Vtg
alu_op = `ALU_OP_SHLL;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
/* ªò½ß */
`ISA_OP_BE : begin // WX^¯mÌt«äriRa == Rbj
br_addr = br_target;
br_taken = (ra_data == rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BNE : begin // WX^¯mÌt«äriRa != Rbj
br_addr = br_target;
br_taken = (ra_data != rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BSGT : begin // WX^¯mÌt«äriRa < Rbj
br_addr = br_target;
br_taken = (s_ra_data < s_rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BUGT : begin // WX^¯mÌȵäriRa < Rbj
br_addr = br_target;
br_taken = (ra_data < rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_JMP : begin // ³ðªò
br_addr = jr_target;
br_taken = `ENABLE;
br_flag = `ENABLE;
end
`ISA_OP_CALL : begin // R[
alu_in_0 = {ret_addr, {`BYTE_OFFSET_W{1'b0}}};
br_addr = jr_target;
br_taken = `ENABLE;
br_flag = `ENABLE;
dst_addr = `REG_ADDR_W'd31;
gpr_we_ = `ENABLE_;
end
/* ANZX½ß */
`ISA_OP_LDW : begin // [hÇÝoµ
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
mem_op = `MEM_OP_LDW;
gpr_we_ = `ENABLE_;
end
`ISA_OP_STW : begin // [h«Ý
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
mem_op = `MEM_OP_STW;
end
/* VXeR[½ß */
`ISA_OP_TRAP : begin // gbv
exp_code = `ISA_EXP_TRAP;
end
/* Á ½ß */
`ISA_OP_RDCR : begin // §äWX^ÌÇÝoµ
if (exe_mode == `CPU_KERNEL_MODE) begin
alu_in_0 = creg_rd_data;
gpr_we_ = `ENABLE_;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
`ISA_OP_WRCR : begin // §äWX^ÖÌ«Ý
if (exe_mode == `CPU_KERNEL_MODE) begin
ctrl_op = `CTRL_OP_WRCR;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
`ISA_OP_EXRT : begin // áO©çÌA
if (exe_mode == `CPU_KERNEL_MODE) begin
ctrl_op = `CTRL_OP_EXRT;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
/* »Ì¼Ì½ß */
default : begin // ¢è`½ß
exp_code = `ISA_EXP_UNDEF_INSN;
end
endcase
end
end
endmodule
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "hi_sniffer.v"
`include "util.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop = conf_word[1];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
hi_sniffer he(
pck0, ck_1356meg, ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
cross_hi, cross_lo,
he_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
// Major modes:
// 000 -- HF reader, transmitting to tag; modulation depth selectable
// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 010 -- HF simulated tag
// 011 -- HF ISO14443-A
// 100 -- HF Snoop
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
/****************************************************************************************
*
* File Name: ddr3.v
* Version: 1.61
* Model: BUS Functional
*
* Dependencies: ddr3_model_parameters.vh
*
* Description: Micron SDRAM DDR3 (Double Data Rate 3)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
* - Duty Cycle Corrector is not modeled
* - Temperature Compensated Self Refresh is not modeled
* - DLL off mode is not modeled.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set DEBUG = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check.
* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n.
* TDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* Improved checking of DQS during writes.
* Added true BL4 operation.
* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers.
* Added ODTS Readout.
* Replaced tZQCL with tZQinit and tZQoper
* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
* Added tRFC checking for Refresh to Power-Down Re-Entry.
* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
* Added Clock Frequency Change during Precharge Power-Down.
* Added -125x speed grades.
* Fixed tRCD checking during Write.
* 1.00 JMK 05/11/07 Initial release
* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF
* Removed temp sensor readout from MPR
* Updated initialization sequence
* Updated timing parameters
* 1.20 JMK 09/05/07 Updated clock frequency change
* Added ddr3_dimm module
* 1.30 JMK 01/23/08 Updated timing parameters
* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133
* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
* Added multi-chip package model support in ddr3_mcp.v
* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades.
* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes
* 1.61 SPH 12/10/09 Only check tIH for cmd_addr if CS# LOW
*****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
// model flags
// `define MODEL_PASR
//Memory Details
`define x2Gb
`define sg125
`define x8
module ddr3_model (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`include "ddr3_model_parameters.vh"
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
parameter feature_truebl4 = 0;
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 4*CL_MAX
// Declare Ports
input rst_n;
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] tdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
//DDR3 clock jitter variables
real tjit_ch_rtime;
real duty_cycle;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg [ADDR_BITS-1:0] mode_reg [`BANKS-1:0];
reg burst_order;
reg [BL_BITS:0] burst_length;
reg blotf;
reg truebl4;
integer cas_latency;
reg dll_reset;
reg dll_locked;
integer write_recovery;
reg low_power;
reg dll_en;
reg [2:0] odt_rtt_nom;
reg [1:0] odt_rtt_wr;
reg odt_en;
reg dyn_odt_en;
reg [1:0] al;
integer additive_latency;
reg write_levelization;
reg duty_cycle_corrector;
reg tdqs_en;
reg out_en;
reg [2:0] pasr;
integer cas_write_latency;
reg asr; // auto self refresh
reg srt; // self refresh temperature range
reg [1:0] mpr_select;
reg mpr_en;
reg odts_readout;
integer read_latency;
integer write_latency;
// cmd encoding
parameter // {cs, ras, cas, we}
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
ZQ = 4'b0110,
NOP = 4'b0111,
// DESEL = 4'b1xxx,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[ZQ ] = "ZQ ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_dll_reset;
reg init_done;
integer init_step;
reg zq_set;
reg er_trfc_max;
reg odt_state;
reg odt_state_dly;
reg dyn_odt_state;
reg dyn_odt_state_dly;
reg prev_odt;
wire [7:0] calibration_pattern = 8'b10101010; // value returned during mpr pre-defined pattern readout
wire [7:0] temp_sensor = 8'h01; // value returned during mpr temp sensor readout
reg [1:0] mr_chk;
reg rd_bc;
integer banki;
// cmd timers/counters
integer ref_cntr;
integer odt_cntr;
integer ck_cntr;
integer ck_txpr;
integer ck_load_mode;
integer ck_refresh;
integer ck_precharge;
integer ck_activate;
integer ck_write;
integer ck_read;
integer ck_zqinit;
integer ck_zqoper;
integer ck_zqcs;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_freq_change;
integer ck_odt;
integer ck_odth8;
integer ck_dll_reset;
integer ck_cke_cmd;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
integer ck_group_activate [1:0];
integer ck_group_write [1:0];
integer ck_group_read [1:0];
time tm_txpr;
time tm_load_mode;
time tm_refresh;
time tm_precharge;
time tm_activate;
time tm_write_end;
time tm_power_down;
time tm_slow_exit_pd;
time tm_self_refresh;
time tm_freq_change;
time tm_cke_cmd;
time tm_ttsinit;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
time tm_group_activate [1:0];
time tm_group_write_end [1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [`MAX_PIPE:0] dyn_odt_pipeline;
reg [BL_BITS:0] bl_pipeline [`MAX_PIPE:0];
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [31:0] check_write_postamble;
reg [31:0] check_write_preamble;
reg [31:0] check_write_dqs_high;
reg [31:0] check_write_dqs_low;
reg [15:0] check_dm_tdipw;
reg [63:0] check_dq_tdipw;
// data timers/counters
time tm_rst_n;
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [15:0];
time tm_dqs [15:0];
time tm_dqs_pos [31:0];
time tm_dqss_pos [31:0];
time tm_dqs_neg [31:0];
time tm_dq [63:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
parameter RFF_BITS = DQ_BITS*BL_MAX;
// %z format uses 8 bytes for every 32 bits or less.
parameter RFF_CHUNK = 8 * (RFF_BITS/32 + (RFF_BITS%32 ? 1 : 0));
reg [1024:1] tmp_model_dir;
integer memfd[`BANKS-1:0];
initial
begin : file_io_open
integer bank;
if (!$value$plusargs("model_data+%s", tmp_model_dir))
begin
tmp_model_dir = "/tmp";
$display(
"%m: at time %t WARNING: no +model_data option specified, using /tmp.",
$time
);
end
for (bank = 0; bank < `BANKS; bank = bank + 1)
memfd[bank] = open_bank_file(bank);
end
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used = 0;
`endif
// receive
reg rst_n_in;
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [15:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [63:0] dq_in;
reg [31:0] dqs_in;
reg odt_in;
reg [15:0] dm_in_pos;
reg [15:0] dm_in_neg;
reg [63:0] dq_in_pos;
reg [63:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [31:0];
reg b2b_write;
reg [BL_BITS:0] wr_burst_length;
reg [31:0] prev_dqs_in;
reg diff_ck;
always @(rst_n ) rst_n_in <= #BUS_DELAY rst_n;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_tdqs) dm_in <= #BUS_DELAY dm_tdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [15:0] dqs_even = dqs_in[15:0];
wire [15:0] dqs_odd = dqs_in[31:16];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
assign tdqs_n = {DQS_BITS{1'bz}};
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
seed = RANDOM_SEED;
ck_cntr = 0;
end
function integer get_rtt_wr;
input [1:0] rtt;
begin
get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0};
end
endfunction
function integer get_rtt_nom;
input [2:0] rtt;
begin
case (rtt)
1: get_rtt_nom = RZQ/4;
2: get_rtt_nom = RZQ/2;
3: get_rtt_nom = RZQ/6;
4: get_rtt_nom = RZQ/12;
5: get_rtt_nom = RZQ/8;
default : get_rtt_nom = 0;
endcase
end
endfunction
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
function integer ceil;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number > $rtoi(number))
ceil = $rtoi(number) + 1;
else
ceil = number;
endfunction
function integer floor;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number < $rtoi(number))
floor = $rtoi(number) - 1;
else
floor = number;
endfunction
`ifdef MAX_MEM
function integer open_bank_file( input integer bank );
integer fd;
reg [2048:1] filename;
begin
$sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank );
fd = $fopen(filename, "w+");
if (fd == 0)
begin
$display("%m: at time %0t ERROR: failed to open %0s.", $time, filename);
$finish;
end
else
begin
if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename);
open_bank_file = fd;
end
end
endfunction
function [RFF_BITS:1] read_from_file(
input integer fd,
input integer index
);
integer code;
integer offset;
reg [1024:1] msg;
reg [RFF_BITS:1] read_value;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
// $fseek returns 0 on success, -1 on failure
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
code = $fscanf(fd, "%z", read_value);
// $fscanf returns number of items read
if (code != 1)
begin
if ($ferror(fd,msg) != 0)
begin
$display("%m: at time %t ERROR: fscanf failed at %d", $time, index);
$display(msg);
$finish;
end
else
read_value = 'hx;
end
/* when reading from unwritten portions of the file, 0 will be returned.
* Use 0 in bit 1 as indicator that invalid data has been read.
* A true 0 is encoded as Z.
*/
if (read_value[1] === 1'bz)
// true 0 encoded as Z, data is valid
read_value[1] = 1'b0;
else if (read_value[1] === 1'b0)
// read from file section that has not been written
read_value = 'hx;
read_from_file = read_value;
end
endfunction
task write_to_file(
input integer fd,
input integer index,
input [RFF_BITS:1] data
);
integer code;
integer offset;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
// encode a valid data
if (data[1] === 1'bz)
data[1] = 1'bx;
else if (data[1] === 1'b0)
data[1] = 1'bz;
$fwrite( fd, "%z", data );
end
endtask
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
write_to_file( memfd[bank], addr, data );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
data = read_from_file( memfd[bank], addr );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
task set_latency;
begin
if (al == 0) begin
additive_latency = 0;
end else begin
additive_latency = cas_latency - al;
end
read_latency = cas_latency + additive_latency;
write_latency = cas_write_latency + additive_latency;
end
endtask
// this task will erase the contents of 0 or more banks
task erase_banks;
input [`BANKS-1:0] banks; //one select bit per bank
reg [BA_BITS-1:0] ba;
reg [`MAX_BITS-1:0] i;
integer bank;
begin
`ifdef MAX_MEM
for (bank = 0; bank < `BANKS; bank = bank + 1)
if (banks[bank] === 1'b1) begin
$fclose(memfd[bank]);
memfd[bank] = open_bank_file(bank);
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
ba = (address[memory_index]>>(ROW_BITS+COL_BITS-BL_BITS));
if (!banks[ba]) begin //bank is selected to keep
address[i] = address[memory_index];
memory[i] = memory[memory_index];
i = i + 1;
end
end
// clean up the unused banks
for (memory_index=i; memory_index<memory_used; memory_index=memory_index+1) begin
address[memory_index] = 'bx;
memory[memory_index] = {8*DQ_BITS{1'bx}};
end
memory_used = i;
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down and out of reset.
// After this task runs, NOP commands must be issued until TZQINIT has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, ZQ, 'bx, 'h400); //ZQCL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
dyn_odt_en = 0;
odt_state = 0;
dyn_odt_state = 0;
// reset bank state
active_bank = 0;
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
mpr_en = 0;
init_step = 0;
init_mode_reg = 0;
init_dll_reset = 0;
zq_set = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
// exit power down and self refresh
prev_cke = 1'bx;
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
dyn_odt_pipeline = 0;
end
endtask
parameter SAME_BANK = 2'd0; // same bank, same group
parameter DIFF_BANK = 2'd1; // different bank, same group
parameter DIFF_GROUP = 2'd2; // different bank, different group
task chk_err;
input [1:0] relationship;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// $display ("truebl4 = %d, relationship = %d, fromcmd = %h, cmd = %h", truebl4, relationship, fromcmd, cmd);
casex ({truebl4, relationship, fromcmd, cmd})
// load mode
{1'bx, DIFF_BANK , LOAD_MODE, LOAD_MODE} : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, READ } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, REFRESH } ,
{1'bx, DIFF_BANK , LOAD_MODE, PRECHARGE} ,
{1'bx, DIFF_BANK , LOAD_MODE, ACTIVATE } ,
{1'bx, DIFF_BANK , LOAD_MODE, ZQ } ,
{1'bx, DIFF_BANK , LOAD_MODE, PWR_DOWN } ,
{1'bx, DIFF_BANK , LOAD_MODE, SELF_REF } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
// refresh
{1'bx, DIFF_BANK , REFRESH , LOAD_MODE} ,
{1'bx, DIFF_BANK , REFRESH , REFRESH } ,
{1'bx, DIFF_BANK , REFRESH , PRECHARGE} ,
{1'bx, DIFF_BANK , REFRESH , ACTIVATE } ,
{1'bx, DIFF_BANK , REFRESH , ZQ } ,
{1'bx, DIFF_BANK , REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , REFRESH , PWR_DOWN } : begin if (ck_cntr - ck_refresh < TREFPDEN) $display ("%m: at time %t ERROR: tREFPDEN violation during %s", $time, cmd_string[cmd]); end
// precharge
{1'bx, SAME_BANK , PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , PRECHARGE, LOAD_MODE} ,
{1'bx, DIFF_BANK , PRECHARGE, REFRESH } ,
{1'bx, DIFF_BANK , PRECHARGE, ZQ } ,
{1'bx, DIFF_BANK , PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PRECHARGE, PWR_DOWN } : ; //tPREPDEN = 1 tCK, can be concurrent with auto precharge
// activate
{1'bx, SAME_BANK , ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, SAME_BANK , ACTIVATE , WRITE } ,
{1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task
{1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end
// write
{1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end
// read
{1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end
// zq
{1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK
{1'bx, DIFF_BANK , ZQ , REFRESH } ,
{1'bx, DIFF_BANK , ZQ , PRECHARGE} ,
{1'bx, DIFF_BANK , ZQ , ACTIVATE } ,
{1'bx, DIFF_BANK , ZQ , ZQ } ,
{1'bx, DIFF_BANK , ZQ , PWR_DOWN } ,
{1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end
// power down
{1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} ,
{1'bx, DIFF_BANK , PWR_DOWN , REFRESH } ,
{1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} ,
{1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } ,
{1'bx, DIFF_BANK , PWR_DOWN , WRITE } ,
{1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } ,
{1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]);
if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
// self refresh
{1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} ,
{1'bx, DIFF_BANK , SELF_REF , REFRESH } ,
{1'bx, DIFF_BANK , SELF_REF , PRECHARGE} ,
{1'bx, DIFF_BANK , SELF_REF , ACTIVATE } ,
{1'bx, DIFF_BANK , SELF_REF , WRITE } ,
{1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } ,
{1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
reg group;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && (cmd != PRECHARGE)) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK , bank, j, cmd);
chk_err(DIFF_BANK , bank, j, cmd);
chk_err(DIFF_GROUP, bank, j, cmd);
end
end
case (cmd)
LOAD_MODE : begin
if (|odt_pipeline)
$display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]);
if (odt_state)
$display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]);
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
if (bank>>2) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
case (bank)
0 : begin
// Burst Length
if (addr[1:0] == 2'b00) begin
burst_length = 8;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else if (addr[1:0] == 2'b01) begin
burst_length = 8;
blotf = 1;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank);
end else if (addr[1:0] == 2'b10) begin
burst_length = 4;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length);
end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin
burst_length = 4;
blotf = 0;
truebl4 = 1;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = {addr[2],addr[6:4]} + 4;
set_latency;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Reserved
if (addr[7] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
init_dll_reset = 1;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
if (addr[11:9] == 0) begin
write_recovery = 16;
end else if (addr[11:9] < 4) begin
write_recovery = addr[11:9] + 4;
end else begin
write_recovery = 2*addr[11:9];
end
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = !addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if ({addr[5], addr[1]} == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6);
end else if ({addr[5], addr[1]} == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7);
end else if ({addr[5], addr[1]} == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]});
end
// ODT Rtt (Rtt_NOM)
odt_rtt_nom = {addr[9], addr[6], addr[2]};
if (odt_rtt_nom == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom));
odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom);
odt_en = 0;
end
// Report the additive latency value
al = addr[4:3];
set_latency;
if (al == 0) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end
// Write Levelization
write_levelization = addr[7];
if (!write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank);
end else if (write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization);
end
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Reserved
if (addr[10] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// TDQS Enable
tdqs_en = addr[11];
if (!tdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (tdqs_en) begin
if (8 == DQ_BITS) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank);
end
else begin
$display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
tdqs_en = 0;
end
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
2 : begin
if (feature_pasr) begin
// Partial Array Self Refresh
pasr = addr[2:0];
case (pasr)
3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank);
3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank);
3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank);
3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank);
3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank);
3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank);
3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank);
3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank);
default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr);
endcase
end
else
if (addr[2:0] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// CAS Write Latency
cas_write_latency = addr[5:3]+5;
set_latency;
if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end
// Auto Self Refresh Method
asr = addr[6];
if (!asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank);
end else if (asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr);
end
// Self Refresh Temperature
srt = addr[7];
if (!srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank);
end else if (srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt);
end
if (asr && srt)
$display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank);
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Dynamic ODT (Rtt_WR)
odt_rtt_wr = addr[10:9];
if (odt_rtt_wr == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank);
dyn_odt_en = 0;
end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr));
dyn_odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr);
dyn_odt_en = 0;
end
// Reserved
if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
mpr_select = addr[1:0];
// MultiPurpose Register Select
if (mpr_select == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank);
end else begin
if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select);
end
// MultiPurpose Register Enable
mpr_en = addr[2];
if (!mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
if (dyn_odt_en && write_levelization)
$display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time);
init_mode_reg[bank] = 1;
mode_reg[bank] = addr;
tm_load_mode <= $time;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
ck_refresh <= ck_cntr;
end
end
PRECHARGE : begin
if (addr[AP]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
end
// PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state),
// or if the previously open row is already in the process of precharging
if (|active_bank) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
for (i=0; i<`BANKS; i=i+1) begin
if (active_bank[i]) begin
if (addr[AP] || (i == bank)) begin
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK, i, j, cmd);
chk_err(DIFF_BANK, i, j, cmd);
end
if (auto_precharge_bank[i]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
active_bank[i] = 1'b0;
tm_bank_precharge[i] <= $time;
tm_precharge <= $time;
ck_precharge <= ck_cntr;
end
end
end
end
end
end
end
ACTIVATE : begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_group_activate[bank[1]] <= $time;
tm_activate <= $time;
tm_bank_activate[bank] <= $time;
ck_group_activate[bank[1]] <= ck_cntr;
ck_activate <= ck_cntr;
end
end
WRITE : begin
if ((!rd_bc && blotf) || (burst_length == 4)) begin // BL=4
if (truebl4) begin
if (ck_cntr - ck_group_read[bank[1]] < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
if (ck_cntr - ck_read < read_latency + TCCD_DG/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);
end else begin
if (ck_cntr - ck_read < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end else begin // BL=8
if (ck_cntr - ck_read < read_latency + TCCD + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_write < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
col = col & -4;
end else begin // BL=8
col = col & -8;
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*write_latency + 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*write_latency + 1] = 8;
if (odt_in) begin
ck_odth8 <= ck_cntr;
end
end
for (j=0; j<(burst_length + 4); j=j+1) begin
dyn_odt_pipeline[2*(write_latency - 2) + j] = 1'b1; // ODTLcnw = WL - 2, ODTLcwn = BL/2 + 2
end
ck_bank_write[bank] <= ck_cntr;
ck_group_write[bank[1]] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during %s.", $time, cmd_string[cmd]);
if (mpr_en && (addr[1:0] != 2'b00)) begin
$display ("%m: at time %t ERROR: %s Failure. addr[1:0] must be zero during Multipurpose Register Read.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank] && !mpr_en) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_read < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP] && !mpr_en) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*read_latency - 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*read_latency - 1] = 8;
if (mpr_en && col%8) begin
$display ("%m: at time %t WARNING: col[2:0] must be set to 3'b000 during a BL8 Multipurpose Register read", $time);
end
end
rd_bc = addr[BC];
ck_bank_read[bank] <= ck_cntr;
ck_group_read[bank[1]] <= ck_cntr;
ck_read <= ck_cntr;
end
end
ZQ : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s long = %d", $time, cmd_string[cmd], addr[AP]);
if (addr[AP]) begin
zq_set = 1;
if (init_done) begin
ck_zqoper <= ck_cntr;
end else begin
ck_zqinit <= ck_cntr;
end
end else begin
ck_zqcs <= ck_cntr;
end
end
end
NOP: begin
if (in_power_down) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Power Down Exit", $time);
if ($time - tm_cke_cmd > TPD_MAX)
$display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if ((active_bank == 0) && low_power) begin // precharge power down with dll off
if (ck_cntr - ck_odt < write_latency - 1)
$display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time);
tm_slow_exit_pd <= $time;
ck_slow_exit_pd <= ck_cntr;
end
tm_power_down <= $time;
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time);
if (ck_cntr - ck_cke_cmd < TCKESR_TCK)
$display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time);
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time - tm_rst_n < 500000000 && check_strict_timing)
$display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time);
tm_txpr <= $time;
ck_txpr <= ck_cntr;
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && init_dll_reset && zq_set) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, SELF_REF);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (odt_state) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
if (feature_pasr)
// Partial Array Self Refresh
case (pasr)
3'b000 : ;//keep Bank 0-7
3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end
3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end
3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end
3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end
3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end
3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end
3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end
endcase
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering precharge power down with dll off and tANPD has not been satisfied
if (low_power && (active_bank == 0) && |odt_pipeline)
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, PWR_DOWN);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
end
endcase
end else if (in_self_refresh || in_power_down) begin
if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP))
$display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time);
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<32; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<32; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1;
end
// write dqs
if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = bl_pipeline[1];
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
wr_burst_length = bl_pipeline[2];
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1;
end
// read dqs
if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = bl_pipeline[0];
end
if (rdq_cntr > 0) begin // read data
if (mpr_en) begin
`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}};
end
`else // all DQ output MPR data
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}};
end
`endif
if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]);
end else begin
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
end
dq_out = dq_temp;
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQH + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQH*tck_avg + TDQSQ) begin
dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin
dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ;
end
// DQSQ requirements
// 1.) less than tDQSQ
// 2.) greater than 0
// 3.) greater than tQH from the previous DQS edge
dqsq_min = 0;
if (dqsq_min < dqsck[i] - TQH*tck_avg) begin
dqsq_min = dqsck[i] - TQH*tck_avg;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TDQSQ + dqsck[i];
dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out;
if (!write_levelization) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en;
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end
end else begin
out_delay = tck_avg/2;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
if (write_levelization !== 1'b1) begin
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
end
endtask
always @ (posedge rst_n_in) begin : reset
integer i;
if (rst_n_in) begin
if ($time < 200000000 && check_strict_timing)
$display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time);
if (cke_in !== 1'b0)
$display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time);
if ($time - tm_cke < 10000)
$display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time);
// clear memory
`ifdef MAX_MEM
// verification group does not erase memory
// for (banki = 0; banki < `BANKS; banki = banki + 1) begin
// $fclose(memfd[banki]);
// memfd[banki] = open_bank_file(banki);
// end
`else
memory_used <= 0; //erase memory
`endif
end
end
always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main
integer i;
if (!rst_n_in) begin
reset_task;
end else begin
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
// Clock Frequency Change is legal:
// 1.) During Self Refresh
// 2.) During Precharge Power Down (DLL on or off)
if (in_self_refresh || (in_power_down && (active_bank == 0))) begin
if (diff_ck) begin
tjit_per_rtime = $time - tm_ck_pos - tck_avg;
end else begin
tjit_per_rtime = $time - tm_ck_neg - tck_avg;
end
if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin
if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK))
$display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time);
if (odt_state) begin
$display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time);
tm_freq_change <= $time;
ck_freq_change <= ck_cntr;
dll_locked = 0;
end
end
end
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (dll_locked) begin
if (mr_chk == 0) begin
mr_chk = 1;
end else if (init_mode_reg[0] && (mr_chk == 1)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME && check_strict_timing)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (ceil(write_recovery*tck_avg) < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
// check the CWL value against the clock frequency
if (check_strict_timing) begin
case (cas_write_latency)
5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
endcase
// check the CL value against the clock frequency
if (!valid_cl(cas_latency, cas_write_latency))
$display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency);
end
mr_chk = 2;
end
end else if (!in_self_refresh) begin
mr_chk = 0;
if (ck_cntr - ck_dll_reset == TDLLK) begin
dll_locked = 1;
end
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]) begin
if ($time - tm_bank_activate[i] >= TRAS_MIN) begin
if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus 4 cycles after Read command
// 3. tRTP after the last 8-bit prefetch
if (read_precharge_bank[i]) begin
if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
ck_precharge = ck_cntr;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
tm_cke_cmd <= $time;
ck_cke_cmd <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin //{
if (truebl4) begin //{
i = ba_pipeline[2*cas_latency - 1];
if ($time - tm_group_write_end[i[1]] < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
if ($time - tm_write_end < TWTR_DG)
$display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]);
end else begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
end
if (rd_pipeline) begin
if (rd_pipeline[2*cas_latency - 1]) begin
tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time;
end
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_group_write_end[i[1]] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh && tm_ck_pos ) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked && check_strict_timing) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<12; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER);
6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER);
7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER);
8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER);
9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER);
10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER);
11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
// check tCL
if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time);
if (tcl_avg < TCL_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
tjit_ch_rtime = tch_i - tch_avg;
duty_cycle = tch_avg/tck_avg;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos = $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked && check_strict_timing) begin
if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos);
if (tch_avg < TCH_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg = $time;
end
// on die termination
if (odt_en || dyn_odt_en) begin
// odt pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS)
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if (ck_cntr - ck_zqinit < TZQINIT)
$display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time);
if (ck_cntr - ck_zqoper < TZQOPER)
$display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time);
if (ck_cntr - ck_zqcs < TZQCS)
$display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time);
// if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
// $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time);
if (ck_cntr - ck_self_refresh < TXSDLL)
$display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
if (!odt_in && (ck_cntr - ck_odt < ODTH4))
$display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time);
if (!odt_in && (ck_cntr - ck_odth8 < ODTH8))
$display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time);
if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
$display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
// async ODT mode applies:
// 1.) during precharge power down with DLL off
// 2.) if tANPD has not been satisfied
// 3.) until tXPDLL has been satisfied
if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin
odt_state = odt_in;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAONPD) odt_state;
end else begin
odt_state_dly <= #(TAOFPD) odt_state;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down
// 3.) during precharge power down with DLL on
end else begin
odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAON) odt_state;
end else begin
odt_state_dly <= #(TAOF*tck_avg) odt_state;
end
end
if (rd_pipeline[RDQSEN_PRE]) begin
odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (odt_cntr > 0) begin
if (odt_state) begin
$display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time);
end
odt_cntr = odt_cntr - 1;
end
if (dyn_odt_en && odt_state) begin
if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0]))
$display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr));
dyn_odt_state = dyn_odt_pipeline[0];
end
dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state;
end
if (cke_in && write_levelization) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if ($time - tm_dqs_pos[i] < TWLH)
$display ("%m: at time %t WARNING: tWLH violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
end
end
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
bl_pipeline[i] = bl_pipeline[i+1];
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline || |dyn_odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
dyn_odt_pipeline = dyn_odt_pipeline>>1;
end
end
end
// receiver(s)
task dqs_even_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
task dqs_odd_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
// Processes to check hold and pulse width of control signals
always @(posedge rst_n_in) begin
if ($time > 100000) begin
if (tm_rst_n + 100000 > $time)
$display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time);
end
tm_rst_n = $time;
end
always @(cke_in) begin
if (rst_n_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if ($time - tm_cke < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time);
end
tm_cke = $time;
end
always @(odt_in) begin
if (rst_n_in && odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if ($time - tm_odt < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (rst_n_in && prev_cke) begin
if ((i == 0) && ($time - tm_ck_pos < TIH)) // always check tIH for CS#
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ((i > 0) && (cs_n_in == 0) &&($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# is low
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ($time - tm_cmd_addr[i] < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [3:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if ($time - tm_dm[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
task dq_timing_check;
input i;
reg [5:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if ($time - tm_dq[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
task dqs_pos_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLMRD)
$display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i);
if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS))
$display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
if (DEBUG)
$display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck);
dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1;
dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck;
for (j=1; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1;
dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0;
end
end
if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(negedge dqs_in[16]) dqs_pos_timing_check(16);
always @(negedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
task dqs_neg_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLDQSEN)
$display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i);
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time);
end
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%16] <= 1'b1;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
check_write_dqs_high[i] <= 1'b0;
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(posedge dqs_in[16]) dqs_neg_timing_check(16);
always @(posedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
endmodule
|
module top(
(* dont_touch = "true" *) input wire pcie_pipe_clk,
input wire pcie_rst_n,
(* dont_touch = "true" *) input wire pcie_clk_p,
input wire pcie_clk_n,
input wire pcie_rx_p,
input wire pcie_rx_n,
output wire pcie_tx_p,
output wire pcie_tx_n,
output drprdy
);
wire pcie_refclk, pcie_gt_refclk, pcie_pll0clk;
wire DRPCLK, DRPRDY, DRPEN, DRPWE;
wire [15:0] DRPDI;
wire [15:0] GTP_COMMON_DRPDI;
wire [15:0] GTP_CHANNEL_DRPDI;
wire [15:0] PCIE_DRPDI;
wire [15:0] DRPDO;
wire [15:0] GTP_COMMON_DRPDO;
wire [15:0] GTP_CHANNEL_DRPDO;
wire [15:0] PCIE_DRPDO;
wire GTP_COMMON_DRPRDY, GTP_CHANNEL_DRPRDY, PCIE_DRPRDY;
assign DRPEN = 1'b1;
assign DRPWE = 1'b1;
assign drprdy = GTP_COMMON_DRPRDY & GTP_CHANNEL_DRPRDY & PCIE_DRPRDY;
genvar i;
generate
for (i = 0; i < 16; i=i+1) begin
assign DRPDO[i] = GTP_COMMON_DRPDO & GTP_CHANNEL_DRPDO & PCIE_DRPDO;
end
endgenerate
generate
for (i = 0; i < 16; i=i+1) begin
assign GTP_COMMON_DRPDI[i] = DRPDI[i];
assign GTP_CHANNEL_DRPDI[i] = DRPDI[i];
assign PCIE_DRPDI[i] = DRPDI[i];
end
endgenerate
IBUFDS_GTE2 IBUFDS_GTE2(
.CEB(pcie_rst_n),
.I(pcie_clk_p),
.IB(pcie_clk_n),
.O(pcie_refclk)
);
GTPE2_COMMON #(
.BIAS_CFG(64'h0000000000050001),
.COMMON_CFG(32'h00000000),
.IS_DRPCLK_INVERTED(1'b0),
.IS_GTGREFCLK0_INVERTED(1'b0),
.IS_GTGREFCLK1_INVERTED(1'b0),
.IS_PLL0LOCKDETCLK_INVERTED(1'b0),
.IS_PLL1LOCKDETCLK_INVERTED(1'b0),
.PLL0_CFG(27'h01F024C),
.PLL0_DMON_CFG(1'b0),
.PLL0_FBDIV(5),
.PLL0_FBDIV_45(5),
.PLL0_INIT_CFG(24'h00001E),
.PLL0_LOCK_CFG(9'h1E8),
.PLL0_REFCLK_DIV(1),
.PLL1_CFG(27'h01F024C),
.PLL1_DMON_CFG(1'b0),
.PLL1_FBDIV(5),
.PLL1_FBDIV_45(5),
.PLL1_INIT_CFG(24'h00001E),
.PLL1_LOCK_CFG(9'h1E8),
.PLL1_REFCLK_DIV(1),
.PLL_CLKOUT_CFG(8'b00000000),
.RSVD_ATTR0(16'h0000),
.RSVD_ATTR1(16'h0000)
) GTP_COMMON_INST (
.BGBYPASSB(1'b1),
.BGMONITORENB(1'b1),
.BGPDB(1'b1),
.BGRCALOVRD({1'b1,1'b1,1'b1,1'b1,1'b1}),
.BGRCALOVRDENB(1'b1),
.DRPADDR(8'b10101010),
.DRPCLK(DRPCLK),
.DRPDI(GTP_COMMON_DRPDI),
.DRPDO(GTP_COMMON_DRPDO),
.DRPEN(DRPEN),
.DRPRDY(GTP_COMMON_DRPRDY),
.DRPWE(DRPWE),
.GTGREFCLK0(1'b0),
.GTGREFCLK1(1'b0),
.GTREFCLK0(pcie_refclk),
.GTREFCLK1(1'b0),
.PLL0OUTCLK(pcie_pll0clk),
.PLL0OUTREFCLK(pcie_gt_refclk),
.PLL0LOCKDETCLK(1'b0),
.PLL0LOCKEN(1'b1),
.PLL0REFCLKSEL({1'b0,1'b0,1'b1}),
.PLL1LOCKDETCLK(1'b0),
.PLL1LOCKEN(1'b1),
.PLL1PD(1'b1),
.PLL1REFCLKSEL({1'b0,1'b0,1'b1}),
.PLL1RESET(1'b1),
.PMARSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.RCALENB(1'b1),
);
GTPE2_CHANNEL #(
.ACJTAG_DEBUG_MODE(1'b0),
.ACJTAG_MODE(1'b0),
.ACJTAG_RESET(1'b0),
.ADAPT_CFG0(20'b00000000000000000000),
.ALIGN_COMMA_DOUBLE("FALSE"),
.ALIGN_COMMA_ENABLE(10'b1111111111),
.ALIGN_COMMA_WORD(1),
.ALIGN_MCOMMA_DET("TRUE"),
.ALIGN_MCOMMA_VALUE(10'b1010000011),
.ALIGN_PCOMMA_DET("TRUE"),
.ALIGN_PCOMMA_VALUE(10'b0101111100),
.CBCC_DATA_SOURCE_SEL("DECODED"),
.CFOK_CFG(43'b1001001000000000000000001000000111010000000),
.CFOK_CFG2(7'b0100000),
.CFOK_CFG3(7'b0100000),
.CFOK_CFG4(1'b0),
.CFOK_CFG5(2'b00),
.CFOK_CFG6(4'b0000),
.CHAN_BOND_KEEP_ALIGN("TRUE"),
.CHAN_BOND_MAX_SKEW(7),
.CHAN_BOND_SEQ_1_1(10'b0001001010),
.CHAN_BOND_SEQ_1_2(10'b0001001010),
.CHAN_BOND_SEQ_1_3(10'b0001001010),
.CHAN_BOND_SEQ_1_4(10'b0110111100),
.CHAN_BOND_SEQ_1_ENABLE(4'b1111),
.CHAN_BOND_SEQ_2_1(10'b0001000101),
.CHAN_BOND_SEQ_2_2(10'b0001000101),
.CHAN_BOND_SEQ_2_3(10'b0001000101),
.CHAN_BOND_SEQ_2_4(10'b0110111100),
.CHAN_BOND_SEQ_2_ENABLE(4'b1111),
.CHAN_BOND_SEQ_2_USE("TRUE"),
.CHAN_BOND_SEQ_LEN(4),
.CLK_COMMON_SWING(1'b0),
.CLK_CORRECT_USE("TRUE"),
.CLK_COR_KEEP_IDLE("TRUE"),
.CLK_COR_MAX_LAT(21),
.CLK_COR_MIN_LAT(19),
.CLK_COR_PRECEDENCE("TRUE"),
.CLK_COR_REPEAT_WAIT(0),
.CLK_COR_SEQ_1_1(10'b0100011100),
.CLK_COR_SEQ_1_2(10'b0000000000),
.CLK_COR_SEQ_1_3(10'b0000000000),
.CLK_COR_SEQ_1_4(10'b0000000000),
.CLK_COR_SEQ_1_ENABLE(4'b1111),
.CLK_COR_SEQ_2_1(10'b0000000000),
.CLK_COR_SEQ_2_2(10'b0000000000),
.CLK_COR_SEQ_2_3(10'b0000000000),
.CLK_COR_SEQ_2_4(10'b0000000000),
.CLK_COR_SEQ_2_ENABLE(4'b0000),
.CLK_COR_SEQ_2_USE("FALSE"),
.CLK_COR_SEQ_LEN(1),
.DEC_MCOMMA_DETECT("TRUE"),
.DEC_PCOMMA_DETECT("TRUE"),
.DEC_VALID_COMMA_ONLY("FALSE"),
.DMONITOR_CFG(24'h000B01),
.ES_CLK_PHASE_SEL(1'b0),
.ES_CONTROL(6'b000000),
.ES_ERRDET_EN("FALSE"),
.ES_EYE_SCAN_EN("FALSE"),
.ES_HORZ_OFFSET(12'h010),
.ES_PMA_CFG(10'b0000000000),
.ES_PRESCALE(5'b00000),
.ES_QUALIFIER(80'h00000000000000000000),
.ES_QUAL_MASK(80'h00000000000000000000),
.ES_SDATA_MASK(80'h00000000000000000000),
.ES_VERT_OFFSET(9'b000000000),
.FTS_DESKEW_SEQ_ENABLE(4'b1111),
.FTS_LANE_DESKEW_CFG(4'b1111),
.FTS_LANE_DESKEW_EN("TRUE"),
.GEARBOX_MODE(3'b000),
.IS_CLKRSVD0_INVERTED(1'b0),
.IS_CLKRSVD1_INVERTED(1'b0),
.IS_DMONITORCLK_INVERTED(1'b0),
.IS_DRPCLK_INVERTED(1'b0),
.IS_RXUSRCLK2_INVERTED(1'b0),
.IS_RXUSRCLK_INVERTED(1'b0),
.IS_SIGVALIDCLK_INVERTED(1'b0),
.IS_TXPHDLYTSTCLK_INVERTED(1'b0),
.IS_TXUSRCLK2_INVERTED(1'b0),
.IS_TXUSRCLK_INVERTED(1'b0),
.LOOPBACK_CFG(1'b0),
.OUTREFCLK_SEL_INV(2'b11),
.PCS_PCIE_EN("TRUE"),
.PCS_RSVD_ATTR(48'h000000000100),
.PD_TRANS_TIME_FROM_P2(12'h03C),
.PD_TRANS_TIME_NONE_P2(8'h09),
.PD_TRANS_TIME_TO_P2(8'h64),
.PMA_LOOPBACK_CFG(1'b0),
.PMA_RSV(32'h00000333),
.PMA_RSV2(32'h00002040),
.PMA_RSV3(2'b00),
.PMA_RSV4(4'b0000),
.PMA_RSV5(1'b0),
.PMA_RSV6(1'b0),
.PMA_RSV7(1'b0),
.RXBUFRESET_TIME(5'b00001),
.RXBUF_ADDR_MODE("FULL"),
.RXBUF_EIDLE_HI_CNT(4'b0100),
.RXBUF_EIDLE_LO_CNT(4'b0000),
.RXBUF_EN("TRUE"),
.RXBUF_RESET_ON_CB_CHANGE("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN("FALSE"),
.RXBUF_RESET_ON_EIDLE("TRUE"),
.RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
.RXBUF_THRESH_OVFLW(61),
.RXBUF_THRESH_OVRD("FALSE"),
.RXBUF_THRESH_UNDFLW(4),
.RXCDRFREQRESET_TIME(5'b00001),
.RXCDRPHRESET_TIME(5'b00001),
.RXCDR_CFG(83'h0000107FE406001041010),
.RXCDR_FR_RESET_ON_EIDLE(1'b0),
.RXCDR_HOLD_DURING_EIDLE(1'b1),
.RXCDR_LOCK_CFG(6'b010101),
.RXCDR_PH_RESET_ON_EIDLE(1'b0),
.RXDLY_CFG(16'h001F),
.RXDLY_LCFG(9'h030),
.RXDLY_TAP_CFG(16'h0000),
.RXGEARBOX_EN("FALSE"),
.RXISCANRESET_TIME(5'b00001),
.RXLPMRESET_TIME(7'b0001111),
.RXLPM_BIAS_STARTUP_DISABLE(1'b0),
.RXLPM_CFG(4'b0110),
.RXLPM_CFG1(1'b0),
.RXLPM_CM_CFG(1'b0),
.RXLPM_GC_CFG(9'b111100010),
.RXLPM_GC_CFG2(3'b001),
.RXLPM_HF_CFG(14'b00001111110000),
.RXLPM_HF_CFG2(5'b01010),
.RXLPM_HF_CFG3(4'b0000),
.RXLPM_HOLD_DURING_EIDLE(1'b1),
.RXLPM_INCM_CFG(1'b1),
.RXLPM_IPCM_CFG(1'b0),
.RXLPM_LF_CFG(18'b000000001111110000),
.RXLPM_LF_CFG2(5'b01010),
.RXLPM_OSINT_CFG(3'b100),
.RXOOB_CFG(7'b0000110),
.RXOOB_CLK_CFG("FABRIC"),
.RXOSCALRESET_TIME(5'b00011),
.RXOSCALRESET_TIMEOUT(5'b00000),
.RXOUT_DIV(2),
.RXPCSRESET_TIME(5'b00001),
.RXPHDLY_CFG(24'h004020),
.RXPH_CFG(24'h000000),
.RXPH_MONITOR_SEL(5'b00000),
.RXPI_CFG0(3'b000),
.RXPI_CFG1(1'b1),
.RXPI_CFG2(1'b1),
.RXPMARESET_TIME(5'b00011),
.RXPRBS_ERR_LOOPBACK(1'b0),
.RXSLIDE_AUTO_WAIT(7),
.RXSLIDE_MODE("PMA"),
.RXSYNC_MULTILANE(1'b1),
.RXSYNC_OVRD(1'b1),
.RXSYNC_SKIP_DA(1'b0),
.RX_BIAS_CFG(16'b0000111100110011),
.RX_BUFFER_CFG(6'b000000),
.RX_CLK25_DIV(4),
.RX_CLKMUX_EN(1'b1),
.RX_CM_SEL(2'b11),
.RX_CM_TRIM(4'b1010),
.RX_DATA_WIDTH(20),
.RX_DDI_SEL(6'b000000),
.RX_DEBUG_CFG(14'b00000000000000),
.RX_DEFER_RESET_BUF_EN("TRUE"),
.RX_DISPERR_SEQ_MATCH("TRUE"),
.RX_OS_CFG(13'b0000010000000),
.RX_SIG_VALID_DLY(10),
.RX_XCLK_SEL("RXREC"),
.SAS_MAX_COM(64),
.SAS_MIN_COM(36),
.SATA_BURST_SEQ_LEN(4'b1111),
.SATA_BURST_VAL(3'b100),
.SATA_EIDLE_VAL(3'b100),
.SATA_MAX_BURST(8),
.SATA_MAX_INIT(21),
.SATA_MAX_WAKE(7),
.SATA_MIN_BURST(4),
.SATA_MIN_INIT(12),
.SATA_MIN_WAKE(4),
.SATA_PLL_CFG("VCO_3000MHZ"),
.SHOW_REALIGN_COMMA("FALSE"),
.TERM_RCAL_CFG(15'b100001000010000),
.TERM_RCAL_OVRD(3'b000),
.TRANS_TIME_RATE(8'h0E),
.TST_RSV(32'h00000000),
.TXBUF_EN("FALSE"),
.TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
.TXDLY_CFG(16'h001F),
.TXDLY_LCFG(9'h030),
.TXDLY_TAP_CFG(16'h0000),
.TXGEARBOX_EN("FALSE"),
.TXOOB_CFG(1'b1),
.TXOUT_DIV(2),
.TXPCSRESET_TIME(5'b00001),
.TXPHDLY_CFG(24'h084020),
.TXPH_CFG(16'h0780),
.TXPH_MONITOR_SEL(5'b00000),
.TXPI_CFG0(2'b00),
.TXPI_CFG1(2'b00),
.TXPI_CFG2(2'b00),
.TXPI_CFG3(1'b0),
.TXPI_CFG4(1'b0),
.TXPI_CFG5(3'b000),
.TXPI_GREY_SEL(1'b0),
.TXPI_INVSTROBE_SEL(1'b0),
.TXPI_PPMCLK_SEL("TXUSRCLK2"),
.TXPI_PPM_CFG(8'b00000000),
.TXPI_SYNFREQ_PPM(3'b000),
.TXPMARESET_TIME(5'b00011),
.TXSYNC_MULTILANE(1'b1),
.TXSYNC_OVRD(1'b1),
.TXSYNC_SKIP_DA(1'b0),
.TX_CLK25_DIV(4),
.TX_CLKMUX_EN(1'b1),
.TX_DATA_WIDTH(20),
.TX_DEEMPH0(6'b010100),
.TX_DEEMPH1(6'b001011),
.TX_DRIVE_MODE("PIPE"),
.TX_EIDLE_ASSERT_DELAY(3'b010),
.TX_EIDLE_DEASSERT_DELAY(3'b010),
.TX_LOOPBACK_DRIVE_HIZ("FALSE"),
.TX_MAINCURSOR_SEL(1'b0),
.TX_MARGIN_FULL_0(7'b1001111),
.TX_MARGIN_FULL_1(7'b1001110),
.TX_MARGIN_FULL_2(7'b1001101),
.TX_MARGIN_FULL_3(7'b1001100),
.TX_MARGIN_FULL_4(7'b1000011),
.TX_MARGIN_LOW_0(7'b1000101),
.TX_MARGIN_LOW_1(7'b1000110),
.TX_MARGIN_LOW_2(7'b1000011),
.TX_MARGIN_LOW_3(7'b1000010),
.TX_MARGIN_LOW_4(7'b1000000),
.TX_PREDRIVER_MODE(1'b0),
.TX_RXDETECT_CFG(14'h0064),
.TX_RXDETECT_REF(3'b011),
.TX_XCLK_SEL("TXUSR"),
.UCODEER_CLR(1'b0),
.USE_PCS_CLK_PHASE_SEL(1'b0)
) GTP_CHANNEL_INST (
.CFGRESET(1'b0),
.CLKRSVD0(1'b0),
.CLKRSVD1(1'b0),
.DMONFIFORESET(1'b0),
.DMONITORCLK(1'b0),
.DRPADDR(8'b10101010),
.DRPCLK(DRPCLK),
.DRPDI(GTP_CHANNEL_DRPDI),
.DRPDO(GTP_CHANNEL_DRPDO),
.DRPEN(DRPEN),
.DRPRDY(GTP_CHANNEL_DRPRDY),
.DRPWE(DRPWE),
.GTPRXN(pcie_rx_n),
.GTPRXP(pcie_rx_p),
.GTPTXN(pcie_tx_n),
.GTPTXP(pcie_tx_p),
.GTRESETSEL(1'b0),
.GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GTRXRESET(pcie_rst_n),
.GTTXRESET(pcie_rst_n),
.PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PLL0CLK(pcie_pll0clk),
.PLL0REFCLK(pcie_gt_refclk),
.PLL1CLK(1'b0),
.PLL1REFCLK(1'b0),
.PMARSVDIN0(1'b0),
.PMARSVDIN1(1'b0),
.PMARSVDIN2(1'b0),
.PMARSVDIN3(1'b0),
.PMARSVDIN4(1'b0),
.RX8B10BEN(1'b1),
.RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.RXCDRHOLD(1'b0),
.RXCDROVRDEN(1'b0),
.RXCDRRESETRSV(1'b0),
.RXCHBONDEN(1'b1),
.RXCHBONDI({1'b0,1'b0,1'b0,1'b0}),
.RXCHBONDLEVEL({1'b0,1'b1,1'b1}),
.RXCHBONDMASTER(1'b1),
.RXCHBONDSLAVE(1'b0),
.RXCOMMADETEN(1'b1),
.RXDDIEN(1'b0),
.RXDFEXYDEN(1'b0),
.RXDLYBYPASS(1'b1),
.RXDLYEN(1'b0),
.RXDLYOVRDEN(1'b0),
.RXDLYSRESET(1'b0),
.RXELECIDLEMODE({1'b0,1'b0}),
.RXGEARBOXSLIP(1'b0),
.RXLPMHFHOLD(1'b0),
.RXLPMHFOVRDEN(1'b0),
.RXLPMLFHOLD(1'b0),
.RXLPMLFOVRDEN(1'b0),
.RXLPMOSINTNTRLEN(1'b0),
.RXLPMRESET(1'b0),
.RXMCOMMAALIGNEN(1'b1),
.RXOOBRESET(1'b0),
.RXOSCALRESET(1'b0),
.RXOSHOLD(1'b0),
.RXOSINTCFG({1'b0,1'b0,1'b1,1'b0}),
.RXOSINTEN(1'b1),
.RXOSINTHOLD(1'b0),
.RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
.RXOSINTNTRLEN(1'b0),
.RXOSINTOVRDEN(1'b0),
.RXOSINTPD(1'b0),
.RXOSINTSTROBE(1'b0),
.RXOSINTTESTOVRDEN(1'b0),
.RXOSOVRDEN(1'b0),
.RXOUTCLKSEL({1'b0,1'b0,1'b0}),
.RXPCOMMAALIGNEN(1'b1),
.RXPCSRESET(pcie_rst_n),
.RXPHALIGN(1'b0),
.RXPHALIGNEN(1'b0),
.RXPHDLYPD(1'b0),
.RXPHDLYRESET(1'b0),
.RXPHOVRDEN(1'b0),
.RXPMARESET(pcie_rst_n),
.RXPRBSCNTRESET(pcie_rst_n),
.RXRATEMODE(1'b0),
.RXSLIDE(1'b0),
.RXSYNCMODE(1'b1),
.RXSYSCLKSEL({1'b0,1'b0}),
.SETERRSTATUS(1'b0),
.TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0}),
.TX8B10BEN(1'b1),
.TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
.TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0}),
.TXCOMINIT(1'b0),
.TXCOMSAS(1'b0),
.TXCOMWAKE(1'b0),
.TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
.TXDIFFPD(1'b0),
.TXDLYBYPASS(1'b0),
.TXDLYHOLD(1'b0),
.TXDLYOVRDEN(1'b0),
.TXDLYUPDOWN(1'b0),
.TXHEADER({1'b0,1'b0,1'b0}),
.TXOUTCLKSEL({1'b0,1'b1,1'b1}),
.TXPCSRESET(1'b0),
.TXPDELECIDLEMODE(1'b0),
.TXPHALIGNEN(1'b1),
.TXPHDLYPD(1'b0),
.TXPHDLYRESET(1'b0),
.TXPHDLYTSTCLK(1'b0),
.TXPHOVRDEN(1'b0),
.TXPIPPMEN(1'b0),
.TXPIPPMOVRDEN(1'b0),
.TXPIPPMPD(1'b0),
.TXPIPPMSEL(1'b0),
.TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.TXPISOPD(1'b0),
.TXPMARESET(1'b0),
.TXPOLARITY(1'b0),
.TXPOSTCURSORINV(1'b0),
.TXPRECURSORINV(1'b0),
.TXRATEMODE(1'b0),
.TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.TXSTARTSEQ(1'b0),
.TXSWING(1'b0),
.TXSYNCMODE(1'b1),
.TXSYSCLKSEL({1'b0,1'b0}),
);
PCIE_2_1 #(
.AER_BASE_PTR(12'h000),
.AER_CAP_ECRC_CHECK_CAPABLE("FALSE"),
.AER_CAP_ECRC_GEN_CAPABLE("FALSE"),
.AER_CAP_ID(16'h0001),
.AER_CAP_MULTIHEADER("FALSE"),
.AER_CAP_NEXTPTR(12'h000),
.AER_CAP_ON("FALSE"),
.AER_CAP_OPTIONAL_ERR_SUPPORT(24'h000000),
.AER_CAP_PERMIT_ROOTERR_UPDATE("FALSE"),
.AER_CAP_VERSION(4'h1),
.ALLOW_X8_GEN2("FALSE"),
.BAR0(32'hFFF00000),
.BAR1(32'h00000000),
.BAR2(32'h00000000),
.BAR3(32'h00000000),
.BAR4(32'h00000000),
.BAR5(32'h00000000),
.CAPABILITIES_PTR(8'h40),
.CARDBUS_CIS_POINTER(32'h00000000),
.CFG_ECRC_ERR_CPLSTAT(0),
.CLASS_CODE(24'h058000),
.CMD_INTX_IMPLEMENTED("FALSE"),
.CPL_TIMEOUT_DISABLE_SUPPORTED("FALSE"),
.CPL_TIMEOUT_RANGES_SUPPORTED(4'h2),
.CRM_MODULE_RSTS(7'h00),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED("FALSE"),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED("FALSE"),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED("FALSE"),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED("FALSE"),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED("FALSE"),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED("FALSE"),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED("FALSE"),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED("FALSE"),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES(2'h0),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING("FALSE"),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED(2'h0),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE("TRUE"),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE("TRUE"),
.DEV_CAP_ENDPOINT_L0S_LATENCY(0),
.DEV_CAP_ENDPOINT_L1_LATENCY(7),
.DEV_CAP_EXT_TAG_SUPPORTED("FALSE"),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE("FALSE"),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(2),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT(0),
.DEV_CAP_ROLE_BASED_ERROR("TRUE"),
.DEV_CAP_RSVD_14_12(0),
.DEV_CAP_RSVD_17_16(0),
.DEV_CAP_RSVD_31_29(0),
.DEV_CONTROL_AUX_POWER_SUPPORTED("FALSE"),
.DEV_CONTROL_EXT_TAG_DEFAULT("FALSE"),
.DISABLE_ASPM_L1_TIMER("FALSE"),
.DISABLE_BAR_FILTERING("FALSE"),
.DISABLE_ERR_MSG("FALSE"),
.DISABLE_ID_CHECK("FALSE"),
.DISABLE_LANE_REVERSAL("TRUE"),
.DISABLE_LOCKED_FILTER("FALSE"),
.DISABLE_PPM_FILTER("FALSE"),
.DISABLE_RX_POISONED_RESP("FALSE"),
.DISABLE_RX_TC_FILTER("FALSE"),
.DISABLE_SCRAMBLING("FALSE"),
.DNSTREAM_LINK_NUM(8'h00),
.DSN_BASE_PTR(12'h100),
.DSN_CAP_ID(16'h0003),
.DSN_CAP_NEXTPTR(12'h000),
.DSN_CAP_ON("TRUE"),
.DSN_CAP_VERSION(4'h1),
.ENABLE_MSG_ROUTE(11'h000),
.ENABLE_RX_TD_ECRC_TRIM("FALSE"),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED("FALSE"),
.ENTER_RVRY_EI_L0("TRUE"),
.EXIT_LOOPBACK_ON_EI("TRUE"),
.EXPANSION_ROM(32'h00000000),
.EXT_CFG_CAP_PTR(6'h3F),
.EXT_CFG_XP_CAP_PTR(10'h3FF),
.HEADER_TYPE(8'h00),
.INFER_EI(5'h00),
.INTERRUPT_PIN(8'h00),
.INTERRUPT_STAT_AUTO("TRUE"),
.IS_SWITCH("FALSE"),
.LAST_CONFIG_DWORD(10'h3FF),
.LINK_CAP_ASPM_OPTIONALITY("FALSE"),
.LINK_CAP_ASPM_SUPPORT(1),
.LINK_CAP_CLOCK_POWER_MANAGEMENT("FALSE"),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP("FALSE"),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1(7),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2(7),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1(7),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2(7),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1(7),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2(7),
.LINK_CAP_L1_EXIT_LATENCY_GEN1(7),
.LINK_CAP_L1_EXIT_LATENCY_GEN2(7),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP("FALSE"),
.LINK_CAP_MAX_LINK_SPEED(4'h2),
.LINK_CAP_MAX_LINK_WIDTH(6'h04),
.LINK_CAP_RSVD_23(0),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE("FALSE"),
.LINK_CONTROL_RCB(0),
.LINK_CTRL2_DEEMPHASIS("FALSE"),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE("FALSE"),
.LINK_CTRL2_TARGET_LINK_SPEED(4'h2),
.LINK_STATUS_SLOT_CLOCK_CONFIG("TRUE"),
.LL_ACK_TIMEOUT(15'h0000),
.LL_ACK_TIMEOUT_EN("FALSE"),
.LL_ACK_TIMEOUT_FUNC(0),
.LL_REPLAY_TIMEOUT(15'h0000),
.LL_REPLAY_TIMEOUT_EN("FALSE"),
.LL_REPLAY_TIMEOUT_FUNC(1),
.LTSSM_MAX_LINK_WIDTH(6'h04),
.MPS_FORCE("FALSE"),
.MSIX_BASE_PTR(8'h9C),
.MSIX_CAP_ID(8'h11),
.MSIX_CAP_NEXTPTR(8'h00),
.MSIX_CAP_ON("FALSE"),
.MSIX_CAP_PBA_BIR(0),
.MSIX_CAP_PBA_OFFSET(29'h00000000),
.MSIX_CAP_TABLE_BIR(0),
.MSIX_CAP_TABLE_OFFSET(29'h00000000),
.MSIX_CAP_TABLE_SIZE(11'h000),
.MSI_BASE_PTR(8'h48),
.MSI_CAP_64_BIT_ADDR_CAPABLE("FALSE"),
.MSI_CAP_ID(8'h05),
.MSI_CAP_MULTIMSGCAP(0),
.MSI_CAP_MULTIMSG_EXTENSION(0),
.MSI_CAP_NEXTPTR(8'h60),
.MSI_CAP_ON("TRUE"),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE("FALSE"),
.N_FTS_COMCLK_GEN1(255),
.N_FTS_COMCLK_GEN2(255),
.N_FTS_GEN1(255),
.N_FTS_GEN2(255),
.PCIE_BASE_PTR(8'h60),
.PCIE_CAP_CAPABILITY_ID(8'h10),
.PCIE_CAP_CAPABILITY_VERSION(4'h2),
.PCIE_CAP_DEVICE_PORT_TYPE(4'h0),
.PCIE_CAP_NEXTPTR(8'h00),
.PCIE_CAP_ON("TRUE"),
.PCIE_CAP_RSVD_15_14(0),
.PCIE_CAP_SLOT_IMPLEMENTED("FALSE"),
.PCIE_REVISION(2),
.PL_AUTO_CONFIG(0),
.PL_FAST_TRAIN("TRUE"),
.PM_ASPML0S_TIMEOUT(15'h0000),
.PM_ASPML0S_TIMEOUT_EN("FALSE"),
.PM_ASPML0S_TIMEOUT_FUNC(0),
.PM_ASPM_FASTEXIT("FALSE"),
.PM_BASE_PTR(8'h40),
.PM_CAP_AUXCURRENT(0),
.PM_CAP_D1SUPPORT("FALSE"),
.PM_CAP_D2SUPPORT("FALSE"),
.PM_CAP_DSI("FALSE"),
.PM_CAP_ID(8'h01),
.PM_CAP_NEXTPTR(8'h48),
.PM_CAP_ON("TRUE"),
.PM_CAP_PMESUPPORT(5'h0F),
.PM_CAP_PME_CLOCK("FALSE"),
.PM_CAP_RSVD_04(0),
.PM_CAP_VERSION(3),
.PM_CSR_B2B3("FALSE"),
.PM_CSR_BPCCEN("FALSE"),
.PM_CSR_NOSOFTRST("TRUE"),
.PM_DATA0(8'h00),
.PM_DATA1(8'h00),
.PM_DATA2(8'h00),
.PM_DATA3(8'h00),
.PM_DATA4(8'h00),
.PM_DATA5(8'h00),
.PM_DATA6(8'h00),
.PM_DATA7(8'h00),
.PM_DATA_SCALE0(2'h0),
.PM_DATA_SCALE1(2'h0),
.PM_DATA_SCALE2(2'h0),
.PM_DATA_SCALE3(2'h0),
.PM_DATA_SCALE4(2'h0),
.PM_DATA_SCALE5(2'h0),
.PM_DATA_SCALE6(2'h0),
.PM_DATA_SCALE7(2'h0),
.PM_MF("FALSE"),
.RBAR_BASE_PTR(12'h000),
.RBAR_CAP_CONTROL_ENCODEDBAR0(5'h00),
.RBAR_CAP_CONTROL_ENCODEDBAR1(5'h00),
.RBAR_CAP_CONTROL_ENCODEDBAR2(5'h00),
.RBAR_CAP_CONTROL_ENCODEDBAR3(5'h00),
.RBAR_CAP_CONTROL_ENCODEDBAR4(5'h00),
.RBAR_CAP_CONTROL_ENCODEDBAR5(5'h00),
.RBAR_CAP_ID(16'h0015),
.RBAR_CAP_INDEX0(3'h0),
.RBAR_CAP_INDEX1(3'h0),
.RBAR_CAP_INDEX2(3'h0),
.RBAR_CAP_INDEX3(3'h0),
.RBAR_CAP_INDEX4(3'h0),
.RBAR_CAP_INDEX5(3'h0),
.RBAR_CAP_NEXTPTR(12'h000),
.RBAR_CAP_ON("FALSE"),
.RBAR_CAP_SUP0(32'h00000001),
.RBAR_CAP_SUP1(32'h00000001),
.RBAR_CAP_SUP2(32'h00000001),
.RBAR_CAP_SUP3(32'h00000001),
.RBAR_CAP_SUP4(32'h00000001),
.RBAR_CAP_SUP5(32'h00000001),
.RBAR_CAP_VERSION(4'h1),
.RBAR_NUM(3'h0),
.RECRC_CHK(0),
.RECRC_CHK_TRIM("FALSE"),
.ROOT_CAP_CRS_SW_VISIBILITY("FALSE"),
.RP_AUTO_SPD(2'h1),
.RP_AUTO_SPD_LOOPCNT(5'h1F),
.SELECT_DLL_IF("FALSE"),
.SLOT_CAP_ATT_BUTTON_PRESENT("FALSE"),
.SLOT_CAP_ATT_INDICATOR_PRESENT("FALSE"),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT("FALSE"),
.SLOT_CAP_HOTPLUG_CAPABLE("FALSE"),
.SLOT_CAP_HOTPLUG_SURPRISE("FALSE"),
.SLOT_CAP_MRL_SENSOR_PRESENT("FALSE"),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT("FALSE"),
.SLOT_CAP_PHYSICAL_SLOT_NUM(13'h0000),
.SLOT_CAP_POWER_CONTROLLER_PRESENT("FALSE"),
.SLOT_CAP_POWER_INDICATOR_PRESENT("FALSE"),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE(0),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE(8'h00),
.SPARE_BIT0(0),
.SPARE_BIT1(0),
.SPARE_BIT2(0),
.SPARE_BIT3(0),
.SPARE_BIT4(0),
.SPARE_BIT5(0),
.SPARE_BIT6(0),
.SPARE_BIT7(0),
.SPARE_BIT8(0),
.SPARE_BYTE0(8'h00),
.SPARE_BYTE1(8'h00),
.SPARE_BYTE2(8'h00),
.SPARE_BYTE3(8'h00),
.SPARE_WORD0(32'h00000000),
.SPARE_WORD1(32'h00000000),
.SPARE_WORD2(32'h00000000),
.SPARE_WORD3(32'h00000000),
.SSL_MESSAGE_AUTO("FALSE"),
.TECRC_EP_INV("FALSE"),
.TL_RBYPASS("FALSE"),
.TL_RX_RAM_RADDR_LATENCY(0),
.TL_RX_RAM_RDATA_LATENCY(2),
.TL_RX_RAM_WRITE_LATENCY(0),
.TL_TFC_DISABLE("FALSE"),
.TL_TX_CHECKS_DISABLE("FALSE"),
.TL_TX_RAM_RADDR_LATENCY(0),
.TL_TX_RAM_RDATA_LATENCY(2),
.TL_TX_RAM_WRITE_LATENCY(0),
.TRN_DW("TRUE"),
.TRN_NP_FC("TRUE"),
.UPCONFIG_CAPABLE("TRUE"),
.UPSTREAM_FACING("TRUE"),
.UR_ATOMIC("FALSE"),
.UR_CFG1("TRUE"),
.UR_INV_REQ("TRUE"),
.UR_PRS_RESPONSE("TRUE"),
.USER_CLK2_DIV2("TRUE"),
.USER_CLK_FREQ(3),
.USE_RID_PINS("FALSE"),
.VC0_CPL_INFINITE("TRUE"),
.VC0_RX_RAM_LIMIT(13'h07FF),
.VC0_TOTAL_CREDITS_CD(850),
.VC0_TOTAL_CREDITS_CH(72),
.VC0_TOTAL_CREDITS_NPD(8),
.VC0_TOTAL_CREDITS_NPH(4),
.VC0_TOTAL_CREDITS_PD(64),
.VC0_TOTAL_CREDITS_PH(4),
.VC0_TX_LASTPACKET(29),
.VC_BASE_PTR(12'h000),
.VC_CAP_ID(16'h0002),
.VC_CAP_NEXTPTR(12'h000),
.VC_CAP_ON("FALSE"),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS("FALSE"),
.VC_CAP_VERSION(4'h1),
.VSEC_BASE_PTR(12'h000),
.VSEC_CAP_HDR_ID(16'h1234),
.VSEC_CAP_HDR_LENGTH(12'h018),
.VSEC_CAP_HDR_REVISION(4'h1),
.VSEC_CAP_ID(16'h000B),
.VSEC_CAP_IS_LINK_VISIBLE("TRUE"),
.VSEC_CAP_NEXTPTR(12'h000),
.VSEC_CAP_ON("FALSE"),
.VSEC_CAP_VERSION(4'h1)
) PCIE_INST (
.DLRSTN(1'b1),
.DRPADDR(8'b10101010),
.DRPCLK(DRPCLK),
.DRPDI(PCIE_DRPDI),
.DRPDO(PCIE_DRPDO),
.DRPEN(DRPEN),
.DRPRDY(PCIE_DRPRDY),
.DRPWE(DRPWE),
.FUNCLVLRSTN(1'b1),
.LL2SENDASREQL1(1'b0),
.LL2SENDENTERL1(1'b0),
.LL2SENDENTERL23(1'b0),
.LL2SENDPMACK(1'b0),
.LL2SUSPENDNOW(1'b0),
.LL2TLPRCV(1'b0),
.PIPECLK(pcie_pipe_clk),
.PLRSTN(1'b1),
.SYSRSTN(pcie_rst_n),
.TL2ASPMSUSPENDCREDITCHECK(1'b0),
.TL2PPMSUSPENDREQ(1'b0),
.TLRSTN(1'b1),
.TRNRFCPRET(1'b1),
.TRNTDLLPSRCRDY(1'b0),
.USERCLK(pcie_pipe_clk),
.USERCLK2(pcie_pipe_clk),
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:47:55 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.v
// Design : system_ov7670_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_0_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
wire xclk;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_0_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod),
.xclk(xclk));
VCC VCC
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "i2c_sender" *)
module system_ov7670_controller_0_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_controller" *)
module system_ov7670_controller_0_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire sys_clk_i_1_n_0;
wire taken;
wire xclk;
system_ov7670_controller_0_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_0_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
LUT1 #(
.INIT(2'h1))
sys_clk_i_1
(.I0(xclk),
.O(sys_clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
sys_clk_reg
(.C(clk),
.CE(1'b1),
.D(sys_clk_i_1_n_0),
.Q(xclk),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_registers" *)
module system_ov7670_controller_0_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module DRAMWriter(
//AXI port
input wire ACLK,
input wire ARESETN,
output reg [31:0] M_AXI_AWADDR,
input wire M_AXI_AWREADY,
output wire M_AXI_AWVALID,
output wire [63:0] M_AXI_WDATA,
output wire [7:0] M_AXI_WSTRB,
input wire M_AXI_WREADY,
output wire M_AXI_WVALID,
output wire M_AXI_WLAST,
input wire [1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire [3:0] M_AXI_AWLEN,
output wire [1:0] M_AXI_AWSIZE,
output wire [1:0] M_AXI_AWBURST,
//Control config
input wire CONFIG_VALID,
output wire CONFIG_READY,
input wire [31:0] CONFIG_START_ADDR,
input wire [31:0] CONFIG_NBYTES,
//RAM port
input wire [63:0] DATA,
output wire DATA_READY,
input wire DATA_VALID
);
assign M_AXI_AWLEN = 4'b1111;
assign M_AXI_AWSIZE = 2'b11;
assign M_AXI_AWBURST = 2'b01;
assign M_AXI_WSTRB = 8'b11111111;
parameter IDLE = 0, RWAIT = 1;
//ADDR logic
reg [31:0] a_count;
reg a_state;
assign M_AXI_AWVALID = (a_state == RWAIT);
always @(posedge ACLK) begin
if (ARESETN == 0) begin
a_state <= IDLE;
M_AXI_AWADDR <= 0;
a_count <= 0;
end else case(a_state)
IDLE: begin
if(CONFIG_VALID) begin
M_AXI_AWADDR <= CONFIG_START_ADDR;
a_count <= CONFIG_NBYTES[31:7];
a_state <= RWAIT;
end
end
RWAIT: begin
if (M_AXI_AWREADY == 1) begin
if(a_count - 1 == 0)
a_state <= IDLE;
a_count <= a_count - 1;
M_AXI_AWADDR <= M_AXI_AWADDR + 128;
end
end
endcase
end
//WRITE logic
reg [31:0] b_count;
reg w_state;
reg [3:0] last_count;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
w_state <= IDLE;
b_count <= 0;
end else case(w_state)
IDLE: begin
if(CONFIG_VALID) begin
b_count <= {CONFIG_NBYTES[31:7],7'b0};
w_state <= RWAIT;
last_count <= 4'b1111;
end
end
RWAIT: begin
if (M_AXI_WREADY && M_AXI_WVALID) begin
//use M_AXI_WDATA
if(b_count - 8 == 0) begin
w_state <= IDLE;
end
last_count <= last_count - 4'b1;
b_count <= b_count - 8;
end
end
endcase
end
assign M_AXI_WLAST = last_count == 4'b0000;
assign M_AXI_WVALID = (w_state == RWAIT) && DATA_VALID;
assign DATA_READY = (w_state == RWAIT) && M_AXI_WREADY;
assign CONFIG_READY = (w_state == IDLE) && (a_state == IDLE);
assign M_AXI_BREADY = 1;
assign M_AXI_WDATA = DATA;
endmodule // DRAMWriter
|
// file: sdram_clk_gen_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module sdram_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
sdram_clk_gen_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_4_V
`define SKY130_FD_SC_HDLL__O31AI_4_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o31ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o31ai_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_4_V
|
(* src = "../../verilog/adt7410.v:1", top = 1 *)
module ADT7410 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/adt7410.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/adt7410.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/adt7410.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/adt7410.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_ReceiveSend_n", src = "../../verilog/adt7410.v:11" *)
output I2C_ReceiveSend_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_ReadCount", src = "../../verilog/adt7410.v:13" *)
output[7:0] I2C_ReadCount_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_StartProcess", src = "../../verilog/adt7410.v:15" *)
output I2C_StartProcess_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Busy", src = "../../verilog/adt7410.v:17" *)
input I2C_Busy_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOReadNext", src = "../../verilog/adt7410.v:19" *)
output I2C_FIFOReadNext_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOWrite", src = "../../verilog/adt7410.v:21" *)
output I2C_FIFOWrite_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataIn", src = "../../verilog/adt7410.v:23" *)
output[7:0] I2C_Data_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataOut", src = "../../verilog/adt7410.v:25" *)
input[7:0] I2C_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Error", src = "../../verilog/adt7410.v:27" *)
input I2C_Error_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/adt7410.v:29" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/adt7410.v:31" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/adt7410.v:33" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "WaitCounterPreset_i", src = "../../verilog/adt7410.v:35" *)
input[15:0] WaitCounterPreset_i
);
wire \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.Overflow_s ;
wire \$techmap\I2CFSM_1.$procmux$1156_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1168_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1169_CMP ;
wire [7:0] \$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.Overflow_s ;
(* src = "../../verilog/i2cfsm.v:10" *)
wire [7:0] \I2CFSM_1.Byte0_o ;
(* src = "../../verilog/i2cfsm.v:11" *)
wire [7:0] \I2CFSM_1.Byte1_o ;
(* src = "../../verilog/i2cfsm.v:8" *)
wire \I2CFSM_1.Done_o ;
(* src = "../../verilog/i2cfsm.v:9" *)
wire \I2CFSM_1.Error_o ;
(* src = "../../verilog/i2cfsm.v:77" *)
wire \I2CFSM_1.I2C_FSM_TimerEnable ;
(* src = "../../verilog/i2cfsm.v:75" *)
wire \I2CFSM_1.I2C_FSM_TimerOvfl ;
(* src = "../../verilog/i2cfsm.v:76" *)
wire \I2CFSM_1.I2C_FSM_TimerPreset ;
(* src = "../../verilog/i2cfsm.v:79" *)
wire \I2CFSM_1.I2C_FSM_Wr0 ;
(* src = "../../verilog/i2cfsm.v:78" *)
wire \I2CFSM_1.I2C_FSM_Wr1 ;
(* src = "../../verilog/i2cfsm.v:7" *)
wire \I2CFSM_1.Start_i ;
(* src = "../../verilog/sensorfsm.v:41" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:35" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:31" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] \SensorFSM_1.SensorValue ;
wire I2CFSM_1_Out14_s;
wire I2CFSM_1_CfgMode_s;
wire I2CFSM_1_CfgClk_s;
wire I2CFSM_1_CfgShift_s;
wire I2CFSM_1_CfgDataIn_s;
wire I2CFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out5_s;
wire SensorFSM_1_Out6_s;
wire SensorFSM_1_Out7_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
Byte2Word \$extract$\Byte2Word$2915 (
.H_i(\I2CFSM_1.Byte1_o ),
.L_i(\I2CFSM_1.Byte0_o ),
.Y_o(\SensorFSM_1.SensorValue )
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2910 (
.A_i(8'b00000000),
.B_i(8'b00000010),
.S_i(I2C_ReceiveSend_n_o),
.Y_o(I2C_ReadCount_o)
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2911 (
.A_i(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ),
.B_i(8'b00000011),
.S_i(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Y_o(I2C_Data_o)
);
ByteMuxQuad \$techmap\I2CFSM_1.$extract$\ByteMuxQuad$2909 (
.A_i(8'b00000000),
.B_i(8'b10010001),
.C_i(8'b10010000),
.D_i(8'b00100000),
.SAB_i(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.SC_i(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.SD_i(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Y_o(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y )
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2906 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr0 ),
.Q_o(\I2CFSM_1.Byte0_o ),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2907 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr1 ),
.Q_o(\I2CFSM_1.Byte1_o ),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.D_s ),
.Direction_i(1'b1),
.Enable_i(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Overflow_o(\$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.Overflow_s ),
.PresetVal_i(WaitCounterPreset_i),
.Preset_i(\I2CFSM_1.I2C_FSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\I2CFSM_1.I2C_FSM_TimerOvfl )
);
I2CFSM I2CFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(I2C_Busy_i),
.In1_i(I2C_Error_i),
.In2_i(\I2CFSM_1.I2C_FSM_TimerOvfl ),
.In3_i(\I2CFSM_1.Start_i ),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.Out1_o(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Out2_o(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Out3_o(\I2CFSM_1.Done_o ),
.Out4_o(\I2CFSM_1.I2C_FSM_Wr0 ),
.Out5_o(I2C_ReceiveSend_n_o),
.Out6_o(I2C_StartProcess_o),
.Out7_o(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.Out8_o(\I2CFSM_1.Error_o ),
.Out9_o(\I2CFSM_1.I2C_FSM_Wr1 ),
.Out10_o(I2C_FIFOReadNext_o),
.Out11_o(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Out12_o(\I2CFSM_1.I2C_FSM_TimerPreset ),
.Out13_o(I2C_FIFOWrite_o),
.Out14_o(I2CFSM_1_Out14_s),
.CfgMode_i(I2CFSM_1_CfgMode_s),
.CfgClk_i(I2CFSM_1_CfgClk_s),
.CfgShift_i(I2CFSM_1_CfgShift_s),
.CfgDataIn_i(I2CFSM_1_CfgDataIn_s),
.CfgDataOut_o(I2CFSM_1_CfgDataOut_s)
);
AbsDiff \$techmap\SensorFSM_1.$extract$\AbsDiff$2904 (
.A_i(\SensorFSM_1.SensorValue ),
.B_i(SensorValue_o),
.D_o(\SensorFSM_1.AbsDiffResult )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.ThisAddSubCmp (
.A_i(\SensorFSM_1.AbsDiffResult ),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.D_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ),
.Sign_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ),
.Zero_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s )
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.D_s ),
.Direction_i(1'b1),
.Enable_i(\SensorFSM_1.SensorFSM_TimerEnable ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.Overflow_s ),
.PresetVal_i(PeriodCounterPreset_i),
.Preset_i(\SensorFSM_1.SensorFSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SensorFSM_1.SensorFSM_TimerOvfl )
);
WordRegister \$techmap\SensorFSM_1.$extract$\WordRegister$2905 (
.Clk_i(Clk_i),
.D_i(\SensorFSM_1.SensorValue ),
.Enable_i(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
SensorFSM SensorFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(\I2CFSM_1.Done_o ),
.In2_i(\I2CFSM_1.Error_o ),
.In3_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In4_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.In5_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\I2CFSM_1.Start_i ),
.Out1_o(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Out2_o(CpuIntr_o),
.Out3_o(\SensorFSM_1.SensorFSM_TimerEnable ),
.Out4_o(\SensorFSM_1.SensorFSM_TimerPreset ),
.Out5_o(SensorFSM_1_Out5_s),
.Out6_o(SensorFSM_1_Out6_s),
.Out7_o(SensorFSM_1_Out7_s),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
assign I2CFSM_1_CfgMode_s = 1'b0;
assign I2CFSM_1_CfgClk_s = 1'b0;
assign I2CFSM_1_CfgShift_s = 1'b0;
assign I2CFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule
|
(* -*- coding: utf-8; coq-prog-args: ("-coqlib" "../.." "-R" ".." "Coq" "-top" "Coq.Classes.Morphisms") -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based morphism definition and standard, minimal instances
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Require Export Coq.Classes.RelationClasses.
Generalizable Variables A eqA B C D R RA RB RC m f x y.
Local Obligation Tactic := simpl_relation.
(** * Morphisms.
We now turn to the definition of [Proper] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism for a relation [R] is a proper element of the relation.
The relation [R] will be instantiated by [respectful] and [A] by an arrow
type for usual morphisms. *)
Section Proper.
Let U := Type.
Context {A B : U}.
Class Proper (R : relation A) (m : A) : Prop :=
proper_prf : R m m.
(** Every element in the carrier of a reflexive relation is a morphism
for this relation. We use a proxy class for this case which is used
internally to discharge reflexivity constraints. The [Reflexive]
instance will almost always be used, but it won't apply in general to
any kind of [Proper (A -> B) _ _] goal, making proof-search much
slower. A cleaner solution would be to be able to set different
priorities in different hint bases and select a particular hint
database for resolution of a type class constraint. *)
Class ProperProxy (R : relation A) (m : A) : Prop :=
proper_proxy : R m m.
Lemma eq_proper_proxy (x : A) : ProperProxy (@eq A) x.
Proof. firstorder. Qed.
Lemma reflexive_proper_proxy `(Reflexive A R) (x : A) : ProperProxy R x.
Proof. firstorder. Qed.
Lemma proper_proper_proxy x `(Proper R x) : ProperProxy R x.
Proof. firstorder. Qed.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : A -> B -> Prop)
(R' : forall (x : A) (y : B), C x -> D y -> Prop) :
(forall x : A, C x) -> (forall x : B, D x) -> Prop :=
fun f g => forall x y, R x y -> R' x y (f x) (g y).
(** The non-dependent version is an instance where we forget dependencies. *)
Definition respectful (R : relation A) (R' : relation B) : relation (A -> B) :=
Eval compute in @respectful_hetero A A (fun _ => B) (fun _ => B) R (fun _ _ => R').
End Proper.
(** We favor the use of Leibniz equality or a declared reflexive relation
when resolving [ProperProxy], otherwise, if the relation is given (not an evar),
we fall back to [Proper]. *)
Hint Extern 1 (ProperProxy _ _) =>
class_apply @eq_proper_proxy || class_apply @reflexive_proper_proxy : typeclass_instances.
Hint Extern 2 (ProperProxy ?R _) =>
not_evar R; class_apply @proper_proper_proxy : typeclass_instances.
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Declare Scope signature_scope.
Delimit Scope signature_scope with signature.
Module ProperNotations.
Notation " R ++> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R ==> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R --> R' " := (@respectful _ _ (flip (R%signature)) (R'%signature))
(right associativity, at level 55) : signature_scope.
End ProperNotations.
Arguments Proper {A}%type R%signature m.
Arguments respectful {A B}%type (R R')%signature _ _.
Export ProperNotations.
Local Open Scope signature_scope.
(** [solve_proper] try to solve the goal [Proper (?==> ... ==>?) f]
by repeated introductions and setoid rewrites. It should work
fine when [f] is a combination of already known morphisms and
quantifiers. *)
Ltac solve_respectful t :=
match goal with
| |- respectful _ _ _ _ =>
let H := fresh "H" in
intros ? ? H; solve_respectful ltac:(setoid_rewrite H; t)
| _ => t; reflexivity
end.
Ltac solve_proper := unfold Proper; solve_respectful ltac:(idtac).
(** [f_equiv] is a clone of [f_equal] that handles setoid equivalences.
For example, if we know that [f] is a morphism for [E1==>E2==>E],
then the goal [E (f x y) (f x' y')] will be transformed by [f_equiv]
into the subgoals [E1 x x'] and [E2 y y'].
*)
Ltac f_equiv :=
match goal with
| |- ?R (?f ?x) (?f' _) =>
let T := type of x in
let Rx := fresh "R" in
evar (Rx : relation T);
let H := fresh in
assert (H : (Rx==>R)%signature f f');
unfold Rx in *; clear Rx; [ f_equiv | apply H; clear H; try reflexivity ]
| |- ?R ?f ?f' =>
solve [change (Proper R f); eauto with typeclass_instances | reflexivity ]
| _ => idtac
end.
Section Relations.
Let U := Type.
Context {A B : U} (P : A -> U).
(** [forall_def] reifies the dependent product as a definition. *)
Definition forall_def : Type := forall x : A, P x.
(** Dependent pointwise lifting of a relation on the range. *)
Definition forall_relation
(sig : forall a, relation (P a)) : relation (forall x, P x) :=
fun f g => forall a, sig a (f a) (g a).
(** Non-dependent pointwise lifting *)
Definition pointwise_relation (R : relation B) : relation (A -> B) :=
fun f g => forall a, R (f a) (g a).
Lemma pointwise_pointwise (R : relation B) :
relation_equivalence (pointwise_relation R) (@eq A ==> R).
Proof. intros. split; reduce; subst; firstorder. Qed.
(** Subrelations induce a morphism on the identity. *)
Global Instance subrelation_id_proper `(subrelation A RA RA') : Proper (RA ==> RA') id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Lemma subrelation_respectful `(subl : subrelation A RA' RA, subr : subrelation B RB RB') :
subrelation (RA ==> RB) (RA' ==> RB').
Proof. unfold subrelation in *; firstorder. Qed.
(** And of course it is reflexive. *)
Lemma subrelation_refl R : @subrelation A R R.
Proof. unfold subrelation; firstorder. Qed.
(** [Proper] is itself a covariant morphism for [subrelation].
We use an unconvertible premise to avoid looping.
*)
Lemma subrelation_proper `(mor : Proper A R' m)
`(unc : Unconvertible (relation A) R R')
`(sub : subrelation A R' R) : Proper R m.
Proof.
intros. apply sub. apply mor.
Qed.
Global Instance proper_subrelation_proper :
Proper (subrelation ++> eq ==> impl) (@Proper A).
Proof. reduce. subst. firstorder. Qed.
Global Instance pointwise_subrelation `(sub : subrelation B R R') :
subrelation (pointwise_relation R) (pointwise_relation R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. apply H. Qed.
(** For dependent function types. *)
Lemma forall_subrelation (R S : forall x : A, relation (P x)) :
(forall a, subrelation (R a) (S a)) -> subrelation (forall_relation R) (forall_relation S).
Proof. reduce. apply H. apply H0. Qed.
End Relations.
Typeclasses Opaque respectful pointwise_relation forall_relation.
Arguments forall_relation {A P}%type sig%signature _ _.
Arguments pointwise_relation A%type {B}%type R%signature _ _.
Hint Unfold Reflexive : core.
Hint Unfold Symmetric : core.
Hint Unfold Transitive : core.
(** Resolution with subrelation: favor decomposing products over applying reflexivity
for unconstrained goals. *)
Ltac subrelation_tac T U :=
(is_ground T ; is_ground U ; class_apply @subrelation_refl) ||
class_apply @subrelation_respectful || class_apply @subrelation_refl.
Hint Extern 3 (@subrelation _ ?T ?U) => subrelation_tac T U : typeclass_instances.
CoInductive apply_subrelation : Prop := do_subrelation.
Ltac proper_subrelation :=
match goal with
[ H : apply_subrelation |- _ ] => clear H ; class_apply @subrelation_proper
end.
Hint Extern 5 (@Proper _ ?H _) => proper_subrelation : typeclass_instances.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
Instance iff_impl_subrelation : subrelation iff impl | 2.
Proof. firstorder. Qed.
Instance iff_flip_impl_subrelation : subrelation iff (flip impl) | 2.
Proof. firstorder. Qed.
(** We use an extern hint to help unification. *)
Hint Extern 4 (subrelation (@forall_relation ?A ?B ?R) (@forall_relation _ _ ?S)) =>
apply (@forall_subrelation A B R S) ; intro : typeclass_instances.
Section GenericInstances.
(* Share universes *)
Let U := Type.
Context {A B C : U}.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Program Instance respectful_per `(PER A R, PER B R') : PER (R ==> R').
Next Obligation.
Proof with auto.
assert(R x0 x0).
transitivity y0... symmetry...
transitivity (y x0)...
Qed.
(** The complement of a relation conserves its proper elements. *)
Program Definition complement_proper
`(mR : Proper (A -> A -> Prop) (RA ==> RA ==> iff) R) :
Proper (RA ==> RA ==> iff) (complement R) := _.
Next Obligation.
Proof.
unfold complement.
pose (mR x y H x0 y0 H0).
intuition.
Qed.
(** The [flip] too, actually the [flip] instance is a bit more general. *)
Program Definition flip_proper
`(mor : Proper (A -> B -> C) (RA ==> RB ==> RC) f) :
Proper (RB ==> RA ==> RC) (flip f) := _.
Next Obligation.
Proof.
apply mor ; auto.
Qed.
(** Every Transitive relation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Global Program
Instance trans_contra_co_morphism
`(Transitive A R) : Proper (R --> R ++> impl) R.
Next Obligation.
Proof with auto.
transitivity x...
transitivity x0...
Qed.
(** Proper declarations for partial applications. *)
Global Program
Instance trans_contra_inv_impl_morphism
`(Transitive A R) : Proper (R --> flip impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
Global Program
Instance trans_co_impl_morphism
`(Transitive A R) : Proper (R ++> impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0...
Qed.
Global Program
Instance trans_sym_co_inv_impl_morphism
`(PER A R) : Proper (R ++> flip impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y... symmetry...
Qed.
Global Program Instance trans_sym_contra_impl_morphism
`(PER A R) : Proper (R --> impl) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0... symmetry...
Qed.
Global Program Instance per_partial_app_morphism
`(PER A R) : Proper (R ==> iff) (R x) | 2.
Next Obligation.
Proof with auto.
split. intros ; transitivity x0...
intros.
transitivity y...
symmetry...
Qed.
(** Every Transitive relation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof to get an [R y z] goal. *)
Global Program
Instance trans_co_eq_inv_impl_morphism
`(Transitive A R) : Proper (R ==> (@eq A) ==> flip impl) R | 2.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
(** Every Symmetric and Transitive relation gives rise to an equivariant morphism. *)
Global Program
Instance PER_morphism `(PER A R) : Proper (R ==> R ==> iff) R | 1.
Next Obligation.
Proof with auto.
split ; intros.
transitivity x0... transitivity x... symmetry...
transitivity y... transitivity y0... symmetry...
Qed.
Lemma symmetric_equiv_flip `(Symmetric A R) : relation_equivalence R (flip R).
Proof. firstorder. Qed.
Global Program Instance compose_proper RA RB RC :
Proper ((RB ==> RC) ==> (RA ==> RB) ==> (RA ==> RC)) (@compose A B C).
Next Obligation.
Proof.
simpl_relation.
unfold compose. apply H. apply H0. apply H1.
Qed.
(** Coq functions are morphisms for Leibniz equality,
applied only if really needed. *)
Global Instance reflexive_eq_dom_reflexive `(Reflexive B R') :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_relation. Qed.
(** [respectful] is a morphism for relation equivalence. *)
Global Instance respectful_morphism :
Proper (relation_equivalence ++> relation_equivalence ++> relation_equivalence)
(@respectful A B).
Proof.
reduce.
unfold respectful, relation_equivalence, predicate_equivalence in * ; simpl in *.
split ; intros.
rewrite <- H0.
apply H1.
rewrite H.
assumption.
rewrite H0.
apply H1.
rewrite <- H.
assumption.
Qed.
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism `(Proper (A -> B) (R ==> R') m, ProperProxy A R x) :
Proper R' (m x).
Proof. simpl_relation. Qed.
Lemma flip_respectful (R : relation A) (R' : relation B) :
relation_equivalence (flip (R ==> R')) (flip R ==> flip R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Treating flip: can't make them direct instances as we
need at least a [flip] present in the goal. *)
Lemma flip1 `(subrelation A R' R) : subrelation (flip (flip R')) R.
Proof. firstorder. Qed.
Lemma flip2 `(subrelation A R R') : subrelation R (flip (flip R')).
Proof. firstorder. Qed.
(** That's if and only if *)
Lemma eq_subrelation `(Reflexive A R) : subrelation (@eq A) R.
Proof. simpl_relation. Qed.
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Definition proper_flip_proper `(mor : Proper A R m) : Proper (flip R) m := mor.
(** Every reflexive relation gives rise to a morphism,
only for immediately solving goals without variables. *)
Lemma reflexive_proper `{Reflexive A R} (x : A) : Proper R x.
Proof. firstorder. Qed.
Lemma proper_eq (x : A) : Proper (@eq A) x.
Proof. intros. apply reflexive_proper. Qed.
End GenericInstances.
Class PartialApplication.
CoInductive normalization_done : Prop := did_normalization.
Class Params {A : Type} (of : A) (arity : nat).
Ltac partial_application_tactic :=
let rec do_partial_apps H m cont :=
match m with
| ?m' ?x => class_apply @Reflexive_partial_app_morphism ;
[(do_partial_apps H m' ltac:(idtac))|clear H]
| _ => cont
end
in
let rec do_partial H ar m :=
lazymatch ar with
| 0%nat => do_partial_apps H m ltac:(fail 1)
| S ?n' =>
match m with
?m' ?x => do_partial H n' m'
end
end
in
let params m sk fk :=
(let m' := fresh in head_of_constr m' m ;
let n := fresh in evar (n:nat) ;
let v := eval compute in n in clear n ;
let H := fresh in
assert(H:Params m' v) by (subst m'; once typeclasses eauto) ;
let v' := eval compute in v in subst m';
(sk H v' || fail 1))
|| fk
in
let on_morphism m cont :=
params m ltac:(fun H n => do_partial H n m)
ltac:(cont)
in
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : @Params _ _ _ |- _ ] => fail 1
| [ |- @Proper ?T _ (?m ?x) ] =>
match goal with
| [ H : PartialApplication |- _ ] =>
class_apply @Reflexive_partial_app_morphism; [|clear H]
| _ => on_morphism (m x)
ltac:(class_apply @Reflexive_partial_app_morphism)
end
end.
(** Bootstrap !!! *)
Instance proper_proper : Proper (relation_equivalence ==> eq ==> iff) (@Proper A).
Proof.
simpl_relation.
reduce in H.
split ; red ; intros.
setoid_rewrite <- H.
apply H0.
setoid_rewrite H.
apply H0.
Qed.
Ltac proper_reflexive :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| _ => class_apply proper_eq || class_apply @reflexive_proper
end.
Hint Extern 1 (subrelation (flip _) _) => class_apply @flip1 : typeclass_instances.
Hint Extern 1 (subrelation _ (flip _)) => class_apply @flip2 : typeclass_instances.
Hint Extern 1 (Proper _ (complement _)) => apply @complement_proper
: typeclass_instances.
Hint Extern 1 (Proper _ (flip _)) => apply @flip_proper
: typeclass_instances.
Hint Extern 2 (@Proper _ (flip _) _) => class_apply @proper_flip_proper
: typeclass_instances.
Hint Extern 4 (@Proper _ _ _) => partial_application_tactic
: typeclass_instances.
Hint Extern 7 (@Proper _ _ _) => proper_reflexive
: typeclass_instances.
(** Special-purpose class to do normalization of signatures w.r.t. flip. *)
Section Normalize.
Context (A : Type).
Class Normalizes (m : relation A) (m' : relation A) : Prop :=
normalizes : relation_equivalence m m'.
(** Current strategy: add [flip] everywhere and reduce using [subrelation]
afterwards. *)
Lemma proper_normalizes_proper `(Normalizes R0 R1, Proper A R1 m) : Proper R0 m.
Proof.
red in H, H0.
rewrite H.
assumption.
Qed.
Lemma flip_atom R : Normalizes R (flip (flip R)).
Proof.
firstorder.
Qed.
End Normalize.
Lemma flip_arrow {A : Type} {B : Type}
`(NA : Normalizes A R (flip R'''), NB : Normalizes B R' (flip R'')) :
Normalizes (A -> B) (R ==> R') (flip (R''' ==> R'')%signature).
Proof.
unfold Normalizes in *. intros.
unfold relation_equivalence in *.
unfold predicate_equivalence in *. simpl in *.
unfold respectful. unfold flip in *. firstorder.
apply NB. apply H. apply NA. apply H0.
apply NB. apply H. apply NA. apply H0.
Qed.
Ltac normalizes :=
match goal with
| [ |- Normalizes _ (respectful _ _) _ ] => class_apply @flip_arrow
| _ => class_apply @flip_atom
end.
Ltac proper_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : apply_subrelation |- @Proper _ ?R _ ] =>
let H := fresh "H" in
set(H:=did_normalization) ; class_apply @proper_normalizes_proper
end.
Hint Extern 1 (Normalizes _ _ _) => normalizes : typeclass_instances.
Hint Extern 6 (@Proper _ _ _) => proper_normalization
: typeclass_instances.
(** When the relation on the domain is symmetric, we can
flip the relation on the codomain. Same for binary functions. *)
Lemma proper_sym_flip :
forall `(Symmetric A R1)`(Proper (A->B) (R1==>R2) f),
Proper (R1==>flip R2) f.
Proof.
intros A R1 Sym B R2 f Hf.
intros x x' Hxx'. apply Hf, Sym, Hxx'.
Qed.
Lemma proper_sym_flip_2 :
forall `(Symmetric A R1)`(Symmetric B R2)`(Proper (A->B->C) (R1==>R2==>R3) f),
Proper (R1==>R2==>flip R3) f.
Proof.
intros A R1 Sym1 B R2 Sym2 C R3 f Hf.
intros x x' Hxx' y y' Hyy'. apply Hf; auto.
Qed.
(** When the relation on the domain is symmetric, a predicate is
compatible with [iff] as soon as it is compatible with [impl].
Same with a binary relation. *)
Lemma proper_sym_impl_iff : forall `(Symmetric A R)`(Proper _ (R==>impl) f),
Proper (R==>iff) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_impl_iff_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>impl) f),
Proper (R==>R'==>iff) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
(** A [PartialOrder] is compatible with its underlying equivalence. *)
Instance PartialOrder_proper `(PartialOrder A eqA R) :
Proper (eqA==>eqA==>iff) R.
Proof.
intros.
apply proper_sym_impl_iff_2; auto with *.
intros x x' Hx y y' Hy Hr.
transitivity x.
generalize (partial_order_equivalence x x'); compute; intuition.
transitivity y; auto.
generalize (partial_order_equivalence y y'); compute; intuition.
Qed.
(** From a [PartialOrder] to the corresponding [StrictOrder]:
[lt = le /\ ~eq].
If the order is total, we could also say [gt = ~le]. *)
Lemma PartialOrder_StrictOrder `(PartialOrder A eqA R) :
StrictOrder (relation_conjunction R (complement eqA)).
Proof.
split; compute.
intros x (_,Hx). apply Hx, Equivalence_Reflexive.
intros x y z (Hxy,Hxy') (Hyz,Hyz'). split.
apply PreOrder_Transitive with y; assumption.
intro Hxz.
apply Hxy'.
apply partial_order_antisym; auto.
rewrite Hxz; auto.
Qed.
(** From a [StrictOrder] to the corresponding [PartialOrder]:
[le = lt \/ eq].
If the order is total, we could also say [ge = ~lt]. *)
Lemma StrictOrder_PreOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iff) R) :
PreOrder (relation_disjunction R eqA).
Proof.
split.
intros x. right. reflexivity.
intros x y z [Hxy|Hxy] [Hyz|Hyz].
left. transitivity y; auto.
left. rewrite <- Hyz; auto.
left. rewrite Hxy; auto.
right. transitivity y; auto.
Qed.
Hint Extern 4 (PreOrder (relation_disjunction _ _)) =>
class_apply StrictOrder_PreOrder : typeclass_instances.
Lemma StrictOrder_PartialOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iff) R) :
PartialOrder eqA (relation_disjunction R eqA).
Proof.
intros. intros x y. compute. intuition.
elim (StrictOrder_Irreflexive x).
transitivity y; auto.
Qed.
Hint Extern 4 (StrictOrder (relation_conjunction _ _)) =>
class_apply PartialOrder_StrictOrder : typeclass_instances.
Hint Extern 4 (PartialOrder _ (relation_disjunction _ _)) =>
class_apply StrictOrder_PartialOrder : typeclass_instances.
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1423170505 : 0;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Loop_loop_height_ibs_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_ibs_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_ibs(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
Loop_loop_height_ibs_rom Loop_loop_height_ibs_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_1_V
`define SKY130_FD_SC_HDLL__O21A_1_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21a_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21a_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$PS_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
|
/**
* tb_draw_fifo.v: test bench for draw fifo
*/
module tb_draw_fifo;
localparam STEP = 2;
localparam REG_FIFO = 32'h0;
localparam REG_STATUS = 32'h4;
wire [15:0] x1, y1, x2, y2, x3, c1, c2, c3;
wire ap_rstn, ap_start;
reg ap_done;
wire ap_idle;
reg ap_clk;
reg s00_axi_aclk;
reg s00_axi_aresetn;
reg [2:0] s00_axi_awaddr;
reg [2:0] s00_axi_awprot = 3'h0;
reg s00_axi_awvalid;
wire s00_axi_awready;
reg [31:0] s00_axi_wdata;
reg [3:0] s00_axi_wstrb = 4'b1111;
reg s00_axi_wvalid;
wire s00_axi_wready;
wire [1:0] s00_axi_bresp;
wire s00_axi_bvalid;
reg s00_axi_bready;
reg [2:0] s00_axi_araddr;
reg [2:0] s00_axi_arprot = 3'h0;
reg s00_axi_arvalid;
wire s00_axi_arready;
wire [2:0] s00_axi_rdata;
wire [1:0] s00_axi_rresp;
wire s00_axi_rvalid;
reg s00_axi_rready;
reg [31:0] rdata = 32'h0;
reg [4:0] done_count = 5'd0;
reg ap_start_diff = 'b0;
reg [4:0] counter_start = 5'd30;
// connect to the draw fifo
draw_fifo_v1_0 draw_fifo_v1_0 (
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.x3(x3),
.c1(c1),
.c2(c2),
.c3(c3),
.ap_rstn(ap_rstn),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_ready(ap_done),
.ap_idle(ap_idle),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
// task for writing data
task write_data;
input [31:0] awaddr;
input [31:0] wdata;
begin
s00_axi_awaddr <= awaddr;
s00_axi_wdata <= wdata;
s00_axi_bready <= 'b0;
#(STEP);
s00_axi_awvalid <= 'b1;
s00_axi_wvalid <= 'b1;
#(STEP);
while (s00_axi_bvalid == 'b0) begin
#(STEP);
end
s00_axi_bready <= 'b1;
s00_axi_awvalid <= 'b0;
s00_axi_wvalid <= 'b0;
#(STEP)
s00_axi_bready <= 'b0;
end
endtask
// task for reading data
task read_data;
input [31:0] araddr;
begin
s00_axi_araddr = araddr;
s00_axi_rready <= 'b0;
#(STEP);
s00_axi_arvalid <= 'b1;
while (s00_axi_rvalid == 'b0) begin
#(STEP);
end
s00_axi_rready <= 'b1;
rdata = s00_axi_rdata;
#(STEP);
s00_axi_arvalid <= 'b0;
s00_axi_rready <= 'b0;
end
endtask
always @(posedge s00_axi_aclk) begin
ap_start_diff <= ap_start;
end
// mimic the end of the draw engine task
always @(posedge s00_axi_aclk) begin
if (~s00_axi_aresetn) begin
ap_done <= 'b0;
end
else if (~ap_done && ap_start && done_count == 5'd1) begin
ap_done <= 'b1;
end
else begin
ap_done <= 'b0;
end
end
always @(posedge s00_axi_aclk) begin
if (~s00_axi_aresetn)
done_count <= counter_start;
else if (ap_done && ap_start)
done_count <= counter_start;
else if (ap_start && ~ap_start_diff)
done_count <= counter_start;
else if (ap_start)
done_count <= (done_count == 5'd0) ? 5'd0 : (done_count - 5'd1);
else
done_count <= done_count;
end
assign ap_idle = ~ap_start && ~ap_done;
// clocks
always begin
s00_axi_aclk <= 'b0;
#(STEP / 2);
s00_axi_aclk = 'b1;
#(STEP / 2);
end
// start simulation
initial begin
s00_axi_aresetn <= 'b0;
counter_start <= 5'd30;
#(STEP * 2);
s00_axi_aresetn <= 'b1;
#(STEP * 2);
// wake up the engine
write_data(REG_STATUS, 32'h80000000);
#(STEP * 2);
// write 15 test data
write_data(REG_FIFO, 32'h00020001);
write_data(REG_FIFO, 32'h00040003);
write_data(REG_FIFO, 32'h00060005);
write_data(REG_FIFO, 32'h00080007);
write_data(REG_FIFO, 32'h00120011);
write_data(REG_FIFO, 32'h00140013);
write_data(REG_FIFO, 32'h00160015);
write_data(REG_FIFO, 32'h00180017);
write_data(REG_FIFO, 32'h00220021);
write_data(REG_FIFO, 32'h00240023);
write_data(REG_FIFO, 32'h00260025);
write_data(REG_FIFO, 32'h00280027);
write_data(REG_FIFO, 32'h00320031);
write_data(REG_FIFO, 32'h00340033);
write_data(REG_FIFO, 32'h00360035);
write_data(REG_FIFO, 32'h00380037);
write_data(REG_FIFO, 32'h00520051);
write_data(REG_FIFO, 32'h00540053);
write_data(REG_FIFO, 32'h00560055);
write_data(REG_FIFO, 32'h00580057);
#(STEP * 40);
write_data(REG_FIFO, 32'h00620061);
write_data(REG_FIFO, 32'h00640063);
write_data(REG_FIFO, 32'h00660065);
#(STEP * 10);
write_data(REG_FIFO, 32'h00680067);
counter_start <= 5'd1;
write_data(REG_FIFO, 32'h00820081);
write_data(REG_FIFO, 32'h00840083);
write_data(REG_FIFO, 32'h00860085);
write_data(REG_FIFO, 32'h00880087);
write_data(REG_FIFO, 32'h00920091);
write_data(REG_FIFO, 32'h00940093);
write_data(REG_FIFO, 32'h00960095);
write_data(REG_FIFO, 32'h00980097);
write_data(REG_FIFO, 32'h00a200a1);
write_data(REG_FIFO, 32'h00a400a3);
write_data(REG_FIFO, 32'h00a600a5);
write_data(REG_FIFO, 32'h00a800a7);
write_data(REG_FIFO, 32'h00b200b1);
write_data(REG_FIFO, 32'h00b400b3);
write_data(REG_FIFO, 32'h00b600b5);
write_data(REG_FIFO, 32'h00b800b7);
// wait fifo_next asserts
#(STEP * 20 * 4);
read_data(REG_FIFO);
// end of the simulation
$stop;
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_uart_transceiver_0_0_stub.v
// Design : DemoInterconnect_uart_transceiver_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "uart_top,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(i_Clk, i_RX_Serial, o_RX_Done, o_RX_Byte,
i_TX_Load, i_TX_Byte, o_TX_Active, o_TX_Serial, o_TX_Done)
/* synthesis syn_black_box black_box_pad_pin="i_Clk,i_RX_Serial,o_RX_Done,o_RX_Byte[7:0],i_TX_Load,i_TX_Byte[7:0],o_TX_Active,o_TX_Serial,o_TX_Done" */;
input i_Clk;
input i_RX_Serial;
output o_RX_Done;
output [7:0]o_RX_Byte;
input i_TX_Load;
input [7:0]i_TX_Byte;
output o_TX_Active;
output o_TX_Serial;
output o_TX_Done;
endmodule
|
/* Cross Clock Test Bench Module
*
* Case I:
* Tests the FIFO by writing the FF byte and reading them back.
*
* Created By David Tran
* Version 0.1.0.0
* Last Modified:05-03-2014
*/
`include "crossclock.v"
module crossclock_tb(
readMode, // Specifies if we want to read to the FIFO
writeMode, // Specifies if we want to write to the FIFO
inputPacket // The input packet
);
parameter bits = 8;
output readMode, writeMode;
reg readMode, writeMode;
output [bits-1:0] inputPacket;
reg [bits-1:0] inputPacket;
reg clkA, clkB, rst;
output [bits-1:0] outputPacket;
wire [bits-1:0] outputPacket;
reg writeEnable;
crossclock FIFO(.wrEnable(writeEnable),
.inputData(inputPacket),
.outputData(outputPacket),
.clkA(clkA),
.clkB(clkB),
.rst(rst)
);
initial
begin
clkA=0;
forever #5 clkA=~clkA;
end
initial
begin
clkB=0;
forever #7 clkB=~clkB;
end
initial
begin
forever begin
@(posedge clkA or posedge clkB); begin // Only output on positive edge
$display("time=%04d RWE=%b%b%b I=%h O=%h clkA=%b clkB=%b", $time,
readMode, writeMode, writeEnable, inputPacket, outputPacket, clkA, clkB);
end
end
end
initial
begin
// Test Case I: Write to capacity and empty
$display("Resetting cross clock FIFO");
rst = 1;
writeEnable = 0;
readMode = 0;
writeMode = 0;
inputPacket = {length{1'b0}};
#20 rst = 0;
#40
#20 writeEnable = 1; writeMode = 1; inputPacket = {length{1'b1}};
$display("Writing");
#80 writeEnable = 0; writeMode = 0; readMode = 1; inputPacket = {bits{1'b0}};
$display("Reading");
#80 readMode = 0;
if (outputPacket === {bits{1'b1}}) begin
$display("Pass");
end else begin
$display("Fail");
end
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__XOR2_FUNCTIONAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/26/2016 08:52:29 AM
// Design Name:
// Module Name: Problem1Integrated
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Pardon the Name haha
module Problem1Integrated(
input [7:0] Input_A,
input [7:0] Input_B,
output GT,
output LT,
output EQ
);
wire part1Wire1, part1Wire2, part1Wire3; // wire1 is GT, 2 IS LT, ansd 3 is EQ
wire part2Wire1, part2Wire2, part2Wire3;
wire part3Wire1, part3Wire2, part3Wire3;
wire part4Wire1, part4Wire2, part4Wire3;
wire part5Wire1, part5Wire2, part5Wire3;
wire part6Wire1, part6Wire2, part6Wire3;
wire part7Wire1, part7Wire2, part7Wire3;
// superflous... wire part8Wire1, part8Wire2, part8Wire3;
Problem4 Part1(
.A(Input_A[0]),
.B(Input_B[0]),
.GTI(0), // Initial O
.LTI(0), // Initial 0
.EQI(1), // Initial 1
.GTO(part1Wire1),
.LTO(part1Wire2),
.EQO(part1Wire3)
);
Problem4 Part2(
.A(Input_A[1]),
.B(Input_B[1]),
.GTI(part1Wire1),
.LTI(part1Wire2),
.EQI(part1Wire3),
.GTO(part2Wire1),
.LTO(part2Wire2),
.EQO(part2Wire3)
);
Problem4 Part3(
.A(Input_A[2]),
.B(Input_B[2]),
.GTI(part2Wire1),
.LTI(part2Wire2),
.EQI(part2Wire3),
.GTO(part3Wire1),
.LTO(part3Wire2),
.EQO(part3Wire3)
);
Problem4 Part4(
.A(Input_A[3]),
.B(Input_B[3]),
.GTI(part3Wire1),
.LTI(part3Wire2),
.EQI(part3Wire3),
.GTO(part4Wire1),
.LTO(part4Wire2),
.EQO(part4Wire3)
);
Problem4 Part5(
.A(Input_A[4]),
.B(Input_B[4]),
.GTI(part4Wire1),
.LTI(part4Wire2),
.EQI(part4Wire3),
.GTO(part5Wire1),
.LTO(part5Wire2),
.EQO(part5Wire3)
);
Problem4 Part6(
.A(Input_A[5]),
.B(Input_B[5]),
.GTI(part5Wire1),
.LTI(part5Wire2),
.EQI(part5Wire3),
.GTO(part6Wire1),
.LTO(part6Wire2),
.EQO(part6Wire3)
);
Problem4 Part7(
.A(Input_A[6]),
.B(Input_B[6]),
.GTI(part6Wire1),
.LTI(part6Wire2),
.EQI(part6Wire3),
.GTO(part7Wire1),
.LTO(part7Wire2),
.EQO(part7Wire3)
);
Problem4 Part8(
.A(Input_A[7]),
.B(Input_B[7]),
.GTI(part7Wire1),
.LTI(part7Wire2),
.EQI(part7Wire3),
.GTO(GT),
.LTO(LT),
.EQO(EQ)
);
endmodule
|
// **************************************************************************
// $Header: /var/lib/cvs/dncvs/FPGA/dini/misc/resync.v,v 1.7 2015/04/07 22:03:42 bpoladian Exp $
// **************************************************************************
// $Log: resync.v,v $
// Revision 1.7 2015/04/07 22:03:42 bpoladian
// Only stop simulation on first warning.
//
// Revision 1.6 2015/04/06 23:58:10 bpoladian
// Resync reset to read clock domain.
//
// Revision 1.5 2013/05/20 17:39:36 claudiug
// added ALLOW_FAST_WRITE_PULSE parameter, disabled by default. Should not change old behavior.
//
// Revision 1.4 2013/03/07 23:10:37 bpoladian
// Fixed typo.
//
// Revision 1.3 2013/03/07 23:07:10 bpoladian
// Added simulation error about asserting wr_pulse too often.
//
// Revision 1.2 2010/11/17 20:41:05 bpoladian
// Syntax fix.
//
// Revision 1.1 2010/11/17 20:03:42 bpoladian
// Initial revision.
//
//
// Description:
// Transfers a group of signals from one clock domain into another.
// The transfer operation is triggered by a "wr_pulse", and data is
// valid on the other side when "rd_pulse" goes active.
// **************************************************************************
`ifdef INCL_RESYNC
`else
`define INCL_RESYNC
module resync #(
parameter DATA_SIZE = 32,
parameter ALLOW_FAST_WRITE_PULSE = 0
)(
input rst,
input wr_clk,
input wr_pulse,
input [DATA_SIZE-1:0] wr_data,
input rd_clk,
output reg rd_pulse,
output reg [DATA_SIZE-1:0] rd_data
);
// **********************************************************************
// REG AND WIRE DECLARATIONS
// **********************************************************************
reg [DATA_SIZE-1:0] data_wrclk;
reg toggle_wr;
reg toggle_return_wr_meta;
reg toggle_return_wr0;
reg toggle_rd_meta;
reg toggle_rd0;
reg toggle_rd1;
// **********************************************************************
// WRITE CLOCK DOMAIN DATA CAPTURE
// **********************************************************************
// synthesis translate_off
reg stop_once;
initial begin
stop_once = 0;
end
// synthesis translate_on
always @(posedge wr_clk or posedge rst) begin
if (rst) begin
toggle_wr <= 1'b0;
toggle_return_wr_meta <= 1'b0;
toggle_return_wr0 <= 1'b0;
data_wrclk[DATA_SIZE-1:0] <= 'h0;
end else begin
toggle_wr <= ALLOW_FAST_WRITE_PULSE ? toggle_wr ^ (wr_pulse & (toggle_wr ^ ~toggle_return_wr0)) : toggle_wr ^ wr_pulse;
toggle_return_wr_meta <= toggle_rd0;
toggle_return_wr0 <= toggle_return_wr_meta;
if (wr_pulse) begin
data_wrclk[DATA_SIZE-1:0] <= wr_data[DATA_SIZE-1:0];
end
// synthesis translate_off
if(wr_pulse & (ALLOW_FAST_WRITE_PULSE ? (toggle_wr ^ ~toggle_return_wr0) : 1'b1) & (toggle_wr ^ toggle_rd1)) begin
$display("%t: %m: ERROR: wr_pulse too early to guarantee safe clock domain crossing!", $realtime);
if(!stop_once) begin
stop_once = 1;
$stop;
end
end
// synthesis translate_on
end
end
// **********************************************************************
// READ CLOCK DOMAIN DATA TRANSFER
// **********************************************************************
wire rd_rst;
reset_resync i_reset_resync (
.rst_in (rst),
.clk_in (wr_clk),
.clk_out (rd_clk),
.rst_out (rd_rst)
);
always @(posedge rd_clk or posedge rd_rst) begin
if (rd_rst) begin
toggle_rd_meta <= 1'b0;
toggle_rd0 <= 1'b0;
toggle_rd1 <= 1'b0;
rd_pulse <= 1'b0;
rd_data <= {DATA_SIZE{1'b0}};
end else begin
toggle_rd_meta <= toggle_wr;
toggle_rd0 <= toggle_rd_meta;
toggle_rd1 <= toggle_rd0;
rd_pulse <= toggle_rd0 ^ toggle_rd1;
if (toggle_rd0 ^ toggle_rd1) begin
rd_data[DATA_SIZE-1:0] <= data_wrclk[DATA_SIZE-1:0];
end
end
end
endmodule
`endif
|
//======================================================================
//
// tb_blake2_core.v
// ----------------
// Testbench for the Blake2 core.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_blake2_core();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DISPLAY_STATE = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_display_state;
reg tb_init;
reg tb_next_block;
reg tb_final_block;
reg [1023 : 0] tb_block;
reg [7 : 0] tb_key_len;
reg [7 : 0] tb_digest_len;
wire tb_ready;
wire [511 : 0] tb_digest;
wire tb_digest_valid;
//----------------------------------------------------------------
// blake2_core devices under test.
//----------------------------------------------------------------
blake2_core dut (
.clk(tb_clk),
.reset_n(tb_reset_n),
.init(tb_init),
.next_block(tb_next_block),
.final_block(tb_final_block),
.key_len(tb_key_len),
.digest_len(tb_digest_len),
.block(tb_block),
.ready(tb_ready),
.digest(tb_digest),
.digest_valid(tb_digest_valid)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// reset_dut
//----------------------------------------------------------------
task reset_dut;
begin
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// inc_tc_ctr()
//----------------------------------------------------------------
task inc_tc_ctr;
begin
tc_ctr = tc_ctr + 1;
end
endtask // inc_tc_ctr
//----------------------------------------------------------------
// inc_error_ctr()
//----------------------------------------------------------------
task inc_error_ctr;
begin
error_ctr = error_ctr + 1;
end
endtask // inc_error_ctr
//----------------------------------------------------------------
// enable_display_state()
//----------------------------------------------------------------
task enable_display_state;
begin
tb_display_state = 1;
end
endtask // enable_display_state
//----------------------------------------------------------------
// disable_display_state()
//----------------------------------------------------------------
task disable_display_state;
begin
tb_display_state = 0;
end
endtask // disable_display_state
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (tb_display_state)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// dump_dut_state()
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("Counters and control state::");
$display("blake2_ctrl_reg = 0x%02x round_ctr_reg = 0x%02x ready = 0x%01x valid = 0x%01x",
dut.blake2_ctrl_reg, dut.round_ctr_reg, tb_ready, tb_digest_valid);
$display("");
$display("Chaining value:");
$display("h[0] = 0x%016x h[1] = 0x%016x h[2] = 0x%016x h[3] = 0x%016x",
dut.h_reg[0], dut.h_reg[1], dut.h_reg[2], dut.h_reg[3]);
$display("h[4] = 0x%016x h[5] = 0x%016x h[6] = 0x%016x h[7] = 0x%016x",
dut.h_reg[4], dut.h_reg[5], dut.h_reg[6], dut.h_reg[7]);
$display("");
$display("Internal state:");
$display("v[00] = 0x%016x v[01] = 0x%016x v[02] = 0x%016x v[03] = 0x%016x",
dut.v_reg[0], dut.v_reg[1], dut.v_reg[2], dut.v_reg[3]);
$display("v[04] = 0x%016x v[05] = 0x%016x v[06] = 0x%016x v[07] = 0x%016x",
dut.v_reg[4], dut.v_reg[5], dut.v_reg[6], dut.v_reg[7]);
$display("v[08] = 0x%016x v[09] = 0x%016x v[10] = 0x%016x v[11] = 0x%016x",
dut.v_reg[8], dut.v_reg[9], dut.v_reg[10], dut.v_reg[11]);
$display("v[12] = 0x%016x v[13] = 0x%016x v[14] = 0x%016x v[15] = 0x%016x",
dut.v_reg[12], dut.v_reg[13], dut.v_reg[14], dut.v_reg[15]);
$display("");
$display("Message block:");
$display("m[00] = 0x%016x m[01] = 0x%016x m[02] = 0x%016x m[03] = 0x%016x",
dut.mselect.m_reg[0], dut.mselect.m_reg[1],
dut.mselect.m_reg[2], dut.mselect.m_reg[3]);
$display("m[04] = 0x%016x m[05] = 0x%016x m[06] = 0x%016x m[07] = 0x%016x",
dut.mselect.m_reg[4], dut.mselect.m_reg[5],
dut.mselect.m_reg[6], dut.mselect.m_reg[7]);
$display("m[08] = 0x%016x m[09] = 0x%016x m[10] = 0x%016x m[11] = 0x%016x",
dut.mselect.m_reg[8], dut.mselect.m_reg[9],
dut.mselect.m_reg[10], dut.mselect.m_reg[11]);
$display("m[12] = 0x%016x m[13] = 0x%016x m[14] = 0x%016x m[15] = 0x%016x",
dut.mselect.m_reg[12], dut.mselect.m_reg[13],
dut.mselect.m_reg[14], dut.mselect.m_reg[15]);
$display("");
end
endtask // dump_state
//----------------------------------------------------------------
// init()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_display_state = 0;
tb_init = 0;
tb_next_block = 0;
tb_final_block = 0;
tb_key_len = 8'h0;
tb_digest_len = 8'h0;
tb_block = 1024'h0;
end
endtask // init
//----------------------------------------------------------------
// test_rfc
// Single block test with the message "abc" as described in
// RFC 6793, Appendix A.
//----------------------------------------------------------------
task test_rfc;
begin
$display("*** TEST_RFC started.");
inc_tc_ctr();
enable_display_state();
tb_key_len = 8'h0;
tb_digest_len = 8'h40;
tb_init = 1;
#(2 * CLK_PERIOD);
tb_init = 0;
tb_block = {24'h616263, 1000'h0};
tb_next_block = 1;
tb_final_block = 1;
#(2 * CLK_PERIOD);
tb_next_block = 0;
tb_final_block = 0;
#(100 * CLK_PERIOD);
disable_display_state();
$display("*** TEST_RFC done.");
end
endtask // test_wiki
//----------------------------------------------------------------
// test_core_init
//
// Verify that the chaining vector is correctly initialized
// based on given key and digest sizes.
//----------------------------------------------------------------
task test_core_init;
begin : test_init
integer errors;
errors = 0;
$display("*** TEST_CORE_INIT started. This should initialize the h_regs.");
inc_tc_ctr();
enable_display_state();
tb_key_len = 8'h0;
tb_digest_len = 8'h40;
tb_display_state = 1;
tb_init = 1;
#(2 * CLK_PERIOD);
tb_init = 0;
#(2 * CLK_PERIOD);
if (dut.h_reg[0] != 64'h6a09e667f2bdc948)
errors = errors + 1;
if (dut.h_reg[1] != 64'hbb67ae8584caa73b)
errors = errors + 1;
if (dut.h_reg[2] != 64'h3c6ef372fe94f82b)
errors = errors + 1;
if (dut.h_reg[3] != 64'ha54ff53a5f1d36f1)
errors = errors + 1;
if (dut.h_reg[4] != 64'h510e527fade682d1)
errors = errors + 1;
if (dut.h_reg[5] != 64'h9b05688c2b3e6c1f)
errors = errors + 1;
if (dut.h_reg[6] != 64'h1f83d9abfb41bd6b)
errors = errors + 1;
if (dut.h_reg[7] != 64'h5be0cd19137e2179)
errors = errors + 1;
if (errors > 0)
begin
inc_error_ctr();
$display("*** TEST_CORE_INIT: ERROR. %01d values are wrong.", errors);
end
disable_display_state();
$display("*** TEST_CORE_INIT done.");
end
endtask // test_core_init
//----------------------------------------------------------------
// blake2_core_test
//----------------------------------------------------------------
initial
begin : blake2_core_test
$display("*** Testbench for blake2_core started.");
init();
reset_dut();
// test_core_init();
test_rfc();
display_test_result();
$display("*** blake2_core simulation done.");
$finish_and_return(error_ctr);
end // blake2_core_test
endmodule // tb_blake2_core
//======================================================================
// EOF tb_blake2_core.v
//======================================================================
|
// MBT 8/27/14
//
// FPGA calibration module (example, only implements Phase 1 and dummy Phase 0,2,3)
//
// See BSG Source Synchronous I/O for specification of this.
//
// everything beginning with "out" is the output channel clock
// everything beginning with "in" is the input channel clock
//
// respect the clock domains!
//
// tests_lp defines the number of real tests; but we have one more "fake"
// test at the end, which causes activation or deactivation of the channel
//
//
`include "bsg_defines.v"
module bsg_source_sync_channel_control_master #(parameter `BSG_INV_PARAM( width_p )
, parameter lg_token_width_p = 6
, parameter lg_out_prepare_hold_cycles_p = 6
// bit vector
, parameter bypass_test_p = 5'b0
, parameter tests_lp = 5
, parameter verbose_lp = 1
)
(// output channel
input out_clk_i
, input out_reset_i // note this is just a synchronized version of core_reset
// we can do calibration in parallel, or channel-by-channel
, input [$clog2(tests_lp+1)-1:0] out_calibration_state_i
// whether we are in the "prepare" part of the state, or the "go" part
// the prepare corresponds to reset being asserted to the slave device
, input out_calib_prepare_i
// this is for the final test, and means that the channel is "blessed"
// i.e. ready to use
, input out_channel_blessed_i
// this is used to force data on to the output channel
// (calibration modes 0 and 1)
, output out_override_en_o
, output [width_p+1-1:0] out_override_valid_data_o
, input out_override_is_posedge_i
// whether the test passed
, output [tests_lp+1-1:0] out_test_pass_r_o
// read the input channel
, input in_clk_i // for sampling the data below
, input in_reset_i // just a synchronized version of core_reset
// negative edge snoop (precedes positive edge in time)
, input [width_p+1-1:0] in_snoop_valid_data_neg_i
// positive edge snoop
, input [width_p+1-1:0] in_snoop_valid_data_pos_i
// AWC: fixme should be out_infinite_credits_o
// basically disable the output module from looking
// at the credit counters
//, output in_infinite_credits_o
, output out_infinite_credits_o
);
// 24 is 16M cycles
localparam counter_min_bits_lp = 24;
localparam counter_bits_lp = `BSG_MAX(counter_min_bits_lp,(width_p+1)*2+1);
logic [counter_bits_lp-1:0] out_ctr_r, out_ctr_n;
logic [width_p+1-1:0] out_override_valid_data_r, out_override_valid_data_n;
logic out_override_en_r, out_override_en_n;
logic out_calib_prepare_i_r;
logic [tests_lp+1-1:0] out_test_pass_r, out_test_pass_n;
// fill pattern with at least as many 10's to fill width_p bits
// having defaults be 10101 reduces electromigration on pads
wire [(((width_p+1)>>1)<<1)-1:0] inactive_pattern
= { ((width_p+1) >> 1) { (2'b01) } };
// we don't strictly need to register this
// as it is registered in the source synchronous output module
// however, this is a non-latency critical path it seems reasonable
// to add an extra flop.
assign out_override_valid_data_o = out_override_valid_data_r;
assign out_override_en_o = out_override_en_r;
assign out_test_pass_r_o = out_test_pass_r[tests_lp:0];
logic [4:0] out_calib_code;
logic out_activating;
// these codes have been chosen very exhaustively
// with consideration to stuck-at faults.
// please do not change them -- mbt
// note; when width_p=3, then only even numbered
// codes will run on the slave device
always_comb
begin
out_activating = 1'b0;
unique case (out_calibration_state_i)
0: out_calib_code = 5'b0_111_1; // reset clk
// phase 1 and 2 are "noisy"
// so keep hamming distance from sActive high
1: out_calib_code = 5'b0_010_0; // Phase 1
2: out_calib_code = 5'b0_010_1; // Phase 2
3: out_calib_code = 5'b0_001_0; // Phase 3
4: out_calib_code = 5'b0_001_1; // Phase 4
tests_lp:
begin
out_calib_code = out_channel_blessed_i
? (5'b0_011_0) // corresponds to channel activated
// --> do prepare part of this state
: (5'b0_100_1); // channel NOT activated (also 0_011_1)
// this pattern should be maximally
// different from active pattern so
// that stuck-at faults do not cause
// accidental activation after the final
// reset.
out_activating = out_channel_blessed_i;
end
default: out_calib_code = 5'b0_000_1; // includes sInactive
endcase
end // always_comb
wire [width_p+1-1:0] out_calib_code_padded;
if (width_p <= 4)
assign out_calib_code_padded = out_calib_code[($bits(out_calib_code)-1)-:(1+width_p)];
else
// we invert the extra bits if we are activating
assign out_calib_code_padded
= { out_calib_code
, inactive_pattern[width_p+1-$bits(out_calib_code)-1:0]
^ { (width_p+1-$bits(out_calib_code)) { out_activating } }
};
logic out_finish_prepare_r, out_finish_prepare_n;
always_ff @(posedge out_clk_i)
begin
out_calib_prepare_i_r <= out_calib_prepare_i;
if (out_reset_i)
out_test_pass_r <= bypass_test_p; // 5/1/17 mbt:temporary fix to accelerate simulation
else
out_test_pass_r <= out_test_pass_n;
out_finish_prepare_r <= out_finish_prepare_n;
// zero the counter on prepare assertion and deassertion
if (out_calib_prepare_i ^ out_calib_prepare_i_r)
out_ctr_r <= counter_bits_lp ' (0);
else
out_ctr_r <= out_ctr_n;
out_override_valid_data_r <= out_override_valid_data_n;
out_override_en_r <= out_override_en_n;
if (verbose_lp)
if ((out_reset_i === 0) & (out_calib_prepare_i !== 'X) & (out_calib_prepare_i ^ out_calib_prepare_i_r))
$display("## Master %m: %s prepare part for Phase %1d (out_calib_prepare_i = %b, out_calib_prepare_i_r = %b)"
, out_calib_prepare_i ? "entering" : "exiting"
, out_calibration_state_i
, out_calib_prepare_i
, out_calib_prepare_i_r
);
end
wire [counter_bits_lp-1:0] out_ctr_r_p1 = out_ctr_r + 1'b1;
wire [tests_lp+1-1:0] out_phase_X_good;
always_comb
begin
out_finish_prepare_n = out_reset_i ? 0: out_finish_prepare_r;
out_ctr_n = out_reset_i ? 0: out_ctr_r;
out_test_pass_n = out_test_pass_r;
out_override_en_n = 1'b0;
out_override_valid_data_n = { 1'b0, (width_p) ' (0) };
// transmit calibration code to slave
// general, if we are in prepare mode, we will
// assert the calibration code.
if (out_calib_prepare_i)
begin
out_override_en_n = 1'b1;
out_finish_prepare_n = 1'b1;
// clear pass bit when we try to prepare
out_test_pass_n[out_calibration_state_i] = 1'b0;
out_override_valid_data_n = out_calib_code_padded;
//
// this pattern causes the node on the other side to assert its
// outgoing token which allows our token logic to be reset.
//
// we want this to occur after reset is asserted but not so soon
// that the everybody has not entered reset, may occur if
// frequencies are very mismatched
//
// We also possibly want to repeat every so often in case the
// system misses the first one.
// however we don't want it to happen again too soon because
// it might interfere with our efforts to do calibration etc.
//
// behavior: every 16 M cycles, wait 2^6 cycles
// assert the token reset code for 2^6 cycles
// and then deassert.
out_ctr_n = out_ctr_r_p1;
if (out_ctr_r[counter_min_bits_lp-1:lg_token_width_p] == 1'b1)
out_override_valid_data_n
= { 2'b11, { (width_p-3) {1'b0} }, out_calibration_state_i[1:0] };
end
else // if we need to finish preparing, which basically means assert the
// calibration code for some cycles after the prepare signal goes down.
if (out_finish_prepare_r)
begin
out_ctr_n = out_ctr_r_p1;
out_override_en_n = 1'b1;
out_override_valid_data_n = out_calib_code_padded;
// if the 7th bit is set (and we have had enough time to reset
// the counter), let's exit the prepare stage
// fixme: magic number
if (out_ctr_r[lg_out_prepare_hold_cycles_p] & ~out_calib_prepare_i_r)
out_finish_prepare_n = 1'b0;
end
else
begin
out_test_pass_n[out_calibration_state_i]
= out_phase_X_good[out_calibration_state_i];
// the first state is clock initialiation, which will spread bad X's
// if we don't zero it on this side
if (~(|out_calibration_state_i))
out_test_pass_n[0] = 1'b1;
unique case (out_calibration_state_i)
2:
begin
// RICH FIXME: statemachine to launch values (from this clk domain)
// (and set bit slip and ODELAY)
// out_override_en = 1'b1;
end
3:
begin
// RICH FIXME: state machine to launch values (from this clk domain)
// out_override_en = 1'b1;
// (and set bit slip and ODELAY)
end
default:
begin
end
endcase // unique case (out_calibration_state_i)
end
end // always_comb
// ***********************************************
// ** "IN" CLK DOMAIN LOGIC BELOW HERE
//
// This logic is basically responsible for checking
// incoming data.
//
// Because we don't know the relationship between the output
// and input clocks; we need to process incoming data in this
// domain; and sending outgoing data in the other domain,
// and only send occasional signals between the two.
//
wire [tests_lp+1-1:0] in_phase_X_good;
// cross clock domain
bsg_launch_sync_sync #(.width_p(tests_lp+1)) in_to_out
(.iclk_i (in_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i (out_clk_i)
,.iclk_data_i({ in_phase_X_good })
,.iclk_data_o()
,.oclk_data_o({ out_phase_X_good })
);
wire [tests_lp-1:0] in_test_enables;
// bit vector of tests to make it more domain-crossing friendly
// in this case, it's okay if they are temporarily enabled at the same time
// so we don't worry about bit synchronization.
wire [tests_lp-1:0] out_test_enables
= (tests_lp) ' ((1 << out_calibration_state_i) & ({ tests_lp { ~out_calib_prepare_i } }));
// send test enables from out clock domain to in clock domain
bsg_launch_sync_sync #(.width_p(tests_lp)) out_to_in
(.iclk_i (out_clk_i)
,.iclk_reset_i(1'b0 )
,.oclk_i (in_clk_i)
,.iclk_data_i({ out_test_enables })
,.iclk_data_o()
,.oclk_data_o({ in_test_enables })
);
// START PHASE 1 CHECK
logic [width_p+1-1:0] in_last_pos_r, in_last_neg_r, in_last_last_pos_r;
logic [2*(width_p+1)-1:0] in_consec_pos_neg_match_r;
logic [2*(width_p+1)-1:0] in_consec_neg_pos_match_r;
// easy case: neg is the low order (fast) bits
//
// neg pos
// t0 (a-1)_lo
// (a-1)_hi
// t1 (a)_lo
// (a)_hi
wire in_pos_neg_match
= ( { in_last_pos_r, in_last_neg_r } + 1'b1)
== ({in_snoop_valid_data_pos_i, in_snoop_valid_data_neg_i});
// harder case: neg is the high order bits.
//
// neg pos
// t-1 (a-2)_hi
// (a-1)_lo
// t0 (a-1)_hi
// (a)_lo
// t1 (a)_hi
// (a+1)_lo
wire in_neg_pos_match
= ( { in_last_neg_r, in_last_last_pos_r } + 1'b1)
== ({ in_snoop_valid_data_neg_i, in_last_pos_r } );
// AWC fixme: this should actually be out_infinite_credits_o
// and needs to be done in the correct clock domain.
// we allow for infinite credits if any of the loopback-style tests
// are enabled.
// assign in_infinite_credits_o = in_test_enables[3] | in_test_enables[4];
assign out_infinite_credits_o = out_test_enables[3] | out_test_enables[4];
always_ff @(posedge in_clk_i)
begin
// probably not strictly necessary, but cleans things up for X prop mode
if (in_reset_i)
begin
in_last_pos_r <= in_snoop_valid_data_pos_i;
in_last_neg_r <= in_snoop_valid_data_neg_i;
in_consec_neg_pos_match_r <= 0;
in_consec_pos_neg_match_r <= 0;
end
if (in_test_enables[2])
begin
in_last_pos_r <= in_snoop_valid_data_pos_i;
in_last_neg_r <= in_snoop_valid_data_neg_i;
in_last_last_pos_r <= in_last_pos_r;
in_consec_pos_neg_match_r <= in_pos_neg_match & ~in_reset_i
? (&in_consec_pos_neg_match_r
? in_consec_pos_neg_match_r
: in_consec_pos_neg_match_r+1'b1
)
: 0;
in_consec_neg_pos_match_r <= in_neg_pos_match & ~in_reset_i
? (&in_consec_neg_pos_match_r
? in_consec_neg_pos_match_r
: in_consec_neg_pos_match_r+1'b1
)
: 0;
// avoid spurious warnings in X prop simulation mode
if (in_test_enables[2] !== 'X)
begin
if ((in_consec_pos_neg_match_r > 100) & !in_pos_neg_match)
$display("## Phase 1 Mismatch(P) %x %x %x %x"
, in_last_pos_r, in_last_neg_r
, in_snoop_valid_data_pos_i, in_snoop_valid_data_neg_i);
if ((in_consec_neg_pos_match_r > 100) & !in_neg_pos_match)
$display("## Phase 1 Mismatch(N) %x %x %x %x"
, in_last_neg_r, in_last_last_pos_r
, in_snoop_valid_data_neg_i, in_last_pos_r);
if (&in_consec_pos_neg_match_r && ~in_pos_neg_match)
$display("## Phase 1 Pos Lock");
if (&in_consec_neg_pos_match_r && ~in_neg_pos_match)
$display("## Phase 1 Neg Lock");
if (verbose_lp)
begin
if ((in_consec_pos_neg_match_r & 12'hfff) == 12'hffe)
$display("## Posmatch %x; negmatch %x"
,in_consec_pos_neg_match_r,in_consec_neg_pos_match_r);
if ((in_consec_neg_pos_match_r & 12'hfff) == 12'hffe)
$display("## Posmatch %x; negmatch %x"
,in_consec_pos_neg_match_r,in_consec_neg_pos_match_r);
end
end
end // if (in_test_enables[2])
end
// clock initialize
assign in_phase_X_good[0] = 1'b1;
// FIXME PHASE 1 CHECK
assign in_phase_X_good[1] = bypass_test_p[1];
// PHASE 2 (test 2) CHECK
assign in_phase_X_good[2] = (&in_consec_neg_pos_match_r)
| (&in_consec_pos_neg_match_r)
| bypass_test_p[2];
// PHASE 3 and PHASE 4 CHECK
assign in_phase_X_good[tests_lp-1:3] = bypass_test_p[tests_lp-1:3];
// DONE
assign in_phase_X_good[tests_lp] = 1'b1;
endmodule
`BSG_ABSTRACT_MODULE(bsg_source_sync_channel_control_master)
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : example_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level module. This module serves as an example,
// and allows the user to synthesize a self-contained design,
// which they can be used to test their hardware.
// In addition to the memory controller, the module instantiates:
// 1. Synthesizable testbench - used to model user's backend logic
// and generate different traffic patterns
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module example_top #
(
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter PORT_MODE = "BI_MODE",
parameter DATA_MODE = 4'b0010,
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE",
parameter EYE_TEST = "FALSE",
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL",
// For small devices, choose one only.
// For large device, choose "DGEN_ALL"
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL",
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter CMD_WDT = 'h3FF,
parameter WR_WDT = 'h1FFF,
parameter RD_WDT = 'h3FF,
parameter SEL_VICTIM_LINE = 0,
parameter BEGIN_ADDRESS = 32'h00000000,
parameter END_ADDRESS = 32'h00ffffff,
parameter PRBS_EADDR_MASK_POS = 32'hff000000,
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter DQ_WIDTH = 16,
// # of DQ (data)
parameter DQS_WIDTH = 2,
parameter DQS_CNT_WIDTH = 1,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter TCQ = 100,
parameter DRAM_TYPE = "DDR2",
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter nCK_PER_CLK = 4,
// # of memory CKs per fabric CLK
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF"
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
// parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,
inout [1:0] ddr2_dqs_p,
// Outputs
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
output tg_compare_error,
output init_calib_complete,
input [11:0] device_temp_i,
// The 12 MSB bits of the temperature sensor transfer
// function need to be connected to this port. This port
// will be synchronized w.r.t. to fabric clock internally.
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
function integer STR_TO_INT;
input [7:0] in;
begin
if(in == "8")
STR_TO_INT = 8;
else if(in == "4")
STR_TO_INT = 4;
else
STR_TO_INT = 0;
end
endfunction
localparam DATA_WIDTH = 16;
localparam RANK_WIDTH = clogb2(RANKS);
localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
//***************************************************************************
// Traffic Gen related parameters (derived)
//***************************************************************************
localparam TG_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
localparam MASK_SIZE = DATA_WIDTH/8;
// Wire declarations
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;
wire [ADDR_WIDTH-1:0] app_addr;
wire [2:0] app_cmd;
wire app_en;
wire app_rdy;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire app_wdf_end;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire app_wdf_rdy;
wire app_sr_active;
wire app_ref_ack;
wire app_zq_ack;
wire app_wdf_wren;
wire [(64+(2*APP_DATA_WIDTH))-1:0] error_status;
wire [(PAYLOAD_WIDTH/8)-1:0] cumlative_dq_lane_error;
wire mem_pattern_init_done;
wire [47:0] tg_wr_data_counts;
wire [47:0] tg_rd_data_counts;
wire modify_enable_sel;
wire [2:0] data_mode_manual_sel;
wire [2:0] addr_mode_manual_sel;
wire [APP_DATA_WIDTH-1:0] cmp_data;
reg [63:0] cmp_data_r;
wire cmp_data_valid;
reg cmp_data_valid_r;
wire cmp_error;
wire [(PAYLOAD_WIDTH/8)-1:0] dq_error_bytelane_cmp;
wire clk;
wire rst;
wire dbg_sel_pi_incdec;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire dbg_sel_po_incdec;
wire dbg_po_f_inc;
wire dbg_po_f_stg23_sel;
wire dbg_po_f_dec;
wire vio_modify_enable;
wire [3:0] vio_data_mode_value;
wire vio_pause_traffic;
wire [2:0] vio_addr_mode_value;
wire [3:0] vio_instr_mode_value;
wire [1:0] vio_bl_mode_value;
wire [9:0] vio_fixed_bl_value;
wire [2:0] vio_fixed_instr_value;
wire vio_data_mask_gen;
wire vio_tg_rst;
wire vio_dbg_sel_pi_incdec;
wire vio_dbg_pi_f_inc;
wire vio_dbg_pi_f_dec;
wire vio_dbg_sel_po_incdec;
wire vio_dbg_po_f_inc;
wire vio_dbg_po_f_stg23_sel;
wire vio_dbg_po_f_dec;
//***************************************************************************
// Start of User Design top instance
//***************************************************************************
// The User design is instantiated below. The memory interface ports are
// connected to the top-level and the application interface ports are
// connected to the traffic generator module. This provides a reference
// for connecting the memory controller to system.
//***************************************************************************
ddr2 #
(
// #parameters_mapping_user_design_top_instance#
// .RST_ACT_LOW (RST_ACT_LOW)
)
u_ddr2
(
// Memory interface ports
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_cke (ddr2_cke),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_dq (ddr2_dq),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_dqs_p (ddr2_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (1'b0),
.app_ref_req (1'b0),
.app_zq_req (1'b0),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (clk),
.ui_clk_sync_rst (rst),
.app_wdf_mask (app_wdf_mask),
// System Clock Ports
.sys_clk_i (sys_clk_i),
// Reference Clock Ports
.clk_ref_i (clk_ref_i),
.device_temp_i (device_temp_i),
.sys_rst (sys_rst)
);
// End of User Design top instance
//***************************************************************************
// The traffic generation module instantiated below drives traffic (patterns)
// on the application interface of the memory controller
//***************************************************************************
mig_7series_v4_0_traffic_gen_top #
(
.TCQ (TCQ),
.SIMULATION (SIMULATION),
.FAMILY ("VIRTEX7"),
.MEM_TYPE (DRAM_TYPE),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
//.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.NUM_DQ_PINS (PAYLOAD_WIDTH),
.MEM_BURST_LEN (BURST_LENGTH),
.MEM_COL_WIDTH (COL_WIDTH),
.PORT_MODE (PORT_MODE),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.DATA_WIDTH (APP_DATA_WIDTH),
.ADDR_WIDTH (TG_ADDR_WIDTH),
.MASK_SIZE (MASK_SIZE),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.DATA_MODE (DATA_MODE),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.CMD_WDT (CMD_WDT),
.RD_WDT (RD_WDT),
.WR_WDT (WR_WDT),
.EYE_TEST (EYE_TEST)
)
u_traffic_gen_top
(
.clk (clk),
.rst (rst),
.tg_only_rst (po_win_tg_rst | vio_tg_rst),
.manual_clear_error (manual_clear_error),
.memc_init_done (init_calib_complete),
.memc_cmd_full (~app_rdy),
.memc_cmd_en (app_en),
.memc_cmd_instr (app_cmd),
.memc_cmd_bl (),
.memc_cmd_addr (app_addr),
.memc_wr_en (app_wdf_wren),
.memc_wr_end (app_wdf_end),
.memc_wr_mask (app_wdf_mask),
.memc_wr_data (app_wdf_data),
.memc_wr_full (~app_wdf_rdy),
.memc_rd_en (),
.memc_rd_data (app_rd_data),
.memc_rd_empty (~app_rd_data_valid),
.qdr_wr_cmd_o (),
.qdr_rd_cmd_o (),
.vio_pause_traffic (vio_pause_traffic),
.vio_modify_enable (vio_modify_enable),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_instr_mode_value (vio_instr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value),
.vio_fixed_bl_value (vio_fixed_bl_value),
.vio_fixed_instr_value(vio_fixed_instr_value),
.vio_data_mask_gen (vio_data_mask_gen),
.fixed_addr_i (32'b0),
.fixed_data_i (32'b0),
.simple_data0 (32'b0),
.simple_data1 (32'b0),
.simple_data2 (32'b0),
.simple_data3 (32'b0),
.simple_data4 (32'b0),
.simple_data5 (32'b0),
.simple_data6 (32'b0),
.simple_data7 (32'b0),
.wdt_en_i (wdt_en_w),
.bram_cmd_i (39'b0),
.bram_valid_i (1'b0),
.bram_rdy_o (),
.cmp_data (cmp_data),
.cmp_data_valid (cmp_data_valid),
.cmp_error (cmp_error),
.wr_data_counts (tg_wr_data_counts),
.rd_data_counts (tg_rd_data_counts),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
.error (tg_compare_error),
.error_status (error_status),
.cumlative_dq_lane_error (cumlative_dq_lane_error),
.cmd_wdt_err_o (cmd_wdt_err_w),
.wr_wdt_err_o (wr_wdt_err_w),
.rd_wdt_err_o (rd_wdt_err_w),
.mem_pattern_init_done (mem_pattern_init_done)
);
//*****************************************************************
// Default values are assigned to the debug inputs of the traffic
// generator
//*****************************************************************
assign vio_modify_enable = 1'b0;
assign vio_data_mode_value = 4'b0010;
assign vio_addr_mode_value = 3'b011;
assign vio_instr_mode_value = 4'b0010;
assign vio_bl_mode_value = 2'b10;
assign vio_fixed_bl_value = 8'd16;
assign vio_data_mask_gen = 1'b0;
assign vio_pause_traffic = 1'b0;
assign vio_fixed_instr_value = 3'b001;
assign dbg_clear_error = 1'b0;
assign po_win_tg_rst = 1'b0;
assign vio_tg_rst = 1'b0;
assign wdt_en_w = 1'b1;
assign dbg_sel_pi_incdec = 'b0;
assign dbg_sel_po_incdec = 'b0;
assign dbg_pi_f_inc = 'b0;
assign dbg_pi_f_dec = 'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
endmodule
|
`timescale 1ps / 1ps
module nes_hci (
input clk,
input rst,
//Host Interface
input i_reset_sm,
input [7:0] i_opcode,
input i_opcode_strobe,
output reg [15:0] o_opcode_status,
output reg o_opcode_ack,
input [15:0] i_address,
input [31:0] i_count,
//Input data path
input i_data_strobe,
output reg o_hci_ready,
input [7:0] i_data,
//Output data path
output reg o_data_strobe,
input i_host_ready,
output reg [7:0] o_data,
//NES Interface
//CPU Interface
input i_cpu_break,
output reg o_cpu_r_nw, //CPU Read/!Write Pin
output reg [15:0] o_cpu_address,
input [7:0] i_cpu_din,
output reg [7:0] o_cpu_dout,
//CPU Debug Registers
output o_dbg_active,
output reg o_cpu_dbg_reg_wr,
output reg [3:0] o_cpu_dbg_reg_sel,
input [7:0] i_cpu_dbg_reg_din,
output reg [7:0] o_cpu_dbg_reg_dout,
//Picture Processing Unit (PPU)
output reg o_ppu_vram_wr,
output reg [15:0] o_ppu_vram_address,
input [7:0] i_ppu_vram_din,
output reg [7:0] o_ppu_vram_dout,
//Cartridge Config Data
output reg [39:0] o_cart_cfg,
output reg o_cart_cfg_update
);
//localparams
// Debug packet opcodes.
localparam [7:0] OP_NOP = 8'h00; //Tested
localparam [7:0] OP_DBG_BRK = 8'h01; //Tested
localparam [7:0] OP_DBG_RUN = 8'h02; //Tested
localparam [7:0] OP_QUERY_DBG_BRK = 8'h03; //Tested
localparam [7:0] OP_CPU_MEM_RD = 8'h04; //Tested
localparam [7:0] OP_CPU_MEM_WR = 8'h05; //Tested
localparam [7:0] OP_CPU_REG_RD = 8'h06; //Tested
localparam [7:0] OP_CPU_REG_WR = 8'h07; //Tested
localparam [7:0] OP_PPU_MEM_RD = 8'h08; //Tested
localparam [7:0] OP_PPU_MEM_WR = 8'h09; //Tested
localparam [7:0] OP_PPU_DISABLE = 8'h0A; //Tested
localparam [7:0] OP_CART_SET_CFG = 8'h0B; //Tested
// Symbolic state representations.
localparam [4:0] S_DISABLED = 5'h00;
localparam [4:0] S_DECODE = 5'h01;
localparam [4:0] S_CPU_MEM_RD = 5'h02;
localparam [4:0] S_CPU_MEM_WR = 5'h03;
localparam [4:0] S_CPU_REG_RD = 5'h04;
localparam [4:0] S_CPU_REG_WR = 5'h05;
localparam [4:0] S_PPU_MEM_RD = 5'h06;
localparam [4:0] S_PPU_MEM_WR = 5'h07;
localparam [4:0] S_PPU_DISABLE_STG_0 = 5'h08;
localparam [4:0] S_PPU_DISABLE_STG_1 = 5'h09;
localparam [4:0] S_PPU_DISABLE_STG_2 = 5'h0A;
localparam [4:0] S_PPU_DISABLE_STG_3 = 5'h0B;
localparam [4:0] S_PPU_DISABLE_STG_4 = 5'h0C;
localparam [4:0] S_PPU_DISABLE_STG_5 = 5'h0D;
localparam [4:0] S_CART_SET_CFG = 5'h0E;
// Opcode Status
localparam OS_OK = 32'h00000001;
localparam OS_ERROR = 32'h00000002;
localparam OS_UNKNOWN_OPCODE = 32'h00000004;
localparam OS_COUNT_IS_ZERO = 32'h00000008;
//registers/wires
reg [4:0] state;
reg [15:0] r_execute_count;
reg r_host_one_shot;
reg [15:0] r_address;
//submodules
//asynchronous logic
assign o_dbg_active = (state != S_DISABLED);
//synchronous logic
always @ (posedge clk) begin
if (rst || i_reset_sm) begin
state <= S_DECODE;
o_opcode_ack <= 0;
o_opcode_status <= 0;
r_execute_count <= 0;
o_hci_ready <= 0;
o_data_strobe <= 0;
o_data <= 0;
//CPU
o_cpu_address <= 0;
o_cpu_dout <= 0;
o_cpu_r_nw <= 1;
//Debug Interface
o_cpu_dbg_reg_wr <= 0;
o_cpu_dbg_reg_sel <= 0;
o_cpu_dbg_reg_dout<= 0;
//Picture Processing Unit (PPU)
o_ppu_vram_wr <= 0;
o_ppu_vram_dout <= 0;
o_ppu_vram_address<= 0;
//Cartridge
o_cart_cfg <= 0;
o_cart_cfg_update <= 0;
r_host_one_shot <= 0;
r_address <= 0;
end
else begin
//De-assert strobes
o_opcode_ack <= 0;
o_opcode_status <= 0;
o_hci_ready <= 0;
o_cart_cfg_update <= 0;
o_cpu_r_nw <= 1;
o_ppu_vram_wr <= 0;
o_data_strobe <= 0;
o_cpu_dbg_reg_wr <= 0;
case (state)
S_DISABLED: begin
o_hci_ready <= 1;
if (i_cpu_break) begin
//Received CPU initiated break. Begin active Debugging
state <= S_DECODE;
end
else if (i_opcode_strobe) begin
case (i_opcode)
//User Initiated break
OP_DBG_BRK: begin
state <= S_DECODE;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
OP_QUERY_DBG_BRK: begin
o_opcode_status <= OS_ERROR;
o_opcode_ack <= 1;
end
OP_NOP: begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
default: begin
o_opcode_status <= OS_UNKNOWN_OPCODE | OS_ERROR;
o_opcode_ack <= 1;
end
endcase
end
end
S_DECODE: begin
o_hci_ready <= 1;
r_execute_count <= 0;
r_address <= i_address;
o_cpu_address <= 0;
o_ppu_vram_address <= 0;
o_cpu_dbg_reg_sel <= 4'h0;
o_cpu_dbg_reg_sel <= i_address[3:0];
r_host_one_shot <= 1;
if (i_opcode_strobe) begin
case (i_opcode)
OP_CPU_MEM_RD: begin
o_cpu_address <= i_address;
state <= S_CPU_MEM_RD;
end
OP_CPU_MEM_WR: state <= S_CPU_MEM_WR;
OP_CPU_REG_RD: state <= S_CPU_REG_RD;
OP_CPU_REG_WR: state <= S_CPU_REG_WR;
OP_PPU_MEM_RD: begin
o_ppu_vram_address <= i_address;
state <= S_PPU_MEM_RD;
end
OP_PPU_MEM_WR: state <= S_PPU_MEM_WR;
OP_CART_SET_CFG: state <= S_CART_SET_CFG;
OP_DBG_BRK: state <= S_DECODE;
OP_PPU_DISABLE: state <= S_PPU_DISABLE_STG_0;
OP_DBG_RUN: begin
//Go into normal execution of code
state <= S_DISABLED;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
OP_QUERY_DBG_BRK: begin
//Yes we are in a debug break
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
OP_NOP: begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
default:
begin
// Invalid opcode. Ignore, but set error code.
o_opcode_status <= OS_UNKNOWN_OPCODE | OS_ERROR;
o_opcode_ack <= 1;
//Stay in decode
end
endcase
end
end
//CPU Mem Read
//User must populate the count and the address
//When data is available read the data [data] * count bytes
S_CPU_MEM_RD: begin
if (r_execute_count >= i_count) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
if (i_host_ready && r_host_one_shot) begin
o_data <= i_cpu_din;
o_data_strobe <= 1;
r_host_one_shot <= 0;
end
if (o_data_strobe) begin
r_execute_count <= r_execute_count + 32'h00000001;
o_cpu_address <= o_cpu_address + 16'h0001;
end
if (!i_host_ready) begin
r_host_one_shot <= 1;
end
end
//CPU Mem Write
//User must populate count and address before sending opcode
S_CPU_MEM_WR: begin
if (r_execute_count >= i_count) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
else if (i_data_strobe) begin
o_cpu_dout <= i_data;
o_cpu_r_nw <= 0;
o_cpu_address <= r_address;
end
else begin
o_hci_ready <= 1;
end
//When the strobe is high increment the counter and address
if (!o_cpu_r_nw) begin
r_execute_count <= r_execute_count + 32'h00000001;
r_address <= r_address + 16'h0001;
end
end
//CPU Read Register
S_CPU_REG_RD: begin
if (i_host_ready) begin
o_data <= i_cpu_dbg_reg_din;
o_data_strobe <= 1;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
end
//CPU Write Register
//Set up the CPU Address for the debug register
S_CPU_REG_WR: begin
o_hci_ready <= 1;
if (i_data_strobe) begin
o_cpu_dbg_reg_wr <= 1;
o_cpu_dbg_reg_dout <= i_data;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
end
//Picture Processing Unit Memory Read
S_PPU_MEM_RD: begin
if (r_execute_count >= i_count) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
else if (i_host_ready && r_host_one_shot) begin
o_data <= i_ppu_vram_din;
o_data_strobe <= 1;
r_host_one_shot <= 0;
end
if (o_data_strobe) begin
r_execute_count <= r_execute_count + 32'h00000001;
o_ppu_vram_address <= o_ppu_vram_address + 16'h0001;
end
if (!i_host_ready) begin
r_host_one_shot <= 1;
end
end
//Picture Processing Unit Memory Write
S_PPU_MEM_WR: begin
if (r_execute_count >= i_count) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
else if (i_data_strobe) begin
o_ppu_vram_dout <= i_data;
o_ppu_vram_wr <= 1;
o_ppu_vram_address <= r_address;
end
else begin
o_hci_ready <= 1;
end
//When the write stobe goes high increment the address
if (o_ppu_vram_wr) begin
r_execute_count <= r_execute_count + 32'h00000001;
r_address <= r_address + 16'h0001;
end
end
S_PPU_DISABLE_STG_0: begin
o_cpu_address <= 16'h2000;
state <= S_PPU_DISABLE_STG_1;
end
S_PPU_DISABLE_STG_1: begin
// Write 0x2000 to 0.
o_cpu_r_nw <= 1;
o_cpu_dout <= 8'h00;
// Set addr to 0x0000 for one cycle (due to PPU quirk only recognizing register
// interface reads/writes when address bits [15-13] change from 3'b001 from another
// value.
o_cpu_address <= 16'h0000;
state <= S_PPU_DISABLE_STG_2;
end
S_PPU_DISABLE_STG_2: begin
o_cpu_address <= 16'h2001;
state <= S_PPU_DISABLE_STG_3;
end
S_PPU_DISABLE_STG_3: begin
// Write 0x2001 to 0.
o_cpu_r_nw <= 1;
o_cpu_dout <= 8'h00;
// Set addr to 0x0000 for one cycle (due to PPU quirk only recognizing register
// interface reads/writes when address bits [15-13] change from 3'b001 from another
// value.
o_cpu_address <= 16'h0000;
state <= S_PPU_DISABLE_STG_4;
end
S_PPU_DISABLE_STG_4: begin
o_cpu_address <= 16'h2002;
state <= S_PPU_DISABLE_STG_5;
end
S_PPU_DISABLE_STG_5: begin
// Read 0x2002 to reset PPU byte pointer.
o_cpu_address <= 16'h0000;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
S_CART_SET_CFG: begin
if (r_execute_count >= 4) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
o_cart_cfg_update <= 1;
end
else if (i_data_strobe && o_hci_ready) begin
o_hci_ready <= 0;
r_execute_count <= r_execute_count + 32'h00000001;
o_cart_cfg <= {o_cart_cfg[31:0], i_data};
end
else begin
o_hci_ready <= 1;
end
//When the write stobe goes high increment the address
end
default: begin
state <= S_DECODE;
end
endcase
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: qdr_rld_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:36:29 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: QDRII+ SRAM / RLDRAM II SDRAM
//Purpose: Phase shift address/commands to center w.rto K/K# clocks at memory
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_rld_phy_ck_addr_cmd_delay #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_LEN = 4, //Burst Length
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3636, // Internal clock period (in ps) - for a 550 MHz clk(clk period-1818ps), fabric clk period is 3636ps
parameter N_CTL_LANES = 3 // Number of control byte lanes
)
(
input clk, // half or quarter rate core clock
input rst, // half or quarter rate core clk reset
input cmd_delay_start,
//input phy_ctl_ready, // PHY Control Block is ready for operation
output reg [5:0] ctl_lane_cnt, // The control byte lane Phaser_Out
// being accessed
output reg po_stg2_f_incdec,// Inc/dec Phaser_Out fine delay line
output reg po_en_stg2_f, // Enable Phaser_Out fine delay inc/dec
output po_ck_addr_cmd_delay_done // Completed delaying Ck,addr,
// cmd and ctl Phaser_Outs
);
localparam TAP_CNT_LIMIT = 63;
//Calculate the tap resolution of the PHASER based on the clock period
localparam FREQ_REF_DIV = (CLK_PERIOD > 5000 ? 4 :
CLK_PERIOD > 2500 ? 2 : 1);
localparam real FREQ_REF_PS = CLK_PERIOD/FREQ_REF_DIV;
localparam integer PHASER_TAP_RES = ((FREQ_REF_PS/2)/64);
// No. of Phaser taps for 1/4 of memory clock period
localparam CALC_TAP_CNT = (CLK_PERIOD / (4 * PHASER_TAP_RES));
//For now make sure our TAP_CNT calculation doesn't overflow
localparam TAP_CNT = (CALC_TAP_CNT > TAP_CNT_LIMIT) ?
TAP_CNT_LIMIT : CALC_TAP_CNT;
// // Quarter memory clock cycle in ps
// localparam DIV4_CK
// = ((CLK_PERIOD/nCK_PER_CLK)/4);
//
// // Determine the number of Phaser_Out taps required to delay by 300 ps
// // 300 ps is the PCB trace uncertainty between CK and DQS byte groups
// localparam TAP_CNT = (300 + ((CLK_PERIOD/nCK_PER_CLK)/64) - 1)/
// ((CLK_PERIOD/nCK_PER_CLK)/64);
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] delay_cnt_r;
assign po_ck_addr_cmd_delay_done = (BURST_LEN == 2)? cmd_delay_start : delay_done_r4;
//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
//the alignment is started once the
always @(posedge clk) begin
if (rst || ~cmd_delay_start || delay_done || (delay_cnt_r == 6'd1)) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end else if (((delay_cnt_r == 6'd0) || (delay_cnt_r == TAP_CNT)) && (ctl_lane_cnt < N_CTL_LANES)) begin
po_stg2_f_incdec <= #TCQ 1'b1;
po_en_stg2_f <= #TCQ 1'b1;
end
end
// delay counter to count TAP_CNT cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_CNT
if (rst || ~cmd_delay_start ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt < N_CTL_LANES)))
delay_cnt_r <= #TCQ TAP_CNT;
else if (po_en_stg2_f && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
//This ensures all ctrl byte lanes have had their output phase shifted.
always @(posedge clk) begin
if (rst || ~cmd_delay_start )
ctl_lane_cnt <= #TCQ 6'b0;
else if (~delay_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delay_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt;
else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delay_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
end
// when all the ctl_lanes have their output phase shifted by 1/4 cycle, delay shifting is done.
always @(posedge clk) begin
if (rst ) begin
delay_done <= #TCQ 1'b0;
//end else if (((delay_cnt_r == 6'd2) && (ctl_lane_cnt == N_CTL_LANES-1)) || (BURST_LEN == 2)) begin
end else if ((delay_cnt_r == 6'd2) && (ctl_lane_cnt == N_CTL_LANES-1)) begin
delay_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
endmodule
|
/*
* Milkymist VJ SoC fjmem flasher
* Copyright (C) 2010 Michael Walle <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module fjmem_jtag (
output jtag_tck,
output jtag_rst,
output jtag_update,
output jtag_shift,
output jtag_tdi,
input jtag_tdo
);
BSCAN_SPARTAN6 #(
.JTAG_CHAIN(1)
) bscan (
.CAPTURE(),
.DRCK(jtag_tck),
.RESET(jtag_rst),
.RUNTEST(),
.SEL(),
.SHIFT(jtag_shift),
.TCK(),
.TDI(jtag_tdi),
.TMS(),
.UPDATE(jtag_update),
.TDO(jtag_tdo)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Apr 14 18:32:23 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top bd_proc_sys_reset_0_0 -prefix
// bd_proc_sys_reset_0_0_ bd_proc_sys_reset_0_0_sim_netlist.v
// Design : bd_proc_sys_reset_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bd_proc_sys_reset_0_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bd_proc_sys_reset_0_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b1" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "artix7" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
bd_proc_sys_reset_0_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module bd_proc_sys_reset_0_0_cdc_sync
(lpf_exr_reg,
scndry_out,
ext_reset_in,
mb_debug_sys_rst,
lpf_exr,
p_3_out,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input ext_reset_in;
input mb_debug_sys_rst;
input lpf_exr;
input [2:0]p_3_out;
input slowest_sync_clk;
wire exr_d1;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(exr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(ext_reset_in),
.I1(mb_debug_sys_rst),
.O(exr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module bd_proc_sys_reset_0_0_cdc_sync_0
(lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
module bd_proc_sys_reset_0_0_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input ext_reset_in;
input mb_debug_sys_rst;
input aux_reset_in;
wire \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
bd_proc_sys_reset_0_0_cdc_sync \ACTIVE_HIGH_EXT.ACT_HI_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
bd_proc_sys_reset_0_0_cdc_sync_0 \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b1" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "artix7" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
module bd_proc_sys_reset_0_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Core;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire bsr;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire pr;
wire slowest_sync_clk;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr),
.Q(bus_struct_reset),
.R(1'b0));
bd_proc_sys_reset_0_0_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\PR_OUT_DFF[0].peripheral_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr),
.Q(peripheral_reset),
.R(1'b0));
bd_proc_sys_reset_0_0_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
.Core(Core),
.bsr(bsr),
.lpf_int(lpf_int),
.pr(pr),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
mb_reset_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core),
.Q(mb_reset),
.R(1'b0));
endmodule
module bd_proc_sys_reset_0_0_sequence_psr
(Core,
bsr,
pr,
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
lpf_int,
slowest_sync_clk);
output Core;
output bsr;
output pr;
output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
wire Core;
wire Core_i_1_n_0;
wire bsr;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1
(.I0(bsr),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1
(.I0(pr),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(Core),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b0))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(Core),
.S(lpf_int));
bd_proc_sys_reset_0_0_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(bsr),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b0))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(bsr),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(Core),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(pr),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b0))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(pr),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
module bd_proc_sys_reset_0_0_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/27/2014 12:04:19 PM
// Design Name:
// Module Name: keyed_permutation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module keyed_permutation #(
parameter UNIT_WIDTH = 1,
parameter NUNITS = 32,
parameter INDEX_WIDTH = 5
)(
input wire i_clk,
input wire [NUNITS*UNIT_WIDTH-1:0] i_dat,
input wire [NUNITS*INDEX_WIDTH-1:0] i_key,
input wire i_inverse,
output reg [NUNITS*UNIT_WIDTH-1:0] o_dat
);
function [INDEX_WIDTH-1:0] get_nth_zero_index;
input [NUNITS-1:0] in;
input [INDEX_WIDTH-1:0] index;
integer i;
reg [INDEX_WIDTH-1:0] zero_index;
reg [INDEX_WIDTH-1:0] out;
begin
out = {INDEX_WIDTH{1'bx}};
zero_index = 0;
for(i=0;i<NUNITS;i=i+1) begin
if(~in[i]) begin
if(index==zero_index) begin
out = i;
end
zero_index = zero_index + 1;
end
end
get_nth_zero_index = out;
end
endfunction
function [NUNITS*INDEX_WIDTH-1:0] compute_map;
input [NUNITS*INDEX_WIDTH-1:0] key;
reg [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS-1:0] done;
reg [INDEX_WIDTH-1:0] outPos;
reg [NUNITS-1:0] outDone;reg [8:0] pos;
reg [INDEX_WIDTH:0] remaining;
integer i;
reg [INDEX_WIDTH-1:0] index;
integer indexWidth;
begin
indexWidth = INDEX_WIDTH;
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
remaining = NUNITS;
for(i=0;i<NUNITS;i=i+1) begin
/*if(i<16) indexWidth = 5;
else if(i<24) indexWidth = 4;
else if(i<28) indexWidth = 3;
else if(i<30) indexWidth = 2;
else indexWidth = 1;*/
index = {INDEX_WIDTH{1'b0}};
if(i!=31) begin
index = key[pos+:INDEX_WIDTH] % remaining;
remaining = remaining - 1;
pos = pos + indexWidth;
end
outPos = get_nth_zero_index(outDone,index);
//$display("%02d -> %02d",i,outPos);
outDone[outPos]=1'b1;
map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=i;
end
compute_map = map;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] permute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[i*UNIT_WIDTH+:UNIT_WIDTH] = in[index*UNIT_WIDTH+:UNIT_WIDTH];
end
permute = out;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] unpermute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[index*UNIT_WIDTH+:UNIT_WIDTH] = in[i*UNIT_WIDTH+:UNIT_WIDTH];
end
unpermute = out;
end
endfunction
reg [NUNITS*INDEX_WIDTH-1:0] map;
always @(posedge i_clk) begin
map <= compute_map(i_key);
o_dat <= i_inverse ? unpermute(i_dat,map) : permute(i_dat,map);
end
/*
always @(i_dat) begin: PERMUTE
reg [INDEX_WIDTH-1:0] i;
reg [INDEX_WIDTH-1:0] index;
map = 0;//compute_map(i_key);
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
if(i_inverse) o_dat[index*UNIT_WIDTH+:UNIT_WIDTH] = i_dat[i*UNIT_WIDTH+:UNIT_WIDTH];
else o_dat[i*UNIT_WIDTH+:UNIT_WIDTH] = i_dat[index*UNIT_WIDTH+:UNIT_WIDTH];
end
end*/
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
module jt10_adpcm_gain(
input rst_n,
input clk, // CPU clock
input cen, // 666 kHz
// pipeline channel
input [5:0] cur_ch,
input [5:0] en_ch,
input match,
input [5:0] atl, // ADPCM Total Level
// Gain update
input [7:0] lracl,
input [2:0] up_ch,
// Data
output [1:0] lr,
input signed [15:0] pcm_in,
output signed [15:0] pcm_att
);
reg [5:0] up_ch_dec;
always @(*)
case(up_ch)
3'd0: up_ch_dec = 6'b000_001;
3'd1: up_ch_dec = 6'b000_010;
3'd2: up_ch_dec = 6'b000_100;
3'd3: up_ch_dec = 6'b001_000;
3'd4: up_ch_dec = 6'b010_000;
3'd5: up_ch_dec = 6'b100_000;
default: up_ch_dec = 6'd0;
endcase
//wire [5:0] en_ch2 = { en_ch[4:0], en_ch[5] }; // shift the bits to fit in the pipeline slot correctly
reg [6:0] db5;
always @(*)
case( db5[2:0] )
3'd0: lin_5b = 10'd512;
3'd1: lin_5b = 10'd470;
3'd2: lin_5b = 10'd431;
3'd3: lin_5b = 10'd395;
3'd4: lin_5b = 10'd362;
3'd5: lin_5b = 10'd332;
3'd6: lin_5b = 10'd305;
3'd7: lin_5b = 10'd280;
endcase
reg [7:0] lracl1, lracl2, lracl3, lracl4, lracl5, lracl6;
reg [9:0] lin_5b, lin1, lin2, lin6;
reg [3:0] sh1, sh6;
// dB to linear conversion
assign lr = lracl1[7:6];
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
lracl1 <= 8'd0; lracl2 <= 8'd0;
lracl3 <= 8'd0; lracl4 <= 8'd0;
lracl5 <= 8'd0; lracl6 <= 8'd0;
db5 <= 'd0;
sh1 <= 4'd0; sh6 <= 4'd0;
lin1 <= 10'd0;
lin6 <= 10'd0;
end else if(cen) begin
// I
lracl2 <= up_ch_dec == cur_ch ? lracl : lracl1;
// II
lracl3 <= lracl2;
// III
lracl4 <= lracl3;
// IV: new data is accepted here
lracl5 <= lracl4;
db5 <= { 2'b0, ~lracl4[4:0] } + {1'b0, ~atl};
// V
lracl6 <= lracl5;
lin6 <= lin_5b;
sh6 <= db5[6:3];
// VI close the loop
lracl1 <= lracl6;
lin1 <= sh6[3] ? 10'h0 : lin6;
sh1 <= sh6;
end
// Apply gain
// The pipeline has 6 stages, there is new input data once every 6*6=36 clock cycles
// New data is read once and it takes 4*6 cycles to get through because the shift
// operation is distributed among several iterations. This prevents the need of
// a 10x16-input mux which is very large. Instead of that, this uses two 10x2-input mux'es
// which iterated allow the max 16 shift operation
reg [3:0] shcnt1, shcnt2, shcnt3, shcnt4, shcnt5, shcnt6;
reg shcnt_mod3, shcnt_mod4, shcnt_mod5;
reg [31:0] pcm2_mul;
wire signed [15:0] lin2s = {6'b0,lin2};
always @(*) begin
shcnt_mod3 = shcnt3 != 0;
shcnt_mod4 = shcnt4 != 0;
shcnt_mod5 = shcnt5 != 0;
pcm2_mul = pcm2 * lin2s;
end
reg signed [15:0] pcm1, pcm2, pcm3, pcm4, pcm5, pcm6;
reg match2;
assign pcm_att = pcm1;
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
pcm1 <= 'd0; pcm2 <= 'd0;
pcm3 <= 'd0; pcm4 <= 'd0;
pcm5 <= 'd0; pcm6 <= 'd0;
shcnt1 <= 'd0; shcnt2 <= 'd0;
shcnt3 <= 'd0; shcnt4 <= 'd0;
shcnt5 <= 'd0; shcnt6 <= 'd0;
end else if(cen) begin
// I
pcm2 <= match ? pcm_in : pcm1;
lin2 <= lin1;
shcnt2 <= match ? sh1 : shcnt1;
match2 <= match;
// II
pcm3 <= match2 ? pcm2_mul[24:9] : pcm2;
shcnt3 <= shcnt2;
// III, shift by 0 or 1
if( shcnt_mod3 ) begin
pcm4 <= pcm3>>>1;
shcnt4 <= shcnt3-1'd1;
end else begin
pcm4 <= pcm3;
shcnt4 <= shcnt3;
end
// IV, shift by 0 or 1
if( shcnt_mod4 ) begin
pcm5 <= pcm4>>>1;
shcnt5 <= shcnt4-1'd1;
end else begin
pcm5 <= pcm4;
shcnt5 <= shcnt4;
end
// V, shift by 0 or 1
if( shcnt_mod5 ) begin
pcm6 <= pcm5>>>1;
shcnt6 <= shcnt5-1'd1;
end else begin
pcm6 <= pcm5;
shcnt6 <= shcnt5;
end
// VI close the loop and output
pcm1 <= pcm6;
shcnt1 <= shcnt6;
end
endmodule // jt10_adpcm_gain
|
`default_nettype none
module pump_probe(
input clk, // 12 MHz base clock
input RS232_Rx, // Receive pin for the FTDI chip
output RS232_Tx, // Transmit pin for the FTDI chip
output PMOD1, // Output pin for the switch
output PMOD4, // Output pin for the SYNC pulse
output PMOD8, // Output pin for the FM pulse
output J1_3,
output J1_4,
output J1_5,
output J1_6,
output J1_7,
output J1_8,
output J1_9,
output J1_10,
output J3_3,
output J3_4,
output J3_5,
output J3_6,
output J3_7,
output J3_8,
output J3_9,
output J3_10,
);
wire clk_pll;
wire lock;
reg resetn = 1;
// Setting the PLL to output a 200 MHz clock, based on code from
// https://gist.github.com/thoughtpolice/8ec923e1b3fc4bb12c11aa23b4dc53b5#file-ice40-v
// Note: These values are slightly different from those outputted by icepll
icepll pll(
.clk(clk),
.clkout(clk_pll),
.locked(lock)
);
// Control the pulses
reg sync_on;
reg pulse_on;
reg pp_on;
reg fm_up;
assign PMOD4 = sync_on;
assign PMOD1 = pulse_on;
assign PMOD8 = fm_up;
// Control the attenuators
parameter att_on_val = 8'd255;
reg [7:0] Att1 = att_on_val;
reg [7:0] Att3 = att_on_val;
reg [7:0] pp_pump = 8'd0;
reg [7:0] pp_probe = att_on_val;
assign J1_3 = Att1[7];
assign J1_4 = Att1[6];
assign J1_5 = Att1[5];
assign J1_6 = Att1[4];
assign J1_7 = Att1[3];
assign J1_8 = Att1[2];
assign J1_9 = Att1[1];
assign J1_10 = Att1[0];
assign J3_3 = Att3[0];
assign J3_4 = Att3[1];
assign J3_5 = Att3[2];
assign J3_6 = Att3[3];
assign J3_7 = Att3[4];
assign J3_8 = Att3[5];
assign J3_9 = Att3[6];
assign J3_10 = Att3[7];
// Running at a 200-MHz clock, our time step is 5 ns.
// All the times are thus divided by 5 ns to get cycles.
// 32-bit allows times up to 21 seconds
parameter stperiod = 32'd2000000; // 10 ms period
parameter stp1width = 32'd30; // 150 ns
parameter stp2width = 32'd30;
parameter stdelay = 32'd2000; // 10 us delay
parameter stp2start = stp1width + stdelay;
parameter stsync_up = stp2start + stp2width;
// The attenuator pulse switches down 10 us after the sync pulse,
// because when it turns off there is a burst of noise, and this
// moves that noise well after the signal
parameter att_delay = 32'd20000;
parameter statt_down = stsync_up + att_delay;
parameter stpump = 1'b1; // The pump is on by default, but can be toggled off
reg [31:0] period = stperiod;
reg [31:0] p1width = stp1width;
reg [31:0] p2width = stp2width;
reg [31:0] delay = stdelay;
reg [31:0] p2start = stp2start;
reg [31:0] sync_up = stsync_up;
reg [31:0] att_down = statt_down;
reg pump = stpump;
reg [31:0] counter = 0; // 32-bit for times up to 21 seconds
reg [10:0] fmcounter = 11'd500; // 11-bit counter for 100 kHz
// The main loops runs on the 200 MHz PLL clock
always @(posedge clk_pll) begin
counter <= (counter < period) ?
counter + 1 : 0;
fmcounter <= (fmcounter < 11'd2000) ?
fmcounter + 1 : 0;
// The beginning of the cycle
/*
* sync_on <= (counter < sync_up) ?
1 : 0;
pulse_on <= (((counter < p1width) && pump) ||
((counter > p2start) && (counter < sync_up))) ?
1 : 0;
Att1 <= (pp_on &&
((counter > att_down) || (counter < p1width))) ?
8'd0 : pp_val;
*/
if (counter < p1width) begin
sync_on = 1;
Att1 = pp_on ? pp_pump : pp_probe;
// Att1 <= pp_on ? 8'd0 : pp_probe;
// Att1 <= pp_on ? pp_probe : att_on_val;
pulse_on = pump ? 1 : 0;
// fm_up = 1;
end
else if (counter < p2start) begin
sync_on <= 1;
Att1 = pp_probe;
// Att1 <= att_on_val;
pulse_on = 0;
// fm_up = 0;
end
else if (counter < sync_up) begin
sync_on <= 1;
Att1 <= pp_probe;
// Att1 <= att_on_val;
pulse_on = 1;
// fm_up <= 0;
end
else if (counter < att_down) begin
sync_on = 0;
Att1 <= pp_probe;
// Att1 <= att_on_val;
pulse_on = 0;
// fm_up <= 0;
end
else begin
sync_on <= 0;
Att1 <= pp_on ? pp_pump : pp_probe;
// Att1 <= pp_on ? 8'd0 : pp_probe;
// Att1 <= pp_on ? pp_probe : att_on_val;
pulse_on <= 0;
// fm_up <= 1;
end // else: !if(counter < att_down)
if (fmcounter < 11'd1000) begin
fm_up <= 1;
end
else begin
fm_up <= 0;
end
end // always @ (posedge clk_pll)
// Setup necessary for UART
wire reset = 0;
reg transmit;
reg [7:0] tx_byte;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire recv_error;
// UART module, from https://github.com/cyrozap/osdvu
uart uart0(
.clk(clk), // The master clock for this module
.rst(reset), // Synchronous reset
.rx(RS232_Rx), // Incoming serial line
.tx(RS232_Tx), // Outgoing serial line
.transmit(transmit), // Signal to transmit
.tx_byte(tx_byte), // Byte to transmit
.received(received), // Indicated that a byte has been received
.rx_byte(rx_byte), // Byte received
.is_receiving(is_receiving), // Low when receive line is idle
.is_transmitting(is_transmitting),// Low when transmit line is idle
.recv_error(recv_error) // Indicates error in receiving packet.
);
// input and output to be communicated
reg [31:0] vinput; // input and output are reserved keywords
reg [7:0] vcontrol; // Control byte, the MSB (most significant byte) of the transmission
reg [7:0] voutput;
reg [7:0] vcheck; // Checksum byte; the input bytes are summed and sent back as output
// We need to receive multiple bytes sequentially, so this sets up both
// reading and writing. Adapted from the uart-adder from
// https://github.com/cyrozap/iCEstick-UART-Demo/pull/3/files
parameter read_A = 1'd0;
parameter read_wait = 1'd1;
parameter write_A = 1'd0;
parameter write_done = 1'd1;
reg writestate = write_A;
reg [5:0] writecount = 0;
reg [1:0] readstate = read_A;
reg [5:0] readcount = 0;
parameter STATE_RECEIVING = 2'd0;
parameter STATE_CALCULATING = 2'd1;
parameter STATE_SENDING = 2'd2;
// These set the behavior based on the control byte
parameter CONT_SET_DELAY = 8'd0;
parameter CONT_SET_PERIOD = 8'd1;
parameter CONT_SET_PUMP = 8'd2;
parameter CONT_SET_PROBE = 8'd3;
parameter CONT_TOGGLE_PUMP = 8'd4;
parameter CONT_SET_ATT = 8'd5;
parameter CONT_READ_TEST = 8'd6;
reg [2:0] state = STATE_RECEIVING;
// The communication runs at the 12 MHz clock rather than the 200 MHz clock.
always @(posedge clk) begin
case (state)
STATE_RECEIVING: begin
transmit <= 0;
case (readstate)
read_A: begin
if(received) begin
if(readcount == 6'd32) begin // Last byte in the transmission
vcontrol <= rx_byte;
state<=STATE_CALCULATING;
readcount <= 0;
readstate <= read_A;
end
else begin // Read the first bytes into vinput
vinput[readcount +: 8]=rx_byte;
readcount = readcount + 8;
readstate <= read_wait;
end
end
end // case: read_A
read_wait: begin // Wait for the next byte to arrive
if(~received) begin
readstate <= read_A;
end
end
endcase // case (readstate)
end // case: STATE_RECEIVING
// Based on the control byte, assign a new value to the desired pulse parameter
STATE_CALCULATING: begin
writestate <= write_A;
vcheck = vinput[31:24] + vinput[23:16] + vinput[15:8] + vinput[7:0];
case (vcontrol)
CONT_SET_DELAY: begin
delay <= vinput;
voutput <= vcheck;
end
CONT_SET_PERIOD: begin
period <= vinput;
voutput <= vcheck;
end
CONT_SET_PUMP: begin
p1width <= vinput;
end
CONT_SET_PROBE: begin
p2width <= vinput;
voutput <= vcheck;
end
CONT_TOGGLE_PUMP: begin
pump <= vinput[0];
voutput <= vcheck;
end
CONT_SET_ATT: begin
pp_probe <= vinput[7:0];
Att1 <= vinput[7:0];
Att3 <= vinput[15:8];
pp_pump <= vinput[23:16];
pp_on <= vinput[24];
voutput <= vcheck;
end
CONT_READ_TEST: begin
voutput <= vcheck;
end
endcase // case (vcontrol)
// state <= STATE_SENDING;
state <= STATE_RECEIVING;
end
/*
* STATE_SENDING: begin
case (writestate)
write_A: begin
if (~ is_transmitting) begin
transmit <= 1;
writestate <= write_done;
tx_byte <= voutput;
state <= STATE_SENDING;
end
end
write_done: begin
if (~ is_transmitting) begin
writestate <= write_A;
state <= STATE_RECEIVING;
transmit <= 0;
end
end
endcase
end
*/
default: begin
// should not be reached
state <= STATE_RECEIVING;
readcount <= read_A;
end
endcase // case (state)
// After each change, update the pulse parameters
p2start <= p1width + delay;
sync_up <= p2start + p2width;
att_down <= sync_up + att_delay;
end // always @ (posedge iCE_CLK)
endmodule // pump_probe
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_2_V
`define SKY130_FD_SC_LS__O21BA_2_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAMB36.v,v 1.16 2007/06/15 20:58:41 wloo Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM
// /___/ /\ Filename : RAMB36.v
// \ \ / \ Timestamp : Tues July 26 16:43:59 PST 2005
// \___\/\___\
//
// Revision:
// 07/26/05 - Initial version.
// 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584).
// 03/14/07 - Removed attribute INITP_FILE (CR 436003).
// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812).
// 06/13/07 - Added high performace version of the model.
// End Revision
`timescale 1 ps/1 ps
module RAMB36 (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB,
ADDRA, ADDRB, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter INIT_FILE = "NONE";
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_MODE = "SAFE";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
localparam SETUP_ALL = 1000;
localparam SETUP_READ_FIRST = 3000;
output CASCADEOUTLATA, CASCADEOUTREGA;
output CASCADEOUTLATB, CASCADEOUTREGB;
output [31:0] DOA;
output [31:0] DOB;
output [3:0] DOPA;
output [3:0] DOPB;
input ENA, CLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA;
input ENB, CLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB;
input [15:0] ADDRA;
input [15:0] ADDRB;
input [31:0] DIA;
input [31:0] DIB;
input [3:0] DIPA;
input [3:0] DIPB;
input [3:0] WEA;
input [3:0] WEB;
tri0 GSR = glbl.GSR;
wire [7:0] dangle_out8;
wire dangle_out;
wire [3:0] dangle_out4;
wire [31:0] dangle_out32;
ARAMB36_INTERNAL INT_RAMB (.DIA({32'b0,DIA}), .ENA(ENA), .WEA({4'b0,WEA}), .SSRA(SSRA), .ADDRA(ADDRA), .CLKA(CLKA), .DOA({dangle_out32,DOA}), .DIB({32'b0,DIB}), .ENB(ENB), .WEB({4'b0,WEB}), .SSRB(SSRB), .ADDRB(ADDRB), .CLKB(CLKB), .DOB(DOB), .GSR(GSR), .DOPA({dangle_out4,DOPA}), .DOPB(DOPB), .DIPA(DIPA), .DIPB({4'b0,DIPB}), .CASCADEOUTLATA(CASCADEOUTLATA), .CASCADEOUTLATB(CASCADEOUTLATB), .CASCADEOUTREGA(CASCADEOUTREGA), .CASCADEOUTREGB(CASCADEOUTREGB), .CASCADEINLATA(CASCADEINLATA), .CASCADEINLATB(CASCADEINLATB), .CASCADEINREGA(CASCADEINREGA), .CASCADEINREGB(CASCADEINREGB), .REGCEA(REGCEA), .REGCEB(REGCEB), .REGCLKA(CLKA), .REGCLKB(CLKB), .DBITERR(dangle_out), .ECCPARITY(dangle_out8), .SBITERR(dangle_out));
defparam INT_RAMB.BRAM_MODE = "TRUE_DUAL_PORT";
defparam INT_RAMB.INIT_A = INIT_A;
defparam INT_RAMB.INIT_B = INIT_B;
defparam INT_RAMB.INIT_FILE = INIT_FILE;
defparam INT_RAMB.SRVAL_A = SRVAL_A;
defparam INT_RAMB.SRVAL_B = SRVAL_B;
defparam INT_RAMB.READ_WIDTH_A = READ_WIDTH_A;
defparam INT_RAMB.READ_WIDTH_B = READ_WIDTH_B;
defparam INT_RAMB.WRITE_WIDTH_A = WRITE_WIDTH_A;
defparam INT_RAMB.WRITE_WIDTH_B = WRITE_WIDTH_B;
defparam INT_RAMB.WRITE_MODE_A = WRITE_MODE_A;
defparam INT_RAMB.WRITE_MODE_B = WRITE_MODE_B;
defparam INT_RAMB.RAM_EXTENSION_A = RAM_EXTENSION_A;
defparam INT_RAMB.RAM_EXTENSION_B = RAM_EXTENSION_B;
defparam INT_RAMB.SETUP_ALL = SETUP_ALL;
defparam INT_RAMB.SETUP_READ_FIRST = SETUP_READ_FIRST;
defparam INT_RAMB.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK;
defparam INT_RAMB.SIM_MODE = SIM_MODE;
defparam INT_RAMB.EN_ECC_READ = "FALSE";
defparam INT_RAMB.EN_ECC_SCRUB = "FALSE";
defparam INT_RAMB.EN_ECC_WRITE = "FALSE";
defparam INT_RAMB.DOA_REG = DOA_REG;
defparam INT_RAMB.DOB_REG = DOB_REG;
defparam INT_RAMB.INIT_00 = INIT_00;
defparam INT_RAMB.INIT_01 = INIT_01;
defparam INT_RAMB.INIT_02 = INIT_02;
defparam INT_RAMB.INIT_03 = INIT_03;
defparam INT_RAMB.INIT_04 = INIT_04;
defparam INT_RAMB.INIT_05 = INIT_05;
defparam INT_RAMB.INIT_06 = INIT_06;
defparam INT_RAMB.INIT_07 = INIT_07;
defparam INT_RAMB.INIT_08 = INIT_08;
defparam INT_RAMB.INIT_09 = INIT_09;
defparam INT_RAMB.INIT_0A = INIT_0A;
defparam INT_RAMB.INIT_0B = INIT_0B;
defparam INT_RAMB.INIT_0C = INIT_0C;
defparam INT_RAMB.INIT_0D = INIT_0D;
defparam INT_RAMB.INIT_0E = INIT_0E;
defparam INT_RAMB.INIT_0F = INIT_0F;
defparam INT_RAMB.INIT_10 = INIT_10;
defparam INT_RAMB.INIT_11 = INIT_11;
defparam INT_RAMB.INIT_12 = INIT_12;
defparam INT_RAMB.INIT_13 = INIT_13;
defparam INT_RAMB.INIT_14 = INIT_14;
defparam INT_RAMB.INIT_15 = INIT_15;
defparam INT_RAMB.INIT_16 = INIT_16;
defparam INT_RAMB.INIT_17 = INIT_17;
defparam INT_RAMB.INIT_18 = INIT_18;
defparam INT_RAMB.INIT_19 = INIT_19;
defparam INT_RAMB.INIT_1A = INIT_1A;
defparam INT_RAMB.INIT_1B = INIT_1B;
defparam INT_RAMB.INIT_1C = INIT_1C;
defparam INT_RAMB.INIT_1D = INIT_1D;
defparam INT_RAMB.INIT_1E = INIT_1E;
defparam INT_RAMB.INIT_1F = INIT_1F;
defparam INT_RAMB.INIT_20 = INIT_20;
defparam INT_RAMB.INIT_21 = INIT_21;
defparam INT_RAMB.INIT_22 = INIT_22;
defparam INT_RAMB.INIT_23 = INIT_23;
defparam INT_RAMB.INIT_24 = INIT_24;
defparam INT_RAMB.INIT_25 = INIT_25;
defparam INT_RAMB.INIT_26 = INIT_26;
defparam INT_RAMB.INIT_27 = INIT_27;
defparam INT_RAMB.INIT_28 = INIT_28;
defparam INT_RAMB.INIT_29 = INIT_29;
defparam INT_RAMB.INIT_2A = INIT_2A;
defparam INT_RAMB.INIT_2B = INIT_2B;
defparam INT_RAMB.INIT_2C = INIT_2C;
defparam INT_RAMB.INIT_2D = INIT_2D;
defparam INT_RAMB.INIT_2E = INIT_2E;
defparam INT_RAMB.INIT_2F = INIT_2F;
defparam INT_RAMB.INIT_30 = INIT_30;
defparam INT_RAMB.INIT_31 = INIT_31;
defparam INT_RAMB.INIT_32 = INIT_32;
defparam INT_RAMB.INIT_33 = INIT_33;
defparam INT_RAMB.INIT_34 = INIT_34;
defparam INT_RAMB.INIT_35 = INIT_35;
defparam INT_RAMB.INIT_36 = INIT_36;
defparam INT_RAMB.INIT_37 = INIT_37;
defparam INT_RAMB.INIT_38 = INIT_38;
defparam INT_RAMB.INIT_39 = INIT_39;
defparam INT_RAMB.INIT_3A = INIT_3A;
defparam INT_RAMB.INIT_3B = INIT_3B;
defparam INT_RAMB.INIT_3C = INIT_3C;
defparam INT_RAMB.INIT_3D = INIT_3D;
defparam INT_RAMB.INIT_3E = INIT_3E;
defparam INT_RAMB.INIT_3F = INIT_3F;
defparam INT_RAMB.INIT_40 = INIT_40;
defparam INT_RAMB.INIT_41 = INIT_41;
defparam INT_RAMB.INIT_42 = INIT_42;
defparam INT_RAMB.INIT_43 = INIT_43;
defparam INT_RAMB.INIT_44 = INIT_44;
defparam INT_RAMB.INIT_45 = INIT_45;
defparam INT_RAMB.INIT_46 = INIT_46;
defparam INT_RAMB.INIT_47 = INIT_47;
defparam INT_RAMB.INIT_48 = INIT_48;
defparam INT_RAMB.INIT_49 = INIT_49;
defparam INT_RAMB.INIT_4A = INIT_4A;
defparam INT_RAMB.INIT_4B = INIT_4B;
defparam INT_RAMB.INIT_4C = INIT_4C;
defparam INT_RAMB.INIT_4D = INIT_4D;
defparam INT_RAMB.INIT_4E = INIT_4E;
defparam INT_RAMB.INIT_4F = INIT_4F;
defparam INT_RAMB.INIT_50 = INIT_50;
defparam INT_RAMB.INIT_51 = INIT_51;
defparam INT_RAMB.INIT_52 = INIT_52;
defparam INT_RAMB.INIT_53 = INIT_53;
defparam INT_RAMB.INIT_54 = INIT_54;
defparam INT_RAMB.INIT_55 = INIT_55;
defparam INT_RAMB.INIT_56 = INIT_56;
defparam INT_RAMB.INIT_57 = INIT_57;
defparam INT_RAMB.INIT_58 = INIT_58;
defparam INT_RAMB.INIT_59 = INIT_59;
defparam INT_RAMB.INIT_5A = INIT_5A;
defparam INT_RAMB.INIT_5B = INIT_5B;
defparam INT_RAMB.INIT_5C = INIT_5C;
defparam INT_RAMB.INIT_5D = INIT_5D;
defparam INT_RAMB.INIT_5E = INIT_5E;
defparam INT_RAMB.INIT_5F = INIT_5F;
defparam INT_RAMB.INIT_60 = INIT_60;
defparam INT_RAMB.INIT_61 = INIT_61;
defparam INT_RAMB.INIT_62 = INIT_62;
defparam INT_RAMB.INIT_63 = INIT_63;
defparam INT_RAMB.INIT_64 = INIT_64;
defparam INT_RAMB.INIT_65 = INIT_65;
defparam INT_RAMB.INIT_66 = INIT_66;
defparam INT_RAMB.INIT_67 = INIT_67;
defparam INT_RAMB.INIT_68 = INIT_68;
defparam INT_RAMB.INIT_69 = INIT_69;
defparam INT_RAMB.INIT_6A = INIT_6A;
defparam INT_RAMB.INIT_6B = INIT_6B;
defparam INT_RAMB.INIT_6C = INIT_6C;
defparam INT_RAMB.INIT_6D = INIT_6D;
defparam INT_RAMB.INIT_6E = INIT_6E;
defparam INT_RAMB.INIT_6F = INIT_6F;
defparam INT_RAMB.INIT_70 = INIT_70;
defparam INT_RAMB.INIT_71 = INIT_71;
defparam INT_RAMB.INIT_72 = INIT_72;
defparam INT_RAMB.INIT_73 = INIT_73;
defparam INT_RAMB.INIT_74 = INIT_74;
defparam INT_RAMB.INIT_75 = INIT_75;
defparam INT_RAMB.INIT_76 = INIT_76;
defparam INT_RAMB.INIT_77 = INIT_77;
defparam INT_RAMB.INIT_78 = INIT_78;
defparam INT_RAMB.INIT_79 = INIT_79;
defparam INT_RAMB.INIT_7A = INIT_7A;
defparam INT_RAMB.INIT_7B = INIT_7B;
defparam INT_RAMB.INIT_7C = INIT_7C;
defparam INT_RAMB.INIT_7D = INIT_7D;
defparam INT_RAMB.INIT_7E = INIT_7E;
defparam INT_RAMB.INIT_7F = INIT_7F;
defparam INT_RAMB.INITP_00 = INITP_00;
defparam INT_RAMB.INITP_01 = INITP_01;
defparam INT_RAMB.INITP_02 = INITP_02;
defparam INT_RAMB.INITP_03 = INITP_03;
defparam INT_RAMB.INITP_04 = INITP_04;
defparam INT_RAMB.INITP_05 = INITP_05;
defparam INT_RAMB.INITP_06 = INITP_06;
defparam INT_RAMB.INITP_07 = INITP_07;
defparam INT_RAMB.INITP_08 = INITP_08;
defparam INT_RAMB.INITP_09 = INITP_09;
defparam INT_RAMB.INITP_0A = INITP_0A;
defparam INT_RAMB.INITP_0B = INITP_0B;
defparam INT_RAMB.INITP_0C = INITP_0C;
defparam INT_RAMB.INITP_0D = INITP_0D;
defparam INT_RAMB.INITP_0E = INITP_0E;
defparam INT_RAMB.INITP_0F = INITP_0F;
specify
(CLKA => DOA[0]) = (100, 100);
(CLKA => DOA[1]) = (100, 100);
(CLKA => DOA[2]) = (100, 100);
(CLKA => DOA[3]) = (100, 100);
(CLKA => DOA[4]) = (100, 100);
(CLKA => DOA[5]) = (100, 100);
(CLKA => DOA[6]) = (100, 100);
(CLKA => DOA[7]) = (100, 100);
(CLKA => DOA[8]) = (100, 100);
(CLKA => DOA[9]) = (100, 100);
(CLKA => DOA[10]) = (100, 100);
(CLKA => DOA[11]) = (100, 100);
(CLKA => DOA[12]) = (100, 100);
(CLKA => DOA[13]) = (100, 100);
(CLKA => DOA[14]) = (100, 100);
(CLKA => DOA[15]) = (100, 100);
(CLKA => DOA[16]) = (100, 100);
(CLKA => DOA[17]) = (100, 100);
(CLKA => DOA[18]) = (100, 100);
(CLKA => DOA[19]) = (100, 100);
(CLKA => DOA[20]) = (100, 100);
(CLKA => DOA[21]) = (100, 100);
(CLKA => DOA[22]) = (100, 100);
(CLKA => DOA[23]) = (100, 100);
(CLKA => DOA[24]) = (100, 100);
(CLKA => DOA[25]) = (100, 100);
(CLKA => DOA[26]) = (100, 100);
(CLKA => DOA[27]) = (100, 100);
(CLKA => DOA[28]) = (100, 100);
(CLKA => DOA[29]) = (100, 100);
(CLKA => DOA[30]) = (100, 100);
(CLKA => DOA[31]) = (100, 100);
(CLKA => DOPA[0]) = (100, 100);
(CLKA => DOPA[1]) = (100, 100);
(CLKA => DOPA[2]) = (100, 100);
(CLKA => DOPA[3]) = (100, 100);
(CLKB => DOB[0]) = (100, 100);
(CLKB => DOB[1]) = (100, 100);
(CLKB => DOB[2]) = (100, 100);
(CLKB => DOB[3]) = (100, 100);
(CLKB => DOB[4]) = (100, 100);
(CLKB => DOB[5]) = (100, 100);
(CLKB => DOB[6]) = (100, 100);
(CLKB => DOB[7]) = (100, 100);
(CLKB => DOB[8]) = (100, 100);
(CLKB => DOB[9]) = (100, 100);
(CLKB => DOB[10]) = (100, 100);
(CLKB => DOB[11]) = (100, 100);
(CLKB => DOB[12]) = (100, 100);
(CLKB => DOB[13]) = (100, 100);
(CLKB => DOB[14]) = (100, 100);
(CLKB => DOB[15]) = (100, 100);
(CLKB => DOB[16]) = (100, 100);
(CLKB => DOB[17]) = (100, 100);
(CLKB => DOB[18]) = (100, 100);
(CLKB => DOB[19]) = (100, 100);
(CLKB => DOB[20]) = (100, 100);
(CLKB => DOB[21]) = (100, 100);
(CLKB => DOB[22]) = (100, 100);
(CLKB => DOB[23]) = (100, 100);
(CLKB => DOB[24]) = (100, 100);
(CLKB => DOB[25]) = (100, 100);
(CLKB => DOB[26]) = (100, 100);
(CLKB => DOB[27]) = (100, 100);
(CLKB => DOB[28]) = (100, 100);
(CLKB => DOB[29]) = (100, 100);
(CLKB => DOB[30]) = (100, 100);
(CLKB => DOB[31]) = (100, 100);
(CLKB => DOPB[0]) = (100, 100);
(CLKB => DOPB[1]) = (100, 100);
(CLKB => DOPB[2]) = (100, 100);
(CLKB => DOPB[3]) = (100, 100);
(CASCADEINLATA => DOA[0]) = (0, 0);
(CASCADEINREGA => DOA[0]) = (0, 0);
(CASCADEINLATB => DOB[0]) = (0, 0);
(CASCADEINREGB => DOB[0]) = (0, 0);
(CLKA => CASCADEOUTLATA) = (100, 100);
(CLKA => CASCADEOUTREGA) = (100, 100);
(CLKB => CASCADEOUTLATB) = (100, 100);
(CLKB => CASCADEOUTREGB) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // RAMB36
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2017 19:09:30
// Design Name:
// Module Name: Display
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module display(
input clk_display,
input [31:0] num,
input [7:0] puntos,
output [7:0] segmentos,
output reg [7:0] anodos
);
reg [2:0] counter;
reg [3:0] X;
always @(posedge clk_display) begin
counter <= counter+3'b1;
end
always @(counter) begin
case (counter)
4'd0: anodos= 8'b01111111;
4'd1: anodos= 8'b10111111;
4'd2: anodos= 8'b11011111;
4'd3: anodos= 8'b11101111;
4'd4: anodos= 8'b11110111;
4'd5: anodos= 8'b11111011;
4'd6: anodos= 8'b11111101;
4'd7: anodos= 8'b11111110;
default: anodos=8'b11111111;
endcase
end
always @(*) begin
case(anodos)
8'b01111111: X=num[31:28];
8'b10111111: X=num[27:24];
8'b11011111: X=num[23:20];
8'b11101111: X=num[19:16];
8'b11110111: X=num[15:12];
8'b11111011: X=num[11:8];
8'b11111101: X=num[7:4];
8'b11111110: X=num[3:0];
default: X=4'b0 ;
endcase
end
Dec_4b_seg Dec(
. NUM(X),
. CATODOS({segmentos})
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_vb_e
//
// Generated
// by: wig
// on: Sat Mar 3 09:45:57 2007
// cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_vb_e.v,v 1.1 2007/03/03 11:17:34 wig Exp $
// $Date: 2007/03/03 11:17:34 $
// $Log: inst_vb_e.v,v $
// Revision 1.1 2007/03/03 11:17:34 wig
// Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
udc: Verilog HEAD HOOK inst_bc1_i
//
//
// Start of Generated Module rtl of inst_vb_e
//
// No user `defines in this module
module inst_vb_e
//
// Generated Module inst_bc1_i
//
(
);
udc: Verilog PARA HOOK inst_bc1_i
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
udc: Verilog BODY HOOK inst_bc1_i
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_vb_e
//
udc: Verilog FOOT HOOK two lines inst_bc1_i
second line inst_bc1_i, config here inst_vb_e_rtl_conf and description verilog udc inst_bc2_i
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.v
*
* If a read and write are issued to the same address the new value is read back.
*
*/
`include "bsg_defines.v"
module bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter byte_offset_width_lp=$clog2(data_width_in_bytes_lp)
, parameter init_mem_p=0
)
(
input clk_i
, input reset_i
// ctrl interface
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input [write_mask_width_lp-1:0] w_mask_i
// read channel
, output logic [width_p-1:0] data_o
);
import "DPI-C" context function
chandle bsg_mem_dma_init(longint unsigned id,
longint unsigned channel_addr_width_fp,
longint unsigned data_width_fp,
longint unsigned mem_els_fp,
longint unsigned init_mem_fp);
import "DPI-C" context function
void bsg_mem_dma_exit(longint unsigned id);
import "DPI-C" context function
byte unsigned bsg_mem_dma_get(chandle handle, longint unsigned addr);
import "DPI-C" context function
void bsg_mem_dma_set(chandle handle, longint unsigned addr, byte val);
chandle memory;
initial begin
memory
= bsg_mem_dma_init(id_p, addr_width_lp, width_p, els_p, init_mem_p);
end
final begin
bsg_mem_dma_exit(id_p);
end
////////////////
// read logic //
////////////////
logic [addr_width_lp+byte_offset_width_lp-1:0] read_byte_addr;
assign read_byte_addr = { r_addr_i, {(byte_offset_width_lp){1'b0}} };
logic [width_p-1:0] data_r;
always_ff @(negedge clk_i) begin
if (r_v_i) begin
for (integer byte_id = 0; byte_id < data_width_in_bytes_lp; byte_id++) begin
data_r[byte_id*8+:8] <= bsg_mem_dma_get(memory, read_byte_addr+byte_id);
end
end
end
// most client code expects outputs to change at the positive edge
always_ff @(posedge clk_i) begin
data_o <= data_r;
end
/////////////////
// write logic //
/////////////////
logic [addr_width_lp+byte_offset_width_lp-1:0] write_byte_addr;
assign write_byte_addr = { w_addr_i, {(byte_offset_width_lp){1'b0}} };
logic [width_p-1:0] mem_data_li;
logic write_valid;
assign write_valid = ~reset_i & w_v_i;
assign mem_data_li = w_data_i;
always_ff @(posedge clk_i) begin
for (integer byte_id = 0; byte_id < data_width_in_bytes_lp; byte_id++) begin
if (write_valid & w_mask_i[byte_id])
bsg_mem_dma_set(memory, write_byte_addr+byte_id, mem_data_li[byte_id*8+:8]);
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma)
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2015 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2015.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : DPHY_DIFFINBUF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DPHY_DIFFINBUF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "TRUE",
parameter ISTANDARD = "DEFAULT"
)(
output HSRX_O,
output LPRX_O_N,
output LPRX_O_P,
input HSRX_DISABLE,
input I,
input IB,
input LPRX_DISABLE
);
// define constants
localparam MODULE_NAME = "DPHY_DIFFINBUF";
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 1;
localparam DIFF_TERM_TRUE = 0;
localparam ISTANDARD_DEFAULT = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DPHY_DIFFINBUF_dr.v"
`else
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [56:1] ISTANDARD_REG = ISTANDARD;
`endif
wire DIFF_TERM_BIN;
wire ISTANDARD_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire HSRX_O_out;
wire LPRX_O_N_out;
wire LPRX_O_P_out;
wire HSRX_DISABLE_in;
wire IB_in;
wire I_in;
wire LPRX_DISABLE_in;
assign HSRX_O = HSRX_O_out;
assign LPRX_O_N = LPRX_O_N_out;
assign LPRX_O_P = LPRX_O_P_out;
assign HSRX_DISABLE_in = HSRX_DISABLE;
assign IB_in = IB;
assign I_in = I;
assign LPRX_DISABLE_in = LPRX_DISABLE;
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_TRUE;
assign ISTANDARD_BIN =
(ISTANDARD_REG == "DEFAULT") ? ISTANDARD_DEFAULT :
ISTANDARD_DEFAULT;
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-103] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1;
$finish;
end
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DIFF_TERM_REG != "TRUE") &&
(DIFF_TERM_REG != "FALSE"))) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
// no check
// if ((attr_test == 1'b1) ||
// ((ISTANDARD_REG != "DEFAULT"))) begin
// $display("Error: [Unisim %s-102] ISTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, ISTANDARD_REG);
// attr_err = 1'b1;
// end
if (attr_err == 1'b1) #1 $finish;
end
reg o_out;
wire [1:0] lp_out;
wire lp_mode;
wire hs_mode;
wire hs_out;
reg [3*8:1] strP,strN;
always @(*)
begin
$sformat(strP, "%v", I);
$sformat(strN, "%v", IB);
end
assign lp_mode = (strP[24:17] == "S") & (strN[24:17] == "S"); // For LP strength type Strong
assign #1 lp_out[0] = lp_mode === 1'b1 ? I_in : 1'b0;
assign #1 lp_out[1] = lp_mode === 1'b1 ? IB_in : 1'b0;
assign HSRX_O_out = (HSRX_DISABLE_in === 1'b0) ? o_out : (HSRX_DISABLE_in === 1'bx || HSRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0;
assign LPRX_O_N_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[1] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0;
assign LPRX_O_P_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[0] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0;
always @ (I_in or IB_in) begin
if (I_in == 1'b1 && IB_in == 1'b0)
o_out <= 1'b1;
else if (I_in == 1'b0 && IB_in == 1'b1)
o_out <= 1'b0;
else if ((I_in === 1'bx) || (IB_in === 1'bx) || I_in === 1'bz || IB_in === 1'bz )
o_out <= 1'bx;
end
specify
(HSRX_DISABLE => HSRX_O) = (0:0:0, 0:0:0);
(I => HSRX_O) = (0:0:0, 0:0:0);
(I => LPRX_O_P) = (0:0:0, 0:0:0);
(IB => HSRX_O) = (0:0:0, 0:0:0);
(IB => LPRX_O_N) = (0:0:0, 0:0:0);
(LPRX_DISABLE => LPRX_O_N) = (0:0:0, 0:0:0);
(LPRX_DISABLE => LPRX_O_P) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.t.a*",2)
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't even get added
// verilator coverage_block_off
$write("");
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
if (0) begin
// CHECK_COVER(-1,"top.t.b*",0)
// Make sure that we don't optimize away zero buckets
end
if (toggle) begin
// CHECK_COVER(-1,"top.t.b*",2)
// t.b1 and t.b2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't
// verilator coverage_block_off
$write("");
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin
// CHECK_COVER(-1,"top.t.t1",1)
end
if (external) begin
// CHECK_COVER(-1,"top.t.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.t.o1",1)
// because under coverage_module_off
end
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_time (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter num_cks = 1;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_TIME";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_time_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_time_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_time_psl_logic.v"
`else
`endmodule // ovl_time
`endif
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module riscv_top
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter CORE_ID = 0
,parameter MEM_CACHE_ADDR_MIN = 0
,parameter MEM_CACHE_ADDR_MAX = 32'hffffffff
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input axi_i_awready_i
,input axi_i_wready_i
,input axi_i_bvalid_i
,input [ 1:0] axi_i_bresp_i
,input [ 3:0] axi_i_bid_i
,input axi_i_arready_i
,input axi_i_rvalid_i
,input [ 31:0] axi_i_rdata_i
,input [ 1:0] axi_i_rresp_i
,input [ 3:0] axi_i_rid_i
,input axi_i_rlast_i
,input axi_d_awready_i
,input axi_d_wready_i
,input axi_d_bvalid_i
,input [ 1:0] axi_d_bresp_i
,input [ 3:0] axi_d_bid_i
,input axi_d_arready_i
,input axi_d_rvalid_i
,input [ 31:0] axi_d_rdata_i
,input [ 1:0] axi_d_rresp_i
,input [ 3:0] axi_d_rid_i
,input axi_d_rlast_i
,input intr_i
,input [ 31:0] reset_vector_i
// Outputs
,output axi_i_awvalid_o
,output [ 31:0] axi_i_awaddr_o
,output [ 3:0] axi_i_awid_o
,output [ 7:0] axi_i_awlen_o
,output [ 1:0] axi_i_awburst_o
,output axi_i_wvalid_o
,output [ 31:0] axi_i_wdata_o
,output [ 3:0] axi_i_wstrb_o
,output axi_i_wlast_o
,output axi_i_bready_o
,output axi_i_arvalid_o
,output [ 31:0] axi_i_araddr_o
,output [ 3:0] axi_i_arid_o
,output [ 7:0] axi_i_arlen_o
,output [ 1:0] axi_i_arburst_o
,output axi_i_rready_o
,output axi_d_awvalid_o
,output [ 31:0] axi_d_awaddr_o
,output [ 3:0] axi_d_awid_o
,output [ 7:0] axi_d_awlen_o
,output [ 1:0] axi_d_awburst_o
,output axi_d_wvalid_o
,output [ 31:0] axi_d_wdata_o
,output [ 3:0] axi_d_wstrb_o
,output axi_d_wlast_o
,output axi_d_bready_o
,output axi_d_arvalid_o
,output [ 31:0] axi_d_araddr_o
,output [ 3:0] axi_d_arid_o
,output [ 7:0] axi_d_arlen_o
,output [ 1:0] axi_d_arburst_o
,output axi_d_rready_o
);
wire icache_valid_w;
wire icache_flush_w;
wire dcache_flush_w;
wire dcache_invalidate_w;
wire dcache_ack_w;
wire [ 10:0] dcache_resp_tag_w;
wire [ 31:0] icache_inst_w;
wire [ 31:0] cpu_id_w = CORE_ID;
wire dcache_rd_w;
wire [ 31:0] dcache_addr_w;
wire dcache_accept_w;
wire icache_invalidate_w;
wire dcache_writeback_w;
wire [ 10:0] dcache_req_tag_w;
wire dcache_cacheable_w;
wire icache_error_w;
wire [ 31:0] dcache_data_rd_w;
wire icache_accept_w;
wire [ 3:0] dcache_wr_w;
wire [ 31:0] icache_pc_w;
wire icache_rd_w;
wire dcache_error_w;
wire [ 31:0] dcache_data_wr_w;
dcache
u_dcache
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(dcache_addr_w)
,.mem_data_wr_i(dcache_data_wr_w)
,.mem_rd_i(dcache_rd_w)
,.mem_wr_i(dcache_wr_w)
,.mem_cacheable_i(dcache_cacheable_w)
,.mem_req_tag_i(dcache_req_tag_w)
,.mem_invalidate_i(dcache_invalidate_w)
,.mem_writeback_i(dcache_writeback_w)
,.mem_flush_i(dcache_flush_w)
,.axi_awready_i(axi_d_awready_i)
,.axi_wready_i(axi_d_wready_i)
,.axi_bvalid_i(axi_d_bvalid_i)
,.axi_bresp_i(axi_d_bresp_i)
,.axi_bid_i(axi_d_bid_i)
,.axi_arready_i(axi_d_arready_i)
,.axi_rvalid_i(axi_d_rvalid_i)
,.axi_rdata_i(axi_d_rdata_i)
,.axi_rresp_i(axi_d_rresp_i)
,.axi_rid_i(axi_d_rid_i)
,.axi_rlast_i(axi_d_rlast_i)
// Outputs
,.mem_data_rd_o(dcache_data_rd_w)
,.mem_accept_o(dcache_accept_w)
,.mem_ack_o(dcache_ack_w)
,.mem_error_o(dcache_error_w)
,.mem_resp_tag_o(dcache_resp_tag_w)
,.axi_awvalid_o(axi_d_awvalid_o)
,.axi_awaddr_o(axi_d_awaddr_o)
,.axi_awid_o(axi_d_awid_o)
,.axi_awlen_o(axi_d_awlen_o)
,.axi_awburst_o(axi_d_awburst_o)
,.axi_wvalid_o(axi_d_wvalid_o)
,.axi_wdata_o(axi_d_wdata_o)
,.axi_wstrb_o(axi_d_wstrb_o)
,.axi_wlast_o(axi_d_wlast_o)
,.axi_bready_o(axi_d_bready_o)
,.axi_arvalid_o(axi_d_arvalid_o)
,.axi_araddr_o(axi_d_araddr_o)
,.axi_arid_o(axi_d_arid_o)
,.axi_arlen_o(axi_d_arlen_o)
,.axi_arburst_o(axi_d_arburst_o)
,.axi_rready_o(axi_d_rready_o)
);
riscv_core
#(
.MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
,.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
)
u_core
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_d_data_rd_i(dcache_data_rd_w)
,.mem_d_accept_i(dcache_accept_w)
,.mem_d_ack_i(dcache_ack_w)
,.mem_d_error_i(dcache_error_w)
,.mem_d_resp_tag_i(dcache_resp_tag_w)
,.mem_i_accept_i(icache_accept_w)
,.mem_i_valid_i(icache_valid_w)
,.mem_i_error_i(icache_error_w)
,.mem_i_inst_i(icache_inst_w)
,.intr_i(intr_i)
,.reset_vector_i(reset_vector_i)
,.cpu_id_i(cpu_id_w)
// Outputs
,.mem_d_addr_o(dcache_addr_w)
,.mem_d_data_wr_o(dcache_data_wr_w)
,.mem_d_rd_o(dcache_rd_w)
,.mem_d_wr_o(dcache_wr_w)
,.mem_d_cacheable_o(dcache_cacheable_w)
,.mem_d_req_tag_o(dcache_req_tag_w)
,.mem_d_invalidate_o(dcache_invalidate_w)
,.mem_d_writeback_o(dcache_writeback_w)
,.mem_d_flush_o(dcache_flush_w)
,.mem_i_rd_o(icache_rd_w)
,.mem_i_flush_o(icache_flush_w)
,.mem_i_invalidate_o(icache_invalidate_w)
,.mem_i_pc_o(icache_pc_w)
);
icache
u_icache
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.req_rd_i(icache_rd_w)
,.req_flush_i(icache_flush_w)
,.req_invalidate_i(icache_invalidate_w)
,.req_pc_i(icache_pc_w)
,.axi_awready_i(axi_i_awready_i)
,.axi_wready_i(axi_i_wready_i)
,.axi_bvalid_i(axi_i_bvalid_i)
,.axi_bresp_i(axi_i_bresp_i)
,.axi_bid_i(axi_i_bid_i)
,.axi_arready_i(axi_i_arready_i)
,.axi_rvalid_i(axi_i_rvalid_i)
,.axi_rdata_i(axi_i_rdata_i)
,.axi_rresp_i(axi_i_rresp_i)
,.axi_rid_i(axi_i_rid_i)
,.axi_rlast_i(axi_i_rlast_i)
// Outputs
,.req_accept_o(icache_accept_w)
,.req_valid_o(icache_valid_w)
,.req_error_o(icache_error_w)
,.req_inst_o(icache_inst_w)
,.axi_awvalid_o(axi_i_awvalid_o)
,.axi_awaddr_o(axi_i_awaddr_o)
,.axi_awid_o(axi_i_awid_o)
,.axi_awlen_o(axi_i_awlen_o)
,.axi_awburst_o(axi_i_awburst_o)
,.axi_wvalid_o(axi_i_wvalid_o)
,.axi_wdata_o(axi_i_wdata_o)
,.axi_wstrb_o(axi_i_wstrb_o)
,.axi_wlast_o(axi_i_wlast_o)
,.axi_bready_o(axi_i_bready_o)
,.axi_arvalid_o(axi_i_arvalid_o)
,.axi_araddr_o(axi_i_araddr_o)
,.axi_arid_o(axi_i_arid_o)
,.axi_arlen_o(axi_i_arlen_o)
,.axi_arburst_o(axi_i_arburst_o)
,.axi_rready_o(axi_i_rready_o)
);
endmodule
|
//This module handles a single amiga audio channel. attached modes are not supported
module paula_audio_channel
(
input clk, //bus clock
input clk7_en,
input cck, //colour clock enable
input reset, //reset
input aen, //address enable
input dmaena, //dma enable
input [3:1] reg_address_in, //register address input
input [15:0] data, //bus data input
output [6:0] volume, //channel volume output
output [7:0] sample, //channel sample output
output intreq, //interrupt request
input intpen, //interrupt pending input
output reg dmareq, //dma request
output reg dmas, //dma special (restart)
input strhor //horizontal strobe
);
//register names and addresses
parameter AUDLEN = 4'h4;
parameter AUDPER = 4'h6;
parameter AUDVOL = 4'h8;
parameter AUDDAT = 4'ha;
//local signals
reg [15:0] audlen; //audio length register
reg [15:0] audper; //audio period register
reg [6:0] audvol; //audio volume register
reg [15:0] auddat; //audio data register
reg [15:0] datbuf; //audio data buffer
reg [2:0] audio_state; //audio current state
reg [2:0] audio_next; //audio next state
wire datwrite; //data register is written
reg volcntrld; //not used
reg pbufld1; //load output sample from sample buffer
reg [15:0] percnt; //audio period counter
reg percount; //decrease period counter
reg percntrld; //reload period counter
wire perfin; //period counter expired
reg [15:0] lencnt; //audio length counter
reg lencount; //decrease length counter
reg lencntrld; //reload length counter
wire lenfin; //length counter expired
reg AUDxDAT; //audio data buffer was written
wire AUDxON; //audio DMA channel is enabled
reg AUDxDR; //audio DMA request
reg AUDxIR; //audio interrupt request
wire AUDxIP; //audio interrupt is pending
reg intreq2_set;
reg intreq2_clr;
reg intreq2; //buffered interrupt request
reg dmasen; //pointer register reloading request
reg penhi; //enable high byte of sample buffer
reg silence; // AMR: disable audio if repeat length is 1
reg silence_d; // AMR: disable audio if repeat length is 1
reg dmaena_d;
//length register bus write
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
audlen[15:0] <= 16'h00_00;
else if (aen && (reg_address_in[3:1]==AUDLEN[3:1]))
audlen[15:0] <= data[15:0];
end
end
//period register bus write
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
audper[15:0] <= 16'h00_00;
else if (aen && (reg_address_in[3:1]==AUDPER[3:1]))
audper[15:0] <= data[15:0];
end
end
//volume register bus write
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
audvol[6:0] <= 7'b000_0000;
else if (aen && (reg_address_in[3:1]==AUDVOL[3:1]))
audvol[6:0] <= data[6:0];
end
end
//data register strobe
assign datwrite = (aen && (reg_address_in[3:1]==AUDDAT[3:1])) ? 1'b1 : 1'b0;
//data register bus write
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
auddat[15:0] <= 16'h00_00;
else if (datwrite)
auddat[15:0] <= data[15:0];
end
end
always @(posedge clk) begin
if (clk7_en) begin
if (datwrite)
AUDxDAT <= 1'b1;
else if (cck)
AUDxDAT <= 1'b0;
end
end
assign AUDxON = dmaena; //dma enable
assign AUDxIP = intpen; //audio interrupt pending
assign intreq = AUDxIR; //audio interrupt request
//period counter
always @(posedge clk) begin
if (clk7_en) begin
if (percntrld && cck)//load period counter from audio period register
percnt[15:0] <= audper[15:0];
else if (percount && cck)//period counter count down
percnt[15:0] <= percnt[15:0] - 16'd1;
end
end
assign perfin = (percnt[15:0]==1 && cck) ? 1'b1 : 1'b0;
//length counter
always @(posedge clk) begin
if (clk7_en) begin
if (lencntrld && cck) begin //load length counter from audio length register
lencnt[15:0] <= (audlen[15:0]);
silence<=1'b0;
if(audlen==1 || audlen==0)
silence<=1'b1;
end else if (lencount && cck)//length counter count down
lencnt[15:0] <= (lencnt[15:0] - 1);
// Silence fix
dmaena_d<=dmaena;
if(dmaena_d==1'b1 && dmaena==1'b0) begin
silence_d<=1'b1; // Prevent next write from unsilencing the channel.
silence<=1'b1;
end
if(AUDxDAT && cck) // Unsilence the channel if the CPU writes to AUDxDAT
if(silence_d)
silence_d<=1'b0;
else
silence<=1'b0;
end
end
assign lenfin = (lencnt[15:0]==1 && cck) ? 1'b1 : 1'b0;
//audio buffer
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
datbuf[15:0] <= 16'h00_00;
else if (pbufld1 && cck)
datbuf[15:0] <= auddat[15:0];
end
end
//assign sample[7:0] = penhi ? datbuf[15:8] : datbuf[7:0];
assign sample[7:0] = silence ? 8'b0 : (penhi ? datbuf[15:8] : datbuf[7:0]);
//volume output
assign volume[6:0] = audvol[6:0];
//dma request logic
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
begin
dmareq <= 1'b0;
dmas <= 1'b0;
end
else if (AUDxDR && cck)
begin
dmareq <= 1'b1;
dmas <= dmasen | lenfin;
end
else if (strhor) //dma request are cleared when transfered to Agnus
begin
dmareq <= 1'b0;
dmas <= 1'b0;
end
end
end
//buffered interrupt request
always @(posedge clk) begin
if (clk7_en) begin
if (cck)
if (intreq2_set)
intreq2 <= 1'b1;
else if (intreq2_clr)
intreq2 <= 1'b0;
end
end
//audio states
parameter AUDIO_STATE_0 = 3'b000;
parameter AUDIO_STATE_1 = 3'b001;
parameter AUDIO_STATE_2 = 3'b011;
parameter AUDIO_STATE_3 = 3'b010;
parameter AUDIO_STATE_4 = 3'b110;
//audio channel state machine
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
audio_state <= AUDIO_STATE_0;
else if (cck)
audio_state <= audio_next;
end
end
//transition function
always @(*) begin
case (audio_state)
AUDIO_STATE_0: //audio FSM idle state
begin
intreq2_clr = 1'b1;
intreq2_set = 1'b0;
lencount = 1'b0;
penhi = 1'b0;
percount = 1'b0;
percntrld = 1'b1;
if (AUDxON) //start of DMA driven audio playback
begin
audio_next = AUDIO_STATE_1;
AUDxDR = 1'b1;
AUDxIR = 1'b0;
dmasen = 1'b1;
lencntrld = 1'b1;
pbufld1 = 1'b0;
volcntrld = 1'b0;
end
else if (AUDxDAT && !AUDxON && !AUDxIP) //CPU driven audio playback
begin
audio_next = AUDIO_STATE_3;
AUDxDR = 1'b0;
AUDxIR = 1'b1;
dmasen = 1'b0;
lencntrld = 1'b0;
pbufld1 = 1'b1;
volcntrld = 1'b1;
end
else
begin
audio_next = AUDIO_STATE_0;
AUDxDR = 1'b0;
AUDxIR = 1'b0;
dmasen = 1'b0;
lencntrld = 1'b0;
pbufld1 = 1'b0;
volcntrld = 1'b0;
end
end
AUDIO_STATE_1: //audio DMA has been enabled
begin
dmasen = 1'b0;
intreq2_clr = 1'b1;
intreq2_set = 1'b0;
lencntrld = 1'b0;
penhi = 1'b0;
percount = 1'b0;
if (AUDxON && AUDxDAT) //requested data has arrived
begin
audio_next = AUDIO_STATE_2;
AUDxDR = 1'b1;
AUDxIR = 1'b1;
lencount = ~lenfin;
pbufld1 = 1'b0; //first data received, discard it since first data access is used to reload pointer
percntrld = 1'b0;
volcntrld = 1'b0;
end
else if (!AUDxON) //audio DMA has been switched off so go to IDLE state
begin
audio_next = AUDIO_STATE_0;
AUDxDR = 1'b0;
AUDxIR = 1'b0;
lencount = 1'b0;
pbufld1 = 1'b0;
percntrld = 1'b0;
volcntrld = 1'b0;
end
else
begin
audio_next = AUDIO_STATE_1;
AUDxDR = 1'b0;
AUDxIR = 1'b0;
lencount = 1'b0;
pbufld1 = 1'b0;
percntrld = 1'b0;
volcntrld = 1'b0;
end
end
AUDIO_STATE_2: //audio DMA has been enabled
begin
dmasen = 1'b0;
intreq2_clr = 1'b1;
intreq2_set = 1'b0;
lencntrld = 1'b0;
penhi = 1'b0;
percount = 1'b0;
if (AUDxON && AUDxDAT) //requested data has arrived
begin
audio_next = AUDIO_STATE_3;
AUDxDR = 1'b1;
AUDxIR = 1'b0;
lencount = ~lenfin;
pbufld1 = 1'b1; //new data has been just received so put it in the output buffer
percntrld = 1'b1;
volcntrld = 1'b1;
end
else if (!AUDxON) //audio DMA has been switched off so go to IDLE state
begin
audio_next = AUDIO_STATE_0;
AUDxDR = 1'b0;
AUDxIR = 1'b0;
lencount = 1'b0;
pbufld1 = 1'b0;
percntrld = 1'b0;
volcntrld = 1'b0;
end
else
begin
audio_next = AUDIO_STATE_2;
AUDxDR = 1'b0;
AUDxIR = 1'b0;
lencount = 1'b0;
pbufld1 = 1'b0;
percntrld = 1'b0;
volcntrld = 1'b0;
end
end
AUDIO_STATE_3: //first sample is being output
begin
AUDxDR = 1'b0;
AUDxIR = 1'b0;
dmasen = 1'b0;
intreq2_clr = 1'b0;
intreq2_set = lenfin & AUDxON & AUDxDAT;
lencount = ~lenfin & AUDxON & AUDxDAT;
lencntrld = lenfin & AUDxON & AUDxDAT;
pbufld1 = 1'b0;
penhi = 1'b1;
volcntrld = 1'b0;
if (perfin) //if period counter expired output other sample from buffer
begin
audio_next = AUDIO_STATE_4;
percount = 1'b0;
percntrld = 1'b1;
end
else
begin
audio_next = AUDIO_STATE_3;
percount = 1'b1;
percntrld = 1'b0;
end
end
AUDIO_STATE_4: //second sample is being output
begin
dmasen = 1'b0;
intreq2_set = lenfin & AUDxON & AUDxDAT;
lencount = ~lenfin & AUDxON & AUDxDAT;
lencntrld = lenfin & AUDxON & AUDxDAT;
penhi = 1'b0;
volcntrld = 1'b0;
if (perfin && (AUDxON || !AUDxIP)) //period counter expired and audio DMA active
begin
audio_next = AUDIO_STATE_3;
AUDxDR = AUDxON;
AUDxIR = (intreq2 & AUDxON) | ~AUDxON;
intreq2_clr = intreq2;
pbufld1 = 1'b1;
percount = 1'b0;
percntrld = 1'b1;
end
else if (perfin && !AUDxON && AUDxIP) //period counter expired and audio DMA inactive
begin
audio_next = AUDIO_STATE_0;
AUDxDR = 1'b0;
AUDxIR = 1'b0;
intreq2_clr = 1'b0;
pbufld1 = 1'b0;
percount = 1'b0;
percntrld = 1'b0;
end
else
begin
audio_next = AUDIO_STATE_4;
AUDxDR = 1'b0;
AUDxIR = 1'b0;
intreq2_clr = 1'b0;
pbufld1 = 1'b0;
percount = 1'b1;
percntrld = 1'b0;
end
end
default:
begin
audio_next = AUDIO_STATE_0;
AUDxDR = 1'b0;
AUDxIR = 1'b0;
dmasen = 1'b0;
intreq2_clr = 1'b0;
intreq2_set = 1'b0;
lencntrld = 1'b0;
lencount = 1'b0;
pbufld1 = 1'b0;
penhi = 1'b0;
percount = 1'b0;
percntrld = 1'b0;
volcntrld = 1'b0;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__AND3B_BEHAVIORAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_BEHAVIORAL_V |
// -----------------------------------------------------------------------
//
// Copyright 2010 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
`include "../../shared/rtl/soclib/pipeconnect.h"
module toplevel(input clk, // 16 MHz
output reg [ 7:0] led,
output ram_lb_n,
output ram_ub_n,
inout [15:0] ram_data,
output ram_oe_n,
output ram_ce1_n,
output ram_we_n,
output ram_ce2,
output [17:0] ram_addr,
input rxd,
output txd
// input exp_rst_n,
// input exp_pres,
// inout [3:32] X202
);
parameter FREQ = 27'd50000000; // 27-bit is enough for 268 MHz
parameter BPS = 230400;
wire reset_button = 0 /*~exp_rst_n*/;
reg [26:0] rst_counter = FREQ;
wire reset = ~rst_counter[26];
wire clock;
wire clock_locked;
wire [ 7:0] rs232out_d;
wire rs232out_w;
wire rs232out_busy;
wire [ 7:0] rs232in_data;
wire rs232in_attention;
wire mem_waitrequest;
wire [ 1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [ 3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [ 1:0] mem_readdataid;
wire `REQ rs232_req;
wire `RES rs232_res;
always @(posedge clock)
if (rs232out_w)
led <= ~rs232out_d;
else if (rs232in_attention)
led <= ~rs232in_data;
always @(posedge clock)
if (reset_button | ~clock_locked)
rst_counter <= FREQ; // 1 sec delay
else if (~rst_counter[26])
rst_counter <= rst_counter - 1'd1;
// Actually, just a 1-1 clock filter at this point
pll pll_inst (
.inclk0 ( clk ),
.c0 ( clock ),
.locked ( clock_locked )
);
yari yari_inst
(.clock(clock)
,.rst(reset)
// Inputs
,.mem_waitrequest (mem_waitrequest)
,.mem_readdata (mem_readdata)
,.mem_readdataid (mem_readdataid)
// Outputs
,.mem_id (mem_id)
,.mem_address (mem_address)
,.mem_read (mem_read)
,.mem_write (mem_write)
,.mem_writedata (mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
defparam yari_inst.FREQ = FREQ;
assign ram_ce2 = 1;
sram16_ctrl sram16_ctrl_inst
(.clock(clock)
,.rst(reset)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.sram_a(ram_addr)
,.sram_d(ram_data)
,.sram_cs_n(ram_ce1_n)
,.sram_be_n({ram_ub_n,ram_lb_n})
,.sram_oe_n(ram_oe_n)
,.sram_we_n(ram_we_n)
);
defparam sram16_ctrl_inst.FREQ = FREQ;
rs232out rs232out_inst
(.clock(clock),
.serial_out(txd),
.transmit_data(rs232out_d),
.we(rs232out_w),
.busy(rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock(clock),
.serial_in(rxd),
.received_data(rs232in_data),
.attention(rs232in_attention));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
rs232 rs232_inst(.clk(clock),
.rst(reset),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_attention),
.rs232in_data(rs232in_data),
.rs232out_busy(rs232out_busy),
.rs232out_w(rs232out_w),
.rs232out_d(rs232out_d));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_TB_V
`define SKY130_FD_SC_HS__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_BEHAVIORAL_V
`define SKY130_FD_SC_HS__FAH_BEHAVIORAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_TB_V
`define SKY130_FD_SC_MS__NOR3B_TB_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__nor3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_TB_V
|
// A parameterized, inferable, true dual-port, dual-clock block RAM in Verilog.
// Thanks to Dan Strother - http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
module dp_ram #(
parameter DATA = 16,
parameter ADDR = 10
) (
// Port A
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
// Port A
always @(posedge a_clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_LP_V
`define SKY130_FD_SC_LP__SDFXBP_LP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxbp_lp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_PP_BLACKBOX_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb16to1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input [15:0] D ;
input [15:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_PP_BLACKBOX_V
|
//
// 8192 bytes, 32bit interface
`timescale 1ns/1ps
module bb_ram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [12:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
wire [3:0] dip;
RAMB16_S9_altera ram0 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[7:0] ),
.rden ( en ),
.wren ( we[0] ),
.q ( data_out[7:0] )
);
defparam ram0.altsyncram_component.init_file = "bb_ram0.mif";
RAMB16_S9_altera ram1 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[15:8] ),
.rden ( en ),
.wren ( we[1] ),
.q ( data_out[15:8] )
);
defparam ram1.altsyncram_component.init_file = "bb_ram1.mif";
RAMB16_S9_altera ram2 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[23:16] ),
.rden ( en ),
.wren ( we[2] ),
.q ( data_out[23:16] )
);
defparam ram2.altsyncram_component.init_file = "bb_ram2.mif";
RAMB16_S9_altera ram3 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[31:24] ),
.rden ( en ),
.wren ( we[3] ),
.q ( data_out[31:24] )
);
defparam ram3.altsyncram_component.init_file = "bb_ram3.mif";
endmodule
|
/*
Name: ClockRecoverSetCounter
Attempts to recover a clock from a serial signal whose frequency is known, set,
and equal to system clock frequency divided by some integer. Reclocked serial
data is then output along with a clock strobe.
Faster is pretty much always better for this type of function, so the clock
recovery system runs at system clock.
Target frequency is set by setting the TARGET_PERIOD value such that
f_target = f_clk / TARGET_PERIOD
*/
module ClkRecoverSetCounter #(
parameter TARGET_PERIOD = 10 ///< Expected # clks for recovered clock
)
(
// Inputs
input clk, ///< System clock
input rst, ///< Reset, synchronous and active high
input rx, ///< Input serial signal
// Outputs
output reg clkStrobe, ///< Recovered clock strobe
output reg rxClocked ///< Synchronized rx data
);
parameter PHASE_HIGH = $clog2(TARGET_PERIOD-1) - 1;
wire intClk; ///< Internal clock
reg [PHASE_HIGH:0] phaseAccum; ///< Phase accumulator for internal clock
reg intClkD1; ///< intClk delayed 1 clk
reg rxD1; ///< rx delayed 1 clk
reg started; ///< Goes high once first edge found
// Debug
wire refClk;
reg isZero;
assign refClk = (phaseAccum == 'd0) && ~isZero;
always @(posedge clk) begin
isZero <= phaseAccum == 'd0;
end
assign intClk = (phaseAccum == (TARGET_PERIOD>>1));
always @(posedge clk) begin
rxD1 <= rx;
intClkD1 <= intClk;
clkStrobe <= intClk & ~intClkD1;
rxClocked <= (intClk & ~intClkD1) ? rx : rxClocked;
end
// Phase accumulator and tracking loop
always @(posedge clk) begin
if (rst) begin
phaseAccum <= 'd0;
started <= 1'b0;
end
else begin
if (started) begin
// Phase lag - increase phase to catch up
if ((rxD1 ^ rx) && (phaseAccum >= (TARGET_PERIOD>>1))) begin
if (phaseAccum == TARGET_PERIOD-1) begin
phaseAccum <= 'd1;
end
else if (phaseAccum == TARGET_PERIOD-2) begin
phaseAccum <= 'd0;
end
else begin
phaseAccum <= phaseAccum + 2'd2;
end
end
// Phase lead - don't increment phase to slow down
else if ((rxD1 ^ rx) && (phaseAccum != 'd0)) begin
phaseAccum <= phaseAccum;
end
// In phase but lagging
else if (phaseAccum == TARGET_PERIOD-1) begin
phaseAccum <= 'd0;
end
else begin
phaseAccum <= phaseAccum + 2'd1;
end
end
else begin
started <= rxD1 ^ rx;
phaseAccum <= 'd0;
end
end
end
endmodule
|
(** * Types: Type Systems *)
Require Export Smallstep.
Hint Constructors multi.
(** Our next major topic is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and numbers, to introduce the basic
ideas of types, typing rules, and the fundamental theorems about
type systems: _type preservation_ and _progress_. Then we'll move
on to the _simply typed lambda-calculus_, which lives at the core
of every modern functional programming language (including
Coq). *)
(* ###################################################################### *)
(** * Typed Arithmetic Expressions *)
(** To motivate the discussion of type systems, let's begin as
usual with an extremely simple toy language. We want it to have
the potential for programs "going wrong" because of runtime type
errors, so we need something a tiny bit more complex than the
language of constants and addition that we used in chapter
[Smallstep]: a single kind of data (just numbers) is too simple,
but just two kinds (numbers and booleans) already gives us enough
material to tell an interesting story.
The language definition is completely routine. The only thing to
notice is that we are _not_ using the [asnum]/[aslist] trick that
we used in chapter [HoareList] to make all the operations total by
forcibly coercing the arguments to [+] (for example) into numbers.
Instead, we simply let terms get stuck if they try to use an
operator with the wrong kind of operands: the [step] relation
doesn't relate them to anything. *)
(* ###################################################################### *)
(** ** Syntax *)
(** Informally:
t ::= true
| false
| if t then t else t
| 0
| succ t
| pred t
| iszero t
Formally:
*)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tzero : tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tiszero : tm -> tm.
(** _Values_ are [true], [false], and numeric values... *)
Inductive bvalue : tm -> Prop :=
| bv_true : bvalue ttrue
| bv_false : bvalue tfalse.
Inductive nvalue : tm -> Prop :=
| nv_zero : nvalue tzero
| nv_succ : forall t, nvalue t -> nvalue (tsucc t).
Definition value (t:tm) := bvalue t \/ nvalue t.
Hint Constructors bvalue nvalue.
Hint Unfold value.
Hint Unfold extend.
(* ###################################################################### *)
(** ** Operational Semantics *)
(** Informally: *)
(**
------------------------------ (ST_IfTrue)
if true then t1 else t2 ==> t1
------------------------------- (ST_IfFalse)
if false then t1 else t2 ==> t2
t1 ==> t1'
------------------------- (ST_If)
if t1 then t2 else t3 ==>
if t1' then t2 else t3
t1 ==> t1'
-------------------- (ST_Succ)
succ t1 ==> succ t1'
------------ (ST_PredZero)
pred 0 ==> 0
numeric value v1
--------------------- (ST_PredSucc)
pred (succ v1) ==> v1
t1 ==> t1'
-------------------- (ST_Pred)
pred t1 ==> pred t1'
----------------- (ST_IszeroZero)
iszero 0 ==> true
numeric value v1
-------------------------- (ST_IszeroSucc)
iszero (succ v1) ==> false
t1 ==> t1'
------------------------ (ST_Iszero)
iszero t1 ==> iszero t1'
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredZero"
| Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
(** Notice that the [step] relation doesn't care about whether
expressions make global sense -- it just checks that the operation
in the _next_ reduction step is being applied to the right kinds
of operands.
For example, the term [succ true] (i.e., [tsucc ttrue] in the
formal syntax) cannot take a step, but the almost as obviously
nonsensical term
succ (if true then true else true)
can take a step (once, before becoming stuck). *)
(* ###################################################################### *)
(** ** Normal Forms and Values *)
(** The first interesting thing about the [step] relation in this
language is that the strong progress theorem from the Smallstep
chapter fails! That is, there are terms that are normal
forms (they can't take a step) but not values (because we have not
included them in our definition of possible "results of
evaluation"). Such terms are _stuck_. *)
Notation step_normal_form := (normal_form step).
Definition stuck (t:tm) : Prop :=
step_normal_form t /\ ~ value t.
Hint Unfold stuck.
(** **** Exercise: 2 stars (some_term_is_stuck) *)
Example some_term_is_stuck :
exists t, stuck t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** However, although values and normal forms are not the same in this
language, the former set is included in the latter. This is
important because it shows we did not accidentally define things
so that some value could still take a step. *)
(** **** Exercise: 3 stars, advanced (value_is_nf) *)
(** Hint: You will reach a point in this proof where you need to
use an induction to reason about a term that is known to be a
numeric value. This induction can be performed either over the
term itself or over the evidence that it is a numeric value. The
proof goes through in either case, but you will find that one way
is quite a bit shorter than the other. For the sake of the
exercise, try to complete the proof both ways. *)
Lemma value_is_nf : forall t,
value t -> step_normal_form t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (step_deterministic) *)
(** Using [value_is_nf], we can show that the [step] relation is
also deterministic... *)
Theorem step_deterministic:
deterministic step.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(** The next critical observation about this language is that,
although there are stuck terms, they are all "nonsensical", mixing
booleans and numbers in a way that we don't even _want_ to have a
meaning. We can easily exclude such ill-typed terms by defining a
_typing relation_ that relates terms to the types (either numeric
or boolean) of their final results. *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty.
(** In informal notation, the typing relation is often written
[|- t \in T], pronounced "[t] has type [T]." The [|-] symbol is
called a "turnstile". (Below, we're going to see richer typing
relations where an additional "context" argument is written to the
left of the turnstile. Here, the context is always empty.) *)
(**
---------------- (T_True)
|- true \in Bool
----------------- (T_False)
|- false \in Bool
|- t1 \in Bool |- t2 \in T |- t3 \in T
-------------------------------------------- (T_If)
|- if t1 then t2 else t3 \in T
------------ (T_Zero)
|- 0 \in Nat
|- t1 \in Nat
------------------ (T_Succ)
|- succ t1 \in Nat
|- t1 \in Nat
------------------ (T_Pred)
|- pred t1 \in Nat
|- t1 \in Nat
--------------------- (T_IsZero)
|- iszero t1 \in Bool
*)
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
where "'|-' t '\in' T" := (has_type t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Iszero" ].
Hint Constructors has_type.
(* ###################################################################### *)
(** *** Examples *)
(** It's important to realize that the typing relation is a
_conservative_ (or _static_) approximation: it does not calculate
the type of the normal form of a term. *)
Example has_type_1 :
|- tif tfalse tzero (tsucc tzero) \in TNat.
Proof.
apply T_If.
apply T_False.
apply T_Zero.
apply T_Succ.
apply T_Zero.
Qed.
(** (Since we've included all the constructors of the typing relation
in the hint database, the [auto] tactic can actually find this
proof automatically.) *)
Example has_type_not :
~ (|- tif tfalse tzero ttrue \in TBool).
Proof.
intros Contra. solve by inversion 2. Qed.
(** **** Exercise: 1 star, optional (succ_hastype_nat__hastype_nat) *)
Example succ_hastype_nat__hastype_nat : forall t,
|- tsucc t \in TNat ->
|- t \in TNat.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Canonical forms *)
(** The following two lemmas capture the basic property that defines
the shape of well-typed values. They say that the definition of value
and the typing relation agree. *)
Lemma bool_canonical : forall t,
|- t \in TBool -> value t -> bvalue t.
Proof.
intros t HT HV.
inversion HV; auto.
induction H; inversion HT; auto.
Qed.
Lemma nat_canonical : forall t,
|- t \in TNat -> value t -> nvalue t.
Proof.
intros t HT HV.
inversion HV.
inversion H; subst; inversion HT.
auto.
Qed.
(* ###################################################################### *)
(** ** Progress *)
(** The typing relation enjoys two critical properties. The first is
that well-typed normal forms are values (i.e., not stuck). *)
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
(** **** Exercise: 3 stars (finish_progress) *)
(** Complete the formal proof of the [progress] property. (Make sure
you understand the informal proof fragment in the following
exercise before starting -- this will save you a lot of time.) *)
Proof with auto.
intros t T HT.
has_type_cases (induction HT) Case...
(* The cases that were obviously values, like T_True and
T_False, were eliminated immediately by auto *)
Case "T_If".
right. inversion IHHT1; clear IHHT1.
SCase "t1 is a value".
apply (bool_canonical t1 HT1) in H.
inversion H; subst; clear H.
exists t2...
exists t3...
SCase "t1 can take a step".
inversion H as [t1' H1].
exists (tif t1' t2 t3)...
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_progress_informal) *)
(** Complete the corresponding informal proof: *)
(** _Theorem_: If [|- t \in T], then either [t] is a value or else
[t ==> t'] for some [t']. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T]. By the IH, either [t1] is a value or else [t1] can step
to some [t1'].
- If [t1] is a value, then by the canonical forms lemmas
and the fact that [|- t1 \in Bool] we have that [t1]
is a [bvalue] -- i.e., it is either [true] or [false].
If [t1 = true], then [t] steps to [t2] by [ST_IfTrue],
while if [t1 = false], then [t] steps to [t3] by
[ST_IfFalse]. Either way, [t] can step, which is what
we wanted to show.
- If [t1] itself can take a step, then, by [ST_If], so can
[t].
(* FILL IN HERE *)
[]
*)
(** This is more interesting than the strong progress theorem that we
saw in the Smallstep chapter, where _all_ normal forms were
values. Here, a term can be stuck, but only if it is ill
typed. *)
(** **** Exercise: 1 star (step_review) *)
(** Quick review. Answer _true_ or _false_. In this language...
- Every well-typed normal form is a value.
- Every value is a normal form.
- The single-step evaluation relation is
a partial function (i.e., it is deterministic).
- The single-step evaluation relation is a _total_ function.
*)
(** [] *)
(* ###################################################################### *)
(** ** Type Preservation *)
(** The second critical property of typing is that, when a well-typed
term takes a step, the result is also a well-typed term.
This theorem is often called the _subject reduction_ property,
because it tells us what happens when the "subject" of the typing
relation is reduced. This terminology comes from thinking of
typing statements as sentences, where the term is the subject and
the type is the predicate. *)
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
(** **** Exercise: 2 stars (finish_preservation) *)
(** Complete the formal proof of the [preservation] property. (Again,
make sure you understand the informal proof fragment in the
following exercise first.) *)
Proof with auto.
intros t t' T HT HE.
generalize dependent t'.
has_type_cases (induction HT) Case;
(* every case needs to introduce a couple of things *)
intros t' HE;
(* and we can deal with several impossible
cases all at once *)
try (solve by inversion).
Case "T_If". inversion HE; subst; clear HE.
SCase "ST_IFTrue". assumption.
SCase "ST_IfFalse". assumption.
SCase "ST_If". apply T_If; try assumption.
apply IHHT1; assumption.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_preservation_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t \in T] and [t ==> t'], then [|- t' \in T]. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T].
Inspecting the rules for the small-step reduction relation and
remembering that [t] has the form [if ...], we see that the
only ones that could have been used to prove [t ==> t'] are
[ST_IfTrue], [ST_IfFalse], or [ST_If].
- If the last rule was [ST_IfTrue], then [t' = t2]. But we
know that [|- t2 \in T], so we are done.
- If the last rule was [ST_IfFalse], then [t' = t3]. But we
know that [|- t3 \in T], so we are done.
- If the last rule was [ST_If], then [t' = if t1' then t2
else t3], where [t1 ==> t1']. We know [|- t1 \in Bool] so,
by the IH, [|- t1' \in Bool]. The [T_If] rule then gives us
[|- if t1' then t2 else t3 \in T], as required.
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars (preservation_alternate_proof) *)
(** Now prove the same property again by induction on the
_evaluation_ derivation instead of on the typing derivation.
Begin by carefully reading and thinking about the first few
lines of the above proof to make sure you understand what
each one is doing. The set-up for this proof is similar, but
not exactly the same. *)
Theorem preservation' : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Type Soundness *)
(** Putting progress and preservation together, we can see that a
well-typed term can _never_ reach a stuck state. *)
Definition multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Corollary soundness : forall t t' T,
|- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T HT P. induction P; intros [R S].
destruct (progress x T HT); auto.
apply IHP. apply (preservation x y T HT H).
unfold stuck. split; auto. Qed.
(* ###################################################################### *)
(** * Aside: the [normalize] Tactic *)
(** When experimenting with definitions of programming languages in
Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t ==>*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are simple but repetitive to do by hand. Consider for
example reducing an arithmetic expression using the small-step
relation [astep]. *)
Definition amultistep st := multi (astep st).
Notation " t '/' st '==>a*' t' " := (amultistep st t t')
(at level 40, st at level 39).
Example astep_example1 :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
apply multi_step with (APlus (ANum 3) (ANum 12)).
apply AS_Plus2.
apply av_num.
apply AS_Mult.
apply multi_step with (ANum 15).
apply AS_Plus.
apply multi_refl.
Qed.
(** We repeatedly apply [multi_step] until we get to a normal
form. The proofs that the intermediate steps are possible are
simple enough that [auto], with appropriate hints, can solve
them. *)
Hint Constructors astep aval.
Example astep_example1' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each [multi_step] we print out the
current goal, so that the user can follow how the term is being
evaluated. *)
Tactic Notation "print_goal" := match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example astep_example1'' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
normalize.
(* At this point in the proof script, the Coq response shows
a trace of how the expression evaluated.
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15))
(multi (astep empty_state) (ANum 15) (ANum 15))
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate
what the normal form of a term is, by proving a goal with an
existential variable in it. *)
Example astep_example1''' : exists e',
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
(* This time, the trace will be:
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??)
(multi (astep empty_state) (ANum 15) ??)
where ?? is the variable ``guessed'' by eapply.
*)
Qed.
(** **** Exercise: 1 star (normalize_ex) *)
Theorem normalize_ex : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (normalize_ex') *)
(** For comparison, prove it using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 2 stars (subject_expansion) *)
(** Having seen the subject reduction property, it is reasonable to
wonder whether the opposity property -- subject _expansion_ --
also holds. That is, is it always the case that, if [t ==> t']
and [|- t' \in T], then [|- t \in T]? If so, prove it. If
not, give a counter-example. (You do not need to prove your
counter-example in Coq, but feel free to do so if you like.)
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (variation1) *)
(** Suppose, that we add this new rule to the typing relation:
| T_SuccBool : forall t,
|- t \in TBool ->
|- tsucc t \in TBool
Which of the following properties remain true in the presence of
this rule? For each one, write either "remains true" or
else "becomes false." If a property becomes false, give a
counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (variation2) *)
(** Suppose, instead, that we add this new rule to the [step] relation:
| ST_Funny1 : forall t2 t3,
(tif ttrue t2 t3) ==> t3
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation3) *)
(** Suppose instead that we add this rule:
| ST_Funny2 : forall t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation4) *)
(** Suppose instead that we add this rule:
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation5) *)
(** Suppose instead that we add this rule:
| T_Funny4 :
|- tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation6) *)
(** Suppose instead that we add this rule:
| T_Funny5 :
|- tpred tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 3 stars, optional (more_variations) *)
(** Make up some exercises of your own along the same lines as
the ones above. Try to find ways of selectively breaking
properties -- i.e., ways of changing the definitions that
break just one of the properties and leave the others alone.
[]
*)
(** **** Exercise: 1 star (remove_predzero) *)
(** The evaluation rule [E_PredZero] is a bit counter-intuitive: we
might feel that it makes more sense for the predecessor of zero to
be undefined, rather than being defined to be zero. Can we
achieve this simply by removing the rule from the definition of
[step]? Would doing so create any problems elsewhere?
(* FILL IN HERE *)
[] *)
(** **** Exercise: 4 stars, advanced (prog_pres_bigstep) *)
(** Suppose our evaluation relation is defined in the big-step style.
What are the appropriate analogs of the progress and preservation
properties?
(* FILL IN HERE *)
[]
*)
(* $Date: 2014-04-08 23:31:16 -0400 (Tue, 08 Apr 2014) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CLKINV_BEHAVIORAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_PP_SYMBOL_V
|
//======================================================================
//
// Module Name: WHIRLPOOL_WCIPHER_THETA
// Description: Theta function of Whirlpool W-Cipher
//
// Language: Verilog-2001
//
// Module Dependencies: none
//
// Developer: Saied H. Khayat
// URL: https://github.com/saiedhk
// Date: May 2014
//
// Copyright Notice: Free use of this library is permitted under the
// guidelines and in accordance with the MIT License (MIT).
// http://opensource.org/licenses/MIT
//
//======================================================================
`timescale 1ns/1ps
//`define DEBUG
`define PRINT_TEST_VECTORS
module WHIRLPOOL_WCIPHER_THETA (
output [7:0] B00, B01, B02, B03, B04, B05, B06, B07,
B10, B11, B12, B13, B14, B15, B16, B17,
B20, B21, B22, B23, B24, B25, B26, B27,
B30, B31, B32, B33, B34, B35, B36, B37,
B40, B41, B42, B43, B44, B45, B46, B47,
B50, B51, B52, B53, B54, B55, B56, B57,
B60, B61, B62, B63, B64, B65, B66, B67,
B70, B71, B72, B73, B74, B75, B76, B77,
input [7:0] A00, A01, A02, A03, A04, A05, A06, A07,
A10, A11, A12, A13, A14, A15, A16, A17,
A20, A21, A22, A23, A24, A25, A26, A27,
A30, A31, A32, A33, A34, A35, A36, A37,
A40, A41, A42, A43, A44, A45, A46, A47,
A50, A51, A52, A53, A54, A55, A56, A57,
A60, A61, A62, A63, A64, A65, A66, A67,
A70, A71, A72, A73, A74, A75, A76, A77
);
localparam REDPOLY = 8'h1D; // reduction polynomial (in hex representation)
//---------functions----------
function [7:0] TIMES_2 ( input [7:0] X );
TIMES_2[7:0] = ( X[7] ) ? ({X[6:0], 1'b0} ^ REDPOLY) : {X[6:0], 1'b0};
endfunction
function [7:0] TIMES_4 ( input [7:0] X );
begin
TIMES_4[7:0] = TIMES_2( TIMES_2 (X[7:0]) );
end
endfunction
function [7:0] TIMES_8 ( input [7:0] X );
begin
TIMES_8[7:0] = TIMES_2( TIMES_2 ( TIMES_2 (X[7:0]) ) );
end
endfunction
function [7:0] TIMES_5 ( input [7:0] X );
begin
TIMES_5[7:0] = TIMES_4( X[7:0] ) ^ X;
end
endfunction
function [7:0] TIMES_9 ( input [7:0] X );
begin
TIMES_9[7:0] = TIMES_8( X[7:0] ) ^ X;
end
endfunction
function [7:0] XORALL ( input [7:0] X0, X1, X2, X3, X4, X5, X6, X7 );
begin
XORALL[7:0] = ( ( (X0 ^ X1) ^ (X2 ^ X3) ) ^ ( (X4 ^ X5) ^ (X6 ^ X7) ) );
end
endfunction
//---------combinational processes----------
// ROW 0
assign B00 = XORALL( A00 , TIMES_9(A01) , TIMES_2(A02) , TIMES_5(A03) , TIMES_8(A04) , A05 , TIMES_4(A06) , A07 );
assign B01 = XORALL( A00 , A01 , TIMES_9(A02) , TIMES_2(A03) , TIMES_5(A04) , TIMES_8(A05) , A06 , TIMES_4(A07) );
assign B02 = XORALL( TIMES_4(A00) , A01 , A02 , TIMES_9(A03) , TIMES_2(A04) , TIMES_5(A05) , TIMES_8(A06) , A07 );
assign B03 = XORALL( A00 , TIMES_4(A01) , A02 , A03 , TIMES_9(A04) , TIMES_2(A05) , TIMES_5(A06) , TIMES_8(A07) );
assign B04 = XORALL( TIMES_8(A00) , A01 , TIMES_4(A02) , A03 , A04 , TIMES_9(A05) , TIMES_2(A06) , TIMES_5(A07) );
assign B05 = XORALL( TIMES_5(A00) , TIMES_8(A01) , A02 , TIMES_4(A03) , A04 , A05 , TIMES_9(A06) , TIMES_2(A07) );
assign B06 = XORALL( TIMES_2(A00) , TIMES_5(A01) , TIMES_8(A02) , A03 , TIMES_4(A04) , A05 , A06 , TIMES_9(A07) );
assign B07 = XORALL( TIMES_9(A00) , TIMES_2(A01) , TIMES_5(A02) , TIMES_8(A03) , A04 , TIMES_4(A05) , A06 , A07 );
// ROW 1
assign B10 = XORALL( A10 , TIMES_9(A11) , TIMES_2(A12) , TIMES_5(A13) , TIMES_8(A14) , A15 , TIMES_4(A16) , A17 );
assign B11 = XORALL( A10 , A11 , TIMES_9(A12) , TIMES_2(A13) , TIMES_5(A14) , TIMES_8(A15) , A16 , TIMES_4(A17) );
assign B12 = XORALL( TIMES_4(A10) , A11 , A12 , TIMES_9(A13) , TIMES_2(A14) , TIMES_5(A15) , TIMES_8(A16) , A17 );
assign B13 = XORALL( A10 , TIMES_4(A11) , A12 , A13 , TIMES_9(A14) , TIMES_2(A15) , TIMES_5(A16) , TIMES_8(A17) );
assign B14 = XORALL( TIMES_8(A10) , A11 , TIMES_4(A12) , A13 , A14 , TIMES_9(A15) , TIMES_2(A16) , TIMES_5(A17) );
assign B15 = XORALL( TIMES_5(A10) , TIMES_8(A11) , A12 , TIMES_4(A13) , A14 , A15 , TIMES_9(A16) , TIMES_2(A17) );
assign B16 = XORALL( TIMES_2(A10) , TIMES_5(A11) , TIMES_8(A12) , A13 , TIMES_4(A14) , A15 , A16 , TIMES_9(A17) );
assign B17 = XORALL( TIMES_9(A10) , TIMES_2(A11) , TIMES_5(A12) , TIMES_8(A13) , A14 , TIMES_4(A15) , A16 , A17 );
// ROW 2
assign B20 = XORALL( A20 , TIMES_9(A21) , TIMES_2(A22) , TIMES_5(A23) , TIMES_8(A24) , A25 , TIMES_4(A26) , A27 );
assign B21 = XORALL( A20 , A21 , TIMES_9(A22) , TIMES_2(A23) , TIMES_5(A24) , TIMES_8(A25) , A26 , TIMES_4(A27) );
assign B22 = XORALL( TIMES_4(A20) , A21 , A22 , TIMES_9(A23) , TIMES_2(A24) , TIMES_5(A25) , TIMES_8(A26) , A27 );
assign B23 = XORALL( A20 , TIMES_4(A21) , A22 , A23 , TIMES_9(A24) , TIMES_2(A25) , TIMES_5(A26) , TIMES_8(A27) );
assign B24 = XORALL( TIMES_8(A20) , A21 , TIMES_4(A22) , A23 , A24 , TIMES_9(A25) , TIMES_2(A26) , TIMES_5(A27) );
assign B25 = XORALL( TIMES_5(A20) , TIMES_8(A21) , A22 , TIMES_4(A23) , A24 , A25 , TIMES_9(A26) , TIMES_2(A27) );
assign B26 = XORALL( TIMES_2(A20) , TIMES_5(A21) , TIMES_8(A22) , A23 , TIMES_4(A24) , A25 , A26 , TIMES_9(A27) );
assign B27 = XORALL( TIMES_9(A20) , TIMES_2(A21) , TIMES_5(A22) , TIMES_8(A23) , A24 , TIMES_4(A25) , A26 , A27 );
// ROW 3
assign B30 = XORALL( A30 , TIMES_9(A31) , TIMES_2(A32) , TIMES_5(A33) , TIMES_8(A34) , A35 , TIMES_4(A36) , A37 );
assign B31 = XORALL( A30 , A31 , TIMES_9(A32) , TIMES_2(A33) , TIMES_5(A34) , TIMES_8(A35) , A36 , TIMES_4(A37) );
assign B32 = XORALL( TIMES_4(A30) , A31 , A32 , TIMES_9(A33) , TIMES_2(A34) , TIMES_5(A35) , TIMES_8(A36) , A37 );
assign B33 = XORALL( A30 , TIMES_4(A31) , A32 , A33 , TIMES_9(A34) , TIMES_2(A35) , TIMES_5(A36) , TIMES_8(A37) );
assign B34 = XORALL( TIMES_8(A30) , A31 , TIMES_4(A32) , A33 , A34 , TIMES_9(A35) , TIMES_2(A36) , TIMES_5(A37) );
assign B35 = XORALL( TIMES_5(A30) , TIMES_8(A31) , A32 , TIMES_4(A33) , A34 , A35 , TIMES_9(A36) , TIMES_2(A37) );
assign B36 = XORALL( TIMES_2(A30) , TIMES_5(A31) , TIMES_8(A32) , A33 , TIMES_4(A34) , A35 , A36 , TIMES_9(A37) );
assign B37 = XORALL( TIMES_9(A30) , TIMES_2(A31) , TIMES_5(A32) , TIMES_8(A33) , A34 , TIMES_4(A35) , A36 , A37 );
// ROW 4
assign B40 = XORALL( A40 , TIMES_9(A41) , TIMES_2(A42) , TIMES_5(A43) , TIMES_8(A44) , A45 , TIMES_4(A46) , A47 );
assign B41 = XORALL( A40 , A41 , TIMES_9(A42) , TIMES_2(A43) , TIMES_5(A44) , TIMES_8(A45) , A46 , TIMES_4(A47) );
assign B42 = XORALL( TIMES_4(A40) , A41 , A42 , TIMES_9(A43) , TIMES_2(A44) , TIMES_5(A45) , TIMES_8(A46) , A47 );
assign B43 = XORALL( A40 , TIMES_4(A41) , A42 , A43 , TIMES_9(A44) , TIMES_2(A45) , TIMES_5(A46) , TIMES_8(A47) );
assign B44 = XORALL( TIMES_8(A40) , A41 , TIMES_4(A42) , A43 , A44 , TIMES_9(A45) , TIMES_2(A46) , TIMES_5(A47) );
assign B45 = XORALL( TIMES_5(A40) , TIMES_8(A41) , A42 , TIMES_4(A43) , A44 , A45 , TIMES_9(A46) , TIMES_2(A47) );
assign B46 = XORALL( TIMES_2(A40) , TIMES_5(A41) , TIMES_8(A42) , A43 , TIMES_4(A44) , A45 , A46 , TIMES_9(A47) );
assign B47 = XORALL( TIMES_9(A40) , TIMES_2(A41) , TIMES_5(A42) , TIMES_8(A43) , A44 , TIMES_4(A45) , A46 , A47 );
// ROW 5
assign B50 = XORALL( A50 , TIMES_9(A51) , TIMES_2(A52) , TIMES_5(A53) , TIMES_8(A54) , A55 , TIMES_4(A56) , A57 );
assign B51 = XORALL( A50 , A51 , TIMES_9(A52) , TIMES_2(A53) , TIMES_5(A54) , TIMES_8(A55) , A56 , TIMES_4(A57) );
assign B52 = XORALL( TIMES_4(A50) , A51 , A52 , TIMES_9(A53) , TIMES_2(A54) , TIMES_5(A55) , TIMES_8(A56) , A57 );
assign B53 = XORALL( A50 , TIMES_4(A51) , A52 , A53 , TIMES_9(A54) , TIMES_2(A55) , TIMES_5(A56) , TIMES_8(A57) );
assign B54 = XORALL( TIMES_8(A50) , A51 , TIMES_4(A52) , A53 , A54 , TIMES_9(A55) , TIMES_2(A56) , TIMES_5(A57) );
assign B55 = XORALL( TIMES_5(A50) , TIMES_8(A51) , A52 , TIMES_4(A53) , A54 , A55 , TIMES_9(A56) , TIMES_2(A57) );
assign B56 = XORALL( TIMES_2(A50) , TIMES_5(A51) , TIMES_8(A52) , A53 , TIMES_4(A54) , A55 , A56 , TIMES_9(A57) );
assign B57 = XORALL( TIMES_9(A50) , TIMES_2(A51) , TIMES_5(A52) , TIMES_8(A53) , A54 , TIMES_4(A55) , A56 , A57 );
// ROW 6
assign B60 = XORALL( A60 , TIMES_9(A61) , TIMES_2(A62) , TIMES_5(A63) , TIMES_8(A64) , A65 , TIMES_4(A66) , A67 );
assign B61 = XORALL( A60 , A61 , TIMES_9(A62) , TIMES_2(A63) , TIMES_5(A64) , TIMES_8(A65) , A66 , TIMES_4(A67) );
assign B62 = XORALL( TIMES_4(A60) , A61 , A62 , TIMES_9(A63) , TIMES_2(A64) , TIMES_5(A65) , TIMES_8(A66) , A67 );
assign B63 = XORALL( A60 , TIMES_4(A61) , A62 , A63 , TIMES_9(A64) , TIMES_2(A65) , TIMES_5(A66) , TIMES_8(A67) );
assign B64 = XORALL( TIMES_8(A60) , A61 , TIMES_4(A62) , A63 , A64 , TIMES_9(A65) , TIMES_2(A66) , TIMES_5(A67) );
assign B65 = XORALL( TIMES_5(A60) , TIMES_8(A61) , A62 , TIMES_4(A63) , A64 , A65 , TIMES_9(A66) , TIMES_2(A67) );
assign B66 = XORALL( TIMES_2(A60) , TIMES_5(A61) , TIMES_8(A62) , A63 , TIMES_4(A64) , A65 , A66 , TIMES_9(A67) );
assign B67 = XORALL( TIMES_9(A60) , TIMES_2(A61) , TIMES_5(A62) , TIMES_8(A63) , A64 , TIMES_4(A65) , A66 , A67 );
// ROW 7
assign B70 = XORALL( A70 , TIMES_9(A71) , TIMES_2(A72) , TIMES_5(A73) , TIMES_8(A74) , A75 , TIMES_4(A76) , A77 );
assign B71 = XORALL( A70 , A71 , TIMES_9(A72) , TIMES_2(A73) , TIMES_5(A74) , TIMES_8(A75) , A76 , TIMES_4(A77) );
assign B72 = XORALL( TIMES_4(A70) , A71 , A72 , TIMES_9(A73) , TIMES_2(A74) , TIMES_5(A75) , TIMES_8(A76) , A77 );
assign B73 = XORALL( A70 , TIMES_4(A71) , A72 , A73 , TIMES_9(A74) , TIMES_2(A75) , TIMES_5(A76) , TIMES_8(A77) );
assign B74 = XORALL( TIMES_8(A70) , A71 , TIMES_4(A72) , A73 , A74 , TIMES_9(A75) , TIMES_2(A76) , TIMES_5(A77) );
assign B75 = XORALL( TIMES_5(A70) , TIMES_8(A71) , A72 , TIMES_4(A73) , A74 , A75 , TIMES_9(A76) , TIMES_2(A77) );
assign B76 = XORALL( TIMES_2(A70) , TIMES_5(A71) , TIMES_8(A72) , A73 , TIMES_4(A74) , A75 , A76 , TIMES_9(A77) );
assign B77 = XORALL( TIMES_9(A70) , TIMES_2(A71) , TIMES_5(A72) , TIMES_8(A73) , A74 , TIMES_4(A75) , A76 , A77 );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_V
`define SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapmet1 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_0_V
`define SKY130_FD_SC_LP__O22AI_0_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_0 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_0 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_BEHAVIORAL_V |
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous DDR output
*/
module ssio_ddr_out #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Use 90 degree clock for transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire clk90,
input wire [WIDTH-1:0] input_d1,
input wire [WIDTH-1:0] input_d2,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire ref_clk = USE_CLK90 == "TRUE" ? clk90 : clk;
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
)
clk_oddr_inst (
.clk(ref_clk),
.d1(1'b1),
.d2(1'b0),
.q(output_clk)
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(WIDTH)
)
data_oddr_inst (
.clk(clk),
.d1(input_d1),
.d2(input_d2),
.q(output_q)
);
endmodule
|
`ifndef INCLUDE_PARAMS
`include "params.v"
`endif
//Data Memory
module DMem(
input wire rst_n,
input wire [`WIDTH - 1:0] add,
inout wire [`WIDTH - 1:0] data,
input wire wr,
input wire rd,
output reg rd_st,
input wire [1:0] mode //mode: 0-word, 1-halfword, 2-byte
// mem trace
`ifdef TRACE_MEM
,input wire Print
`endif
);
reg [7:0] mem [0:`WIDTH - 1];
reg [`WIDTH - 1:0] data_r;
assign data = (rd == 1)? data_r : 32'bZ;
always @(posedge wr) begin
case (mode)
0: begin // word
{mem[add], mem[add+1], mem[add+2], mem[add+3]} = data;
end
1: begin // half-word
{mem[add], mem[add+1]} = data[15:0];
end
2: begin // byte
mem[add] = data[7:0];
end
endcase
end
always @(posedge rd) begin
rd_st = 0;
case (mode)
0: begin // word
data_r = {mem[add], mem[add+1], mem[add+2], mem[add+3]};
rd_st = 1;
end
1: begin // half-word
data_r = {16'b0 ,mem[add], mem[add+1]};
rd_st = 1;
end
2: begin // byte
data_r = {24'b0, mem[add]};
rd_st = 1;
end
endcase
end
always @(negedge rst_n) begin
$readmemh("data.hex", mem, 0, 20);
end
`ifdef TRACE_MEM
always @(posedge Print) begin
$writememh("data.hex", mem, 0, 20);
end
`endif
endmodule |
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module to_driver_sd_avs(
input wire clk_sys,
input wire rst,
input wire ao486_rst,
// input hdd_avalon_master
input wire [31:0] hdd_avalon_master_address,
input wire hdd_avalon_master_read,
output wire [31:0] hdd_avalon_master_readdata,
input wire hdd_avalon_master_write,
input wire [31:0] hdd_avalon_master_writedata,
output wire hdd_avalon_master_waitrequest,
output reg hdd_avalon_master_readdatavalid,
// input bios_loader
input wire [31:0] bios_loader_address,
input wire bios_loader_read,
output wire [31:0] bios_loader_readdata,
input wire bios_loader_write,
input wire [31:0] bios_loader_writedata,
output wire bios_loader_waitrequest,
input wire [3:0] bios_loader_byteenable,
// output driver_sd_avs
output wire [1:0] driver_sd_avs_address,
output wire driver_sd_avs_read,
input wire [31:0] driver_sd_avs_readdata,
output wire driver_sd_avs_write,
output wire [31:0] driver_sd_avs_writedata
);
assign driver_sd_avs_address = (~ao486_rst) ? hdd_avalon_master_address[3:2] : bios_loader_address[3:2];
assign driver_sd_avs_read = (~ao486_rst) ? hdd_avalon_master_read : bios_loader_read && bios_loader_address[31:4] == 28'h0;
assign driver_sd_avs_write = (~ao486_rst) ? hdd_avalon_master_write : bios_loader_write && bios_loader_address[31:4] == 28'h0;
assign driver_sd_avs_writedata = (~ao486_rst) ? hdd_avalon_master_writedata : bios_loader_writedata;
assign hdd_avalon_master_readdata = (~ao486_rst) ? driver_sd_avs_readdata : 0;
assign hdd_avalon_master_waitrequest = 0;
always @(posedge clk_sys) hdd_avalon_master_readdatavalid <= (~ao486_rst) ? driver_sd_avs_read : 0;
assign bios_loader_readdata = (~ao486_rst) ? 0 : driver_sd_avs_readdata;
assign bios_loader_waitrequest = 0;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:28:13 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire d_ff1_operation_out, d_ff3_sign_out, n281, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, intadd_364_CI, intadd_364_SUM_2_,
intadd_364_SUM_1_, intadd_364_SUM_0_, intadd_364_n3, intadd_364_n2,
intadd_364_n1, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461;
wire [3:1] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n975), .CK(clk), .RN(n1457), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n974), .CK(clk), .RN(n1457), .Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n973), .CK(clk), .RN(n1457), .Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n972), .CK(clk), .RN(n1457), .Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n971), .CK(clk), .RN(n1457), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n970), .CK(clk), .RN(n1457), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n969), .CK(clk), .RN(n1460), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n968), .CK(clk), .RN(n1459), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n967), .CK(clk), .RN(n1460), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n966), .CK(clk), .RN(n1459), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n965), .CK(clk), .RN(n281), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n964), .CK(clk), .RN(n281), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n963), .CK(clk), .RN(n281), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n962), .CK(clk), .RN(n281), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n961), .CK(clk), .RN(n281), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n960), .CK(clk), .RN(n281), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n959), .CK(clk), .RN(n1456), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n958), .CK(clk), .RN(n1456), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n957), .CK(clk), .RN(n1456), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n956), .CK(clk), .RN(n1456), .Q(d_ff1_Z[25])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n949), .CK(clk), .RN(n1455), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n948), .CK(clk), .RN(n1455), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n947), .CK(clk), .RN(n1455), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n946), .CK(clk), .RN(n1455), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n945), .CK(clk), .RN(n1455), .Q(d_ff_Zn[4])
);
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n940), .CK(clk), .RN(n1455), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n939), .CK(clk), .RN(n1454), .Q(d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n938), .CK(clk), .RN(n1454), .Q(d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n937), .CK(clk), .RN(n1454), .Q(d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n936), .CK(clk), .RN(n1454), .Q(d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n935), .CK(clk), .RN(n1454), .Q(d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n934), .CK(clk), .RN(n1454), .Q(d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n933), .CK(clk), .RN(n1454), .Q(d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n932), .CK(clk), .RN(n1454), .Q(d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n931), .CK(clk), .RN(n1454), .Q(d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n924), .CK(clk), .RN(n1453), .Q(d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n923), .CK(clk), .RN(n1453), .Q(d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n922), .CK(clk), .RN(n1453), .Q(d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n921), .CK(clk), .RN(n1453), .Q(d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n920), .CK(clk), .RN(n1453), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n821), .CK(clk), .RN(n1443), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n820), .CK(clk), .RN(n1443), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n819), .CK(clk), .RN(n1442), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n818), .CK(clk), .RN(n1442), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n817), .CK(clk), .RN(n1442), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n812), .CK(clk), .RN(n1442), .QN(n1060) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n811), .CK(clk), .RN(n1442), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n810), .CK(clk), .RN(n1442), .QN(n1061) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n806), .CK(clk), .RN(n1441), .QN(n1062) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1441), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1441), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n707), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n706), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n645), .CK(clk), .RN(n1439), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n644), .CK(clk), .RN(n1439), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n643), .CK(clk), .RN(n1439), .QN(n1063)
);
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n642), .CK(clk), .RN(n1439), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n795), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n794), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n793), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n792), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n791), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n790), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n789), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n788), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n787), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n786), .CK(clk), .RN(n1438), .Q(
d_ff2_Z[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n785), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n784), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n783), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n782), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n781), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n780), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n779), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n778), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n777), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n776), .CK(clk), .RN(n1437), .Q(
d_ff2_Z[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n775), .CK(clk), .RN(n1436), .Q(
d_ff2_Z[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n771), .CK(clk), .RN(n1436), .Q(
d_ff2_Z[29]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n983), .CK(clk), .RN(n1458), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n1419) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n656), .CK(clk), .RN(n1425), .Q(
d_ff2_X[24]), .QN(n1415) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(n988), .CK(clk), .RN(n1459), .Q(
cont_iter_out[1]), .QN(n1414) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n808), .CK(clk), .RN(n1441), .QN(n1412) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n982), .CK(clk), .RN(n1458), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n1411) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n984), .CK(clk), .RN(n1458), .Q(
d_ff1_operation_out), .QN(n1410) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n985), .CK(clk), .RN(n1458), .Q(
cont_var_out[0]), .QN(n1409) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(n986), .CK(clk), .RN(n1459), .Q(
cont_iter_out[3]), .QN(n1408) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n852), .CK(clk), .RN(n1449), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n851), .CK(clk), .RN(n1449), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n850), .CK(clk), .RN(n1448), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n849), .CK(clk), .RN(n1448), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n848), .CK(clk), .RN(n1448), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n847), .CK(clk), .RN(n1448), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n846), .CK(clk), .RN(n1448), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n845), .CK(clk), .RN(n1447), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n844), .CK(clk), .RN(n1447), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n843), .CK(clk), .RN(n1447), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n842), .CK(clk), .RN(n1447), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n841), .CK(clk), .RN(n1447), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n840), .CK(clk), .RN(n1446), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n839), .CK(clk), .RN(n1446), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n838), .CK(clk), .RN(n1446), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n837), .CK(clk), .RN(n1446), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n836), .CK(clk), .RN(n1446), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n835), .CK(clk), .RN(n1445), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n834), .CK(clk), .RN(n1445), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n832), .CK(clk), .RN(n1445), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n831), .CK(clk), .RN(n1445), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n830), .CK(clk), .RN(n1444), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n829), .CK(clk), .RN(n1444), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n828), .CK(clk), .RN(n1444), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n827), .CK(clk), .RN(n1444), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n826), .CK(clk), .RN(n1444), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n825), .CK(clk), .RN(n1443), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n824), .CK(clk), .RN(n1443), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n823), .CK(clk), .RN(n1443), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n822), .CK(clk), .RN(n1443), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n833), .CK(clk), .RN(n1445), .Q(
data_output[20]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n768), .CK(clk), .RN(n1436), .Q(
d_ff3_sign_out) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(n721), .CK(clk), .RN(n1431), .Q(
d_ff2_Y[23]), .QN(n1417) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n1458), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n1460), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n1458), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(n987), .CK(clk), .RN(n1076), .Q(n1422),
.QN(n1413) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(n652), .CK(clk), .RN(n1425), .Q(
d_ff2_X[28]), .QN(n1420) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n989), .CK(clk), .RN(n1460), .Q(n1064),
.QN(n1423) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n653), .CK(clk), .RN(n1425), .Q(
d_ff2_X[27]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n1458), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n1078), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n1416) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n754), .CK(clk), .RN(n1434), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n676), .CK(clk), .RN(n1427), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n722), .CK(clk), .RN(n1431), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n647), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_x_out[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1427), .Q(
d_ff2_X[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n925), .CK(clk), .RN(n1453), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n976), .CK(clk), .RN(n1457), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n648), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_x_out[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n799), .CK(clk), .RN(n1439), .Q(
d_ff2_Z[1]) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n717), .CK(clk), .RN(n1431), .Q(
d_ff2_Y[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n657), .CK(clk), .RN(n1425), .Q(
d_ff2_X[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n715), .CK(clk), .RN(n1430), .Q(
d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n718), .CK(clk), .RN(n1431), .Q(
d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1431), .Q(
d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n720), .CK(clk), .RN(n1431), .Q(
d_ff2_Y[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n769), .CK(clk), .RN(n1436), .Q(
d_ff2_Z[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n714), .CK(clk), .RN(n1430), .Q(
d_ff2_Y[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n859), .CK(clk), .RN(n1444), .Q(d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n860), .CK(clk), .RN(n1444), .Q(d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n865), .CK(clk), .RN(n1445), .Q(d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n866), .CK(clk), .RN(n1445), .Q(d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n868), .CK(clk), .RN(n1446), .Q(d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n869), .CK(clk), .RN(n1446), .Q(d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n871), .CK(clk), .RN(n1446), .Q(d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n872), .CK(clk), .RN(n1446), .Q(d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n873), .CK(clk), .RN(n1447), .Q(d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n875), .CK(clk), .RN(n1447), .Q(d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n856), .CK(clk), .RN(n1443), .Q(d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n857), .CK(clk), .RN(n1443), .Q(d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n858), .CK(clk), .RN(n1444), .Q(d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n861), .CK(clk), .RN(n1444), .Q(d_ff_Xn[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n705), .CK(clk), .RN(n1430), .Q(
d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n723), .CK(clk), .RN(n1431), .Q(
d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n725), .CK(clk), .RN(n1431), .Q(
d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n727), .CK(clk), .RN(n1432), .Q(
d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n729), .CK(clk), .RN(n1432), .Q(
d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n731), .CK(clk), .RN(n1432), .Q(
d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n733), .CK(clk), .RN(n1432), .Q(
d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n735), .CK(clk), .RN(n1432), .Q(
d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n737), .CK(clk), .RN(n1433), .Q(
d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1433), .Q(
d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n741), .CK(clk), .RN(n1433), .Q(
d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n743), .CK(clk), .RN(n1433), .Q(
d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n745), .CK(clk), .RN(n1433), .Q(
d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n747), .CK(clk), .RN(n1434), .Q(
d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n749), .CK(clk), .RN(n1434), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n751), .CK(clk), .RN(n1434), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n753), .CK(clk), .RN(n1434), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n755), .CK(clk), .RN(n1434), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n757), .CK(clk), .RN(n1435), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n759), .CK(clk), .RN(n1435), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n761), .CK(clk), .RN(n1435), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n763), .CK(clk), .RN(n1435), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1435), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n767), .CK(clk), .RN(n1436), .Q(
d_ff2_Y[0]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n863), .CK(clk), .RN(n1445), .Q(d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n864), .CK(clk), .RN(n1445), .Q(d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n867), .CK(clk), .RN(n1445), .Q(d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n870), .CK(clk), .RN(n1446), .Q(d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n874), .CK(clk), .RN(n1447), .Q(d_ff_Xn[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n687), .CK(clk), .RN(n1428), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n695), .CK(clk), .RN(n1429), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n703), .CK(clk), .RN(n1430), .Q(
d_ff2_X[0]) );
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n889), .CK(clk), .RN(n1449), .Q(d_ff_Yn[28]) );
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n894), .CK(clk), .RN(n1450), .Q(d_ff_Yn[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n650), .CK(clk), .RN(n1425), .Q(
d_ff2_X[30]) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n814), .CK(clk), .RN(n1442), .Q(
d_ff3_LUT_out[7]) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n816), .CK(clk), .RN(n1442), .Q(
d_ff3_LUT_out[5]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n1459), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n774), .CK(clk), .RN(n1436), .Q(
d_ff2_Z[26]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n798), .CK(clk), .RN(n1439), .Q(
d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n772), .CK(clk), .RN(n1436), .Q(
d_ff2_Z[28]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n815), .CK(clk), .RN(n1442), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n716), .CK(clk), .RN(n1431), .Q(
d_ff2_Y[28]), .QN(n1421) );
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n917), .CK(clk), .RN(n1452), .Q(d_ff_Yn[0])
);
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n916), .CK(clk), .RN(n1452), .Q(d_ff_Yn[1])
);
DFFRX1TS d_ff4_Yn_Q_reg_2_ ( .D(n915), .CK(clk), .RN(n1452), .Q(d_ff_Yn[2])
);
DFFRX1TS d_ff4_Yn_Q_reg_3_ ( .D(n914), .CK(clk), .RN(n1452), .Q(d_ff_Yn[3])
);
DFFRX1TS d_ff4_Yn_Q_reg_4_ ( .D(n913), .CK(clk), .RN(n1452), .Q(d_ff_Yn[4])
);
DFFRX1TS d_ff4_Yn_Q_reg_5_ ( .D(n912), .CK(clk), .RN(n1452), .Q(d_ff_Yn[5])
);
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n911), .CK(clk), .RN(n1452), .Q(d_ff_Yn[6])
);
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n910), .CK(clk), .RN(n1452), .Q(d_ff_Yn[7])
);
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n909), .CK(clk), .RN(n1451), .Q(d_ff_Yn[8])
);
DFFRX1TS d_ff4_Yn_Q_reg_9_ ( .D(n908), .CK(clk), .RN(n1451), .Q(d_ff_Yn[9])
);
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n887), .CK(clk), .RN(n1449), .Q(d_ff_Yn[30]) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n886), .CK(clk), .RN(n1449), .Q(d_ff_Yn[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n659), .CK(clk), .RN(n1426), .Q(
d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n641), .CK(clk), .RN(n1425), .Q(
d_ff2_X[31]) );
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n907), .CK(clk), .RN(n1451), .Q(d_ff_Yn[10]) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n906), .CK(clk), .RN(n1451), .Q(d_ff_Yn[11]) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n905), .CK(clk), .RN(n1451), .Q(d_ff_Yn[12]) );
DFFRX1TS d_ff4_Yn_Q_reg_13_ ( .D(n904), .CK(clk), .RN(n1451), .Q(d_ff_Yn[13]) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n903), .CK(clk), .RN(n1451), .Q(d_ff_Yn[14]) );
DFFRX1TS d_ff4_Yn_Q_reg_15_ ( .D(n902), .CK(clk), .RN(n1451), .Q(d_ff_Yn[15]) );
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n901), .CK(clk), .RN(n1451), .Q(d_ff_Yn[16]) );
DFFRX1TS d_ff4_Yn_Q_reg_17_ ( .D(n900), .CK(clk), .RN(n1451), .Q(d_ff_Yn[17]) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n899), .CK(clk), .RN(n1450), .Q(d_ff_Yn[18]) );
DFFRX1TS d_ff4_Yn_Q_reg_19_ ( .D(n898), .CK(clk), .RN(n1450), .Q(d_ff_Yn[19]) );
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n897), .CK(clk), .RN(n1450), .Q(d_ff_Yn[20]) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n896), .CK(clk), .RN(n1450), .Q(d_ff_Yn[21]) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n895), .CK(clk), .RN(n1450), .Q(d_ff_Yn[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n893), .CK(clk), .RN(n1450), .Q(d_ff_Yn[24]) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n892), .CK(clk), .RN(n1450), .Q(d_ff_Yn[25]) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n891), .CK(clk), .RN(n1450), .Q(d_ff_Yn[26]) );
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n890), .CK(clk), .RN(n1450), .Q(d_ff_Yn[27]) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n888), .CK(clk), .RN(n1449), .Q(d_ff_Yn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n862), .CK(clk), .RN(n1444), .Q(d_ff_Xn[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n773), .CK(clk), .RN(n1436), .Q(
d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n770), .CK(clk), .RN(n1436), .Q(
d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n797), .CK(clk), .RN(n1439), .Q(
d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n796), .CK(clk), .RN(n1439), .Q(
d_ff2_Z[4]) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n990), .CK(clk), .RN(n1460), .Q(
cont_var_out[1]), .QN(n1418) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n1460), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n813), .CK(clk), .RN(n1442), .Q(
d_ff3_LUT_out[8]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1441), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n1424), .CK(clk), .RN(
n1458), .Q(inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS reg_LUT_Q_reg_13_ ( .D(n809), .CK(clk), .RN(n1441), .QN(n1461) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n651), .CK(clk), .RN(n1425), .Q(
d_ff2_X[29]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n807), .CK(clk), .RN(n1441), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n752), .CK(clk), .RN(n1434), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n756), .CK(clk), .RN(n1435), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n758), .CK(clk), .RN(n1435), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n760), .CK(clk), .RN(n1435), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n762), .CK(clk), .RN(n1435), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n764), .CK(clk), .RN(n1435), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1436), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n710), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n711), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n712), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n640), .CK(clk), .RN(n1425), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n666), .CK(clk), .RN(n1426), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1427), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1427), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n674), .CK(clk), .RN(n1427), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n678), .CK(clk), .RN(n1428), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n680), .CK(clk), .RN(n1428), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n682), .CK(clk), .RN(n1428), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n684), .CK(clk), .RN(n1428), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n686), .CK(clk), .RN(n1428), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n688), .CK(clk), .RN(n1429), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n692), .CK(clk), .RN(n1429), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n694), .CK(clk), .RN(n1429), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n696), .CK(clk), .RN(n1429), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n698), .CK(clk), .RN(n1430), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n700), .CK(clk), .RN(n1430), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n702), .CK(clk), .RN(n1430), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n704), .CK(clk), .RN(n1430), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n724), .CK(clk), .RN(n1431), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n726), .CK(clk), .RN(n1432), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n728), .CK(clk), .RN(n1432), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n730), .CK(clk), .RN(n1432), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n732), .CK(clk), .RN(n1432), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n734), .CK(clk), .RN(n1432), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n736), .CK(clk), .RN(n1433), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n738), .CK(clk), .RN(n1433), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1433), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n742), .CK(clk), .RN(n1433), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n744), .CK(clk), .RN(n1433), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n746), .CK(clk), .RN(n1434), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n748), .CK(clk), .RN(n1434), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n750), .CK(clk), .RN(n1434), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n658), .CK(clk), .RN(n1426), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n660), .CK(clk), .RN(n1426), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n662), .CK(clk), .RN(n1426), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n664), .CK(clk), .RN(n1426), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1427), .Q(
d_ff3_sh_x_out[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n654), .CK(clk), .RN(n1425), .Q(
d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n655), .CK(clk), .RN(n1425), .Q(
d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n693), .CK(clk), .RN(n1429), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n697), .CK(clk), .RN(n1429), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n699), .CK(clk), .RN(n1430), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n701), .CK(clk), .RN(n1430), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n663), .CK(clk), .RN(n1426), .Q(
d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n665), .CK(clk), .RN(n1426), .Q(
d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n669), .CK(clk), .RN(n1427), .Q(
d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1427), .Q(
d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n677), .CK(clk), .RN(n1427), .Q(
d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n679), .CK(clk), .RN(n1428), .Q(
d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n683), .CK(clk), .RN(n1428), .Q(
d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n689), .CK(clk), .RN(n1429), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n691), .CK(clk), .RN(n1429), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_shift_x_Q_reg_26_ ( .D(n646), .CK(clk), .RN(n1439), .Q(
d_ff3_sh_x_out[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n667), .CK(clk), .RN(n1426), .Q(
d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1427), .Q(
d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n681), .CK(clk), .RN(n1428), .Q(
d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n685), .CK(clk), .RN(n1428), .Q(
d_ff2_X[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n918), .CK(clk), .RN(n1452), .Q(d_ff_Zn[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n919), .CK(clk), .RN(n1452), .Q(d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n926), .CK(clk), .RN(n1453), .Q(d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n927), .CK(clk), .RN(n1453), .Q(d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n928), .CK(clk), .RN(n1453), .Q(d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n930), .CK(clk), .RN(n1454), .Q(d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n941), .CK(clk), .RN(n1455), .Q(d_ff_Zn[8])
);
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1441), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_LUT_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1441), .Q(
d_ff3_LUT_out[26]) );
DFFRX1TS reg_shift_y_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_y_out[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n854), .CK(clk), .RN(n1443), .Q(d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n855), .CK(clk), .RN(n1443), .Q(d_ff_Xn[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n661), .CK(clk), .RN(n1426), .Q(
d_ff2_X[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n929), .CK(clk), .RN(n1453), .Q(d_ff_Zn[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n853), .CK(clk), .RN(n1449), .Q(
data_output[0]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n708), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_y_out[28]) );
DFFRX1TS reg_Z0_Q_reg_4_ ( .D(n977), .CK(clk), .RN(n1457), .Q(d_ff1_Z[4]) );
DFFRX1TS reg_Z0_Q_reg_3_ ( .D(n978), .CK(clk), .RN(n1457), .Q(d_ff1_Z[3]) );
DFFRX1TS reg_Z0_Q_reg_2_ ( .D(n979), .CK(clk), .RN(n1457), .Q(d_ff1_Z[2]) );
DFFRX1TS reg_Z0_Q_reg_1_ ( .D(n980), .CK(clk), .RN(n1458), .Q(d_ff1_Z[1]) );
DFFRX1TS reg_Z0_Q_reg_0_ ( .D(n981), .CK(clk), .RN(n1458), .Q(d_ff1_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n942), .CK(clk), .RN(n1455), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n943), .CK(clk), .RN(n1455), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n944), .CK(clk), .RN(n1455), .Q(d_ff_Zn[5])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n950), .CK(clk), .RN(n1456), .Q(d_ff1_Z[31])
);
DFFRX1TS reg_Z0_Q_reg_30_ ( .D(n951), .CK(clk), .RN(n1456), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n952), .CK(clk), .RN(n1456), .Q(d_ff1_Z[29])
);
DFFRX1TS reg_Z0_Q_reg_28_ ( .D(n953), .CK(clk), .RN(n1456), .Q(d_ff1_Z[28])
);
DFFRX1TS reg_Z0_Q_reg_26_ ( .D(n955), .CK(clk), .RN(n1456), .Q(d_ff1_Z[26])
);
DFFRX1TS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1440), .Q(
d_ff3_sh_x_out[23]) );
DFFRX1TS reg_shift_y_Q_reg_23_ ( .D(n713), .CK(clk), .RN(n1441), .Q(
d_ff3_sh_y_out[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n800), .CK(clk), .RN(n1439), .Q(
d_ff2_Z[0]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n876), .CK(clk), .RN(n1447), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n877), .CK(clk), .RN(n1447), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n878), .CK(clk), .RN(n1448), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n879), .CK(clk), .RN(n1448), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n880), .CK(clk), .RN(n1448), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n881), .CK(clk), .RN(n1448), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n882), .CK(clk), .RN(n1448), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n883), .CK(clk), .RN(n1449), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n884), .CK(clk), .RN(n1449), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n885), .CK(clk), .RN(n1449), .Q(d_ff_Xn[0])
);
ADDFX1TS intadd_364_U4 ( .A(d_ff2_Y[24]), .B(n1414), .CI(intadd_364_CI),
.CO(intadd_364_n3), .S(intadd_364_SUM_0_) );
ADDFX1TS intadd_364_U3 ( .A(d_ff2_Y[25]), .B(n1413), .CI(intadd_364_n3),
.CO(intadd_364_n2), .S(intadd_364_SUM_1_) );
ADDFX1TS intadd_364_U2 ( .A(d_ff2_Y[26]), .B(n1408), .CI(intadd_364_n2),
.CO(intadd_364_n1), .S(intadd_364_SUM_2_) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n690), .CK(clk), .RN(n1429), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n954), .CK(clk), .RN(n1456), .Q(d_ff1_Z[27])
);
AOI222X1TS U705 ( .A0(n1348), .A1(d_ff2_Z[29]), .B0(n1226), .B1(d_ff1_Z[29]),
.C0(d_ff_Zn[29]), .C1(n1225), .Y(n1221) );
AOI222X1TS U706 ( .A0(n1351), .A1(d_ff2_Z[24]), .B0(n1226), .B1(d_ff1_Z[24]),
.C0(d_ff_Zn[24]), .C1(n1225), .Y(n1200) );
AOI222X1TS U707 ( .A0(n1348), .A1(d_ff2_Z[23]), .B0(n1226), .B1(d_ff1_Z[23]),
.C0(d_ff_Zn[23]), .C1(n1225), .Y(n1203) );
AOI222X1TS U708 ( .A0(n1284), .A1(d_ff2_Y[8]), .B0(n1070), .B1(d_ff2_X[8]),
.C0(d_ff2_Z[8]), .C1(n1283), .Y(n1140) );
AOI222X1TS U709 ( .A0(n1284), .A1(d_ff2_Y[6]), .B0(n1133), .B1(d_ff2_X[6]),
.C0(d_ff2_Z[6]), .C1(n1283), .Y(n1146) );
AOI222X1TS U710 ( .A0(n1097), .A1(d_ff2_Y[9]), .B0(n1070), .B1(d_ff2_X[9]),
.C0(d_ff2_Z[9]), .C1(n1142), .Y(n1134) );
AOI222X1TS U711 ( .A0(n1097), .A1(d_ff2_Y[7]), .B0(n1133), .B1(d_ff2_X[7]),
.C0(d_ff2_Z[7]), .C1(n1283), .Y(n1144) );
AOI222X1TS U712 ( .A0(n1131), .A1(d_ff3_sh_x_out[25]), .B0(n1286), .B1(
d_ff3_sh_y_out[25]), .C0(d_ff3_LUT_out[25]), .C1(n1283), .Y(n1101) );
AOI222X1TS U713 ( .A0(n1131), .A1(d_ff3_sh_x_out[24]), .B0(n1286), .B1(
d_ff3_sh_y_out[24]), .C0(n1145), .C1(d_ff3_LUT_out[24]), .Y(n1104) );
AOI222X1TS U714 ( .A0(n1131), .A1(d_ff3_sh_x_out[4]), .B0(n1286), .B1(
d_ff3_sh_y_out[4]), .C0(n1145), .C1(d_ff3_LUT_out[4]), .Y(n1105) );
AOI222X1TS U715 ( .A0(n1131), .A1(d_ff3_sh_x_out[10]), .B0(n1286), .B1(
d_ff3_sh_y_out[10]), .C0(n1135), .C1(d_ff3_LUT_out[10]), .Y(n1098) );
AOI222X1TS U716 ( .A0(n1284), .A1(d_ff2_Y[5]), .B0(n1127), .B1(d_ff2_X[5]),
.C0(d_ff2_Z[5]), .C1(n1283), .Y(n1126) );
AOI222X1TS U717 ( .A0(n1097), .A1(d_ff2_Y[10]), .B0(n1127), .B1(d_ff2_X[10]),
.C0(d_ff2_Z[10]), .C1(n1135), .Y(n1128) );
AOI222X1TS U718 ( .A0(n1097), .A1(d_ff2_Y[11]), .B0(n1127), .B1(d_ff2_X[11]),
.C0(d_ff2_Z[11]), .C1(n1145), .Y(n1123) );
AOI222X1TS U719 ( .A0(n1097), .A1(d_ff2_Y[12]), .B0(n1127), .B1(d_ff2_X[12]),
.C0(d_ff2_Z[12]), .C1(n1135), .Y(n1124) );
AOI222X1TS U720 ( .A0(n1097), .A1(d_ff2_Y[14]), .B0(n1127), .B1(d_ff2_X[14]),
.C0(d_ff2_Z[14]), .C1(n1142), .Y(n1122) );
AOI222X1TS U721 ( .A0(n1110), .A1(d_ff2_Y[15]), .B0(n1127), .B1(d_ff2_X[15]),
.C0(d_ff2_Z[15]), .C1(n1135), .Y(n1121) );
AOI222X1TS U722 ( .A0(n1110), .A1(d_ff2_Y[16]), .B0(n1127), .B1(d_ff2_X[16]),
.C0(d_ff2_Z[16]), .C1(n1145), .Y(n1111) );
AOI222X1TS U723 ( .A0(n1110), .A1(d_ff2_Y[17]), .B0(n1127), .B1(d_ff2_X[17]),
.C0(d_ff2_Z[17]), .C1(n1142), .Y(n1118) );
AOI222X1TS U724 ( .A0(n1136), .A1(d_ff2_Y[18]), .B0(n1127), .B1(d_ff2_X[18]),
.C0(d_ff2_Z[18]), .C1(n1135), .Y(n1117) );
AOI222X1TS U725 ( .A0(n1136), .A1(d_ff2_Y[19]), .B0(n1127), .B1(d_ff2_X[19]),
.C0(d_ff2_Z[19]), .C1(n1145), .Y(n1114) );
AOI222X1TS U726 ( .A0(n1131), .A1(d_ff3_sh_x_out[1]), .B0(n1130), .B1(
d_ff3_sh_y_out[1]), .C0(n1145), .C1(d_ff3_LUT_out[1]), .Y(n1132) );
AOI222X1TS U727 ( .A0(n1136), .A1(d_ff3_sh_x_out[0]), .B0(n1130), .B1(
d_ff3_sh_y_out[0]), .C0(n1142), .C1(d_ff3_LUT_out[0]), .Y(n1129) );
AOI222X1TS U728 ( .A0(n1110), .A1(d_ff2_Y[13]), .B0(n1130), .B1(d_ff2_X[13]),
.C0(d_ff2_Z[13]), .C1(n1145), .Y(n1120) );
AOI222X1TS U729 ( .A0(n1136), .A1(d_ff2_Y[20]), .B0(n1130), .B1(d_ff2_X[20]),
.C0(d_ff2_Z[20]), .C1(n1135), .Y(n1125) );
AOI222X1TS U730 ( .A0(n1136), .A1(d_ff2_Y[21]), .B0(n1130), .B1(d_ff2_X[21]),
.C0(d_ff2_Z[21]), .C1(n1279), .Y(n1113) );
AOI222X1TS U731 ( .A0(n1136), .A1(d_ff2_Y[22]), .B0(n1130), .B1(d_ff2_X[22]),
.C0(d_ff2_Z[22]), .C1(n1279), .Y(n1116) );
AOI222X1TS U732 ( .A0(n1136), .A1(d_ff2_Y[25]), .B0(n1130), .B1(d_ff2_X[25]),
.C0(d_ff2_Z[25]), .C1(n1279), .Y(n1115) );
AOI222X1TS U733 ( .A0(n1131), .A1(d_ff3_sh_x_out[2]), .B0(n1133), .B1(
d_ff3_sh_y_out[2]), .C0(n1135), .C1(d_ff3_LUT_out[2]), .Y(n1106) );
OA21X2TS U734 ( .A0(n1147), .A1(ready_cordic), .B0(n1150), .Y(n1151) );
INVX2TS U735 ( .A(n1065), .Y(n1424) );
AO22XLTS U736 ( .A0(n1363), .A1(d_ff_Yn[25]), .B0(d_ff2_Y[25]), .B1(n1365),
.Y(n719) );
AO22XLTS U737 ( .A0(n1350), .A1(d_ff_Yn[1]), .B0(d_ff2_Y[1]), .B1(n1373),
.Y(n765) );
AO22XLTS U738 ( .A0(n1350), .A1(d_ff_Yn[7]), .B0(d_ff2_Y[7]), .B1(n1373),
.Y(n753) );
AO22XLTS U739 ( .A0(n1350), .A1(d_ff_Yn[13]), .B0(d_ff2_Y[13]), .B1(n1373),
.Y(n741) );
AO22XLTS U740 ( .A0(n1350), .A1(d_ff_Yn[14]), .B0(d_ff2_Y[14]), .B1(n1365),
.Y(n739) );
AO22XLTS U741 ( .A0(n1405), .A1(d_ff_Yn[15]), .B0(d_ff2_Y[15]), .B1(n1404),
.Y(n737) );
AO22XLTS U742 ( .A0(n1405), .A1(d_ff_Yn[18]), .B0(d_ff2_Y[18]), .B1(n1365),
.Y(n731) );
AO22XLTS U743 ( .A0(n1405), .A1(d_ff_Yn[19]), .B0(d_ff2_Y[19]), .B1(n1404),
.Y(n729) );
AO22XLTS U744 ( .A0(n1363), .A1(d_ff_Yn[24]), .B0(d_ff2_Y[24]), .B1(n1373),
.Y(n720) );
AO22XLTS U745 ( .A0(n1363), .A1(d_ff_Yn[26]), .B0(d_ff2_Y[26]), .B1(n1404),
.Y(n718) );
AO22XLTS U746 ( .A0(n1363), .A1(d_ff_Yn[30]), .B0(d_ff2_Y[30]), .B1(n1404),
.Y(n714) );
AO22XLTS U747 ( .A0(n1363), .A1(d_ff_Xn[4]), .B0(d_ff2_X[4]), .B1(n1373),
.Y(n695) );
AO22XLTS U748 ( .A0(n1363), .A1(d_ff_Xn[8]), .B0(d_ff2_X[8]), .B1(n1365),
.Y(n687) );
AO22XLTS U749 ( .A0(n1405), .A1(d_ff_Xn[31]), .B0(d_ff2_X[31]), .B1(n1404),
.Y(n641) );
AOI222X1TS U750 ( .A0(n1351), .A1(d_ff2_Z[31]), .B0(n1226), .B1(d_ff1_Z[31]),
.C0(d_ff_Zn[31]), .C1(n1368), .Y(n1223) );
AO22XLTS U751 ( .A0(n1366), .A1(d_ff_Xn[11]), .B0(d_ff2_X[11]), .B1(n1365),
.Y(n681) );
AO22XLTS U752 ( .A0(n1366), .A1(d_ff_Xn[15]), .B0(d_ff2_X[15]), .B1(n1404),
.Y(n673) );
AO22XLTS U753 ( .A0(n1309), .A1(result_add_subt[30]), .B0(n1308), .B1(
d_ff_Zn[30]), .Y(n919) );
AOI222X1TS U754 ( .A0(n1136), .A1(d_ff2_Y[31]), .B0(n1130), .B1(d_ff2_X[31]),
.C0(d_ff2_Z[31]), .C1(n1279), .Y(n1109) );
AOI222X1TS U755 ( .A0(n1136), .A1(d_ff2_Y[26]), .B0(n1130), .B1(d_ff2_X[26]),
.C0(d_ff2_Z[26]), .C1(n1279), .Y(n1112) );
INVX3TS U756 ( .A(n1370), .Y(n1235) );
INVX2TS U757 ( .A(n1372), .Y(n1227) );
AOI222X1TS U758 ( .A0(n1284), .A1(d_ff2_Y[1]), .B0(n1070), .B1(d_ff2_X[1]),
.C0(d_ff2_Z[1]), .C1(n1283), .Y(n1139) );
INVX2TS U759 ( .A(n1401), .Y(n1390) );
AOI222X1TS U760 ( .A0(n1136), .A1(d_ff2_Y[0]), .B0(n1070), .B1(d_ff2_X[0]),
.C0(d_ff2_Z[0]), .C1(n1142), .Y(n1137) );
AOI222X1TS U761 ( .A0(n1131), .A1(d_ff3_sh_x_out[8]), .B0(n1286), .B1(
d_ff3_sh_y_out[8]), .C0(n1142), .C1(d_ff3_LUT_out[8]), .Y(n1103) );
AOI222X1TS U762 ( .A0(n1284), .A1(d_ff2_Y[2]), .B0(n1070), .B1(d_ff2_X[2]),
.C0(d_ff2_Z[2]), .C1(n1283), .Y(n1138) );
INVX3TS U763 ( .A(n1401), .Y(n1364) );
INVX2TS U764 ( .A(n1401), .Y(n1399) );
AOI222X1TS U765 ( .A0(n1284), .A1(d_ff2_Y[4]), .B0(n1070), .B1(d_ff2_X[4]),
.C0(d_ff2_Z[4]), .C1(n1283), .Y(n1141) );
CLKBUFX3TS U766 ( .A(n1349), .Y(n1406) );
CLKBUFX3TS U767 ( .A(n1349), .Y(n1352) );
CLKBUFX3TS U768 ( .A(n1349), .Y(n1367) );
CLKBUFX3TS U769 ( .A(n1349), .Y(n1393) );
CLKBUFX3TS U770 ( .A(n1349), .Y(n1360) );
CLKBUFX3TS U771 ( .A(n1313), .Y(n1311) );
INVX2TS U772 ( .A(n1100), .Y(n1135) );
INVX1TS U773 ( .A(n1374), .Y(n1388) );
INVX3TS U774 ( .A(n1100), .Y(n1142) );
OAI211X2TS U775 ( .A0(n1422), .A1(n1288), .B0(n1256), .C0(n1339), .Y(n1332)
);
NAND3BX1TS U776 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n1072), .Y(n1065) );
CLKBUFX3TS U777 ( .A(n1322), .Y(n1324) );
NAND2BX1TS U778 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1079), .Y(n1080)
);
NOR2X1TS U779 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n1158) );
BUFX3TS U780 ( .A(n1174), .Y(n1254) );
NOR2X1TS U781 ( .A(n1287), .B(n1263), .Y(n1147) );
INVX2TS U782 ( .A(n1401), .Y(n1353) );
AO22XLTS U783 ( .A0(n1318), .A1(result_add_subt[31]), .B0(n1317), .B1(
d_ff_Yn[31]), .Y(n886) );
AO22XLTS U784 ( .A0(d_ff2_Y[28]), .A1(n1365), .B0(n1058), .B1(d_ff_Yn[28]),
.Y(n716) );
AO22XLTS U785 ( .A0(d_ff2_X[30]), .A1(n1404), .B0(n1058), .B1(d_ff_Xn[30]),
.Y(n650) );
AO22XLTS U786 ( .A0(n1363), .A1(d_ff_Yn[29]), .B0(d_ff2_Y[29]), .B1(n1373),
.Y(n715) );
AO22XLTS U787 ( .A0(n1363), .A1(d_ff_Yn[27]), .B0(d_ff2_Y[27]), .B1(n1373),
.Y(n717) );
AO22XLTS U788 ( .A0(n1327), .A1(result_add_subt[31]), .B0(n1321), .B1(
d_ff_Xn[31]), .Y(n854) );
CLKINVX3TS U789 ( .A(n1166), .Y(n1252) );
CLKINVX3TS U790 ( .A(n1166), .Y(n1188) );
CLKINVX3TS U791 ( .A(n1166), .Y(n1178) );
INVX2TS U792 ( .A(enab_cont_iter), .Y(n1287) );
OAI21XLTS U793 ( .A0(n1260), .A1(n1258), .B0(n1093), .Y(add_subt_dataB[3])
);
OAI21XLTS U794 ( .A0(n1100), .A1(n1461), .B0(n1096), .Y(add_subt_dataB[13])
);
OAI21XLTS U795 ( .A0(n1100), .A1(n1258), .B0(n1092), .Y(add_subt_dataB[16])
);
OAI21XLTS U796 ( .A0(n1260), .A1(n1412), .B0(n1094), .Y(add_subt_dataB[17])
);
AOI222X1TS U797 ( .A0(n1131), .A1(d_ff3_sh_x_out[23]), .B0(n1286), .B1(
d_ff3_sh_y_out[23]), .C0(n1145), .C1(d_ff3_LUT_out[23]), .Y(n1099) );
AO22XLTS U798 ( .A0(n1325), .A1(result_add_subt[23]), .B0(n1324), .B1(
d_ff_Xn[23]), .Y(n862) );
AO22XLTS U799 ( .A0(n1316), .A1(result_add_subt[29]), .B0(n1317), .B1(
d_ff_Yn[29]), .Y(n888) );
AO22XLTS U800 ( .A0(n1316), .A1(result_add_subt[27]), .B0(n1317), .B1(
d_ff_Yn[27]), .Y(n890) );
AO22XLTS U801 ( .A0(n1316), .A1(result_add_subt[26]), .B0(n1315), .B1(
d_ff_Yn[26]), .Y(n891) );
AO22XLTS U802 ( .A0(n1316), .A1(result_add_subt[25]), .B0(n1314), .B1(
d_ff_Yn[25]), .Y(n892) );
AO22XLTS U803 ( .A0(n1316), .A1(result_add_subt[24]), .B0(n1313), .B1(
d_ff_Yn[24]), .Y(n893) );
AO22XLTS U804 ( .A0(n1316), .A1(result_add_subt[22]), .B0(n1314), .B1(
d_ff_Yn[22]), .Y(n895) );
AO22XLTS U805 ( .A0(n1316), .A1(result_add_subt[21]), .B0(n1314), .B1(
d_ff_Yn[21]), .Y(n896) );
AO22XLTS U806 ( .A0(n1316), .A1(result_add_subt[20]), .B0(n1314), .B1(
d_ff_Yn[20]), .Y(n897) );
AO22XLTS U807 ( .A0(n1312), .A1(result_add_subt[19]), .B0(n1314), .B1(
d_ff_Yn[19]), .Y(n898) );
AO22XLTS U808 ( .A0(n1312), .A1(result_add_subt[18]), .B0(n1314), .B1(
d_ff_Yn[18]), .Y(n899) );
AO22XLTS U809 ( .A0(n1312), .A1(result_add_subt[17]), .B0(n1311), .B1(
d_ff_Yn[17]), .Y(n900) );
AO22XLTS U810 ( .A0(n1312), .A1(result_add_subt[16]), .B0(n1311), .B1(
d_ff_Yn[16]), .Y(n901) );
AO22XLTS U811 ( .A0(n1312), .A1(result_add_subt[15]), .B0(n1311), .B1(
d_ff_Yn[15]), .Y(n902) );
AO22XLTS U812 ( .A0(n1312), .A1(result_add_subt[14]), .B0(n1311), .B1(
d_ff_Yn[14]), .Y(n903) );
AO22XLTS U813 ( .A0(n1312), .A1(result_add_subt[13]), .B0(n1311), .B1(
d_ff_Yn[13]), .Y(n904) );
AO22XLTS U814 ( .A0(n1312), .A1(result_add_subt[12]), .B0(n1311), .B1(
d_ff_Yn[12]), .Y(n905) );
AO22XLTS U815 ( .A0(n1312), .A1(result_add_subt[11]), .B0(n1311), .B1(
d_ff_Yn[11]), .Y(n906) );
AO22XLTS U816 ( .A0(n1312), .A1(result_add_subt[10]), .B0(n1311), .B1(
d_ff_Yn[10]), .Y(n907) );
AO22XLTS U817 ( .A0(n1058), .A1(d_ff_Xn[22]), .B0(d_ff2_X[22]), .B1(n1365),
.Y(n659) );
AO22XLTS U818 ( .A0(n1318), .A1(result_add_subt[30]), .B0(n1317), .B1(
d_ff_Yn[30]), .Y(n887) );
AO22XLTS U819 ( .A0(n1310), .A1(result_add_subt[9]), .B0(n1311), .B1(
d_ff_Yn[9]), .Y(n908) );
AO22XLTS U820 ( .A0(n1310), .A1(result_add_subt[8]), .B0(n1311), .B1(
d_ff_Yn[8]), .Y(n909) );
AO22XLTS U821 ( .A0(n1310), .A1(result_add_subt[7]), .B0(n1315), .B1(
d_ff_Yn[7]), .Y(n910) );
AO22XLTS U822 ( .A0(n1310), .A1(result_add_subt[6]), .B0(n1315), .B1(
d_ff_Yn[6]), .Y(n911) );
AO22XLTS U823 ( .A0(n1310), .A1(result_add_subt[5]), .B0(n1315), .B1(
d_ff_Yn[5]), .Y(n912) );
AO22XLTS U824 ( .A0(n1310), .A1(result_add_subt[4]), .B0(n1315), .B1(
d_ff_Yn[4]), .Y(n913) );
AO22XLTS U825 ( .A0(n1310), .A1(result_add_subt[3]), .B0(n1315), .B1(
d_ff_Yn[3]), .Y(n914) );
AO22XLTS U826 ( .A0(n1310), .A1(result_add_subt[2]), .B0(n1315), .B1(
d_ff_Yn[2]), .Y(n915) );
AO22XLTS U827 ( .A0(n1310), .A1(result_add_subt[1]), .B0(n1315), .B1(
d_ff_Yn[1]), .Y(n916) );
AO22XLTS U828 ( .A0(n1310), .A1(result_add_subt[0]), .B0(n1317), .B1(
d_ff_Yn[0]), .Y(n917) );
AO22XLTS U829 ( .A0(n1316), .A1(result_add_subt[23]), .B0(n1314), .B1(
d_ff_Yn[23]), .Y(n894) );
AO22XLTS U830 ( .A0(n1316), .A1(result_add_subt[28]), .B0(n1317), .B1(
d_ff_Yn[28]), .Y(n889) );
AO22XLTS U831 ( .A0(n1363), .A1(d_ff_Xn[0]), .B0(d_ff2_X[0]), .B1(n1227),
.Y(n703) );
AO22XLTS U832 ( .A0(n1323), .A1(result_add_subt[11]), .B0(n1321), .B1(
d_ff_Xn[11]), .Y(n874) );
AO22XLTS U833 ( .A0(n1323), .A1(result_add_subt[15]), .B0(n1321), .B1(
d_ff_Xn[15]), .Y(n870) );
AO22XLTS U834 ( .A0(n1323), .A1(result_add_subt[18]), .B0(n1324), .B1(
d_ff_Xn[18]), .Y(n867) );
AO22XLTS U835 ( .A0(n1325), .A1(result_add_subt[21]), .B0(n1324), .B1(
d_ff_Xn[21]), .Y(n864) );
AO22XLTS U836 ( .A0(n1325), .A1(result_add_subt[22]), .B0(n1324), .B1(
d_ff_Xn[22]), .Y(n863) );
AO22XLTS U837 ( .A0(n1058), .A1(d_ff_Yn[0]), .B0(d_ff2_Y[0]), .B1(n1227),
.Y(n767) );
AO22XLTS U838 ( .A0(n1058), .A1(d_ff_Yn[2]), .B0(d_ff2_Y[2]), .B1(n1365),
.Y(n763) );
AO22XLTS U839 ( .A0(n1058), .A1(d_ff_Yn[3]), .B0(d_ff2_Y[3]), .B1(n1404),
.Y(n761) );
AO22XLTS U840 ( .A0(n1058), .A1(d_ff_Yn[4]), .B0(d_ff2_Y[4]), .B1(n1351),
.Y(n759) );
AO22XLTS U841 ( .A0(n1350), .A1(d_ff_Yn[5]), .B0(d_ff2_Y[5]), .B1(n1348),
.Y(n757) );
AO22XLTS U842 ( .A0(n1350), .A1(d_ff_Yn[6]), .B0(d_ff2_Y[6]), .B1(n1227),
.Y(n755) );
AO22XLTS U843 ( .A0(n1350), .A1(d_ff_Yn[8]), .B0(d_ff2_Y[8]), .B1(n1348),
.Y(n751) );
AO22XLTS U844 ( .A0(n1350), .A1(d_ff_Yn[9]), .B0(d_ff2_Y[9]), .B1(n1227),
.Y(n749) );
AO22XLTS U845 ( .A0(n1405), .A1(d_ff_Yn[10]), .B0(d_ff2_Y[10]), .B1(n1351),
.Y(n747) );
AO22XLTS U846 ( .A0(n1350), .A1(d_ff_Yn[11]), .B0(d_ff2_Y[11]), .B1(n1348),
.Y(n745) );
AO22XLTS U847 ( .A0(n1350), .A1(d_ff_Yn[12]), .B0(d_ff2_Y[12]), .B1(n1227),
.Y(n743) );
AO22XLTS U848 ( .A0(n1405), .A1(d_ff_Yn[16]), .B0(d_ff2_Y[16]), .B1(n1351),
.Y(n735) );
AO22XLTS U849 ( .A0(n1405), .A1(d_ff_Yn[17]), .B0(d_ff2_Y[17]), .B1(n1348),
.Y(n733) );
AO22XLTS U850 ( .A0(n1405), .A1(d_ff_Yn[20]), .B0(d_ff2_Y[20]), .B1(n1351),
.Y(n727) );
AO22XLTS U851 ( .A0(n1405), .A1(d_ff_Yn[21]), .B0(d_ff2_Y[21]), .B1(n1348),
.Y(n725) );
AO22XLTS U852 ( .A0(n1405), .A1(d_ff_Yn[22]), .B0(d_ff2_Y[22]), .B1(n1227),
.Y(n723) );
AO22XLTS U853 ( .A0(n1363), .A1(d_ff_Yn[31]), .B0(d_ff2_Y[31]), .B1(n1351),
.Y(n705) );
AO22XLTS U854 ( .A0(n1325), .A1(result_add_subt[24]), .B0(n1324), .B1(
d_ff_Xn[24]), .Y(n861) );
AO22XLTS U855 ( .A0(n1325), .A1(result_add_subt[27]), .B0(n1324), .B1(
d_ff_Xn[27]), .Y(n858) );
AO22XLTS U856 ( .A0(n1325), .A1(result_add_subt[28]), .B0(n1326), .B1(
d_ff_Xn[28]), .Y(n857) );
AO22XLTS U857 ( .A0(n1325), .A1(result_add_subt[29]), .B0(n1326), .B1(
d_ff_Xn[29]), .Y(n856) );
AO22XLTS U858 ( .A0(n1323), .A1(result_add_subt[10]), .B0(n1322), .B1(
d_ff_Xn[10]), .Y(n875) );
AO22XLTS U859 ( .A0(n1323), .A1(result_add_subt[12]), .B0(n1326), .B1(
d_ff_Xn[12]), .Y(n873) );
AO22XLTS U860 ( .A0(n1323), .A1(result_add_subt[13]), .B0(n1320), .B1(
d_ff_Xn[13]), .Y(n872) );
AO22XLTS U861 ( .A0(n1323), .A1(result_add_subt[14]), .B0(n1320), .B1(
d_ff_Xn[14]), .Y(n871) );
AO22XLTS U862 ( .A0(n1323), .A1(result_add_subt[16]), .B0(n1321), .B1(
d_ff_Xn[16]), .Y(n869) );
AO22XLTS U863 ( .A0(n1323), .A1(result_add_subt[17]), .B0(n1321), .B1(
d_ff_Xn[17]), .Y(n868) );
AO22XLTS U864 ( .A0(n1323), .A1(result_add_subt[19]), .B0(n1324), .B1(
d_ff_Xn[19]), .Y(n866) );
AO22XLTS U865 ( .A0(n1325), .A1(result_add_subt[20]), .B0(n1324), .B1(
d_ff_Xn[20]), .Y(n865) );
AO22XLTS U866 ( .A0(n1325), .A1(result_add_subt[25]), .B0(n1324), .B1(
d_ff_Xn[25]), .Y(n860) );
AO22XLTS U867 ( .A0(n1325), .A1(result_add_subt[26]), .B0(n1324), .B1(
d_ff_Xn[26]), .Y(n859) );
AO22XLTS U868 ( .A0(n1058), .A1(d_ff_Xn[23]), .B0(d_ff2_X[23]), .B1(n1373),
.Y(n657) );
AO21XLTS U869 ( .A0(d_ff3_sh_x_out[24]), .A1(n1382), .B0(n1381), .Y(n648) );
AO22XLTS U870 ( .A0(n1292), .A1(d_ff1_Z[5]), .B0(n1293), .B1(data_in[5]),
.Y(n976) );
AO22XLTS U871 ( .A0(n1309), .A1(result_add_subt[24]), .B0(n1305), .B1(
d_ff_Zn[24]), .Y(n925) );
AO22XLTS U872 ( .A0(n1395), .A1(n1384), .B0(n1393), .B1(d_ff3_sh_x_out[25]),
.Y(n647) );
AO22XLTS U873 ( .A0(n1399), .A1(d_ff2_Y[22]), .B0(n1360), .B1(
d_ff3_sh_y_out[22]), .Y(n722) );
AO22XLTS U874 ( .A0(n1407), .A1(d_ff2_X[13]), .B0(n1367), .B1(
d_ff3_sh_x_out[13]), .Y(n676) );
AO22XLTS U875 ( .A0(n1353), .A1(d_ff2_Y[6]), .B0(n1382), .B1(
d_ff3_sh_y_out[6]), .Y(n754) );
NOR2XLTS U876 ( .A(n1262), .B(n1306), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
AO22XLTS U877 ( .A0(n1319), .A1(result_add_subt[0]), .B0(n1326), .B1(
d_ff_Xn[0]), .Y(n885) );
AO22XLTS U878 ( .A0(n1319), .A1(result_add_subt[1]), .B0(n1320), .B1(
d_ff_Xn[1]), .Y(n884) );
AO22XLTS U879 ( .A0(n1319), .A1(result_add_subt[2]), .B0(n1320), .B1(
d_ff_Xn[2]), .Y(n883) );
AO22XLTS U880 ( .A0(n1319), .A1(result_add_subt[3]), .B0(n1320), .B1(
d_ff_Xn[3]), .Y(n882) );
AO22XLTS U881 ( .A0(n1319), .A1(result_add_subt[4]), .B0(n1320), .B1(
d_ff_Xn[4]), .Y(n881) );
AO22XLTS U882 ( .A0(n1319), .A1(result_add_subt[5]), .B0(n1320), .B1(
d_ff_Xn[5]), .Y(n880) );
AO22XLTS U883 ( .A0(n1319), .A1(result_add_subt[6]), .B0(n1320), .B1(
d_ff_Xn[6]), .Y(n879) );
AO22XLTS U884 ( .A0(n1319), .A1(result_add_subt[7]), .B0(n1320), .B1(
d_ff_Xn[7]), .Y(n878) );
AO22XLTS U885 ( .A0(n1319), .A1(result_add_subt[8]), .B0(n1321), .B1(
d_ff_Xn[8]), .Y(n877) );
AO22XLTS U886 ( .A0(n1319), .A1(result_add_subt[9]), .B0(n1321), .B1(
d_ff_Xn[9]), .Y(n876) );
OAI21XLTS U887 ( .A0(n1340), .A1(intadd_364_CI), .B0(n1107), .Y(n713) );
AO22XLTS U888 ( .A0(n1300), .A1(d_ff1_Z[26]), .B0(n1298), .B1(data_in[26]),
.Y(n955) );
AO22XLTS U889 ( .A0(n1300), .A1(d_ff1_Z[27]), .B0(n1297), .B1(data_in[27]),
.Y(n954) );
AO22XLTS U890 ( .A0(n1300), .A1(d_ff1_Z[28]), .B0(n1298), .B1(data_in[28]),
.Y(n953) );
AO22XLTS U891 ( .A0(n1300), .A1(d_ff1_Z[29]), .B0(n1298), .B1(data_in[29]),
.Y(n952) );
AO22XLTS U892 ( .A0(n1300), .A1(d_ff1_Z[30]), .B0(n1298), .B1(data_in[30]),
.Y(n951) );
AO22XLTS U893 ( .A0(n1300), .A1(d_ff1_Z[31]), .B0(n1299), .B1(data_in[31]),
.Y(n950) );
AO22XLTS U894 ( .A0(n1301), .A1(result_add_subt[5]), .B0(n1306), .B1(
d_ff_Zn[5]), .Y(n944) );
AO22XLTS U895 ( .A0(n1301), .A1(result_add_subt[6]), .B0(n1306), .B1(
d_ff_Zn[6]), .Y(n943) );
AO22XLTS U896 ( .A0(n1301), .A1(result_add_subt[7]), .B0(n1302), .B1(
d_ff_Zn[7]), .Y(n942) );
AO22XLTS U897 ( .A0(n1292), .A1(d_ff1_Z[0]), .B0(n1297), .B1(data_in[0]),
.Y(n981) );
AO22XLTS U898 ( .A0(n1292), .A1(d_ff1_Z[1]), .B0(n1297), .B1(data_in[1]),
.Y(n980) );
AO22XLTS U899 ( .A0(n1292), .A1(d_ff1_Z[2]), .B0(n1297), .B1(data_in[2]),
.Y(n979) );
AO22XLTS U900 ( .A0(n1292), .A1(d_ff1_Z[3]), .B0(n1297), .B1(data_in[3]),
.Y(n978) );
AO22XLTS U901 ( .A0(n1292), .A1(d_ff1_Z[4]), .B0(n1297), .B1(data_in[4]),
.Y(n977) );
AO22XLTS U902 ( .A0(n1395), .A1(n1356), .B0(n1360), .B1(d_ff3_sh_y_out[28]),
.Y(n708) );
AO22XLTS U903 ( .A0(n1309), .A1(result_add_subt[20]), .B0(n1304), .B1(
d_ff_Zn[20]), .Y(n929) );
AO22XLTS U904 ( .A0(n1368), .A1(d_ff_Xn[21]), .B0(d_ff2_X[21]), .B1(n1227),
.Y(n661) );
AO22XLTS U905 ( .A0(n1327), .A1(result_add_subt[30]), .B0(n1321), .B1(
d_ff_Xn[30]), .Y(n855) );
AOI2BB2XLTS U906 ( .B0(n1399), .B1(n1354), .A0N(d_ff3_sh_y_out[27]), .A1N(
n1390), .Y(n709) );
OAI21XLTS U907 ( .A0(cont_iter_out[3]), .A1(n1379), .B0(n1108), .Y(n802) );
AO22XLTS U908 ( .A0(n1309), .A1(result_add_subt[8]), .B0(n1302), .B1(
d_ff_Zn[8]), .Y(n941) );
AO22XLTS U909 ( .A0(n1309), .A1(result_add_subt[19]), .B0(n1308), .B1(
d_ff_Zn[19]), .Y(n930) );
AO22XLTS U910 ( .A0(n1309), .A1(result_add_subt[21]), .B0(n1305), .B1(
d_ff_Zn[21]), .Y(n928) );
AO22XLTS U911 ( .A0(n1309), .A1(result_add_subt[22]), .B0(n1305), .B1(
d_ff_Zn[22]), .Y(n927) );
AO22XLTS U912 ( .A0(n1309), .A1(result_add_subt[23]), .B0(n1305), .B1(
d_ff_Zn[23]), .Y(n926) );
AO22XLTS U913 ( .A0(n1309), .A1(result_add_subt[31]), .B0(n1308), .B1(
d_ff_Zn[31]), .Y(n918) );
AO22XLTS U914 ( .A0(n1366), .A1(d_ff_Xn[9]), .B0(d_ff2_X[9]), .B1(n1348),
.Y(n685) );
AO22XLTS U915 ( .A0(n1366), .A1(d_ff_Xn[18]), .B0(d_ff2_X[18]), .B1(n1351),
.Y(n667) );
AO22XLTS U916 ( .A0(n1395), .A1(n1386), .B0(n1393), .B1(d_ff3_sh_x_out[26]),
.Y(n646) );
AO22XLTS U917 ( .A0(n1407), .A1(d_ff2_X[17]), .B0(n1393), .B1(
d_ff3_sh_x_out[17]), .Y(n668) );
AO22XLTS U918 ( .A0(n1403), .A1(d_ff2_X[19]), .B0(n1393), .B1(
d_ff3_sh_x_out[19]), .Y(n664) );
AO22XLTS U919 ( .A0(n1403), .A1(d_ff2_X[20]), .B0(n1393), .B1(
d_ff3_sh_x_out[20]), .Y(n662) );
AO22XLTS U920 ( .A0(n1403), .A1(d_ff2_X[21]), .B0(n1393), .B1(
d_ff3_sh_x_out[21]), .Y(n660) );
AO22XLTS U921 ( .A0(n1395), .A1(d_ff2_X[22]), .B0(n1393), .B1(
d_ff3_sh_x_out[22]), .Y(n658) );
AO22XLTS U922 ( .A0(n1364), .A1(d_ff2_Y[8]), .B0(n1352), .B1(
d_ff3_sh_y_out[8]), .Y(n750) );
AO22XLTS U923 ( .A0(n1362), .A1(d_ff2_Y[9]), .B0(n1352), .B1(
d_ff3_sh_y_out[9]), .Y(n748) );
AO22XLTS U924 ( .A0(n1364), .A1(d_ff2_Y[10]), .B0(n1352), .B1(
d_ff3_sh_y_out[10]), .Y(n746) );
AO22XLTS U925 ( .A0(n1407), .A1(d_ff2_Y[11]), .B0(n1352), .B1(
d_ff3_sh_y_out[11]), .Y(n744) );
AO22XLTS U926 ( .A0(n1353), .A1(d_ff2_Y[12]), .B0(n1352), .B1(
d_ff3_sh_y_out[12]), .Y(n742) );
AO22XLTS U927 ( .A0(n1395), .A1(d_ff2_Y[13]), .B0(n1352), .B1(
d_ff3_sh_y_out[13]), .Y(n740) );
AO22XLTS U928 ( .A0(n1390), .A1(d_ff2_Y[14]), .B0(n1352), .B1(
d_ff3_sh_y_out[14]), .Y(n738) );
AO22XLTS U929 ( .A0(n1390), .A1(d_ff2_Y[15]), .B0(n1352), .B1(
d_ff3_sh_y_out[15]), .Y(n736) );
AO22XLTS U930 ( .A0(n1362), .A1(d_ff2_Y[16]), .B0(n1352), .B1(
d_ff3_sh_y_out[16]), .Y(n734) );
AO22XLTS U931 ( .A0(n1390), .A1(d_ff2_Y[17]), .B0(n1352), .B1(
d_ff3_sh_y_out[17]), .Y(n732) );
AO22XLTS U932 ( .A0(n1395), .A1(d_ff2_Y[18]), .B0(n1360), .B1(
d_ff3_sh_y_out[18]), .Y(n730) );
AO22XLTS U933 ( .A0(n1362), .A1(d_ff2_Y[19]), .B0(n1360), .B1(
d_ff3_sh_y_out[19]), .Y(n728) );
AO22XLTS U934 ( .A0(n1399), .A1(d_ff2_Y[20]), .B0(n1360), .B1(
d_ff3_sh_y_out[20]), .Y(n726) );
AO22XLTS U935 ( .A0(n1362), .A1(d_ff2_Y[21]), .B0(n1360), .B1(
d_ff3_sh_y_out[21]), .Y(n724) );
AO22XLTS U936 ( .A0(n1407), .A1(d_ff2_Y[31]), .B0(n1406), .B1(
d_ff3_sh_y_out[31]), .Y(n704) );
AO22XLTS U937 ( .A0(n1403), .A1(d_ff2_X[0]), .B0(n1406), .B1(
d_ff3_sh_x_out[0]), .Y(n702) );
AO22XLTS U938 ( .A0(n1407), .A1(d_ff2_X[1]), .B0(n1406), .B1(
d_ff3_sh_x_out[1]), .Y(n700) );
AO22XLTS U939 ( .A0(n1407), .A1(d_ff2_X[2]), .B0(n1406), .B1(
d_ff3_sh_x_out[2]), .Y(n698) );
AO22XLTS U940 ( .A0(n1407), .A1(d_ff2_X[3]), .B0(n1406), .B1(
d_ff3_sh_x_out[3]), .Y(n696) );
AO22XLTS U941 ( .A0(n1403), .A1(d_ff2_X[4]), .B0(n1406), .B1(
d_ff3_sh_x_out[4]), .Y(n694) );
AO22XLTS U942 ( .A0(n1362), .A1(d_ff2_X[5]), .B0(n1406), .B1(
d_ff3_sh_x_out[5]), .Y(n692) );
AO22XLTS U943 ( .A0(n1353), .A1(d_ff2_X[6]), .B0(n1406), .B1(
d_ff3_sh_x_out[6]), .Y(n690) );
AO22XLTS U944 ( .A0(n1364), .A1(d_ff2_X[7]), .B0(n1367), .B1(
d_ff3_sh_x_out[7]), .Y(n688) );
AO22XLTS U945 ( .A0(n1399), .A1(d_ff2_X[8]), .B0(n1406), .B1(
d_ff3_sh_x_out[8]), .Y(n686) );
AO22XLTS U946 ( .A0(n1353), .A1(d_ff2_X[9]), .B0(n1367), .B1(
d_ff3_sh_x_out[9]), .Y(n684) );
AO22XLTS U947 ( .A0(n1390), .A1(d_ff2_X[10]), .B0(n1367), .B1(
d_ff3_sh_x_out[10]), .Y(n682) );
AO22XLTS U948 ( .A0(n1390), .A1(d_ff2_X[11]), .B0(n1367), .B1(
d_ff3_sh_x_out[11]), .Y(n680) );
AO22XLTS U949 ( .A0(n1407), .A1(d_ff2_X[12]), .B0(n1367), .B1(
d_ff3_sh_x_out[12]), .Y(n678) );
AO22XLTS U950 ( .A0(n1399), .A1(d_ff2_X[14]), .B0(n1367), .B1(
d_ff3_sh_x_out[14]), .Y(n674) );
AO22XLTS U951 ( .A0(n1403), .A1(d_ff2_X[15]), .B0(n1367), .B1(
d_ff3_sh_x_out[15]), .Y(n672) );
AO22XLTS U952 ( .A0(n1403), .A1(d_ff2_X[16]), .B0(n1367), .B1(
d_ff3_sh_x_out[16]), .Y(n670) );
AO22XLTS U953 ( .A0(n1403), .A1(d_ff2_X[18]), .B0(n1367), .B1(
d_ff3_sh_x_out[18]), .Y(n666) );
AO22XLTS U954 ( .A0(n1407), .A1(d_ff2_X[31]), .B0(n1406), .B1(
d_ff3_sh_x_out[31]), .Y(n640) );
AO22XLTS U955 ( .A0(n1399), .A1(intadd_364_SUM_0_), .B0(n1360), .B1(
d_ff3_sh_y_out[24]), .Y(n712) );
AO22XLTS U956 ( .A0(n1353), .A1(intadd_364_SUM_1_), .B0(n1360), .B1(
d_ff3_sh_y_out[25]), .Y(n711) );
AO22XLTS U957 ( .A0(n1362), .A1(intadd_364_SUM_2_), .B0(n1360), .B1(
d_ff3_sh_y_out[26]), .Y(n710) );
AO22XLTS U958 ( .A0(n1362), .A1(d_ff2_Y[0]), .B0(n1382), .B1(
d_ff3_sh_y_out[0]), .Y(n766) );
AO22XLTS U959 ( .A0(n1395), .A1(d_ff2_Y[1]), .B0(n1382), .B1(
d_ff3_sh_y_out[1]), .Y(n764) );
AO22XLTS U960 ( .A0(n1362), .A1(d_ff2_Y[2]), .B0(n1382), .B1(
d_ff3_sh_y_out[2]), .Y(n762) );
AO22XLTS U961 ( .A0(n1362), .A1(d_ff2_Y[3]), .B0(n1382), .B1(
d_ff3_sh_y_out[3]), .Y(n760) );
AO22XLTS U962 ( .A0(n1395), .A1(d_ff2_Y[4]), .B0(n1382), .B1(
d_ff3_sh_y_out[4]), .Y(n758) );
AO22XLTS U963 ( .A0(n1362), .A1(d_ff2_Y[5]), .B0(n1382), .B1(
d_ff3_sh_y_out[5]), .Y(n756) );
AO22XLTS U964 ( .A0(n1395), .A1(d_ff2_Y[7]), .B0(n1382), .B1(
d_ff3_sh_y_out[7]), .Y(n752) );
AO22XLTS U965 ( .A0(n1364), .A1(n1341), .B0(n1382), .B1(d_ff3_LUT_out[19]),
.Y(n807) );
NAND2BXLTS U966 ( .AN(d_ff3_LUT_out[27]), .B(n1397), .Y(n801) );
AO22XLTS U967 ( .A0(n1403), .A1(n1413), .B0(n1401), .B1(d_ff3_LUT_out[8]),
.Y(n813) );
OAI21XLTS U968 ( .A0(beg_fsm_cordic), .A1(n1259), .B0(n1162), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
AOI2BB2XLTS U969 ( .B0(n1422), .B1(n1289), .A0N(n1289), .A1N(n1422), .Y(n987) );
AO21XLTS U970 ( .A0(enab_cont_iter), .A1(n1263), .B0(n1159), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
AO22XLTS U971 ( .A0(d_ff2_Y[23]), .A1(n1227), .B0(n1058), .B1(d_ff_Yn[23]),
.Y(n721) );
AO22XLTS U972 ( .A0(n1349), .A1(d_ff3_sign_out), .B0(n1353), .B1(d_ff2_Z[31]), .Y(n768) );
OAI21XLTS U973 ( .A0(n1155), .A1(n1166), .B0(n1154), .Y(n822) );
AOI2BB2XLTS U974 ( .B0(n1291), .B1(n1409), .A0N(n1409), .A1N(n1291), .Y(n985) );
AO22XLTS U975 ( .A0(n1292), .A1(d_ff1_operation_out), .B0(n1299), .B1(
operation), .Y(n984) );
AO22XLTS U976 ( .A0(n1292), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1297),
.B1(shift_region_flag[1]), .Y(n982) );
OAI211XLTS U977 ( .A0(n1364), .A1(n1412), .B0(n1328), .C0(n1342), .Y(n808)
);
OAI211XLTS U978 ( .A0(n1291), .A1(n1087), .B0(n1082), .C0(n1073), .Y(n990)
);
AO22XLTS U979 ( .A0(n1292), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1297),
.B1(shift_region_flag[0]), .Y(n983) );
AO22XLTS U980 ( .A0(n1403), .A1(n1402), .B0(n1401), .B1(d_ff3_sh_x_out[30]),
.Y(n642) );
AO22XLTS U981 ( .A0(n1395), .A1(n1394), .B0(n1393), .B1(d_ff3_sh_x_out[28]),
.Y(n644) );
OAI21XLTS U982 ( .A0(n1392), .A1(n1420), .B0(n1396), .Y(n1394) );
AOI2BB2XLTS U983 ( .B0(n1390), .B1(n1389), .A0N(d_ff3_sh_x_out[27]), .A1N(
n1388), .Y(n645) );
AO22XLTS U984 ( .A0(n1407), .A1(n1361), .B0(n1360), .B1(d_ff3_sh_y_out[30]),
.Y(n706) );
AOI2BB2XLTS U985 ( .B0(n1353), .B1(n1358), .A0N(d_ff3_sh_y_out[29]), .A1N(
n1353), .Y(n707) );
NOR2XLTS U986 ( .A(n1423), .B(n1380), .Y(n1344) );
OAI21XLTS U987 ( .A0(n1375), .A1(n1342), .B0(n1238), .Y(n804) );
NAND2BXLTS U988 ( .AN(n1337), .B(n1336), .Y(n811) );
OAI211XLTS U989 ( .A0(n1364), .A1(n1060), .B0(n1257), .C0(n1338), .Y(n812)
);
OAI21XLTS U990 ( .A0(n1422), .A1(n1380), .B0(n1240), .Y(n817) );
OAI211XLTS U991 ( .A0(n1399), .A1(n1258), .B0(n1328), .C0(n1257), .Y(n818)
);
OAI21XLTS U992 ( .A0(n1379), .A1(n1256), .B0(n1164), .Y(n819) );
AO22XLTS U993 ( .A0(n1307), .A1(result_add_subt[29]), .B0(n1308), .B1(
d_ff_Zn[29]), .Y(n920) );
AO22XLTS U994 ( .A0(n1307), .A1(result_add_subt[28]), .B0(n1308), .B1(
d_ff_Zn[28]), .Y(n921) );
AO22XLTS U995 ( .A0(n1307), .A1(result_add_subt[27]), .B0(n1308), .B1(
d_ff_Zn[27]), .Y(n922) );
AO22XLTS U996 ( .A0(n1307), .A1(result_add_subt[26]), .B0(n1308), .B1(
d_ff_Zn[26]), .Y(n923) );
AO22XLTS U997 ( .A0(n1307), .A1(result_add_subt[25]), .B0(n1306), .B1(
d_ff_Zn[25]), .Y(n924) );
AO22XLTS U998 ( .A0(n1303), .A1(result_add_subt[18]), .B0(n1305), .B1(
d_ff_Zn[18]), .Y(n931) );
AO22XLTS U999 ( .A0(n1303), .A1(result_add_subt[17]), .B0(n1305), .B1(
d_ff_Zn[17]), .Y(n932) );
AO22XLTS U1000 ( .A0(n1303), .A1(result_add_subt[16]), .B0(n1302), .B1(
d_ff_Zn[16]), .Y(n933) );
AO22XLTS U1001 ( .A0(n1303), .A1(result_add_subt[15]), .B0(n1302), .B1(
d_ff_Zn[15]), .Y(n934) );
AO22XLTS U1002 ( .A0(n1303), .A1(result_add_subt[14]), .B0(n1302), .B1(
d_ff_Zn[14]), .Y(n935) );
AO22XLTS U1003 ( .A0(n1307), .A1(result_add_subt[13]), .B0(n1302), .B1(
d_ff_Zn[13]), .Y(n936) );
AO22XLTS U1004 ( .A0(n1307), .A1(result_add_subt[12]), .B0(n1302), .B1(
d_ff_Zn[12]), .Y(n937) );
AO22XLTS U1005 ( .A0(n1307), .A1(result_add_subt[11]), .B0(n1302), .B1(
d_ff_Zn[11]), .Y(n938) );
AO22XLTS U1006 ( .A0(n1307), .A1(result_add_subt[10]), .B0(n1302), .B1(
d_ff_Zn[10]), .Y(n939) );
AO22XLTS U1007 ( .A0(n1307), .A1(result_add_subt[9]), .B0(n1302), .B1(
d_ff_Zn[9]), .Y(n940) );
AO22XLTS U1008 ( .A0(n1303), .A1(result_add_subt[4]), .B0(n1306), .B1(
d_ff_Zn[4]), .Y(n945) );
AO22XLTS U1009 ( .A0(n1303), .A1(result_add_subt[3]), .B0(n1306), .B1(
d_ff_Zn[3]), .Y(n946) );
AO22XLTS U1010 ( .A0(n1303), .A1(result_add_subt[2]), .B0(n1306), .B1(
d_ff_Zn[2]), .Y(n947) );
AO22XLTS U1011 ( .A0(n1303), .A1(result_add_subt[1]), .B0(n1306), .B1(
d_ff_Zn[1]), .Y(n948) );
AO22XLTS U1012 ( .A0(n1303), .A1(result_add_subt[0]), .B0(n1304), .B1(
d_ff_Zn[0]), .Y(n949) );
AO22XLTS U1013 ( .A0(n1296), .A1(d_ff1_Z[25]), .B0(n1298), .B1(data_in[25]),
.Y(n956) );
AO22XLTS U1014 ( .A0(n1296), .A1(d_ff1_Z[24]), .B0(n1295), .B1(data_in[24]),
.Y(n957) );
AO22XLTS U1015 ( .A0(n1296), .A1(d_ff1_Z[23]), .B0(n1295), .B1(data_in[23]),
.Y(n958) );
AO22XLTS U1016 ( .A0(n1296), .A1(d_ff1_Z[22]), .B0(n1295), .B1(data_in[22]),
.Y(n959) );
AO22XLTS U1017 ( .A0(n1296), .A1(d_ff1_Z[21]), .B0(n1295), .B1(data_in[21]),
.Y(n960) );
AO22XLTS U1018 ( .A0(n1296), .A1(d_ff1_Z[20]), .B0(n1295), .B1(data_in[20]),
.Y(n961) );
AO22XLTS U1019 ( .A0(n1296), .A1(d_ff1_Z[19]), .B0(n1295), .B1(data_in[19]),
.Y(n962) );
AO22XLTS U1020 ( .A0(n1296), .A1(d_ff1_Z[18]), .B0(n1295), .B1(data_in[18]),
.Y(n963) );
AO22XLTS U1021 ( .A0(n1296), .A1(d_ff1_Z[17]), .B0(n1295), .B1(data_in[17]),
.Y(n964) );
AO22XLTS U1022 ( .A0(n1296), .A1(d_ff1_Z[16]), .B0(n1295), .B1(data_in[16]),
.Y(n965) );
AO22XLTS U1023 ( .A0(n1294), .A1(d_ff1_Z[15]), .B0(n1295), .B1(data_in[15]),
.Y(n966) );
AO22XLTS U1024 ( .A0(n1294), .A1(d_ff1_Z[14]), .B0(n1293), .B1(data_in[14]),
.Y(n967) );
AO22XLTS U1025 ( .A0(n1294), .A1(d_ff1_Z[13]), .B0(n1293), .B1(data_in[13]),
.Y(n968) );
AO22XLTS U1026 ( .A0(n1294), .A1(d_ff1_Z[12]), .B0(n1293), .B1(data_in[12]),
.Y(n969) );
AO22XLTS U1027 ( .A0(n1294), .A1(d_ff1_Z[11]), .B0(n1293), .B1(data_in[11]),
.Y(n970) );
AO22XLTS U1028 ( .A0(n1294), .A1(d_ff1_Z[10]), .B0(n1293), .B1(data_in[10]),
.Y(n971) );
AO22XLTS U1029 ( .A0(n1294), .A1(d_ff1_Z[9]), .B0(n1293), .B1(data_in[9]),
.Y(n972) );
AO22XLTS U1030 ( .A0(n1294), .A1(d_ff1_Z[8]), .B0(n1293), .B1(data_in[8]),
.Y(n973) );
AO22XLTS U1031 ( .A0(n1294), .A1(d_ff1_Z[7]), .B0(n1293), .B1(data_in[7]),
.Y(n974) );
AO22XLTS U1032 ( .A0(n1294), .A1(d_ff1_Z[6]), .B0(n1293), .B1(data_in[6]),
.Y(n975) );
CLKBUFX2TS U1033 ( .A(n1366), .Y(n1368) );
BUFX3TS U1034 ( .A(n1193), .Y(n1371) );
NAND2X1TS U1035 ( .A(n1194), .B(n1370), .Y(n1193) );
INVX2TS U1036 ( .A(n1064), .Y(n1375) );
INVX2TS U1037 ( .A(n1371), .Y(n1058) );
INVX2TS U1038 ( .A(n1058), .Y(n1059) );
AOI222X4TS U1039 ( .A0(n1235), .A1(d_ff2_Z[8]), .B0(n1234), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n1233), .Y(n1232) );
AOI222X1TS U1040 ( .A0(n1284), .A1(d_ff2_Y[3]), .B0(n1133), .B1(d_ff2_X[3]),
.C0(d_ff2_Z[3]), .C1(n1283), .Y(n1143) );
NOR4BX2TS U1041 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(inst_CORDIC_FSM_v3_state_reg[4]),
.D(n1080), .Y(n1159) );
OAI21XLTS U1042 ( .A0(n1135), .A1(n1261), .B0(n1397), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
CLKBUFX3TS U1043 ( .A(n1075), .Y(n1076) );
CLKINVX3TS U1044 ( .A(n1100), .Y(n1283) );
CLKINVX3TS U1045 ( .A(n1100), .Y(n1145) );
NOR2X2TS U1046 ( .A(cont_iter_out[3]), .B(n1413), .Y(n1345) );
NOR2X2TS U1047 ( .A(n1408), .B(n1413), .Y(n1191) );
AOI222X1TS U1048 ( .A0(n1244), .A1(data_output[23]), .B0(n1253), .B1(
d_ff_Yn[23]), .C0(n1252), .C1(d_ff_Xn[23]), .Y(n1242) );
AOI222X1TS U1049 ( .A0(n1254), .A1(data_output[29]), .B0(n1253), .B1(
d_ff_Yn[29]), .C0(n1252), .C1(d_ff_Xn[29]), .Y(n1255) );
AOI222X1TS U1050 ( .A0(n1254), .A1(data_output[27]), .B0(n1253), .B1(
d_ff_Yn[27]), .C0(n1252), .C1(d_ff_Xn[27]), .Y(n1249) );
AOI222X1TS U1051 ( .A0(n1254), .A1(data_output[26]), .B0(n1253), .B1(
d_ff_Yn[26]), .C0(n1252), .C1(d_ff_Xn[26]), .Y(n1250) );
AOI222X1TS U1052 ( .A0(n1254), .A1(data_output[25]), .B0(n1253), .B1(
d_ff_Yn[25]), .C0(n1252), .C1(d_ff_Xn[25]), .Y(n1248) );
AOI222X1TS U1053 ( .A0(n1254), .A1(data_output[24]), .B0(n1253), .B1(
d_ff_Yn[24]), .C0(n1252), .C1(d_ff_Xn[24]), .Y(n1247) );
AOI222X1TS U1054 ( .A0(n1254), .A1(data_output[22]), .B0(n1253), .B1(
d_ff_Yn[22]), .C0(n1252), .C1(d_ff_Xn[22]), .Y(n1246) );
AOI222X1TS U1055 ( .A0(n1244), .A1(data_output[21]), .B0(n1243), .B1(
d_ff_Yn[21]), .C0(n1252), .C1(d_ff_Xn[21]), .Y(n1245) );
AOI222X1TS U1056 ( .A0(n1244), .A1(data_output[20]), .B0(n1243), .B1(
d_ff_Yn[20]), .C0(n1188), .C1(d_ff_Xn[20]), .Y(n1165) );
AOI222X1TS U1057 ( .A0(n1244), .A1(data_output[19]), .B0(n1243), .B1(
d_ff_Yn[19]), .C0(n1188), .C1(d_ff_Xn[19]), .Y(n1187) );
AOI222X1TS U1058 ( .A0(n1244), .A1(data_output[18]), .B0(n1243), .B1(
d_ff_Yn[18]), .C0(n1188), .C1(d_ff_Xn[18]), .Y(n1181) );
AOI222X1TS U1059 ( .A0(n1244), .A1(data_output[17]), .B0(n1243), .B1(
d_ff_Yn[17]), .C0(n1188), .C1(d_ff_Xn[17]), .Y(n1186) );
AOI222X1TS U1060 ( .A0(n1244), .A1(data_output[16]), .B0(n1243), .B1(
d_ff_Yn[16]), .C0(n1188), .C1(d_ff_Xn[16]), .Y(n1185) );
AOI222X1TS U1061 ( .A0(n1244), .A1(data_output[15]), .B0(n1243), .B1(
d_ff_Yn[15]), .C0(n1188), .C1(d_ff_Xn[15]), .Y(n1180) );
AOI222X1TS U1062 ( .A0(n1244), .A1(data_output[14]), .B0(n1243), .B1(
d_ff_Yn[14]), .C0(n1188), .C1(d_ff_Xn[14]), .Y(n1183) );
AOI222X1TS U1063 ( .A0(n1244), .A1(data_output[13]), .B0(n1243), .B1(
d_ff_Yn[13]), .C0(n1188), .C1(d_ff_Xn[13]), .Y(n1184) );
AOI222X1TS U1064 ( .A0(n1189), .A1(data_output[12]), .B0(n1243), .B1(
d_ff_Yn[12]), .C0(n1188), .C1(d_ff_Xn[12]), .Y(n1190) );
AOI222X1TS U1065 ( .A0(n1189), .A1(data_output[11]), .B0(n1151), .B1(
d_ff_Yn[11]), .C0(n1188), .C1(d_ff_Xn[11]), .Y(n1182) );
AOI222X1TS U1066 ( .A0(n1189), .A1(data_output[10]), .B0(n1151), .B1(
d_ff_Yn[10]), .C0(n1178), .C1(d_ff_Xn[10]), .Y(n1177) );
OAI31XLTS U1067 ( .A0(cont_iter_out[3]), .A1(n1064), .A2(n1379), .B0(n1068),
.Y(n815) );
CLKBUFX3TS U1068 ( .A(n1077), .Y(n1078) );
AOI222X4TS U1069 ( .A0(n1235), .A1(d_ff2_Z[5]), .B0(n1234), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n1233), .Y(n1213) );
AOI222X4TS U1070 ( .A0(n1235), .A1(d_ff2_Z[6]), .B0(n1234), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n1233), .Y(n1212) );
AOI222X4TS U1071 ( .A0(n1235), .A1(d_ff2_Z[7]), .B0(n1234), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n1233), .Y(n1236) );
AOI222X4TS U1072 ( .A0(n1227), .A1(d_ff2_Z[19]), .B0(n1219), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n1229), .Y(n1197) );
AOI222X4TS U1073 ( .A0(n1373), .A1(d_ff2_Z[20]), .B0(n1219), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n1225), .Y(n1211) );
AOI222X4TS U1074 ( .A0(n1365), .A1(d_ff2_Z[21]), .B0(n1219), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n1225), .Y(n1210) );
AOI222X4TS U1075 ( .A0(n1404), .A1(d_ff2_Z[22]), .B0(n1226), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n1225), .Y(n1209) );
AOI222X4TS U1076 ( .A0(n1351), .A1(d_ff2_Z[25]), .B0(n1226), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n1225), .Y(n1218) );
OAI33X4TS U1077 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n1419), .B0(n1411), .B1(n1410), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n1152) );
OAI21XLTS U1078 ( .A0(n1343), .A1(n1380), .B0(n1192), .Y(n821) );
NOR2X2TS U1079 ( .A(n1345), .B(n1334), .Y(n1343) );
OAI21X2TS U1080 ( .A0(n1191), .A1(n1423), .B0(n1339), .Y(n1334) );
NAND2X2TS U1081 ( .A(cont_iter_out[3]), .B(n1413), .Y(n1339) );
OAI32X1TS U1082 ( .A0(n1289), .A1(n1423), .A2(n1287), .B0(n1414), .B1(n1289),
.Y(n988) );
NOR3X4TS U1083 ( .A(n1287), .B(n1423), .C(n1414), .Y(n1289) );
AOI222X4TS U1084 ( .A0(n1230), .A1(d_ff2_Z[10]), .B0(n1234), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n1229), .Y(n1231) );
AOI222X4TS U1085 ( .A0(n1230), .A1(d_ff2_Z[14]), .B0(n1219), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n1229), .Y(n1220) );
AOI222X4TS U1086 ( .A0(n1230), .A1(d_ff2_Z[9]), .B0(n1234), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n1233), .Y(n1208) );
AOI222X4TS U1087 ( .A0(n1230), .A1(d_ff2_Z[15]), .B0(n1219), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n1229), .Y(n1207) );
AOI222X4TS U1088 ( .A0(n1230), .A1(d_ff2_Z[16]), .B0(n1219), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n1229), .Y(n1206) );
AOI222X4TS U1089 ( .A0(n1230), .A1(d_ff2_Z[11]), .B0(n1234), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n1229), .Y(n1205) );
AOI222X4TS U1090 ( .A0(n1230), .A1(d_ff2_Z[12]), .B0(n1219), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n1229), .Y(n1202) );
AOI222X4TS U1091 ( .A0(n1230), .A1(d_ff2_Z[13]), .B0(n1219), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n1229), .Y(n1201) );
AOI222X4TS U1092 ( .A0(n1230), .A1(d_ff2_Z[17]), .B0(n1219), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n1229), .Y(n1199) );
AOI222X4TS U1093 ( .A0(n1348), .A1(d_ff2_Z[18]), .B0(n1219), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n1229), .Y(n1198) );
AOI222X1TS U1094 ( .A0(n1254), .A1(data_output[28]), .B0(n1253), .B1(
d_ff_Yn[28]), .C0(n1252), .C1(d_ff_Xn[28]), .Y(n1251) );
INVX2TS U1095 ( .A(n1423), .Y(n1288) );
INVX2TS U1096 ( .A(n1149), .Y(n1166) );
NOR2X1TS U1097 ( .A(n1254), .B(n1150), .Y(n1149) );
NOR2X4TS U1098 ( .A(ready_cordic), .B(n1147), .Y(n1174) );
NOR3BX1TS U1099 ( .AN(n1069), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[3]), .Y(n1157) );
OAI21XLTS U1100 ( .A0(n1355), .A1(n1421), .B0(n1357), .Y(n1356) );
INVX2TS U1101 ( .A(n1193), .Y(n1366) );
AOI211XLTS U1102 ( .A0(d_ff3_LUT_out[6]), .A1(n1340), .B0(n1067), .C0(n1163),
.Y(n1068) );
NAND2X1TS U1103 ( .A(n1070), .B(ready_add_subt), .Y(n1313) );
NAND2BX1TS U1104 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(n1157), .Y(n1074) );
INVX2TS U1105 ( .A(d_ff3_LUT_out[3]), .Y(n1258) );
OAI21XLTS U1106 ( .A0(n1341), .A1(n1346), .B0(n1090), .Y(n805) );
OAI21XLTS U1107 ( .A0(n1100), .A1(n1060), .B0(n1095), .Y(add_subt_dataB[9])
);
OAI21XLTS U1108 ( .A0(n1260), .A1(n1412), .B0(n1091), .Y(add_subt_dataB[20])
);
OAI21XLTS U1109 ( .A0(n1082), .A1(n1417), .B0(n1071), .Y(add_subt_dataA[23])
);
NOR4X2TS U1110 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[3]),
.D(inst_CORDIC_FSM_v3_state_reg[0]), .Y(n1079) );
NOR3X2TS U1111 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(inst_CORDIC_FSM_v3_state_reg[1]),
.Y(n1069) );
NAND3X1TS U1112 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1079), .C(n1069),
.Y(n1264) );
INVX2TS U1113 ( .A(n1264), .Y(ready_cordic) );
NOR3BX1TS U1114 ( .AN(n1079), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[1]), .Y(n1072) );
NOR3X1TS U1115 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n1066) );
NAND4BX1TS U1116 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n1066), .D(n1069), .Y(n1374) );
BUFX3TS U1117 ( .A(n1374), .Y(n1349) );
BUFX3TS U1118 ( .A(n1349), .Y(n1401) );
NAND2X2TS U1119 ( .A(n1399), .B(n1414), .Y(n1379) );
BUFX3TS U1120 ( .A(n1401), .Y(n1340) );
AOI211X1TS U1121 ( .A0(n1423), .A1(n1414), .B0(n1340), .C0(n1339), .Y(n1067)
);
NAND2X2TS U1122 ( .A(n1364), .B(cont_iter_out[1]), .Y(n1380) );
NOR3X1TS U1123 ( .A(n1422), .B(n1423), .C(n1380), .Y(n1163) );
NOR3X4TS U1124 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(n1416), .C(n1074),
.Y(enab_cont_iter) );
NAND2X1TS U1125 ( .A(cont_var_out[1]), .B(n1409), .Y(n1082) );
NAND2X1TS U1126 ( .A(cont_var_out[0]), .B(n1418), .Y(n1087) );
INVX2TS U1127 ( .A(n1087), .Y(n1070) );
BUFX3TS U1128 ( .A(n1070), .Y(n1274) );
OR2X2TS U1129 ( .A(n1418), .B(n1409), .Y(n1260) );
BUFX3TS U1130 ( .A(n1260), .Y(n1100) );
AOI22X1TS U1131 ( .A0(n1274), .A1(d_ff2_X[23]), .B0(d_ff2_Z[23]), .B1(n1135),
.Y(n1071) );
NAND3BX1TS U1132 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(n1072), .Y(n1261) );
NOR3BX2TS U1133 ( .AN(n1261), .B(enab_cont_iter), .C(ready_add_subt), .Y(
n1291) );
NAND2X1TS U1134 ( .A(n1291), .B(cont_var_out[1]), .Y(n1073) );
NAND3BX1TS U1135 ( .AN(n1074), .B(inst_CORDIC_FSM_v3_state_reg[5]), .C(n1416), .Y(n1262) );
NAND2X1TS U1136 ( .A(n1261), .B(n1262), .Y(beg_add_subt) );
INVX2TS U1137 ( .A(rst), .Y(n281) );
CLKBUFX2TS U1138 ( .A(n281), .Y(n1075) );
BUFX3TS U1139 ( .A(n1076), .Y(n1442) );
BUFX3TS U1140 ( .A(n1075), .Y(n1440) );
BUFX3TS U1141 ( .A(n1076), .Y(n1439) );
BUFX3TS U1142 ( .A(n1075), .Y(n1438) );
BUFX3TS U1143 ( .A(n1075), .Y(n1437) );
CLKBUFX2TS U1144 ( .A(n281), .Y(n1077) );
BUFX3TS U1145 ( .A(n1078), .Y(n1435) );
BUFX3TS U1146 ( .A(n1078), .Y(n1434) );
BUFX3TS U1147 ( .A(n1077), .Y(n1433) );
BUFX3TS U1148 ( .A(n1078), .Y(n1460) );
BUFX3TS U1149 ( .A(n1460), .Y(n1457) );
BUFX3TS U1150 ( .A(n1460), .Y(n1456) );
BUFX3TS U1151 ( .A(n1460), .Y(n1455) );
BUFX3TS U1152 ( .A(n1076), .Y(n1459) );
BUFX3TS U1153 ( .A(n1459), .Y(n1454) );
BUFX3TS U1154 ( .A(n1459), .Y(n1453) );
BUFX3TS U1155 ( .A(n1459), .Y(n1452) );
BUFX3TS U1156 ( .A(n1459), .Y(n1451) );
BUFX3TS U1157 ( .A(n1459), .Y(n1450) );
BUFX3TS U1158 ( .A(n1077), .Y(n1436) );
BUFX3TS U1159 ( .A(n1076), .Y(n1443) );
BUFX3TS U1160 ( .A(n1076), .Y(n1444) );
BUFX3TS U1161 ( .A(n1075), .Y(n1445) );
BUFX3TS U1162 ( .A(n1076), .Y(n1446) );
BUFX3TS U1163 ( .A(n1076), .Y(n1447) );
BUFX3TS U1164 ( .A(n1075), .Y(n1448) );
BUFX3TS U1165 ( .A(n1078), .Y(n1449) );
BUFX3TS U1166 ( .A(n1076), .Y(n1441) );
BUFX3TS U1167 ( .A(n1077), .Y(n1425) );
BUFX3TS U1168 ( .A(n1077), .Y(n1426) );
BUFX3TS U1169 ( .A(n1078), .Y(n1427) );
BUFX3TS U1170 ( .A(n1077), .Y(n1428) );
BUFX3TS U1171 ( .A(n1460), .Y(n1458) );
BUFX3TS U1172 ( .A(n1078), .Y(n1429) );
BUFX3TS U1173 ( .A(n1078), .Y(n1432) );
BUFX3TS U1174 ( .A(n1078), .Y(n1430) );
BUFX3TS U1175 ( .A(n1078), .Y(n1431) );
NAND3X1TS U1176 ( .A(n1191), .B(n1288), .C(cont_iter_out[1]), .Y(n1263) );
INVX2TS U1177 ( .A(n1082), .Y(n1097) );
CLKBUFX2TS U1178 ( .A(n1097), .Y(n1265) );
NAND2X2TS U1179 ( .A(n1265), .B(ready_add_subt), .Y(n1305) );
CLKBUFX2TS U1180 ( .A(n1305), .Y(n1304) );
INVX2TS U1181 ( .A(n1304), .Y(n1301) );
BUFX3TS U1182 ( .A(n1305), .Y(n1302) );
BUFX3TS U1183 ( .A(n1305), .Y(n1306) );
AOI22X1TS U1184 ( .A0(n1274), .A1(d_ff3_sh_y_out[29]), .B0(n1145), .B1(
d_ff3_LUT_out[27]), .Y(n1081) );
OAI21XLTS U1185 ( .A0(n1082), .A1(n1063), .B0(n1081), .Y(add_subt_dataB[29])
);
BUFX3TS U1186 ( .A(n1265), .Y(n1277) );
AOI22X1TS U1187 ( .A0(n1277), .A1(d_ff3_sh_x_out[15]), .B0(n1274), .B1(
d_ff3_sh_y_out[15]), .Y(n1083) );
OAI21XLTS U1188 ( .A0(n1100), .A1(n1412), .B0(n1083), .Y(add_subt_dataB[15])
);
BUFX3TS U1189 ( .A(n1265), .Y(n1280) );
AOI22X1TS U1190 ( .A0(n1280), .A1(d_ff3_sh_x_out[21]), .B0(n1274), .B1(
d_ff3_sh_y_out[21]), .Y(n1084) );
OAI21XLTS U1191 ( .A0(n1100), .A1(n1062), .B0(n1084), .Y(add_subt_dataB[21])
);
BUFX3TS U1192 ( .A(n1265), .Y(n1284) );
AOI22X1TS U1193 ( .A0(n1284), .A1(d_ff2_Y[24]), .B0(d_ff2_Z[24]), .B1(n1142),
.Y(n1085) );
OAI21XLTS U1194 ( .A0(n1087), .A1(n1415), .B0(n1085), .Y(add_subt_dataA[24])
);
AOI22X1TS U1195 ( .A0(n1277), .A1(d_ff2_Y[28]), .B0(d_ff2_Z[28]), .B1(n1135),
.Y(n1086) );
OAI21XLTS U1196 ( .A0(n1087), .A1(n1420), .B0(n1086), .Y(add_subt_dataA[28])
);
BUFX3TS U1197 ( .A(n1401), .Y(n1397) );
BUFX3TS U1198 ( .A(n1274), .Y(n1133) );
AOI22X1TS U1199 ( .A0(n1277), .A1(d_ff3_sh_x_out[18]), .B0(n1133), .B1(
d_ff3_sh_y_out[18]), .Y(n1088) );
OAI21XLTS U1200 ( .A0(n1260), .A1(n1461), .B0(n1088), .Y(add_subt_dataB[18])
);
AOI22X1TS U1201 ( .A0(n1277), .A1(d_ff3_sh_x_out[12]), .B0(n1133), .B1(
d_ff3_sh_y_out[12]), .Y(n1089) );
OAI21XLTS U1202 ( .A0(n1100), .A1(n1061), .B0(n1089), .Y(add_subt_dataB[12])
);
INVX2TS U1203 ( .A(n1191), .Y(n1341) );
NAND2X1TS U1204 ( .A(n1353), .B(n1375), .Y(n1346) );
AOI32X1TS U1205 ( .A0(n1064), .A1(n1399), .A2(n1341), .B0(d_ff3_LUT_out[23]),
.B1(n1340), .Y(n1090) );
BUFX3TS U1206 ( .A(n1133), .Y(n1276) );
AOI22X1TS U1207 ( .A0(n1280), .A1(d_ff3_sh_x_out[20]), .B0(n1276), .B1(
d_ff3_sh_y_out[20]), .Y(n1091) );
AOI22X1TS U1208 ( .A0(n1277), .A1(d_ff3_sh_x_out[16]), .B0(n1276), .B1(
d_ff3_sh_y_out[16]), .Y(n1092) );
AOI22X1TS U1209 ( .A0(n1277), .A1(d_ff3_sh_x_out[3]), .B0(n1276), .B1(
d_ff3_sh_y_out[3]), .Y(n1093) );
AOI22X1TS U1210 ( .A0(n1280), .A1(d_ff3_sh_x_out[17]), .B0(n1276), .B1(
d_ff3_sh_y_out[17]), .Y(n1094) );
AOI22X1TS U1211 ( .A0(n1277), .A1(d_ff3_sh_x_out[9]), .B0(n1276), .B1(
d_ff3_sh_y_out[9]), .Y(n1095) );
AOI22X1TS U1212 ( .A0(n1277), .A1(d_ff3_sh_x_out[13]), .B0(n1276), .B1(
d_ff3_sh_y_out[13]), .Y(n1096) );
CLKBUFX2TS U1213 ( .A(n1097), .Y(n1110) );
BUFX3TS U1214 ( .A(n1110), .Y(n1131) );
BUFX3TS U1215 ( .A(n1274), .Y(n1286) );
INVX2TS U1216 ( .A(n1098), .Y(add_subt_dataB[10]) );
INVX2TS U1217 ( .A(n1099), .Y(add_subt_dataB[23]) );
INVX2TS U1218 ( .A(n1101), .Y(add_subt_dataB[25]) );
AOI222X1TS U1219 ( .A0(n1131), .A1(d_ff3_sh_x_out[26]), .B0(n1286), .B1(
d_ff3_sh_y_out[26]), .C0(n1283), .C1(d_ff3_LUT_out[26]), .Y(n1102) );
INVX2TS U1220 ( .A(n1102), .Y(add_subt_dataB[26]) );
INVX2TS U1221 ( .A(n1103), .Y(add_subt_dataB[8]) );
INVX2TS U1222 ( .A(n1104), .Y(add_subt_dataB[24]) );
INVX2TS U1223 ( .A(n1105), .Y(add_subt_dataB[4]) );
INVX2TS U1224 ( .A(n1106), .Y(add_subt_dataB[2]) );
NAND2X1TS U1225 ( .A(n1064), .B(n1417), .Y(intadd_364_CI) );
INVX2TS U1226 ( .A(n1346), .Y(n1376) );
AOI22X1TS U1227 ( .A0(d_ff2_Y[23]), .A1(n1376), .B0(d_ff3_sh_y_out[23]),
.B1(n1397), .Y(n1107) );
AOI21X1TS U1228 ( .A0(n1422), .A1(n1064), .B0(cont_iter_out[3]), .Y(n1239)
);
AOI22X1TS U1229 ( .A0(n1399), .A1(n1239), .B0(d_ff3_LUT_out[26]), .B1(n1397),
.Y(n1108) );
BUFX3TS U1230 ( .A(n1110), .Y(n1136) );
BUFX3TS U1231 ( .A(n1133), .Y(n1130) );
INVX2TS U1232 ( .A(n1260), .Y(n1279) );
INVX2TS U1233 ( .A(n1109), .Y(add_subt_dataA[31]) );
BUFX3TS U1234 ( .A(n1133), .Y(n1127) );
INVX2TS U1235 ( .A(n1111), .Y(add_subt_dataA[16]) );
INVX2TS U1236 ( .A(n1112), .Y(add_subt_dataA[26]) );
INVX2TS U1237 ( .A(n1113), .Y(add_subt_dataA[21]) );
INVX2TS U1238 ( .A(n1114), .Y(add_subt_dataA[19]) );
INVX2TS U1239 ( .A(n1115), .Y(add_subt_dataA[25]) );
INVX2TS U1240 ( .A(n1116), .Y(add_subt_dataA[22]) );
INVX2TS U1241 ( .A(n1117), .Y(add_subt_dataA[18]) );
INVX2TS U1242 ( .A(n1118), .Y(add_subt_dataA[17]) );
AOI222X1TS U1243 ( .A0(n1131), .A1(d_ff3_sh_x_out[6]), .B0(n1130), .B1(
d_ff3_sh_y_out[6]), .C0(d_ff3_LUT_out[6]), .C1(n1279), .Y(n1119) );
INVX2TS U1244 ( .A(n1119), .Y(add_subt_dataB[6]) );
INVX2TS U1245 ( .A(n1120), .Y(add_subt_dataA[13]) );
INVX2TS U1246 ( .A(n1121), .Y(add_subt_dataA[15]) );
INVX2TS U1247 ( .A(n1122), .Y(add_subt_dataA[14]) );
INVX2TS U1248 ( .A(n1123), .Y(add_subt_dataA[11]) );
INVX2TS U1249 ( .A(n1124), .Y(add_subt_dataA[12]) );
INVX2TS U1250 ( .A(n1125), .Y(add_subt_dataA[20]) );
INVX2TS U1251 ( .A(n1126), .Y(add_subt_dataA[5]) );
INVX2TS U1252 ( .A(n1128), .Y(add_subt_dataA[10]) );
INVX2TS U1253 ( .A(n1129), .Y(add_subt_dataB[0]) );
INVX2TS U1254 ( .A(n1132), .Y(add_subt_dataB[1]) );
INVX2TS U1255 ( .A(n1134), .Y(add_subt_dataA[9]) );
INVX2TS U1256 ( .A(n1137), .Y(add_subt_dataA[0]) );
INVX2TS U1257 ( .A(n1138), .Y(add_subt_dataA[2]) );
INVX2TS U1258 ( .A(n1139), .Y(add_subt_dataA[1]) );
INVX2TS U1259 ( .A(n1140), .Y(add_subt_dataA[8]) );
INVX2TS U1260 ( .A(n1141), .Y(add_subt_dataA[4]) );
INVX2TS U1261 ( .A(n1143), .Y(add_subt_dataA[3]) );
INVX2TS U1262 ( .A(n1144), .Y(add_subt_dataA[7]) );
INVX2TS U1263 ( .A(n1146), .Y(add_subt_dataA[6]) );
XNOR2X1TS U1264 ( .A(n1152), .B(d_ff_Xn[31]), .Y(n1155) );
XNOR2X1TS U1265 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n1148) );
XNOR2X1TS U1266 ( .A(d_ff1_shift_region_flag_out[0]), .B(n1148), .Y(n1150)
);
BUFX3TS U1267 ( .A(n1151), .Y(n1173) );
BUFX3TS U1268 ( .A(n1173), .Y(n1253) );
XOR2X1TS U1269 ( .A(d_ff_Yn[31]), .B(n1152), .Y(n1153) );
AOI22X1TS U1270 ( .A0(n1254), .A1(data_output[31]), .B0(n1253), .B1(n1153),
.Y(n1154) );
AOI222X1TS U1271 ( .A0(n1174), .A1(data_output[0]), .B0(d_ff_Yn[0]), .B1(
n1173), .C0(d_ff_Xn[0]), .C1(n1149), .Y(n1156) );
INVX2TS U1272 ( .A(n1156), .Y(n853) );
NAND3X1TS U1273 ( .A(n1158), .B(inst_CORDIC_FSM_v3_state_reg[0]), .C(n1157),
.Y(n1259) );
NOR2BX1TS U1274 ( .AN(n1259), .B(n1159), .Y(n1160) );
INVX2TS U1275 ( .A(n1160), .Y(n1297) );
INVX2TS U1276 ( .A(n1298), .Y(n1292) );
BUFX3TS U1277 ( .A(n1424), .Y(n1370) );
NOR4X1TS U1278 ( .A(enab_cont_iter), .B(n1390), .C(n1370), .D(beg_add_subt),
.Y(n1161) );
AOI32X1TS U1279 ( .A0(n1292), .A1(n1264), .A2(n1161), .B0(ready_cordic),
.B1(ack_cordic), .Y(n1162) );
INVX2TS U1280 ( .A(n1345), .Y(n1256) );
AOI21X1TS U1281 ( .A0(d_ff3_LUT_out[2]), .A1(n1397), .B0(n1163), .Y(n1164)
);
BUFX3TS U1282 ( .A(n1174), .Y(n1244) );
BUFX3TS U1283 ( .A(n1173), .Y(n1243) );
INVX2TS U1284 ( .A(n1165), .Y(n833) );
BUFX3TS U1285 ( .A(n1174), .Y(n1189) );
AOI222X1TS U1286 ( .A0(n1189), .A1(data_output[8]), .B0(n1173), .B1(
d_ff_Yn[8]), .C0(n1178), .C1(d_ff_Xn[8]), .Y(n1167) );
INVX2TS U1287 ( .A(n1167), .Y(n845) );
AOI222X1TS U1288 ( .A0(n1189), .A1(data_output[9]), .B0(n1173), .B1(
d_ff_Yn[9]), .C0(n1178), .C1(d_ff_Xn[9]), .Y(n1168) );
INVX2TS U1289 ( .A(n1168), .Y(n844) );
AOI222X1TS U1290 ( .A0(n1189), .A1(data_output[4]), .B0(n1173), .B1(
d_ff_Yn[4]), .C0(n1178), .C1(d_ff_Xn[4]), .Y(n1169) );
INVX2TS U1291 ( .A(n1169), .Y(n849) );
AOI222X1TS U1292 ( .A0(n1189), .A1(data_output[5]), .B0(n1173), .B1(
d_ff_Yn[5]), .C0(n1178), .C1(d_ff_Xn[5]), .Y(n1170) );
INVX2TS U1293 ( .A(n1170), .Y(n848) );
AOI222X1TS U1294 ( .A0(n1189), .A1(data_output[7]), .B0(n1151), .B1(
d_ff_Yn[7]), .C0(n1178), .C1(d_ff_Xn[7]), .Y(n1171) );
INVX2TS U1295 ( .A(n1171), .Y(n846) );
AOI222X1TS U1296 ( .A0(n1174), .A1(data_output[2]), .B0(n1173), .B1(
d_ff_Yn[2]), .C0(n1178), .C1(d_ff_Xn[2]), .Y(n1172) );
INVX2TS U1297 ( .A(n1172), .Y(n851) );
AOI222X1TS U1298 ( .A0(n1174), .A1(data_output[1]), .B0(n1173), .B1(
d_ff_Yn[1]), .C0(n1178), .C1(d_ff_Xn[1]), .Y(n1175) );
INVX2TS U1299 ( .A(n1175), .Y(n852) );
AOI222X1TS U1300 ( .A0(n1189), .A1(data_output[6]), .B0(n1173), .B1(
d_ff_Yn[6]), .C0(n1178), .C1(d_ff_Xn[6]), .Y(n1176) );
INVX2TS U1301 ( .A(n1176), .Y(n847) );
INVX2TS U1302 ( .A(n1177), .Y(n843) );
AOI222X1TS U1303 ( .A0(n1189), .A1(data_output[3]), .B0(n1151), .B1(
d_ff_Yn[3]), .C0(n1178), .C1(d_ff_Xn[3]), .Y(n1179) );
INVX2TS U1304 ( .A(n1179), .Y(n850) );
INVX2TS U1305 ( .A(n1180), .Y(n838) );
INVX2TS U1306 ( .A(n1181), .Y(n835) );
INVX2TS U1307 ( .A(n1182), .Y(n842) );
INVX2TS U1308 ( .A(n1183), .Y(n839) );
INVX2TS U1309 ( .A(n1184), .Y(n840) );
INVX2TS U1310 ( .A(n1185), .Y(n837) );
INVX2TS U1311 ( .A(n1186), .Y(n836) );
INVX2TS U1312 ( .A(n1187), .Y(n834) );
INVX2TS U1313 ( .A(n1190), .Y(n841) );
AOI211X1TS U1314 ( .A0(n1064), .A1(n1408), .B0(n1422), .C0(n1379), .Y(n1337)
);
AOI21X1TS U1315 ( .A0(d_ff3_LUT_out[0]), .A1(n1397), .B0(n1337), .Y(n1192)
);
NAND4X1TS U1316 ( .A(n1408), .B(n1413), .C(n1375), .D(n1414), .Y(n1194) );
BUFX3TS U1317 ( .A(n1366), .Y(n1233) );
NOR2X2TS U1318 ( .A(n1235), .B(n1194), .Y(n1204) );
AOI222X1TS U1319 ( .A0(n1235), .A1(d_ff2_Z[0]), .B0(n1233), .B1(d_ff_Zn[0]),
.C0(n1204), .C1(d_ff1_Z[0]), .Y(n1195) );
INVX2TS U1320 ( .A(n1195), .Y(n800) );
AOI222X1TS U1321 ( .A0(n1235), .A1(d_ff2_Z[1]), .B0(n1204), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1233), .Y(n1196) );
INVX2TS U1322 ( .A(n1196), .Y(n799) );
BUFX3TS U1323 ( .A(n1424), .Y(n1372) );
BUFX3TS U1324 ( .A(n1204), .Y(n1219) );
BUFX3TS U1325 ( .A(n1366), .Y(n1229) );
INVX2TS U1326 ( .A(n1197), .Y(n781) );
INVX2TS U1327 ( .A(n1370), .Y(n1230) );
INVX2TS U1328 ( .A(n1198), .Y(n782) );
INVX2TS U1329 ( .A(n1199), .Y(n783) );
BUFX3TS U1330 ( .A(n1204), .Y(n1226) );
BUFX3TS U1331 ( .A(n1366), .Y(n1225) );
INVX2TS U1332 ( .A(n1200), .Y(n776) );
INVX2TS U1333 ( .A(n1201), .Y(n787) );
INVX2TS U1334 ( .A(n1202), .Y(n788) );
INVX2TS U1335 ( .A(n1203), .Y(n777) );
BUFX3TS U1336 ( .A(n1204), .Y(n1234) );
INVX2TS U1337 ( .A(n1205), .Y(n789) );
INVX2TS U1338 ( .A(n1206), .Y(n784) );
INVX2TS U1339 ( .A(n1207), .Y(n785) );
INVX2TS U1340 ( .A(n1208), .Y(n791) );
INVX2TS U1341 ( .A(n1209), .Y(n778) );
INVX2TS U1342 ( .A(n1210), .Y(n779) );
INVX2TS U1343 ( .A(n1211), .Y(n780) );
INVX2TS U1344 ( .A(n1212), .Y(n794) );
INVX2TS U1345 ( .A(n1213), .Y(n795) );
AOI222X1TS U1346 ( .A0(n1235), .A1(d_ff2_Z[4]), .B0(n1234), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n1233), .Y(n1214) );
INVX2TS U1347 ( .A(n1214), .Y(n796) );
AOI222X1TS U1348 ( .A0(n1235), .A1(d_ff2_Z[3]), .B0(n1234), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n1233), .Y(n1215) );
INVX2TS U1349 ( .A(n1215), .Y(n797) );
AOI222X1TS U1350 ( .A0(n1373), .A1(d_ff2_Z[28]), .B0(n1226), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n1225), .Y(n1216) );
INVX2TS U1351 ( .A(n1216), .Y(n772) );
AOI222X1TS U1352 ( .A0(n1235), .A1(d_ff2_Z[2]), .B0(n1234), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1233), .Y(n1217) );
INVX2TS U1353 ( .A(n1217), .Y(n798) );
INVX2TS U1354 ( .A(n1218), .Y(n775) );
INVX2TS U1355 ( .A(n1220), .Y(n786) );
INVX2TS U1356 ( .A(n1372), .Y(n1373) );
INVX2TS U1357 ( .A(n1221), .Y(n771) );
AOI222X1TS U1358 ( .A0(n1227), .A1(d_ff2_Z[30]), .B0(n1226), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n1366), .Y(n1222) );
INVX2TS U1359 ( .A(n1222), .Y(n770) );
INVX2TS U1360 ( .A(n1223), .Y(n769) );
AOI222X1TS U1361 ( .A0(n1365), .A1(d_ff2_Z[27]), .B0(n1226), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n1225), .Y(n1224) );
INVX2TS U1362 ( .A(n1224), .Y(n773) );
AOI222X1TS U1363 ( .A0(n1404), .A1(d_ff2_Z[26]), .B0(n1226), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n1225), .Y(n1228) );
INVX2TS U1364 ( .A(n1228), .Y(n774) );
INVX2TS U1365 ( .A(n1231), .Y(n790) );
INVX2TS U1366 ( .A(n1232), .Y(n792) );
INVX2TS U1367 ( .A(n1236), .Y(n793) );
OAI2BB1X1TS U1368 ( .A0N(n1339), .A1N(n1256), .B0(n1364), .Y(n1328) );
INVX2TS U1369 ( .A(n1380), .Y(n1335) );
NAND2X1TS U1370 ( .A(n1335), .B(n1341), .Y(n1342) );
INVX2TS U1371 ( .A(n1379), .Y(n1330) );
NAND2X1TS U1372 ( .A(n1064), .B(n1341), .Y(n1237) );
AOI22X1TS U1373 ( .A0(n1330), .A1(n1237), .B0(d_ff3_LUT_out[24]), .B1(n1340),
.Y(n1238) );
AOI22X1TS U1374 ( .A0(n1239), .A1(n1330), .B0(d_ff3_LUT_out[4]), .B1(n1340),
.Y(n1240) );
AOI222X1TS U1375 ( .A0(n1254), .A1(data_output[30]), .B0(n1253), .B1(
d_ff_Yn[30]), .C0(n1252), .C1(d_ff_Xn[30]), .Y(n1241) );
INVX2TS U1376 ( .A(n1241), .Y(n823) );
INVX2TS U1377 ( .A(n1242), .Y(n830) );
INVX2TS U1378 ( .A(n1245), .Y(n832) );
INVX2TS U1379 ( .A(n1246), .Y(n831) );
INVX2TS U1380 ( .A(n1247), .Y(n829) );
INVX2TS U1381 ( .A(n1248), .Y(n828) );
INVX2TS U1382 ( .A(n1249), .Y(n826) );
INVX2TS U1383 ( .A(n1250), .Y(n827) );
INVX2TS U1384 ( .A(n1251), .Y(n825) );
INVX2TS U1385 ( .A(n1255), .Y(n824) );
NAND2X1TS U1386 ( .A(n1330), .B(n1341), .Y(n1257) );
NAND2X1TS U1387 ( .A(n1335), .B(n1332), .Y(n1338) );
NOR2BX1TS U1388 ( .AN(beg_fsm_cordic), .B(n1259), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
INVX2TS U1389 ( .A(n1306), .Y(n1309) );
OAI22X1TS U1390 ( .A0(n1309), .A1(n1262), .B0(n1261), .B1(n1260), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
OAI22X1TS U1391 ( .A0(ack_cordic), .A1(n1264), .B0(n1287), .B1(n1263), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
AOI2BB2XLTS U1392 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(op_add_subt) );
AO22XLTS U1393 ( .A0(n1265), .A1(d_ff3_sh_x_out[31]), .B0(n1133), .B1(
d_ff3_sh_y_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U1394 ( .A0(n1265), .A1(d_ff3_sh_x_out[30]), .B0(n1070), .B1(
d_ff3_sh_y_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U1395 ( .A0(n1280), .A1(d_ff3_sh_x_out[28]), .B0(n1274), .B1(
d_ff3_sh_y_out[28]), .Y(n1266) );
NAND2X1TS U1396 ( .A(n1142), .B(d_ff3_LUT_out[27]), .Y(n1267) );
NAND2X1TS U1397 ( .A(n1266), .B(n1267), .Y(add_subt_dataB[28]) );
AOI22X1TS U1398 ( .A0(n1280), .A1(d_ff3_sh_x_out[27]), .B0(n1274), .B1(
d_ff3_sh_y_out[27]), .Y(n1268) );
NAND2X1TS U1399 ( .A(n1268), .B(n1267), .Y(add_subt_dataB[27]) );
INVX2TS U1400 ( .A(n1260), .Y(n1271) );
AOI22X1TS U1401 ( .A0(n1280), .A1(d_ff3_sh_x_out[22]), .B0(n1274), .B1(
d_ff3_sh_y_out[22]), .Y(n1269) );
OAI2BB1X1TS U1402 ( .A0N(n1271), .A1N(d_ff3_LUT_out[19]), .B0(n1269), .Y(
add_subt_dataB[22]) );
AOI22X1TS U1403 ( .A0(n1280), .A1(d_ff3_sh_x_out[19]), .B0(n1276), .B1(
d_ff3_sh_y_out[19]), .Y(n1270) );
OAI2BB1X1TS U1404 ( .A0N(n1271), .A1N(d_ff3_LUT_out[19]), .B0(n1270), .Y(
add_subt_dataB[19]) );
AOI22X1TS U1405 ( .A0(n1280), .A1(d_ff3_sh_x_out[14]), .B0(n1276), .B1(
d_ff3_sh_y_out[14]), .Y(n1272) );
OAI2BB1X1TS U1406 ( .A0N(n1279), .A1N(d_ff3_LUT_out[5]), .B0(n1272), .Y(
add_subt_dataB[14]) );
AOI22X1TS U1407 ( .A0(n1280), .A1(d_ff3_sh_x_out[11]), .B0(n1276), .B1(
d_ff3_sh_y_out[11]), .Y(n1273) );
OAI2BB1X1TS U1408 ( .A0N(n1279), .A1N(d_ff3_LUT_out[7]), .B0(n1273), .Y(
add_subt_dataB[11]) );
AOI22X1TS U1409 ( .A0(n1277), .A1(d_ff3_sh_x_out[7]), .B0(n1274), .B1(
d_ff3_sh_y_out[7]), .Y(n1275) );
OAI2BB1X1TS U1410 ( .A0N(n1279), .A1N(d_ff3_LUT_out[7]), .B0(n1275), .Y(
add_subt_dataB[7]) );
AOI22X1TS U1411 ( .A0(n1277), .A1(d_ff3_sh_x_out[5]), .B0(n1276), .B1(
d_ff3_sh_y_out[5]), .Y(n1278) );
OAI2BB1X1TS U1412 ( .A0N(n1279), .A1N(d_ff3_LUT_out[5]), .B0(n1278), .Y(
add_subt_dataB[5]) );
AOI22X1TS U1413 ( .A0(n1280), .A1(d_ff2_Y[30]), .B0(d_ff2_Z[30]), .B1(n1142),
.Y(n1281) );
OAI2BB1X1TS U1414 ( .A0N(n1286), .A1N(d_ff2_X[30]), .B0(n1281), .Y(
add_subt_dataA[30]) );
AOI22X1TS U1415 ( .A0(n1284), .A1(d_ff2_Y[29]), .B0(d_ff2_Z[29]), .B1(n1142),
.Y(n1282) );
OAI2BB1X1TS U1416 ( .A0N(n1286), .A1N(d_ff2_X[29]), .B0(n1282), .Y(
add_subt_dataA[29]) );
AOI22X1TS U1417 ( .A0(n1284), .A1(d_ff2_Y[27]), .B0(d_ff2_Z[27]), .B1(n1145),
.Y(n1285) );
OAI2BB1X1TS U1418 ( .A0N(n1286), .A1N(d_ff2_X[27]), .B0(n1285), .Y(
add_subt_dataA[27]) );
AOI22X1TS U1419 ( .A0(enab_cont_iter), .A1(n1288), .B0(n1423), .B1(n1287),
.Y(n989) );
NAND2X1TS U1420 ( .A(n1422), .B(n1289), .Y(n1290) );
XNOR2X1TS U1421 ( .A(cont_iter_out[3]), .B(n1290), .Y(n986) );
BUFX3TS U1422 ( .A(n1297), .Y(n1298) );
CLKBUFX2TS U1423 ( .A(n1298), .Y(n1299) );
BUFX3TS U1424 ( .A(n1297), .Y(n1293) );
INVX2TS U1425 ( .A(n1299), .Y(n1294) );
BUFX3TS U1426 ( .A(n1298), .Y(n1295) );
INVX2TS U1427 ( .A(n1299), .Y(n1296) );
INVX2TS U1428 ( .A(n1299), .Y(n1300) );
INVX2TS U1429 ( .A(n1304), .Y(n1303) );
INVX2TS U1430 ( .A(n1304), .Y(n1307) );
CLKBUFX2TS U1431 ( .A(n1306), .Y(n1308) );
BUFX3TS U1432 ( .A(n1313), .Y(n1315) );
INVX2TS U1433 ( .A(n1315), .Y(n1310) );
BUFX3TS U1434 ( .A(n1313), .Y(n1314) );
INVX2TS U1435 ( .A(n1314), .Y(n1312) );
INVX2TS U1436 ( .A(n1314), .Y(n1316) );
CLKBUFX2TS U1437 ( .A(n1315), .Y(n1317) );
INVX2TS U1438 ( .A(n1314), .Y(n1318) );
NAND3X1TS U1439 ( .A(n1418), .B(n1409), .C(ready_add_subt), .Y(n1322) );
BUFX3TS U1440 ( .A(n1322), .Y(n1321) );
BUFX3TS U1441 ( .A(n1321), .Y(n1320) );
INVX2TS U1442 ( .A(n1320), .Y(n1319) );
CLKBUFX2TS U1443 ( .A(n1321), .Y(n1326) );
INVX2TS U1444 ( .A(n1326), .Y(n1323) );
INVX2TS U1445 ( .A(n1326), .Y(n1325) );
INVX2TS U1446 ( .A(n1326), .Y(n1327) );
AOI22X1TS U1447 ( .A0(n1330), .A1(n1332), .B0(d_ff3_LUT_out[1]), .B1(n1340),
.Y(n1329) );
NAND2X1TS U1448 ( .A(n1329), .B(n1328), .Y(n820) );
AOI22X1TS U1449 ( .A0(n1330), .A1(n1334), .B0(d_ff3_LUT_out[5]), .B1(n1340),
.Y(n1331) );
NAND2X1TS U1450 ( .A(n1331), .B(n1338), .Y(n816) );
AOI22X1TS U1451 ( .A0(n1364), .A1(n1332), .B0(d_ff3_LUT_out[7]), .B1(n1340),
.Y(n1333) );
NAND2X1TS U1452 ( .A(n1333), .B(n1342), .Y(n814) );
INVX2TS U1453 ( .A(n1349), .Y(n1403) );
AOI22X1TS U1454 ( .A0(n1335), .A1(n1334), .B0(d_ff3_LUT_out[10]), .B1(n1397),
.Y(n1336) );
OAI221XLTS U1455 ( .A0(n1390), .A1(n1061), .B0(n1393), .B1(n1339), .C0(n1338), .Y(n810) );
AOI22X1TS U1456 ( .A0(n1364), .A1(n1343), .B0(n1461), .B1(n1340), .Y(n809)
);
BUFX3TS U1457 ( .A(n1401), .Y(n1382) );
OAI221XLTS U1458 ( .A0(n1353), .A1(n1062), .B0(n1393), .B1(n1343), .C0(n1342), .Y(n806) );
AOI22X1TS U1459 ( .A0(n1345), .A1(n1344), .B0(d_ff3_LUT_out[25]), .B1(n1397),
.Y(n1347) );
AOI32X1TS U1460 ( .A0(n1379), .A1(n1347), .A2(n1346), .B0(n1422), .B1(n1347),
.Y(n803) );
INVX2TS U1461 ( .A(n1349), .Y(n1362) );
BUFX3TS U1462 ( .A(n1368), .Y(n1350) );
INVX2TS U1463 ( .A(n1372), .Y(n1348) );
INVX2TS U1464 ( .A(n1374), .Y(n1395) );
INVX2TS U1465 ( .A(n1372), .Y(n1351) );
BUFX3TS U1466 ( .A(n1368), .Y(n1405) );
INVX2TS U1467 ( .A(n1349), .Y(n1407) );
INVX2TS U1468 ( .A(n1372), .Y(n1404) );
BUFX3TS U1469 ( .A(n1368), .Y(n1363) );
INVX2TS U1470 ( .A(n1372), .Y(n1365) );
NOR2X1TS U1471 ( .A(d_ff2_Y[27]), .B(intadd_364_n1), .Y(n1355) );
AOI21X1TS U1472 ( .A0(intadd_364_n1), .A1(d_ff2_Y[27]), .B0(n1355), .Y(n1354) );
OR3X1TS U1473 ( .A(d_ff2_Y[27]), .B(d_ff2_Y[28]), .C(intadd_364_n1), .Y(
n1357) );
NOR2X1TS U1474 ( .A(d_ff2_Y[29]), .B(n1357), .Y(n1359) );
AOI21X1TS U1475 ( .A0(d_ff2_Y[29]), .A1(n1357), .B0(n1359), .Y(n1358) );
XOR2X1TS U1476 ( .A(d_ff2_Y[30]), .B(n1359), .Y(n1361) );
CLKBUFX2TS U1477 ( .A(n1372), .Y(n1369) );
OA22X1TS U1478 ( .A0(d_ff_Xn[1]), .A1(n1059), .B0(n1369), .B1(d_ff2_X[1]),
.Y(n701) );
OA22X1TS U1479 ( .A0(d_ff_Xn[2]), .A1(n1371), .B0(n1369), .B1(d_ff2_X[2]),
.Y(n699) );
OA22X1TS U1480 ( .A0(d_ff_Xn[3]), .A1(n1059), .B0(n1369), .B1(d_ff2_X[3]),
.Y(n697) );
OA22X1TS U1481 ( .A0(d_ff_Xn[5]), .A1(n1371), .B0(n1369), .B1(d_ff2_X[5]),
.Y(n693) );
OA22X1TS U1482 ( .A0(d_ff_Xn[6]), .A1(n1059), .B0(n1369), .B1(d_ff2_X[6]),
.Y(n691) );
OA22X1TS U1483 ( .A0(d_ff_Xn[7]), .A1(n1371), .B0(n1372), .B1(d_ff2_X[7]),
.Y(n689) );
OA22X1TS U1484 ( .A0(d_ff_Xn[10]), .A1(n1059), .B0(n1370), .B1(d_ff2_X[10]),
.Y(n683) );
OA22X1TS U1485 ( .A0(d_ff_Xn[12]), .A1(n1371), .B0(n1424), .B1(d_ff2_X[12]),
.Y(n679) );
OA22X1TS U1486 ( .A0(d_ff_Xn[13]), .A1(n1059), .B0(n1424), .B1(d_ff2_X[13]),
.Y(n677) );
OA22X1TS U1487 ( .A0(d_ff_Xn[14]), .A1(n1371), .B0(n1424), .B1(d_ff2_X[14]),
.Y(n675) );
OA22X1TS U1488 ( .A0(d_ff_Xn[16]), .A1(n1371), .B0(n1424), .B1(d_ff2_X[16]),
.Y(n671) );
OA22X1TS U1489 ( .A0(d_ff_Xn[17]), .A1(n1059), .B0(n1424), .B1(d_ff2_X[17]),
.Y(n669) );
OA22X1TS U1490 ( .A0(d_ff_Xn[19]), .A1(n1371), .B0(n1424), .B1(d_ff2_X[19]),
.Y(n665) );
OA22X1TS U1491 ( .A0(d_ff_Xn[20]), .A1(n1059), .B0(n1424), .B1(d_ff2_X[20]),
.Y(n663) );
OA22X1TS U1492 ( .A0(n1370), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n1059),
.Y(n656) );
OA22X1TS U1493 ( .A0(d_ff_Xn[25]), .A1(n1371), .B0(n1369), .B1(d_ff2_X[25]),
.Y(n655) );
OA22X1TS U1494 ( .A0(d_ff_Xn[26]), .A1(n1059), .B0(n1369), .B1(d_ff2_X[26]),
.Y(n654) );
OA22X1TS U1495 ( .A0(n1370), .A1(d_ff2_X[27]), .B0(d_ff_Xn[27]), .B1(n1371),
.Y(n653) );
OA22X1TS U1496 ( .A0(n1372), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1059),
.Y(n652) );
OA22X1TS U1497 ( .A0(n1372), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n1193),
.Y(n651) );
NOR2X2TS U1498 ( .A(d_ff2_X[23]), .B(n1375), .Y(n1383) );
AOI22X1TS U1499 ( .A0(n1376), .A1(d_ff2_X[23]), .B0(d_ff3_sh_x_out[23]),
.B1(n1397), .Y(n1377) );
OAI2BB1X1TS U1500 ( .A0N(n1388), .A1N(n1383), .B0(n1377), .Y(n649) );
XOR2X1TS U1501 ( .A(n1383), .B(d_ff2_X[24]), .Y(n1378) );
MXI2X1TS U1502 ( .A(n1380), .B(n1379), .S0(n1378), .Y(n1381) );
AOI222X1TS U1503 ( .A0(cont_iter_out[1]), .A1(n1383), .B0(cont_iter_out[1]),
.B1(n1415), .C0(n1383), .C1(n1415), .Y(n1385) );
CMPR32X2TS U1504 ( .A(n1413), .B(d_ff2_X[25]), .C(n1385), .CO(n1387), .S(
n1384) );
CMPR32X2TS U1505 ( .A(n1408), .B(d_ff2_X[26]), .C(n1387), .CO(n1391), .S(
n1386) );
NOR2X1TS U1506 ( .A(d_ff2_X[27]), .B(n1391), .Y(n1392) );
AOI21X1TS U1507 ( .A0(n1391), .A1(d_ff2_X[27]), .B0(n1392), .Y(n1389) );
OR3X1TS U1508 ( .A(n1391), .B(d_ff2_X[27]), .C(d_ff2_X[28]), .Y(n1396) );
NOR2X1TS U1509 ( .A(d_ff2_X[29]), .B(n1396), .Y(n1400) );
AOI21X1TS U1510 ( .A0(d_ff2_X[29]), .A1(n1396), .B0(n1400), .Y(n1398) );
AOI22X1TS U1511 ( .A0(n1390), .A1(n1398), .B0(n1063), .B1(n1397), .Y(n643)
);
XOR2X1TS U1512 ( .A(d_ff2_X[30]), .B(n1400), .Y(n1402) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S50KAPWR_2_V
`define SKY130_FD_SC_LP__DLYBUF4S50KAPWR_2_V
/**
* dlybuf4s50kapwr: Delay Buffer 4-stage 0.50um length inner stage
* gates on keep-alive power rail.
*
* Verilog wrapper for dlybuf4s50kapwr with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s50kapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlybuf4s50kapwr_2 (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlybuf4s50kapwr base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlybuf4s50kapwr_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlybuf4s50kapwr base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S50KAPWR_2_V
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
test tt();
defparam foo = 3; /* This should generate an error. */
endmodule // main
module test;
parameter foo = 10;
reg [foo-1:0] bar;
endmodule // test
|
module premuat_8(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [27:0] o1;
reg signed [27:0] o2;
reg signed [27:0] o3;
reg signed [27:0] o4;
reg signed [27:0] o5;
reg signed [27:0] o6;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1=i_2;
o2=i_4;
o3=i_6;
o4=i_1;
o5=i_3;
o6=i_5;
end
else
begin
o1=i_4;
o2=i_1;
o3=i_5;
o4=i_2;
o5=i_6;
o6=i_3;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=i_7;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:04:52 01/04/2013
// Design Name: ctrl_reg_readback
// Module Name: H:/Firmware/FONT5_base/ISE13/FONT5_base/ctrl_reg_rb_tb.v
// Project Name: FONT5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ctrl_reg_readback
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ctrl_reg_rb_tb;
// Inputs
reg clk;
reg rst;
//reg [6:0] data;
reg tx_en;
reg tx_data_loaded;
// Outputs
wire tx_data_ready;
//wire [7:0] tx_data;
wire tx_complete;
wire [5:0] tx_cnt;
// Instantiate the Unit Under Test (UUT)
ctrl_reg_readback uut (
.clk(clk),
.rst(rst),
//.data(data),
.tx_en(tx_en),
.tx_data_loaded(tx_data_loaded),
.tx_data_ready(tx_data_ready),
//.tx_data(tx_data),
.tx_complete(tx_complete),
.tx_cnt(tx_cnt)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
//data = 0;
tx_en = 0;
tx_data_loaded = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst = 1;
tx_en = 0;
#100;
rst=0;
tx_en = 1;
end
always #12.5 clk = !clk;
always @(*) begin
if (tx_data_ready) tx_data_loaded = 1;
else if (tx_data_loaded) #0 tx_data_loaded = 0;
else tx_data_loaded = tx_data_loaded;
if (tx_complete) tx_en=0;
else tx_en = tx_en;
end
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll1.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pll1 (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "200.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "5000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_demux_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_0_axis_tready = 0;
reg output_1_axis_tready = 0;
reg output_2_axis_tready = 0;
reg output_3_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_0_axis_tdata;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire output_0_axis_tuser;
wire [7:0] output_1_axis_tdata;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire output_1_axis_tuser;
wire [7:0] output_2_axis_tdata;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire output_2_axis_tuser;
wire [7:0] output_3_axis_tdata;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser);
// dump file
$dumpfile("test_axis_demux_4.lxt");
$dumpvars(0, test_axis_demux_4);
end
axis_demux_4 #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tready(output_0_axis_tready),
.output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tready(output_1_axis_tready),
.output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tready(output_2_axis_tready),
.output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tready(output_3_axis_tready),
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
|
`timescale 1ns / 1ps
module uart_test(
input clk,
input rst,
input [7:0] sw,
input rx,
input write,
input read,
input speed_up,
input speed_down,
output tx,
output rdy,
output full,
output [7:0]seg,
output [3:0] an
);
reg [3:0] baud;
wire up, down, reset;
wire up_pulse, down_pulse;
wire write_pulse, read_pulse;
always @ (posedge clk) begin
if(reset == 1'b1) begin
baud <= 4'h5;
end
else if(up_pulse == 1'b1) begin
if (baud < 4'h9) begin
baud <= baud + 1'b1;
end
else begin
baud <= baud;
end
end
else if(down_pulse == 1'b1) begin
if(baud > 4'h0) begin
baud <= baud - 1'b1;
end
else begin
baud <= baud;
end
end
else begin
baud <= baud;
end
end
high_to_pulse htp_up(
.CLK(clk),
.IN(up),
.OUT(up_pulse)
);
high_to_pulse htp_down(
.CLK(clk),
.IN(down),
.OUT(down_pulse)
);
high_to_pulse htp_write(
.CLK(clk),
.IN(write),
.OUT(write_pulse)
);
high_to_pulse htp_read(
.CLK(clk),
.IN(read),
.OUT(read_pulse)
);
uart_ctrl uart(
.CLK(clk),
.RST(reset),
.EN(1'b1),
.BAUD(baud),
.TXEN(1'b1),
.RXEN(1'b1),
.TX(tx),
.RX(rx),
.WRITE(write_pulse),
.WRDATA(sw),
.ISFULL(full),
.READ(read_pulse),
.RDDATA(seg),
.DATARDY(rdy)
);
debounce debounce_speed_up(
.CLK(clk),
.IN(speed_up),
.OUT(up)
);
debounce debounce_speed_down(
.CLK(clk),
.IN(speed_down),
.OUT(down)
);
debounce debounce_reset(
.CLK(clk),
.IN(rst),
.OUT(reset)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Cal Poly Pomona
// Engineer: Byron Phung
//
// Create Date: 23:27:29 04/27/2016
// Design Name: Search_8Comparators
// Module Name: D:/Documents/College/CalPolyPomona/SeniorProject/hardware-accelerated-dna-matching-and-variation-detection/Hardware/Verilog/Search_8Comparators_tf.v
// Project Name: Verilog
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Search_8Comparators
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Search_8Comparators_tf;
// Inputs
reg clock;
reg reset;
reg [1023:0] data;
reg [63:0] key;
// Outputs
wire match;
// Instantiate the Unit Under Test (UUT)
Search_8Comparators uut (
.clock(clock),
.reset(reset),
.data(data),
.key(key),
.match(match)
);
// Alternate the clock every unit of time.
initial begin
clock = 0;
repeat (1_000_000)
#1 clock =~ clock;
end
initial begin
// Initialization
reset = 1;
data = 1024'b0100111010111010001100110010000010010111001110111010001010111000010111111100010011101110000010000010010100001010001111011010010010001101000100100001111100010111001110011110010001000111110010000001101100000000100100011000011100011110000110111011011000111011010000011010011011010000011111101100101100000101011101010011000010001110001110100111011000000100101000000100001010011010000011000100100000100011001101110000100011001111110001010011001100101011100100000000110000110000001010011010001000101101111000111100111100110000111100010000001000010000100110000000000011110011101000101100110011000011111000000001001001100100000000000000000001000010000010011001111000110001000010111111110101100000111110011001111000100000001100000011111111010110000010111100110111111110101110111110010001100001110010111001000110101011011110111000000100001101110000110000110010101000111001110001011100110101111100000001001100011000111011101000100000101011100000000110111010111101101001000100011110011010101110101111110111100100011100001111111110001011;
key = 64'b0100111010111010001100110010000010010111001110111010001010111000;
@(negedge clock);
// Turn off the reset and let the module be tested as is.
reset = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_NSR_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DFF_NSR_SYMBOL_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$NSR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
input SET ,
//# {{clocks|Clocking}}
input CLK_N
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_NSR_SYMBOL_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpciexpav_stif_reg_fifo
#(
parameter FIFO_DEPTH = 5,
parameter DATA_WIDTH = 304
)
(
// global signals
input clk,
input rstn,
input srst,
input wrreq,
input rdreq,
input [DATA_WIDTH-1:0] data,
output [DATA_WIDTH-1:0] q,
output reg [3:0] fifo_count
);
reg [DATA_WIDTH-1:0] fifo_reg[FIFO_DEPTH-1:0];
wire [FIFO_DEPTH-1:0] fifo_wrreq;
// fifo word counter
always @(posedge clk or negedge rstn)
begin
if(~rstn)
fifo_count <= 4'h0;
else if (srst)
fifo_count <= 4'h0;
else if (rdreq & ~wrreq)
fifo_count <= fifo_count - 1;
else if(~rdreq & wrreq)
fifo_count <= fifo_count + 1;
end
generate
genvar i;
for(i=0; i< FIFO_DEPTH -1; i=i+1)
begin: register_array
assign fifo_wrreq[i] = wrreq & (fifo_count == i | (fifo_count == i + 1 & rdreq)) ;
always @(posedge clk or negedge rstn)
begin
if(~rstn)
fifo_reg[i] <= {DATA_WIDTH{1'b0}};
else if (srst)
fifo_reg[i] <= {DATA_WIDTH{1'b0}};
else if(fifo_wrreq[i])
fifo_reg[i] <= data;
else if(rdreq)
fifo_reg[i] <= fifo_reg[i+1];
end
end
endgenerate
/// the last register
assign fifo_wrreq[FIFO_DEPTH-1] = wrreq & (fifo_count == FIFO_DEPTH - 1 | (fifo_count == FIFO_DEPTH & rdreq)) ;
always @(posedge clk or negedge rstn)
begin
if(~rstn)
fifo_reg[FIFO_DEPTH-1] <= {DATA_WIDTH{1'b0}};
else if (srst)
fifo_reg[FIFO_DEPTH-1] <= {DATA_WIDTH{1'b0}};
else if(fifo_wrreq[FIFO_DEPTH-1])
fifo_reg[FIFO_DEPTH-1] <= data;
end
assign q = fifo_reg[0];
endmodule
|
//*****************************************************************************
//(c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : qdr_rld_phy_read_vld_gen.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Nov 19, 2008
// \___\/\___\
//
//Device: 7 Series
//Design: QDRII+ SRAM / RLDRAM II SDRAM
//
//Purpose:
// This module
// 1. Generates the valid signals for the read data sent to the user interface.
// 2. The valids are generated by delaying the incoming read commands from the
// write path by some amount determined by the latency calibration.
//
//Revision History:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_rld_phy_read_vld_gen #
(
parameter BURST_LEN = 4, // 4 = Burst Length 4, 2 = Burst Length 2
parameter nCK_PER_CLK = 2,
parameter TCQ = 100 // Register delay
)
(
// System Signals
input clk, // main system half freq clk
input rst_clk, // reset syncrhonized to clk
// Write Interface
input [nCK_PER_CLK-1:0] int_rd_cmd_n, // read command(s) - only bit 0 is used for BL4
// Stage 2 Calibration Interface
input [4:0] valid_latency, // amount to delay read command
input cal_done, // indicates calibration is complete
// User Interface
output reg [nCK_PER_CLK-1:0] data_valid, // data valid for read data
// ChipScope Debug Signals
output [4:0] dbg_valid_lat
);
wire [nCK_PER_CLK-1:0] data_valid_int;
reg [nCK_PER_CLK-1:0] data_valid_int_r1;
reg [nCK_PER_CLK-1:0] data_valid_int_r2;
//Read Data valid depends on BL as well as what slot a command is placed in.
//The latency is computed based on a single command placed in slot0. If a read
//command comes into another slot we have to adjust accordingly.
// nCK_PER_CLK == 2
// BL2:
// Slot 0: Slot 0 valid
// Slot 1: Slot 1 valid
// BL4:
// Slot 0, Slot 0/1 valid
// Slot 1, Slot 1 valid, Slot 0 (reg) valid
// BL8:
// Slot 0, Slot 0/1 valid, Slot 0/1 (reg) valid
// Slot 1, Slot 1 valid, Slot 0/1 (reg) valid, Slot 0 (reg2) valid
// nCK_PER_CLK == 4
// BL2:
// Slot 0: Slot 0 valid
// Slot 1: Slot 1 valid
// Slot 2: Slot 2 valid
// Slot 3: Slot 3 valid
// BL4:
// Slot 0, Slot 0/1 valid
// Slot 1, Slot 1/2 valid
// Slot 2: Slot 2/3 valid
// Slot 3: Slot 3 valid, Slot 0 (reg) valid
// BL8:
// Slot 0, Slot 0/1/2/3 valid
// Slot 1, Slot 1/2/3 valid, Slot 0 (reg) valid
// Slot 2, Slot 2/3 valid, Slot 0/1 (reg) valid
// Slot 3, Slot 3 valid, Slot 0/1/2 (reg) valid
generate
genvar i;
for (i=0; i < nCK_PER_CLK; i = i+1) begin : gen_rd_valid
// Delay the incoming rd_cmd by valid_latency number of cycles in order to
// generate the data valid for read data
SRLC32E u_vld_gen_srl_inst (
.Q (data_valid_int[i]),
.Q31 ( ),
.A (valid_latency),
.CE (1'b1),
.CLK (clk),
.D (~int_rd_cmd_n[i])
);
always @(posedge clk)
begin
data_valid_int_r1[i] <=#TCQ data_valid_int[i];
data_valid_int_r2[i] <=#TCQ data_valid_int_r1[i];
end
if (nCK_PER_CLK == 2) begin : gen_data_valid_2
// Only issue valids after calibration has completed
always @(posedge clk) begin
if (rst_clk || !cal_done) begin
data_valid[i] <= #TCQ 0;
end else begin
if (BURST_LEN==2) begin
data_valid[i] <= #TCQ data_valid_int[i];
end else if (BURST_LEN==4) begin
if (i==0)
data_valid[0] <= #TCQ data_valid_int[0] | data_valid_int_r1[1];
else
data_valid[1] <= #TCQ data_valid_int[0] | data_valid_int[1] ;
end else begin //BURST_LEN==8
if (i==0)
data_valid[0] <= #TCQ data_valid_int[0] | data_valid_int_r1[0] |
data_valid_int_r1[1] | data_valid_int_r2[1];
else
data_valid[1] <= #TCQ data_valid_int[0] | data_valid_int_r1[0] |
data_valid_int[1] | data_valid_int_r1[1];
end
end
end //end of always
end else if (nCK_PER_CLK == 4) begin : gen_data_valid_4
// Only issue valids after calibration has completed
always @(posedge clk) begin
if (rst_clk || !cal_done) begin
data_valid[i] <= #TCQ 0;
end else begin
if (BURST_LEN==2) begin
data_valid[i] <= #TCQ data_valid_int[i];
end else if (BURST_LEN==4) begin
if (i==0)
data_valid[0] <= #TCQ data_valid_int[0] | data_valid_int_r1[3];
else if (i==1)
data_valid[1] <= #TCQ data_valid_int[0] | data_valid_int[1] ;
else if (i==2)
data_valid[2] <= #TCQ data_valid_int[1] | data_valid_int[2] ;
else //i==3
data_valid[3] <= #TCQ data_valid_int[2] | data_valid_int[3] ;
end else begin //BURST_LEN==8
if (i==0)
data_valid[0] <= #TCQ data_valid_int[0] | data_valid_int_r1[1] |
data_valid_int_r1[2] | data_valid_int_r1[3];
else if (i==1)
data_valid[1] <= #TCQ data_valid_int[0] | data_valid_int[1] |
data_valid_int_r1[2] | data_valid_int_r1[3];
else if (i==2)
data_valid[2] <= #TCQ data_valid_int[0] | data_valid_int[1] |
data_valid_int[2] | data_valid_int_r1[3];
else //i==3
data_valid[3] <= #TCQ data_valid_int[0] | data_valid_int[1] |
data_valid_int[2] | data_valid_int[3];
end
end
end //end of always
end //end of gen_data_valid_4
end //end of for
endgenerate
// Assign debug signals
assign dbg_valid_lat = valid_latency;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Register Block
// File : der_top.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the top level register block for Imagine-MI
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_top
(
input de_clk, // drawing engine clock input
input de_rstn, // de reset input
input hb_clk, // host bus clock input
input hb_rstn, // host reset input
input [31:0] hb_din, // host bus data
input [8:2] dlp_adr, // host bus address through preproc
input [8:2] hb_adr_r, // host bus address bypasses preproc
input hb_wstrb, // host bus write strobes
input [3:0] hb_ben, // host bus byte enables.
input hb_csn, // host bus chip select.
input [15:0] lpat_state, // line pattern state register
input [53:0] dl_rdback, // dlp read back data.
input [4:0] flow, // Flow register.
input busy_dlp, // Busy feedback from the DLP.
input de_clint_tog, // Clip Interrupt Toggle Signal.
input de_ddint_tog, // Drawing Done Int Toggle Signal.
input sup_done, // 3D setup is done.
input abort_cmd, // 3D setup abort.
input dex_busy, // Drawing engine 2D EX busy.
input pc_last, // Last push to the Pixel Cache.
input cmd_done_3d, // Last Pixel generated, for current cmd.
output goline, // Start 2D Line.
output goblt, // Start 2D BLT.
output pal_load, // Load Texture Palette.
output tc_inv_cmd, // Invalidate Texture.
output go_sup, // Start the setup engine.
output load_actv_3d, // Start 3D execution.
output cmdcpyclr, // Command copy clear.
output load_actvn,
output tc_xyw_sel, // Sel TC or XYW for cache writing
output [11:0] buf_ctrl_2, // buffer control register output.
output [1:0] ps_1, // pixel size bits.
output [27:0] sorg_2, // source origin register output
output [27:0] dorg_2, // destination origin register output
output [31:0] de_sorg_2, // source origin register output
output [31:0] de_dorg_2, // destination origin register output
output [11:0] sptch_2, // source pitch register output
output [11:0] dptch_2, // destination pitch register output
output [3:0] opc_1, // opcode register output
output [3:0] opc_15, // opcode register output
output [3:0] rop_1, // raster opcode register output
output [3:0] rop_2, // raster opcode register output
output [4:0] style_2, // drawing style register output
output solid_1, // Solid level one signal.
output prst_1, // drawing pattern style register
output nlst_2, // drawing pattern style register
output or_apat_1, // Or of apat_1
output [1:0] apat_2, // drawing area pattern mode.
output [2:0] hdf_1, // Host data format.
output [2:0] clp_2, // drawing clip control register
output [31:0] fore_2, // foreground color register output
output [31:0] back_2, // background color register output
output [31:0] lpat_1, // Line Pattern Level 1
output [15:0] pctrl_1,
output [31:0] clptl_1,
output [31:0] clpbr_1,
output [3:0] mask_2, // plane mask register output
output [23:0] de_key_2, // Key data out
output [159:0] xydat_1, // level 1 XY data for 2D
output [15:0] alpha_2, // Alpha register
output [17:0] acntrl_2, // Alpha control register
output [31:0] hb_dout, // host bus read back path
output busy_hb, // busy to the host.
output stpl_1, // packed stipple bit level one
output de_ca_rdy, // cache ready bit to the exec unit
output ps16s_2, // 8bpp host data
output ps565s_2, // 8bpp host data
output cmd_trig_comb,
output [1:0] bc_lvl_2,
output interrupt,
output [6:0] mem_offset, // Define an offset for operations
output [3:0] sorg_upper, // Define an offset for text
output load_15,
output busy_3d,
output abort_cmd_flag // Used to clear busy after an abort.
);
`ifdef CORE_3D parameter en_3d = 1'b1;
`else parameter en_3d =1'b0;
`endif
wire [1:0] intm;
wire [1:0] intp;
wire [13:0] buf_ctrl_1;
wire [31:0] sorg_1;
wire [31:0] dorg_1;
wire [11:0] sptch_1;
wire [11:0] dptch_1;
wire [4:0] style_1;
wire nlst_1;
wire [1:0] apat_1;
wire [2:0] clp_1;
wire [31:0] fore_1;
wire [31:0] back_1;
wire [3:0] mask_1;
wire [23:0] de_key_1;
wire [31:0] xy0_1;
wire [31:0] xy1_1;
wire [31:0] xy2_1;
wire [31:0] xy3_1;
wire [31:0] xy4_1;
wire [15:0] alpha_1;
wire [17:0] acntrl_1;
wire [31:0] mf_sorg_2; /* multi function sorg. */
wire [31:0] mf_dorg_2; /* multi function dorg. */
wire cr_pulse;
wire hb_ca_rdy;
wire bc_co;
wire [1:0] bc_lvl_1;
wire prst;
wire cmdrdy;
wire cmdack;
wire [3:0] opc_2;
der_reg_1 u_der_reg_1
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.hb_din (hb_din),
.dlp_adr (dlp_adr),
.hb_wstrb (hb_wstrb),
.hb_ben (hb_ben),
.hb_csn (hb_csn),
.cmdack (cmdack),
.de_clint_tog (de_clint_tog),
.de_ddint_tog (de_ddint_tog),
.en_3d (en_3d),
.intm (intm),
.intp (intp),
.buf_ctrl_1 ({cr_pulse,buf_ctrl_1}),
.sorg_1 (sorg_1),
.dorg_1 (dorg_1),
.sptch_1 (sptch_1),
.dptch_1 (dptch_1),
.opc_1 (opc_1),
.rop_1 (rop_1),
.style_1 (style_1),
.patrn_1 ({prst,nlst_1,apat_1}),
.hdf_1 (hdf_1),
.clp_1 (clp_1),
.fore_1 (fore_1),
.back_1 (back_1),
.mask_1 (mask_1),
.de_key_1 (de_key_1),
.lpat_1 (lpat_1),
.pctrl_1 (pctrl_1),
.clptl_1 (clptl_1),
.clpbr_1 (clpbr_1),
.xy0_1 (xy0_1),
.xy1_1 (xy1_1),
.xy2_1 (xy2_1),
.xy3_1 (xy3_1),
.xy4_1 (xy4_1),
.alpha_1 (alpha_1),
.acntrl_1 (acntrl_1),
.cmdrdy (cmdrdy),
.busy_hb (busy_hb),
.stpl_1 (stpl_1),
.cmd_trig_comb (cmd_trig_comb),
.bc_lvl_1 (bc_lvl_1),
.interrupt (interrupt),
.mem_offset_1 (mem_offset),
.sorg_upper_1 (sorg_upper)
);
`ifdef CORE_3D
wire [13:0] buf_ctrl_15;
wire [31:0] sorg_15;
wire [31:0] dorg_15;
wire [31:0] mf_sorg_15;
wire [31:0] mf_dorg_15;
wire [11:0] sptch_15;
wire [11:0] dptch_15;
wire [4:0] style_15;
wire nlst_15;
wire [1:0] apat_15;
wire [2:0] clp_15;
wire [31:0] fore_15;
wire [31:0] back_15;
wire [3:0] mask_15;
wire [23:0] de_key_15;
wire [31:0] xy0_15;
wire [31:0] xy1_15;
wire [31:0] xy2_15;
wire [31:0] xy3_15;
wire [31:0] xy4_15;
wire [15:0] alpha_15;
wire [17:0] acntrl_15;
wire [1:0] bc_lvl_15;
wire [3:0] rop_15;
assign solid_1 = style_15[0];
assign tc_xyw_sel = buf_ctrl_15[11];
assign ps_1 = buf_ctrl_15[8:7];
assign xydat_1 = {xy0_15,xy1_15,xy2_15,xy3_15,xy4_15};
der_reg_15 u_der_reg_15
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.load_15 (load_15),
.buf_ctrl_1 ({buf_ctrl_1[13:12], buf_ctrl_1[10:0]}),
.sorg_1 (sorg_1),
.dorg_1 (dorg_1),
.sptch_1 (sptch_1),
.dptch_1 (dptch_1),
.rop_1 (rop_1),
.style_1 (style_1),
.nlst_1 (nlst_1),
.apat_1 (apat_1),
.clp_1 (clp_1),
.fore_1 (fore_1),
.back_1 (back_1),
.mask_1 (mask_1),
.de_key_1 (de_key_1),
.alpha_1 (alpha_1),
.acntrl_1 (acntrl_1),
.bc_lvl_1 (bc_lvl_1),
.opc_1 (opc_1),
.xy0_1 (xy0_1),
.xy1_1 (xy1_1),
.xy2_1 (xy2_1),
.xy3_1 (xy3_1),
.xy4_1 (xy4_1),
.buf_ctrl_15 ({bc_co,buf_ctrl_15}),
.sorg_15 (sorg_15),
.dorg_15 (dorg_15),
.sptch_15 (sptch_15),
.dptch_15 (dptch_15),
.rop_15 (rop_15),
.style_15 (style_15),
.nlst_15 (nlst_15),
.apat_15 (apat_15),
.clp_15 (clp_15),
.fore_15 (fore_15),
.back_15 (back_15),
.mask_15 (mask_15),
.de_key_15 (de_key_15),
.alpha_15 (alpha_15),
.acntrl_15 (acntrl_15),
.bc_lvl_15 (bc_lvl_15),
.opc_15 (opc_15),
.xy0_15 (xy0_15),
.xy1_15 (xy1_15),
.xy2_15 (xy2_15),
.xy3_15 (xy3_15),
.xy4_15 (xy4_15)
);
der_reg_2 u_der_reg_2
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.load_actvn (load_actvn),
.cmdcpyclr (cmdcpyclr),
.buf_ctrl_1 ({1'b0, buf_ctrl_15[12], buf_ctrl_15[10:0]}),
.sorg_1 (sorg_15),
.dorg_1 (dorg_15),
.sptch_1 (sptch_15),
.dptch_1 (dptch_15),
.rop_1 (rop_15),
.opc_1 (opc_15),
.style_1 (style_15),
.nlst_1 (nlst_15),
.apat_1 (apat_15),
.clp_1 (clp_15),
.fore_1 (fore_15),
.back_1 (back_15),
.mask_1 (mask_15),
.de_key_1 (de_key_15),
.alpha_1 (alpha_15),
.acntrl_1 (acntrl_15),
.bc_lvl_1 (bc_lvl_15),
`else
assign solid_1 = style_1[0];
assign tc_xyw_sel = buf_ctrl_1[11];
assign ps_1 = buf_ctrl_1[8:7];
assign xydat_1 = {xy0_1,xy1_1,xy2_1,xy3_1,xy4_1};
der_reg_2 u_der_reg_2
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.load_actvn (load_actvn),
.cmdcpyclr (cmdcpyclr),
.buf_ctrl_1 ({buf_ctrl_1[13:12], buf_ctrl_1[10:0]}),
.sorg_1 (sorg_1),
.dorg_1 (dorg_1),
.sptch_1 (sptch_1),
.dptch_1 (dptch_1),
.rop_1 (rop_1),
.opc_1 (opc_1),
.style_1 (style_1),
.nlst_1 (nlst_1),
.apat_1 (apat_1),
.clp_1 (clp_1),
.fore_1 (fore_1),
.back_1 (back_1),
.mask_1 (mask_1),
.de_key_1 (de_key_1),
.alpha_1 (alpha_1),
.acntrl_1 (acntrl_1),
.bc_lvl_1 (bc_lvl_1),
`endif
.buf_ctrl_2 ({bc_co,buf_ctrl_2}),
.sorg_2 (mf_sorg_2),
.dorg_2 (mf_dorg_2),
.sptch_2 (sptch_2),
.dptch_2 (dptch_2),
.rop_2 (rop_2),
.style_2 (style_2),
.nlst_2 (nlst_2),
.apat_2 (apat_2),
.clp_2 (clp_2),
.fore_2 (fore_2),
.back_2 (back_2),
.mask_2 (mask_2),
.de_key_2 (de_key_2),
.alpha_2 (alpha_2),
.acntrl_2 (acntrl_2),
.bc_lvl_2 (bc_lvl_2),
.opc_2 (opc_2)
);
der_rdmux D_RDMUX
(
.hb_adr (hb_adr_r),
.intm (intm),
.intp (intp),
.flow (flow),
.busy (busy_dlp),
.buf_ctrl_1 ({hb_ca_rdy,buf_ctrl_1}),
.sorg_1 (sorg_1),
.dorg_1 (dorg_1),
.sptch_1 (sptch_1),
.dptch_1 (dptch_1),
.opc_1 (opc_1),
.rop_1 (rop_1),
.style_1 (style_1),
.patrn_1 ({prst,nlst_1,apat_1}),
.hdf_1 (hdf_1),
.clp_1 (clp_1),
.fore_1 (fore_1),
.back_1 (back_1),
.mask_1 (mask_1),
.de_key_1 (de_key_1),
.lpat_1 (lpat_1),
.pctrl_1 (pctrl_1),
.clptl_1 (clptl_1),
.clpbr_1 (clpbr_1),
.xy0_1 (xy0_1),
.xy1_1 (xy1_1),
.xy2_1 (xy2_1),
.xy3_1 (xy3_1),
.xy4_1 (xy4_1),
.alpha_1 (alpha_1),
.acntrl_1 (acntrl_1),
.lpat_state (lpat_state),
.dl_rdback (dl_rdback),
.bc_lvl_1 (bc_lvl_1),
.mem_offset_1 (mem_offset),
.sorg_upper_1 (sorg_upper),
.hb_dout (hb_dout)
);
der_misc u_der_misc
(
.de_clk (de_clk),
.hb_clk (hb_clk),
.prst (prst),
.cr_pulse (cr_pulse),
.ps_sel_2 (buf_ctrl_2[10:9]),
.bc_co (bc_co),
.mf_sorg_2 (mf_sorg_2),
.mf_dorg_2 (mf_dorg_2),
.apat_1 (apat_1),
.sd_selector (buf_ctrl_2[4]),
.prst_1 (prst_1),
.hb_ca_rdy (hb_ca_rdy),
.de_ca_rdy (de_ca_rdy),
.ps16s_2 (ps16s_2),
.ps565s_2 (ps565s_2),
.de_sorg_2 (de_sorg_2),
.de_dorg_2 (de_dorg_2),
.sorg_2 (sorg_2),
.dorg_2 (dorg_2),
.or_apat_1 (or_apat_1)
);
// Command Dispatcher.
der_smdisp u_der_smdisp
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.en_3d (en_3d),
.cmdrdy (cmdrdy),
.sup_done (sup_done),
.abort_cmd (abort_cmd),
.dex_busy (dex_busy),
.opc_1 (opc_1),
.opc_15 (opc_15),
.opc_2 (opc_2),
.pc_last (pc_last),
.cmd_done_3d (cmd_done_3d),
// Outputs
.go_sup (go_sup),
.load_15 (load_15), // Transfer parameters from L1 to L1.5
.load_actvn (load_actvn), // Transfer parameters from L1.5 to L2
.load_actv_3d (load_actv_3d),// Transfer parameters from L1.5 to L2, in 3D engine.
.goline (goline),
.goblt (goblt),
.pal_load (pal_load),
.tc_inv_cmd (tc_inv_cmd),
.cmdack (cmdack),
.cmdcpyclr (cmdcpyclr),
.busy_3d (busy_3d),
.abort_cmd_flag (abort_cmd_flag)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_1_V
`define SKY130_FD_SC_MS__CONB_1_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog wrapper for conb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__conb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__conb_1 (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__conb base (
.HI(HI),
.LO(LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__conb base (
.HI(HI),
.LO(LO)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 11:13:07 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_ODD1_left_N51,
Sgf_operation_ODD1_left_N50, Sgf_operation_ODD1_left_N49,
Sgf_operation_ODD1_left_N48, Sgf_operation_ODD1_left_N47,
Sgf_operation_ODD1_left_N46, Sgf_operation_ODD1_left_N45,
Sgf_operation_ODD1_left_N44, Sgf_operation_ODD1_left_N43,
Sgf_operation_ODD1_left_N42, Sgf_operation_ODD1_left_N41,
Sgf_operation_ODD1_left_N40, Sgf_operation_ODD1_left_N39,
Sgf_operation_ODD1_left_N38, Sgf_operation_ODD1_left_N37,
Sgf_operation_ODD1_left_N36, Sgf_operation_ODD1_left_N35,
Sgf_operation_ODD1_left_N34, Sgf_operation_ODD1_left_N33,
Sgf_operation_ODD1_left_N32, Sgf_operation_ODD1_left_N31,
Sgf_operation_ODD1_left_N30, Sgf_operation_ODD1_left_N29,
Sgf_operation_ODD1_left_N28, Sgf_operation_ODD1_left_N27,
Sgf_operation_ODD1_left_N26, Sgf_operation_ODD1_left_N25,
Sgf_operation_ODD1_left_N24, Sgf_operation_ODD1_left_N23,
Sgf_operation_ODD1_left_N22, Sgf_operation_ODD1_left_N21,
Sgf_operation_ODD1_left_N20, Sgf_operation_ODD1_left_N19,
Sgf_operation_ODD1_left_N18, Sgf_operation_ODD1_left_N17,
Sgf_operation_ODD1_left_N16, Sgf_operation_ODD1_left_N15,
Sgf_operation_ODD1_left_N14, Sgf_operation_ODD1_left_N13,
Sgf_operation_ODD1_left_N12, Sgf_operation_ODD1_left_N11,
Sgf_operation_ODD1_left_N10, Sgf_operation_ODD1_left_N9,
Sgf_operation_ODD1_left_N8, Sgf_operation_ODD1_left_N7,
Sgf_operation_ODD1_left_N6, Sgf_operation_ODD1_left_N5,
Sgf_operation_ODD1_left_N4, Sgf_operation_ODD1_left_N3,
Sgf_operation_ODD1_left_N2, Sgf_operation_ODD1_left_N1,
Sgf_operation_ODD1_left_N0, Sgf_operation_ODD1_right_N53,
Sgf_operation_ODD1_right_N52, Sgf_operation_ODD1_right_N51,
Sgf_operation_ODD1_right_N50, Sgf_operation_ODD1_right_N49,
Sgf_operation_ODD1_right_N48, Sgf_operation_ODD1_right_N47,
Sgf_operation_ODD1_right_N46, Sgf_operation_ODD1_right_N45,
Sgf_operation_ODD1_right_N44, Sgf_operation_ODD1_right_N43,
Sgf_operation_ODD1_right_N42, Sgf_operation_ODD1_right_N41,
Sgf_operation_ODD1_right_N40, Sgf_operation_ODD1_right_N39,
Sgf_operation_ODD1_right_N38, Sgf_operation_ODD1_right_N37,
Sgf_operation_ODD1_right_N36, Sgf_operation_ODD1_right_N35,
Sgf_operation_ODD1_right_N34, Sgf_operation_ODD1_right_N33,
Sgf_operation_ODD1_right_N32, Sgf_operation_ODD1_right_N31,
Sgf_operation_ODD1_right_N30, Sgf_operation_ODD1_right_N29,
Sgf_operation_ODD1_right_N28, Sgf_operation_ODD1_right_N27,
Sgf_operation_ODD1_right_N26, Sgf_operation_ODD1_right_N25,
Sgf_operation_ODD1_right_N24, Sgf_operation_ODD1_right_N23,
Sgf_operation_ODD1_right_N22, Sgf_operation_ODD1_right_N21,
Sgf_operation_ODD1_right_N20, Sgf_operation_ODD1_right_N19,
Sgf_operation_ODD1_right_N18, Sgf_operation_ODD1_right_N17,
Sgf_operation_ODD1_right_N16, Sgf_operation_ODD1_right_N15,
Sgf_operation_ODD1_right_N14, Sgf_operation_ODD1_right_N13,
Sgf_operation_ODD1_right_N12, Sgf_operation_ODD1_right_N11,
Sgf_operation_ODD1_right_N10, Sgf_operation_ODD1_right_N9,
Sgf_operation_ODD1_right_N8, Sgf_operation_ODD1_right_N7,
Sgf_operation_ODD1_right_N6, Sgf_operation_ODD1_right_N5,
Sgf_operation_ODD1_right_N4, Sgf_operation_ODD1_right_N3,
Sgf_operation_ODD1_right_N2, Sgf_operation_ODD1_right_N1,
Sgf_operation_ODD1_right_N0, Sgf_operation_ODD1_middle_N55,
Sgf_operation_ODD1_middle_N54, Sgf_operation_ODD1_middle_N53,
Sgf_operation_ODD1_middle_N52, Sgf_operation_ODD1_middle_N51,
Sgf_operation_ODD1_middle_N50, Sgf_operation_ODD1_middle_N49,
Sgf_operation_ODD1_middle_N48, Sgf_operation_ODD1_middle_N47,
Sgf_operation_ODD1_middle_N46, Sgf_operation_ODD1_middle_N45,
Sgf_operation_ODD1_middle_N44, Sgf_operation_ODD1_middle_N43,
Sgf_operation_ODD1_middle_N42, Sgf_operation_ODD1_middle_N41,
Sgf_operation_ODD1_middle_N40, Sgf_operation_ODD1_middle_N39,
Sgf_operation_ODD1_middle_N38, Sgf_operation_ODD1_middle_N37,
Sgf_operation_ODD1_middle_N36, Sgf_operation_ODD1_middle_N35,
Sgf_operation_ODD1_middle_N34, Sgf_operation_ODD1_middle_N33,
Sgf_operation_ODD1_middle_N32, Sgf_operation_ODD1_middle_N31,
Sgf_operation_ODD1_middle_N30, Sgf_operation_ODD1_middle_N29,
Sgf_operation_ODD1_middle_N28, Sgf_operation_ODD1_middle_N27,
Sgf_operation_ODD1_middle_N26, Sgf_operation_ODD1_middle_N25,
Sgf_operation_ODD1_middle_N24, Sgf_operation_ODD1_middle_N23,
Sgf_operation_ODD1_middle_N22, Sgf_operation_ODD1_middle_N21,
Sgf_operation_ODD1_middle_N20, Sgf_operation_ODD1_middle_N19,
Sgf_operation_ODD1_middle_N18, Sgf_operation_ODD1_middle_N17,
Sgf_operation_ODD1_middle_N16, Sgf_operation_ODD1_middle_N15,
Sgf_operation_ODD1_middle_N14, Sgf_operation_ODD1_middle_N13,
Sgf_operation_ODD1_middle_N12, Sgf_operation_ODD1_middle_N11,
Sgf_operation_ODD1_middle_N10, Sgf_operation_ODD1_middle_N9,
Sgf_operation_ODD1_middle_N8, Sgf_operation_ODD1_middle_N7,
Sgf_operation_ODD1_middle_N6, Sgf_operation_ODD1_middle_N5,
Sgf_operation_ODD1_middle_N4, Sgf_operation_ODD1_middle_N3,
Sgf_operation_ODD1_middle_N2, Sgf_operation_ODD1_middle_N1,
Sgf_operation_ODD1_middle_N0, n287, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436,
n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491,
n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, DP_OP_168J24_122_1342_n617,
DP_OP_168J24_122_1342_n587, DP_OP_36J24_124_1029_n28,
DP_OP_36J24_124_1029_n27, DP_OP_36J24_124_1029_n26,
DP_OP_36J24_124_1029_n25, DP_OP_36J24_124_1029_n24,
DP_OP_36J24_124_1029_n23, DP_OP_36J24_124_1029_n22,
DP_OP_36J24_124_1029_n21, DP_OP_36J24_124_1029_n20,
DP_OP_36J24_124_1029_n19, DP_OP_36J24_124_1029_n18,
DP_OP_36J24_124_1029_n12, DP_OP_36J24_124_1029_n11,
DP_OP_36J24_124_1029_n10, DP_OP_36J24_124_1029_n9,
DP_OP_36J24_124_1029_n8, DP_OP_36J24_124_1029_n7,
DP_OP_36J24_124_1029_n6, DP_OP_36J24_124_1029_n5,
DP_OP_36J24_124_1029_n4, DP_OP_36J24_124_1029_n3,
DP_OP_36J24_124_1029_n2, DP_OP_36J24_124_1029_n1, mult_x_24_n1657,
mult_x_24_n1656, mult_x_24_n1655, mult_x_24_n1654, mult_x_24_n1653,
mult_x_24_n1652, mult_x_24_n1651, mult_x_24_n1650, mult_x_24_n1649,
mult_x_24_n1648, mult_x_24_n1647, mult_x_24_n1646, mult_x_24_n1645,
mult_x_24_n1644, mult_x_24_n1643, mult_x_24_n1642, mult_x_24_n1641,
mult_x_24_n1640, mult_x_24_n1639, mult_x_24_n1638, mult_x_24_n1630,
mult_x_24_n1629, mult_x_24_n1628, mult_x_24_n1627, mult_x_24_n1626,
mult_x_24_n1625, mult_x_24_n1624, mult_x_24_n1623, mult_x_24_n1622,
mult_x_24_n1621, mult_x_24_n1620, mult_x_24_n1619, mult_x_24_n1618,
mult_x_24_n1617, mult_x_24_n1616, mult_x_24_n1615, mult_x_24_n1614,
mult_x_24_n1613, mult_x_24_n1612, mult_x_24_n1611, mult_x_24_n1610,
mult_x_24_n1609, mult_x_24_n1608, mult_x_24_n1603, mult_x_24_n1602,
mult_x_24_n1601, mult_x_24_n1600, mult_x_24_n1599, mult_x_24_n1597,
mult_x_24_n1596, mult_x_24_n1595, mult_x_24_n1594, mult_x_24_n1593,
mult_x_24_n1592, mult_x_24_n1591, mult_x_24_n1590, mult_x_24_n1589,
mult_x_24_n1588, mult_x_24_n1587, mult_x_24_n1586, mult_x_24_n1585,
mult_x_24_n1584, mult_x_24_n1583, mult_x_24_n1582, mult_x_24_n1581,
mult_x_24_n1580, mult_x_24_n1579, mult_x_24_n1578, mult_x_24_n1570,
mult_x_24_n1569, mult_x_24_n1568, mult_x_24_n1567, mult_x_24_n1566,
mult_x_24_n1565, mult_x_24_n1564, mult_x_24_n1563, mult_x_24_n1562,
mult_x_24_n1561, mult_x_24_n1560, mult_x_24_n1559, mult_x_24_n1558,
mult_x_24_n1557, mult_x_24_n1556, mult_x_24_n1555, mult_x_24_n1554,
mult_x_24_n1553, mult_x_24_n1552, mult_x_24_n1551, mult_x_24_n1550,
mult_x_24_n1549, mult_x_24_n1548, mult_x_24_n1543, mult_x_24_n1542,
mult_x_24_n1541, mult_x_24_n1540, mult_x_24_n1539, mult_x_24_n1537,
mult_x_24_n1536, mult_x_24_n1535, mult_x_24_n1534, mult_x_24_n1533,
mult_x_24_n1532, mult_x_24_n1531, mult_x_24_n1530, mult_x_24_n1529,
mult_x_24_n1528, mult_x_24_n1527, mult_x_24_n1526, mult_x_24_n1525,
mult_x_24_n1524, mult_x_24_n1523, mult_x_24_n1522, mult_x_24_n1521,
mult_x_24_n1520, mult_x_24_n1519, mult_x_24_n1510, mult_x_24_n1509,
mult_x_24_n1508, mult_x_24_n1507, mult_x_24_n1506, mult_x_24_n1505,
mult_x_24_n1504, mult_x_24_n1503, mult_x_24_n1502, mult_x_24_n1501,
mult_x_24_n1500, mult_x_24_n1499, mult_x_24_n1498, mult_x_24_n1497,
mult_x_24_n1496, mult_x_24_n1495, mult_x_24_n1494, mult_x_24_n1493,
mult_x_24_n1492, mult_x_24_n1491, mult_x_24_n1490, mult_x_24_n1489,
mult_x_24_n1488, mult_x_24_n1483, mult_x_24_n1482, mult_x_24_n1481,
mult_x_24_n1480, mult_x_24_n1479, mult_x_24_n1477, mult_x_24_n1476,
mult_x_24_n1475, mult_x_24_n1474, mult_x_24_n1473, mult_x_24_n1472,
mult_x_24_n1471, mult_x_24_n1470, mult_x_24_n1469, mult_x_24_n1468,
mult_x_24_n1467, mult_x_24_n1466, mult_x_24_n1465, mult_x_24_n1464,
mult_x_24_n1463, mult_x_24_n1462, mult_x_24_n1461, mult_x_24_n1460,
mult_x_24_n1450, mult_x_24_n1449, mult_x_24_n1448, mult_x_24_n1447,
mult_x_24_n1446, mult_x_24_n1445, mult_x_24_n1444, mult_x_24_n1443,
mult_x_24_n1442, mult_x_24_n1441, mult_x_24_n1440, mult_x_24_n1439,
mult_x_24_n1438, mult_x_24_n1437, mult_x_24_n1436, mult_x_24_n1435,
mult_x_24_n1434, mult_x_24_n1433, mult_x_24_n1432, mult_x_24_n1431,
mult_x_24_n1430, mult_x_24_n1429, mult_x_24_n1428, mult_x_24_n1423,
mult_x_24_n1422, mult_x_24_n1421, mult_x_24_n1420, mult_x_24_n1419,
mult_x_24_n1418, mult_x_24_n1415, mult_x_24_n1414, mult_x_24_n1413,
mult_x_24_n1412, mult_x_24_n1410, mult_x_24_n1409, mult_x_24_n1408,
mult_x_24_n1407, mult_x_24_n1406, mult_x_24_n1405, mult_x_24_n1404,
mult_x_24_n1403, mult_x_24_n1402, mult_x_24_n1401, mult_x_24_n1400,
mult_x_24_n1109, mult_x_24_n1108, mult_x_24_n1107, mult_x_24_n1106,
mult_x_24_n1105, mult_x_24_n1104, mult_x_24_n1100, mult_x_24_n1099,
mult_x_24_n1098, mult_x_24_n1094, mult_x_24_n1093, mult_x_24_n1092,
mult_x_24_n1088, mult_x_24_n1087, mult_x_24_n1086, mult_x_24_n1067,
mult_x_24_n1064, mult_x_24_n1062, mult_x_24_n1061, mult_x_24_n1060,
mult_x_24_n1059, mult_x_24_n1057, mult_x_24_n1056, mult_x_24_n1055,
mult_x_24_n1054, mult_x_24_n1052, mult_x_24_n1051, mult_x_24_n1050,
mult_x_24_n1047, mult_x_24_n1045, mult_x_24_n1044, mult_x_24_n1043,
mult_x_24_n1040, mult_x_24_n1039, mult_x_24_n1038, mult_x_24_n1037,
mult_x_24_n1036, mult_x_24_n1034, mult_x_24_n1033, mult_x_24_n1032,
mult_x_24_n1031, mult_x_24_n1030, mult_x_24_n1029, mult_x_24_n1028,
mult_x_24_n1026, mult_x_24_n1025, mult_x_24_n1024, mult_x_24_n1023,
mult_x_24_n1022, mult_x_24_n1021, mult_x_24_n1020, mult_x_24_n1018,
mult_x_24_n1017, mult_x_24_n1016, mult_x_24_n1015, mult_x_24_n1014,
mult_x_24_n1013, mult_x_24_n1012, mult_x_24_n1010, mult_x_24_n1009,
mult_x_24_n1008, mult_x_24_n1007, mult_x_24_n1006, mult_x_24_n1005,
mult_x_24_n1002, mult_x_24_n1000, mult_x_24_n999, mult_x_24_n998,
mult_x_24_n997, mult_x_24_n996, mult_x_24_n995, mult_x_24_n992,
mult_x_24_n991, mult_x_24_n990, mult_x_24_n989, mult_x_24_n988,
mult_x_24_n987, mult_x_24_n986, mult_x_24_n985, mult_x_24_n983,
mult_x_24_n982, mult_x_24_n981, mult_x_24_n980, mult_x_24_n979,
mult_x_24_n978, mult_x_24_n977, mult_x_24_n976, mult_x_24_n975,
mult_x_24_n974, mult_x_24_n972, mult_x_24_n971, mult_x_24_n970,
mult_x_24_n969, mult_x_24_n968, mult_x_24_n967, mult_x_24_n966,
mult_x_24_n965, mult_x_24_n964, mult_x_24_n963, mult_x_24_n961,
mult_x_24_n960, mult_x_24_n959, mult_x_24_n958, mult_x_24_n957,
mult_x_24_n956, mult_x_24_n955, mult_x_24_n954, mult_x_24_n953,
mult_x_24_n952, mult_x_24_n950, mult_x_24_n949, mult_x_24_n948,
mult_x_24_n947, mult_x_24_n946, mult_x_24_n945, mult_x_24_n944,
mult_x_24_n943, mult_x_24_n942, mult_x_24_n939, mult_x_24_n937,
mult_x_24_n936, mult_x_24_n935, mult_x_24_n934, mult_x_24_n933,
mult_x_24_n932, mult_x_24_n931, mult_x_24_n930, mult_x_24_n929,
mult_x_24_n926, mult_x_24_n925, mult_x_24_n924, mult_x_24_n923,
mult_x_24_n922, mult_x_24_n921, mult_x_24_n920, mult_x_24_n919,
mult_x_24_n918, mult_x_24_n917, mult_x_24_n916, mult_x_24_n914,
mult_x_24_n913, mult_x_24_n912, mult_x_24_n911, mult_x_24_n910,
mult_x_24_n909, mult_x_24_n908, mult_x_24_n907, mult_x_24_n906,
mult_x_24_n905, mult_x_24_n904, mult_x_24_n903, mult_x_24_n902,
mult_x_24_n901, mult_x_24_n900, mult_x_24_n899, mult_x_24_n898,
mult_x_24_n897, mult_x_24_n896, mult_x_24_n895, mult_x_24_n894,
mult_x_24_n893, mult_x_24_n892, mult_x_24_n891, mult_x_24_n890,
mult_x_24_n889, mult_x_24_n888, mult_x_24_n887, mult_x_24_n886,
mult_x_24_n885, mult_x_24_n884, mult_x_24_n883, mult_x_24_n882,
mult_x_24_n881, mult_x_24_n880, mult_x_24_n879, mult_x_24_n878,
mult_x_24_n877, mult_x_24_n876, mult_x_24_n875, mult_x_24_n874,
mult_x_24_n873, mult_x_24_n872, mult_x_24_n871, mult_x_24_n870,
mult_x_24_n869, mult_x_24_n868, mult_x_24_n867, mult_x_24_n866,
mult_x_24_n865, mult_x_24_n864, mult_x_24_n863, mult_x_24_n862,
mult_x_24_n861, mult_x_24_n860, mult_x_24_n859, mult_x_24_n858,
mult_x_24_n857, mult_x_24_n856, mult_x_24_n855, mult_x_24_n854,
mult_x_24_n853, mult_x_24_n852, mult_x_24_n851, mult_x_24_n850,
mult_x_24_n849, mult_x_24_n848, mult_x_24_n847, mult_x_24_n846,
mult_x_24_n845, mult_x_24_n844, mult_x_24_n843, mult_x_24_n842,
mult_x_24_n841, mult_x_24_n840, mult_x_24_n839, mult_x_24_n838,
mult_x_24_n837, mult_x_24_n836, mult_x_24_n835, mult_x_24_n834,
mult_x_24_n833, mult_x_24_n832, mult_x_24_n831, mult_x_24_n829,
mult_x_24_n828, mult_x_24_n827, mult_x_24_n826, mult_x_24_n825,
mult_x_24_n824, mult_x_24_n823, mult_x_24_n822, mult_x_24_n821,
mult_x_24_n820, mult_x_24_n819, mult_x_24_n817, mult_x_24_n816,
mult_x_24_n815, mult_x_24_n814, mult_x_24_n813, mult_x_24_n812,
mult_x_24_n811, mult_x_24_n810, mult_x_24_n809, mult_x_24_n808,
mult_x_24_n807, mult_x_24_n806, mult_x_24_n805, mult_x_24_n804,
mult_x_24_n803, mult_x_24_n802, mult_x_24_n801, mult_x_24_n800,
mult_x_24_n799, mult_x_24_n798, mult_x_24_n797, mult_x_24_n796,
mult_x_24_n795, mult_x_24_n794, mult_x_24_n793, mult_x_24_n792,
mult_x_24_n791, mult_x_24_n790, mult_x_24_n789, mult_x_24_n788,
mult_x_24_n787, mult_x_24_n786, mult_x_24_n784, mult_x_24_n783,
mult_x_24_n782, mult_x_24_n781, mult_x_24_n780, mult_x_24_n779,
mult_x_24_n778, mult_x_24_n777, mult_x_24_n776, mult_x_24_n775,
mult_x_24_n774, mult_x_24_n773, mult_x_24_n772, mult_x_24_n771,
mult_x_24_n770, mult_x_24_n769, mult_x_24_n768, mult_x_24_n767,
mult_x_24_n765, mult_x_24_n764, mult_x_24_n763, mult_x_24_n762,
mult_x_24_n761, mult_x_24_n760, mult_x_24_n759, mult_x_24_n758,
mult_x_24_n756, mult_x_24_n755, mult_x_24_n754, mult_x_24_n753,
mult_x_24_n752, mult_x_24_n751, mult_x_24_n750, mult_x_24_n749,
mult_x_24_n748, mult_x_24_n747, mult_x_24_n746, mult_x_24_n745,
mult_x_24_n744, mult_x_24_n743, mult_x_24_n742, mult_x_24_n741,
mult_x_24_n740, mult_x_24_n739, mult_x_24_n738, mult_x_24_n737,
mult_x_24_n736, mult_x_24_n735, mult_x_24_n734, mult_x_24_n732,
mult_x_24_n731, mult_x_24_n730, mult_x_24_n729, mult_x_24_n728,
mult_x_24_n727, mult_x_24_n726, mult_x_24_n725, mult_x_24_n724,
mult_x_24_n723, mult_x_24_n722, mult_x_24_n721, mult_x_24_n719,
mult_x_24_n718, mult_x_24_n717, mult_x_24_n716, mult_x_24_n715,
mult_x_24_n713, mult_x_24_n712, mult_x_24_n711, mult_x_24_n710,
mult_x_24_n709, mult_x_24_n708, mult_x_24_n707, mult_x_24_n706,
mult_x_24_n705, mult_x_24_n704, mult_x_24_n703, mult_x_24_n702,
mult_x_24_n701, mult_x_24_n700, mult_x_24_n698, mult_x_24_n697,
mult_x_24_n696, mult_x_24_n695, mult_x_24_n694, mult_x_24_n693,
mult_x_23_n1481, mult_x_23_n1480, mult_x_23_n1479, mult_x_23_n1478,
mult_x_23_n1477, mult_x_23_n1476, mult_x_23_n1475, mult_x_23_n1474,
mult_x_23_n1473, mult_x_23_n1472, mult_x_23_n1471, mult_x_23_n1470,
mult_x_23_n1469, mult_x_23_n1468, mult_x_23_n1467, mult_x_23_n1466,
mult_x_23_n1465, mult_x_23_n1464, mult_x_23_n1463, mult_x_23_n1455,
mult_x_23_n1454, mult_x_23_n1453, mult_x_23_n1452, mult_x_23_n1451,
mult_x_23_n1450, mult_x_23_n1449, mult_x_23_n1448, mult_x_23_n1447,
mult_x_23_n1446, mult_x_23_n1445, mult_x_23_n1444, mult_x_23_n1443,
mult_x_23_n1442, mult_x_23_n1441, mult_x_23_n1440, mult_x_23_n1439,
mult_x_23_n1438, mult_x_23_n1437, mult_x_23_n1436, mult_x_23_n1435,
mult_x_23_n1434, mult_x_23_n1429, mult_x_23_n1428, mult_x_23_n1427,
mult_x_23_n1426, mult_x_23_n1425, mult_x_23_n1423, mult_x_23_n1422,
mult_x_23_n1421, mult_x_23_n1420, mult_x_23_n1419, mult_x_23_n1418,
mult_x_23_n1417, mult_x_23_n1416, mult_x_23_n1415, mult_x_23_n1414,
mult_x_23_n1413, mult_x_23_n1412, mult_x_23_n1411, mult_x_23_n1410,
mult_x_23_n1409, mult_x_23_n1408, mult_x_23_n1407, mult_x_23_n1406,
mult_x_23_n1405, mult_x_23_n1397, mult_x_23_n1396, mult_x_23_n1395,
mult_x_23_n1394, mult_x_23_n1393, mult_x_23_n1392, mult_x_23_n1391,
mult_x_23_n1390, mult_x_23_n1389, mult_x_23_n1388, mult_x_23_n1387,
mult_x_23_n1386, mult_x_23_n1385, mult_x_23_n1384, mult_x_23_n1383,
mult_x_23_n1382, mult_x_23_n1381, mult_x_23_n1380, mult_x_23_n1379,
mult_x_23_n1378, mult_x_23_n1377, mult_x_23_n1371, mult_x_23_n1370,
mult_x_23_n1369, mult_x_23_n1368, mult_x_23_n1367, mult_x_23_n1365,
mult_x_23_n1364, mult_x_23_n1363, mult_x_23_n1362, mult_x_23_n1361,
mult_x_23_n1360, mult_x_23_n1359, mult_x_23_n1358, mult_x_23_n1357,
mult_x_23_n1356, mult_x_23_n1355, mult_x_23_n1354, mult_x_23_n1353,
mult_x_23_n1352, mult_x_23_n1351, mult_x_23_n1350, mult_x_23_n1349,
mult_x_23_n1348, mult_x_23_n1347, mult_x_23_n1339, mult_x_23_n1338,
mult_x_23_n1337, mult_x_23_n1336, mult_x_23_n1335, mult_x_23_n1334,
mult_x_23_n1333, mult_x_23_n1332, mult_x_23_n1331, mult_x_23_n1330,
mult_x_23_n1329, mult_x_23_n1328, mult_x_23_n1327, mult_x_23_n1326,
mult_x_23_n1325, mult_x_23_n1324, mult_x_23_n1323, mult_x_23_n1322,
mult_x_23_n1321, mult_x_23_n1320, mult_x_23_n1313, mult_x_23_n1312,
mult_x_23_n1311, mult_x_23_n1310, mult_x_23_n1309, mult_x_23_n1305,
mult_x_23_n1304, mult_x_23_n1303, mult_x_23_n1302, mult_x_23_n1301,
mult_x_23_n1300, mult_x_23_n1299, mult_x_23_n1298, mult_x_23_n1297,
mult_x_23_n1296, mult_x_23_n1295, mult_x_23_n1294, mult_x_23_n1293,
mult_x_23_n1292, mult_x_23_n1291, mult_x_23_n1290, mult_x_23_n1289,
mult_x_23_n1280, mult_x_23_n1277, mult_x_23_n1276, mult_x_23_n1275,
mult_x_23_n1274, mult_x_23_n1272, mult_x_23_n1270, mult_x_23_n1269,
mult_x_23_n1268, mult_x_23_n1267, mult_x_23_n1266, mult_x_23_n1264,
mult_x_23_n1263, mult_x_23_n1262, mult_x_23_n1251, mult_x_23_n1250,
mult_x_23_n1248, mult_x_23_n1247, mult_x_23_n1246, mult_x_23_n1244,
mult_x_23_n1243, mult_x_23_n1242, mult_x_23_n958, mult_x_23_n955,
mult_x_23_n953, mult_x_23_n952, mult_x_23_n951, mult_x_23_n950,
mult_x_23_n948, mult_x_23_n947, mult_x_23_n946, mult_x_23_n945,
mult_x_23_n943, mult_x_23_n942, mult_x_23_n941, mult_x_23_n938,
mult_x_23_n936, mult_x_23_n935, mult_x_23_n934, mult_x_23_n931,
mult_x_23_n930, mult_x_23_n929, mult_x_23_n928, mult_x_23_n927,
mult_x_23_n925, mult_x_23_n924, mult_x_23_n923, mult_x_23_n922,
mult_x_23_n921, mult_x_23_n920, mult_x_23_n919, mult_x_23_n917,
mult_x_23_n916, mult_x_23_n915, mult_x_23_n914, mult_x_23_n913,
mult_x_23_n912, mult_x_23_n911, mult_x_23_n909, mult_x_23_n908,
mult_x_23_n907, mult_x_23_n906, mult_x_23_n905, mult_x_23_n904,
mult_x_23_n903, mult_x_23_n901, mult_x_23_n900, mult_x_23_n899,
mult_x_23_n898, mult_x_23_n897, mult_x_23_n896, mult_x_23_n893,
mult_x_23_n891, mult_x_23_n890, mult_x_23_n889, mult_x_23_n888,
mult_x_23_n887, mult_x_23_n886, mult_x_23_n883, mult_x_23_n882,
mult_x_23_n881, mult_x_23_n880, mult_x_23_n879, mult_x_23_n878,
mult_x_23_n877, mult_x_23_n876, mult_x_23_n874, mult_x_23_n873,
mult_x_23_n872, mult_x_23_n871, mult_x_23_n870, mult_x_23_n869,
mult_x_23_n868, mult_x_23_n867, mult_x_23_n866, mult_x_23_n865,
mult_x_23_n863, mult_x_23_n862, mult_x_23_n861, mult_x_23_n860,
mult_x_23_n859, mult_x_23_n858, mult_x_23_n857, mult_x_23_n856,
mult_x_23_n855, mult_x_23_n854, mult_x_23_n852, mult_x_23_n851,
mult_x_23_n850, mult_x_23_n849, mult_x_23_n848, mult_x_23_n847,
mult_x_23_n846, mult_x_23_n845, mult_x_23_n844, mult_x_23_n843,
mult_x_23_n841, mult_x_23_n840, mult_x_23_n839, mult_x_23_n838,
mult_x_23_n837, mult_x_23_n836, mult_x_23_n835, mult_x_23_n834,
mult_x_23_n833, mult_x_23_n832, mult_x_23_n830, mult_x_23_n829,
mult_x_23_n828, mult_x_23_n827, mult_x_23_n826, mult_x_23_n825,
mult_x_23_n824, mult_x_23_n823, mult_x_23_n822, mult_x_23_n821,
mult_x_23_n820, mult_x_23_n819, mult_x_23_n818, mult_x_23_n817,
mult_x_23_n816, mult_x_23_n815, mult_x_23_n814, mult_x_23_n813,
mult_x_23_n812, mult_x_23_n811, mult_x_23_n810, mult_x_23_n809,
mult_x_23_n808, mult_x_23_n807, mult_x_23_n806, mult_x_23_n805,
mult_x_23_n804, mult_x_23_n803, mult_x_23_n802, mult_x_23_n801,
mult_x_23_n800, mult_x_23_n799, mult_x_23_n798, mult_x_23_n797,
mult_x_23_n796, mult_x_23_n795, mult_x_23_n794, mult_x_23_n793,
mult_x_23_n792, mult_x_23_n791, mult_x_23_n790, mult_x_23_n789,
mult_x_23_n788, mult_x_23_n787, mult_x_23_n786, mult_x_23_n785,
mult_x_23_n784, mult_x_23_n783, mult_x_23_n782, mult_x_23_n781,
mult_x_23_n780, mult_x_23_n779, mult_x_23_n778, mult_x_23_n777,
mult_x_23_n776, mult_x_23_n775, mult_x_23_n774, mult_x_23_n773,
mult_x_23_n772, mult_x_23_n771, mult_x_23_n770, mult_x_23_n769,
mult_x_23_n768, mult_x_23_n767, mult_x_23_n766, mult_x_23_n765,
mult_x_23_n764, mult_x_23_n763, mult_x_23_n762, mult_x_23_n761,
mult_x_23_n760, mult_x_23_n759, mult_x_23_n758, mult_x_23_n757,
mult_x_23_n756, mult_x_23_n755, mult_x_23_n754, mult_x_23_n753,
mult_x_23_n752, mult_x_23_n751, mult_x_23_n750, mult_x_23_n749,
mult_x_23_n748, mult_x_23_n747, mult_x_23_n746, mult_x_23_n745,
mult_x_23_n744, mult_x_23_n743, mult_x_23_n742, mult_x_23_n741,
mult_x_23_n740, mult_x_23_n739, mult_x_23_n738, mult_x_23_n737,
mult_x_23_n736, mult_x_23_n735, mult_x_23_n733, mult_x_23_n732,
mult_x_23_n731, mult_x_23_n730, mult_x_23_n729, mult_x_23_n728,
mult_x_23_n727, mult_x_23_n726, mult_x_23_n725, mult_x_23_n724,
mult_x_23_n723, mult_x_23_n722, mult_x_23_n721, mult_x_23_n720,
mult_x_23_n719, mult_x_23_n718, mult_x_23_n717, mult_x_23_n716,
mult_x_23_n714, mult_x_23_n713, mult_x_23_n712, mult_x_23_n711,
mult_x_23_n710, mult_x_23_n709, mult_x_23_n708, mult_x_23_n707,
mult_x_23_n706, mult_x_23_n703, mult_x_23_n702, mult_x_23_n701,
mult_x_23_n700, mult_x_23_n699, mult_x_23_n698, mult_x_23_n697,
mult_x_23_n696, mult_x_23_n695, mult_x_23_n694, mult_x_23_n693,
mult_x_23_n692, mult_x_23_n691, mult_x_23_n690, mult_x_23_n689,
mult_x_23_n688, mult_x_23_n687, mult_x_23_n686, mult_x_23_n685,
mult_x_23_n684, mult_x_23_n683, mult_x_23_n682, mult_x_23_n681,
mult_x_23_n679, mult_x_23_n678, mult_x_23_n677, mult_x_23_n676,
mult_x_23_n675, mult_x_23_n674, mult_x_23_n673, mult_x_23_n672,
mult_x_23_n671, mult_x_23_n670, mult_x_23_n669, mult_x_23_n668,
mult_x_23_n666, mult_x_23_n665, mult_x_23_n664, mult_x_23_n663,
mult_x_23_n662, mult_x_23_n661, mult_x_23_n658, mult_x_23_n657,
mult_x_23_n656, mult_x_23_n655, mult_x_23_n654, mult_x_23_n653,
mult_x_23_n652, mult_x_23_n651, mult_x_23_n650, mult_x_23_n649,
mult_x_23_n648, mult_x_23_n647, mult_x_23_n646, mult_x_23_n645,
mult_x_23_n643, mult_x_23_n642, mult_x_23_n641, mult_x_23_n640,
mult_x_23_n639, mult_x_23_n638, mult_x_23_n637, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785,
n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796,
n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818,
n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829,
n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840,
n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851,
n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085,
n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095,
n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105,
n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115,
n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135,
n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145,
n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155,
n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165,
n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185,
n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195,
n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205,
n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215,
n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225,
n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235,
n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245,
n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255,
n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265,
n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275,
n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285,
n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295,
n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305,
n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315,
n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325,
n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335,
n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345,
n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355,
n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365,
n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375,
n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385,
n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395,
n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755,
n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765,
n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775,
n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785,
n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795,
n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035,
n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045,
n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105,
n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115,
n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125,
n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135,
n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145,
n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155,
n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165,
n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175,
n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185,
n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195,
n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205,
n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215,
n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225,
n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235,
n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245,
n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255,
n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265,
n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275,
n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285,
n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295,
n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305,
n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315,
n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325,
n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335,
n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345,
n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355,
n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365,
n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375,
n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385,
n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395,
n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405,
n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415,
n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425,
n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435,
n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445,
n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455,
n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465,
n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475,
n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485,
n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495,
n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505,
n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515,
n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525,
n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535,
n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545,
n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555,
n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565,
n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575,
n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585,
n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595,
n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605,
n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615,
n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625,
n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635,
n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645,
n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655,
n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665,
n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675,
n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685,
n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695,
n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705,
n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715,
n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725,
n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735,
n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745,
n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785,
n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795,
n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805,
n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815,
n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825,
n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835,
n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845,
n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855,
n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865,
n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875,
n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885,
n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975,
n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985,
n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995,
n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005,
n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015,
n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025,
n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035,
n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045,
n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055,
n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065,
n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075,
n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085,
n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095,
n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105,
n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115,
n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125,
n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135,
n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145,
n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155,
n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165,
n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175,
n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185,
n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195,
n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205,
n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215,
n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225,
n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235,
n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245,
n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255,
n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265,
n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275,
n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285,
n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295,
n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305,
n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315,
n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325,
n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335,
n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345,
n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355,
n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365,
n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375,
n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385,
n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395,
n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405,
n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415,
n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425,
n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435,
n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445,
n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455,
n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465,
n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475,
n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485,
n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495,
n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505,
n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515,
n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525,
n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535,
n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545,
n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555,
n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565,
n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575,
n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585,
n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595,
n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605,
n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615,
n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625,
n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635,
n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645,
n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655,
n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665,
n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675,
n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685,
n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695,
n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705,
n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715,
n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725,
n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735,
n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745,
n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755,
n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765,
n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775,
n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785,
n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795,
n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805,
n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815,
n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825,
n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835,
n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845,
n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855,
n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865,
n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875,
n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885,
n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895,
n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905,
n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915,
n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925,
n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935,
n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945,
n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955,
n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965,
n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975,
n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985,
n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995,
n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005,
n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015,
n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025,
n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035,
n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045,
n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055,
n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065,
n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075,
n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085,
n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095,
n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105,
n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115,
n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125,
n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135,
n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145,
n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155,
n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165,
n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175,
n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185,
n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195,
n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205,
n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215,
n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225,
n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235,
n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245,
n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255,
n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265,
n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275,
n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285,
n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295,
n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305,
n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315,
n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325,
n7326, n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335,
n7336, n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345,
n7346, n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355,
n7356, n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365,
n7366, n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375,
n7376, n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385,
n7386, n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395,
n7396, n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405,
n7406, n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415,
n7416, n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425,
n7426, n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435,
n7436, n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445,
n7446, n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455,
n7456, n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465,
n7466, n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475,
n7476, n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485,
n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496,
n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506,
n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516,
n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526,
n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536,
n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546,
n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556,
n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566,
n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576,
n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586,
n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596,
n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606,
n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616,
n7617, n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626,
n7627, n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636,
n7637, n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646,
n7647, n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656,
n7657, n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666,
n7667, n7668, n7669, n7670, n7671, n7672, n7673, n7674, n7675, n7676,
n7677, n7678, n7679, n7680, n7681, n7682, n7683, n7684, n7685, n7686,
n7687, n7688, n7689, n7690, n7691, n7692, n7693, n7694, n7695, n7696,
n7697, n7698, n7699, n7700, n7701, n7702, n7703, n7704, n7705, n7706,
n7707, n7708, n7709, n7710, n7711, n7712, n7713, n7714, n7715, n7716,
n7717, n7718, n7719, n7720, n7721, n7722, n7723, n7724, n7725, n7726,
n7727, n7728, n7729, n7730, n7731, n7732, n7733, n7734, n7735, n7736,
n7737, n7738, n7739, n7740, n7741, n7742, n7743, n7744, n7745, n7746,
n7747, n7748, n7749, n7750, n7751, n7752, n7753, n7754, n7755, n7756,
n7757, n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765, n7766,
n7767, n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775, n7776,
n7777, n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785, n7786,
n7787, n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795, n7796,
n7797, n7798, n7799, n7800, n7801, n7802, n7803, n7804, n7805, n7806,
n7807, n7808, n7809, n7810, n7811, n7812, n7813, n7814, n7815, n7816,
n7817, n7818, n7819, n7820, n7821, n7822, n7823, n7824, n7825, n7826,
n7827, n7828, n7829, n7830, n7831, n7832, n7833, n7834, n7835, n7836,
n7837, n7838, n7839, n7840, n7841, n7842, n7843, n7844, n7845, n7846,
n7847, n7848, n7849, n7850, n7851, n7852, n7853, n7854, n7855, n7856,
n7857, n7858, n7859, n7860, n7861, n7862, n7863, n7864, n7865, n7866,
n7867, n7868, n7869, n7870, n7871, n7872, n7873, n7874, n7875, n7876,
n7877, n7878, n7879, n7880, n7881, n7882, n7883, n7884, n7885, n7886,
n7887, n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896,
n7897, n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906,
n7907, n7908, n7909, n7910, n7911, n7912, n7913, n7914, n7915, n7916,
n7917, n7918, n7919, n7920, n7921, n7922, n7923, n7924, n7925, n7926,
n7927, n7928, n7929, n7930, n7931, n7932, n7933, n7934, n7935, n7936,
n7937, n7938, n7939, n7940, n7941, n7942, n7943, n7944, n7945, n7946,
n7947, n7948, n7949, n7950, n7951, n7952, n7953, n7954, n7955, n7956,
n7957, n7958, n7959, n7960, n7961, n7962, n7963, n7964, n7965, n7966,
n7967, n7968, n7969, n7970, n7971, n7972, n7973, n7974, n7975, n7976,
n7977, n7978, n7979, n7980, n7981, n7982, n7983, n7984, n7985, n7986,
n7987, n7988, n7989, n7990, n7991, n7992, n7993, n7994, n7995, n7996,
n7997, n7998, n7999, n8000, n8001, n8002, n8003, n8004, n8005, n8006,
n8007, n8008, n8009, n8010, n8011, n8012, n8013, n8014, n8015, n8016,
n8017, n8018, n8019, n8020, n8021, n8022, n8023, n8024, n8025, n8026,
n8027, n8028, n8029, n8030, n8031, n8032, n8033, n8034, n8035, n8036,
n8037, n8038, n8039, n8040, n8041, n8042, n8043, n8044, n8045, n8046,
n8047, n8048, n8049, n8050, n8051, n8052, n8053, n8054, n8055, n8056,
n8057, n8058, n8059, n8060, n8061, n8062, n8063, n8064, n8065, n8066,
n8067, n8068, n8069, n8070, n8071, n8072, n8073, n8074, n8075, n8076,
n8077, n8078, n8079, n8080, n8081, n8082, n8083, n8084, n8085, n8086,
n8087, n8088, n8089, n8090, n8091, n8092, n8093, n8094, n8095, n8096,
n8097, n8098, n8099, n8100, n8101, n8102, n8103, n8104, n8105, n8106,
n8107, n8108, n8109, n8110, n8111, n8112, n8113, n8114, n8115, n8116,
n8117, n8118, n8119, n8120, n8121, n8122, n8123, n8124, n8125, n8126,
n8127, n8128, n8129, n8130, n8131, n8132, n8133, n8134, n8135, n8136,
n8137, n8138, n8139, n8140, n8141, n8142, n8143, n8144, n8145, n8146,
n8147, n8148, n8149, n8150, n8151, n8152, n8153, n8154, n8155, n8156,
n8157, n8158, n8159, n8160, n8161, n8162, n8163, n8164, n8165, n8166,
n8167, n8168, n8169, n8170, n8171, n8172, n8173, n8174, n8175, n8176,
n8177, n8178, n8179, n8180, n8181, n8182, n8183, n8184, n8185, n8186,
n8187, n8188, n8189, n8190, n8191, n8192, n8193, n8194, n8195, n8196,
n8197, n8198, n8199, n8200, n8201, n8202, n8203, n8204, n8205, n8206,
n8207, n8208, n8209, n8210, n8211, n8212, n8213, n8214, n8215, n8216,
n8217, n8218, n8219, n8220, n8221, n8222, n8223, n8224, n8225, n8226,
n8227, n8228, n8229, n8230, n8231, n8232, n8233, n8234, n8235, n8236,
n8237, n8238, n8239, n8240, n8241, n8242, n8243, n8244, n8245, n8246,
n8247, n8248, n8249, n8250, n8251, n8252, n8253, n8254, n8255, n8256,
n8257, n8258, n8259, n8260, n8261, n8262, n8263, n8264, n8265, n8266,
n8267, n8268, n8269, n8270, n8271, n8272, n8273, n8274, n8275, n8276,
n8277, n8278, n8279, n8280, n8281, n8282, n8283, n8284, n8285, n8286,
n8287, n8288, n8289, n8290, n8291, n8292, n8293, n8294, n8295, n8296,
n8297, n8298, n8299, n8300, n8301, n8302, n8303, n8304, n8305, n8306,
n8307, n8308, n8309, n8310, n8311, n8312, n8313, n8314, n8315, n8316,
n8317, n8318, n8319, n8320, n8321, n8322, n8323, n8324, n8325, n8326,
n8327, n8328, n8329, n8330, n8331, n8332, n8333, n8334, n8335, n8336,
n8337, n8338, n8339, n8340, n8341, n8342, n8343, n8344, n8345, n8346,
n8347, n8348, n8349, n8350, n8351, n8352, n8353, n8354, n8355, n8356,
n8357, n8358, n8359, n8360, n8361, n8362, n8363, n8364, n8365, n8366,
n8367, n8368, n8369, n8370, n8371, n8372, n8373, n8374, n8375, n8376,
n8377, n8378, n8379, n8380, n8381, n8382, n8383, n8384, n8385, n8386,
n8387, n8388, n8389, n8390, n8391, n8392, n8393, n8394, n8395, n8396,
n8397, n8398, n8399, n8400, n8401, n8402, n8403, n8404, n8405, n8406,
n8407, n8408, n8409, n8410, n8411, n8412, n8413, n8414, n8415, n8416,
n8417, n8418, n8419, n8420, n8421, n8422, n8423, n8424, n8425, n8426,
n8427, n8428, n8429, n8430, n8431, n8432, n8433, n8434, n8435, n8436,
n8437, n8438, n8439, n8440, n8441, n8442, n8443, n8444, n8445, n8446,
n8447, n8448, n8449, n8450, n8451, n8452, n8453, n8454, n8455, n8456,
n8457, n8458, n8459, n8460, n8461, n8462, n8463, n8464, n8465, n8466,
n8467, n8468, n8469, n8470, n8471, n8472, n8473, n8474, n8475, n8476,
n8477, n8478, n8479, n8480, n8481, n8482, n8483, n8484, n8485, n8486,
n8487, n8488, n8489, n8490, n8491, n8492, n8493, n8494, n8495, n8496,
n8497, n8498, n8499, n8500, n8501, n8502, n8503, n8504, n8505, n8506,
n8507, n8508, n8509, n8510, n8511, n8512, n8513, n8514, n8515, n8516,
n8517, n8518, n8519, n8520, n8521, n8522, n8523, n8524, n8525, n8526,
n8527, n8528, n8529, n8530, n8531, n8532, n8533, n8534, n8535, n8536;
wire [105:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [52:0] Add_result;
wire [52:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [11:0] Exp_module_Data_S;
wire [26:0] Sgf_operation_Result;
wire [55:0] Sgf_operation_ODD1_Q_middle;
wire [53:27] Sgf_operation_ODD1_Q_right;
wire [51:0] Sgf_operation_ODD1_Q_left;
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_28_ ( .D(
Sgf_operation_ODD1_left_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[28]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_30_ ( .D(
Sgf_operation_ODD1_left_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[30]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_31_ ( .D(
Sgf_operation_ODD1_left_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[31]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_32_ ( .D(
Sgf_operation_ODD1_left_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[32]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_33_ ( .D(
Sgf_operation_ODD1_left_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[33]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_34_ ( .D(
Sgf_operation_ODD1_left_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[34]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_35_ ( .D(
Sgf_operation_ODD1_left_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[35]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_39_ ( .D(
Sgf_operation_ODD1_left_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[39]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_41_ ( .D(
Sgf_operation_ODD1_left_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[41]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_42_ ( .D(
Sgf_operation_ODD1_left_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[42]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_43_ ( .D(
Sgf_operation_ODD1_left_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[43]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_44_ ( .D(
Sgf_operation_ODD1_left_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[44]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_45_ ( .D(
Sgf_operation_ODD1_left_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[45]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_46_ ( .D(
Sgf_operation_ODD1_left_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[46]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_49_ ( .D(
Sgf_operation_ODD1_left_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[49]) );
DFFHQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_50_ ( .D(
Sgf_operation_ODD1_left_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[50]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_32_ ( .D(
Sgf_operation_ODD1_right_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[32]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_35_ ( .D(
Sgf_operation_ODD1_right_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[35]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_37_ ( .D(
Sgf_operation_ODD1_right_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[37]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_38_ ( .D(
Sgf_operation_ODD1_right_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[38]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_43_ ( .D(
Sgf_operation_ODD1_right_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[43]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_45_ ( .D(
Sgf_operation_ODD1_right_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[45]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_46_ ( .D(
Sgf_operation_ODD1_right_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[46]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_47_ ( .D(
Sgf_operation_ODD1_right_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[47]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_48_ ( .D(
Sgf_operation_ODD1_right_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[48]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_49_ ( .D(
Sgf_operation_ODD1_right_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[49]) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_50_ ( .D(
Sgf_operation_ODD1_right_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[50]) );
DFFQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_51_ ( .D(
Sgf_operation_ODD1_right_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[51]) );
DFFQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_53_ ( .D(
Sgf_operation_ODD1_right_N53), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[53]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_51_ ( .D(
Sgf_operation_ODD1_middle_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[51]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_52_ ( .D(
Sgf_operation_ODD1_middle_N52), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[52]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_53_ ( .D(
Sgf_operation_ODD1_middle_N53), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[53]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_54_ ( .D(
Sgf_operation_ODD1_middle_N54), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[54]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_55_ ( .D(
Sgf_operation_ODD1_middle_N55), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[55]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n715), .CK(clk), .RN(
n8518), .Q(Op_MY[63]) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n581), .CK(clk),
.RN(n8518), .Q(zero_flag) );
DFFRXLTS Sel_A_Q_reg_0_ ( .D(n710), .CK(clk), .RN(n8518), .Q(FSM_selector_A),
.QN(n8471) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_51_ ( .D(n697), .CK(clk), .RN(
n8519), .Q(Op_MX[51]), .QN(n750) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_50_ ( .D(n696), .CK(clk), .RN(
n8519), .Q(Op_MX[50]), .QN(n1034) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_49_ ( .D(n695), .CK(clk), .RN(
n8519), .Q(Op_MX[49]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_48_ ( .D(n694), .CK(clk), .RN(
n8519), .Q(Op_MX[48]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_47_ ( .D(n693), .CK(clk), .RN(
n8519), .Q(Op_MX[47]), .QN(n1015) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_46_ ( .D(n692), .CK(clk), .RN(
n8519), .Q(Op_MX[46]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_45_ ( .D(n691), .CK(clk), .RN(
n8520), .Q(Op_MX[45]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_44_ ( .D(n690), .CK(clk), .RN(
n8520), .Q(Op_MX[44]), .QN(n1035) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_43_ ( .D(n689), .CK(clk), .RN(
n8520), .Q(Op_MX[43]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_42_ ( .D(n688), .CK(clk), .RN(
n8520), .Q(Op_MX[42]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_41_ ( .D(n687), .CK(clk), .RN(
n8520), .Q(Op_MX[41]), .QN(n1022) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_40_ ( .D(n686), .CK(clk), .RN(
n8520), .Q(Op_MX[40]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_39_ ( .D(n685), .CK(clk), .RN(
n8520), .Q(Op_MX[39]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_38_ ( .D(n684), .CK(clk), .RN(
n8520), .Q(Op_MX[38]), .QN(n1020) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_37_ ( .D(n683), .CK(clk), .RN(
n8520), .Q(Op_MX[37]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_36_ ( .D(n682), .CK(clk), .RN(
n8520), .Q(Op_MX[36]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_35_ ( .D(n681), .CK(clk), .RN(
n8521), .Q(Op_MX[35]), .QN(n793) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_34_ ( .D(n680), .CK(clk), .RN(
n8521), .Q(Op_MX[34]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_33_ ( .D(n679), .CK(clk), .RN(
n8521), .Q(Op_MX[33]), .QN(n748) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_32_ ( .D(n678), .CK(clk), .RN(
n8521), .Q(Op_MX[32]), .QN(n767) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n677), .CK(clk), .RN(
n8521), .Q(Op_MX[31]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n676), .CK(clk), .RN(
n8521), .Q(Op_MX[30]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n675), .CK(clk), .RN(
n8521), .Q(Op_MX[29]), .QN(n1032) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n674), .CK(clk), .RN(
n8521), .Q(Op_MX[28]), .QN(n766) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n672), .CK(clk), .RN(
n8521), .Q(Op_MX[26]), .QN(n971) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n671), .CK(clk), .RN(
n8522), .Q(Op_MX[25]), .QN(n794) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n670), .CK(clk), .RN(
n8522), .Q(Op_MX[24]), .QN(n751) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n669), .CK(clk), .RN(
n8522), .Q(Op_MX[23]), .QN(n772) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n668), .CK(clk), .RN(
n8522), .Q(Op_MX[22]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n667), .CK(clk), .RN(
n8522), .Q(Op_MX[21]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n666), .CK(clk), .RN(
n8522), .Q(Op_MX[20]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n665), .CK(clk), .RN(
n8522), .Q(Op_MX[19]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n664), .CK(clk), .RN(
n8522), .Q(Op_MX[18]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n663), .CK(clk), .RN(
n8522), .Q(Op_MX[17]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n662), .CK(clk), .RN(
n8522), .Q(Op_MX[16]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n661), .CK(clk), .RN(
n8523), .Q(Op_MX[15]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n660), .CK(clk), .RN(
n8523), .Q(Op_MX[14]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n659), .CK(clk), .RN(
n8523), .Q(Op_MX[13]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n658), .CK(clk), .RN(
n8523), .Q(Op_MX[12]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n657), .CK(clk), .RN(
n8523), .Q(Op_MX[11]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n656), .CK(clk), .RN(
n8523), .Q(Op_MX[10]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n655), .CK(clk), .RN(
n8523), .Q(Op_MX[9]), .QN(n770) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n654), .CK(clk), .RN(
n8523), .Q(Op_MX[8]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n653), .CK(clk), .RN(
n8523), .Q(Op_MX[7]), .QN(n800) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n652), .CK(clk), .RN(
n8523), .Q(Op_MX[6]), .QN(n747) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n651), .CK(clk), .RN(
n8524), .Q(Op_MX[5]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n650), .CK(clk), .RN(
n8524), .Q(Op_MX[4]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n649), .CK(clk), .RN(
n8524), .Q(Op_MX[3]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n648), .CK(clk), .RN(
n8524), .Q(Op_MX[2]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n647), .CK(clk), .RN(
n8524), .Q(Op_MX[1]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n646), .CK(clk), .RN(
n8524), .Q(Op_MX[0]), .QN(n764) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n579), .CK(clk), .RN(n8529),
.Q(Add_result[0]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_50_ ( .D(n632), .CK(clk), .RN(
n8531), .Q(Op_MY[50]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n631), .CK(clk), .RN(
n8531), .Q(Op_MY[49]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_48_ ( .D(n630), .CK(clk), .RN(
n8531), .Q(Op_MY[48]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n629), .CK(clk), .RN(
n8531), .Q(Op_MY[47]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_46_ ( .D(n628), .CK(clk), .RN(
n8531), .Q(Op_MY[46]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_45_ ( .D(n627), .CK(clk), .RN(
n8531), .Q(Op_MY[45]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_44_ ( .D(n626), .CK(clk), .RN(
n8532), .Q(Op_MY[44]), .QN(n773) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n625), .CK(clk), .RN(
n8532), .Q(Op_MY[43]), .QN(n804) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_42_ ( .D(n624), .CK(clk), .RN(
n8532), .Q(Op_MY[42]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_41_ ( .D(n623), .CK(clk), .RN(
n8532), .Q(Op_MY[41]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_40_ ( .D(n622), .CK(clk), .RN(
n8532), .Q(Op_MY[40]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_39_ ( .D(n621), .CK(clk), .RN(
n8532), .Q(Op_MY[39]), .QN(n765) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_38_ ( .D(n620), .CK(clk), .RN(
n8532), .Q(Op_MY[38]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_37_ ( .D(n619), .CK(clk), .RN(
n8532), .Q(Op_MY[37]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_36_ ( .D(n618), .CK(clk), .RN(
n8532), .Q(Op_MY[36]), .QN(n802) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_35_ ( .D(n617), .CK(clk), .RN(
n8532), .Q(Op_MY[35]), .QN(n782) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_34_ ( .D(n616), .CK(clk), .RN(
n8535), .Q(Op_MY[34]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_33_ ( .D(n615), .CK(clk), .RN(
n8534), .Q(Op_MY[33]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n613), .CK(clk), .RN(
n8534), .Q(Op_MY[31]), .QN(n798) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n612), .CK(clk), .RN(
n8535), .Q(Op_MY[30]), .QN(n801) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n611), .CK(clk), .RN(
n8535), .Q(Op_MY[29]), .QN(n854) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n610), .CK(clk), .RN(
n8535), .Q(Op_MY[28]), .QN(n797) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n609), .CK(clk), .RN(
n8535), .Q(Op_MY[27]), .QN(n803) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n608), .CK(clk), .RN(
n8534), .Q(Op_MY[26]), .QN(n1017) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n607), .CK(clk), .RN(
n8533), .Q(Op_MY[25]), .QN(n1010) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n606), .CK(clk), .RN(
n8533), .Q(Op_MY[24]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n605), .CK(clk), .RN(
n8533), .Q(Op_MY[23]), .QN(n769) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n604), .CK(clk), .RN(
n8533), .Q(Op_MY[22]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n603), .CK(clk), .RN(
n8533), .Q(Op_MY[21]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n602), .CK(clk), .RN(
n8533), .Q(Op_MY[20]), .QN(n1018) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n601), .CK(clk), .RN(
n8533), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n600), .CK(clk), .RN(
n8533), .Q(Op_MY[18]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n599), .CK(clk), .RN(
n8533), .Q(Op_MY[17]), .QN(n783) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n598), .CK(clk), .RN(
n8510), .Q(Op_MY[16]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n597), .CK(clk), .RN(
n8503), .Q(Op_MY[15]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n596), .CK(clk), .RN(
n8503), .Q(Op_MY[14]), .QN(n1009) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n595), .CK(clk), .RN(
n8503), .Q(Op_MY[13]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n594), .CK(clk), .RN(
n8503), .Q(Op_MY[12]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n593), .CK(clk), .RN(
n8503), .Q(Op_MY[11]), .QN(n735) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n592), .CK(clk), .RN(
n8503), .Q(Op_MY[10]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n591), .CK(clk), .RN(
n8503), .Q(Op_MY[9]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n590), .CK(clk), .RN(
n8503), .Q(Op_MY[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n589), .CK(clk), .RN(
n8503), .Q(Op_MY[7]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n588), .CK(clk), .RN(
n8504), .Q(Op_MY[6]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n587), .CK(clk), .RN(
n8504), .Q(Op_MY[5]), .QN(n730) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n586), .CK(clk), .RN(
n8504), .Q(Op_MY[4]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n585), .CK(clk), .RN(
n8504), .Q(Op_MY[3]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n584), .CK(clk), .RN(
n8504), .Q(Op_MY[2]), .QN(n1013) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n583), .CK(clk), .RN(
n8504), .Q(Op_MY[1]), .QN(n1005) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n582), .CK(clk), .RN(
n8504), .Q(Op_MY[0]), .QN(n999) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_52_ ( .D(n473), .CK(clk), .RN(
n8497), .Q(P_Sgf[52]) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n419), .CK(clk), .RN(n8504), .Q(
FSM_selector_B[0]), .QN(n8450) );
DFFHQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_44_ ( .D(
Sgf_operation_ODD1_right_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n287),
.CK(clk), .RN(n8518), .Q(final_result_ieee[63]), .QN(n8490) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n356), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[3]), .QN(n8489) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n360), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[7]), .QN(n8488) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n366), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[13]), .QN(n8487) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n368), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[15]), .QN(n8486) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n370), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[17]), .QN(n8485) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n372), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[19]), .QN(n8484) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n362), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[9]), .QN(n8483) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n364), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[11]), .QN(n8482) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n374), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[21]), .QN(n8481) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n376), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[23]), .QN(n8480) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n378), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[25]), .QN(n8479) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n380), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[27]), .QN(n8478) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n382), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[29]), .QN(n8477) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n390), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[37]), .QN(n8476) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n384), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[31]), .QN(n8475) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n386), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[33]), .QN(n8474) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n388), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[35]), .QN(n8473) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n394), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[41]), .QN(n8472) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n367), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[14]), .QN(n8469) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n359), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[6]), .QN(n8468) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n365), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[12]), .QN(n8467) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n369), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[16]), .QN(n8466) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n371), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[18]), .QN(n8465) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n389), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[36]), .QN(n8464) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n375), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[22]), .QN(n8463) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n379), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[26]), .QN(n8462) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n383), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[30]), .QN(n8461) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n361), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[8]), .QN(n8460) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n363), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[10]), .QN(n8459) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n373), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[20]), .QN(n8458) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n377), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[24]), .QN(n8457) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n381), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[28]), .QN(n8456) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n385), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[32]), .QN(n8455) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n387), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[34]), .QN(n8454) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n393), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[40]), .QN(n8452) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n391), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[38]), .QN(n8451) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n392), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[39]), .QN(n8449) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n709), .CK(clk), .RN(n8505), .Q(FSM_selector_C),
.QN(n8448) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n351),
.CK(clk), .RN(n8511), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n350),
.CK(clk), .RN(n8511), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n349),
.CK(clk), .RN(n8512), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n348),
.CK(clk), .RN(n8512), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n347),
.CK(clk), .RN(n8512), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n346),
.CK(clk), .RN(n8512), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n345),
.CK(clk), .RN(n8512), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n344),
.CK(clk), .RN(n8512), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n343),
.CK(clk), .RN(n8512), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n342),
.CK(clk), .RN(n8512), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n341),
.CK(clk), .RN(n8512), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n340),
.CK(clk), .RN(n8512), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n339),
.CK(clk), .RN(n8513), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n338),
.CK(clk), .RN(n8513), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n337),
.CK(clk), .RN(n8513), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n336),
.CK(clk), .RN(n8513), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n335),
.CK(clk), .RN(n8513), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n334),
.CK(clk), .RN(n8513), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n333),
.CK(clk), .RN(n8513), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n332),
.CK(clk), .RN(n8513), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n331),
.CK(clk), .RN(n8513), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n330),
.CK(clk), .RN(n8513), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n329),
.CK(clk), .RN(n8514), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n328),
.CK(clk), .RN(n8514), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n327),
.CK(clk), .RN(n8514), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n326),
.CK(clk), .RN(n8514), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n325),
.CK(clk), .RN(n8514), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n324),
.CK(clk), .RN(n8514), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n323),
.CK(clk), .RN(n8514), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n322),
.CK(clk), .RN(n8514), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n321),
.CK(clk), .RN(n8514), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n320),
.CK(clk), .RN(n8514), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n319),
.CK(clk), .RN(n8515), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n318),
.CK(clk), .RN(n8515), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n317),
.CK(clk), .RN(n8515), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n316),
.CK(clk), .RN(n8515), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n315),
.CK(clk), .RN(n8515), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n314),
.CK(clk), .RN(n8515), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n313),
.CK(clk), .RN(n8515), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n312),
.CK(clk), .RN(n8515), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n311),
.CK(clk), .RN(n8515), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n310),
.CK(clk), .RN(n8515), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n309),
.CK(clk), .RN(n8516), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n308),
.CK(clk), .RN(n8516), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n307),
.CK(clk), .RN(n8516), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n306),
.CK(clk), .RN(n8516), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n305),
.CK(clk), .RN(n8516), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n304),
.CK(clk), .RN(n8516), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n303),
.CK(clk), .RN(n8516), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n302),
.CK(clk), .RN(n8516), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n301),
.CK(clk), .RN(n8516), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n300),
.CK(clk), .RN(n8516), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n299),
.CK(clk), .RN(n8517), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n298),
.CK(clk), .RN(n8517), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n297),
.CK(clk), .RN(n8517), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n296),
.CK(clk), .RN(n8517), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n295),
.CK(clk), .RN(n8517), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n294),
.CK(clk), .RN(n8517), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n293),
.CK(clk), .RN(n8517), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n292),
.CK(clk), .RN(n8517), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n291),
.CK(clk), .RN(n8517), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n290),
.CK(clk), .RN(n8517), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n289),
.CK(clk), .RN(n8518), .Q(final_result_ieee[62]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n405), .CK(clk), .RN(n8504), .Q(
Exp_module_Overflow_flag_A) );
DFFQX1TS Sgf_operation_ODD1_left_Data_S_o_reg_51_ ( .D(
Sgf_operation_ODD1_left_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[51]) );
CMPR32X2TS DP_OP_36J24_124_1029_U2 ( .A(n8366), .B(S_Oper_A_exp[11]), .C(
DP_OP_36J24_124_1029_n2), .CO(DP_OP_36J24_124_1029_n1), .S(
Exp_module_Data_S[11]) );
CMPR32X2TS DP_OP_36J24_124_1029_U9 ( .A(DP_OP_36J24_124_1029_n24), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J24_124_1029_n9), .CO(
DP_OP_36J24_124_1029_n8), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J24_124_1029_U10 ( .A(DP_OP_36J24_124_1029_n25), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J24_124_1029_n10), .CO(
DP_OP_36J24_124_1029_n9), .S(Exp_module_Data_S[3]) );
CMPR42X2TS mult_x_24_U887 ( .A(mult_x_24_n1064), .B(mult_x_24_n1603), .C(
mult_x_24_n1067), .D(mult_x_24_n1630), .ICI(mult_x_24_n1657), .S(
mult_x_24_n1062), .ICO(mult_x_24_n1060), .CO(mult_x_24_n1061) );
CMPR42X2TS mult_x_24_U885 ( .A(mult_x_24_n1059), .B(mult_x_24_n1602), .C(
mult_x_24_n1060), .D(mult_x_24_n1656), .ICI(mult_x_24_n1629), .S(
mult_x_24_n1057), .ICO(mult_x_24_n1055), .CO(mult_x_24_n1056) );
CMPR42X2TS mult_x_24_U883 ( .A(mult_x_24_n1054), .B(mult_x_24_n1628), .C(
mult_x_24_n1601), .D(mult_x_24_n1655), .ICI(mult_x_24_n1055), .S(
mult_x_24_n1052), .ICO(mult_x_24_n1050), .CO(mult_x_24_n1051) );
CMPR42X2TS mult_x_24_U880 ( .A(mult_x_24_n1047), .B(mult_x_24_n1600), .C(
mult_x_24_n1627), .D(mult_x_24_n1654), .ICI(mult_x_24_n1050), .S(
mult_x_24_n1045), .ICO(mult_x_24_n1043), .CO(mult_x_24_n1044) );
CMPR42X2TS mult_x_24_U877 ( .A(mult_x_24_n1653), .B(mult_x_24_n1626), .C(
mult_x_24_n1599), .D(mult_x_24_n1040), .ICI(mult_x_24_n1043), .S(
mult_x_24_n1038), .ICO(mult_x_24_n1036), .CO(mult_x_24_n1037) );
CMPR42X2TS mult_x_24_U874 ( .A(mult_x_24_n1652), .B(mult_x_24_n1625), .C(
mult_x_24_n1039), .D(mult_x_24_n1033), .ICI(mult_x_24_n1036), .S(
mult_x_24_n1031), .ICO(mult_x_24_n1029), .CO(mult_x_24_n1030) );
CMPR42X2TS mult_x_24_U872 ( .A(mult_x_24_n1028), .B(mult_x_24_n1543), .C(
mult_x_24_n1034), .D(mult_x_24_n1570), .ICI(mult_x_24_n1651), .S(
mult_x_24_n1026), .ICO(mult_x_24_n1024), .CO(mult_x_24_n1025) );
CMPR42X2TS mult_x_24_U871 ( .A(mult_x_24_n1624), .B(mult_x_24_n1597), .C(
mult_x_24_n1032), .D(mult_x_24_n1029), .ICI(mult_x_24_n1026), .S(
mult_x_24_n1023), .ICO(mult_x_24_n1021), .CO(mult_x_24_n1022) );
CMPR42X2TS mult_x_24_U869 ( .A(mult_x_24_n1020), .B(mult_x_24_n1542), .C(
mult_x_24_n1024), .D(mult_x_24_n1623), .ICI(mult_x_24_n1596), .S(
mult_x_24_n1018), .ICO(mult_x_24_n1016), .CO(mult_x_24_n1017) );
CMPR42X2TS mult_x_24_U868 ( .A(mult_x_24_n1569), .B(mult_x_24_n1650), .C(
mult_x_24_n1025), .D(mult_x_24_n1021), .ICI(mult_x_24_n1018), .S(
mult_x_24_n1015), .ICO(mult_x_24_n1013), .CO(mult_x_24_n1014) );
CMPR42X1TS mult_x_24_U866 ( .A(mult_x_24_n1012), .B(mult_x_24_n1568), .C(
mult_x_24_n1541), .D(mult_x_24_n1622), .ICI(mult_x_24_n1016), .S(
mult_x_24_n1010), .ICO(mult_x_24_n1008), .CO(mult_x_24_n1009) );
CMPR42X2TS mult_x_24_U865 ( .A(mult_x_24_n1595), .B(mult_x_24_n1649), .C(
mult_x_24_n1017), .D(mult_x_24_n1013), .ICI(mult_x_24_n1010), .S(
mult_x_24_n1007), .ICO(mult_x_24_n1005), .CO(mult_x_24_n1006) );
CMPR42X2TS mult_x_24_U862 ( .A(mult_x_24_n1002), .B(mult_x_24_n1540), .C(
mult_x_24_n1594), .D(mult_x_24_n1567), .ICI(mult_x_24_n1648), .S(
mult_x_24_n1000), .ICO(mult_x_24_n998), .CO(mult_x_24_n999) );
CMPR42X2TS mult_x_24_U861 ( .A(mult_x_24_n1621), .B(mult_x_24_n1008), .C(
mult_x_24_n1009), .D(mult_x_24_n1000), .ICI(mult_x_24_n1005), .S(
mult_x_24_n997), .ICO(mult_x_24_n995), .CO(mult_x_24_n996) );
CMPR42X2TS mult_x_24_U858 ( .A(mult_x_24_n1593), .B(mult_x_24_n1539), .C(
mult_x_24_n992), .D(mult_x_24_n1620), .ICI(mult_x_24_n998), .S(
mult_x_24_n990), .ICO(mult_x_24_n988), .CO(mult_x_24_n989) );
CMPR42X2TS mult_x_24_U857 ( .A(mult_x_24_n1566), .B(mult_x_24_n1647), .C(
mult_x_24_n999), .D(mult_x_24_n990), .ICI(mult_x_24_n995), .S(
mult_x_24_n987), .ICO(mult_x_24_n985), .CO(mult_x_24_n986) );
CMPR42X2TS mult_x_24_U853 ( .A(mult_x_24_n1619), .B(mult_x_24_n982), .C(
mult_x_24_n989), .D(mult_x_24_n980), .ICI(mult_x_24_n985), .S(
mult_x_24_n977), .ICO(mult_x_24_n975), .CO(mult_x_24_n976) );
CMPR42X2TS mult_x_24_U851 ( .A(mult_x_24_n974), .B(mult_x_24_n1483), .C(
mult_x_24_n983), .D(mult_x_24_n1510), .ICI(mult_x_24_n1537), .S(
mult_x_24_n972), .ICO(mult_x_24_n970), .CO(mult_x_24_n971) );
CMPR42X2TS mult_x_24_U850 ( .A(mult_x_24_n1591), .B(mult_x_24_n1564), .C(
mult_x_24_n981), .D(mult_x_24_n1645), .ICI(mult_x_24_n978), .S(
mult_x_24_n969), .ICO(mult_x_24_n967), .CO(mult_x_24_n968) );
CMPR42X2TS mult_x_24_U849 ( .A(mult_x_24_n1618), .B(mult_x_24_n972), .C(
mult_x_24_n979), .D(mult_x_24_n969), .ICI(mult_x_24_n975), .S(
mult_x_24_n966), .ICO(mult_x_24_n964), .CO(mult_x_24_n965) );
CMPR42X2TS mult_x_24_U847 ( .A(mult_x_24_n963), .B(mult_x_24_n1482), .C(
mult_x_24_n970), .D(mult_x_24_n1536), .ICI(mult_x_24_n1563), .S(
mult_x_24_n961), .ICO(mult_x_24_n959), .CO(mult_x_24_n960) );
CMPR42X2TS mult_x_24_U845 ( .A(mult_x_24_n971), .B(mult_x_24_n961), .C(
mult_x_24_n968), .D(mult_x_24_n958), .ICI(mult_x_24_n964), .S(
mult_x_24_n955), .ICO(mult_x_24_n953), .CO(mult_x_24_n954) );
CMPR42X2TS mult_x_24_U842 ( .A(mult_x_24_n1562), .B(mult_x_24_n1616), .C(
mult_x_24_n1589), .D(mult_x_24_n1643), .ICI(mult_x_24_n960), .S(
mult_x_24_n947), .ICO(mult_x_24_n945), .CO(mult_x_24_n946) );
CMPR42X2TS mult_x_24_U841 ( .A(mult_x_24_n956), .B(mult_x_24_n950), .C(
mult_x_24_n957), .D(mult_x_24_n947), .ICI(mult_x_24_n953), .S(
mult_x_24_n944), .ICO(mult_x_24_n942), .CO(mult_x_24_n943) );
CMPR42X1TS mult_x_24_U837 ( .A(mult_x_24_n1507), .B(mult_x_24_n948), .C(
mult_x_24_n1588), .D(mult_x_24_n1642), .ICI(mult_x_24_n945), .S(
mult_x_24_n934), .ICO(mult_x_24_n932), .CO(mult_x_24_n933) );
CMPR42X2TS mult_x_24_U836 ( .A(mult_x_24_n949), .B(mult_x_24_n937), .C(
mult_x_24_n946), .D(mult_x_24_n934), .ICI(mult_x_24_n942), .S(
mult_x_24_n931), .ICO(mult_x_24_n929), .CO(mult_x_24_n930) );
CMPR42X2TS mult_x_24_U833 ( .A(mult_x_24_n1533), .B(mult_x_24_n1479), .C(
mult_x_24_n926), .D(mult_x_24_n1560), .ICI(mult_x_24_n932), .S(
mult_x_24_n924), .ICO(mult_x_24_n922), .CO(mult_x_24_n923) );
CMPR42X2TS mult_x_24_U832 ( .A(mult_x_24_n1506), .B(mult_x_24_n1614), .C(
mult_x_24_n1641), .D(mult_x_24_n1587), .ICI(mult_x_24_n935), .S(
mult_x_24_n921), .ICO(mult_x_24_n919), .CO(mult_x_24_n920) );
CMPR42X2TS mult_x_24_U831 ( .A(mult_x_24_n936), .B(mult_x_24_n924), .C(
mult_x_24_n933), .D(mult_x_24_n921), .ICI(mult_x_24_n929), .S(
mult_x_24_n918), .ICO(mult_x_24_n916), .CO(mult_x_24_n917) );
CMPR42X2TS mult_x_24_U828 ( .A(mult_x_24_n1532), .B(mult_x_24_n1505), .C(
mult_x_24_n925), .D(mult_x_24_n1559), .ICI(mult_x_24_n919), .S(
mult_x_24_n911), .ICO(mult_x_24_n909), .CO(mult_x_24_n910) );
CMPR42X2TS mult_x_24_U826 ( .A(mult_x_24_n923), .B(mult_x_24_n911), .C(
mult_x_24_n920), .D(mult_x_24_n908), .ICI(mult_x_24_n916), .S(
mult_x_24_n905), .ICO(mult_x_24_n903), .CO(mult_x_24_n904) );
CMPR42X2TS mult_x_24_U825 ( .A(mult_x_24_n1109), .B(mult_x_24_n1423), .C(
mult_x_24_n914), .D(mult_x_24_n1450), .ICI(mult_x_24_n1477), .S(
mult_x_24_n902), .ICO(mult_x_24_n900), .CO(mult_x_24_n901) );
CMPR42X2TS mult_x_24_U822 ( .A(mult_x_24_n910), .B(mult_x_24_n899), .C(
mult_x_24_n907), .D(mult_x_24_n896), .ICI(mult_x_24_n903), .S(
mult_x_24_n893), .ICO(mult_x_24_n891), .CO(mult_x_24_n892) );
CMPR42X2TS mult_x_24_U821 ( .A(mult_x_24_n1108), .B(mult_x_24_n1422), .C(
mult_x_24_n900), .D(mult_x_24_n1476), .ICI(mult_x_24_n1503), .S(
mult_x_24_n890), .ICO(mult_x_24_n888), .CO(mult_x_24_n889) );
CMPR42X2TS mult_x_24_U819 ( .A(mult_x_24_n1611), .B(mult_x_24_n1557), .C(
mult_x_24_n901), .D(mult_x_24_n897), .ICI(mult_x_24_n890), .S(
mult_x_24_n884), .ICO(mult_x_24_n882), .CO(mult_x_24_n883) );
CMPR42X2TS mult_x_24_U815 ( .A(mult_x_24_n1610), .B(mult_x_24_n1556), .C(
mult_x_24_n885), .D(mult_x_24_n878), .ICI(mult_x_24_n882), .S(
mult_x_24_n872), .ICO(mult_x_24_n870), .CO(mult_x_24_n871) );
CMPR42X1TS mult_x_24_U813 ( .A(n6730), .B(mult_x_24_n1106), .C(
mult_x_24_n1420), .D(mult_x_24_n1447), .ICI(mult_x_24_n1501), .S(
mult_x_24_n866), .ICO(mult_x_24_n864), .CO(mult_x_24_n865) );
CMPR42X1TS mult_x_24_U812 ( .A(mult_x_24_n1474), .B(mult_x_24_n876), .C(
mult_x_24_n1528), .D(mult_x_24_n1582), .ICI(mult_x_24_n873), .S(
mult_x_24_n863), .ICO(mult_x_24_n861), .CO(mult_x_24_n862) );
CMPR42X2TS mult_x_24_U811 ( .A(mult_x_24_n1609), .B(mult_x_24_n1555), .C(
mult_x_24_n877), .D(mult_x_24_n870), .ICI(mult_x_24_n866), .S(
mult_x_24_n860), .ICO(mult_x_24_n858), .CO(mult_x_24_n859) );
CMPR42X2TS mult_x_24_U808 ( .A(mult_x_24_n1608), .B(mult_x_24_n1500), .C(
mult_x_24_n864), .D(mult_x_24_n1581), .ICI(mult_x_24_n865), .S(
mult_x_24_n851), .ICO(mult_x_24_n849), .CO(mult_x_24_n850) );
CMPR42X2TS mult_x_24_U807 ( .A(mult_x_24_n1554), .B(mult_x_24_n1527), .C(
mult_x_24_n861), .D(mult_x_24_n854), .ICI(mult_x_24_n858), .S(
mult_x_24_n848), .ICO(mult_x_24_n846), .CO(mult_x_24_n847) );
CMPR42X2TS mult_x_24_U805 ( .A(n1013), .B(n730), .C(mult_x_24_n1104), .D(
mult_x_24_n1418), .ICI(mult_x_24_n1472), .S(mult_x_24_n842), .ICO(
mult_x_24_n840), .CO(mult_x_24_n841) );
CMPR42X2TS mult_x_24_U803 ( .A(mult_x_24_n1553), .B(mult_x_24_n852), .C(
mult_x_24_n842), .D(mult_x_24_n853), .ICI(mult_x_24_n846), .S(
mult_x_24_n836), .ICO(mult_x_24_n834), .CO(mult_x_24_n835) );
CMPR42X2TS mult_x_24_U802 ( .A(mult_x_24_n850), .B(mult_x_24_n839), .C(
mult_x_24_n847), .D(mult_x_24_n836), .ICI(mult_x_24_n843), .S(
mult_x_24_n833), .ICO(mult_x_24_n831), .CO(mult_x_24_n832) );
CMPR42X2TS mult_x_24_U799 ( .A(mult_x_24_n1471), .B(mult_x_24_n1444), .C(
mult_x_24_n1498), .D(mult_x_24_n1552), .ICI(mult_x_24_n837), .S(
mult_x_24_n827), .ICO(mult_x_24_n825), .CO(mult_x_24_n826) );
CMPR42X2TS mult_x_24_U798 ( .A(mult_x_24_n1579), .B(mult_x_24_n1525), .C(
mult_x_24_n829), .D(mult_x_24_n841), .ICI(mult_x_24_n834), .S(
mult_x_24_n824), .ICO(mult_x_24_n822), .CO(mult_x_24_n823) );
CMPR42X2TS mult_x_24_U797 ( .A(mult_x_24_n827), .B(mult_x_24_n838), .C(
mult_x_24_n824), .D(mult_x_24_n835), .ICI(mult_x_24_n831), .S(
mult_x_24_n821), .ICO(mult_x_24_n819), .CO(mult_x_24_n820) );
CMPR42X2TS mult_x_24_U794 ( .A(mult_x_24_n1443), .B(mult_x_24_n1578), .C(
mult_x_24_n1470), .D(mult_x_24_n828), .ICI(mult_x_24_n825), .S(
mult_x_24_n815), .ICO(mult_x_24_n813), .CO(mult_x_24_n814) );
CMPR42X2TS mult_x_24_U793 ( .A(mult_x_24_n1551), .B(mult_x_24_n1497), .C(
mult_x_24_n1524), .D(mult_x_24_n817), .ICI(mult_x_24_n822), .S(
mult_x_24_n812), .ICO(mult_x_24_n810), .CO(mult_x_24_n811) );
CMPR42X2TS mult_x_24_U792 ( .A(mult_x_24_n826), .B(mult_x_24_n815), .C(
mult_x_24_n812), .D(mult_x_24_n823), .ICI(mult_x_24_n819), .S(
mult_x_24_n809), .ICO(mult_x_24_n807), .CO(mult_x_24_n808) );
CMPR42X2TS mult_x_24_U790 ( .A(mult_x_24_n806), .B(mult_x_24_n1415), .C(
mult_x_24_n1442), .D(mult_x_24_n816), .ICI(mult_x_24_n1496), .S(
mult_x_24_n804), .ICO(mult_x_24_n802), .CO(mult_x_24_n803) );
CMPR42X2TS mult_x_24_U789 ( .A(mult_x_24_n1550), .B(mult_x_24_n1469), .C(
mult_x_24_n1523), .D(mult_x_24_n813), .ICI(mult_x_24_n810), .S(
mult_x_24_n801), .ICO(mult_x_24_n799), .CO(mult_x_24_n800) );
CMPR42X2TS mult_x_24_U788 ( .A(mult_x_24_n814), .B(mult_x_24_n804), .C(
mult_x_24_n811), .D(mult_x_24_n801), .ICI(mult_x_24_n807), .S(
mult_x_24_n798), .ICO(mult_x_24_n796), .CO(mult_x_24_n797) );
CMPR42X2TS mult_x_24_U785 ( .A(mult_x_24_n1549), .B(mult_x_24_n1468), .C(
mult_x_24_n1522), .D(mult_x_24_n802), .ICI(mult_x_24_n803), .S(
mult_x_24_n791), .ICO(mult_x_24_n789), .CO(mult_x_24_n790) );
CMPR42X2TS mult_x_24_U784 ( .A(mult_x_24_n799), .B(mult_x_24_n794), .C(
mult_x_24_n800), .D(mult_x_24_n791), .ICI(mult_x_24_n796), .S(
mult_x_24_n788), .ICO(mult_x_24_n786), .CO(mult_x_24_n787) );
CMPR42X2TS mult_x_24_U782 ( .A(mult_x_24_n1099), .B(mult_x_24_n795), .C(
mult_x_24_n1413), .D(mult_x_24_n1548), .ICI(mult_x_24_n1440), .S(
mult_x_24_n784), .ICO(mult_x_24_n782), .CO(mult_x_24_n783) );
CMPR42X2TS mult_x_24_U781 ( .A(mult_x_24_n1521), .B(mult_x_24_n1494), .C(
mult_x_24_n1467), .D(mult_x_24_n792), .ICI(mult_x_24_n784), .S(
mult_x_24_n781), .ICO(mult_x_24_n779), .CO(mult_x_24_n780) );
CMPR42X2TS mult_x_24_U780 ( .A(mult_x_24_n789), .B(mult_x_24_n793), .C(
mult_x_24_n790), .D(mult_x_24_n781), .ICI(mult_x_24_n786), .S(
mult_x_24_n778), .ICO(mult_x_24_n776), .CO(mult_x_24_n777) );
CMPR42X2TS mult_x_24_U779 ( .A(n735), .B(mult_x_24_n1100), .C(
mult_x_24_n1098), .D(mult_x_24_n1412), .ICI(mult_x_24_n1466), .S(
mult_x_24_n775), .ICO(mult_x_24_n773), .CO(mult_x_24_n774) );
CMPR42X2TS mult_x_24_U778 ( .A(mult_x_24_n1520), .B(mult_x_24_n1493), .C(
mult_x_24_n1439), .D(mult_x_24_n782), .ICI(mult_x_24_n775), .S(
mult_x_24_n772), .ICO(mult_x_24_n770), .CO(mult_x_24_n771) );
CMPR42X2TS mult_x_24_U777 ( .A(mult_x_24_n779), .B(mult_x_24_n783), .C(
mult_x_24_n780), .D(mult_x_24_n772), .ICI(mult_x_24_n776), .S(
mult_x_24_n769), .ICO(mult_x_24_n767), .CO(mult_x_24_n768) );
CMPR42X2TS mult_x_24_U773 ( .A(mult_x_24_n1438), .B(mult_x_24_n770), .C(
mult_x_24_n771), .D(mult_x_24_n763), .ICI(mult_x_24_n767), .S(
mult_x_24_n760), .ICO(mult_x_24_n758), .CO(mult_x_24_n759) );
CMPR42X2TS mult_x_24_U770 ( .A(mult_x_24_n1410), .B(mult_x_24_n764), .C(
mult_x_24_n1491), .D(mult_x_24_n1437), .ICI(mult_x_24_n761), .S(
mult_x_24_n754), .ICO(mult_x_24_n752), .CO(mult_x_24_n753) );
CMPR42X2TS mult_x_24_U769 ( .A(mult_x_24_n1464), .B(mult_x_24_n756), .C(
mult_x_24_n762), .D(mult_x_24_n754), .ICI(mult_x_24_n758), .S(
mult_x_24_n751), .ICO(mult_x_24_n749), .CO(mult_x_24_n750) );
CMPR42X1TS mult_x_24_U745 ( .A(n769), .B(mult_x_24_n1088), .C(
mult_x_24_n1086), .D(mult_x_24_n1400), .ICI(mult_x_24_n696), .S(
mult_x_24_n695), .ICO(mult_x_24_n693), .CO(mult_x_24_n694) );
CMPR42X2TS mult_x_23_U802 ( .A(mult_x_23_n950), .B(mult_x_23_n1428), .C(
mult_x_23_n951), .D(mult_x_23_n1480), .ICI(mult_x_23_n1454), .S(
mult_x_23_n948), .ICO(mult_x_23_n946), .CO(mult_x_23_n947) );
CMPR42X2TS mult_x_23_U800 ( .A(mult_x_23_n945), .B(mult_x_23_n1453), .C(
mult_x_23_n1427), .D(mult_x_23_n946), .ICI(mult_x_23_n1479), .S(
mult_x_23_n943), .ICO(mult_x_23_n941), .CO(mult_x_23_n942) );
CMPR42X2TS mult_x_23_U794 ( .A(mult_x_23_n1451), .B(mult_x_23_n1425), .C(
mult_x_23_n931), .D(mult_x_23_n934), .ICI(mult_x_23_n1477), .S(
mult_x_23_n929), .ICO(mult_x_23_n927), .CO(mult_x_23_n928) );
CMPR42X2TS mult_x_23_U791 ( .A(mult_x_23_n1476), .B(mult_x_23_n930), .C(
mult_x_23_n924), .D(mult_x_23_n1450), .ICI(mult_x_23_n927), .S(
mult_x_23_n922), .ICO(mult_x_23_n920), .CO(mult_x_23_n921) );
CMPR42X2TS mult_x_23_U789 ( .A(mult_x_23_n919), .B(mult_x_23_n1371), .C(
mult_x_23_n925), .D(mult_x_23_n1397), .ICI(mult_x_23_n1449), .S(
mult_x_23_n917), .ICO(mult_x_23_n915), .CO(mult_x_23_n916) );
CMPR42X2TS mult_x_23_U788 ( .A(mult_x_23_n1423), .B(mult_x_23_n923), .C(
mult_x_23_n1475), .D(mult_x_23_n920), .ICI(mult_x_23_n917), .S(
mult_x_23_n914), .ICO(mult_x_23_n912), .CO(mult_x_23_n913) );
CMPR42X1TS mult_x_23_U786 ( .A(mult_x_23_n911), .B(mult_x_23_n1370), .C(
mult_x_23_n915), .D(mult_x_23_n1422), .ICI(mult_x_23_n1474), .S(
mult_x_23_n909), .ICO(mult_x_23_n907), .CO(mult_x_23_n908) );
CMPR42X1TS mult_x_23_U783 ( .A(mult_x_23_n903), .B(mult_x_23_n1395), .C(
mult_x_23_n1369), .D(mult_x_23_n1447), .ICI(mult_x_23_n907), .S(
mult_x_23_n901), .ICO(mult_x_23_n899), .CO(mult_x_23_n900) );
CMPR42X2TS mult_x_23_U782 ( .A(mult_x_23_n1421), .B(mult_x_23_n1473), .C(
mult_x_23_n908), .D(mult_x_23_n904), .ICI(mult_x_23_n901), .S(
mult_x_23_n898), .ICO(mult_x_23_n896), .CO(mult_x_23_n897) );
CMPR42X2TS mult_x_23_U779 ( .A(mult_x_23_n1368), .B(mult_x_23_n893), .C(
mult_x_23_n1420), .D(mult_x_23_n1394), .ICI(mult_x_23_n1446), .S(
mult_x_23_n891), .ICO(mult_x_23_n889), .CO(mult_x_23_n890) );
CMPR42X2TS mult_x_23_U778 ( .A(mult_x_23_n899), .B(mult_x_23_n1472), .C(
mult_x_23_n900), .D(mult_x_23_n891), .ICI(mult_x_23_n896), .S(
mult_x_23_n888), .ICO(mult_x_23_n886), .CO(mult_x_23_n887) );
CMPR42X2TS mult_x_23_U775 ( .A(mult_x_23_n1393), .B(mult_x_23_n1367), .C(
mult_x_23_n1445), .D(mult_x_23_n883), .ICI(mult_x_23_n1419), .S(
mult_x_23_n881), .ICO(mult_x_23_n879), .CO(mult_x_23_n880) );
CMPR42X2TS mult_x_23_U774 ( .A(mult_x_23_n889), .B(mult_x_23_n1471), .C(
mult_x_23_n890), .D(mult_x_23_n881), .ICI(mult_x_23_n886), .S(
mult_x_23_n878), .ICO(mult_x_23_n876), .CO(mult_x_23_n877) );
CMPR42X2TS mult_x_23_U771 ( .A(mult_x_23_n1418), .B(mult_x_23_n882), .C(
mult_x_23_n1470), .D(mult_x_23_n873), .ICI(mult_x_23_n1444), .S(
mult_x_23_n871), .ICO(mult_x_23_n869), .CO(mult_x_23_n870) );
CMPR42X2TS mult_x_23_U770 ( .A(mult_x_23_n879), .B(mult_x_23_n1392), .C(
mult_x_23_n880), .D(mult_x_23_n871), .ICI(mult_x_23_n876), .S(
mult_x_23_n868), .ICO(mult_x_23_n866), .CO(mult_x_23_n867) );
CMPR42X2TS mult_x_23_U768 ( .A(mult_x_23_n865), .B(mult_x_23_n1313), .C(
mult_x_23_n874), .D(mult_x_23_n1339), .ICI(mult_x_23_n1365), .S(
mult_x_23_n863), .ICO(mult_x_23_n861), .CO(mult_x_23_n862) );
CMPR42X2TS mult_x_23_U767 ( .A(mult_x_23_n1391), .B(mult_x_23_n872), .C(
mult_x_23_n1443), .D(mult_x_23_n1417), .ICI(mult_x_23_n869), .S(
mult_x_23_n860), .ICO(mult_x_23_n858), .CO(mult_x_23_n859) );
CMPR42X2TS mult_x_23_U766 ( .A(mult_x_23_n1469), .B(mult_x_23_n863), .C(
mult_x_23_n870), .D(mult_x_23_n860), .ICI(mult_x_23_n866), .S(
mult_x_23_n857), .ICO(mult_x_23_n855), .CO(mult_x_23_n856) );
CMPR42X2TS mult_x_23_U764 ( .A(mult_x_23_n854), .B(mult_x_23_n1312), .C(
mult_x_23_n861), .D(mult_x_23_n1364), .ICI(mult_x_23_n1338), .S(
mult_x_23_n852), .ICO(mult_x_23_n850), .CO(mult_x_23_n851) );
CMPR42X2TS mult_x_23_U763 ( .A(mult_x_23_n1416), .B(mult_x_23_n1468), .C(
mult_x_23_n1390), .D(mult_x_23_n862), .ICI(mult_x_23_n858), .S(
mult_x_23_n849), .ICO(mult_x_23_n847), .CO(mult_x_23_n848) );
CMPR42X1TS mult_x_23_U760 ( .A(mult_x_23_n843), .B(mult_x_23_n1337), .C(
mult_x_23_n1311), .D(mult_x_23_n1389), .ICI(mult_x_23_n850), .S(
mult_x_23_n841), .ICO(mult_x_23_n839), .CO(mult_x_23_n840) );
CMPR42X2TS mult_x_23_U759 ( .A(mult_x_23_n1441), .B(mult_x_23_n1363), .C(
mult_x_23_n1415), .D(mult_x_23_n851), .ICI(mult_x_23_n841), .S(
mult_x_23_n838), .ICO(mult_x_23_n836), .CO(mult_x_23_n837) );
CMPR42X2TS mult_x_23_U758 ( .A(mult_x_23_n1467), .B(mult_x_23_n847), .C(
mult_x_23_n848), .D(mult_x_23_n844), .ICI(mult_x_23_n838), .S(
mult_x_23_n835), .ICO(mult_x_23_n833), .CO(mult_x_23_n834) );
CMPR42X2TS mult_x_23_U750 ( .A(mult_x_23_n1413), .B(mult_x_23_n819), .C(
mult_x_23_n826), .D(mult_x_23_n816), .ICI(mult_x_23_n822), .S(
mult_x_23_n813), .ICO(mult_x_23_n811), .CO(mult_x_23_n812) );
CMPR42X2TS mult_x_23_U746 ( .A(mult_x_23_n818), .B(mult_x_23_n808), .C(
mult_x_23_n815), .D(mult_x_23_n805), .ICI(mult_x_23_n811), .S(
mult_x_23_n802), .ICO(mult_x_23_n800), .CO(mult_x_23_n801) );
CMPR42X1TS mult_x_23_U743 ( .A(mult_x_23_n1385), .B(mult_x_23_n799), .C(
mult_x_23_n1359), .D(mult_x_23_n1411), .ICI(mult_x_23_n803), .S(
mult_x_23_n794), .ICO(mult_x_23_n792), .CO(mult_x_23_n793) );
CMPR42X2TS mult_x_23_U739 ( .A(mult_x_23_n788), .B(mult_x_23_n1332), .C(
mult_x_23_n1384), .D(mult_x_23_n1436), .ICI(mult_x_23_n792), .S(
mult_x_23_n783), .ICO(mult_x_23_n781), .CO(mult_x_23_n782) );
CMPR42X2TS mult_x_23_U738 ( .A(mult_x_23_n796), .B(mult_x_23_n786), .C(
mult_x_23_n793), .D(mult_x_23_n783), .ICI(mult_x_23_n789), .S(
mult_x_23_n780), .ICO(mult_x_23_n778), .CO(mult_x_23_n779) );
CMPR42X1TS mult_x_23_U736 ( .A(mult_x_23_n1331), .B(mult_x_23_n1435), .C(
mult_x_23_n777), .D(mult_x_23_n787), .ICI(mult_x_23_n784), .S(
mult_x_23_n775), .ICO(mult_x_23_n773), .CO(mult_x_23_n774) );
CMPR42X2TS mult_x_23_U734 ( .A(mult_x_23_n785), .B(mult_x_23_n775), .C(
mult_x_23_n782), .D(mult_x_23_n772), .ICI(mult_x_23_n778), .S(
mult_x_23_n769), .ICO(mult_x_23_n767), .CO(mult_x_23_n768) );
CMPR42X2TS mult_x_23_U732 ( .A(mult_x_23_n1304), .B(mult_x_23_n776), .C(
mult_x_23_n1434), .D(mult_x_23_n1408), .ICI(mult_x_23_n773), .S(
mult_x_23_n764), .ICO(mult_x_23_n762), .CO(mult_x_23_n763) );
CMPR42X2TS mult_x_23_U730 ( .A(mult_x_23_n774), .B(mult_x_23_n764), .C(
mult_x_23_n771), .D(mult_x_23_n761), .ICI(mult_x_23_n767), .S(
mult_x_23_n758), .ICO(mult_x_23_n756), .CO(mult_x_23_n757) );
CMPR42X2TS mult_x_23_U727 ( .A(mult_x_23_n1381), .B(mult_x_23_n1303), .C(
mult_x_23_n1355), .D(mult_x_23_n1407), .ICI(mult_x_23_n759), .S(
mult_x_23_n750), .ICO(mult_x_23_n748), .CO(mult_x_23_n749) );
CMPR42X2TS mult_x_23_U723 ( .A(mult_x_23_n751), .B(mult_x_23_n1276), .C(
mult_x_23_n1328), .D(mult_x_23_n1380), .ICI(mult_x_23_n748), .S(
mult_x_23_n740), .ICO(mult_x_23_n738), .CO(mult_x_23_n739) );
CMPR42X2TS mult_x_23_U722 ( .A(mult_x_23_n743), .B(mult_x_23_n752), .C(
mult_x_23_n749), .D(mult_x_23_n740), .ICI(mult_x_23_n745), .S(
mult_x_23_n737), .ICO(mult_x_23_n735), .CO(mult_x_23_n736) );
CMPR42X1TS mult_x_23_U720 ( .A(mult_x_23_n744), .B(mult_x_23_n1251), .C(
mult_x_23_n1275), .D(mult_x_23_n1405), .ICI(mult_x_23_n1379), .S(
mult_x_23_n732), .ICO(mult_x_23_n730), .CO(mult_x_23_n731) );
CMPR42X2TS mult_x_23_U718 ( .A(mult_x_23_n738), .B(mult_x_23_n732), .C(
mult_x_23_n739), .D(mult_x_23_n729), .ICI(mult_x_23_n735), .S(
mult_x_23_n726), .ICO(mult_x_23_n724), .CO(mult_x_23_n725) );
CMPR42X2TS mult_x_23_U712 ( .A(mult_x_23_n1377), .B(mult_x_23_n1325), .C(
mult_x_23_n1299), .D(mult_x_23_n713), .ICI(mult_x_23_n1351), .S(
mult_x_23_n711), .ICO(mult_x_23_n709), .CO(mult_x_23_n710) );
CMPR42X2TS mult_x_23_U708 ( .A(mult_x_23_n1298), .B(mult_x_23_n1350), .C(
mult_x_23_n1272), .D(mult_x_23_n712), .ICI(mult_x_23_n709), .S(
mult_x_23_n701), .ICO(mult_x_23_n699), .CO(mult_x_23_n700) );
CMPR42X2TS mult_x_23_U707 ( .A(mult_x_23_n703), .B(mult_x_23_n1324), .C(
mult_x_23_n710), .D(mult_x_23_n701), .ICI(mult_x_23_n706), .S(
mult_x_23_n698), .ICO(mult_x_23_n696), .CO(mult_x_23_n697) );
CMPR42X2TS mult_x_23_U705 ( .A(mult_x_23_n1248), .B(mult_x_23_n1323), .C(
mult_x_23_n695), .D(mult_x_23_n702), .ICI(mult_x_23_n699), .S(
mult_x_23_n693), .ICO(mult_x_23_n691), .CO(mult_x_23_n692) );
CMPR42X2TS mult_x_23_U704 ( .A(mult_x_23_n1349), .B(mult_x_23_n1297), .C(
mult_x_23_n700), .D(mult_x_23_n693), .ICI(mult_x_23_n696), .S(
mult_x_23_n690), .ICO(mult_x_23_n688), .CO(mult_x_23_n689) );
CMPR42X2TS mult_x_23_U696 ( .A(mult_x_23_n1320), .B(mult_x_23_n1268), .C(
mult_x_23_n677), .D(mult_x_23_n672), .ICI(mult_x_23_n673), .S(
mult_x_23_n670), .ICO(mult_x_23_n668), .CO(mult_x_23_n669) );
CMPR42X2TS mult_x_23_U693 ( .A(mult_x_23_n1267), .B(mult_x_23_n665), .C(
mult_x_23_n1293), .D(mult_x_23_n671), .ICI(mult_x_23_n668), .S(
mult_x_23_n663), .ICO(mult_x_23_n661), .CO(mult_x_23_n662) );
CMPR42X2TS mult_x_23_U686 ( .A(mult_x_23_n648), .B(mult_x_23_n1290), .C(
mult_x_23_n652), .D(mult_x_23_n1264), .ICI(mult_x_23_n649), .S(
mult_x_23_n647), .ICO(mult_x_23_n645), .CO(mult_x_23_n646) );
CMPR42X2TS mult_x_23_U702 ( .A(mult_x_23_n687), .B(mult_x_23_n1348), .C(
mult_x_23_n1296), .D(mult_x_23_n694), .ICI(mult_x_23_n1270), .S(
mult_x_23_n686), .ICO(mult_x_23_n684), .CO(mult_x_23_n685) );
CMPR42X2TS mult_x_23_U748 ( .A(mult_x_23_n1360), .B(mult_x_23_n820), .C(
mult_x_23_n1464), .D(mult_x_23_n1412), .ICI(mult_x_23_n1386), .S(
mult_x_23_n808), .ICO(mult_x_23_n806), .CO(mult_x_23_n807) );
CMPR42X2TS mult_x_24_U755 ( .A(mult_x_24_n1432), .B(mult_x_24_n1405), .C(
mult_x_24_n719), .D(mult_x_24_n725), .ICI(mult_x_24_n721), .S(
mult_x_24_n717), .ICO(mult_x_24_n715), .CO(mult_x_24_n716) );
CMPR42X2TS mult_x_23_U726 ( .A(mult_x_23_n763), .B(mult_x_23_n753), .C(
mult_x_23_n760), .D(mult_x_23_n750), .ICI(mult_x_23_n756), .S(
mult_x_23_n747), .ICO(mult_x_23_n745), .CO(mult_x_23_n746) );
CMPR42X2TS mult_x_23_U752 ( .A(mult_x_23_n1335), .B(mult_x_23_n1309), .C(
mult_x_23_n1387), .D(mult_x_23_n821), .ICI(mult_x_23_n825), .S(
mult_x_23_n819), .ICO(mult_x_23_n817), .CO(mult_x_23_n818) );
CMPR42X2TS mult_x_23_U762 ( .A(mult_x_23_n1442), .B(mult_x_23_n852), .C(
mult_x_23_n859), .D(mult_x_23_n855), .ICI(mult_x_23_n849), .S(
mult_x_23_n846), .ICO(mult_x_23_n844), .CO(mult_x_23_n845) );
CMPR42X2TS mult_x_23_U683 ( .A(n1015), .B(mult_x_23_n643), .C(
mult_x_23_n1242), .D(mult_x_23_n640), .ICI(mult_x_23_n1262), .S(
mult_x_23_n639), .ICO(mult_x_23_n637), .CO(mult_x_23_n638) );
CMPR42X2TS mult_x_23_U719 ( .A(mult_x_23_n1327), .B(mult_x_23_n741), .C(
mult_x_23_n1301), .D(mult_x_23_n1353), .ICI(mult_x_23_n742), .S(
mult_x_23_n729), .ICO(mult_x_23_n727), .CO(mult_x_23_n728) );
CMPR42X2TS mult_x_24_U814 ( .A(mult_x_24_n886), .B(mult_x_24_n875), .C(
mult_x_24_n883), .D(mult_x_24_n879), .ICI(mult_x_24_n872), .S(
mult_x_24_n869), .ICO(mult_x_24_n867), .CO(mult_x_24_n868) );
CMPR42X2TS mult_x_23_U754 ( .A(mult_x_23_n836), .B(mult_x_23_n830), .C(
mult_x_23_n837), .D(mult_x_23_n833), .ICI(mult_x_23_n827), .S(
mult_x_23_n824), .ICO(mult_x_23_n822), .CO(mult_x_23_n823) );
CMPR42X2TS mult_x_24_U820 ( .A(mult_x_24_n1449), .B(mult_x_24_n1638), .C(
mult_x_24_n1530), .D(mult_x_24_n1584), .ICI(mult_x_24_n894), .S(
mult_x_24_n887), .ICO(mult_x_24_n885), .CO(mult_x_24_n886) );
CMPR42X2TS mult_x_24_U810 ( .A(mult_x_24_n874), .B(mult_x_24_n863), .C(
mult_x_24_n871), .D(mult_x_24_n860), .ICI(mult_x_24_n867), .S(
mult_x_24_n857), .ICO(mult_x_24_n855), .CO(mult_x_24_n856) );
CMPR42X2TS mult_x_24_U806 ( .A(mult_x_24_n862), .B(mult_x_24_n851), .C(
mult_x_24_n859), .D(mult_x_24_n848), .ICI(mult_x_24_n855), .S(
mult_x_24_n845), .ICO(mult_x_24_n843), .CO(mult_x_24_n844) );
CMPR42X2TS mult_x_24_U827 ( .A(mult_x_24_n1640), .B(mult_x_24_n1586), .C(
mult_x_24_n1613), .D(mult_x_24_n913), .ICI(mult_x_24_n922), .S(
mult_x_24_n908), .ICO(mult_x_24_n906), .CO(mult_x_24_n907) );
CMPR42X2TS mult_x_23_U785 ( .A(mult_x_23_n1396), .B(mult_x_23_n1448), .C(
mult_x_23_n916), .D(mult_x_23_n912), .ICI(mult_x_23_n909), .S(
mult_x_23_n906), .ICO(mult_x_23_n904), .CO(mult_x_23_n905) );
CMPR42X2TS mult_x_23_U731 ( .A(mult_x_23_n1356), .B(mult_x_23_n766), .C(
mult_x_23_n1330), .D(mult_x_23_n1382), .ICI(mult_x_23_n770), .S(
mult_x_23_n761), .ICO(mult_x_23_n759), .CO(mult_x_23_n760) );
CMPR42X2TS mult_x_23_U711 ( .A(mult_x_23_n722), .B(mult_x_23_n719), .C(
mult_x_23_n711), .D(mult_x_23_n720), .ICI(mult_x_23_n716), .S(
mult_x_23_n708), .ICO(mult_x_23_n706), .CO(mult_x_23_n707) );
CMPR42X2TS mult_x_24_U750 ( .A(mult_x_24_n708), .B(mult_x_24_n1430), .C(
mult_x_24_n1403), .D(mult_x_24_n712), .ICI(mult_x_24_n709), .S(
mult_x_24_n706), .ICO(mult_x_24_n704), .CO(mult_x_24_n705) );
CMPR42X2TS mult_x_23_U699 ( .A(mult_x_23_n687), .B(mult_x_23_n1247), .C(
mult_x_23_n1347), .D(mult_x_23_n1269), .ICI(mult_x_23_n1321), .S(
mult_x_23_n678), .ICO(mult_x_23_n676), .CO(mult_x_23_n677) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n418), .CK(clk), .RN(n8504), .Q(
FSM_selector_B[1]), .QN(n8536) );
DFFX1TS Sgf_operation_ODD1_right_Data_S_o_reg_0_ ( .D(
Sgf_operation_ODD1_right_N0), .CK(clk), .Q(Sgf_operation_Result[0]),
.QN(DP_OP_168J24_122_1342_n587) );
DFFX1TS Sgf_operation_ODD1_left_Data_S_o_reg_22_ ( .D(
Sgf_operation_ODD1_left_N22), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[22]), .QN(DP_OP_168J24_122_1342_n617) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_32_ ( .D(
Sgf_operation_ODD1_middle_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[32]) );
DFFRX1TS FS_Module_state_reg_reg_1_ ( .D(n712), .CK(clk), .RN(n8497), .Q(
FS_Module_state_reg[1]), .QN(n1036) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n357), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[4]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n355), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n358), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n395), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n397), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n399), .CK(clk),
.RN(n8506), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n401), .CK(clk),
.RN(n8505), .Q(Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n403), .CK(clk),
.RN(n8506), .Q(Sgf_normalized_result[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n396), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[43]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n398), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[45]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n400), .CK(clk),
.RN(n8535), .Q(Sgf_normalized_result[47]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n402), .CK(clk),
.RN(n8535), .Q(Sgf_normalized_result[49]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n404), .CK(clk),
.RN(n8535), .Q(Sgf_normalized_result[51]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_105_ ( .D(n420), .CK(clk), .RN(
n8497), .Q(P_Sgf[105]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n703), .CK(clk), .RN(
n8503), .Q(Op_MX[57]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n707), .CK(clk), .RN(
n8518), .Q(Op_MX[61]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n575), .CK(clk), .RN(n8529),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n572), .CK(clk), .RN(n8529),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n8529),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n8529),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n569), .CK(clk), .RN(n8528),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n568), .CK(clk), .RN(n8528),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n567), .CK(clk), .RN(n8528),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n566), .CK(clk), .RN(n8528),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n565), .CK(clk), .RN(n8528),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n564), .CK(clk), .RN(n8528),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n563), .CK(clk), .RN(n8528),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n8528),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n561), .CK(clk), .RN(n8528),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n560), .CK(clk), .RN(n8528),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n559), .CK(clk), .RN(n8527),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n558), .CK(clk), .RN(n8527),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n557), .CK(clk), .RN(n8527),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n556), .CK(clk), .RN(n8527),
.Q(Add_result[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n555), .CK(clk), .RN(n8527),
.Q(Add_result[24]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n554), .CK(clk), .RN(n8527),
.Q(Add_result[25]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n553), .CK(clk), .RN(n8527),
.Q(Add_result[26]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n552), .CK(clk), .RN(n8527),
.Q(Add_result[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n551), .CK(clk), .RN(n8527),
.Q(Add_result[28]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n540), .CK(clk), .RN(n8525),
.Q(Add_result[39]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n539), .CK(clk), .RN(n8525),
.Q(Add_result[40]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n538), .CK(clk), .RN(n8525),
.Q(Add_result[41]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n537), .CK(clk), .RN(n8525),
.Q(Add_result[42]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n708), .CK(clk), .RN(
n8518), .Q(Op_MX[62]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n698), .CK(clk), .RN(
n8519), .Q(Op_MX[52]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n639), .CK(clk), .RN(
n8530), .Q(Op_MY[57]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n643), .CK(clk), .RN(
n8530), .Q(Op_MY[61]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_104_ ( .D(n520), .CK(clk), .RN(
n8502), .Q(P_Sgf[104]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_91_ ( .D(n512), .CK(clk), .RN(
n8501), .Q(P_Sgf[91]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n644), .CK(clk), .RN(
n8530), .Q(Op_MY[62]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n635), .CK(clk), .RN(
n8531), .Q(Op_MY[53]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_53_ ( .D(n474), .CK(clk), .RN(
n8497), .Q(P_Sgf[53]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_55_ ( .D(n476), .CK(clk), .RN(
n8497), .Q(P_Sgf[55]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_58_ ( .D(n479), .CK(clk), .RN(
n8498), .Q(P_Sgf[58]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_59_ ( .D(n480), .CK(clk), .RN(
n8498), .Q(P_Sgf[59]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_60_ ( .D(n481), .CK(clk), .RN(
n8498), .Q(P_Sgf[60]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_61_ ( .D(n482), .CK(clk), .RN(
n8498), .Q(P_Sgf[61]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_62_ ( .D(n483), .CK(clk), .RN(
n8498), .Q(P_Sgf[62]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_63_ ( .D(n484), .CK(clk), .RN(
n8498), .Q(P_Sgf[63]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_64_ ( .D(n485), .CK(clk), .RN(
n8498), .Q(P_Sgf[64]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_65_ ( .D(n486), .CK(clk), .RN(
n8498), .Q(P_Sgf[65]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_66_ ( .D(n487), .CK(clk), .RN(
n8499), .Q(P_Sgf[66]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_67_ ( .D(n488), .CK(clk), .RN(
n8499), .Q(P_Sgf[67]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_68_ ( .D(n489), .CK(clk), .RN(
n8499), .Q(P_Sgf[68]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_69_ ( .D(n490), .CK(clk), .RN(
n8499), .Q(P_Sgf[69]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_70_ ( .D(n491), .CK(clk), .RN(
n8499), .Q(P_Sgf[70]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_71_ ( .D(n492), .CK(clk), .RN(
n8499), .Q(P_Sgf[71]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_72_ ( .D(n493), .CK(clk), .RN(
n8499), .Q(P_Sgf[72]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_73_ ( .D(n494), .CK(clk), .RN(
n8499), .Q(P_Sgf[73]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_74_ ( .D(n495), .CK(clk), .RN(
n8499), .Q(P_Sgf[74]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_75_ ( .D(n496), .CK(clk), .RN(
n8499), .Q(P_Sgf[75]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_76_ ( .D(n497), .CK(clk), .RN(
n8500), .Q(P_Sgf[76]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_77_ ( .D(n498), .CK(clk), .RN(
n8500), .Q(P_Sgf[77]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_78_ ( .D(n499), .CK(clk), .RN(
n8500), .Q(P_Sgf[78]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_79_ ( .D(n500), .CK(clk), .RN(
n8500), .Q(P_Sgf[79]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_80_ ( .D(n501), .CK(clk), .RN(
n8500), .Q(P_Sgf[80]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_81_ ( .D(n502), .CK(clk), .RN(
n8500), .Q(P_Sgf[81]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_82_ ( .D(n503), .CK(clk), .RN(
n8500), .Q(P_Sgf[82]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_83_ ( .D(n504), .CK(clk), .RN(
n8500), .Q(P_Sgf[83]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_84_ ( .D(n505), .CK(clk), .RN(
n8500), .Q(P_Sgf[84]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_85_ ( .D(n506), .CK(clk), .RN(
n8500), .Q(P_Sgf[85]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_86_ ( .D(n507), .CK(clk), .RN(
n8501), .Q(P_Sgf[86]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_87_ ( .D(n508), .CK(clk), .RN(
n8501), .Q(P_Sgf[87]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_88_ ( .D(n509), .CK(clk), .RN(
n8501), .Q(P_Sgf[88]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_89_ ( .D(n510), .CK(clk), .RN(
n8501), .Q(P_Sgf[89]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_90_ ( .D(n511), .CK(clk), .RN(
n8501), .Q(P_Sgf[90]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_92_ ( .D(n513), .CK(clk), .RN(
n8501), .Q(P_Sgf[92]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_93_ ( .D(n514), .CK(clk), .RN(
n8501), .Q(P_Sgf[93]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n352), .CK(clk), .RN(n8511),
.Q(underflow_flag), .QN(n8491) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n580), .CK(clk),
.RN(n8535), .Q(Sgf_normalized_result[52]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_0_ ( .D(n421), .CK(clk), .RN(
n8497), .Q(P_Sgf[0]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_4_ ( .D(n425), .CK(clk), .RN(
n8496), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_8_ ( .D(n429), .CK(clk), .RN(
n8496), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_12_ ( .D(n433), .CK(clk), .RN(
n8495), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_16_ ( .D(n437), .CK(clk), .RN(
n8495), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_20_ ( .D(n441), .CK(clk), .RN(
n8495), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_24_ ( .D(n445), .CK(clk), .RN(
n8494), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_28_ ( .D(n449), .CK(clk), .RN(
n8494), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_32_ ( .D(n453), .CK(clk), .RN(
n8493), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_36_ ( .D(n457), .CK(clk), .RN(
n8493), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_51_ ( .D(n472), .CK(clk), .RN(
n8492), .Q(P_Sgf[51]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_41_ ( .D(n462), .CK(clk), .RN(
n8492), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_47_ ( .D(n468), .CK(clk), .RN(
n8493), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n645), .CK(clk), .RN(
n8524), .Q(Op_MX[63]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n526), .CK(clk), .RN(
n8530), .Q(FSM_add_overflow_flag), .QN(n8453) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n701), .CK(clk), .RN(
n8519), .Q(Op_MX[55]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n699), .CK(clk), .RN(
n8519), .Q(Op_MX[53]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n527), .CK(clk), .RN(n8530),
.Q(Add_result[52]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n353), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_102_ ( .D(n524), .CK(clk), .RN(
n8502), .Q(P_Sgf[102]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_48_ ( .D(n469), .CK(clk), .RN(
n8492), .Q(P_Sgf[48]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_38_ ( .D(n459), .CK(clk), .RN(
n8493), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_34_ ( .D(n455), .CK(clk), .RN(
n8493), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_30_ ( .D(n451), .CK(clk), .RN(
n8494), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_26_ ( .D(n447), .CK(clk), .RN(
n8494), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_22_ ( .D(n443), .CK(clk), .RN(
n8494), .Q(P_Sgf[22]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_18_ ( .D(n439), .CK(clk), .RN(
n8495), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_14_ ( .D(n435), .CK(clk), .RN(
n8495), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_10_ ( .D(n431), .CK(clk), .RN(
n8496), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_6_ ( .D(n427), .CK(clk), .RN(
n8496), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_2_ ( .D(n423), .CK(clk), .RN(
n8496), .Q(P_Sgf[2]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_49_ ( .D(n470), .CK(clk), .RN(
n8492), .Q(P_Sgf[49]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_37_ ( .D(n458), .CK(clk), .RN(
n8493), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_33_ ( .D(n454), .CK(clk), .RN(
n8493), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_29_ ( .D(n450), .CK(clk), .RN(
n8494), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_25_ ( .D(n446), .CK(clk), .RN(
n8494), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_21_ ( .D(n442), .CK(clk), .RN(
n8495), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_17_ ( .D(n438), .CK(clk), .RN(
n8495), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_13_ ( .D(n434), .CK(clk), .RN(
n8495), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_9_ ( .D(n430), .CK(clk), .RN(
n8496), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_5_ ( .D(n426), .CK(clk), .RN(
n8496), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_1_ ( .D(n422), .CK(clk), .RN(
n8497), .Q(P_Sgf[1]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_50_ ( .D(n471), .CK(clk), .RN(
n8492), .Q(P_Sgf[50]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_39_ ( .D(n460), .CK(clk), .RN(
n8493), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_35_ ( .D(n456), .CK(clk), .RN(
n8493), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_31_ ( .D(n452), .CK(clk), .RN(
n8494), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_27_ ( .D(n448), .CK(clk), .RN(
n8494), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_23_ ( .D(n444), .CK(clk), .RN(
n8494), .Q(P_Sgf[23]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_19_ ( .D(n440), .CK(clk), .RN(
n8495), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_15_ ( .D(n436), .CK(clk), .RN(
n8495), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_11_ ( .D(n432), .CK(clk), .RN(
n8496), .Q(P_Sgf[11]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_7_ ( .D(n428), .CK(clk), .RN(
n8496), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_3_ ( .D(n424), .CK(clk), .RN(
n8496), .Q(P_Sgf[3]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_46_ ( .D(n467), .CK(clk), .RN(
n8493), .Q(P_Sgf[46]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_43_ ( .D(n464), .CK(clk), .RN(
n8492), .Q(P_Sgf[43]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_45_ ( .D(n466), .CK(clk), .RN(
n8492), .Q(P_Sgf[45]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_42_ ( .D(n463), .CK(clk), .RN(
n8492), .Q(P_Sgf[42]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_44_ ( .D(n465), .CK(clk), .RN(
n8492), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_40_ ( .D(n461), .CK(clk), .RN(
n8492), .Q(P_Sgf[40]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n705), .CK(clk), .RN(
n8518), .Q(Op_MX[59]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n706), .CK(clk), .RN(
n8518), .Q(Op_MX[60]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n702), .CK(clk), .RN(
n8526), .Q(Op_MX[56]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n704), .CK(clk), .RN(
n8518), .Q(Op_MX[58]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n700), .CK(clk), .RN(
n8519), .Q(Op_MX[54]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n528), .CK(clk), .RN(n8524),
.Q(Add_result[51]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n529), .CK(clk), .RN(n8524),
.Q(Add_result[50]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n530), .CK(clk), .RN(n8524),
.Q(Add_result[49]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n576), .CK(clk), .RN(n8529),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n574), .CK(clk), .RN(n8529),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n573), .CK(clk), .RN(n8529),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n550), .CK(clk), .RN(n8527),
.Q(Add_result[29]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n549), .CK(clk), .RN(n8526),
.Q(Add_result[30]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n548), .CK(clk), .RN(n8526),
.Q(Add_result[31]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n547), .CK(clk), .RN(n8526),
.Q(Add_result[32]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n546), .CK(clk), .RN(n8526),
.Q(Add_result[33]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n531), .CK(clk), .RN(n8525),
.Q(Add_result[48]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n532), .CK(clk), .RN(n8525),
.Q(Add_result[47]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n533), .CK(clk), .RN(n8525),
.Q(Add_result[46]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n534), .CK(clk), .RN(n8525),
.Q(Add_result[45]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n535), .CK(clk), .RN(n8525),
.Q(Add_result[44]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n536), .CK(clk), .RN(n8525),
.Q(Add_result[43]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n541), .CK(clk), .RN(n8526),
.Q(Add_result[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n542), .CK(clk), .RN(n8526),
.Q(Add_result[37]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n543), .CK(clk), .RN(n8526),
.Q(Add_result[36]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n544), .CK(clk), .RN(n8526),
.Q(Add_result[35]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n545), .CK(clk), .RN(n8526),
.Q(Add_result[34]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n577), .CK(clk), .RN(n8529),
.Q(Add_result[2]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n641), .CK(clk), .RN(
n8530), .Q(Op_MY[59]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n637), .CK(clk), .RN(
n8530), .Q(Op_MY[55]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n417), .CK(clk), .RN(n7462),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n416), .CK(clk), .RN(n8506),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n415), .CK(clk), .RN(n7465),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n414), .CK(clk), .RN(n7461),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n413), .CK(clk), .RN(n7463),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n412), .CK(clk), .RN(n8505),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n411), .CK(clk), .RN(n7462),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n410), .CK(clk), .RN(n8506),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n409), .CK(clk), .RN(n8505),
.Q(exp_oper_result[8]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_9_ ( .D(n408), .CK(clk), .RN(n8506),
.Q(exp_oper_result[9]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n407), .CK(clk), .RN(n8505),
.Q(exp_oper_result[10]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n642), .CK(clk), .RN(
n8530), .Q(Op_MY[60]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n638), .CK(clk), .RN(
n8530), .Q(Op_MY[56]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n8529),
.Q(Add_result[1]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n640), .CK(clk), .RN(
n8530), .Q(Op_MY[58]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n636), .CK(clk), .RN(
n8531), .Q(Op_MY[54]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n354), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n406), .CK(clk), .RN(n8506),
.Q(exp_oper_result[11]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_103_ ( .D(n525), .CK(clk), .RN(
n8502), .Q(P_Sgf[103]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_101_ ( .D(n523), .CK(clk), .RN(
n8502), .Q(P_Sgf[101]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_100_ ( .D(n522), .CK(clk), .RN(
n8502), .Q(P_Sgf[100]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_99_ ( .D(n521), .CK(clk), .RN(
n8502), .Q(P_Sgf[99]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_98_ ( .D(n519), .CK(clk), .RN(
n8502), .Q(P_Sgf[98]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_97_ ( .D(n518), .CK(clk), .RN(
n8502), .Q(P_Sgf[97]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_96_ ( .D(n517), .CK(clk), .RN(
n8502), .Q(P_Sgf[96]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_95_ ( .D(n516), .CK(clk), .RN(
n8501), .Q(P_Sgf[95]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_94_ ( .D(n515), .CK(clk), .RN(
n8501), .Q(P_Sgf[94]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_57_ ( .D(n478), .CK(clk), .RN(
n8498), .Q(P_Sgf[57]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_56_ ( .D(n477), .CK(clk), .RN(
n8498), .Q(P_Sgf[56]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_54_ ( .D(n475), .CK(clk), .RN(
n8497), .Q(P_Sgf[54]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_51_ ( .D(n633), .CK(clk), .RN(
n8531), .Q(Op_MY[51]), .QN(n1031) );
DFFQX1TS Sgf_operation_ODD1_left_Data_S_o_reg_0_ ( .D(
Sgf_operation_ODD1_left_N0), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[0]) );
DFFQX1TS Sgf_operation_ODD1_left_Data_S_o_reg_1_ ( .D(
Sgf_operation_ODD1_left_N1), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[1]) );
DFFHQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_5_ ( .D(
Sgf_operation_ODD1_left_N5), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[5]) );
DFFHQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_13_ ( .D(
Sgf_operation_ODD1_left_N13), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[13]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_5_ ( .D(
Sgf_operation_ODD1_right_N5), .CK(clk), .Q(Sgf_operation_Result[5]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_6_ ( .D(
Sgf_operation_ODD1_right_N6), .CK(clk), .Q(Sgf_operation_Result[6]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_11_ ( .D(
Sgf_operation_ODD1_right_N11), .CK(clk), .Q(Sgf_operation_Result[11])
);
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_12_ ( .D(
Sgf_operation_ODD1_right_N12), .CK(clk), .Q(Sgf_operation_Result[12])
);
DFFHQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_15_ ( .D(
Sgf_operation_ODD1_right_N15), .CK(clk), .Q(Sgf_operation_Result[15])
);
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_17_ ( .D(
Sgf_operation_ODD1_right_N17), .CK(clk), .Q(Sgf_operation_Result[17])
);
DFFHQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_20_ ( .D(
Sgf_operation_ODD1_right_N20), .CK(clk), .Q(Sgf_operation_Result[20])
);
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_30_ ( .D(
Sgf_operation_ODD1_right_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[30]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_31_ ( .D(
Sgf_operation_ODD1_right_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[31]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_33_ ( .D(
Sgf_operation_ODD1_right_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[33]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_34_ ( .D(
Sgf_operation_ODD1_right_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[34]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_42_ ( .D(
Sgf_operation_ODD1_right_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[42]) );
DFFQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_52_ ( .D(
Sgf_operation_ODD1_right_N52), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[52]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_0_ ( .D(
Sgf_operation_ODD1_middle_N0), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[0]) );
DFFHQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_5_ ( .D(
Sgf_operation_ODD1_middle_N5), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[5]) );
DFFHQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_8_ ( .D(
Sgf_operation_ODD1_middle_N8), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[8]) );
DFFHQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_13_ ( .D(
Sgf_operation_ODD1_middle_N13), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[13]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_28_ ( .D(
Sgf_operation_ODD1_middle_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[28]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_31_ ( .D(
Sgf_operation_ODD1_middle_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[31]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_33_ ( .D(
Sgf_operation_ODD1_middle_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[33]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_34_ ( .D(
Sgf_operation_ODD1_middle_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[34]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_43_ ( .D(
Sgf_operation_ODD1_middle_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[43]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n711), .CK(clk), .RN(n8502), .Q(
FS_Module_state_reg[2]), .QN(n8447) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n713), .CK(clk), .RN(n8497), .Q(
FS_Module_state_reg[0]), .QN(n8446) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_46_ ( .D(
Sgf_operation_ODD1_middle_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[46]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_47_ ( .D(
Sgf_operation_ODD1_middle_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[47]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_50_ ( .D(
Sgf_operation_ODD1_middle_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[50]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n634), .CK(clk), .RN(
n8531), .Q(Op_MY[52]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_40_ ( .D(
Sgf_operation_ODD1_middle_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[40]) );
ADDFHX2TS DP_OP_36J24_124_1029_U6 ( .A(DP_OP_36J24_124_1029_n21), .B(
S_Oper_A_exp[7]), .CI(DP_OP_36J24_124_1029_n6), .CO(
DP_OP_36J24_124_1029_n5), .S(Exp_module_Data_S[7]) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_32_ ( .D(n614), .CK(clk), .RN(
n8534), .Q(n755) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n673), .CK(clk), .RN(
n8521), .Q(Op_MX[27]), .QN(n1006) );
DFFHQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_6_ ( .D(
Sgf_operation_ODD1_left_N6), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[6]) );
DFFQX2TS Sgf_operation_ODD1_middle_Data_S_o_reg_48_ ( .D(
Sgf_operation_ODD1_middle_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[48]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_17_ ( .D(
Sgf_operation_ODD1_left_N17), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[17]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_26_ ( .D(
Sgf_operation_ODD1_left_N26), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[26]) );
ADDFHX2TS DP_OP_36J24_124_1029_U12 ( .A(DP_OP_36J24_124_1029_n27), .B(
S_Oper_A_exp[1]), .CI(DP_OP_36J24_124_1029_n12), .CO(
DP_OP_36J24_124_1029_n11), .S(Exp_module_Data_S[1]) );
ADDFHX2TS DP_OP_36J24_124_1029_U11 ( .A(DP_OP_36J24_124_1029_n26), .B(
S_Oper_A_exp[2]), .CI(DP_OP_36J24_124_1029_n11), .CO(
DP_OP_36J24_124_1029_n10), .S(Exp_module_Data_S[2]) );
ADDFHX2TS DP_OP_36J24_124_1029_U8 ( .A(DP_OP_36J24_124_1029_n23), .B(
S_Oper_A_exp[5]), .CI(DP_OP_36J24_124_1029_n8), .CO(
DP_OP_36J24_124_1029_n7), .S(Exp_module_Data_S[5]) );
ADDFHX2TS DP_OP_36J24_124_1029_U7 ( .A(DP_OP_36J24_124_1029_n22), .B(
S_Oper_A_exp[6]), .CI(DP_OP_36J24_124_1029_n7), .CO(
DP_OP_36J24_124_1029_n6), .S(Exp_module_Data_S[6]) );
ADDFHX2TS DP_OP_36J24_124_1029_U5 ( .A(DP_OP_36J24_124_1029_n20), .B(
S_Oper_A_exp[8]), .CI(DP_OP_36J24_124_1029_n5), .CO(
DP_OP_36J24_124_1029_n4), .S(Exp_module_Data_S[8]) );
ADDFHX2TS DP_OP_36J24_124_1029_U4 ( .A(DP_OP_36J24_124_1029_n19), .B(
S_Oper_A_exp[9]), .CI(DP_OP_36J24_124_1029_n4), .CO(
DP_OP_36J24_124_1029_n3), .S(Exp_module_Data_S[9]) );
DFFHQX1TS Sgf_operation_ODD1_left_Data_S_o_reg_37_ ( .D(
Sgf_operation_ODD1_left_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[37]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_38_ ( .D(
Sgf_operation_ODD1_middle_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[38]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_7_ ( .D(
Sgf_operation_ODD1_left_N7), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[7]) );
DFFQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_28_ ( .D(
Sgf_operation_ODD1_right_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[28]) );
DFFQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_7_ ( .D(
Sgf_operation_ODD1_middle_N7), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[7]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_23_ ( .D(
Sgf_operation_ODD1_middle_N23), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[23]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_20_ ( .D(
Sgf_operation_ODD1_left_N20), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[20]) );
DFFQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_9_ ( .D(
Sgf_operation_ODD1_left_N9), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[9]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_12_ ( .D(
Sgf_operation_ODD1_left_N12), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[12]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_2_ ( .D(
Sgf_operation_ODD1_left_N2), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[2]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_3_ ( .D(
Sgf_operation_ODD1_left_N3), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[3]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_11_ ( .D(
Sgf_operation_ODD1_left_N11), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[11]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_24_ ( .D(
Sgf_operation_ODD1_left_N24), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[24]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_25_ ( .D(
Sgf_operation_ODD1_left_N25), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[25]) );
DFFHQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_26_ ( .D(
Sgf_operation_ODD1_right_N26), .CK(clk), .Q(Sgf_operation_Result[26])
);
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_1_ ( .D(
Sgf_operation_ODD1_right_N1), .CK(clk), .Q(Sgf_operation_Result[1]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_3_ ( .D(
Sgf_operation_ODD1_right_N3), .CK(clk), .Q(Sgf_operation_Result[3]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_4_ ( .D(
Sgf_operation_ODD1_right_N4), .CK(clk), .Q(Sgf_operation_Result[4]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_10_ ( .D(
Sgf_operation_ODD1_right_N10), .CK(clk), .Q(Sgf_operation_Result[10])
);
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_8_ ( .D(
Sgf_operation_ODD1_right_N8), .CK(clk), .Q(Sgf_operation_Result[8]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_13_ ( .D(
Sgf_operation_ODD1_right_N13), .CK(clk), .Q(Sgf_operation_Result[13])
);
DFFHQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_8_ ( .D(
Sgf_operation_ODD1_left_N8), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[8]) );
DFFHQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_27_ ( .D(
Sgf_operation_ODD1_left_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[27]) );
DFFHQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_29_ ( .D(
Sgf_operation_ODD1_left_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[29]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_16_ ( .D(
Sgf_operation_ODD1_right_N16), .CK(clk), .Q(Sgf_operation_Result[16])
);
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_19_ ( .D(
Sgf_operation_ODD1_right_N19), .CK(clk), .Q(Sgf_operation_Result[19])
);
DFFQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_9_ ( .D(
Sgf_operation_ODD1_right_N9), .CK(clk), .Q(Sgf_operation_Result[9]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_4_ ( .D(
Sgf_operation_ODD1_left_N4), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[4]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_18_ ( .D(
Sgf_operation_ODD1_right_N18), .CK(clk), .Q(Sgf_operation_Result[18])
);
DFFQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_16_ ( .D(
Sgf_operation_ODD1_left_N16), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[16]) );
DFFQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_19_ ( .D(
Sgf_operation_ODD1_left_N19), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[19]) );
DFFQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_14_ ( .D(
Sgf_operation_ODD1_left_N14), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[14]) );
DFFQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_18_ ( .D(
Sgf_operation_ODD1_left_N18), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[18]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_14_ ( .D(
Sgf_operation_ODD1_right_N14), .CK(clk), .Q(Sgf_operation_Result[14])
);
DFFHQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_25_ ( .D(
Sgf_operation_ODD1_right_N25), .CK(clk), .Q(Sgf_operation_Result[25])
);
DFFHQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_2_ ( .D(
Sgf_operation_ODD1_right_N2), .CK(clk), .Q(Sgf_operation_Result[2]) );
DFFHQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_7_ ( .D(
Sgf_operation_ODD1_right_N7), .CK(clk), .Q(Sgf_operation_Result[7]) );
DFFHQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_21_ ( .D(
Sgf_operation_ODD1_right_N21), .CK(clk), .Q(Sgf_operation_Result[21])
);
DFFHQX1TS Sgf_operation_ODD1_right_Data_S_o_reg_22_ ( .D(
Sgf_operation_ODD1_right_N22), .CK(clk), .Q(Sgf_operation_Result[22])
);
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_15_ ( .D(
Sgf_operation_ODD1_left_N15), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[15]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_10_ ( .D(
Sgf_operation_ODD1_left_N10), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[10]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_21_ ( .D(
Sgf_operation_ODD1_left_N21), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[21]) );
DFFQX4TS Sgf_operation_ODD1_left_Data_S_o_reg_23_ ( .D(
Sgf_operation_ODD1_left_N23), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[23]) );
DFFQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_27_ ( .D(
Sgf_operation_ODD1_right_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[27]) );
DFFQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_29_ ( .D(
Sgf_operation_ODD1_right_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[29]) );
DFFQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_23_ ( .D(
Sgf_operation_ODD1_right_N23), .CK(clk), .Q(Sgf_operation_Result[23])
);
DFFQX4TS Sgf_operation_ODD1_right_Data_S_o_reg_24_ ( .D(
Sgf_operation_ODD1_right_N24), .CK(clk), .Q(Sgf_operation_Result[24])
);
DFFQX1TS Sgf_operation_ODD1_left_Data_S_o_reg_40_ ( .D(
Sgf_operation_ODD1_left_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[40]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_41_ ( .D(
Sgf_operation_ODD1_right_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[41]) );
DFFQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_47_ ( .D(
Sgf_operation_ODD1_left_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[47]) );
DFFHQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_36_ ( .D(
Sgf_operation_ODD1_right_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[36]) );
DFFHQX2TS Sgf_operation_ODD1_left_Data_S_o_reg_38_ ( .D(
Sgf_operation_ODD1_left_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[38]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_21_ ( .D(
Sgf_operation_ODD1_middle_N21), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[21]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_22_ ( .D(
Sgf_operation_ODD1_middle_N22), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[22]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_16_ ( .D(
Sgf_operation_ODD1_middle_N16), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[16]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_10_ ( .D(
Sgf_operation_ODD1_middle_N10), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[10]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_20_ ( .D(
Sgf_operation_ODD1_middle_N20), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[20]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_24_ ( .D(
Sgf_operation_ODD1_middle_N24), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[24]) );
DFFHQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_1_ ( .D(
Sgf_operation_ODD1_middle_N1), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[1]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_29_ ( .D(
Sgf_operation_ODD1_middle_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[29]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_30_ ( .D(
Sgf_operation_ODD1_middle_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[30]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_25_ ( .D(
Sgf_operation_ODD1_middle_N25), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[25]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_26_ ( .D(
Sgf_operation_ODD1_middle_N26), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[26]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_15_ ( .D(
Sgf_operation_ODD1_middle_N15), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[15]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_19_ ( .D(
Sgf_operation_ODD1_middle_N19), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[19]) );
DFFHQX1TS Sgf_operation_ODD1_left_Data_S_o_reg_36_ ( .D(
Sgf_operation_ODD1_left_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[36]) );
DFFQX2TS Sgf_operation_ODD1_middle_Data_S_o_reg_27_ ( .D(
Sgf_operation_ODD1_middle_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[27]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_9_ ( .D(
Sgf_operation_ODD1_middle_N9), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[9]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_14_ ( .D(
Sgf_operation_ODD1_middle_N14), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[14]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_18_ ( .D(
Sgf_operation_ODD1_middle_N18), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[18]) );
DFFQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_2_ ( .D(
Sgf_operation_ODD1_middle_N2), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[2]) );
DFFQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_3_ ( .D(
Sgf_operation_ODD1_middle_N3), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[3]) );
DFFQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_4_ ( .D(
Sgf_operation_ODD1_middle_N4), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[4]) );
DFFQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_6_ ( .D(
Sgf_operation_ODD1_middle_N6), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[6]) );
DFFQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_11_ ( .D(
Sgf_operation_ODD1_middle_N11), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[11]) );
DFFQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_12_ ( .D(
Sgf_operation_ODD1_middle_N12), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[12]) );
DFFQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_17_ ( .D(
Sgf_operation_ODD1_middle_N17), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[17]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_39_ ( .D(
Sgf_operation_ODD1_right_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[39]) );
DFFQX2TS Sgf_operation_ODD1_right_Data_S_o_reg_40_ ( .D(
Sgf_operation_ODD1_right_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[40]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_36_ ( .D(
Sgf_operation_ODD1_middle_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[36]) );
DFFHQX4TS Sgf_operation_ODD1_middle_Data_S_o_reg_39_ ( .D(
Sgf_operation_ODD1_middle_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[39]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_35_ ( .D(
Sgf_operation_ODD1_middle_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[35]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_44_ ( .D(
Sgf_operation_ODD1_middle_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[44]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_37_ ( .D(
Sgf_operation_ODD1_middle_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[37]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_41_ ( .D(
Sgf_operation_ODD1_middle_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[41]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_45_ ( .D(
Sgf_operation_ODD1_middle_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[45]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_42_ ( .D(
Sgf_operation_ODD1_middle_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[42]) );
DFFQX1TS Sgf_operation_ODD1_left_Data_S_o_reg_48_ ( .D(
Sgf_operation_ODD1_left_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[48]) );
DFFQX1TS Sgf_operation_ODD1_middle_Data_S_o_reg_49_ ( .D(
Sgf_operation_ODD1_middle_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[49]) );
CMPR42X1TS mult_x_23_U756 ( .A(mult_x_23_n1310), .B(mult_x_23_n832), .C(
mult_x_23_n1362), .D(mult_x_23_n1336), .ICI(mult_x_23_n1388), .S(
mult_x_23_n830), .ICO(mult_x_23_n828), .CO(mult_x_23_n829) );
CMPR32X2TS DP_OP_36J24_124_1029_U13 ( .A(S_Oper_A_exp[0]), .B(n904), .C(
DP_OP_36J24_124_1029_n28), .CO(DP_OP_36J24_124_1029_n12), .S(
Exp_module_Data_S[0]) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n714), .CK(clk), .RN(n8497), .Q(
FS_Module_state_reg[3]), .QN(n8470) );
CMPR32X2TS DP_OP_36J24_124_1029_U3 ( .A(DP_OP_36J24_124_1029_n18), .B(
S_Oper_A_exp[10]), .C(DP_OP_36J24_124_1029_n3), .CO(
DP_OP_36J24_124_1029_n2), .S(Exp_module_Data_S[10]) );
CLKMX2X2TS U746 ( .A(P_Sgf[61]), .B(n8068), .S0(n8133), .Y(n482) );
XNOR2X2TS U747 ( .A(n5169), .B(n5168), .Y(Sgf_operation_ODD1_left_N43) );
XNOR2X2TS U748 ( .A(n4775), .B(n4774), .Y(Sgf_operation_ODD1_left_N32) );
XNOR2X1TS U749 ( .A(n5236), .B(n5235), .Y(Sgf_operation_ODD1_right_N31) );
XNOR2X2TS U750 ( .A(n4861), .B(n4860), .Y(Sgf_operation_ODD1_left_N36) );
XNOR2X2TS U751 ( .A(n7334), .B(n7333), .Y(Sgf_operation_ODD1_middle_N42) );
XNOR2X2TS U752 ( .A(n7243), .B(n7242), .Y(Sgf_operation_ODD1_middle_N37) );
XNOR2X2TS U753 ( .A(n7304), .B(n7303), .Y(Sgf_operation_ODD1_middle_N51) );
XNOR2X2TS U754 ( .A(n7342), .B(n7341), .Y(Sgf_operation_ODD1_middle_N38) );
XNOR2X2TS U755 ( .A(n7414), .B(n7413), .Y(Sgf_operation_ODD1_middle_N41) );
XOR2X2TS U756 ( .A(n816), .B(n6734), .Y(Sgf_operation_ODD1_right_N42) );
XOR2X2TS U757 ( .A(n4893), .B(n6091), .Y(Sgf_operation_ODD1_right_N30) );
BUFX3TS U758 ( .A(n8189), .Y(n8133) );
BUFX3TS U759 ( .A(n8189), .Y(n8188) );
BUFX3TS U760 ( .A(n8189), .Y(n8190) );
BUFX3TS U761 ( .A(n8189), .Y(n8224) );
BUFX3TS U762 ( .A(n8189), .Y(n8293) );
BUFX3TS U763 ( .A(n8189), .Y(n7712) );
BUFX3TS U764 ( .A(n8189), .Y(n7988) );
BUFX3TS U765 ( .A(n8189), .Y(n7850) );
BUFX3TS U766 ( .A(n8191), .Y(n8192) );
INVX2TS U767 ( .A(n8443), .Y(n8434) );
INVX2TS U768 ( .A(n8443), .Y(n8363) );
INVX2TS U769 ( .A(n8443), .Y(n8361) );
INVX2TS U770 ( .A(n8443), .Y(n8436) );
INVX2TS U771 ( .A(n8440), .Y(n8435) );
INVX2TS U772 ( .A(n8440), .Y(n8437) );
INVX2TS U773 ( .A(n8442), .Y(n8439) );
INVX2TS U774 ( .A(n8442), .Y(n8360) );
INVX2TS U775 ( .A(n8442), .Y(n8362) );
INVX2TS U776 ( .A(n8355), .Y(n941) );
INVX2TS U777 ( .A(n8355), .Y(n942) );
XOR2X1TS U778 ( .A(n7693), .B(n7692), .Y(n7694) );
XOR2X2TS U779 ( .A(n7512), .B(n7511), .Y(n7513) );
XOR2X2TS U780 ( .A(n7657), .B(n7656), .Y(n7658) );
XOR2X2TS U781 ( .A(n7711), .B(n7710), .Y(n7713) );
AOI21X1TS U782 ( .A0(n7108), .A1(n6097), .B0(n6096), .Y(n6102) );
XOR2X2TS U783 ( .A(n7604), .B(n7603), .Y(n7605) );
XOR2X2TS U784 ( .A(n7623), .B(n7622), .Y(n7624) );
XOR2X2TS U785 ( .A(n7632), .B(n7631), .Y(n7633) );
XOR2X2TS U786 ( .A(n7613), .B(n7612), .Y(n7614) );
XOR2X2TS U787 ( .A(n7725), .B(n7724), .Y(n7726) );
NAND2X1TS U788 ( .A(n4879), .B(n5221), .Y(n4881) );
NAND2X1TS U789 ( .A(n7354), .B(n7352), .Y(n7247) );
NAND2X1TS U790 ( .A(n5256), .B(n5258), .Y(n5261) );
INVX2TS U791 ( .A(n5316), .Y(n5331) );
INVX2TS U792 ( .A(n6146), .Y(n6163) );
INVX2TS U793 ( .A(n5332), .Y(n5989) );
BUFX3TS U794 ( .A(n8189), .Y(n8191) );
INVX2TS U795 ( .A(n897), .Y(n7274) );
NOR2X1TS U796 ( .A(n7095), .B(n7097), .Y(n7100) );
NOR2XLTS U797 ( .A(n7257), .B(n7437), .Y(n7261) );
NAND2XLTS U798 ( .A(n7335), .B(n7340), .Y(n3912) );
NAND2XLTS U799 ( .A(n7373), .B(n7376), .Y(n7378) );
AOI21X2TS U800 ( .A0(n7325), .A1(n4828), .B0(n4827), .Y(n4829) );
NAND2X1TS U801 ( .A(n7417), .B(n7407), .Y(n7409) );
CLKAND2X2TS U802 ( .A(n7323), .B(n4694), .Y(n745) );
NAND2X2TS U803 ( .A(n7323), .B(n3925), .Y(n3927) );
AOI21X2TS U804 ( .A0(n7427), .A1(n7426), .B0(n7425), .Y(n7428) );
AOI21X2TS U805 ( .A0(n7849), .A1(n7847), .B0(n7834), .Y(n7839) );
AOI21X2TS U806 ( .A0(n5225), .A1(n4879), .B0(n4878), .Y(n4880) );
NAND2X2TS U807 ( .A(n7323), .B(n771), .Y(n7327) );
NAND2X2TS U808 ( .A(n1021), .B(n7323), .Y(n3578) );
AOI21X2TS U809 ( .A0(n5174), .A1(n5173), .B0(n5172), .Y(n5175) );
AOI21X2TS U810 ( .A0(n7908), .A1(n7906), .B0(n7892), .Y(n7897) );
OAI21X1TS U811 ( .A0(n8032), .A1(n8046), .B0(n8047), .Y(n8037) );
OAI21X1TS U812 ( .A0(n762), .A1(n5300), .B0(n5301), .Y(n5291) );
BUFX3TS U813 ( .A(n8440), .Y(n8442) );
OAI21X1TS U814 ( .A0(n8080), .A1(n8076), .B0(n8077), .Y(n8067) );
AOI21X1TS U815 ( .A0(n7427), .A1(n7407), .B0(n7406), .Y(n7408) );
AOI21X1TS U816 ( .A0(n7336), .A1(n7340), .B0(n3910), .Y(n3911) );
INVX2TS U817 ( .A(n7244), .Y(n7360) );
NOR2X1TS U818 ( .A(n7315), .B(n4692), .Y(n4694) );
INVX2TS U819 ( .A(n7803), .Y(n7819) );
INVX2TS U820 ( .A(n3908), .Y(n7340) );
INVX2TS U821 ( .A(n5109), .Y(n7407) );
CLKBUFX2TS U822 ( .A(n3909), .Y(n7336) );
INVX8TS U823 ( .A(n7123), .Y(n7379) );
INVX2TS U824 ( .A(n7278), .Y(n7289) );
NAND2X1TS U825 ( .A(n4921), .B(n3901), .Y(n3903) );
INVX2TS U826 ( .A(n7254), .Y(n7376) );
BUFX3TS U827 ( .A(n8189), .Y(n8354) );
INVX2TS U828 ( .A(n7330), .Y(n7417) );
INVX2TS U829 ( .A(n7287), .Y(n7354) );
NOR2X2TS U830 ( .A(n4885), .B(n4877), .Y(n4879) );
OAI21X2TS U831 ( .A0(n7357), .A1(n7356), .B0(n7355), .Y(n7358) );
NOR2X2TS U832 ( .A(n7353), .B(n7356), .Y(n7359) );
NAND2X2TS U833 ( .A(n7733), .B(n7701), .Y(n7711) );
AND2X2TS U834 ( .A(n7489), .B(n8470), .Y(n8365) );
OAI21X1TS U835 ( .A0(n4777), .A1(n4793), .B0(n4794), .Y(n4778) );
INVX2TS U836 ( .A(n7473), .Y(n8433) );
OR3X2TS U837 ( .A(n8364), .B(underflow_flag), .C(overflow_flag), .Y(n8440)
);
INVX6TS U838 ( .A(n4821), .Y(n7292) );
NOR2X1TS U839 ( .A(n5111), .B(n5117), .Y(n5120) );
NAND2X1TS U840 ( .A(n7544), .B(n7547), .Y(n7546) );
AOI21X1TS U841 ( .A0(n4950), .A1(n4938), .B0(n4937), .Y(n4939) );
NAND2X2TS U842 ( .A(n3917), .B(n3556), .Y(n3575) );
INVX2TS U843 ( .A(n8443), .Y(n8364) );
NAND2X1TS U844 ( .A(n3897), .B(n3896), .Y(n4962) );
NAND2XLTS U845 ( .A(n7535), .B(FSM_add_overflow_flag), .Y(n4649) );
INVX4TS U846 ( .A(n7544), .Y(n8070) );
NOR3X2TS U847 ( .A(n8446), .B(FS_Module_state_reg[2]), .C(n7535), .Y(n7489)
);
NOR2X2TS U848 ( .A(n7294), .B(n7300), .Y(n4824) );
AND2X4TS U849 ( .A(FS_Module_state_reg[3]), .B(n7469), .Y(n8443) );
NOR2X1TS U850 ( .A(n7813), .B(n7720), .Y(n7741) );
NOR2X1TS U851 ( .A(n7928), .B(n7825), .Y(n7855) );
OAI21X1TS U852 ( .A0(n4936), .A1(n4935), .B0(n4934), .Y(n4937) );
OR2X2TS U853 ( .A(mult_x_24_n698), .B(mult_x_24_n701), .Y(n5023) );
NAND2X4TS U854 ( .A(n7352), .B(n2931), .Y(n2933) );
INVX2TS U855 ( .A(n8261), .Y(n8305) );
CLKINVX1TS U856 ( .A(n8369), .Y(n7469) );
NOR2X2TS U857 ( .A(n1288), .B(n1298), .Y(n1301) );
AND2X2TS U858 ( .A(n7482), .B(n7535), .Y(n7544) );
NAND2X1TS U859 ( .A(mult_x_24_n723), .B(mult_x_24_n728), .Y(n1277) );
NAND2X1TS U860 ( .A(mult_x_24_n717), .B(mult_x_24_n722), .Y(n1297) );
NOR2X4TS U861 ( .A(n3516), .B(n3515), .Y(n7238) );
NOR2X2TS U862 ( .A(mult_x_24_n717), .B(mult_x_24_n722), .Y(n1288) );
NAND2X2TS U863 ( .A(mult_x_23_n747), .B(mult_x_23_n757), .Y(n4899) );
NAND2X2TS U864 ( .A(mult_x_23_n758), .B(mult_x_23_n768), .Y(n4913) );
NAND2X2TS U865 ( .A(mult_x_23_n726), .B(mult_x_23_n736), .Y(n4794) );
NAND2X2TS U866 ( .A(mult_x_23_n718), .B(mult_x_23_n725), .Y(n4783) );
NOR2X1TS U867 ( .A(mult_x_24_n723), .B(mult_x_24_n728), .Y(n1275) );
CLKINVX3TS U868 ( .A(n5062), .Y(n4635) );
INVX2TS U869 ( .A(n5148), .Y(n3883) );
NAND2XLTS U870 ( .A(n7534), .B(n7481), .Y(n7482) );
NAND3X2TS U871 ( .A(FS_Module_state_reg[0]), .B(n7535), .C(n8447), .Y(n8369)
);
NOR2X6TS U872 ( .A(n7437), .B(n7262), .Y(n2453) );
OAI21X2TS U873 ( .A0(n3537), .A1(n7418), .B0(n3536), .Y(n3538) );
NOR2X1TS U874 ( .A(n7928), .B(n7718), .Y(n7800) );
NOR2X2TS U875 ( .A(n5217), .B(n5244), .Y(n1186) );
NOR2X6TS U876 ( .A(n5109), .B(n7410), .Y(n7343) );
NOR2X6TS U877 ( .A(n7128), .B(n7269), .Y(n7435) );
NOR2X4TS U878 ( .A(n7254), .B(n7380), .Y(n2921) );
NOR2X4TS U879 ( .A(n3908), .B(n3913), .Y(n3524) );
AOI21X1TS U880 ( .A0(n1295), .A1(n1294), .B0(n1293), .Y(n1296) );
NOR2X4TS U881 ( .A(n3526), .B(n3525), .Y(n5109) );
NOR2X4TS U882 ( .A(n2922), .B(n2923), .Y(n7278) );
NAND2X4TS U883 ( .A(n3516), .B(n3515), .Y(n7237) );
NOR2X4TS U884 ( .A(n3530), .B(n3529), .Y(n7345) );
NAND2X4TS U885 ( .A(n2927), .B(n2926), .Y(n7355) );
NOR2X4TS U886 ( .A(mult_x_23_n856), .B(mult_x_23_n846), .Y(n5319) );
NOR2X4TS U887 ( .A(mult_x_23_n726), .B(mult_x_23_n736), .Y(n4793) );
NOR2X4TS U888 ( .A(mult_x_24_n881), .B(mult_x_24_n892), .Y(n7097) );
NAND2X4TS U889 ( .A(mult_x_23_n813), .B(mult_x_23_n823), .Y(n5301) );
NOR2X6TS U890 ( .A(n2929), .B(n2928), .Y(n7363) );
NOR2X6TS U891 ( .A(n2916), .B(n2917), .Y(n7254) );
NOR2X6TS U892 ( .A(n3520), .B(n3519), .Y(n3908) );
NAND2X2TS U893 ( .A(n2929), .B(n2928), .Y(n7364) );
NAND2X2TS U894 ( .A(n2452), .B(n2451), .Y(n7263) );
NAND2X2TS U895 ( .A(n3528), .B(n3527), .Y(n7411) );
NOR2X2TS U896 ( .A(mult_x_23_n647), .B(mult_x_23_n650), .Y(n5177) );
NOR2X2TS U897 ( .A(mult_x_23_n835), .B(mult_x_23_n845), .Y(n5305) );
NAND2X2TS U898 ( .A(mult_x_23_n651), .B(mult_x_23_n655), .Y(n5171) );
NOR2X2TS U899 ( .A(n2445), .B(n2446), .Y(n7128) );
OR2X4TS U900 ( .A(n3545), .B(n3546), .Y(n791) );
NAND2X2TS U901 ( .A(n2914), .B(n2913), .Y(n7369) );
NOR2X4TS U902 ( .A(n2451), .B(n2452), .Y(n7262) );
NAND2X4TS U903 ( .A(n7139), .B(n7143), .Y(n2193) );
INVX2TS U904 ( .A(n5158), .Y(n5195) );
NAND2X4TS U905 ( .A(n1016), .B(n7432), .Y(n3537) );
NOR2X4TS U906 ( .A(mult_x_23_n758), .B(mult_x_23_n768), .Y(n4912) );
NAND2X4TS U907 ( .A(n6119), .B(n6113), .Y(n953) );
NAND2X4TS U908 ( .A(n768), .B(n788), .Y(n5220) );
INVX2TS U909 ( .A(n3837), .Y(n5149) );
INVX2TS U910 ( .A(n7270), .Y(n760) );
NAND2X4TS U911 ( .A(n6128), .B(n6124), .Y(n6117) );
INVX2TS U912 ( .A(n7717), .Y(n7928) );
INVX4TS U913 ( .A(n7275), .Y(n7324) );
NAND2X1TS U914 ( .A(n5258), .B(n1012), .Y(n3891) );
OAI21X1TS U915 ( .A0(n1292), .A1(n5016), .B0(n1291), .Y(n1293) );
OR2X6TS U916 ( .A(n3532), .B(n3531), .Y(n1016) );
OR2X6TS U917 ( .A(n2190), .B(n2189), .Y(n7139) );
NAND2X1TS U918 ( .A(n3551), .B(n3550), .Y(n4695) );
OR2X2TS U919 ( .A(mult_x_24_n750), .B(mult_x_24_n743), .Y(n1027) );
OR2X2TS U920 ( .A(mult_x_24_n751), .B(mult_x_24_n759), .Y(n1028) );
OR2X2TS U921 ( .A(mult_x_23_n646), .B(mult_x_23_n642), .Y(n5267) );
OR2X4TS U922 ( .A(mult_x_24_n798), .B(mult_x_24_n808), .Y(n768) );
OR2X4TS U923 ( .A(mult_x_23_n878), .B(mult_x_23_n887), .Y(n787) );
NAND2X2TS U924 ( .A(n2447), .B(n2448), .Y(n7270) );
NOR2X2TS U925 ( .A(mult_x_23_n669), .B(mult_x_23_n663), .Y(n3836) );
NOR2X2TS U926 ( .A(mult_x_24_n987), .B(mult_x_24_n996), .Y(n1174) );
OR2X4TS U927 ( .A(mult_x_23_n857), .B(mult_x_23_n867), .Y(n1008) );
OR2X4TS U928 ( .A(mult_x_24_n820), .B(mult_x_24_n809), .Y(n788) );
INVX4TS U929 ( .A(n7144), .Y(n7134) );
INVX2TS U930 ( .A(n7148), .Y(n2185) );
NOR2X2TS U931 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n7485) );
INVX2TS U932 ( .A(n5324), .Y(n5329) );
INVX2TS U933 ( .A(n7147), .Y(n7152) );
NOR2X6TS U934 ( .A(n7388), .B(n7157), .Y(n7393) );
ADDFHX2TS U935 ( .A(n2426), .B(n2425), .CI(n2424), .CO(n2451), .S(n2450) );
INVX4TS U936 ( .A(n6122), .Y(n6128) );
NAND2X1TS U937 ( .A(mult_x_23_n906), .B(mult_x_23_n913), .Y(n5345) );
INVX2TS U938 ( .A(n2183), .Y(n965) );
NOR2X4TS U939 ( .A(mult_x_24_n1007), .B(mult_x_24_n1014), .Y(n6947) );
NOR2X6TS U940 ( .A(n1945), .B(n1944), .Y(n7400) );
NAND2X2TS U941 ( .A(n1945), .B(n1944), .Y(n7401) );
NOR2X2TS U942 ( .A(n1939), .B(n1938), .Y(n7157) );
NAND2X2TS U943 ( .A(mult_x_24_n743), .B(mult_x_24_n750), .Y(n4873) );
NAND2X2TS U944 ( .A(mult_x_24_n798), .B(mult_x_24_n808), .Y(n4852) );
NAND2X2TS U945 ( .A(mult_x_23_n878), .B(mult_x_23_n887), .Y(n5990) );
CLKINVX6TS U946 ( .A(n6124), .Y(n1176) );
NAND2X1TS U947 ( .A(mult_x_24_n778), .B(mult_x_24_n787), .Y(n4845) );
NOR2X6TS U948 ( .A(n4425), .B(n8000), .Y(n4427) );
ADDFHX2TS U949 ( .A(n3271), .B(n3270), .CI(n3269), .CO(n3318), .S(n3314) );
AOI21X2TS U950 ( .A0(n789), .A1(n7177), .B0(n1600), .Y(n1601) );
CMPR32X2TS U951 ( .A(n3083), .B(n3082), .C(n3081), .CO(n3133), .S(n3066) );
OR2X6TS U952 ( .A(mult_x_24_n1015), .B(mult_x_24_n1022), .Y(n6150) );
CMPR32X2TS U953 ( .A(n3127), .B(n3126), .C(n3125), .CO(n3566), .S(n3563) );
CMPR32X2TS U954 ( .A(n3114), .B(n3113), .C(n3112), .CO(n3564), .S(n3561) );
NAND2X1TS U955 ( .A(n8308), .B(n4331), .Y(n4333) );
INVX2TS U956 ( .A(n6149), .Y(n1171) );
INVX2TS U957 ( .A(n5355), .Y(n5350) );
CMPR32X2TS U958 ( .A(n3101), .B(n3100), .C(n3099), .CO(n3150), .S(n3139) );
INVX2TS U959 ( .A(n7168), .Y(n7174) );
AOI21X2TS U960 ( .A0(n4417), .A1(n8061), .B0(n4416), .Y(n8001) );
NAND2X2TS U961 ( .A(n4616), .B(n7887), .Y(n4618) );
NOR2X2TS U962 ( .A(n7185), .B(n7226), .Y(n1595) );
INVX2TS U963 ( .A(n7181), .Y(n7177) );
NAND2X2TS U964 ( .A(n8322), .B(n4393), .Y(n4395) );
CMPR32X2TS U965 ( .A(n1925), .B(n1924), .C(n1923), .CO(n1934), .S(n1935) );
CMPR32X2TS U966 ( .A(n3216), .B(n3215), .C(n3214), .CO(n3268), .S(n3262) );
CMPR32X2TS U967 ( .A(n1265), .B(n1264), .C(n1263), .CO(mult_x_23_n664), .S(
mult_x_23_n665) );
CMPR32X2TS U968 ( .A(n2895), .B(n2894), .C(n2893), .CO(n3197), .S(n2892) );
CMPR32X2TS U969 ( .A(n4741), .B(n6223), .C(n4740), .CO(mult_x_24_n712), .S(
mult_x_24_n713) );
CMPR42X1TS U970 ( .A(mult_x_23_n1333), .B(mult_x_23_n1463), .C(
mult_x_23_n809), .D(mult_x_23_n1437), .ICI(mult_x_23_n806), .S(
mult_x_23_n797), .ICO(mult_x_23_n795), .CO(mult_x_23_n796) );
CMPR42X1TS U971 ( .A(mult_x_23_n1358), .B(mult_x_23_n1280), .C(
mult_x_23_n1410), .D(mult_x_23_n798), .ICI(mult_x_23_n795), .S(
mult_x_23_n786), .ICO(mult_x_23_n784), .CO(mult_x_23_n785) );
NOR2X4TS U972 ( .A(mult_x_23_n936), .B(mult_x_23_n942), .Y(n5359) );
NAND2X2TS U973 ( .A(n1730), .B(n1729), .Y(n7169) );
NAND2X2TS U974 ( .A(mult_x_23_n936), .B(mult_x_23_n942), .Y(n5360) );
NOR2X2TS U975 ( .A(mult_x_23_n922), .B(mult_x_23_n928), .Y(n3746) );
NAND2X2TS U976 ( .A(n1593), .B(n1592), .Y(n7186) );
NOR2X1TS U977 ( .A(n7601), .B(n7603), .Y(n5063) );
CLKXOR2X2TS U978 ( .A(n5503), .B(n5868), .Y(mult_x_23_n1294) );
NOR2X2TS U979 ( .A(n7891), .B(n7893), .Y(n4616) );
NOR2X2TS U980 ( .A(n7791), .B(n7780), .Y(n4630) );
NOR2X2TS U981 ( .A(n8076), .B(n8063), .Y(n4417) );
NOR2X2TS U982 ( .A(n8128), .B(n8117), .Y(n4409) );
XOR2X1TS U983 ( .A(n4704), .B(n6021), .Y(mult_x_23_n1275) );
NOR2X2TS U984 ( .A(n7948), .B(n7950), .Y(n4610) );
OAI21X2TS U985 ( .A0(n8302), .A1(n8295), .B0(n8296), .Y(n8278) );
ADDFHX2TS U986 ( .A(n1931), .B(n1930), .CI(n1929), .CO(n1921), .S(n1932) );
OAI21X2TS U987 ( .A0(n8347), .A1(n8343), .B0(n8348), .Y(n8160) );
NAND2X2TS U988 ( .A(n7193), .B(n7197), .Y(n1571) );
OAI21X1TS U989 ( .A0(n8063), .A1(n8077), .B0(n8064), .Y(n4416) );
OAI21X1TS U990 ( .A0(n7950), .A1(n7961), .B0(n7951), .Y(n4609) );
OAI21X1TS U991 ( .A0(n8334), .A1(n8330), .B0(n8335), .Y(n4392) );
NOR2X2TS U992 ( .A(n7858), .B(n7861), .Y(n7829) );
CMPR32X2TS U993 ( .A(n3132), .B(n3131), .C(n3130), .CO(n3151), .S(n3126) );
CMPR32X2TS U994 ( .A(n1916), .B(n1915), .C(n1914), .CO(n2166), .S(n1918) );
CMPR32X2TS U995 ( .A(n1855), .B(n1854), .C(n1853), .CO(n1868), .S(n1922) );
CMPR32X2TS U996 ( .A(n2393), .B(n2392), .C(n2391), .CO(n2396), .S(n2412) );
CMPR32X2TS U997 ( .A(n3013), .B(n3012), .C(n3011), .CO(n3017), .S(n3014) );
CMPR32X2TS U998 ( .A(n1858), .B(n1857), .C(n1856), .CO(n1867), .S(n1931) );
CMPR32X2TS U999 ( .A(mult_x_23_n666), .B(n5838), .C(n5837), .CO(
mult_x_23_n657), .S(mult_x_23_n658) );
CMPR32X2TS U1000 ( .A(n2699), .B(n2698), .C(n2697), .CO(n2795), .S(n2745) );
CMPR32X2TS U1001 ( .A(n4759), .B(n4758), .C(n4757), .CO(mult_x_24_n912), .S(
mult_x_24_n913) );
CMPR32X2TS U1002 ( .A(n7491), .B(n5428), .C(n5427), .CO(mult_x_23_n776), .S(
mult_x_23_n777) );
CMPR32X2TS U1003 ( .A(n2813), .B(n2812), .C(n2811), .CO(n2900), .S(n2849) );
CMPR32X2TS U1004 ( .A(n2868), .B(n2867), .C(n2866), .CO(n3206), .S(n2901) );
CMPR32X2TS U1005 ( .A(n3397), .B(n3396), .C(n3395), .CO(n3486), .S(n3504) );
NAND2X1TS U1006 ( .A(n4628), .B(Sgf_operation_ODD1_Q_left[27]), .Y(n7781) );
CMPR32X2TS U1007 ( .A(n3117), .B(n3116), .C(n3115), .CO(n3127), .S(n3122) );
NAND2X1TS U1008 ( .A(n4627), .B(Sgf_operation_ODD1_Q_left[26]), .Y(n7792) );
NOR2X1TS U1009 ( .A(n4384), .B(Sgf_operation_ODD1_Q_right[44]), .Y(n8281) );
OR2X2TS U1010 ( .A(n1566), .B(n1565), .Y(n7197) );
NAND2X1TS U1011 ( .A(n7611), .B(Sgf_operation_ODD1_Q_left[42]), .Y(n7601) );
NAND2X1TS U1012 ( .A(n4406), .B(Sgf_operation_ODD1_Q_left[2]), .Y(n8129) );
NAND2X1TS U1013 ( .A(n4625), .B(Sgf_operation_ODD1_Q_left[24]), .Y(n7816) );
OR2X2TS U1014 ( .A(n1537), .B(n1536), .Y(n7201) );
NAND2X1TS U1015 ( .A(n4328), .B(Sgf_operation_ODD1_Q_right[40]), .Y(n8317)
);
CMPR32X2TS U1016 ( .A(n2755), .B(n2754), .C(n2753), .CO(n2850), .S(n2796) );
OR2X4TS U1017 ( .A(mult_x_24_n1057), .B(mult_x_24_n1061), .Y(n779) );
NAND2X2TS U1018 ( .A(n1568), .B(n1567), .Y(n7192) );
NOR2X1TS U1019 ( .A(n7531), .B(n7640), .Y(n7628) );
NAND2X1TS U1020 ( .A(n989), .B(n4284), .Y(n4293) );
NAND2X1TS U1021 ( .A(n4390), .B(Sgf_operation_ODD1_Q_right[48]), .Y(n8330)
);
NOR2X2TS U1022 ( .A(n4642), .B(Sgf_operation_ODD1_Q_left[28]), .Y(n7755) );
NOR2X2TS U1023 ( .A(n4643), .B(Sgf_operation_ODD1_Q_left[29]), .Y(n7744) );
NOR2X2TS U1024 ( .A(n4619), .B(Sgf_operation_ODD1_Q_left[20]), .Y(n7858) );
NOR2X1TS U1025 ( .A(n4390), .B(Sgf_operation_ODD1_Q_right[48]), .Y(n8327) );
NAND2X2TS U1026 ( .A(n4605), .B(Sgf_operation_ODD1_Q_left[12]), .Y(n7984) );
NAND2X2TS U1027 ( .A(n4643), .B(Sgf_operation_ODD1_Q_left[29]), .Y(n7745) );
CLKXOR2X2TS U1028 ( .A(n6698), .B(n8445), .Y(mult_x_24_n1640) );
CLKXOR2X2TS U1029 ( .A(n5572), .B(n7498), .Y(mult_x_23_n1348) );
NAND2X2TS U1030 ( .A(n4611), .B(Sgf_operation_ODD1_Q_left[16]), .Y(n7930) );
CLKXOR2X2TS U1031 ( .A(n5714), .B(n8404), .Y(mult_x_23_n1435) );
CMPR32X2TS U1032 ( .A(n1864), .B(n1863), .C(n1862), .CO(n1929), .S(n1937) );
ADDFHX1TS U1033 ( .A(n1843), .B(n1842), .CI(n1841), .CO(n1870), .S(n1866) );
OAI21X2TS U1034 ( .A0(n7006), .A1(n6966), .B0(n6514), .Y(n6515) );
XOR2X1TS U1035 ( .A(n5765), .B(n5819), .Y(mult_x_23_n1463) );
XOR2X1TS U1036 ( .A(n6518), .B(n6968), .Y(mult_x_24_n1491) );
XOR2X1TS U1037 ( .A(n6752), .B(n6758), .Y(mult_x_24_n1585) );
XOR2X1TS U1038 ( .A(n5723), .B(n5736), .Y(mult_x_23_n1439) );
XOR2X1TS U1039 ( .A(n6402), .B(n836), .Y(mult_x_24_n1434) );
ADDFHX1TS U1040 ( .A(n2844), .B(n2843), .CI(n2842), .CO(n2893), .S(n2845) );
OAI22X1TS U1041 ( .A0(n3277), .A1(n3428), .B0(n3345), .B1(n3344), .Y(n3325)
);
XOR2X1TS U1042 ( .A(n5593), .B(n6002), .Y(mult_x_23_n1359) );
NAND2X2TS U1043 ( .A(n4398), .B(Sgf_operation_ODD1_Q_right[50]), .Y(n8343)
);
ADDFHX2TS U1044 ( .A(n2129), .B(n2128), .CI(n2127), .CO(n2144), .S(n2161) );
ADDFX2TS U1045 ( .A(n2719), .B(n2718), .CI(n2717), .CO(n2751), .S(n2728) );
INVX2TS U1046 ( .A(n1569), .Y(n7193) );
OAI21XLTS U1047 ( .A0(n5925), .A1(n5878), .B0(n5626), .Y(n5627) );
OAI21X1TS U1048 ( .A0(n5938), .A1(n5684), .B0(n5681), .Y(n5682) );
XOR2X1TS U1049 ( .A(n2156), .B(n2155), .Y(n959) );
OAI21X1TS U1050 ( .A0(n5887), .A1(n5684), .B0(n5669), .Y(n5671) );
OAI21X1TS U1051 ( .A0(n6850), .A1(n6925), .B0(n6306), .Y(n6307) );
ADDFHX2TS U1052 ( .A(n1574), .B(n1573), .CI(n1572), .CO(n1596), .S(n1593) );
OAI21X1TS U1053 ( .A0(n6967), .A1(n6442), .B0(n6381), .Y(n6382) );
CMPR32X2TS U1054 ( .A(n3038), .B(n3037), .C(n3036), .CO(n3058), .S(n3021) );
CMPR32X2TS U1055 ( .A(n5107), .B(n5106), .C(n5105), .CO(mult_x_23_n923), .S(
mult_x_23_n924) );
CMPR32X2TS U1056 ( .A(n2037), .B(n2036), .C(n2035), .CO(n2400), .S(n2067) );
CMPR32X2TS U1057 ( .A(n7067), .B(mult_x_24_n773), .C(n7066), .CO(
mult_x_24_n764), .S(mult_x_24_n765) );
CMPR32X2TS U1058 ( .A(n2989), .B(n2988), .C(n2987), .CO(n3012), .S(n2970) );
CMPR32X2TS U1059 ( .A(n3300), .B(n3299), .C(n3298), .CO(n3357), .S(n3295) );
CMPR32X2TS U1060 ( .A(n2995), .B(n2994), .C(n2993), .CO(n3022), .S(n3008) );
BUFX3TS U1061 ( .A(n8366), .Y(n904) );
NOR2X1TS U1062 ( .A(n739), .B(n3157), .Y(n3094) );
NOR2X1TS U1063 ( .A(n3120), .B(n3157), .Y(n3160) );
XOR2X1TS U1064 ( .A(n4363), .B(n4362), .Y(n4384) );
XOR2X1TS U1065 ( .A(n4318), .B(n4317), .Y(n4328) );
AOI222X1TS U1066 ( .A0(n6923), .A1(n6922), .B0(n6921), .B1(Op_MX[21]), .C0(
n6920), .C1(n878), .Y(n6924) );
XOR2X1TS U1067 ( .A(n4595), .B(n4594), .Y(n4612) );
NAND2X1TS U1068 ( .A(n1537), .B(n1536), .Y(n7200) );
NAND2X2TS U1069 ( .A(mult_x_23_n948), .B(mult_x_23_n952), .Y(n5367) );
OAI21X1TS U1070 ( .A0(n5876), .A1(n5904), .B0(n5875), .Y(n6051) );
NOR2X1TS U1071 ( .A(n7620), .B(n7622), .Y(n7611) );
OAI22X1TS U1072 ( .A0(n2824), .A1(n3430), .B0(n2764), .B1(n3006), .Y(n2834)
);
CLKXOR2X2TS U1073 ( .A(n6548), .B(n6827), .Y(mult_x_24_n1521) );
OAI22X1TS U1074 ( .A0(n2763), .A1(n3279), .B0(n2841), .B1(n2762), .Y(n2835)
);
OAI22X1TS U1075 ( .A0(n2479), .A1(n3336), .B0(n2517), .B1(n3335), .Y(n2487)
);
OAI22X1TS U1076 ( .A0(n2757), .A1(n3231), .B0(n2806), .B1(n3335), .Y(n2812)
);
OAI22X1TS U1077 ( .A0(n2499), .A1(n2809), .B0(n2498), .B1(n2497), .Y(n2528)
);
XOR2X1TS U1078 ( .A(n6049), .B(Op_MX[50]), .Y(n6050) );
OAI22X1TS U1079 ( .A0(n2807), .A1(n3407), .B0(n2875), .B1(n3405), .Y(n2867)
);
NAND2X1TS U1080 ( .A(n7530), .B(n7717), .Y(n7640) );
XOR2X1TS U1081 ( .A(n6541), .B(n835), .Y(mult_x_24_n1509) );
XOR2X1TS U1082 ( .A(n6537), .B(n835), .Y(mult_x_24_n1506) );
OAI21X1TS U1083 ( .A0(n5925), .A1(n5827), .B0(n5826), .Y(n5829) );
XOR2X1TS U1084 ( .A(n5645), .B(n5644), .Y(mult_x_23_n1387) );
XOR2X1TS U1085 ( .A(n6671), .B(n6820), .Y(mult_x_24_n1617) );
XOR2X1TS U1086 ( .A(n5737), .B(n5736), .Y(mult_x_23_n1445) );
XOR2X1TS U1087 ( .A(n6472), .B(n8392), .Y(mult_x_24_n1449) );
OAI21X2TS U1088 ( .A0(n5896), .A1(n5886), .B0(n5506), .Y(n5507) );
OAI22X1TS U1089 ( .A0(n2564), .A1(n3432), .B0(n2652), .B1(n3430), .Y(n2614)
);
CMPR32X2TS U1090 ( .A(n2132), .B(n2131), .C(n2130), .CO(n2128), .S(n2171) );
OAI21X1TS U1091 ( .A0(n5945), .A1(n5924), .B0(n5822), .Y(n5823) );
ADDFHX1TS U1092 ( .A(n3394), .B(n3393), .CI(n3392), .CO(n3445), .S(n3487) );
XNOR2X1TS U1093 ( .A(n3249), .B(n3409), .Y(n3289) );
ADDFHX1TS U1094 ( .A(n1806), .B(n1805), .CI(n1804), .CO(n1899), .S(n1855) );
OAI21XLTS U1095 ( .A0(n5879), .A1(n5761), .B0(n5711), .Y(n5710) );
AOI222X1TS U1096 ( .A0(n882), .A1(n5796), .B0(n865), .B1(n5982), .C0(n6017),
.C1(n6005), .Y(n4703) );
ADDFHX1TS U1097 ( .A(n3454), .B(n3453), .CI(n3452), .CO(n2972), .S(n3462) );
OAI21X1TS U1098 ( .A0(n6993), .A1(n6788), .B0(n6510), .Y(n6511) );
OAI21X1TS U1099 ( .A0(n6993), .A1(n6792), .B0(n4738), .Y(n4739) );
XOR2X1TS U1100 ( .A(n4751), .B(n7494), .Y(n4758) );
XOR2X1TS U1101 ( .A(n5420), .B(n6021), .Y(n5421) );
XNOR2X2TS U1102 ( .A(n738), .B(n3363), .Y(n3026) );
XNOR2X1TS U1103 ( .A(n909), .B(n2221), .Y(n3128) );
XNOR2X2TS U1104 ( .A(n3349), .B(n3346), .Y(n3280) );
XNOR2X1TS U1105 ( .A(n753), .B(n2221), .Y(n3121) );
XNOR2X1TS U1106 ( .A(n4135), .B(n4134), .Y(n4414) );
XNOR2X2TS U1107 ( .A(n4585), .B(n4584), .Y(n4613) );
XOR2X2TS U1108 ( .A(n4099), .B(n4098), .Y(n4418) );
XNOR2X1TS U1109 ( .A(n4556), .B(n4130), .Y(n4421) );
CMPR32X2TS U1110 ( .A(n3382), .B(n3381), .C(n3380), .CO(n3393), .S(n3434) );
XOR2X2TS U1111 ( .A(n6770), .B(n6851), .Y(mult_x_24_n1551) );
AO21XLTS U1112 ( .A0(n2877), .A1(n2018), .B0(n2876), .Y(n3183) );
NAND2X1TS U1113 ( .A(n7630), .B(Sgf_operation_ODD1_Q_left[40]), .Y(n7620) );
INVX2TS U1114 ( .A(n6189), .Y(n6184) );
CLKXOR2X2TS U1115 ( .A(n4681), .B(n5567), .Y(n4690) );
NOR2X1TS U1116 ( .A(n7529), .B(n7938), .Y(n7717) );
OAI21X2TS U1117 ( .A0(n6043), .A1(n6061), .B0(n5405), .Y(n5834) );
CLKXOR2X2TS U1118 ( .A(n6738), .B(n7076), .Y(mult_x_24_n1444) );
CLKXOR2X2TS U1119 ( .A(n7077), .B(n8392), .Y(mult_x_24_n1442) );
OAI22X1TS U1120 ( .A0(n2320), .A1(n3279), .B0(n2319), .B1(n2762), .Y(n2337)
);
AOI222X1TS U1121 ( .A0(n6796), .A1(n875), .B0(n6806), .B1(n7008), .C0(n6805),
.C1(n910), .Y(n6743) );
OAI22X1TS U1122 ( .A0(n2306), .A1(n2809), .B0(n2499), .B1(n2772), .Y(n2456)
);
OAI22X1TS U1123 ( .A0(n2332), .A1(n932), .B0(n2318), .B1(n2715), .Y(n2338)
);
CLKXOR2X2TS U1124 ( .A(n6439), .B(n8392), .Y(mult_x_24_n1441) );
OAI21X2TS U1125 ( .A0(n6048), .A1(n4965), .B0(n6047), .Y(n6049) );
XOR2X1TS U1126 ( .A(n6856), .B(n6695), .Y(mult_x_24_n1625) );
XOR2X1TS U1127 ( .A(n6712), .B(n8445), .Y(mult_x_24_n1646) );
XOR2X1TS U1128 ( .A(n1221), .B(n6820), .Y(mult_x_24_n1616) );
XOR2X1TS U1129 ( .A(n6688), .B(n940), .Y(mult_x_24_n1624) );
XNOR2X1TS U1130 ( .A(n900), .B(Op_MX[26]), .Y(n3219) );
OAI21X1TS U1131 ( .A0(n6048), .A1(n5861), .B0(n5735), .Y(n5737) );
OAI21X1TS U1132 ( .A0(n4590), .A1(n4586), .B0(n4587), .Y(n4473) );
ADDFHX1TS U1133 ( .A(n2291), .B(n2290), .CI(n2289), .CO(n2299), .S(n2353) );
XNOR2X1TS U1134 ( .A(n914), .B(n3329), .Y(n3332) );
OAI21X1TS U1135 ( .A0(n6048), .A1(n5620), .B0(n5643), .Y(n5645) );
XNOR2X1TS U1136 ( .A(n3334), .B(n2583), .Y(n2366) );
XNOR2X1TS U1137 ( .A(n853), .B(n2997), .Y(n3032) );
XNOR2X1TS U1138 ( .A(n3287), .B(n3346), .Y(n2763) );
XNOR2X1TS U1139 ( .A(n3330), .B(n2939), .Y(n2722) );
XNOR2X2TS U1140 ( .A(n916), .B(n2784), .Y(n2807) );
XNOR2X1TS U1141 ( .A(n919), .B(n2468), .Y(n2367) );
XNOR2X2TS U1142 ( .A(n3303), .B(n2944), .Y(n2764) );
ADDFX2TS U1143 ( .A(n1535), .B(n1534), .CI(n1533), .CO(n1536), .S(n1527) );
XNOR2X1TS U1144 ( .A(n918), .B(n2632), .Y(n2364) );
XNOR2X2TS U1145 ( .A(n3330), .B(n2944), .Y(n2824) );
OAI21X1TS U1146 ( .A0(n6850), .A1(n7013), .B0(n6487), .Y(n6488) );
XNOR2X2TS U1147 ( .A(n3285), .B(n3074), .Y(n2875) );
ADDFHX2TS U1148 ( .A(n2828), .B(n2827), .CI(n2826), .CO(n2885), .S(n2842) );
OAI21X1TS U1149 ( .A0(n6793), .A1(n6792), .B0(n6791), .Y(n6795) );
XNOR2X1TS U1150 ( .A(n3410), .B(n2822), .Y(n2655) );
XNOR2X2TS U1151 ( .A(n753), .B(n3346), .Y(n3404) );
XNOR2X1TS U1152 ( .A(n919), .B(n2583), .Y(n2316) );
XNOR2X1TS U1153 ( .A(n3384), .B(n3275), .Y(n2774) );
XNOR2X2TS U1154 ( .A(n3384), .B(n3409), .Y(n3339) );
OAI21X1TS U1155 ( .A0(n7039), .A1(n6872), .B0(n4750), .Y(n4751) );
AOI21X1TS U1156 ( .A0(n4139), .A1(n4137), .B0(n4093), .Y(n4099) );
XNOR2X1TS U1157 ( .A(n3334), .B(n3275), .Y(n2723) );
XNOR2X1TS U1158 ( .A(n3276), .B(n2720), .Y(n2773) );
XNOR2X1TS U1159 ( .A(n3165), .B(n2784), .Y(n2649) );
AOI21X1TS U1160 ( .A0(n4599), .A1(n4598), .B0(n4597), .Y(n4604) );
CMPR32X2TS U1161 ( .A(n1666), .B(n1665), .C(n1664), .CO(n1696), .S(n1658) );
INVX6TS U1162 ( .A(n5002), .Y(n5792) );
INVX6TS U1163 ( .A(n6276), .Y(n6703) );
XOR2X1TS U1164 ( .A(n3699), .B(n5763), .Y(n3732) );
NOR2X1TS U1165 ( .A(n2629), .B(n3583), .Y(n2711) );
CMPR32X2TS U1166 ( .A(n1466), .B(n1465), .C(n1464), .CO(n1639), .S(n1486) );
BUFX3TS U1167 ( .A(n5491), .Y(n6035) );
INVX6TS U1168 ( .A(n3865), .Y(n5879) );
BUFX3TS U1169 ( .A(n4965), .Y(n6067) );
INVX2TS U1170 ( .A(n866), .Y(n868) );
INVX8TS U1171 ( .A(n1237), .Y(n6048) );
AOI222X1TS U1172 ( .A0(n6870), .A1(Op_MX[18]), .B0(n6834), .B1(n6790), .C0(
n6867), .C1(n6562), .Y(n6791) );
INVX4TS U1173 ( .A(n1036), .Y(n7535) );
INVX1TS U1174 ( .A(n4636), .Y(n4637) );
OAI22X1TS U1175 ( .A0(n2313), .A1(n3089), .B0(n2231), .B1(n3331), .Y(n2257)
);
NAND2X1TS U1176 ( .A(n7528), .B(n8057), .Y(n7938) );
AOI222X1TS U1177 ( .A0(n884), .A1(n875), .B0(n6727), .B1(Op_MX[11]), .C0(
n6914), .C1(n6904), .Y(n6721) );
OAI22X1TS U1178 ( .A0(n2265), .A1(n2976), .B0(n2330), .B1(n3006), .Y(n2290)
);
NAND2X2TS U1179 ( .A(n1155), .B(n1154), .Y(n6189) );
OAI22X1TS U1180 ( .A0(n1832), .A1(n2730), .B0(n1873), .B1(n2303), .Y(n1889)
);
NOR2X1TS U1181 ( .A(n7644), .B(n5060), .Y(n7630) );
XOR2X1TS U1182 ( .A(n6880), .B(n7490), .Y(mult_x_24_n1539) );
NOR2X2TS U1183 ( .A(n2825), .B(n3583), .Y(n3182) );
XNOR2X1TS U1184 ( .A(n3176), .B(n3227), .Y(n2332) );
OAI21X2TS U1185 ( .A0(n7006), .A1(n6973), .B0(n6972), .Y(n6975) );
OAI21X2TS U1186 ( .A0(n7063), .A1(n7062), .B0(n7061), .Y(n7065) );
XNOR2X1TS U1187 ( .A(n3364), .B(n3227), .Y(n2333) );
XNOR2X1TS U1188 ( .A(n914), .B(n2771), .Y(n2101) );
OAI22X1TS U1189 ( .A0(n2272), .A1(n3188), .B0(n2271), .B1(n3231), .Y(n2347)
);
XNOR2X1TS U1190 ( .A(n3359), .B(n3343), .Y(n2500) );
XNOR2X1TS U1191 ( .A(n3276), .B(n2254), .Y(n2262) );
XNOR2X1TS U1192 ( .A(n914), .B(n3363), .Y(n2967) );
OAI21XLTS U1193 ( .A0(n7014), .A1(n7005), .B0(n6719), .Y(n6720) );
XNOR2X1TS U1194 ( .A(n2954), .B(n3343), .Y(n2270) );
XNOR2X1TS U1195 ( .A(n2869), .B(n2650), .Y(n2557) );
OAI21X1TS U1196 ( .A0(n7086), .A1(n6763), .B0(n6467), .Y(n6468) );
XNOR2X1TS U1197 ( .A(n3165), .B(n1872), .Y(n1808) );
XNOR2X2TS U1198 ( .A(n860), .B(n2784), .Y(n2558) );
XNOR2X2TS U1199 ( .A(n921), .B(n2771), .Y(n2349) );
XNOR2X1TS U1200 ( .A(n900), .B(n2264), .Y(n2230) );
XNOR2X2TS U1201 ( .A(n922), .B(n2822), .Y(n2304) );
XNOR2X2TS U1202 ( .A(n915), .B(n2720), .Y(n2306) );
XNOR2X1TS U1203 ( .A(n2873), .B(n2881), .Y(n2334) );
XNOR2X1TS U1204 ( .A(n3582), .B(n2944), .Y(n2977) );
XNOR2X2TS U1205 ( .A(n753), .B(n3409), .Y(n2991) );
XNOR2X1TS U1206 ( .A(n3338), .B(n3383), .Y(n3418) );
XNOR2X2TS U1207 ( .A(n912), .B(n3409), .Y(n2968) );
XNOR2X1TS U1208 ( .A(n3223), .B(n1740), .Y(n1838) );
XNOR2X2TS U1209 ( .A(n913), .B(n2469), .Y(n1839) );
XNOR2X1TS U1210 ( .A(n3223), .B(n2254), .Y(n1492) );
XNOR2X1TS U1211 ( .A(n3364), .B(n2944), .Y(n2564) );
XNOR2X1TS U1212 ( .A(n916), .B(n2294), .Y(n2319) );
XNOR2X1TS U1213 ( .A(n916), .B(n1708), .Y(n1807) );
XNOR2X1TS U1214 ( .A(n3285), .B(n3275), .Y(n2292) );
CMPR32X2TS U1215 ( .A(n1163), .B(n1162), .C(n1161), .CO(n1164), .S(n1157) );
INVX6TS U1216 ( .A(n1219), .Y(n6832) );
BUFX8TS U1217 ( .A(n2008), .Y(n3349) );
INVX6TS U1218 ( .A(n6319), .Y(n6933) );
INVX6TS U1219 ( .A(n6437), .Y(n7063) );
BUFX8TS U1220 ( .A(n3226), .Y(n853) );
INVX2TS U1221 ( .A(n769), .Y(n836) );
BUFX8TS U1222 ( .A(n1964), .Y(n3338) );
INVX2TS U1223 ( .A(n1017), .Y(n6946) );
BUFX6TS U1224 ( .A(n3331), .Y(n3407) );
INVX8TS U1225 ( .A(n3828), .Y(n7006) );
INVX4TS U1226 ( .A(n2942), .Y(n3346) );
INVX8TS U1227 ( .A(n6265), .Y(n6769) );
NAND2XLTS U1228 ( .A(n5599), .B(n5597), .Y(n4701) );
INVX8TS U1229 ( .A(n4734), .Y(n6993) );
BUFX3TS U1230 ( .A(n5569), .Y(n6007) );
BUFX3TS U1231 ( .A(n4671), .Y(n6014) );
CLKINVX6TS U1232 ( .A(n5835), .Y(n6010) );
BUFX8TS U1233 ( .A(n2045), .Y(n2459) );
INVX4TS U1234 ( .A(n3051), .Y(n3409) );
BUFX3TS U1235 ( .A(n2877), .Y(n2809) );
BUFX8TS U1236 ( .A(n3419), .Y(n3336) );
BUFX6TS U1237 ( .A(n3276), .Y(n909) );
BUFX3TS U1238 ( .A(n6011), .Y(n5561) );
AOI222X1TS U1239 ( .A0(n6839), .A1(n8412), .B0(n7045), .B1(n7069), .C0(n7043), .C1(Op_MX[12]), .Y(n6604) );
CLKBUFX2TS U1240 ( .A(n3880), .Y(n5940) );
OAI22X2TS U1241 ( .A0(n1719), .A1(n3427), .B0(n1651), .B1(n3428), .Y(n1721)
);
NOR2X2TS U1242 ( .A(n8447), .B(FS_Module_state_reg[3]), .Y(n7480) );
CLKINVX3TS U1243 ( .A(n4113), .Y(n4126) );
NAND2X1TS U1244 ( .A(n7527), .B(n8108), .Y(n8057) );
AOI222X1TS U1245 ( .A0(n6817), .A1(n875), .B0(n6903), .B1(Op_MX[11]), .C0(
n6902), .C1(n6904), .Y(n6687) );
AOI222X1TS U1246 ( .A0(n5859), .A1(n814), .B0(n5712), .B1(Op_MY[36]), .C0(
n5751), .C1(n832), .Y(n5752) );
CLKXOR2X2TS U1247 ( .A(n5917), .B(n895), .Y(mult_x_23_n1429) );
AOI21X2TS U1248 ( .A0(n4983), .A1(n4982), .B0(n4981), .Y(n4988) );
NOR2X1TS U1249 ( .A(n7993), .B(n7523), .Y(n7939) );
BUFX3TS U1250 ( .A(n2815), .Y(n3303) );
INVX4TS U1251 ( .A(n2937), .Y(n3167) );
AOI21X2TS U1252 ( .A0(n1242), .A1(n1241), .B0(n1240), .Y(n1245) );
XNOR2X1TS U1253 ( .A(n2869), .B(n2264), .Y(n2265) );
XNOR2X1TS U1254 ( .A(n3276), .B(n2468), .Y(n2511) );
XNOR2X1TS U1255 ( .A(n3276), .B(n2583), .Y(n2654) );
XNOR2X1TS U1256 ( .A(n2954), .B(n2771), .Y(n2029) );
XNOR2X1TS U1257 ( .A(n911), .B(n2294), .Y(n2064) );
XNOR2X2TS U1258 ( .A(n906), .B(n2650), .Y(n2272) );
XNOR2X1TS U1259 ( .A(n3223), .B(n2070), .Y(n2062) );
XOR2X1TS U1260 ( .A(n4688), .B(n5567), .Y(n6086) );
XNOR2X2TS U1261 ( .A(n2789), .B(n3329), .Y(n2503) );
XNOR2X2TS U1262 ( .A(n3582), .B(n2469), .Y(n2561) );
XNOR2X2TS U1263 ( .A(n3410), .B(n2720), .Y(n2498) );
XNOR2X2TS U1264 ( .A(n862), .B(n2784), .Y(n2231) );
XNOR2X2TS U1265 ( .A(n915), .B(n3190), .Y(n2635) );
OAI21X1TS U1266 ( .A0(n7075), .A1(n6792), .B0(n6498), .Y(n6499) );
BUFX4TS U1267 ( .A(n888), .Y(n3279) );
INVX2TS U1268 ( .A(n3403), .Y(n889) );
XNOR2X1TS U1269 ( .A(n917), .B(n2632), .Y(n1610) );
XNOR2X2TS U1270 ( .A(n741), .B(n2650), .Y(n2271) );
XNOR2X1TS U1271 ( .A(n856), .B(n2254), .Y(n1544) );
AOI21X1TS U1272 ( .A0(n5600), .A1(n5599), .B0(n5598), .Y(n5605) );
OAI21X1TS U1273 ( .A0(n7086), .A1(n7085), .B0(n7084), .Y(n7088) );
NAND2X1TS U1274 ( .A(n4551), .B(Sgf_operation_ODD1_Q_middle[54]), .Y(n4636)
);
XNOR2X1TS U1275 ( .A(n3364), .B(n2881), .Y(n2017) );
CLKXOR2X2TS U1276 ( .A(n1072), .B(n1071), .Y(n1103) );
XNOR2X1TS U1277 ( .A(n3384), .B(n2822), .Y(n2470) );
XNOR2X1TS U1278 ( .A(n912), .B(n2720), .Y(n2656) );
XNOR2X1TS U1279 ( .A(n920), .B(n2822), .Y(n2600) );
XNOR2X1TS U1280 ( .A(n3359), .B(n2469), .Y(n1833) );
XNOR2X1TS U1281 ( .A(n2873), .B(n2653), .Y(n2025) );
XNOR2X1TS U1282 ( .A(n2789), .B(n3230), .Y(n2263) );
XNOR2X1TS U1283 ( .A(n2789), .B(n2944), .Y(n2099) );
XNOR2X1TS U1284 ( .A(n3287), .B(n3275), .Y(n2634) );
BUFX3TS U1285 ( .A(n822), .Y(n6813) );
BUFX3TS U1286 ( .A(n5075), .Y(n6869) );
BUFX3TS U1287 ( .A(n6531), .Y(n6960) );
BUFX6TS U1288 ( .A(n1313), .Y(n2878) );
BUFX3TS U1289 ( .A(n6237), .Y(n7085) );
BUFX8TS U1290 ( .A(n1313), .Y(n860) );
INVX6TS U1291 ( .A(n6453), .Y(n6855) );
INVX2TS U1292 ( .A(n1017), .Y(n7078) );
INVX4TS U1293 ( .A(n3426), .Y(n3275) );
INVX6TS U1294 ( .A(n6367), .Y(n6775) );
NOR2X1TS U1295 ( .A(n2535), .B(n3583), .Y(n2576) );
INVX4TS U1296 ( .A(n2786), .Y(n2583) );
INVX6TS U1297 ( .A(n6236), .Y(n6912) );
BUFX8TS U1298 ( .A(n2957), .Y(n912) );
BUFX8TS U1299 ( .A(n1785), .Y(n3287) );
BUFX3TS U1300 ( .A(n5665), .Y(n5978) );
BUFX3TS U1301 ( .A(n5620), .Y(n5985) );
BUFX3TS U1302 ( .A(n4749), .Y(n6872) );
BUFX3TS U1303 ( .A(n4805), .Y(n6763) );
BUFX8TS U1304 ( .A(n1447), .Y(n3368) );
BUFX8TS U1305 ( .A(n1447), .Y(n916) );
BUFX3TS U1306 ( .A(n5081), .Y(n6899) );
INVX6TS U1307 ( .A(n3623), .Y(n5905) );
BUFX3TS U1308 ( .A(n6639), .Y(n6990) );
NAND2X1TS U1309 ( .A(n6273), .B(n6272), .Y(n6274) );
BUFX4TS U1310 ( .A(n1895), .Y(n2368) );
BUFX16TS U1311 ( .A(n2950), .Y(n3276) );
INVX2TS U1312 ( .A(n3403), .Y(n890) );
BUFX4TS U1313 ( .A(n1973), .Y(n3410) );
BUFX6TS U1314 ( .A(n2008), .Y(n918) );
BUFX6TS U1315 ( .A(n3165), .Y(n856) );
INVX8TS U1316 ( .A(n6358), .Y(n7014) );
BUFX6TS U1317 ( .A(n2225), .Y(n3376) );
AOI222X1TS U1318 ( .A0(n7011), .A1(Op_MX[14]), .B0(n6834), .B1(n7069), .C0(
n5076), .C1(n7068), .Y(n6498) );
NOR2X1TS U1319 ( .A(n7700), .B(n4644), .Y(n5059) );
BUFX16TS U1320 ( .A(n3330), .Y(n921) );
OAI22X1TS U1321 ( .A0(n2582), .A1(n3154), .B0(n2536), .B1(n2966), .Y(n2575)
);
OR2X2TS U1322 ( .A(n4550), .B(Sgf_operation_ODD1_Q_middle[53]), .Y(n4551) );
BUFX8TS U1323 ( .A(n2225), .Y(n930) );
BUFX6TS U1324 ( .A(n6893), .Y(n7003) );
INVX4TS U1325 ( .A(n2876), .Y(n2720) );
INVX2TS U1326 ( .A(n5096), .Y(n866) );
AOI222X1TS U1327 ( .A0(n871), .A1(n6005), .B0(n873), .B1(Op_MY[36]), .C0(
n5801), .C1(n8385), .Y(n5803) );
CLKXOR2X2TS U1328 ( .A(n4716), .B(n892), .Y(n5136) );
BUFX8TS U1329 ( .A(n3176), .Y(n913) );
BUFX6TS U1330 ( .A(n2086), .Y(n3231) );
XNOR2X1TS U1331 ( .A(n2577), .B(n2871), .Y(n2616) );
XOR2X1TS U1332 ( .A(n3641), .B(n5763), .Y(n3701) );
XNOR2X1TS U1333 ( .A(n3358), .B(n2532), .Y(n2579) );
XNOR2X1TS U1334 ( .A(n3230), .B(n2580), .Y(n2088) );
XNOR2X2TS U1335 ( .A(n2580), .B(n3329), .Y(n2211) );
XOR2X1TS U1336 ( .A(n3800), .B(n5663), .Y(n4762) );
BUFX8TS U1337 ( .A(n3359), .Y(n2873) );
BUFX8TS U1338 ( .A(n3364), .Y(n2954) );
BUFX6TS U1339 ( .A(n1964), .Y(n920) );
XNOR2X1TS U1340 ( .A(n3668), .B(n5804), .Y(n5394) );
BUFX6TS U1341 ( .A(n2532), .Y(n2789) );
BUFX3TS U1342 ( .A(n6239), .Y(n7081) );
NAND2X1TS U1343 ( .A(n4528), .B(n4527), .Y(n4531) );
INVX12TS U1344 ( .A(n4525), .Y(n4488) );
BUFX8TS U1345 ( .A(n1462), .Y(n917) );
BUFX3TS U1346 ( .A(n822), .Y(n6902) );
BUFX6TS U1347 ( .A(n3880), .Y(n5899) );
NAND2X1TS U1348 ( .A(n6289), .B(n6288), .Y(n6290) );
NAND2X1TS U1349 ( .A(n6397), .B(n6396), .Y(n6398) );
INVX6TS U1350 ( .A(n5493), .Y(n5844) );
BUFX3TS U1351 ( .A(n6558), .Y(n6876) );
NAND2XLTS U1352 ( .A(n4982), .B(n4980), .Y(n4977) );
NAND2X1TS U1353 ( .A(n6302), .B(n6301), .Y(n6303) );
NAND2X1TS U1354 ( .A(n6434), .B(n6433), .Y(n6435) );
NAND2X1TS U1355 ( .A(n6262), .B(n6261), .Y(n6263) );
NAND2X1TS U1356 ( .A(n6297), .B(n6295), .Y(n1217) );
INVX4TS U1357 ( .A(n1067), .Y(n6865) );
BUFX4TS U1358 ( .A(n2532), .Y(n908) );
BUFX8TS U1359 ( .A(n6920), .Y(n7057) );
BUFX3TS U1360 ( .A(n6920), .Y(n7080) );
BUFX4TS U1361 ( .A(n6615), .Y(n7043) );
BUFX12TS U1362 ( .A(n1248), .Y(n5454) );
CLKBUFX2TS U1363 ( .A(n2578), .Y(n2956) );
CLKINVX6TS U1364 ( .A(n2709), .Y(n907) );
BUFX3TS U1365 ( .A(n4717), .Y(n6809) );
BUFX8TS U1366 ( .A(n1429), .Y(n3222) );
BUFX12TS U1367 ( .A(n1772), .Y(n3330) );
OAI21X2TS U1368 ( .A0(n740), .A1(n6299), .B0(n6298), .Y(n6304) );
NAND2BXLTS U1369 ( .AN(n2198), .B(n2650), .Y(n1991) );
OAI21X1TS U1370 ( .A0(n6824), .A1(n6788), .B0(n4715), .Y(n4716) );
INVX4TS U1371 ( .A(n5711), .Y(n5857) );
BUFX12TS U1372 ( .A(n2084), .Y(n3331) );
NAND2X2TS U1373 ( .A(n4992), .B(n4995), .Y(n4998) );
BUFX6TS U1374 ( .A(n1622), .Y(n934) );
BUFX4TS U1375 ( .A(n6239), .Y(n7058) );
BUFX12TS U1376 ( .A(n1882), .Y(n935) );
XNOR2X2TS U1377 ( .A(n2580), .B(n2944), .Y(n1884) );
XNOR2X1TS U1378 ( .A(n2223), .B(n3358), .Y(n2209) );
XNOR2X2TS U1379 ( .A(n2580), .B(n2997), .Y(n1994) );
XNOR2X2TS U1380 ( .A(n857), .B(n3227), .Y(n1624) );
BUFX3TS U1381 ( .A(n6238), .Y(n7060) );
XNOR2X2TS U1382 ( .A(n858), .B(n3343), .Y(n1651) );
XNOR2X1TS U1383 ( .A(n2198), .B(n3230), .Y(n1992) );
OAI22X1TS U1384 ( .A0(n1502), .A1(n7231), .B0(n929), .B1(n1810), .Y(n7223)
);
XNOR2X2TS U1385 ( .A(n6366), .B(n6365), .Y(n6367) );
XNOR2X2TS U1386 ( .A(n6452), .B(n6451), .Y(n6453) );
BUFX3TS U1387 ( .A(n2628), .Y(n1895) );
BUFX6TS U1388 ( .A(n5076), .Y(n6867) );
INVX6TS U1389 ( .A(n1127), .Y(n7039) );
BUFX3TS U1390 ( .A(n2627), .Y(n2559) );
INVX2TS U1391 ( .A(n793), .Y(n895) );
AND3X2TS U1392 ( .A(n4665), .B(n4664), .C(n1795), .Y(n5560) );
BUFX6TS U1393 ( .A(n6982), .Y(n7019) );
INVX4TS U1394 ( .A(n2692), .Y(n2650) );
INVX12TS U1395 ( .A(n733), .Y(n740) );
INVX2TS U1396 ( .A(n1018), .Y(n6861) );
BUFX6TS U1397 ( .A(n5096), .Y(n5830) );
BUFX6TS U1398 ( .A(n2097), .Y(n3350) );
NAND2X1TS U1399 ( .A(n6463), .B(n6462), .Y(n6464) );
BUFX3TS U1400 ( .A(n6544), .Y(n7023) );
BUFX4TS U1401 ( .A(n5668), .Y(n5698) );
BUFX3TS U1402 ( .A(n2627), .Y(n2053) );
NAND2X1TS U1403 ( .A(n6343), .B(n6424), .Y(n6344) );
NAND2X1TS U1404 ( .A(n6450), .B(n6449), .Y(n6451) );
NAND2X1TS U1405 ( .A(n6355), .B(n6354), .Y(n6356) );
BUFX3TS U1406 ( .A(n2628), .Y(n2560) );
NAND2XLTS U1407 ( .A(n6238), .B(n825), .Y(n4745) );
BUFX12TS U1408 ( .A(n2945), .Y(n3384) );
CLKINVX6TS U1409 ( .A(n2709), .Y(n906) );
INVX8TS U1410 ( .A(n3107), .Y(n3329) );
INVX6TS U1411 ( .A(n2942), .Y(n2939) );
BUFX6TS U1412 ( .A(n6238), .Y(n6923) );
BUFX4TS U1413 ( .A(n2877), .Y(n2100) );
BUFX6TS U1414 ( .A(n6512), .Y(n6962) );
BUFX6TS U1415 ( .A(n2788), .Y(n2045) );
INVX2TS U1416 ( .A(n5751), .Y(n5711) );
NAND3X2TS U1417 ( .A(n3626), .B(n3625), .C(n3624), .Y(n5493) );
BUFX4TS U1418 ( .A(n6405), .Y(n6473) );
OAI21X2TS U1419 ( .A0(n6461), .A1(n6231), .B0(n6230), .Y(n6235) );
AOI21X2TS U1420 ( .A0(n6269), .A1(n6245), .B0(n6244), .Y(n6246) );
BUFX4TS U1421 ( .A(n4675), .Y(n6012) );
INVX4TS U1422 ( .A(n3426), .Y(n2070) );
OAI21X2TS U1423 ( .A0(n2282), .A1(n819), .B0(n2280), .Y(n2286) );
OAI21X2TS U1424 ( .A0(n6461), .A1(n6447), .B0(n6446), .Y(n6452) );
BUFX6TS U1425 ( .A(n1429), .Y(n3179) );
BUFX3TS U1426 ( .A(n1500), .Y(n2477) );
CLKXOR2X2TS U1427 ( .A(n2206), .B(Op_MX[25]), .Y(n2207) );
NAND2X6TS U1428 ( .A(n4381), .B(n4141), .Y(n4144) );
BUFX4TS U1429 ( .A(n4672), .Y(n5564) );
BUFX6TS U1430 ( .A(n1882), .Y(n3415) );
BUFX12TS U1431 ( .A(n732), .Y(n2580) );
BUFX4TS U1432 ( .A(n1710), .Y(n2762) );
CLKINVX3TS U1433 ( .A(n4142), .Y(n4143) );
INVX6TS U1434 ( .A(n2937), .Y(n2871) );
CLKINVX6TS U1435 ( .A(n3107), .Y(n2784) );
XNOR2X2TS U1436 ( .A(n859), .B(n2771), .Y(n1482) );
AOI21X2TS U1437 ( .A0(n6392), .A1(n6297), .B0(n6296), .Y(n6298) );
OAI21X1TS U1438 ( .A0(n5043), .A1(n6841), .B0(n5008), .Y(n5009) );
BUFX3TS U1439 ( .A(n1478), .Y(n2016) );
XNOR2X1TS U1440 ( .A(n859), .B(n2632), .Y(n1502) );
XNOR2X2TS U1441 ( .A(n4721), .B(n6517), .Y(n6943) );
XNOR2X2TS U1442 ( .A(n858), .B(n2881), .Y(n1430) );
CLKXOR2X4TS U1443 ( .A(n1096), .B(n1095), .Y(n6900) );
BUFX3TS U1444 ( .A(n5081), .Y(n7025) );
XNOR2X1TS U1445 ( .A(n7232), .B(n2881), .Y(n1428) );
ADDHX1TS U1446 ( .A(n8404), .B(n3675), .CO(n3685), .S(n3676) );
XOR2X2TS U1447 ( .A(n3636), .B(n3635), .Y(n3697) );
INVX6TS U1448 ( .A(n1424), .Y(n2881) );
INVX6TS U1449 ( .A(n5667), .Y(n5928) );
INVX6TS U1450 ( .A(n4140), .Y(n4381) );
INVX4TS U1451 ( .A(n1007), .Y(n2632) );
INVX6TS U1452 ( .A(n2074), .Y(n3107) );
BUFX3TS U1453 ( .A(n3717), .Y(n5929) );
INVX8TS U1454 ( .A(n2534), .Y(n858) );
INVX6TS U1455 ( .A(n1615), .Y(n3426) );
BUFX3TS U1456 ( .A(n3796), .Y(n5960) );
CLKINVX6TS U1457 ( .A(n2786), .Y(n1708) );
INVX4TS U1458 ( .A(n1007), .Y(n2254) );
INVX6TS U1459 ( .A(n3220), .Y(n1872) );
NOR2BX2TS U1460 ( .AN(n5083), .B(n5082), .Y(n6558) );
NAND2X1TS U1461 ( .A(n7011), .B(n825), .Y(n4707) );
NAND2X1TS U1462 ( .A(n6736), .B(n825), .Y(n4806) );
NAND2X4TS U1463 ( .A(n2738), .B(n1324), .Y(n2788) );
NAND2X1TS U1464 ( .A(n1451), .B(n1812), .Y(n1500) );
BUFX6TS U1465 ( .A(n6065), .Y(n6019) );
BUFX8TS U1466 ( .A(n3129), .Y(n2937) );
BUFX6TS U1467 ( .A(n4749), .Y(n7013) );
BUFX6TS U1468 ( .A(n4675), .Y(n5922) );
BUFX6TS U1469 ( .A(n5081), .Y(n6984) );
BUFX6TS U1470 ( .A(n6454), .Y(n6440) );
INVX8TS U1471 ( .A(n3005), .Y(n2944) );
NAND2BX2TS U1472 ( .AN(n4742), .B(n4743), .Y(n6237) );
NAND2X6TS U1473 ( .A(n3031), .B(n1880), .Y(n1882) );
BUFX4TS U1474 ( .A(n5045), .Y(n6841) );
BUFX6TS U1475 ( .A(n1029), .Y(n2198) );
INVX3TS U1476 ( .A(n1352), .Y(n861) );
INVX4TS U1477 ( .A(n5877), .Y(n5660) );
INVX8TS U1478 ( .A(n2786), .Y(n2653) );
BUFX3TS U1479 ( .A(n1029), .Y(n7232) );
BUFX3TS U1480 ( .A(n6817), .Y(n6905) );
BUFX4TS U1481 ( .A(n732), .Y(n857) );
INVX4TS U1482 ( .A(n6281), .Y(n6392) );
INVX2TS U1483 ( .A(n2941), .Y(n2713) );
INVX8TS U1484 ( .A(n1718), .Y(n3403) );
INVX2TS U1485 ( .A(n6693), .Y(n823) );
BUFX6TS U1486 ( .A(n6589), .Y(n7045) );
CLKINVX6TS U1487 ( .A(n2876), .Y(n1740) );
INVX8TS U1488 ( .A(n2942), .Y(n2294) );
INVX6TS U1489 ( .A(n3005), .Y(n2264) );
BUFX12TS U1490 ( .A(n2215), .Y(n3301) );
CLKXOR2X2TS U1491 ( .A(n1619), .B(n1647), .Y(n1620) );
AOI21X1TS U1492 ( .A0(n2002), .A1(n2237), .B0(n2243), .Y(n1968) );
AOI21X1TS U1493 ( .A0(n6429), .A1(n6420), .B0(n6423), .Y(n6341) );
NOR2X2TS U1494 ( .A(n6279), .B(n6395), .Y(n6284) );
BUFX3TS U1495 ( .A(n5650), .Y(n5661) );
BUFX4TS U1496 ( .A(n4805), .Y(n6442) );
CLKINVX6TS U1497 ( .A(n3051), .Y(n2518) );
BUFX4TS U1498 ( .A(n5668), .Y(n5975) );
AOI21X1TS U1499 ( .A0(n2002), .A1(n2001), .B0(n2000), .Y(n2003) );
OAI21X1TS U1500 ( .A0(n3822), .A1(n6248), .B0(n6249), .Y(n3823) );
INVX12TS U1501 ( .A(n2281), .Y(n819) );
INVX6TS U1502 ( .A(n1876), .Y(n3051) );
NOR2X1TS U1503 ( .A(n1618), .B(n1617), .Y(n1619) );
NAND2X1TS U1504 ( .A(n1125), .B(n6230), .Y(n1126) );
NOR2X1TS U1505 ( .A(n1378), .B(n1377), .Y(n1380) );
NOR2X1TS U1506 ( .A(n5935), .B(n5942), .Y(n5455) );
BUFX6TS U1507 ( .A(n5045), .Y(n6999) );
NAND2XLTS U1508 ( .A(n3796), .B(n824), .Y(n3797) );
INVX4TS U1509 ( .A(n5789), .Y(n5964) );
BUFX3TS U1510 ( .A(n1112), .Y(n6889) );
BUFX3TS U1511 ( .A(n5748), .Y(n5742) );
INVX2TS U1512 ( .A(n5974), .Y(n5667) );
INVX4TS U1513 ( .A(n1518), .Y(n2786) );
NAND2X4TS U1514 ( .A(n6322), .B(n1216), .Y(n6280) );
NAND2BX2TS U1515 ( .AN(n4736), .B(n4737), .Y(n4749) );
BUFX3TS U1516 ( .A(n1080), .Y(n7005) );
INVX3TS U1517 ( .A(n2222), .Y(n2534) );
OAI21X2TS U1518 ( .A0(n1211), .A1(n6361), .B0(n1210), .Y(n1212) );
INVX4TS U1519 ( .A(n1794), .Y(n3005) );
INVX4TS U1520 ( .A(n1747), .Y(n2942) );
NAND2X2TS U1521 ( .A(n2278), .B(n2284), .Y(n2260) );
AOI21X2TS U1522 ( .A0(n2279), .A1(n2284), .B0(n2258), .Y(n2259) );
NOR2X1TS U1523 ( .A(n4502), .B(n4505), .Y(n4514) );
BUFX12TS U1524 ( .A(n2694), .Y(n3031) );
BUFX3TS U1525 ( .A(n4717), .Y(n6788) );
NAND2X2TS U1526 ( .A(n1697), .B(n1754), .Y(n1676) );
NAND2X2TS U1527 ( .A(n5935), .B(n5942), .Y(n5464) );
NAND2X2TS U1528 ( .A(n5939), .B(n5775), .Y(n5406) );
NOR2X2TS U1529 ( .A(n5771), .B(n5775), .Y(n3848) );
CLKXOR2X4TS U1530 ( .A(n1449), .B(n1448), .Y(n1007) );
BUFX3TS U1531 ( .A(n1424), .Y(n3220) );
BUFX3TS U1532 ( .A(n6644), .Y(n6992) );
NOR2X2TS U1533 ( .A(n1250), .B(n1249), .Y(n5398) );
NAND2X1TS U1534 ( .A(n4491), .B(n4490), .Y(n4504) );
NAND2X1TS U1535 ( .A(n1449), .B(n1448), .Y(n1415) );
BUFX6TS U1536 ( .A(Op_MY[48]), .Y(n5939) );
NOR2X1TS U1537 ( .A(n1417), .B(n3652), .Y(n1419) );
BUFX6TS U1538 ( .A(Op_MY[49]), .Y(n5775) );
NOR2X1TS U1539 ( .A(n3634), .B(n1401), .Y(n1403) );
BUFX6TS U1540 ( .A(Op_MY[47]), .Y(n5942) );
BUFX3TS U1541 ( .A(n1056), .Y(n6683) );
NOR2X1TS U1542 ( .A(n1797), .B(n1796), .Y(n1799) );
INVX3TS U1543 ( .A(n1755), .Y(n1697) );
NAND2BX1TS U1544 ( .AN(n1006), .B(n3652), .Y(n5766) );
OR2X2TS U1545 ( .A(Op_MY[51]), .B(Op_MY[24]), .Y(n2284) );
NOR2BX2TS U1546 ( .AN(n1114), .B(n1113), .Y(n6620) );
NOR2BX2TS U1547 ( .AN(n4709), .B(n4710), .Y(n6512) );
BUFX6TS U1548 ( .A(n1112), .Y(n6750) );
BUFX6TS U1549 ( .A(n4717), .Y(n6966) );
INVX1TS U1550 ( .A(n1965), .Y(n1976) );
NAND2X4TS U1551 ( .A(n1209), .B(n6420), .Y(n1211) );
INVX2TS U1552 ( .A(n1356), .Y(n947) );
NAND3X2TS U1553 ( .A(n3652), .B(n766), .C(n1006), .Y(n5789) );
NAND2BX2TS U1554 ( .AN(n3638), .B(n3639), .Y(n5861) );
NAND2X2TS U1555 ( .A(n2218), .B(Op_MX[25]), .Y(n2219) );
INVX12TS U1556 ( .A(n2281), .Y(n817) );
NAND2X4TS U1557 ( .A(n6391), .B(n3818), .Y(n3816) );
OAI21X2TS U1558 ( .A0(n1365), .A1(n1362), .B0(n1363), .Y(n1351) );
NAND2X4TS U1559 ( .A(n6457), .B(n1207), .Y(n6362) );
NAND2X2TS U1560 ( .A(n1370), .B(n1369), .Y(n1371) );
INVX2TS U1561 ( .A(n6693), .Y(n822) );
NOR2X2TS U1562 ( .A(n1353), .B(n3720), .Y(n1354) );
CLKXOR2X4TS U1563 ( .A(Op_MX[51]), .B(Op_MX[24]), .Y(n2204) );
XNOR2X2TS U1564 ( .A(Op_MY[18]), .B(Op_MY[19]), .Y(n4735) );
BUFX4TS U1565 ( .A(Op_MY[50]), .Y(n5771) );
XOR2X2TS U1566 ( .A(Op_MY[19]), .B(Op_MY[20]), .Y(n4737) );
OAI21X2TS U1567 ( .A0(n6819), .A1(n764), .B0(n1052), .Y(n1053) );
BUFX4TS U1568 ( .A(n6644), .Y(n6973) );
XOR2X2TS U1569 ( .A(Op_MX[48]), .B(Op_MX[49]), .Y(n3612) );
NAND2X2TS U1570 ( .A(n3619), .B(n3724), .Y(n4972) );
XNOR2X2TS U1571 ( .A(n1417), .B(n1414), .Y(n1416) );
XNOR2X2TS U1572 ( .A(n1394), .B(n1402), .Y(n1395) );
CLKXOR2X2TS U1573 ( .A(n1054), .B(n1073), .Y(n1055) );
OAI21X1TS U1574 ( .A0(n1672), .A1(n1753), .B0(n1757), .Y(n1699) );
NAND2X2TS U1575 ( .A(n6023), .B(n6038), .Y(n1251) );
NOR2X1TS U1576 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n1414) );
NAND2X1TS U1577 ( .A(Op_MX[22]), .B(Op_MX[49]), .Y(n2072) );
NAND2X1TS U1578 ( .A(n3953), .B(n3952), .Y(n4197) );
NAND2X1TS U1579 ( .A(n3941), .B(n3940), .Y(n4186) );
NOR2X1TS U1580 ( .A(n1711), .B(n4655), .Y(n1712) );
INVX6TS U1581 ( .A(n773), .Y(n829) );
INVX6TS U1582 ( .A(n6053), .Y(n4966) );
AND2X2TS U1583 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n1448) );
INVX6TS U1584 ( .A(n8444), .Y(n7503) );
NOR2X2TS U1585 ( .A(Op_MX[17]), .B(Op_MX[16]), .Y(n6333) );
BUFX8TS U1586 ( .A(Op_MY[46]), .Y(n5935) );
NOR2X4TS U1587 ( .A(n3704), .B(n3706), .Y(n1225) );
NAND2BX2TS U1588 ( .AN(n1114), .B(n1115), .Y(n6644) );
NOR2X1TS U1589 ( .A(n4591), .B(n4581), .Y(n4474) );
NAND2X2TS U1590 ( .A(Op_MY[51]), .B(Op_MY[24]), .Y(n2283) );
NAND2BX2TS U1591 ( .AN(n4709), .B(n4711), .Y(n4717) );
NAND2X4TS U1592 ( .A(n1951), .B(n1956), .Y(n2238) );
NAND2X2TS U1593 ( .A(n1744), .B(n1743), .Y(n1745) );
NOR2X2TS U1594 ( .A(n6945), .B(Op_MX[16]), .Y(n6414) );
NOR2X6TS U1595 ( .A(n6425), .B(n6432), .Y(n1209) );
NAND2X2TS U1596 ( .A(n1339), .B(n1338), .Y(n1370) );
BUFX8TS U1597 ( .A(n1130), .Y(n6681) );
XOR2X1TS U1598 ( .A(Op_MX[44]), .B(Op_MX[45]), .Y(n1878) );
XOR2X2TS U1599 ( .A(Op_MX[12]), .B(Op_MX[39]), .Y(n1617) );
BUFX6TS U1600 ( .A(n5087), .Y(n6796) );
NAND2X2TS U1601 ( .A(n833), .B(n6959), .Y(n6272) );
NAND2X1TS U1602 ( .A(n828), .B(n5963), .Y(n5602) );
NOR2X4TS U1603 ( .A(n6231), .B(n1205), .Y(n6457) );
OAI21X1TS U1604 ( .A0(n4123), .A1(n4122), .B0(n4121), .Y(n4439) );
BUFX12TS U1605 ( .A(Op_MY[43]), .Y(n6038) );
NOR2X4TS U1606 ( .A(n3812), .B(n6300), .Y(n6391) );
BUFX6TS U1607 ( .A(Op_MY[45]), .Y(n5906) );
NAND2X1TS U1608 ( .A(Op_MX[18]), .B(Op_MX[45]), .Y(n1874) );
NAND2X1TS U1609 ( .A(Op_MX[10]), .B(Op_MX[37]), .Y(n1358) );
NAND2X1TS U1610 ( .A(Op_MX[8]), .B(Op_MX[35]), .Y(n1338) );
NAND2X1TS U1611 ( .A(n4109), .B(n4108), .Y(n4122) );
NAND2X1TS U1612 ( .A(n4462), .B(n4461), .Y(n4592) );
NAND2X1TS U1613 ( .A(n4129), .B(n4128), .Y(n4553) );
NAND2X1TS U1614 ( .A(n4467), .B(n4466), .Y(n4587) );
NAND2X1TS U1615 ( .A(n4092), .B(n4091), .Y(n4136) );
INVX6TS U1616 ( .A(n1020), .Y(n7500) );
NOR2X4TS U1617 ( .A(n4711), .B(n4709), .Y(n5087) );
OAI21X2TS U1618 ( .A0(Op_MX[8]), .A1(Op_MX[35]), .B0(Op_MX[7]), .Y(n1339) );
NAND2X2TS U1619 ( .A(n4001), .B(n4000), .Y(n4378) );
NOR2X2TS U1620 ( .A(n4453), .B(n4452), .Y(n4568) );
INVX8TS U1621 ( .A(n1009), .Y(n7490) );
NOR2X2TS U1622 ( .A(Op_MX[5]), .B(Op_MX[32]), .Y(n1396) );
NOR2X2TS U1623 ( .A(Op_MX[15]), .B(Op_MX[42]), .Y(n1742) );
NAND2X2TS U1624 ( .A(n3986), .B(n3985), .Y(n4344) );
NAND2X2TS U1625 ( .A(n3972), .B(n3971), .Y(n4365) );
NAND2X2TS U1626 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n6415) );
NAND2X2TS U1627 ( .A(Op_MX[17]), .B(Op_MX[16]), .Y(n6334) );
NAND2X2TS U1628 ( .A(Op_MX[51]), .B(Op_MX[24]), .Y(n2196) );
NOR2X6TS U1629 ( .A(n6785), .B(n7056), .Y(n6425) );
NOR2X4TS U1630 ( .A(n1144), .B(n1146), .Y(n1120) );
NOR2X4TS U1631 ( .A(n5892), .B(n5901), .Y(n3706) );
NOR2X2TS U1632 ( .A(n3652), .B(n1006), .Y(n3662) );
NOR2X2TS U1633 ( .A(n4467), .B(n4466), .Y(n4586) );
NAND2BX2TS U1634 ( .AN(n1058), .B(n1059), .Y(n1130) );
BUFX6TS U1635 ( .A(Op_MY[42]), .Y(n6023) );
NAND2X4TS U1636 ( .A(n7079), .B(n826), .Y(n6230) );
NAND2X2TS U1637 ( .A(n1315), .B(n1314), .Y(n1398) );
OR2X4TS U1638 ( .A(n6584), .B(n6897), .Y(n1000) );
BUFX3TS U1639 ( .A(Op_MY[35]), .Y(n7508) );
XOR2X2TS U1640 ( .A(Op_MY[10]), .B(Op_MY[11]), .Y(n5036) );
BUFX12TS U1641 ( .A(Op_MY[40]), .Y(n5963) );
NOR2X2TS U1642 ( .A(n4470), .B(n4469), .Y(n4478) );
NOR2X6TS U1643 ( .A(n6952), .B(n6484), .Y(n6395) );
BUFX4TS U1644 ( .A(Op_MX[24]), .Y(n6959) );
BUFX4TS U1645 ( .A(Op_MY[38]), .Y(n6016) );
NAND2X4TS U1646 ( .A(n902), .B(n3632), .Y(n3647) );
NOR2X6TS U1647 ( .A(n7008), .B(n6753), .Y(n6448) );
XOR2X2TS U1648 ( .A(Op_MX[32]), .B(Op_MX[33]), .Y(n3634) );
NAND2X2TS U1649 ( .A(n6829), .B(n6930), .Y(n6315) );
NOR2X4TS U1650 ( .A(n1777), .B(n1780), .Y(n1951) );
NOR2X2TS U1651 ( .A(n4455), .B(n4454), .Y(n4578) );
BUFX6TS U1652 ( .A(Op_MX[22]), .Y(n6484) );
BUFX3TS U1653 ( .A(Op_MY[29]), .Y(n8374) );
NOR2X4TS U1654 ( .A(n3974), .B(n3973), .Y(n4336) );
NOR2X4TS U1655 ( .A(Op_MY[43]), .B(Op_MY[16]), .Y(n1777) );
NOR2X4TS U1656 ( .A(n3972), .B(n3971), .Y(n4364) );
NAND2X2TS U1657 ( .A(n4057), .B(n4056), .Y(n4280) );
BUFX8TS U1658 ( .A(Op_MX[11]), .Y(n7008) );
NAND2X6TS U1659 ( .A(Op_MY[43]), .B(Op_MY[16]), .Y(n1779) );
NAND2X2TS U1660 ( .A(Op_MY[47]), .B(Op_MY[20]), .Y(n1975) );
NAND2X2TS U1661 ( .A(n4069), .B(n4068), .Y(n4369) );
BUFX6TS U1662 ( .A(Op_MX[8]), .Y(n7079) );
NOR2X1TS U1663 ( .A(n4001), .B(n4000), .Y(n4357) );
NAND2X2TS U1664 ( .A(Op_MY[50]), .B(Op_MY[23]), .Y(n2239) );
CLKXOR2X2TS U1665 ( .A(Op_MY[5]), .B(Op_MY[4]), .Y(n1059) );
INVX12TS U1666 ( .A(n6974), .Y(n7040) );
NAND2X4TS U1667 ( .A(n6897), .B(n905), .Y(n1074) );
BUFX16TS U1668 ( .A(Op_MX[9]), .Y(n6958) );
BUFX16TS U1669 ( .A(Op_MX[12]), .Y(n7068) );
BUFX12TS U1670 ( .A(Op_MX[13]), .Y(n7056) );
NAND2X2TS U1671 ( .A(n6897), .B(Op_MX[3]), .Y(n1075) );
NOR2X2TS U1672 ( .A(n4069), .B(n4068), .Y(n4324) );
BUFX6TS U1673 ( .A(Op_MX[15]), .Y(n6945) );
BUFX6TS U1674 ( .A(Op_MX[10]), .Y(n910) );
BUFX12TS U1675 ( .A(Op_MY[34]), .Y(n5901) );
NOR2X4TS U1676 ( .A(Op_MY[50]), .B(Op_MY[23]), .Y(n2241) );
BUFX6TS U1677 ( .A(Op_MX[1]), .Y(n6243) );
NOR2X4TS U1678 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n2236) );
NAND2X2TS U1679 ( .A(n6584), .B(n6863), .Y(n1093) );
BUFX6TS U1680 ( .A(Op_MX[20]), .Y(n877) );
NOR2X2TS U1681 ( .A(n6874), .B(n6863), .Y(n1063) );
NAND2X2TS U1682 ( .A(n6874), .B(n6863), .Y(n1064) );
BUFX4TS U1683 ( .A(Op_MX[10]), .Y(n6753) );
BUFX12TS U1684 ( .A(Op_MX[11]), .Y(n827) );
NAND2X1TS U1685 ( .A(n8414), .B(n826), .Y(n1147) );
CMPR32X2TS U1686 ( .A(Sgf_operation_ODD1_Q_middle[42]), .B(n7612), .C(n4449),
.CO(n4456), .S(n4455) );
CMPR32X2TS U1687 ( .A(Sgf_operation_ODD1_Q_middle[25]), .B(n3939), .C(n3938),
.CO(n3940), .S(n3935) );
INVX6TS U1688 ( .A(n800), .Y(n826) );
CMPR32X2TS U1689 ( .A(Sgf_operation_ODD1_Q_middle[26]), .B(n3937), .C(n3936),
.CO(n3942), .S(n3941) );
OAI21X2TS U1690 ( .A0(Op_MX[12]), .A1(Op_MX[39]), .B0(Op_MX[11]), .Y(n1614)
);
NAND2X2TS U1691 ( .A(Op_MX[12]), .B(Op_MX[39]), .Y(n1613) );
INVX3TS U1692 ( .A(n755), .Y(n756) );
NAND2X4TS U1693 ( .A(n1453), .B(n1458), .Y(n1755) );
BUFX12TS U1694 ( .A(Op_MX[4]), .Y(n6863) );
BUFX6TS U1695 ( .A(Op_MX[0]), .Y(n825) );
BUFX12TS U1696 ( .A(Op_MX[14]), .Y(n8412) );
BUFX6TS U1697 ( .A(Op_MX[2]), .Y(n6897) );
BUFX6TS U1698 ( .A(Op_MX[1]), .Y(n905) );
NOR2X4TS U1699 ( .A(n1668), .B(n1671), .Y(n1754) );
NAND2X4TS U1700 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n1363) );
NAND2X4TS U1701 ( .A(Op_MY[41]), .B(Op_MY[14]), .Y(n1757) );
NOR2X6TS U1702 ( .A(n755), .B(Op_MY[5]), .Y(n1389) );
NOR2X6TS U1703 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n1327) );
NOR2X6TS U1704 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1671) );
NOR2X6TS U1705 ( .A(Op_MY[38]), .B(Op_MY[11]), .Y(n1455) );
NOR2X6TS U1706 ( .A(Op_MY[28]), .B(Op_MY[1]), .Y(n1373) );
NAND2X2TS U1707 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1456) );
NOR2X6TS U1708 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n1362) );
NAND2X2TS U1709 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1669) );
NAND2X2TS U1710 ( .A(Op_MY[38]), .B(Op_MY[11]), .Y(n1454) );
NOR2X4TS U1711 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1668) );
NOR2X4TS U1712 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1336) );
NOR2X4TS U1713 ( .A(Op_MY[42]), .B(Op_MY[15]), .Y(n1758) );
INVX2TS U1714 ( .A(n1754), .Y(n1673) );
NAND2X2TS U1715 ( .A(Op_MY[42]), .B(Op_MY[15]), .Y(n1756) );
NAND2X1TS U1716 ( .A(n1441), .B(n1456), .Y(n1437) );
XNOR2X2TS U1717 ( .A(n741), .B(n4730), .Y(n2582) );
NOR2X2TS U1718 ( .A(Op_MX[13]), .B(Op_MX[40]), .Y(n1648) );
NOR2X2TS U1719 ( .A(n877), .B(n6952), .Y(n6300) );
INVX4TS U1720 ( .A(n6361), .Y(n6429) );
OAI22X1TS U1721 ( .A0(n2087), .A1(n3188), .B0(n2086), .B1(n1992), .Y(n2089)
);
BUFX6TS U1722 ( .A(n1029), .Y(n2223) );
AOI22X1TS U1723 ( .A0(n7010), .A1(n5041), .B0(n6870), .B1(n905), .Y(n4705)
);
NOR2X2TS U1724 ( .A(n8414), .B(n826), .Y(n1146) );
AO21X2TS U1725 ( .A0(n2788), .A1(n2787), .B0(n2786), .Y(n2828) );
XNOR2X2TS U1726 ( .A(n920), .B(n2720), .Y(n2499) );
XNOR2X1TS U1727 ( .A(n3330), .B(n2881), .Y(n2305) );
INVX4TS U1728 ( .A(n3220), .Y(n2822) );
BUFX8TS U1729 ( .A(n1785), .Y(n922) );
CLKXOR2X2TS U1730 ( .A(n1354), .B(n1369), .Y(n1355) );
AOI222X1TS U1731 ( .A0(n6964), .A1(n6884), .B0(n6786), .B1(n7020), .C0(n6531), .C1(n7018), .Y(n4722) );
OAI21X2TS U1732 ( .A0(n6461), .A1(n6342), .B0(n6341), .Y(n6345) );
OAI21X1TS U1733 ( .A0(n4484), .A1(n4483), .B0(n4482), .Y(n4485) );
XNOR2X1TS U1734 ( .A(n3176), .B(n2944), .Y(n2652) );
XNOR2X1TS U1735 ( .A(n918), .B(n2720), .Y(n2588) );
XNOR2X2TS U1736 ( .A(n917), .B(n3383), .Y(n2757) );
INVX2TS U1737 ( .A(n3176), .Y(n2938) );
XNOR2X2TS U1738 ( .A(n3410), .B(n3275), .Y(n2898) );
XNOR2X2TS U1739 ( .A(n3276), .B(n3190), .Y(n3229) );
XNOR2X1TS U1740 ( .A(n3276), .B(n2822), .Y(n2882) );
BUFX6TS U1741 ( .A(n1462), .Y(n3285) );
NAND2X1TS U1742 ( .A(n6316), .B(n6315), .Y(n6317) );
AOI222X1TS U1743 ( .A0(n6964), .A1(n8412), .B0(n6786), .B1(n7069), .C0(n6805), .C1(n7068), .Y(n6532) );
CLKINVX6TS U1744 ( .A(n6019), .Y(n880) );
NOR2X2TS U1745 ( .A(n4665), .B(n4664), .Y(n4675) );
INVX4TS U1746 ( .A(n5594), .Y(n5997) );
BUFX12TS U1747 ( .A(n1973), .Y(n919) );
OAI22X1TS U1748 ( .A0(n2480), .A1(n3279), .B0(n2520), .B1(n3401), .Y(n2486)
);
ADDFX2TS U1749 ( .A(n2516), .B(n2515), .CI(n2514), .CO(n2542), .S(n2507) );
OAI22X1TS U1750 ( .A0(n2302), .A1(n2368), .B0(n2311), .B1(n2510), .Y(n2310)
);
OAI22X1TS U1751 ( .A0(n2305), .A1(n2016), .B0(n2335), .B1(n3222), .Y(n2340)
);
XNOR2X1TS U1752 ( .A(n3384), .B(n2583), .Y(n2365) );
XNOR2X1TS U1753 ( .A(n919), .B(n2287), .Y(n2009) );
OAI22X1TS U1754 ( .A0(n2029), .A1(n2100), .B0(n2039), .B1(n2772), .Y(n2125)
);
ADDFX2TS U1755 ( .A(n1887), .B(n1886), .CI(n1885), .CO(n2026), .S(n1893) );
XNOR2X1TS U1756 ( .A(n3223), .B(n1872), .Y(n1832) );
OAI21XLTS U1757 ( .A0(n7086), .A1(n6872), .B0(n6504), .Y(n6505) );
BUFX3TS U1758 ( .A(n6995), .Y(n6843) );
NAND2X1TS U1759 ( .A(n1148), .B(n1147), .Y(n1149) );
AOI22X1TS U1760 ( .A0(n5701), .A1(n902), .B0(n5668), .B1(n4966), .Y(n3695)
);
CLKINVX3TS U1761 ( .A(n5711), .Y(n5732) );
OAI22X1TS U1762 ( .A0(n2958), .A1(n3350), .B0(n2977), .B1(n3430), .Y(n2985)
);
BUFX3TS U1763 ( .A(n2097), .Y(n3432) );
OAI22X1TS U1764 ( .A0(n3289), .A1(n935), .B0(n3339), .B1(n3413), .Y(n3327)
);
OAI22X1TS U1765 ( .A0(n2774), .A1(n934), .B0(n2818), .B1(n3344), .Y(n2831)
);
BUFX6TS U1766 ( .A(n1751), .Y(n2839) );
BUFX8TS U1767 ( .A(n1478), .Y(n3178) );
BUFX12TS U1768 ( .A(n6239), .Y(n6921) );
AOI222X1TS U1769 ( .A0(n6870), .A1(n6847), .B0(n6834), .B1(n6846), .C0(n6491), .C1(n6930), .Y(n6487) );
BUFX3TS U1770 ( .A(n4749), .Y(n6792) );
OAI21X1TS U1771 ( .A0(n6984), .A1(n764), .B0(n5039), .Y(n5040) );
BUFX4TS U1772 ( .A(n3880), .Y(n6060) );
BUFX4TS U1773 ( .A(n4672), .Y(n6011) );
CLKINVX3TS U1774 ( .A(n5493), .Y(n5884) );
CLKINVX3TS U1775 ( .A(n973), .Y(n5902) );
CLKINVX3TS U1776 ( .A(n5789), .Y(n6077) );
OAI21XLTS U1777 ( .A0(n979), .A1(n6014), .B0(n5558), .Y(n5559) );
BUFX3TS U1778 ( .A(n5701), .Y(n5976) );
ADDHX1TS U1779 ( .A(n1653), .B(n1652), .CO(n1720), .S(n1666) );
XNOR2X1TS U1780 ( .A(n3223), .B(n1611), .Y(n1439) );
CLKXOR2X2TS U1781 ( .A(n4804), .B(n7076), .Y(n5208) );
XNOR2X2TS U1782 ( .A(n1150), .B(n1149), .Y(n1151) );
OAI21XLTS U1783 ( .A0(n6036), .A1(n5978), .B0(n5699), .Y(n5700) );
OAI21XLTS U1784 ( .A0(n5931), .A1(n6007), .B0(n5616), .Y(n5617) );
INVX2TS U1785 ( .A(n4359), .Y(n4361) );
NAND2X1TS U1786 ( .A(n3990), .B(n3989), .Y(n4353) );
OAI21X2TS U1787 ( .A0(n4307), .A1(n4306), .B0(n4305), .Y(n4313) );
NAND2X1TS U1788 ( .A(n4536), .B(n4535), .Y(n4538) );
OAI21X2TS U1789 ( .A0(n4488), .A1(n4515), .B0(n4522), .Y(n4495) );
AOI21X2TS U1790 ( .A0(n8004), .A1(n4423), .B0(n4422), .Y(n4424) );
NAND2X1TS U1791 ( .A(n3957), .B(n3956), .Y(n4206) );
OAI22X1TS U1792 ( .A0(n2991), .A1(n3415), .B0(n2998), .B1(n3413), .Y(n3001)
);
BUFX12TS U1793 ( .A(n2946), .Y(n3089) );
OAI22X1TS U1794 ( .A0(n1809), .A1(n2730), .B0(n1808), .B1(n2303), .Y(n1860)
);
INVX6TS U1795 ( .A(n6253), .Y(n6967) );
BUFX4TS U1796 ( .A(n6237), .Y(n7062) );
XOR2X1TS U1797 ( .A(n7065), .B(n7064), .Y(n7066) );
OAI21X1TS U1798 ( .A0(n729), .A1(n6792), .B0(n6494), .Y(n6495) );
OAI21X1TS U1799 ( .A0(n6918), .A1(n6841), .B0(n6598), .Y(n6599) );
BUFX3TS U1800 ( .A(n6644), .Y(n7038) );
OAI21XLTS U1801 ( .A0(n6008), .A1(n6067), .B0(n5972), .Y(n5973) );
OAI21XLTS U1802 ( .A0(n6008), .A1(n6014), .B0(n5552), .Y(n5553) );
XNOR2X1TS U1803 ( .A(n859), .B(n2469), .Y(n1511) );
XOR2X1TS U1804 ( .A(n6744), .B(n835), .Y(mult_x_24_n1504) );
OAI21XLTS U1805 ( .A0(n7086), .A1(n7049), .B0(n6609), .Y(n6610) );
OAI21X1TS U1806 ( .A0(n8283), .A1(n8289), .B0(n8284), .Y(n4386) );
NOR2XLTS U1807 ( .A(n5057), .B(n5056), .Y(n5058) );
NOR2X2TS U1808 ( .A(n7833), .B(n7835), .Y(n4624) );
OAI21X2TS U1809 ( .A0(n8001), .A1(n4425), .B0(n4424), .Y(n4426) );
NOR2XLTS U1810 ( .A(n8451), .B(n8449), .Y(n7515) );
OAI21X1TS U1811 ( .A0(n3570), .A1(n7301), .B0(n3569), .Y(n3571) );
OAI21XLTS U1812 ( .A0(n6993), .A1(n7074), .B0(n6376), .Y(n6377) );
INVX2TS U1813 ( .A(n1017), .Y(n7087) );
CLKINVX3TS U1814 ( .A(n1017), .Y(n7064) );
XOR2X1TS U1815 ( .A(n6483), .B(n6861), .Y(mult_x_24_n1463) );
INVX6TS U1816 ( .A(n5468), .Y(n5896) );
CLKINVX3TS U1817 ( .A(n1035), .Y(n5926) );
XOR2X1TS U1818 ( .A(n5555), .B(n737), .Y(mult_x_23_n1335) );
OAI21XLTS U1819 ( .A0(n5931), .A1(n5978), .B0(n5930), .Y(n5932) );
CLKINVX3TS U1820 ( .A(n1038), .Y(n7018) );
XOR2X1TS U1821 ( .A(n4209), .B(n4208), .Y(n4407) );
NOR2XLTS U1822 ( .A(Sgf_normalized_result[4]), .B(Sgf_normalized_result[5]),
.Y(n7527) );
XNOR2X2TS U1823 ( .A(n4340), .B(n4339), .Y(n4388) );
NAND2X1TS U1824 ( .A(n5059), .B(n5058), .Y(n7644) );
CLKXOR2X2TS U1825 ( .A(n4590), .B(n4589), .Y(n4614) );
NOR2X1TS U1826 ( .A(n4398), .B(Sgf_operation_ODD1_Q_right[50]), .Y(n8340) );
OA21X1TS U1827 ( .A0(n3591), .A1(n3597), .B0(n3598), .Y(n792) );
INVX4TS U1828 ( .A(n4825), .Y(n7295) );
AOI21X1TS U1829 ( .A0(n3807), .A1(n3806), .B0(n3805), .Y(n5118) );
NAND2X2TS U1830 ( .A(n1182), .B(n7094), .Y(n1184) );
CMPR42X1TS U1831 ( .A(mult_x_23_n1277), .B(mult_x_23_n1329), .C(
mult_x_23_n755), .D(mult_x_23_n765), .ICI(mult_x_23_n762), .S(
mult_x_23_n753), .ICO(mult_x_23_n751), .CO(mult_x_23_n752) );
OAI21X1TS U1832 ( .A0(n7424), .A1(n7423), .B0(n7422), .Y(n7425) );
NOR2X2TS U1833 ( .A(n7416), .B(n7345), .Y(n7347) );
NOR2X4TS U1834 ( .A(n2450), .B(n2449), .Y(n7437) );
INVX2TS U1835 ( .A(n7151), .Y(n2186) );
OA21X2TS U1836 ( .A0(n7196), .A1(n1569), .B0(n7192), .Y(n1570) );
NOR2X6TS U1837 ( .A(mult_x_24_n845), .B(mult_x_24_n856), .Y(n5232) );
INVX2TS U1838 ( .A(n845), .Y(n847) );
NAND2X1TS U1839 ( .A(n4621), .B(Sgf_operation_ODD1_Q_left[22]), .Y(n7846) );
INVX2TS U1840 ( .A(n7919), .Y(n7921) );
NOR2X2TS U1841 ( .A(n4412), .B(Sgf_operation_ODD1_Q_left[4]), .Y(n8099) );
INVX2TS U1842 ( .A(n7652), .Y(n7653) );
NAND2X2TS U1843 ( .A(n7480), .B(n8446), .Y(n7533) );
NOR2X6TS U1844 ( .A(n3776), .B(n5154), .Y(n3778) );
NOR2X4TS U1845 ( .A(n4908), .B(n4912), .Y(n3765) );
NOR2X4TS U1846 ( .A(mult_x_23_n813), .B(mult_x_23_n823), .Y(n5300) );
NAND2X4TS U1847 ( .A(n3526), .B(n3525), .Y(n7405) );
INVX2TS U1848 ( .A(n4692), .Y(n7321) );
NAND2X1TS U1849 ( .A(n7417), .B(n7347), .Y(n7349) );
NAND2X2TS U1850 ( .A(n2190), .B(n2189), .Y(n7138) );
OAI21XLTS U1851 ( .A0(n7397), .A1(n7396), .B0(n7395), .Y(n7398) );
INVX2TS U1852 ( .A(n1733), .Y(n7170) );
OR2X1TS U1853 ( .A(n1516), .B(n1515), .Y(n7210) );
INVX2TS U1854 ( .A(n6136), .Y(n6132) );
NOR2XLTS U1855 ( .A(n7690), .B(n8464), .Y(n7681) );
OAI21XLTS U1856 ( .A0(n8305), .A1(n8301), .B0(n8302), .Y(n8299) );
NAND2X2TS U1857 ( .A(n7536), .B(n7535), .Y(n7547) );
INVX2TS U1858 ( .A(n7860), .Y(n7875) );
INVX4TS U1859 ( .A(n8087), .Y(n8103) );
NOR2XLTS U1860 ( .A(n7671), .B(n8451), .Y(n7665) );
NOR2XLTS U1861 ( .A(n8015), .B(n8467), .Y(n7995) );
NAND2X4TS U1862 ( .A(n2921), .B(n7373), .Y(n7287) );
OR2X4TS U1863 ( .A(n7330), .B(n3541), .Y(n1023) );
OA21X2TS U1864 ( .A0(n5164), .A1(n3903), .B0(n3902), .Y(n3904) );
NAND2X4TS U1865 ( .A(n1939), .B(n1938), .Y(n7385) );
NAND2X1TS U1866 ( .A(mult_x_24_n698), .B(mult_x_24_n701), .Y(n5022) );
NAND2X2TS U1867 ( .A(n1276), .B(n1279), .Y(n5027) );
OR2X1TS U1868 ( .A(mult_x_23_n639), .B(mult_x_23_n641), .Y(n5273) );
AOI21X1TS U1869 ( .A0(n5186), .A1(n5185), .B0(n5184), .Y(n5187) );
AOI21X1TS U1870 ( .A0(n4790), .A1(n4779), .B0(n4778), .Y(n4780) );
INVX2TS U1871 ( .A(n7127), .Y(n7436) );
OAI21XLTS U1872 ( .A0(n7160), .A1(n7162), .B0(n7161), .Y(n7167) );
BUFX3TS U1873 ( .A(n1029), .Y(n929) );
BUFX4TS U1874 ( .A(n6092), .Y(n4893) );
OAI21XLTS U1875 ( .A0(n6951), .A1(n6947), .B0(n6948), .Y(n6145) );
XNOR2X2TS U1876 ( .A(n7685), .B(n7684), .Y(n7686) );
XNOR2X1TS U1877 ( .A(n8067), .B(n8066), .Y(n8068) );
INVX2TS U1878 ( .A(n8433), .Y(n8186) );
INVX4TS U1879 ( .A(n6093), .Y(n7108) );
NAND2X2TS U1880 ( .A(n7485), .B(FS_Module_state_reg[3]), .Y(n7534) );
CLKINVX3TS U1881 ( .A(n803), .Y(n824) );
CLKINVX3TS U1882 ( .A(n8433), .Y(n7768) );
CLKINVX3TS U1883 ( .A(n8365), .Y(n7496) );
CLKINVX3TS U1884 ( .A(n8372), .Y(n7505) );
INVX2TS U1885 ( .A(n1035), .Y(n737) );
OAI21X2TS U1886 ( .A0(n7430), .A1(n7310), .B0(n7309), .Y(n7314) );
XOR2X1TS U1887 ( .A(n743), .B(n7250), .Y(Sgf_operation_ODD1_middle_N34) );
OAI31X1TS U1888 ( .A0(FS_Module_state_reg[1]), .A1(n7488), .A2(n8446), .B0(
n7487), .Y(n712) );
XOR2X1TS U1889 ( .A(n5271), .B(n4765), .Y(Sgf_operation_ODD1_left_N35) );
OR2X1TS U1890 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
BUFX6TS U1891 ( .A(n5095), .Y(n5825) );
BUFX3TS U1892 ( .A(Op_MX[26]), .Y(n2221) );
XNOR2X2TS U1893 ( .A(n858), .B(n1794), .Y(n728) );
XNOR2X4TS U1894 ( .A(n820), .B(n6417), .Y(n729) );
CLKINVX3TS U1895 ( .A(n730), .Y(n940) );
OR2X1TS U1896 ( .A(n4233), .B(Sgf_operation_ODD1_Q_right[30]), .Y(n731) );
XNOR2X4TS U1897 ( .A(n1365), .B(n749), .Y(n732) );
AND3X4TS U1898 ( .A(n4711), .B(n4710), .C(n4709), .Y(n6531) );
BUFX3TS U1899 ( .A(n6531), .Y(n6805) );
INVX2TS U1900 ( .A(n6686), .Y(n6815) );
BUFX3TS U1901 ( .A(n6686), .Y(n6903) );
AO21X4TS U1902 ( .A0(n1214), .A1(n1213), .B0(n1212), .Y(n733) );
OR2X2TS U1903 ( .A(n1596), .B(n1597), .Y(n734) );
INVX4TS U1904 ( .A(n801), .Y(n851) );
CLKXOR2X4TS U1905 ( .A(n1413), .B(n1418), .Y(n736) );
CLKINVX3TS U1906 ( .A(n872), .Y(n873) );
BUFX3TS U1907 ( .A(n753), .Y(n899) );
BUFX3TS U1908 ( .A(n8365), .Y(n8372) );
XNOR2X2TS U1909 ( .A(n7808), .B(n7807), .Y(n7809) );
NOR2X4TS U1910 ( .A(n7512), .B(n7511), .Y(n5071) );
INVX4TS U1911 ( .A(n7683), .Y(n7693) );
NOR2X4TS U1912 ( .A(n7287), .B(n2933), .Y(n2935) );
OR2X2TS U1913 ( .A(n5161), .B(n3903), .Y(n3905) );
NAND2X4TS U1914 ( .A(n2923), .B(n2922), .Y(n7288) );
NOR2X4TS U1915 ( .A(n2193), .B(n7142), .Y(n2195) );
CLKINVX2TS U1916 ( .A(n7133), .Y(n7135) );
NOR2X4TS U1917 ( .A(n6117), .B(n953), .Y(n952) );
INVX3TS U1918 ( .A(n5162), .Y(n4950) );
NAND2X4TS U1919 ( .A(n2912), .B(n2911), .Y(n7124) );
NOR2X1TS U1920 ( .A(n7394), .B(n7396), .Y(n7399) );
NOR2X4TS U1921 ( .A(n7269), .B(n7129), .Y(n759) );
INVX2TS U1922 ( .A(n6112), .Y(n1179) );
AOI21X2TS U1923 ( .A0(n3568), .A1(n4832), .B0(n3567), .Y(n3569) );
NAND2X4TS U1924 ( .A(n2445), .B(n2446), .Y(n7129) );
NOR2X4TS U1925 ( .A(n4935), .B(n3891), .Y(n3893) );
NOR2X6TS U1926 ( .A(n8111), .B(n4411), .Y(n7999) );
NOR2X6TS U1927 ( .A(mult_x_24_n976), .B(mult_x_24_n966), .Y(n6122) );
ADDFHX2TS U1928 ( .A(n2444), .B(n2443), .CI(n2442), .CO(n2447), .S(n2446) );
NAND2X2TS U1929 ( .A(mult_x_24_n706), .B(mult_x_24_n710), .Y(n5016) );
NOR2X4TS U1930 ( .A(mult_x_23_n662), .B(mult_x_23_n656), .Y(n5189) );
NAND2X2TS U1931 ( .A(n3564), .B(n3563), .Y(n7312) );
INVX1TS U1932 ( .A(n7744), .Y(n7746) );
OAI2BB1X2TS U1933 ( .A0N(n2156), .A1N(n2155), .B0(n958), .Y(n2172) );
NOR2X4TS U1934 ( .A(n7173), .B(n1733), .Y(n1734) );
INVX2TS U1935 ( .A(n7169), .Y(n1735) );
ADDFHX2TS U1936 ( .A(n3262), .B(n3261), .CI(n3260), .CO(n3269), .S(n3265) );
INVX1TS U1937 ( .A(n8277), .Y(n8280) );
OAI21X2TS U1938 ( .A0(n2156), .A1(n2155), .B0(n2154), .Y(n958) );
NAND2X2TS U1939 ( .A(n4418), .B(Sgf_operation_ODD1_Q_left[8]), .Y(n8047) );
NAND2X2TS U1940 ( .A(n4414), .B(Sgf_operation_ODD1_Q_left[6]), .Y(n8077) );
INVX2TS U1941 ( .A(n8310), .Y(n8312) );
CLKMX2X2TS U1942 ( .A(P_Sgf[29]), .B(n8204), .S0(n8224), .Y(n450) );
INVX12TS U1943 ( .A(n739), .Y(n915) );
INVX6TS U1944 ( .A(n3384), .Y(n739) );
NAND2X2TS U1945 ( .A(n4384), .B(Sgf_operation_ODD1_Q_right[44]), .Y(n8289)
);
OAI21X1TS U1946 ( .A0(n6912), .A1(n6899), .B0(n6582), .Y(n6583) );
OAI21X1TS U1947 ( .A0(n6912), .A1(n6907), .B0(n6689), .Y(n6690) );
ADDHX2TS U1948 ( .A(n5052), .B(n5051), .CO(n6986), .S(mult_x_24_n1054) );
CLKMX2X2TS U1949 ( .A(n7828), .B(Add_result[25]), .S0(n8030), .Y(n554) );
INVX6TS U1950 ( .A(n1151), .Y(n6879) );
CMPR22X2TS U1951 ( .A(n5033), .B(n5032), .CO(n5052), .S(mult_x_24_n1059) );
CLKMX2X2TS U1952 ( .A(n7845), .B(Add_result[24]), .S0(n8186), .Y(n555) );
OAI21X1TS U1953 ( .A0(n6865), .A1(n6809), .B0(n6542), .Y(n6543) );
CLKMX2X2TS U1954 ( .A(P_Sgf[28]), .B(n8200), .S0(n8224), .Y(n449) );
CLKMX2X2TS U1955 ( .A(n7790), .B(Add_result[28]), .S0(n8030), .Y(n551) );
INVX12TS U1956 ( .A(n733), .Y(n820) );
OR2X2TS U1957 ( .A(n7223), .B(n7222), .Y(n7225) );
ADDHX2TS U1958 ( .A(n1100), .B(n1099), .CO(n1072), .S(n1101) );
CLKMX2X2TS U1959 ( .A(n7857), .B(Add_result[23]), .S0(n8030), .Y(n556) );
CLKMX2X2TS U1960 ( .A(n7814), .B(Add_result[26]), .S0(n8030), .Y(n553) );
CLKMX2X2TS U1961 ( .A(n7802), .B(Add_result[27]), .S0(n8030), .Y(n552) );
ADDHX1TS U1962 ( .A(n1423), .B(n1422), .CO(n1625), .S(n1466) );
ADDHX2TS U1963 ( .A(n1476), .B(n1475), .CO(n1468), .S(n1580) );
BUFX6TS U1964 ( .A(n3226), .Y(n3582) );
AO21X1TS U1965 ( .A0(n934), .A1(n2214), .B0(n3426), .Y(n2961) );
BUFX12TS U1966 ( .A(n2788), .Y(n2739) );
NAND3X1TS U1967 ( .A(n8370), .B(n8369), .C(n8368), .Y(n711) );
ADDHX2TS U1968 ( .A(n940), .B(n1089), .CO(n1099), .S(n1090) );
AO21X1TS U1969 ( .A0(n3376), .A1(n2956), .B0(n3129), .Y(n3161) );
AO21X1TS U1970 ( .A0(n2839), .A1(n2215), .B0(n3367), .Y(n3382) );
INVX8TS U1971 ( .A(n3403), .Y(n888) );
AO21X1TS U1972 ( .A0(n935), .A1(n3052), .B0(n3051), .Y(n3080) );
ADDHX2TS U1973 ( .A(n5208), .B(n5207), .CO(n5210), .S(mult_x_24_n963) );
INVX2TS U1974 ( .A(n7601), .Y(n7602) );
CLKMX2X2TS U1975 ( .A(n8060), .B(Add_result[9]), .S0(n8030), .Y(n570) );
BUFX12TS U1976 ( .A(n2577), .Y(n911) );
BUFX12TS U1977 ( .A(n2097), .Y(n3006) );
BUFX12TS U1978 ( .A(n2735), .Y(n3165) );
INVX12TS U1979 ( .A(n861), .Y(n741) );
OAI21X1TS U1980 ( .A0(n8447), .A1(n8367), .B0(FS_Module_state_reg[3]), .Y(
n7483) );
CLKMX2X2TS U1981 ( .A(n7929), .B(Add_result[18]), .S0(n8030), .Y(n561) );
BUFX12TS U1982 ( .A(n2084), .Y(n931) );
INVX2TS U1983 ( .A(n8440), .Y(n7470) );
AO21X1TS U1984 ( .A0(n865), .A1(n5769), .B0(n882), .Y(n5445) );
CLKMX2X2TS U1985 ( .A(Data_MY[54]), .B(Op_MY[54]), .S0(n8371), .Y(n636) );
CLKMX2X2TS U1986 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n896), .Y(n663) );
INVX2TS U1987 ( .A(n7620), .Y(n7621) );
MX2X1TS U1988 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n7504), .Y(n672) );
AND2X2TS U1989 ( .A(n6060), .B(n829), .Y(n5404) );
AOI222X1TS U1990 ( .A0(n6889), .A1(Op_MX[14]), .B0(n6887), .B1(n7069), .C0(
n7032), .C1(n875), .Y(n6640) );
AOI222X1TS U1991 ( .A0(n6848), .A1(n927), .B0(n7045), .B1(n6790), .C0(n6615),
.C1(n6894), .Y(n6596) );
CLKMX2X2TS U1992 ( .A(Data_MX[54]), .B(Op_MX[54]), .S0(n8371), .Y(n700) );
INVX4TS U1993 ( .A(n880), .Y(n882) );
CLKMX2X2TS U1994 ( .A(Data_MX[53]), .B(Op_MX[53]), .S0(n7505), .Y(n699) );
CLKMX2X2TS U1995 ( .A(Data_MY[17]), .B(n835), .S0(n7505), .Y(n599) );
CLKMX2X2TS U1996 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n8371), .Y(n598) );
CLKMX2X2TS U1997 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n7505), .Y(n597) );
NAND2X6TS U1998 ( .A(n3089), .B(n2082), .Y(n2084) );
CLKMX2X2TS U1999 ( .A(Data_MY[52]), .B(Op_MY[52]), .S0(n7505), .Y(n634) );
AOI222X1TS U2000 ( .A0(n7011), .A1(n6894), .B0(n6834), .B1(n939), .C0(n6867),
.C1(n6785), .Y(n6494) );
CLKMX2X2TS U2001 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n7505), .Y(n594) );
CLKMX2X2TS U2002 ( .A(Data_MX[59]), .B(Op_MX[59]), .S0(n7505), .Y(n705) );
CLKMX2X2TS U2003 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n7506), .Y(n593) );
CLKMX2X2TS U2004 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n7509), .Y(n590) );
INVX4TS U2005 ( .A(n1124), .Y(n1096) );
CLKMX2X2TS U2006 ( .A(Data_MY[32]), .B(n755), .S0(n8371), .Y(n614) );
INVX8TS U2007 ( .A(n736), .Y(n2469) );
AND2X2TS U2008 ( .A(n5940), .B(n5779), .Y(n3863) );
AND2X2TS U2009 ( .A(n5899), .B(n6016), .Y(n5874) );
AND2X2TS U2010 ( .A(n6060), .B(n6023), .Y(n1238) );
AOI222X1TS U2011 ( .A0(n6839), .A1(n6894), .B0(n7045), .B1(n937), .C0(n6615),
.C1(n8412), .Y(n6600) );
AND2X2TS U2012 ( .A(n5940), .B(n5769), .Y(n3873) );
CLKMX2X2TS U2013 ( .A(Data_MY[45]), .B(Op_MY[45]), .S0(n8371), .Y(n627) );
CLKMX2X2TS U2014 ( .A(Data_MY[39]), .B(Op_MY[39]), .S0(n8371), .Y(n621) );
AOI222X1TS U2015 ( .A0(n885), .A1(n8412), .B0(n6916), .B1(n7069), .C0(n6914),
.C1(n875), .Y(n6717) );
INVX4TS U2016 ( .A(n863), .Y(n865) );
INVX4TS U2017 ( .A(n973), .Y(n5936) );
AOI222X1TS U2018 ( .A0(n885), .A1(Op_MX[13]), .B0(n1083), .B1(n7009), .C0(
n6914), .C1(n6853), .Y(n6719) );
CLKMX2X2TS U2019 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n7496), .Y(n660) );
INVX4TS U2020 ( .A(n8433), .Y(n8030) );
CLKMX2X2TS U2021 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n7497), .Y(n651) );
BUFX12TS U2022 ( .A(n2563), .Y(n2976) );
CLKMX2X2TS U2023 ( .A(Data_MX[2]), .B(n8402), .S0(n7501), .Y(n648) );
CLKMX2X2TS U2024 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n7502), .Y(n646) );
CLKMX2X2TS U2025 ( .A(P_Sgf[7]), .B(Sgf_operation_Result[7]), .S0(n8190),
.Y(n428) );
CLKMX2X2TS U2026 ( .A(P_Sgf[4]), .B(Sgf_operation_Result[4]), .S0(n8190),
.Y(n425) );
CLKMX2X2TS U2027 ( .A(P_Sgf[8]), .B(Sgf_operation_Result[8]), .S0(n8190),
.Y(n429) );
CLKMX2X2TS U2028 ( .A(P_Sgf[12]), .B(Sgf_operation_Result[12]), .S0(n8190),
.Y(n433) );
CLKMX2X2TS U2029 ( .A(P_Sgf[11]), .B(Sgf_operation_Result[11]), .S0(n8190),
.Y(n432) );
INVX4TS U2030 ( .A(n8372), .Y(n8371) );
MX2X1TS U2031 ( .A(Data_MX[51]), .B(Op_MX[51]), .S0(n7499), .Y(n697) );
MX2X1TS U2032 ( .A(Data_MX[50]), .B(Op_MX[50]), .S0(n7502), .Y(n696) );
CLKMX2X2TS U2033 ( .A(Data_MX[49]), .B(Op_MX[49]), .S0(n7499), .Y(n695) );
BUFX16TS U2034 ( .A(n2578), .Y(n3118) );
CLKMX2X2TS U2035 ( .A(P_Sgf[10]), .B(Sgf_operation_Result[10]), .S0(n8190),
.Y(n431) );
CLKMX2X2TS U2036 ( .A(P_Sgf[5]), .B(Sgf_operation_Result[5]), .S0(n8190),
.Y(n426) );
OAI31X1TS U2037 ( .A0(n8433), .A1(n8430), .A2(n8536), .B0(n7472), .Y(n418)
);
BUFX12TS U2038 ( .A(n1710), .Y(n2940) );
CLKMX2X2TS U2039 ( .A(P_Sgf[6]), .B(Sgf_operation_Result[6]), .S0(n8190),
.Y(n427) );
CLKMX2X2TS U2040 ( .A(P_Sgf[9]), .B(Sgf_operation_Result[9]), .S0(n8190),
.Y(n430) );
CLKINVX2TS U2041 ( .A(n4106), .Y(n4088) );
CLKMX2X2TS U2042 ( .A(P_Sgf[13]), .B(Sgf_operation_Result[13]), .S0(n8190),
.Y(n434) );
INVX2TS U2043 ( .A(n4166), .Y(n4168) );
INVX2TS U2044 ( .A(n4352), .Y(n4354) );
INVX2TS U2045 ( .A(n4347), .Y(n4349) );
NOR2X1TS U2046 ( .A(n778), .B(n806), .Y(n807) );
NOR2X1TS U2047 ( .A(n775), .B(n805), .Y(n8381) );
INVX2TS U2048 ( .A(n4189), .Y(n4191) );
NOR2X1TS U2049 ( .A(n774), .B(n809), .Y(n8407) );
INVX2TS U2050 ( .A(n4151), .Y(n4153) );
INVX2TS U2051 ( .A(n4278), .Y(n4261) );
AO21X1TS U2052 ( .A0(n6011), .A1(n5769), .B0(n5922), .Y(n5526) );
NAND4X1TS U2053 ( .A(n7457), .B(n7456), .C(n7455), .D(n7454), .Y(n7459) );
INVX4TS U2054 ( .A(n4702), .Y(n5863) );
CLKINVX2TS U2055 ( .A(n4264), .Y(n4244) );
INVX2TS U2056 ( .A(n4123), .Y(n4117) );
INVX2TS U2057 ( .A(n7824), .Y(n7825) );
NAND2X6TS U2058 ( .A(n905), .B(n825), .Y(n1073) );
NAND2X2TS U2059 ( .A(n3997), .B(n3996), .Y(n4173) );
CLKMX2X2TS U2060 ( .A(Op_MX[55]), .B(exp_oper_result[3]), .S0(n847), .Y(
S_Oper_A_exp[3]) );
NAND2X2TS U2061 ( .A(n4455), .B(n4454), .Y(n4596) );
NOR2X2TS U2062 ( .A(n4544), .B(n4543), .Y(n4548) );
INVX2TS U2063 ( .A(n6310), .Y(n6327) );
CLKMX2X2TS U2064 ( .A(Op_MX[56]), .B(exp_oper_result[4]), .S0(n847), .Y(
S_Oper_A_exp[4]) );
NOR2X4TS U2065 ( .A(n4057), .B(n4056), .Y(n4279) );
NAND2X2TS U2066 ( .A(n4085), .B(n4084), .Y(n4157) );
NAND2X2TS U2067 ( .A(n4451), .B(n4450), .Y(n4564) );
NOR2X1TS U2068 ( .A(n808), .B(n776), .Y(n777) );
AND2X2TS U2069 ( .A(n2250), .B(n8393), .Y(n2251) );
NAND2X4TS U2070 ( .A(n7489), .B(FS_Module_state_reg[3]), .Y(n7473) );
INVX4TS U2071 ( .A(n1007), .Y(n2287) );
INVX2TS U2072 ( .A(n5535), .Y(n5537) );
XOR2X1TS U2073 ( .A(n1419), .B(n1418), .Y(n1420) );
AND2X2TS U2074 ( .A(n6946), .B(n6785), .Y(n6224) );
INVX4TS U2075 ( .A(n6517), .Y(n6968) );
INVX3TS U2076 ( .A(n735), .Y(n6851) );
INVX4TS U2077 ( .A(n2221), .Y(n3583) );
INVX2TS U2078 ( .A(n7480), .Y(n7481) );
CLKAND2X2TS U2079 ( .A(n7078), .B(n6874), .Y(mult_x_24_n1104) );
INVX6TS U2080 ( .A(n3813), .Y(n6989) );
INVX4TS U2081 ( .A(n1450), .Y(n1812) );
INVX3TS U2082 ( .A(n6974), .Y(n6758) );
INVX4TS U2083 ( .A(n3813), .Y(n6963) );
INVX4TS U2084 ( .A(n2221), .Y(n3157) );
INVX3TS U2085 ( .A(n6974), .Y(n6891) );
AND2X2TS U2086 ( .A(Op_MY[26]), .B(n6959), .Y(n5128) );
INVX12TS U2087 ( .A(n8444), .Y(n835) );
AND2X2TS U2088 ( .A(n6946), .B(n6484), .Y(mult_x_24_n1087) );
INVX3TS U2089 ( .A(n735), .Y(n7051) );
INVX2TS U2090 ( .A(n730), .Y(n8377) );
INVX4TS U2091 ( .A(n1034), .Y(n6069) );
INVX4TS U2092 ( .A(n769), .Y(n8392) );
INVX4TS U2093 ( .A(Op_MX[26]), .Y(n3813) );
INVX4TS U2094 ( .A(n767), .Y(n5736) );
INVX4TS U2095 ( .A(n1020), .Y(n5663) );
INVX4TS U2096 ( .A(n1015), .Y(n5847) );
INVX12TS U2097 ( .A(Op_MY[8]), .Y(n6974) );
INVX4TS U2098 ( .A(n1035), .Y(n5567) );
INVX4TS U2099 ( .A(n1022), .Y(n5828) );
INVX4TS U2100 ( .A(n1015), .Y(n7493) );
INVX4TS U2101 ( .A(n1017), .Y(n6882) );
INVX4TS U2102 ( .A(n767), .Y(n5763) );
INVX4TS U2103 ( .A(n1031), .Y(n5769) );
INVX4TS U2104 ( .A(n1009), .Y(n7027) );
INVX4TS U2105 ( .A(n1020), .Y(n5644) );
INVX4TS U2106 ( .A(n803), .Y(n3632) );
INVX4TS U2107 ( .A(n1031), .Y(n5883) );
INVX4TS U2108 ( .A(n769), .Y(n7076) );
INVX4TS U2109 ( .A(n1032), .Y(n5819) );
INVX4TS U2110 ( .A(n1015), .Y(n5868) );
BUFX12TS U2111 ( .A(Op_MX[3]), .Y(n6584) );
INVX4TS U2112 ( .A(n1022), .Y(n7498) );
INVX4TS U2113 ( .A(n1022), .Y(n6002) );
INVX4TS U2114 ( .A(n1009), .Y(n6827) );
MX2X2TS U2115 ( .A(P_Sgf[105]), .B(n5072), .S0(n8188), .Y(n420) );
XOR2X2TS U2116 ( .A(n3921), .B(n993), .Y(Sgf_operation_ODD1_middle_N49) );
CLKMX2X2TS U2117 ( .A(P_Sgf[79]), .B(n7809), .S0(n7850), .Y(n500) );
CLKMX2X2TS U2118 ( .A(P_Sgf[81]), .B(n7785), .S0(n7850), .Y(n502) );
OA21X2TS U2119 ( .A0(n7379), .A1(n7247), .B0(n7246), .Y(n743) );
CLKMX2X2TS U2120 ( .A(P_Sgf[78]), .B(n7820), .S0(n7850), .Y(n499) );
CLKMX2X2TS U2121 ( .A(P_Sgf[103]), .B(n7543), .S0(n8191), .Y(n525) );
CLKMX2X2TS U2122 ( .A(P_Sgf[76]), .B(n7851), .S0(n7850), .Y(n497) );
XOR2X2TS U2123 ( .A(n7839), .B(n7838), .Y(n7840) );
CLKMX2X2TS U2124 ( .A(P_Sgf[72]), .B(n7909), .S0(n7988), .Y(n493) );
CLKMX2X2TS U2125 ( .A(P_Sgf[80]), .B(n7796), .S0(n7850), .Y(n501) );
CLKMX2X2TS U2126 ( .A(P_Sgf[71]), .B(n7924), .S0(n7988), .Y(n492) );
CLKMX2X2TS U2127 ( .A(P_Sgf[75]), .B(n7866), .S0(n7988), .Y(n496) );
CLKMX2X2TS U2128 ( .A(P_Sgf[70]), .B(n7934), .S0(n7988), .Y(n491) );
NAND2X6TS U2129 ( .A(n7542), .B(Sgf_operation_ODD1_Q_left[49]), .Y(n7512) );
CLKMX2X2TS U2130 ( .A(P_Sgf[74]), .B(n7876), .S0(n7988), .Y(n495) );
CLKMX2X2TS U2131 ( .A(P_Sgf[69]), .B(n7955), .S0(n7988), .Y(n490) );
XOR2X1TS U2132 ( .A(n6102), .B(n6101), .Y(Sgf_operation_ODD1_right_N27) );
XNOR2X2TS U2133 ( .A(n4786), .B(n4785), .Y(Sgf_operation_ODD1_left_N34) );
CLKMX2X2TS U2134 ( .A(P_Sgf[102]), .B(n7555), .S0(n8191), .Y(n524) );
XOR2X1TS U2135 ( .A(n7379), .B(n7126), .Y(Sgf_operation_ODD1_middle_N28) );
CLKMX2X2TS U2136 ( .A(P_Sgf[84]), .B(n7734), .S0(n7850), .Y(n505) );
CLKMX2X2TS U2137 ( .A(P_Sgf[68]), .B(n7965), .S0(n7988), .Y(n489) );
XOR2X1TS U2138 ( .A(n5297), .B(n5296), .Y(Sgf_operation_ODD1_left_N26) );
OR2X2TS U2139 ( .A(n5142), .B(n5143), .Y(n1026) );
CLKMX2X2TS U2140 ( .A(P_Sgf[101]), .B(n7563), .S0(n8191), .Y(n523) );
CLKMX2X2TS U2141 ( .A(P_Sgf[82]), .B(n7760), .S0(n7850), .Y(n503) );
INVX8TS U2142 ( .A(n6106), .Y(n6130) );
CLKMX2X2TS U2143 ( .A(P_Sgf[100]), .B(n7571), .S0(n8191), .Y(n522) );
CLKMX2X2TS U2144 ( .A(P_Sgf[63]), .B(n8038), .S0(n8133), .Y(n484) );
CLKMX2X2TS U2145 ( .A(P_Sgf[62]), .B(n8051), .S0(n8133), .Y(n483) );
XOR2X1TS U2146 ( .A(n6135), .B(n6134), .Y(Sgf_operation_ODD1_right_N20) );
OAI21X1TS U2147 ( .A0(n7154), .A1(n7137), .B0(n7136), .Y(n7141) );
CLKMX2X2TS U2148 ( .A(P_Sgf[66]), .B(n7989), .S0(n7988), .Y(n487) );
NAND2X4TS U2149 ( .A(n3575), .B(n792), .Y(n3576) );
XOR2X1TS U2150 ( .A(n5331), .B(n5330), .Y(Sgf_operation_ODD1_left_N20) );
CLKMX2X2TS U2151 ( .A(P_Sgf[60]), .B(n8081), .S0(n8133), .Y(n481) );
OAI21X1TS U2152 ( .A0(n7154), .A1(n7147), .B0(n7151), .Y(n7150) );
INVX3TS U2153 ( .A(n7305), .Y(n7308) );
OAI21X1TS U2154 ( .A0(n7154), .A1(n7142), .B0(n7133), .Y(n7146) );
XOR2X1TS U2155 ( .A(n7154), .B(n7153), .Y(Sgf_operation_ODD1_middle_N20) );
NOR2X6TS U2156 ( .A(n7570), .B(n7569), .Y(n7561) );
CLKMX2X2TS U2157 ( .A(P_Sgf[56]), .B(n8134), .S0(n8133), .Y(n477) );
XOR2X1TS U2158 ( .A(n5339), .B(n5338), .Y(Sgf_operation_ODD1_left_N18) );
OAI21X1TS U2159 ( .A0(n5331), .A1(n5324), .B0(n5328), .Y(n5327) );
CLKMX2X2TS U2160 ( .A(P_Sgf[55]), .B(n8145), .S0(n8188), .Y(n476) );
XOR2X1TS U2161 ( .A(n7160), .B(n7175), .Y(Sgf_operation_ODD1_middle_N13) );
CLKMX2X2TS U2162 ( .A(P_Sgf[58]), .B(n8104), .S0(n8133), .Y(n479) );
NAND2X4TS U2163 ( .A(n7335), .B(n3524), .Y(n7330) );
CLKMX2X2TS U2164 ( .A(P_Sgf[53]), .B(n8167), .S0(n8188), .Y(n474) );
CLKMX2X2TS U2165 ( .A(P_Sgf[59]), .B(n8093), .S0(n8133), .Y(n480) );
CLKMX2X2TS U2166 ( .A(P_Sgf[49]), .B(n8339), .S0(n8354), .Y(n470) );
OAI21X1TS U2167 ( .A0(n7160), .A1(n7168), .B0(n7173), .Y(n7172) );
INVX3TS U2168 ( .A(n1290), .Y(n1276) );
CLKMX2X2TS U2169 ( .A(P_Sgf[54]), .B(n8154), .S0(n8188), .Y(n475) );
XOR2X1TS U2170 ( .A(n6951), .B(n6950), .Y(Sgf_operation_ODD1_right_N17) );
XOR2X1TS U2171 ( .A(n6159), .B(n6158), .Y(Sgf_operation_ODD1_right_N15) );
XOR2X1TS U2172 ( .A(n6152), .B(n6151), .Y(Sgf_operation_ODD1_right_N16) );
INVX8TS U2173 ( .A(n5250), .Y(n5221) );
INVX2TS U2174 ( .A(n7131), .Y(n7154) );
OAI21X1TS U2175 ( .A0(n5950), .A1(n5946), .B0(n5947), .Y(n5348) );
INVX2TS U2176 ( .A(n7155), .Y(n7156) );
CLKMX2X2TS U2177 ( .A(P_Sgf[48]), .B(n8329), .S0(n8354), .Y(n469) );
XOR2X1TS U2178 ( .A(n5950), .B(n5949), .Y(Sgf_operation_ODD1_left_N15) );
CLKMX2X2TS U2179 ( .A(P_Sgf[51]), .B(n8352), .S0(n8354), .Y(n472) );
XOR2X1TS U2180 ( .A(n5354), .B(n5353), .Y(Sgf_operation_ODD1_left_N14) );
XOR2X1TS U2181 ( .A(n7180), .B(n7179), .Y(Sgf_operation_ODD1_middle_N12) );
CLKMX2X2TS U2182 ( .A(P_Sgf[52]), .B(n8176), .S0(n8188), .Y(n473) );
NOR2X6TS U2183 ( .A(n3537), .B(n7345), .Y(n3539) );
NAND2X4TS U2184 ( .A(n2453), .B(n7435), .Y(n2455) );
INVX3TS U2185 ( .A(n6733), .Y(n1269) );
AND2X2TS U2186 ( .A(n1273), .B(n1297), .Y(n984) );
NAND2X6TS U2187 ( .A(n966), .B(n965), .Y(n964) );
CLKMX2X2TS U2188 ( .A(P_Sgf[45]), .B(n8288), .S0(n8293), .Y(n466) );
CLKMX2X2TS U2189 ( .A(P_Sgf[47]), .B(n8271), .S0(n8293), .Y(n468) );
CLKMX2X2TS U2190 ( .A(P_Sgf[46]), .B(n8276), .S0(n8293), .Y(n467) );
CLKMX2X2TS U2191 ( .A(P_Sgf[50]), .B(n8342), .S0(n8354), .Y(n471) );
INVX2TS U2192 ( .A(n7159), .Y(n7160) );
AND2X2TS U2193 ( .A(n3920), .B(n3922), .Y(n993) );
OAI21X1TS U2194 ( .A0(n6957), .A1(n6953), .B0(n6954), .Y(n6169) );
AND2X2TS U2195 ( .A(n785), .B(n1267), .Y(n982) );
NAND2X1TS U2196 ( .A(n7322), .B(n7321), .Y(n821) );
AND2X2TS U2197 ( .A(n3930), .B(n3929), .Y(n969) );
NAND2X4TS U2198 ( .A(n7578), .B(Sgf_operation_ODD1_Q_left[45]), .Y(n5066) );
OR2X4TS U2199 ( .A(n955), .B(n1174), .Y(n949) );
XOR2X1TS U2200 ( .A(n6957), .B(n6956), .Y(Sgf_operation_ODD1_right_N12) );
XOR2X1TS U2201 ( .A(n6175), .B(n6174), .Y(Sgf_operation_ODD1_right_N11) );
NAND2X4TS U2202 ( .A(n7110), .B(n7107), .Y(n6094) );
AND2X2TS U2203 ( .A(n1289), .B(n1277), .Y(n983) );
CLKMX2X2TS U2204 ( .A(P_Sgf[44]), .B(n8294), .S0(n8293), .Y(n465) );
INVX3TS U2205 ( .A(n7328), .Y(n3547) );
NOR2X4TS U2206 ( .A(n7590), .B(n7592), .Y(n7579) );
CLKMX2X2TS U2207 ( .A(P_Sgf[43]), .B(n8300), .S0(n8354), .Y(n464) );
AND2X2TS U2208 ( .A(n5185), .B(n5183), .Y(n992) );
AND2X2TS U2209 ( .A(n1284), .B(n1291), .Y(n985) );
OAI21X1TS U2210 ( .A0(n7230), .A1(n7226), .B0(n7227), .Y(n7189) );
AND2X2TS U2211 ( .A(n4696), .B(n4695), .Y(n1003) );
CLKMX2X2TS U2212 ( .A(n8187), .B(FSM_add_overflow_flag), .S0(n8186), .Y(n526) );
XOR2X1TS U2213 ( .A(n5955), .B(n5954), .Y(Sgf_operation_ODD1_left_N11) );
AND2X2TS U2214 ( .A(n4919), .B(n5153), .Y(n978) );
CLKMX2X2TS U2215 ( .A(P_Sgf[41]), .B(n8315), .S0(n8354), .Y(n462) );
XOR2X1TS U2216 ( .A(n7230), .B(n7229), .Y(Sgf_operation_ODD1_middle_N9) );
OAI21X1TS U2217 ( .A0(n5955), .A1(n5951), .B0(n5952), .Y(n5363) );
NOR2X4TS U2218 ( .A(n3923), .B(n3928), .Y(n4820) );
ADDFHX2TS U2219 ( .A(n2859), .B(n2858), .CI(n2857), .CO(n2926), .S(n2924) );
INVX2TS U2220 ( .A(n5285), .Y(n5287) );
INVX3TS U2221 ( .A(n6123), .Y(n1177) );
XOR2X1TS U2222 ( .A(n5369), .B(n5368), .Y(Sgf_operation_ODD1_left_N10) );
XOR2X1TS U2223 ( .A(n7195), .B(n7194), .Y(Sgf_operation_ODD1_middle_N8) );
OR2X4TS U2224 ( .A(mult_x_23_n675), .B(mult_x_23_n682), .Y(n3773) );
OR2X6TS U2225 ( .A(mult_x_24_n977), .B(mult_x_24_n986), .Y(n972) );
AND2X2TS U2226 ( .A(n3807), .B(n3804), .Y(n1024) );
CLKMX2X2TS U2227 ( .A(Exp_module_Data_S[11]), .B(exp_oper_result[11]), .S0(
n942), .Y(n406) );
AND2X2TS U2228 ( .A(n3834), .B(n5116), .Y(n974) );
CLKMX2X2TS U2229 ( .A(P_Sgf[39]), .B(n8260), .S0(n8293), .Y(n460) );
CLKMX2X2TS U2230 ( .A(P_Sgf[42]), .B(n8306), .S0(n8354), .Y(n463) );
NOR2X4TS U2231 ( .A(n3836), .B(n5189), .Y(n3884) );
CLKMX2X2TS U2232 ( .A(P_Sgf[40]), .B(n8321), .S0(n8354), .Y(n461) );
ADDFHX2TS U2233 ( .A(n2778), .B(n2777), .CI(n2776), .CO(n2858), .S(n2803) );
OAI21X2TS U2234 ( .A0(n5177), .A1(n5171), .B0(n5178), .Y(n4948) );
CLKMX2X2TS U2235 ( .A(P_Sgf[37]), .B(n8247), .S0(n8293), .Y(n458) );
XNOR2X2TS U2236 ( .A(DP_OP_36J24_124_1029_n1), .B(n4698), .Y(n4699) );
AND2X2TS U2237 ( .A(n3599), .B(n3598), .Y(n968) );
ADDFHX2TS U2238 ( .A(n2429), .B(n2428), .CI(n2427), .CO(n2445), .S(n2190) );
CLKMX2X2TS U2239 ( .A(n7532), .B(Add_result[52]), .S0(n8186), .Y(n527) );
AND2X2TS U2240 ( .A(n5267), .B(n4956), .Y(n1033) );
NAND2X4TS U2241 ( .A(n5273), .B(n5267), .Y(n4935) );
NAND2X4TS U2242 ( .A(n1008), .B(n5329), .Y(n5318) );
CLKMX2X2TS U2243 ( .A(P_Sgf[36]), .B(n8241), .S0(n8293), .Y(n457) );
NAND2X4TS U2244 ( .A(n8116), .B(n4409), .Y(n4411) );
CLKMX2X2TS U2245 ( .A(n7540), .B(Add_result[51]), .S0(n8432), .Y(n528) );
NAND2X4TS U2246 ( .A(n7174), .B(n7170), .Y(n7162) );
CLKMX2X2TS U2247 ( .A(P_Sgf[35]), .B(n8235), .S0(n8293), .Y(n456) );
ADDFHX2TS U2248 ( .A(n2408), .B(n2407), .CI(n2406), .CO(n2679), .S(n2424) );
ADDFHX2TS U2249 ( .A(n3194), .B(n3193), .CI(n3192), .CO(n3264), .S(n3212) );
AND2X2TS U2250 ( .A(n5258), .B(n4943), .Y(n1011) );
CLKMX2X2TS U2251 ( .A(P_Sgf[38]), .B(n8251), .S0(n8293), .Y(n459) );
ADDFHX2TS U2252 ( .A(n2174), .B(n2173), .CI(n2172), .CO(n2165), .S(n2175) );
OAI21X1TS U2253 ( .A0(n8320), .A1(n8316), .B0(n8317), .Y(n8314) );
XOR2X1TS U2254 ( .A(n6188), .B(n6187), .Y(Sgf_operation_ODD1_right_N8) );
CLKMX2X2TS U2255 ( .A(Exp_module_Data_S[10]), .B(exp_oper_result[10]), .S0(
n941), .Y(n407) );
ADDFHX2TS U2256 ( .A(n3044), .B(n3043), .CI(n3042), .CO(n3548), .S(n3545) );
ADDFHX2TS U2257 ( .A(n2361), .B(n2360), .CI(n2359), .CO(n2671), .S(n2407) );
OR2X2TS U2258 ( .A(n3566), .B(n3565), .Y(n4832) );
AND2X2TS U2259 ( .A(n4931), .B(n4930), .Y(n980) );
NAND2X4TS U2260 ( .A(n8161), .B(n4403), .Y(n8111) );
ADDFHX2TS U2261 ( .A(n3016), .B(n3015), .CI(n3014), .CO(n3039), .S(n3470) );
ADDFHX2TS U2262 ( .A(n2705), .B(n2704), .CI(n2703), .CO(n2801), .S(n2747) );
CLKMX2X2TS U2263 ( .A(Exp_module_Data_S[9]), .B(exp_oper_result[9]), .S0(
n942), .Y(n408) );
ADDFHX2TS U2264 ( .A(n2553), .B(n2552), .CI(n2551), .CO(n2593), .S(n2676) );
ADDFHX2TS U2265 ( .A(n2799), .B(n2798), .CI(n2797), .CO(n2837), .S(n2777) );
CLKMX2X2TS U2266 ( .A(P_Sgf[34]), .B(n8229), .S0(n8293), .Y(n455) );
ADDFHX2TS U2267 ( .A(n2162), .B(n2161), .CI(n2160), .CO(n2147), .S(n2163) );
ADDFHX2TS U2268 ( .A(n2168), .B(n2167), .CI(n2166), .CO(n2177), .S(n2178) );
ADDFHX2TS U2269 ( .A(n2144), .B(n2143), .CI(n2142), .CO(n2428), .S(n2145) );
CLKMX2X2TS U2270 ( .A(P_Sgf[33]), .B(n8225), .S0(n8224), .Y(n454) );
ADDFHX2TS U2271 ( .A(n2141), .B(n2140), .CI(n2139), .CO(n2433), .S(n2146) );
ADDFHX2TS U2272 ( .A(n2417), .B(n2416), .CI(n2415), .CO(n2436), .S(n2429) );
ADDFHX2TS U2273 ( .A(n2796), .B(n2795), .CI(n2794), .CO(n2851), .S(n2802) );
CLKMX2X2TS U2274 ( .A(n7552), .B(Add_result[50]), .S0(n7768), .Y(n529) );
AND2X2TS U2275 ( .A(n4963), .B(n4962), .Y(n967) );
ADDFHX2TS U2276 ( .A(n2856), .B(n2855), .CI(n2854), .CO(n2905), .S(n2859) );
NOR2X4TS U2277 ( .A(n8149), .B(n8140), .Y(n8116) );
CLKMX2X2TS U2278 ( .A(n7560), .B(Add_result[49]), .S0(n7666), .Y(n530) );
INVX2TS U2279 ( .A(n8140), .Y(n8142) );
OR2X2TS U2280 ( .A(n3888), .B(n3887), .Y(n1012) );
ADDFHX2TS U2281 ( .A(n2384), .B(n2383), .CI(n2382), .CO(n2669), .S(n2426) );
ADDFHX2TS U2282 ( .A(n2068), .B(n2067), .CI(n2066), .CO(n2435), .S(n2143) );
ADDFHX2TS U2283 ( .A(n2892), .B(n2891), .CI(n2890), .CO(n3194), .S(n2907) );
OAI21X1TS U2284 ( .A0(n4929), .A1(n4962), .B0(n4930), .Y(n3900) );
ADDFHX2TS U2285 ( .A(n2159), .B(n2158), .CI(n2157), .CO(n2142), .S(n2164) );
CLKMX2X2TS U2286 ( .A(P_Sgf[32]), .B(n8218), .S0(n8224), .Y(n453) );
ADDFHX2TS U2287 ( .A(n3460), .B(n3459), .CI(n3458), .CO(n3472), .S(n3469) );
XOR2X1TS U2288 ( .A(n7208), .B(n7207), .Y(Sgf_operation_ODD1_middle_N5) );
CLKMX2X2TS U2289 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(
n941), .Y(n409) );
OR2X2TS U2290 ( .A(n5130), .B(n5129), .Y(n5132) );
XOR2X1TS U2291 ( .A(n6203), .B(n6202), .Y(Sgf_operation_ODD1_right_N5) );
ADDFHX2TS U2292 ( .A(n2644), .B(n2643), .CI(n2642), .CO(n2726), .S(n2664) );
CLKMX2X2TS U2293 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(
n942), .Y(n410) );
ADDFHX2TS U2294 ( .A(n1642), .B(n1641), .CI(n1640), .CO(n1732), .S(n1599) );
CLKMX2X2TS U2295 ( .A(n7568), .B(Add_result[48]), .S0(n7768), .Y(n531) );
OAI21X1TS U2296 ( .A0(n6202), .A1(n6199), .B0(n6200), .Y(n6198) );
XOR2X1TS U2297 ( .A(n5384), .B(n5383), .Y(Sgf_operation_ODD1_left_N5) );
XOR2X2TS U2298 ( .A(n6488), .B(n6794), .Y(mult_x_24_n1465) );
XOR2X2TS U2299 ( .A(n6746), .B(n6851), .Y(mult_x_24_n1550) );
XOR2X2TS U2300 ( .A(n6773), .B(n6827), .Y(mult_x_24_n1525) );
XOR2X1TS U2301 ( .A(n6524), .B(n6968), .Y(mult_x_24_n1496) );
OAI21X1TS U2302 ( .A0(n7006), .A1(n6925), .B0(n3831), .Y(n3832) );
OAI21X1TS U2303 ( .A0(n6918), .A1(n6932), .B0(n6917), .Y(n6919) );
OAI21X1TS U2304 ( .A0(n6832), .A1(n6966), .B0(n6523), .Y(n6524) );
INVX2TS U2305 ( .A(n5834), .Y(n5838) );
CLKMX2X2TS U2306 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(
n941), .Y(n411) );
OAI21X1TS U2307 ( .A0(n6769), .A1(n6925), .B0(n6266), .Y(n6267) );
OAI21X1TS U2308 ( .A0(n8317), .A1(n8310), .B0(n8311), .Y(n4330) );
INVX2TS U2309 ( .A(n8088), .Y(n8090) );
XOR2X1TS U2310 ( .A(n5774), .B(n7491), .Y(mult_x_23_n1465) );
XOR2X1TS U2311 ( .A(n5865), .B(n3866), .Y(mult_x_23_n1268) );
XOR2X1TS U2312 ( .A(n7217), .B(n7216), .Y(Sgf_operation_ODD1_middle_N3) );
ADDFHX2TS U2313 ( .A(n2793), .B(n2792), .CI(n2791), .CO(n2852), .S(n2799) );
XOR2X2TS U2314 ( .A(n4549), .B(n4546), .Y(n4627) );
INVX2TS U2315 ( .A(n8347), .Y(n8349) );
INVX2TS U2316 ( .A(n8266), .Y(n8268) );
OR2X2TS U2317 ( .A(n3735), .B(n3734), .Y(n5815) );
ADDFHX2TS U2318 ( .A(n1499), .B(n1498), .CI(n1497), .CO(n1598), .S(n1597) );
CLKMX2X2TS U2319 ( .A(n7576), .B(Add_result[47]), .S0(n7666), .Y(n532) );
CLKMX2X2TS U2320 ( .A(n7723), .B(Add_result[33]), .S0(n7768), .Y(n546) );
CLKMX2X2TS U2321 ( .A(P_Sgf[30]), .B(n8210), .S0(n8224), .Y(n451) );
ADDFHX2TS U2322 ( .A(n1846), .B(n1845), .CI(n1844), .CO(n1842), .S(n1928) );
CLKMX2X2TS U2323 ( .A(P_Sgf[31]), .B(n8214), .S0(n8224), .Y(n452) );
ADDFHX2TS U2324 ( .A(n2641), .B(n2640), .CI(n2639), .CO(n2703), .S(n2643) );
CLKMX2X2TS U2325 ( .A(n7731), .B(Add_result[32]), .S0(n7768), .Y(n547) );
XOR2X1TS U2326 ( .A(n5627), .B(n5644), .Y(mult_x_23_n1379) );
ADDFHX2TS U2327 ( .A(n1564), .B(n1563), .CI(n1562), .CO(n1565), .S(n1537) );
OAI21X1TS U2328 ( .A0(n5781), .A1(n5924), .B0(n5529), .Y(n5530) );
OAI21X1TS U2329 ( .A0(n729), .A1(n6932), .B0(n6895), .Y(n6896) );
OAI21X1TS U2330 ( .A0(n5781), .A1(n6083), .B0(n5780), .Y(n5782) );
OAI21X1TS U2331 ( .A0(n6993), .A1(n7025), .B0(n6226), .Y(n6227) );
OAI21X1TS U2332 ( .A0(n5773), .A1(n5827), .B0(n5574), .Y(n5575) );
OAI21X1TS U2333 ( .A0(n6084), .A1(n936), .B0(n5728), .Y(n5729) );
OAI21X1TS U2334 ( .A0(n5781), .A1(n5827), .B0(n5576), .Y(n5577) );
XOR2X1TS U2335 ( .A(n5389), .B(n5388), .Y(Sgf_operation_ODD1_left_N4) );
XOR2X2TS U2336 ( .A(n5545), .B(n5926), .Y(mult_x_23_n1329) );
OAI21X1TS U2337 ( .A0(n6084), .A1(n4965), .B0(n5864), .Y(n5865) );
OAI21X1TS U2338 ( .A0(n6993), .A1(n7062), .B0(n5114), .Y(n5115) );
CLKMX2X2TS U2339 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(
n942), .Y(n412) );
OAI22X2TS U2340 ( .A0(n2588), .A1(n928), .B0(n2656), .B1(n2772), .Y(n2638)
);
ADDFHX2TS U2341 ( .A(n1894), .B(n1893), .CI(n1892), .CO(n2134), .S(n1897) );
INVX8TS U2342 ( .A(n6338), .Y(n6918) );
INVX8TS U2343 ( .A(n6305), .Y(n6850) );
ADDFHX1TS U2344 ( .A(n3254), .B(n3253), .CI(n3252), .CO(n3292), .S(n3215) );
CLKMX2X2TS U2345 ( .A(n7589), .B(Add_result[46]), .S0(n7666), .Y(n533) );
OAI21X1TS U2346 ( .A0(n5905), .A1(n5985), .B0(n5654), .Y(n5655) );
INVX4TS U2347 ( .A(n3053), .Y(n738) );
OAI21X1TS U2348 ( .A0(n6879), .A1(n7085), .B0(n6370), .Y(n6371) );
OAI21X1TS U2349 ( .A0(n5905), .A1(n6014), .B0(n5556), .Y(n5557) );
OAI21X1TS U2350 ( .A0(n5968), .A1(n5620), .B0(n5646), .Y(n5647) );
OAI21X1TS U2351 ( .A0(n6048), .A1(n6042), .B0(n5787), .Y(n5788) );
OAI21X1TS U2352 ( .A0(n6036), .A1(n6042), .B0(n5794), .Y(n5795) );
OAI21X1TS U2353 ( .A0(n6036), .A1(n936), .B0(n5743), .Y(n5744) );
OAI21X1TS U2354 ( .A0(n6026), .A1(n5620), .B0(n5641), .Y(n5642) );
OAI21X1TS U2355 ( .A0(n6912), .A1(n6872), .B0(n6506), .Y(n6507) );
OAI21X1TS U2356 ( .A0(n6036), .A1(n6007), .B0(n5606), .Y(n5607) );
ADDFHX2TS U2357 ( .A(n6073), .B(n6072), .CI(n6071), .CO(n6074), .S(
mult_x_23_n832) );
OAI21X1TS U2358 ( .A0(n5925), .A1(n5924), .B0(n5923), .Y(n5927) );
OAI21X1TS U2359 ( .A0(n5968), .A1(n6042), .B0(n5967), .Y(n5969) );
OAI21X1TS U2360 ( .A0(n5968), .A1(n936), .B0(n5738), .Y(n5739) );
OAI21X1TS U2361 ( .A0(n6912), .A1(n6729), .B0(n6728), .Y(n6731) );
OAI21X1TS U2362 ( .A0(n6912), .A1(n7049), .B0(n6611), .Y(n6612) );
CLKMX2X2TS U2363 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(
n941), .Y(n413) );
OAI21X1TS U2364 ( .A0(n6026), .A1(n936), .B0(n5733), .Y(n5734) );
OAI21X1TS U2365 ( .A0(n6775), .A1(n6729), .B0(n6721), .Y(n6722) );
BUFX12TS U2366 ( .A(n5912), .Y(n6043) );
OAI21X1TS U2367 ( .A0(n7086), .A1(n7038), .B0(n6649), .Y(n6650) );
OAI21X1TS U2368 ( .A0(n6036), .A1(n5985), .B0(n5961), .Y(n5962) );
OAI21X1TS U2369 ( .A0(n6036), .A1(n6035), .B0(n6034), .Y(n6037) );
XOR2X1TS U2370 ( .A(n6838), .B(n6695), .Y(mult_x_24_n1628) );
OAI21X1TS U2371 ( .A0(n6855), .A1(n6729), .B0(n6723), .Y(n6724) );
OAI21X1TS U2372 ( .A0(n5905), .A1(n5807), .B0(n5806), .Y(n5808) );
CLKMX2X2TS U2373 ( .A(n7769), .B(Add_result[29]), .S0(n7768), .Y(n550) );
ADDFHX2TS U2374 ( .A(n1551), .B(n1550), .CI(n1549), .CO(n1556), .S(n1563) );
OAI21X1TS U2375 ( .A0(n7086), .A1(n6809), .B0(n6536), .Y(n6537) );
OAI21X1TS U2376 ( .A0(n6879), .A1(n6907), .B0(n6691), .Y(n6692) );
OAI21X1TS U2377 ( .A0(n7086), .A1(n6729), .B0(n6725), .Y(n6726) );
CLKMX2X2TS U2378 ( .A(n7754), .B(Add_result[30]), .S0(n7768), .Y(n549) );
CLKMX2X2TS U2379 ( .A(n7743), .B(Add_result[31]), .S0(n8432), .Y(n548) );
OAI21X1TS U2380 ( .A0(n6879), .A1(n6809), .B0(n6540), .Y(n6541) );
OAI21X1TS U2381 ( .A0(n6879), .A1(n6899), .B0(n6878), .Y(n6880) );
CLKMX2X2TS U2382 ( .A(n7599), .B(Add_result[45]), .S0(n8432), .Y(n534) );
OAI21X1TS U2383 ( .A0(n6036), .A1(n6014), .B0(n6013), .Y(n6015) );
ADDHX2TS U2384 ( .A(n1750), .B(n1749), .CO(n1819), .S(n1836) );
OAI21X1TS U2385 ( .A0(n5905), .A1(n936), .B0(n5754), .Y(n5755) );
OAI21X1TS U2386 ( .A0(n6855), .A1(n6907), .B0(n6854), .Y(n6856) );
XOR2X2TS U2387 ( .A(n6800), .B(n835), .Y(mult_x_24_n1508) );
INVX2TS U2388 ( .A(n8295), .Y(n8297) );
ADDFHX2TS U2389 ( .A(n2886), .B(n2885), .CI(n2884), .CO(n3184), .S(n2887) );
OAI21X1TS U2390 ( .A0(n6879), .A1(n7038), .B0(n6651), .Y(n6652) );
ADDFHX2TS U2391 ( .A(n1633), .B(n1632), .CI(n1631), .CO(n1657), .S(n1629) );
OAI21X1TS U2392 ( .A0(n6775), .A1(n6907), .B0(n6687), .Y(n6688) );
BUFX8TS U2393 ( .A(n3865), .Y(n5887) );
AO22X1TS U2394 ( .A0(Sgf_normalized_result[51]), .A1(n8439), .B0(
final_result_ieee[51]), .B1(n8438), .Y(n300) );
OAI21X1TS U2395 ( .A0(n6008), .A1(n5807), .B0(n5799), .Y(n5800) );
OAI21X1TS U2396 ( .A0(n6865), .A1(n7038), .B0(n6857), .Y(n6858) );
NOR2X1TS U2397 ( .A(n3369), .B(n971), .Y(n3380) );
CLKMX2X2TS U2398 ( .A(n7610), .B(Add_result[44]), .S0(n8432), .Y(n535) );
OAI21X1TS U2399 ( .A0(n6008), .A1(n936), .B0(n5749), .Y(n5750) );
CLKMX2X2TS U2400 ( .A(n7667), .B(Add_result[39]), .S0(n7666), .Y(n540) );
CMPR22X2TS U2401 ( .A(n4799), .B(n4798), .CO(mult_x_23_n958), .S(n3739) );
OAI21X1TS U2402 ( .A0(n6865), .A1(n7049), .B0(n6618), .Y(n6619) );
CLKMX2X2TS U2403 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(
n942), .Y(n414) );
OAI21X1TS U2404 ( .A0(n5876), .A1(n936), .B0(n5746), .Y(n5747) );
INVX8TS U2405 ( .A(n6466), .Y(n7086) );
OAI21X1TS U2406 ( .A0(n6008), .A1(n5978), .B0(n5977), .Y(n5979) );
ADDHX2TS U2407 ( .A(n1531), .B(n1530), .CO(n1549), .S(n1535) );
ADDHX2TS U2408 ( .A(n6944), .B(n6943), .CO(n7093), .S(mult_x_24_n1020) );
AO22X1TS U2409 ( .A0(n8360), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[9]), .B1(n8361), .Y(n342) );
AO22X1TS U2410 ( .A0(n8360), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[10]), .B1(n8361), .Y(n341) );
AO22X1TS U2411 ( .A0(n8360), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[11]), .B1(n8361), .Y(n340) );
XOR2X1TS U2412 ( .A(n998), .B(n6212), .Y(Sgf_operation_ODD1_right_N2) );
AO22X1TS U2413 ( .A0(n8362), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[12]), .B1(n8361), .Y(n339) );
OAI21X2TS U2414 ( .A0(n7039), .A1(n6809), .B0(n6799), .Y(n6800) );
ADDFHX1TS U2415 ( .A(n1470), .B(n1469), .CI(n1468), .CO(n1464), .S(n1489) );
AO22X1TS U2416 ( .A0(n8362), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[13]), .B1(n8363), .Y(n338) );
AO22X1TS U2417 ( .A0(n8362), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[14]), .B1(n8363), .Y(n337) );
AO22X1TS U2418 ( .A0(n8362), .A1(Sgf_normalized_result[15]), .B0(
final_result_ieee[15]), .B1(n8363), .Y(n336) );
OR2X2TS U2419 ( .A(n4290), .B(Sgf_operation_ODD1_Q_right[37]), .Y(n989) );
AO22X1TS U2420 ( .A0(n8362), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[16]), .B1(n8363), .Y(n335) );
AO22X1TS U2421 ( .A0(n8362), .A1(Sgf_normalized_result[17]), .B0(
final_result_ieee[17]), .B1(n8363), .Y(n334) );
OR2X2TS U2422 ( .A(n4289), .B(Sgf_operation_ODD1_Q_right[36]), .Y(n4284) );
ADDHX2TS U2423 ( .A(n7017), .B(n7016), .CO(n7030), .S(n5055) );
AO22X1TS U2424 ( .A0(n8362), .A1(Sgf_normalized_result[18]), .B0(
final_result_ieee[18]), .B1(n8363), .Y(n333) );
AO22X1TS U2425 ( .A0(n8362), .A1(Sgf_normalized_result[19]), .B0(
final_result_ieee[19]), .B1(n8363), .Y(n332) );
AO22X1TS U2426 ( .A0(n8362), .A1(Sgf_normalized_result[20]), .B0(
final_result_ieee[20]), .B1(n8363), .Y(n331) );
AO22X1TS U2427 ( .A0(n8362), .A1(Sgf_normalized_result[21]), .B0(
final_result_ieee[21]), .B1(n8363), .Y(n330) );
AO22X1TS U2428 ( .A0(n8439), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[22]), .B1(n8363), .Y(n329) );
OAI21X2TS U2429 ( .A0(n7039), .A1(n6763), .B0(n6762), .Y(n6764) );
ADDFHX2TS U2430 ( .A(n1722), .B(n1721), .CI(n1720), .CO(n1834), .S(n1686) );
CLKMX2X2TS U2431 ( .A(n7682), .B(Add_result[37]), .S0(n7768), .Y(n542) );
AO22X1TS U2432 ( .A0(n8360), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[4]), .B1(n8361), .Y(n347) );
BUFX12TS U2433 ( .A(n2957), .Y(n3278) );
INVX8TS U2434 ( .A(n6346), .Y(n7075) );
OAI21X1TS U2435 ( .A0(n6008), .A1(n6007), .B0(n6006), .Y(n6009) );
AO22X1TS U2436 ( .A0(n8360), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n8361), .Y(n348) );
AO22X1TS U2437 ( .A0(n8360), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[5]), .B1(n8361), .Y(n346) );
AO22X1TS U2438 ( .A0(n8360), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n8361), .Y(n345) );
AO22X1TS U2439 ( .A0(n8360), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[7]), .B1(n8361), .Y(n344) );
AO22X1TS U2440 ( .A0(n8360), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[8]), .B1(n8361), .Y(n343) );
OR2X2TS U2441 ( .A(n4286), .B(Sgf_operation_ODD1_Q_right[35]), .Y(n988) );
AO22X1TS U2442 ( .A0(Sgf_normalized_result[49]), .A1(n8437), .B0(
final_result_ieee[49]), .B1(n8438), .Y(n302) );
OAI21X1TS U2443 ( .A0(n5762), .A1(n5761), .B0(n5760), .Y(n5764) );
CLKBUFX2TS U2444 ( .A(n3702), .Y(n894) );
AO22X1TS U2445 ( .A0(Sgf_normalized_result[50]), .A1(n8437), .B0(
final_result_ieee[50]), .B1(n8438), .Y(n301) );
AO22X1TS U2446 ( .A0(Sgf_normalized_result[39]), .A1(n8435), .B0(
final_result_ieee[39]), .B1(n8436), .Y(n312) );
XOR2X1TS U2447 ( .A(n5853), .B(n895), .Y(mult_x_23_n1428) );
OAI21X1TS U2448 ( .A0(n5957), .A1(n5807), .B0(n5803), .Y(n5805) );
AO22X1TS U2449 ( .A0(Sgf_normalized_result[40]), .A1(n8435), .B0(
final_result_ieee[40]), .B1(n8436), .Y(n311) );
AO22X1TS U2450 ( .A0(Sgf_normalized_result[38]), .A1(n8435), .B0(
final_result_ieee[38]), .B1(n8434), .Y(n313) );
AO22X1TS U2451 ( .A0(Sgf_normalized_result[37]), .A1(n8435), .B0(
final_result_ieee[37]), .B1(n8434), .Y(n314) );
AO22X1TS U2452 ( .A0(Sgf_normalized_result[41]), .A1(n8437), .B0(
final_result_ieee[41]), .B1(n8436), .Y(n310) );
AO22X1TS U2453 ( .A0(Sgf_normalized_result[1]), .A1(n7470), .B0(
final_result_ieee[1]), .B1(n8434), .Y(n350) );
AO22X1TS U2454 ( .A0(Sgf_normalized_result[0]), .A1(n7470), .B0(
final_result_ieee[0]), .B1(n8434), .Y(n351) );
XOR2X2TS U2455 ( .A(n3722), .B(n895), .Y(n4798) );
AO22X1TS U2456 ( .A0(Sgf_normalized_result[36]), .A1(n8435), .B0(
final_result_ieee[36]), .B1(n8438), .Y(n315) );
AO22X1TS U2457 ( .A0(Sgf_normalized_result[42]), .A1(n8437), .B0(
final_result_ieee[42]), .B1(n8436), .Y(n309) );
AO22X1TS U2458 ( .A0(Sgf_normalized_result[43]), .A1(n8437), .B0(
final_result_ieee[43]), .B1(n8436), .Y(n308) );
AO22X1TS U2459 ( .A0(Sgf_normalized_result[44]), .A1(n8437), .B0(
final_result_ieee[44]), .B1(n8436), .Y(n307) );
OR2X2TS U2460 ( .A(n4255), .B(Sgf_operation_ODD1_Q_right[32]), .Y(n987) );
ADDHX2TS U2461 ( .A(n3716), .B(n3715), .CO(n4799), .S(n3733) );
AO22X1TS U2462 ( .A0(Sgf_normalized_result[45]), .A1(n8437), .B0(
final_result_ieee[45]), .B1(n8436), .Y(n306) );
CLKMX2X2TS U2463 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(
n941), .Y(n415) );
OAI21X1TS U2464 ( .A0(n6001), .A1(n936), .B0(n5756), .Y(n5757) );
AO22X1TS U2465 ( .A0(Sgf_normalized_result[35]), .A1(n8435), .B0(
final_result_ieee[35]), .B1(n8434), .Y(n316) );
AO22X1TS U2466 ( .A0(Sgf_normalized_result[46]), .A1(n8437), .B0(
final_result_ieee[46]), .B1(n8436), .Y(n305) );
BUFX12TS U2467 ( .A(n2869), .Y(n3223) );
CLKMX2X2TS U2468 ( .A(n7699), .B(Add_result[35]), .S0(n7768), .Y(n544) );
AO22X1TS U2469 ( .A0(Sgf_normalized_result[34]), .A1(n8435), .B0(
final_result_ieee[34]), .B1(n8434), .Y(n317) );
CLKMX2X2TS U2470 ( .A(n7691), .B(Add_result[36]), .S0(n8432), .Y(n543) );
AO22X1TS U2471 ( .A0(Sgf_normalized_result[47]), .A1(n8437), .B0(
final_result_ieee[47]), .B1(n8436), .Y(n304) );
AO22X1TS U2472 ( .A0(Sgf_normalized_result[33]), .A1(n8435), .B0(
final_result_ieee[33]), .B1(n8434), .Y(n318) );
OAI21X1TS U2473 ( .A0(n5957), .A1(n936), .B0(n5752), .Y(n5753) );
CLKMX2X2TS U2474 ( .A(n7672), .B(Add_result[38]), .S0(n7768), .Y(n541) );
CLKMX2X2TS U2475 ( .A(n7619), .B(Add_result[43]), .S0(n8432), .Y(n536) );
AO22X1TS U2476 ( .A0(Sgf_normalized_result[48]), .A1(n8437), .B0(
final_result_ieee[48]), .B1(n8436), .Y(n303) );
AO22X1TS U2477 ( .A0(Sgf_normalized_result[32]), .A1(n8435), .B0(
final_result_ieee[32]), .B1(n8434), .Y(n319) );
OAI21X1TS U2478 ( .A0(n5957), .A1(n6014), .B0(n5554), .Y(n5555) );
AO22X1TS U2479 ( .A0(Sgf_normalized_result[31]), .A1(n8435), .B0(
final_result_ieee[31]), .B1(n8434), .Y(n320) );
OR2X2TS U2480 ( .A(n1504), .B(n1503), .Y(n7219) );
ADDHX2TS U2481 ( .A(n4763), .B(n4762), .CO(n5993), .S(mult_x_23_n945) );
ADDHX1TS U2482 ( .A(n1134), .B(n1133), .CO(n4728), .S(n1142) );
CLKMX2X2TS U2483 ( .A(n7960), .B(Add_result[16]), .S0(n7473), .Y(n563) );
OAI21X1TS U2484 ( .A0(n5762), .A1(n5985), .B0(n5662), .Y(n5664) );
OR2X2TS U2485 ( .A(n1091), .B(n1090), .Y(n1014) );
CLKMX2X2TS U2486 ( .A(n7871), .B(Add_result[22]), .S0(n8030), .Y(n557) );
CLKMX2X2TS U2487 ( .A(n7655), .B(Add_result[40]), .S0(n7666), .Y(n539) );
CMPR22X2TS U2488 ( .A(n5212), .B(n5211), .CO(n6059), .S(mult_x_23_n854) );
OAI21X1TS U2489 ( .A0(n5957), .A1(n6007), .B0(n5610), .Y(n5611) );
CLKMX2X2TS U2490 ( .A(n7643), .B(Add_result[41]), .S0(n7666), .Y(n538) );
OAI21X1TS U2491 ( .A0(n5957), .A1(n5985), .B0(n5956), .Y(n5958) );
ADDHX2TS U2492 ( .A(n835), .B(n6940), .CO(n6944), .S(mult_x_24_n1028) );
ADDHX2TS U2493 ( .A(n2229), .B(n2228), .CO(n2232), .S(n2322) );
CLKMX2X2TS U2494 ( .A(n8110), .B(Add_result[5]), .S0(n7473), .Y(n574) );
CLKMX2X2TS U2495 ( .A(n8098), .B(Add_result[6]), .S0(n8432), .Y(n573) );
CLKMX2X2TS U2496 ( .A(n7915), .B(Add_result[19]), .S0(n7473), .Y(n560) );
CLKMX2X2TS U2497 ( .A(n8138), .B(Add_result[3]), .S0(n8432), .Y(n576) );
AOI222X1TS U2498 ( .A0(n6817), .A1(n6756), .B0(n887), .B1(n6701), .C0(n6813),
.C1(n6816), .Y(n6664) );
CLKMX2X2TS U2499 ( .A(n7904), .B(Add_result[20]), .S0(n7666), .Y(n559) );
OAI21X1TS U2500 ( .A0(n5931), .A1(n5985), .B0(n5103), .Y(n5104) );
CLKMX2X2TS U2501 ( .A(n7629), .B(Add_result[42]), .S0(n7666), .Y(n537) );
CLKMX2X2TS U2502 ( .A(n7982), .B(Add_result[14]), .S0(n7473), .Y(n565) );
CLKMX2X2TS U2503 ( .A(n7996), .B(Add_result[13]), .S0(n7473), .Y(n566) );
AO21X1TS U2504 ( .A0(Sgf_normalized_result[52]), .A1(n8070), .B0(n7538), .Y(
n580) );
CLKMX2X2TS U2505 ( .A(n8016), .B(Add_result[12]), .S0(n7666), .Y(n567) );
CLKMX2X2TS U2506 ( .A(n8031), .B(Add_result[11]), .S0(n7473), .Y(n568) );
BUFX3TS U2507 ( .A(n7545), .Y(n7899) );
CLKMX2X2TS U2508 ( .A(n8045), .B(Add_result[10]), .S0(n7473), .Y(n569) );
XOR2X2TS U2509 ( .A(n1045), .B(n1044), .Y(n1046) );
OAI21X1TS U2510 ( .A0(n5931), .A1(n6035), .B0(n5524), .Y(n5525) );
AO21X1TS U2511 ( .A0(n3331), .A1(n2946), .B0(n3107), .Y(n3117) );
AO21X1TS U2512 ( .A0(n3231), .A1(n1990), .B0(n2692), .Y(n3095) );
ADDHX2TS U2513 ( .A(n6021), .B(n5909), .CO(n5211), .S(mult_x_23_n865) );
CLKMX2X2TS U2514 ( .A(n8086), .B(Add_result[7]), .S0(n8186), .Y(n572) );
XOR2X2TS U2515 ( .A(n4748), .B(n7064), .Y(n6938) );
BUFX3TS U2516 ( .A(n7545), .Y(n8183) );
OAI211X1TS U2517 ( .A0(n4698), .A1(n8428), .B0(n7483), .C0(n8070), .Y(n714)
);
CLKMX2X2TS U2518 ( .A(n7709), .B(Add_result[34]), .S0(n8432), .Y(n545) );
CLKMX2X2TS U2519 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(
n942), .Y(n416) );
AND2X2TS U2520 ( .A(n3672), .B(n7491), .Y(n5396) );
XOR2X2TS U2521 ( .A(n3696), .B(n895), .Y(n3716) );
AOI222X1TS U2522 ( .A0(n6817), .A1(n6847), .B0(n886), .B1(n6846), .C0(n6813),
.C1(n874), .Y(n6668) );
NOR2X1TS U2523 ( .A(n7959), .B(n8466), .Y(n7942) );
OR2X2TS U2524 ( .A(n4240), .B(Sgf_operation_ODD1_Q_right[31]), .Y(n991) );
CMPR22X2TS U2525 ( .A(n4761), .B(n4760), .CO(n4763), .S(mult_x_23_n950) );
INVX6TS U2526 ( .A(n3611), .Y(n5762) );
OAI21X1TS U2527 ( .A0(n6068), .A1(n5978), .B0(n5852), .Y(n5853) );
CLKMX2X2TS U2528 ( .A(P_Sgf[15]), .B(Sgf_operation_Result[15]), .S0(n8192),
.Y(n436) );
CLKMX2X2TS U2529 ( .A(P_Sgf[19]), .B(Sgf_operation_Result[19]), .S0(n8192),
.Y(n440) );
BUFX12TS U2530 ( .A(n1622), .Y(n3428) );
AOI222X1TS U2531 ( .A0(n6683), .A1(n6888), .B0(n886), .B1(n6886), .C0(n823),
.C1(n6884), .Y(n1135) );
OAI21X1TS U2532 ( .A0(n6068), .A1(n5861), .B0(n3698), .Y(n3699) );
AO21X1TS U2533 ( .A0(n7472), .A1(FSM_selector_B[0]), .B0(n7468), .Y(n419) );
CLKMX2X2TS U2534 ( .A(P_Sgf[23]), .B(Sgf_operation_Result[23]), .S0(n8192),
.Y(n444) );
AOI222X1TS U2535 ( .A0(n6683), .A1(n937), .B0(n887), .B1(n7071), .C0(n823),
.C1(n6569), .Y(n6678) );
CLKMX2X2TS U2536 ( .A(P_Sgf[20]), .B(Sgf_operation_Result[20]), .S0(n8192),
.Y(n441) );
NOR2X1TS U2537 ( .A(n7479), .B(n8367), .Y(n713) );
ADDHX2TS U2538 ( .A(n4686), .B(n4685), .CO(n6087), .S(mult_x_23_n911) );
AOI222X1TS U2539 ( .A0(n7036), .A1(n6853), .B0(n7034), .B1(n7082), .C0(n7032), .C1(Op_MX[9]), .Y(n6647) );
OR2X2TS U2540 ( .A(n3677), .B(n3676), .Y(n786) );
CLKMX2X2TS U2541 ( .A(P_Sgf[22]), .B(Sgf_operation_Result[22]), .S0(n8192),
.Y(n443) );
CLKMX2X2TS U2542 ( .A(P_Sgf[18]), .B(Sgf_operation_Result[18]), .S0(n8192),
.Y(n439) );
CLKMX2X2TS U2543 ( .A(P_Sgf[14]), .B(Sgf_operation_Result[14]), .S0(n8192),
.Y(n435) );
CLKMX2X2TS U2544 ( .A(P_Sgf[16]), .B(Sgf_operation_Result[16]), .S0(n8192),
.Y(n437) );
AOI222X1TS U2545 ( .A0(n6683), .A1(n6928), .B0(n887), .B1(n6915), .C0(n823),
.C1(n938), .Y(n6674) );
CLKMX2X2TS U2546 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(
n941), .Y(n417) );
BUFX12TS U2547 ( .A(n2877), .Y(n928) );
AOI222X1TS U2548 ( .A0(n6817), .A1(n927), .B0(n887), .B1(n6790), .C0(n823),
.C1(n6894), .Y(n6672) );
CLKMX2X2TS U2549 ( .A(P_Sgf[21]), .B(Sgf_operation_Result[21]), .S0(n8192),
.Y(n442) );
CLKMX2X2TS U2550 ( .A(P_Sgf[17]), .B(Sgf_operation_Result[17]), .S0(n8192),
.Y(n438) );
OAI21X1TS U2551 ( .A0(n8186), .A1(Sgf_normalized_result[2]), .B0(n7474), .Y(
n577) );
ADDHX2TS U2552 ( .A(n5094), .B(n5093), .CO(n5102), .S(n3803) );
NAND2X2TS U2553 ( .A(n962), .B(n961), .Y(n960) );
CLKMX2X2TS U2554 ( .A(Data_MX[60]), .B(Op_MX[60]), .S0(n7509), .Y(n706) );
CLKMX2X2TS U2555 ( .A(Data_MY[55]), .B(Op_MY[55]), .S0(n7495), .Y(n637) );
NAND2BX1TS U2556 ( .AN(n929), .B(n1708), .Y(n1520) );
AOI222X1TS U2557 ( .A0(n5983), .A1(n832), .B0(n5981), .B1(n5858), .C0(n5660),
.C1(n5892), .Y(n5656) );
CLKMX2X2TS U2558 ( .A(P_Sgf[25]), .B(Sgf_operation_Result[25]), .S0(n8224),
.Y(n446) );
CLKMX2X2TS U2559 ( .A(Data_MX[56]), .B(Op_MX[56]), .S0(n8353), .Y(n702) );
CLKMX2X2TS U2560 ( .A(Data_MY[60]), .B(Op_MY[60]), .S0(n7509), .Y(n642) );
NAND2X6TS U2561 ( .A(n3178), .B(n1355), .Y(n1429) );
AOI222X1TS U2562 ( .A0(n5983), .A1(n5858), .B0(n5981), .B1(n5998), .C0(n5660), .C1(n755), .Y(n5658) );
CLKMX2X2TS U2563 ( .A(P_Sgf[2]), .B(Sgf_operation_Result[2]), .S0(n8188),
.Y(n423) );
CLKMX2X2TS U2564 ( .A(Data_MX[58]), .B(Op_MX[58]), .S0(n7504), .Y(n704) );
AOI222X1TS U2565 ( .A0(n6839), .A1(Op_MX[4]), .B0(n7045), .B1(n6886), .C0(
n6615), .C1(n6884), .Y(n5046) );
CLKMX2X2TS U2566 ( .A(P_Sgf[3]), .B(Sgf_operation_Result[3]), .S0(n8188),
.Y(n424) );
NOR2X1TS U2567 ( .A(n7928), .B(n8465), .Y(n7914) );
NOR2X1TS U2568 ( .A(n7969), .B(n8469), .Y(n7970) );
AOI222X1TS U2569 ( .A0(n6889), .A1(n874), .B0(n6970), .B1(n6929), .C0(n6990),
.C1(n6928), .Y(n6631) );
CLKMX2X2TS U2570 ( .A(P_Sgf[27]), .B(n8196), .S0(n8224), .Y(n448) );
CLKMX2X2TS U2571 ( .A(Data_MY[59]), .B(Op_MY[59]), .S0(n7506), .Y(n641) );
NAND2X6TS U2572 ( .A(n2976), .B(n1800), .Y(n2097) );
AND2X2TS U2573 ( .A(n6060), .B(n5963), .Y(n5205) );
CLKMX2X2TS U2574 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n8353), .Y(n600) );
CLKMX2X2TS U2575 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n7495), .Y(n669) );
CLKMX2X2TS U2576 ( .A(P_Sgf[0]), .B(Sgf_operation_Result[0]), .S0(n8188),
.Y(n421) );
NAND2BX1TS U2577 ( .AN(n7232), .B(n1872), .Y(n1427) );
AOI222X1TS U2578 ( .A0(n6877), .A1(n6859), .B0(n7021), .B1(Op_MX[4]), .C0(
n7019), .C1(n6584), .Y(n6585) );
CLKMX2X2TS U2579 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n8353), .Y(n668) );
NAND2BX1TS U2580 ( .AN(n7232), .B(n2070), .Y(n1621) );
ADDHX2TS U2581 ( .A(Op_MX[44]), .B(n5910), .CO(n4685), .S(mult_x_23_n919) );
AOI222X1TS U2582 ( .A0(n7023), .A1(n7044), .B0(n7021), .B1(Op_MX[3]), .C0(
n7019), .C1(n6897), .Y(n6898) );
AOI222X1TS U2583 ( .A0(n6796), .A1(n6847), .B0(n6786), .B1(n6846), .C0(n6960), .C1(n874), .Y(n6521) );
AOI222X1TS U2584 ( .A0(n6839), .A1(n938), .B0(n7045), .B1(n7071), .C0(n6615),
.C1(n6569), .Y(n6602) );
CLKMX2X2TS U2585 ( .A(Data_MX[18]), .B(n927), .S0(n7504), .Y(n664) );
CLKMX2X2TS U2586 ( .A(Data_MY[27]), .B(n824), .S0(n7504), .Y(n609) );
CLKMX2X2TS U2587 ( .A(Data_MY[51]), .B(Op_MY[51]), .S0(n8353), .Y(n633) );
CLKMX2X2TS U2588 ( .A(Data_MY[29]), .B(n855), .S0(n896), .Y(n611) );
CLKMX2X2TS U2589 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n896), .Y(n612) );
CLKMX2X2TS U2590 ( .A(Data_MY[31]), .B(n8376), .S0(n7504), .Y(n613) );
CLKMX2X2TS U2591 ( .A(Data_MY[33]), .B(Op_MY[33]), .S0(n7506), .Y(n615) );
AOI222X1TS U2592 ( .A0(n6877), .A1(n7082), .B0(n6876), .B1(Op_MX[9]), .C0(
n6581), .C1(n7079), .Y(n6579) );
CLKMX2X2TS U2593 ( .A(Data_MY[35]), .B(n8385), .S0(n8353), .Y(n617) );
CLKMX2X2TS U2594 ( .A(Data_MY[36]), .B(n838), .S0(n896), .Y(n618) );
NAND2X6TS U2595 ( .A(n2940), .B(n1713), .Y(n1718) );
CLKMX2X2TS U2596 ( .A(Data_MY[53]), .B(Op_MY[53]), .S0(n7506), .Y(n635) );
CLKMX2X2TS U2597 ( .A(Data_MY[62]), .B(Op_MY[62]), .S0(n896), .Y(n644) );
CLKMX2X2TS U2598 ( .A(Data_MY[38]), .B(Op_MY[38]), .S0(n896), .Y(n620) );
CLKMX2X2TS U2599 ( .A(Data_MY[61]), .B(Op_MY[61]), .S0(n7509), .Y(n643) );
CLKMX2X2TS U2600 ( .A(Data_MY[57]), .B(Op_MY[57]), .S0(n7506), .Y(n639) );
CLKMX2X2TS U2601 ( .A(Data_MY[40]), .B(Op_MY[40]), .S0(n7504), .Y(n622) );
CLKMX2X2TS U2602 ( .A(Data_MX[52]), .B(Op_MX[52]), .S0(n7504), .Y(n698) );
CLKMX2X2TS U2603 ( .A(Data_MX[62]), .B(Op_MX[62]), .S0(n8353), .Y(n708) );
CLKMX2X2TS U2604 ( .A(Data_MY[42]), .B(Op_MY[42]), .S0(n7509), .Y(n624) );
NAND2BX1TS U2605 ( .AN(n2223), .B(n2784), .Y(n2083) );
AOI222X1TS U2606 ( .A0(n7047), .A1(n7046), .B0(n7045), .B1(n7044), .C0(n7043), .C1(n7042), .Y(n7048) );
CLKMX2X2TS U2607 ( .A(Data_MY[47]), .B(Op_MY[47]), .S0(n8353), .Y(n629) );
CLKMX2X2TS U2608 ( .A(Data_MY[48]), .B(Op_MY[48]), .S0(n8353), .Y(n630) );
CLKMX2X2TS U2609 ( .A(Data_MY[49]), .B(Op_MY[49]), .S0(n896), .Y(n631) );
CLKMX2X2TS U2610 ( .A(Data_MY[50]), .B(Op_MY[50]), .S0(n7504), .Y(n632) );
AO22X1TS U2611 ( .A0(n8433), .A1(Sgf_normalized_result[0]), .B0(n7768), .B1(
Add_result[0]), .Y(n579) );
XOR2X2TS U2612 ( .A(n3783), .B(n6002), .Y(n5094) );
NOR2X4TS U2613 ( .A(n8448), .B(n7546), .Y(n8039) );
NOR2X4TS U2614 ( .A(FSM_selector_C), .B(n7546), .Y(n7545) );
CLKMX2X2TS U2615 ( .A(Data_MY[56]), .B(Op_MY[56]), .S0(n896), .Y(n638) );
NAND2BX1TS U2616 ( .AN(n929), .B(n2287), .Y(n1501) );
ADDHX2TS U2617 ( .A(Op_MY[26]), .B(n4800), .CO(n4810), .S(n4816) );
CLKMX2X2TS U2618 ( .A(P_Sgf[26]), .B(Sgf_operation_Result[26]), .S0(n8224),
.Y(n447) );
CLKMX2X2TS U2619 ( .A(Data_MY[0]), .B(n8386), .S0(n8353), .Y(n582) );
CLKMX2X2TS U2620 ( .A(Data_MY[2]), .B(n8391), .S0(n7504), .Y(n584) );
XOR2X2TS U2621 ( .A(n4807), .B(n7076), .Y(n6942) );
CLKMX2X2TS U2622 ( .A(Data_MX[55]), .B(Op_MX[55]), .S0(n8353), .Y(n701) );
CLKMX2X2TS U2623 ( .A(Data_MY[5]), .B(n6695), .S0(n7495), .Y(n587) );
AO22X1TS U2624 ( .A0(n8433), .A1(Sgf_normalized_result[1]), .B0(n8432), .B1(
Add_result[1]), .Y(n578) );
CLKMX2X2TS U2625 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n7495), .Y(n588) );
AO22X1TS U2626 ( .A0(n8372), .A1(Data_MX[63]), .B0(n7509), .B1(Op_MX[63]),
.Y(n645) );
CLKMX2X2TS U2627 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n7495), .Y(n589) );
CLKMX2X2TS U2628 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n7506), .Y(n670) );
CLKMX2X2TS U2629 ( .A(Data_MY[58]), .B(Op_MY[58]), .S0(n7495), .Y(n640) );
CLKMX2X2TS U2630 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n7509), .Y(n591) );
CLKMX2X2TS U2631 ( .A(Data_MX[57]), .B(Op_MX[57]), .S0(n7495), .Y(n703) );
CLKMX2X2TS U2632 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n7506), .Y(n671) );
CLKMX2X2TS U2633 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n7509), .Y(n592) );
CLKMX2X2TS U2634 ( .A(Data_MX[61]), .B(Op_MX[61]), .S0(n7506), .Y(n707) );
BUFX12TS U2635 ( .A(n1828), .Y(n2738) );
CLKMX2X2TS U2636 ( .A(P_Sgf[24]), .B(Sgf_operation_Result[24]), .S0(n8224),
.Y(n445) );
CLKMX2X2TS U2637 ( .A(Data_MY[14]), .B(n7490), .S0(n7495), .Y(n596) );
CLKMX2X2TS U2638 ( .A(n8075), .B(Add_result[8]), .S0(n8030), .Y(n571) );
AOI222X1TS U2639 ( .A0(n6839), .A1(n6928), .B0(n7045), .B1(n6915), .C0(n6615), .C1(n938), .Y(n6598) );
CLKMX2X2TS U2640 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n7495), .Y(n595) );
CLKMX2X2TS U2641 ( .A(Data_MX[42]), .B(Op_MX[42]), .S0(n7501), .Y(n688) );
CLKMX2X2TS U2642 ( .A(Data_MX[43]), .B(Op_MX[43]), .S0(n7499), .Y(n689) );
CLKMX2X2TS U2643 ( .A(Data_MX[41]), .B(n7498), .S0(n7497), .Y(n687) );
BUFX16TS U2644 ( .A(n1990), .Y(n3188) );
CLKMX2X2TS U2645 ( .A(Data_MX[40]), .B(Op_MX[40]), .S0(n7502), .Y(n686) );
OR2X2TS U2646 ( .A(n8354), .B(n8430), .Y(n8355) );
CLKMX2X2TS U2647 ( .A(Data_MX[39]), .B(Op_MX[39]), .S0(n7499), .Y(n685) );
AOI222X1TS U2648 ( .A0(n5960), .A1(n8376), .B0(n5661), .B1(n830), .C0(n5660),
.C1(n8374), .Y(n3789) );
CLKMX2X2TS U2649 ( .A(Data_MX[38]), .B(n7500), .S0(n7502), .Y(n684) );
CLKMX2X2TS U2650 ( .A(Data_MX[37]), .B(Op_MX[37]), .S0(n7499), .Y(n683) );
XOR2X2TS U2651 ( .A(n8366), .B(n5255), .Y(DP_OP_36J24_124_1029_n28) );
CLKMX2X2TS U2652 ( .A(Data_MX[36]), .B(Op_MX[36]), .S0(n7501), .Y(n682) );
NAND2X2TS U2653 ( .A(n4474), .B(n4480), .Y(n4483) );
CLKMX2X2TS U2654 ( .A(Data_MX[34]), .B(Op_MX[34]), .S0(n7497), .Y(n680) );
CLKMX2X2TS U2655 ( .A(Data_MX[32]), .B(Op_MX[32]), .S0(n7499), .Y(n678) );
INVX2TS U2656 ( .A(n4574), .Y(n4575) );
AO21X1TS U2657 ( .A0(n4730), .A1(n6244), .B0(n4729), .Y(n790) );
INVX12TS U2658 ( .A(n3051), .Y(n2997) );
INVX4TS U2659 ( .A(n8433), .Y(n8432) );
CLKMX2X2TS U2660 ( .A(Data_MX[48]), .B(Op_MX[48]), .S0(n7501), .Y(n694) );
CLKMX2X2TS U2661 ( .A(Data_MX[47]), .B(n7493), .S0(n7502), .Y(n693) );
CLKMX2X2TS U2662 ( .A(Data_MX[8]), .B(n8413), .S0(n7496), .Y(n654) );
CLKMX2X2TS U2663 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n7496), .Y(n653) );
CLKMX2X2TS U2664 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n7501), .Y(n652) );
CLKMX2X2TS U2665 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n7502), .Y(n650) );
CLKMX2X2TS U2666 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n7499), .Y(n649) );
CLKMX2X2TS U2667 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n7497), .Y(n647) );
INVX12TS U2668 ( .A(n3367), .Y(n3227) );
AOI222X1TS U2669 ( .A0(n1047), .A1(Op_MX[9]), .B0(n6727), .B1(n6910), .C0(
n6914), .C1(n6909), .Y(n6728) );
CLKMX2X2TS U2670 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n7497), .Y(n601) );
CLKMX2X2TS U2671 ( .A(Data_MY[20]), .B(n7494), .S0(n7501), .Y(n602) );
OAI21X2TS U2672 ( .A0(n5043), .A1(n7062), .B0(n981), .Y(n4744) );
CLKMX2X2TS U2673 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n7501), .Y(n603) );
OAI21X1TS U2674 ( .A0(n1001), .A1(n5861), .B0(n3640), .Y(n3641) );
CLKMX2X2TS U2675 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n7497), .Y(n606) );
INVX4TS U2676 ( .A(n8433), .Y(n7666) );
CLKMX2X2TS U2677 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n7501), .Y(n607) );
CLKMX2X2TS U2678 ( .A(Data_MY[26]), .B(n8393), .S0(n7499), .Y(n608) );
CLKMX2X2TS U2679 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n7501), .Y(n677) );
CLKMX2X2TS U2680 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n7497), .Y(n676) );
CLKMX2X2TS U2681 ( .A(Data_MX[29]), .B(n7491), .S0(n7501), .Y(n675) );
CLKMX2X2TS U2682 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n7497), .Y(n674) );
CLKMX2X2TS U2683 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n7502), .Y(n673) );
INVX4TS U2684 ( .A(n8372), .Y(n7506) );
AO21X1TS U2685 ( .A0(n868), .A1(n5769), .B0(n5825), .Y(n5573) );
INVX4TS U2686 ( .A(n8372), .Y(n7495) );
INVX4TS U2687 ( .A(n8372), .Y(n8353) );
INVX4TS U2688 ( .A(n8372), .Y(n896) );
INVX12TS U2689 ( .A(n3426), .Y(n3343) );
CLKMX2X2TS U2690 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n7496), .Y(n662) );
CLKMX2X2TS U2691 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n7496), .Y(n656) );
XOR2X2TS U2692 ( .A(n4659), .B(n5847), .Y(n4682) );
CLKMX2X2TS U2693 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n7496), .Y(n659) );
CLKMX2X2TS U2694 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n7496), .Y(n655) );
AOI222X1TS U2695 ( .A0(n885), .A1(n874), .B0(n6727), .B1(n6929), .C0(n7003),
.C1(n6928), .Y(n6931) );
CLKMX2X2TS U2696 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n7496), .Y(n661) );
NAND2BX1TS U2697 ( .AN(n8368), .B(P_Sgf[105]), .Y(n7472) );
NAND2X1TS U2698 ( .A(n6065), .B(n824), .Y(n4970) );
NAND3X2TS U2699 ( .A(n1059), .B(n1058), .C(n1057), .Y(n6693) );
NAND2X4TS U2700 ( .A(n2627), .B(n1420), .Y(n2628) );
AOI222X1TS U2701 ( .A0(n6081), .A1(n848), .B0(n6079), .B1(n830), .C0(n5964),
.C1(n8374), .Y(n3683) );
NOR2X1TS U2702 ( .A(n7718), .B(n7522), .Y(n7530) );
AOI222X1TS U2703 ( .A0(n7083), .A1(n6859), .B0(n7058), .B1(Op_MX[4]), .C0(
n7057), .C1(n6584), .Y(n6374) );
NOR2X4TS U2704 ( .A(n1673), .B(n1753), .Y(n1700) );
NOR2X1TS U2705 ( .A(n8368), .B(P_Sgf[105]), .Y(n7477) );
CLKAND2X2TS U2706 ( .A(n6440), .B(n7001), .Y(n6378) );
INVX2TS U2707 ( .A(n4103), .Y(n4097) );
INVX2TS U2708 ( .A(n4600), .Y(n4602) );
INVX2TS U2709 ( .A(n4300), .Y(n4302) );
INVX2TS U2710 ( .A(n4336), .Y(n4338) );
OAI21X2TS U2711 ( .A0(n4266), .A1(n4263), .B0(n4267), .Y(n4032) );
INVX2TS U2712 ( .A(n4364), .Y(n4366) );
INVX2TS U2713 ( .A(n4557), .Y(n4559) );
INVX2TS U2714 ( .A(n4314), .Y(n4316) );
XOR2X2TS U2715 ( .A(n1799), .B(n1798), .Y(n1800) );
INVX2TS U2716 ( .A(n4568), .Y(n4570) );
INVX1TS U2717 ( .A(n4373), .Y(n4375) );
BUFX16TS U2718 ( .A(n3796), .Y(n5653) );
NOR2X4TS U2719 ( .A(n4562), .B(n4568), .Y(n4573) );
INVX2TS U2720 ( .A(n4216), .Y(n4218) );
NOR2X1TS U2721 ( .A(n8097), .B(n8468), .Y(n8085) );
AOI222X1TS U2722 ( .A0(n7060), .A1(n7044), .B0(n7058), .B1(Op_MX[3]), .C0(
n7057), .C1(n6897), .Y(n6881) );
INVX2TS U2723 ( .A(n4176), .Y(n4178) );
AOI222X1TS U2724 ( .A0(n7083), .A1(n7082), .B0(n7081), .B1(Op_MX[9]), .C0(
n7080), .C1(n7079), .Y(n7084) );
INVX2TS U2725 ( .A(n4250), .Y(n4252) );
OAI21X1TS U2726 ( .A0(n6053), .A1(n5861), .B0(n3644), .Y(n3645) );
BUFX8TS U2727 ( .A(n3853), .Y(n5904) );
OR2X2TS U2728 ( .A(n4551), .B(Sgf_operation_ODD1_Q_middle[54]), .Y(n4638) );
NOR2X1TS U2729 ( .A(n8126), .B(Sgf_normalized_result[4]), .Y(n8109) );
NAND2X4TS U2730 ( .A(n6232), .B(n6230), .Y(n6458) );
NAND2X2TS U2731 ( .A(n4544), .B(n4543), .Y(n4547) );
CLKMX2X2TS U2732 ( .A(Op_MX[54]), .B(exp_oper_result[2]), .S0(n846), .Y(
S_Oper_A_exp[2]) );
NAND2X4TS U2733 ( .A(n1064), .B(n1093), .Y(n1121) );
NAND2X2TS U2734 ( .A(n1252), .B(n1251), .Y(n5399) );
OR2X2TS U2735 ( .A(n4536), .B(n4535), .Y(n4540) );
CLKMX2X2TS U2736 ( .A(Op_MX[58]), .B(exp_oper_result[6]), .S0(n847), .Y(
S_Oper_A_exp[6]) );
CLKMX2X2TS U2737 ( .A(Op_MX[59]), .B(exp_oper_result[7]), .S0(n847), .Y(
S_Oper_A_exp[7]) );
CLKMX2X2TS U2738 ( .A(Op_MX[60]), .B(exp_oper_result[8]), .S0(n847), .Y(
S_Oper_A_exp[8]) );
OR2X2TS U2739 ( .A(n4511), .B(n4510), .Y(n4518) );
CLKMX2X2TS U2740 ( .A(Op_MX[61]), .B(exp_oper_result[9]), .S0(n847), .Y(
S_Oper_A_exp[9]) );
CLKMX2X2TS U2741 ( .A(Op_MX[62]), .B(exp_oper_result[10]), .S0(n847), .Y(
S_Oper_A_exp[10]) );
NOR2X6TS U2742 ( .A(n7533), .B(n7535), .Y(n8366) );
NOR2X4TS U2743 ( .A(n6287), .B(n6395), .Y(n3818) );
NAND2X4TS U2744 ( .A(n1793), .B(n1798), .Y(n1791) );
OAI21X4TS U2745 ( .A0(n7534), .A1(n4649), .B0(n7533), .Y(n8189) );
CLKAND2X2TS U2746 ( .A(n6946), .B(n874), .Y(n4741) );
BUFX8TS U2747 ( .A(n6512), .Y(n6786) );
INVX2TS U2748 ( .A(n1327), .Y(n1310) );
INVX2TS U2749 ( .A(n2241), .Y(n2005) );
AND2X2TS U2750 ( .A(n7078), .B(n8414), .Y(n6936) );
CLKAND2X2TS U2751 ( .A(n7078), .B(n826), .Y(n7091) );
AND2X2TS U2752 ( .A(n7078), .B(n6958), .Y(mult_x_24_n1100) );
CLKAND2X2TS U2753 ( .A(n7078), .B(n6863), .Y(mult_x_24_n1105) );
INVX1TS U2754 ( .A(n7940), .Y(n7941) );
ADDFHX2TS U2755 ( .A(Sgf_operation_ODD1_Q_middle[40]), .B(n7631), .CI(n4446),
.CO(n4452), .S(n4451) );
INVX4TS U2756 ( .A(n2205), .Y(n3853) );
OR2X2TS U2757 ( .A(n4542), .B(Sgf_operation_ODD1_Q_middle[52]), .Y(n4543) );
INVX1TS U2758 ( .A(n7993), .Y(n7994) );
AND2X2TS U2759 ( .A(Op_MY[26]), .B(n8403), .Y(n6217) );
INVX2TS U2760 ( .A(n1455), .Y(n1444) );
NOR2X1TS U2761 ( .A(n8058), .B(n7526), .Y(n7528) );
NOR2X1TS U2762 ( .A(n7940), .B(n7524), .Y(n7525) );
ADDFHX2TS U2763 ( .A(Sgf_operation_ODD1_Q_middle[16]), .B(n3964), .CI(n3963),
.CO(n3965), .S(n4001) );
OR2X2TS U2764 ( .A(n4007), .B(Sgf_operation_ODD1_Q_middle[1]), .Y(n4010) );
INVX2TS U2765 ( .A(n1670), .Y(n1604) );
ADDFHX2TS U2766 ( .A(Sgf_operation_ODD1_Q_middle[18]), .B(n3970), .CI(n3969),
.CO(n3973), .S(n3972) );
NOR2X1TS U2767 ( .A(n7721), .B(n7520), .Y(n7521) );
NOR2X1TS U2768 ( .A(n7826), .B(n7517), .Y(n7518) );
NAND2X4TS U2769 ( .A(n902), .B(n855), .Y(n3646) );
ADDFHX2TS U2770 ( .A(Sgf_operation_ODD1_Q_middle[19]), .B(n3977), .CI(n3976),
.CO(n3985), .S(n3974) );
ADDFHX2TS U2771 ( .A(Sgf_operation_ODD1_Q_middle[14]), .B(n4053), .CI(n4052),
.CO(n4070), .S(n4069) );
INVX1TS U2772 ( .A(n8108), .Y(n8126) );
AND2X2TS U2773 ( .A(n6946), .B(n6945), .Y(mult_x_24_n1094) );
INVX6TS U2774 ( .A(n1034), .Y(n3866) );
XOR2X2TS U2775 ( .A(Op_MX[10]), .B(Op_MX[37]), .Y(n1377) );
INVX12TS U2776 ( .A(n793), .Y(n7492) );
XOR2X2TS U2777 ( .A(n747), .B(n748), .Y(n1401) );
XOR2X2TS U2778 ( .A(n3628), .B(n7493), .Y(n3629) );
OR2X2TS U2779 ( .A(n903), .B(n8374), .Y(n996) );
NAND2X4TS U2780 ( .A(n3572), .B(n4820), .Y(n3592) );
CLKINVX6TS U2781 ( .A(n3281), .Y(n901) );
XOR2X4TS U2782 ( .A(n742), .B(n1034), .Y(n6058) );
OA21X1TS U2783 ( .A0(n5437), .A1(n4965), .B0(n5214), .Y(n742) );
OAI21X2TS U2784 ( .A0(n6053), .A1(n4671), .B0(n4676), .Y(n4677) );
OAI21X1TS U2785 ( .A0(n7379), .A1(n7378), .B0(n7377), .Y(n7384) );
INVX8TS U2786 ( .A(n752), .Y(n753) );
OAI21X1TS U2787 ( .A0(n4888), .A1(n4877), .B0(n4876), .Y(n4878) );
NOR2X4TS U2788 ( .A(n7068), .B(n7056), .Y(n6353) );
XOR2X2TS U2789 ( .A(n7329), .B(n763), .Y(Sgf_operation_ODD1_middle_N46) );
NAND2X2TS U2790 ( .A(n4985), .B(n4980), .Y(n1228) );
NOR2X4TS U2791 ( .A(mult_x_23_n898), .B(mult_x_23_n905), .Y(n5333) );
BUFX6TS U2792 ( .A(n1130), .Y(n6819) );
OAI21X2TS U2793 ( .A0(n6194), .A1(n6200), .B0(n6195), .Y(n1107) );
NAND2X6TS U2794 ( .A(n771), .B(n791), .Y(n7315) );
OR2X4TS U2795 ( .A(n3544), .B(n3543), .Y(n771) );
XNOR2X2TS U2796 ( .A(n3349), .B(n3383), .Y(n2992) );
BUFX4TS U2797 ( .A(n3717), .Y(n5701) );
OAI21X2TS U2798 ( .A0(Op_MX[6]), .A1(Op_MX[33]), .B0(Op_MX[5]), .Y(n1342) );
OAI21X1TS U2799 ( .A0(n7379), .A1(n7253), .B0(n7252), .Y(n7256) );
OAI21X2TS U2800 ( .A0(n7293), .A1(n7300), .B0(n7301), .Y(n4823) );
XNOR2X2TS U2801 ( .A(n899), .B(n3074), .Y(n3075) );
CLKXOR2X2TS U2802 ( .A(n1050), .B(n8445), .Y(n1104) );
OAI22X1TS U2803 ( .A0(n1651), .A1(n3427), .B0(n1623), .B1(n1622), .Y(n1652)
);
AOI222X2TS U2804 ( .A0(n7072), .A1(n6886), .B0(n7070), .B1(n7022), .C0(n6473), .C1(n7020), .Y(n4801) );
OAI21X4TS U2805 ( .A0(n7776), .A1(n4632), .B0(n4631), .Y(n4633) );
ADDFHX2TS U2806 ( .A(n2104), .B(n2103), .CI(n2102), .CO(n2115), .S(n2110) );
ADDFHX2TS U2807 ( .A(n3241), .B(n3240), .CI(n3239), .CO(n3315), .S(n3263) );
ADDFHX2TS U2808 ( .A(n3164), .B(n3163), .CI(n3162), .CO(n3216), .S(n3205) );
NAND2X4TS U2809 ( .A(mult_x_23_n835), .B(mult_x_23_n845), .Y(n5312) );
NAND2X4TS U2810 ( .A(n3601), .B(n3646), .Y(n1222) );
OAI21X1TS U2811 ( .A0(n5896), .A1(n5684), .B0(n5683), .Y(n5685) );
OAI21X4TS U2812 ( .A0(n4250), .A1(n4246), .B0(n4251), .Y(n4242) );
XNOR2X2TS U2813 ( .A(n856), .B(n1611), .Y(n1483) );
NAND2X4TS U2814 ( .A(n1318), .B(n1317), .Y(n1413) );
NAND2X2TS U2815 ( .A(n4870), .B(n5221), .Y(n4872) );
ADDFHX2TS U2816 ( .A(n3505), .B(n3504), .CI(n3503), .CO(n3510), .S(n3500) );
NOR2X6TS U2817 ( .A(mult_x_23_n888), .B(mult_x_23_n897), .Y(n5335) );
XOR2X2TS U2818 ( .A(n6546), .B(n6827), .Y(mult_x_24_n1520) );
NAND2X2TS U2819 ( .A(n6268), .B(n6245), .Y(n6247) );
ADDFHX2TS U2820 ( .A(n2150), .B(n2149), .CI(n2148), .CO(n2174), .S(n2167) );
INVX12TS U2821 ( .A(n944), .Y(n2869) );
ADDFX2TS U2822 ( .A(Sgf_operation_ODD1_Q_middle[17]), .B(n3968), .CI(n3967),
.CO(n3971), .S(n3966) );
XOR2X2TS U2823 ( .A(n4119), .B(n4118), .Y(n4420) );
ADDFHX2TS U2824 ( .A(n3247), .B(n3246), .CI(n3245), .CO(n3274), .S(n3243) );
NAND2X6TS U2825 ( .A(n3301), .B(n1381), .Y(n1751) );
NOR2X4TS U2826 ( .A(n6155), .B(n6153), .Y(n6148) );
OAI21X2TS U2827 ( .A0(n6092), .A1(n6088), .B0(n6089), .Y(n5236) );
NOR2X2TS U2828 ( .A(n5402), .B(n5535), .Y(n1254) );
ADDFHX2TS U2829 ( .A(n1524), .B(n1523), .CI(n1522), .CO(n1533), .S(n1516) );
XOR2X2TS U2830 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n1417) );
AOI21X4TS U2831 ( .A0(n5013), .A1(n5017), .B0(n1281), .Y(n1282) );
OAI21X4TS U2832 ( .A0(n5026), .A1(n1287), .B0(n5028), .Y(n5013) );
ADDFHX2TS U2833 ( .A(n2372), .B(n2371), .CI(n2370), .CO(n2405), .S(n2411) );
OAI21X4TS U2834 ( .A0(Op_MX[4]), .A1(Op_MX[31]), .B0(Op_MX[3]), .Y(n1314) );
OAI21X1TS U2835 ( .A0(n5957), .A1(n5978), .B0(n5704), .Y(n5705) );
OAI21X1TS U2836 ( .A0(n5957), .A1(n5904), .B0(n4979), .Y(mult_x_23_n1250) );
INVX8TS U2837 ( .A(n4974), .Y(n4999) );
XNOR2X2TS U2838 ( .A(n5219), .B(n5218), .Y(Sgf_operation_ODD1_right_N32) );
NAND2X2TS U2839 ( .A(n6213), .B(n6214), .Y(n6212) );
ADDFHX2TS U2840 ( .A(n1660), .B(n1659), .CI(n1658), .CO(n1693), .S(n1683) );
NAND2X4TS U2841 ( .A(n1342), .B(n1341), .Y(n1394) );
ADDFHX2TS U2842 ( .A(n1487), .B(n1486), .CI(n1485), .CO(n1640), .S(n1497) );
ADDFHX2TS U2843 ( .A(n2043), .B(n2042), .CI(n2041), .CO(n2011), .S(n2056) );
AOI21X2TS U2844 ( .A0(n7325), .A1(n4821), .B0(n3917), .Y(n3918) );
AO21X4TS U2845 ( .A0(n744), .A1(n745), .B0(n746), .Y(n4697) );
INVX4TS U2846 ( .A(n891), .Y(n744) );
AO21X2TS U2847 ( .A0(n7325), .A1(n4694), .B0(n4693), .Y(n746) );
NAND2X4TS U2848 ( .A(n2449), .B(n2450), .Y(n7438) );
OAI21X1TS U2849 ( .A0(n7362), .A1(n7379), .B0(n7361), .Y(n7367) );
ADDFHX2TS U2850 ( .A(n1870), .B(n1869), .CI(n1868), .CO(n2180), .S(n1919) );
ADDFHX2TS U2851 ( .A(n1824), .B(n1823), .CI(n1822), .CO(n1916), .S(n1853) );
OAI21X2TS U2852 ( .A0(n6092), .A1(n5243), .B0(n5242), .Y(n5248) );
CMPR42X2TS U2853 ( .A(mult_x_24_n703), .B(mult_x_24_n707), .C(
mult_x_24_n1429), .D(mult_x_24_n1402), .ICI(mult_x_24_n704), .S(
mult_x_24_n702), .ICO(mult_x_24_n700), .CO(mult_x_24_n701) );
OAI21X2TS U2854 ( .A0(n7430), .A1(n3578), .B0(n3577), .Y(n3590) );
OAI21X2TS U2855 ( .A0(n7306), .A1(n4826), .B0(n7312), .Y(n4827) );
NOR2X4TS U2856 ( .A(n3564), .B(n3563), .Y(n4826) );
XNOR2X2TS U2857 ( .A(n856), .B(n1740), .Y(n1689) );
XNOR2X2TS U2858 ( .A(n3330), .B(n2221), .Y(n2974) );
OAI21X2TS U2859 ( .A0(n7295), .A1(n3592), .B0(n3591), .Y(n3593) );
OAI21X2TS U2860 ( .A0(n979), .A1(n6035), .B0(n5438), .Y(n5439) );
NAND2X4TS U2861 ( .A(n7323), .B(n3594), .Y(n3596) );
NOR2X4TS U2862 ( .A(n7305), .B(n4826), .Y(n4828) );
OAI21X2TS U2863 ( .A0(n6092), .A1(n5250), .B0(n5249), .Y(n5253) );
INVX12TS U2864 ( .A(n4834), .Y(n6092) );
INVX4TS U2865 ( .A(n1287), .Y(n5029) );
BUFX20TS U2866 ( .A(Op_MX[19]), .Y(n6930) );
CMPR42X2TS U2867 ( .A(n8444), .B(mult_x_24_n1094), .C(mult_x_24_n1092), .D(
mult_x_24_n1433), .ICI(mult_x_24_n1460), .S(mult_x_24_n726), .ICO(
mult_x_24_n724), .CO(mult_x_24_n725) );
AOI21X2TS U2868 ( .A0(n7325), .A1(n7318), .B0(n7317), .Y(n7319) );
OAI22X2TS U2869 ( .A0(n1748), .A1(n2940), .B0(n1718), .B1(n1717), .Y(n1749)
);
ADDFHX2TS U2870 ( .A(n3175), .B(n3174), .CI(n3173), .CO(n3261), .S(n3208) );
ADDFHX2TS U2871 ( .A(n3210), .B(n3209), .CI(n3208), .CO(n3239), .S(n3213) );
OAI21X2TS U2872 ( .A0(n891), .A1(n3919), .B0(n3918), .Y(n3921) );
XOR2X1TS U2873 ( .A(n6605), .B(n7051), .Y(mult_x_24_n1562) );
OAI21X1TS U2874 ( .A0(n7075), .A1(n6841), .B0(n6604), .Y(n6605) );
XOR2X4TS U2875 ( .A(n5110), .B(n976), .Y(Sgf_operation_ODD1_middle_N40) );
XOR2X4TS U2876 ( .A(Op_MX[29]), .B(Op_MX[28]), .Y(n3652) );
OAI21X4TS U2877 ( .A0(n5359), .A1(n5952), .B0(n5360), .Y(n3744) );
OAI21X4TS U2878 ( .A0(n6141), .A1(n6948), .B0(n6142), .Y(n956) );
NOR2X4TS U2879 ( .A(n6947), .B(n6141), .Y(n957) );
NAND2X4TS U2880 ( .A(n8005), .B(n4423), .Y(n4425) );
NAND2X4TS U2881 ( .A(n851), .B(n8374), .Y(n3601) );
OR2X4TS U2882 ( .A(n8374), .B(n851), .Y(n1002) );
NOR2X4TS U2883 ( .A(n851), .B(n848), .Y(n3655) );
NAND2X4TS U2884 ( .A(n851), .B(n848), .Y(n3679) );
OAI21X1TS U2885 ( .A0(n1001), .A1(n5569), .B0(n5832), .Y(n5833) );
OR2X4TS U2886 ( .A(mult_x_24_n778), .B(mult_x_24_n787), .Y(n4846) );
OAI21X4TS U2887 ( .A0(Op_MX[20]), .A1(Op_MX[47]), .B0(Op_MX[19]), .Y(n1989)
);
OAI21X4TS U2888 ( .A0(n5271), .A1(n5157), .B0(n5156), .Y(n5160) );
INVX12TS U2889 ( .A(n3772), .Y(n5271) );
INVX16TS U2890 ( .A(n6735), .Y(n815) );
AOI21X4TS U2891 ( .A0(n4846), .A1(n1189), .B0(n1188), .Y(n1190) );
XOR2X2TS U2892 ( .A(n7000), .B(n8373), .Y(mult_x_24_n1549) );
NOR2X6TS U2893 ( .A(mult_x_24_n1023), .B(mult_x_24_n1030), .Y(n6155) );
AOI222X4TS U2894 ( .A0(n6848), .A1(n6847), .B0(n7045), .B1(n6846), .C0(n6997), .C1(n6930), .Y(n6849) );
AOI222X1TS U2895 ( .A0(n6839), .A1(n6884), .B0(n7045), .B1(n7020), .C0(n6615), .C1(n7018), .Y(n5037) );
NOR2X4TS U2896 ( .A(Op_MY[35]), .B(Op_MY[8]), .Y(n1431) );
NAND2X4TS U2897 ( .A(Op_MY[35]), .B(Op_MY[8]), .Y(n1433) );
OAI21X2TS U2898 ( .A0(n8326), .A1(n8325), .B0(n8324), .Y(n8333) );
OAI21X4TS U2899 ( .A0(n4323), .A1(n4322), .B0(n4321), .Y(n4372) );
ADDFHX2TS U2900 ( .A(n1142), .B(n1141), .CI(n1140), .CO(n1156), .S(n1155) );
NOR2X6TS U2901 ( .A(n7775), .B(n4632), .Y(n4634) );
ADDFHX2TS U2902 ( .A(n2112), .B(n2111), .CI(n2110), .CO(n2141), .S(n2157) );
CLKINVX12TS U2903 ( .A(Op_MY[17]), .Y(n8444) );
NOR2X8TS U2904 ( .A(Op_MY[44]), .B(Op_MY[17]), .Y(n1780) );
CLKXOR2X2TS U2905 ( .A(n3671), .B(n5804), .Y(n5395) );
NOR2X2TS U2906 ( .A(n5394), .B(n5393), .Y(n5391) );
OAI21X2TS U2907 ( .A0(n7026), .A1(n6788), .B0(n4722), .Y(n4723) );
XOR2X4TS U2908 ( .A(n5040), .B(n7027), .Y(n5048) );
OAI21X2TS U2909 ( .A0(n7893), .A1(n7905), .B0(n7894), .Y(n4615) );
ADDFHX2TS U2910 ( .A(n4051), .B(Sgf_operation_ODD1_Q_middle[15]), .CI(n4050),
.CO(n4000), .S(n4071) );
OAI21X2TS U2911 ( .A0(n7919), .A1(n7930), .B0(n7920), .Y(n7888) );
OAI21X2TS U2912 ( .A0(n5293), .A1(n5301), .B0(n5294), .Y(n3759) );
CMPR42X2TS U2913 ( .A(mult_x_23_n839), .B(mult_x_23_n1466), .C(
mult_x_23_n1414), .D(mult_x_23_n1440), .ICI(mult_x_23_n840), .S(
mult_x_23_n827), .ICO(mult_x_23_n825), .CO(mult_x_23_n826) );
NAND2X4TS U2914 ( .A(n1075), .B(n1074), .Y(n1040) );
ADDFHX2TS U2915 ( .A(n3733), .B(n3732), .CI(n3731), .CO(n3734), .S(n3714) );
XOR2X4TS U2916 ( .A(n4561), .B(n4560), .Y(n4605) );
INVX16TS U2917 ( .A(n6735), .Y(n816) );
CMPR42X2TS U2918 ( .A(mult_x_24_n1465), .B(mult_x_24_n1519), .C(
mult_x_24_n1492), .D(mult_x_24_n765), .ICI(mult_x_24_n774), .S(
mult_x_24_n763), .ICO(mult_x_24_n761), .CO(mult_x_24_n762) );
ADDFHX2TS U2919 ( .A(n5995), .B(n5994), .CI(n5993), .CO(n3801), .S(
mult_x_23_n938) );
AOI21X4TS U2920 ( .A0(n5352), .A1(n5350), .B0(n3747), .Y(n3748) );
XOR2X1TS U2921 ( .A(n3931), .B(n969), .Y(Sgf_operation_ODD1_middle_N50) );
OAI21X2TS U2922 ( .A0(n7295), .A1(n3923), .B0(n3922), .Y(n3924) );
NOR2X4TS U2923 ( .A(mult_x_23_n877), .B(mult_x_23_n868), .Y(n5324) );
ADDFHX4TS U2924 ( .A(n4691), .B(n4690), .CI(n4689), .CO(mult_x_23_n882), .S(
mult_x_23_n883) );
NAND2X4TS U2925 ( .A(n6449), .B(n6462), .Y(n1206) );
BUFX8TS U2926 ( .A(Op_MX[20]), .Y(n876) );
XOR2X2TS U2927 ( .A(Op_MX[20]), .B(Op_MX[47]), .Y(n1985) );
NOR2X6TS U2928 ( .A(mult_x_23_n698), .B(mult_x_23_n707), .Y(n4857) );
CMPR42X2TS U2929 ( .A(n793), .B(mult_x_23_n733), .C(mult_x_23_n1250), .D(
mult_x_23_n1300), .ICI(mult_x_23_n1352), .S(mult_x_23_n723), .ICO(
mult_x_23_n714), .CO(mult_x_23_n722) );
NOR2X6TS U2930 ( .A(n1176), .B(n6127), .Y(n1178) );
OR2X8TS U2931 ( .A(mult_x_24_n955), .B(mult_x_24_n965), .Y(n6124) );
XOR2X2TS U2932 ( .A(n4706), .B(n6220), .Y(n5074) );
OAI21X2TS U2933 ( .A0(n5043), .A1(n6792), .B0(n4705), .Y(n4706) );
NOR2X4TS U2934 ( .A(n7508), .B(n850), .Y(n3618) );
NOR2X8TS U2935 ( .A(n7315), .B(n3555), .Y(n4821) );
NOR2X4TS U2936 ( .A(n7292), .B(n7294), .Y(n7297) );
XNOR2X2TS U2937 ( .A(n3384), .B(n3167), .Y(n3003) );
XNOR2X2TS U2938 ( .A(n3334), .B(n3167), .Y(n2990) );
BUFX20TS U2939 ( .A(n3249), .Y(n3334) );
OAI21X4TS U2940 ( .A0(n5335), .A1(n5340), .B0(n5336), .Y(n5987) );
CMPR22X2TS U2941 ( .A(n6087), .B(n6086), .CO(n5138), .S(mult_x_23_n903) );
NOR2X4TS U2942 ( .A(n3723), .B(n3618), .Y(n4975) );
NOR2X2TS U2943 ( .A(n5027), .B(n1287), .Y(n5012) );
OAI21X1TS U2944 ( .A0(n6933), .A1(n7074), .B0(n6408), .Y(n6409) );
BUFX12TS U2945 ( .A(n5494), .Y(n6031) );
NOR2X4TS U2946 ( .A(n7238), .B(n7239), .Y(n7335) );
NAND2X2TS U2947 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n1318) );
ADDFHX2TS U2948 ( .A(n3274), .B(n3273), .CI(n3272), .CO(n3375), .S(n3270) );
OAI21X1TS U2949 ( .A0(n5876), .A1(n5985), .B0(n5651), .Y(n5652) );
OAI21X1TS U2950 ( .A0(n5876), .A1(n5978), .B0(n5702), .Y(n5703) );
OAI21X1TS U2951 ( .A0(n5876), .A1(n6014), .B0(n5550), .Y(n5551) );
OAI21X1TS U2952 ( .A0(n5876), .A1(n6035), .B0(n5518), .Y(n5519) );
AOI21X2TS U2953 ( .A0(n4866), .A1(n1028), .B0(n4865), .Y(n4867) );
OAI21X4TS U2954 ( .A0(n4161), .A1(n4003), .B0(n3995), .Y(n4142) );
AOI21X2TS U2955 ( .A0(n4334), .A1(n4002), .B0(n3975), .Y(n4161) );
OAI21X2TS U2956 ( .A0(n4595), .A1(n4591), .B0(n4592), .Y(n4585) );
NAND2X4TS U2957 ( .A(mult_x_23_n683), .B(mult_x_23_n689), .Y(n5158) );
OAI21X4TS U2958 ( .A0(n5271), .A1(n5261), .B0(n5260), .Y(n5264) );
AOI21X4TS U2959 ( .A0(n5259), .A1(n5258), .B0(n5257), .Y(n5260) );
AOI21X2TS U2960 ( .A0(n8103), .A1(n8062), .B0(n8061), .Y(n8080) );
OAI21X2TS U2961 ( .A0(n4236), .A1(n8202), .B0(n4235), .Y(n8213) );
NAND2X1TS U2962 ( .A(n781), .B(n731), .Y(n4236) );
AOI21X2TS U2963 ( .A0(n986), .A1(n8198), .B0(n4231), .Y(n8202) );
OAI21X2TS U2964 ( .A0(n7026), .A1(n6792), .B0(n5077), .Y(n5078) );
NOR2X4TS U2965 ( .A(n6958), .B(n910), .Y(n6444) );
INVX4TS U2966 ( .A(n6362), .Y(n6422) );
NOR2X4TS U2967 ( .A(n7079), .B(n826), .Y(n6231) );
NOR2X8TS U2968 ( .A(n3517), .B(n3518), .Y(n7239) );
ADDFHX4TS U2969 ( .A(n3496), .B(n3495), .CI(n3494), .CO(n3532), .S(n3529) );
XNOR2X2TS U2970 ( .A(n915), .B(n3383), .Y(n3420) );
OAI21X1TS U2971 ( .A0(n6026), .A1(n5665), .B0(n5691), .Y(n5692) );
OAI21X2TS U2972 ( .A0(Op_MX[10]), .A1(Op_MX[37]), .B0(Op_MX[9]), .Y(n1359)
);
OAI21X1TS U2973 ( .A0(n891), .A1(n7330), .B0(n5108), .Y(n5110) );
OAI21X1TS U2974 ( .A0(n891), .A1(n3912), .B0(n3911), .Y(n3916) );
ADDFHX2TS U2975 ( .A(n2986), .B(n2985), .CI(n2984), .CO(n3013), .S(n2981) );
OR2X4TS U2976 ( .A(n3534), .B(n3533), .Y(n7432) );
ADDFHX4TS U2977 ( .A(n3469), .B(n3468), .CI(n3467), .CO(n3534), .S(n3531) );
XNOR2X2TS U2978 ( .A(n857), .B(n1747), .Y(n1817) );
NOR2X6TS U2979 ( .A(n4856), .B(n4857), .Y(n4917) );
NOR2X4TS U2980 ( .A(n4976), .B(n4984), .Y(n1229) );
CMPR42X2TS U2981 ( .A(mult_x_23_n730), .B(mult_x_23_n1274), .C(
mult_x_23_n1326), .D(mult_x_23_n1378), .ICI(mult_x_23_n731), .S(
mult_x_23_n721), .ICO(mult_x_23_n719), .CO(mult_x_23_n720) );
NOR2X4TS U2982 ( .A(Op_MY[36]), .B(n5802), .Y(n4976) );
OAI22X4TS U2983 ( .A0(n1801), .A1(n2976), .B0(n3350), .B1(n3005), .Y(n1816)
);
AND2X4TS U2984 ( .A(n1364), .B(n1363), .Y(n749) );
NOR2X4TS U2985 ( .A(n1063), .B(n1062), .Y(n1118) );
NOR2X4TS U2986 ( .A(n6874), .B(n8414), .Y(n1144) );
ADDFHX4TS U2987 ( .A(n2432), .B(n2431), .CI(n2430), .CO(n2421), .S(n2444) );
ADDFHX4TS U2988 ( .A(n2402), .B(n2401), .CI(n2400), .CO(n2431), .S(n2415) );
OAI21X2TS U2989 ( .A0(n6778), .A1(n6984), .B0(n6552), .Y(n6553) );
INVX12TS U2990 ( .A(n6292), .Y(n6778) );
CMPR42X2TS U2991 ( .A(mult_x_23_n1383), .B(mult_x_23_n1305), .C(
mult_x_23_n1357), .D(mult_x_23_n1409), .ICI(mult_x_23_n781), .S(
mult_x_23_n772), .ICO(mult_x_23_n770), .CO(mult_x_23_n771) );
NAND2X4TS U2992 ( .A(mult_x_24_n1015), .B(mult_x_24_n1022), .Y(n6149) );
OAI21X2TS U2993 ( .A0(n979), .A1(n5985), .B0(n5656), .Y(n5657) );
ADDFHX2TS U2994 ( .A(n1890), .B(n1889), .CI(n1888), .CO(n2155), .S(n1914) );
OAI22X4TS U2995 ( .A0(n3179), .A1(n3220), .B0(n1427), .B1(n2303), .Y(n1476)
);
XNOR2X1TS U2996 ( .A(n2223), .B(n2221), .Y(n2224) );
OAI22X2TS U2997 ( .A0(n2579), .A1(n930), .B0(n2616), .B1(n3360), .Y(n2619)
);
XOR2X4TS U2998 ( .A(Op_MX[4]), .B(Op_MX[31]), .Y(n1321) );
NOR2X4TS U2999 ( .A(n4264), .B(n4266), .Y(n4033) );
NOR2X4TS U3000 ( .A(n4031), .B(n4030), .Y(n4266) );
NOR2X4TS U3001 ( .A(n5062), .B(n5066), .Y(n5069) );
AOI21X4TS U3002 ( .A0(n4639), .A1(n4638), .B0(n4637), .Y(n4641) );
OAI21X4TS U3003 ( .A0(n4549), .A1(n4548), .B0(n4547), .Y(n4639) );
ADDFHX2TS U3004 ( .A(n2603), .B(n2602), .CI(n2601), .CO(n2640), .S(n2609) );
OAI21X4TS U3005 ( .A0(Op_MX[14]), .A1(Op_MX[41]), .B0(Op_MX[13]), .Y(n1715)
);
NAND2X4TS U3006 ( .A(n6433), .B(n6424), .Y(n1208) );
OAI21X1TS U3007 ( .A0(n729), .A1(n6681), .B0(n6676), .Y(n6677) );
OAI22X1TS U3008 ( .A0(n2367), .A1(n2560), .B0(n2302), .B1(n2510), .Y(n2358)
);
OAI22X1TS U3009 ( .A0(n2511), .A1(n2560), .B0(n2561), .B1(n2510), .Y(n2587)
);
OAI22X2TS U3010 ( .A0(n1511), .A1(n2559), .B0(n2560), .B1(n1508), .Y(n1512)
);
AO21X1TS U3011 ( .A0(n2628), .A1(n2627), .B0(n736), .Y(n2712) );
OAI21X1TS U3012 ( .A0(n7316), .A1(n4692), .B0(n7322), .Y(n4693) );
XNOR2X4TS U3013 ( .A(n909), .B(n3409), .Y(n2998) );
NAND2X2TS U3014 ( .A(Op_MX[4]), .B(Op_MX[31]), .Y(n1315) );
AOI21X4TS U3015 ( .A0(n7998), .A1(n4427), .B0(n4426), .Y(n4428) );
ADDFHX4TS U3016 ( .A(n4041), .B(Sgf_operation_ODD1_Q_middle[9]), .CI(n4040),
.CO(n4058), .S(n4057) );
CLKINVX12TS U3017 ( .A(n2281), .Y(n818) );
XNOR2X2TS U3018 ( .A(n3278), .B(n2468), .Y(n2311) );
OAI21X4TS U3019 ( .A0(n816), .A1(n3811), .B0(n3810), .Y(n3835) );
AOI222X2TS U3020 ( .A0(n7060), .A1(n7022), .B0(n7058), .B1(n6243), .C0(n7057), .C1(n7018), .Y(n4747) );
AOI21X4TS U3021 ( .A0(n7830), .A1(n4624), .B0(n4623), .Y(n7776) );
OAI21X2TS U3022 ( .A0(n7835), .A1(n7846), .B0(n7836), .Y(n4623) );
NOR2X2TS U3023 ( .A(n4586), .B(n4478), .Y(n4480) );
XNOR2X2TS U3024 ( .A(n4513), .B(n4512), .Y(n4622) );
NOR2BX4TS U3025 ( .AN(n1006), .B(n766), .Y(n3669) );
CMPR42X2TS U3026 ( .A(mult_x_24_n939), .B(mult_x_24_n1480), .C(
mult_x_24_n1561), .D(mult_x_24_n1534), .ICI(mult_x_24_n1615), .S(
mult_x_24_n937), .ICO(mult_x_24_n935), .CO(mult_x_24_n936) );
XOR2X2TS U3027 ( .A(n4809), .B(n7076), .Y(n5209) );
CMPR42X2TS U3028 ( .A(mult_x_23_n1439), .B(mult_x_23_n828), .C(
mult_x_23_n1361), .D(mult_x_23_n1465), .ICI(mult_x_23_n829), .S(
mult_x_23_n816), .ICO(mult_x_23_n814), .CO(mult_x_23_n815) );
NOR2X8TS U3029 ( .A(n3615), .B(n3614), .Y(n6065) );
XNOR2X2TS U3030 ( .A(n3349), .B(n2583), .Y(n2460) );
ADDFHX2TS U3031 ( .A(n2821), .B(n2820), .CI(n2819), .CO(n2903), .S(n2854) );
ADDFHX2TS U3032 ( .A(n2832), .B(n2831), .CI(n2830), .CO(n2861), .S(n2819) );
XOR2X2TS U3033 ( .A(n2825), .B(n2650), .Y(n2314) );
XNOR2X2TS U3034 ( .A(n856), .B(n2650), .Y(n2517) );
XNOR2X2TS U3035 ( .A(n860), .B(n2650), .Y(n2479) );
AO21X4TS U3036 ( .A0(n750), .A1(n751), .B0(n772), .Y(n2197) );
XOR2X4TS U3037 ( .A(n2261), .B(Op_MY[25]), .Y(n752) );
ADDFHX2TS U3038 ( .A(n2626), .B(n2625), .CI(n2624), .CO(n2748), .S(n2660) );
NOR2X6TS U3039 ( .A(n2913), .B(n2914), .Y(n2915) );
XNOR2X4TS U3040 ( .A(n911), .B(n2784), .Y(n2521) );
CMPR42X2TS U3041 ( .A(mult_x_24_n1431), .B(mult_x_24_n1404), .C(
mult_x_24_n713), .D(mult_x_24_n718), .ICI(mult_x_24_n715), .S(
mult_x_24_n711), .ICO(mult_x_24_n709), .CO(mult_x_24_n710) );
NOR2X4TS U3042 ( .A(n6310), .B(n6314), .Y(n1216) );
ADDFHX4TS U3043 ( .A(n2438), .B(n2437), .CI(n2436), .CO(n2441), .S(n2442) );
ADDFHX4TS U3044 ( .A(n2414), .B(n2413), .CI(n2412), .CO(n2423), .S(n2437) );
ADDFHX4TS U3045 ( .A(n2387), .B(n2386), .CI(n2385), .CO(n2414), .S(n2410) );
ADDFX2TS U3046 ( .A(n2390), .B(n2389), .CI(n2388), .CO(n2413), .S(n2416) );
XNOR2X2TS U3047 ( .A(n906), .B(n2784), .Y(n2313) );
BUFX6TS U3048 ( .A(n6105), .Y(n6106) );
NOR2X6TS U3049 ( .A(mult_x_24_n997), .B(mult_x_24_n1006), .Y(n6141) );
XOR2X2TS U3050 ( .A(n4368), .B(n4367), .Y(n4385) );
NOR2X2TS U3051 ( .A(n8264), .B(n8266), .Y(n8322) );
ADDFHX2TS U3052 ( .A(n1899), .B(n1898), .CI(n1897), .CO(n2168), .S(n1869) );
NOR2X4TS U3053 ( .A(n4700), .B(n5601), .Y(n4995) );
NOR2X4TS U3054 ( .A(n6016), .B(n828), .Y(n4700) );
NAND2X4TS U3055 ( .A(n4995), .B(n1231), .Y(n1233) );
OAI21X1TS U3056 ( .A0(n6043), .A1(n5665), .B0(n5688), .Y(n5689) );
XNOR2X2TS U3057 ( .A(n2878), .B(Op_MX[26]), .Y(n2829) );
NAND2BX1TS U3058 ( .AN(n7232), .B(n2264), .Y(n1801) );
INVX12TS U3059 ( .A(n1768), .Y(n2281) );
ADDFHX2TS U3060 ( .A(n2907), .B(n2906), .CI(n2905), .CO(n3211), .S(n2908) );
ADDFHX2TS U3061 ( .A(n2782), .B(n2781), .CI(n2780), .CO(n2846), .S(n2791) );
OAI21X1TS U3062 ( .A0(n6053), .A1(n5665), .B0(n997), .Y(n3636) );
OAI21X1TS U3063 ( .A0(n6053), .A1(n5569), .B0(n3784), .Y(n3785) );
OAI21X1TS U3064 ( .A0(n6053), .A1(n4965), .B0(n4970), .Y(n4971) );
AOI21X4TS U3065 ( .A0(n6173), .A1(n6171), .B0(n1166), .Y(n1167) );
ADDFHX2TS U3066 ( .A(n6223), .B(mult_x_24_n724), .CI(n6222), .CO(
mult_x_24_n718), .S(mult_x_24_n719) );
NAND2X2TS U3067 ( .A(mult_x_24_n716), .B(mult_x_24_n711), .Y(n5028) );
NAND2X4TS U3068 ( .A(mult_x_24_n944), .B(mult_x_24_n954), .Y(n6118) );
XNOR2X2TS U3069 ( .A(n2198), .B(n2939), .Y(n1717) );
INVX4TS U3070 ( .A(n2184), .Y(n966) );
XNOR2X4TS U3071 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n1418) );
ADDFHX2TS U3072 ( .A(n1852), .B(n1851), .CI(n1850), .CO(n1926), .S(n1924) );
OAI22X2TS U3073 ( .A0(n1707), .A1(n2477), .B0(n1811), .B1(n1974), .Y(n1852)
);
OAI22X2TS U3074 ( .A0(n1813), .A1(n1812), .B0(n1811), .B1(n1810), .Y(n1859)
);
XNOR2X2TS U3075 ( .A(n2873), .B(n2254), .Y(n1811) );
NOR2X6TS U3076 ( .A(n3528), .B(n3527), .Y(n7410) );
BUFX20TS U3077 ( .A(n2815), .Y(n914) );
ADDFHX2TS U3078 ( .A(n2329), .B(n2328), .CI(n2327), .CO(n2548), .S(n2384) );
ADDFHX2TS U3079 ( .A(n2381), .B(n2380), .CI(n2379), .CO(n2383), .S(n2418) );
ADDFHX2TS U3080 ( .A(n2341), .B(n2340), .CI(n2339), .CO(n2343), .S(n2379) );
XOR2X2TS U3081 ( .A(Op_MY[1]), .B(n6934), .Y(n1048) );
NOR2X4TS U3082 ( .A(n4306), .B(n4075), .Y(n4077) );
OAI21X1TS U3083 ( .A0(n5887), .A1(n6083), .B0(n5767), .Y(n5768) );
XNOR2X2TS U3084 ( .A(n2261), .B(Op_MY[25]), .Y(n754) );
OAI21X1TS U3085 ( .A0(n7379), .A1(n7368), .B0(n7124), .Y(n7372) );
OAI21X2TS U3086 ( .A0(n8266), .A1(n8273), .B0(n8267), .Y(n8323) );
XNOR2X4TS U3087 ( .A(Op_MX[5]), .B(Op_MX[32]), .Y(n1397) );
BUFX12TS U3088 ( .A(Op_MX[5]), .Y(n6874) );
OAI21X2TS U3089 ( .A0(n7430), .A1(n7327), .B0(n7326), .Y(n7329) );
AOI21X2TS U3090 ( .A0(n7325), .A1(n771), .B0(n7324), .Y(n7326) );
OAI22X2TS U3091 ( .A0(n2634), .A1(n3201), .B0(n2723), .B1(n2817), .Y(n2701)
);
NOR2X8TS U3092 ( .A(n5220), .B(n1191), .Y(n4862) );
NAND2X4TS U3093 ( .A(n5229), .B(n4846), .Y(n1191) );
XNOR2X1TS U3094 ( .A(n908), .B(n2939), .Y(n2044) );
OAI22X2TS U3095 ( .A0(n1621), .A1(n3427), .B0(n3428), .B1(n3426), .Y(n1653)
);
XNOR2X4TS U3096 ( .A(n8010), .B(n8009), .Y(n8011) );
OAI21X2TS U3097 ( .A0(n8021), .A1(n8017), .B0(n8018), .Y(n8010) );
NOR2X2TS U3098 ( .A(n8281), .B(n8283), .Y(n4387) );
NAND2X4TS U3099 ( .A(Op_MY[44]), .B(Op_MY[17]), .Y(n1778) );
OAI22X2TS U3100 ( .A0(n2262), .A1(n2477), .B0(n2478), .B1(n2476), .Y(n2458)
);
XNOR2X2TS U3101 ( .A(n853), .B(n2254), .Y(n2478) );
XNOR2X1TS U3102 ( .A(n920), .B(n2583), .Y(n2317) );
ADDFHX2TS U3103 ( .A(n2835), .B(n2834), .CI(n2833), .CO(n2860), .S(n2821) );
ADDFHX2TS U3104 ( .A(n2254), .B(n2576), .CI(n2575), .CO(n2620), .S(n2573) );
XOR2X4TS U3105 ( .A(n2203), .B(n2202), .Y(n2578) );
XOR2X2TS U3106 ( .A(n3334), .B(n3367), .Y(n2590) );
INVX4TS U3107 ( .A(n3367), .Y(n3190) );
AOI21X4TS U3108 ( .A0(n5358), .A1(n3745), .B0(n3744), .Y(n5349) );
NAND2X2TS U3109 ( .A(Op_MY[36]), .B(n7507), .Y(n4980) );
ADDFHX2TS U3110 ( .A(n2752), .B(n2751), .CI(n2750), .CO(n2856), .S(n2800) );
AOI21X4TS U3111 ( .A0(n6147), .A1(n6150), .B0(n1171), .Y(n1172) );
XOR2X2TS U3112 ( .A(n1403), .B(n1402), .Y(n1404) );
CLKINVX3TS U3113 ( .A(n1345), .Y(n1365) );
AOI21X2TS U3114 ( .A0(n8115), .A1(n4409), .B0(n4408), .Y(n4410) );
OAI21X2TS U3115 ( .A0(n8117), .A1(n8129), .B0(n8118), .Y(n4408) );
NAND2X6TS U3116 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1385) );
OAI21X4TS U3117 ( .A0(n5452), .A1(n1258), .B0(n1257), .Y(n3859) );
XOR2X4TS U3118 ( .A(n5829), .B(n5828), .Y(mult_x_23_n1350) );
OAI22X4TS U3119 ( .A0(n1482), .A1(n2808), .B0(n1481), .B1(n2100), .Y(n1545)
);
NAND2X4TS U3120 ( .A(n1614), .B(n1613), .Y(n1646) );
XNOR2X2TS U3121 ( .A(n857), .B(n3343), .Y(n1719) );
INVX4TS U3122 ( .A(n1332), .Y(n1388) );
NOR2X4TS U3123 ( .A(n3548), .B(n3549), .Y(n4692) );
ADDFHX4TS U3124 ( .A(n3066), .B(n3065), .CI(n3064), .CO(n3551), .S(n3549) );
ADDFHX2TS U3125 ( .A(n3200), .B(n3199), .CI(n3198), .CO(n3244), .S(n3196) );
ADDFHX4TS U3126 ( .A(n2596), .B(n2595), .CI(n2594), .CO(n2665), .S(n2592) );
INVX16TS U3127 ( .A(n2937), .Y(n3358) );
OAI22X2TS U3128 ( .A0(n1807), .A1(n2459), .B0(n1814), .B1(n2315), .Y(n1861)
);
NAND2X2TS U3129 ( .A(n4607), .B(Sgf_operation_ODD1_Q_left[14]), .Y(n7961) );
OAI21X4TS U3130 ( .A0(n4577), .A1(n4576), .B0(n4575), .Y(n4599) );
INVX4TS U3131 ( .A(n4567), .Y(n4577) );
XOR2X4TS U3132 ( .A(n4697), .B(n1003), .Y(Sgf_operation_ODD1_middle_N48) );
OAI21X2TS U3133 ( .A0(n6769), .A1(n6984), .B0(n6547), .Y(n6548) );
ADDFHX2TS U3134 ( .A(n2118), .B(n2117), .CI(n2116), .CO(n2417), .S(n2139) );
NAND2X8TS U3135 ( .A(n4766), .B(n3763), .Y(n3771) );
NAND2X2TS U3136 ( .A(n1697), .B(n1603), .Y(n1606) );
ADDFHX2TS U3137 ( .A(n1849), .B(n1848), .CI(n1847), .CO(n1927), .S(n1862) );
OAI22X1TS U3138 ( .A0(n1838), .A1(n2808), .B0(n1689), .B1(n2100), .Y(n1848)
);
ADDFHX4TS U3139 ( .A(n2729), .B(n2728), .CI(n2727), .CO(n2778), .S(n2725) );
NOR2X4TS U3140 ( .A(n4357), .B(n4359), .Y(n4335) );
BUFX8TS U3141 ( .A(n2086), .Y(n3419) );
NAND2X6TS U3142 ( .A(n3188), .B(n1987), .Y(n2086) );
ADDFHX2TS U3143 ( .A(n2344), .B(n2343), .CI(n2342), .CO(n2554), .S(n2382) );
NOR2X4TS U3144 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n2075) );
NOR2X4TS U3145 ( .A(n7300), .B(n3570), .Y(n3572) );
NAND2X2TS U3146 ( .A(n7311), .B(n4832), .Y(n3570) );
ADDFHX2TS U3147 ( .A(n2632), .B(n2631), .CI(n2630), .CO(n2707), .S(n2618) );
NOR2X6TS U3148 ( .A(Op_MY[46]), .B(Op_MY[19]), .Y(n1954) );
ADDFHX4TS U3149 ( .A(n2275), .B(n2274), .CI(n2273), .CO(n2321), .S(n2346) );
ADDFHX2TS U3150 ( .A(n2269), .B(n2268), .CI(n2267), .CO(n2466), .S(n2344) );
OAI21X4TS U3151 ( .A0(n1327), .A1(n1406), .B0(n1326), .Y(n1328) );
XOR2X2TS U3152 ( .A(n6555), .B(n6827), .Y(mult_x_24_n1524) );
ADDFHX2TS U3153 ( .A(n2352), .B(n2351), .CI(n2350), .CO(n2391), .S(n2388) );
XNOR2X2TS U3154 ( .A(n2198), .B(n2944), .Y(n1802) );
ADDFHX2TS U3155 ( .A(n1696), .B(n1695), .CI(n1694), .CO(n1925), .S(n1691) );
XNOR2X2TS U3156 ( .A(n862), .B(n1979), .Y(n1645) );
OR2X4TS U3157 ( .A(n888), .B(n2942), .Y(n757) );
OR2X4TS U3158 ( .A(n1716), .B(n2762), .Y(n758) );
NAND2X4TS U3159 ( .A(n757), .B(n758), .Y(n1750) );
NAND2X4TS U3160 ( .A(n1754), .B(n1760), .Y(n1764) );
ADDFHX2TS U3161 ( .A(n1589), .B(n1588), .CI(n1587), .CO(n1590), .S(n1568) );
ADDFHX2TS U3162 ( .A(n2767), .B(n2766), .CI(n2765), .CO(n2833), .S(n2760) );
ADDFHX2TS U3163 ( .A(n1007), .B(n2712), .CI(n2711), .CO(n2766), .S(n2708) );
ADDFHX2TS U3164 ( .A(n2702), .B(n2701), .CI(n2700), .CO(n2794), .S(n2705) );
OAI22X2TS U3165 ( .A0(n2304), .A1(n2730), .B0(n2461), .B1(n2303), .Y(n2457)
);
BUFX16TS U3166 ( .A(Op_MX[18]), .Y(n6829) );
INVX8TS U3167 ( .A(n4862), .Y(n4885) );
XNOR2X2TS U3168 ( .A(n3349), .B(n2468), .Y(n2302) );
NOR2X4TS U3169 ( .A(n755), .B(n5892), .Y(n3704) );
ADDFHX2TS U3170 ( .A(n2544), .B(n2543), .CI(n2542), .CO(n2570), .S(n2529) );
XNOR2X2TS U3171 ( .A(n921), .B(n3227), .Y(n2513) );
OAI22X2TS U3172 ( .A0(n2558), .A1(n3407), .B0(n2649), .B1(n3405), .Y(n2647)
);
ADDFHX2TS U3173 ( .A(n2115), .B(n2114), .CI(n2113), .CO(n2409), .S(n2140) );
NOR2X8TS U3174 ( .A(n1405), .B(n1327), .Y(n1329) );
ADDFHX2TS U3175 ( .A(n2355), .B(n2354), .CI(n2353), .CO(n2342), .S(n2395) );
ADDFHX4TS U3176 ( .A(n2180), .B(n2179), .CI(n2178), .CO(n2182), .S(n1945) );
NOR2X4TS U3177 ( .A(n7368), .B(n2915), .Y(n7373) );
ADDFHX2TS U3178 ( .A(n1561), .B(n1560), .CI(n1559), .CO(n1567), .S(n1566) );
XNOR2X2TS U3179 ( .A(n1321), .B(n1316), .Y(n1320) );
ADDFHX2TS U3180 ( .A(n2770), .B(n2769), .CI(n2768), .CO(n2820), .S(n2750) );
NAND2X4TS U3181 ( .A(Op_MY[30]), .B(Op_MY[3]), .Y(n1348) );
XNOR2X2TS U3182 ( .A(Op_MY[3]), .B(Op_MY[4]), .Y(n1057) );
ADDFHX2TS U3183 ( .A(n2528), .B(n2527), .CI(n2526), .CO(n2607), .S(n2531) );
XOR2X2TS U3184 ( .A(n5710), .B(n8404), .Y(mult_x_23_n1434) );
AOI21X2TS U3185 ( .A0(n5225), .A1(n4890), .B0(n4889), .Y(n4891) );
BUFX12TS U3186 ( .A(Op_MX[21]), .Y(n6952) );
ADDFHX4TS U3187 ( .A(n2177), .B(n2176), .CI(n2175), .CO(n2183), .S(n2181) );
ADDFHX2TS U3188 ( .A(n2171), .B(n2170), .CI(n2169), .CO(n2160), .S(n2176) );
ADDFHX2TS U3189 ( .A(n2123), .B(n2122), .CI(n2121), .CO(n2152), .S(n2156) );
NOR2X8TS U3190 ( .A(n6094), .B(n6098), .Y(n7094) );
NOR2X4TS U3191 ( .A(n7079), .B(n6958), .Y(n1205) );
ADDFHX2TS U3192 ( .A(n2623), .B(n2622), .CI(n2621), .CO(n2744), .S(n2626) );
ADDFHX2TS U3193 ( .A(n2574), .B(n2573), .CI(n2572), .CO(n2623), .S(n2568) );
ADDFHX2TS U3194 ( .A(n2539), .B(n2538), .CI(n2537), .CO(n2572), .S(n2523) );
NOR2X4TS U3195 ( .A(Op_MY[47]), .B(Op_MY[20]), .Y(n1965) );
NOR2X6TS U3196 ( .A(n1965), .B(n1967), .Y(n2237) );
AOI21X2TS U3197 ( .A0(n2279), .A1(n2284), .B0(n2250), .Y(n2248) );
XNOR2X2TS U3198 ( .A(n899), .B(n2583), .Y(n2584) );
AOI21X4TS U3199 ( .A0(n4994), .A1(n1231), .B0(n1230), .Y(n1232) );
NAND2X4TS U3200 ( .A(n5481), .B(n5476), .Y(n1230) );
NAND2X4TS U3201 ( .A(n5602), .B(n5597), .Y(n4994) );
CMPR42X2TS U3202 ( .A(mult_x_23_n1244), .B(mult_x_23_n657), .C(
mult_x_23_n653), .D(mult_x_23_n1291), .ICI(mult_x_23_n654), .S(
mult_x_23_n651), .ICO(mult_x_23_n649), .CO(mult_x_23_n650) );
INVX12TS U3203 ( .A(n1013), .Y(n6934) );
AO21X4TS U3204 ( .A0(n3222), .A1(n3221), .B0(n3220), .Y(n3300) );
OAI21X2TS U3205 ( .A0(n891), .A1(n7429), .B0(n7428), .Y(n7434) );
NAND2X4TS U3206 ( .A(n1402), .B(n1394), .Y(n1343) );
NAND2X4TS U3207 ( .A(Op_MY[45]), .B(Op_MY[18]), .Y(n1953) );
OAI21X2TS U3208 ( .A0(n817), .A1(n1969), .B0(n1968), .Y(n1972) );
ADDFHX2TS U3209 ( .A(n2378), .B(n2377), .CI(n2376), .CO(n2381), .S(n2403) );
CMPR42X2TS U3210 ( .A(mult_x_23_n684), .B(mult_x_23_n1295), .C(
mult_x_23_n685), .D(mult_x_23_n678), .ICI(mult_x_23_n681), .S(
mult_x_23_n675), .ICO(mult_x_23_n673), .CO(mult_x_23_n674) );
OAI21X1TS U3211 ( .A0(n6026), .A1(n4965), .B0(n5474), .Y(n5475) );
NAND2X2TS U3212 ( .A(n1147), .B(n1143), .Y(n1119) );
INVX12TS U3213 ( .A(n1214), .Y(n6461) );
OAI21X1TS U3214 ( .A0(n7075), .A1(n6681), .B0(n6680), .Y(n6682) );
OAI21X1TS U3215 ( .A0(n7086), .A1(n6899), .B0(n6579), .Y(n6580) );
ADDFHX2TS U3216 ( .A(n2638), .B(n2637), .CI(n2636), .CO(n2704), .S(n2624) );
OAI21X2TS U3217 ( .A0(n1405), .A1(n1409), .B0(n1406), .Y(n1312) );
BUFX12TS U3218 ( .A(Op_MY[33]), .Y(n5892) );
NAND2X4TS U3219 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n1406) );
NOR2X6TS U3220 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n1405) );
NOR2X6TS U3221 ( .A(n2447), .B(n2448), .Y(n7269) );
NOR2X2TS U3222 ( .A(n1878), .B(n1877), .Y(n1879) );
OAI21X2TS U3223 ( .A0(Op_MX[18]), .A1(Op_MX[45]), .B0(Op_MX[17]), .Y(n1875)
);
XOR2X4TS U3224 ( .A(Op_MX[18]), .B(Op_MX[45]), .Y(n1877) );
ADDFHX2TS U3225 ( .A(n2509), .B(n2508), .CI(n2507), .CO(n2530), .S(n2549) );
ADDFHX4TS U3226 ( .A(n1683), .B(n1682), .CI(n1681), .CO(n1729), .S(n1731) );
ADDFHX4TS U3227 ( .A(n1657), .B(n1656), .CI(n1655), .CO(n1727), .S(n1681) );
ADDFHX2TS U3228 ( .A(n2301), .B(n2300), .CI(n2299), .CO(n2494), .S(n2360) );
OAI21X1TS U3229 ( .A0(n5968), .A1(n4671), .B0(n5546), .Y(n5547) );
OAI21X1TS U3230 ( .A0(n5968), .A1(n5491), .B0(n5514), .Y(n5515) );
CMPR42X2TS U3231 ( .A(mult_x_24_n1531), .B(mult_x_24_n1504), .C(
mult_x_24_n912), .D(mult_x_24_n1558), .ICI(mult_x_24_n906), .S(
mult_x_24_n899), .ICO(mult_x_24_n897), .CO(mult_x_24_n898) );
ADDFHX2TS U3232 ( .A(n2620), .B(n2619), .CI(n2618), .CO(n2697), .S(n2622) );
ADDFHX2TS U3233 ( .A(n2889), .B(n2888), .CI(n2887), .CO(n3173), .S(n2862) );
XNOR2X2TS U3234 ( .A(n753), .B(n2822), .Y(n2823) );
NOR2X4TS U3235 ( .A(n1362), .B(n1346), .Y(n1309) );
ADDFHX2TS U3236 ( .A(n2375), .B(n2374), .CI(n2373), .CO(n2356), .S(n2404) );
OAI21X1TS U3237 ( .A0(n5781), .A1(n5470), .B0(n5450), .Y(n5451) );
NOR2X8TS U3238 ( .A(Op_MY[41]), .B(Op_MY[14]), .Y(n1753) );
XNOR2X2TS U3239 ( .A(n3303), .B(n2881), .Y(n2335) );
NOR2X4TS U3240 ( .A(n8017), .B(n8006), .Y(n4423) );
OR2X8TS U3241 ( .A(n759), .B(n760), .Y(n7258) );
XNOR2X4TS U3242 ( .A(n907), .B(n2871), .Y(n2533) );
CMPR42X2TS U3243 ( .A(mult_x_23_n1426), .B(mult_x_23_n938), .C(
mult_x_23_n1452), .D(mult_x_23_n1478), .ICI(mult_x_23_n941), .S(
mult_x_23_n936), .ICO(mult_x_23_n934), .CO(mult_x_23_n935) );
NOR2X6TS U3244 ( .A(n3788), .B(n3787), .Y(n3796) );
INVX6TS U3245 ( .A(n1787), .Y(n2709) );
ADDFHX4TS U3246 ( .A(n2593), .B(n2592), .CI(n2591), .CO(n2667), .S(n2684) );
XNOR2X4TS U3247 ( .A(n4473), .B(n4472), .Y(n4619) );
OAI21X4TS U3248 ( .A0(n924), .A1(n5199), .B0(n5198), .Y(n5202) );
AOI21X2TS U3249 ( .A0(n5197), .A1(n5196), .B0(n5195), .Y(n5198) );
ADDFHX2TS U3250 ( .A(n1496), .B(n1495), .CI(n1494), .CO(n1498), .S(n1572) );
NOR2X8TS U3251 ( .A(n2919), .B(n2918), .Y(n7380) );
NAND2X4TS U3252 ( .A(n3767), .B(n4789), .Y(n3769) );
NOR2X4TS U3253 ( .A(n4782), .B(n4793), .Y(n3767) );
OAI21X1TS U3254 ( .A0(n6026), .A1(n4671), .B0(n5542), .Y(n5543) );
NAND2X4TS U3255 ( .A(mult_x_24_n1007), .B(mult_x_24_n1014), .Y(n6948) );
OAI21X1TS U3256 ( .A0(n1001), .A1(n5684), .B0(n5916), .Y(n5917) );
AND2X4TS U3257 ( .A(n1700), .B(n1697), .Y(n1019) );
ADDFHX2TS U3258 ( .A(n2338), .B(n2337), .CI(n2336), .CO(n2328), .S(n2380) );
NOR2X4TS U3259 ( .A(n6785), .B(Op_MX[15]), .Y(n6432) );
OAI21X1TS U3260 ( .A0(n729), .A1(n6841), .B0(n6600), .Y(n6601) );
CMPR22X2TS U3261 ( .A(n2506), .B(n2505), .CO(n2537), .S(n2473) );
XNOR2X4TS U3262 ( .A(n913), .B(n2939), .Y(n2520) );
NOR2X4TS U3263 ( .A(n1452), .B(n1455), .Y(n1458) );
XOR2X4TS U3264 ( .A(n4944), .B(n1011), .Y(Sgf_operation_ODD1_left_N47) );
NOR2X4TS U3265 ( .A(mult_x_23_n769), .B(mult_x_23_n779), .Y(n4908) );
OAI21X1TS U3266 ( .A0(n5968), .A1(n5569), .B0(n5592), .Y(n5593) );
NAND2X4TS U3267 ( .A(mult_x_23_n824), .B(mult_x_23_n834), .Y(n5308) );
OAI21X1TS U3268 ( .A0(n6048), .A1(n5665), .B0(n5693), .Y(n5695) );
NOR2X2TS U3269 ( .A(n8171), .B(n8162), .Y(n4403) );
AOI21X4TS U3270 ( .A0(n8160), .A1(n4403), .B0(n4402), .Y(n8112) );
XNOR2X2TS U3271 ( .A(n4180), .B(n4179), .Y(n4400) );
NOR2X6TS U3272 ( .A(n1950), .B(n1954), .Y(n1956) );
NOR2X4TS U3273 ( .A(n833), .B(n6484), .Y(n6287) );
NAND2X4TS U3274 ( .A(n833), .B(n6484), .Y(n6288) );
NOR2X6TS U3275 ( .A(n1943), .B(n1942), .Y(n7396) );
ADDFHX4TS U3276 ( .A(n1919), .B(n1918), .CI(n1917), .CO(n1944), .S(n1943) );
ADDFHX2TS U3277 ( .A(n2126), .B(n2125), .CI(n2124), .CO(n2127), .S(n2151) );
XNOR2X4TS U3278 ( .A(n1793), .B(n1798), .Y(n1794) );
CMPR42X2TS U3279 ( .A(mult_x_23_n1292), .B(mult_x_23_n664), .C(
mult_x_23_n658), .D(mult_x_23_n1266), .ICI(mult_x_23_n661), .S(
mult_x_23_n656), .ICO(mult_x_23_n654), .CO(mult_x_23_n655) );
OAI21X1TS U3280 ( .A0(n5781), .A1(n5886), .B0(n5500), .Y(n5501) );
ADDFHX4TS U3281 ( .A(n1728), .B(n1727), .CI(n1726), .CO(n1736), .S(n1730) );
ADDFHX2TS U3282 ( .A(n1693), .B(n1692), .CI(n1691), .CO(n1936), .S(n1726) );
XOR2X4TS U3283 ( .A(n4920), .B(n978), .Y(Sgf_operation_ODD1_left_N37) );
AOI21X2TS U3284 ( .A0(n8323), .A1(n4393), .B0(n4392), .Y(n4394) );
NOR2X2TS U3285 ( .A(n8327), .B(n8334), .Y(n4393) );
AOI21X2TS U3286 ( .A0(n3767), .A1(n4788), .B0(n3766), .Y(n3768) );
OAI21X4TS U3287 ( .A0(n4771), .A1(n4899), .B0(n4772), .Y(n4788) );
OAI21X1TS U3288 ( .A0(n5938), .A1(n5827), .B0(n5580), .Y(n5581) );
NOR2X8TS U3289 ( .A(n7248), .B(n7363), .Y(n2931) );
OAI22X2TS U3290 ( .A0(n2721), .A1(n928), .B0(n2773), .B1(n2772), .Y(n2770)
);
XNOR2X2TS U3291 ( .A(n899), .B(n2720), .Y(n2721) );
OAI21X2TS U3292 ( .A0(n4934), .A1(n3891), .B0(n3890), .Y(n3892) );
AOI21X4TS U3293 ( .A0(n5273), .A1(n5266), .B0(n3885), .Y(n4934) );
CMPR42X2TS U3294 ( .A(mult_x_23_n648), .B(mult_x_23_n1289), .C(
mult_x_23_n1263), .D(mult_x_23_n1243), .ICI(mult_x_23_n645), .S(
mult_x_23_n642), .ICO(mult_x_23_n640), .CO(mult_x_23_n641) );
OAI21X1TS U3295 ( .A0(n5879), .A1(n5886), .B0(n5493), .Y(n5492) );
NAND2X4TS U3296 ( .A(mult_x_23_n790), .B(mult_x_23_n780), .Y(n4904) );
NOR2X6TS U3297 ( .A(n2927), .B(n2926), .Y(n7248) );
XNOR2X2TS U3298 ( .A(n3334), .B(n3346), .Y(n2841) );
OAI22X2TS U3299 ( .A0(n2968), .A1(n935), .B0(n2991), .B1(n3413), .Y(n2988)
);
NOR2X8TS U3300 ( .A(n7396), .B(n7400), .Y(n1947) );
ADDFHX2TS U3301 ( .A(n1913), .B(n1912), .CI(n1911), .CO(n2148), .S(n1915) );
NOR2X2TS U3302 ( .A(n7919), .B(n7916), .Y(n7887) );
NOR2X4TS U3303 ( .A(n4614), .B(Sgf_operation_ODD1_Q_left[19]), .Y(n7893) );
ADDFHX4TS U3304 ( .A(n2165), .B(n2164), .CI(n2163), .CO(n2187), .S(n2184) );
XOR2X2TS U3305 ( .A(n1376), .B(n948), .Y(n2222) );
INVX2TS U3306 ( .A(n7200), .Y(n1538) );
OAI21X2TS U3307 ( .A0(n891), .A1(n7349), .B0(n7348), .Y(n7351) );
OAI21X1TS U3308 ( .A0(n7424), .A1(n7345), .B0(n7418), .Y(n7346) );
ADDFHX4TS U3309 ( .A(n2677), .B(n2676), .CI(n2675), .CO(n2682), .S(n2687) );
ADDFHX2TS U3310 ( .A(n2547), .B(n2546), .CI(n2545), .CO(n2569), .S(n2552) );
XNOR2X4TS U3311 ( .A(n738), .B(n2822), .Y(n2461) );
OAI21X4TS U3312 ( .A0(n5164), .A1(n5163), .B0(n5162), .Y(n5174) );
XOR2X2TS U3313 ( .A(n5509), .B(n5868), .Y(mult_x_23_n1298) );
OAI21X1TS U3314 ( .A0(n6043), .A1(n5886), .B0(n5508), .Y(n5509) );
CLKINVX12TS U3315 ( .A(n7600), .Y(n7733) );
NOR2X4TS U3316 ( .A(n4451), .B(n4450), .Y(n4562) );
CMPR42X2TS U3317 ( .A(mult_x_24_n1592), .B(mult_x_24_n1565), .C(
mult_x_24_n991), .D(mult_x_24_n1646), .ICI(mult_x_24_n988), .S(
mult_x_24_n980), .ICO(mult_x_24_n978), .CO(mult_x_24_n979) );
NOR2X4TS U3318 ( .A(n6448), .B(n6444), .Y(n1207) );
NAND2X4TS U3319 ( .A(n7079), .B(n6958), .Y(n6232) );
ADDFHX4TS U3320 ( .A(n1922), .B(n1921), .CI(n1920), .CO(n1942), .S(n1941) );
XNOR2X4TS U3321 ( .A(Op_MX[15]), .B(Op_MX[42]), .Y(n1743) );
OAI21X4TS U3322 ( .A0(n7395), .A1(n7400), .B0(n7401), .Y(n1946) );
XOR2X4TS U3323 ( .A(Op_MX[14]), .B(Op_MX[41]), .Y(n1711) );
XOR2X2TS U3324 ( .A(n1070), .B(n6891), .Y(n1111) );
OAI21X2TS U3325 ( .A0(n6973), .A1(n1038), .B0(n995), .Y(n1070) );
OAI21X1TS U3326 ( .A0(n7086), .A1(n6907), .B0(n6906), .Y(n6908) );
NAND2X4TS U3327 ( .A(n7779), .B(n4630), .Y(n4632) );
AOI21X4TS U3328 ( .A0(n7778), .A1(n4630), .B0(n4629), .Y(n4631) );
NOR2X6TS U3329 ( .A(n7600), .B(n4645), .Y(n7683) );
ADDFHX2TS U3330 ( .A(n2865), .B(n2864), .CI(n2863), .CO(n3207), .S(n2899) );
XNOR2X2TS U3331 ( .A(n3338), .B(n3275), .Y(n2818) );
ADDFHX2TS U3332 ( .A(n2138), .B(n2137), .CI(n2136), .CO(n2158), .S(n2169) );
ADDFHX4TS U3333 ( .A(n2147), .B(n2146), .CI(n2145), .CO(n2189), .S(n2188) );
ADDFHX4TS U3334 ( .A(n3472), .B(n3471), .CI(n3470), .CO(n3544), .S(n3533) );
CMPR42X2TS U3335 ( .A(mult_x_24_n1639), .B(mult_x_24_n1585), .C(
mult_x_24_n1612), .D(mult_x_24_n909), .ICI(mult_x_24_n902), .S(
mult_x_24_n896), .ICO(mult_x_24_n894), .CO(mult_x_24_n895) );
NOR2X6TS U3336 ( .A(n2924), .B(n2925), .Y(n7282) );
OAI22X2TS U3337 ( .A0(n2470), .A1(n3179), .B0(n2600), .B1(n2016), .Y(n2586)
);
XNOR2X2TS U3338 ( .A(n7542), .B(n7541), .Y(n7543) );
OAI21X2TS U3339 ( .A0(n4568), .A1(n4564), .B0(n4569), .Y(n4574) );
CMPR42X2TS U3340 ( .A(mult_x_24_n1093), .B(mult_x_24_n740), .C(
mult_x_24_n1488), .D(mult_x_24_n1434), .ICI(mult_x_24_n1461), .S(
mult_x_24_n732), .ICO(mult_x_24_n730), .CO(mult_x_24_n731) );
CMPR42X2TS U3341 ( .A(mult_x_24_n1406), .B(mult_x_24_n730), .C(
mult_x_24_n731), .D(mult_x_24_n726), .ICI(mult_x_24_n727), .S(
mult_x_24_n723), .ICO(mult_x_24_n721), .CO(mult_x_24_n722) );
NOR2X4TS U3342 ( .A(mult_x_24_n711), .B(mult_x_24_n716), .Y(n1287) );
OAI21X4TS U3343 ( .A0(n7262), .A1(n7438), .B0(n7263), .Y(n943) );
ADDFHX4TS U3344 ( .A(n2423), .B(n2422), .CI(n2421), .CO(n2425), .S(n2439) );
NAND2X2TS U3345 ( .A(n7829), .B(n4624), .Y(n7775) );
XOR2X2TS U3346 ( .A(n3916), .B(n970), .Y(Sgf_operation_ODD1_middle_N39) );
NAND2BX1TS U3347 ( .AN(n2223), .B(n2518), .Y(n1881) );
XNOR2X2TS U3348 ( .A(n7434), .B(n7433), .Y(Sgf_operation_ODD1_middle_N44) );
INVX4TS U3349 ( .A(n7344), .Y(n7424) );
OAI21X4TS U3350 ( .A0(n1671), .A1(n1670), .B0(n1669), .Y(n1761) );
NAND2X4TS U3351 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1670) );
OAI21X4TS U3352 ( .A0(n7875), .A1(n7832), .B0(n7831), .Y(n7849) );
NOR2X2TS U3353 ( .A(n6023), .B(n6038), .Y(n1250) );
OAI21X1TS U3354 ( .A0(n5879), .A1(n5684), .B0(n5667), .Y(n5666) );
OAI21X1TS U3355 ( .A0(n6043), .A1(n936), .B0(n5730), .Y(n5731) );
NOR2X6TS U3356 ( .A(n5307), .B(n5305), .Y(n5299) );
CMPR42X2TS U3357 ( .A(mult_x_24_n748), .B(mult_x_24_n1490), .C(
mult_x_24_n1463), .D(mult_x_24_n1409), .ICI(mult_x_24_n1436), .S(
mult_x_24_n746), .ICO(mult_x_24_n744), .CO(mult_x_24_n745) );
CMPR42X2TS U3358 ( .A(mult_x_24_n755), .B(mult_x_24_n752), .C(mult_x_24_n753), .D(mult_x_24_n746), .ICI(mult_x_24_n749), .S(mult_x_24_n743), .ICO(
mult_x_24_n741), .CO(mult_x_24_n742) );
NOR2X8TS U3359 ( .A(n4877), .B(n1196), .Y(n1198) );
NAND2X4TS U3360 ( .A(n1028), .B(n1027), .Y(n1196) );
XNOR2X2TS U3361 ( .A(n7351), .B(n7350), .Y(Sgf_operation_ODD1_middle_N43) );
BUFX12TS U3362 ( .A(n2936), .Y(n7430) );
OAI21X2TS U3363 ( .A0(n7430), .A1(n7332), .B0(n7331), .Y(n7334) );
OA21X4TS U3364 ( .A0(n7430), .A1(n7320), .B0(n7319), .Y(n761) );
XOR2X4TS U3365 ( .A(n761), .B(n821), .Y(Sgf_operation_ODD1_middle_N47) );
OA21X4TS U3366 ( .A0(n5141), .A1(n5143), .B0(n5144), .Y(n1025) );
NOR2X4TS U3367 ( .A(n1286), .B(n1292), .Y(n1295) );
NOR2X4TS U3368 ( .A(mult_x_24_n706), .B(mult_x_24_n710), .Y(n1286) );
XNOR2X4TS U3369 ( .A(n4884), .B(n4883), .Y(Sgf_operation_ODD1_right_N40) );
OAI21X4TS U3370 ( .A0(n4893), .A1(n4881), .B0(n4880), .Y(n4884) );
OAI21X4TS U3371 ( .A0(n6855), .A1(n7085), .B0(n6754), .Y(n6755) );
ADDFHX4TS U3372 ( .A(n3511), .B(n3510), .CI(n3509), .CO(n3528), .S(n3525) );
NOR2X4TS U3373 ( .A(n1753), .B(n1758), .Y(n1760) );
XNOR2X4TS U3374 ( .A(n4896), .B(n4895), .Y(Sgf_operation_ODD1_right_N39) );
XOR2X2TS U3375 ( .A(n6742), .B(n6861), .Y(mult_x_24_n1469) );
OAI21X4TS U3376 ( .A0(n4893), .A1(n4892), .B0(n4891), .Y(n4896) );
OAI21X4TS U3377 ( .A0(n818), .A1(n2260), .B0(n2259), .Y(n2261) );
OAI21X1TS U3378 ( .A0(n5879), .A1(n5807), .B0(n5789), .Y(n5765) );
OAI21X4TS U3379 ( .A0(n4903), .A1(n5286), .B0(n4904), .Y(n5277) );
NOR2X8TS U3380 ( .A(mult_x_23_n780), .B(mult_x_23_n790), .Y(n4903) );
CMPR42X2TS U3381 ( .A(mult_x_23_n807), .B(mult_x_23_n797), .C(mult_x_23_n804), .D(mult_x_23_n794), .ICI(mult_x_23_n800), .S(mult_x_23_n791), .ICO(
mult_x_23_n789), .CO(mult_x_23_n790) );
NAND2X4TS U3382 ( .A(n7321), .B(n4696), .Y(n3555) );
NOR2X4TS U3383 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1452) );
OAI21X4TS U3384 ( .A0(n891), .A1(n3927), .B0(n3926), .Y(n3931) );
AOI21X4TS U3385 ( .A0(n7325), .A1(n3925), .B0(n3924), .Y(n3926) );
XNOR2X4TS U3386 ( .A(n5147), .B(n5146), .Y(Sgf_operation_ODD1_right_N52) );
OAI21X4TS U3387 ( .A0(n816), .A1(n5142), .B0(n5141), .Y(n5147) );
OAI21X1TS U3388 ( .A0(n729), .A1(n7062), .B0(n6739), .Y(n6740) );
NOR2X8TS U3389 ( .A(n4903), .B(n5285), .Y(n5276) );
NOR2X4TS U3390 ( .A(mult_x_23_n791), .B(mult_x_23_n801), .Y(n5285) );
OAI21X4TS U3391 ( .A0(n4856), .A1(n924), .B0(n4855), .Y(n4861) );
OAI21X2TS U3392 ( .A0(n6043), .A1(n5620), .B0(n5638), .Y(n5639) );
XOR2X1TS U3393 ( .A(Op_MX[36]), .B(Op_MX[37]), .Y(n1378) );
INVX2TS U3394 ( .A(n3859), .Y(n3860) );
AOI21X2TS U3395 ( .A0(n4481), .A1(n4480), .B0(n4479), .Y(n4482) );
CLKAND2X2TS U3396 ( .A(n6946), .B(n905), .Y(mult_x_24_n1108) );
OAI21X1TS U3397 ( .A0(n5437), .A1(n5924), .B0(n4687), .Y(n4688) );
NOR2X4TS U3398 ( .A(n1730), .B(n1729), .Y(n1733) );
AOI21X2TS U3399 ( .A0(n6269), .A1(n4731), .B0(n790), .Y(n4732) );
CLKAND2X2TS U3400 ( .A(Op_MY[26]), .B(n834), .Y(mult_x_24_n1086) );
AOI21X2TS U3401 ( .A0(n5366), .A1(n5365), .B0(n3741), .Y(n3742) );
NOR2X2TS U3402 ( .A(n5000), .B(n5480), .Y(n1231) );
NOR2X4TS U3403 ( .A(Op_MY[48]), .B(Op_MY[21]), .Y(n1967) );
NOR2X1TS U3404 ( .A(n1985), .B(n3626), .Y(n1986) );
OAI22X1TS U3405 ( .A0(n2737), .A1(n3407), .B0(n2785), .B1(n3405), .Y(n2781)
);
NAND2X4TS U3406 ( .A(n1325), .B(n1329), .Y(n1333) );
XOR2X1TS U3407 ( .A(Op_MX[38]), .B(Op_MX[39]), .Y(n1618) );
ADDFHX2TS U3408 ( .A(n2057), .B(n2056), .CI(n2055), .CO(n2048), .S(n2136) );
AOI21X1TS U3409 ( .A0(n6269), .A1(n6273), .B0(n6257), .Y(n6258) );
INVX2TS U3410 ( .A(n4967), .Y(n863) );
OAI21X1TS U3411 ( .A0(n6053), .A1(n5491), .B0(n4658), .Y(n4659) );
NAND2X1TS U3412 ( .A(n5840), .B(n824), .Y(n4658) );
NAND2X4TS U3413 ( .A(n3658), .B(n3679), .Y(n3607) );
OAI21X2TS U3414 ( .A0(n4279), .A1(n4277), .B0(n4280), .Y(n4272) );
AOI21X2TS U3415 ( .A0(n4439), .A1(n4438), .B0(n4437), .Y(n4440) );
NAND2X4TS U3416 ( .A(n2201), .B(n2200), .Y(n2202) );
ADDFHX2TS U3417 ( .A(n1687), .B(n1686), .CI(n1685), .CO(n1863), .S(n1723) );
NOR2X2TS U3418 ( .A(n6362), .B(n1211), .Y(n1213) );
AOI21X2TS U3419 ( .A0(n6269), .A1(n3824), .B0(n3823), .Y(n3825) );
OAI21X2TS U3420 ( .A0(n6778), .A1(n6442), .B0(n6387), .Y(n6388) );
CLKAND2X2TS U3421 ( .A(n6962), .B(n7001), .Y(n6513) );
CLKAND2X2TS U3422 ( .A(n6946), .B(n827), .Y(mult_x_24_n1098) );
CLKAND2X2TS U3423 ( .A(n7078), .B(n7079), .Y(n6937) );
OAI21X1TS U3424 ( .A0(n6918), .A1(n6792), .B0(n6741), .Y(n6742) );
OAI21X2TS U3425 ( .A0(n6967), .A1(n6973), .B0(n6757), .Y(n6759) );
CLKAND2X2TS U3426 ( .A(n1083), .B(n7001), .Y(n7002) );
CLKAND2X2TS U3427 ( .A(n7078), .B(n825), .Y(mult_x_24_n1109) );
CLKINVX6TS U3428 ( .A(n863), .Y(n864) );
CLKAND2X2TS U3429 ( .A(n6060), .B(n6038), .Y(n1246) );
OAI21X1TS U3430 ( .A0(n6062), .A1(n4671), .B0(n4673), .Y(n4674) );
BUFX3TS U3431 ( .A(n5045), .Y(n7049) );
NOR2XLTS U3432 ( .A(FSM_selector_B[1]), .B(Op_MY[52]), .Y(n5254) );
OAI21X1TS U3433 ( .A0(n4356), .A1(n4352), .B0(n4353), .Y(n4170) );
AOI21X2TS U3434 ( .A0(n8226), .A1(n4295), .B0(n4294), .Y(n8248) );
NOR2X1TS U3435 ( .A(n4326), .B(Sgf_operation_ODD1_Q_right[38]), .Y(n8249) );
NOR2X1TS U3436 ( .A(n8249), .B(n8255), .Y(n8308) );
NAND2X1TS U3437 ( .A(n988), .B(n8227), .Y(n8237) );
XOR2X1TS U3438 ( .A(n4572), .B(n4571), .Y(n4607) );
OAI21X1TS U3439 ( .A0(n4209), .A1(n4205), .B0(n4206), .Y(n4155) );
NAND2X4TS U3440 ( .A(n3539), .B(n7343), .Y(n3541) );
NAND2X4TS U3441 ( .A(n5904), .B(Op_MX[51]), .Y(n973) );
AOI21X2TS U3442 ( .A0(n1301), .A1(n1300), .B0(n1299), .Y(n1302) );
OAI21X1TS U3443 ( .A0(n1298), .A1(n1297), .B0(n1296), .Y(n1299) );
INVX4TS U3444 ( .A(n1304), .Y(n1280) );
CMPR42X2TS U3445 ( .A(mult_x_23_n955), .B(mult_x_23_n1429), .C(
mult_x_23_n958), .D(mult_x_23_n1455), .ICI(mult_x_23_n1481), .S(
mult_x_23_n953), .ICO(mult_x_23_n951), .CO(mult_x_23_n952) );
NOR2X1TS U3446 ( .A(Sgf_operation_ODD1_Q_right[34]), .B(n4285), .Y(n8231) );
INVX2TS U3447 ( .A(n8057), .Y(n8097) );
NAND2X4TS U3448 ( .A(n3544), .B(n3543), .Y(n7275) );
BUFX8TS U3449 ( .A(n7325), .Y(n897) );
AOI21X2TS U3450 ( .A0(n7360), .A1(n7359), .B0(n7358), .Y(n7361) );
INVX2TS U3451 ( .A(n7379), .Y(n7281) );
NAND2X4TS U3452 ( .A(n2182), .B(n2181), .Y(n7151) );
NOR2X4TS U3453 ( .A(n1941), .B(n1940), .Y(n7388) );
NOR2X4TS U3454 ( .A(n1737), .B(n1736), .Y(n7163) );
NOR2X4TS U3455 ( .A(n1735), .B(n1734), .Y(n7161) );
NAND2X4TS U3456 ( .A(n1732), .B(n1731), .Y(n7173) );
NOR2X4TS U3457 ( .A(n1593), .B(n1592), .Y(n7185) );
NOR2X4TS U3458 ( .A(mult_x_24_n893), .B(mult_x_24_n904), .Y(n6098) );
NAND2X4TS U3459 ( .A(mult_x_24_n966), .B(mult_x_24_n976), .Y(n6127) );
INVX2TS U3460 ( .A(n6176), .Y(n6171) );
NAND2X4TS U3461 ( .A(mult_x_24_n1057), .B(mult_x_24_n1061), .Y(n6176) );
NAND2X1TS U3462 ( .A(n4958), .B(n4963), .Y(n4928) );
NOR2X4TS U3463 ( .A(n5161), .B(n4925), .Y(n4958) );
NOR2X4TS U3464 ( .A(mult_x_23_n802), .B(mult_x_23_n812), .Y(n5293) );
NAND2X4TS U3465 ( .A(mult_x_23_n914), .B(mult_x_23_n921), .Y(n5947) );
INVX2TS U3466 ( .A(n1459), .Y(n1435) );
INVX2TS U3467 ( .A(n1452), .Y(n1441) );
INVX2TS U3468 ( .A(n2238), .Y(n1998) );
NAND2X1TS U3469 ( .A(n1998), .B(n2237), .Y(n1969) );
AOI21X1TS U3470 ( .A0(n2002), .A1(n1976), .B0(n1958), .Y(n1959) );
INVX2TS U3471 ( .A(n1975), .Y(n1958) );
NAND2X1TS U3472 ( .A(n1998), .B(n1976), .Y(n1960) );
NAND2X1TS U3473 ( .A(n1951), .B(n1901), .Y(n1903) );
AOI21X1TS U3474 ( .A0(n1957), .A1(n1901), .B0(n1900), .Y(n1902) );
XNOR2X1TS U3475 ( .A(n900), .B(n2784), .Y(n2785) );
XNOR2X1TS U3476 ( .A(n2580), .B(n3358), .Y(n2227) );
INVX2TS U3477 ( .A(n1780), .Y(n1769) );
INVX2TS U3478 ( .A(n1671), .Y(n1607) );
INVX2TS U3479 ( .A(n1668), .Y(n1603) );
NAND2X1TS U3480 ( .A(n1453), .B(n1441), .Y(n1443) );
NOR2X4TS U3481 ( .A(n1336), .B(n1389), .Y(n1325) );
CLKBUFX2TS U3482 ( .A(n1346), .Y(n1347) );
XNOR2X1TS U3483 ( .A(n3227), .B(n3226), .Y(n3302) );
AOI21X2TS U3484 ( .A0(n1761), .A1(n1760), .B0(n1759), .Y(n1762) );
OAI21X2TS U3485 ( .A0(n1758), .A1(n1757), .B0(n1756), .Y(n1759) );
NAND2X1TS U3486 ( .A(n2001), .B(n1998), .Y(n2004) );
XNOR2X1TS U3487 ( .A(n3285), .B(n3167), .Y(n3218) );
XNOR2X1TS U3488 ( .A(n3368), .B(n2871), .Y(n3168) );
XNOR2X1TS U3489 ( .A(n2873), .B(n3230), .Y(n3187) );
XNOR2X1TS U3490 ( .A(n2815), .B(n2997), .Y(n2880) );
XNOR2X1TS U3491 ( .A(n3368), .B(n2650), .Y(n2693) );
ADDFHX2TS U3492 ( .A(n2708), .B(n2707), .CI(n2706), .CO(n2761), .S(n2702) );
XNOR2X1TS U3493 ( .A(n860), .B(n2871), .Y(n2736) );
OAI22X1TS U3494 ( .A0(n2503), .A1(n3407), .B0(n2521), .B1(n3405), .Y(n2524)
);
XNOR2X1TS U3495 ( .A(n912), .B(n2583), .Y(n2541) );
XNOR2X1TS U3496 ( .A(n753), .B(n2468), .Y(n2512) );
XNOR2X1TS U3497 ( .A(n917), .B(n3346), .Y(n2216) );
XNOR2X1TS U3498 ( .A(n860), .B(n2518), .Y(n2266) );
XNOR2X1TS U3499 ( .A(n3176), .B(n3343), .Y(n2217) );
XNOR2X1TS U3500 ( .A(n3334), .B(n2720), .Y(n2307) );
XNOR2X1TS U3501 ( .A(n3165), .B(n2264), .Y(n2330) );
OAI22X1TS U3502 ( .A0(n1994), .A1(n3031), .B0(n1993), .B1(n935), .Y(n2042)
);
NAND2X1TS U3503 ( .A(n1334), .B(n1433), .Y(n1335) );
NAND2X2TS U3504 ( .A(n755), .B(Op_MY[5]), .Y(n1390) );
NAND2X1TS U3505 ( .A(n1387), .B(n1385), .Y(n1337) );
NAND2X4TS U3506 ( .A(n4975), .B(n1229), .Y(n4991) );
NOR2X2TS U3507 ( .A(n4324), .B(n4373), .Y(n4073) );
AOI21X2TS U3508 ( .A0(n4320), .A1(n4073), .B0(n4072), .Y(n4074) );
OAI21X1TS U3509 ( .A0(n4373), .A1(n4369), .B0(n4374), .Y(n4072) );
NOR2X2TS U3510 ( .A(n4275), .B(n4300), .Y(n4063) );
AOI21X2TS U3511 ( .A0(n4574), .A1(n4459), .B0(n4458), .Y(n4484) );
NAND2X1TS U3512 ( .A(n4573), .B(n4459), .Y(n4475) );
AOI21X1TS U3513 ( .A0(n4149), .A1(n3961), .B0(n3960), .Y(n3962) );
NAND2X2TS U3514 ( .A(n4150), .B(n3961), .Y(n3999) );
AO21X1TS U3515 ( .A0(n888), .A1(n1710), .B0(n2942), .Y(n2980) );
NOR2X1TS U3516 ( .A(n2975), .B(n3583), .Y(n3029) );
OAI22X1TS U3517 ( .A0(n3280), .A1(n3279), .B0(n3347), .B1(n3401), .Y(n3324)
);
ADDFX2TS U3518 ( .A(n3328), .B(n3327), .CI(n3326), .CO(n3489), .S(n3321) );
NAND2X2TS U3519 ( .A(n2244), .B(n2237), .Y(n2246) );
NAND2X1TS U3520 ( .A(n2283), .B(n1010), .Y(n2250) );
XNOR2X1TS U3521 ( .A(n853), .B(n3230), .Y(n3073) );
XNOR2X1TS U3522 ( .A(n3276), .B(n3348), .Y(n2958) );
BUFX3TS U3523 ( .A(n935), .Y(n3250) );
OAI22X1TS U3524 ( .A0(n3180), .A1(n3179), .B0(n3178), .B1(n3220), .Y(n3258)
);
OAI22X1TS U3525 ( .A0(n2823), .A1(n3179), .B0(n2882), .B1(n2016), .Y(n2889)
);
ADDFHX2TS U3526 ( .A(n2847), .B(n2846), .CI(n2845), .CO(n2891), .S(n2853) );
ADDFHX2TS U3527 ( .A(n2490), .B(n2489), .CI(n2488), .CO(n2491), .S(n2496) );
XNOR2X1TS U3528 ( .A(n3334), .B(n2468), .Y(n2059) );
XNOR2X1TS U3529 ( .A(n3165), .B(n2070), .Y(n2061) );
XNOR2X1TS U3530 ( .A(n741), .B(n2294), .Y(n1818) );
CLKBUFX2TS U3531 ( .A(n2016), .Y(n3221) );
AOI21X2TS U3532 ( .A0(n1209), .A1(n6423), .B0(n1208), .Y(n1210) );
NAND2X1TS U3533 ( .A(n6389), .B(n6297), .Y(n6299) );
INVX2TS U3534 ( .A(n6280), .Y(n6389) );
OAI21X1TS U3535 ( .A0(n7075), .A1(n7062), .B0(n6347), .Y(n6348) );
AOI222X1TS U3536 ( .A0(n7060), .A1(n7071), .B0(n7058), .B1(n6569), .C0(n7080), .C1(n7068), .Y(n6347) );
AOI21X1TS U3537 ( .A0(n6392), .A1(n6284), .B0(n6283), .Y(n6285) );
NAND2X1TS U3538 ( .A(n6284), .B(n6389), .Y(n6286) );
OAI21X1TS U3539 ( .A0(n7014), .A1(n7013), .B0(n7012), .Y(n7015) );
OAI21XLTS U3540 ( .A0(n7014), .A1(n6966), .B0(n6534), .Y(n6535) );
BUFX3TS U3541 ( .A(n6454), .Y(n6760) );
BUFX3TS U3542 ( .A(n5075), .Y(n6834) );
AOI21X2TS U3543 ( .A0(n6429), .A1(n6364), .B0(n6350), .Y(n6351) );
NAND2X1TS U3544 ( .A(n6422), .B(n6364), .Y(n6352) );
INVX2TS U3545 ( .A(n6349), .Y(n6364) );
CLKAND2X2TS U3546 ( .A(n5899), .B(n5802), .Y(n4989) );
CLKAND2X2TS U3547 ( .A(n5899), .B(n852), .Y(n5417) );
CLKAND2X2TS U3548 ( .A(n5899), .B(n849), .Y(n5423) );
CLKAND2X2TS U3549 ( .A(n6060), .B(n851), .Y(n5429) );
OAI21X1TS U3550 ( .A0(n5957), .A1(n6035), .B0(n5431), .Y(n5432) );
OAI21X1TS U3551 ( .A0(n5762), .A1(n6067), .B0(n3616), .Y(n3617) );
CLKAND2X2TS U3552 ( .A(n6060), .B(n855), .Y(n3604) );
CLKAND2X2TS U3553 ( .A(n6060), .B(Op_MY[28]), .Y(n5435) );
NAND2X2TS U3554 ( .A(n5398), .B(n1254), .Y(n5453) );
NOR2X2TS U3555 ( .A(n829), .B(n5906), .Y(n5402) );
NOR2X1TS U3556 ( .A(n6038), .B(n829), .Y(n1249) );
INVX2TS U3557 ( .A(n1248), .Y(n1242) );
NAND2X1TS U3558 ( .A(n6038), .B(n829), .Y(n1252) );
NOR2X2TS U3559 ( .A(n6045), .B(n6023), .Y(n5480) );
NAND2X1TS U3560 ( .A(n6045), .B(n6023), .Y(n5481) );
NOR2X2TS U3561 ( .A(n5963), .B(n6045), .Y(n5000) );
NOR2X2TS U3562 ( .A(n828), .B(n5963), .Y(n5601) );
NAND2X2TS U3563 ( .A(n6016), .B(Op_MY[39]), .Y(n5597) );
NAND2X2TS U3564 ( .A(n4335), .B(n4002), .Y(n4160) );
NAND2X2TS U3565 ( .A(n4271), .B(n4063), .Y(n4306) );
INVX2TS U3566 ( .A(Sgf_operation_Result[7]), .Y(n4037) );
NOR2X1TS U3567 ( .A(n4156), .B(n4131), .Y(n4101) );
OAI22X1TS U3568 ( .A0(n3034), .A1(n3336), .B0(n3045), .B1(n3417), .Y(n3055)
);
ADDFHX2TS U3569 ( .A(n3478), .B(n3477), .CI(n3476), .CO(n3492), .S(n3503) );
OAI22X1TS U3570 ( .A0(n3347), .A1(n890), .B0(n3404), .B1(n3401), .Y(n3396)
);
ADDFHX2TS U3571 ( .A(n3342), .B(n3341), .CI(n3340), .CO(n3505), .S(n3372) );
AOI21X1TS U3572 ( .A0(n1256), .A1(n3841), .B0(n1255), .Y(n1257) );
NOR2X4TS U3573 ( .A(n2246), .B(n2238), .Y(n2278) );
ADDFHX2TS U3574 ( .A(n3481), .B(n3480), .CI(n3479), .CO(n3440), .S(n3491) );
ADDFX1TS U3575 ( .A(n3238), .B(n3237), .CI(n3236), .CO(n3266), .S(n3260) );
ADDFHX2TS U3576 ( .A(n2862), .B(n2861), .CI(n2860), .CO(n3210), .S(n2902) );
OAI22X1TS U3577 ( .A0(n1832), .A1(n3178), .B0(n1808), .B1(n3222), .Y(n1805)
);
ADDHX1TS U3578 ( .A(n1546), .B(n1545), .CO(n1540), .S(n1558) );
INVX4TS U3579 ( .A(n861), .Y(n862) );
NOR2X2TS U3580 ( .A(n3814), .B(n6248), .Y(n3824) );
CLKBUFX2TS U3581 ( .A(n3815), .Y(n6281) );
CLKAND2X2TS U3582 ( .A(n7010), .B(n7001), .Y(n6218) );
NAND2X1TS U3583 ( .A(n6322), .B(n6327), .Y(n6313) );
AOI21X1TS U3584 ( .A0(n6392), .A1(n6391), .B0(n6390), .Y(n6393) );
NAND2X1TS U3585 ( .A(n6389), .B(n6391), .Y(n6394) );
OAI21X1TS U3586 ( .A0(n6967), .A1(n6984), .B0(n6545), .Y(n6546) );
AOI222X1TS U3587 ( .A0(n883), .A1(n874), .B0(n7010), .B1(n6929), .C0(n6491),
.C1(n6559), .Y(n6492) );
OAI21X1TS U3588 ( .A0(n7006), .A1(n6999), .B0(n6998), .Y(n7000) );
CLKAND2X2TS U3589 ( .A(n6995), .B(n7001), .Y(n6996) );
AOI222X1TS U3590 ( .A0(n7072), .A1(n7071), .B0(n7070), .B1(n7069), .C0(n844),
.C1(n7068), .Y(n7073) );
OAI21X1TS U3591 ( .A0(n6967), .A1(n6999), .B0(n6745), .Y(n6746) );
AOI222X1TS U3592 ( .A0(n6771), .A1(n6922), .B0(n6980), .B1(Op_MX[21]), .C0(
n6982), .C1(n878), .Y(n6554) );
OAI21X2TS U3593 ( .A0(n6769), .A1(n6999), .B0(n6768), .Y(n6770) );
OAI21X2TS U3594 ( .A0(n6933), .A1(n6788), .B0(n6747), .Y(n6748) );
CLKAND2X2TS U3595 ( .A(n6970), .B(n7001), .Y(n6971) );
AOI222X1TS U3596 ( .A0(n6771), .A1(n6814), .B0(n7021), .B1(n879), .C0(n6982),
.C1(n6930), .Y(n6772) );
CLKAND2X2TS U3597 ( .A(n7078), .B(n6584), .Y(mult_x_24_n1106) );
CLKAND2X2TS U3598 ( .A(n887), .B(n7001), .Y(n6657) );
AOI222X1TS U3599 ( .A0(n6683), .A1(n6963), .B0(n886), .B1(n6961), .C0(n6813),
.C1(n6756), .Y(n6660) );
CLKAND2X2TS U3600 ( .A(n6897), .B(Op_MY[26]), .Y(mult_x_24_n1107) );
AOI222X1TS U3601 ( .A0(n6839), .A1(n874), .B0(n6995), .B1(n6929), .C0(n6997),
.C1(n6928), .Y(n6840) );
AOI222X1TS U3602 ( .A0(n6817), .A1(n926), .B0(n887), .B1(n6767), .C0(n6813),
.C1(n833), .Y(n6662) );
OAI21X1TS U3603 ( .A0(n729), .A1(n7025), .B0(n6565), .Y(n6566) );
AOI222X1TS U3604 ( .A0(n7023), .A1(n7071), .B0(n7021), .B1(n6569), .C0(n6581), .C1(n7068), .Y(n6570) );
AOI222X1TS U3605 ( .A0(n6750), .A1(n877), .B0(n6970), .B1(n6830), .C0(n6990),
.C1(Op_MX[18]), .Y(n6629) );
AOI222X1TS U3606 ( .A0(n6817), .A1(Op_MX[23]), .B0(n887), .B1(n6922), .C0(
n6813), .C1(n6847), .Y(n6666) );
OAI21X1TS U3607 ( .A0(n6967), .A1(n7005), .B0(n6697), .Y(n6698) );
OAI21X1TS U3608 ( .A0(n6879), .A1(n6872), .B0(n6871), .Y(n6873) );
OAI21XLTS U3609 ( .A0(n7014), .A1(n6999), .B0(n6606), .Y(n6607) );
AOI222X1TS U3610 ( .A0(n6848), .A1(n875), .B0(n6843), .B1(n7008), .C0(n7043),
.C1(n6904), .Y(n6774) );
AOI222X1TS U3611 ( .A0(n884), .A1(n6847), .B0(n6916), .B1(n6846), .C0(n7003),
.C1(n874), .Y(n6709) );
NAND2X4TS U3612 ( .A(n6958), .B(n6753), .Y(n6462) );
AOI222X1TS U3613 ( .A0(n6683), .A1(n6894), .B0(n886), .B1(n937), .C0(n6902),
.C1(n8412), .Y(n6676) );
AOI222X1TS U3614 ( .A0(n6750), .A1(n875), .B0(n7034), .B1(n827), .C0(n7032),
.C1(n6904), .Y(n6645) );
NAND2X1TS U3615 ( .A(n6428), .B(n6422), .Y(n6431) );
AOI21X2TS U3616 ( .A0(n6429), .A1(n6428), .B0(n6427), .Y(n6430) );
OAI21X1TS U3617 ( .A0(n6426), .A1(n6425), .B0(n6424), .Y(n6427) );
NAND2X1TS U3618 ( .A(n6457), .B(n6463), .Y(n6447) );
NAND2X2TS U3619 ( .A(n7008), .B(n910), .Y(n6449) );
AOI222X1TS U3620 ( .A0(n6683), .A1(n8412), .B0(n6903), .B1(n7069), .C0(n6902), .C1(n875), .Y(n6680) );
OAI21XLTS U3621 ( .A0(n7014), .A1(n6819), .B0(n6684), .Y(n6685) );
AOI222X1TS U3622 ( .A0(n6683), .A1(Op_MX[13]), .B0(n6903), .B1(n7009), .C0(
n6902), .C1(n6853), .Y(n6684) );
XOR2X2TS U3623 ( .A(n4719), .B(n892), .Y(n6940) );
OAI21XLTS U3624 ( .A0(n7063), .A1(n6932), .B0(n6715), .Y(n6716) );
BUFX3TS U3625 ( .A(n6639), .Y(n7032) );
NAND2X1TS U3626 ( .A(n6422), .B(n6420), .Y(n6342) );
NAND2X2TS U3627 ( .A(n6785), .B(n7056), .Y(n6424) );
XOR2X1TS U3628 ( .A(n5044), .B(n7027), .Y(n7016) );
AOI22X1TS U3629 ( .A0(n6558), .A1(n5041), .B0(n6771), .B1(n6243), .Y(n5042)
);
AOI21X2TS U3630 ( .A0(n1096), .A1(n1118), .B0(n1121), .Y(n1145) );
NAND2X2TS U3631 ( .A(n6874), .B(n8414), .Y(n1143) );
NAND2X1TS U3632 ( .A(n5883), .B(n5771), .Y(n3868) );
AOI21X1TS U3633 ( .A0(n5936), .A1(n6045), .B0(n1238), .Y(n1239) );
CLKAND2X2TS U3634 ( .A(n6060), .B(n6045), .Y(n5889) );
OAI21X1TS U3635 ( .A0(n5912), .A1(n5470), .B0(n5472), .Y(n5473) );
OAI21X1TS U3636 ( .A0(n5887), .A1(n5827), .B0(n5571), .Y(n5572) );
CLKAND2X2TS U3637 ( .A(n5899), .B(n828), .Y(n5897) );
CLKAND2X2TS U3638 ( .A(n5899), .B(n8385), .Y(n5900) );
AOI222X1TS U3639 ( .A0(n882), .A1(n6028), .B0(n865), .B1(n6005), .C0(n6017),
.C1(n850), .Y(n5972) );
AO21XLTS U3640 ( .A0(n5975), .A1(n5769), .B0(n5701), .Y(n5672) );
AO21XLTS U3641 ( .A0(n5745), .A1(n5769), .B0(n5859), .Y(n5715) );
AOI222X1TS U3642 ( .A0(n5922), .A1(n5796), .B0(n5561), .B1(n5982), .C0(n6010), .C1(n6005), .Y(n5550) );
AO21XLTS U3643 ( .A0(n873), .A1(n5769), .B0(n870), .Y(n5770) );
NOR2X1TS U3644 ( .A(n5942), .B(n5939), .Y(n5457) );
NAND2X1TS U3645 ( .A(n5942), .B(n5939), .Y(n5458) );
AOI222X1TS U3646 ( .A0(n5983), .A1(n6005), .B0(n5981), .B1(n837), .C0(n5980),
.C1(n8385), .Y(n5956) );
NOR2X2TS U3647 ( .A(n5906), .B(n5935), .Y(n5535) );
NAND2X1TS U3648 ( .A(n5906), .B(n5935), .Y(n5536) );
XOR2X1TS U3649 ( .A(n4684), .B(n5567), .Y(n5139) );
NAND2X2TS U3650 ( .A(n7507), .B(n6016), .Y(n4985) );
NAND2X2TS U3651 ( .A(n5901), .B(n7508), .Y(n3724) );
NOR2X2TS U3652 ( .A(n5901), .B(n7508), .Y(n3723) );
NAND2X1TS U3653 ( .A(Op_MY[35]), .B(Op_MY[36]), .Y(n3619) );
INVX2TS U3654 ( .A(n3618), .Y(n3620) );
XOR2X1TS U3655 ( .A(n4677), .B(n5567), .Y(n5910) );
NAND2X1TS U3656 ( .A(n4675), .B(n4966), .Y(n4676) );
NAND2X1TS U3657 ( .A(n5963), .B(n6045), .Y(n5476) );
BUFX3TS U3658 ( .A(n5650), .Y(n5959) );
NOR2X2TS U3659 ( .A(n848), .B(n852), .Y(n3657) );
NOR2X2TS U3660 ( .A(n4071), .B(n4070), .Y(n4373) );
AOI21X1TS U3661 ( .A0(n4381), .A1(n4335), .B0(n4334), .Y(n4368) );
AOI21X2TS U3662 ( .A0(n4343), .A1(n4165), .B0(n4164), .Y(n4356) );
NOR2X2TS U3663 ( .A(n4029), .B(n4028), .Y(n4264) );
INVX2TS U3664 ( .A(n4272), .Y(n4273) );
INVX2TS U3665 ( .A(n4271), .Y(n4274) );
INVX2TS U3666 ( .A(n4275), .Y(n4298) );
NAND2X1TS U3667 ( .A(n4061), .B(n4060), .Y(n4301) );
INVX2TS U3668 ( .A(n4320), .Y(n4321) );
NAND2X1TS U3669 ( .A(n4027), .B(n4026), .Y(n4251) );
OAI21X2TS U3670 ( .A0(n4522), .A1(n4521), .B0(n4520), .Y(n4523) );
NAND2X1TS U3671 ( .A(n4514), .B(n4518), .Y(n4521) );
INVX2TS U3672 ( .A(n4580), .Y(n4595) );
AOI21X1TS U3673 ( .A0(n4183), .A1(n4182), .B0(n4181), .Y(n4188) );
ADDFHX2TS U3674 ( .A(n3019), .B(n3018), .CI(n3017), .CO(n3044), .S(n3040) );
ADDFX2TS U3675 ( .A(n3372), .B(n3371), .CI(n3370), .CO(n3498), .S(n3373) );
ADDFHX2TS U3676 ( .A(n3502), .B(n3501), .CI(n3500), .CO(n3511), .S(n3499) );
INVX2TS U3677 ( .A(n4183), .Y(n4175) );
OAI22X1TS U3678 ( .A0(n3121), .A1(n3155), .B0(n3128), .B1(n3422), .Y(n3130)
);
OAI21X2TS U3679 ( .A0(n3928), .A1(n3922), .B0(n3929), .Y(n4822) );
INVX2TS U3680 ( .A(n7432), .Y(n3535) );
OAI22X1TS U3681 ( .A0(n3092), .A1(n3361), .B0(n3105), .B1(n3378), .Y(n3102)
);
ADDFHX2TS U3682 ( .A(n3466), .B(n3465), .CI(n3464), .CO(n3467), .S(n3494) );
ADDFHX2TS U3683 ( .A(n2904), .B(n2903), .CI(n2902), .CO(n3192), .S(n2910) );
ADDFHX2TS U3684 ( .A(n2749), .B(n2748), .CI(n2747), .CO(n2776), .S(n2691) );
INVX2TS U3685 ( .A(n812), .Y(n813) );
INVX2TS U3686 ( .A(n2660), .Y(n812) );
ADDFHX2TS U3687 ( .A(n2135), .B(n2134), .CI(n2133), .CO(n2170), .S(n2154) );
OAI22X1TS U3688 ( .A0(n1610), .A1(n2363), .B0(n1680), .B1(n1974), .Y(n1660)
);
ADDFHX2TS U3689 ( .A(n1630), .B(n1629), .CI(n1628), .CO(n1682), .S(n1642) );
ADDFX2TS U3690 ( .A(n1580), .B(n1579), .CI(n1578), .CO(n1496), .S(n1585) );
OAI22X1TS U3691 ( .A0(n1477), .A1(n2808), .B0(n1479), .B1(n2100), .Y(n1579)
);
BUFX3TS U3692 ( .A(n1828), .Y(n2787) );
NAND2X4TS U3693 ( .A(Op_MY[27]), .B(Op_MY[0]), .Y(n948) );
AOI21X1TS U3694 ( .A0(n6390), .A1(n3818), .B0(n3817), .Y(n3819) );
NOR2X4TS U3695 ( .A(n3816), .B(n6280), .Y(n6268) );
AND2X2TS U3696 ( .A(n4730), .B(n6245), .Y(n4731) );
NAND2X1TS U3697 ( .A(n5023), .B(n3807), .Y(n5111) );
CLKAND2X2TS U3698 ( .A(n6921), .B(n7001), .Y(n3830) );
CLKAND2X2TS U3699 ( .A(Op_MY[26]), .B(n6952), .Y(mult_x_24_n1088) );
NAND2X1TS U3700 ( .A(n1295), .B(n5029), .Y(n1298) );
CLKAND2X2TS U3701 ( .A(Op_MY[26]), .B(n879), .Y(n6216) );
CLKAND2X2TS U3702 ( .A(n6946), .B(n6559), .Y(mult_x_24_n1092) );
AOI222X1TS U3703 ( .A0(n6923), .A1(n6814), .B0(n7058), .B1(n877), .C0(n7080),
.C1(n874), .Y(n6306) );
CLKAND2X2TS U3704 ( .A(n6946), .B(n6562), .Y(mult_x_24_n1093) );
NAND2X2TS U3705 ( .A(n1198), .B(n4862), .Y(n1200) );
CMPR42X1TS U3706 ( .A(mult_x_24_n740), .B(mult_x_24_n747), .C(
mult_x_24_n1489), .D(mult_x_24_n1435), .ICI(mult_x_24_n1462), .S(
mult_x_24_n739), .ICO(mult_x_24_n737), .CO(mult_x_24_n738) );
XOR2X1TS U3707 ( .A(n6969), .B(n6968), .Y(mult_x_24_n1490) );
BUFX4TS U3708 ( .A(n5075), .Y(n7010) );
BUFX3TS U3709 ( .A(n5076), .Y(n6491) );
CLKAND2X2TS U3710 ( .A(n6946), .B(n7056), .Y(n6229) );
BUFX3TS U3711 ( .A(n6454), .Y(n7070) );
CLKAND2X2TS U3712 ( .A(n7078), .B(n910), .Y(mult_x_24_n1099) );
CMPR42X1TS U3713 ( .A(mult_x_24_n795), .B(mult_x_24_n805), .C(
mult_x_24_n1441), .D(mult_x_24_n1414), .ICI(mult_x_24_n1495), .S(
mult_x_24_n794), .ICO(mult_x_24_n792), .CO(mult_x_24_n793) );
XOR2X1TS U3714 ( .A(n6994), .B(n8378), .Y(mult_x_24_n1578) );
XOR2X1TS U3715 ( .A(n6759), .B(n6758), .Y(mult_x_24_n1580) );
CMPR42X1TS U3716 ( .A(mult_x_24_n1475), .B(mult_x_24_n888), .C(
mult_x_24_n1529), .D(mult_x_24_n1583), .ICI(mult_x_24_n889), .S(
mult_x_24_n875), .ICO(mult_x_24_n873), .CO(mult_x_24_n874) );
CMPR42X1TS U3717 ( .A(mult_x_24_n952), .B(mult_x_24_n1508), .C(
mult_x_24_n1481), .D(mult_x_24_n1535), .ICI(mult_x_24_n959), .S(
mult_x_24_n950), .ICO(mult_x_24_n948), .CO(mult_x_24_n949) );
INVX6TS U3718 ( .A(n6330), .Y(n6793) );
NAND2X1TS U3719 ( .A(n6327), .B(n6326), .Y(n6328) );
INVX2TS U3720 ( .A(n6815), .Y(n887) );
OAI21X1TS U3721 ( .A0(n7039), .A1(n6907), .B0(n6837), .Y(n6838) );
ADDHX1TS U3722 ( .A(n4728), .B(n4727), .CO(mult_x_24_n1067), .S(n1163) );
BUFX3TS U3723 ( .A(n1130), .Y(n6907) );
AOI222X1TS U3724 ( .A0(n6683), .A1(n7042), .B0(n886), .B1(n7022), .C0(n822),
.C1(n6822), .Y(n1078) );
INVX6TS U3725 ( .A(n1046), .Y(n7050) );
NAND2X1TS U3726 ( .A(n1043), .B(n1064), .Y(n1044) );
CLKXOR2X2TS U3727 ( .A(n1061), .B(n940), .Y(n1071) );
NAND2X1TS U3728 ( .A(n1094), .B(n1093), .Y(n1095) );
NAND2X1TS U3729 ( .A(n1000), .B(n1075), .Y(n1076) );
CLKAND2X2TS U3730 ( .A(n5940), .B(n5775), .Y(n3854) );
CLKAND2X2TS U3731 ( .A(n5940), .B(n5939), .Y(n5941) );
CLKAND2X2TS U3732 ( .A(n5940), .B(n5935), .Y(n5894) );
CLKAND2X2TS U3733 ( .A(n5940), .B(n5942), .Y(n5934) );
CLKAND2X2TS U3734 ( .A(n6060), .B(n5906), .Y(n5907) );
AO21XLTS U3735 ( .A0(n5494), .A1(n5769), .B0(n6033), .Y(n5495) );
OAI21X2TS U3736 ( .A0(n5945), .A1(n5470), .B0(n5411), .Y(n5412) );
OAI21X1TS U3737 ( .A0(n6026), .A1(n6061), .B0(n1247), .Y(n1265) );
OAI21X1TS U3738 ( .A0(n4782), .A1(n4794), .B0(n4783), .Y(n3766) );
NOR2X2TS U3739 ( .A(n3769), .B(n4898), .Y(n3763) );
CMPR42X1TS U3740 ( .A(mult_x_23_n744), .B(mult_x_23_n754), .C(
mult_x_23_n1302), .D(mult_x_23_n1406), .ICI(mult_x_23_n1354), .S(
mult_x_23_n743), .ICO(mult_x_23_n741), .CO(mult_x_23_n742) );
CMPR42X1TS U3741 ( .A(mult_x_23_n810), .B(mult_x_23_n817), .C(
mult_x_23_n1334), .D(mult_x_23_n1438), .ICI(mult_x_23_n814), .S(
mult_x_23_n805), .ICO(mult_x_23_n803), .CO(mult_x_23_n804) );
XOR2X1TS U3742 ( .A(n5842), .B(n5847), .Y(mult_x_23_n1313) );
CLKBUFX2TS U3743 ( .A(n5653), .Y(n5983) );
CLKBUFX2TS U3744 ( .A(n5650), .Y(n5981) );
AOI222X1TS U3745 ( .A0(n5929), .A1(n848), .B0(n5698), .B1(n830), .C0(n5928),
.C1(n855), .Y(n5852) );
OAI21XLTS U3746 ( .A0(n979), .A1(n5807), .B0(n3727), .Y(n3728) );
NAND2X1TS U3747 ( .A(n3708), .B(n3707), .Y(n3709) );
OAI21X2TS U3748 ( .A0(n3705), .A1(n3704), .B0(n3703), .Y(n3710) );
AND3X2TS U3749 ( .A(n3639), .B(n3638), .C(n3637), .Y(n5751) );
INVX2TS U3750 ( .A(n4205), .Y(n4207) );
NOR2X1TS U3751 ( .A(n8301), .B(n8295), .Y(n8277) );
OAI21X1TS U3752 ( .A0(n4508), .A1(n4507), .B0(n4506), .Y(n4513) );
NOR2X1TS U3753 ( .A(n7983), .B(n7972), .Y(n7944) );
OAI21X1TS U3754 ( .A0(n7972), .A1(n7984), .B0(n7973), .Y(n7945) );
ADDFX2TS U3755 ( .A(n3041), .B(n3040), .CI(n3039), .CO(n3546), .S(n3543) );
AND2X2TS U3756 ( .A(n4821), .B(n3556), .Y(n1021) );
BUFX3TS U3757 ( .A(n2941), .Y(n3154) );
INVX2TS U3758 ( .A(n4820), .Y(n7294) );
ADDHX1TS U3759 ( .A(n1513), .B(n1512), .CO(n1522), .S(n1509) );
AND3X4TS U3760 ( .A(n1048), .B(n1005), .C(n999), .Y(n6893) );
OAI21XLTS U3761 ( .A0(n6084), .A1(n5665), .B0(n5686), .Y(n5687) );
XOR2X1TS U3762 ( .A(n3645), .B(n5763), .Y(n3675) );
INVX4TS U3763 ( .A(n3649), .Y(n5437) );
AOI21X1TS U3764 ( .A0(n7427), .A1(n7343), .B0(n7344), .Y(n7331) );
INVX2TS U3765 ( .A(n8117), .Y(n8119) );
MX2X1TS U3766 ( .A(Op_MX[52]), .B(exp_oper_result[0]), .S0(n846), .Y(
S_Oper_A_exp[0]) );
NAND4XLTS U3767 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n8356) );
INVX2TS U3768 ( .A(n7893), .Y(n7895) );
INVX2TS U3769 ( .A(n8006), .Y(n8008) );
INVX2TS U3770 ( .A(n8063), .Y(n8065) );
INVX2TS U3771 ( .A(n5328), .Y(n3756) );
OR2X2TS U3772 ( .A(n3551), .B(n3550), .Y(n4696) );
INVX2TS U3773 ( .A(n4826), .Y(n7311) );
AOI21X2TS U3774 ( .A0(n7325), .A1(n7308), .B0(n7307), .Y(n7309) );
AOI21X1TS U3775 ( .A0(n7427), .A1(n7347), .B0(n7346), .Y(n7348) );
CLKAND2X2TS U3776 ( .A(n6946), .B(n926), .Y(n5126) );
XOR3X1TS U3777 ( .A(n1017), .B(n5128), .C(n5127), .Y(n5129) );
AOI21X2TS U3778 ( .A0(n1280), .A1(n1279), .B0(n1278), .Y(n5026) );
OAI21X1TS U3779 ( .A0(n4888), .A1(n4868), .B0(n4867), .Y(n4869) );
OAI21XLTS U3780 ( .A0(n5222), .A1(n4840), .B0(n5228), .Y(n4841) );
NOR2X1TS U3781 ( .A(n5152), .B(n5154), .Y(n5194) );
OR2X4TS U3782 ( .A(mult_x_23_n683), .B(mult_x_23_n689), .Y(n5196) );
OAI21X1TS U3783 ( .A0(n5155), .A1(n5154), .B0(n5153), .Y(n5197) );
NAND2X4TS U3784 ( .A(n5276), .B(n3765), .Y(n4898) );
NAND2X4TS U3785 ( .A(mult_x_23_n791), .B(mult_x_23_n801), .Y(n5286) );
NAND2X1TS U3786 ( .A(n3735), .B(n3734), .Y(n5814) );
INVX2TS U3787 ( .A(Sgf_operation_ODD1_left_N0), .Y(n3672) );
BUFX3TS U3788 ( .A(n803), .Y(n6053) );
NAND2X1TS U3789 ( .A(n7415), .B(n7418), .Y(n7333) );
NAND2X1TS U3790 ( .A(n7417), .B(n7343), .Y(n7332) );
CLKAND2X2TS U3791 ( .A(n7407), .B(n7405), .Y(n976) );
INVX2TS U3792 ( .A(n8149), .Y(n8151) );
INVX2TS U3793 ( .A(n8128), .Y(n8130) );
MX2X1TS U3794 ( .A(P_Sgf[98]), .B(n7594), .S0(n8191), .Y(n519) );
MX2X1TS U3795 ( .A(P_Sgf[99]), .B(n7584), .S0(n8191), .Y(n521) );
INVX2TS U3796 ( .A(n7578), .Y(n7581) );
INVX2TS U3797 ( .A(n8301), .Y(n8303) );
OAI21XLTS U3798 ( .A0(n8238), .A1(n8231), .B0(n8230), .Y(n8234) );
MX2X1TS U3799 ( .A(P_Sgf[1]), .B(Sgf_operation_Result[1]), .S0(n8188), .Y(
n422) );
MX2X1TS U3800 ( .A(P_Sgf[90]), .B(n7675), .S0(n7712), .Y(n511) );
MX2X1TS U3801 ( .A(P_Sgf[83]), .B(n7749), .S0(n7850), .Y(n504) );
INVX2TS U3802 ( .A(n7755), .Y(n7757) );
INVX2TS U3803 ( .A(n7791), .Y(n7793) );
MX2X1TS U3804 ( .A(P_Sgf[67]), .B(n7977), .S0(n7988), .Y(n488) );
OAI21XLTS U3805 ( .A0(n7987), .A1(n7983), .B0(n7984), .Y(n7976) );
MX2X1TS U3806 ( .A(P_Sgf[64]), .B(n8022), .S0(n8133), .Y(n485) );
INVX2TS U3807 ( .A(n8017), .Y(n8019) );
INVX2TS U3808 ( .A(n8076), .Y(n8078) );
OAI21XLTS U3809 ( .A0(n8087), .A1(n8099), .B0(n8100), .Y(n8092) );
OAI21XLTS U3810 ( .A0(n8175), .A1(n8171), .B0(n8172), .Y(n8166) );
MX2X1TS U3811 ( .A(n7884), .B(Add_result[21]), .S0(n8186), .Y(n558) );
MX2X1TS U3812 ( .A(n7943), .B(Add_result[17]), .S0(n8186), .Y(n562) );
MX2X1TS U3813 ( .A(n7971), .B(Add_result[15]), .S0(n7473), .Y(n564) );
MX2X1TS U3814 ( .A(n8127), .B(Add_result[4]), .S0(n8186), .Y(n575) );
XNOR2X1TS U3815 ( .A(n7291), .B(n7290), .Y(Sgf_operation_ODD1_middle_N32) );
NAND2X1TS U3816 ( .A(n7289), .B(n7288), .Y(n7290) );
OAI21X1TS U3817 ( .A0(n7379), .A1(n7287), .B0(n7244), .Y(n7291) );
OAI21X1TS U3818 ( .A0(n7005), .A1(n764), .B0(n1039), .Y(
Sgf_operation_ODD1_right_N0) );
NAND2X1TS U3819 ( .A(n7432), .B(n7431), .Y(n7433) );
NAND2X1TS U3820 ( .A(n7417), .B(n7426), .Y(n7429) );
NAND2X1TS U3821 ( .A(n7323), .B(n7318), .Y(n7320) );
AND2X2TS U3822 ( .A(n791), .B(n7328), .Y(n763) );
NAND2X1TS U3823 ( .A(n771), .B(n7275), .Y(n7276) );
NAND2X1TS U3824 ( .A(n7412), .B(n7411), .Y(n7413) );
AND2X2TS U3825 ( .A(n3915), .B(n3914), .Y(n970) );
NAND2X1TS U3826 ( .A(n7340), .B(n7339), .Y(n7341) );
NAND2X1TS U3827 ( .A(n7241), .B(n7240), .Y(n7242) );
XOR2X2TS U3828 ( .A(n3907), .B(n977), .Y(Sgf_operation_ODD1_left_N51) );
CLKAND2X2TS U3829 ( .A(n5943), .B(n3906), .Y(n977) );
OAI31X1TS U3830 ( .A0(n7535), .A1(n7484), .A2(n7534), .B0(n8448), .Y(n709)
);
MX2X1TS U3831 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n7495), .Y(n583) );
MX2X1TS U3832 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n8371), .Y(n585) );
MX2X1TS U3833 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n896), .Y(n586) );
MX2X1TS U3834 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n7499), .Y(n604) );
MX2X1TS U3835 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n7502), .Y(n605) );
MX2X1TS U3836 ( .A(Data_MY[28]), .B(n903), .S0(n7505), .Y(n610) );
MX2X1TS U3837 ( .A(Data_MY[34]), .B(Op_MY[34]), .S0(n896), .Y(n616) );
MX2X1TS U3838 ( .A(Data_MY[37]), .B(n5802), .S0(n8371), .Y(n619) );
MX2X1TS U3839 ( .A(Data_MY[41]), .B(Op_MY[41]), .S0(n7509), .Y(n623) );
MX2X1TS U3840 ( .A(Data_MY[43]), .B(Op_MY[43]), .S0(n8371), .Y(n625) );
MX2X1TS U3841 ( .A(Data_MY[44]), .B(Op_MY[44]), .S0(n7505), .Y(n626) );
MX2X1TS U3842 ( .A(Data_MY[46]), .B(Op_MY[46]), .S0(n7506), .Y(n628) );
MX2X1TS U3843 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n7496), .Y(n657) );
MX2X1TS U3844 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n7496), .Y(n658) );
MX2X1TS U3845 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n7509), .Y(n665) );
MX2X1TS U3846 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n7505), .Y(n666) );
MX2X1TS U3847 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n7506), .Y(n667) );
MX2X1TS U3848 ( .A(Data_MX[33]), .B(Op_MX[33]), .S0(n7502), .Y(n679) );
MX2X1TS U3849 ( .A(Data_MX[35]), .B(n7492), .S0(n7497), .Y(n681) );
MX2X1TS U3850 ( .A(Data_MX[44]), .B(n737), .S0(n7499), .Y(n690) );
MX2X1TS U3851 ( .A(Data_MX[45]), .B(Op_MX[45]), .S0(n7502), .Y(n691) );
MX2X1TS U3852 ( .A(Data_MX[46]), .B(Op_MX[46]), .S0(n7497), .Y(n692) );
NAND2X1TS U3853 ( .A(n7302), .B(n7301), .Y(n7303) );
OAI21X2TS U3854 ( .A0(n7430), .A1(n7299), .B0(n7298), .Y(n7304) );
NAND2X1TS U3855 ( .A(n7419), .B(n1016), .Y(n7350) );
XOR2X1TS U3856 ( .A(n891), .B(n4652), .Y(Sgf_operation_ODD1_middle_N36) );
XNOR2X1TS U3857 ( .A(n7367), .B(n7366), .Y(Sgf_operation_ODD1_middle_N35) );
NAND2X1TS U3858 ( .A(n7365), .B(n7364), .Y(n7366) );
NAND2X1TS U3859 ( .A(n7249), .B(n7355), .Y(n7250) );
XNOR2X1TS U3860 ( .A(n7286), .B(n7285), .Y(Sgf_operation_ODD1_middle_N33) );
NAND2X1TS U3861 ( .A(n7284), .B(n7283), .Y(n7285) );
OAI2BB1X1TS U3862 ( .A0N(n7281), .A1N(n799), .B0(n7280), .Y(n7286) );
XNOR2X1TS U3863 ( .A(n7384), .B(n7383), .Y(Sgf_operation_ODD1_middle_N31) );
NAND2X1TS U3864 ( .A(n7382), .B(n7381), .Y(n7383) );
XNOR2X1TS U3865 ( .A(n7256), .B(n7255), .Y(Sgf_operation_ODD1_middle_N30) );
NAND2X1TS U3866 ( .A(n7374), .B(n7376), .Y(n7255) );
XNOR2X1TS U3867 ( .A(n7372), .B(n7371), .Y(Sgf_operation_ODD1_middle_N29) );
NAND2X1TS U3868 ( .A(n7370), .B(n7369), .Y(n7371) );
XOR2X1TS U3869 ( .A(n7266), .B(n7265), .Y(Sgf_operation_ODD1_middle_N27) );
NAND2X1TS U3870 ( .A(n7264), .B(n7263), .Y(n7265) );
AOI21X1TS U3871 ( .A0(n7436), .A1(n7261), .B0(n7260), .Y(n7266) );
XOR2X1TS U3872 ( .A(n7441), .B(n7440), .Y(Sgf_operation_ODD1_middle_N26) );
NAND2X1TS U3873 ( .A(n7439), .B(n7438), .Y(n7440) );
XOR2X1TS U3874 ( .A(n7273), .B(n7272), .Y(Sgf_operation_ODD1_middle_N25) );
NAND2X1TS U3875 ( .A(n7271), .B(n7270), .Y(n7272) );
AOI21X1TS U3876 ( .A0(n7436), .A1(n7268), .B0(n7267), .Y(n7273) );
NAND2X1TS U3877 ( .A(n7148), .B(n964), .Y(n7149) );
XOR2X1TS U3878 ( .A(n7404), .B(n7403), .Y(Sgf_operation_ODD1_middle_N19) );
NAND2X1TS U3879 ( .A(n7402), .B(n7401), .Y(n7403) );
AOI21X1TS U3880 ( .A0(n7156), .A1(n7399), .B0(n7398), .Y(n7404) );
XOR2X1TS U3881 ( .A(n7236), .B(n7235), .Y(Sgf_operation_ODD1_middle_N18) );
NAND2X1TS U3882 ( .A(n7234), .B(n7395), .Y(n7235) );
XOR2X1TS U3883 ( .A(n7392), .B(n7391), .Y(Sgf_operation_ODD1_middle_N17) );
NAND2X1TS U3884 ( .A(n7389), .B(n7390), .Y(n7391) );
AOI21X1TS U3885 ( .A0(n7156), .A1(n7387), .B0(n7386), .Y(n7392) );
CLKAND2X2TS U3886 ( .A(n7225), .B(n7224), .Y(Sgf_operation_ODD1_middle_N1)
);
XNOR2X1TS U3887 ( .A(n5253), .B(n5252), .Y(Sgf_operation_ODD1_right_N34) );
XNOR2X1TS U3888 ( .A(n5248), .B(n5247), .Y(Sgf_operation_ODD1_right_N33) );
XOR2X1TS U3889 ( .A(n7105), .B(n7104), .Y(Sgf_operation_ODD1_right_N29) );
NAND2X1TS U3890 ( .A(n7103), .B(n7102), .Y(n7104) );
AOI21X1TS U3891 ( .A0(n7108), .A1(n7100), .B0(n7099), .Y(n7105) );
XOR2X1TS U3892 ( .A(n6979), .B(n6978), .Y(Sgf_operation_ODD1_right_N28) );
NAND2X1TS U3893 ( .A(n6977), .B(n7096), .Y(n6978) );
XOR2X1TS U3894 ( .A(n7112), .B(n7111), .Y(Sgf_operation_ODD1_right_N26) );
AOI21X1TS U3895 ( .A0(n7108), .A1(n7107), .B0(n7106), .Y(n7112) );
OAI21XLTS U3896 ( .A0(n6130), .A1(n6111), .B0(n6110), .Y(n6115) );
OAI21XLTS U3897 ( .A0(n6130), .A1(n6117), .B0(n6116), .Y(n6121) );
OAI21XLTS U3898 ( .A0(n6130), .A1(n6122), .B0(n6127), .Y(n6126) );
XOR2XLTS U3899 ( .A(n6130), .B(n6129), .Y(Sgf_operation_ODD1_right_N21) );
AOI21X1TS U3900 ( .A0(n6139), .A1(n6137), .B0(n6132), .Y(n6135) );
XOR2XLTS U3901 ( .A(n6208), .B(n6207), .Y(Sgf_operation_ODD1_right_N4) );
AOI21X2TS U3902 ( .A0(n5268), .A1(n5267), .B0(n5266), .Y(n5269) );
XOR2X2TS U3903 ( .A(n3781), .B(n992), .Y(Sgf_operation_ODD1_left_N41) );
INVX2TS U3904 ( .A(n4856), .Y(n4764) );
XNOR2X2TS U3905 ( .A(n4797), .B(n4796), .Y(Sgf_operation_ODD1_left_N33) );
AOI21X1TS U3906 ( .A0(n5315), .A1(n5292), .B0(n5291), .Y(n5297) );
XOR2X1TS U3907 ( .A(n5992), .B(n5991), .Y(Sgf_operation_ODD1_left_N19) );
NAND2X1TS U3908 ( .A(n787), .B(n5990), .Y(n5991) );
AOI21X1TS U3909 ( .A0(n5989), .A1(n5988), .B0(n5987), .Y(n5992) );
AOI21X1TS U3910 ( .A0(n5989), .A1(n5341), .B0(n5334), .Y(n5339) );
XOR2XLTS U3911 ( .A(n5813), .B(n5812), .Y(Sgf_operation_ODD1_left_N7) );
XOR2X2TS U3912 ( .A(n6782), .B(n6882), .Y(mult_x_24_n1418) );
OAI22X2TS U3913 ( .A0(n1529), .A1(n2738), .B0(n1519), .B1(n2045), .Y(n1531)
);
CLKXOR2X4TS U3914 ( .A(n1320), .B(n1319), .Y(n1828) );
XOR2X2TS U3915 ( .A(n5449), .B(Op_MX[50]), .Y(mult_x_23_n1263) );
OAI21X4TS U3916 ( .A0(n891), .A1(n4830), .B0(n4829), .Y(n4833) );
ADDFX2TS U3917 ( .A(n3457), .B(n3456), .CI(n3455), .CO(n3461), .S(n3441) );
XOR2X2TS U3918 ( .A(n4708), .B(n6794), .Y(n4714) );
ADDFHX2TS U3919 ( .A(n2746), .B(n2745), .CI(n2744), .CO(n2797), .S(n2749) );
ADDFHX4TS U3920 ( .A(n1934), .B(n1933), .CI(n1932), .CO(n1940), .S(n1939) );
ADDFHX2TS U3921 ( .A(n2587), .B(n2586), .CI(n2585), .CO(n2625), .S(n2596) );
AOI21X2TS U3922 ( .A0(n3893), .A1(n4948), .B0(n3892), .Y(n3894) );
OAI21X1TS U3923 ( .A0(n5938), .A1(n6052), .B0(n5937), .Y(mult_x_23_n1243) );
ADDFHX4TS U3924 ( .A(n2441), .B(n2440), .CI(n2439), .CO(n2449), .S(n2448) );
OAI21X1TS U3925 ( .A0(n6068), .A1(n6014), .B0(n4680), .Y(n4681) );
OAI21X1TS U3926 ( .A0(n5781), .A1(n5761), .B0(n5720), .Y(n5721) );
OR2X6TS U3927 ( .A(n2188), .B(n2187), .Y(n7143) );
XOR2X2TS U3928 ( .A(n3617), .B(n6069), .Y(n3630) );
NOR2X4TS U3929 ( .A(n1431), .B(n1434), .Y(n1453) );
BUFX12TS U3930 ( .A(n1763), .Y(n1698) );
OA21X1TS U3931 ( .A0(n5307), .A1(n5312), .B0(n5308), .Y(n762) );
NOR2X8TS U3932 ( .A(mult_x_23_n834), .B(mult_x_23_n824), .Y(n5307) );
OR2X4TS U3933 ( .A(n1599), .B(n1598), .Y(n789) );
OAI21X2TS U3934 ( .A0(n5162), .A1(n3895), .B0(n3894), .Y(n4923) );
CMPR42X2TS U3935 ( .A(n1022), .B(mult_x_23_n679), .C(mult_x_23_n1246), .D(
mult_x_23_n1294), .ICI(mult_x_23_n676), .S(mult_x_23_n672), .ICO(
mult_x_23_n666), .CO(mult_x_23_n671) );
NOR2X4TS U3936 ( .A(n6005), .B(n6016), .Y(n4984) );
NOR2X2TS U3937 ( .A(n5951), .B(n5359), .Y(n3745) );
INVX4TS U3938 ( .A(n3634), .Y(n3719) );
ADDFX2TS U3939 ( .A(n3357), .B(n3356), .CI(n3355), .CO(n3477), .S(n3341) );
ADDFHX2TS U3940 ( .A(n2734), .B(n2733), .CI(n2732), .CO(n2792), .S(n2741) );
OAI22X1TS U3941 ( .A0(n2216), .A1(n890), .B0(n2480), .B1(n2762), .Y(n2464)
);
ADDFX2TS U3942 ( .A(n2487), .B(n2486), .CI(n2485), .CO(n2597), .S(n2492) );
XNOR2X2TS U3943 ( .A(n3364), .B(n2939), .Y(n2480) );
NAND2X4TS U3944 ( .A(mult_x_24_n918), .B(mult_x_24_n930), .Y(n6103) );
OAI21X2TS U3945 ( .A0(n1145), .A1(n1144), .B0(n1143), .Y(n1150) );
XOR2X2TS U3946 ( .A(n6630), .B(n6758), .Y(mult_x_24_n1586) );
ADDFHX4TS U3947 ( .A(n2668), .B(n2667), .CI(n2666), .CO(n2918), .S(n2917) );
ADDFHX2TS U3948 ( .A(n2568), .B(n2567), .CI(n2566), .CO(n2657), .S(n2571) );
NAND2X2TS U3949 ( .A(mult_x_24_n751), .B(mult_x_24_n759), .Y(n4882) );
XNOR2X1TS U3950 ( .A(n5231), .B(n5230), .Y(Sgf_operation_ODD1_right_N36) );
OAI21X2TS U3951 ( .A0(n6092), .A1(n5227), .B0(n5226), .Y(n5231) );
OAI21X2TS U3952 ( .A0(n5280), .A1(n4781), .B0(n4780), .Y(n4786) );
INVX4TS U3953 ( .A(n4897), .Y(n4790) );
NOR2X8TS U3954 ( .A(n7278), .B(n7282), .Y(n7352) );
ADDFHX4TS U3955 ( .A(n2805), .B(n2804), .CI(n2803), .CO(n2925), .S(n2923) );
AOI222X1TS U3956 ( .A0(n6065), .A1(n8375), .B0(n6064), .B1(n6055), .C0(n6063), .C1(n6054), .Y(n6056) );
XNOR2X2TS U3957 ( .A(n2954), .B(n2653), .Y(n1829) );
ADDFHX2TS U3958 ( .A(n3135), .B(n3134), .CI(n3133), .CO(n3558), .S(n3550) );
AOI21X2TS U3959 ( .A0(n4822), .A1(n3572), .B0(n3571), .Y(n3591) );
ADDFHX4TS U3960 ( .A(n2681), .B(n2680), .CI(n2679), .CO(n2911), .S(n2452) );
CMPR42X2TS U3961 ( .A(mult_x_24_n1509), .B(mult_x_24_n1590), .C(
mult_x_24_n1617), .D(mult_x_24_n1644), .ICI(mult_x_24_n967), .S(
mult_x_24_n958), .ICO(mult_x_24_n956), .CO(mult_x_24_n957) );
OAI21X4TS U3962 ( .A0(n5161), .A1(n5271), .B0(n5164), .Y(n5151) );
BUFX3TS U3963 ( .A(n5712), .Y(n5745) );
INVX4TS U3964 ( .A(n765), .Y(n828) );
INVX2TS U3965 ( .A(n3662), .Y(n869) );
INVX2TS U3966 ( .A(n6405), .Y(n843) );
INVX4TS U3967 ( .A(n843), .Y(n844) );
INVX4TS U3968 ( .A(n880), .Y(n881) );
INVX4TS U3969 ( .A(n798), .Y(n848) );
BUFX3TS U3970 ( .A(Op_MX[13]), .Y(n6569) );
INVX4TS U3971 ( .A(n811), .Y(n1047) );
OR2X2TS U3972 ( .A(n999), .B(n1048), .Y(n811) );
INVX4TS U3973 ( .A(n756), .Y(n852) );
INVX2TS U3974 ( .A(n3669), .Y(n872) );
INVX2TS U3975 ( .A(n802), .Y(n850) );
OR2X1TS U3976 ( .A(n6021), .B(n737), .Y(n774) );
OR2X1TS U3977 ( .A(n6220), .B(Op_MY[17]), .Y(n775) );
OR2X1TS U3978 ( .A(n927), .B(n6562), .Y(n776) );
OR2X1TS U3979 ( .A(n8378), .B(Op_MY[51]), .Y(n778) );
INVX4TS U3980 ( .A(n772), .Y(n833) );
CLKINVX3TS U3981 ( .A(n772), .Y(n834) );
BUFX3TS U3982 ( .A(Op_MX[16]), .Y(n6562) );
OR2X2TS U3983 ( .A(mult_x_23_n929), .B(mult_x_23_n935), .Y(n780) );
OR2X1TS U3984 ( .A(n4232), .B(Sgf_operation_ODD1_Q_right[29]), .Y(n781) );
BUFX3TS U3985 ( .A(Op_MX[17]), .Y(n6559) );
OR2X2TS U3986 ( .A(mult_x_24_n760), .B(mult_x_24_n768), .Y(n784) );
OR2X2TS U3987 ( .A(mult_x_24_n729), .B(mult_x_24_n735), .Y(n785) );
INVX4TS U3988 ( .A(n794), .Y(n925) );
AOI22X1TS U3989 ( .A0(n5712), .A1(n4966), .B0(n5748), .B1(n6054), .Y(n795)
);
NAND2X1TS U3990 ( .A(n6060), .B(n824), .Y(n796) );
NOR2BX2TS U3991 ( .AN(n3614), .B(n3613), .Y(n4967) );
NOR2BX2TS U3992 ( .AN(n4654), .B(n4653), .Y(n5096) );
CLKBUFX2TS U3993 ( .A(Op_MY[31]), .Y(n7510) );
AND2X2TS U3994 ( .A(n7354), .B(n7289), .Y(n799) );
INVX6TS U3995 ( .A(n811), .Y(n884) );
OR2X1TS U3996 ( .A(Op_MY[14]), .B(n8373), .Y(n805) );
OR2X1TS U3997 ( .A(Op_MY[50]), .B(n6820), .Y(n806) );
OR2X1TS U3998 ( .A(Op_MX[21]), .B(Op_MX[20]), .Y(n808) );
OR2X1TS U3999 ( .A(Op_MX[41]), .B(Op_MX[35]), .Y(n809) );
NOR4X1TS U4000 ( .A(Op_MY[22]), .B(Op_MY[21]), .C(Op_MY[16]), .D(Op_MY[3]),
.Y(n810) );
OAI21X2TS U4001 ( .A0(n7101), .A1(n7096), .B0(n7102), .Y(n1181) );
CMPR42X2TS U4002 ( .A(mult_x_24_n898), .B(mult_x_24_n887), .C(mult_x_24_n895), .D(mult_x_24_n884), .ICI(mult_x_24_n891), .S(mult_x_24_n881), .ICO(
mult_x_24_n879), .CO(mult_x_24_n880) );
OAI21X2TS U4003 ( .A0(n7026), .A1(n6681), .B0(n1060), .Y(n1061) );
NAND2X4TS U4004 ( .A(n1118), .B(n1120), .Y(n1123) );
XOR2X2TS U4005 ( .A(n6821), .B(n8377), .Y(mult_x_24_n1614) );
NAND2X4TS U4006 ( .A(n2917), .B(n2916), .Y(n7374) );
ADDFHX2TS U4007 ( .A(n2458), .B(n2457), .CI(n2456), .CO(n2553), .S(n2495) );
BUFX3TS U4008 ( .A(Op_MY[37]), .Y(n814) );
BUFX3TS U4009 ( .A(Op_MY[37]), .Y(n7507) );
INVX8TS U4010 ( .A(n1203), .Y(n6735) );
AOI21X4TS U4011 ( .A0(n5987), .A1(n787), .B0(n3752), .Y(n3753) );
OAI21X4TS U4012 ( .A0(n7355), .A1(n7363), .B0(n7364), .Y(n2930) );
AOI21X2TS U4013 ( .A0(n4959), .A1(n4963), .B0(n4926), .Y(n4927) );
NAND2X2TS U4014 ( .A(n5458), .B(n5464), .Y(n3841) );
NAND2X2TS U4015 ( .A(n4863), .B(n1028), .Y(n4868) );
OAI21X4TS U4016 ( .A0(n4912), .A1(n5281), .B0(n4913), .Y(n3764) );
NOR2X4TS U4017 ( .A(n1591), .B(n1590), .Y(n7226) );
BUFX20TS U4018 ( .A(n2936), .Y(n891) );
ADDFHX4TS U4019 ( .A(n3316), .B(n3315), .CI(n3314), .CO(n3519), .S(n3517) );
ADDFHX2TS U4020 ( .A(n2326), .B(n2325), .CI(n2324), .CO(n2467), .S(n2327) );
NOR2X4TS U4021 ( .A(n2912), .B(n2911), .Y(n7368) );
ADDFHX2TS U4022 ( .A(n3147), .B(n3146), .CI(n3145), .CO(n3560), .S(n3557) );
ADDFHX2TS U4023 ( .A(n1937), .B(n1936), .CI(n1935), .CO(n1938), .S(n1737) );
OAI21X4TS U4024 ( .A0(n924), .A1(n3905), .B0(n3904), .Y(n3907) );
CMPR42X2TS U4025 ( .A(mult_x_24_n1445), .B(mult_x_24_n1580), .C(
mult_x_24_n1526), .D(mult_x_24_n1499), .ICI(mult_x_24_n849), .S(
mult_x_24_n839), .ICO(mult_x_24_n837), .CO(mult_x_24_n838) );
XNOR2X2TS U4026 ( .A(n859), .B(n1518), .Y(n1529) );
ADDFHX2TS U4027 ( .A(n1861), .B(n1860), .CI(n1859), .CO(n1854), .S(n1930) );
XNOR2X2TS U4028 ( .A(n3285), .B(n2583), .Y(n1814) );
ADDFHX4TS U4029 ( .A(n3499), .B(n3498), .CI(n3497), .CO(n3526), .S(n3521) );
ADDFHX2TS U4030 ( .A(n3375), .B(n3374), .CI(n3373), .CO(n3497), .S(n3317) );
AOI21X1TS U4031 ( .A0(n7156), .A1(n7393), .B0(n7233), .Y(n7236) );
XOR2X4TS U4032 ( .A(n1400), .B(n1399), .Y(n2018) );
ADDFHX4TS U4033 ( .A(n3265), .B(n3264), .CI(n3263), .CO(n3518), .S(n3516) );
CMPR42X2TS U4034 ( .A(n6934), .B(mult_x_24_n1105), .C(mult_x_24_n1473), .D(
mult_x_24_n1446), .ICI(mult_x_24_n1419), .S(mult_x_24_n854), .ICO(
mult_x_24_n852), .CO(mult_x_24_n853) );
ADDFHX4TS U4035 ( .A(n2691), .B(n2690), .CI(n2689), .CO(n2922), .S(n2919) );
OAI21X1TS U4036 ( .A0(n7075), .A1(n6992), .B0(n6640), .Y(n6641) );
AOI21X4TS U4037 ( .A0(n5121), .A1(n5120), .B0(n5119), .Y(n5141) );
NOR2X4TS U4038 ( .A(Op_MX[17]), .B(n6829), .Y(n6310) );
XNOR2X4TS U4039 ( .A(n2685), .B(n2688), .Y(n2678) );
ADDFHX4TS U4040 ( .A(n2671), .B(n2670), .CI(n2669), .CO(n2685), .S(n2680) );
ADDFHX2TS U4041 ( .A(n2435), .B(n2434), .CI(n2433), .CO(n2443), .S(n2427) );
XNOR2X2TS U4042 ( .A(n1397), .B(n1398), .Y(n1518) );
BUFX3TS U4043 ( .A(Op_MY[31]), .Y(n8376) );
INVX2TS U4044 ( .A(n801), .Y(n830) );
INVX2TS U4045 ( .A(n782), .Y(n831) );
INVX2TS U4046 ( .A(n782), .Y(n832) );
BUFX3TS U4047 ( .A(n5840), .Y(n5845) );
BUFX3TS U4048 ( .A(n5840), .Y(n6033) );
INVX2TS U4049 ( .A(n802), .Y(n837) );
INVX2TS U4050 ( .A(n802), .Y(n838) );
INVX2TS U4051 ( .A(n804), .Y(n839) );
INVX2TS U4052 ( .A(n804), .Y(n840) );
INVX2TS U4053 ( .A(n770), .Y(n841) );
INVX2TS U4054 ( .A(n770), .Y(n842) );
INVX2TS U4055 ( .A(FSM_selector_A), .Y(n845) );
INVX2TS U4056 ( .A(n845), .Y(n846) );
INVX2TS U4057 ( .A(n798), .Y(n849) );
OAI21X2TS U4058 ( .A0(n819), .A1(n2004), .B0(n2003), .Y(n2007) );
OAI21X2TS U4059 ( .A0(n817), .A1(n2238), .B0(n2247), .Y(n1978) );
OAI21X2TS U4060 ( .A0(n819), .A1(n1777), .B0(n1779), .Y(n1771) );
OAI21X2TS U4061 ( .A0(n817), .A1(n1960), .B0(n1959), .Y(n1963) );
OAI21X2TS U4062 ( .A0(n740), .A1(n6414), .B0(n6415), .Y(n6337) );
OAI21X2TS U4063 ( .A0(n740), .A1(n6259), .B0(n6258), .Y(n6264) );
OAI21X2TS U4064 ( .A0(n820), .A1(n6313), .B0(n6312), .Y(n6318) );
OAI21X2TS U4065 ( .A0(n740), .A1(n6394), .B0(n6393), .Y(n6399) );
OAI21X2TS U4066 ( .A0(n740), .A1(n6286), .B0(n6285), .Y(n6291) );
OAI21X2TS U4067 ( .A0(n740), .A1(n6280), .B0(n6281), .Y(n1218) );
XNOR2X2TS U4068 ( .A(n853), .B(n2771), .Y(n2810) );
XNOR2X2TS U4069 ( .A(n853), .B(n2939), .Y(n2951) );
INVX4TS U4070 ( .A(n854), .Y(n855) );
INVX8TS U4071 ( .A(n2534), .Y(n859) );
XNOR2X2TS U4072 ( .A(n858), .B(n1747), .Y(n1748) );
INVX4TS U4073 ( .A(n866), .Y(n867) );
INVX4TS U4074 ( .A(n869), .Y(n870) );
INVX2TS U4075 ( .A(n869), .Y(n871) );
BUFX3TS U4076 ( .A(n6930), .Y(n874) );
AOI222X4TS U4077 ( .A0(n6736), .A1(n6814), .B0(n7070), .B1(n6846), .C0(n6405), .C1(n6930), .Y(n6403) );
BUFX3TS U4078 ( .A(n7068), .Y(n875) );
NOR2X2TS U4079 ( .A(n827), .B(n7068), .Y(n6349) );
NAND2X2TS U4080 ( .A(n7068), .B(n7056), .Y(n6354) );
NAND2X2TS U4081 ( .A(n827), .B(n7068), .Y(n6363) );
CLKBUFX2TS U4082 ( .A(Op_MX[20]), .Y(n878) );
CLKBUFX2TS U4083 ( .A(Op_MX[20]), .Y(n879) );
NAND2X2TS U4084 ( .A(n876), .B(n6930), .Y(n6295) );
NAND2X2TS U4085 ( .A(n876), .B(n6952), .Y(n6301) );
AOI222X1TS U4086 ( .A0(n6817), .A1(n879), .B0(n887), .B1(n6830), .C0(n6813),
.C1(n8403), .Y(n1220) );
NOR2X2TS U4087 ( .A(n876), .B(n6930), .Y(n3812) );
BUFX3TS U4088 ( .A(n7011), .Y(n883) );
NOR2X6TS U4089 ( .A(n4737), .B(n4736), .Y(n7011) );
BUFX6TS U4090 ( .A(n7011), .Y(n6870) );
INVX2TS U4091 ( .A(n811), .Y(n885) );
CLKINVX6TS U4092 ( .A(n6815), .Y(n886) );
NAND2X2TS U4093 ( .A(n886), .B(n5041), .Y(n962) );
OAI21X2TS U4094 ( .A0(n891), .A1(n3596), .B0(n3595), .Y(n3600) );
OAI21X2TS U4095 ( .A0(n7430), .A1(n7409), .B0(n7408), .Y(n7414) );
OAI21X2TS U4096 ( .A0(n7430), .A1(n7238), .B0(n7237), .Y(n7243) );
OAI21X2TS U4097 ( .A0(n7430), .A1(n1023), .B0(n7274), .Y(n7277) );
OAI21X2TS U4098 ( .A0(n7430), .A1(n7338), .B0(n7337), .Y(n7342) );
NOR2X4TS U4099 ( .A(n7547), .B(FSM_selector_C), .Y(n8069) );
INVX2TS U4100 ( .A(n783), .Y(n892) );
INVX2TS U4101 ( .A(n783), .Y(n893) );
BUFX3TS U4102 ( .A(n7471), .Y(n8535) );
NAND2X1TS U4103 ( .A(n5395), .B(n5396), .Y(n5393) );
NOR2X2TS U4104 ( .A(n3714), .B(n3713), .Y(n5809) );
BUFX4TS U4105 ( .A(n6620), .Y(n6887) );
INVX2TS U4106 ( .A(n6974), .Y(n8378) );
NOR4X1TS U4107 ( .A(Op_MX[25]), .B(Op_MX[1]), .C(Op_MX[38]), .D(n8404), .Y(
n8405) );
INVX2TS U4108 ( .A(n767), .Y(n8404) );
AOI222X1TS U4109 ( .A0(n5748), .A1(n5796), .B0(n5712), .B1(n5982), .C0(n5751), .C1(n814), .Y(n5746) );
AOI222X1TS U4110 ( .A0(n5748), .A1(n6024), .B0(n5759), .B1(n840), .C0(n5732),
.C1(n5966), .Y(n5733) );
BUFX3TS U4111 ( .A(Op_MX[18]), .Y(n927) );
INVX2TS U4112 ( .A(n735), .Y(n8373) );
ADDFHX2TS U4113 ( .A(n5055), .B(n5054), .CI(n5053), .CO(mult_x_24_n1039),
.S(mult_x_24_n1040) );
CLKINVX3TS U4114 ( .A(n1013), .Y(n8391) );
NOR2X4TS U4115 ( .A(FS_Module_state_reg[3]), .B(n8369), .Y(n8430) );
INVX2TS U4116 ( .A(n1154), .Y(n963) );
CLKXOR2X2TS U4117 ( .A(n1153), .B(n8391), .Y(n1154) );
NOR3XLTS U4118 ( .A(Op_MX[34]), .B(Op_MX[53]), .C(Op_MX[52]), .Y(n8419) );
INVX4TS U4119 ( .A(n8365), .Y(n7502) );
INVX4TS U4120 ( .A(n8372), .Y(n7509) );
INVX4TS U4121 ( .A(n8365), .Y(n7497) );
INVX4TS U4122 ( .A(n8365), .Y(n7501) );
INVX4TS U4123 ( .A(n8365), .Y(n7499) );
AOI21X2TS U4124 ( .A0(n7325), .A1(n3594), .B0(n3593), .Y(n3595) );
AOI21X2TS U4125 ( .A0(n7325), .A1(n7297), .B0(n7296), .Y(n7298) );
AOI222X1TS U4126 ( .A0(n5748), .A1(n5871), .B0(n5745), .B1(n5870), .C0(n5732), .C1(n6080), .Y(n5724) );
BUFX4TS U4127 ( .A(n3179), .Y(n2730) );
XNOR2X2TS U4128 ( .A(n3359), .B(n2997), .Y(n2816) );
BUFX16TS U4129 ( .A(n1706), .Y(n3359) );
XNOR2X1TS U4130 ( .A(n3334), .B(n3383), .Y(n3385) );
INVX4TS U4131 ( .A(n3334), .Y(n3053) );
INVX8TS U4132 ( .A(n2474), .Y(n3281) );
CLKINVX12TS U4133 ( .A(n3281), .Y(n900) );
XNOR2X1TS U4134 ( .A(n901), .B(n1979), .Y(n2030) );
XNOR2X1TS U4135 ( .A(n901), .B(n1872), .Y(n1873) );
XNOR2X1TS U4136 ( .A(n900), .B(n2871), .Y(n2872) );
INVX2TS U4137 ( .A(n901), .Y(n3282) );
INVX4TS U4138 ( .A(n797), .Y(n902) );
INVX2TS U4139 ( .A(n797), .Y(n903) );
XNOR2X1TS U4140 ( .A(n908), .B(n2997), .Y(n2277) );
INVX2TS U4141 ( .A(n853), .Y(n3584) );
XNOR2X1TS U4142 ( .A(n3582), .B(n3343), .Y(n3429) );
XNOR2X2TS U4143 ( .A(n853), .B(n2881), .Y(n3180) );
XNOR2X2TS U4144 ( .A(n909), .B(n3167), .Y(n3105) );
XNOR2X2TS U4145 ( .A(n909), .B(n3383), .Y(n3045) );
XNOR2X1TS U4146 ( .A(n3368), .B(n2518), .Y(n2562) );
XNOR2X1TS U4147 ( .A(n917), .B(n2221), .Y(n3366) );
INVX2TS U4148 ( .A(n917), .Y(n2953) );
XNOR2X1TS U4149 ( .A(n919), .B(n3383), .Y(n2969) );
INVX2TS U4150 ( .A(n922), .Y(n3033) );
BUFX6TS U4151 ( .A(n5494), .Y(n923) );
AOI222X1TS U4152 ( .A0(n5840), .A1(n6055), .B0(n5494), .B1(n5839), .C0(n5844), .C1(n5213), .Y(n4662) );
INVX16TS U4153 ( .A(n3772), .Y(n924) );
OAI21X2TS U4154 ( .A0(n924), .A1(n3780), .B0(n3779), .Y(n3781) );
OAI21X2TS U4155 ( .A0(n924), .A1(n5166), .B0(n5165), .Y(n5169) );
OAI21X2TS U4156 ( .A0(n5271), .A1(n5176), .B0(n5175), .Y(n5181) );
OAI21X2TS U4157 ( .A0(n924), .A1(n5188), .B0(n5187), .Y(n5193) );
OAI21X2TS U4158 ( .A0(n5271), .A1(n5270), .B0(n5269), .Y(n5275) );
INVX2TS U4159 ( .A(n794), .Y(n926) );
NOR2X4TS U4160 ( .A(n925), .B(n6959), .Y(n6260) );
NAND2X2TS U4161 ( .A(n925), .B(n6959), .Y(n6261) );
NOR2X2TS U4162 ( .A(n6989), .B(n925), .Y(n6248) );
NOR2X2TS U4163 ( .A(n6829), .B(n6930), .Y(n6314) );
NAND2X4TS U4164 ( .A(Op_MX[17]), .B(n6829), .Y(n6326) );
OAI22X1TS U4165 ( .A0(n2810), .A1(n2100), .B0(n2808), .B1(n2876), .Y(n2866)
);
NAND2X6TS U4166 ( .A(n2808), .B(n1404), .Y(n2877) );
NAND2BX1TS U4167 ( .AN(n2223), .B(n4730), .Y(n2220) );
OAI22X1TS U4168 ( .A0(n3218), .A1(n3376), .B0(n3284), .B1(n3360), .Y(n3297)
);
BUFX3TS U4169 ( .A(n3376), .Y(n3361) );
OAI22X1TS U4170 ( .A0(n3332), .A1(n3333), .B0(n3304), .B1(n3331), .Y(n3355)
);
OAI22X1TS U4171 ( .A0(n2231), .A1(n3089), .B0(n2211), .B1(n931), .Y(n2323)
);
OAI22X2TS U4172 ( .A0(n2083), .A1(n3089), .B0(n3331), .B1(n3107), .Y(n2213)
);
BUFX3TS U4173 ( .A(n1751), .Y(n932) );
BUFX3TS U4174 ( .A(n1751), .Y(n933) );
OAI22X1TS U4175 ( .A0(n1645), .A1(n3301), .B0(n1624), .B1(n2839), .Y(n1665)
);
OAI22X1TS U4176 ( .A0(n2062), .A1(n3427), .B0(n2061), .B1(n3428), .Y(n2104)
);
BUFX3TS U4177 ( .A(n934), .Y(n3201) );
CLKMX2X2TS U4178 ( .A(Exp_module_Overflow_flag_A), .B(n4699), .S0(n8188),
.Y(n405) );
OAI22X1TS U4179 ( .A0(n1479), .A1(n2808), .B0(n1482), .B1(n928), .Y(n1541)
);
ADDFHX2TS U4180 ( .A(n1558), .B(n1557), .CI(n1556), .CO(n1587), .S(n1559) );
NOR4X1TS U4181 ( .A(Op_MX[45]), .B(Op_MX[39]), .C(Op_MX[27]), .D(Op_MX[51]),
.Y(n8408) );
BUFX3TS U4182 ( .A(n6558), .Y(n6980) );
AOI222X1TS U4183 ( .A0(n5748), .A1(n5779), .B0(n5745), .B1(n5778), .C0(n5732), .C1(n5871), .Y(n5720) );
CLKXOR2X2TS U4184 ( .A(n3654), .B(n5819), .Y(n3691) );
CLKINVX3TS U4185 ( .A(n793), .Y(n5694) );
OAI22X2TS U4186 ( .A0(beg_FSM), .A1(n8533), .B0(ack_FSM), .B1(n7478), .Y(
n8367) );
NOR2X2TS U4187 ( .A(n5123), .B(n5122), .Y(n5143) );
XOR2X1TS U4188 ( .A(n1110), .B(n6891), .Y(n1134) );
NOR3XLTS U4189 ( .A(Op_MY[25]), .B(Op_MY[52]), .C(Op_MY[53]), .Y(n8394) );
NOR4X1TS U4190 ( .A(n8393), .B(n8392), .C(n8391), .D(Op_MY[62]), .Y(n8395)
);
CLKMX2X2TS U4191 ( .A(P_Sgf[91]), .B(n4650), .S0(n7712), .Y(n512) );
XOR2X1TS U4192 ( .A(n3785), .B(n6002), .Y(n3791) );
NAND2BX4TS U4193 ( .AN(n3638), .B(n3639), .Y(n936) );
OAI21XLTS U4194 ( .A0(n979), .A1(n5861), .B0(n5860), .Y(n5862) );
BUFX3TS U4195 ( .A(n5861), .Y(n5761) );
XOR2X4TS U4196 ( .A(Op_MX[32]), .B(Op_MX[31]), .Y(n3639) );
INVX2TS U4197 ( .A(n6945), .Y(n7059) );
INVX2TS U4198 ( .A(n7059), .Y(n937) );
INVX2TS U4199 ( .A(n7059), .Y(n938) );
INVX2TS U4200 ( .A(n7059), .Y(n939) );
AOI222X1TS U4201 ( .A0(n7023), .A1(n938), .B0(n7021), .B1(Op_MX[14]), .C0(
n7019), .C1(n7056), .Y(n6567) );
AOI222X1TS U4202 ( .A0(n7060), .A1(n937), .B0(n7058), .B1(Op_MX[14]), .C0(
n7057), .C1(n7056), .Y(n7061) );
NOR4X1TS U4203 ( .A(Op_MX[26]), .B(Op_MX[47]), .C(Op_MX[29]), .D(Op_MX[62]),
.Y(n8420) );
NOR2X4TS U4204 ( .A(n7547), .B(n8448), .Y(n8178) );
XOR2X2TS U4205 ( .A(n960), .B(n6695), .Y(n1100) );
XOR2X2TS U4206 ( .A(n1053), .B(n8377), .Y(n1089) );
INVX4TS U4207 ( .A(n8372), .Y(n7504) );
NAND2X1TS U4208 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n8108) );
CMPR42X1TS U4209 ( .A(n6934), .B(mult_x_24_n1107), .C(mult_x_24_n1448), .D(
mult_x_24_n1421), .ICI(mult_x_24_n1502), .S(mult_x_24_n878), .ICO(
mult_x_24_n876), .CO(mult_x_24_n877) );
CLKINVX3TS U4210 ( .A(n1013), .Y(n8445) );
AOI21X4TS U4211 ( .A0(n7258), .A1(n2453), .B0(n943), .Y(n2454) );
XOR2X4TS U4212 ( .A(n945), .B(n1412), .Y(n944) );
OAI21X4TS U4213 ( .A0(n1675), .A1(n1431), .B0(n1433), .Y(n945) );
OAI21X4TS U4214 ( .A0(n1373), .A1(n948), .B0(n1374), .Y(n1345) );
NOR2X8TS U4215 ( .A(n947), .B(n946), .Y(n1029) );
INVX2TS U4216 ( .A(n948), .Y(n946) );
OAI21X4TS U4217 ( .A0(n6131), .A1(n949), .B0(n954), .Y(n6105) );
AOI21X4TS U4218 ( .A0(n6140), .A1(n957), .B0(n956), .Y(n6131) );
OAI21X4TS U4219 ( .A0(n1173), .A1(n6146), .B0(n1172), .Y(n6140) );
INVX2TS U4220 ( .A(n1174), .Y(n6137) );
AOI21X4TS U4221 ( .A0(n6105), .A1(n952), .B0(n950), .Y(n6093) );
OAI21X4TS U4222 ( .A0(n6116), .A1(n953), .B0(n951), .Y(n950) );
AOI21X4TS U4223 ( .A0(n6108), .A1(n6113), .B0(n1179), .Y(n951) );
NOR2X8TS U4224 ( .A(n1178), .B(n1177), .Y(n6116) );
AOI21X4TS U4225 ( .A0(n6132), .A1(n972), .B0(n1175), .Y(n954) );
INVX2TS U4226 ( .A(n972), .Y(n955) );
XOR2X4TS U4227 ( .A(n959), .B(n2154), .Y(n2179) );
AOI2BB2X2TS U4228 ( .B0(n6817), .B1(n6822), .A0N(n6681), .A1N(n5043), .Y(
n961) );
NAND2BX4TS U4229 ( .AN(n1155), .B(n963), .Y(n6190) );
AOI21X4TS U4230 ( .A0(n2186), .A1(n964), .B0(n2185), .Y(n7133) );
NAND2X4TS U4231 ( .A(n7152), .B(n964), .Y(n7142) );
ADDFHX2TS U4232 ( .A(n2153), .B(n2152), .CI(n2151), .CO(n2162), .S(n2173) );
OAI22X1TS U4233 ( .A0(n2099), .A1(n2976), .B0(n2063), .B1(n3006), .Y(n2103)
);
CLKXOR2X2TS U4234 ( .A(n3705), .B(n3610), .Y(n3611) );
AOI21X1TS U4235 ( .A0(n7108), .A1(n7094), .B0(n6976), .Y(n6979) );
AOI222X1TS U4236 ( .A0(n6889), .A1(n6894), .B0(n6887), .B1(n938), .C0(n6885),
.C1(Op_MX[14]), .Y(n6765) );
NOR2X2TS U4237 ( .A(mult_x_23_n651), .B(mult_x_23_n655), .Y(n5167) );
AOI21X1TS U4238 ( .A0(n7436), .A1(n7435), .B0(n7258), .Y(n7441) );
XOR2X4TS U4239 ( .A(n5011), .B(n7051), .Y(n6941) );
NOR2X2TS U4240 ( .A(n4885), .B(n4868), .Y(n4870) );
BUFX16TS U4241 ( .A(n2018), .Y(n2808) );
CMPR42X2TS U4242 ( .A(mult_x_24_n1407), .B(mult_x_24_n737), .C(
mult_x_24_n738), .D(mult_x_24_n732), .ICI(mult_x_24_n734), .S(
mult_x_24_n729), .ICO(mult_x_24_n727), .CO(mult_x_24_n728) );
XNOR2X4TS U4243 ( .A(n1401), .B(n1396), .Y(n1400) );
ADDFHX2TS U4244 ( .A(n2405), .B(n2404), .CI(n2403), .CO(n2419), .S(n2430) );
AND3X4TS U4245 ( .A(n5036), .B(n5035), .C(n5034), .Y(n6615) );
OAI21X2TS U4246 ( .A0(n7026), .A1(n6841), .B0(n5037), .Y(n5038) );
NOR2BX2TS U4247 ( .AN(n1058), .B(n1057), .Y(n6686) );
ADDFHX2TS U4248 ( .A(n2556), .B(n2555), .CI(n2554), .CO(n2675), .S(n2681) );
NAND2X4TS U4249 ( .A(n1398), .B(n1397), .Y(n1399) );
CMPR42X2TS U4250 ( .A(mult_x_24_n1408), .B(mult_x_24_n744), .C(
mult_x_24_n739), .D(mult_x_24_n745), .ICI(mult_x_24_n741), .S(
mult_x_24_n736), .ICO(mult_x_24_n734), .CO(mult_x_24_n735) );
ADDFHX2TS U4251 ( .A(n2599), .B(n2598), .CI(n2597), .CO(n2644), .S(n2595) );
NAND2X4TS U4252 ( .A(Op_MY[28]), .B(Op_MY[1]), .Y(n1374) );
ADDFHX2TS U4253 ( .A(n2612), .B(n2611), .CI(n2610), .CO(n2663), .S(n2683) );
ADDFHX2TS U4254 ( .A(n2609), .B(n2608), .CI(n2607), .CO(n2642), .S(n2612) );
XNOR2X2TS U4255 ( .A(n3364), .B(n3230), .Y(n2806) );
OAI21X2TS U4256 ( .A0(n6926), .A1(n6966), .B0(n6797), .Y(n6798) );
XNOR2X2TS U4257 ( .A(n912), .B(n3346), .Y(n3347) );
OAI21X2TS U4258 ( .A0(n6778), .A1(n6966), .B0(n6777), .Y(n6779) );
NOR2X4TS U4259 ( .A(n7292), .B(n3923), .Y(n3925) );
OAI21X2TS U4260 ( .A0(n5437), .A1(n5684), .B0(n3721), .Y(n3722) );
XNOR2X2TS U4261 ( .A(n3176), .B(n3230), .Y(n2874) );
ADDFHX2TS U4262 ( .A(n2550), .B(n2549), .CI(n2548), .CO(n2677), .S(n2670) );
NAND2X4TS U4263 ( .A(mult_x_23_n698), .B(mult_x_23_n707), .Y(n4858) );
OAI22X2TS U4264 ( .A0(n728), .A1(n2976), .B0(n1802), .B1(n3006), .Y(n1815)
);
CMPR42X2TS U4265 ( .A(mult_x_23_n691), .B(mult_x_23_n1322), .C(
mult_x_23_n686), .D(mult_x_23_n692), .ICI(mult_x_23_n688), .S(
mult_x_23_n683), .ICO(mult_x_23_n681), .CO(mult_x_23_n682) );
OAI22X2TS U4266 ( .A0(n1624), .A1(n3301), .B0(n1383), .B1(n1751), .Y(n1626)
);
ADDFHX2TS U4267 ( .A(n2052), .B(n2051), .CI(n2050), .CO(n2138), .S(n2149) );
OAI22X2TS U4268 ( .A0(n1384), .A1(n3301), .B0(n1751), .B1(n3367), .Y(n1422)
);
XNOR2X2TS U4269 ( .A(n859), .B(n3227), .Y(n1383) );
NAND2X4TS U4270 ( .A(n6334), .B(n6415), .Y(n6323) );
OAI22X2TS U4271 ( .A0(n1993), .A1(n3031), .B0(n1883), .B1(n3415), .Y(n1995)
);
CMPR42X2TS U4272 ( .A(mult_x_23_n727), .B(mult_x_23_n723), .C(mult_x_23_n728), .D(mult_x_23_n721), .ICI(mult_x_23_n724), .S(mult_x_23_n718), .ICO(
mult_x_23_n716), .CO(mult_x_23_n717) );
OAI21X2TS U4273 ( .A0(Op_MX[22]), .A1(Op_MX[49]), .B0(Op_MX[21]), .Y(n2073)
);
NAND2X4TS U4274 ( .A(n6261), .B(n6272), .Y(n6244) );
NAND2X4TS U4275 ( .A(n6354), .B(n6363), .Y(n6423) );
NAND2X4TS U4276 ( .A(n6301), .B(n6295), .Y(n6390) );
NAND2X2TS U4277 ( .A(n848), .B(n852), .Y(n3658) );
XNOR2X4TS U4278 ( .A(Op_MX[43]), .B(Op_MX[42]), .Y(n1795) );
CLKXOR2X4TS U4279 ( .A(Op_MX[50]), .B(Op_MX[51]), .Y(n2205) );
XOR2X4TS U4280 ( .A(n7492), .B(Op_MX[34]), .Y(n3720) );
XNOR2X4TS U4281 ( .A(Op_MX[31]), .B(Op_MX[30]), .Y(n3637) );
XOR2X4TS U4282 ( .A(Op_MX[41]), .B(Op_MX[40]), .Y(n4655) );
XOR2X4TS U4283 ( .A(Op_MX[47]), .B(Op_MX[46]), .Y(n3626) );
CLKBUFX2TS U4284 ( .A(n1616), .Y(n2214) );
OR2X1TS U4285 ( .A(n6897), .B(n6243), .Y(n975) );
XNOR2X4TS U4286 ( .A(n4999), .B(n3726), .Y(n979) );
AOI22X1TS U4287 ( .A0(n6921), .A1(n5041), .B0(n6923), .B1(n6822), .Y(n981)
);
OR2X1TS U4288 ( .A(n4230), .B(Sgf_operation_ODD1_Q_right[28]), .Y(n986) );
OR2X1TS U4289 ( .A(n4256), .B(Sgf_operation_ODD1_Q_right[33]), .Y(n990) );
AOI22X1TS U4290 ( .A0(n6440), .A1(n5041), .B0(n6736), .B1(n6243), .Y(n994)
);
NAND2X1TS U4291 ( .A(n1112), .B(n825), .Y(n995) );
NAND2X1TS U4292 ( .A(n3717), .B(n824), .Y(n997) );
XNOR2X2TS U4293 ( .A(n1082), .B(n8391), .Y(n998) );
CLKBUFX2TS U4294 ( .A(Op_MY[0]), .Y(n8386) );
CLKXOR2X4TS U4295 ( .A(n3603), .B(n3602), .Y(n1001) );
AND2X2TS U4296 ( .A(n4832), .B(n4831), .Y(n1004) );
INVX2TS U4297 ( .A(Op_MX[0]), .Y(n1038) );
CLKBUFX2TS U4298 ( .A(Op_MX[2]), .Y(n8402) );
BUFX6TS U4299 ( .A(Op_MX[6]), .Y(n8414) );
CLKBUFX2TS U4300 ( .A(Op_MY[26]), .Y(n8393) );
INVX2TS U4301 ( .A(n1018), .Y(n6220) );
AND2X2TS U4302 ( .A(n2284), .B(n8393), .Y(n1030) );
OR2X4TS U4303 ( .A(FSM_selector_B[1]), .B(n8450), .Y(n1037) );
OAI21X2TS U4304 ( .A0(n2241), .A1(n2240), .B0(n2239), .Y(n2242) );
INVX2TS U4305 ( .A(n3813), .Y(n4730) );
NOR2X2TS U4306 ( .A(n6421), .B(n6425), .Y(n6428) );
NOR2X2TS U4307 ( .A(n3848), .B(n3846), .Y(n1256) );
NAND2X1TS U4308 ( .A(n4433), .B(n4438), .Y(n4441) );
INVX2TS U4309 ( .A(n2577), .Y(n2825) );
NOR2X1TS U4310 ( .A(n2581), .B(n3583), .Y(n2631) );
NAND2X1TS U4311 ( .A(n6268), .B(n6273), .Y(n6259) );
XNOR2X1TS U4312 ( .A(n3330), .B(n3230), .Y(n3288) );
INVX2TS U4313 ( .A(Sgf_operation_Result[2]), .Y(n4009) );
INVX2TS U4314 ( .A(Sgf_operation_Result[9]), .Y(n4041) );
INVX4TS U4315 ( .A(n3005), .Y(n3348) );
XNOR2X1TS U4316 ( .A(n3176), .B(n3363), .Y(n3423) );
OAI22X1TS U4317 ( .A0(n2475), .A1(n3031), .B0(n2312), .B1(n3415), .Y(n2516)
);
BUFX3TS U4318 ( .A(n2563), .Y(n3290) );
NAND2X1TS U4319 ( .A(n6250), .B(n6249), .Y(n6251) );
BUFX4TS U4320 ( .A(n6982), .Y(n6581) );
AOI22X1TS U4321 ( .A0(n5922), .A1(n903), .B0(n4672), .B1(n4966), .Y(n4673)
);
XNOR2X1TS U4322 ( .A(n4007), .B(Sgf_operation_ODD1_Q_middle[1]), .Y(n4006)
);
OAI22X1TS U4323 ( .A0(n3362), .A1(n3361), .B0(n3377), .B1(n3360), .Y(n3436)
);
BUFX3TS U4324 ( .A(n2694), .Y(n3411) );
OAI22X1TS U4325 ( .A0(n3168), .A1(n930), .B0(n3218), .B1(n3360), .Y(n3253)
);
OAI22X1TS U4326 ( .A0(n2031), .A1(n3301), .B0(n1908), .B1(n2839), .Y(n2052)
);
BUFX4TS U4327 ( .A(n6639), .Y(n6885) );
NAND2X1TS U4328 ( .A(n5603), .B(n5602), .Y(n5604) );
INVX2TS U4329 ( .A(n4266), .Y(n4268) );
INVX2TS U4330 ( .A(n4324), .Y(n4371) );
INVX2TS U4331 ( .A(n4187), .Y(n4184) );
INVX2TS U4332 ( .A(n4433), .Y(n4125) );
OAI21X2TS U4333 ( .A0(n4581), .A1(n4592), .B0(n4582), .Y(n4481) );
INVX2TS U4334 ( .A(n4519), .Y(n4506) );
OAI22X1TS U4335 ( .A0(n1426), .A1(n3178), .B0(n1430), .B1(n3222), .Y(n1469)
);
BUFX3TS U4336 ( .A(n4805), .Y(n7074) );
ADDHX1TS U4337 ( .A(n7494), .B(n4714), .CO(n5073), .S(n5137) );
OAI21X2TS U4338 ( .A0(n6999), .A1(n764), .B0(n5010), .Y(n5011) );
OAI21X2TS U4339 ( .A0(n5792), .A1(n5886), .B0(n5516), .Y(n5517) );
NAND2X1TS U4340 ( .A(n3659), .B(n3658), .Y(n3660) );
INVX2TS U4341 ( .A(n7418), .Y(n7421) );
INVX2TS U4342 ( .A(n4346), .Y(n4343) );
AOI21X1TS U4343 ( .A0(n4113), .A1(n4112), .B0(n4111), .Y(n4119) );
XOR2X1TS U4344 ( .A(n3798), .B(n5663), .Y(n5933) );
XNOR2X2TS U4345 ( .A(n4193), .B(n4192), .Y(n4404) );
XOR2X1TS U4346 ( .A(n4126), .B(n4110), .Y(n4419) );
XOR3X1TS U4347 ( .A(n3813), .B(n3586), .C(n3585), .Y(n3587) );
ADDFX2TS U4348 ( .A(n7055), .B(n7054), .CI(n7053), .CO(mult_x_24_n1032), .S(
mult_x_24_n1033) );
XOR2X1TS U4349 ( .A(n1079), .B(n6820), .Y(n1137) );
OAI21X1TS U4350 ( .A0(FSM_selector_B[0]), .A1(n5254), .B0(n1037), .Y(n5255)
);
NAND2X1TS U4351 ( .A(n4285), .B(Sgf_operation_ODD1_Q_right[34]), .Y(n8230)
);
INVX2TS U4352 ( .A(n8283), .Y(n8285) );
INVX2TS U4353 ( .A(n8334), .Y(n8336) );
INVX2TS U4354 ( .A(n8162), .Y(n8164) );
INVX2TS U4355 ( .A(n8033), .Y(n8035) );
NAND2X1TS U4356 ( .A(n4613), .B(Sgf_operation_ODD1_Q_left[18]), .Y(n7905) );
INVX2TS U4357 ( .A(n7835), .Y(n7837) );
INVX2TS U4358 ( .A(n7780), .Y(n7782) );
OAI21XLTS U4359 ( .A0(n8139), .A1(n8149), .B0(n8150), .Y(n8144) );
INVX2TS U4360 ( .A(n7918), .Y(n7933) );
NOR2X2TS U4361 ( .A(n7674), .B(n7673), .Y(n4648) );
XOR2X1TS U4362 ( .A(n7674), .B(n7673), .Y(n7675) );
INVX2TS U4363 ( .A(n1032), .Y(n7491) );
NAND2X1TS U4364 ( .A(n7223), .B(n7222), .Y(n7224) );
AOI21X1TS U4365 ( .A0(n6163), .A1(n6148), .B0(n6147), .Y(n6152) );
OAI21XLTS U4366 ( .A0(n5383), .A1(n5380), .B0(n5381), .Y(n5379) );
NAND2BX2TS U4367 ( .AN(n999), .B(n1048), .Y(n1080) );
NAND2X1TS U4368 ( .A(n884), .B(n825), .Y(n1039) );
INVX2TS U4369 ( .A(n1073), .Y(n1041) );
AOI21X4TS U4370 ( .A0(n1000), .A1(n1041), .B0(n1040), .Y(n1124) );
NOR2X4TS U4371 ( .A(n6584), .B(n6863), .Y(n1062) );
INVX2TS U4372 ( .A(n1062), .Y(n1094) );
INVX2TS U4373 ( .A(n1093), .Y(n1042) );
AOI21X2TS U4374 ( .A0(n1096), .A1(n1094), .B0(n1042), .Y(n1045) );
INVX2TS U4375 ( .A(n1063), .Y(n1043) );
BUFX3TS U4376 ( .A(n1080), .Y(n6729) );
BUFX3TS U4377 ( .A(Op_MX[5]), .Y(n7046) );
NOR2BX4TS U4378 ( .AN(n999), .B(n1005), .Y(n1083) );
BUFX3TS U4379 ( .A(n1083), .Y(n6916) );
BUFX3TS U4380 ( .A(Op_MX[4]), .Y(n7044) );
BUFX3TS U4381 ( .A(n6584), .Y(n7042) );
AOI222X1TS U4382 ( .A0(n1047), .A1(n7046), .B0(n6916), .B1(n7044), .C0(n6893), .C1(n7042), .Y(n1049) );
OAI21X1TS U4383 ( .A0(n7050), .A1(n6729), .B0(n1049), .Y(n1050) );
INVX2TS U4384 ( .A(n1013), .Y(n6730) );
OR2X2TS U4385 ( .A(n905), .B(n825), .Y(n1051) );
NAND2X4TS U4386 ( .A(n1051), .B(n1073), .Y(n5043) );
XNOR2X4TS U4387 ( .A(n6934), .B(Op_MY[3]), .Y(n1058) );
INVX4TS U4388 ( .A(n1038), .Y(n5041) );
NOR2X4TS U4389 ( .A(n1059), .B(n1058), .Y(n1056) );
BUFX4TS U4390 ( .A(n1056), .Y(n6817) );
BUFX3TS U4391 ( .A(n6243), .Y(n6822) );
INVX2TS U4392 ( .A(n730), .Y(n6695) );
NAND2X1TS U4393 ( .A(n1056), .B(n825), .Y(n1052) );
NAND2X2TS U4394 ( .A(n975), .B(n1074), .Y(n1054) );
INVX6TS U4395 ( .A(n1055), .Y(n7026) );
BUFX3TS U4396 ( .A(Op_MX[2]), .Y(n6884) );
BUFX3TS U4397 ( .A(n6243), .Y(n7020) );
AOI222X2TS U4398 ( .A0(n6683), .A1(n6884), .B0(n886), .B1(n7020), .C0(n822),
.C1(n7018), .Y(n1060) );
NOR2X2TS U4399 ( .A(n1104), .B(n1103), .Y(n6199) );
INVX2TS U4400 ( .A(n1144), .Y(n1065) );
NAND2X1TS U4401 ( .A(n1065), .B(n1143), .Y(n1066) );
XOR2X2TS U4402 ( .A(n1145), .B(n1066), .Y(n1067) );
BUFX3TS U4403 ( .A(n8414), .Y(n7031) );
BUFX3TS U4404 ( .A(n1083), .Y(n6727) );
BUFX3TS U4405 ( .A(Op_MX[5]), .Y(n6859) );
BUFX3TS U4406 ( .A(n6863), .Y(n6888) );
AOI222X1TS U4407 ( .A0(n1047), .A1(n7031), .B0(n6727), .B1(n6859), .C0(n6893), .C1(n6888), .Y(n1068) );
OAI21X1TS U4408 ( .A0(n6865), .A1(n6729), .B0(n1068), .Y(n1069) );
XOR2X1TS U4409 ( .A(n1069), .B(n8445), .Y(n1106) );
XNOR2X4TS U4410 ( .A(Op_MY[6]), .B(Op_MY[5]), .Y(n1114) );
XOR2X4TS U4411 ( .A(Op_MY[7]), .B(n7040), .Y(n1115) );
NOR2X4TS U4412 ( .A(n1115), .B(n1114), .Y(n1112) );
AND2X4TS U4413 ( .A(n1072), .B(n1071), .Y(n1138) );
NAND2X1TS U4414 ( .A(n1074), .B(n1073), .Y(n1077) );
XOR2X4TS U4415 ( .A(n1077), .B(n1076), .Y(n6824) );
BUFX3TS U4416 ( .A(n8402), .Y(n7022) );
OAI21X1TS U4417 ( .A0(n6824), .A1(n6681), .B0(n1078), .Y(n1079) );
NOR2X2TS U4418 ( .A(n1106), .B(n1105), .Y(n6194) );
NOR2X2TS U4419 ( .A(n6199), .B(n6194), .Y(n1108) );
BUFX3TS U4420 ( .A(n1080), .Y(n6932) );
AOI222X1TS U4421 ( .A0(n885), .A1(n6884), .B0(n6916), .B1(n7020), .C0(n6893),
.C1(n7018), .Y(n1081) );
OAI21X1TS U4422 ( .A0(n7026), .A1(n6932), .B0(n1081), .Y(n1082) );
AOI22X1TS U4423 ( .A0(n884), .A1(n6243), .B0(n6727), .B1(n7018), .Y(n1084)
);
OAI21X1TS U4424 ( .A0(n5043), .A1(n6932), .B0(n1084), .Y(n1085) );
XOR2X1TS U4425 ( .A(n1085), .B(n6934), .Y(n6213) );
INVX2TS U4426 ( .A(Sgf_operation_ODD1_right_N0), .Y(n1086) );
AND2X2TS U4427 ( .A(n1086), .B(n8445), .Y(n6214) );
NOR2X4TS U4428 ( .A(n998), .B(n6212), .Y(n6210) );
AOI222X1TS U4429 ( .A0(n884), .A1(n7042), .B0(n6916), .B1(n7022), .C0(n6893),
.C1(n6822), .Y(n1087) );
OAI21X1TS U4430 ( .A0(n6824), .A1(n6932), .B0(n1087), .Y(n1088) );
XOR2X1TS U4431 ( .A(n1088), .B(n6730), .Y(n1091) );
NAND2X1TS U4432 ( .A(n1091), .B(n1090), .Y(n6209) );
INVX2TS U4433 ( .A(n6209), .Y(n1092) );
AOI21X4TS U4434 ( .A0(n6210), .A1(n1014), .B0(n1092), .Y(n6208) );
BUFX3TS U4435 ( .A(Op_MX[3]), .Y(n6886) );
AOI222X1TS U4436 ( .A0(n884), .A1(n6888), .B0(n6916), .B1(n6886), .C0(n6893),
.C1(n6884), .Y(n1097) );
OAI21X1TS U4437 ( .A0(n6900), .A1(n6729), .B0(n1097), .Y(n1098) );
XOR2X1TS U4438 ( .A(n1098), .B(n8445), .Y(n1102) );
NOR2X1TS U4439 ( .A(n1102), .B(n1101), .Y(n6204) );
NAND2X1TS U4440 ( .A(n1102), .B(n1101), .Y(n6205) );
OAI21X4TS U4441 ( .A0(n6208), .A1(n6204), .B0(n6205), .Y(n6193) );
NAND2X1TS U4442 ( .A(n1104), .B(n1103), .Y(n6200) );
NAND2X1TS U4443 ( .A(n1106), .B(n1105), .Y(n6195) );
AOI21X4TS U4444 ( .A0(n1108), .A1(n6193), .B0(n1107), .Y(n6183) );
XNOR2X2TS U4445 ( .A(Op_MY[6]), .B(Op_MY[7]), .Y(n1113) );
AOI22X1TS U4446 ( .A0(n6620), .A1(n5041), .B0(n6750), .B1(n6822), .Y(n1109)
);
OAI21X1TS U4447 ( .A0(n5043), .A1(n6992), .B0(n1109), .Y(n1110) );
ADDHX1TS U4448 ( .A(n7040), .B(n1111), .CO(n1133), .S(n1139) );
AND3X4TS U4449 ( .A(n1115), .B(n1114), .C(n1113), .Y(n6639) );
AOI222X1TS U4450 ( .A0(n6889), .A1(n6884), .B0(n6887), .B1(n7020), .C0(n6885), .C1(n7018), .Y(n1116) );
OAI21X1TS U4451 ( .A0(n7026), .A1(n6992), .B0(n1116), .Y(n1117) );
XOR2X1TS U4452 ( .A(n1117), .B(n6891), .Y(n4727) );
AOI21X4TS U4453 ( .A0(n1121), .A1(n1120), .B0(n1119), .Y(n1122) );
OAI21X4TS U4454 ( .A0(n1124), .A1(n1123), .B0(n1122), .Y(n1214) );
INVX2TS U4455 ( .A(n6231), .Y(n1125) );
XOR2X4TS U4456 ( .A(n6461), .B(n1126), .Y(n1127) );
BUFX3TS U4457 ( .A(Op_MX[8]), .Y(n8413) );
BUFX3TS U4458 ( .A(n8413), .Y(n7035) );
CLKBUFX2TS U4459 ( .A(Op_MX[7]), .Y(n6780) );
BUFX3TS U4460 ( .A(n6780), .Y(n7033) );
BUFX6TS U4461 ( .A(n6893), .Y(n6914) );
AOI222X1TS U4462 ( .A0(n1047), .A1(n7035), .B0(n6727), .B1(n7033), .C0(n6914), .C1(n7031), .Y(n1128) );
OAI21X1TS U4463 ( .A0(n7039), .A1(n6729), .B0(n1128), .Y(n1129) );
XOR2X1TS U4464 ( .A(n1129), .B(n6934), .Y(n1162) );
AOI222X1TS U4465 ( .A0(n6905), .A1(n7046), .B0(n6903), .B1(n7044), .C0(n823),
.C1(n7042), .Y(n1131) );
OAI21X1TS U4466 ( .A0(n7050), .A1(n6907), .B0(n1131), .Y(n1132) );
XOR2X1TS U4467 ( .A(n1132), .B(n940), .Y(n1161) );
OAI21X1TS U4468 ( .A0(n6900), .A1(n6907), .B0(n1135), .Y(n1136) );
XOR2X1TS U4469 ( .A(n1136), .B(n6695), .Y(n1141) );
ADDFHX2TS U4470 ( .A(n1139), .B(n1138), .CI(n1137), .CO(n1140), .S(n1105) );
OR2X4TS U4471 ( .A(n1157), .B(n1156), .Y(n6186) );
INVX2TS U4472 ( .A(n1146), .Y(n1148) );
BUFX3TS U4473 ( .A(n6780), .Y(n6909) );
CLKBUFX2TS U4474 ( .A(n8414), .Y(n6875) );
BUFX3TS U4475 ( .A(n6875), .Y(n6868) );
AOI222X1TS U4476 ( .A0(n1047), .A1(n6909), .B0(n6727), .B1(n6868), .C0(n6893), .C1(n7046), .Y(n1152) );
OAI21X1TS U4477 ( .A0(n6879), .A1(n6729), .B0(n1152), .Y(n1153) );
NAND2X2TS U4478 ( .A(n6186), .B(n6190), .Y(n1160) );
NAND2X2TS U4479 ( .A(n1157), .B(n1156), .Y(n6185) );
INVX2TS U4480 ( .A(n6185), .Y(n1158) );
AOI21X4TS U4481 ( .A0(n6186), .A1(n6184), .B0(n1158), .Y(n1159) );
OAI21X4TS U4482 ( .A0(n6183), .A1(n1160), .B0(n1159), .Y(n6181) );
OR2X2TS U4483 ( .A(mult_x_24_n1062), .B(n1164), .Y(n6180) );
NAND2X2TS U4484 ( .A(mult_x_24_n1062), .B(n1164), .Y(n6179) );
INVX2TS U4485 ( .A(n6179), .Y(n1165) );
AOI21X4TS U4486 ( .A0(n6181), .A1(n6180), .B0(n1165), .Y(n6170) );
OR2X4TS U4487 ( .A(mult_x_24_n1052), .B(mult_x_24_n1056), .Y(n6173) );
NAND2X2TS U4488 ( .A(n6173), .B(n779), .Y(n1168) );
NAND2X2TS U4489 ( .A(mult_x_24_n1052), .B(mult_x_24_n1056), .Y(n6172) );
INVX2TS U4490 ( .A(n6172), .Y(n1166) );
OAI21X4TS U4491 ( .A0(n6170), .A1(n1168), .B0(n1167), .Y(n6164) );
NOR2X4TS U4492 ( .A(mult_x_24_n1038), .B(mult_x_24_n1044), .Y(n6165) );
NOR2X4TS U4493 ( .A(mult_x_24_n1045), .B(mult_x_24_n1051), .Y(n6953) );
NOR2X2TS U4494 ( .A(n6165), .B(n6953), .Y(n1170) );
NAND2X2TS U4495 ( .A(mult_x_24_n1045), .B(mult_x_24_n1051), .Y(n6954) );
NAND2X2TS U4496 ( .A(mult_x_24_n1038), .B(mult_x_24_n1044), .Y(n6166) );
OAI21X2TS U4497 ( .A0(n6165), .A1(n6954), .B0(n6166), .Y(n1169) );
AOI21X4TS U4498 ( .A0(n6164), .A1(n1170), .B0(n1169), .Y(n6146) );
NOR2X2TS U4499 ( .A(mult_x_24_n1031), .B(mult_x_24_n1037), .Y(n6153) );
NAND2X2TS U4500 ( .A(n6148), .B(n6150), .Y(n1173) );
NAND2X2TS U4501 ( .A(mult_x_24_n1031), .B(mult_x_24_n1037), .Y(n6160) );
NAND2X2TS U4502 ( .A(mult_x_24_n1023), .B(mult_x_24_n1030), .Y(n6156) );
OAI21X4TS U4503 ( .A0(n6155), .A1(n6160), .B0(n6156), .Y(n6147) );
NAND2X2TS U4504 ( .A(mult_x_24_n997), .B(mult_x_24_n1006), .Y(n6142) );
NAND2X4TS U4505 ( .A(mult_x_24_n987), .B(mult_x_24_n996), .Y(n6136) );
NAND2X2TS U4506 ( .A(mult_x_24_n977), .B(mult_x_24_n986), .Y(n6133) );
INVX2TS U4507 ( .A(n6133), .Y(n1175) );
OR2X4TS U4508 ( .A(mult_x_24_n944), .B(mult_x_24_n954), .Y(n6119) );
OR2X4TS U4509 ( .A(mult_x_24_n931), .B(mult_x_24_n943), .Y(n6113) );
NAND2X2TS U4510 ( .A(mult_x_24_n955), .B(mult_x_24_n965), .Y(n6123) );
INVX4TS U4511 ( .A(n6118), .Y(n6108) );
NAND2X2TS U4512 ( .A(mult_x_24_n931), .B(mult_x_24_n943), .Y(n6112) );
NOR2X6TS U4513 ( .A(mult_x_24_n880), .B(mult_x_24_n869), .Y(n7101) );
NOR2X4TS U4514 ( .A(n7101), .B(n7097), .Y(n1182) );
OR2X4TS U4515 ( .A(mult_x_24_n905), .B(mult_x_24_n917), .Y(n7110) );
OR2X4TS U4516 ( .A(mult_x_24_n930), .B(mult_x_24_n918), .Y(n7107) );
INVX4TS U4517 ( .A(n6103), .Y(n7106) );
NAND2X2TS U4518 ( .A(mult_x_24_n905), .B(mult_x_24_n917), .Y(n7109) );
INVX2TS U4519 ( .A(n7109), .Y(n1180) );
AOI21X4TS U4520 ( .A0(n7110), .A1(n7106), .B0(n1180), .Y(n6095) );
NAND2X2TS U4521 ( .A(mult_x_24_n893), .B(mult_x_24_n904), .Y(n6099) );
OAI21X4TS U4522 ( .A0(n6095), .A1(n6098), .B0(n6099), .Y(n6976) );
NAND2X2TS U4523 ( .A(mult_x_24_n881), .B(mult_x_24_n892), .Y(n7096) );
NAND2X2TS U4524 ( .A(mult_x_24_n869), .B(mult_x_24_n880), .Y(n7102) );
AOI21X4TS U4525 ( .A0(n6976), .A1(n1182), .B0(n1181), .Y(n1183) );
OAI21X4TS U4526 ( .A0(n6093), .A1(n1184), .B0(n1183), .Y(n4834) );
NOR2X4TS U4527 ( .A(mult_x_24_n777), .B(mult_x_24_n769), .Y(n4887) );
INVX2TS U4528 ( .A(n4887), .Y(n4837) );
NAND2X4TS U4529 ( .A(n4837), .B(n784), .Y(n4877) );
NOR2X4TS U4530 ( .A(mult_x_24_n797), .B(mult_x_24_n788), .Y(n4840) );
INVX2TS U4531 ( .A(n4840), .Y(n5229) );
NOR2X4TS U4532 ( .A(mult_x_24_n857), .B(mult_x_24_n868), .Y(n6088) );
NOR2X4TS U4533 ( .A(n6088), .B(n5232), .Y(n5237) );
NOR2X4TS U4534 ( .A(mult_x_24_n833), .B(mult_x_24_n844), .Y(n5217) );
NOR2X4TS U4535 ( .A(mult_x_24_n821), .B(mult_x_24_n832), .Y(n5244) );
NAND2X4TS U4536 ( .A(n5237), .B(n1186), .Y(n5250) );
NOR2X4TS U4537 ( .A(n1200), .B(n5250), .Y(n1202) );
NAND2X4TS U4538 ( .A(mult_x_24_n857), .B(mult_x_24_n868), .Y(n6089) );
NAND2X2TS U4539 ( .A(mult_x_24_n845), .B(mult_x_24_n856), .Y(n5233) );
OAI21X4TS U4540 ( .A0(n5232), .A1(n6089), .B0(n5233), .Y(n5241) );
NAND2X2TS U4541 ( .A(mult_x_24_n833), .B(mult_x_24_n844), .Y(n5238) );
NAND2X2TS U4542 ( .A(mult_x_24_n821), .B(mult_x_24_n832), .Y(n5245) );
OAI21X2TS U4543 ( .A0(n5238), .A1(n5244), .B0(n5245), .Y(n1185) );
AOI21X4TS U4544 ( .A0(n5241), .A1(n1186), .B0(n1185), .Y(n5249) );
NAND2X2TS U4545 ( .A(mult_x_24_n820), .B(mult_x_24_n809), .Y(n5251) );
INVX2TS U4546 ( .A(n5251), .Y(n4849) );
INVX2TS U4547 ( .A(n4852), .Y(n1187) );
AOI21X4TS U4548 ( .A0(n4849), .A1(n768), .B0(n1187), .Y(n5222) );
NAND2X2TS U4549 ( .A(mult_x_24_n788), .B(mult_x_24_n797), .Y(n5228) );
INVX2TS U4550 ( .A(n5228), .Y(n1189) );
INVX2TS U4551 ( .A(n4845), .Y(n1188) );
OAI21X4TS U4552 ( .A0(n5222), .A1(n1191), .B0(n1190), .Y(n4864) );
NAND2X2TS U4553 ( .A(mult_x_24_n769), .B(mult_x_24_n777), .Y(n4886) );
INVX2TS U4554 ( .A(n4886), .Y(n1193) );
NAND2X2TS U4555 ( .A(mult_x_24_n760), .B(mult_x_24_n768), .Y(n4894) );
INVX2TS U4556 ( .A(n4894), .Y(n1192) );
AOI21X4TS U4557 ( .A0(n784), .A1(n1193), .B0(n1192), .Y(n4876) );
INVX2TS U4558 ( .A(n4882), .Y(n4865) );
INVX2TS U4559 ( .A(n4873), .Y(n1194) );
AOI21X2TS U4560 ( .A0(n1027), .A1(n4865), .B0(n1194), .Y(n1195) );
OAI21X2TS U4561 ( .A0(n4876), .A1(n1196), .B0(n1195), .Y(n1197) );
AOI21X4TS U4562 ( .A0(n4864), .A1(n1198), .B0(n1197), .Y(n1199) );
OAI21X4TS U4563 ( .A0(n1200), .A1(n5249), .B0(n1199), .Y(n1201) );
AOI21X4TS U4564 ( .A0(n4834), .A1(n1202), .B0(n1201), .Y(n1203) );
NOR2X2TS U4565 ( .A(mult_x_24_n736), .B(mult_x_24_n742), .Y(n1266) );
NAND2X2TS U4566 ( .A(mult_x_24_n736), .B(mult_x_24_n742), .Y(n6733) );
OAI21X2TS U4567 ( .A0(n816), .A1(n1266), .B0(n6733), .Y(n1204) );
NAND2X2TS U4568 ( .A(mult_x_24_n729), .B(mult_x_24_n735), .Y(n1267) );
XOR2X4TS U4569 ( .A(n1204), .B(n982), .Y(Sgf_operation_ODD1_right_N43) );
BUFX20TS U4570 ( .A(n8412), .Y(n6785) );
NOR2X8TS U4571 ( .A(n6349), .B(n6353), .Y(n6420) );
AOI21X4TS U4572 ( .A0(n6458), .A1(n1207), .B0(n1206), .Y(n6361) );
NAND2X2TS U4573 ( .A(n6785), .B(n6945), .Y(n6433) );
NOR2X6TS U4574 ( .A(n6333), .B(n6414), .Y(n6322) );
NAND2X1TS U4575 ( .A(n6315), .B(n6326), .Y(n1215) );
AOI21X4TS U4576 ( .A0(n1216), .A1(n6323), .B0(n1215), .Y(n3815) );
INVX2TS U4577 ( .A(n3812), .Y(n6297) );
XNOR2X4TS U4578 ( .A(n1218), .B(n1217), .Y(n1219) );
CLKBUFX2TS U4579 ( .A(Op_MX[19]), .Y(n6749) );
BUFX3TS U4580 ( .A(n6749), .Y(n6830) );
OAI21X1TS U4581 ( .A0(n6832), .A1(n6819), .B0(n1220), .Y(n1221) );
INVX2TS U4582 ( .A(n730), .Y(n6820) );
NOR2X6TS U4583 ( .A(n3655), .B(n3657), .Y(n3608) );
NAND2X4TS U4584 ( .A(n3608), .B(n1225), .Y(n1227) );
INVX2TS U4585 ( .A(n3647), .Y(n1223) );
AOI21X4TS U4586 ( .A0(n1002), .A1(n1223), .B0(n1222), .Y(n3606) );
NAND2X2TS U4587 ( .A(n5892), .B(n5901), .Y(n3707) );
NAND2X4TS U4588 ( .A(n755), .B(n5892), .Y(n3703) );
NAND2X1TS U4589 ( .A(n3707), .B(n3703), .Y(n1224) );
AOI21X4TS U4590 ( .A0(n3607), .A1(n1225), .B0(n1224), .Y(n1226) );
OAI21X4TS U4591 ( .A0(n1227), .A1(n3606), .B0(n1226), .Y(n4974) );
BUFX16TS U4592 ( .A(Op_MY[41]), .Y(n6045) );
NOR2X4TS U4593 ( .A(n4991), .B(n1233), .Y(n1235) );
AOI21X4TS U4594 ( .A0(n4972), .A1(n1229), .B0(n1228), .Y(n4993) );
OAI21X4TS U4595 ( .A0(n4993), .A1(n1233), .B0(n1232), .Y(n1234) );
AOI21X4TS U4596 ( .A0(n4974), .A1(n1235), .B0(n1234), .Y(n1248) );
INVX2TS U4597 ( .A(n1250), .Y(n1241) );
NAND2X1TS U4598 ( .A(n1241), .B(n1251), .Y(n1236) );
XNOR2X4TS U4599 ( .A(n1242), .B(n1236), .Y(n1237) );
BUFX3TS U4600 ( .A(n3853), .Y(n6061) );
NOR2BX4TS U4601 ( .AN(n5904), .B(Op_MX[51]), .Y(n3880) );
OAI21X2TS U4602 ( .A0(n6048), .A1(n6061), .B0(n1239), .Y(mult_x_23_n1246) );
INVX2TS U4603 ( .A(n1251), .Y(n1240) );
INVX2TS U4604 ( .A(n1249), .Y(n1243) );
NAND2X1TS U4605 ( .A(n1243), .B(n1252), .Y(n1244) );
XNOR2X4TS U4606 ( .A(n1245), .B(n1244), .Y(n6026) );
AOI21X1TS U4607 ( .A0(n5936), .A1(n6023), .B0(n1246), .Y(n1247) );
INVX2TS U4608 ( .A(mult_x_23_n666), .Y(n1264) );
NOR2X2TS U4609 ( .A(n5939), .B(n5775), .Y(n3846) );
NOR2X4TS U4610 ( .A(n5455), .B(n5457), .Y(n3842) );
NAND2X4TS U4611 ( .A(n1256), .B(n3842), .Y(n1258) );
NOR2X4TS U4612 ( .A(n1258), .B(n5453), .Y(n3858) );
OR2X2TS U4613 ( .A(n5883), .B(n5771), .Y(n3870) );
NAND2X2TS U4614 ( .A(n3858), .B(n3870), .Y(n1260) );
NAND2X2TS U4615 ( .A(n829), .B(n5906), .Y(n5531) );
NAND2X1TS U4616 ( .A(n5536), .B(n5531), .Y(n1253) );
AOI21X4TS U4617 ( .A0(n5399), .A1(n1254), .B0(n1253), .Y(n5452) );
NAND2X1TS U4618 ( .A(n5771), .B(n5775), .Y(n3849) );
NAND2X1TS U4619 ( .A(n3849), .B(n5406), .Y(n1255) );
AOI21X4TS U4620 ( .A0(n3859), .A1(n3870), .B0(Op_MY[51]), .Y(n1259) );
OAI21X4TS U4621 ( .A0(n5454), .A1(n1260), .B0(n1259), .Y(n3865) );
XNOR2X4TS U4622 ( .A(Op_MX[41]), .B(Op_MX[42]), .Y(n4664) );
XOR2X4TS U4623 ( .A(Op_MX[44]), .B(Op_MX[43]), .Y(n4665) );
NAND2BX4TS U4624 ( .AN(n4664), .B(n4665), .Y(n4671) );
BUFX3TS U4625 ( .A(n4671), .Y(n5924) );
INVX4TS U4626 ( .A(n5560), .Y(n5835) );
INVX4TS U4627 ( .A(n5835), .Y(n5919) );
NOR2BX4TS U4628 ( .AN(n4664), .B(n1795), .Y(n4672) );
AOI21X1TS U4629 ( .A0(n5919), .A1(n5883), .B0(n6011), .Y(n1261) );
OAI21X1TS U4630 ( .A0(n5887), .A1(n5924), .B0(n1261), .Y(n1262) );
XOR2X1TS U4631 ( .A(n1262), .B(Op_MX[44]), .Y(n1263) );
INVX2TS U4632 ( .A(n1266), .Y(n6732) );
NAND2X4TS U4633 ( .A(n6732), .B(n785), .Y(n1290) );
INVX2TS U4634 ( .A(n1267), .Y(n1268) );
AOI21X4TS U4635 ( .A0(n1269), .A1(n785), .B0(n1268), .Y(n1304) );
OAI21X2TS U4636 ( .A0(n816), .A1(n1290), .B0(n1304), .Y(n1270) );
INVX4TS U4637 ( .A(n1275), .Y(n1289) );
XOR2X4TS U4638 ( .A(n1270), .B(n983), .Y(Sgf_operation_ODD1_right_N44) );
NAND2X1TS U4639 ( .A(n1276), .B(n1289), .Y(n1272) );
INVX2TS U4640 ( .A(n1277), .Y(n1300) );
AOI21X1TS U4641 ( .A0(n1280), .A1(n1289), .B0(n1300), .Y(n1271) );
OAI21X2TS U4642 ( .A0(n815), .A1(n1272), .B0(n1271), .Y(n1274) );
INVX2TS U4643 ( .A(n1288), .Y(n1273) );
XOR2X4TS U4644 ( .A(n1274), .B(n984), .Y(Sgf_operation_ODD1_right_N45) );
NOR2X2TS U4645 ( .A(n1275), .B(n1288), .Y(n1279) );
INVX2TS U4646 ( .A(n1286), .Y(n5017) );
NAND2X1TS U4647 ( .A(n5012), .B(n5017), .Y(n1283) );
OAI21X1TS U4648 ( .A0(n1277), .A1(n1288), .B0(n1297), .Y(n1278) );
INVX2TS U4649 ( .A(n5016), .Y(n1281) );
OAI21X2TS U4650 ( .A0(n815), .A1(n1283), .B0(n1282), .Y(n1285) );
NOR2X2TS U4651 ( .A(mult_x_24_n705), .B(mult_x_24_n702), .Y(n1292) );
INVX2TS U4652 ( .A(n1292), .Y(n1284) );
NAND2X1TS U4653 ( .A(mult_x_24_n705), .B(mult_x_24_n702), .Y(n1291) );
XOR2X4TS U4654 ( .A(n1285), .B(n985), .Y(Sgf_operation_ODD1_right_N48) );
NAND2X4TS U4655 ( .A(n1301), .B(n1289), .Y(n1303) );
NOR2X6TS U4656 ( .A(n1290), .B(n1303), .Y(n5112) );
NAND2X1TS U4657 ( .A(n5112), .B(n5023), .Y(n1306) );
INVX2TS U4658 ( .A(n5028), .Y(n1294) );
OAI21X4TS U4659 ( .A0(n1304), .A1(n1303), .B0(n1302), .Y(n5121) );
INVX2TS U4660 ( .A(n5022), .Y(n3806) );
AOI21X1TS U4661 ( .A0(n5121), .A1(n5023), .B0(n3806), .Y(n1305) );
OAI21X2TS U4662 ( .A0(n815), .A1(n1306), .B0(n1305), .Y(n1307) );
OR2X2TS U4663 ( .A(mult_x_24_n695), .B(mult_x_24_n697), .Y(n3807) );
NAND2X1TS U4664 ( .A(mult_x_24_n695), .B(mult_x_24_n697), .Y(n3804) );
XOR2X4TS U4665 ( .A(n1307), .B(n1024), .Y(Sgf_operation_ODD1_right_N50) );
NOR2X8TS U4666 ( .A(Op_MY[30]), .B(Op_MY[3]), .Y(n1346) );
OAI21X4TS U4667 ( .A0(n1346), .A1(n1363), .B0(n1348), .Y(n1308) );
AOI21X4TS U4668 ( .A0(n1345), .A1(n1309), .B0(n1308), .Y(n1332) );
OAI21X4TS U4669 ( .A0(n1389), .A1(n1385), .B0(n1390), .Y(n1330) );
AOI21X4TS U4670 ( .A0(n1388), .A1(n1325), .B0(n1330), .Y(n1409) );
NAND2X2TS U4671 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n1326) );
NAND2X1TS U4672 ( .A(n1310), .B(n1326), .Y(n1311) );
XNOR2X4TS U4673 ( .A(n1312), .B(n1311), .Y(n1313) );
XNOR2X1TS U4674 ( .A(n860), .B(n1708), .Y(n1421) );
NOR2X2TS U4675 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n1316) );
OAI21X2TS U4676 ( .A0(Op_MX[29]), .A1(Op_MX[2]), .B0(Op_MX[1]), .Y(n1317) );
NAND2X2TS U4677 ( .A(n1413), .B(n1418), .Y(n1319) );
INVX2TS U4678 ( .A(n3637), .Y(n1322) );
NOR2X1TS U4679 ( .A(n1322), .B(n1321), .Y(n1323) );
XOR2X1TS U4680 ( .A(n1323), .B(n1397), .Y(n1324) );
AOI21X4TS U4681 ( .A0(n1330), .A1(n1329), .B0(n1328), .Y(n1331) );
OAI21X4TS U4682 ( .A0(n1333), .A1(n1332), .B0(n1331), .Y(n1767) );
INVX12TS U4683 ( .A(n1767), .Y(n1675) );
INVX2TS U4684 ( .A(n1431), .Y(n1334) );
XOR2X4TS U4685 ( .A(n1675), .B(n1335), .Y(n2735) );
XNOR2X1TS U4686 ( .A(n856), .B(n1708), .Y(n1635) );
BUFX3TS U4687 ( .A(n1828), .Y(n2315) );
OAI22X1TS U4688 ( .A0(n1421), .A1(n2459), .B0(n1635), .B1(n2315), .Y(n1630)
);
INVX2TS U4689 ( .A(n1336), .Y(n1387) );
XNOR2X2TS U4690 ( .A(n1388), .B(n1337), .Y(n1787) );
XNOR2X4TS U4691 ( .A(Op_MX[9]), .B(Op_MX[36]), .Y(n1369) );
XOR2X4TS U4692 ( .A(n1370), .B(n1369), .Y(n1424) );
XNOR2X1TS U4693 ( .A(n907), .B(n1872), .Y(n1634) );
CLKXOR2X4TS U4694 ( .A(Op_MX[8]), .B(Op_MX[35]), .Y(n1353) );
NOR2X2TS U4695 ( .A(Op_MX[7]), .B(Op_MX[34]), .Y(n1340) );
XNOR2X4TS U4696 ( .A(n1353), .B(n1340), .Y(n1344) );
XNOR2X4TS U4697 ( .A(Op_MX[7]), .B(Op_MX[34]), .Y(n1402) );
NAND2X1TS U4698 ( .A(Op_MX[6]), .B(Op_MX[33]), .Y(n1341) );
XOR2X4TS U4699 ( .A(n1344), .B(n1343), .Y(n1478) );
INVX2TS U4700 ( .A(n1347), .Y(n1349) );
NAND2X2TS U4701 ( .A(n1349), .B(n1348), .Y(n1350) );
XNOR2X4TS U4702 ( .A(n1351), .B(n1350), .Y(n1352) );
XNOR2X1TS U4703 ( .A(n741), .B(n1872), .Y(n1425) );
OAI22X1TS U4704 ( .A0(n1634), .A1(n3178), .B0(n1425), .B1(n3222), .Y(n1633)
);
OR2X4TS U4705 ( .A(n3632), .B(Op_MY[0]), .Y(n1356) );
NOR2X2TS U4706 ( .A(Op_MX[11]), .B(Op_MX[38]), .Y(n1357) );
XNOR2X4TS U4707 ( .A(n1617), .B(n1357), .Y(n1361) );
XNOR2X4TS U4708 ( .A(Op_MX[11]), .B(Op_MX[38]), .Y(n1379) );
NAND2X4TS U4709 ( .A(n1359), .B(n1358), .Y(n1366) );
NAND2X2TS U4710 ( .A(n1379), .B(n1366), .Y(n1360) );
XOR2X4TS U4711 ( .A(n1361), .B(n1360), .Y(n1616) );
NOR2BX1TS U4712 ( .AN(n1029), .B(n2214), .Y(n1627) );
INVX2TS U4713 ( .A(n1362), .Y(n1364) );
XNOR2X4TS U4714 ( .A(n1379), .B(n1366), .Y(n1367) );
INVX8TS U4715 ( .A(n1367), .Y(n3367) );
NOR2X2TS U4716 ( .A(Op_MX[9]), .B(Op_MX[36]), .Y(n1368) );
XNOR2X4TS U4717 ( .A(n1377), .B(n1368), .Y(n1372) );
XOR2X4TS U4718 ( .A(n1372), .B(n1371), .Y(n2215) );
INVX2TS U4719 ( .A(n1373), .Y(n1375) );
NAND2X2TS U4720 ( .A(n1375), .B(n1374), .Y(n1376) );
XOR2X1TS U4721 ( .A(n1380), .B(n1379), .Y(n1381) );
XNOR2X1TS U4722 ( .A(n2223), .B(n3227), .Y(n1382) );
OAI22X2TS U4723 ( .A0(n1383), .A1(n3301), .B0(n1382), .B1(n1751), .Y(n1423)
);
INVX4TS U4724 ( .A(n3367), .Y(n1979) );
NAND2BX1TS U4725 ( .AN(n2198), .B(n1979), .Y(n1384) );
INVX2TS U4726 ( .A(n1385), .Y(n1386) );
AOI21X4TS U4727 ( .A0(n1388), .A1(n1387), .B0(n1386), .Y(n1393) );
INVX2TS U4728 ( .A(n1389), .Y(n1391) );
NAND2X1TS U4729 ( .A(n1391), .B(n1390), .Y(n1392) );
XOR2X4TS U4730 ( .A(n1393), .B(n1392), .Y(n2532) );
INVX6TS U4731 ( .A(n1395), .Y(n2876) );
INVX12TS U4732 ( .A(n2876), .Y(n2771) );
XNOR2X1TS U4733 ( .A(n908), .B(n2771), .Y(n1410) );
INVX2TS U4734 ( .A(n1405), .Y(n1407) );
NAND2X1TS U4735 ( .A(n1407), .B(n1406), .Y(n1408) );
XOR2X4TS U4736 ( .A(n1409), .B(n1408), .Y(n2577) );
XNOR2X1TS U4737 ( .A(n911), .B(n1740), .Y(n1636) );
BUFX3TS U4738 ( .A(n2018), .Y(n2497) );
OAI22X1TS U4739 ( .A0(n1410), .A1(n2809), .B0(n1636), .B1(n2497), .Y(n1631)
);
XNOR2X1TS U4740 ( .A(n907), .B(n1740), .Y(n1467) );
OAI22X1TS U4741 ( .A0(n1410), .A1(n2808), .B0(n1467), .B1(n2100), .Y(n1474)
);
NOR2X8TS U4742 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n1434) );
CLKINVX1TS U4743 ( .A(n1434), .Y(n1411) );
NAND2X4TS U4744 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n1432) );
NAND2X1TS U4745 ( .A(n1411), .B(n1432), .Y(n1412) );
INVX4TS U4746 ( .A(n736), .Y(n1611) );
XNOR2X4TS U4747 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n1449) );
XOR2X4TS U4748 ( .A(n1416), .B(n1415), .Y(n2627) );
OAI22X1TS U4749 ( .A0(n1439), .A1(n2559), .B0(n1483), .B1(n1895), .Y(n1473)
);
XNOR2X1TS U4750 ( .A(n911), .B(n1708), .Y(n1471) );
OAI22X1TS U4751 ( .A0(n1421), .A1(n2738), .B0(n1471), .B1(n2045), .Y(n1472)
);
XNOR2X1TS U4752 ( .A(n2580), .B(n2881), .Y(n1426) );
OAI22X1TS U4753 ( .A0(n1425), .A1(n3178), .B0(n1426), .B1(n3222), .Y(n1465)
);
NOR2BX1TS U4754 ( .AN(n1029), .B(n2215), .Y(n1470) );
BUFX3TS U4755 ( .A(n1478), .Y(n2303) );
OAI22X2TS U4756 ( .A0(n1430), .A1(n3178), .B0(n1429), .B1(n1428), .Y(n1475)
);
INVX2TS U4757 ( .A(n1453), .Y(n1436) );
OAI21X4TS U4758 ( .A0(n1434), .A1(n1433), .B0(n1432), .Y(n1459) );
OAI21X4TS U4759 ( .A0(n1675), .A1(n1436), .B0(n1435), .Y(n1438) );
XNOR2X4TS U4760 ( .A(n1438), .B(n1437), .Y(n2474) );
XNOR2X1TS U4761 ( .A(n901), .B(n1611), .Y(n1612) );
OAI22X1TS U4762 ( .A0(n1439), .A1(n2368), .B0(n1612), .B1(n2053), .Y(n1638)
);
INVX2TS U4763 ( .A(n1456), .Y(n1440) );
AOI21X1TS U4764 ( .A0(n1459), .A1(n1441), .B0(n1440), .Y(n1442) );
OAI21X4TS U4765 ( .A0(n1675), .A1(n1443), .B0(n1442), .Y(n1446) );
NAND2X1TS U4766 ( .A(n1444), .B(n1454), .Y(n1445) );
XNOR2X4TS U4767 ( .A(n1446), .B(n1445), .Y(n1447) );
XNOR2X1TS U4768 ( .A(n3368), .B(n2287), .Y(n1463) );
XOR2X1TS U4769 ( .A(n1006), .B(n1449), .Y(n1451) );
XOR2X1TS U4770 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n1450) );
BUFX3TS U4771 ( .A(n1500), .Y(n2363) );
OAI21X4TS U4772 ( .A0(n1456), .A1(n1455), .B0(n1454), .Y(n1457) );
AOI21X4TS U4773 ( .A0(n1459), .A1(n1458), .B0(n1457), .Y(n1763) );
OAI21X4TS U4774 ( .A0(n1675), .A1(n1755), .B0(n1698), .Y(n1461) );
NAND2X1TS U4775 ( .A(n1603), .B(n1670), .Y(n1460) );
XNOR2X4TS U4776 ( .A(n1461), .B(n1460), .Y(n1462) );
BUFX3TS U4777 ( .A(n1812), .Y(n1974) );
OAI22X1TS U4778 ( .A0(n1463), .A1(n2363), .B0(n1610), .B1(n1974), .Y(n1637)
);
XNOR2X1TS U4779 ( .A(n901), .B(n2287), .Y(n1484) );
OAI22X1TS U4780 ( .A0(n1484), .A1(n2363), .B0(n1463), .B1(n1974), .Y(n1487)
);
XNOR2X1TS U4781 ( .A(n862), .B(n1740), .Y(n1477) );
OAI22X1TS U4782 ( .A0(n1467), .A1(n2808), .B0(n1477), .B1(n2100), .Y(n1490)
);
XNOR2X1TS U4783 ( .A(n908), .B(n2653), .Y(n1491) );
OAI22X1TS U4784 ( .A0(n1491), .A1(n2459), .B0(n1471), .B1(n2315), .Y(n1488)
);
CMPR32X2TS U4785 ( .A(n1474), .B(n1473), .C(n1472), .CO(n1628), .S(n1499) );
XNOR2X1TS U4786 ( .A(n857), .B(n2771), .Y(n1479) );
NOR2BX1TS U4787 ( .AN(n1029), .B(n3221), .Y(n1542) );
NAND2BX1TS U4788 ( .AN(n7232), .B(n1740), .Y(n1480) );
OAI22X1TS U4789 ( .A0(n1480), .A1(n2808), .B0(n2877), .B1(n2876), .Y(n1546)
);
XNOR2X1TS U4790 ( .A(n929), .B(n2771), .Y(n1481) );
XNOR2X1TS U4791 ( .A(n860), .B(n1611), .Y(n1493) );
OAI22X1TS U4792 ( .A0(n1493), .A1(n2368), .B0(n1483), .B1(n2053), .Y(n1495)
);
OAI22X1TS U4793 ( .A0(n1492), .A1(n2363), .B0(n1484), .B1(n1974), .Y(n1494)
);
CMPR32X2TS U4794 ( .A(n1490), .B(n1489), .C(n1488), .CO(n1485), .S(n1574) );
XNOR2X1TS U4795 ( .A(n907), .B(n1708), .Y(n1539) );
OAI22X1TS U4796 ( .A0(n1491), .A1(n2738), .B0(n1539), .B1(n2045), .Y(n1583)
);
BUFX3TS U4797 ( .A(n1500), .Y(n1810) );
OAI22X1TS U4798 ( .A0(n1492), .A1(n1812), .B0(n1544), .B1(n1810), .Y(n1582)
);
XNOR2X1TS U4799 ( .A(n911), .B(n1611), .Y(n1543) );
OAI22X1TS U4800 ( .A0(n1493), .A1(n2559), .B0(n1543), .B1(n1895), .Y(n1581)
);
NAND2X2TS U4801 ( .A(n789), .B(n734), .Y(n1602) );
CLKBUFX2TS U4802 ( .A(n1812), .Y(n7231) );
NAND2X1TS U4803 ( .A(n2477), .B(n1501), .Y(n7222) );
INVX2TS U4804 ( .A(n7224), .Y(n7220) );
XNOR2X1TS U4805 ( .A(n857), .B(n2254), .Y(n1506) );
OAI22X1TS U4806 ( .A0(n1506), .A1(n1812), .B0(n1502), .B1(n1810), .Y(n1504)
);
NOR2BX1TS U4807 ( .AN(n929), .B(n2559), .Y(n1503) );
NAND2X1TS U4808 ( .A(n1504), .B(n1503), .Y(n7218) );
INVX2TS U4809 ( .A(n7218), .Y(n1505) );
AOI21X4TS U4810 ( .A0(n7220), .A1(n7219), .B0(n1505), .Y(n7217) );
XNOR2X1TS U4811 ( .A(n741), .B(n2254), .Y(n1514) );
OAI22X1TS U4812 ( .A0(n1514), .A1(n1812), .B0(n1506), .B1(n1810), .Y(n1510)
);
NAND2BX1TS U4813 ( .AN(n2198), .B(n1611), .Y(n1507) );
OAI22X1TS U4814 ( .A0(n2560), .A1(n736), .B0(n1507), .B1(n2053), .Y(n1513)
);
XNOR2X1TS U4815 ( .A(n2198), .B(n2469), .Y(n1508) );
NOR2X1TS U4816 ( .A(n1510), .B(n1509), .Y(n7213) );
NAND2X1TS U4817 ( .A(n1510), .B(n1509), .Y(n7214) );
OAI21X4TS U4818 ( .A0(n7217), .A1(n7213), .B0(n7214), .Y(n7211) );
NOR2BX1TS U4819 ( .AN(n929), .B(n2787), .Y(n1524) );
XNOR2X1TS U4820 ( .A(n857), .B(n2469), .Y(n1521) );
OAI22X1TS U4821 ( .A0(n1521), .A1(n2053), .B0(n1511), .B1(n1895), .Y(n1523)
);
XNOR2X1TS U4822 ( .A(n907), .B(n2287), .Y(n1525) );
OAI22X1TS U4823 ( .A0(n1525), .A1(n1812), .B0(n1514), .B1(n1810), .Y(n1515)
);
NAND2X1TS U4824 ( .A(n1516), .B(n1515), .Y(n7209) );
INVX2TS U4825 ( .A(n7209), .Y(n1517) );
AOI21X4TS U4826 ( .A0(n7211), .A1(n7210), .B0(n1517), .Y(n7207) );
XNOR2X1TS U4827 ( .A(n929), .B(n2653), .Y(n1519) );
OAI22X1TS U4828 ( .A0(n1520), .A1(n2738), .B0(n2739), .B1(n2786), .Y(n1530)
);
XNOR2X1TS U4829 ( .A(n862), .B(n1611), .Y(n1528) );
OAI22X1TS U4830 ( .A0(n1528), .A1(n2559), .B0(n1521), .B1(n1895), .Y(n1534)
);
XNOR2X1TS U4831 ( .A(n908), .B(n2287), .Y(n1532) );
OAI22X1TS U4832 ( .A0(n1532), .A1(n7231), .B0(n1525), .B1(n1810), .Y(n1526)
);
NOR2X2TS U4833 ( .A(n1527), .B(n1526), .Y(n7204) );
NAND2X2TS U4834 ( .A(n1527), .B(n1526), .Y(n7205) );
OAI21X4TS U4835 ( .A0(n7207), .A1(n7204), .B0(n7205), .Y(n7202) );
XNOR2X1TS U4836 ( .A(n907), .B(n1611), .Y(n1552) );
OAI22X1TS U4837 ( .A0(n1552), .A1(n2559), .B0(n1528), .B1(n1895), .Y(n1564)
);
NOR2BX1TS U4838 ( .AN(n7232), .B(n2018), .Y(n1551) );
XNOR2X1TS U4839 ( .A(n2580), .B(n2653), .Y(n1547) );
OAI22X2TS U4840 ( .A0(n1547), .A1(n2738), .B0(n1529), .B1(n2045), .Y(n1550)
);
XNOR2X1TS U4841 ( .A(n911), .B(n2632), .Y(n1554) );
OAI22X1TS U4842 ( .A0(n1532), .A1(n2363), .B0(n1554), .B1(n1974), .Y(n1562)
);
AOI21X4TS U4843 ( .A0(n7202), .A1(n7201), .B0(n1538), .Y(n7190) );
XNOR2X1TS U4844 ( .A(n741), .B(n1708), .Y(n1548) );
OAI22X1TS U4845 ( .A0(n1539), .A1(n2738), .B0(n1548), .B1(n2045), .Y(n1577)
);
ADDFHX2TS U4846 ( .A(n1542), .B(n1541), .CI(n1540), .CO(n1578), .S(n1576) );
XNOR2X1TS U4847 ( .A(n2789), .B(n2469), .Y(n1553) );
OAI22X1TS U4848 ( .A0(n1553), .A1(n2368), .B0(n1543), .B1(n2053), .Y(n1575)
);
XNOR2X1TS U4849 ( .A(n860), .B(n2632), .Y(n1555) );
OAI22X1TS U4850 ( .A0(n1555), .A1(n2363), .B0(n1544), .B1(n1974), .Y(n1588)
);
OAI22X1TS U4851 ( .A0(n1548), .A1(n2738), .B0(n1547), .B1(n2045), .Y(n1557)
);
OAI22X1TS U4852 ( .A0(n1553), .A1(n2559), .B0(n1552), .B1(n1895), .Y(n1561)
);
OAI22X1TS U4853 ( .A0(n1555), .A1(n1812), .B0(n1554), .B1(n1810), .Y(n1560)
);
NOR2X4TS U4854 ( .A(n1568), .B(n1567), .Y(n1569) );
NAND2X2TS U4855 ( .A(n1566), .B(n1565), .Y(n7196) );
OAI21X4TS U4856 ( .A0(n7190), .A1(n1571), .B0(n1570), .Y(n7184) );
ADDFHX2TS U4857 ( .A(n1577), .B(n1576), .CI(n1575), .CO(n1586), .S(n1589) );
CMPR32X2TS U4858 ( .A(n1583), .B(n1582), .C(n1581), .CO(n1573), .S(n1584) );
CMPR32X2TS U4859 ( .A(n1586), .B(n1585), .C(n1584), .CO(n1592), .S(n1591) );
NAND2X2TS U4860 ( .A(n1591), .B(n1590), .Y(n7227) );
OAI21X4TS U4861 ( .A0(n7185), .A1(n7227), .B0(n7186), .Y(n1594) );
AOI21X4TS U4862 ( .A0(n7184), .A1(n1595), .B0(n1594), .Y(n7176) );
NAND2X2TS U4863 ( .A(n1597), .B(n1596), .Y(n7181) );
NAND2X2TS U4864 ( .A(n1599), .B(n1598), .Y(n7178) );
INVX2TS U4865 ( .A(n7178), .Y(n1600) );
OAI21X4TS U4866 ( .A0(n1602), .A1(n7176), .B0(n1601), .Y(n7159) );
AOI2BB1X4TS U4867 ( .A0N(n1698), .A1N(n1668), .B0(n1604), .Y(n1605) );
OAI21X4TS U4868 ( .A0(n1606), .A1(n1675), .B0(n1605), .Y(n1609) );
NAND2X1TS U4869 ( .A(n1607), .B(n1669), .Y(n1608) );
XNOR2X4TS U4870 ( .A(n1609), .B(n1608), .Y(n3217) );
BUFX20TS U4871 ( .A(n3217), .Y(n3364) );
XNOR2X1TS U4872 ( .A(n2954), .B(n2632), .Y(n1680) );
XNOR2X1TS U4873 ( .A(n916), .B(n1611), .Y(n1667) );
OAI22X1TS U4874 ( .A0(n1612), .A1(n2368), .B0(n1667), .B1(n2053), .Y(n1659)
);
XNOR2X4TS U4875 ( .A(Op_MX[13]), .B(Op_MX[40]), .Y(n1647) );
XNOR2X4TS U4876 ( .A(n1646), .B(n1647), .Y(n1615) );
BUFX12TS U4877 ( .A(n1616), .Y(n3427) );
NAND2X4TS U4878 ( .A(n3427), .B(n1620), .Y(n1622) );
XNOR2X1TS U4879 ( .A(n2198), .B(n3343), .Y(n1623) );
ADDFHX2TS U4880 ( .A(n1627), .B(n1626), .CI(n1625), .CO(n1664), .S(n1632) );
XNOR2X1TS U4881 ( .A(n2789), .B(n2881), .Y(n1654) );
OAI22X1TS U4882 ( .A0(n1654), .A1(n3178), .B0(n1634), .B1(n3222), .Y(n1663)
);
XNOR2X1TS U4883 ( .A(n2869), .B(n1708), .Y(n1644) );
OAI22X1TS U4884 ( .A0(n1644), .A1(n2738), .B0(n1635), .B1(n2045), .Y(n1662)
);
XNOR2X1TS U4885 ( .A(n860), .B(n1740), .Y(n1643) );
OAI22X1TS U4886 ( .A0(n1643), .A1(n2808), .B0(n1636), .B1(n2809), .Y(n1661)
);
ADDFHX2TS U4887 ( .A(n1639), .B(n1638), .CI(n1637), .CO(n1655), .S(n1641) );
NOR2X4TS U4888 ( .A(n1731), .B(n1732), .Y(n7168) );
OAI22X1TS U4889 ( .A0(n1643), .A1(n928), .B0(n1689), .B1(n2497), .Y(n1725)
);
XNOR2X1TS U4890 ( .A(n901), .B(n1708), .Y(n1709) );
OAI22X1TS U4891 ( .A0(n1644), .A1(n2459), .B0(n1709), .B1(n2315), .Y(n1724)
);
XNOR2X1TS U4892 ( .A(n907), .B(n1979), .Y(n1688) );
OAI22X1TS U4893 ( .A0(n1688), .A1(n3301), .B0(n1645), .B1(n2839), .Y(n1687)
);
NAND2X2TS U4894 ( .A(n1647), .B(n1646), .Y(n1650) );
XNOR2X4TS U4895 ( .A(n1711), .B(n1648), .Y(n1649) );
XOR2X4TS U4896 ( .A(n1650), .B(n1649), .Y(n1710) );
NOR2BX1TS U4897 ( .AN(n929), .B(n1710), .Y(n1722) );
XNOR2X1TS U4898 ( .A(n911), .B(n1872), .Y(n1690) );
OAI22X1TS U4899 ( .A0(n1654), .A1(n2730), .B0(n1690), .B1(n2303), .Y(n1685)
);
ADDFX2TS U4900 ( .A(n1663), .B(n1662), .CI(n1661), .CO(n1692), .S(n1656) );
INVX4TS U4901 ( .A(n736), .Y(n2468) );
XNOR2X1TS U4902 ( .A(n917), .B(n2468), .Y(n1684) );
OAI22X1TS U4903 ( .A0(n1667), .A1(n2368), .B0(n1684), .B1(n2053), .Y(n1695)
);
INVX2TS U4904 ( .A(n1761), .Y(n1672) );
OA21X4TS U4905 ( .A0(n1698), .A1(n1673), .B0(n1672), .Y(n1674) );
OAI21X4TS U4906 ( .A0(n1676), .A1(n1675), .B0(n1674), .Y(n1679) );
INVX2TS U4907 ( .A(n1753), .Y(n1677) );
NAND2X1TS U4908 ( .A(n1677), .B(n1757), .Y(n1678) );
XNOR2X4TS U4909 ( .A(n1679), .B(n1678), .Y(n3283) );
BUFX20TS U4910 ( .A(n3283), .Y(n3176) );
XNOR2X1TS U4911 ( .A(n913), .B(n2254), .Y(n1707) );
BUFX3TS U4912 ( .A(n1812), .Y(n2476) );
OAI22X1TS U4913 ( .A0(n1680), .A1(n2363), .B0(n1707), .B1(n2476), .Y(n1694)
);
XNOR2X1TS U4914 ( .A(n2954), .B(n2469), .Y(n1840) );
OAI22X1TS U4915 ( .A0(n1684), .A1(n1895), .B0(n1840), .B1(n2053), .Y(n1864)
);
XNOR2X1TS U4916 ( .A(n908), .B(n3227), .Y(n1752) );
OAI22X1TS U4917 ( .A0(n1752), .A1(n3301), .B0(n1688), .B1(n932), .Y(n1849)
);
XNOR2X1TS U4918 ( .A(n2878), .B(n1872), .Y(n1809) );
OAI22X1TS U4919 ( .A0(n1809), .A1(n3178), .B0(n1690), .B1(n3222), .Y(n1847)
);
INVX2TS U4920 ( .A(n1698), .Y(n1701) );
AOI21X4TS U4921 ( .A0(n1701), .A1(n1700), .B0(n1699), .Y(n1702) );
OAI2BB1X4TS U4922 ( .A0N(n1019), .A1N(n1767), .B0(n1702), .Y(n1705) );
INVX2TS U4923 ( .A(n1758), .Y(n1703) );
NAND2X1TS U4924 ( .A(n1703), .B(n1756), .Y(n1704) );
XNOR2X4TS U4925 ( .A(n1705), .B(n1704), .Y(n1706) );
OAI22X1TS U4926 ( .A0(n1709), .A1(n2459), .B0(n1807), .B1(n2315), .Y(n1851)
);
XOR2X1TS U4927 ( .A(n1712), .B(n1743), .Y(n1713) );
NAND2X2TS U4928 ( .A(Op_MX[14]), .B(Op_MX[41]), .Y(n1714) );
NAND2X4TS U4929 ( .A(n1715), .B(n1714), .Y(n1744) );
XNOR2X4TS U4930 ( .A(n1744), .B(n1743), .Y(n1747) );
NAND2BX1TS U4931 ( .AN(n2198), .B(n2294), .Y(n1716) );
XNOR2X1TS U4932 ( .A(n862), .B(n2070), .Y(n1741) );
OAI22X1TS U4933 ( .A0(n1741), .A1(n3427), .B0(n1719), .B1(n3428), .Y(n1835)
);
CMPR32X2TS U4934 ( .A(n1725), .B(n1724), .C(n1723), .CO(n1923), .S(n1728) );
NOR2X4TS U4935 ( .A(n7162), .B(n7163), .Y(n1739) );
NAND2X2TS U4936 ( .A(n1737), .B(n1736), .Y(n7164) );
OAI21X4TS U4937 ( .A0(n7161), .A1(n7163), .B0(n7164), .Y(n1738) );
AOI21X4TS U4938 ( .A0(n7159), .A1(n1739), .B0(n1738), .Y(n7155) );
XNOR2X1TS U4939 ( .A(n901), .B(n1740), .Y(n1837) );
XNOR2X1TS U4940 ( .A(n916), .B(n1740), .Y(n1830) );
OAI22X1TS U4941 ( .A0(n1837), .A1(n928), .B0(n1830), .B1(n2497), .Y(n1843)
);
XNOR2X1TS U4942 ( .A(n906), .B(n2070), .Y(n1775) );
OAI22X1TS U4943 ( .A0(n1775), .A1(n3427), .B0(n1741), .B1(n3428), .Y(n1846)
);
XOR2X4TS U4944 ( .A(Op_MX[16]), .B(Op_MX[43]), .Y(n1796) );
XNOR2X4TS U4945 ( .A(n1796), .B(n1742), .Y(n1746) );
XOR2X4TS U4946 ( .A(n1746), .B(n1745), .Y(n2563) );
NOR2BX1TS U4947 ( .AN(n929), .B(n2563), .Y(n1821) );
OAI22X2TS U4948 ( .A0(n1817), .A1(n2940), .B0(n1748), .B1(n888), .Y(n1820)
);
XNOR2X1TS U4949 ( .A(n911), .B(n1979), .Y(n1776) );
BUFX3TS U4950 ( .A(n2215), .Y(n2715) );
OAI22X1TS U4951 ( .A0(n1752), .A1(n933), .B0(n1776), .B1(n2715), .Y(n1844)
);
NOR2X4TS U4952 ( .A(n1755), .B(n1764), .Y(n1766) );
OAI21X4TS U4953 ( .A0(n1764), .A1(n1763), .B0(n1762), .Y(n1765) );
AOI21X4TS U4954 ( .A0(n1767), .A1(n1766), .B0(n1765), .Y(n1768) );
NAND2X1TS U4955 ( .A(n1769), .B(n1778), .Y(n1770) );
XNOR2X4TS U4956 ( .A(n1771), .B(n1770), .Y(n1772) );
XNOR2X1TS U4957 ( .A(n3330), .B(n2287), .Y(n1786) );
INVX2TS U4958 ( .A(n1777), .Y(n1773) );
NAND2X1TS U4959 ( .A(n1773), .B(n1779), .Y(n1774) );
XOR2X4TS U4960 ( .A(n818), .B(n1774), .Y(n2815) );
XNOR2X1TS U4961 ( .A(n3303), .B(n2254), .Y(n1813) );
OAI22X1TS U4962 ( .A0(n1786), .A1(n2476), .B0(n1813), .B1(n1810), .Y(n1841)
);
XNOR2X1TS U4963 ( .A(n908), .B(n3343), .Y(n1803) );
OAI22X1TS U4964 ( .A0(n1803), .A1(n3427), .B0(n1775), .B1(n934), .Y(n1806)
);
XNOR2X1TS U4965 ( .A(n2878), .B(n1979), .Y(n1831) );
OAI22X1TS U4966 ( .A0(n1831), .A1(n3301), .B0(n1776), .B1(n933), .Y(n1804)
);
INVX2TS U4967 ( .A(n1951), .Y(n1782) );
OAI21X4TS U4968 ( .A0(n1780), .A1(n1779), .B0(n1778), .Y(n1957) );
INVX2TS U4969 ( .A(n1957), .Y(n1781) );
OAI21X4TS U4970 ( .A0(n819), .A1(n1782), .B0(n1781), .Y(n1784) );
NOR2X4TS U4971 ( .A(Op_MY[45]), .B(Op_MY[18]), .Y(n1950) );
INVX2TS U4972 ( .A(n1950), .Y(n1901) );
NAND2X1TS U4973 ( .A(n1901), .B(n1953), .Y(n1783) );
XNOR2X4TS U4974 ( .A(n1784), .B(n1783), .Y(n1785) );
XNOR2X1TS U4975 ( .A(n922), .B(n2632), .Y(n1907) );
OAI22X1TS U4976 ( .A0(n1786), .A1(n2363), .B0(n1907), .B1(n1974), .Y(n1898)
);
XNOR2X1TS U4977 ( .A(n1787), .B(n2294), .Y(n1909) );
OAI22X1TS U4978 ( .A0(n1909), .A1(n2940), .B0(n1818), .B1(n890), .Y(n1894)
);
NOR2X2TS U4979 ( .A(Op_MX[17]), .B(Op_MX[44]), .Y(n1788) );
XNOR2X4TS U4980 ( .A(n1877), .B(n1788), .Y(n1792) );
OAI21X4TS U4981 ( .A0(Op_MX[16]), .A1(Op_MX[43]), .B0(Op_MX[15]), .Y(n1790)
);
NAND2X2TS U4982 ( .A(Op_MX[16]), .B(Op_MX[43]), .Y(n1789) );
NAND2X4TS U4983 ( .A(n1790), .B(n1789), .Y(n1793) );
XNOR2X4TS U4984 ( .A(Op_MX[17]), .B(Op_MX[44]), .Y(n1798) );
XOR2X4TS U4985 ( .A(n1792), .B(n1791), .Y(n2694) );
CLKBUFX2TS U4986 ( .A(n2694), .Y(n3052) );
NOR2BX1TS U4987 ( .AN(n1029), .B(n3052), .Y(n1887) );
INVX2TS U4988 ( .A(n1795), .Y(n1797) );
OAI22X2TS U4989 ( .A0(n1884), .A1(n2976), .B0(n728), .B1(n3006), .Y(n1886)
);
XNOR2X1TS U4990 ( .A(n911), .B(n2070), .Y(n1910) );
BUFX3TS U4991 ( .A(n2214), .Y(n2817) );
OAI22X1TS U4992 ( .A0(n1803), .A1(n3201), .B0(n1910), .B1(n2817), .Y(n1892)
);
OAI22X1TS U4993 ( .A0(n1814), .A1(n2459), .B0(n1829), .B1(n2315), .Y(n1824)
);
BUFX3TS U4994 ( .A(n2627), .Y(n2510) );
OAI22X1TS U4995 ( .A0(n1839), .A1(n2560), .B0(n1833), .B1(n2510), .Y(n1823)
);
CMPR22X2TS U4996 ( .A(n1816), .B(n1815), .CO(n1885), .S(n1827) );
OAI22X1TS U4997 ( .A0(n1818), .A1(n2940), .B0(n1817), .B1(n888), .Y(n1826)
);
ADDFHX2TS U4998 ( .A(n1821), .B(n1820), .CI(n1819), .CO(n1825), .S(n1845) );
ADDFHX2TS U4999 ( .A(n1827), .B(n1826), .CI(n1825), .CO(n1913), .S(n1822) );
XNOR2X1TS U5000 ( .A(n3176), .B(n2653), .Y(n1891) );
OAI22X1TS U5001 ( .A0(n1829), .A1(n2459), .B0(n1891), .B1(n2787), .Y(n1912)
);
XNOR2X1TS U5002 ( .A(n917), .B(n2720), .Y(n1871) );
OAI22X1TS U5003 ( .A0(n1830), .A1(n928), .B0(n1871), .B1(n2497), .Y(n1911)
);
XNOR2X1TS U5004 ( .A(n3165), .B(n1979), .Y(n1908) );
OAI22X1TS U5005 ( .A0(n1831), .A1(n932), .B0(n1908), .B1(n2715), .Y(n1890)
);
XNOR2X1TS U5006 ( .A(n914), .B(n2469), .Y(n1896) );
OAI22X1TS U5007 ( .A0(n1896), .A1(n2559), .B0(n1833), .B1(n1895), .Y(n1888)
);
ADDFHX2TS U5008 ( .A(n1836), .B(n1835), .CI(n1834), .CO(n1858), .S(n1850) );
OAI22X1TS U5009 ( .A0(n1838), .A1(n2809), .B0(n1837), .B1(n2497), .Y(n1857)
);
OAI22X1TS U5010 ( .A0(n1840), .A1(n2368), .B0(n1839), .B1(n2053), .Y(n1856)
);
ADDFHX2TS U5011 ( .A(n1867), .B(n1866), .CI(n1865), .CO(n1917), .S(n1920) );
OAI22X1TS U5012 ( .A0(n1871), .A1(n2100), .B0(n2029), .B1(n2497), .Y(n2123)
);
XNOR2X1TS U5013 ( .A(n3368), .B(n1872), .Y(n2024) );
OAI22X1TS U5014 ( .A0(n1873), .A1(n2730), .B0(n2024), .B1(n2303), .Y(n2122)
);
XNOR2X4TS U5015 ( .A(Op_MX[19]), .B(Op_MX[46]), .Y(n1982) );
NAND2X4TS U5016 ( .A(n1875), .B(n1874), .Y(n1981) );
XNOR2X4TS U5017 ( .A(n1982), .B(n1981), .Y(n1876) );
XOR2X1TS U5018 ( .A(n1879), .B(n1982), .Y(n1880) );
OAI22X1TS U5019 ( .A0(n1881), .A1(n3031), .B0(n1882), .B1(n3051), .Y(n1996)
);
XNOR2X2TS U5020 ( .A(n858), .B(n2997), .Y(n1993) );
XNOR2X1TS U5021 ( .A(n2223), .B(n2997), .Y(n1883) );
XNOR2X1TS U5022 ( .A(n741), .B(n2264), .Y(n2040) );
OAI22X1TS U5023 ( .A0(n2040), .A1(n2976), .B0(n1884), .B1(n3006), .Y(n2027)
);
OAI22X1TS U5024 ( .A0(n1891), .A1(n2739), .B0(n2025), .B1(n2315), .Y(n2135)
);
XNOR2X1TS U5025 ( .A(n921), .B(n2469), .Y(n2054) );
OAI22X1TS U5026 ( .A0(n2054), .A1(n2559), .B0(n1896), .B1(n1895), .Y(n2133)
);
INVX2TS U5027 ( .A(n1953), .Y(n1900) );
OAI21X4TS U5028 ( .A0(n818), .A1(n1903), .B0(n1902), .Y(n1906) );
CLKINVX1TS U5029 ( .A(n1954), .Y(n1904) );
NAND2X2TS U5030 ( .A(Op_MY[46]), .B(Op_MY[19]), .Y(n1952) );
NAND2X1TS U5031 ( .A(n1904), .B(n1952), .Y(n1905) );
XNOR2X4TS U5032 ( .A(n1906), .B(n1905), .Y(n3249) );
XNOR2X1TS U5033 ( .A(n3334), .B(n2287), .Y(n2120) );
OAI22X1TS U5034 ( .A0(n1907), .A1(n2363), .B0(n2120), .B1(n1974), .Y(n2150)
);
XNOR2X1TS U5035 ( .A(n2869), .B(n1979), .Y(n2031) );
OAI22X1TS U5036 ( .A0(n2044), .A1(n2940), .B0(n1909), .B1(n889), .Y(n2051)
);
XNOR2X1TS U5037 ( .A(n860), .B(n2070), .Y(n2022) );
OAI22X1TS U5038 ( .A0(n2022), .A1(n3427), .B0(n1910), .B1(n934), .Y(n2050)
);
CMPR32X2TS U5039 ( .A(n1928), .B(n1927), .C(n1926), .CO(n1865), .S(n1933) );
NAND2X4TS U5040 ( .A(n1947), .B(n7393), .Y(n1949) );
NAND2X2TS U5041 ( .A(n1941), .B(n1940), .Y(n7389) );
OAI21X4TS U5042 ( .A0(n7388), .A1(n7385), .B0(n7389), .Y(n7233) );
NAND2X4TS U5043 ( .A(n1943), .B(n1942), .Y(n7395) );
AOI21X4TS U5044 ( .A0(n1947), .A1(n7233), .B0(n1946), .Y(n1948) );
OAI21X4TS U5045 ( .A0(n7155), .A1(n1949), .B0(n1948), .Y(n7131) );
OAI21X4TS U5046 ( .A0(n1954), .A1(n1953), .B0(n1952), .Y(n1955) );
AOI21X4TS U5047 ( .A0(n1957), .A1(n1956), .B0(n1955), .Y(n2247) );
INVX4TS U5048 ( .A(n2247), .Y(n2002) );
INVX2TS U5049 ( .A(n1967), .Y(n1961) );
NAND2X2TS U5050 ( .A(Op_MY[48]), .B(Op_MY[21]), .Y(n1966) );
NAND2X1TS U5051 ( .A(n1961), .B(n1966), .Y(n1962) );
XNOR2X4TS U5052 ( .A(n1963), .B(n1962), .Y(n1964) );
XNOR2X1TS U5053 ( .A(n3338), .B(n2287), .Y(n2058) );
OAI21X4TS U5054 ( .A0(n1967), .A1(n1975), .B0(n1966), .Y(n2243) );
INVX2TS U5055 ( .A(n2236), .Y(n1970) );
NAND2X2TS U5056 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n2240) );
NAND2X1TS U5057 ( .A(n1970), .B(n2240), .Y(n1971) );
XNOR2X4TS U5058 ( .A(n1972), .B(n1971), .Y(n1973) );
OAI22X1TS U5059 ( .A0(n2058), .A1(n2477), .B0(n2009), .B1(n1974), .Y(n2118)
);
NAND2X1TS U5060 ( .A(n1976), .B(n1975), .Y(n1977) );
XNOR2X4TS U5061 ( .A(n1978), .B(n1977), .Y(n2945) );
XNOR2X1TS U5062 ( .A(n915), .B(n2468), .Y(n2010) );
OAI22X1TS U5063 ( .A0(n2059), .A1(n2560), .B0(n2010), .B1(n2510), .Y(n2117)
);
XNOR2X1TS U5064 ( .A(n3285), .B(n2822), .Y(n2023) );
OAI22X1TS U5065 ( .A0(n2023), .A1(n3222), .B0(n2017), .B1(n2303), .Y(n2021)
);
XNOR2X1TS U5066 ( .A(n3368), .B(n1979), .Y(n2014) );
OAI22X1TS U5067 ( .A0(n2030), .A1(n933), .B0(n2014), .B1(n2715), .Y(n2020)
);
NOR2X2TS U5068 ( .A(Op_MX[19]), .B(Op_MX[46]), .Y(n1980) );
XNOR2X4TS U5069 ( .A(n1985), .B(n1980), .Y(n1984) );
NAND2X2TS U5070 ( .A(n1982), .B(n1981), .Y(n1983) );
XOR2X4TS U5071 ( .A(n1984), .B(n1983), .Y(n1990) );
XNOR2X4TS U5072 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n2076) );
XOR2X1TS U5073 ( .A(n1986), .B(n2076), .Y(n1987) );
NAND2X2TS U5074 ( .A(Op_MX[20]), .B(Op_MX[47]), .Y(n1988) );
NAND2X4TS U5075 ( .A(n1989), .B(n1988), .Y(n2077) );
XOR2X4TS U5076 ( .A(n2077), .B(n2076), .Y(n2692) );
BUFX4TS U5077 ( .A(n1990), .Y(n3335) );
OAI22X2TS U5078 ( .A0(n3419), .A1(n2692), .B0(n1991), .B1(n3335), .Y(n2090)
);
INVX8TS U5079 ( .A(n2692), .Y(n3230) );
XNOR2X2TS U5080 ( .A(n859), .B(n3230), .Y(n2087) );
XNOR2X1TS U5081 ( .A(n741), .B(n2518), .Y(n2092) );
OAI22X1TS U5082 ( .A0(n2092), .A1(n3031), .B0(n1994), .B1(n3415), .Y(n2012)
);
NOR2BX1TS U5083 ( .AN(n7232), .B(n1990), .Y(n2043) );
ADDHX1TS U5084 ( .A(n1996), .B(n1995), .CO(n2041), .S(n2028) );
XNOR2X1TS U5085 ( .A(n922), .B(n2583), .Y(n2105) );
OAI22X1TS U5086 ( .A0(n2105), .A1(n2459), .B0(n2366), .B1(n2315), .Y(n2390)
);
INVX2TS U5087 ( .A(n2237), .Y(n1997) );
NOR2X2TS U5088 ( .A(n1997), .B(n2236), .Y(n2001) );
INVX2TS U5089 ( .A(n2243), .Y(n1999) );
OAI21X1TS U5090 ( .A0(n1999), .A1(n2236), .B0(n2240), .Y(n2000) );
NAND2X1TS U5091 ( .A(n2005), .B(n2239), .Y(n2006) );
XNOR2X4TS U5092 ( .A(n2007), .B(n2006), .Y(n2008) );
OAI22X1TS U5093 ( .A0(n2009), .A1(n2477), .B0(n2364), .B1(n2476), .Y(n2389)
);
XNOR2X1TS U5094 ( .A(n2869), .B(n2294), .Y(n2295) );
XNOR2X1TS U5095 ( .A(n3165), .B(n2294), .Y(n2015) );
OAI22X1TS U5096 ( .A0(n2295), .A1(n2940), .B0(n2015), .B1(n890), .Y(n2352)
);
XNOR2X1TS U5097 ( .A(n907), .B(n2518), .Y(n2093) );
OAI22X1TS U5098 ( .A0(n2277), .A1(n3031), .B0(n2093), .B1(n3415), .Y(n2351)
);
XNOR2X1TS U5099 ( .A(n860), .B(n2264), .Y(n2331) );
XNOR2X1TS U5100 ( .A(n911), .B(n2264), .Y(n2098) );
OAI22X1TS U5101 ( .A0(n2331), .A1(n2976), .B0(n2098), .B1(n3006), .Y(n2350)
);
XNOR2X1TS U5102 ( .A(n3338), .B(n2468), .Y(n2369) );
OAI22X1TS U5103 ( .A0(n2010), .A1(n2560), .B0(n2369), .B1(n2510), .Y(n2402)
);
ADDFHX2TS U5104 ( .A(n2013), .B(n2012), .CI(n2011), .CO(n2034), .S(n2019) );
XNOR2X1TS U5105 ( .A(n901), .B(n2070), .Y(n2071) );
OAI22X1TS U5106 ( .A0(n2062), .A1(n3201), .B0(n2071), .B1(n2817), .Y(n2033)
);
XNOR2X1TS U5107 ( .A(n917), .B(n3190), .Y(n2069) );
OAI22X1TS U5108 ( .A0(n2014), .A1(n932), .B0(n2069), .B1(n2715), .Y(n2032)
);
XNOR2X1TS U5109 ( .A(n2878), .B(n2294), .Y(n2065) );
OAI22X1TS U5110 ( .A0(n2065), .A1(n3279), .B0(n2015), .B1(n2762), .Y(n2037)
);
XNOR2X1TS U5111 ( .A(n3176), .B(n2881), .Y(n2091) );
OAI22X1TS U5112 ( .A0(n2017), .A1(n2730), .B0(n2091), .B1(n2016), .Y(n2036)
);
BUFX3TS U5113 ( .A(n2018), .Y(n2772) );
XNOR2X1TS U5114 ( .A(n2873), .B(n2771), .Y(n2038) );
OAI22X1TS U5115 ( .A0(n2101), .A1(n2772), .B0(n2038), .B1(n928), .Y(n2035)
);
ADDFHX2TS U5116 ( .A(n2021), .B(n2020), .CI(n2019), .CO(n2116), .S(n2129) );
OAI22X1TS U5117 ( .A0(n2022), .A1(n3201), .B0(n2061), .B1(n2817), .Y(n2132)
);
OAI22X1TS U5118 ( .A0(n2024), .A1(n2730), .B0(n2023), .B1(n2303), .Y(n2131)
);
XNOR2X1TS U5119 ( .A(n3303), .B(n2653), .Y(n2046) );
OAI22X1TS U5120 ( .A0(n2046), .A1(n2787), .B0(n2025), .B1(n2045), .Y(n2130)
);
ADDFHX2TS U5121 ( .A(n2028), .B(n2027), .CI(n2026), .CO(n2126), .S(n2121) );
XNOR2X1TS U5122 ( .A(n913), .B(n2771), .Y(n2039) );
OAI22X1TS U5123 ( .A0(n2031), .A1(n932), .B0(n2030), .B1(n2715), .Y(n2124)
);
ADDFHX2TS U5124 ( .A(n2034), .B(n2033), .CI(n2032), .CO(n2401), .S(n2068) );
OAI22X1TS U5125 ( .A0(n2039), .A1(n928), .B0(n2038), .B1(n2497), .Y(n2049)
);
XNOR2X1TS U5126 ( .A(n906), .B(n2264), .Y(n2063) );
OAI22X1TS U5127 ( .A0(n2063), .A1(n2976), .B0(n2040), .B1(n3006), .Y(n2057)
);
OAI22X1TS U5128 ( .A0(n2044), .A1(n3279), .B0(n2064), .B1(n2762), .Y(n2055)
);
XNOR2X1TS U5129 ( .A(n921), .B(n2653), .Y(n2106) );
OAI22X1TS U5130 ( .A0(n2106), .A1(n1828), .B0(n2046), .B1(n2045), .Y(n2047)
);
ADDFHX2TS U5131 ( .A(n2049), .B(n2048), .CI(n2047), .CO(n2066), .S(n2159) );
XNOR2X1TS U5132 ( .A(n922), .B(n2468), .Y(n2060) );
OAI22X1TS U5133 ( .A0(n2054), .A1(n2368), .B0(n2060), .B1(n2053), .Y(n2137)
);
XNOR2X1TS U5134 ( .A(n3384), .B(n2287), .Y(n2119) );
OAI22X1TS U5135 ( .A0(n2119), .A1(n2477), .B0(n2058), .B1(n2476), .Y(n2112)
);
OAI22X1TS U5136 ( .A0(n2060), .A1(n2368), .B0(n2059), .B1(n2510), .Y(n2111)
);
OAI22X1TS U5137 ( .A0(n2065), .A1(n2940), .B0(n2064), .B1(n889), .Y(n2102)
);
OAI22X1TS U5138 ( .A0(n2069), .A1(n933), .B0(n2333), .B1(n2715), .Y(n2372)
);
XNOR2X1TS U5139 ( .A(n3368), .B(n2070), .Y(n2293) );
OAI22X1TS U5140 ( .A0(n2071), .A1(n3201), .B0(n2293), .B1(n2817), .Y(n2371)
);
XNOR2X4TS U5141 ( .A(Op_MX[50]), .B(Op_MX[23]), .Y(n2201) );
NAND2X4TS U5142 ( .A(n2073), .B(n2072), .Y(n2200) );
XNOR2X4TS U5143 ( .A(n2201), .B(n2200), .Y(n2074) );
XOR2X4TS U5144 ( .A(Op_MX[22]), .B(Op_MX[49]), .Y(n2080) );
XNOR2X4TS U5145 ( .A(n2080), .B(n2075), .Y(n2079) );
NAND2X4TS U5146 ( .A(n2077), .B(n2076), .Y(n2078) );
XOR2X4TS U5147 ( .A(n2079), .B(n2078), .Y(n2946) );
NOR2X2TS U5148 ( .A(n3612), .B(n2080), .Y(n2081) );
XOR2X1TS U5149 ( .A(n2081), .B(n2201), .Y(n2082) );
XNOR2X2TS U5150 ( .A(n859), .B(n3329), .Y(n2210) );
XNOR2X1TS U5151 ( .A(n2223), .B(n3329), .Y(n2085) );
OAI22X2TS U5152 ( .A0(n2210), .A1(n3089), .B0(n2085), .B1(n2084), .Y(n2212)
);
OAI22X1TS U5153 ( .A0(n2271), .A1(n3188), .B0(n2088), .B1(n3231), .Y(n2297)
);
NOR2BX1TS U5154 ( .AN(n1029), .B(n2946), .Y(n2096) );
OAI22X2TS U5155 ( .A0(n2088), .A1(n3188), .B0(n2087), .B1(n3231), .Y(n2095)
);
CMPR22X2TS U5156 ( .A(n2090), .B(n2089), .CO(n2094), .S(n2013) );
OAI22X1TS U5157 ( .A0(n2091), .A1(n3179), .B0(n2334), .B1(n2303), .Y(n2387)
);
OAI22X1TS U5158 ( .A0(n2093), .A1(n3031), .B0(n2092), .B1(n3415), .Y(n2109)
);
ADDFHX2TS U5159 ( .A(n2096), .B(n2095), .CI(n2094), .CO(n2296), .S(n2108) );
OAI22X1TS U5160 ( .A0(n2099), .A1(n3432), .B0(n2098), .B1(n3290), .Y(n2107)
);
OAI22X1TS U5161 ( .A0(n2349), .A1(n2772), .B0(n2101), .B1(n2809), .Y(n2385)
);
OAI22X1TS U5162 ( .A0(n2106), .A1(n2459), .B0(n2105), .B1(n2315), .Y(n2114)
);
ADDFHX2TS U5163 ( .A(n2109), .B(n2108), .CI(n2107), .CO(n2386), .S(n2113) );
OAI22X1TS U5164 ( .A0(n2120), .A1(n2477), .B0(n2119), .B1(n2476), .Y(n2153)
);
NOR2X4TS U5165 ( .A(n2181), .B(n2182), .Y(n7147) );
NAND2X4TS U5166 ( .A(n2184), .B(n2183), .Y(n7148) );
NAND2X4TS U5167 ( .A(n2188), .B(n2187), .Y(n7144) );
INVX4TS U5168 ( .A(n7138), .Y(n2191) );
AOI21X4TS U5169 ( .A0(n7139), .A1(n7134), .B0(n2191), .Y(n2192) );
OAI21X4TS U5170 ( .A0(n2193), .A1(n7133), .B0(n2192), .Y(n2194) );
AOI21X4TS U5171 ( .A0(n7131), .A1(n2195), .B0(n2194), .Y(n7127) );
NAND2X4TS U5172 ( .A(n2197), .B(n2196), .Y(n2218) );
XOR2X4TS U5173 ( .A(n2218), .B(Op_MX[25]), .Y(n3129) );
NAND2BX1TS U5174 ( .AN(n2223), .B(n2871), .Y(n2208) );
NOR2X2TS U5175 ( .A(Op_MX[50]), .B(Op_MX[23]), .Y(n2199) );
XNOR2X4TS U5176 ( .A(n2204), .B(n2199), .Y(n2203) );
NOR2X2TS U5177 ( .A(n2205), .B(n2204), .Y(n2206) );
NAND2X6TS U5178 ( .A(n3118), .B(n2207), .Y(n2225) );
OAI22X2TS U5179 ( .A0(n2208), .A1(n3118), .B0(n2225), .B1(n2937), .Y(n2229)
);
XNOR2X2TS U5180 ( .A(n858), .B(n3358), .Y(n2226) );
OAI22X2TS U5181 ( .A0(n2226), .A1(n3118), .B0(n2209), .B1(n2225), .Y(n2228)
);
NOR2BX1TS U5182 ( .AN(n1029), .B(n2956), .Y(n2275) );
OAI22X2TS U5183 ( .A0(n2211), .A1(n3089), .B0(n2210), .B1(n931), .Y(n2274)
);
CMPR22X2TS U5184 ( .A(n2213), .B(n2212), .CO(n2273), .S(n2298) );
OAI22X1TS U5185 ( .A0(n2265), .A1(n3432), .B0(n2230), .B1(n3290), .Y(n2325)
);
BUFX3TS U5186 ( .A(n2214), .Y(n3344) );
OAI22X1TS U5187 ( .A0(n2270), .A1(n3201), .B0(n2217), .B1(n3344), .Y(n2324)
);
XNOR2X1TS U5188 ( .A(n3165), .B(n2518), .Y(n2312) );
OAI22X1TS U5189 ( .A0(n2266), .A1(n3250), .B0(n2312), .B1(n3411), .Y(n2269)
);
OAI22X1TS U5190 ( .A0(n2319), .A1(n3279), .B0(n2216), .B1(n2762), .Y(n2268)
);
XNOR2X1TS U5191 ( .A(n914), .B(n3227), .Y(n2235) );
BUFX3TS U5192 ( .A(n2215), .Y(n3228) );
XNOR2X2TS U5193 ( .A(n2873), .B(n3227), .Y(n2318) );
OAI22X1TS U5194 ( .A0(n2235), .A1(n3228), .B0(n2318), .B1(n932), .Y(n2267)
);
OAI22X1TS U5195 ( .A0(n2217), .A1(n934), .B0(n2500), .B1(n2817), .Y(n2463)
);
XOR2X4TS U5196 ( .A(n2219), .B(n3813), .Y(n2941) );
OAI21X1TS U5197 ( .A0(n2713), .A1(n971), .B0(n2220), .Y(n2506) );
XNOR2X1TS U5198 ( .A(n2222), .B(n2221), .Y(n2504) );
BUFX8TS U5199 ( .A(n2713), .Y(n2966) );
OAI22X1TS U5200 ( .A0(n2504), .A1(n3154), .B0(n2224), .B1(n2966), .Y(n2505)
);
XNOR2X1TS U5201 ( .A(n1352), .B(n2871), .Y(n2502) );
OAI22X1TS U5202 ( .A0(n2502), .A1(n3118), .B0(n2227), .B1(n3376), .Y(n2472)
);
NOR2BX1TS U5203 ( .AN(n2198), .B(n2941), .Y(n2234) );
OAI22X2TS U5204 ( .A0(n2227), .A1(n3118), .B0(n2226), .B1(n930), .Y(n2233)
);
XNOR2X1TS U5205 ( .A(n916), .B(n2264), .Y(n2481) );
OAI22X1TS U5206 ( .A0(n2230), .A1(n3432), .B0(n2481), .B1(n3290), .Y(n2490)
);
ADDFHX2TS U5207 ( .A(n2234), .B(n2233), .CI(n2232), .CO(n2471), .S(n2256) );
OAI22X1TS U5208 ( .A0(n2263), .A1(n3336), .B0(n2314), .B1(n3335), .Y(n2255)
);
OAI22X1TS U5209 ( .A0(n2513), .A1(n3228), .B0(n2235), .B1(n932), .Y(n2488)
);
NOR2X4TS U5210 ( .A(n2241), .B(n2236), .Y(n2244) );
AOI21X4TS U5211 ( .A0(n2244), .A1(n2243), .B0(n2242), .Y(n2245) );
OAI21X4TS U5212 ( .A0(n2247), .A1(n2246), .B0(n2245), .Y(n2279) );
OAI21X4TS U5213 ( .A0(n818), .A1(n2260), .B0(n2248), .Y(n2249) );
XNOR2X4TS U5214 ( .A(n2249), .B(n1017), .Y(n2950) );
NAND2X2TS U5215 ( .A(n2278), .B(n1030), .Y(n2253) );
AOI21X2TS U5216 ( .A0(n2279), .A1(n1030), .B0(n2251), .Y(n2252) );
OAI21X4TS U5217 ( .A0(n817), .A1(n2253), .B0(n2252), .Y(n3226) );
ADDFHX2TS U5218 ( .A(n2257), .B(n2256), .CI(n2255), .CO(n2489), .S(n2301) );
INVX2TS U5219 ( .A(n2283), .Y(n2258) );
XNOR2X1TS U5220 ( .A(n753), .B(n2632), .Y(n2288) );
OAI22X1TS U5221 ( .A0(n2288), .A1(n2477), .B0(n2262), .B1(n2476), .Y(n2300)
);
OAI22X1TS U5222 ( .A0(n2263), .A1(n3188), .B0(n2272), .B1(n3231), .Y(n2291)
);
XNOR2X1TS U5223 ( .A(n2577), .B(n2518), .Y(n2276) );
OAI22X1TS U5224 ( .A0(n2266), .A1(n3031), .B0(n2276), .B1(n935), .Y(n2289)
);
OAI22X1TS U5225 ( .A0(n2292), .A1(n3201), .B0(n2270), .B1(n2817), .Y(n2341)
);
OAI22X1TS U5226 ( .A0(n2277), .A1(n3250), .B0(n2276), .B1(n3411), .Y(n2345)
);
INVX2TS U5227 ( .A(n2278), .Y(n2282) );
INVX2TS U5228 ( .A(n2279), .Y(n2280) );
NAND2X1TS U5229 ( .A(n2284), .B(n2283), .Y(n2285) );
XNOR2X4TS U5230 ( .A(n2286), .B(n2285), .Y(n2957) );
XNOR2X1TS U5231 ( .A(n912), .B(n2632), .Y(n2362) );
OAI22X1TS U5232 ( .A0(n2362), .A1(n2477), .B0(n2288), .B1(n2476), .Y(n2355)
);
XNOR2X1TS U5233 ( .A(n3287), .B(n2720), .Y(n2348) );
OAI22X1TS U5234 ( .A0(n2348), .A1(n2809), .B0(n2307), .B1(n2497), .Y(n2354)
);
OAI22X1TS U5235 ( .A0(n2365), .A1(n2739), .B0(n2317), .B1(n2787), .Y(n2357)
);
OAI22X1TS U5236 ( .A0(n2293), .A1(n3201), .B0(n2292), .B1(n2817), .Y(n2375)
);
XNOR2X1TS U5237 ( .A(n2474), .B(n2294), .Y(n2320) );
OAI22X1TS U5238 ( .A0(n2295), .A1(n3279), .B0(n2320), .B1(n2762), .Y(n2374)
);
ADDFHX2TS U5239 ( .A(n2298), .B(n2297), .CI(n2296), .CO(n2373), .S(n2370) );
OAI22X1TS U5240 ( .A0(n2305), .A1(n2730), .B0(n2304), .B1(n2303), .Y(n2309)
);
OAI22X1TS U5241 ( .A0(n2307), .A1(n928), .B0(n2306), .B1(n2772), .Y(n2308)
);
CMPR32X2TS U5242 ( .A(n2310), .B(n2309), .C(n2308), .CO(n2550), .S(n2359) );
OAI22X1TS U5243 ( .A0(n2311), .A1(n2560), .B0(n2512), .B1(n2510), .Y(n2509)
);
OAI22X1TS U5244 ( .A0(n2316), .A1(n2739), .B0(n2460), .B1(n2787), .Y(n2508)
);
XNOR2X1TS U5245 ( .A(n2869), .B(n2518), .Y(n2475) );
OAI22X1TS U5246 ( .A0(n2503), .A1(n3089), .B0(n2313), .B1(n931), .Y(n2515)
);
OAI22X1TS U5247 ( .A0(n2479), .A1(n3188), .B0(n2314), .B1(n3231), .Y(n2514)
);
OAI22X1TS U5248 ( .A0(n2317), .A1(n2739), .B0(n2316), .B1(n2315), .Y(n2329)
);
ADDFHX2TS U5249 ( .A(n2323), .B(n2322), .CI(n2321), .CO(n2326), .S(n2336) );
OAI22X1TS U5250 ( .A0(n2331), .A1(n3432), .B0(n2330), .B1(n3290), .Y(n2378)
);
OAI22X1TS U5251 ( .A0(n2333), .A1(n2839), .B0(n2332), .B1(n3228), .Y(n2377)
);
OAI22X1TS U5252 ( .A0(n2335), .A1(n3178), .B0(n2334), .B1(n3222), .Y(n2376)
);
ADDFHX2TS U5253 ( .A(n2347), .B(n2346), .CI(n2345), .CO(n2339), .S(n2393) );
OAI22X1TS U5254 ( .A0(n2349), .A1(n2809), .B0(n2348), .B1(n2497), .Y(n2392)
);
ADDFHX2TS U5255 ( .A(n2358), .B(n2357), .CI(n2356), .CO(n2361), .S(n2394) );
OAI22X1TS U5256 ( .A0(n2364), .A1(n2363), .B0(n2362), .B1(n2476), .Y(n2399)
);
OAI22X1TS U5257 ( .A0(n2366), .A1(n2739), .B0(n2365), .B1(n1828), .Y(n2398)
);
OAI22X1TS U5258 ( .A0(n2369), .A1(n2368), .B0(n2367), .B1(n2510), .Y(n2397)
);
ADDFHX2TS U5259 ( .A(n2396), .B(n2395), .CI(n2394), .CO(n2408), .S(n2422) );
CMPR32X2TS U5260 ( .A(n2399), .B(n2398), .C(n2397), .CO(n2420), .S(n2432) );
ADDFHX4TS U5261 ( .A(n2411), .B(n2410), .CI(n2409), .CO(n2438), .S(n2434) );
ADDFHX2TS U5262 ( .A(n2420), .B(n2419), .CI(n2418), .CO(n2406), .S(n2440) );
OAI21X4TS U5263 ( .A0(n7127), .A1(n2455), .B0(n2454), .Y(n7123) );
OAI22X1TS U5264 ( .A0(n2460), .A1(n2459), .B0(n2541), .B1(n1828), .Y(n2547)
);
OAI22X1TS U5265 ( .A0(n2461), .A1(n3179), .B0(n2470), .B1(n2016), .Y(n2546)
);
ADDFHX2TS U5266 ( .A(n2464), .B(n2463), .CI(n2462), .CO(n2545), .S(n2465) );
ADDFHX2TS U5267 ( .A(n2467), .B(n2466), .CI(n2465), .CO(n2551), .S(n2556) );
OAI22X1TS U5268 ( .A0(n2498), .A1(n2809), .B0(n2588), .B1(n2772), .Y(n2585)
);
ADDFHX2TS U5269 ( .A(n2473), .B(n2472), .CI(n2471), .CO(n2484), .S(n2462) );
XNOR2X1TS U5270 ( .A(n2518), .B(n2474), .Y(n2519) );
OAI22X1TS U5271 ( .A0(n2475), .A1(n3250), .B0(n2519), .B1(n3411), .Y(n2483)
);
OAI22X1TS U5272 ( .A0(n2478), .A1(n2477), .B0(n1007), .B1(n2476), .Y(n2482)
);
XNOR2X1TS U5273 ( .A(n3330), .B(n3343), .Y(n2589) );
XNOR2X1TS U5274 ( .A(n914), .B(n3343), .Y(n2501) );
OAI22X1TS U5275 ( .A0(n2589), .A1(n3344), .B0(n2501), .B1(n934), .Y(n2598)
);
BUFX3TS U5276 ( .A(n1710), .Y(n3401) );
XNOR2X1TS U5277 ( .A(n917), .B(n3348), .Y(n2522) );
OAI22X1TS U5278 ( .A0(n2481), .A1(n3432), .B0(n2522), .B1(n3290), .Y(n2485)
);
ADDFHX2TS U5279 ( .A(n2484), .B(n2483), .CI(n2482), .CO(n2599), .S(n2493) );
ADDFHX2TS U5280 ( .A(n2493), .B(n2492), .CI(n2491), .CO(n2594), .S(n2674) );
ADDFHX2TS U5281 ( .A(n2496), .B(n2495), .CI(n2494), .CO(n2673), .S(n2555) );
OAI22X1TS U5282 ( .A0(n2501), .A1(n3344), .B0(n2500), .B1(n934), .Y(n2527)
);
OAI22X1TS U5283 ( .A0(n2533), .A1(n3118), .B0(n2502), .B1(n3376), .Y(n2525)
);
BUFX3TS U5284 ( .A(n2946), .Y(n3405) );
NOR2BX1TS U5285 ( .AN(n7232), .B(n971), .Y(n2539) );
XNOR2X1TS U5286 ( .A(n2221), .B(n732), .Y(n2536) );
OAI22X1TS U5287 ( .A0(n2536), .A1(n3154), .B0(n2504), .B1(n2966), .Y(n2538)
);
OAI22X1TS U5288 ( .A0(n2512), .A1(n2560), .B0(n2511), .B1(n2510), .Y(n2544)
);
XNOR2X1TS U5289 ( .A(n922), .B(n3190), .Y(n2540) );
OAI22X1TS U5290 ( .A0(n2513), .A1(n933), .B0(n2540), .B1(n2715), .Y(n2543)
);
OAI22X1TS U5291 ( .A0(n2557), .A1(n3188), .B0(n2517), .B1(n3231), .Y(n2603)
);
OAI22X1TS U5292 ( .A0(n2519), .A1(n3250), .B0(n2562), .B1(n3411), .Y(n2602)
);
XNOR2X1TS U5293 ( .A(n3359), .B(n2939), .Y(n2565) );
OAI22X1TS U5294 ( .A0(n2520), .A1(n890), .B0(n2565), .B1(n2762), .Y(n2601)
);
OAI22X1TS U5295 ( .A0(n2558), .A1(n3089), .B0(n2521), .B1(n931), .Y(n2606)
);
OAI22X1TS U5296 ( .A0(n2522), .A1(n3432), .B0(n2564), .B1(n3290), .Y(n2605)
);
ADDFHX2TS U5297 ( .A(n2525), .B(n2524), .CI(n2523), .CO(n2604), .S(n2526) );
ADDFHX2TS U5298 ( .A(n2531), .B(n2530), .CI(n2529), .CO(n2611), .S(n2672) );
OAI22X1TS U5299 ( .A0(n2579), .A1(n3118), .B0(n2533), .B1(n3376), .Y(n2574)
);
INVX2TS U5300 ( .A(n859), .Y(n2535) );
OAI22X1TS U5301 ( .A0(n2540), .A1(n933), .B0(n2590), .B1(n2715), .Y(n2567)
);
OAI22X1TS U5302 ( .A0(n2541), .A1(n2739), .B0(n2584), .B1(n1828), .Y(n2566)
);
XNOR2X2TS U5303 ( .A(n2650), .B(n900), .Y(n2651) );
OAI22X2TS U5304 ( .A0(n2557), .A1(n3336), .B0(n2651), .B1(n3335), .Y(n2648)
);
OAI22X1TS U5305 ( .A0(n2561), .A1(n2560), .B0(n2559), .B1(n736), .Y(n2646)
);
XNOR2X1TS U5306 ( .A(n917), .B(n3409), .Y(n2617) );
OAI22X1TS U5307 ( .A0(n2562), .A1(n3250), .B0(n2617), .B1(n3411), .Y(n2615)
);
BUFX3TS U5308 ( .A(n2563), .Y(n3430) );
XNOR2X1TS U5309 ( .A(n914), .B(n2939), .Y(n2645) );
OAI22X1TS U5310 ( .A0(n2645), .A1(n2940), .B0(n2565), .B1(n889), .Y(n2613)
);
ADDFHX2TS U5311 ( .A(n2571), .B(n2570), .CI(n2569), .CO(n2661), .S(n2610) );
BUFX3TS U5312 ( .A(n2956), .Y(n3360) );
INVX2TS U5313 ( .A(n857), .Y(n2581) );
XNOR2X2TS U5314 ( .A(n906), .B(n4730), .Y(n2633) );
OAI22X2TS U5315 ( .A0(n2633), .A1(n3154), .B0(n2582), .B1(n2966), .Y(n2630)
);
OAI22X1TS U5316 ( .A0(n2584), .A1(n2739), .B0(n2654), .B1(n1828), .Y(n2621)
);
OAI22X1TS U5317 ( .A0(n2589), .A1(n3201), .B0(n2634), .B1(n2817), .Y(n2637)
);
OAI22X1TS U5318 ( .A0(n2590), .A1(n933), .B0(n2635), .B1(n3228), .Y(n2636)
);
OAI22X1TS U5319 ( .A0(n2600), .A1(n3179), .B0(n2655), .B1(n2016), .Y(n2641)
);
CMPR32X2TS U5320 ( .A(n2606), .B(n2605), .C(n2604), .CO(n2639), .S(n2608) );
CMPR32X2TS U5321 ( .A(n2615), .B(n2614), .C(n2613), .CO(n2746), .S(n2658) );
OAI22X1TS U5322 ( .A0(n2736), .A1(n3118), .B0(n2616), .B1(n930), .Y(n2699)
);
XNOR2X1TS U5323 ( .A(n3364), .B(n2997), .Y(n2695) );
OAI22X1TS U5324 ( .A0(n2617), .A1(n3250), .B0(n2695), .B1(n3411), .Y(n2698)
);
INVX2TS U5325 ( .A(n741), .Y(n2629) );
XNOR2X1TS U5326 ( .A(n2789), .B(n4730), .Y(n2714) );
OAI22X1TS U5327 ( .A0(n2714), .A1(n3154), .B0(n2633), .B1(n2966), .Y(n2706)
);
XNOR2X1TS U5328 ( .A(n3338), .B(n3190), .Y(n2716) );
OAI22X1TS U5329 ( .A0(n2635), .A1(n932), .B0(n2716), .B1(n3228), .Y(n2700)
);
OAI22X1TS U5330 ( .A0(n2722), .A1(n3401), .B0(n2645), .B1(n889), .Y(n2743)
);
ADDFHX2TS U5331 ( .A(n2648), .B(n2647), .CI(n2646), .CO(n2742), .S(n2659) );
XNOR2X1TS U5332 ( .A(n2869), .B(n2784), .Y(n2737) );
OAI22X1TS U5333 ( .A0(n2737), .A1(n3089), .B0(n2649), .B1(n931), .Y(n2734)
);
OAI22X1TS U5334 ( .A0(n2651), .A1(n2086), .B0(n2693), .B1(n3335), .Y(n2733)
);
XNOR2X1TS U5335 ( .A(n3359), .B(n2944), .Y(n2696) );
OAI22X1TS U5336 ( .A0(n2652), .A1(n3350), .B0(n2696), .B1(n3290), .Y(n2732)
);
XNOR2X1TS U5337 ( .A(n853), .B(n2653), .Y(n2740) );
OAI22X1TS U5338 ( .A0(n2654), .A1(n2739), .B0(n2740), .B1(n2787), .Y(n2719)
);
XNOR2X1TS U5339 ( .A(n3349), .B(n2822), .Y(n2731) );
OAI22X1TS U5340 ( .A0(n2655), .A1(n2730), .B0(n2731), .B1(n2016), .Y(n2718)
);
OAI22X1TS U5341 ( .A0(n2656), .A1(n2809), .B0(n2721), .B1(n2772), .Y(n2717)
);
ADDFHX2TS U5342 ( .A(n2659), .B(n2658), .CI(n2657), .CO(n2727), .S(n2662) );
ADDFHX2TS U5343 ( .A(n2662), .B(n2661), .CI(n813), .CO(n2724), .S(n2668) );
ADDFHX2TS U5344 ( .A(n2665), .B(n2664), .CI(n2663), .CO(n2689), .S(n2666) );
ADDFHX2TS U5345 ( .A(n2674), .B(n2673), .CI(n2672), .CO(n2591), .S(n2688) );
XNOR2X4TS U5346 ( .A(n2678), .B(n2687), .Y(n2912) );
ADDFHX4TS U5347 ( .A(n2684), .B(n2683), .CI(n2682), .CO(n2916), .S(n2914) );
OAI21X4TS U5348 ( .A0(n2687), .A1(n2688), .B0(n2685), .Y(n2686) );
OAI2BB1X4TS U5349 ( .A0N(n2688), .A1N(n2687), .B0(n2686), .Y(n2913) );
INVX4TS U5350 ( .A(n2692), .Y(n3383) );
OAI22X1TS U5351 ( .A0(n2693), .A1(n3336), .B0(n2757), .B1(n3335), .Y(n2755)
);
XNOR2X2TS U5352 ( .A(n913), .B(n2997), .Y(n2758) );
BUFX3TS U5353 ( .A(n2694), .Y(n3413) );
OAI22X1TS U5354 ( .A0(n2695), .A1(n3250), .B0(n2758), .B1(n3413), .Y(n2754)
);
OAI22X1TS U5355 ( .A0(n2764), .A1(n3430), .B0(n2696), .B1(n3006), .Y(n2753)
);
INVX2TS U5356 ( .A(n906), .Y(n2710) );
NOR2X2TS U5357 ( .A(n2710), .B(n971), .Y(n2827) );
INVX2TS U5358 ( .A(n2827), .Y(n2767) );
BUFX4TS U5359 ( .A(n2713), .Y(n3155) );
BUFX3TS U5360 ( .A(n3155), .Y(n3424) );
XNOR2X1TS U5361 ( .A(n2577), .B(n4730), .Y(n2756) );
BUFX3TS U5362 ( .A(n2941), .Y(n3365) );
OAI22X1TS U5363 ( .A0(n2714), .A1(n3424), .B0(n2756), .B1(n3365), .Y(n2765)
);
XNOR2X1TS U5364 ( .A(n919), .B(n3190), .Y(n2775) );
OAI22X1TS U5365 ( .A0(n2716), .A1(n932), .B0(n2775), .B1(n2715), .Y(n2759)
);
OAI22X1TS U5366 ( .A0(n2722), .A1(n3279), .B0(n2763), .B1(n2762), .Y(n2769)
);
OAI22X1TS U5367 ( .A0(n2723), .A1(n3428), .B0(n2774), .B1(n3344), .Y(n2768)
);
ADDFHX4TS U5368 ( .A(n2726), .B(n2725), .CI(n2724), .CO(n2804), .S(n2690) );
XNOR2X1TS U5369 ( .A(n3278), .B(n2822), .Y(n2779) );
OAI22X1TS U5370 ( .A0(n2731), .A1(n2730), .B0(n2779), .B1(n3221), .Y(n2793)
);
XNOR2X1TS U5371 ( .A(n2735), .B(n2871), .Y(n2783) );
OAI22X1TS U5372 ( .A0(n2736), .A1(n930), .B0(n2783), .B1(n3360), .Y(n2782)
);
OAI22X1TS U5373 ( .A0(n2740), .A1(n2739), .B0(n2738), .B1(n2786), .Y(n2780)
);
CMPR32X2TS U5374 ( .A(n2743), .B(n2742), .C(n2741), .CO(n2798), .S(n2729) );
OAI22X1TS U5375 ( .A0(n2829), .A1(n3154), .B0(n2756), .B1(n2966), .Y(n2813)
);
OAI22X1TS U5376 ( .A0(n2758), .A1(n3415), .B0(n2816), .B1(n3411), .Y(n2811)
);
ADDFHX2TS U5377 ( .A(n2761), .B(n2760), .CI(n2759), .CO(n2848), .S(n2752) );
OAI22X1TS U5378 ( .A0(n2773), .A1(n928), .B0(n2810), .B1(n2772), .Y(n2832)
);
XNOR2X1TS U5379 ( .A(n3349), .B(n3190), .Y(n2840) );
OAI22X1TS U5380 ( .A0(n2775), .A1(n933), .B0(n2840), .B1(n3228), .Y(n2830)
);
OAI22X1TS U5381 ( .A0(n2779), .A1(n3179), .B0(n2823), .B1(n2016), .Y(n2847)
);
XNOR2X1TS U5382 ( .A(n2869), .B(n2871), .Y(n2814) );
OAI22X1TS U5383 ( .A0(n2814), .A1(n3118), .B0(n2783), .B1(n930), .Y(n2844)
);
OAI22X1TS U5384 ( .A0(n2785), .A1(n3407), .B0(n2807), .B1(n3405), .Y(n2843)
);
INVX2TS U5385 ( .A(n2789), .Y(n2790) );
NOR2X1TS U5386 ( .A(n2790), .B(n3583), .Y(n2826) );
ADDFHX2TS U5387 ( .A(n2802), .B(n2801), .CI(n2800), .CO(n2836), .S(n2805) );
BUFX3TS U5388 ( .A(n1990), .Y(n3417) );
OAI22X1TS U5389 ( .A0(n2806), .A1(n3336), .B0(n2874), .B1(n3417), .Y(n2868)
);
INVX4TS U5390 ( .A(n3107), .Y(n3074) );
OAI22X1TS U5391 ( .A0(n2814), .A1(n3376), .B0(n2872), .B1(n3360), .Y(n2865)
);
OAI22X1TS U5392 ( .A0(n2880), .A1(n3413), .B0(n2816), .B1(n935), .Y(n2864)
);
OAI22X1TS U5393 ( .A0(n2818), .A1(n3428), .B0(n2898), .B1(n2817), .Y(n2863)
);
XNOR2X2TS U5394 ( .A(n922), .B(n3348), .Y(n2883) );
OAI22X1TS U5395 ( .A0(n2824), .A1(n3432), .B0(n2883), .B1(n3290), .Y(n2888)
);
INVX2TS U5396 ( .A(n3182), .Y(n2886) );
XNOR2X1TS U5397 ( .A(n3165), .B(n4730), .Y(n2870) );
OAI22X1TS U5398 ( .A0(n2829), .A1(n3424), .B0(n2870), .B1(n3365), .Y(n2884)
);
ADDFHX2TS U5399 ( .A(n2838), .B(n2837), .CI(n2836), .CO(n2909), .S(n2857) );
XNOR2X1TS U5400 ( .A(n3278), .B(n3190), .Y(n2896) );
OAI22X1TS U5401 ( .A0(n2840), .A1(n933), .B0(n2896), .B1(n3228), .Y(n2895)
);
XNOR2X1TS U5402 ( .A(n3384), .B(n3346), .Y(n2897) );
OAI22X1TS U5403 ( .A0(n2841), .A1(n890), .B0(n2897), .B1(n3401), .Y(n2894)
);
CMPR32X2TS U5404 ( .A(n2850), .B(n2849), .C(n2848), .CO(n2890), .S(n2855) );
ADDFHX2TS U5405 ( .A(n2853), .B(n2852), .CI(n2851), .CO(n2906), .S(n2838) );
XNOR2X1TS U5406 ( .A(n2869), .B(Op_MX[26]), .Y(n3169) );
OAI22X1TS U5407 ( .A0(n3169), .A1(n3154), .B0(n2870), .B1(n2966), .Y(n3164)
);
OAI22X1TS U5408 ( .A0(n2872), .A1(n3376), .B0(n3168), .B1(n3360), .Y(n3163)
);
OAI22X1TS U5409 ( .A0(n2874), .A1(n3419), .B0(n3187), .B1(n3335), .Y(n3162)
);
XNOR2X1TS U5410 ( .A(n3364), .B(n3329), .Y(n3177) );
OAI22X1TS U5411 ( .A0(n2875), .A1(n3407), .B0(n3177), .B1(n3405), .Y(n3172)
);
INVX2TS U5412 ( .A(n2878), .Y(n2879) );
NOR2X1TS U5413 ( .A(n2879), .B(n971), .Y(n3181) );
XNOR2X1TS U5414 ( .A(n3330), .B(n2997), .Y(n3189) );
OAI22X1TS U5415 ( .A0(n3189), .A1(n3413), .B0(n2880), .B1(n3415), .Y(n3170)
);
OAI22X1TS U5416 ( .A0(n2882), .A1(n3179), .B0(n3180), .B1(n2016), .Y(n3186)
);
XNOR2X1TS U5417 ( .A(n3249), .B(n3348), .Y(n3203) );
OAI22X1TS U5418 ( .A0(n2883), .A1(n3432), .B0(n3203), .B1(n3290), .Y(n3185)
);
XNOR2X1TS U5419 ( .A(n753), .B(n3190), .Y(n3191) );
OAI22X1TS U5420 ( .A0(n2896), .A1(n932), .B0(n3191), .B1(n3228), .Y(n3200)
);
XNOR2X1TS U5421 ( .A(n3338), .B(n3346), .Y(n3204) );
OAI22X1TS U5422 ( .A0(n2897), .A1(n889), .B0(n3204), .B1(n3401), .Y(n3199)
);
XNOR2X1TS U5423 ( .A(n918), .B(n3275), .Y(n3202) );
OAI22X1TS U5424 ( .A0(n2898), .A1(n934), .B0(n3202), .B1(n3344), .Y(n3198)
);
CMPR32X2TS U5425 ( .A(n2901), .B(n2900), .C(n2899), .CO(n3195), .S(n2904) );
ADDFHX4TS U5426 ( .A(n2910), .B(n2909), .CI(n2908), .CO(n2928), .S(n2927) );
OAI21X4TS U5427 ( .A0(n2915), .A1(n7124), .B0(n7369), .Y(n7251) );
NAND2X4TS U5428 ( .A(n2919), .B(n2918), .Y(n7381) );
OAI21X4TS U5429 ( .A0(n7380), .A1(n7374), .B0(n7381), .Y(n2920) );
AOI21X4TS U5430 ( .A0(n2921), .A1(n7251), .B0(n2920), .Y(n7244) );
NAND2X4TS U5431 ( .A(n2925), .B(n2924), .Y(n7283) );
OAI21X4TS U5432 ( .A0(n7282), .A1(n7288), .B0(n7283), .Y(n7245) );
AOI21X4TS U5433 ( .A0(n7245), .A1(n2931), .B0(n2930), .Y(n2932) );
OAI21X4TS U5434 ( .A0(n7244), .A1(n2933), .B0(n2932), .Y(n2934) );
AOI21X4TS U5435 ( .A0(n7123), .A1(n2935), .B0(n2934), .Y(n2936) );
XNOR2X1TS U5436 ( .A(n3287), .B(n3167), .Y(n2964) );
OAI22X1TS U5437 ( .A0(n2964), .A1(n930), .B0(n2990), .B1(n3360), .Y(n2983)
);
NOR2X2TS U5438 ( .A(n2938), .B(n3583), .Y(n2979) );
INVX2TS U5439 ( .A(n2979), .Y(n2949) );
OAI22X1TS U5440 ( .A0(n2951), .A1(n889), .B0(n2940), .B1(n2942), .Y(n2948)
);
BUFX3TS U5441 ( .A(n2221), .Y(n3363) );
BUFX3TS U5442 ( .A(n2941), .Y(n3422) );
XNOR2X1TS U5443 ( .A(n3359), .B(n3363), .Y(n2952) );
OAI22X1TS U5444 ( .A0(n2967), .A1(n3422), .B0(n2952), .B1(n2966), .Y(n2947)
);
INVX2TS U5445 ( .A(n3359), .Y(n2943) );
NOR2X1TS U5446 ( .A(n2943), .B(n3583), .Y(n2978) );
XNOR2X1TS U5447 ( .A(n2945), .B(n3074), .Y(n2962) );
XNOR2X1TS U5448 ( .A(n920), .B(n3074), .Y(n2973) );
BUFX3TS U5449 ( .A(n2946), .Y(n3333) );
OAI22X1TS U5450 ( .A0(n2962), .A1(n3331), .B0(n2973), .B1(n3333), .Y(n2984)
);
CMPR32X2TS U5451 ( .A(n2949), .B(n2948), .C(n2947), .CO(n2982), .S(n3448) );
XNOR2X1TS U5452 ( .A(n3346), .B(n2950), .Y(n3402) );
OAI22X1TS U5453 ( .A0(n3402), .A1(n889), .B0(n2951), .B1(n3401), .Y(n3388)
);
OAI22X1TS U5454 ( .A0(n3423), .A1(n3155), .B0(n2952), .B1(n3365), .Y(n3387)
);
NOR2X2TS U5455 ( .A(n2953), .B(n971), .Y(n3421) );
INVX2TS U5456 ( .A(n2954), .Y(n2955) );
NOR2X1TS U5457 ( .A(n2955), .B(n3157), .Y(n2960) );
XNOR2X1TS U5458 ( .A(n3330), .B(n3358), .Y(n2965) );
BUFX3TS U5459 ( .A(n2956), .Y(n3378) );
XNOR2X1TS U5460 ( .A(n914), .B(n3358), .Y(n3379) );
OAI22X1TS U5461 ( .A0(n2965), .A1(n3378), .B0(n3379), .B1(n930), .Y(n3391)
);
XNOR2X1TS U5462 ( .A(n2957), .B(n3348), .Y(n3431) );
XNOR2X1TS U5463 ( .A(n754), .B(n3348), .Y(n2959) );
OAI22X1TS U5464 ( .A0(n3431), .A1(n3350), .B0(n2959), .B1(n3430), .Y(n3390)
);
XNOR2X1TS U5465 ( .A(n3287), .B(n3074), .Y(n3406) );
XNOR2X1TS U5466 ( .A(n3249), .B(n3074), .Y(n2963) );
OAI22X1TS U5467 ( .A0(n3406), .A1(n3407), .B0(n2963), .B1(n3405), .Y(n3389)
);
OAI22X1TS U5468 ( .A0(n2959), .A1(n3350), .B0(n2958), .B1(n3430), .Y(n3454)
);
OAI22X1TS U5469 ( .A0(n3418), .A1(n3336), .B0(n2969), .B1(n3417), .Y(n3453)
);
XNOR2X1TS U5470 ( .A(n918), .B(n3409), .Y(n3414) );
OAI22X1TS U5471 ( .A0(n3414), .A1(n3250), .B0(n2968), .B1(n3413), .Y(n3452)
);
CMPR32X2TS U5472 ( .A(n2961), .B(n3421), .C(n2960), .CO(n3451), .S(n3386) );
OAI22X1TS U5473 ( .A0(n2963), .A1(n931), .B0(n2962), .B1(n3333), .Y(n3450)
);
OAI22X1TS U5474 ( .A0(n2965), .A1(n3376), .B0(n2964), .B1(n3360), .Y(n3449)
);
OAI22X1TS U5475 ( .A0(n2974), .A1(n3422), .B0(n2967), .B1(n2966), .Y(n2989)
);
OAI22X1TS U5476 ( .A0(n2969), .A1(n3419), .B0(n2992), .B1(n3417), .Y(n2987)
);
CMPR32X2TS U5477 ( .A(n2972), .B(n2971), .C(n2970), .CO(n3471), .S(n3458) );
XNOR2X1TS U5478 ( .A(n919), .B(n3074), .Y(n2999) );
OAI22X1TS U5479 ( .A0(n2973), .A1(n931), .B0(n2999), .B1(n3405), .Y(n3010)
);
XNOR2X1TS U5480 ( .A(n3287), .B(n3363), .Y(n3004) );
OAI22X1TS U5481 ( .A0(n2974), .A1(n3424), .B0(n3004), .B1(n3365), .Y(n3009)
);
INVX2TS U5482 ( .A(n914), .Y(n2975) );
INVX2TS U5483 ( .A(n3029), .Y(n2995) );
OAI22X1TS U5484 ( .A0(n2977), .A1(n3350), .B0(n2976), .B1(n3005), .Y(n2994)
);
CMPR32X2TS U5485 ( .A(n2980), .B(n2979), .C(n2978), .CO(n2993), .S(n2986) );
CMPR32X2TS U5486 ( .A(n2983), .B(n2982), .C(n2981), .CO(n3015), .S(n3460) );
OAI22X1TS U5487 ( .A0(n2990), .A1(n3361), .B0(n3003), .B1(n3378), .Y(n3002)
);
XNOR2X1TS U5488 ( .A(n3278), .B(n3383), .Y(n2996) );
OAI22X1TS U5489 ( .A0(n2992), .A1(n3336), .B0(n2996), .B1(n3417), .Y(n3000)
);
XNOR2X1TS U5490 ( .A(n754), .B(n3383), .Y(n3034) );
OAI22X1TS U5491 ( .A0(n2996), .A1(n3419), .B0(n3034), .B1(n3417), .Y(n3038)
);
OAI22X1TS U5492 ( .A0(n2998), .A1(n3415), .B0(n3032), .B1(n3413), .Y(n3037)
);
XNOR2X1TS U5493 ( .A(n3349), .B(n3074), .Y(n3035) );
OAI22X1TS U5494 ( .A0(n2999), .A1(n3331), .B0(n3035), .B1(n3333), .Y(n3036)
);
CMPR32X2TS U5495 ( .A(n3002), .B(n3001), .C(n3000), .CO(n3020), .S(n3011) );
XNOR2X1TS U5496 ( .A(n920), .B(n3167), .Y(n3027) );
OAI22X1TS U5497 ( .A0(n3003), .A1(n3361), .B0(n3027), .B1(n3378), .Y(n3025)
);
OAI22X1TS U5498 ( .A0(n3004), .A1(n3424), .B0(n3026), .B1(n3365), .Y(n3024)
);
AO21X1TS U5499 ( .A0(n3006), .A1(n2563), .B0(n3005), .Y(n3030) );
INVX2TS U5500 ( .A(n921), .Y(n3007) );
NOR2X1TS U5501 ( .A(n3007), .B(n3583), .Y(n3028) );
CMPR32X2TS U5502 ( .A(n3010), .B(n3009), .C(n3008), .CO(n3018), .S(n3016) );
CMPR32X2TS U5503 ( .A(n3022), .B(n3021), .C(n3020), .CO(n3043), .S(n3041) );
CMPR32X2TS U5504 ( .A(n3025), .B(n3024), .C(n3023), .CO(n3063), .S(n3019) );
XNOR2X1TS U5505 ( .A(n915), .B(Op_MX[26]), .Y(n3047) );
OAI22X1TS U5506 ( .A0(n3026), .A1(n3155), .B0(n3047), .B1(n3422), .Y(n3050)
);
XNOR2X1TS U5507 ( .A(n919), .B(n3167), .Y(n3054) );
OAI22X1TS U5508 ( .A0(n3027), .A1(n3361), .B0(n3054), .B1(n3360), .Y(n3049)
);
CMPR32X2TS U5509 ( .A(n3030), .B(n3029), .C(n3028), .CO(n3048), .S(n3023) );
OAI22X1TS U5510 ( .A0(n3032), .A1(n935), .B0(n3031), .B1(n3051), .Y(n3057)
);
NOR2X2TS U5511 ( .A(n3033), .B(n3157), .Y(n3079) );
INVX2TS U5512 ( .A(n3079), .Y(n3056) );
XNOR2X1TS U5513 ( .A(n3278), .B(n3074), .Y(n3046) );
OAI22X1TS U5514 ( .A0(n3035), .A1(n3407), .B0(n3046), .B1(n3333), .Y(n3059)
);
OAI22X1TS U5515 ( .A0(n3045), .A1(n3419), .B0(n3073), .B1(n3417), .Y(n3072)
);
OAI22X1TS U5516 ( .A0(n3046), .A1(n931), .B0(n3075), .B1(n3333), .Y(n3071)
);
XNOR2X1TS U5517 ( .A(n3338), .B(n3363), .Y(n3077) );
OAI22X1TS U5518 ( .A0(n3047), .A1(n3155), .B0(n3077), .B1(n3422), .Y(n3070)
);
CMPR32X2TS U5519 ( .A(n3050), .B(n3049), .C(n3048), .CO(n3082), .S(n3062) );
NOR2X1TS U5520 ( .A(n3053), .B(n3157), .Y(n3078) );
XNOR2X1TS U5521 ( .A(n918), .B(n3167), .Y(n3076) );
OAI22X1TS U5522 ( .A0(n3054), .A1(n3361), .B0(n3076), .B1(n3378), .Y(n3068)
);
CMPR32X2TS U5523 ( .A(n3057), .B(n3056), .C(n3055), .CO(n3067), .S(n3060) );
ADDFX2TS U5524 ( .A(n3060), .B(n3059), .CI(n3058), .CO(n3065), .S(n3061) );
CMPR32X2TS U5525 ( .A(n3063), .B(n3062), .C(n3061), .CO(n3064), .S(n3042) );
CMPR32X2TS U5526 ( .A(n3069), .B(n3068), .C(n3067), .CO(n3135), .S(n3081) );
CMPR32X2TS U5527 ( .A(n3072), .B(n3071), .C(n3070), .CO(n3144), .S(n3083) );
OAI22X1TS U5528 ( .A0(n3073), .A1(n3419), .B0(n3188), .B1(n2692), .Y(n3098)
);
INVX2TS U5529 ( .A(n3094), .Y(n3097) );
XNOR2X1TS U5530 ( .A(n3276), .B(n3074), .Y(n3084) );
OAI22X1TS U5531 ( .A0(n3075), .A1(n3331), .B0(n3084), .B1(n3333), .Y(n3096)
);
XNOR2X1TS U5532 ( .A(n912), .B(n3167), .Y(n3086) );
OAI22X1TS U5533 ( .A0(n3076), .A1(n930), .B0(n3086), .B1(n3378), .Y(n3138)
);
XNOR2X1TS U5534 ( .A(n3410), .B(n3363), .Y(n3085) );
OAI22X1TS U5535 ( .A0(n3077), .A1(n3155), .B0(n3085), .B1(n3365), .Y(n3137)
);
CMPR32X2TS U5536 ( .A(n3080), .B(n3079), .C(n3078), .CO(n3136), .S(n3069) );
XNOR2X1TS U5537 ( .A(n3582), .B(n3329), .Y(n3090) );
OAI22X1TS U5538 ( .A0(n3084), .A1(n931), .B0(n3090), .B1(n3333), .Y(n3101)
);
XNOR2X1TS U5539 ( .A(n918), .B(n3363), .Y(n3087) );
OAI22X1TS U5540 ( .A0(n3085), .A1(n3155), .B0(n3087), .B1(n3422), .Y(n3100)
);
XNOR2X1TS U5541 ( .A(n753), .B(n3167), .Y(n3092) );
OAI22X1TS U5542 ( .A0(n3086), .A1(n3361), .B0(n3092), .B1(n3378), .Y(n3099)
);
XNOR2X1TS U5543 ( .A(n3278), .B(n3363), .Y(n3106) );
OAI22X1TS U5544 ( .A0(n3087), .A1(n3424), .B0(n3106), .B1(n3422), .Y(n3111)
);
INVX2TS U5545 ( .A(n920), .Y(n3088) );
NOR2X1TS U5546 ( .A(n3088), .B(n3157), .Y(n3093) );
OAI22X1TS U5547 ( .A0(n3090), .A1(n3331), .B0(n3089), .B1(n3107), .Y(n3104)
);
INVX2TS U5548 ( .A(n3410), .Y(n3091) );
NOR2X2TS U5549 ( .A(n3091), .B(n3157), .Y(n3116) );
INVX2TS U5550 ( .A(n3116), .Y(n3103) );
CMPR32X2TS U5551 ( .A(n3095), .B(n3094), .C(n3093), .CO(n3110), .S(n3141) );
CMPR32X2TS U5552 ( .A(n3098), .B(n3097), .C(n3096), .CO(n3140), .S(n3143) );
CMPR32X2TS U5553 ( .A(n3104), .B(n3103), .C(n3102), .CO(n3114), .S(n3109) );
XNOR2X1TS U5554 ( .A(n853), .B(n3358), .Y(n3119) );
OAI22X1TS U5555 ( .A0(n3105), .A1(n3361), .B0(n3119), .B1(n3378), .Y(n3124)
);
OAI22X1TS U5556 ( .A0(n3106), .A1(n3155), .B0(n3121), .B1(n3422), .Y(n3123)
);
INVX2TS U5557 ( .A(n918), .Y(n3108) );
NOR2X1TS U5558 ( .A(n3108), .B(n3157), .Y(n3115) );
CMPR32X2TS U5559 ( .A(n3111), .B(n3110), .C(n3109), .CO(n3112), .S(n3149) );
NOR2X4TS U5560 ( .A(n3562), .B(n3561), .Y(n7300) );
OAI22X1TS U5561 ( .A0(n3119), .A1(n3361), .B0(n3118), .B1(n3129), .Y(n3132)
);
INVX2TS U5562 ( .A(n912), .Y(n3120) );
INVX2TS U5563 ( .A(n3160), .Y(n3131) );
CMPR32X2TS U5564 ( .A(n3124), .B(n3123), .C(n3122), .CO(n3125), .S(n3113) );
XNOR2X1TS U5565 ( .A(n853), .B(Op_MX[26]), .Y(n3156) );
OAI22X1TS U5566 ( .A0(n3128), .A1(n3155), .B0(n3156), .B1(n3422), .Y(n3153)
);
NOR2X1TS U5567 ( .A(n752), .B(n3157), .Y(n3159) );
CMPR32X2TS U5568 ( .A(n3138), .B(n3137), .C(n3136), .CO(n3147), .S(n3142) );
CMPR32X2TS U5569 ( .A(n3141), .B(n3140), .C(n3139), .CO(n3148), .S(n3146) );
CMPR32X2TS U5570 ( .A(n3144), .B(n3143), .C(n3142), .CO(n3145), .S(n3134) );
NOR2X4TS U5571 ( .A(n3558), .B(n3557), .Y(n3923) );
CMPR32X2TS U5572 ( .A(n3150), .B(n3149), .C(n3148), .CO(n3562), .S(n3559) );
NOR2X4TS U5573 ( .A(n3560), .B(n3559), .Y(n3928) );
CMPR32X2TS U5574 ( .A(n3153), .B(n3152), .C(n3151), .CO(n3574), .S(n3565) );
OAI22X1TS U5575 ( .A0(n3156), .A1(n3155), .B0(n3154), .B1(n971), .Y(n3581)
);
INVX2TS U5576 ( .A(n909), .Y(n3158) );
NOR2X1TS U5577 ( .A(n3158), .B(n3157), .Y(n3585) );
INVX2TS U5578 ( .A(n3585), .Y(n3580) );
CMPR32X2TS U5579 ( .A(n3161), .B(n3160), .C(n3159), .CO(n3579), .S(n3152) );
NOR2X2TS U5580 ( .A(n3574), .B(n3573), .Y(n3597) );
NOR2X2TS U5581 ( .A(n3592), .B(n3597), .Y(n3556) );
INVX2TS U5582 ( .A(n3165), .Y(n3166) );
NOR2X2TS U5583 ( .A(n3166), .B(n971), .Y(n3299) );
INVX2TS U5584 ( .A(n3299), .Y(n3254) );
OAI22X1TS U5585 ( .A0(n3169), .A1(n3424), .B0(n3219), .B1(n3365), .Y(n3252)
);
CMPR32X2TS U5586 ( .A(n3172), .B(n3171), .C(n3170), .CO(n3214), .S(n3175) );
XNOR2X1TS U5587 ( .A(n3176), .B(n3329), .Y(n3225) );
OAI22X1TS U5588 ( .A0(n3177), .A1(n3407), .B0(n3225), .B1(n3333), .Y(n3259)
);
CMPR32X2TS U5589 ( .A(n3183), .B(n3182), .C(n3181), .CO(n3257), .S(n3171) );
ADDFHX2TS U5590 ( .A(n3186), .B(n3185), .CI(n3184), .CO(n3237), .S(n3174) );
XNOR2X1TS U5591 ( .A(n914), .B(n3230), .Y(n3232) );
OAI22X1TS U5592 ( .A0(n3232), .A1(n3188), .B0(n3187), .B1(n3231), .Y(n3235)
);
XNOR2X1TS U5593 ( .A(n3287), .B(n3409), .Y(n3251) );
OAI22X1TS U5594 ( .A0(n3189), .A1(n3250), .B0(n3251), .B1(n3411), .Y(n3234)
);
OAI22X1TS U5595 ( .A0(n3191), .A1(n933), .B0(n3229), .B1(n3228), .Y(n3233)
);
ADDFX2TS U5596 ( .A(n3197), .B(n3196), .CI(n3195), .CO(n3241), .S(n3193) );
XNOR2X1TS U5597 ( .A(n3278), .B(n3275), .Y(n3248) );
OAI22X1TS U5598 ( .A0(n3202), .A1(n3201), .B0(n3248), .B1(n3344), .Y(n3247)
);
XNOR2X1TS U5599 ( .A(n3384), .B(n3348), .Y(n3256) );
OAI22X1TS U5600 ( .A0(n3203), .A1(n3350), .B0(n3256), .B1(n3430), .Y(n3246)
);
XNOR2X1TS U5601 ( .A(n919), .B(n3346), .Y(n3255) );
OAI22X1TS U5602 ( .A0(n3204), .A1(n3279), .B0(n3255), .B1(n3401), .Y(n3245)
);
CMPR32X2TS U5603 ( .A(n3207), .B(n3206), .C(n3205), .CO(n3242), .S(n3209) );
ADDFHX4TS U5604 ( .A(n3213), .B(n3212), .CI(n3211), .CO(n3515), .S(n2929) );
XNOR2X1TS U5605 ( .A(n3217), .B(n3358), .Y(n3284) );
XNOR2X1TS U5606 ( .A(n916), .B(n4730), .Y(n3286) );
OAI22X1TS U5607 ( .A0(n3219), .A1(n3424), .B0(n3286), .B1(n3365), .Y(n3296)
);
INVX2TS U5608 ( .A(n3223), .Y(n3224) );
NOR2X1TS U5609 ( .A(n3224), .B(n971), .Y(n3298) );
XNOR2X1TS U5610 ( .A(n3359), .B(n3329), .Y(n3304) );
OAI22X1TS U5611 ( .A0(n3225), .A1(n3331), .B0(n3304), .B1(n3405), .Y(n3307)
);
OAI22X1TS U5612 ( .A0(n3229), .A1(n2839), .B0(n3302), .B1(n3228), .Y(n3306)
);
OAI22X1TS U5613 ( .A0(n3288), .A1(n3417), .B0(n3232), .B1(n3231), .Y(n3305)
);
CMPR32X2TS U5614 ( .A(n3235), .B(n3234), .C(n3233), .CO(n3311), .S(n3236) );
CMPR32X2TS U5615 ( .A(n3244), .B(n3243), .C(n3242), .CO(n3271), .S(n3240) );
XNOR2X1TS U5616 ( .A(n753), .B(n3275), .Y(n3277) );
OAI22X1TS U5617 ( .A0(n3248), .A1(n3428), .B0(n3277), .B1(n3344), .Y(n3294)
);
OAI22X1TS U5618 ( .A0(n3251), .A1(n3250), .B0(n3289), .B1(n3411), .Y(n3293)
);
OAI22X1TS U5619 ( .A0(n3255), .A1(n890), .B0(n3280), .B1(n3401), .Y(n3310)
);
XNOR2X1TS U5620 ( .A(n920), .B(n3348), .Y(n3291) );
OAI22X1TS U5621 ( .A0(n3256), .A1(n3350), .B0(n3291), .B1(n3430), .Y(n3309)
);
CMPR32X2TS U5622 ( .A(n3259), .B(n3258), .C(n3257), .CO(n3308), .S(n3238) );
CMPR32X2TS U5623 ( .A(n3268), .B(n3267), .C(n3266), .CO(n3319), .S(n3316) );
XNOR2X1TS U5624 ( .A(n3276), .B(n3275), .Y(n3345) );
NOR2X2TS U5625 ( .A(n3282), .B(n971), .Y(n3381) );
INVX2TS U5626 ( .A(n3381), .Y(n3354) );
XNOR2X1TS U5627 ( .A(n3358), .B(n3283), .Y(n3362) );
OAI22X1TS U5628 ( .A0(n3284), .A1(n930), .B0(n3362), .B1(n3378), .Y(n3353)
);
OAI22X1TS U5629 ( .A0(n3286), .A1(n3424), .B0(n3366), .B1(n3365), .Y(n3352)
);
XNOR2X1TS U5630 ( .A(n3287), .B(n3383), .Y(n3337) );
OAI22X1TS U5631 ( .A0(n3288), .A1(n3336), .B0(n3337), .B1(n3335), .Y(n3328)
);
XNOR2X1TS U5632 ( .A(n919), .B(n3348), .Y(n3351) );
OAI22X1TS U5633 ( .A0(n3291), .A1(n3350), .B0(n3351), .B1(n3290), .Y(n3326)
);
CMPR32X2TS U5634 ( .A(n3294), .B(n3293), .C(n3292), .CO(n3320), .S(n3273) );
CMPR32X2TS U5635 ( .A(n3297), .B(n3296), .C(n3295), .CO(n3342), .S(n3313) );
OAI22X1TS U5636 ( .A0(n3302), .A1(n2839), .B0(n3301), .B1(n3367), .Y(n3356)
);
CMPR32X2TS U5637 ( .A(n3307), .B(n3306), .C(n3305), .CO(n3340), .S(n3312) );
CMPR32X2TS U5638 ( .A(n3310), .B(n3309), .C(n3308), .CO(n3371), .S(n3272) );
ADDFHX2TS U5639 ( .A(n3313), .B(n3312), .CI(n3311), .CO(n3370), .S(n3267) );
ADDFHX4TS U5640 ( .A(n3319), .B(n3318), .CI(n3317), .CO(n3522), .S(n3520) );
CMPR32X2TS U5641 ( .A(n3322), .B(n3321), .C(n3320), .CO(n3502), .S(n3374) );
CMPR32X2TS U5642 ( .A(n3325), .B(n3324), .C(n3323), .CO(n3490), .S(n3322) );
XNOR2X1TS U5643 ( .A(n921), .B(n3329), .Y(n3408) );
OAI22X1TS U5644 ( .A0(n3408), .A1(n3333), .B0(n3332), .B1(n931), .Y(n3400)
);
OAI22X1TS U5645 ( .A0(n3337), .A1(n3336), .B0(n3385), .B1(n3335), .Y(n3399)
);
XNOR2X1TS U5646 ( .A(n3338), .B(n3409), .Y(n3412) );
OAI22X1TS U5647 ( .A0(n3339), .A1(n3415), .B0(n3412), .B1(n3413), .Y(n3398)
);
OAI22X1TS U5648 ( .A0(n3345), .A1(n934), .B0(n3429), .B1(n3344), .Y(n3397)
);
XNOR2X1TS U5649 ( .A(n3349), .B(n3348), .Y(n3433) );
OAI22X1TS U5650 ( .A0(n3351), .A1(n3350), .B0(n3433), .B1(n3430), .Y(n3395)
);
ADDFHX2TS U5651 ( .A(n3354), .B(n3353), .CI(n3352), .CO(n3478), .S(n3323) );
XNOR2X1TS U5652 ( .A(n3359), .B(n3358), .Y(n3377) );
XNOR2X1TS U5653 ( .A(n3364), .B(n3363), .Y(n3425) );
OAI22X1TS U5654 ( .A0(n3366), .A1(n3424), .B0(n3425), .B1(n3365), .Y(n3435)
);
INVX2TS U5655 ( .A(n3368), .Y(n3369) );
NOR2X8TS U5656 ( .A(n3522), .B(n3521), .Y(n3913) );
OAI22X1TS U5657 ( .A0(n3379), .A1(n3378), .B0(n3377), .B1(n3376), .Y(n3394)
);
OAI22X1TS U5658 ( .A0(n3385), .A1(n3419), .B0(n3420), .B1(n3417), .Y(n3392)
);
CMPR32X2TS U5659 ( .A(n3388), .B(n3387), .C(n3386), .CO(n3447), .S(n3444) );
CMPR32X2TS U5660 ( .A(n3391), .B(n3390), .C(n3389), .CO(n3446), .S(n3443) );
CMPR32X2TS U5661 ( .A(n3400), .B(n3399), .C(n3398), .CO(n3485), .S(n3488) );
OAI22X1TS U5662 ( .A0(n3404), .A1(n889), .B0(n3402), .B1(n3401), .Y(n3475)
);
OAI22X1TS U5663 ( .A0(n3408), .A1(n3407), .B0(n3406), .B1(n3405), .Y(n3474)
);
XNOR2X1TS U5664 ( .A(n919), .B(n3409), .Y(n3416) );
OAI22X1TS U5665 ( .A0(n3412), .A1(n935), .B0(n3416), .B1(n3411), .Y(n3473)
);
OAI22X1TS U5666 ( .A0(n3416), .A1(n935), .B0(n3414), .B1(n3413), .Y(n3457)
);
OAI22X1TS U5667 ( .A0(n3420), .A1(n3419), .B0(n3418), .B1(n3417), .Y(n3456)
);
INVX2TS U5668 ( .A(n3421), .Y(n3439) );
OAI22X1TS U5669 ( .A0(n3425), .A1(n3424), .B0(n3423), .B1(n3422), .Y(n3438)
);
OAI22X1TS U5670 ( .A0(n3429), .A1(n3428), .B0(n3427), .B1(n3426), .Y(n3437)
);
OAI22X1TS U5671 ( .A0(n3433), .A1(n3432), .B0(n3431), .B1(n3430), .Y(n3481)
);
ADDFHX2TS U5672 ( .A(n3436), .B(n3435), .CI(n3434), .CO(n3480), .S(n3476) );
CMPR32X2TS U5673 ( .A(n3439), .B(n3438), .C(n3437), .CO(n3455), .S(n3479) );
ADDFHX1TS U5674 ( .A(n3442), .B(n3441), .CI(n3440), .CO(n3495), .S(n3482) );
ADDFX2TS U5675 ( .A(n3445), .B(n3444), .CI(n3443), .CO(n3466), .S(n3484) );
CMPR32X2TS U5676 ( .A(n3448), .B(n3447), .C(n3446), .CO(n3459), .S(n3465) );
CMPR32X2TS U5677 ( .A(n3451), .B(n3450), .C(n3449), .CO(n2971), .S(n3463) );
CMPR32X2TS U5678 ( .A(n3463), .B(n3462), .C(n3461), .CO(n3468), .S(n3464) );
CMPR32X2TS U5679 ( .A(n3475), .B(n3474), .C(n3473), .CO(n3442), .S(n3493) );
ADDFHX2TS U5680 ( .A(n3484), .B(n3483), .CI(n3482), .CO(n3496), .S(n3513) );
CMPR32X2TS U5681 ( .A(n3487), .B(n3486), .C(n3485), .CO(n3483), .S(n3508) );
CMPR32X2TS U5682 ( .A(n3490), .B(n3489), .C(n3488), .CO(n3507), .S(n3501) );
CMPR32X2TS U5683 ( .A(n3493), .B(n3492), .C(n3491), .CO(n3514), .S(n3506) );
ADDFHX2TS U5684 ( .A(n3508), .B(n3507), .CI(n3506), .CO(n3512), .S(n3509) );
ADDFHX2TS U5685 ( .A(n3514), .B(n3513), .CI(n3512), .CO(n3530), .S(n3527) );
INVX16TS U5686 ( .A(n1023), .Y(n7323) );
NAND2X4TS U5687 ( .A(n3518), .B(n3517), .Y(n7240) );
OAI21X4TS U5688 ( .A0(n7239), .A1(n7237), .B0(n7240), .Y(n3909) );
NAND2X4TS U5689 ( .A(n3520), .B(n3519), .Y(n7339) );
NAND2X4TS U5690 ( .A(n3522), .B(n3521), .Y(n3914) );
OAI21X4TS U5691 ( .A0(n3913), .A1(n7339), .B0(n3914), .Y(n3523) );
AOI21X4TS U5692 ( .A0(n3909), .A1(n3524), .B0(n3523), .Y(n5108) );
OAI21X4TS U5693 ( .A0(n7410), .A1(n7405), .B0(n7411), .Y(n7344) );
NAND2X4TS U5694 ( .A(n3530), .B(n3529), .Y(n7418) );
NAND2X4TS U5695 ( .A(n3532), .B(n3531), .Y(n7419) );
NAND2X2TS U5696 ( .A(n3534), .B(n3533), .Y(n7431) );
OA21X4TS U5697 ( .A0(n3535), .A1(n7419), .B0(n7431), .Y(n3536) );
AOI21X4TS U5698 ( .A0(n7344), .A1(n3539), .B0(n3538), .Y(n3540) );
OAI21X4TS U5699 ( .A0(n5108), .A1(n3541), .B0(n3540), .Y(n3542) );
BUFX20TS U5700 ( .A(n3542), .Y(n7325) );
NAND2X2TS U5701 ( .A(n3546), .B(n3545), .Y(n7328) );
AOI21X4TS U5702 ( .A0(n7324), .A1(n791), .B0(n3547), .Y(n7316) );
NAND2X2TS U5703 ( .A(n3549), .B(n3548), .Y(n7322) );
INVX2TS U5704 ( .A(n7322), .Y(n3553) );
INVX2TS U5705 ( .A(n4695), .Y(n3552) );
AOI21X4TS U5706 ( .A0(n3553), .A1(n4696), .B0(n3552), .Y(n3554) );
OAI21X4TS U5707 ( .A0(n7316), .A1(n3555), .B0(n3554), .Y(n4825) );
BUFX3TS U5708 ( .A(n4825), .Y(n3917) );
NAND2X2TS U5709 ( .A(n3558), .B(n3557), .Y(n3922) );
NAND2X2TS U5710 ( .A(n3560), .B(n3559), .Y(n3929) );
NAND2X2TS U5711 ( .A(n3562), .B(n3561), .Y(n7301) );
INVX2TS U5712 ( .A(n7312), .Y(n3568) );
NAND2X1TS U5713 ( .A(n3566), .B(n3565), .Y(n4831) );
INVX2TS U5714 ( .A(n4831), .Y(n3567) );
NAND2X1TS U5715 ( .A(n3574), .B(n3573), .Y(n3598) );
AOI21X4TS U5716 ( .A0(n897), .A1(n1021), .B0(n3576), .Y(n3577) );
CMPR32X2TS U5717 ( .A(n3581), .B(n3580), .C(n3579), .CO(n3588), .S(n3573) );
NOR2X1TS U5718 ( .A(n3584), .B(n3583), .Y(n3586) );
NAND2X1TS U5719 ( .A(n3588), .B(n3587), .Y(n3589) );
XOR2X4TS U5720 ( .A(n3590), .B(n3589), .Y(Sgf_operation_ODD1_middle_N55) );
NOR2X2TS U5721 ( .A(n7292), .B(n3592), .Y(n3594) );
INVX2TS U5722 ( .A(n3597), .Y(n3599) );
XOR2X4TS U5723 ( .A(n3600), .B(n968), .Y(Sgf_operation_ODD1_middle_N54) );
NAND2X1TS U5724 ( .A(n3646), .B(n3647), .Y(n3603) );
NAND2X2TS U5725 ( .A(n1002), .B(n3601), .Y(n3602) );
AOI21X1TS U5726 ( .A0(n5936), .A1(n903), .B0(n3604), .Y(n3605) );
OAI21X1TS U5727 ( .A0(n1001), .A1(n6061), .B0(n3605), .Y(n3631) );
INVX4TS U5728 ( .A(n3606), .Y(n3682) );
AOI21X4TS U5729 ( .A0(n3682), .A1(n3608), .B0(n3607), .Y(n3705) );
INVX2TS U5730 ( .A(n3704), .Y(n3609) );
NAND2X1TS U5731 ( .A(n3609), .B(n3703), .Y(n3610) );
XNOR2X4TS U5732 ( .A(Op_MX[47]), .B(Op_MX[48]), .Y(n3614) );
XOR2X4TS U5733 ( .A(n3866), .B(Op_MX[49]), .Y(n3615) );
NAND2BX4TS U5734 ( .AN(n3614), .B(n3615), .Y(n4965) );
BUFX3TS U5735 ( .A(Op_MY[33]), .Y(n5856) );
INVX2TS U5736 ( .A(n3612), .Y(n3613) );
BUFX8TS U5737 ( .A(n4967), .Y(n6064) );
BUFX3TS U5738 ( .A(n852), .Y(n5758) );
NAND3X4TS U5739 ( .A(n3615), .B(n3614), .C(n3613), .Y(n4702) );
INVX8TS U5740 ( .A(n4702), .Y(n6063) );
AOI222X1TS U5741 ( .A0(n881), .A1(n5856), .B0(n6064), .B1(n5758), .C0(n6063),
.C1(n849), .Y(n3616) );
OAI21X2TS U5742 ( .A0(n4999), .A1(n3723), .B0(n3724), .Y(n3622) );
NAND2X1TS U5743 ( .A(n3620), .B(n3619), .Y(n3621) );
XNOR2X4TS U5744 ( .A(n3622), .B(n3621), .Y(n3623) );
XNOR2X4TS U5745 ( .A(Op_MX[44]), .B(Op_MX[45]), .Y(n3625) );
NAND2BX4TS U5746 ( .AN(n3625), .B(n3626), .Y(n5491) );
NOR2X8TS U5747 ( .A(n3626), .B(n3625), .Y(n5840) );
XNOR2X2TS U5748 ( .A(Op_MX[45]), .B(Op_MX[46]), .Y(n3624) );
NOR2BX4TS U5749 ( .AN(n3625), .B(n3624), .Y(n5494) );
BUFX3TS U5750 ( .A(Op_MY[34]), .Y(n5999) );
AOI222X1TS U5751 ( .A0(n5845), .A1(n837), .B0(n6031), .B1(n831), .C0(n5844),
.C1(n5999), .Y(n3627) );
OAI21X1TS U5752 ( .A0(n5905), .A1(n6035), .B0(n3627), .Y(n3628) );
ADDFX2TS U5753 ( .A(n3631), .B(n3630), .CI(n3629), .CO(mult_x_23_n798), .S(
mult_x_23_n799) );
BUFX3TS U5754 ( .A(n5766), .Y(n5807) );
NAND2X1TS U5755 ( .A(n870), .B(n824), .Y(n3633) );
OAI21X1TS U5756 ( .A0(n5807), .A1(n6053), .B0(n3633), .Y(
Sgf_operation_ODD1_left_N0) );
NAND2BX4TS U5757 ( .AN(n3719), .B(n3720), .Y(n5665) );
NOR2X4TS U5758 ( .A(n3720), .B(n3719), .Y(n3717) );
CLKINVX1TS U5759 ( .A(n793), .Y(n3635) );
XNOR2X4TS U5760 ( .A(Op_MX[29]), .B(Op_MX[30]), .Y(n3638) );
NOR2X4TS U5761 ( .A(n3639), .B(n3638), .Y(n5748) );
NOR2BX4TS U5762 ( .AN(n3638), .B(n3637), .Y(n5712) );
BUFX4TS U5763 ( .A(n5712), .Y(n5759) );
BUFX3TS U5764 ( .A(n8374), .Y(n6055) );
BUFX3TS U5765 ( .A(n903), .Y(n6054) );
AOI222X1TS U5766 ( .A0(n5742), .A1(n8375), .B0(n5759), .B1(n6055), .C0(n5751), .C1(n6054), .Y(n3640) );
OR2X2TS U5767 ( .A(n903), .B(n824), .Y(n3642) );
NAND2X4TS U5768 ( .A(n3642), .B(n3647), .Y(n6062) );
OAI21X1TS U5769 ( .A0(n6062), .A1(n5861), .B0(n795), .Y(n3643) );
XOR2X1TS U5770 ( .A(n3643), .B(n5763), .Y(n3686) );
NAND2X1TS U5771 ( .A(n5748), .B(n4966), .Y(n3644) );
NAND2X2TS U5772 ( .A(n996), .B(n3646), .Y(n3648) );
XOR2X2TS U5773 ( .A(n3648), .B(n3647), .Y(n3649) );
BUFX3TS U5774 ( .A(n8374), .Y(n5843) );
BUFX3TS U5775 ( .A(n903), .Y(n5839) );
INVX2TS U5776 ( .A(n803), .Y(n5213) );
AOI222X1TS U5777 ( .A0(n5742), .A1(n5843), .B0(n5759), .B1(n5839), .C0(n5751), .C1(n5213), .Y(n3650) );
OAI21X1TS U5778 ( .A0(n5437), .A1(n5861), .B0(n3650), .Y(n3651) );
XOR2X1TS U5779 ( .A(n3651), .B(n5763), .Y(n3665) );
BUFX3TS U5780 ( .A(n3669), .Y(n6079) );
AOI222X1TS U5781 ( .A0(n871), .A1(n5856), .B0(n6079), .B1(n5758), .C0(n5964),
.C1(n849), .Y(n3653) );
OAI21X1TS U5782 ( .A0(n5762), .A1(n5807), .B0(n3653), .Y(n3654) );
NOR2X4TS U5783 ( .A(n3692), .B(n3691), .Y(n5375) );
INVX2TS U5784 ( .A(n3655), .Y(n3680) );
INVX2TS U5785 ( .A(n3679), .Y(n3656) );
AOI21X2TS U5786 ( .A0(n3682), .A1(n3680), .B0(n3656), .Y(n3661) );
INVX2TS U5787 ( .A(n3657), .Y(n3659) );
XNOR2X4TS U5788 ( .A(n3661), .B(n3660), .Y(n5931) );
BUFX3TS U5789 ( .A(n5766), .Y(n6042) );
BUFX3TS U5790 ( .A(n3662), .Y(n6081) );
BUFX3TS U5791 ( .A(n852), .Y(n5996) );
AOI222X1TS U5792 ( .A0(n6081), .A1(n5996), .B0(n6079), .B1(n8376), .C0(n5964), .C1(n851), .Y(n3663) );
OAI21X1TS U5793 ( .A0(n5931), .A1(n6042), .B0(n3663), .Y(n3664) );
XOR2X1TS U5794 ( .A(n3664), .B(n5819), .Y(n3690) );
CMPR22X2TS U5795 ( .A(n3666), .B(n3665), .CO(n3700), .S(n3689) );
NOR2X2TS U5796 ( .A(n3690), .B(n3689), .Y(n5380) );
NOR2X2TS U5797 ( .A(n5375), .B(n5380), .Y(n3694) );
AOI222X1TS U5798 ( .A0(n6081), .A1(n5843), .B0(n6079), .B1(n5839), .C0(n5964), .C1(n5213), .Y(n3667) );
OAI21X1TS U5799 ( .A0(n5437), .A1(n6042), .B0(n3667), .Y(n3668) );
INVX2TS U5800 ( .A(n1032), .Y(n5804) );
AOI22X1TS U5801 ( .A0(n870), .A1(n903), .B0(n873), .B1(n4966), .Y(n3670) );
OAI21X1TS U5802 ( .A0(n6062), .A1(n6042), .B0(n3670), .Y(n3671) );
AOI222X1TS U5803 ( .A0(n6081), .A1(n8375), .B0(n6079), .B1(n6055), .C0(n5964), .C1(n6054), .Y(n3673) );
OAI21X1TS U5804 ( .A0(n1001), .A1(n6042), .B0(n3673), .Y(n3674) );
XOR2X1TS U5805 ( .A(n3674), .B(n5804), .Y(n3677) );
NAND2X1TS U5806 ( .A(n3677), .B(n3676), .Y(n5390) );
INVX2TS U5807 ( .A(n5390), .Y(n3678) );
AOI21X2TS U5808 ( .A0(n5391), .A1(n786), .B0(n3678), .Y(n5389) );
NAND2X1TS U5809 ( .A(n3680), .B(n3679), .Y(n3681) );
CLKXOR2X4TS U5810 ( .A(n3682), .B(n3681), .Y(n6068) );
BUFX3TS U5811 ( .A(n851), .Y(n8375) );
OAI21X1TS U5812 ( .A0(n6068), .A1(n5807), .B0(n3683), .Y(n3684) );
XOR2X1TS U5813 ( .A(n3684), .B(n5804), .Y(n3688) );
CMPR22X2TS U5814 ( .A(n3686), .B(n3685), .CO(n3666), .S(n3687) );
NOR2X1TS U5815 ( .A(n3688), .B(n3687), .Y(n5385) );
NAND2X1TS U5816 ( .A(n3688), .B(n3687), .Y(n5386) );
OAI21X4TS U5817 ( .A0(n5389), .A1(n5385), .B0(n5386), .Y(n5374) );
NAND2X1TS U5818 ( .A(n3690), .B(n3689), .Y(n5381) );
NAND2X2TS U5819 ( .A(n3692), .B(n3691), .Y(n5376) );
OAI21X2TS U5820 ( .A0(n5375), .A1(n5381), .B0(n5376), .Y(n3693) );
AOI21X4TS U5821 ( .A0(n3694), .A1(n5374), .B0(n3693), .Y(n5813) );
XNOR2X2TS U5822 ( .A(Op_MX[33]), .B(Op_MX[34]), .Y(n3718) );
NOR2BX4TS U5823 ( .AN(n3719), .B(n3718), .Y(n5668) );
OAI21X1TS U5824 ( .A0(n6062), .A1(n5665), .B0(n3695), .Y(n3696) );
ADDHXLTS U5825 ( .A(n7492), .B(n3697), .CO(n3715), .S(n3702) );
AOI222X1TS U5826 ( .A0(n5742), .A1(n849), .B0(n5759), .B1(n830), .C0(n5857),
.C1(n5843), .Y(n3698) );
ADDFHX2TS U5827 ( .A(n894), .B(n3701), .CI(n3700), .CO(n3731), .S(n3692) );
INVX2TS U5828 ( .A(n3706), .Y(n3708) );
XOR2X4TS U5829 ( .A(n3710), .B(n3709), .Y(n6001) );
BUFX3TS U5830 ( .A(Op_MY[33]), .Y(n5998) );
AOI222X1TS U5831 ( .A0(n871), .A1(n5999), .B0(n873), .B1(n5998), .C0(n5964),
.C1(n5996), .Y(n3711) );
OAI21X1TS U5832 ( .A0(n6001), .A1(n5807), .B0(n3711), .Y(n3712) );
XOR2X1TS U5833 ( .A(n3712), .B(n5819), .Y(n3713) );
NAND2X2TS U5834 ( .A(n3714), .B(n3713), .Y(n5810) );
OAI21X4TS U5835 ( .A0(n5813), .A1(n5809), .B0(n5810), .Y(n5817) );
AND3X4TS U5836 ( .A(n3720), .B(n3719), .C(n3718), .Y(n5974) );
AOI222X1TS U5837 ( .A0(n5929), .A1(n855), .B0(n5975), .B1(n5839), .C0(n5928),
.C1(n5213), .Y(n3721) );
INVX2TS U5838 ( .A(n3723), .Y(n3725) );
NAND2X2TS U5839 ( .A(n3725), .B(n3724), .Y(n3726) );
BUFX3TS U5840 ( .A(Op_MY[35]), .Y(n8385) );
BUFX3TS U5841 ( .A(Op_MY[34]), .Y(n5858) );
AOI222X1TS U5842 ( .A0(n871), .A1(n832), .B0(n873), .B1(n5858), .C0(n5964),
.C1(n5892), .Y(n3727) );
XOR2X1TS U5843 ( .A(n3728), .B(n5819), .Y(n3738) );
AOI222X1TS U5844 ( .A0(n5742), .A1(n5996), .B0(n5759), .B1(n8376), .C0(n5857), .C1(n830), .Y(n3729) );
OAI21X1TS U5845 ( .A0(n5931), .A1(n5761), .B0(n3729), .Y(n3730) );
XOR2X1TS U5846 ( .A(n3730), .B(n5763), .Y(n3737) );
INVX2TS U5847 ( .A(n5814), .Y(n3736) );
AOI21X4TS U5848 ( .A0(n5817), .A1(n5815), .B0(n3736), .Y(n5364) );
OR2X4TS U5849 ( .A(mult_x_23_n948), .B(mult_x_23_n952), .Y(n5366) );
CMPR32X2TS U5850 ( .A(n3739), .B(n3738), .C(n3737), .CO(n3740), .S(n3735) );
OR2X2TS U5851 ( .A(mult_x_23_n953), .B(n3740), .Y(n5371) );
NAND2X2TS U5852 ( .A(n5366), .B(n5371), .Y(n3743) );
NAND2X2TS U5853 ( .A(mult_x_23_n953), .B(n3740), .Y(n5370) );
INVX2TS U5854 ( .A(n5370), .Y(n5365) );
INVX2TS U5855 ( .A(n5367), .Y(n3741) );
OAI21X4TS U5856 ( .A0(n5364), .A1(n3743), .B0(n3742), .Y(n5358) );
NOR2X4TS U5857 ( .A(mult_x_23_n943), .B(mult_x_23_n947), .Y(n5951) );
NAND2X2TS U5858 ( .A(mult_x_23_n943), .B(mult_x_23_n947), .Y(n5952) );
INVX4TS U5859 ( .A(n3746), .Y(n5352) );
NAND2X2TS U5860 ( .A(n780), .B(n5352), .Y(n3749) );
NAND2X2TS U5861 ( .A(mult_x_23_n929), .B(mult_x_23_n935), .Y(n5355) );
NAND2X2TS U5862 ( .A(mult_x_23_n922), .B(mult_x_23_n928), .Y(n5351) );
INVX2TS U5863 ( .A(n5351), .Y(n3747) );
OAI21X4TS U5864 ( .A0(n5349), .A1(n3749), .B0(n3748), .Y(n5343) );
NOR2X4TS U5865 ( .A(mult_x_23_n906), .B(mult_x_23_n913), .Y(n5344) );
NOR2X4TS U5866 ( .A(mult_x_23_n914), .B(mult_x_23_n921), .Y(n5946) );
NOR2X2TS U5867 ( .A(n5344), .B(n5946), .Y(n3751) );
OAI21X2TS U5868 ( .A0(n5344), .A1(n5947), .B0(n5345), .Y(n3750) );
AOI21X4TS U5869 ( .A0(n5343), .A1(n3751), .B0(n3750), .Y(n5332) );
NOR2X4TS U5870 ( .A(n5335), .B(n5333), .Y(n5988) );
NAND2X2TS U5871 ( .A(n5988), .B(n787), .Y(n3754) );
NAND2X4TS U5872 ( .A(mult_x_23_n898), .B(mult_x_23_n905), .Y(n5340) );
NAND2X2TS U5873 ( .A(mult_x_23_n888), .B(mult_x_23_n897), .Y(n5336) );
INVX2TS U5874 ( .A(n5990), .Y(n3752) );
OAI21X4TS U5875 ( .A0(n5332), .A1(n3754), .B0(n3753), .Y(n5316) );
NOR2X4TS U5876 ( .A(n5318), .B(n5319), .Y(n3758) );
NAND2X4TS U5877 ( .A(mult_x_23_n868), .B(mult_x_23_n877), .Y(n5328) );
NAND2X2TS U5878 ( .A(mult_x_23_n857), .B(mult_x_23_n867), .Y(n5325) );
INVX2TS U5879 ( .A(n5325), .Y(n3755) );
AOI21X4TS U5880 ( .A0(n3756), .A1(n1008), .B0(n3755), .Y(n5317) );
NAND2X2TS U5881 ( .A(mult_x_23_n846), .B(mult_x_23_n856), .Y(n5320) );
OAI21X4TS U5882 ( .A0(n5317), .A1(n5319), .B0(n5320), .Y(n3757) );
AOI21X4TS U5883 ( .A0(n5316), .A1(n3758), .B0(n3757), .Y(n5289) );
NOR2X6TS U5884 ( .A(n5300), .B(n5293), .Y(n3760) );
NAND2X4TS U5885 ( .A(n3760), .B(n5299), .Y(n3762) );
OAI21X4TS U5886 ( .A0(n5307), .A1(n5312), .B0(n5308), .Y(n5298) );
NAND2X2TS U5887 ( .A(mult_x_23_n802), .B(mult_x_23_n812), .Y(n5294) );
AOI21X4TS U5888 ( .A0(n5298), .A1(n3760), .B0(n3759), .Y(n3761) );
OAI21X4TS U5889 ( .A0(n5289), .A1(n3762), .B0(n3761), .Y(n4766) );
NOR2X4TS U5890 ( .A(mult_x_23_n718), .B(mult_x_23_n725), .Y(n4782) );
NOR2X4TS U5891 ( .A(mult_x_23_n747), .B(mult_x_23_n757), .Y(n4767) );
NOR2X4TS U5892 ( .A(mult_x_23_n737), .B(mult_x_23_n746), .Y(n4771) );
NOR2X4TS U5893 ( .A(n4767), .B(n4771), .Y(n4789) );
NAND2X2TS U5894 ( .A(mult_x_23_n769), .B(mult_x_23_n779), .Y(n5281) );
AOI21X4TS U5895 ( .A0(n5277), .A1(n3765), .B0(n3764), .Y(n4897) );
NAND2X2TS U5896 ( .A(mult_x_23_n737), .B(mult_x_23_n746), .Y(n4772) );
OA21X4TS U5897 ( .A0(n4897), .A1(n3769), .B0(n3768), .Y(n3770) );
NAND2X8TS U5898 ( .A(n3771), .B(n3770), .Y(n3772) );
NOR2X4TS U5899 ( .A(mult_x_23_n717), .B(mult_x_23_n708), .Y(n4856) );
NAND2X4TS U5900 ( .A(n5196), .B(n3773), .Y(n3776) );
NOR2X6TS U5901 ( .A(mult_x_23_n690), .B(mult_x_23_n697), .Y(n5154) );
NAND2X6TS U5902 ( .A(n4917), .B(n3778), .Y(n5161) );
NOR2X4TS U5903 ( .A(mult_x_23_n670), .B(mult_x_23_n674), .Y(n3837) );
NOR2X2TS U5904 ( .A(n5161), .B(n3837), .Y(n5182) );
INVX2TS U5905 ( .A(n5182), .Y(n3780) );
NAND2X4TS U5906 ( .A(mult_x_23_n708), .B(mult_x_23_n717), .Y(n4855) );
OAI21X4TS U5907 ( .A0(n4855), .A1(n4857), .B0(n4858), .Y(n4918) );
NAND2X2TS U5908 ( .A(mult_x_23_n690), .B(mult_x_23_n697), .Y(n5153) );
NAND2X2TS U5909 ( .A(mult_x_23_n675), .B(mult_x_23_n682), .Y(n5200) );
INVX2TS U5910 ( .A(n5200), .Y(n3774) );
AOI21X4TS U5911 ( .A0(n3773), .A1(n5195), .B0(n3774), .Y(n3775) );
OAI21X4TS U5912 ( .A0(n3776), .A1(n5153), .B0(n3775), .Y(n3777) );
AOI21X4TS U5913 ( .A0(n4918), .A1(n3778), .B0(n3777), .Y(n4946) );
NAND2X2TS U5914 ( .A(mult_x_23_n670), .B(mult_x_23_n674), .Y(n5148) );
OAI21X2TS U5915 ( .A0(n4946), .A1(n3837), .B0(n5148), .Y(n5186) );
INVX2TS U5916 ( .A(n5186), .Y(n3779) );
INVX2TS U5917 ( .A(n3836), .Y(n5185) );
NAND2X2TS U5918 ( .A(mult_x_23_n669), .B(mult_x_23_n663), .Y(n5183) );
XNOR2X4TS U5919 ( .A(Op_MX[38]), .B(Op_MX[39]), .Y(n4654) );
NAND2BX4TS U5920 ( .AN(n4654), .B(n4655), .Y(n5569) );
NOR2X4TS U5921 ( .A(n4655), .B(n4654), .Y(n5095) );
XNOR2X2TS U5922 ( .A(Op_MX[39]), .B(Op_MX[40]), .Y(n4653) );
AOI22X1TS U5923 ( .A0(n5825), .A1(n903), .B0(n5096), .B1(n4966), .Y(n3782)
);
OAI21X1TS U5924 ( .A0(n6062), .A1(n5569), .B0(n3782), .Y(n3783) );
NAND2X2TS U5925 ( .A(n5095), .B(n824), .Y(n3784) );
XNOR2X4TS U5926 ( .A(Op_MX[35]), .B(Op_MX[36]), .Y(n3787) );
XOR2X4TS U5927 ( .A(n7500), .B(Op_MX[37]), .Y(n3788) );
NAND2BX4TS U5928 ( .AN(n3787), .B(n3788), .Y(n5620) );
XNOR2X2TS U5929 ( .A(Op_MX[37]), .B(Op_MX[36]), .Y(n3786) );
NOR2BX4TS U5930 ( .AN(n3787), .B(n3786), .Y(n5650) );
NAND3X4TS U5931 ( .A(n3788), .B(n3787), .C(n3786), .Y(n5877) );
OAI21X1TS U5932 ( .A0(n6068), .A1(n5985), .B0(n3789), .Y(n3790) );
XOR2X1TS U5933 ( .A(n3790), .B(n5663), .Y(n3802) );
ADDHX1TS U5934 ( .A(n7498), .B(n3791), .CO(n5093), .S(n5995) );
AOI222X1TS U5935 ( .A0(n5960), .A1(n830), .B0(n5661), .B1(n6055), .C0(n5660),
.C1(n6054), .Y(n3792) );
OAI21X1TS U5936 ( .A0(n1001), .A1(n5878), .B0(n3792), .Y(n3793) );
XOR2X1TS U5937 ( .A(n3793), .B(n5663), .Y(n5994) );
AOI22X2TS U5938 ( .A0(n5653), .A1(n6054), .B0(n5959), .B1(n4966), .Y(n3794)
);
OAI21X2TS U5939 ( .A0(n6062), .A1(n5620), .B0(n3794), .Y(n3795) );
XOR2X2TS U5940 ( .A(n3795), .B(n5663), .Y(n4761) );
OAI21X2TS U5941 ( .A0(n6053), .A1(n5620), .B0(n3797), .Y(n3798) );
AOI222X1TS U5942 ( .A0(n5960), .A1(n6055), .B0(n5661), .B1(n5839), .C0(n5660), .C1(n5213), .Y(n3799) );
OAI21X1TS U5943 ( .A0(n5437), .A1(n5878), .B0(n3799), .Y(n3800) );
ADDFX2TS U5944 ( .A(n3803), .B(n3802), .CI(n3801), .CO(mult_x_23_n930), .S(
mult_x_23_n931) );
INVX2TS U5945 ( .A(n5111), .Y(n3809) );
NAND2X1TS U5946 ( .A(n5112), .B(n3809), .Y(n3811) );
INVX2TS U5947 ( .A(n3804), .Y(n3805) );
INVX2TS U5948 ( .A(n5118), .Y(n3808) );
AOI21X1TS U5949 ( .A0(n5121), .A1(n3809), .B0(n3808), .Y(n3810) );
INVX2TS U5950 ( .A(n5128), .Y(n5125) );
NOR2X4TS U5951 ( .A(n834), .B(n6959), .Y(n6256) );
NOR2X6TS U5952 ( .A(n6256), .B(n6260), .Y(n6245) );
INVX2TS U5953 ( .A(n6245), .Y(n3814) );
NAND2X2TS U5954 ( .A(n6268), .B(n3824), .Y(n3826) );
INVX2TS U5955 ( .A(n3815), .Y(n3821) );
INVX2TS U5956 ( .A(n3816), .Y(n3820) );
NAND2X4TS U5957 ( .A(n6952), .B(n6484), .Y(n6396) );
NAND2X1TS U5958 ( .A(n6288), .B(n6396), .Y(n3817) );
OAI2BB1X4TS U5959 ( .A0N(n3821), .A1N(n3820), .B0(n3819), .Y(n6269) );
INVX2TS U5960 ( .A(n6244), .Y(n3822) );
NAND2X2TS U5961 ( .A(n6989), .B(n925), .Y(n6249) );
OAI21X4TS U5962 ( .A0(n820), .A1(n3826), .B0(n3825), .Y(n3827) );
XNOR2X4TS U5963 ( .A(n3827), .B(n3813), .Y(n3828) );
XNOR2X4TS U5964 ( .A(Op_MY[23]), .B(Op_MY[24]), .Y(n4742) );
XOR2X4TS U5965 ( .A(Op_MY[26]), .B(Op_MY[25]), .Y(n4743) );
BUFX8TS U5966 ( .A(n6237), .Y(n6925) );
XNOR2X2TS U5967 ( .A(Op_MY[24]), .B(Op_MY[25]), .Y(n3829) );
AND3X6TS U5968 ( .A(n4743), .B(n4742), .C(n3829), .Y(n6920) );
NOR2BX4TS U5969 ( .AN(n4742), .B(n3829), .Y(n6239) );
INVX2TS U5970 ( .A(n3813), .Y(n7001) );
AOI21X1TS U5971 ( .A0(n6920), .A1(n926), .B0(n3830), .Y(n3831) );
XOR2X1TS U5972 ( .A(n3832), .B(n7087), .Y(n5113) );
NOR2X2TS U5973 ( .A(mult_x_24_n694), .B(n3833), .Y(n5117) );
INVX2TS U5974 ( .A(n5117), .Y(n3834) );
NAND2X1TS U5975 ( .A(mult_x_24_n694), .B(n3833), .Y(n5116) );
XOR2X4TS U5976 ( .A(n3835), .B(n974), .Y(Sgf_operation_ODD1_right_N51) );
NAND2X4TS U5977 ( .A(n3884), .B(n5149), .Y(n5163) );
BUFX3TS U5978 ( .A(n4965), .Y(n5470) );
AOI21X1TS U5979 ( .A0(n5863), .A1(n5883), .B0(n865), .Y(n3838) );
OAI21X1TS U5980 ( .A0(n5887), .A1(n5470), .B0(n3838), .Y(n3839) );
XOR2X1TS U5981 ( .A(n3839), .B(n6021), .Y(n3876) );
INVX2TS U5982 ( .A(n3876), .Y(n3857) );
INVX2TS U5983 ( .A(n5453), .Y(n3840) );
NAND2X2TS U5984 ( .A(n3840), .B(n3842), .Y(n3845) );
INVX2TS U5985 ( .A(n5452), .Y(n3843) );
AOI21X2TS U5986 ( .A0(n3843), .A1(n3842), .B0(n3841), .Y(n3844) );
OAI21X4TS U5987 ( .A0(n5454), .A1(n3845), .B0(n3844), .Y(n5409) );
INVX2TS U5988 ( .A(n3846), .Y(n5407) );
INVX2TS U5989 ( .A(n5406), .Y(n3847) );
AOI21X4TS U5990 ( .A0(n5409), .A1(n5407), .B0(n3847), .Y(n3852) );
INVX2TS U5991 ( .A(n3848), .Y(n3850) );
NAND2X1TS U5992 ( .A(n3850), .B(n3849), .Y(n3851) );
XNOR2X4TS U5993 ( .A(n3852), .B(n3851), .Y(n5781) );
BUFX3TS U5994 ( .A(n3853), .Y(n6052) );
INVX2TS U5995 ( .A(n973), .Y(n5943) );
AOI21X1TS U5996 ( .A0(n5943), .A1(n5939), .B0(n3854), .Y(n3855) );
OAI21X1TS U5997 ( .A0(n5781), .A1(n6052), .B0(n3855), .Y(n3856) );
OR2X2TS U5998 ( .A(mult_x_23_n638), .B(n3886), .Y(n5258) );
CMPR32X2TS U5999 ( .A(n3857), .B(mult_x_23_n637), .C(n3856), .CO(n3888), .S(
n3886) );
INVX2TS U6000 ( .A(n3858), .Y(n3861) );
OAI21X4TS U6001 ( .A0(n5454), .A1(n3861), .B0(n3860), .Y(n3871) );
NAND2X1TS U6002 ( .A(n3870), .B(n3868), .Y(n3862) );
XOR2X4TS U6003 ( .A(n3871), .B(n3862), .Y(n5925) );
BUFX3TS U6004 ( .A(Op_MY[50]), .Y(n5779) );
AOI21X1TS U6005 ( .A0(n5943), .A1(n5775), .B0(n3863), .Y(n3864) );
OAI21X1TS U6006 ( .A0(n5925), .A1(n6052), .B0(n3864), .Y(n3879) );
INVX2TS U6007 ( .A(n3879), .Y(n3877) );
OAI21X1TS U6008 ( .A0(n5879), .A1(n5470), .B0(n4702), .Y(n3867) );
BUFX3TS U6009 ( .A(n3866), .Y(n6021) );
XOR2X1TS U6010 ( .A(n3867), .B(n6021), .Y(n3875) );
NOR2X4TS U6011 ( .A(n5167), .B(n5177), .Y(n4949) );
NAND2X4TS U6012 ( .A(n3893), .B(n4949), .Y(n3895) );
NOR2X4TS U6013 ( .A(n5163), .B(n3895), .Y(n4921) );
INVX2TS U6014 ( .A(n3868), .Y(n3869) );
AOI21X4TS U6015 ( .A0(n3871), .A1(n3870), .B0(n3869), .Y(n3872) );
XNOR2X4TS U6016 ( .A(n3872), .B(n5769), .Y(n5773) );
AOI21X1TS U6017 ( .A0(n5943), .A1(n5771), .B0(n3873), .Y(n3874) );
OAI21X1TS U6018 ( .A0(n5773), .A1(n6052), .B0(n3874), .Y(n3878) );
CMPR32X2TS U6019 ( .A(n3877), .B(n3876), .C(n3875), .CO(n3896), .S(n3887) );
NOR2X1TS U6020 ( .A(n3897), .B(n3896), .Y(n4922) );
CMPR32X2TS U6021 ( .A(n1034), .B(n3879), .C(n3878), .CO(n3899), .S(n3897) );
AOI21X1TS U6022 ( .A0(n5943), .A1(n5883), .B0(n5899), .Y(n3881) );
OAI21X1TS U6023 ( .A0(n6052), .A1(n5887), .B0(n3881), .Y(n3906) );
INVX2TS U6024 ( .A(n3906), .Y(n3898) );
NOR2X2TS U6025 ( .A(n3899), .B(n3898), .Y(n4929) );
NOR2X1TS U6026 ( .A(n4922), .B(n4929), .Y(n3901) );
BUFX8TS U6027 ( .A(n4946), .Y(n5164) );
NAND2X1TS U6028 ( .A(mult_x_23_n662), .B(mult_x_23_n656), .Y(n5190) );
OAI21X2TS U6029 ( .A0(n5183), .A1(n5189), .B0(n5190), .Y(n3882) );
AOI21X4TS U6030 ( .A0(n3884), .A1(n3883), .B0(n3882), .Y(n5162) );
NAND2X1TS U6031 ( .A(mult_x_23_n647), .B(mult_x_23_n650), .Y(n5178) );
NAND2X1TS U6032 ( .A(mult_x_23_n642), .B(mult_x_23_n646), .Y(n4956) );
INVX2TS U6033 ( .A(n4956), .Y(n5266) );
NAND2X1TS U6034 ( .A(mult_x_23_n639), .B(mult_x_23_n641), .Y(n5272) );
INVX2TS U6035 ( .A(n5272), .Y(n3885) );
NAND2X1TS U6036 ( .A(mult_x_23_n638), .B(n3886), .Y(n4943) );
INVX2TS U6037 ( .A(n4943), .Y(n5257) );
NAND2X1TS U6038 ( .A(n3888), .B(n3887), .Y(n5262) );
INVX2TS U6039 ( .A(n5262), .Y(n3889) );
AOI21X1TS U6040 ( .A0(n5257), .A1(n1012), .B0(n3889), .Y(n3890) );
NAND2X1TS U6041 ( .A(n3899), .B(n3898), .Y(n4930) );
AOI21X1TS U6042 ( .A0(n4923), .A1(n3901), .B0(n3900), .Y(n3902) );
INVX2TS U6043 ( .A(n7339), .Y(n3910) );
INVX2TS U6044 ( .A(n3913), .Y(n3915) );
NAND2X2TS U6045 ( .A(n7323), .B(n4821), .Y(n3919) );
INVX2TS U6046 ( .A(n3923), .Y(n3920) );
INVX2TS U6047 ( .A(n3928), .Y(n3930) );
INVX2TS U6048 ( .A(Sgf_operation_Result[25]), .Y(n3939) );
INVX2TS U6049 ( .A(Sgf_operation_ODD1_Q_left[25]), .Y(n3938) );
INVX2TS U6050 ( .A(Sgf_operation_Result[24]), .Y(n3933) );
INVX2TS U6051 ( .A(Sgf_operation_ODD1_Q_left[24]), .Y(n3932) );
NOR2X2TS U6052 ( .A(n3935), .B(n3934), .Y(n4176) );
CMPR32X2TS U6053 ( .A(n3933), .B(Sgf_operation_ODD1_Q_middle[24]), .C(n3932),
.CO(n3934), .S(n3997) );
INVX2TS U6054 ( .A(Sgf_operation_Result[23]), .Y(n3983) );
INVX2TS U6055 ( .A(Sgf_operation_ODD1_Q_left[23]), .Y(n3982) );
NAND2X1TS U6056 ( .A(n3935), .B(n3934), .Y(n4177) );
OAI21X2TS U6057 ( .A0(n4176), .A1(n4173), .B0(n4177), .Y(n4181) );
INVX2TS U6058 ( .A(Sgf_operation_ODD1_Q_left[27]), .Y(n3946) );
INVX2TS U6059 ( .A(Sgf_operation_ODD1_Q_right[27]), .Y(n3945) );
INVX2TS U6060 ( .A(Sgf_operation_Result[26]), .Y(n3937) );
INVX2TS U6061 ( .A(Sgf_operation_ODD1_Q_left[26]), .Y(n3936) );
NOR2X2TS U6062 ( .A(n3943), .B(n3942), .Y(n4189) );
NOR2X2TS U6063 ( .A(n3941), .B(n3940), .Y(n4187) );
NOR2X2TS U6064 ( .A(n4189), .B(n4187), .Y(n3998) );
NAND2X1TS U6065 ( .A(n3943), .B(n3942), .Y(n4190) );
OAI21X1TS U6066 ( .A0(n4189), .A1(n4186), .B0(n4190), .Y(n3944) );
AOI21X2TS U6067 ( .A0(n4181), .A1(n3998), .B0(n3944), .Y(n4146) );
INVX2TS U6068 ( .A(Sgf_operation_ODD1_Q_left[28]), .Y(n3948) );
INVX2TS U6069 ( .A(Sgf_operation_ODD1_Q_right[28]), .Y(n3947) );
CMPR32X2TS U6070 ( .A(n3946), .B(Sgf_operation_ODD1_Q_middle[27]), .C(n3945),
.CO(n3952), .S(n3943) );
NOR2X2TS U6071 ( .A(n3953), .B(n3952), .Y(n4198) );
INVX2TS U6072 ( .A(Sgf_operation_ODD1_Q_left[29]), .Y(n3950) );
INVX2TS U6073 ( .A(Sgf_operation_ODD1_Q_right[29]), .Y(n3949) );
CMPR32X2TS U6074 ( .A(Sgf_operation_ODD1_Q_middle[28]), .B(n3948), .C(n3947),
.CO(n3954), .S(n3953) );
NOR2X2TS U6075 ( .A(n3955), .B(n3954), .Y(n4200) );
NOR2X2TS U6076 ( .A(n4198), .B(n4200), .Y(n4150) );
INVX2TS U6077 ( .A(Sgf_operation_ODD1_Q_right[30]), .Y(n3951) );
INVX2TS U6078 ( .A(Sgf_operation_ODD1_Q_left[30]), .Y(n7732) );
CMPR32X2TS U6079 ( .A(Sgf_operation_ODD1_Q_middle[29]), .B(n3950), .C(n3949),
.CO(n3956), .S(n3955) );
NOR2X2TS U6080 ( .A(n3957), .B(n3956), .Y(n4205) );
INVX2TS U6081 ( .A(Sgf_operation_ODD1_Q_right[31]), .Y(n4082) );
INVX2TS U6082 ( .A(Sgf_operation_ODD1_Q_left[31]), .Y(n7724) );
CMPR32X2TS U6083 ( .A(Sgf_operation_ODD1_Q_middle[30]), .B(n3951), .C(n7732),
.CO(n3958), .S(n3957) );
NOR2X2TS U6084 ( .A(n3959), .B(n3958), .Y(n4151) );
NOR2X2TS U6085 ( .A(n4205), .B(n4151), .Y(n3961) );
NAND2X1TS U6086 ( .A(n3955), .B(n3954), .Y(n4201) );
OAI21X2TS U6087 ( .A0(n4200), .A1(n4197), .B0(n4201), .Y(n4149) );
NAND2X1TS U6088 ( .A(n3959), .B(n3958), .Y(n4152) );
OAI21X1TS U6089 ( .A0(n4151), .A1(n4206), .B0(n4152), .Y(n3960) );
OAI21X2TS U6090 ( .A0(n4146), .A1(n3999), .B0(n3962), .Y(n4081) );
INVX2TS U6091 ( .A(Sgf_operation_Result[17]), .Y(n3968) );
INVX2TS U6092 ( .A(Sgf_operation_ODD1_Q_left[17]), .Y(n3967) );
INVX2TS U6093 ( .A(Sgf_operation_Result[16]), .Y(n3964) );
INVX2TS U6094 ( .A(Sgf_operation_ODD1_Q_left[16]), .Y(n3963) );
NOR2X2TS U6095 ( .A(n3966), .B(n3965), .Y(n4359) );
INVX2TS U6096 ( .A(Sgf_operation_Result[15]), .Y(n4051) );
INVX2TS U6097 ( .A(Sgf_operation_ODD1_Q_left[15]), .Y(n4050) );
NAND2X1TS U6098 ( .A(n3966), .B(n3965), .Y(n4360) );
OAI21X2TS U6099 ( .A0(n4359), .A1(n4378), .B0(n4360), .Y(n4334) );
INVX2TS U6100 ( .A(Sgf_operation_Result[18]), .Y(n3970) );
INVX2TS U6101 ( .A(Sgf_operation_ODD1_Q_left[18]), .Y(n3969) );
INVX2TS U6102 ( .A(Sgf_operation_Result[19]), .Y(n3977) );
INVX2TS U6103 ( .A(Sgf_operation_ODD1_Q_left[19]), .Y(n3976) );
NOR2X2TS U6104 ( .A(n4364), .B(n4336), .Y(n4002) );
NAND2X1TS U6105 ( .A(n3974), .B(n3973), .Y(n4337) );
OAI21X1TS U6106 ( .A0(n4336), .A1(n4365), .B0(n4337), .Y(n3975) );
INVX2TS U6107 ( .A(Sgf_operation_Result[20]), .Y(n3979) );
INVX2TS U6108 ( .A(Sgf_operation_ODD1_Q_left[20]), .Y(n3978) );
NOR2X2TS U6109 ( .A(n3986), .B(n3985), .Y(n4345) );
INVX2TS U6110 ( .A(Sgf_operation_Result[21]), .Y(n3981) );
INVX2TS U6111 ( .A(Sgf_operation_ODD1_Q_left[21]), .Y(n3980) );
CMPR32X2TS U6112 ( .A(n3979), .B(Sgf_operation_ODD1_Q_middle[20]), .C(n3978),
.CO(n3987), .S(n3986) );
NOR2X2TS U6113 ( .A(n3988), .B(n3987), .Y(n4347) );
NOR2X2TS U6114 ( .A(n4345), .B(n4347), .Y(n4165) );
INVX2TS U6115 ( .A(Sgf_operation_Result[22]), .Y(n3984) );
CMPR32X2TS U6116 ( .A(Sgf_operation_ODD1_Q_middle[21]), .B(n3981), .C(n3980),
.CO(n3989), .S(n3988) );
NOR2X2TS U6117 ( .A(n3990), .B(n3989), .Y(n4352) );
CMPR32X2TS U6118 ( .A(n3983), .B(Sgf_operation_ODD1_Q_middle[23]), .C(n3982),
.CO(n3996), .S(n3992) );
CMPR32X2TS U6119 ( .A(Sgf_operation_ODD1_Q_middle[22]), .B(n3984), .C(
DP_OP_168J24_122_1342_n617), .CO(n3991), .S(n3990) );
NOR2X2TS U6120 ( .A(n3992), .B(n3991), .Y(n4166) );
NOR2X2TS U6121 ( .A(n4352), .B(n4166), .Y(n3994) );
NAND2X4TS U6122 ( .A(n4165), .B(n3994), .Y(n4003) );
NAND2X1TS U6123 ( .A(n3988), .B(n3987), .Y(n4348) );
OAI21X2TS U6124 ( .A0(n4347), .A1(n4344), .B0(n4348), .Y(n4164) );
NAND2X1TS U6125 ( .A(n3992), .B(n3991), .Y(n4167) );
OAI21X1TS U6126 ( .A0(n4166), .A1(n4353), .B0(n4167), .Y(n3993) );
AOI21X2TS U6127 ( .A0(n4164), .A1(n3994), .B0(n3993), .Y(n3995) );
NOR2X2TS U6128 ( .A(n3997), .B(n3996), .Y(n4174) );
NOR2X2TS U6129 ( .A(n4174), .B(n4176), .Y(n4182) );
NAND2X2TS U6130 ( .A(n4182), .B(n3998), .Y(n4145) );
NOR2X4TS U6131 ( .A(n3999), .B(n4145), .Y(n4079) );
NOR2X4TS U6132 ( .A(n4160), .B(n4003), .Y(n4141) );
NAND2X4TS U6133 ( .A(n4079), .B(n4141), .Y(n4078) );
INVX2TS U6134 ( .A(Sgf_operation_Result[1]), .Y(n4007) );
INVX2TS U6135 ( .A(Sgf_operation_ODD1_Q_left[1]), .Y(n4005) );
NOR2X2TS U6136 ( .A(n4006), .B(n4005), .Y(n4221) );
OR2X2TS U6137 ( .A(DP_OP_168J24_122_1342_n587), .B(
Sgf_operation_ODD1_Q_middle[0]), .Y(n4227) );
INVX2TS U6138 ( .A(Sgf_operation_ODD1_Q_left[0]), .Y(n4228) );
NAND2X2TS U6139 ( .A(DP_OP_168J24_122_1342_n587), .B(
Sgf_operation_ODD1_Q_middle[0]), .Y(n4226) );
INVX2TS U6140 ( .A(n4226), .Y(n4004) );
AOI21X2TS U6141 ( .A0(n4227), .A1(n4228), .B0(n4004), .Y(n4224) );
NAND2X2TS U6142 ( .A(n4006), .B(n4005), .Y(n4222) );
OAI21X4TS U6143 ( .A0(n4221), .A1(n4224), .B0(n4222), .Y(n4210) );
INVX2TS U6144 ( .A(Sgf_operation_ODD1_Q_left[2]), .Y(n4008) );
NOR2X4TS U6145 ( .A(n4011), .B(n4010), .Y(n4214) );
INVX2TS U6146 ( .A(Sgf_operation_Result[3]), .Y(n4017) );
INVX2TS U6147 ( .A(Sgf_operation_ODD1_Q_left[3]), .Y(n4016) );
CMPR32X2TS U6148 ( .A(n4009), .B(Sgf_operation_ODD1_Q_middle[2]), .C(n4008),
.CO(n4012), .S(n4011) );
NOR2X4TS U6149 ( .A(n4013), .B(n4012), .Y(n4216) );
NOR2X2TS U6150 ( .A(n4214), .B(n4216), .Y(n4015) );
NAND2X2TS U6151 ( .A(n4011), .B(n4010), .Y(n4213) );
NAND2X2TS U6152 ( .A(n4013), .B(n4012), .Y(n4217) );
OAI21X4TS U6153 ( .A0(n4216), .A1(n4213), .B0(n4217), .Y(n4014) );
AOI21X4TS U6154 ( .A0(n4210), .A1(n4015), .B0(n4014), .Y(n4237) );
INVX2TS U6155 ( .A(Sgf_operation_Result[4]), .Y(n4019) );
INVX2TS U6156 ( .A(Sgf_operation_ODD1_Q_left[4]), .Y(n4018) );
CMPR32X2TS U6157 ( .A(Sgf_operation_ODD1_Q_middle[3]), .B(n4017), .C(n4016),
.CO(n4024), .S(n4013) );
NOR2X2TS U6158 ( .A(n4025), .B(n4024), .Y(n4238) );
INVX2TS U6159 ( .A(Sgf_operation_Result[5]), .Y(n4021) );
INVX2TS U6160 ( .A(Sgf_operation_ODD1_Q_left[5]), .Y(n4020) );
CMPR32X2TS U6161 ( .A(Sgf_operation_ODD1_Q_middle[4]), .B(n4019), .C(n4018),
.CO(n4026), .S(n4025) );
NOR2X4TS U6162 ( .A(n4027), .B(n4026), .Y(n4250) );
NOR2X2TS U6163 ( .A(n4238), .B(n4250), .Y(n4243) );
INVX2TS U6164 ( .A(Sgf_operation_Result[6]), .Y(n4023) );
INVX2TS U6165 ( .A(Sgf_operation_ODD1_Q_left[6]), .Y(n4022) );
CMPR32X2TS U6166 ( .A(Sgf_operation_ODD1_Q_middle[5]), .B(n4021), .C(n4020),
.CO(n4028), .S(n4027) );
INVX2TS U6167 ( .A(Sgf_operation_ODD1_Q_left[7]), .Y(n4036) );
CMPR32X2TS U6168 ( .A(Sgf_operation_ODD1_Q_middle[6]), .B(n4023), .C(n4022),
.CO(n4030), .S(n4029) );
NAND2X2TS U6169 ( .A(n4243), .B(n4033), .Y(n4035) );
NAND2X2TS U6170 ( .A(n4025), .B(n4024), .Y(n4246) );
NAND2X2TS U6171 ( .A(n4029), .B(n4028), .Y(n4263) );
NAND2X1TS U6172 ( .A(n4031), .B(n4030), .Y(n4267) );
AOI21X4TS U6173 ( .A0(n4242), .A1(n4033), .B0(n4032), .Y(n4034) );
OAI21X4TS U6174 ( .A0(n4237), .A1(n4035), .B0(n4034), .Y(n4260) );
INVX2TS U6175 ( .A(Sgf_operation_Result[8]), .Y(n4039) );
INVX2TS U6176 ( .A(Sgf_operation_ODD1_Q_left[8]), .Y(n4038) );
CMPR32X2TS U6177 ( .A(n4037), .B(Sgf_operation_ODD1_Q_middle[7]), .C(n4036),
.CO(n4054), .S(n4031) );
NOR2X2TS U6178 ( .A(n4055), .B(n4054), .Y(n4278) );
INVX2TS U6179 ( .A(Sgf_operation_ODD1_Q_left[9]), .Y(n4040) );
CMPR32X2TS U6180 ( .A(n4039), .B(Sgf_operation_ODD1_Q_middle[8]), .C(n4038),
.CO(n4056), .S(n4055) );
NOR2X2TS U6181 ( .A(n4278), .B(n4279), .Y(n4271) );
INVX2TS U6182 ( .A(Sgf_operation_Result[10]), .Y(n4043) );
INVX2TS U6183 ( .A(Sgf_operation_ODD1_Q_left[10]), .Y(n4042) );
NOR2X2TS U6184 ( .A(n4059), .B(n4058), .Y(n4275) );
INVX2TS U6185 ( .A(Sgf_operation_Result[11]), .Y(n4045) );
INVX2TS U6186 ( .A(Sgf_operation_ODD1_Q_left[11]), .Y(n4044) );
CMPR32X2TS U6187 ( .A(Sgf_operation_ODD1_Q_middle[10]), .B(n4043), .C(n4042),
.CO(n4060), .S(n4059) );
NOR2X4TS U6188 ( .A(n4061), .B(n4060), .Y(n4300) );
INVX2TS U6189 ( .A(Sgf_operation_Result[12]), .Y(n4047) );
INVX2TS U6190 ( .A(Sgf_operation_ODD1_Q_left[12]), .Y(n4046) );
CMPR32X2TS U6191 ( .A(Sgf_operation_ODD1_Q_middle[11]), .B(n4045), .C(n4044),
.CO(n4064), .S(n4061) );
NOR2X2TS U6192 ( .A(n4065), .B(n4064), .Y(n4308) );
INVX2TS U6193 ( .A(Sgf_operation_Result[13]), .Y(n4049) );
INVX2TS U6194 ( .A(Sgf_operation_ODD1_Q_left[13]), .Y(n4048) );
CMPR32X2TS U6195 ( .A(Sgf_operation_ODD1_Q_middle[12]), .B(n4047), .C(n4046),
.CO(n4066), .S(n4065) );
NOR2X4TS U6196 ( .A(n4067), .B(n4066), .Y(n4314) );
NOR2X2TS U6197 ( .A(n4308), .B(n4314), .Y(n4319) );
INVX2TS U6198 ( .A(Sgf_operation_Result[14]), .Y(n4053) );
INVX2TS U6199 ( .A(Sgf_operation_ODD1_Q_left[14]), .Y(n4052) );
CMPR32X2TS U6200 ( .A(n4049), .B(Sgf_operation_ODD1_Q_middle[13]), .C(n4048),
.CO(n4068), .S(n4067) );
NAND2X4TS U6201 ( .A(n4319), .B(n4073), .Y(n4075) );
NAND2X2TS U6202 ( .A(n4055), .B(n4054), .Y(n4277) );
NAND2X2TS U6203 ( .A(n4059), .B(n4058), .Y(n4296) );
OAI21X2TS U6204 ( .A0(n4300), .A1(n4296), .B0(n4301), .Y(n4062) );
AOI21X4TS U6205 ( .A0(n4272), .A1(n4063), .B0(n4062), .Y(n4305) );
NAND2X2TS U6206 ( .A(n4065), .B(n4064), .Y(n4310) );
NAND2X1TS U6207 ( .A(n4067), .B(n4066), .Y(n4315) );
OAI21X2TS U6208 ( .A0(n4314), .A1(n4310), .B0(n4315), .Y(n4320) );
NAND2X1TS U6209 ( .A(n4071), .B(n4070), .Y(n4374) );
OAI21X4TS U6210 ( .A0(n4305), .A1(n4075), .B0(n4074), .Y(n4076) );
AOI21X4TS U6211 ( .A0(n4260), .A1(n4077), .B0(n4076), .Y(n4140) );
AOI2BB2X4TS U6212 ( .B0(n4142), .B1(n4079), .A0N(n4078), .A1N(n4140), .Y(
n4080) );
NAND2BX4TS U6213 ( .AN(n4081), .B(n4080), .Y(n4525) );
INVX2TS U6214 ( .A(Sgf_operation_ODD1_Q_left[32]), .Y(n7710) );
INVX2TS U6215 ( .A(Sgf_operation_ODD1_Q_right[32]), .Y(n4083) );
CMPR32X2TS U6216 ( .A(Sgf_operation_ODD1_Q_middle[31]), .B(n4082), .C(n7724),
.CO(n4084), .S(n3959) );
NOR2X2TS U6217 ( .A(n4085), .B(n4084), .Y(n4156) );
INVX2TS U6218 ( .A(Sgf_operation_ODD1_Q_left[33]), .Y(n7702) );
INVX2TS U6219 ( .A(Sgf_operation_ODD1_Q_right[33]), .Y(n4090) );
CMPR32X2TS U6220 ( .A(Sgf_operation_ODD1_Q_middle[32]), .B(n7710), .C(n4083),
.CO(n4086), .S(n4085) );
NOR2X2TS U6221 ( .A(n4087), .B(n4086), .Y(n4131) );
INVX2TS U6222 ( .A(n4101), .Y(n4089) );
NAND2X1TS U6223 ( .A(n4087), .B(n4086), .Y(n4132) );
OAI21X1TS U6224 ( .A0(n4131), .A1(n4157), .B0(n4132), .Y(n4106) );
OAI21X2TS U6225 ( .A0(n4488), .A1(n4089), .B0(n4088), .Y(n4139) );
INVX2TS U6226 ( .A(Sgf_operation_ODD1_Q_left[34]), .Y(n7692) );
INVX2TS U6227 ( .A(Sgf_operation_ODD1_Q_right[34]), .Y(n4094) );
CMPR32X2TS U6228 ( .A(Sgf_operation_ODD1_Q_middle[33]), .B(n7702), .C(n4090),
.CO(n4091), .S(n4087) );
NOR2X1TS U6229 ( .A(n4092), .B(n4091), .Y(n4100) );
INVX2TS U6230 ( .A(n4100), .Y(n4137) );
INVX2TS U6231 ( .A(n4136), .Y(n4093) );
INVX2TS U6232 ( .A(Sgf_operation_ODD1_Q_left[35]), .Y(n7685) );
INVX2TS U6233 ( .A(Sgf_operation_ODD1_Q_right[35]), .Y(n4107) );
CMPR32X2TS U6234 ( .A(Sgf_operation_ODD1_Q_middle[34]), .B(n7692), .C(n4094),
.CO(n4095), .S(n4092) );
NOR2X2TS U6235 ( .A(n4096), .B(n4095), .Y(n4103) );
NAND2X1TS U6236 ( .A(n4096), .B(n4095), .Y(n4102) );
NAND2X1TS U6237 ( .A(n4097), .B(n4102), .Y(n4098) );
NOR2X2TS U6238 ( .A(n4418), .B(Sgf_operation_ODD1_Q_left[8]), .Y(n8046) );
NOR2X2TS U6239 ( .A(n4100), .B(n4103), .Y(n4105) );
NAND2X2TS U6240 ( .A(n4101), .B(n4105), .Y(n4434) );
OAI21X1TS U6241 ( .A0(n4103), .A1(n4136), .B0(n4102), .Y(n4104) );
AOI21X4TS U6242 ( .A0(n4106), .A1(n4105), .B0(n4104), .Y(n4442) );
OAI21X4TS U6243 ( .A0(n4488), .A1(n4434), .B0(n4442), .Y(n4113) );
INVX2TS U6244 ( .A(Sgf_operation_ODD1_Q_right[36]), .Y(n4114) );
INVX2TS U6245 ( .A(Sgf_operation_ODD1_Q_left[36]), .Y(n7673) );
CMPR32X2TS U6246 ( .A(Sgf_operation_ODD1_Q_middle[35]), .B(n7685), .C(n4107),
.CO(n4108), .S(n4096) );
NOR2X1TS U6247 ( .A(n4109), .B(n4108), .Y(n4120) );
INVX2TS U6248 ( .A(n4120), .Y(n4112) );
NAND2X1TS U6249 ( .A(n4112), .B(n4122), .Y(n4110) );
NOR2X2TS U6250 ( .A(n4419), .B(Sgf_operation_ODD1_Q_left[9]), .Y(n8033) );
NOR2X2TS U6251 ( .A(n8046), .B(n8033), .Y(n8005) );
INVX2TS U6252 ( .A(n4122), .Y(n4111) );
INVX2TS U6253 ( .A(Sgf_operation_ODD1_Q_left[37]), .Y(n4647) );
INVX2TS U6254 ( .A(Sgf_operation_ODD1_Q_right[37]), .Y(n4127) );
CMPR32X2TS U6255 ( .A(Sgf_operation_ODD1_Q_middle[36]), .B(n4114), .C(n7673),
.CO(n4115), .S(n4109) );
NOR2X2TS U6256 ( .A(n4116), .B(n4115), .Y(n4123) );
NAND2X1TS U6257 ( .A(n4116), .B(n4115), .Y(n4121) );
NAND2X1TS U6258 ( .A(n4117), .B(n4121), .Y(n4118) );
NOR2X2TS U6259 ( .A(n4420), .B(Sgf_operation_ODD1_Q_left[10]), .Y(n8017) );
NOR2X2TS U6260 ( .A(n4120), .B(n4123), .Y(n4433) );
INVX2TS U6261 ( .A(n4439), .Y(n4124) );
OAI21X4TS U6262 ( .A0(n4126), .A1(n4125), .B0(n4124), .Y(n4556) );
INVX2TS U6263 ( .A(Sgf_operation_ODD1_Q_left[38]), .Y(n7656) );
INVX2TS U6264 ( .A(Sgf_operation_ODD1_Q_right[38]), .Y(n4431) );
CMPR32X2TS U6265 ( .A(Sgf_operation_ODD1_Q_middle[37]), .B(n4647), .C(n4127),
.CO(n4128), .S(n4116) );
NOR2X2TS U6266 ( .A(n4129), .B(n4128), .Y(n4432) );
INVX2TS U6267 ( .A(n4432), .Y(n4555) );
NAND2X1TS U6268 ( .A(n4555), .B(n4553), .Y(n4130) );
NOR2X2TS U6269 ( .A(n4421), .B(Sgf_operation_ODD1_Q_left[11]), .Y(n8006) );
OAI21X1TS U6270 ( .A0(n4488), .A1(n4156), .B0(n4157), .Y(n4135) );
INVX2TS U6271 ( .A(n4131), .Y(n4133) );
NAND2X1TS U6272 ( .A(n4133), .B(n4132), .Y(n4134) );
NOR2X2TS U6273 ( .A(n4414), .B(Sgf_operation_ODD1_Q_left[6]), .Y(n8076) );
NAND2X1TS U6274 ( .A(n4137), .B(n4136), .Y(n4138) );
XNOR2X1TS U6275 ( .A(n4139), .B(n4138), .Y(n4415) );
NOR2X2TS U6276 ( .A(n4415), .B(Sgf_operation_ODD1_Q_left[7]), .Y(n8063) );
NAND2X8TS U6277 ( .A(n4144), .B(n4143), .Y(n4183) );
INVX2TS U6278 ( .A(n4145), .Y(n4148) );
INVX2TS U6279 ( .A(n4146), .Y(n4147) );
AOI21X4TS U6280 ( .A0(n4183), .A1(n4148), .B0(n4147), .Y(n4199) );
INVX4TS U6281 ( .A(n4199), .Y(n4196) );
AOI21X4TS U6282 ( .A0(n4196), .A1(n4150), .B0(n4149), .Y(n4209) );
NAND2X1TS U6283 ( .A(n4153), .B(n4152), .Y(n4154) );
XNOR2X2TS U6284 ( .A(n4155), .B(n4154), .Y(n4412) );
INVX2TS U6285 ( .A(n4156), .Y(n4158) );
NAND2X1TS U6286 ( .A(n4158), .B(n4157), .Y(n4159) );
XOR2X1TS U6287 ( .A(n4488), .B(n4159), .Y(n4413) );
NOR2X2TS U6288 ( .A(n4413), .B(Sgf_operation_ODD1_Q_left[5]), .Y(n8088) );
NOR2X2TS U6289 ( .A(n8099), .B(n8088), .Y(n8062) );
NAND2X2TS U6290 ( .A(n4417), .B(n8062), .Y(n8000) );
INVX2TS U6291 ( .A(n4160), .Y(n4163) );
INVX2TS U6292 ( .A(n4161), .Y(n4162) );
AOI21X4TS U6293 ( .A0(n4381), .A1(n4163), .B0(n4162), .Y(n4346) );
NAND2X1TS U6294 ( .A(n4168), .B(n4167), .Y(n4169) );
XNOR2X2TS U6295 ( .A(n4170), .B(n4169), .Y(n4398) );
INVX2TS U6296 ( .A(n4174), .Y(n4171) );
NAND2X1TS U6297 ( .A(n4171), .B(n4173), .Y(n4172) );
XNOR2X1TS U6298 ( .A(n4183), .B(n4172), .Y(n4399) );
NOR2X2TS U6299 ( .A(n4399), .B(Sgf_operation_ODD1_Q_right[51]), .Y(n8347) );
NOR2X2TS U6300 ( .A(n8340), .B(n8347), .Y(n8161) );
OAI21X1TS U6301 ( .A0(n4175), .A1(n4174), .B0(n4173), .Y(n4180) );
NAND2X1TS U6302 ( .A(n4178), .B(n4177), .Y(n4179) );
NOR2X2TS U6303 ( .A(n4400), .B(Sgf_operation_ODD1_Q_right[52]), .Y(n8171) );
NAND2X1TS U6304 ( .A(n4184), .B(n4186), .Y(n4185) );
CLKXOR2X2TS U6305 ( .A(n4188), .B(n4185), .Y(n4401) );
NOR2X2TS U6306 ( .A(n4401), .B(Sgf_operation_ODD1_Q_right[53]), .Y(n8162) );
OAI21X1TS U6307 ( .A0(n4188), .A1(n4187), .B0(n4186), .Y(n4193) );
NAND2X1TS U6308 ( .A(n4191), .B(n4190), .Y(n4192) );
NOR2X2TS U6309 ( .A(n4404), .B(Sgf_operation_ODD1_Q_left[0]), .Y(n8149) );
INVX2TS U6310 ( .A(n4198), .Y(n4194) );
NAND2X1TS U6311 ( .A(n4194), .B(n4197), .Y(n4195) );
XNOR2X1TS U6312 ( .A(n4196), .B(n4195), .Y(n4405) );
NOR2X2TS U6313 ( .A(n4405), .B(Sgf_operation_ODD1_Q_left[1]), .Y(n8140) );
OAI21X1TS U6314 ( .A0(n4199), .A1(n4198), .B0(n4197), .Y(n4204) );
CLKINVX1TS U6315 ( .A(n4200), .Y(n4202) );
NAND2X1TS U6316 ( .A(n4202), .B(n4201), .Y(n4203) );
XNOR2X1TS U6317 ( .A(n4204), .B(n4203), .Y(n4406) );
NOR2X2TS U6318 ( .A(n4406), .B(Sgf_operation_ODD1_Q_left[2]), .Y(n8128) );
NAND2X1TS U6319 ( .A(n4207), .B(n4206), .Y(n4208) );
NOR2X2TS U6320 ( .A(n4407), .B(Sgf_operation_ODD1_Q_left[3]), .Y(n8117) );
NAND2X4TS U6321 ( .A(n4427), .B(n7999), .Y(n4429) );
INVX2TS U6322 ( .A(n4210), .Y(n4215) );
INVX2TS U6323 ( .A(n4214), .Y(n4211) );
NAND2X1TS U6324 ( .A(n4211), .B(n4213), .Y(n4212) );
XOR2X1TS U6325 ( .A(n4215), .B(n4212), .Y(n4232) );
OAI21X1TS U6326 ( .A0(n4215), .A1(n4214), .B0(n4213), .Y(n4220) );
NAND2X1TS U6327 ( .A(n4218), .B(n4217), .Y(n4219) );
XNOR2X1TS U6328 ( .A(n4220), .B(n4219), .Y(n4233) );
INVX1TS U6329 ( .A(n4221), .Y(n4223) );
NAND2X1TS U6330 ( .A(n4223), .B(n4222), .Y(n4225) );
XOR2X1TS U6331 ( .A(n4225), .B(n4224), .Y(n4230) );
NAND2X1TS U6332 ( .A(n4227), .B(n4226), .Y(n4229) );
XNOR2X1TS U6333 ( .A(n4229), .B(n4228), .Y(n8193) );
NAND2X1TS U6334 ( .A(n8193), .B(Sgf_operation_ODD1_Q_right[27]), .Y(n8194)
);
INVX2TS U6335 ( .A(n8194), .Y(n8198) );
NAND2X1TS U6336 ( .A(n4230), .B(Sgf_operation_ODD1_Q_right[28]), .Y(n8197)
);
INVX2TS U6337 ( .A(n8197), .Y(n4231) );
NAND2X1TS U6338 ( .A(n4232), .B(Sgf_operation_ODD1_Q_right[29]), .Y(n8201)
);
INVX2TS U6339 ( .A(n8201), .Y(n8205) );
NAND2X1TS U6340 ( .A(n4233), .B(Sgf_operation_ODD1_Q_right[30]), .Y(n8207)
);
INVX2TS U6341 ( .A(n8207), .Y(n4234) );
AOI21X1TS U6342 ( .A0(n8205), .A1(n731), .B0(n4234), .Y(n4235) );
INVX4TS U6343 ( .A(n4237), .Y(n4249) );
INVX2TS U6344 ( .A(n4238), .Y(n4248) );
NAND2X1TS U6345 ( .A(n4248), .B(n4246), .Y(n4239) );
XNOR2X1TS U6346 ( .A(n4249), .B(n4239), .Y(n4240) );
NAND2X1TS U6347 ( .A(n4240), .B(Sgf_operation_ODD1_Q_right[31]), .Y(n8211)
);
INVX2TS U6348 ( .A(n8211), .Y(n4241) );
AOI21X2TS U6349 ( .A0(n8213), .A1(n991), .B0(n4241), .Y(n8215) );
AOI21X4TS U6350 ( .A0(n4249), .A1(n4243), .B0(n4242), .Y(n4265) );
NAND2X1TS U6351 ( .A(n4244), .B(n4263), .Y(n4245) );
XOR2X1TS U6352 ( .A(n4265), .B(n4245), .Y(n4256) );
INVX2TS U6353 ( .A(n4246), .Y(n4247) );
AOI21X1TS U6354 ( .A0(n4249), .A1(n4248), .B0(n4247), .Y(n4254) );
NAND2X1TS U6355 ( .A(n4252), .B(n4251), .Y(n4253) );
XOR2X1TS U6356 ( .A(n4254), .B(n4253), .Y(n4255) );
NAND2X1TS U6357 ( .A(n990), .B(n987), .Y(n4259) );
NAND2X1TS U6358 ( .A(n4255), .B(Sgf_operation_ODD1_Q_right[32]), .Y(n8216)
);
INVX2TS U6359 ( .A(n8216), .Y(n8219) );
NAND2X1TS U6360 ( .A(n4256), .B(Sgf_operation_ODD1_Q_right[33]), .Y(n8221)
);
INVX2TS U6361 ( .A(n8221), .Y(n4257) );
AOI21X1TS U6362 ( .A0(n990), .A1(n8219), .B0(n4257), .Y(n4258) );
OAI21X4TS U6363 ( .A0(n8215), .A1(n4259), .B0(n4258), .Y(n8226) );
INVX4TS U6364 ( .A(n4260), .Y(n4307) );
NAND2X1TS U6365 ( .A(n4261), .B(n4277), .Y(n4262) );
XOR2X1TS U6366 ( .A(n4307), .B(n4262), .Y(n4286) );
OAI21X1TS U6367 ( .A0(n4265), .A1(n4264), .B0(n4263), .Y(n4270) );
NAND2X1TS U6368 ( .A(n4268), .B(n4267), .Y(n4269) );
XNOR2X1TS U6369 ( .A(n4270), .B(n4269), .Y(n4285) );
INVX2TS U6370 ( .A(n8231), .Y(n8227) );
OAI21X2TS U6371 ( .A0(n4307), .A1(n4274), .B0(n4273), .Y(n4299) );
NAND2X1TS U6372 ( .A(n4298), .B(n4296), .Y(n4276) );
XNOR2X1TS U6373 ( .A(n4299), .B(n4276), .Y(n4290) );
OAI21X1TS U6374 ( .A0(n4307), .A1(n4278), .B0(n4277), .Y(n4283) );
INVX2TS U6375 ( .A(n4279), .Y(n4281) );
NAND2X1TS U6376 ( .A(n4281), .B(n4280), .Y(n4282) );
XNOR2X1TS U6377 ( .A(n4283), .B(n4282), .Y(n4289) );
NOR2X2TS U6378 ( .A(n8237), .B(n4293), .Y(n4295) );
INVX2TS U6379 ( .A(n8230), .Y(n4288) );
NAND2X1TS U6380 ( .A(n4286), .B(Sgf_operation_ODD1_Q_right[35]), .Y(n8232)
);
INVX2TS U6381 ( .A(n8232), .Y(n4287) );
AOI21X2TS U6382 ( .A0(n988), .A1(n4288), .B0(n4287), .Y(n8236) );
NAND2X1TS U6383 ( .A(n4289), .B(Sgf_operation_ODD1_Q_right[36]), .Y(n8239)
);
INVX2TS U6384 ( .A(n8239), .Y(n8242) );
NAND2X1TS U6385 ( .A(n4290), .B(Sgf_operation_ODD1_Q_right[37]), .Y(n8244)
);
INVX2TS U6386 ( .A(n8244), .Y(n4291) );
AOI21X1TS U6387 ( .A0(n989), .A1(n8242), .B0(n4291), .Y(n4292) );
OAI21X1TS U6388 ( .A0(n8236), .A1(n4293), .B0(n4292), .Y(n4294) );
INVX2TS U6389 ( .A(n4296), .Y(n4297) );
AOI21X1TS U6390 ( .A0(n4299), .A1(n4298), .B0(n4297), .Y(n4304) );
NAND2X1TS U6391 ( .A(n4302), .B(n4301), .Y(n4303) );
CLKXOR2X2TS U6392 ( .A(n4304), .B(n4303), .Y(n4326) );
INVX4TS U6393 ( .A(n4313), .Y(n4323) );
INVX2TS U6394 ( .A(n4308), .Y(n4312) );
NAND2X1TS U6395 ( .A(n4312), .B(n4310), .Y(n4309) );
XOR2X1TS U6396 ( .A(n4323), .B(n4309), .Y(n4327) );
NOR2X2TS U6397 ( .A(n4327), .B(Sgf_operation_ODD1_Q_right[39]), .Y(n8255) );
INVX2TS U6398 ( .A(n4310), .Y(n4311) );
AOI21X1TS U6399 ( .A0(n4313), .A1(n4312), .B0(n4311), .Y(n4318) );
NAND2X1TS U6400 ( .A(n4316), .B(n4315), .Y(n4317) );
NOR2X2TS U6401 ( .A(n4328), .B(Sgf_operation_ODD1_Q_right[40]), .Y(n8316) );
INVX2TS U6402 ( .A(n4319), .Y(n4322) );
NAND2X1TS U6403 ( .A(n4371), .B(n4369), .Y(n4325) );
XNOR2X1TS U6404 ( .A(n4372), .B(n4325), .Y(n4329) );
NOR2X2TS U6405 ( .A(n4329), .B(Sgf_operation_ODD1_Q_right[41]), .Y(n8310) );
NOR2X2TS U6406 ( .A(n8316), .B(n8310), .Y(n4331) );
NAND2X2TS U6407 ( .A(n4326), .B(Sgf_operation_ODD1_Q_right[38]), .Y(n8252)
);
NAND2X1TS U6408 ( .A(n4327), .B(Sgf_operation_ODD1_Q_right[39]), .Y(n8256)
);
OAI21X1TS U6409 ( .A0(n8252), .A1(n8255), .B0(n8256), .Y(n8307) );
NAND2X1TS U6410 ( .A(n4329), .B(Sgf_operation_ODD1_Q_right[41]), .Y(n8311)
);
AOI21X1TS U6411 ( .A0(n4331), .A1(n8307), .B0(n4330), .Y(n4332) );
OAI21X4TS U6412 ( .A0(n8248), .A1(n4333), .B0(n4332), .Y(n8261) );
OAI21X1TS U6413 ( .A0(n4368), .A1(n4364), .B0(n4365), .Y(n4340) );
NAND2X1TS U6414 ( .A(n4338), .B(n4337), .Y(n4339) );
NOR2X2TS U6415 ( .A(n4388), .B(Sgf_operation_ODD1_Q_right[46]), .Y(n8264) );
INVX2TS U6416 ( .A(n4345), .Y(n4341) );
NAND2X1TS U6417 ( .A(n4341), .B(n4344), .Y(n4342) );
XNOR2X1TS U6418 ( .A(n4343), .B(n4342), .Y(n4389) );
NOR2X2TS U6419 ( .A(n4389), .B(Sgf_operation_ODD1_Q_right[47]), .Y(n8266) );
OAI21X1TS U6420 ( .A0(n4346), .A1(n4345), .B0(n4344), .Y(n4351) );
NAND2X1TS U6421 ( .A(n4349), .B(n4348), .Y(n4350) );
XNOR2X1TS U6422 ( .A(n4351), .B(n4350), .Y(n4390) );
NAND2X1TS U6423 ( .A(n4354), .B(n4353), .Y(n4355) );
CLKXOR2X2TS U6424 ( .A(n4356), .B(n4355), .Y(n4391) );
NOR2X2TS U6425 ( .A(n4391), .B(Sgf_operation_ODD1_Q_right[49]), .Y(n8334) );
INVX2TS U6426 ( .A(n4357), .Y(n4379) );
INVX2TS U6427 ( .A(n4378), .Y(n4358) );
AOI21X1TS U6428 ( .A0(n4381), .A1(n4379), .B0(n4358), .Y(n4363) );
NAND2X1TS U6429 ( .A(n4361), .B(n4360), .Y(n4362) );
NAND2X1TS U6430 ( .A(n4366), .B(n4365), .Y(n4367) );
NOR2X2TS U6431 ( .A(n4385), .B(Sgf_operation_ODD1_Q_right[45]), .Y(n8283) );
INVX2TS U6432 ( .A(n4369), .Y(n4370) );
AOI21X1TS U6433 ( .A0(n4372), .A1(n4371), .B0(n4370), .Y(n4377) );
NAND2X1TS U6434 ( .A(n4375), .B(n4374), .Y(n4376) );
CLKXOR2X2TS U6435 ( .A(n4377), .B(n4376), .Y(n4382) );
NOR2X2TS U6436 ( .A(n4382), .B(Sgf_operation_ODD1_Q_right[42]), .Y(n8301) );
NAND2X1TS U6437 ( .A(n4379), .B(n4378), .Y(n4380) );
XNOR2X1TS U6438 ( .A(n4381), .B(n4380), .Y(n4383) );
NOR2X2TS U6439 ( .A(n4383), .B(Sgf_operation_ODD1_Q_right[43]), .Y(n8295) );
NAND2X2TS U6440 ( .A(n4387), .B(n8277), .Y(n8263) );
NOR2X2TS U6441 ( .A(n4395), .B(n8263), .Y(n4397) );
NAND2X2TS U6442 ( .A(n4382), .B(Sgf_operation_ODD1_Q_right[42]), .Y(n8302)
);
NAND2X1TS U6443 ( .A(n4383), .B(Sgf_operation_ODD1_Q_right[43]), .Y(n8296)
);
NAND2X1TS U6444 ( .A(n4385), .B(Sgf_operation_ODD1_Q_right[45]), .Y(n8284)
);
AOI21X2TS U6445 ( .A0(n4387), .A1(n8278), .B0(n4386), .Y(n8262) );
NAND2X2TS U6446 ( .A(n4388), .B(Sgf_operation_ODD1_Q_right[46]), .Y(n8273)
);
NAND2X1TS U6447 ( .A(n4389), .B(Sgf_operation_ODD1_Q_right[47]), .Y(n8267)
);
NAND2X1TS U6448 ( .A(n4391), .B(Sgf_operation_ODD1_Q_right[49]), .Y(n8335)
);
OAI21X2TS U6449 ( .A0(n8262), .A1(n4395), .B0(n4394), .Y(n4396) );
AOI21X4TS U6450 ( .A0(n8261), .A1(n4397), .B0(n4396), .Y(n7997) );
NAND2X1TS U6451 ( .A(n4399), .B(Sgf_operation_ODD1_Q_right[51]), .Y(n8348)
);
NAND2X1TS U6452 ( .A(n4400), .B(Sgf_operation_ODD1_Q_right[52]), .Y(n8172)
);
NAND2X1TS U6453 ( .A(n4401), .B(Sgf_operation_ODD1_Q_right[53]), .Y(n8163)
);
OAI21X1TS U6454 ( .A0(n8162), .A1(n8172), .B0(n8163), .Y(n4402) );
NAND2X2TS U6455 ( .A(n4404), .B(Sgf_operation_ODD1_Q_left[0]), .Y(n8150) );
NAND2X1TS U6456 ( .A(n4405), .B(Sgf_operation_ODD1_Q_left[1]), .Y(n8141) );
OAI21X4TS U6457 ( .A0(n8140), .A1(n8150), .B0(n8141), .Y(n8115) );
NAND2X1TS U6458 ( .A(n4407), .B(Sgf_operation_ODD1_Q_left[3]), .Y(n8118) );
OAI21X4TS U6459 ( .A0(n8112), .A1(n4411), .B0(n4410), .Y(n7998) );
NAND2X2TS U6460 ( .A(n4412), .B(Sgf_operation_ODD1_Q_left[4]), .Y(n8100) );
NAND2X1TS U6461 ( .A(n4413), .B(Sgf_operation_ODD1_Q_left[5]), .Y(n8089) );
OAI21X4TS U6462 ( .A0(n8100), .A1(n8088), .B0(n8089), .Y(n8061) );
NAND2X1TS U6463 ( .A(n4415), .B(Sgf_operation_ODD1_Q_left[7]), .Y(n8064) );
NAND2X1TS U6464 ( .A(n4419), .B(Sgf_operation_ODD1_Q_left[9]), .Y(n8034) );
OAI21X2TS U6465 ( .A0(n8033), .A1(n8047), .B0(n8034), .Y(n8004) );
NAND2X1TS U6466 ( .A(n4420), .B(Sgf_operation_ODD1_Q_left[10]), .Y(n8018) );
NAND2X1TS U6467 ( .A(n4421), .B(Sgf_operation_ODD1_Q_left[11]), .Y(n8007) );
OAI21X2TS U6468 ( .A0(n8006), .A1(n8018), .B0(n8007), .Y(n4422) );
OAI21X4TS U6469 ( .A0(n4429), .A1(n7997), .B0(n4428), .Y(n7770) );
INVX2TS U6470 ( .A(Sgf_operation_ODD1_Q_right[44]), .Y(n4430) );
INVX2TS U6471 ( .A(Sgf_operation_ODD1_Q_left[44]), .Y(n7592) );
INVX2TS U6472 ( .A(Sgf_operation_ODD1_Q_left[43]), .Y(n7603) );
INVX2TS U6473 ( .A(Sgf_operation_ODD1_Q_right[43]), .Y(n4448) );
NOR2X2TS U6474 ( .A(n4462), .B(n4461), .Y(n4591) );
INVX2TS U6475 ( .A(Sgf_operation_ODD1_Q_left[45]), .Y(n7582) );
INVX2TS U6476 ( .A(Sgf_operation_ODD1_Q_right[45]), .Y(n4465) );
CMPR32X2TS U6477 ( .A(Sgf_operation_ODD1_Q_middle[44]), .B(n4430), .C(n7592),
.CO(n4463), .S(n4462) );
NOR2X2TS U6478 ( .A(n4464), .B(n4463), .Y(n4581) );
INVX2TS U6479 ( .A(Sgf_operation_ODD1_Q_left[39]), .Y(n7646) );
INVX2TS U6480 ( .A(Sgf_operation_ODD1_Q_right[39]), .Y(n4445) );
CMPR32X2TS U6481 ( .A(Sgf_operation_ODD1_Q_middle[38]), .B(n7656), .C(n4431),
.CO(n4435), .S(n4129) );
NOR2X2TS U6482 ( .A(n4436), .B(n4435), .Y(n4557) );
NOR2X2TS U6483 ( .A(n4432), .B(n4557), .Y(n4438) );
NOR2X2TS U6484 ( .A(n4434), .B(n4441), .Y(n4476) );
INVX2TS U6485 ( .A(n4476), .Y(n4444) );
NAND2X1TS U6486 ( .A(n4436), .B(n4435), .Y(n4558) );
OAI21X1TS U6487 ( .A0(n4557), .A1(n4553), .B0(n4558), .Y(n4437) );
OAI21X4TS U6488 ( .A0(n4442), .A1(n4441), .B0(n4440), .Y(n4487) );
INVX2TS U6489 ( .A(n4487), .Y(n4443) );
OAI21X4TS U6490 ( .A0(n4488), .A1(n4444), .B0(n4443), .Y(n4567) );
INVX2TS U6491 ( .A(Sgf_operation_ODD1_Q_left[40]), .Y(n7631) );
INVX2TS U6492 ( .A(Sgf_operation_ODD1_Q_right[40]), .Y(n4446) );
CMPR32X2TS U6493 ( .A(Sgf_operation_ODD1_Q_middle[39]), .B(n7646), .C(n4445),
.CO(n4450), .S(n4436) );
INVX2TS U6494 ( .A(Sgf_operation_ODD1_Q_left[41]), .Y(n7622) );
INVX2TS U6495 ( .A(Sgf_operation_ODD1_Q_right[41]), .Y(n4447) );
INVX2TS U6496 ( .A(Sgf_operation_ODD1_Q_left[42]), .Y(n7612) );
INVX2TS U6497 ( .A(Sgf_operation_ODD1_Q_right[42]), .Y(n4449) );
CMPR32X2TS U6498 ( .A(Sgf_operation_ODD1_Q_middle[41]), .B(n7622), .C(n4447),
.CO(n4454), .S(n4453) );
CMPR32X2TS U6499 ( .A(Sgf_operation_ODD1_Q_middle[43]), .B(n7603), .C(n4448),
.CO(n4461), .S(n4457) );
NOR2X2TS U6500 ( .A(n4457), .B(n4456), .Y(n4600) );
NOR2X2TS U6501 ( .A(n4578), .B(n4600), .Y(n4459) );
INVX2TS U6502 ( .A(n4475), .Y(n4460) );
NAND2X1TS U6503 ( .A(n4453), .B(n4452), .Y(n4569) );
NAND2X1TS U6504 ( .A(n4457), .B(n4456), .Y(n4601) );
OAI21X1TS U6505 ( .A0(n4600), .A1(n4596), .B0(n4601), .Y(n4458) );
OAI2BB1X4TS U6506 ( .A0N(n4567), .A1N(n4460), .B0(n4484), .Y(n4580) );
NAND2X1TS U6507 ( .A(n4464), .B(n4463), .Y(n4582) );
AOI21X2TS U6508 ( .A0(n4474), .A1(n4580), .B0(n4481), .Y(n4590) );
INVX2TS U6509 ( .A(Sgf_operation_ODD1_Q_left[46]), .Y(n7569) );
INVX2TS U6510 ( .A(Sgf_operation_ODD1_Q_right[46]), .Y(n4468) );
CMPR32X2TS U6511 ( .A(Sgf_operation_ODD1_Q_middle[45]), .B(n7582), .C(n4465),
.CO(n4466), .S(n4464) );
INVX2TS U6512 ( .A(Sgf_operation_ODD1_Q_left[47]), .Y(n7562) );
INVX2TS U6513 ( .A(Sgf_operation_ODD1_Q_right[47]), .Y(n4489) );
CMPR32X2TS U6514 ( .A(Sgf_operation_ODD1_Q_middle[46]), .B(n7569), .C(n4468),
.CO(n4469), .S(n4467) );
INVX2TS U6515 ( .A(n4478), .Y(n4471) );
NAND2X1TS U6516 ( .A(n4470), .B(n4469), .Y(n4477) );
NAND2X1TS U6517 ( .A(n4471), .B(n4477), .Y(n4472) );
NOR2X2TS U6518 ( .A(n4475), .B(n4483), .Y(n4486) );
NAND2X2TS U6519 ( .A(n4476), .B(n4486), .Y(n4515) );
OAI21X1TS U6520 ( .A0(n4478), .A1(n4587), .B0(n4477), .Y(n4479) );
AOI21X4TS U6521 ( .A0(n4487), .A1(n4486), .B0(n4485), .Y(n4522) );
INVX2TS U6522 ( .A(n4495), .Y(n4508) );
INVX2TS U6523 ( .A(Sgf_operation_ODD1_Q_left[48]), .Y(n7553) );
INVX2TS U6524 ( .A(Sgf_operation_ODD1_Q_right[48]), .Y(n4496) );
CMPR32X2TS U6525 ( .A(Sgf_operation_ODD1_Q_middle[47]), .B(n7562), .C(n4489),
.CO(n4490), .S(n4470) );
NOR2X1TS U6526 ( .A(n4491), .B(n4490), .Y(n4502) );
INVX2TS U6527 ( .A(n4502), .Y(n4494) );
NAND2X1TS U6528 ( .A(n4494), .B(n4504), .Y(n4492) );
XOR2X1TS U6529 ( .A(n4508), .B(n4492), .Y(n4620) );
NOR2X2TS U6530 ( .A(n4620), .B(Sgf_operation_ODD1_Q_left[21]), .Y(n7861) );
INVX2TS U6531 ( .A(n4504), .Y(n4493) );
AOI21X1TS U6532 ( .A0(n4495), .A1(n4494), .B0(n4493), .Y(n4501) );
INVX2TS U6533 ( .A(Sgf_operation_ODD1_Q_left[49]), .Y(n7541) );
INVX2TS U6534 ( .A(Sgf_operation_ODD1_Q_right[49]), .Y(n4509) );
CMPR32X2TS U6535 ( .A(Sgf_operation_ODD1_Q_middle[48]), .B(n7553), .C(n4496),
.CO(n4497), .S(n4491) );
NOR2X2TS U6536 ( .A(n4498), .B(n4497), .Y(n4505) );
INVX2TS U6537 ( .A(n4505), .Y(n4499) );
NAND2X1TS U6538 ( .A(n4498), .B(n4497), .Y(n4503) );
NAND2X1TS U6539 ( .A(n4499), .B(n4503), .Y(n4500) );
XOR2X1TS U6540 ( .A(n4501), .B(n4500), .Y(n4621) );
NOR2X2TS U6541 ( .A(n4621), .B(Sgf_operation_ODD1_Q_left[22]), .Y(n7833) );
INVX2TS U6542 ( .A(n4514), .Y(n4507) );
OAI21X1TS U6543 ( .A0(n4505), .A1(n4504), .B0(n4503), .Y(n4519) );
INVX2TS U6544 ( .A(Sgf_operation_ODD1_Q_left[50]), .Y(n7511) );
INVX2TS U6545 ( .A(Sgf_operation_ODD1_Q_right[50]), .Y(n4526) );
CMPR32X2TS U6546 ( .A(Sgf_operation_ODD1_Q_middle[49]), .B(n7541), .C(n4509),
.CO(n4510), .S(n4498) );
NAND2X1TS U6547 ( .A(n4511), .B(n4510), .Y(n4516) );
NAND2X1TS U6548 ( .A(n4518), .B(n4516), .Y(n4512) );
NOR2X2TS U6549 ( .A(n4622), .B(Sgf_operation_ODD1_Q_left[23]), .Y(n7835) );
NOR2X2TS U6550 ( .A(n4515), .B(n4521), .Y(n4524) );
INVX2TS U6551 ( .A(n4516), .Y(n4517) );
AOI21X1TS U6552 ( .A0(n4519), .A1(n4518), .B0(n4517), .Y(n4520) );
AOI21X4TS U6553 ( .A0(n4525), .A1(n4524), .B0(n4523), .Y(n4533) );
INVX2TS U6554 ( .A(Sgf_operation_ODD1_Q_left[51]), .Y(n5070) );
INVX2TS U6555 ( .A(Sgf_operation_ODD1_Q_right[51]), .Y(n4534) );
CMPR32X2TS U6556 ( .A(Sgf_operation_ODD1_Q_middle[50]), .B(n7511), .C(n4526),
.CO(n4527), .S(n4511) );
NOR2X1TS U6557 ( .A(n4528), .B(n4527), .Y(n4532) );
INVX2TS U6558 ( .A(n4532), .Y(n4529) );
NAND2X1TS U6559 ( .A(n4529), .B(n4531), .Y(n4530) );
XOR2X1TS U6560 ( .A(n4533), .B(n4530), .Y(n4625) );
NOR2X2TS U6561 ( .A(n4625), .B(Sgf_operation_ODD1_Q_left[24]), .Y(n7815) );
OAI21X4TS U6562 ( .A0(n4533), .A1(n4532), .B0(n4531), .Y(n4541) );
INVX2TS U6563 ( .A(Sgf_operation_ODD1_Q_right[52]), .Y(n4542) );
XNOR2X1TS U6564 ( .A(n4542), .B(Sgf_operation_ODD1_Q_middle[52]), .Y(n4536)
);
CMPR32X2TS U6565 ( .A(Sgf_operation_ODD1_Q_middle[51]), .B(n5070), .C(n4534),
.CO(n4535), .S(n4528) );
NAND2X1TS U6566 ( .A(n4540), .B(n4538), .Y(n4537) );
XNOR2X1TS U6567 ( .A(n4541), .B(n4537), .Y(n4626) );
NOR2X2TS U6568 ( .A(n4626), .B(Sgf_operation_ODD1_Q_left[25]), .Y(n7804) );
NOR2X2TS U6569 ( .A(n7815), .B(n7804), .Y(n7779) );
INVX2TS U6570 ( .A(n4538), .Y(n4539) );
AOI21X4TS U6571 ( .A0(n4541), .A1(n4540), .B0(n4539), .Y(n4549) );
INVX2TS U6572 ( .A(Sgf_operation_ODD1_Q_right[53]), .Y(n4550) );
XNOR2X1TS U6573 ( .A(n4550), .B(Sgf_operation_ODD1_Q_middle[53]), .Y(n4544)
);
INVX2TS U6574 ( .A(n4548), .Y(n4545) );
NAND2X1TS U6575 ( .A(n4545), .B(n4547), .Y(n4546) );
NOR2X2TS U6576 ( .A(n4627), .B(Sgf_operation_ODD1_Q_left[26]), .Y(n7791) );
NAND2X1TS U6577 ( .A(n4638), .B(n4636), .Y(n4552) );
XNOR2X4TS U6578 ( .A(n4639), .B(n4552), .Y(n4628) );
NOR2X2TS U6579 ( .A(n4628), .B(Sgf_operation_ODD1_Q_left[27]), .Y(n7780) );
INVX2TS U6580 ( .A(n4553), .Y(n4554) );
AOI21X2TS U6581 ( .A0(n4556), .A1(n4555), .B0(n4554), .Y(n4561) );
NAND2X1TS U6582 ( .A(n4559), .B(n4558), .Y(n4560) );
NOR2X2TS U6583 ( .A(n4605), .B(Sgf_operation_ODD1_Q_left[12]), .Y(n7983) );
INVX2TS U6584 ( .A(n4562), .Y(n4566) );
NAND2X1TS U6585 ( .A(n4566), .B(n4564), .Y(n4563) );
XOR2X1TS U6586 ( .A(n4577), .B(n4563), .Y(n4606) );
NOR2X2TS U6587 ( .A(n4606), .B(Sgf_operation_ODD1_Q_left[13]), .Y(n7972) );
INVX2TS U6588 ( .A(n4564), .Y(n4565) );
AOI21X1TS U6589 ( .A0(n4567), .A1(n4566), .B0(n4565), .Y(n4572) );
NAND2X1TS U6590 ( .A(n4570), .B(n4569), .Y(n4571) );
NOR2X2TS U6591 ( .A(n4607), .B(Sgf_operation_ODD1_Q_left[14]), .Y(n7948) );
INVX2TS U6592 ( .A(n4573), .Y(n4576) );
INVX2TS U6593 ( .A(n4578), .Y(n4598) );
NAND2X1TS U6594 ( .A(n4598), .B(n4596), .Y(n4579) );
XNOR2X1TS U6595 ( .A(n4599), .B(n4579), .Y(n4608) );
NOR2X2TS U6596 ( .A(n4608), .B(Sgf_operation_ODD1_Q_left[15]), .Y(n7950) );
NAND2X2TS U6597 ( .A(n7944), .B(n4610), .Y(n7886) );
INVX2TS U6598 ( .A(n4581), .Y(n4583) );
NAND2X1TS U6599 ( .A(n4583), .B(n4582), .Y(n4584) );
NOR2X2TS U6600 ( .A(n4613), .B(Sgf_operation_ODD1_Q_left[18]), .Y(n7891) );
INVX2TS U6601 ( .A(n4586), .Y(n4588) );
NAND2X1TS U6602 ( .A(n4588), .B(n4587), .Y(n4589) );
INVX2TS U6603 ( .A(n4591), .Y(n4593) );
NAND2X1TS U6604 ( .A(n4593), .B(n4592), .Y(n4594) );
NOR2X2TS U6605 ( .A(n4612), .B(Sgf_operation_ODD1_Q_left[17]), .Y(n7919) );
INVX2TS U6606 ( .A(n4596), .Y(n4597) );
NAND2X1TS U6607 ( .A(n4602), .B(n4601), .Y(n4603) );
CLKXOR2X2TS U6608 ( .A(n4604), .B(n4603), .Y(n4611) );
NOR2X2TS U6609 ( .A(n4611), .B(Sgf_operation_ODD1_Q_left[16]), .Y(n7916) );
NOR2X4TS U6610 ( .A(n7886), .B(n4618), .Y(n7771) );
NAND2X4TS U6611 ( .A(n4634), .B(n7771), .Y(n5062) );
NAND2X1TS U6612 ( .A(n4606), .B(Sgf_operation_ODD1_Q_left[13]), .Y(n7973) );
NAND2X1TS U6613 ( .A(n4608), .B(Sgf_operation_ODD1_Q_left[15]), .Y(n7951) );
AOI21X2TS U6614 ( .A0(n7945), .A1(n4610), .B0(n4609), .Y(n7885) );
NAND2X1TS U6615 ( .A(n4612), .B(Sgf_operation_ODD1_Q_left[17]), .Y(n7920) );
NAND2X1TS U6616 ( .A(n4614), .B(Sgf_operation_ODD1_Q_left[19]), .Y(n7894) );
AOI21X2TS U6617 ( .A0(n7888), .A1(n4616), .B0(n4615), .Y(n4617) );
OAI21X4TS U6618 ( .A0(n7885), .A1(n4618), .B0(n4617), .Y(n7772) );
NAND2X2TS U6619 ( .A(n4619), .B(Sgf_operation_ODD1_Q_left[20]), .Y(n7872) );
NAND2X1TS U6620 ( .A(n4620), .B(Sgf_operation_ODD1_Q_left[21]), .Y(n7862) );
OAI21X2TS U6621 ( .A0(n7861), .A1(n7872), .B0(n7862), .Y(n7830) );
NAND2X1TS U6622 ( .A(n4622), .B(Sgf_operation_ODD1_Q_left[23]), .Y(n7836) );
NAND2X1TS U6623 ( .A(n4626), .B(Sgf_operation_ODD1_Q_left[25]), .Y(n7805) );
OAI21X2TS U6624 ( .A0(n7804), .A1(n7816), .B0(n7805), .Y(n7778) );
OAI21X2TS U6625 ( .A0(n7780), .A1(n7792), .B0(n7781), .Y(n4629) );
AOI21X4TS U6626 ( .A0(n7772), .A1(n4634), .B0(n4633), .Y(n5067) );
OAI2BB1X4TS U6627 ( .A0N(n7770), .A1N(n4635), .B0(n5067), .Y(n7577) );
XOR2X4TS U6628 ( .A(n4641), .B(Sgf_operation_ODD1_Q_middle[55]), .Y(n4642)
);
INVX2TS U6629 ( .A(Sgf_operation_ODD1_Q_middle[55]), .Y(n4640) );
AND2X4TS U6630 ( .A(n4641), .B(n4640), .Y(n4643) );
NOR2X4TS U6631 ( .A(n7755), .B(n7744), .Y(n5061) );
NAND2X2TS U6632 ( .A(n4642), .B(Sgf_operation_ODD1_Q_left[28]), .Y(n7756) );
OAI21X4TS U6633 ( .A0(n7756), .A1(n7744), .B0(n7745), .Y(n5064) );
AOI21X4TS U6634 ( .A0(n7577), .A1(n5061), .B0(n5064), .Y(n7600) );
NAND2X1TS U6635 ( .A(Sgf_operation_ODD1_Q_left[30]), .B(
Sgf_operation_ODD1_Q_left[31]), .Y(n7700) );
NAND2X1TS U6636 ( .A(Sgf_operation_ODD1_Q_left[32]), .B(
Sgf_operation_ODD1_Q_left[33]), .Y(n4644) );
INVX2TS U6637 ( .A(n5059), .Y(n4645) );
NAND2X1TS U6638 ( .A(Sgf_operation_ODD1_Q_left[34]), .B(
Sgf_operation_ODD1_Q_left[35]), .Y(n5057) );
INVX2TS U6639 ( .A(n5057), .Y(n4646) );
NAND2X4TS U6640 ( .A(n7683), .B(n4646), .Y(n7674) );
XNOR2X4TS U6641 ( .A(n4648), .B(n4647), .Y(n4650) );
INVX2TS U6642 ( .A(n7238), .Y(n4651) );
NAND2X1TS U6643 ( .A(n4651), .B(n7237), .Y(n4652) );
NAND3X4TS U6644 ( .A(n4655), .B(n4654), .C(n4653), .Y(n5594) );
AOI222X1TS U6645 ( .A0(n5825), .A1(n831), .B0(n867), .B1(n5858), .C0(n5997),
.C1(n5856), .Y(n4656) );
OAI21X1TS U6646 ( .A0(n979), .A1(n6007), .B0(n4656), .Y(n4657) );
XOR2X1TS U6647 ( .A(n4657), .B(n7498), .Y(n4670) );
AOI22X2TS U6648 ( .A0(n5845), .A1(n6054), .B0(n5494), .B1(n4966), .Y(n4660)
);
OAI21X2TS U6649 ( .A0(n6062), .A1(n5491), .B0(n4660), .Y(n4661) );
XOR2X2TS U6650 ( .A(n4661), .B(n5847), .Y(n4678) );
OAI21X1TS U6651 ( .A0(n5437), .A1(n5491), .B0(n4662), .Y(n4663) );
XOR2X1TS U6652 ( .A(n4663), .B(n5847), .Y(n5203) );
AOI222X1TS U6653 ( .A0(n6012), .A1(n5758), .B0(n5564), .B1(n8376), .C0(n6010), .C1(n8375), .Y(n4666) );
OAI21X1TS U6654 ( .A0(n5931), .A1(n6014), .B0(n4666), .Y(n4667) );
XOR2X1TS U6655 ( .A(n4667), .B(n5567), .Y(n4668) );
ADDFHX2TS U6656 ( .A(n4670), .B(n4669), .CI(n4668), .CO(mult_x_23_n872), .S(
mult_x_23_n873) );
XOR2X2TS U6657 ( .A(n4674), .B(n5567), .Y(n4686) );
ADDHX1TS U6658 ( .A(n4679), .B(n4678), .CO(n5204), .S(n4691) );
AOI222X1TS U6659 ( .A0(n6012), .A1(n7510), .B0(n5564), .B1(Op_MY[30]), .C0(
n5560), .C1(n5843), .Y(n4680) );
ADDHX1TS U6660 ( .A(n7493), .B(n4682), .CO(n4679), .S(n5140) );
AOI222X1TS U6661 ( .A0(n6012), .A1(n8375), .B0(n5564), .B1(n6055), .C0(n5560), .C1(n5839), .Y(n4683) );
OAI21X1TS U6662 ( .A0(n1001), .A1(n5924), .B0(n4683), .Y(n4684) );
AOI222X1TS U6663 ( .A0(n6012), .A1(n5843), .B0(n5564), .B1(n5839), .C0(n5560), .C1(n5213), .Y(n4687) );
INVX2TS U6664 ( .A(n904), .Y(n4698) );
OAI21X4TS U6665 ( .A0(n4999), .A1(n4991), .B0(n4993), .Y(n5600) );
INVX2TS U6666 ( .A(n4700), .Y(n5599) );
XOR2X4TS U6667 ( .A(n5600), .B(n4701), .Y(n5876) );
BUFX3TS U6668 ( .A(Op_MY[39]), .Y(n5796) );
BUFX3TS U6669 ( .A(Op_MY[38]), .Y(n5982) );
INVX2TS U6670 ( .A(n4702), .Y(n6017) );
OAI21X1TS U6671 ( .A0(n5876), .A1(n6067), .B0(n4703), .Y(n4704) );
XNOR2X4TS U6672 ( .A(Op_MY[18]), .B(n7503), .Y(n4736) );
NOR2BX4TS U6673 ( .AN(n4736), .B(n4735), .Y(n5075) );
BUFX3TS U6674 ( .A(n6861), .Y(n7494) );
OAI21X2TS U6675 ( .A0(n7013), .A1(n764), .B0(n4707), .Y(n4708) );
XNOR2X4TS U6676 ( .A(Op_MY[15]), .B(Op_MY[14]), .Y(n4709) );
XOR2X4TS U6677 ( .A(n835), .B(Op_MY[16]), .Y(n4711) );
BUFX4TS U6678 ( .A(n5087), .Y(n6964) );
XNOR2X2TS U6679 ( .A(Op_MY[15]), .B(Op_MY[16]), .Y(n4710) );
AOI222X1TS U6680 ( .A0(n6964), .A1(n6888), .B0(n6786), .B1(n6886), .C0(n6531), .C1(n6897), .Y(n4712) );
OAI21X1TS U6681 ( .A0(n6900), .A1(n6809), .B0(n4712), .Y(n4713) );
CLKBUFX2TS U6682 ( .A(n8444), .Y(n6517) );
XOR2X1TS U6683 ( .A(n4713), .B(n893), .Y(n4725) );
AOI222X1TS U6684 ( .A0(n6964), .A1(n7042), .B0(n6786), .B1(n7022), .C0(n6531), .C1(n7020), .Y(n4715) );
NAND2X2TS U6685 ( .A(n6796), .B(n825), .Y(n4718) );
OAI21X2TS U6686 ( .A0(n6966), .A1(n764), .B0(n4718), .Y(n4719) );
AOI22X1TS U6687 ( .A0(n6512), .A1(n5041), .B0(n6796), .B1(n6822), .Y(n4720)
);
OAI21X2TS U6688 ( .A0(n5043), .A1(n6788), .B0(n4720), .Y(n4721) );
XOR2X1TS U6689 ( .A(n4723), .B(n892), .Y(n7092) );
ADDFHX2TS U6690 ( .A(n4726), .B(n4725), .CI(n4724), .CO(mult_x_24_n991), .S(
mult_x_24_n992) );
INVX2TS U6691 ( .A(n6217), .Y(n6223) );
NAND2X2TS U6692 ( .A(n6268), .B(n4731), .Y(n4733) );
INVX2TS U6693 ( .A(n6249), .Y(n4729) );
OAI21X4TS U6694 ( .A0(n4733), .A1(n740), .B0(n4732), .Y(n4734) );
AND3X4TS U6695 ( .A(n4737), .B(n4736), .C(n4735), .Y(n5076) );
NAND2X1TS U6696 ( .A(n6491), .B(n6989), .Y(n4738) );
XOR2X1TS U6697 ( .A(n4739), .B(n6220), .Y(n4740) );
NOR2X4TS U6698 ( .A(n4743), .B(n4742), .Y(n6238) );
XOR2X2TS U6699 ( .A(n4744), .B(n6882), .Y(n4811) );
OAI21X2TS U6700 ( .A0(n6925), .A1(n764), .B0(n4745), .Y(n4746) );
XOR2X2TS U6701 ( .A(n4746), .B(n7064), .Y(n4800) );
OAI21X1TS U6702 ( .A0(n7026), .A1(n7062), .B0(n4747), .Y(n4748) );
AOI222X1TS U6703 ( .A0(n6870), .A1(n7035), .B0(n6869), .B1(n7033), .C0(n5076), .C1(n6875), .Y(n4750) );
XNOR2X4TS U6704 ( .A(Op_MY[21]), .B(Op_MY[20]), .Y(n4753) );
XOR2X4TS U6705 ( .A(Op_MY[23]), .B(Op_MY[22]), .Y(n4754) );
NAND2BX4TS U6706 ( .AN(n4753), .B(n4754), .Y(n4805) );
NOR2X4TS U6707 ( .A(n4754), .B(n4753), .Y(n4803) );
BUFX3TS U6708 ( .A(n4803), .Y(n6761) );
XNOR2X2TS U6709 ( .A(Op_MY[21]), .B(Op_MY[22]), .Y(n4752) );
NOR2BX4TS U6710 ( .AN(n4753), .B(n4752), .Y(n6454) );
AND3X6TS U6711 ( .A(n4754), .B(n4753), .C(n4752), .Y(n6405) );
AOI222X1TS U6712 ( .A0(n6761), .A1(n6859), .B0(n7070), .B1(n7044), .C0(n6473), .C1(n6584), .Y(n4755) );
OAI21X1TS U6713 ( .A0(n7050), .A1(n6763), .B0(n4755), .Y(n4756) );
XOR2X1TS U6714 ( .A(n4756), .B(n836), .Y(n4757) );
NAND2X1TS U6715 ( .A(n4764), .B(n4855), .Y(n4765) );
INVX8TS U6716 ( .A(n4766), .Y(n5280) );
INVX2TS U6717 ( .A(n4898), .Y(n4787) );
INVX2TS U6718 ( .A(n4767), .Y(n4900) );
NAND2X1TS U6719 ( .A(n4787), .B(n4900), .Y(n4770) );
INVX2TS U6720 ( .A(n4899), .Y(n4768) );
AOI21X1TS U6721 ( .A0(n4790), .A1(n4900), .B0(n4768), .Y(n4769) );
OAI21X2TS U6722 ( .A0(n5280), .A1(n4770), .B0(n4769), .Y(n4775) );
INVX2TS U6723 ( .A(n4771), .Y(n4773) );
NAND2X1TS U6724 ( .A(n4773), .B(n4772), .Y(n4774) );
INVX2TS U6725 ( .A(n4789), .Y(n4776) );
NOR2X2TS U6726 ( .A(n4776), .B(n4793), .Y(n4779) );
NAND2X1TS U6727 ( .A(n4779), .B(n4787), .Y(n4781) );
INVX2TS U6728 ( .A(n4788), .Y(n4777) );
INVX2TS U6729 ( .A(n4782), .Y(n4784) );
NAND2X1TS U6730 ( .A(n4784), .B(n4783), .Y(n4785) );
NAND2X1TS U6731 ( .A(n4787), .B(n4789), .Y(n4792) );
AOI21X1TS U6732 ( .A0(n4790), .A1(n4789), .B0(n4788), .Y(n4791) );
OAI21X2TS U6733 ( .A0(n5280), .A1(n4792), .B0(n4791), .Y(n4797) );
INVX2TS U6734 ( .A(n4793), .Y(n4795) );
NAND2X1TS U6735 ( .A(n4795), .B(n4794), .Y(n4796) );
BUFX4TS U6736 ( .A(n4803), .Y(n7072) );
OAI21X1TS U6737 ( .A0(n6824), .A1(n7074), .B0(n4801), .Y(n4802) );
CLKXOR2X2TS U6738 ( .A(n4802), .B(n7076), .Y(n4815) );
BUFX8TS U6739 ( .A(n4803), .Y(n6736) );
OAI21X2TS U6740 ( .A0(n5043), .A1(n7074), .B0(n994), .Y(n4804) );
OAI21X2TS U6741 ( .A0(n6442), .A1(n764), .B0(n4806), .Y(n4807) );
AOI222X1TS U6742 ( .A0(n7072), .A1(n7022), .B0(n7070), .B1(n905), .C0(n6473),
.C1(n7018), .Y(n4808) );
OAI21X2TS U6743 ( .A0(n7026), .A1(n7074), .B0(n4808), .Y(n4809) );
ADDHX1TS U6744 ( .A(n4811), .B(n4810), .CO(n6939), .S(n4819) );
AOI222X1TS U6745 ( .A0(n7072), .A1(n7044), .B0(n7070), .B1(n6886), .C0(n6473), .C1(n6897), .Y(n4812) );
OAI21X1TS U6746 ( .A0(n6900), .A1(n6763), .B0(n4812), .Y(n4813) );
XOR2X1TS U6747 ( .A(n4813), .B(n836), .Y(n4818) );
ADDFHX2TS U6748 ( .A(n4816), .B(n4815), .CI(n4814), .CO(n4817), .S(
mult_x_24_n939) );
ADDFHX2TS U6749 ( .A(n4819), .B(n4818), .CI(n4817), .CO(mult_x_24_n925), .S(
mult_x_24_n926) );
NAND2X4TS U6750 ( .A(n4821), .B(n4824), .Y(n7305) );
NAND2X2TS U6751 ( .A(n7323), .B(n4828), .Y(n4830) );
INVX2TS U6752 ( .A(n4822), .Y(n7293) );
AOI21X4TS U6753 ( .A0(n4825), .A1(n4824), .B0(n4823), .Y(n7306) );
XOR2X4TS U6754 ( .A(n4833), .B(n1004), .Y(Sgf_operation_ODD1_middle_N53) );
NAND2X1TS U6755 ( .A(n5221), .B(n4862), .Y(n4836) );
INVX8TS U6756 ( .A(n5249), .Y(n5225) );
AOI21X1TS U6757 ( .A0(n5225), .A1(n4862), .B0(n4864), .Y(n4835) );
OAI21X2TS U6758 ( .A0(n6092), .A1(n4836), .B0(n4835), .Y(n4839) );
NAND2X1TS U6759 ( .A(n4837), .B(n4886), .Y(n4838) );
XNOR2X4TS U6760 ( .A(n4839), .B(n4838), .Y(Sgf_operation_ODD1_right_N38) );
NOR2X1TS U6761 ( .A(n4840), .B(n5220), .Y(n4842) );
NAND2X1TS U6762 ( .A(n5221), .B(n4842), .Y(n4844) );
AOI21X1TS U6763 ( .A0(n5225), .A1(n4842), .B0(n4841), .Y(n4843) );
OAI21X2TS U6764 ( .A0(n6092), .A1(n4844), .B0(n4843), .Y(n4848) );
NAND2X1TS U6765 ( .A(n4846), .B(n4845), .Y(n4847) );
XNOR2X4TS U6766 ( .A(n4848), .B(n4847), .Y(Sgf_operation_ODD1_right_N37) );
NAND2X1TS U6767 ( .A(n5221), .B(n788), .Y(n4851) );
AOI21X1TS U6768 ( .A0(n5225), .A1(n788), .B0(n4849), .Y(n4850) );
OAI21X2TS U6769 ( .A0(n6092), .A1(n4851), .B0(n4850), .Y(n4854) );
NAND2X1TS U6770 ( .A(n768), .B(n4852), .Y(n4853) );
XNOR2X4TS U6771 ( .A(n4854), .B(n4853), .Y(Sgf_operation_ODD1_right_N35) );
INVX2TS U6772 ( .A(n4857), .Y(n4859) );
NAND2X1TS U6773 ( .A(n4859), .B(n4858), .Y(n4860) );
INVX2TS U6774 ( .A(n4877), .Y(n4863) );
INVX4TS U6775 ( .A(n4864), .Y(n4888) );
INVX2TS U6776 ( .A(n4876), .Y(n4866) );
AOI21X2TS U6777 ( .A0(n4870), .A1(n5225), .B0(n4869), .Y(n4871) );
OAI21X2TS U6778 ( .A0(n6092), .A1(n4872), .B0(n4871), .Y(n4875) );
NAND2X1TS U6779 ( .A(n4873), .B(n1027), .Y(n4874) );
XNOR2X4TS U6780 ( .A(n4875), .B(n4874), .Y(Sgf_operation_ODD1_right_N41) );
NAND2X1TS U6781 ( .A(n1028), .B(n4882), .Y(n4883) );
NOR2X1TS U6782 ( .A(n4885), .B(n4887), .Y(n4890) );
NAND2X2TS U6783 ( .A(n4890), .B(n5221), .Y(n4892) );
OAI21X1TS U6784 ( .A0(n4888), .A1(n4887), .B0(n4886), .Y(n4889) );
NAND2X1TS U6785 ( .A(n784), .B(n4894), .Y(n4895) );
OAI21X1TS U6786 ( .A0(n5280), .A1(n4898), .B0(n4897), .Y(n4902) );
NAND2X1TS U6787 ( .A(n4900), .B(n4899), .Y(n4901) );
XNOR2X2TS U6788 ( .A(n4902), .B(n4901), .Y(Sgf_operation_ODD1_left_N31) );
OAI21X1TS U6789 ( .A0(n5280), .A1(n5285), .B0(n5286), .Y(n4907) );
INVX2TS U6790 ( .A(n4903), .Y(n4905) );
NAND2X1TS U6791 ( .A(n4905), .B(n4904), .Y(n4906) );
XNOR2X2TS U6792 ( .A(n4907), .B(n4906), .Y(Sgf_operation_ODD1_left_N28) );
INVX2TS U6793 ( .A(n4908), .Y(n5282) );
NAND2X1TS U6794 ( .A(n5276), .B(n5282), .Y(n4911) );
INVX2TS U6795 ( .A(n5281), .Y(n4909) );
AOI21X1TS U6796 ( .A0(n5277), .A1(n5282), .B0(n4909), .Y(n4910) );
OAI21X1TS U6797 ( .A0(n5280), .A1(n4911), .B0(n4910), .Y(n4916) );
INVX2TS U6798 ( .A(n4912), .Y(n4914) );
NAND2X1TS U6799 ( .A(n4914), .B(n4913), .Y(n4915) );
XNOR2X2TS U6800 ( .A(n4916), .B(n4915), .Y(Sgf_operation_ODD1_left_N30) );
INVX2TS U6801 ( .A(n4917), .Y(n5152) );
INVX2TS U6802 ( .A(n4918), .Y(n5155) );
OAI21X2TS U6803 ( .A0(n924), .A1(n5152), .B0(n5155), .Y(n4920) );
INVX2TS U6804 ( .A(n5154), .Y(n4919) );
INVX2TS U6805 ( .A(n4921), .Y(n4925) );
INVX2TS U6806 ( .A(n4922), .Y(n4963) );
INVX2TS U6807 ( .A(n4923), .Y(n4924) );
OAI21X4TS U6808 ( .A0(n5164), .A1(n4925), .B0(n4924), .Y(n4959) );
INVX2TS U6809 ( .A(n4962), .Y(n4926) );
OAI21X2TS U6810 ( .A0(n5271), .A1(n4928), .B0(n4927), .Y(n4932) );
INVX2TS U6811 ( .A(n4929), .Y(n4931) );
XOR2X4TS U6812 ( .A(n4932), .B(n980), .Y(Sgf_operation_ODD1_left_N50) );
INVX2TS U6813 ( .A(n4949), .Y(n4933) );
NOR2X2TS U6814 ( .A(n4933), .B(n4935), .Y(n4938) );
INVX2TS U6815 ( .A(n5163), .Y(n4945) );
NAND2X2TS U6816 ( .A(n4938), .B(n4945), .Y(n4940) );
NOR2X2TS U6817 ( .A(n5161), .B(n4940), .Y(n5256) );
INVX2TS U6818 ( .A(n5256), .Y(n4942) );
INVX2TS U6819 ( .A(n4948), .Y(n4936) );
OAI21X4TS U6820 ( .A0(n5164), .A1(n4940), .B0(n4939), .Y(n5259) );
INVX2TS U6821 ( .A(n5259), .Y(n4941) );
OAI21X2TS U6822 ( .A0(n924), .A1(n4942), .B0(n4941), .Y(n4944) );
NAND2X2TS U6823 ( .A(n4945), .B(n4949), .Y(n4947) );
NOR2X2TS U6824 ( .A(n5161), .B(n4947), .Y(n5265) );
INVX2TS U6825 ( .A(n5265), .Y(n4955) );
INVX2TS U6826 ( .A(n4946), .Y(n4953) );
INVX2TS U6827 ( .A(n4947), .Y(n4952) );
AOI21X1TS U6828 ( .A0(n4950), .A1(n4949), .B0(n4948), .Y(n4951) );
OAI2BB1X4TS U6829 ( .A0N(n4953), .A1N(n4952), .B0(n4951), .Y(n5268) );
INVX2TS U6830 ( .A(n5268), .Y(n4954) );
OAI21X2TS U6831 ( .A0(n5271), .A1(n4955), .B0(n4954), .Y(n4957) );
XOR2X4TS U6832 ( .A(n4957), .B(n1033), .Y(Sgf_operation_ODD1_left_N45) );
INVX2TS U6833 ( .A(n4958), .Y(n4961) );
INVX2TS U6834 ( .A(n4959), .Y(n4960) );
OAI21X2TS U6835 ( .A0(n5271), .A1(n4961), .B0(n4960), .Y(n4964) );
XOR2X4TS U6836 ( .A(n4964), .B(n967), .Y(Sgf_operation_ODD1_left_N49) );
AOI22X1TS U6837 ( .A0(n6065), .A1(n6054), .B0(n4967), .B1(n4966), .Y(n4968)
);
OAI21X2TS U6838 ( .A0(n6062), .A1(n4965), .B0(n4968), .Y(n4969) );
XOR2X2TS U6839 ( .A(n4969), .B(n6069), .Y(n5212) );
XOR2X2TS U6840 ( .A(n4971), .B(n6069), .Y(n5909) );
INVX2TS U6841 ( .A(n4972), .Y(n4973) );
OAI2BB1X4TS U6842 ( .A0N(n4975), .A1N(n4974), .B0(n4973), .Y(n4983) );
INVX2TS U6843 ( .A(n4976), .Y(n4982) );
XOR2X4TS U6844 ( .A(n4983), .B(n4977), .Y(n5957) );
AND2X2TS U6845 ( .A(n5899), .B(n850), .Y(n4978) );
AOI21X1TS U6846 ( .A0(n5902), .A1(n8385), .B0(n4978), .Y(n4979) );
INVX2TS U6847 ( .A(mult_x_23_n714), .Y(n5007) );
INVX2TS U6848 ( .A(n4980), .Y(n4981) );
INVX1TS U6849 ( .A(n4984), .Y(n4986) );
NAND2X1TS U6850 ( .A(n4986), .B(n4985), .Y(n4987) );
XNOR2X4TS U6851 ( .A(n4988), .B(n4987), .Y(n6008) );
AOI21X1TS U6852 ( .A0(n5902), .A1(n850), .B0(n4989), .Y(n4990) );
OAI21X1TS U6853 ( .A0(n6008), .A1(n5904), .B0(n4990), .Y(n5006) );
INVX2TS U6854 ( .A(n4991), .Y(n4992) );
INVX2TS U6855 ( .A(n4993), .Y(n4996) );
AOI21X4TS U6856 ( .A0(n4996), .A1(n4995), .B0(n4994), .Y(n4997) );
OAI21X4TS U6857 ( .A0(n4999), .A1(n4998), .B0(n4997), .Y(n5479) );
INVX2TS U6858 ( .A(n5000), .Y(n5478) );
NAND2X1TS U6859 ( .A(n5478), .B(n5476), .Y(n5001) );
XNOR2X4TS U6860 ( .A(n5479), .B(n5001), .Y(n5002) );
BUFX3TS U6861 ( .A(Op_MY[41]), .Y(n5790) );
BUFX3TS U6862 ( .A(Op_MY[40]), .Y(n6032) );
AOI222X1TS U6863 ( .A0(n6065), .A1(n5790), .B0(n6064), .B1(n6032), .C0(n6017), .C1(n828), .Y(n5003) );
OAI21X1TS U6864 ( .A0(n5792), .A1(n5470), .B0(n5003), .Y(n5004) );
XOR2X1TS U6865 ( .A(n5004), .B(n6069), .Y(n5005) );
ADDFHX2TS U6866 ( .A(n5007), .B(n5006), .CI(n5005), .CO(mult_x_23_n712), .S(
mult_x_23_n713) );
XNOR2X4TS U6867 ( .A(Op_MY[9]), .B(n7040), .Y(n5035) );
NAND2BX4TS U6868 ( .AN(n5035), .B(n5036), .Y(n5045) );
XNOR2X2TS U6869 ( .A(Op_MY[9]), .B(Op_MY[10]), .Y(n5034) );
NOR2BX4TS U6870 ( .AN(n5035), .B(n5034), .Y(n6589) );
NOR2X4TS U6871 ( .A(n5036), .B(n5035), .Y(n6608) );
BUFX12TS U6872 ( .A(n6608), .Y(n6848) );
AOI22X1TS U6873 ( .A0(n6589), .A1(n5041), .B0(n6848), .B1(n905), .Y(n5008)
);
XOR2X2TS U6874 ( .A(n5009), .B(n7051), .Y(n5033) );
NAND2X2TS U6875 ( .A(n6848), .B(n5041), .Y(n5010) );
INVX2TS U6876 ( .A(n5012), .Y(n5015) );
INVX2TS U6877 ( .A(n5013), .Y(n5014) );
OAI21X2TS U6878 ( .A0(n815), .A1(n5015), .B0(n5014), .Y(n5019) );
NAND2X1TS U6879 ( .A(n5017), .B(n5016), .Y(n5018) );
XNOR2X4TS U6880 ( .A(n5019), .B(n5018), .Y(Sgf_operation_ODD1_right_N47) );
INVX2TS U6881 ( .A(n5112), .Y(n5021) );
INVX2TS U6882 ( .A(n5121), .Y(n5020) );
OAI21X2TS U6883 ( .A0(n815), .A1(n5021), .B0(n5020), .Y(n5025) );
NAND2X1TS U6884 ( .A(n5023), .B(n5022), .Y(n5024) );
XNOR2X4TS U6885 ( .A(n5025), .B(n5024), .Y(Sgf_operation_ODD1_right_N49) );
OAI21X2TS U6886 ( .A0(n815), .A1(n5027), .B0(n5026), .Y(n5031) );
NAND2X1TS U6887 ( .A(n5029), .B(n5028), .Y(n5030) );
XNOR2X4TS U6888 ( .A(n5031), .B(n5030), .Y(Sgf_operation_ODD1_right_N46) );
BUFX4TS U6889 ( .A(n6608), .Y(n6839) );
XOR2X1TS U6890 ( .A(n5038), .B(n7051), .Y(n5051) );
XNOR2X4TS U6891 ( .A(Op_MY[12]), .B(Op_MY[11]), .Y(n5083) );
XOR2X4TS U6892 ( .A(Op_MY[13]), .B(n7490), .Y(n5084) );
NAND2BX4TS U6893 ( .AN(n5083), .B(n5084), .Y(n5081) );
NOR2X4TS U6894 ( .A(n5084), .B(n5083), .Y(n6544) );
BUFX8TS U6895 ( .A(n6544), .Y(n6771) );
NAND2X2TS U6896 ( .A(n6771), .B(n5041), .Y(n5039) );
XNOR2X2TS U6897 ( .A(Op_MY[12]), .B(Op_MY[13]), .Y(n5082) );
OAI21X1TS U6898 ( .A0(n5043), .A1(n7025), .B0(n5042), .Y(n5044) );
OAI21X1TS U6899 ( .A0(n6900), .A1(n7049), .B0(n5046), .Y(n5047) );
XOR2X1TS U6900 ( .A(n5047), .B(n7051), .Y(n5054) );
ADDHX1TS U6901 ( .A(n7490), .B(n5048), .CO(n7017), .S(n6988) );
AOI222X1TS U6902 ( .A0(n6839), .A1(n7042), .B0(n7045), .B1(n7022), .C0(n6615), .C1(n6822), .Y(n5049) );
OAI21X1TS U6903 ( .A0(n6824), .A1(n6841), .B0(n5049), .Y(n5050) );
XOR2X1TS U6904 ( .A(n5050), .B(n7051), .Y(n6987) );
NAND2X1TS U6905 ( .A(Sgf_operation_ODD1_Q_left[36]), .B(
Sgf_operation_ODD1_Q_left[37]), .Y(n5056) );
NAND2X1TS U6906 ( .A(Sgf_operation_ODD1_Q_left[38]), .B(
Sgf_operation_ODD1_Q_left[39]), .Y(n5060) );
NAND2X2TS U6907 ( .A(n5061), .B(n5063), .Y(n7591) );
NOR2X4TS U6908 ( .A(n7591), .B(n7592), .Y(n7578) );
NAND2X2TS U6909 ( .A(n5064), .B(n5063), .Y(n7590) );
NAND2X2TS U6910 ( .A(n7579), .B(Sgf_operation_ODD1_Q_left[45]), .Y(n5065) );
OAI21X4TS U6911 ( .A0(n5067), .A1(n5066), .B0(n5065), .Y(n5068) );
AOI21X4TS U6912 ( .A0(n7770), .A1(n5069), .B0(n5068), .Y(n7570) );
NAND2X4TS U6913 ( .A(n7561), .B(Sgf_operation_ODD1_Q_left[47]), .Y(n7554) );
NOR2X8TS U6914 ( .A(n7554), .B(n7553), .Y(n7542) );
XNOR2X4TS U6915 ( .A(n5071), .B(n5070), .Y(n5072) );
ADDHX1TS U6916 ( .A(n5074), .B(n5073), .CO(n5080), .S(n4726) );
AOI222X1TS U6917 ( .A0(n6870), .A1(n6884), .B0(n6834), .B1(n7020), .C0(n6867), .C1(n7018), .Y(n5077) );
XOR2X1TS U6918 ( .A(n5078), .B(n6794), .Y(n5079) );
CMPR22X2TS U6919 ( .A(n5080), .B(n5079), .CO(mult_x_24_n983), .S(n5092) );
BUFX3TS U6920 ( .A(n6544), .Y(n6877) );
BUFX3TS U6921 ( .A(n8413), .Y(n6910) );
AND3X6TS U6922 ( .A(n5084), .B(n5083), .C(n5082), .Y(n6982) );
AOI222X1TS U6923 ( .A0(n6877), .A1(n6910), .B0(n6876), .B1(n6780), .C0(n6581), .C1(n8414), .Y(n5085) );
OAI21X1TS U6924 ( .A0(n7039), .A1(n6899), .B0(n5085), .Y(n5086) );
XOR2X1TS U6925 ( .A(n5086), .B(n7490), .Y(n5091) );
BUFX3TS U6926 ( .A(n5087), .Y(n6807) );
AOI222X1TS U6927 ( .A0(n6807), .A1(n7046), .B0(n6786), .B1(n7044), .C0(n6805), .C1(n6584), .Y(n5088) );
OAI21X1TS U6928 ( .A0(n7050), .A1(n6809), .B0(n5088), .Y(n5089) );
XOR2X1TS U6929 ( .A(n5089), .B(n893), .Y(n5090) );
ADDFHX2TS U6930 ( .A(n5092), .B(n5091), .CI(n5090), .CO(mult_x_24_n981), .S(
mult_x_24_n982) );
BUFX4TS U6931 ( .A(n5095), .Y(n5831) );
AOI222X1TS U6932 ( .A0(n5831), .A1(n5843), .B0(n5830), .B1(n5839), .C0(n5997), .C1(n5213), .Y(n5097) );
OAI21X1TS U6933 ( .A0(n5437), .A1(n5827), .B0(n5097), .Y(n5098) );
XOR2X1TS U6934 ( .A(n5098), .B(n6002), .Y(n5101) );
AOI222X1TS U6935 ( .A0(n5976), .A1(n831), .B0(n5698), .B1(n5858), .C0(n5928),
.C1(n5892), .Y(n5099) );
OAI21X1TS U6936 ( .A0(n979), .A1(n5978), .B0(n5099), .Y(n5100) );
XOR2X1TS U6937 ( .A(n5100), .B(n7492), .Y(n5107) );
CMPR22X2TS U6938 ( .A(n5102), .B(n5101), .CO(mult_x_23_n925), .S(n5106) );
AOI222X1TS U6939 ( .A0(n5960), .A1(n5996), .B0(n5661), .B1(n8376), .C0(n5660), .C1(n851), .Y(n5103) );
XOR2X1TS U6940 ( .A(n5104), .B(n5663), .Y(n5105) );
NAND2X2TS U6941 ( .A(n5112), .B(n5120), .Y(n5142) );
CMPR32X2TS U6942 ( .A(n5125), .B(mult_x_24_n693), .C(n5113), .CO(n5123), .S(
n3833) );
NAND2X1TS U6943 ( .A(n6920), .B(n6989), .Y(n5114) );
XOR2X1TS U6944 ( .A(n5115), .B(n7087), .Y(n5124) );
OAI21X1TS U6945 ( .A0(n5118), .A1(n5117), .B0(n5116), .Y(n5119) );
NAND2X1TS U6946 ( .A(n5123), .B(n5122), .Y(n5144) );
OAI21X4TS U6947 ( .A0(n816), .A1(n1026), .B0(n1025), .Y(n5134) );
CMPR32X2TS U6948 ( .A(n5126), .B(n5125), .C(n5124), .CO(n5130), .S(n5122) );
CLKAND2X2TS U6949 ( .A(n6963), .B(Op_MY[26]), .Y(n5127) );
NAND2X1TS U6950 ( .A(n5130), .B(n5129), .Y(n5131) );
NAND2X1TS U6951 ( .A(n5132), .B(n5131), .Y(n5133) );
XNOR2X4TS U6952 ( .A(n5134), .B(n5133), .Y(Sgf_operation_ODD1_right_N53) );
ADDFHX2TS U6953 ( .A(n5137), .B(n5136), .CI(n5135), .CO(n4724), .S(
mult_x_24_n1002) );
ADDFHX2TS U6954 ( .A(n5140), .B(n5139), .CI(n5138), .CO(n4689), .S(
mult_x_23_n893) );
INVX2TS U6955 ( .A(n5143), .Y(n5145) );
NAND2X1TS U6956 ( .A(n5145), .B(n5144), .Y(n5146) );
NAND2X1TS U6957 ( .A(n5149), .B(n5148), .Y(n5150) );
XNOR2X4TS U6958 ( .A(n5151), .B(n5150), .Y(Sgf_operation_ODD1_left_N40) );
INVX2TS U6959 ( .A(n5194), .Y(n5157) );
INVX2TS U6960 ( .A(n5197), .Y(n5156) );
NAND2X1TS U6961 ( .A(n5158), .B(n5196), .Y(n5159) );
XNOR2X4TS U6962 ( .A(n5160), .B(n5159), .Y(Sgf_operation_ODD1_left_N38) );
NOR2X2TS U6963 ( .A(n5161), .B(n5163), .Y(n5170) );
INVX2TS U6964 ( .A(n5170), .Y(n5166) );
INVX2TS U6965 ( .A(n5174), .Y(n5165) );
INVX2TS U6966 ( .A(n5167), .Y(n5173) );
NAND2X1TS U6967 ( .A(n5173), .B(n5171), .Y(n5168) );
NAND2X1TS U6968 ( .A(n5170), .B(n5173), .Y(n5176) );
INVX2TS U6969 ( .A(n5171), .Y(n5172) );
INVX2TS U6970 ( .A(n5177), .Y(n5179) );
NAND2X1TS U6971 ( .A(n5179), .B(n5178), .Y(n5180) );
XNOR2X4TS U6972 ( .A(n5181), .B(n5180), .Y(Sgf_operation_ODD1_left_N44) );
NAND2X1TS U6973 ( .A(n5182), .B(n5185), .Y(n5188) );
INVX2TS U6974 ( .A(n5183), .Y(n5184) );
INVX2TS U6975 ( .A(n5189), .Y(n5191) );
NAND2X1TS U6976 ( .A(n5191), .B(n5190), .Y(n5192) );
XNOR2X4TS U6977 ( .A(n5193), .B(n5192), .Y(Sgf_operation_ODD1_left_N42) );
NAND2X1TS U6978 ( .A(n5194), .B(n5196), .Y(n5199) );
NAND2X1TS U6979 ( .A(n3773), .B(n5200), .Y(n5201) );
XNOR2X4TS U6980 ( .A(n5202), .B(n5201), .Y(Sgf_operation_ODD1_left_N39) );
CMPR22X2TS U6981 ( .A(n5204), .B(n5203), .CO(mult_x_23_n874), .S(n4669) );
AOI21X1TS U6982 ( .A0(n5902), .A1(n828), .B0(n5205), .Y(n5206) );
OAI21X4TS U6983 ( .A0(n5792), .A1(n6061), .B0(n5206), .Y(mult_x_23_n679) );
CMPR22X2TS U6984 ( .A(n5210), .B(n5209), .CO(n4814), .S(mult_x_24_n952) );
AOI222X1TS U6985 ( .A0(n881), .A1(n5843), .B0(n6064), .B1(n5839), .C0(n6063),
.C1(n5213), .Y(n5214) );
INVX2TS U6986 ( .A(n5237), .Y(n5216) );
INVX2TS U6987 ( .A(n5241), .Y(n5215) );
OAI21X1TS U6988 ( .A0(n6092), .A1(n5216), .B0(n5215), .Y(n5219) );
INVX2TS U6989 ( .A(n5217), .Y(n5240) );
NAND2X1TS U6990 ( .A(n5240), .B(n5238), .Y(n5218) );
INVX2TS U6991 ( .A(n5220), .Y(n5224) );
NAND2X1TS U6992 ( .A(n5221), .B(n5224), .Y(n5227) );
INVX2TS U6993 ( .A(n5222), .Y(n5223) );
AOI21X2TS U6994 ( .A0(n5225), .A1(n5224), .B0(n5223), .Y(n5226) );
NAND2X1TS U6995 ( .A(n5229), .B(n5228), .Y(n5230) );
INVX2TS U6996 ( .A(n5232), .Y(n5234) );
NAND2X1TS U6997 ( .A(n5234), .B(n5233), .Y(n5235) );
NAND2X1TS U6998 ( .A(n5237), .B(n5240), .Y(n5243) );
INVX2TS U6999 ( .A(n5238), .Y(n5239) );
AOI21X1TS U7000 ( .A0(n5241), .A1(n5240), .B0(n5239), .Y(n5242) );
INVX2TS U7001 ( .A(n5244), .Y(n5246) );
NAND2X1TS U7002 ( .A(n5246), .B(n5245), .Y(n5247) );
NAND2X1TS U7003 ( .A(n788), .B(n5251), .Y(n5252) );
NAND2X1TS U7004 ( .A(n1012), .B(n5262), .Y(n5263) );
XNOR2X4TS U7005 ( .A(n5264), .B(n5263), .Y(Sgf_operation_ODD1_left_N48) );
NAND2X1TS U7006 ( .A(n5265), .B(n5267), .Y(n5270) );
NAND2X1TS U7007 ( .A(n5273), .B(n5272), .Y(n5274) );
XNOR2X4TS U7008 ( .A(n5275), .B(n5274), .Y(Sgf_operation_ODD1_left_N46) );
INVX2TS U7009 ( .A(n5276), .Y(n5279) );
INVX2TS U7010 ( .A(n5277), .Y(n5278) );
OAI21X2TS U7011 ( .A0(n5280), .A1(n5279), .B0(n5278), .Y(n5284) );
NAND2X1TS U7012 ( .A(n5282), .B(n5281), .Y(n5283) );
XNOR2X1TS U7013 ( .A(n5284), .B(n5283), .Y(Sgf_operation_ODD1_left_N29) );
NAND2X1TS U7014 ( .A(n5287), .B(n5286), .Y(n5288) );
XOR2X1TS U7015 ( .A(n5280), .B(n5288), .Y(Sgf_operation_ODD1_left_N27) );
INVX4TS U7016 ( .A(n5289), .Y(n5315) );
INVX2TS U7017 ( .A(n5299), .Y(n5290) );
NOR2X1TS U7018 ( .A(n5290), .B(n5300), .Y(n5292) );
INVX2TS U7019 ( .A(n5293), .Y(n5295) );
NAND2X1TS U7020 ( .A(n5295), .B(n5294), .Y(n5296) );
AOI21X1TS U7021 ( .A0(n5315), .A1(n5299), .B0(n5298), .Y(n5304) );
INVX2TS U7022 ( .A(n5300), .Y(n5302) );
NAND2X1TS U7023 ( .A(n5302), .B(n5301), .Y(n5303) );
XOR2X1TS U7024 ( .A(n5304), .B(n5303), .Y(Sgf_operation_ODD1_left_N25) );
INVX2TS U7025 ( .A(n5305), .Y(n5313) );
INVX2TS U7026 ( .A(n5312), .Y(n5306) );
AOI21X1TS U7027 ( .A0(n5315), .A1(n5313), .B0(n5306), .Y(n5311) );
INVX2TS U7028 ( .A(n5307), .Y(n5309) );
NAND2X1TS U7029 ( .A(n5309), .B(n5308), .Y(n5310) );
XOR2X1TS U7030 ( .A(n5311), .B(n5310), .Y(Sgf_operation_ODD1_left_N24) );
NAND2X1TS U7031 ( .A(n5313), .B(n5312), .Y(n5314) );
XNOR2X1TS U7032 ( .A(n5315), .B(n5314), .Y(Sgf_operation_ODD1_left_N23) );
OAI21X1TS U7033 ( .A0(n5331), .A1(n5318), .B0(n5317), .Y(n5323) );
INVX2TS U7034 ( .A(n5319), .Y(n5321) );
NAND2X1TS U7035 ( .A(n5321), .B(n5320), .Y(n5322) );
XNOR2X1TS U7036 ( .A(n5323), .B(n5322), .Y(Sgf_operation_ODD1_left_N22) );
NAND2X1TS U7037 ( .A(n1008), .B(n5325), .Y(n5326) );
XNOR2X1TS U7038 ( .A(n5327), .B(n5326), .Y(Sgf_operation_ODD1_left_N21) );
NAND2X1TS U7039 ( .A(n5329), .B(n5328), .Y(n5330) );
INVX2TS U7040 ( .A(n5333), .Y(n5341) );
INVX2TS U7041 ( .A(n5340), .Y(n5334) );
INVX2TS U7042 ( .A(n5335), .Y(n5337) );
NAND2X1TS U7043 ( .A(n5337), .B(n5336), .Y(n5338) );
NAND2X1TS U7044 ( .A(n5341), .B(n5340), .Y(n5342) );
XNOR2X1TS U7045 ( .A(n5989), .B(n5342), .Y(Sgf_operation_ODD1_left_N17) );
INVX2TS U7046 ( .A(n5343), .Y(n5950) );
INVX2TS U7047 ( .A(n5344), .Y(n5346) );
NAND2X1TS U7048 ( .A(n5346), .B(n5345), .Y(n5347) );
XNOR2X1TS U7049 ( .A(n5348), .B(n5347), .Y(Sgf_operation_ODD1_left_N16) );
INVX2TS U7050 ( .A(n5349), .Y(n5357) );
AOI21X1TS U7051 ( .A0(n5357), .A1(n780), .B0(n5350), .Y(n5354) );
NAND2X1TS U7052 ( .A(n5352), .B(n5351), .Y(n5353) );
NAND2X1TS U7053 ( .A(n780), .B(n5355), .Y(n5356) );
XNOR2X1TS U7054 ( .A(n5357), .B(n5356), .Y(Sgf_operation_ODD1_left_N13) );
INVX2TS U7055 ( .A(n5358), .Y(n5955) );
INVX2TS U7056 ( .A(n5359), .Y(n5361) );
NAND2X1TS U7057 ( .A(n5361), .B(n5360), .Y(n5362) );
XNOR2X1TS U7058 ( .A(n5363), .B(n5362), .Y(Sgf_operation_ODD1_left_N12) );
INVX2TS U7059 ( .A(n5364), .Y(n5373) );
AOI21X1TS U7060 ( .A0(n5373), .A1(n5371), .B0(n5365), .Y(n5369) );
NAND2X1TS U7061 ( .A(n5367), .B(n5366), .Y(n5368) );
NAND2X1TS U7062 ( .A(n5371), .B(n5370), .Y(n5372) );
XNOR2X1TS U7063 ( .A(n5373), .B(n5372), .Y(Sgf_operation_ODD1_left_N9) );
INVX2TS U7064 ( .A(n5374), .Y(n5383) );
INVX2TS U7065 ( .A(n5375), .Y(n5377) );
NAND2X1TS U7066 ( .A(n5377), .B(n5376), .Y(n5378) );
XNOR2X1TS U7067 ( .A(n5379), .B(n5378), .Y(Sgf_operation_ODD1_left_N6) );
INVX2TS U7068 ( .A(n5380), .Y(n5382) );
NAND2X1TS U7069 ( .A(n5382), .B(n5381), .Y(n5384) );
INVX2TS U7070 ( .A(n5385), .Y(n5387) );
NAND2X1TS U7071 ( .A(n5387), .B(n5386), .Y(n5388) );
NAND2X1TS U7072 ( .A(n786), .B(n5390), .Y(n5392) );
XNOR2X1TS U7073 ( .A(n5392), .B(n5391), .Y(Sgf_operation_ODD1_left_N3) );
XOR2X1TS U7074 ( .A(n5394), .B(n5393), .Y(Sgf_operation_ODD1_left_N2) );
INVX2TS U7075 ( .A(n5395), .Y(n5397) );
XNOR2X1TS U7076 ( .A(n5397), .B(n5396), .Y(Sgf_operation_ODD1_left_N1) );
INVX2TS U7077 ( .A(n5398), .Y(n5401) );
INVX2TS U7078 ( .A(n5399), .Y(n5400) );
OAI21X4TS U7079 ( .A0(n5454), .A1(n5401), .B0(n5400), .Y(n5534) );
INVX2TS U7080 ( .A(n5402), .Y(n5533) );
NAND2X1TS U7081 ( .A(n5533), .B(n5531), .Y(n5403) );
XOR2X4TS U7082 ( .A(n5534), .B(n5403), .Y(n5912) );
AOI21X1TS U7083 ( .A0(n5936), .A1(n6038), .B0(n5404), .Y(n5405) );
NAND2X1TS U7084 ( .A(n5407), .B(n5406), .Y(n5408) );
XNOR2X4TS U7085 ( .A(n5409), .B(n5408), .Y(n5410) );
INVX8TS U7086 ( .A(n5410), .Y(n5945) );
BUFX3TS U7087 ( .A(Op_MY[49]), .Y(n5918) );
BUFX3TS U7088 ( .A(Op_MY[48]), .Y(n5821) );
AOI222X1TS U7089 ( .A0(n882), .A1(n5918), .B0(n864), .B1(n5821), .C0(n5863),
.C1(n5942), .Y(n5411) );
XOR2X1TS U7090 ( .A(n5412), .B(Op_MX[50]), .Y(n5413) );
CMPR32X2TS U7091 ( .A(n1035), .B(n5834), .C(n5413), .CO(mult_x_23_n652), .S(
mult_x_23_n653) );
AND2X2TS U7092 ( .A(n5899), .B(n5892), .Y(n5414) );
AOI21X1TS U7093 ( .A0(n5902), .A1(n852), .B0(n5414), .Y(n5415) );
OAI21X1TS U7094 ( .A0(n6001), .A1(n5904), .B0(n5415), .Y(n5416) );
CMPR32X2TS U7095 ( .A(n767), .B(n1032), .C(n5416), .CO(mult_x_23_n754), .S(
mult_x_23_n755) );
AOI21X1TS U7096 ( .A0(n5902), .A1(n849), .B0(n5417), .Y(n5418) );
OAI21X1TS U7097 ( .A0(n5762), .A1(n6061), .B0(n5418), .Y(n5422) );
AOI222X1TS U7098 ( .A0(n881), .A1(n837), .B0(n864), .B1(n8385), .C0(n6063),
.C1(n5901), .Y(n5419) );
OAI21X1TS U7099 ( .A0(n5905), .A1(n6067), .B0(n5419), .Y(n5420) );
CMPR32X2TS U7100 ( .A(n7491), .B(n5422), .C(n5421), .CO(mult_x_23_n765), .S(
mult_x_23_n766) );
AOI21X1TS U7101 ( .A0(n5902), .A1(Op_MY[30]), .B0(n5423), .Y(n5424) );
OAI21X1TS U7102 ( .A0(n5931), .A1(n5904), .B0(n5424), .Y(n5428) );
AOI222X1TS U7103 ( .A0(n881), .A1(n831), .B0(n864), .B1(n5858), .C0(n6063),
.C1(n5892), .Y(n5425) );
OAI21X1TS U7104 ( .A0(n979), .A1(n6067), .B0(n5425), .Y(n5426) );
XOR2X1TS U7105 ( .A(n5426), .B(n6021), .Y(n5427) );
AOI21X1TS U7106 ( .A0(n5936), .A1(n855), .B0(n5429), .Y(n5430) );
OAI21X1TS U7107 ( .A0(n6068), .A1(n5904), .B0(n5430), .Y(n5434) );
BUFX3TS U7108 ( .A(Op_MY[37]), .Y(n6005) );
INVX2TS U7109 ( .A(n5493), .Y(n6029) );
AOI222X1TS U7110 ( .A0(n5845), .A1(n5802), .B0(n923), .B1(n837), .C0(n6029),
.C1(n831), .Y(n5431) );
XOR2X1TS U7111 ( .A(n5432), .B(n7493), .Y(n5433) );
CMPR32X2TS U7112 ( .A(n7491), .B(n5434), .C(n5433), .CO(mult_x_23_n787), .S(
mult_x_23_n788) );
AOI21X1TS U7113 ( .A0(n5936), .A1(n824), .B0(n5435), .Y(n5436) );
OAI21X1TS U7114 ( .A0(n5437), .A1(n6061), .B0(n5436), .Y(n5444) );
AOI222X1TS U7115 ( .A0(n5845), .A1(n831), .B0(n923), .B1(n5858), .C0(n5844),
.C1(n5856), .Y(n5438) );
XOR2X2TS U7116 ( .A(n5439), .B(n7493), .Y(n5443) );
AOI222X1TS U7117 ( .A0(n6065), .A1(n5758), .B0(n6064), .B1(n7510), .C0(n6063), .C1(n851), .Y(n5440) );
OAI21X1TS U7118 ( .A0(n5931), .A1(n6067), .B0(n5440), .Y(n5441) );
XOR2X1TS U7119 ( .A(n5441), .B(n6069), .Y(n5442) );
CMPR32X2TS U7120 ( .A(n5444), .B(n5443), .C(n5442), .CO(mult_x_23_n809), .S(
mult_x_23_n810) );
AOI21X1TS U7121 ( .A0(n5863), .A1(n5771), .B0(n5445), .Y(n5446) );
OAI21X1TS U7122 ( .A0(n5773), .A1(n5470), .B0(n5446), .Y(n5447) );
XOR2X1TS U7123 ( .A(n5447), .B(n3866), .Y(mult_x_23_n1262) );
INVX2TS U7124 ( .A(n1031), .Y(n5921) );
BUFX3TS U7125 ( .A(Op_MY[50]), .Y(n5920) );
AOI222X1TS U7126 ( .A0(n882), .A1(n5921), .B0(n865), .B1(n5920), .C0(n5863),
.C1(n5775), .Y(n5448) );
OAI21X1TS U7127 ( .A0(n5925), .A1(n5470), .B0(n5448), .Y(n5449) );
BUFX3TS U7128 ( .A(Op_MY[49]), .Y(n5778) );
AOI222X1TS U7129 ( .A0(n6019), .A1(n5779), .B0(n865), .B1(n5778), .C0(n5863),
.C1(n5939), .Y(n5450) );
XOR2X1TS U7130 ( .A(n5451), .B(n3866), .Y(mult_x_23_n1264) );
OAI21X4TS U7131 ( .A0(n5454), .A1(n5453), .B0(n5452), .Y(n5467) );
INVX2TS U7132 ( .A(n5455), .Y(n5465) );
INVX2TS U7133 ( .A(n5464), .Y(n5456) );
AOI21X4TS U7134 ( .A0(n5467), .A1(n5465), .B0(n5456), .Y(n5461) );
INVX2TS U7135 ( .A(n5457), .Y(n5459) );
NAND2X1TS U7136 ( .A(n5459), .B(n5458), .Y(n5460) );
XNOR2X4TS U7137 ( .A(n5461), .B(n5460), .Y(n5938) );
BUFX3TS U7138 ( .A(Op_MY[48]), .Y(n5871) );
BUFX3TS U7139 ( .A(Op_MY[47]), .Y(n5870) );
AOI222X1TS U7140 ( .A0(n882), .A1(n5871), .B0(n865), .B1(n5870), .C0(n5863),
.C1(n5935), .Y(n5462) );
OAI21X1TS U7141 ( .A0(n5938), .A1(n5470), .B0(n5462), .Y(n5463) );
XOR2X1TS U7142 ( .A(n5463), .B(Op_MX[50]), .Y(mult_x_23_n1266) );
NAND2X1TS U7143 ( .A(n5465), .B(n5464), .Y(n5466) );
XNOR2X4TS U7144 ( .A(n5467), .B(n5466), .Y(n5468) );
BUFX3TS U7145 ( .A(Op_MY[47]), .Y(n5849) );
BUFX3TS U7146 ( .A(Op_MY[46]), .Y(n5866) );
AOI222X1TS U7147 ( .A0(n882), .A1(n5849), .B0(n865), .B1(n5866), .C0(n5863),
.C1(n5906), .Y(n5469) );
OAI21X1TS U7148 ( .A0(n5896), .A1(n5470), .B0(n5469), .Y(n5471) );
XOR2X1TS U7149 ( .A(n5471), .B(n3866), .Y(mult_x_23_n1267) );
BUFX3TS U7150 ( .A(Op_MY[45]), .Y(n6040) );
BUFX3TS U7151 ( .A(Op_MY[44]), .Y(n6039) );
AOI222X1TS U7152 ( .A0(n6065), .A1(n6040), .B0(n864), .B1(n6039), .C0(n5863),
.C1(n6038), .Y(n5472) );
XOR2X1TS U7153 ( .A(n5473), .B(Op_MX[50]), .Y(mult_x_23_n1269) );
BUFX3TS U7154 ( .A(Op_MY[44]), .Y(n6024) );
AOI222X1TS U7155 ( .A0(n6019), .A1(n6024), .B0(n6064), .B1(n839), .C0(n5863),
.C1(n6023), .Y(n5474) );
XOR2X1TS U7156 ( .A(n5475), .B(Op_MX[50]), .Y(mult_x_23_n1270) );
INVX2TS U7157 ( .A(n5476), .Y(n5477) );
AOI21X4TS U7158 ( .A0(n5479), .A1(n5478), .B0(n5477), .Y(n5484) );
INVX2TS U7159 ( .A(n5480), .Y(n5482) );
NAND2X1TS U7160 ( .A(n5482), .B(n5481), .Y(n5483) );
XNOR2X4TS U7161 ( .A(n5484), .B(n5483), .Y(n5968) );
BUFX3TS U7162 ( .A(Op_MY[42]), .Y(n5966) );
BUFX3TS U7163 ( .A(Op_MY[41]), .Y(n5965) );
AOI222X1TS U7164 ( .A0(n882), .A1(n5966), .B0(n6064), .B1(n5965), .C0(n6063),
.C1(n5963), .Y(n5485) );
OAI21X1TS U7165 ( .A0(n5968), .A1(n4965), .B0(n5485), .Y(n5486) );
XOR2X1TS U7166 ( .A(n5486), .B(n6069), .Y(mult_x_23_n1272) );
BUFX3TS U7167 ( .A(Op_MY[37]), .Y(n5802) );
AOI222X1TS U7168 ( .A0(n882), .A1(n5802), .B0(n864), .B1(n837), .C0(n6017),
.C1(n8385), .Y(n5487) );
OAI21X1TS U7169 ( .A0(n5957), .A1(n6067), .B0(n5487), .Y(n5488) );
XOR2X1TS U7170 ( .A(n5488), .B(n6021), .Y(mult_x_23_n1277) );
AOI222X1TS U7171 ( .A0(n882), .A1(n5999), .B0(n864), .B1(n5998), .C0(n6063),
.C1(n5996), .Y(n5489) );
OAI21X1TS U7172 ( .A0(n6001), .A1(n6067), .B0(n5489), .Y(n5490) );
XOR2X1TS U7173 ( .A(n5490), .B(n6069), .Y(mult_x_23_n1280) );
BUFX3TS U7174 ( .A(n5491), .Y(n5886) );
XOR2X1TS U7175 ( .A(n5492), .B(n7493), .Y(mult_x_23_n1289) );
AOI21X1TS U7176 ( .A0(n5884), .A1(n5779), .B0(n5495), .Y(n5496) );
OAI21X1TS U7177 ( .A0(n5773), .A1(n5886), .B0(n5496), .Y(n5497) );
XOR2X1TS U7178 ( .A(n5497), .B(n5868), .Y(mult_x_23_n1291) );
AOI222X1TS U7179 ( .A0(n6033), .A1(n5921), .B0(n923), .B1(n5920), .C0(n5884),
.C1(n5918), .Y(n5498) );
OAI21X1TS U7180 ( .A0(n5925), .A1(n5886), .B0(n5498), .Y(n5499) );
XOR2X1TS U7181 ( .A(n5499), .B(n5868), .Y(mult_x_23_n1292) );
AOI222X1TS U7182 ( .A0(n6033), .A1(n5920), .B0(n5494), .B1(n5778), .C0(n5884), .C1(n5871), .Y(n5500) );
XOR2X1TS U7183 ( .A(n5501), .B(n5868), .Y(mult_x_23_n1293) );
AOI222X1TS U7184 ( .A0(n6033), .A1(n5778), .B0(n923), .B1(n5821), .C0(n5884),
.C1(n5849), .Y(n5502) );
OAI21X1TS U7185 ( .A0(n5945), .A1(n5886), .B0(n5502), .Y(n5503) );
BUFX3TS U7186 ( .A(Op_MY[46]), .Y(n6080) );
AOI222X1TS U7187 ( .A0(n6033), .A1(n5821), .B0(n6031), .B1(n5870), .C0(n5884), .C1(n6080), .Y(n5504) );
OAI21X1TS U7188 ( .A0(n5938), .A1(n5886), .B0(n5504), .Y(n5505) );
XOR2X1TS U7189 ( .A(n5505), .B(n5868), .Y(mult_x_23_n1295) );
AOI222X1TS U7190 ( .A0(n5845), .A1(n5942), .B0(n923), .B1(n5866), .C0(n5884),
.C1(n6040), .Y(n5506) );
XOR2X1TS U7191 ( .A(n5507), .B(n5868), .Y(mult_x_23_n1296) );
BUFX3TS U7192 ( .A(Op_MY[45]), .Y(n6078) );
AOI222X1TS U7193 ( .A0(n5840), .A1(n6078), .B0(n6031), .B1(n6039), .C0(n5884), .C1(n840), .Y(n5508) );
AOI222X1TS U7194 ( .A0(n6033), .A1(n6039), .B0(n5494), .B1(n839), .C0(n5884),
.C1(n5966), .Y(n5510) );
OAI21X1TS U7195 ( .A0(n6026), .A1(n5491), .B0(n5510), .Y(n5511) );
XOR2X1TS U7196 ( .A(n5511), .B(n5868), .Y(mult_x_23_n1299) );
BUFX3TS U7197 ( .A(Op_MY[42]), .Y(n6046) );
AOI222X1TS U7198 ( .A0(n5840), .A1(n839), .B0(n923), .B1(n6046), .C0(n5844),
.C1(n5790), .Y(n5512) );
OAI21X1TS U7199 ( .A0(n6048), .A1(n5491), .B0(n5512), .Y(n5513) );
XOR2X1TS U7200 ( .A(n5513), .B(n5868), .Y(mult_x_23_n1300) );
BUFX3TS U7201 ( .A(Op_MY[40]), .Y(n6018) );
AOI222X1TS U7202 ( .A0(n6033), .A1(n6046), .B0(n6031), .B1(n5965), .C0(n5844), .C1(n6018), .Y(n5514) );
XOR2X1TS U7203 ( .A(n5515), .B(n5847), .Y(mult_x_23_n1301) );
AOI222X1TS U7204 ( .A0(n5840), .A1(n5965), .B0(n5494), .B1(n6032), .C0(n6029), .C1(n5796), .Y(n5516) );
XOR2X1TS U7205 ( .A(n5517), .B(n5847), .Y(mult_x_23_n1302) );
BUFX3TS U7206 ( .A(Op_MY[39]), .Y(n6030) );
AOI222X1TS U7207 ( .A0(n5845), .A1(n6030), .B0(n6031), .B1(n5982), .C0(n6029), .C1(n6005), .Y(n5518) );
XOR2X1TS U7208 ( .A(n5519), .B(n7493), .Y(mult_x_23_n1304) );
AOI222X1TS U7209 ( .A0(n5845), .A1(n5858), .B0(n923), .B1(n5998), .C0(n5844),
.C1(n852), .Y(n5520) );
OAI21X1TS U7210 ( .A0(n6001), .A1(n6035), .B0(n5520), .Y(n5521) );
XOR2X1TS U7211 ( .A(n5521), .B(n5847), .Y(mult_x_23_n1309) );
AOI222X1TS U7212 ( .A0(n5845), .A1(n5998), .B0(n923), .B1(n5758), .C0(n5844),
.C1(n7510), .Y(n5522) );
OAI21X1TS U7213 ( .A0(n5762), .A1(n6035), .B0(n5522), .Y(n5523) );
XOR2X1TS U7214 ( .A(n5523), .B(n5847), .Y(mult_x_23_n1310) );
AOI222X1TS U7215 ( .A0(n5840), .A1(n5996), .B0(n6031), .B1(n8376), .C0(n5844), .C1(n8375), .Y(n5524) );
XOR2X1TS U7216 ( .A(n5525), .B(n5847), .Y(mult_x_23_n1311) );
AOI21X1TS U7217 ( .A0(n5919), .A1(n5779), .B0(n5526), .Y(n5527) );
OAI21X1TS U7218 ( .A0(n5773), .A1(n5924), .B0(n5527), .Y(n5528) );
XOR2X1TS U7219 ( .A(n5528), .B(n5926), .Y(mult_x_23_n1320) );
AOI222X1TS U7220 ( .A0(n5922), .A1(n5779), .B0(n6011), .B1(n5778), .C0(n5919), .C1(n5871), .Y(n5529) );
XOR2X1TS U7221 ( .A(n5530), .B(n5926), .Y(mult_x_23_n1322) );
INVX2TS U7222 ( .A(n5531), .Y(n5532) );
AOI21X4TS U7223 ( .A0(n5534), .A1(n5533), .B0(n5532), .Y(n5539) );
NAND2X1TS U7224 ( .A(n5537), .B(n5536), .Y(n5538) );
XNOR2X4TS U7225 ( .A(n5539), .B(n5538), .Y(n6084) );
AOI222X1TS U7226 ( .A0(n6012), .A1(n6080), .B0(n5564), .B1(n6078), .C0(n5919), .C1(n6024), .Y(n5540) );
OAI21X1TS U7227 ( .A0(n6084), .A1(n4671), .B0(n5540), .Y(n5541) );
XOR2X1TS U7228 ( .A(n5541), .B(n5926), .Y(mult_x_23_n1326) );
AOI222X1TS U7229 ( .A0(n5922), .A1(n6024), .B0(n5564), .B1(n840), .C0(n5919),
.C1(n5966), .Y(n5542) );
XOR2X1TS U7230 ( .A(n5543), .B(n5926), .Y(mult_x_23_n1328) );
AOI222X1TS U7231 ( .A0(n6012), .A1(n840), .B0(n5564), .B1(n6046), .C0(n6010),
.C1(n5790), .Y(n5544) );
OAI21X1TS U7232 ( .A0(n6048), .A1(n4671), .B0(n5544), .Y(n5545) );
AOI222X1TS U7233 ( .A0(n6012), .A1(n5966), .B0(n5564), .B1(n5965), .C0(n5560), .C1(n6018), .Y(n5546) );
XOR2X1TS U7234 ( .A(n5547), .B(n5567), .Y(mult_x_23_n1330) );
AOI222X1TS U7235 ( .A0(n6012), .A1(n5790), .B0(n5564), .B1(n6032), .C0(n6010), .C1(n5796), .Y(n5548) );
OAI21X1TS U7236 ( .A0(n5792), .A1(n4671), .B0(n5548), .Y(n5549) );
XOR2X1TS U7237 ( .A(n5549), .B(n5567), .Y(mult_x_23_n1331) );
XOR2X1TS U7238 ( .A(n5551), .B(n737), .Y(mult_x_23_n1333) );
BUFX3TS U7239 ( .A(n5922), .Y(n5565) );
BUFX3TS U7240 ( .A(Op_MY[38]), .Y(n6028) );
AOI222X1TS U7241 ( .A0(n5565), .A1(n6028), .B0(n5561), .B1(n814), .C0(n6010),
.C1(n838), .Y(n5552) );
XOR2X1TS U7242 ( .A(n5553), .B(n737), .Y(mult_x_23_n1334) );
AOI222X1TS U7243 ( .A0(n5565), .A1(n5802), .B0(n5561), .B1(n837), .C0(n6010),
.C1(n832), .Y(n5554) );
AOI222X1TS U7244 ( .A0(n5565), .A1(n838), .B0(n5561), .B1(n8385), .C0(n5560),
.C1(n5999), .Y(n5556) );
XOR2X1TS U7245 ( .A(n5557), .B(n737), .Y(mult_x_23_n1336) );
AOI222X1TS U7246 ( .A0(n5565), .A1(n832), .B0(n5561), .B1(n5858), .C0(n6010),
.C1(n5856), .Y(n5558) );
XOR2X1TS U7247 ( .A(n5559), .B(n737), .Y(mult_x_23_n1337) );
AOI222X1TS U7248 ( .A0(n5565), .A1(n5999), .B0(n5561), .B1(n5998), .C0(n5560), .C1(n5996), .Y(n5562) );
OAI21X1TS U7249 ( .A0(n6001), .A1(n6014), .B0(n5562), .Y(n5563) );
XOR2X1TS U7250 ( .A(n5563), .B(n5567), .Y(mult_x_23_n1338) );
AOI222X1TS U7251 ( .A0(n5565), .A1(n5856), .B0(n5564), .B1(n5758), .C0(n6010), .C1(n849), .Y(n5566) );
OAI21X1TS U7252 ( .A0(n5762), .A1(n6014), .B0(n5566), .Y(n5568) );
XOR2X1TS U7253 ( .A(n5568), .B(n5567), .Y(mult_x_23_n1339) );
BUFX3TS U7254 ( .A(n5569), .Y(n5827) );
OAI21X1TS U7255 ( .A0(n5879), .A1(n5827), .B0(n5594), .Y(n5570) );
XOR2X1TS U7256 ( .A(n5570), .B(n7498), .Y(mult_x_23_n1347) );
INVX4TS U7257 ( .A(n5594), .Y(n5824) );
AOI21X1TS U7258 ( .A0(n5824), .A1(n5883), .B0(n867), .Y(n5571) );
AOI21X1TS U7259 ( .A0(n5824), .A1(n5779), .B0(n5573), .Y(n5574) );
XOR2X1TS U7260 ( .A(n5575), .B(n5828), .Y(mult_x_23_n1349) );
AOI222X1TS U7261 ( .A0(n5825), .A1(n5779), .B0(n868), .B1(n5778), .C0(n5824),
.C1(n5871), .Y(n5576) );
XOR2X1TS U7262 ( .A(n5577), .B(n5828), .Y(mult_x_23_n1351) );
AOI222X1TS U7263 ( .A0(n5825), .A1(n5918), .B0(n868), .B1(n5821), .C0(n5824),
.C1(n5849), .Y(n5578) );
OAI21X1TS U7264 ( .A0(n5945), .A1(n5827), .B0(n5578), .Y(n5579) );
XOR2X1TS U7265 ( .A(n5579), .B(n5828), .Y(mult_x_23_n1352) );
AOI222X1TS U7266 ( .A0(n5825), .A1(n5871), .B0(n868), .B1(n5870), .C0(n5824),
.C1(n6080), .Y(n5580) );
XOR2X1TS U7267 ( .A(n5581), .B(n5828), .Y(mult_x_23_n1353) );
AOI222X1TS U7268 ( .A0(n5825), .A1(n5849), .B0(n868), .B1(n5866), .C0(n5824),
.C1(n6040), .Y(n5582) );
OAI21X1TS U7269 ( .A0(n5896), .A1(n5827), .B0(n5582), .Y(n5583) );
XOR2X1TS U7270 ( .A(n5583), .B(n5828), .Y(mult_x_23_n1354) );
AOI222X1TS U7271 ( .A0(n5831), .A1(n6080), .B0(n5830), .B1(n6078), .C0(n5824), .C1(n6024), .Y(n5584) );
OAI21X1TS U7272 ( .A0(n6084), .A1(n5827), .B0(n5584), .Y(n5585) );
XOR2X1TS U7273 ( .A(n5585), .B(n5828), .Y(mult_x_23_n1355) );
AOI222X1TS U7274 ( .A0(n5831), .A1(n6040), .B0(n867), .B1(n6039), .C0(n5824),
.C1(n839), .Y(n5586) );
OAI21X1TS U7275 ( .A0(n5912), .A1(n5569), .B0(n5586), .Y(n5587) );
XOR2X1TS U7276 ( .A(n5587), .B(n5828), .Y(mult_x_23_n1356) );
AOI222X1TS U7277 ( .A0(n5825), .A1(n6024), .B0(n5830), .B1(n839), .C0(n5824),
.C1(n5966), .Y(n5588) );
OAI21X1TS U7278 ( .A0(n6026), .A1(n5569), .B0(n5588), .Y(n5589) );
XOR2X1TS U7279 ( .A(n5589), .B(n5828), .Y(mult_x_23_n1357) );
AOI222X1TS U7280 ( .A0(n5831), .A1(n840), .B0(n5830), .B1(n6046), .C0(n5997),
.C1(n5790), .Y(n5590) );
OAI21X1TS U7281 ( .A0(n6048), .A1(n5569), .B0(n5590), .Y(n5591) );
XOR2X1TS U7282 ( .A(n5591), .B(n5828), .Y(mult_x_23_n1358) );
AOI222X1TS U7283 ( .A0(n5831), .A1(n5966), .B0(n5830), .B1(n5965), .C0(n5997), .C1(n6018), .Y(n5592) );
INVX2TS U7284 ( .A(n5594), .Y(n6004) );
AOI222X1TS U7285 ( .A0(n5831), .A1(n5790), .B0(n5830), .B1(n6032), .C0(n6004), .C1(n5796), .Y(n5595) );
OAI21X1TS U7286 ( .A0(n5792), .A1(n5569), .B0(n5595), .Y(n5596) );
XOR2X1TS U7287 ( .A(n5596), .B(n6002), .Y(mult_x_23_n1360) );
INVX2TS U7288 ( .A(n5597), .Y(n5598) );
INVX2TS U7289 ( .A(n5601), .Y(n5603) );
XNOR2X4TS U7290 ( .A(n5605), .B(n5604), .Y(n6036) );
AOI222X1TS U7291 ( .A0(n5831), .A1(n6018), .B0(n868), .B1(n6030), .C0(n6004),
.C1(n6028), .Y(n5606) );
XOR2X1TS U7292 ( .A(n5607), .B(n7498), .Y(mult_x_23_n1361) );
AOI222X1TS U7293 ( .A0(n5825), .A1(n5796), .B0(n867), .B1(n5982), .C0(n6004),
.C1(n5802), .Y(n5608) );
OAI21X1TS U7294 ( .A0(n5876), .A1(n6007), .B0(n5608), .Y(n5609) );
XOR2X1TS U7295 ( .A(n5609), .B(n7498), .Y(mult_x_23_n1362) );
AOI222X1TS U7296 ( .A0(n5095), .A1(n814), .B0(n868), .B1(n837), .C0(n6004),
.C1(n832), .Y(n5610) );
XOR2X1TS U7297 ( .A(n5611), .B(n7498), .Y(mult_x_23_n1364) );
AOI222X1TS U7298 ( .A0(n5095), .A1(n838), .B0(n868), .B1(n831), .C0(n5997),
.C1(n5999), .Y(n5612) );
OAI21X1TS U7299 ( .A0(n5905), .A1(n6007), .B0(n5612), .Y(n5613) );
XOR2X1TS U7300 ( .A(n5613), .B(n7498), .Y(mult_x_23_n1365) );
AOI222X1TS U7301 ( .A0(n5095), .A1(n5856), .B0(n5830), .B1(n5758), .C0(n5997), .C1(n7510), .Y(n5614) );
OAI21X1TS U7302 ( .A0(n5762), .A1(n6007), .B0(n5614), .Y(n5615) );
XOR2X1TS U7303 ( .A(n5615), .B(n6002), .Y(mult_x_23_n1368) );
AOI222X1TS U7304 ( .A0(n5831), .A1(n5996), .B0(n5830), .B1(n8376), .C0(n5997), .C1(n8375), .Y(n5616) );
XOR2X1TS U7305 ( .A(n5617), .B(n6002), .Y(mult_x_23_n1369) );
AOI222X1TS U7306 ( .A0(n5831), .A1(n7510), .B0(n5830), .B1(n830), .C0(n5997),
.C1(n5843), .Y(n5618) );
OAI21X1TS U7307 ( .A0(n6068), .A1(n6007), .B0(n5618), .Y(n5619) );
XOR2X1TS U7308 ( .A(n5619), .B(n6002), .Y(mult_x_23_n1370) );
BUFX3TS U7309 ( .A(n5620), .Y(n5878) );
INVX4TS U7310 ( .A(n5877), .Y(n5640) );
AOI21X1TS U7311 ( .A0(n5640), .A1(n5883), .B0(n5959), .Y(n5621) );
OAI21X1TS U7312 ( .A0(n5887), .A1(n5878), .B0(n5621), .Y(n5622) );
XOR2X1TS U7313 ( .A(n5622), .B(Op_MX[38]), .Y(mult_x_23_n1377) );
AO21X1TS U7314 ( .A0(n5959), .A1(n5921), .B0(n5653), .Y(n5623) );
AOI21X1TS U7315 ( .A0(n5640), .A1(n5771), .B0(n5623), .Y(n5624) );
OAI21X1TS U7316 ( .A0(n5773), .A1(n5878), .B0(n5624), .Y(n5625) );
XOR2X1TS U7317 ( .A(n5625), .B(n5644), .Y(mult_x_23_n1378) );
AOI222X1TS U7318 ( .A0(n5653), .A1(n5921), .B0(n5959), .B1(n5920), .C0(n5640), .C1(n5775), .Y(n5626) );
AOI222X1TS U7319 ( .A0(n5653), .A1(n5920), .B0(n5959), .B1(n5778), .C0(n5640), .C1(n5939), .Y(n5628) );
OAI21X1TS U7320 ( .A0(n5781), .A1(n5878), .B0(n5628), .Y(n5629) );
XOR2X1TS U7321 ( .A(n5629), .B(n5644), .Y(mult_x_23_n1380) );
AOI222X1TS U7322 ( .A0(n5653), .A1(n5778), .B0(n5959), .B1(n5821), .C0(n5640), .C1(n5942), .Y(n5630) );
OAI21X1TS U7323 ( .A0(n5945), .A1(n5878), .B0(n5630), .Y(n5631) );
XOR2X1TS U7324 ( .A(n5631), .B(n5644), .Y(mult_x_23_n1381) );
AOI222X1TS U7325 ( .A0(n5653), .A1(n5821), .B0(n5959), .B1(n5870), .C0(n5640), .C1(n5935), .Y(n5632) );
OAI21X1TS U7326 ( .A0(n5938), .A1(n5878), .B0(n5632), .Y(n5633) );
XOR2X1TS U7327 ( .A(n5633), .B(n5644), .Y(mult_x_23_n1382) );
AOI222X1TS U7328 ( .A0(n5653), .A1(n5870), .B0(n5959), .B1(n5866), .C0(n5640), .C1(n5906), .Y(n5634) );
OAI21X1TS U7329 ( .A0(n5896), .A1(n5878), .B0(n5634), .Y(n5635) );
XOR2X1TS U7330 ( .A(n5635), .B(n5644), .Y(mult_x_23_n1383) );
AOI222X1TS U7331 ( .A0(n5960), .A1(n5866), .B0(n5661), .B1(n6078), .C0(n5640), .C1(n829), .Y(n5636) );
OAI21X1TS U7332 ( .A0(n6084), .A1(n5620), .B0(n5636), .Y(n5637) );
XOR2X1TS U7333 ( .A(n5637), .B(n5644), .Y(mult_x_23_n1384) );
AOI222X1TS U7334 ( .A0(n5960), .A1(n6078), .B0(n5959), .B1(n6039), .C0(n5640), .C1(n6038), .Y(n5638) );
XOR2X1TS U7335 ( .A(n5639), .B(n5644), .Y(mult_x_23_n1385) );
AOI222X1TS U7336 ( .A0(n5653), .A1(n6039), .B0(n5661), .B1(n840), .C0(n5640),
.C1(n6023), .Y(n5641) );
XOR2X1TS U7337 ( .A(n5642), .B(n5644), .Y(mult_x_23_n1386) );
AOI222X1TS U7338 ( .A0(n5960), .A1(n839), .B0(n5661), .B1(n6046), .C0(n5660),
.C1(n6045), .Y(n5643) );
AOI222X1TS U7339 ( .A0(n5960), .A1(n6046), .B0(n5661), .B1(n5965), .C0(n5660), .C1(n5963), .Y(n5646) );
XOR2X1TS U7340 ( .A(n5647), .B(n5663), .Y(mult_x_23_n1388) );
INVX2TS U7341 ( .A(n5877), .Y(n5980) );
AOI222X1TS U7342 ( .A0(n5960), .A1(n5965), .B0(n5661), .B1(n6032), .C0(n5980), .C1(n828), .Y(n5648) );
OAI21X1TS U7343 ( .A0(n5792), .A1(n5620), .B0(n5648), .Y(n5649) );
XOR2X1TS U7344 ( .A(n5649), .B(n5663), .Y(mult_x_23_n1389) );
AOI222X1TS U7345 ( .A0(n5653), .A1(n6030), .B0(n5981), .B1(n5982), .C0(n5980), .C1(n5802), .Y(n5651) );
XOR2X1TS U7346 ( .A(n5652), .B(n7500), .Y(mult_x_23_n1391) );
AOI222X1TS U7347 ( .A0(n5983), .A1(n850), .B0(n5981), .B1(n832), .C0(n5980),
.C1(n5901), .Y(n5654) );
XOR2X1TS U7348 ( .A(n5655), .B(n7500), .Y(mult_x_23_n1394) );
XOR2X1TS U7349 ( .A(n5657), .B(n7500), .Y(mult_x_23_n1395) );
OAI21X1TS U7350 ( .A0(n6001), .A1(n5985), .B0(n5658), .Y(n5659) );
XOR2X1TS U7351 ( .A(n5659), .B(n5663), .Y(mult_x_23_n1396) );
AOI222X1TS U7352 ( .A0(n5983), .A1(n5998), .B0(n5661), .B1(n5758), .C0(n5660), .C1(n849), .Y(n5662) );
XOR2X1TS U7353 ( .A(n5664), .B(n5663), .Y(mult_x_23_n1397) );
BUFX3TS U7354 ( .A(n5665), .Y(n5684) );
XOR2X1TS U7355 ( .A(n5666), .B(n7492), .Y(mult_x_23_n1405) );
INVX4TS U7356 ( .A(n5667), .Y(n5690) );
AOI21X1TS U7357 ( .A0(n5690), .A1(n5883), .B0(n5975), .Y(n5669) );
CLKINVX1TS U7358 ( .A(n793), .Y(n5670) );
XOR2X1TS U7359 ( .A(n5671), .B(n5670), .Y(mult_x_23_n1406) );
AOI21X1TS U7360 ( .A0(n5690), .A1(n5771), .B0(n5672), .Y(n5673) );
OAI21X1TS U7361 ( .A0(n5773), .A1(n5684), .B0(n5673), .Y(n5674) );
XOR2X1TS U7362 ( .A(n5674), .B(n5694), .Y(mult_x_23_n1407) );
AOI222X1TS U7363 ( .A0(n5701), .A1(n5921), .B0(n5698), .B1(n5920), .C0(n5690), .C1(n5775), .Y(n5675) );
OAI21X1TS U7364 ( .A0(n5925), .A1(n5684), .B0(n5675), .Y(n5676) );
XOR2X1TS U7365 ( .A(n5676), .B(n5694), .Y(mult_x_23_n1408) );
AOI222X1TS U7366 ( .A0(n5701), .A1(n5779), .B0(n5698), .B1(n5778), .C0(n5690), .C1(n5939), .Y(n5677) );
OAI21X1TS U7367 ( .A0(n5781), .A1(n5684), .B0(n5677), .Y(n5678) );
XOR2X1TS U7368 ( .A(n5678), .B(n5694), .Y(mult_x_23_n1409) );
AOI222X1TS U7369 ( .A0(n5701), .A1(n5918), .B0(n5698), .B1(n5821), .C0(n5690), .C1(n5870), .Y(n5679) );
OAI21X1TS U7370 ( .A0(n5945), .A1(n5684), .B0(n5679), .Y(n5680) );
XOR2X1TS U7371 ( .A(n5680), .B(n5694), .Y(mult_x_23_n1410) );
AOI222X1TS U7372 ( .A0(n5701), .A1(n5871), .B0(n5698), .B1(n5870), .C0(n5690), .C1(n5935), .Y(n5681) );
XOR2X1TS U7373 ( .A(n5682), .B(n5694), .Y(mult_x_23_n1411) );
AOI222X1TS U7374 ( .A0(n5701), .A1(n5849), .B0(n5975), .B1(n5866), .C0(n5690), .C1(n5906), .Y(n5683) );
XOR2X1TS U7375 ( .A(n5685), .B(n5694), .Y(mult_x_23_n1412) );
AOI222X1TS U7376 ( .A0(n5929), .A1(n6080), .B0(n5975), .B1(n6078), .C0(n5690), .C1(n829), .Y(n5686) );
XOR2X1TS U7377 ( .A(n5687), .B(n5694), .Y(mult_x_23_n1413) );
AOI222X1TS U7378 ( .A0(n5929), .A1(n6040), .B0(n5975), .B1(n6039), .C0(n5690), .C1(n6038), .Y(n5688) );
XOR2X1TS U7379 ( .A(n5689), .B(n5694), .Y(mult_x_23_n1414) );
AOI222X1TS U7380 ( .A0(n5701), .A1(n6024), .B0(n5668), .B1(n840), .C0(n5690),
.C1(n6023), .Y(n5691) );
XOR2X1TS U7381 ( .A(n5692), .B(n5694), .Y(mult_x_23_n1415) );
AOI222X1TS U7382 ( .A0(n5929), .A1(n839), .B0(n5698), .B1(n6046), .C0(n5928),
.C1(n6045), .Y(n5693) );
XOR2X1TS U7383 ( .A(n5695), .B(n5694), .Y(mult_x_23_n1416) );
AOI222X1TS U7384 ( .A0(n5929), .A1(n5790), .B0(n5975), .B1(n6032), .C0(n5974), .C1(n828), .Y(n5696) );
OAI21X1TS U7385 ( .A0(n5792), .A1(n5665), .B0(n5696), .Y(n5697) );
XOR2X1TS U7386 ( .A(n5697), .B(n895), .Y(mult_x_23_n1418) );
AOI222X1TS U7387 ( .A0(n5929), .A1(n6018), .B0(n5668), .B1(n6030), .C0(n5974), .C1(n6016), .Y(n5699) );
XOR2X1TS U7388 ( .A(n5700), .B(n7492), .Y(mult_x_23_n1419) );
AOI222X1TS U7389 ( .A0(n5701), .A1(n5796), .B0(n5975), .B1(n5982), .C0(n5974), .C1(n6005), .Y(n5702) );
XOR2X1TS U7390 ( .A(n5703), .B(n7492), .Y(mult_x_23_n1420) );
AOI222X1TS U7391 ( .A0(n5976), .A1(n814), .B0(n5698), .B1(n838), .C0(n5974),
.C1(n8385), .Y(n5704) );
XOR2X1TS U7392 ( .A(n5705), .B(n7492), .Y(mult_x_23_n1422) );
AOI222X1TS U7393 ( .A0(n5976), .A1(n838), .B0(n5668), .B1(n831), .C0(n5928),
.C1(n5901), .Y(n5706) );
OAI21X1TS U7394 ( .A0(n5905), .A1(n5978), .B0(n5706), .Y(n5707) );
XOR2X1TS U7395 ( .A(n5707), .B(n7492), .Y(mult_x_23_n1423) );
AOI222X1TS U7396 ( .A0(n5976), .A1(n5856), .B0(n5975), .B1(n5758), .C0(n5928), .C1(n849), .Y(n5708) );
OAI21X1TS U7397 ( .A0(n5762), .A1(n5978), .B0(n5708), .Y(n5709) );
XOR2X1TS U7398 ( .A(n5709), .B(n895), .Y(mult_x_23_n1426) );
AOI21X1TS U7399 ( .A0(n5732), .A1(n5883), .B0(n5745), .Y(n5713) );
OAI21X1TS U7400 ( .A0(n5887), .A1(n5761), .B0(n5713), .Y(n5714) );
AOI21X1TS U7401 ( .A0(n5732), .A1(n5771), .B0(n5715), .Y(n5716) );
OAI21X1TS U7402 ( .A0(n5773), .A1(n5761), .B0(n5716), .Y(n5717) );
XOR2X1TS U7403 ( .A(n5717), .B(n5736), .Y(mult_x_23_n1436) );
AOI222X1TS U7404 ( .A0(n5859), .A1(n5921), .B0(n5745), .B1(n5920), .C0(n5732), .C1(n5918), .Y(n5718) );
OAI21X1TS U7405 ( .A0(n5925), .A1(n5761), .B0(n5718), .Y(n5719) );
XOR2X1TS U7406 ( .A(n5719), .B(n5736), .Y(mult_x_23_n1437) );
XOR2X1TS U7407 ( .A(n5721), .B(n5736), .Y(mult_x_23_n1438) );
AOI222X1TS U7408 ( .A0(n5859), .A1(n5918), .B0(n5745), .B1(n5821), .C0(n5732), .C1(n5849), .Y(n5722) );
OAI21X1TS U7409 ( .A0(n5945), .A1(n5761), .B0(n5722), .Y(n5723) );
OAI21X1TS U7410 ( .A0(n5938), .A1(n5761), .B0(n5724), .Y(n5725) );
XOR2X1TS U7411 ( .A(n5725), .B(n5736), .Y(mult_x_23_n1440) );
AOI222X1TS U7412 ( .A0(n5859), .A1(n5849), .B0(n5745), .B1(n5866), .C0(n5732), .C1(n6040), .Y(n5726) );
OAI21X1TS U7413 ( .A0(n5896), .A1(n5761), .B0(n5726), .Y(n5727) );
XOR2X1TS U7414 ( .A(n5727), .B(n5736), .Y(mult_x_23_n1441) );
AOI222X1TS U7415 ( .A0(n5742), .A1(n6080), .B0(n5759), .B1(n6078), .C0(n5732), .C1(n6024), .Y(n5728) );
XOR2X1TS U7416 ( .A(n5729), .B(n5736), .Y(mult_x_23_n1442) );
AOI222X1TS U7417 ( .A0(n5742), .A1(n6040), .B0(n5745), .B1(n6039), .C0(n5732), .C1(Op_MY[43]), .Y(n5730) );
XOR2X1TS U7418 ( .A(n5731), .B(n5736), .Y(mult_x_23_n1443) );
XOR2X1TS U7419 ( .A(n5734), .B(n5736), .Y(mult_x_23_n1444) );
AOI222X1TS U7420 ( .A0(n5742), .A1(Op_MY[43]), .B0(n5759), .B1(n6046), .C0(
n5857), .C1(n5790), .Y(n5735) );
AOI222X1TS U7421 ( .A0(n5742), .A1(n5966), .B0(n5759), .B1(n5965), .C0(n5857), .C1(n6018), .Y(n5738) );
XOR2X1TS U7422 ( .A(n5739), .B(n5763), .Y(mult_x_23_n1446) );
AOI222X1TS U7423 ( .A0(n5742), .A1(n5790), .B0(n5759), .B1(n6032), .C0(n5751), .C1(n5796), .Y(n5740) );
OAI21X1TS U7424 ( .A0(n5792), .A1(n5861), .B0(n5740), .Y(n5741) );
XOR2X1TS U7425 ( .A(n5741), .B(n5763), .Y(mult_x_23_n1447) );
AOI222X1TS U7426 ( .A0(n5742), .A1(n6018), .B0(n5745), .B1(n6030), .C0(n5857), .C1(n6028), .Y(n5743) );
XOR2X1TS U7427 ( .A(n5744), .B(Op_MX[32]), .Y(mult_x_23_n1448) );
XOR2X1TS U7428 ( .A(n5747), .B(n8404), .Y(mult_x_23_n1449) );
BUFX3TS U7429 ( .A(n5748), .Y(n5859) );
AOI222X1TS U7430 ( .A0(n5859), .A1(n6028), .B0(n5712), .B1(n6005), .C0(n5857), .C1(n838), .Y(n5749) );
XOR2X1TS U7431 ( .A(n5750), .B(Op_MX[32]), .Y(mult_x_23_n1450) );
XOR2X1TS U7432 ( .A(n5753), .B(n8404), .Y(mult_x_23_n1451) );
AOI222X1TS U7433 ( .A0(n5859), .A1(n837), .B0(n5712), .B1(n8385), .C0(n5857),
.C1(n5999), .Y(n5754) );
XOR2X1TS U7434 ( .A(n5755), .B(n8404), .Y(mult_x_23_n1452) );
AOI222X1TS U7435 ( .A0(n5859), .A1(n5999), .B0(n5712), .B1(n5998), .C0(n5857), .C1(n852), .Y(n5756) );
XOR2X1TS U7436 ( .A(n5757), .B(n5763), .Y(mult_x_23_n1454) );
AOI222X1TS U7437 ( .A0(n5859), .A1(n5856), .B0(n5759), .B1(n5758), .C0(n5857), .C1(n848), .Y(n5760) );
XOR2X1TS U7438 ( .A(n5764), .B(n5763), .Y(mult_x_23_n1455) );
BUFX3TS U7439 ( .A(n5766), .Y(n6083) );
AOI21X1TS U7440 ( .A0(n6077), .A1(n5769), .B0(n873), .Y(n5767) );
XOR2X1TS U7441 ( .A(n5768), .B(n7491), .Y(mult_x_23_n1464) );
AOI21X1TS U7442 ( .A0(n6077), .A1(n5771), .B0(n5770), .Y(n5772) );
OAI21X1TS U7443 ( .A0(n5773), .A1(n6083), .B0(n5772), .Y(n5774) );
AOI222X1TS U7444 ( .A0(n870), .A1(n5921), .B0(n3669), .B1(n5920), .C0(n6077),
.C1(n5775), .Y(n5776) );
OAI21X1TS U7445 ( .A0(n5925), .A1(n6083), .B0(n5776), .Y(n5777) );
XOR2X1TS U7446 ( .A(n5777), .B(n5819), .Y(mult_x_23_n1466) );
AOI222X1TS U7447 ( .A0(n871), .A1(n5779), .B0(n3669), .B1(n5778), .C0(n6077),
.C1(n5939), .Y(n5780) );
XOR2X1TS U7448 ( .A(n5782), .B(n5819), .Y(mult_x_23_n1467) );
AOI222X1TS U7449 ( .A0(n870), .A1(n5871), .B0(n3669), .B1(n5870), .C0(n6077),
.C1(n5935), .Y(n5783) );
OAI21X1TS U7450 ( .A0(n5938), .A1(n6083), .B0(n5783), .Y(n5784) );
XOR2X1TS U7451 ( .A(n5784), .B(n5819), .Y(mult_x_23_n1469) );
AOI222X1TS U7452 ( .A0(n870), .A1(n5849), .B0(n873), .B1(n5866), .C0(n6077),
.C1(n5906), .Y(n5785) );
OAI21X1TS U7453 ( .A0(n5896), .A1(n6083), .B0(n5785), .Y(n5786) );
XOR2X1TS U7454 ( .A(n5786), .B(n7491), .Y(mult_x_23_n1470) );
AOI222X1TS U7455 ( .A0(n6081), .A1(Op_MY[43]), .B0(n6079), .B1(n6046), .C0(
n5964), .C1(n6045), .Y(n5787) );
XOR2X1TS U7456 ( .A(n5788), .B(n7491), .Y(mult_x_23_n1474) );
INVX2TS U7457 ( .A(n5789), .Y(n5801) );
AOI222X1TS U7458 ( .A0(n6081), .A1(n5790), .B0(n6079), .B1(n6032), .C0(n5801), .C1(n828), .Y(n5791) );
OAI21X1TS U7459 ( .A0(n5792), .A1(n6042), .B0(n5791), .Y(n5793) );
XOR2X1TS U7460 ( .A(n5793), .B(n5804), .Y(mult_x_23_n1476) );
AOI222X1TS U7461 ( .A0(n6081), .A1(n6018), .B0(n873), .B1(n6030), .C0(n5801),
.C1(n6016), .Y(n5794) );
XOR2X1TS U7462 ( .A(n5795), .B(n5804), .Y(mult_x_23_n1477) );
AOI222X1TS U7463 ( .A0(n871), .A1(n5796), .B0(n3669), .B1(n5982), .C0(n5801),
.C1(n814), .Y(n5797) );
OAI21X1TS U7464 ( .A0(n5876), .A1(n5807), .B0(n5797), .Y(n5798) );
XOR2X1TS U7465 ( .A(n5798), .B(n5804), .Y(mult_x_23_n1478) );
AOI222X1TS U7466 ( .A0(n870), .A1(n6028), .B0(n873), .B1(n814), .C0(n5801),
.C1(n850), .Y(n5799) );
XOR2X1TS U7467 ( .A(n5800), .B(n5804), .Y(mult_x_23_n1479) );
XOR2X1TS U7468 ( .A(n5805), .B(n5804), .Y(mult_x_23_n1480) );
AOI222X1TS U7469 ( .A0(n870), .A1(n838), .B0(n3669), .B1(n831), .C0(n5964),
.C1(n5901), .Y(n5806) );
XOR2X1TS U7470 ( .A(n5808), .B(n5819), .Y(mult_x_23_n1481) );
INVX2TS U7471 ( .A(n5809), .Y(n5811) );
NAND2X1TS U7472 ( .A(n5811), .B(n5810), .Y(n5812) );
NAND2X1TS U7473 ( .A(n5815), .B(n5814), .Y(n5816) );
XNOR2X1TS U7474 ( .A(n5817), .B(n5816), .Y(Sgf_operation_ODD1_left_N8) );
AOI222X1TS U7475 ( .A0(n871), .A1(n5918), .B0(n873), .B1(n5821), .C0(n6077),
.C1(n5942), .Y(n5818) );
OAI21X1TS U7476 ( .A0(n5945), .A1(n6083), .B0(n5818), .Y(n5820) );
XOR2X1TS U7477 ( .A(n5820), .B(n5819), .Y(mult_x_23_n1468) );
AOI222X1TS U7478 ( .A0(n5922), .A1(n5918), .B0(n6011), .B1(n5821), .C0(n5919), .C1(n5849), .Y(n5822) );
XOR2X1TS U7479 ( .A(n5823), .B(n5926), .Y(mult_x_23_n1323) );
AOI222X1TS U7480 ( .A0(n5825), .A1(n5921), .B0(n867), .B1(n5920), .C0(n5824),
.C1(n5918), .Y(n5826) );
AOI222X1TS U7481 ( .A0(n5831), .A1(n8375), .B0(n5830), .B1(n6055), .C0(n5997), .C1(n6054), .Y(n5832) );
XOR2X1TS U7482 ( .A(n5833), .B(n6002), .Y(mult_x_23_n1371) );
OAI21X1TS U7483 ( .A0(n5879), .A1(n5924), .B0(n5835), .Y(n5836) );
XOR2X1TS U7484 ( .A(n5836), .B(n737), .Y(n5837) );
AOI222X1TS U7485 ( .A0(n5840), .A1(n8375), .B0(n6031), .B1(n6055), .C0(n5844), .C1(n5839), .Y(n5841) );
OAI21X1TS U7486 ( .A0(n1001), .A1(n5491), .B0(n5841), .Y(n5842) );
AOI222X1TS U7487 ( .A0(n5845), .A1(n8376), .B0(n923), .B1(n830), .C0(n5844),
.C1(n5843), .Y(n5846) );
OAI21X1TS U7488 ( .A0(n6068), .A1(n6035), .B0(n5846), .Y(n5848) );
XOR2X1TS U7489 ( .A(n5848), .B(n5847), .Y(mult_x_23_n1312) );
AOI222X1TS U7490 ( .A0(n5922), .A1(n5849), .B0(n6011), .B1(n5866), .C0(n5919), .C1(n6040), .Y(n5850) );
OAI21X1TS U7491 ( .A0(n5896), .A1(n5924), .B0(n5850), .Y(n5851) );
XOR2X1TS U7492 ( .A(n5851), .B(n5926), .Y(mult_x_23_n1325) );
AOI222X1TS U7493 ( .A0(n5976), .A1(n5999), .B0(n5668), .B1(n5998), .C0(n5928), .C1(n852), .Y(n5854) );
OAI21X1TS U7494 ( .A0(n6001), .A1(n5978), .B0(n5854), .Y(n5855) );
XOR2X1TS U7495 ( .A(n5855), .B(n895), .Y(mult_x_23_n1425) );
AOI222X1TS U7496 ( .A0(n5859), .A1(n832), .B0(n5745), .B1(n5858), .C0(n5857),
.C1(n5856), .Y(n5860) );
XOR2X1TS U7497 ( .A(n5862), .B(n8404), .Y(mult_x_23_n1453) );
AOI222X1TS U7498 ( .A0(n6019), .A1(n6080), .B0(n6064), .B1(n6078), .C0(n5863), .C1(n829), .Y(n5864) );
AOI222X1TS U7499 ( .A0(n6033), .A1(n5866), .B0(n923), .B1(n6078), .C0(n5884),
.C1(n6024), .Y(n5867) );
OAI21X1TS U7500 ( .A0(n6084), .A1(n5491), .B0(n5867), .Y(n5869) );
XOR2X1TS U7501 ( .A(n5869), .B(n5868), .Y(mult_x_23_n1297) );
AOI222X1TS U7502 ( .A0(n5922), .A1(n5871), .B0(n6011), .B1(n5870), .C0(n5919), .C1(n6080), .Y(n5872) );
OAI21X1TS U7503 ( .A0(n5938), .A1(n5924), .B0(n5872), .Y(n5873) );
XOR2X1TS U7504 ( .A(n5873), .B(n5926), .Y(mult_x_23_n1324) );
AOI21X1TS U7505 ( .A0(n5902), .A1(n814), .B0(n5874), .Y(n5875) );
INVX2TS U7506 ( .A(n6051), .Y(n5882) );
OAI21X1TS U7507 ( .A0(n5879), .A1(n5878), .B0(n5877), .Y(n5880) );
XOR2X1TS U7508 ( .A(n5880), .B(n7500), .Y(n5881) );
CMPR32X2TS U7509 ( .A(n5882), .B(mult_x_23_n714), .C(n5881), .CO(
mult_x_23_n702), .S(mult_x_23_n703) );
AOI21X1TS U7510 ( .A0(n5884), .A1(n5883), .B0(n5494), .Y(n5885) );
OAI21X1TS U7511 ( .A0(n5887), .A1(n5886), .B0(n5885), .Y(n5888) );
XOR2X1TS U7512 ( .A(n5888), .B(n7493), .Y(mult_x_23_n1290) );
AOI21X1TS U7513 ( .A0(n5936), .A1(n5963), .B0(n5889), .Y(n5890) );
OAI21X1TS U7514 ( .A0(n5968), .A1(n6061), .B0(n5890), .Y(mult_x_23_n1247) );
AND2X2TS U7515 ( .A(n5899), .B(n5901), .Y(n5891) );
AOI21X1TS U7516 ( .A0(n5902), .A1(n5892), .B0(n5891), .Y(n5893) );
OAI21X2TS U7517 ( .A0(n979), .A1(n5904), .B0(n5893), .Y(mult_x_23_n733) );
AOI21X1TS U7518 ( .A0(n5936), .A1(n5906), .B0(n5894), .Y(n5895) );
OAI21X2TS U7519 ( .A0(n5896), .A1(n6052), .B0(n5895), .Y(mult_x_23_n643) );
AOI21X1TS U7520 ( .A0(n5902), .A1(n6016), .B0(n5897), .Y(n5898) );
OAI21X1TS U7521 ( .A0(n6036), .A1(n6052), .B0(n5898), .Y(mult_x_23_n1248) );
AOI21X1TS U7522 ( .A0(n5902), .A1(n5901), .B0(n5900), .Y(n5903) );
OAI21X1TS U7523 ( .A0(n5905), .A1(n5904), .B0(n5903), .Y(mult_x_23_n1251) );
AOI21X1TS U7524 ( .A0(n5936), .A1(n829), .B0(n5907), .Y(n5908) );
OAI21X1TS U7525 ( .A0(n6084), .A1(n6052), .B0(n5908), .Y(mult_x_23_n1244) );
INVX2TS U7526 ( .A(mult_x_23_n679), .Y(mult_x_23_n687) );
AOI222X1TS U7527 ( .A0(n6012), .A1(n6040), .B0(n6011), .B1(n6039), .C0(n5919), .C1(n839), .Y(n5911) );
OAI21X1TS U7528 ( .A0(n5912), .A1(n4671), .B0(n5911), .Y(n5913) );
XOR2X1TS U7529 ( .A(n5913), .B(n5926), .Y(mult_x_23_n1327) );
AOI222X1TS U7530 ( .A0(n5929), .A1(n5966), .B0(n5975), .B1(n5965), .C0(n5928), .C1(n5963), .Y(n5914) );
OAI21X1TS U7531 ( .A0(n5968), .A1(n5665), .B0(n5914), .Y(n5915) );
XOR2X1TS U7532 ( .A(n5915), .B(n895), .Y(mult_x_23_n1417) );
AOI222X1TS U7533 ( .A0(n5929), .A1(n8375), .B0(n5698), .B1(n6055), .C0(n5928), .C1(n6054), .Y(n5916) );
AOI222X1TS U7534 ( .A0(n5922), .A1(n5921), .B0(n6011), .B1(n5920), .C0(n5919), .C1(n5918), .Y(n5923) );
XOR2X1TS U7535 ( .A(n5927), .B(n5926), .Y(mult_x_23_n1321) );
INVX2TS U7536 ( .A(mult_x_23_n733), .Y(mult_x_23_n744) );
INVX2TS U7537 ( .A(mult_x_23_n643), .Y(mult_x_23_n648) );
AOI222X1TS U7538 ( .A0(n5929), .A1(n5996), .B0(n5668), .B1(n8376), .C0(n5928), .C1(Op_MY[30]), .Y(n5930) );
XOR2X1TS U7539 ( .A(n5932), .B(n895), .Y(mult_x_23_n1427) );
ADDHX1TS U7540 ( .A(n7500), .B(n5933), .CO(n4760), .S(mult_x_23_n955) );
AOI21X1TS U7541 ( .A0(n5936), .A1(n5935), .B0(n5934), .Y(n5937) );
AOI21X1TS U7542 ( .A0(n5943), .A1(n5942), .B0(n5941), .Y(n5944) );
OAI21X1TS U7543 ( .A0(n5945), .A1(n6052), .B0(n5944), .Y(mult_x_23_n1242) );
INVX2TS U7544 ( .A(n5946), .Y(n5948) );
NAND2X1TS U7545 ( .A(n5948), .B(n5947), .Y(n5949) );
INVX2TS U7546 ( .A(n5951), .Y(n5953) );
NAND2X1TS U7547 ( .A(n5953), .B(n5952), .Y(n5954) );
XOR2X1TS U7548 ( .A(n5958), .B(n7500), .Y(mult_x_23_n1393) );
AOI222X1TS U7549 ( .A0(n5960), .A1(n6032), .B0(n5959), .B1(n6030), .C0(n5980), .C1(n6016), .Y(n5961) );
XOR2X1TS U7550 ( .A(n5962), .B(n7500), .Y(mult_x_23_n1390) );
AOI222X1TS U7551 ( .A0(n6081), .A1(n5966), .B0(n6079), .B1(n5965), .C0(n5964), .C1(n5963), .Y(n5967) );
XOR2X1TS U7552 ( .A(n5969), .B(Op_MX[29]), .Y(mult_x_23_n1475) );
AOI222X1TS U7553 ( .A0(n6033), .A1(n5982), .B0(n6031), .B1(n814), .C0(n6029),
.C1(n837), .Y(n5970) );
OAI21X1TS U7554 ( .A0(n6008), .A1(n6035), .B0(n5970), .Y(n5971) );
XOR2X1TS U7555 ( .A(n5971), .B(n7493), .Y(mult_x_23_n1305) );
XOR2X1TS U7556 ( .A(n5973), .B(n6021), .Y(mult_x_23_n1276) );
AOI222X1TS U7557 ( .A0(n5976), .A1(n6028), .B0(n5698), .B1(n7507), .C0(n5974), .C1(n850), .Y(n5977) );
XOR2X1TS U7558 ( .A(n5979), .B(n7492), .Y(mult_x_23_n1421) );
AOI222X1TS U7559 ( .A0(n5983), .A1(n5982), .B0(n5981), .B1(n814), .C0(n5980),
.C1(n850), .Y(n5984) );
OAI21X1TS U7560 ( .A0(n6008), .A1(n5985), .B0(n5984), .Y(n5986) );
XOR2X1TS U7561 ( .A(n5986), .B(n7500), .Y(mult_x_23_n1392) );
AOI222X1TS U7562 ( .A0(n5095), .A1(n5999), .B0(n867), .B1(n5998), .C0(n5997),
.C1(n5996), .Y(n6000) );
OAI21X1TS U7563 ( .A0(n6001), .A1(n6007), .B0(n6000), .Y(n6003) );
XOR2X1TS U7564 ( .A(n6003), .B(n6002), .Y(mult_x_23_n1367) );
AOI222X1TS U7565 ( .A0(n5095), .A1(n6028), .B0(n868), .B1(n5802), .C0(n6004),
.C1(n838), .Y(n6006) );
XOR2X1TS U7566 ( .A(n6009), .B(n7498), .Y(mult_x_23_n1363) );
AOI222X1TS U7567 ( .A0(n6012), .A1(n6018), .B0(n6011), .B1(n6030), .C0(n6010), .C1(n6028), .Y(n6013) );
XOR2X1TS U7568 ( .A(n6015), .B(n737), .Y(mult_x_23_n1332) );
AOI222X1TS U7569 ( .A0(n881), .A1(n6018), .B0(n865), .B1(n6030), .C0(n6017),
.C1(n6016), .Y(n6020) );
OAI21X1TS U7570 ( .A0(n6036), .A1(n6067), .B0(n6020), .Y(n6022) );
XOR2X1TS U7571 ( .A(n6022), .B(n6021), .Y(mult_x_23_n1274) );
AOI222X1TS U7572 ( .A0(n871), .A1(n6024), .B0(n6079), .B1(n840), .C0(n6077),
.C1(n6023), .Y(n6025) );
OAI21X1TS U7573 ( .A0(n6026), .A1(n6042), .B0(n6025), .Y(n6027) );
XOR2X1TS U7574 ( .A(n6027), .B(Op_MX[29]), .Y(mult_x_23_n1473) );
AOI222X1TS U7575 ( .A0(n6033), .A1(n6032), .B0(n6031), .B1(n6030), .C0(n6029), .C1(n6028), .Y(n6034) );
XOR2X1TS U7576 ( .A(n6037), .B(n7493), .Y(mult_x_23_n1303) );
AOI222X1TS U7577 ( .A0(n6081), .A1(n6040), .B0(n3669), .B1(n6039), .C0(n6077), .C1(n6038), .Y(n6041) );
OAI21X1TS U7578 ( .A0(n6043), .A1(n6042), .B0(n6041), .Y(n6044) );
XOR2X1TS U7579 ( .A(n6044), .B(Op_MX[29]), .Y(mult_x_23_n1472) );
AOI222X1TS U7580 ( .A0(n6065), .A1(n839), .B0(n6064), .B1(n6046), .C0(n6063),
.C1(n6045), .Y(n6047) );
ADDFHX1TS U7581 ( .A(n1020), .B(n6051), .CI(n6050), .CO(mult_x_23_n694), .S(
mult_x_23_n695) );
NOR2X1TS U7582 ( .A(n6053), .B(n6052), .Y(n6073) );
OAI21X1TS U7583 ( .A0(n1001), .A1(n4965), .B0(n6056), .Y(n6057) );
XOR2X2TS U7584 ( .A(n6057), .B(n6069), .Y(n6072) );
CMPR22X2TS U7585 ( .A(n6059), .B(n6058), .CO(n6071), .S(mult_x_23_n843) );
OAI21X1TS U7586 ( .A0(n6062), .A1(n6061), .B0(n796), .Y(n6076) );
AOI222X1TS U7587 ( .A0(n6065), .A1(n7510), .B0(n6064), .B1(n851), .C0(n6063),
.C1(n5843), .Y(n6066) );
OAI21X1TS U7588 ( .A0(n6068), .A1(n6067), .B0(n6066), .Y(n6070) );
XOR2X1TS U7589 ( .A(n6070), .B(n6069), .Y(n6075) );
ADDFHX1TS U7590 ( .A(n6076), .B(n6075), .CI(n6074), .CO(mult_x_23_n820), .S(
mult_x_23_n821) );
AOI222X1TS U7591 ( .A0(n6081), .A1(n6080), .B0(n6079), .B1(n6078), .C0(n6077), .C1(n829), .Y(n6082) );
OAI21X1TS U7592 ( .A0(n6084), .A1(n6083), .B0(n6082), .Y(n6085) );
XOR2X1TS U7593 ( .A(n6085), .B(Op_MX[29]), .Y(mult_x_23_n1471) );
INVX2TS U7594 ( .A(n6088), .Y(n6090) );
NAND2X1TS U7595 ( .A(n6090), .B(n6089), .Y(n6091) );
INVX2TS U7596 ( .A(n6094), .Y(n6097) );
INVX2TS U7597 ( .A(n6095), .Y(n6096) );
INVX2TS U7598 ( .A(n6098), .Y(n6100) );
NAND2X1TS U7599 ( .A(n6100), .B(n6099), .Y(n6101) );
NAND2X1TS U7600 ( .A(n7107), .B(n6103), .Y(n6104) );
XNOR2X1TS U7601 ( .A(n7108), .B(n6104), .Y(Sgf_operation_ODD1_right_N25) );
INVX2TS U7602 ( .A(n6117), .Y(n6107) );
NAND2X1TS U7603 ( .A(n6107), .B(n6119), .Y(n6111) );
INVX2TS U7604 ( .A(n6116), .Y(n6109) );
AOI21X1TS U7605 ( .A0(n6109), .A1(n6119), .B0(n6108), .Y(n6110) );
NAND2X1TS U7606 ( .A(n6113), .B(n6112), .Y(n6114) );
XNOR2X1TS U7607 ( .A(n6115), .B(n6114), .Y(Sgf_operation_ODD1_right_N24) );
NAND2X1TS U7608 ( .A(n6119), .B(n6118), .Y(n6120) );
XNOR2X1TS U7609 ( .A(n6121), .B(n6120), .Y(Sgf_operation_ODD1_right_N23) );
NAND2X1TS U7610 ( .A(n6124), .B(n6123), .Y(n6125) );
XNOR2X1TS U7611 ( .A(n6126), .B(n6125), .Y(Sgf_operation_ODD1_right_N22) );
NAND2X1TS U7612 ( .A(n6128), .B(n6127), .Y(n6129) );
INVX2TS U7613 ( .A(n6131), .Y(n6139) );
NAND2X1TS U7614 ( .A(n972), .B(n6133), .Y(n6134) );
NAND2X1TS U7615 ( .A(n6137), .B(n6136), .Y(n6138) );
XNOR2X1TS U7616 ( .A(n6139), .B(n6138), .Y(Sgf_operation_ODD1_right_N19) );
INVX2TS U7617 ( .A(n6140), .Y(n6951) );
INVX2TS U7618 ( .A(n6141), .Y(n6143) );
NAND2X1TS U7619 ( .A(n6143), .B(n6142), .Y(n6144) );
XNOR2X1TS U7620 ( .A(n6145), .B(n6144), .Y(Sgf_operation_ODD1_right_N18) );
NAND2X1TS U7621 ( .A(n6150), .B(n6149), .Y(n6151) );
INVX2TS U7622 ( .A(n6153), .Y(n6161) );
INVX2TS U7623 ( .A(n6160), .Y(n6154) );
AOI21X1TS U7624 ( .A0(n6163), .A1(n6161), .B0(n6154), .Y(n6159) );
INVX2TS U7625 ( .A(n6155), .Y(n6157) );
NAND2X1TS U7626 ( .A(n6157), .B(n6156), .Y(n6158) );
NAND2X1TS U7627 ( .A(n6161), .B(n6160), .Y(n6162) );
XNOR2X1TS U7628 ( .A(n6163), .B(n6162), .Y(Sgf_operation_ODD1_right_N14) );
INVX2TS U7629 ( .A(n6164), .Y(n6957) );
INVX2TS U7630 ( .A(n6165), .Y(n6167) );
NAND2X1TS U7631 ( .A(n6167), .B(n6166), .Y(n6168) );
XNOR2X1TS U7632 ( .A(n6169), .B(n6168), .Y(Sgf_operation_ODD1_right_N13) );
INVX2TS U7633 ( .A(n6170), .Y(n6178) );
AOI21X1TS U7634 ( .A0(n6178), .A1(n779), .B0(n6171), .Y(n6175) );
NAND2X1TS U7635 ( .A(n6173), .B(n6172), .Y(n6174) );
NAND2X1TS U7636 ( .A(n779), .B(n6176), .Y(n6177) );
XNOR2X1TS U7637 ( .A(n6178), .B(n6177), .Y(Sgf_operation_ODD1_right_N10) );
NAND2X1TS U7638 ( .A(n6180), .B(n6179), .Y(n6182) );
XNOR2X1TS U7639 ( .A(n6182), .B(n6181), .Y(Sgf_operation_ODD1_right_N9) );
INVX2TS U7640 ( .A(n6183), .Y(n6192) );
AOI21X1TS U7641 ( .A0(n6192), .A1(n6190), .B0(n6184), .Y(n6188) );
NAND2X1TS U7642 ( .A(n6186), .B(n6185), .Y(n6187) );
NAND2X1TS U7643 ( .A(n6190), .B(n6189), .Y(n6191) );
XNOR2X1TS U7644 ( .A(n6192), .B(n6191), .Y(Sgf_operation_ODD1_right_N7) );
INVX2TS U7645 ( .A(n6193), .Y(n6202) );
INVX2TS U7646 ( .A(n6194), .Y(n6196) );
NAND2X1TS U7647 ( .A(n6196), .B(n6195), .Y(n6197) );
XNOR2X1TS U7648 ( .A(n6198), .B(n6197), .Y(Sgf_operation_ODD1_right_N6) );
INVX2TS U7649 ( .A(n6199), .Y(n6201) );
NAND2X1TS U7650 ( .A(n6201), .B(n6200), .Y(n6203) );
INVX2TS U7651 ( .A(n6204), .Y(n6206) );
NAND2X1TS U7652 ( .A(n6206), .B(n6205), .Y(n6207) );
NAND2X1TS U7653 ( .A(n1014), .B(n6209), .Y(n6211) );
XNOR2X1TS U7654 ( .A(n6211), .B(n6210), .Y(Sgf_operation_ODD1_right_N3) );
INVX2TS U7655 ( .A(n6213), .Y(n6215) );
XNOR2X1TS U7656 ( .A(n6215), .B(n6214), .Y(Sgf_operation_ODD1_right_N1) );
CMPR32X2TS U7657 ( .A(n1018), .B(n6217), .C(n6216), .CO(mult_x_24_n707), .S(
mult_x_24_n708) );
AOI21X1TS U7658 ( .A0(n6491), .A1(n925), .B0(n6218), .Y(n6219) );
OAI21X1TS U7659 ( .A0(n7006), .A1(n7013), .B0(n6219), .Y(n6221) );
XOR2X1TS U7660 ( .A(n6221), .B(n6220), .Y(n6222) );
AND2X2TS U7661 ( .A(n7087), .B(n875), .Y(n6225) );
CMPR32X2TS U7662 ( .A(n1009), .B(n6225), .C(n6224), .CO(mult_x_24_n747), .S(
mult_x_24_n748) );
INVX2TS U7663 ( .A(n6225), .Y(n7067) );
NAND2X1TS U7664 ( .A(n6982), .B(n6989), .Y(n6226) );
XOR2X1TS U7665 ( .A(n6227), .B(Op_MY[14]), .Y(n6228) );
CMPR32X2TS U7666 ( .A(n6229), .B(n7067), .C(n6228), .CO(mult_x_24_n755), .S(
mult_x_24_n756) );
INVX2TS U7667 ( .A(n6936), .Y(n7090) );
INVX2TS U7668 ( .A(n1205), .Y(n6233) );
NAND2X1TS U7669 ( .A(n6233), .B(n6232), .Y(n6234) );
XNOR2X4TS U7670 ( .A(n6235), .B(n6234), .Y(n6236) );
BUFX3TS U7671 ( .A(n6238), .Y(n7083) );
AOI222X1TS U7672 ( .A0(n7083), .A1(n841), .B0(n7081), .B1(n8413), .C0(n7080),
.C1(n6780), .Y(n6240) );
OAI21X2TS U7673 ( .A0(n6912), .A1(n7085), .B0(n6240), .Y(n6241) );
XOR2X1TS U7674 ( .A(n6241), .B(n6882), .Y(n6242) );
CMPR32X2TS U7675 ( .A(n7090), .B(mult_x_24_n840), .C(n6242), .CO(
mult_x_24_n828), .S(mult_x_24_n829) );
OAI21X4TS U7676 ( .A0(n740), .A1(n6247), .B0(n6246), .Y(n6252) );
INVX2TS U7677 ( .A(n6248), .Y(n6250) );
XNOR2X4TS U7678 ( .A(n6252), .B(n6251), .Y(n6253) );
AOI222X1TS U7679 ( .A0(n7060), .A1(n6963), .B0(n6921), .B1(n925), .C0(n6920),
.C1(n6959), .Y(n6254) );
OAI21X1TS U7680 ( .A0(n6967), .A1(n6925), .B0(n6254), .Y(n6255) );
XOR2X1TS U7681 ( .A(n6255), .B(n7087), .Y(mult_x_24_n1400) );
INVX2TS U7682 ( .A(n6256), .Y(n6273) );
INVX2TS U7683 ( .A(n6272), .Y(n6257) );
INVX2TS U7684 ( .A(n6260), .Y(n6262) );
XNOR2X4TS U7685 ( .A(n6264), .B(n6263), .Y(n6265) );
BUFX3TS U7686 ( .A(Op_MX[25]), .Y(n6961) );
AOI222X1TS U7687 ( .A0(n6923), .A1(n6961), .B0(n6921), .B1(Op_MX[24]), .C0(
n6920), .C1(n834), .Y(n6266) );
XOR2X1TS U7688 ( .A(n6267), .B(n7064), .Y(mult_x_24_n1401) );
INVX2TS U7689 ( .A(n6268), .Y(n6271) );
INVX2TS U7690 ( .A(n6269), .Y(n6270) );
OAI21X4TS U7691 ( .A0(n740), .A1(n6271), .B0(n6270), .Y(n6275) );
XNOR2X4TS U7692 ( .A(n6275), .B(n6274), .Y(n6276) );
BUFX3TS U7693 ( .A(Op_MX[24]), .Y(n6767) );
AOI222X1TS U7694 ( .A0(n6923), .A1(n6767), .B0(n6921), .B1(n834), .C0(n6920),
.C1(n6551), .Y(n6277) );
OAI21X1TS U7695 ( .A0(n6703), .A1(n6925), .B0(n6277), .Y(n6278) );
XOR2X1TS U7696 ( .A(n6278), .B(n7078), .Y(mult_x_24_n1402) );
INVX2TS U7697 ( .A(n6391), .Y(n6279) );
INVX2TS U7698 ( .A(n6390), .Y(n6282) );
OAI21X1TS U7699 ( .A0(n6282), .A1(n6395), .B0(n6396), .Y(n6283) );
INVX2TS U7700 ( .A(n6287), .Y(n6289) );
XNOR2X4TS U7701 ( .A(n6291), .B(n6290), .Y(n6292) );
BUFX3TS U7702 ( .A(n834), .Y(n6701) );
CLKBUFX2TS U7703 ( .A(Op_MX[22]), .Y(n6551) );
AOI222X1TS U7704 ( .A0(n6923), .A1(n6701), .B0(n6921), .B1(n6551), .C0(n7080), .C1(n6952), .Y(n6293) );
OAI21X1TS U7705 ( .A0(n6778), .A1(n6925), .B0(n6293), .Y(n6294) );
XOR2X1TS U7706 ( .A(n6294), .B(n7064), .Y(mult_x_24_n1403) );
INVX2TS U7707 ( .A(n6295), .Y(n6296) );
INVX2TS U7708 ( .A(n6300), .Y(n6302) );
XNOR2X4TS U7709 ( .A(n6304), .B(n6303), .Y(n6305) );
BUFX3TS U7710 ( .A(Op_MX[21]), .Y(n6814) );
XOR2X1TS U7711 ( .A(n6307), .B(n7064), .Y(mult_x_24_n1405) );
BUFX3TS U7712 ( .A(n878), .Y(n6846) );
AOI222X1TS U7713 ( .A0(n6923), .A1(n6846), .B0(n6921), .B1(n6749), .C0(n6920), .C1(n927), .Y(n6308) );
OAI21X1TS U7714 ( .A0(n6832), .A1(n6925), .B0(n6308), .Y(n6309) );
XOR2X1TS U7715 ( .A(n6309), .B(n7064), .Y(mult_x_24_n1406) );
INVX2TS U7716 ( .A(n6326), .Y(n6311) );
AOI21X1TS U7717 ( .A0(n6323), .A1(n6327), .B0(n6311), .Y(n6312) );
INVX2TS U7718 ( .A(n6314), .Y(n6316) );
XNOR2X4TS U7719 ( .A(n6318), .B(n6317), .Y(n6319) );
CLKBUFX2TS U7720 ( .A(Op_MX[18]), .Y(n8403) );
AOI222X1TS U7721 ( .A0(n7060), .A1(n6830), .B0(n6921), .B1(n927), .C0(n6920),
.C1(n6559), .Y(n6320) );
OAI21X1TS U7722 ( .A0(n6933), .A1(n7062), .B0(n6320), .Y(n6321) );
XOR2X1TS U7723 ( .A(n6321), .B(n7064), .Y(mult_x_24_n1407) );
INVX2TS U7724 ( .A(n6322), .Y(n6325) );
INVX2TS U7725 ( .A(n6323), .Y(n6324) );
OAI21X4TS U7726 ( .A0(n820), .A1(n6325), .B0(n6324), .Y(n6329) );
XNOR2X4TS U7727 ( .A(n6329), .B(n6328), .Y(n6330) );
BUFX3TS U7728 ( .A(n6829), .Y(n6929) );
AOI222X1TS U7729 ( .A0(n6923), .A1(n6929), .B0(n7058), .B1(n6559), .C0(n7057), .C1(n6562), .Y(n6331) );
OAI21X1TS U7730 ( .A0(n6793), .A1(n7062), .B0(n6331), .Y(n6332) );
XOR2X1TS U7731 ( .A(n6332), .B(n6882), .Y(mult_x_24_n1408) );
INVX2TS U7732 ( .A(n6333), .Y(n6335) );
NAND2X1TS U7733 ( .A(n6335), .B(n6334), .Y(n6336) );
XNOR2X4TS U7734 ( .A(n6337), .B(n6336), .Y(n6338) );
BUFX3TS U7735 ( .A(n6559), .Y(n6790) );
AOI222X1TS U7736 ( .A0(n7060), .A1(n6790), .B0(n7058), .B1(n6562), .C0(n7057), .C1(n6945), .Y(n6339) );
OAI21X1TS U7737 ( .A0(n6918), .A1(n7062), .B0(n6339), .Y(n6340) );
XOR2X1TS U7738 ( .A(n6340), .B(n7064), .Y(mult_x_24_n1409) );
INVX2TS U7739 ( .A(n6425), .Y(n6343) );
XNOR2X4TS U7740 ( .A(n6345), .B(n6344), .Y(n6346) );
BUFX3TS U7741 ( .A(n8412), .Y(n7071) );
XOR2X1TS U7742 ( .A(n6348), .B(n6882), .Y(mult_x_24_n1412) );
INVX2TS U7743 ( .A(n6363), .Y(n6350) );
OAI21X4TS U7744 ( .A0(n6461), .A1(n6352), .B0(n6351), .Y(n6357) );
INVX2TS U7745 ( .A(n6353), .Y(n6355) );
XNOR2X4TS U7746 ( .A(n6357), .B(n6356), .Y(n6358) );
BUFX3TS U7747 ( .A(n6569), .Y(n7069) );
AOI222X1TS U7748 ( .A0(n7060), .A1(n7069), .B0(n6921), .B1(Op_MX[12]), .C0(
n7080), .C1(n7008), .Y(n6359) );
OAI21X1TS U7749 ( .A0(n7014), .A1(n6925), .B0(n6359), .Y(n6360) );
XOR2X1TS U7750 ( .A(n6360), .B(n7087), .Y(mult_x_24_n1413) );
OAI21X2TS U7751 ( .A0(n6461), .A1(n6362), .B0(n6361), .Y(n6366) );
NAND2X1TS U7752 ( .A(n6364), .B(n6363), .Y(n6365) );
BUFX3TS U7753 ( .A(n875), .Y(n7009) );
CLKBUFX2TS U7754 ( .A(Op_MX[11]), .Y(n6574) );
AOI222X1TS U7755 ( .A0(n6923), .A1(n7009), .B0(n7081), .B1(n6574), .C0(n7080), .C1(n910), .Y(n6368) );
OAI21X1TS U7756 ( .A0(n6775), .A1(n7085), .B0(n6368), .Y(n6369) );
XOR2X1TS U7757 ( .A(n6369), .B(n7087), .Y(mult_x_24_n1414) );
AOI222X1TS U7758 ( .A0(n7083), .A1(n7033), .B0(n7081), .B1(n6875), .C0(n7057), .C1(n6874), .Y(n6370) );
XOR2X1TS U7759 ( .A(n6371), .B(n7087), .Y(mult_x_24_n1419) );
AOI222X1TS U7760 ( .A0(n7083), .A1(n6868), .B0(n7081), .B1(Op_MX[5]), .C0(
n7057), .C1(n6863), .Y(n6372) );
OAI21X1TS U7761 ( .A0(n6865), .A1(n7085), .B0(n6372), .Y(n6373) );
XOR2X1TS U7762 ( .A(n6373), .B(n6882), .Y(mult_x_24_n1420) );
OAI21X1TS U7763 ( .A0(n7050), .A1(n7085), .B0(n6374), .Y(n6375) );
XOR2X1TS U7764 ( .A(n6375), .B(n6882), .Y(mult_x_24_n1421) );
NAND2X1TS U7765 ( .A(n6405), .B(n6989), .Y(n6376) );
XOR2X1TS U7766 ( .A(n6377), .B(n8392), .Y(mult_x_24_n1428) );
AOI21X1TS U7767 ( .A0(n6405), .A1(n925), .B0(n6378), .Y(n6379) );
OAI21X1TS U7768 ( .A0(n7006), .A1(n6442), .B0(n6379), .Y(n6380) );
XOR2X1TS U7769 ( .A(n6380), .B(n8392), .Y(mult_x_24_n1429) );
AOI222X1TS U7770 ( .A0(n7072), .A1(n6963), .B0(n6440), .B1(n6961), .C0(n6405), .C1(n6959), .Y(n6381) );
XOR2X1TS U7771 ( .A(n6382), .B(n836), .Y(mult_x_24_n1430) );
AOI222X1TS U7772 ( .A0(n6736), .A1(n6961), .B0(n6440), .B1(n6767), .C0(n6405), .C1(n834), .Y(n6383) );
OAI21X1TS U7773 ( .A0(n6769), .A1(n6442), .B0(n6383), .Y(n6384) );
XOR2X1TS U7774 ( .A(n6384), .B(Op_MY[23]), .Y(mult_x_24_n1431) );
AOI222X1TS U7775 ( .A0(n6736), .A1(n6767), .B0(n6440), .B1(n6701), .C0(n6405), .C1(n6484), .Y(n6385) );
OAI21X1TS U7776 ( .A0(n6703), .A1(n6442), .B0(n6385), .Y(n6386) );
XOR2X1TS U7777 ( .A(n6386), .B(Op_MY[23]), .Y(mult_x_24_n1432) );
BUFX3TS U7778 ( .A(n6551), .Y(n6922) );
AOI222X1TS U7779 ( .A0(n6736), .A1(n6701), .B0(n6440), .B1(n6922), .C0(n844),
.C1(n6952), .Y(n6387) );
XOR2X1TS U7780 ( .A(n6388), .B(n836), .Y(mult_x_24_n1433) );
INVX2TS U7781 ( .A(n6395), .Y(n6397) );
XNOR2X4TS U7782 ( .A(n6399), .B(n6398), .Y(n6400) );
INVX12TS U7783 ( .A(n6400), .Y(n6926) );
AOI222X1TS U7784 ( .A0(n6736), .A1(n6922), .B0(n6440), .B1(n6814), .C0(n844),
.C1(n879), .Y(n6401) );
OAI21X1TS U7785 ( .A0(n6926), .A1(n6442), .B0(n6401), .Y(n6402) );
OAI21X2TS U7786 ( .A0(n6850), .A1(n6442), .B0(n6403), .Y(n6404) );
XOR2X1TS U7787 ( .A(n6404), .B(n836), .Y(mult_x_24_n1435) );
AOI222X1TS U7788 ( .A0(n6736), .A1(n6846), .B0(n6440), .B1(n6830), .C0(n6405), .C1(n927), .Y(n6406) );
OAI21X1TS U7789 ( .A0(n6832), .A1(n6442), .B0(n6406), .Y(n6407) );
XOR2X1TS U7790 ( .A(n6407), .B(n8392), .Y(mult_x_24_n1436) );
AOI222X1TS U7791 ( .A0(n7072), .A1(n6830), .B0(n6440), .B1(n6929), .C0(n844),
.C1(n6559), .Y(n6408) );
XOR2X1TS U7792 ( .A(n6409), .B(n8392), .Y(mult_x_24_n1437) );
AOI222X1TS U7793 ( .A0(n6736), .A1(n6929), .B0(n7070), .B1(n6790), .C0(n6473), .C1(n6562), .Y(n6410) );
OAI21X1TS U7794 ( .A0(n6793), .A1(n7074), .B0(n6410), .Y(n6411) );
XOR2X1TS U7795 ( .A(n6411), .B(Op_MY[23]), .Y(mult_x_24_n1438) );
BUFX3TS U7796 ( .A(n6562), .Y(n6915) );
AOI222X1TS U7797 ( .A0(n7072), .A1(n6790), .B0(n7070), .B1(n6915), .C0(n6473), .C1(n6945), .Y(n6412) );
OAI21X1TS U7798 ( .A0(n6918), .A1(n7074), .B0(n6412), .Y(n6413) );
XOR2X1TS U7799 ( .A(n6413), .B(n836), .Y(mult_x_24_n1439) );
INVX2TS U7800 ( .A(n6414), .Y(n6416) );
NAND2X1TS U7801 ( .A(n6416), .B(n6415), .Y(n6417) );
AOI222X1TS U7802 ( .A0(n7072), .A1(n6915), .B0(n7070), .B1(n938), .C0(n6473),
.C1(n6785), .Y(n6418) );
OAI21X1TS U7803 ( .A0(n729), .A1(n7074), .B0(n6418), .Y(n6419) );
XOR2X1TS U7804 ( .A(n6419), .B(n8392), .Y(mult_x_24_n1440) );
INVX2TS U7805 ( .A(n6420), .Y(n6421) );
INVX2TS U7806 ( .A(n6423), .Y(n6426) );
OAI21X4TS U7807 ( .A0(n6461), .A1(n6431), .B0(n6430), .Y(n6436) );
INVX2TS U7808 ( .A(n6432), .Y(n6434) );
XNOR2X4TS U7809 ( .A(n6436), .B(n6435), .Y(n6437) );
AOI222X1TS U7810 ( .A0(n7072), .A1(n939), .B0(n7070), .B1(n7071), .C0(n6473),
.C1(n7056), .Y(n6438) );
OAI21X1TS U7811 ( .A0(n7063), .A1(n7074), .B0(n6438), .Y(n6439) );
AOI222X1TS U7812 ( .A0(n7072), .A1(n7069), .B0(n6440), .B1(n7009), .C0(n844),
.C1(n827), .Y(n6441) );
OAI21X1TS U7813 ( .A0(n7014), .A1(n6442), .B0(n6441), .Y(n6443) );
XOR2X1TS U7814 ( .A(n6443), .B(n836), .Y(mult_x_24_n1443) );
INVX2TS U7815 ( .A(n6444), .Y(n6463) );
INVX2TS U7816 ( .A(n6462), .Y(n6445) );
AOI21X1TS U7817 ( .A0(n6458), .A1(n6463), .B0(n6445), .Y(n6446) );
INVX2TS U7818 ( .A(n6448), .Y(n6450) );
BUFX3TS U7819 ( .A(n6753), .Y(n7082) );
AOI222X1TS U7820 ( .A0(n6761), .A1(n6574), .B0(n6760), .B1(n7082), .C0(n844),
.C1(n6958), .Y(n6455) );
OAI21X1TS U7821 ( .A0(n6855), .A1(n6763), .B0(n6455), .Y(n6456) );
XOR2X1TS U7822 ( .A(n6456), .B(n7076), .Y(mult_x_24_n1445) );
INVX2TS U7823 ( .A(n6457), .Y(n6460) );
INVX2TS U7824 ( .A(n6458), .Y(n6459) );
OAI21X4TS U7825 ( .A0(n6461), .A1(n6460), .B0(n6459), .Y(n6465) );
XNOR2X4TS U7826 ( .A(n6465), .B(n6464), .Y(n6466) );
AOI222X1TS U7827 ( .A0(n6761), .A1(n7082), .B0(n6760), .B1(n841), .C0(n844),
.C1(n7079), .Y(n6467) );
XOR2X1TS U7828 ( .A(n6468), .B(n7076), .Y(mult_x_24_n1446) );
AOI222X1TS U7829 ( .A0(n6761), .A1(n841), .B0(n6760), .B1(n6910), .C0(n844),
.C1(n826), .Y(n6469) );
OAI21X1TS U7830 ( .A0(n6912), .A1(n6763), .B0(n6469), .Y(n6470) );
XOR2X1TS U7831 ( .A(n6470), .B(n8392), .Y(mult_x_24_n1447) );
AOI222X1TS U7832 ( .A0(n6761), .A1(n7033), .B0(n6760), .B1(n6868), .C0(n6473), .C1(n6874), .Y(n6471) );
OAI21X1TS U7833 ( .A0(n6879), .A1(n6763), .B0(n6471), .Y(n6472) );
AOI222X1TS U7834 ( .A0(n6761), .A1(n6868), .B0(n6760), .B1(n6859), .C0(n6473), .C1(n6888), .Y(n6474) );
OAI21X1TS U7835 ( .A0(n6865), .A1(n6763), .B0(n6474), .Y(n6475) );
XOR2X1TS U7836 ( .A(n6475), .B(n7076), .Y(mult_x_24_n1450) );
AOI222X1TS U7837 ( .A0(n883), .A1(n6963), .B0(n7010), .B1(n6961), .C0(n6491),
.C1(n6959), .Y(n6476) );
OAI21X1TS U7838 ( .A0(n6967), .A1(n7013), .B0(n6476), .Y(n6477) );
INVX2TS U7839 ( .A(n1018), .Y(n6794) );
XOR2X1TS U7840 ( .A(n6477), .B(n6861), .Y(mult_x_24_n1460) );
AOI222X1TS U7841 ( .A0(n883), .A1(n926), .B0(n7010), .B1(n6767), .C0(n6491),
.C1(n834), .Y(n6478) );
OAI21X1TS U7842 ( .A0(n6769), .A1(n7013), .B0(n6478), .Y(n6479) );
XOR2X1TS U7843 ( .A(n6479), .B(n6220), .Y(mult_x_24_n1461) );
BUFX3TS U7844 ( .A(Op_MX[24]), .Y(n6756) );
AOI222X1TS U7845 ( .A0(n883), .A1(n6756), .B0(n7010), .B1(n6701), .C0(n6491),
.C1(n6484), .Y(n6480) );
OAI21X1TS U7846 ( .A0(n6703), .A1(n7013), .B0(n6480), .Y(n6481) );
XOR2X1TS U7847 ( .A(n6481), .B(n6794), .Y(mult_x_24_n1462) );
AOI222X1TS U7848 ( .A0(n883), .A1(n833), .B0(n7010), .B1(n6922), .C0(n6491),
.C1(n6952), .Y(n6482) );
OAI21X1TS U7849 ( .A0(n6778), .A1(n7013), .B0(n6482), .Y(n6483) );
BUFX3TS U7850 ( .A(n6484), .Y(n6816) );
AOI222X1TS U7851 ( .A0(n883), .A1(n6816), .B0(n7010), .B1(n6814), .C0(n6491),
.C1(n877), .Y(n6485) );
OAI21X1TS U7852 ( .A0(n6926), .A1(n7013), .B0(n6485), .Y(n6486) );
XOR2X1TS U7853 ( .A(n6486), .B(n6861), .Y(mult_x_24_n1464) );
BUFX3TS U7854 ( .A(Op_MX[21]), .Y(n6847) );
AOI222X1TS U7855 ( .A0(n883), .A1(n877), .B0(n7010), .B1(n6830), .C0(n6491),
.C1(n8403), .Y(n6489) );
OAI21X1TS U7856 ( .A0(n6832), .A1(n7013), .B0(n6489), .Y(n6490) );
XOR2X1TS U7857 ( .A(n6490), .B(n6794), .Y(mult_x_24_n1466) );
OAI21X1TS U7858 ( .A0(n6933), .A1(n6792), .B0(n6492), .Y(n6493) );
XOR2X1TS U7859 ( .A(n6493), .B(n6861), .Y(mult_x_24_n1467) );
BUFX3TS U7860 ( .A(n6562), .Y(n6894) );
XOR2X1TS U7861 ( .A(n6495), .B(n6220), .Y(mult_x_24_n1470) );
AOI222X1TS U7862 ( .A0(n7011), .A1(n937), .B0(n6834), .B1(n7071), .C0(n6867),
.C1(n7056), .Y(n6496) );
OAI21X1TS U7863 ( .A0(n7063), .A1(n6792), .B0(n6496), .Y(n6497) );
XOR2X1TS U7864 ( .A(n6497), .B(n6861), .Y(mult_x_24_n1471) );
XOR2X1TS U7865 ( .A(n6499), .B(n6794), .Y(mult_x_24_n1472) );
AOI222X1TS U7866 ( .A0(n6870), .A1(Op_MX[12]), .B0(n6869), .B1(n6574), .C0(
n5076), .C1(n6753), .Y(n6500) );
OAI21X1TS U7867 ( .A0(n6775), .A1(n6872), .B0(n6500), .Y(n6501) );
XOR2X1TS U7868 ( .A(n6501), .B(n7494), .Y(mult_x_24_n1474) );
BUFX3TS U7869 ( .A(n7008), .Y(n6853) );
AOI222X1TS U7870 ( .A0(n883), .A1(n6853), .B0(n6869), .B1(n7082), .C0(n5076),
.C1(n841), .Y(n6502) );
OAI21X1TS U7871 ( .A0(n6855), .A1(n6872), .B0(n6502), .Y(n6503) );
XOR2X1TS U7872 ( .A(n6503), .B(n7494), .Y(mult_x_24_n1475) );
BUFX3TS U7873 ( .A(n910), .Y(n6904) );
AOI222X1TS U7874 ( .A0(n883), .A1(n6904), .B0(n6869), .B1(n842), .C0(n5076),
.C1(n8413), .Y(n6504) );
XOR2X1TS U7875 ( .A(n6505), .B(n7494), .Y(mult_x_24_n1476) );
AOI222X1TS U7876 ( .A0(n883), .A1(n841), .B0(n6869), .B1(n6910), .C0(n5076),
.C1(n826), .Y(n6506) );
XOR2X1TS U7877 ( .A(n6507), .B(n7494), .Y(mult_x_24_n1477) );
AOI222X1TS U7878 ( .A0(n6870), .A1(n7046), .B0(n6834), .B1(n7044), .C0(n6867), .C1(n6584), .Y(n6508) );
OAI21X1TS U7879 ( .A0(n7050), .A1(n6872), .B0(n6508), .Y(n6509) );
XOR2X1TS U7880 ( .A(n6509), .B(n6861), .Y(mult_x_24_n1481) );
NAND2X1TS U7881 ( .A(n6960), .B(n6989), .Y(n6510) );
XOR2X1TS U7882 ( .A(n6511), .B(n893), .Y(mult_x_24_n1488) );
AOI21X1TS U7883 ( .A0(n6960), .A1(n926), .B0(n6513), .Y(n6514) );
XOR2X1TS U7884 ( .A(n6515), .B(n893), .Y(mult_x_24_n1489) );
AOI222X1TS U7885 ( .A0(n6796), .A1(n925), .B0(n6962), .B1(n6767), .C0(n6960),
.C1(n834), .Y(n6516) );
OAI21X1TS U7886 ( .A0(n6769), .A1(n6966), .B0(n6516), .Y(n6518) );
AOI222X1TS U7887 ( .A0(n6796), .A1(n6756), .B0(n6962), .B1(n6701), .C0(n6960), .C1(n6551), .Y(n6519) );
OAI21X1TS U7888 ( .A0(n6703), .A1(n6966), .B0(n6519), .Y(n6520) );
XOR2X1TS U7889 ( .A(n6520), .B(n6968), .Y(mult_x_24_n1492) );
OAI21X1TS U7890 ( .A0(n6850), .A1(n6966), .B0(n6521), .Y(n6522) );
XOR2X1TS U7891 ( .A(n6522), .B(n6968), .Y(mult_x_24_n1495) );
AOI222X1TS U7892 ( .A0(n6796), .A1(n878), .B0(n6962), .B1(n6830), .C0(n6960),
.C1(n927), .Y(n6523) );
AOI222X1TS U7893 ( .A0(n6796), .A1(Op_MX[18]), .B0(n6786), .B1(n6790), .C0(
n6805), .C1(Op_MX[16]), .Y(n6525) );
OAI21X1TS U7894 ( .A0(n6793), .A1(n6788), .B0(n6525), .Y(n6526) );
XOR2X1TS U7895 ( .A(n6526), .B(n6968), .Y(mult_x_24_n1498) );
BUFX3TS U7896 ( .A(n6559), .Y(n6928) );
AOI222X1TS U7897 ( .A0(n6964), .A1(n6928), .B0(n6786), .B1(n6915), .C0(n6531), .C1(n6945), .Y(n6527) );
OAI21X1TS U7898 ( .A0(n6918), .A1(n6788), .B0(n6527), .Y(n6528) );
XOR2X1TS U7899 ( .A(n6528), .B(n6968), .Y(mult_x_24_n1499) );
AOI222X1TS U7900 ( .A0(n6964), .A1(n939), .B0(n6786), .B1(n7071), .C0(n6531),
.C1(n7056), .Y(n6529) );
OAI21X1TS U7901 ( .A0(n7063), .A1(n6788), .B0(n6529), .Y(n6530) );
XOR2X1TS U7902 ( .A(n6530), .B(n893), .Y(mult_x_24_n1501) );
OAI21X1TS U7903 ( .A0(n7075), .A1(n6788), .B0(n6532), .Y(n6533) );
XOR2X1TS U7904 ( .A(n6533), .B(n893), .Y(mult_x_24_n1502) );
AOI222X1TS U7905 ( .A0(n6964), .A1(n6569), .B0(n6962), .B1(n7009), .C0(n6805), .C1(n7008), .Y(n6534) );
XOR2X1TS U7906 ( .A(n6535), .B(n835), .Y(mult_x_24_n1503) );
BUFX4TS U7907 ( .A(n6962), .Y(n6806) );
AOI222X1TS U7908 ( .A0(n6807), .A1(n6904), .B0(n6806), .B1(n842), .C0(n6805),
.C1(n7079), .Y(n6536) );
AOI222X1TS U7909 ( .A0(n6807), .A1(n6958), .B0(n6806), .B1(n6910), .C0(n6805), .C1(n826), .Y(n6538) );
OAI21X1TS U7910 ( .A0(n6912), .A1(n6809), .B0(n6538), .Y(n6539) );
XOR2X1TS U7911 ( .A(n6539), .B(n835), .Y(mult_x_24_n1507) );
AOI222X1TS U7912 ( .A0(n6807), .A1(n6909), .B0(n6806), .B1(n6868), .C0(n6531), .C1(n6874), .Y(n6540) );
AOI222X1TS U7913 ( .A0(n6807), .A1(n7031), .B0(n6806), .B1(n6859), .C0(n6531), .C1(n6863), .Y(n6542) );
XOR2X1TS U7914 ( .A(n6543), .B(n893), .Y(mult_x_24_n1510) );
AOI222X1TS U7915 ( .A0(n7023), .A1(n6963), .B0(n6980), .B1(n925), .C0(n6581),
.C1(n6959), .Y(n6545) );
AOI222X1TS U7916 ( .A0(n6771), .A1(n6961), .B0(n6980), .B1(Op_MX[24]), .C0(
n6982), .C1(n834), .Y(n6547) );
AOI222X1TS U7917 ( .A0(n6771), .A1(n6767), .B0(n6980), .B1(n833), .C0(n6982),
.C1(n6551), .Y(n6549) );
OAI21X1TS U7918 ( .A0(n6703), .A1(n6984), .B0(n6549), .Y(n6550) );
XOR2X1TS U7919 ( .A(n6550), .B(n6827), .Y(mult_x_24_n1522) );
AOI222X1TS U7920 ( .A0(n6771), .A1(n6701), .B0(n6980), .B1(n6551), .C0(n6581), .C1(n6952), .Y(n6552) );
XOR2X1TS U7921 ( .A(n6553), .B(n6827), .Y(mult_x_24_n1523) );
OAI21X1TS U7922 ( .A0(n6926), .A1(n6984), .B0(n6554), .Y(n6555) );
AOI222X1TS U7923 ( .A0(n6771), .A1(n6846), .B0(n6980), .B1(n6749), .C0(n6581), .C1(n6829), .Y(n6556) );
OAI21X1TS U7924 ( .A0(n6832), .A1(n6984), .B0(n6556), .Y(n6557) );
XOR2X1TS U7925 ( .A(n6557), .B(n6827), .Y(mult_x_24_n1526) );
BUFX6TS U7926 ( .A(n6558), .Y(n7021) );
AOI222X1TS U7927 ( .A0(n6771), .A1(n6929), .B0(n7021), .B1(n6559), .C0(n7019), .C1(n6562), .Y(n6560) );
OAI21X1TS U7928 ( .A0(n6793), .A1(n7025), .B0(n6560), .Y(n6561) );
XOR2X1TS U7929 ( .A(n6561), .B(n6827), .Y(mult_x_24_n1528) );
AOI222X1TS U7930 ( .A0(n7023), .A1(n6790), .B0(n7021), .B1(n6562), .C0(n7019), .C1(n6945), .Y(n6563) );
OAI21X1TS U7931 ( .A0(n6918), .A1(n7025), .B0(n6563), .Y(n6564) );
XOR2X1TS U7932 ( .A(n6564), .B(n6827), .Y(mult_x_24_n1529) );
AOI222X1TS U7933 ( .A0(n7023), .A1(n6915), .B0(n7021), .B1(n939), .C0(n7019),
.C1(n6785), .Y(n6565) );
XOR2X1TS U7934 ( .A(n6566), .B(n7027), .Y(mult_x_24_n1530) );
OAI21X1TS U7935 ( .A0(n7063), .A1(n7025), .B0(n6567), .Y(n6568) );
XOR2X1TS U7936 ( .A(n6568), .B(n7027), .Y(mult_x_24_n1531) );
OAI21X1TS U7937 ( .A0(n7075), .A1(n7025), .B0(n6570), .Y(n6571) );
XOR2X1TS U7938 ( .A(n6571), .B(n7027), .Y(mult_x_24_n1532) );
AOI222X1TS U7939 ( .A0(n7023), .A1(n7069), .B0(n6980), .B1(Op_MX[12]), .C0(
n6581), .C1(n7008), .Y(n6572) );
OAI21X1TS U7940 ( .A0(n7014), .A1(n6984), .B0(n6572), .Y(n6573) );
XOR2X1TS U7941 ( .A(n6573), .B(n7490), .Y(mult_x_24_n1533) );
AOI222X1TS U7942 ( .A0(n6771), .A1(n7009), .B0(n6876), .B1(n6574), .C0(n6581), .C1(n6753), .Y(n6575) );
OAI21X1TS U7943 ( .A0(n6775), .A1(n6899), .B0(n6575), .Y(n6576) );
XOR2X1TS U7944 ( .A(n6576), .B(n7490), .Y(mult_x_24_n1534) );
AOI222X1TS U7945 ( .A0(n6877), .A1(n827), .B0(n6876), .B1(n6753), .C0(n6581),
.C1(n6958), .Y(n6577) );
OAI21X1TS U7946 ( .A0(n6855), .A1(n6899), .B0(n6577), .Y(n6578) );
XOR2X1TS U7947 ( .A(n6578), .B(n7490), .Y(mult_x_24_n1535) );
XOR2X1TS U7948 ( .A(n6580), .B(n7490), .Y(mult_x_24_n1536) );
AOI222X1TS U7949 ( .A0(n6877), .A1(n842), .B0(n6876), .B1(n8413), .C0(n6581),
.C1(n826), .Y(n6582) );
XOR2X1TS U7950 ( .A(n6583), .B(n7490), .Y(mult_x_24_n1537) );
OAI21X1TS U7951 ( .A0(n7050), .A1(n6899), .B0(n6585), .Y(n6586) );
XOR2X1TS U7952 ( .A(n6586), .B(n7027), .Y(mult_x_24_n1541) );
BUFX6TS U7953 ( .A(n6615), .Y(n6997) );
NAND2X1TS U7954 ( .A(n6997), .B(n6989), .Y(n6587) );
OAI21X1TS U7955 ( .A0(n6993), .A1(n6841), .B0(n6587), .Y(n6588) );
XOR2X1TS U7956 ( .A(n6588), .B(n8373), .Y(mult_x_24_n1548) );
BUFX8TS U7957 ( .A(n6589), .Y(n6995) );
AOI222X1TS U7958 ( .A0(n6848), .A1(n6756), .B0(n6995), .B1(n6701), .C0(n6997), .C1(n6816), .Y(n6590) );
OAI21X1TS U7959 ( .A0(n6703), .A1(n6999), .B0(n6590), .Y(n6591) );
XOR2X1TS U7960 ( .A(n6591), .B(n6851), .Y(mult_x_24_n1552) );
AOI222X1TS U7961 ( .A0(n6848), .A1(Op_MX[23]), .B0(n6995), .B1(n6922), .C0(
n6997), .C1(n6847), .Y(n6592) );
OAI21X1TS U7962 ( .A0(n6778), .A1(n6999), .B0(n6592), .Y(n6593) );
XOR2X1TS U7963 ( .A(n6593), .B(n6851), .Y(mult_x_24_n1553) );
AOI222X1TS U7964 ( .A0(n6848), .A1(n6816), .B0(n6995), .B1(n6814), .C0(n6997), .C1(n877), .Y(n6594) );
OAI21X1TS U7965 ( .A0(n6926), .A1(n6999), .B0(n6594), .Y(n6595) );
XOR2X1TS U7966 ( .A(n6595), .B(n6851), .Y(mult_x_24_n1554) );
OAI21X1TS U7967 ( .A0(n6793), .A1(n6841), .B0(n6596), .Y(n6597) );
XOR2X1TS U7968 ( .A(n6597), .B(n6851), .Y(mult_x_24_n1558) );
XOR2X1TS U7969 ( .A(n6599), .B(n6851), .Y(mult_x_24_n1559) );
XOR2X1TS U7970 ( .A(n6601), .B(n7051), .Y(mult_x_24_n1560) );
OAI21X1TS U7971 ( .A0(n7063), .A1(n6841), .B0(n6602), .Y(n6603) );
XOR2X1TS U7972 ( .A(n6603), .B(n7051), .Y(mult_x_24_n1561) );
AOI222X1TS U7973 ( .A0(n6839), .A1(n6569), .B0(n6995), .B1(n7009), .C0(n7043), .C1(n6853), .Y(n6606) );
XOR2X1TS U7974 ( .A(n6607), .B(Op_MY[11]), .Y(mult_x_24_n1563) );
BUFX3TS U7975 ( .A(n6608), .Y(n7047) );
AOI222X1TS U7976 ( .A0(n7047), .A1(n6904), .B0(n6843), .B1(n842), .C0(n7043),
.C1(n7035), .Y(n6609) );
XOR2X1TS U7977 ( .A(n6610), .B(Op_MY[11]), .Y(mult_x_24_n1566) );
AOI222X1TS U7978 ( .A0(n7047), .A1(n841), .B0(n6843), .B1(n6910), .C0(n7043),
.C1(n6909), .Y(n6611) );
XOR2X1TS U7979 ( .A(n6612), .B(n8373), .Y(mult_x_24_n1567) );
AOI222X1TS U7980 ( .A0(n7047), .A1(n7035), .B0(n6843), .B1(n7033), .C0(n7043), .C1(n7031), .Y(n6613) );
OAI21X1TS U7981 ( .A0(n7039), .A1(n7049), .B0(n6613), .Y(n6614) );
XOR2X1TS U7982 ( .A(n6614), .B(n8373), .Y(mult_x_24_n1568) );
AOI222X1TS U7983 ( .A0(n7047), .A1(n6909), .B0(n6843), .B1(n6868), .C0(n6615), .C1(n7046), .Y(n6616) );
OAI21X1TS U7984 ( .A0(n6879), .A1(n7049), .B0(n6616), .Y(n6617) );
XOR2X1TS U7985 ( .A(n6617), .B(n8373), .Y(mult_x_24_n1569) );
AOI222X1TS U7986 ( .A0(n7047), .A1(n7031), .B0(n6843), .B1(n6859), .C0(n7043), .C1(n6888), .Y(n6618) );
XOR2X1TS U7987 ( .A(n6619), .B(n7051), .Y(mult_x_24_n1570) );
BUFX6TS U7988 ( .A(n6620), .Y(n6970) );
AOI222X1TS U7989 ( .A0(n6750), .A1(n926), .B0(n6970), .B1(n6767), .C0(n6990),
.C1(n833), .Y(n6621) );
OAI21X1TS U7990 ( .A0(n6769), .A1(n6973), .B0(n6621), .Y(n6622) );
XOR2X1TS U7991 ( .A(n6622), .B(n6758), .Y(mult_x_24_n1581) );
AOI222X1TS U7992 ( .A0(n6750), .A1(n6756), .B0(n6970), .B1(n6701), .C0(n6990), .C1(n6816), .Y(n6623) );
OAI21X1TS U7993 ( .A0(n6703), .A1(n6973), .B0(n6623), .Y(n6624) );
XOR2X1TS U7994 ( .A(n6624), .B(n6758), .Y(mult_x_24_n1582) );
AOI222X1TS U7995 ( .A0(n6750), .A1(Op_MX[23]), .B0(n6970), .B1(n6922), .C0(
n6990), .C1(n6847), .Y(n6625) );
OAI21X1TS U7996 ( .A0(n6778), .A1(n6973), .B0(n6625), .Y(n6626) );
XOR2X1TS U7997 ( .A(n6626), .B(n6758), .Y(mult_x_24_n1583) );
AOI222X1TS U7998 ( .A0(n6750), .A1(n6816), .B0(n6970), .B1(n6814), .C0(n6990), .C1(n878), .Y(n6627) );
OAI21X1TS U7999 ( .A0(n6926), .A1(n6973), .B0(n6627), .Y(n6628) );
XOR2X1TS U8000 ( .A(n6628), .B(n6758), .Y(mult_x_24_n1584) );
OAI21X1TS U8001 ( .A0(n6832), .A1(n6973), .B0(n6629), .Y(n6630) );
OAI21X1TS U8002 ( .A0(n6933), .A1(n6992), .B0(n6631), .Y(n6632) );
XOR2X1TS U8003 ( .A(n6632), .B(n6758), .Y(mult_x_24_n1587) );
AOI222X1TS U8004 ( .A0(n6750), .A1(n8403), .B0(n6887), .B1(n6790), .C0(n6885), .C1(n6894), .Y(n6633) );
OAI21X1TS U8005 ( .A0(n6793), .A1(n6992), .B0(n6633), .Y(n6634) );
XOR2X1TS U8006 ( .A(n6634), .B(n6758), .Y(mult_x_24_n1588) );
AOI222X1TS U8007 ( .A0(n6889), .A1(n6928), .B0(n6887), .B1(n6915), .C0(n6885), .C1(n939), .Y(n6635) );
OAI21X1TS U8008 ( .A0(n6918), .A1(n6992), .B0(n6635), .Y(n6636) );
XOR2X1TS U8009 ( .A(n6636), .B(n6758), .Y(mult_x_24_n1589) );
AOI222X1TS U8010 ( .A0(n6889), .A1(n939), .B0(n6887), .B1(n7071), .C0(n6885),
.C1(n6569), .Y(n6637) );
OAI21X1TS U8011 ( .A0(n7063), .A1(n6992), .B0(n6637), .Y(n6638) );
XOR2X1TS U8012 ( .A(n6638), .B(n6891), .Y(mult_x_24_n1591) );
XOR2X1TS U8013 ( .A(n6641), .B(n6891), .Y(mult_x_24_n1592) );
AOI222X1TS U8014 ( .A0(n6889), .A1(Op_MX[13]), .B0(n6970), .B1(n7009), .C0(
n7032), .C1(n6853), .Y(n6642) );
OAI21X1TS U8015 ( .A0(n7014), .A1(n6973), .B0(n6642), .Y(n6643) );
XOR2X1TS U8016 ( .A(n6643), .B(n7040), .Y(mult_x_24_n1593) );
BUFX4TS U8017 ( .A(n6970), .Y(n7034) );
OAI21X1TS U8018 ( .A0(n6775), .A1(n7038), .B0(n6645), .Y(n6646) );
XOR2X1TS U8019 ( .A(n6646), .B(n7040), .Y(mult_x_24_n1594) );
BUFX3TS U8020 ( .A(n6750), .Y(n7036) );
OAI21X1TS U8021 ( .A0(n6855), .A1(n7038), .B0(n6647), .Y(n6648) );
XOR2X1TS U8022 ( .A(n6648), .B(n7040), .Y(mult_x_24_n1595) );
AOI222X1TS U8023 ( .A0(n7036), .A1(n6904), .B0(n7034), .B1(n842), .C0(n7032),
.C1(n7035), .Y(n6649) );
XOR2X1TS U8024 ( .A(n6650), .B(n7040), .Y(mult_x_24_n1596) );
AOI222X1TS U8025 ( .A0(n7036), .A1(n6909), .B0(n7034), .B1(n6868), .C0(n6885), .C1(n7046), .Y(n6651) );
XOR2X1TS U8026 ( .A(n6652), .B(n7040), .Y(mult_x_24_n1599) );
AOI222X1TS U8027 ( .A0(n7036), .A1(n7046), .B0(n6887), .B1(n7044), .C0(n6885), .C1(n7042), .Y(n6653) );
OAI21X1TS U8028 ( .A0(n7050), .A1(n7038), .B0(n6653), .Y(n6654) );
XOR2X1TS U8029 ( .A(n6654), .B(n6891), .Y(mult_x_24_n1601) );
NAND2X1TS U8030 ( .A(n6813), .B(n6989), .Y(n6655) );
OAI21X1TS U8031 ( .A0(n6993), .A1(n6681), .B0(n6655), .Y(n6656) );
XOR2X1TS U8032 ( .A(n6656), .B(n940), .Y(mult_x_24_n1608) );
AOI21X1TS U8033 ( .A0(n6813), .A1(n926), .B0(n6657), .Y(n6658) );
OAI21X1TS U8034 ( .A0(n7006), .A1(n6819), .B0(n6658), .Y(n6659) );
XOR2X1TS U8035 ( .A(n6659), .B(n940), .Y(mult_x_24_n1609) );
OAI21X1TS U8036 ( .A0(n6967), .A1(n6819), .B0(n6660), .Y(n6661) );
XOR2X1TS U8037 ( .A(n6661), .B(n6695), .Y(mult_x_24_n1610) );
OAI21X1TS U8038 ( .A0(n6769), .A1(n6819), .B0(n6662), .Y(n6663) );
XOR2X1TS U8039 ( .A(n6663), .B(n8377), .Y(mult_x_24_n1611) );
OAI21X1TS U8040 ( .A0(n6703), .A1(n6819), .B0(n6664), .Y(n6665) );
XOR2X1TS U8041 ( .A(n6665), .B(n940), .Y(mult_x_24_n1612) );
OAI21X1TS U8042 ( .A0(n6778), .A1(n6819), .B0(n6666), .Y(n6667) );
XOR2X1TS U8043 ( .A(n6667), .B(n6820), .Y(mult_x_24_n1613) );
OAI21X1TS U8044 ( .A0(n6850), .A1(n6819), .B0(n6668), .Y(n6669) );
XOR2X1TS U8045 ( .A(n6669), .B(n8377), .Y(mult_x_24_n1615) );
AOI222X1TS U8046 ( .A0(n6683), .A1(n6749), .B0(n886), .B1(n6929), .C0(n6813),
.C1(n6928), .Y(n6670) );
OAI21X1TS U8047 ( .A0(n6933), .A1(n6681), .B0(n6670), .Y(n6671) );
OAI21X1TS U8048 ( .A0(n6793), .A1(n6681), .B0(n6672), .Y(n6673) );
XOR2X1TS U8049 ( .A(n6673), .B(n6820), .Y(mult_x_24_n1618) );
OAI21X1TS U8050 ( .A0(n6918), .A1(n6681), .B0(n6674), .Y(n6675) );
XOR2X1TS U8051 ( .A(n6675), .B(n940), .Y(mult_x_24_n1619) );
XOR2X1TS U8052 ( .A(n6677), .B(n940), .Y(mult_x_24_n1620) );
OAI21X1TS U8053 ( .A0(n7063), .A1(n6681), .B0(n6678), .Y(n6679) );
XOR2X1TS U8054 ( .A(n6679), .B(n6695), .Y(mult_x_24_n1621) );
XOR2X1TS U8055 ( .A(n6682), .B(n6695), .Y(mult_x_24_n1622) );
XOR2X1TS U8056 ( .A(n6685), .B(n6695), .Y(mult_x_24_n1623) );
AOI222X1TS U8057 ( .A0(n6905), .A1(Op_MX[9]), .B0(n6903), .B1(n6910), .C0(
n6902), .C1(n6909), .Y(n6689) );
XOR2X1TS U8058 ( .A(n6690), .B(n6820), .Y(mult_x_24_n1627) );
AOI222X1TS U8059 ( .A0(n6905), .A1(n6909), .B0(n6903), .B1(n6868), .C0(n823),
.C1(n7046), .Y(n6691) );
XOR2X1TS U8060 ( .A(n6692), .B(n940), .Y(mult_x_24_n1629) );
AOI222X1TS U8061 ( .A0(n6905), .A1(n7031), .B0(n6903), .B1(n6859), .C0(n823),
.C1(n6888), .Y(n6694) );
OAI21X1TS U8062 ( .A0(n6865), .A1(n6907), .B0(n6694), .Y(n6696) );
XOR2X1TS U8063 ( .A(n6696), .B(n6820), .Y(mult_x_24_n1630) );
AOI222X1TS U8064 ( .A0(n885), .A1(n6963), .B0(n1083), .B1(n6961), .C0(n7003),
.C1(n6756), .Y(n6697) );
AOI222X1TS U8065 ( .A0(n1047), .A1(n926), .B0(n1083), .B1(n6767), .C0(n7003),
.C1(n833), .Y(n6699) );
OAI21X1TS U8066 ( .A0(n6769), .A1(n7005), .B0(n6699), .Y(n6700) );
XOR2X1TS U8067 ( .A(n6700), .B(n8391), .Y(mult_x_24_n1641) );
AOI222X1TS U8068 ( .A0(n1047), .A1(n6756), .B0(n1083), .B1(n6701), .C0(n7003), .C1(n6816), .Y(n6702) );
OAI21X1TS U8069 ( .A0(n6703), .A1(n7005), .B0(n6702), .Y(n6704) );
XOR2X1TS U8070 ( .A(n6704), .B(n6730), .Y(mult_x_24_n1642) );
AOI222X1TS U8071 ( .A0(n885), .A1(Op_MX[23]), .B0(n1083), .B1(n6922), .C0(
n7003), .C1(n6847), .Y(n6705) );
OAI21X1TS U8072 ( .A0(n6778), .A1(n7005), .B0(n6705), .Y(n6706) );
XOR2X1TS U8073 ( .A(n6706), .B(n8391), .Y(mult_x_24_n1643) );
AOI222X1TS U8074 ( .A0(n884), .A1(n6816), .B0(n1083), .B1(n6814), .C0(n7003),
.C1(Op_MX[20]), .Y(n6707) );
OAI21X1TS U8075 ( .A0(n6926), .A1(n7005), .B0(n6707), .Y(n6708) );
XOR2X1TS U8076 ( .A(n6708), .B(n6730), .Y(mult_x_24_n1644) );
OAI21X1TS U8077 ( .A0(n6850), .A1(n7005), .B0(n6709), .Y(n6710) );
XOR2X1TS U8078 ( .A(n6710), .B(n6730), .Y(mult_x_24_n1645) );
AOI222X1TS U8079 ( .A0(n885), .A1(n879), .B0(n1083), .B1(n6830), .C0(n7003),
.C1(n927), .Y(n6711) );
OAI21X1TS U8080 ( .A0(n6832), .A1(n7005), .B0(n6711), .Y(n6712) );
AOI222X1TS U8081 ( .A0(n885), .A1(n927), .B0(n6916), .B1(n6790), .C0(n6914),
.C1(n6894), .Y(n6713) );
OAI21X1TS U8082 ( .A0(n6793), .A1(n6932), .B0(n6713), .Y(n6714) );
XOR2X1TS U8083 ( .A(n6714), .B(n8391), .Y(mult_x_24_n1648) );
AOI222X1TS U8084 ( .A0(n884), .A1(n938), .B0(n6916), .B1(n7071), .C0(n6893),
.C1(n6569), .Y(n6715) );
XOR2X1TS U8085 ( .A(n6716), .B(n8445), .Y(mult_x_24_n1651) );
OAI21X1TS U8086 ( .A0(n7075), .A1(n6932), .B0(n6717), .Y(n6718) );
XOR2X1TS U8087 ( .A(n6718), .B(n6730), .Y(mult_x_24_n1652) );
XOR2X1TS U8088 ( .A(n6720), .B(n8445), .Y(mult_x_24_n1653) );
XOR2X1TS U8089 ( .A(n6722), .B(n6730), .Y(mult_x_24_n1654) );
AOI222X1TS U8090 ( .A0(n1047), .A1(n6853), .B0(n6727), .B1(n7082), .C0(n6914), .C1(n841), .Y(n6723) );
XOR2X1TS U8091 ( .A(n6724), .B(n8445), .Y(mult_x_24_n1655) );
AOI222X1TS U8092 ( .A0(n1047), .A1(n6904), .B0(n6727), .B1(n842), .C0(n6914),
.C1(n7035), .Y(n6725) );
XOR2X1TS U8093 ( .A(n6726), .B(n6730), .Y(mult_x_24_n1656) );
XOR2X1TS U8094 ( .A(n6731), .B(n6730), .Y(mult_x_24_n1657) );
NAND2X1TS U8095 ( .A(n6733), .B(n6732), .Y(n6734) );
AOI222X1TS U8096 ( .A0(n6736), .A1(n7009), .B0(n6760), .B1(n6574), .C0(n844),
.C1(n910), .Y(n6737) );
OAI21X1TS U8097 ( .A0(n6775), .A1(n6763), .B0(n6737), .Y(n6738) );
AOI222X1TS U8098 ( .A0(n7060), .A1(n6915), .B0(n7058), .B1(n939), .C0(n7057),
.C1(n6785), .Y(n6739) );
XOR2X1TS U8099 ( .A(n6740), .B(n6882), .Y(mult_x_24_n1410) );
AOI222X1TS U8100 ( .A0(n7011), .A1(n6928), .B0(n6834), .B1(n6915), .C0(n6867), .C1(n6945), .Y(n6741) );
OAI21X1TS U8101 ( .A0(n6775), .A1(n6809), .B0(n6743), .Y(n6744) );
AOI222X1TS U8102 ( .A0(n6839), .A1(n6963), .B0(n6995), .B1(n6961), .C0(n6997), .C1(n6756), .Y(n6745) );
AOI222X1TS U8103 ( .A0(n6964), .A1(Op_MX[19]), .B0(n6962), .B1(n6929), .C0(
n6960), .C1(n6559), .Y(n6747) );
XOR2X1TS U8104 ( .A(n6748), .B(n6968), .Y(mult_x_24_n1497) );
AOI222X1TS U8105 ( .A0(n6750), .A1(n6847), .B0(n6887), .B1(n6846), .C0(n6990), .C1(n6749), .Y(n6751) );
OAI21X1TS U8106 ( .A0(n6850), .A1(n6973), .B0(n6751), .Y(n6752) );
AOI222X1TS U8107 ( .A0(n7083), .A1(n6574), .B0(n7081), .B1(n6753), .C0(n7080), .C1(n6958), .Y(n6754) );
XOR2X1TS U8108 ( .A(n6755), .B(n6882), .Y(mult_x_24_n1415) );
AOI222X1TS U8109 ( .A0(n6889), .A1(n6963), .B0(n6970), .B1(n6961), .C0(n6990), .C1(n6756), .Y(n6757) );
AOI222X1TS U8110 ( .A0(n6761), .A1(n6910), .B0(n6760), .B1(n7033), .C0(n844),
.C1(n8414), .Y(n6762) );
XOR2X1TS U8111 ( .A(n6764), .B(n836), .Y(mult_x_24_n1448) );
OAI21X1TS U8112 ( .A0(n729), .A1(n6992), .B0(n6765), .Y(n6766) );
XOR2X1TS U8113 ( .A(n6766), .B(n6891), .Y(mult_x_24_n1590) );
AOI222X1TS U8114 ( .A0(n6848), .A1(Op_MX[25]), .B0(n6995), .B1(n6767), .C0(
n6997), .C1(n833), .Y(n6768) );
OAI21X1TS U8115 ( .A0(n6850), .A1(n6984), .B0(n6772), .Y(n6773) );
OAI21X1TS U8116 ( .A0(n6775), .A1(n7049), .B0(n6774), .Y(n6776) );
XOR2X1TS U8117 ( .A(n6776), .B(n8373), .Y(mult_x_24_n1564) );
AOI222X1TS U8118 ( .A0(n6796), .A1(n834), .B0(n6962), .B1(n6922), .C0(n6960),
.C1(n6952), .Y(n6777) );
XOR2X1TS U8119 ( .A(n6779), .B(n6968), .Y(mult_x_24_n1493) );
AOI222X1TS U8120 ( .A0(n7083), .A1(n6910), .B0(n7081), .B1(n6780), .C0(n7080), .C1(n6875), .Y(n6781) );
OAI21X1TS U8121 ( .A0(n7039), .A1(n7085), .B0(n6781), .Y(n6782) );
AOI222X1TS U8122 ( .A0(n7011), .A1(n7042), .B0(n6834), .B1(n7022), .C0(n6867), .C1(n6822), .Y(n6783) );
OAI21X1TS U8123 ( .A0(n6824), .A1(n6792), .B0(n6783), .Y(n6784) );
XOR2X1TS U8124 ( .A(n6784), .B(n6220), .Y(mult_x_24_n1483) );
AOI222X1TS U8125 ( .A0(n6964), .A1(n6894), .B0(n6786), .B1(n937), .C0(n6531),
.C1(n6785), .Y(n6787) );
OAI21X1TS U8126 ( .A0(n729), .A1(n6788), .B0(n6787), .Y(n6789) );
XOR2X1TS U8127 ( .A(n6789), .B(n893), .Y(mult_x_24_n1500) );
XOR2X1TS U8128 ( .A(n6795), .B(n6794), .Y(mult_x_24_n1468) );
AOI222X1TS U8129 ( .A0(n6796), .A1(n6816), .B0(n6962), .B1(n6814), .C0(n6960), .C1(n879), .Y(n6797) );
XOR2X1TS U8130 ( .A(n6798), .B(n6968), .Y(mult_x_24_n1494) );
AOI222X1TS U8131 ( .A0(n6807), .A1(n7035), .B0(n6806), .B1(n7033), .C0(n6805), .C1(n6875), .Y(n6799) );
AOI222X1TS U8132 ( .A0(n7060), .A1(n6886), .B0(n7058), .B1(n8402), .C0(n7057), .C1(n6822), .Y(n6801) );
OAI21X1TS U8133 ( .A0(n6824), .A1(n7062), .B0(n6801), .Y(n6802) );
XOR2X1TS U8134 ( .A(n6802), .B(n7064), .Y(mult_x_24_n1423) );
NAND2X1TS U8135 ( .A(n7003), .B(n7001), .Y(n6803) );
OAI21X1TS U8136 ( .A0(n6993), .A1(n6932), .B0(n6803), .Y(n6804) );
XOR2X1TS U8137 ( .A(n6804), .B(n6934), .Y(mult_x_24_n1638) );
AOI222X1TS U8138 ( .A0(n6807), .A1(n6853), .B0(n6806), .B1(n7082), .C0(n6805), .C1(n6958), .Y(n6808) );
OAI21X1TS U8139 ( .A0(n6855), .A1(n6809), .B0(n6808), .Y(n6810) );
XOR2X1TS U8140 ( .A(n6810), .B(n835), .Y(mult_x_24_n1505) );
AOI222X1TS U8141 ( .A0(n7023), .A1(n6886), .B0(n7021), .B1(n8402), .C0(n7019), .C1(n7020), .Y(n6811) );
OAI21X1TS U8142 ( .A0(n6824), .A1(n7025), .B0(n6811), .Y(n6812) );
XOR2X1TS U8143 ( .A(n6812), .B(n7027), .Y(mult_x_24_n1543) );
AOI222X1TS U8144 ( .A0(n6817), .A1(n6816), .B0(n887), .B1(n6814), .C0(n6813),
.C1(n877), .Y(n6818) );
OAI21X1TS U8145 ( .A0(n6926), .A1(n6819), .B0(n6818), .Y(n6821) );
AOI222X1TS U8146 ( .A0(n6889), .A1(n7042), .B0(n6887), .B1(n7022), .C0(n6885), .C1(n6822), .Y(n6823) );
OAI21X1TS U8147 ( .A0(n6824), .A1(n6992), .B0(n6823), .Y(n6825) );
XOR2X1TS U8148 ( .A(n6825), .B(n6891), .Y(mult_x_24_n1603) );
AOI222X1TS U8149 ( .A0(n7023), .A1(n6830), .B0(n6980), .B1(n8403), .C0(n6982), .C1(n6559), .Y(n6826) );
OAI21X1TS U8150 ( .A0(n6933), .A1(n7025), .B0(n6826), .Y(n6828) );
XOR2X1TS U8151 ( .A(n6828), .B(n6827), .Y(mult_x_24_n1527) );
AOI222X1TS U8152 ( .A0(n6848), .A1(n878), .B0(n6995), .B1(n6830), .C0(n6997),
.C1(n8403), .Y(n6831) );
OAI21X1TS U8153 ( .A0(n6832), .A1(n6999), .B0(n6831), .Y(n6833) );
XOR2X1TS U8154 ( .A(n6833), .B(n6851), .Y(mult_x_24_n1556) );
AOI222X1TS U8155 ( .A0(n7011), .A1(n6888), .B0(n6834), .B1(n6886), .C0(n6867), .C1(n6897), .Y(n6835) );
OAI21X1TS U8156 ( .A0(n6900), .A1(n6872), .B0(n6835), .Y(n6836) );
XOR2X1TS U8157 ( .A(n6836), .B(n6220), .Y(mult_x_24_n1482) );
AOI222X1TS U8158 ( .A0(n6905), .A1(n7035), .B0(n6903), .B1(n7033), .C0(n6902), .C1(n7031), .Y(n6837) );
OAI21X1TS U8159 ( .A0(n6933), .A1(n6841), .B0(n6840), .Y(n6842) );
XOR2X1TS U8160 ( .A(n6842), .B(n6851), .Y(mult_x_24_n1557) );
AOI222X1TS U8161 ( .A0(n7047), .A1(n6853), .B0(n6843), .B1(n7082), .C0(n7043), .C1(n842), .Y(n6844) );
OAI21X1TS U8162 ( .A0(n6855), .A1(n7049), .B0(n6844), .Y(n6845) );
XOR2X1TS U8163 ( .A(n6845), .B(n8373), .Y(mult_x_24_n1565) );
OAI21X1TS U8164 ( .A0(n6850), .A1(n6999), .B0(n6849), .Y(n6852) );
XOR2X1TS U8165 ( .A(n6852), .B(n6851), .Y(mult_x_24_n1555) );
AOI222X1TS U8166 ( .A0(n6905), .A1(n6853), .B0(n6903), .B1(n7082), .C0(n6902), .C1(n841), .Y(n6854) );
AOI222X1TS U8167 ( .A0(n7036), .A1(n7031), .B0(n7034), .B1(n6859), .C0(n6885), .C1(n6888), .Y(n6857) );
XOR2X1TS U8168 ( .A(n6858), .B(n6891), .Y(mult_x_24_n1600) );
AOI222X1TS U8169 ( .A0(n6870), .A1(n7031), .B0(n6869), .B1(n6859), .C0(n6867), .C1(n6863), .Y(n6860) );
OAI21X1TS U8170 ( .A0(n6865), .A1(n6872), .B0(n6860), .Y(n6862) );
XOR2X1TS U8171 ( .A(n6862), .B(n6794), .Y(mult_x_24_n1480) );
AOI222X1TS U8172 ( .A0(n6877), .A1(n6868), .B0(n6876), .B1(Op_MX[5]), .C0(
n7019), .C1(n6863), .Y(n6864) );
OAI21X1TS U8173 ( .A0(n6865), .A1(n6899), .B0(n6864), .Y(n6866) );
XOR2X1TS U8174 ( .A(n6866), .B(n7027), .Y(mult_x_24_n1540) );
AOI222X1TS U8175 ( .A0(n6870), .A1(n6909), .B0(n6869), .B1(n6868), .C0(n6867), .C1(n6874), .Y(n6871) );
XOR2X1TS U8176 ( .A(n6873), .B(n7494), .Y(mult_x_24_n1479) );
AOI222X1TS U8177 ( .A0(n6877), .A1(n7033), .B0(n6876), .B1(n6875), .C0(n7019), .C1(n6874), .Y(n6878) );
OAI21X1TS U8178 ( .A0(n6900), .A1(n7085), .B0(n6881), .Y(n6883) );
XOR2X1TS U8179 ( .A(n6883), .B(n6882), .Y(mult_x_24_n1422) );
AOI222X1TS U8180 ( .A0(n6889), .A1(n6888), .B0(n6887), .B1(n6886), .C0(n6885), .C1(n6884), .Y(n6890) );
OAI21X1TS U8181 ( .A0(n6900), .A1(n7038), .B0(n6890), .Y(n6892) );
XOR2X1TS U8182 ( .A(n6892), .B(n6891), .Y(mult_x_24_n1602) );
AOI222X1TS U8183 ( .A0(n885), .A1(n6894), .B0(n6916), .B1(n937), .C0(n6893),
.C1(n8412), .Y(n6895) );
XOR2X1TS U8184 ( .A(n6896), .B(n8445), .Y(mult_x_24_n1650) );
OAI21X1TS U8185 ( .A0(n6900), .A1(n6899), .B0(n6898), .Y(n6901) );
XOR2X1TS U8186 ( .A(n6901), .B(n7027), .Y(mult_x_24_n1542) );
AOI222X1TS U8187 ( .A0(n6905), .A1(n6904), .B0(n6903), .B1(n842), .C0(n6902),
.C1(n7035), .Y(n6906) );
XOR2X1TS U8188 ( .A(n6908), .B(n6820), .Y(mult_x_24_n1626) );
AOI222X1TS U8189 ( .A0(n7036), .A1(n841), .B0(n7034), .B1(n6910), .C0(n7032),
.C1(n6909), .Y(n6911) );
OAI21X1TS U8190 ( .A0(n6912), .A1(n7038), .B0(n6911), .Y(n6913) );
XOR2X1TS U8191 ( .A(n6913), .B(n7040), .Y(mult_x_24_n1597) );
AOI222X1TS U8192 ( .A0(n884), .A1(n6928), .B0(n6916), .B1(n6915), .C0(n6914),
.C1(n939), .Y(n6917) );
XOR2X1TS U8193 ( .A(n6919), .B(n8391), .Y(mult_x_24_n1649) );
OAI21X1TS U8194 ( .A0(n6926), .A1(n6925), .B0(n6924), .Y(n6927) );
XOR2X1TS U8195 ( .A(n6927), .B(n7087), .Y(mult_x_24_n1404) );
OAI21X1TS U8196 ( .A0(n6933), .A1(n6932), .B0(n6931), .Y(n6935) );
XOR2X1TS U8197 ( .A(n6935), .B(n8391), .Y(mult_x_24_n1647) );
CMPR32X2TS U8198 ( .A(n6974), .B(n6937), .C(n6936), .CO(mult_x_24_n805), .S(
mult_x_24_n806) );
ADDHX1TS U8199 ( .A(n6939), .B(n6938), .CO(mult_x_24_n914), .S(n4759) );
ADDHX1TS U8200 ( .A(n8373), .B(n6941), .CO(n5032), .S(mult_x_24_n1064) );
ADDHX1TS U8201 ( .A(n7076), .B(n6942), .CO(n5207), .S(mult_x_24_n974) );
INVX2TS U8202 ( .A(mult_x_24_n1094), .Y(mult_x_24_n740) );
INVX2TS U8203 ( .A(n6947), .Y(n6949) );
NAND2X1TS U8204 ( .A(n6949), .B(n6948), .Y(n6950) );
INVX2TS U8205 ( .A(mult_x_24_n1088), .Y(mult_x_24_n703) );
INVX2TS U8206 ( .A(n6953), .Y(n6955) );
NAND2X1TS U8207 ( .A(n6955), .B(n6954), .Y(n6956) );
INVX2TS U8208 ( .A(mult_x_24_n1100), .Y(mult_x_24_n795) );
AOI222X1TS U8209 ( .A0(n6964), .A1(n6963), .B0(n6962), .B1(n6961), .C0(n6960), .C1(n6959), .Y(n6965) );
OAI21X1TS U8210 ( .A0(n6967), .A1(n6966), .B0(n6965), .Y(n6969) );
AOI21X1TS U8211 ( .A0(n6990), .A1(n926), .B0(n6971), .Y(n6972) );
XOR2X1TS U8212 ( .A(n6975), .B(n8378), .Y(mult_x_24_n1579) );
INVX2TS U8213 ( .A(n7097), .Y(n6977) );
AND2X2TS U8214 ( .A(n6980), .B(n7001), .Y(n6981) );
AOI21X1TS U8215 ( .A0(n6982), .A1(n925), .B0(n6981), .Y(n6983) );
OAI21X2TS U8216 ( .A0(n7006), .A1(n6984), .B0(n6983), .Y(n6985) );
XOR2X1TS U8217 ( .A(n6985), .B(Op_MY[14]), .Y(mult_x_24_n1519) );
ADDFHX1TS U8218 ( .A(n6988), .B(n6987), .CI(n6986), .CO(n5053), .S(
mult_x_24_n1047) );
NAND2X1TS U8219 ( .A(n6990), .B(n6989), .Y(n6991) );
OAI21X1TS U8220 ( .A0(n6993), .A1(n6992), .B0(n6991), .Y(n6994) );
AOI21X1TS U8221 ( .A0(n6997), .A1(Op_MX[25]), .B0(n6996), .Y(n6998) );
AOI21X1TS U8222 ( .A0(n7003), .A1(Op_MX[25]), .B0(n7002), .Y(n7004) );
OAI21X1TS U8223 ( .A0(n7006), .A1(n7005), .B0(n7004), .Y(n7007) );
XOR2X1TS U8224 ( .A(n7007), .B(n8391), .Y(mult_x_24_n1639) );
AOI222X1TS U8225 ( .A0(n7011), .A1(n6569), .B0(n7010), .B1(n7009), .C0(n5076), .C1(n827), .Y(n7012) );
XOR2X2TS U8226 ( .A(n7015), .B(n7494), .Y(mult_x_24_n1473) );
AOI222X1TS U8227 ( .A0(n7023), .A1(n7022), .B0(n7021), .B1(n7020), .C0(n7019), .C1(n7018), .Y(n7024) );
OAI21X1TS U8228 ( .A0(n7026), .A1(n7025), .B0(n7024), .Y(n7028) );
XOR2X1TS U8229 ( .A(n7028), .B(n7027), .Y(n7029) );
CMPR22X2TS U8230 ( .A(n7030), .B(n7029), .CO(mult_x_24_n1034), .S(n7055) );
AOI222X1TS U8231 ( .A0(n7036), .A1(n7035), .B0(n7034), .B1(n7033), .C0(n7032), .C1(n7031), .Y(n7037) );
OAI21X1TS U8232 ( .A0(n7039), .A1(n7038), .B0(n7037), .Y(n7041) );
XOR2X1TS U8233 ( .A(n7041), .B(n7040), .Y(n7054) );
OAI21X1TS U8234 ( .A0(n7050), .A1(n7049), .B0(n7048), .Y(n7052) );
XOR2X1TS U8235 ( .A(n7052), .B(n7051), .Y(n7053) );
OAI21X1TS U8236 ( .A0(n7075), .A1(n7074), .B0(n7073), .Y(n7077) );
XOR2X1TS U8237 ( .A(n7088), .B(n7087), .Y(n7089) );
ADDFHX1TS U8238 ( .A(n7091), .B(n7090), .CI(n7089), .CO(mult_x_24_n816), .S(
mult_x_24_n817) );
ADDHX1TS U8239 ( .A(n7093), .B(n7092), .CO(n5135), .S(mult_x_24_n1012) );
INVX2TS U8240 ( .A(n7094), .Y(n7095) );
INVX2TS U8241 ( .A(n6976), .Y(n7098) );
OAI21X1TS U8242 ( .A0(n7098), .A1(n7097), .B0(n7096), .Y(n7099) );
INVX2TS U8243 ( .A(n7101), .Y(n7103) );
NAND2X1TS U8244 ( .A(n7110), .B(n7109), .Y(n7111) );
NOR3BX1TS U8245 ( .AN(Op_MY[62]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n7113) );
XOR2X1TS U8246 ( .A(n904), .B(n7113), .Y(DP_OP_36J24_124_1029_n18) );
OAI2BB1X1TS U8247 ( .A0N(Op_MY[61]), .A1N(n8536), .B0(n1037), .Y(n7114) );
XOR2X1TS U8248 ( .A(n8366), .B(n7114), .Y(DP_OP_36J24_124_1029_n19) );
OAI2BB1X1TS U8249 ( .A0N(Op_MY[60]), .A1N(n8536), .B0(n1037), .Y(n7115) );
XOR2X1TS U8250 ( .A(n904), .B(n7115), .Y(DP_OP_36J24_124_1029_n20) );
OAI2BB1X1TS U8251 ( .A0N(Op_MY[59]), .A1N(n8536), .B0(n1037), .Y(n7116) );
XOR2X1TS U8252 ( .A(n8366), .B(n7116), .Y(DP_OP_36J24_124_1029_n21) );
OAI2BB1X1TS U8253 ( .A0N(Op_MY[58]), .A1N(n8536), .B0(n1037), .Y(n7117) );
XOR2X1TS U8254 ( .A(n904), .B(n7117), .Y(DP_OP_36J24_124_1029_n22) );
OAI2BB1X1TS U8255 ( .A0N(Op_MY[57]), .A1N(n8536), .B0(n1037), .Y(n7118) );
XOR2X1TS U8256 ( .A(n8366), .B(n7118), .Y(DP_OP_36J24_124_1029_n23) );
OAI2BB1X1TS U8257 ( .A0N(Op_MY[56]), .A1N(n8536), .B0(n1037), .Y(n7119) );
XOR2X1TS U8258 ( .A(n904), .B(n7119), .Y(DP_OP_36J24_124_1029_n24) );
OAI2BB1X1TS U8259 ( .A0N(Op_MY[55]), .A1N(n8536), .B0(n1037), .Y(n7120) );
XOR2X1TS U8260 ( .A(n8366), .B(n7120), .Y(DP_OP_36J24_124_1029_n25) );
OAI2BB1X1TS U8261 ( .A0N(Op_MY[54]), .A1N(n8536), .B0(n1037), .Y(n7121) );
XOR2X1TS U8262 ( .A(n904), .B(n7121), .Y(DP_OP_36J24_124_1029_n26) );
OAI2BB1X1TS U8263 ( .A0N(Op_MY[53]), .A1N(n8536), .B0(n1037), .Y(n7122) );
XOR2X1TS U8264 ( .A(n8366), .B(n7122), .Y(DP_OP_36J24_124_1029_n27) );
INVX2TS U8265 ( .A(n7368), .Y(n7125) );
NAND2X1TS U8266 ( .A(n7125), .B(n7124), .Y(n7126) );
INVX2TS U8267 ( .A(n7128), .Y(n7268) );
NAND2X1TS U8268 ( .A(n7268), .B(n7129), .Y(n7130) );
XNOR2X1TS U8269 ( .A(n7436), .B(n7130), .Y(Sgf_operation_ODD1_middle_N24) );
INVX2TS U8270 ( .A(n7142), .Y(n7132) );
NAND2X1TS U8271 ( .A(n7132), .B(n7143), .Y(n7137) );
AOI21X1TS U8272 ( .A0(n7135), .A1(n7143), .B0(n7134), .Y(n7136) );
NAND2X1TS U8273 ( .A(n7139), .B(n7138), .Y(n7140) );
XNOR2X1TS U8274 ( .A(n7141), .B(n7140), .Y(Sgf_operation_ODD1_middle_N23) );
NAND2X1TS U8275 ( .A(n7144), .B(n7143), .Y(n7145) );
XNOR2X1TS U8276 ( .A(n7146), .B(n7145), .Y(Sgf_operation_ODD1_middle_N22) );
XNOR2X1TS U8277 ( .A(n7150), .B(n7149), .Y(Sgf_operation_ODD1_middle_N21) );
NAND2X1TS U8278 ( .A(n7152), .B(n7151), .Y(n7153) );
INVX2TS U8279 ( .A(n7157), .Y(n7387) );
NAND2X1TS U8280 ( .A(n7387), .B(n7385), .Y(n7158) );
XNOR2X1TS U8281 ( .A(n7156), .B(n7158), .Y(Sgf_operation_ODD1_middle_N16) );
INVX2TS U8282 ( .A(n7163), .Y(n7165) );
NAND2X1TS U8283 ( .A(n7165), .B(n7164), .Y(n7166) );
XNOR2X1TS U8284 ( .A(n7167), .B(n7166), .Y(Sgf_operation_ODD1_middle_N15) );
NAND2X1TS U8285 ( .A(n7170), .B(n7169), .Y(n7171) );
XNOR2X1TS U8286 ( .A(n7172), .B(n7171), .Y(Sgf_operation_ODD1_middle_N14) );
NAND2X1TS U8287 ( .A(n7174), .B(n7173), .Y(n7175) );
INVX2TS U8288 ( .A(n7176), .Y(n7183) );
AOI21X1TS U8289 ( .A0(n7183), .A1(n734), .B0(n7177), .Y(n7180) );
NAND2X1TS U8290 ( .A(n789), .B(n7178), .Y(n7179) );
NAND2X1TS U8291 ( .A(n7181), .B(n734), .Y(n7182) );
XNOR2X1TS U8292 ( .A(n7183), .B(n7182), .Y(Sgf_operation_ODD1_middle_N11) );
INVX2TS U8293 ( .A(n7184), .Y(n7230) );
INVX2TS U8294 ( .A(n7185), .Y(n7187) );
NAND2X1TS U8295 ( .A(n7187), .B(n7186), .Y(n7188) );
XNOR2X1TS U8296 ( .A(n7189), .B(n7188), .Y(Sgf_operation_ODD1_middle_N10) );
INVX2TS U8297 ( .A(n7190), .Y(n7199) );
INVX2TS U8298 ( .A(n7196), .Y(n7191) );
AOI21X1TS U8299 ( .A0(n7199), .A1(n7197), .B0(n7191), .Y(n7195) );
NAND2X1TS U8300 ( .A(n7193), .B(n7192), .Y(n7194) );
NAND2X1TS U8301 ( .A(n7197), .B(n7196), .Y(n7198) );
XNOR2X1TS U8302 ( .A(n7199), .B(n7198), .Y(Sgf_operation_ODD1_middle_N7) );
NAND2X1TS U8303 ( .A(n7201), .B(n7200), .Y(n7203) );
XNOR2X1TS U8304 ( .A(n7203), .B(n7202), .Y(Sgf_operation_ODD1_middle_N6) );
INVX2TS U8305 ( .A(n7204), .Y(n7206) );
NAND2X1TS U8306 ( .A(n7206), .B(n7205), .Y(n7208) );
NAND2X1TS U8307 ( .A(n7210), .B(n7209), .Y(n7212) );
XNOR2X1TS U8308 ( .A(n7212), .B(n7211), .Y(Sgf_operation_ODD1_middle_N4) );
INVX2TS U8309 ( .A(n7213), .Y(n7215) );
NAND2X1TS U8310 ( .A(n7215), .B(n7214), .Y(n7216) );
NAND2X1TS U8311 ( .A(n7219), .B(n7218), .Y(n7221) );
XNOR2X1TS U8312 ( .A(n7221), .B(n7220), .Y(Sgf_operation_ODD1_middle_N2) );
INVX2TS U8313 ( .A(n7226), .Y(n7228) );
NAND2X1TS U8314 ( .A(n7228), .B(n7227), .Y(n7229) );
NOR2BX1TS U8315 ( .AN(n929), .B(n7231), .Y(Sgf_operation_ODD1_middle_N0) );
INVX2TS U8316 ( .A(n7396), .Y(n7234) );
INVX2TS U8317 ( .A(n7239), .Y(n7241) );
AOI21X2TS U8318 ( .A0(n7360), .A1(n7352), .B0(n7245), .Y(n7246) );
BUFX3TS U8319 ( .A(n7248), .Y(n7356) );
INVX2TS U8320 ( .A(n7356), .Y(n7249) );
INVX2TS U8321 ( .A(n7373), .Y(n7253) );
INVX2TS U8322 ( .A(n7251), .Y(n7252) );
INVX2TS U8323 ( .A(n7435), .Y(n7257) );
INVX2TS U8324 ( .A(n7258), .Y(n7259) );
OAI21X1TS U8325 ( .A0(n7259), .A1(n7437), .B0(n7438), .Y(n7260) );
INVX2TS U8326 ( .A(n7262), .Y(n7264) );
INVX2TS U8327 ( .A(n7129), .Y(n7267) );
INVX2TS U8328 ( .A(n7269), .Y(n7271) );
XNOR2X4TS U8329 ( .A(n7277), .B(n7276), .Y(Sgf_operation_ODD1_middle_N45) );
INVX2TS U8330 ( .A(n7288), .Y(n7279) );
AOI21X2TS U8331 ( .A0(n7360), .A1(n7289), .B0(n7279), .Y(n7280) );
INVX2TS U8332 ( .A(n7282), .Y(n7284) );
NAND2X2TS U8333 ( .A(n7323), .B(n7297), .Y(n7299) );
OAI21X2TS U8334 ( .A0(n7295), .A1(n7294), .B0(n7293), .Y(n7296) );
INVX2TS U8335 ( .A(n7300), .Y(n7302) );
NAND2X2TS U8336 ( .A(n7323), .B(n7308), .Y(n7310) );
INVX2TS U8337 ( .A(n7306), .Y(n7307) );
NAND2X1TS U8338 ( .A(n7312), .B(n7311), .Y(n7313) );
XNOR2X4TS U8339 ( .A(n7314), .B(n7313), .Y(Sgf_operation_ODD1_middle_N52) );
INVX2TS U8340 ( .A(n7315), .Y(n7318) );
INVX2TS U8341 ( .A(n7316), .Y(n7317) );
INVX4TS U8342 ( .A(n5108), .Y(n7427) );
INVX2TS U8343 ( .A(n7345), .Y(n7415) );
INVX2TS U8344 ( .A(n7335), .Y(n7338) );
INVX2TS U8345 ( .A(n7336), .Y(n7337) );
INVX4TS U8346 ( .A(n7343), .Y(n7416) );
INVX2TS U8347 ( .A(n7352), .Y(n7353) );
NAND2X2TS U8348 ( .A(n7359), .B(n7354), .Y(n7362) );
INVX2TS U8349 ( .A(n7245), .Y(n7357) );
INVX2TS U8350 ( .A(n7363), .Y(n7365) );
INVX2TS U8351 ( .A(n2915), .Y(n7370) );
INVX2TS U8352 ( .A(n7374), .Y(n7375) );
AOI21X1TS U8353 ( .A0(n7376), .A1(n7251), .B0(n7375), .Y(n7377) );
INVX2TS U8354 ( .A(n7380), .Y(n7382) );
INVX2TS U8355 ( .A(n7385), .Y(n7386) );
INVX2TS U8356 ( .A(n7388), .Y(n7390) );
INVX2TS U8357 ( .A(n7393), .Y(n7394) );
INVX2TS U8358 ( .A(n7233), .Y(n7397) );
INVX2TS U8359 ( .A(n7400), .Y(n7402) );
INVX2TS U8360 ( .A(n7405), .Y(n7406) );
INVX2TS U8361 ( .A(n7410), .Y(n7412) );
NAND2X2TS U8362 ( .A(n7415), .B(n1016), .Y(n7423) );
NOR2X4TS U8363 ( .A(n7416), .B(n7423), .Y(n7426) );
INVX2TS U8364 ( .A(n7419), .Y(n7420) );
AOI21X1TS U8365 ( .A0(n1016), .A1(n7421), .B0(n7420), .Y(n7422) );
INVX2TS U8366 ( .A(n7437), .Y(n7439) );
NAND3X2TS U8367 ( .A(n7485), .B(n8470), .C(n1036), .Y(n7471) );
CLKBUFX2TS U8368 ( .A(n8535), .Y(n8534) );
CLKXOR2X2TS U8369 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n7475) );
NOR4X1TS U8370 ( .A(P_Sgf[0]), .B(P_Sgf[1]), .C(P_Sgf[2]), .D(P_Sgf[3]), .Y(
n7457) );
NOR4X1TS U8371 ( .A(P_Sgf[4]), .B(P_Sgf[5]), .C(P_Sgf[6]), .D(P_Sgf[7]), .Y(
n7456) );
NOR4X1TS U8372 ( .A(P_Sgf[51]), .B(P_Sgf[49]), .C(P_Sgf[48]), .D(P_Sgf[50]),
.Y(n7455) );
OR4X2TS U8373 ( .A(P_Sgf[47]), .B(P_Sgf[45]), .C(P_Sgf[46]), .D(P_Sgf[44]),
.Y(n7453) );
OR4X2TS U8374 ( .A(P_Sgf[41]), .B(P_Sgf[42]), .C(P_Sgf[43]), .D(P_Sgf[40]),
.Y(n7452) );
NOR4X1TS U8375 ( .A(P_Sgf[8]), .B(P_Sgf[9]), .C(P_Sgf[10]), .D(P_Sgf[11]),
.Y(n7445) );
NOR4X1TS U8376 ( .A(P_Sgf[12]), .B(P_Sgf[13]), .C(P_Sgf[14]), .D(P_Sgf[15]),
.Y(n7444) );
NOR4X1TS U8377 ( .A(P_Sgf[16]), .B(P_Sgf[17]), .C(P_Sgf[18]), .D(P_Sgf[19]),
.Y(n7443) );
NOR4X1TS U8378 ( .A(P_Sgf[20]), .B(P_Sgf[21]), .C(P_Sgf[22]), .D(P_Sgf[23]),
.Y(n7442) );
NAND4XLTS U8379 ( .A(n7445), .B(n7444), .C(n7443), .D(n7442), .Y(n7451) );
NOR4X1TS U8380 ( .A(P_Sgf[24]), .B(P_Sgf[25]), .C(P_Sgf[26]), .D(P_Sgf[27]),
.Y(n7449) );
NOR4X1TS U8381 ( .A(P_Sgf[28]), .B(P_Sgf[29]), .C(P_Sgf[30]), .D(P_Sgf[31]),
.Y(n7448) );
NOR4X1TS U8382 ( .A(P_Sgf[32]), .B(P_Sgf[33]), .C(P_Sgf[34]), .D(P_Sgf[35]),
.Y(n7447) );
NOR4X1TS U8383 ( .A(P_Sgf[36]), .B(P_Sgf[37]), .C(P_Sgf[38]), .D(P_Sgf[39]),
.Y(n7446) );
NAND4XLTS U8384 ( .A(n7449), .B(n7448), .C(n7447), .D(n7446), .Y(n7450) );
NOR4X1TS U8385 ( .A(n7453), .B(n7452), .C(n7451), .D(n7450), .Y(n7454) );
MXI2X1TS U8386 ( .A(n7475), .B(round_mode[1]), .S0(round_mode[0]), .Y(n7458)
);
OAI211X1TS U8387 ( .A0(n7475), .A1(round_mode[1]), .B0(n7459), .C0(n7458),
.Y(n7484) );
INVX2TS U8388 ( .A(rst), .Y(n7460) );
BUFX3TS U8389 ( .A(n7460), .Y(n8495) );
CLKBUFX2TS U8390 ( .A(n7460), .Y(n7464) );
BUFX3TS U8391 ( .A(n7464), .Y(n8494) );
BUFX3TS U8392 ( .A(n7460), .Y(n8493) );
BUFX3TS U8393 ( .A(n7460), .Y(n8492) );
BUFX3TS U8394 ( .A(n7464), .Y(n8498) );
BUFX3TS U8395 ( .A(n7460), .Y(n8499) );
BUFX3TS U8396 ( .A(n7460), .Y(n8500) );
BUFX3TS U8397 ( .A(n7464), .Y(n8501) );
CLKBUFX2TS U8398 ( .A(n7471), .Y(n7461) );
BUFX3TS U8399 ( .A(n7461), .Y(n8512) );
BUFX3TS U8400 ( .A(n7465), .Y(n8513) );
BUFX3TS U8401 ( .A(n8505), .Y(n8514) );
BUFX3TS U8402 ( .A(n8506), .Y(n8509) );
BUFX3TS U8403 ( .A(n8505), .Y(n8508) );
BUFX3TS U8404 ( .A(n7462), .Y(n8510) );
CLKBUFX2TS U8405 ( .A(n7471), .Y(n7463) );
BUFX3TS U8406 ( .A(n7461), .Y(n8515) );
BUFX3TS U8407 ( .A(n7465), .Y(n8516) );
BUFX3TS U8408 ( .A(n8506), .Y(n8517) );
BUFX3TS U8409 ( .A(n7463), .Y(n8511) );
CLKBUFX2TS U8410 ( .A(n7471), .Y(n7462) );
BUFX3TS U8411 ( .A(n8505), .Y(n8507) );
CLKBUFX2TS U8412 ( .A(n7471), .Y(n7465) );
BUFX3TS U8413 ( .A(n7463), .Y(n8504) );
BUFX3TS U8414 ( .A(n7464), .Y(n8496) );
BUFX3TS U8415 ( .A(n7461), .Y(n8527) );
BUFX3TS U8416 ( .A(n8506), .Y(n8525) );
BUFX3TS U8417 ( .A(n7462), .Y(n8524) );
BUFX3TS U8418 ( .A(n7463), .Y(n8523) );
BUFX3TS U8419 ( .A(n7461), .Y(n8522) );
BUFX3TS U8420 ( .A(n7465), .Y(n8521) );
BUFX3TS U8421 ( .A(n7462), .Y(n8520) );
BUFX3TS U8422 ( .A(n7463), .Y(n8519) );
BUFX3TS U8423 ( .A(n8505), .Y(n8526) );
BUFX3TS U8424 ( .A(n7461), .Y(n8503) );
BUFX3TS U8425 ( .A(n7465), .Y(n8518) );
BUFX3TS U8426 ( .A(n7464), .Y(n8502) );
BUFX3TS U8427 ( .A(n7464), .Y(n8497) );
BUFX3TS U8428 ( .A(n7465), .Y(n8528) );
BUFX3TS U8429 ( .A(n8505), .Y(n8529) );
BUFX3TS U8430 ( .A(n8506), .Y(n8532) );
BUFX3TS U8431 ( .A(n7462), .Y(n8530) );
BUFX3TS U8432 ( .A(n7463), .Y(n8531) );
NOR2XLTS U8433 ( .A(n8446), .B(FS_Module_state_reg[3]), .Y(n7467) );
NOR2XLTS U8434 ( .A(n8447), .B(n7535), .Y(n7466) );
NAND2X1TS U8435 ( .A(n7467), .B(n7466), .Y(n8368) );
INVX2TS U8436 ( .A(n8430), .Y(n8427) );
NAND2X1TS U8437 ( .A(n8427), .B(n7666), .Y(n7468) );
BUFX3TS U8438 ( .A(n8443), .Y(n8441) );
OA22X1TS U8439 ( .A0(n8441), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n8442), .Y(n294) );
OA22X1TS U8440 ( .A0(n8441), .A1(final_result_ieee[60]), .B0(
exp_oper_result[8]), .B1(n8442), .Y(n291) );
OA22X1TS U8441 ( .A0(n8441), .A1(final_result_ieee[59]), .B0(
exp_oper_result[7]), .B1(n8442), .Y(n292) );
OA22X1TS U8442 ( .A0(n8441), .A1(final_result_ieee[58]), .B0(
exp_oper_result[6]), .B1(n8442), .Y(n293) );
OA22X1TS U8443 ( .A0(n8441), .A1(final_result_ieee[53]), .B0(
exp_oper_result[1]), .B1(n8442), .Y(n298) );
BUFX3TS U8444 ( .A(n8534), .Y(n8533) );
BUFX3TS U8445 ( .A(n7471), .Y(n8505) );
BUFX3TS U8446 ( .A(n7471), .Y(n8506) );
NAND2X1TS U8447 ( .A(n8030), .B(Add_result[2]), .Y(n7474) );
NOR2X1TS U8448 ( .A(n8470), .B(n8447), .Y(n7488) );
NAND3X1TS U8449 ( .A(n7488), .B(n8446), .C(n1036), .Y(n7478) );
INVX2TS U8450 ( .A(n7478), .Y(ready) );
NOR2XLTS U8451 ( .A(n7475), .B(underflow_flag), .Y(n7476) );
OAI32X1TS U8452 ( .A0(n8434), .A1(n7476), .A2(overflow_flag), .B0(n8441),
.B1(n8490), .Y(n287) );
INVX2TS U8453 ( .A(zero_flag), .Y(n8428) );
AOI211X1TS U8454 ( .A0(n8366), .A1(n8428), .B0(n7485), .C0(n7477), .Y(n7479)
);
AOI32X1TS U8455 ( .A0(FS_Module_state_reg[3]), .A1(n7485), .A2(n7484), .B0(
n7535), .B1(n7485), .Y(n7487) );
CLKMX2X2TS U8456 ( .A(P_Sgf[104]), .B(n7513), .S0(n8354), .Y(n520) );
NAND2X1TS U8457 ( .A(Sgf_normalized_result[34]), .B(
Sgf_normalized_result[35]), .Y(n7679) );
NAND2X1TS U8458 ( .A(Sgf_normalized_result[36]), .B(
Sgf_normalized_result[37]), .Y(n7514) );
NOR2X1TS U8459 ( .A(n7679), .B(n7514), .Y(n7664) );
NAND2X1TS U8460 ( .A(n7664), .B(n7515), .Y(n7652) );
NOR2X1TS U8461 ( .A(n7652), .B(n8452), .Y(n7641) );
NAND2X1TS U8462 ( .A(n7641), .B(Sgf_normalized_result[41]), .Y(n7531) );
NAND2X1TS U8463 ( .A(Sgf_normalized_result[18]), .B(
Sgf_normalized_result[19]), .Y(n7882) );
NAND2X1TS U8464 ( .A(Sgf_normalized_result[20]), .B(
Sgf_normalized_result[21]), .Y(n7516) );
NOR2X1TS U8465 ( .A(n7882), .B(n7516), .Y(n7824) );
NAND2X1TS U8466 ( .A(Sgf_normalized_result[22]), .B(
Sgf_normalized_result[23]), .Y(n7826) );
NAND2X1TS U8467 ( .A(Sgf_normalized_result[24]), .B(
Sgf_normalized_result[25]), .Y(n7517) );
NAND2X1TS U8468 ( .A(n7824), .B(n7518), .Y(n7718) );
NAND2X1TS U8469 ( .A(Sgf_normalized_result[26]), .B(
Sgf_normalized_result[27]), .Y(n7766) );
NAND2X1TS U8470 ( .A(Sgf_normalized_result[28]), .B(
Sgf_normalized_result[29]), .Y(n7519) );
NOR2X1TS U8471 ( .A(n7766), .B(n7519), .Y(n7719) );
NAND2X1TS U8472 ( .A(Sgf_normalized_result[30]), .B(
Sgf_normalized_result[31]), .Y(n7721) );
NAND2X1TS U8473 ( .A(Sgf_normalized_result[32]), .B(
Sgf_normalized_result[33]), .Y(n7520) );
NAND2X1TS U8474 ( .A(n7719), .B(n7521), .Y(n7522) );
NAND2X1TS U8475 ( .A(Sgf_normalized_result[10]), .B(
Sgf_normalized_result[11]), .Y(n7993) );
NAND2X1TS U8476 ( .A(Sgf_normalized_result[12]), .B(
Sgf_normalized_result[13]), .Y(n7523) );
NAND2X1TS U8477 ( .A(Sgf_normalized_result[14]), .B(
Sgf_normalized_result[15]), .Y(n7940) );
NAND2X1TS U8478 ( .A(Sgf_normalized_result[16]), .B(
Sgf_normalized_result[17]), .Y(n7524) );
NAND2X1TS U8479 ( .A(n7939), .B(n7525), .Y(n7529) );
NAND2X1TS U8480 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n8058) );
NAND2X1TS U8481 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n7526) );
MXI2X1TS U8482 ( .A(P_Sgf[104]), .B(Add_result[52]), .S0(FSM_selector_C),
.Y(n7537) );
OAI21X1TS U8483 ( .A0(n7534), .A1(n8453), .B0(n7533), .Y(n7536) );
AOI21X1TS U8484 ( .A0(n7537), .A1(n7547), .B0(n8070), .Y(n7538) );
AHHCINX2TS U8485 ( .A(Sgf_normalized_result[51]), .CIN(n7539), .S(n7540),
.CO(n8184) );
BUFX3TS U8486 ( .A(n8183), .Y(n7639) );
BUFX3TS U8487 ( .A(n8039), .Y(n7637) );
BUFX3TS U8488 ( .A(n8178), .Y(n7634) );
AOI22X1TS U8489 ( .A0(n7634), .A1(Add_result[52]), .B0(
Sgf_normalized_result[51]), .B1(n8070), .Y(n7548) );
OAI2BB1X1TS U8490 ( .A0N(P_Sgf[104]), .A1N(n8069), .B0(n7548), .Y(n7549) );
AOI21X1TS U8491 ( .A0(n7637), .A1(Add_result[51]), .B0(n7549), .Y(n7550) );
OAI2BB1X1TS U8492 ( .A0N(n7639), .A1N(P_Sgf[103]), .B0(n7550), .Y(n404) );
AHHCONX2TS U8493 ( .A(Sgf_normalized_result[50]), .CI(n7551), .CON(n7539),
.S(n7552) );
XOR2X1TS U8494 ( .A(n7554), .B(n7553), .Y(n7555) );
AOI22X1TS U8495 ( .A0(n7634), .A1(Add_result[51]), .B0(
Sgf_normalized_result[50]), .B1(n8070), .Y(n7556) );
OAI2BB1X1TS U8496 ( .A0N(P_Sgf[103]), .A1N(n8069), .B0(n7556), .Y(n7557) );
AOI21X1TS U8497 ( .A0(n7637), .A1(Add_result[50]), .B0(n7557), .Y(n7558) );
OAI2BB1X1TS U8498 ( .A0N(n7639), .A1N(P_Sgf[102]), .B0(n7558), .Y(n403) );
AHHCINX2TS U8499 ( .A(Sgf_normalized_result[49]), .CIN(n7559), .S(n7560),
.CO(n7551) );
XNOR2X1TS U8500 ( .A(n7562), .B(n7561), .Y(n7563) );
BUFX3TS U8501 ( .A(n8069), .Y(n7661) );
BUFX3TS U8502 ( .A(n8070), .Y(n7659) );
AOI22X1TS U8503 ( .A0(n7634), .A1(Add_result[50]), .B0(
Sgf_normalized_result[49]), .B1(n7659), .Y(n7564) );
OAI2BB1X1TS U8504 ( .A0N(n7661), .A1N(P_Sgf[102]), .B0(n7564), .Y(n7565) );
AOI21X1TS U8505 ( .A0(n7637), .A1(Add_result[49]), .B0(n7565), .Y(n7566) );
OAI2BB1X1TS U8506 ( .A0N(n7639), .A1N(P_Sgf[101]), .B0(n7566), .Y(n402) );
AHHCONX2TS U8507 ( .A(Sgf_normalized_result[48]), .CI(n7567), .CON(n7559),
.S(n7568) );
XOR2X1TS U8508 ( .A(n7570), .B(n7569), .Y(n7571) );
AOI22X1TS U8509 ( .A0(n7634), .A1(Add_result[49]), .B0(
Sgf_normalized_result[48]), .B1(n7659), .Y(n7572) );
OAI2BB1X1TS U8510 ( .A0N(n7661), .A1N(P_Sgf[101]), .B0(n7572), .Y(n7573) );
AOI21X1TS U8511 ( .A0(n7637), .A1(Add_result[48]), .B0(n7573), .Y(n7574) );
OAI2BB1X1TS U8512 ( .A0N(n7639), .A1N(P_Sgf[100]), .B0(n7574), .Y(n401) );
AHHCINX2TS U8513 ( .A(Sgf_normalized_result[47]), .CIN(n7575), .S(n7576),
.CO(n7567) );
INVX4TS U8514 ( .A(n7577), .Y(n7759) );
INVX2TS U8515 ( .A(n7579), .Y(n7580) );
OAI21X1TS U8516 ( .A0(n7759), .A1(n7581), .B0(n7580), .Y(n7583) );
XNOR2X1TS U8517 ( .A(n7583), .B(n7582), .Y(n7584) );
AOI22X1TS U8518 ( .A0(n7634), .A1(Add_result[48]), .B0(
Sgf_normalized_result[47]), .B1(n7659), .Y(n7585) );
OAI2BB1X1TS U8519 ( .A0N(n7661), .A1N(P_Sgf[100]), .B0(n7585), .Y(n7586) );
AOI21X1TS U8520 ( .A0(n7637), .A1(Add_result[47]), .B0(n7586), .Y(n7587) );
OAI2BB1X1TS U8521 ( .A0N(n7639), .A1N(P_Sgf[99]), .B0(n7587), .Y(n400) );
AHHCONX2TS U8522 ( .A(Sgf_normalized_result[46]), .CI(n7588), .CON(n7575),
.S(n7589) );
OAI21X1TS U8523 ( .A0(n7759), .A1(n7591), .B0(n7590), .Y(n7593) );
XNOR2X1TS U8524 ( .A(n7593), .B(n7592), .Y(n7594) );
AOI22X1TS U8525 ( .A0(n7634), .A1(Add_result[47]), .B0(
Sgf_normalized_result[46]), .B1(n7659), .Y(n7595) );
OAI2BB1X1TS U8526 ( .A0N(n7661), .A1N(P_Sgf[99]), .B0(n7595), .Y(n7596) );
AOI21X1TS U8527 ( .A0(n7637), .A1(Add_result[46]), .B0(n7596), .Y(n7597) );
OAI2BB1X1TS U8528 ( .A0N(n7639), .A1N(P_Sgf[98]), .B0(n7597), .Y(n399) );
AHHCINX2TS U8529 ( .A(Sgf_normalized_result[45]), .CIN(n7598), .S(n7599),
.CO(n7588) );
NAND2X1TS U8530 ( .A(n7733), .B(n7602), .Y(n7604) );
CLKMX2X2TS U8531 ( .A(P_Sgf[97]), .B(n7605), .S0(n8191), .Y(n518) );
AOI22X1TS U8532 ( .A0(n7634), .A1(Add_result[46]), .B0(
Sgf_normalized_result[45]), .B1(n7659), .Y(n7606) );
OAI2BB1X1TS U8533 ( .A0N(n7661), .A1N(P_Sgf[98]), .B0(n7606), .Y(n7607) );
AOI21X1TS U8534 ( .A0(n7637), .A1(Add_result[45]), .B0(n7607), .Y(n7608) );
OAI2BB1X1TS U8535 ( .A0N(n7639), .A1N(P_Sgf[97]), .B0(n7608), .Y(n398) );
AHHCONX2TS U8536 ( .A(Sgf_normalized_result[44]), .CI(n7609), .CON(n7598),
.S(n7610) );
NAND2X1TS U8537 ( .A(n7733), .B(n7611), .Y(n7613) );
CLKMX2X2TS U8538 ( .A(P_Sgf[96]), .B(n7614), .S0(n8191), .Y(n517) );
AOI22X1TS U8539 ( .A0(n7634), .A1(Add_result[45]), .B0(
Sgf_normalized_result[44]), .B1(n7659), .Y(n7615) );
OAI2BB1X1TS U8540 ( .A0N(n7661), .A1N(P_Sgf[97]), .B0(n7615), .Y(n7616) );
AOI21X1TS U8541 ( .A0(n7637), .A1(Add_result[44]), .B0(n7616), .Y(n7617) );
OAI2BB1X1TS U8542 ( .A0N(n7639), .A1N(P_Sgf[96]), .B0(n7617), .Y(n397) );
AHHCINX2TS U8543 ( .A(Sgf_normalized_result[43]), .CIN(n7618), .S(n7619),
.CO(n7609) );
NAND2X1TS U8544 ( .A(n7733), .B(n7621), .Y(n7623) );
CLKMX2X2TS U8545 ( .A(P_Sgf[95]), .B(n7624), .S0(n7712), .Y(n516) );
AOI22X1TS U8546 ( .A0(n7634), .A1(Add_result[44]), .B0(
Sgf_normalized_result[43]), .B1(n7659), .Y(n7625) );
OAI2BB1X1TS U8547 ( .A0N(n7661), .A1N(P_Sgf[96]), .B0(n7625), .Y(n7626) );
AOI21X1TS U8548 ( .A0(n7637), .A1(Add_result[43]), .B0(n7626), .Y(n7627) );
OAI2BB1X1TS U8549 ( .A0N(n7639), .A1N(P_Sgf[95]), .B0(n7627), .Y(n396) );
AHHCONX2TS U8550 ( .A(Sgf_normalized_result[42]), .CI(n7628), .CON(n7618),
.S(n7629) );
NAND2X1TS U8551 ( .A(n7733), .B(n7630), .Y(n7632) );
CLKMX2X2TS U8552 ( .A(P_Sgf[94]), .B(n7633), .S0(n7712), .Y(n515) );
AOI22X1TS U8553 ( .A0(n7634), .A1(Add_result[43]), .B0(
Sgf_normalized_result[42]), .B1(n7659), .Y(n7635) );
OAI2BB1X1TS U8554 ( .A0N(n7661), .A1N(P_Sgf[95]), .B0(n7635), .Y(n7636) );
AOI21X1TS U8555 ( .A0(n7637), .A1(Add_result[42]), .B0(n7636), .Y(n7638) );
OAI2BB1X1TS U8556 ( .A0N(n7639), .A1N(P_Sgf[94]), .B0(n7638), .Y(n395) );
INVX2TS U8557 ( .A(n7640), .Y(n7708) );
NAND2X1TS U8558 ( .A(n7708), .B(n7641), .Y(n7642) );
XOR2X1TS U8559 ( .A(n7642), .B(n8472), .Y(n7643) );
INVX2TS U8560 ( .A(n7644), .Y(n7645) );
NAND2X2TS U8561 ( .A(n7733), .B(n7645), .Y(n7657) );
NOR2X4TS U8562 ( .A(n7657), .B(n7656), .Y(n7647) );
XNOR2X4TS U8563 ( .A(n7647), .B(n7646), .Y(n7648) );
CLKMX2X2TS U8564 ( .A(P_Sgf[93]), .B(n7648), .S0(n7712), .Y(n514) );
BUFX3TS U8565 ( .A(n8183), .Y(n7740) );
BUFX3TS U8566 ( .A(n8039), .Y(n7738) );
BUFX3TS U8567 ( .A(n8178), .Y(n7735) );
AOI22X1TS U8568 ( .A0(n7735), .A1(Add_result[42]), .B0(
Sgf_normalized_result[41]), .B1(n7659), .Y(n7649) );
OAI2BB1X1TS U8569 ( .A0N(n7661), .A1N(P_Sgf[94]), .B0(n7649), .Y(n7650) );
AOI21X1TS U8570 ( .A0(n7738), .A1(Add_result[41]), .B0(n7650), .Y(n7651) );
OAI2BB1X1TS U8571 ( .A0N(n7740), .A1N(P_Sgf[93]), .B0(n7651), .Y(n394) );
NAND2X1TS U8572 ( .A(n7708), .B(n7653), .Y(n7654) );
XOR2X1TS U8573 ( .A(n7654), .B(n8452), .Y(n7655) );
CLKMX2X2TS U8574 ( .A(P_Sgf[92]), .B(n7658), .S0(n7712), .Y(n513) );
AOI22X1TS U8575 ( .A0(n7735), .A1(Add_result[41]), .B0(
Sgf_normalized_result[40]), .B1(n7659), .Y(n7660) );
OAI2BB1X1TS U8576 ( .A0N(n7661), .A1N(P_Sgf[93]), .B0(n7660), .Y(n7662) );
AOI21X1TS U8577 ( .A0(n7738), .A1(Add_result[40]), .B0(n7662), .Y(n7663) );
OAI2BB1X1TS U8578 ( .A0N(n7740), .A1N(P_Sgf[92]), .B0(n7663), .Y(n393) );
NAND2X1TS U8579 ( .A(n7708), .B(n7664), .Y(n7671) );
XNOR2X1TS U8580 ( .A(n7665), .B(n8449), .Y(n7667) );
BUFX3TS U8581 ( .A(n8069), .Y(n7763) );
BUFX3TS U8582 ( .A(n8070), .Y(n7761) );
AOI22X1TS U8583 ( .A0(n7735), .A1(Add_result[40]), .B0(
Sgf_normalized_result[39]), .B1(n7761), .Y(n7668) );
OAI2BB1X1TS U8584 ( .A0N(n7763), .A1N(P_Sgf[92]), .B0(n7668), .Y(n7669) );
AOI21X1TS U8585 ( .A0(n7738), .A1(Add_result[39]), .B0(n7669), .Y(n7670) );
OAI2BB1X1TS U8586 ( .A0N(n7740), .A1N(P_Sgf[91]), .B0(n7670), .Y(n392) );
XOR2X1TS U8587 ( .A(n7671), .B(n8451), .Y(n7672) );
AOI22X1TS U8588 ( .A0(n7735), .A1(Add_result[39]), .B0(
Sgf_normalized_result[38]), .B1(n7761), .Y(n7676) );
OAI2BB1X1TS U8589 ( .A0N(n7763), .A1N(P_Sgf[91]), .B0(n7676), .Y(n7677) );
AOI21X1TS U8590 ( .A0(n7738), .A1(Add_result[38]), .B0(n7677), .Y(n7678) );
OAI2BB1X1TS U8591 ( .A0N(n7740), .A1N(P_Sgf[90]), .B0(n7678), .Y(n391) );
INVX2TS U8592 ( .A(n7679), .Y(n7680) );
NAND2X1TS U8593 ( .A(n7708), .B(n7680), .Y(n7690) );
XNOR2X1TS U8594 ( .A(n7681), .B(n8476), .Y(n7682) );
NOR2X4TS U8595 ( .A(n7693), .B(n7692), .Y(n7684) );
CLKMX2X2TS U8596 ( .A(P_Sgf[89]), .B(n7686), .S0(n7712), .Y(n510) );
AOI22X1TS U8597 ( .A0(n7735), .A1(Add_result[38]), .B0(
Sgf_normalized_result[37]), .B1(n7761), .Y(n7687) );
OAI2BB1X1TS U8598 ( .A0N(n7763), .A1N(P_Sgf[90]), .B0(n7687), .Y(n7688) );
AOI21X1TS U8599 ( .A0(n7738), .A1(Add_result[37]), .B0(n7688), .Y(n7689) );
OAI2BB1X1TS U8600 ( .A0N(n7740), .A1N(P_Sgf[89]), .B0(n7689), .Y(n390) );
XOR2X1TS U8601 ( .A(n7690), .B(n8464), .Y(n7691) );
CLKMX2X2TS U8602 ( .A(P_Sgf[88]), .B(n7694), .S0(n7712), .Y(n509) );
AOI22X1TS U8603 ( .A0(n7735), .A1(Add_result[37]), .B0(
Sgf_normalized_result[36]), .B1(n7761), .Y(n7695) );
OAI2BB1X1TS U8604 ( .A0N(n7763), .A1N(P_Sgf[89]), .B0(n7695), .Y(n7696) );
AOI21X1TS U8605 ( .A0(n7738), .A1(Add_result[36]), .B0(n7696), .Y(n7697) );
OAI2BB1X1TS U8606 ( .A0N(n7740), .A1N(P_Sgf[88]), .B0(n7697), .Y(n389) );
NAND2X1TS U8607 ( .A(n7708), .B(Sgf_normalized_result[34]), .Y(n7698) );
XOR2X1TS U8608 ( .A(n7698), .B(n8473), .Y(n7699) );
INVX2TS U8609 ( .A(n7700), .Y(n7701) );
NOR2X4TS U8610 ( .A(n7711), .B(n7710), .Y(n7703) );
XNOR2X4TS U8611 ( .A(n7703), .B(n7702), .Y(n7704) );
CLKMX2X2TS U8612 ( .A(P_Sgf[87]), .B(n7704), .S0(n7712), .Y(n508) );
AOI22X1TS U8613 ( .A0(n7735), .A1(Add_result[36]), .B0(
Sgf_normalized_result[35]), .B1(n7761), .Y(n7705) );
OAI2BB1X1TS U8614 ( .A0N(n7763), .A1N(P_Sgf[88]), .B0(n7705), .Y(n7706) );
AOI21X1TS U8615 ( .A0(n7738), .A1(Add_result[35]), .B0(n7706), .Y(n7707) );
OAI2BB1X1TS U8616 ( .A0N(n7740), .A1N(P_Sgf[87]), .B0(n7707), .Y(n388) );
XNOR2X1TS U8617 ( .A(n7708), .B(n8454), .Y(n7709) );
CLKMX2X2TS U8618 ( .A(P_Sgf[86]), .B(n7713), .S0(n7712), .Y(n507) );
AOI22X1TS U8619 ( .A0(n7735), .A1(Add_result[35]), .B0(
Sgf_normalized_result[34]), .B1(n7761), .Y(n7714) );
OAI2BB1X1TS U8620 ( .A0N(n7763), .A1N(P_Sgf[87]), .B0(n7714), .Y(n7715) );
AOI21X1TS U8621 ( .A0(n7738), .A1(Add_result[34]), .B0(n7715), .Y(n7716) );
OAI2BB1X1TS U8622 ( .A0N(n7740), .A1N(P_Sgf[86]), .B0(n7716), .Y(n387) );
INVX2TS U8623 ( .A(n7800), .Y(n7813) );
INVX2TS U8624 ( .A(n7719), .Y(n7720) );
INVX2TS U8625 ( .A(n7741), .Y(n7753) );
NOR2X1TS U8626 ( .A(n7753), .B(n7721), .Y(n7730) );
NAND2X1TS U8627 ( .A(n7730), .B(Sgf_normalized_result[32]), .Y(n7722) );
XOR2X1TS U8628 ( .A(n7722), .B(n8474), .Y(n7723) );
NAND2X1TS U8629 ( .A(n7733), .B(Sgf_operation_ODD1_Q_left[30]), .Y(n7725) );
CLKMX2X2TS U8630 ( .A(P_Sgf[85]), .B(n7726), .S0(n7850), .Y(n506) );
AOI22X1TS U8631 ( .A0(n7735), .A1(Add_result[34]), .B0(
Sgf_normalized_result[33]), .B1(n7761), .Y(n7727) );
OAI2BB1X1TS U8632 ( .A0N(n7763), .A1N(P_Sgf[86]), .B0(n7727), .Y(n7728) );
AOI21X1TS U8633 ( .A0(n7738), .A1(Add_result[33]), .B0(n7728), .Y(n7729) );
OAI2BB1X1TS U8634 ( .A0N(n7740), .A1N(P_Sgf[85]), .B0(n7729), .Y(n386) );
XNOR2X1TS U8635 ( .A(n7730), .B(n8455), .Y(n7731) );
XNOR2X1TS U8636 ( .A(n7733), .B(n7732), .Y(n7734) );
AOI22X1TS U8637 ( .A0(n7735), .A1(Add_result[33]), .B0(
Sgf_normalized_result[32]), .B1(n7761), .Y(n7736) );
OAI2BB1X1TS U8638 ( .A0N(n7763), .A1N(P_Sgf[85]), .B0(n7736), .Y(n7737) );
AOI21X1TS U8639 ( .A0(n7738), .A1(Add_result[32]), .B0(n7737), .Y(n7739) );
OAI2BB1X1TS U8640 ( .A0N(n7740), .A1N(P_Sgf[84]), .B0(n7739), .Y(n385) );
NAND2X1TS U8641 ( .A(n7741), .B(Sgf_normalized_result[30]), .Y(n7742) );
XOR2X1TS U8642 ( .A(n7742), .B(n8475), .Y(n7743) );
OAI21X1TS U8643 ( .A0(n7759), .A1(n7755), .B0(n7756), .Y(n7748) );
NAND2X1TS U8644 ( .A(n7746), .B(n7745), .Y(n7747) );
XNOR2X1TS U8645 ( .A(n7748), .B(n7747), .Y(n7749) );
BUFX3TS U8646 ( .A(n8039), .Y(n7880) );
BUFX3TS U8647 ( .A(n8178), .Y(n7877) );
AOI22X1TS U8648 ( .A0(n7877), .A1(Add_result[32]), .B0(
Sgf_normalized_result[31]), .B1(n7761), .Y(n7750) );
OAI2BB1X1TS U8649 ( .A0N(n7763), .A1N(P_Sgf[84]), .B0(n7750), .Y(n7751) );
AOI21X1TS U8650 ( .A0(n7880), .A1(Add_result[31]), .B0(n7751), .Y(n7752) );
OAI2BB1X1TS U8651 ( .A0N(n7899), .A1N(P_Sgf[83]), .B0(n7752), .Y(n384) );
XOR2X1TS U8652 ( .A(n7753), .B(n8461), .Y(n7754) );
NAND2X1TS U8653 ( .A(n7757), .B(n7756), .Y(n7758) );
XOR2X1TS U8654 ( .A(n7759), .B(n7758), .Y(n7760) );
AOI22X1TS U8655 ( .A0(n7877), .A1(Add_result[31]), .B0(
Sgf_normalized_result[30]), .B1(n7761), .Y(n7762) );
OAI2BB1X1TS U8656 ( .A0N(n7763), .A1N(P_Sgf[83]), .B0(n7762), .Y(n7764) );
AOI21X1TS U8657 ( .A0(n7880), .A1(Add_result[30]), .B0(n7764), .Y(n7765) );
OAI2BB1X1TS U8658 ( .A0N(n7899), .A1N(P_Sgf[82]), .B0(n7765), .Y(n383) );
NOR2X1TS U8659 ( .A(n7813), .B(n7766), .Y(n7789) );
NAND2X1TS U8660 ( .A(n7789), .B(Sgf_normalized_result[28]), .Y(n7767) );
XOR2X1TS U8661 ( .A(n7767), .B(n8477), .Y(n7769) );
INVX8TS U8662 ( .A(n7770), .Y(n7987) );
INVX2TS U8663 ( .A(n7771), .Y(n7774) );
INVX2TS U8664 ( .A(n7772), .Y(n7773) );
OAI21X4TS U8665 ( .A0(n7987), .A1(n7774), .B0(n7773), .Y(n7860) );
INVX2TS U8666 ( .A(n7775), .Y(n7777) );
OAI2BB1X4TS U8667 ( .A0N(n7860), .A1N(n7777), .B0(n7776), .Y(n7803) );
AOI21X4TS U8668 ( .A0(n7803), .A1(n7779), .B0(n7778), .Y(n7795) );
OAI21X2TS U8669 ( .A0(n7795), .A1(n7791), .B0(n7792), .Y(n7784) );
NAND2X1TS U8670 ( .A(n7782), .B(n7781), .Y(n7783) );
XNOR2X4TS U8671 ( .A(n7784), .B(n7783), .Y(n7785) );
BUFX3TS U8672 ( .A(n8069), .Y(n7911) );
BUFX3TS U8673 ( .A(n8070), .Y(n8040) );
AOI22X1TS U8674 ( .A0(n7877), .A1(Add_result[30]), .B0(
Sgf_normalized_result[29]), .B1(n8040), .Y(n7786) );
OAI2BB1X1TS U8675 ( .A0N(n7911), .A1N(P_Sgf[82]), .B0(n7786), .Y(n7787) );
AOI21X1TS U8676 ( .A0(n7880), .A1(Add_result[29]), .B0(n7787), .Y(n7788) );
OAI2BB1X1TS U8677 ( .A0N(n7899), .A1N(P_Sgf[81]), .B0(n7788), .Y(n382) );
XNOR2X1TS U8678 ( .A(n7789), .B(n8456), .Y(n7790) );
NAND2X1TS U8679 ( .A(n7793), .B(n7792), .Y(n7794) );
XOR2X1TS U8680 ( .A(n7795), .B(n7794), .Y(n7796) );
AOI22X1TS U8681 ( .A0(n7877), .A1(Add_result[29]), .B0(
Sgf_normalized_result[28]), .B1(n8040), .Y(n7797) );
OAI2BB1X1TS U8682 ( .A0N(n7911), .A1N(P_Sgf[81]), .B0(n7797), .Y(n7798) );
AOI21X1TS U8683 ( .A0(n7880), .A1(Add_result[28]), .B0(n7798), .Y(n7799) );
OAI2BB1X1TS U8684 ( .A0N(n7899), .A1N(P_Sgf[80]), .B0(n7799), .Y(n381) );
NAND2X1TS U8685 ( .A(n7800), .B(Sgf_normalized_result[26]), .Y(n7801) );
XOR2X1TS U8686 ( .A(n7801), .B(n8478), .Y(n7802) );
OAI21X4TS U8687 ( .A0(n7819), .A1(n7815), .B0(n7816), .Y(n7808) );
CLKINVX1TS U8688 ( .A(n7804), .Y(n7806) );
NAND2X1TS U8689 ( .A(n7806), .B(n7805), .Y(n7807) );
AOI22X1TS U8690 ( .A0(n7877), .A1(Add_result[28]), .B0(
Sgf_normalized_result[27]), .B1(n8040), .Y(n7810) );
OAI2BB1X1TS U8691 ( .A0N(n7911), .A1N(P_Sgf[80]), .B0(n7810), .Y(n7811) );
AOI21X1TS U8692 ( .A0(n7880), .A1(Add_result[27]), .B0(n7811), .Y(n7812) );
OAI2BB1X1TS U8693 ( .A0N(n7545), .A1N(P_Sgf[79]), .B0(n7812), .Y(n380) );
XOR2X1TS U8694 ( .A(n7813), .B(n8462), .Y(n7814) );
INVX2TS U8695 ( .A(n7815), .Y(n7817) );
NAND2X1TS U8696 ( .A(n7817), .B(n7816), .Y(n7818) );
XOR2X1TS U8697 ( .A(n7819), .B(n7818), .Y(n7820) );
AOI22X1TS U8698 ( .A0(n7877), .A1(Add_result[27]), .B0(
Sgf_normalized_result[26]), .B1(n8040), .Y(n7821) );
OAI2BB1X1TS U8699 ( .A0N(n7911), .A1N(P_Sgf[79]), .B0(n7821), .Y(n7822) );
AOI21X1TS U8700 ( .A0(n7880), .A1(Add_result[26]), .B0(n7822), .Y(n7823) );
OAI2BB1X1TS U8701 ( .A0N(n7545), .A1N(P_Sgf[78]), .B0(n7823), .Y(n379) );
INVX2TS U8702 ( .A(n7855), .Y(n7870) );
NOR2X1TS U8703 ( .A(n7870), .B(n7826), .Y(n7844) );
NAND2X1TS U8704 ( .A(n7844), .B(Sgf_normalized_result[24]), .Y(n7827) );
XOR2X1TS U8705 ( .A(n7827), .B(n8479), .Y(n7828) );
INVX2TS U8706 ( .A(n7829), .Y(n7832) );
INVX2TS U8707 ( .A(n7830), .Y(n7831) );
INVX2TS U8708 ( .A(n7833), .Y(n7847) );
INVX2TS U8709 ( .A(n7846), .Y(n7834) );
NAND2X1TS U8710 ( .A(n7837), .B(n7836), .Y(n7838) );
CLKMX2X2TS U8711 ( .A(P_Sgf[77]), .B(n7840), .S0(n7850), .Y(n498) );
AOI22X1TS U8712 ( .A0(n7877), .A1(Add_result[26]), .B0(
Sgf_normalized_result[25]), .B1(n8040), .Y(n7841) );
OAI2BB1X1TS U8713 ( .A0N(n7911), .A1N(P_Sgf[78]), .B0(n7841), .Y(n7842) );
AOI21X1TS U8714 ( .A0(n7880), .A1(Add_result[25]), .B0(n7842), .Y(n7843) );
OAI2BB1X1TS U8715 ( .A0N(n7545), .A1N(P_Sgf[77]), .B0(n7843), .Y(n378) );
XNOR2X1TS U8716 ( .A(n7844), .B(n8457), .Y(n7845) );
NAND2X1TS U8717 ( .A(n7847), .B(n7846), .Y(n7848) );
XNOR2X1TS U8718 ( .A(n7849), .B(n7848), .Y(n7851) );
AOI22X1TS U8719 ( .A0(n7877), .A1(Add_result[25]), .B0(
Sgf_normalized_result[24]), .B1(n8040), .Y(n7852) );
OAI2BB1X1TS U8720 ( .A0N(n7911), .A1N(P_Sgf[77]), .B0(n7852), .Y(n7853) );
AOI21X1TS U8721 ( .A0(n7880), .A1(Add_result[24]), .B0(n7853), .Y(n7854) );
OAI2BB1X1TS U8722 ( .A0N(n7545), .A1N(P_Sgf[76]), .B0(n7854), .Y(n377) );
NAND2X1TS U8723 ( .A(n7855), .B(Sgf_normalized_result[22]), .Y(n7856) );
XOR2X1TS U8724 ( .A(n7856), .B(n8480), .Y(n7857) );
INVX2TS U8725 ( .A(n7858), .Y(n7873) );
INVX2TS U8726 ( .A(n7872), .Y(n7859) );
AOI21X1TS U8727 ( .A0(n7860), .A1(n7873), .B0(n7859), .Y(n7865) );
INVX2TS U8728 ( .A(n7861), .Y(n7863) );
NAND2X1TS U8729 ( .A(n7863), .B(n7862), .Y(n7864) );
XOR2X1TS U8730 ( .A(n7865), .B(n7864), .Y(n7866) );
AOI22X1TS U8731 ( .A0(n7877), .A1(Add_result[24]), .B0(
Sgf_normalized_result[23]), .B1(n8040), .Y(n7867) );
OAI2BB1X1TS U8732 ( .A0N(n7911), .A1N(P_Sgf[76]), .B0(n7867), .Y(n7868) );
AOI21X1TS U8733 ( .A0(n7880), .A1(Add_result[23]), .B0(n7868), .Y(n7869) );
OAI2BB1X1TS U8734 ( .A0N(n7899), .A1N(P_Sgf[75]), .B0(n7869), .Y(n376) );
XOR2X1TS U8735 ( .A(n7870), .B(n8463), .Y(n7871) );
NAND2X1TS U8736 ( .A(n7873), .B(n7872), .Y(n7874) );
XOR2X1TS U8737 ( .A(n7875), .B(n7874), .Y(n7876) );
AOI22X1TS U8738 ( .A0(n7877), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n8040), .Y(n7878) );
OAI2BB1X1TS U8739 ( .A0N(n7911), .A1N(P_Sgf[75]), .B0(n7878), .Y(n7879) );
AOI21X1TS U8740 ( .A0(n7880), .A1(Add_result[22]), .B0(n7879), .Y(n7881) );
OAI2BB1X1TS U8741 ( .A0N(n7899), .A1N(P_Sgf[74]), .B0(n7881), .Y(n375) );
NOR2X1TS U8742 ( .A(n7928), .B(n7882), .Y(n7903) );
NAND2X1TS U8743 ( .A(n7903), .B(Sgf_normalized_result[20]), .Y(n7883) );
XOR2X1TS U8744 ( .A(n7883), .B(n8481), .Y(n7884) );
OAI21X4TS U8745 ( .A0(n7987), .A1(n7886), .B0(n7885), .Y(n7918) );
INVX2TS U8746 ( .A(n7887), .Y(n7890) );
INVX2TS U8747 ( .A(n7888), .Y(n7889) );
OAI21X4TS U8748 ( .A0(n7933), .A1(n7890), .B0(n7889), .Y(n7908) );
INVX2TS U8749 ( .A(n7891), .Y(n7906) );
INVX2TS U8750 ( .A(n7905), .Y(n7892) );
NAND2X1TS U8751 ( .A(n7895), .B(n7894), .Y(n7896) );
XOR2X1TS U8752 ( .A(n7897), .B(n7896), .Y(n7898) );
CLKMX2X2TS U8753 ( .A(P_Sgf[73]), .B(n7898), .S0(n7988), .Y(n494) );
BUFX3TS U8754 ( .A(n7899), .Y(n8028) );
BUFX3TS U8755 ( .A(n8039), .Y(n8026) );
BUFX3TS U8756 ( .A(n8178), .Y(n8023) );
AOI22X1TS U8757 ( .A0(n8023), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n8040), .Y(n7900) );
OAI2BB1X1TS U8758 ( .A0N(n7911), .A1N(P_Sgf[74]), .B0(n7900), .Y(n7901) );
AOI21X1TS U8759 ( .A0(n8026), .A1(Add_result[21]), .B0(n7901), .Y(n7902) );
OAI2BB1X1TS U8760 ( .A0N(n8028), .A1N(P_Sgf[73]), .B0(n7902), .Y(n374) );
XNOR2X1TS U8761 ( .A(n7903), .B(n8458), .Y(n7904) );
NAND2X1TS U8762 ( .A(n7906), .B(n7905), .Y(n7907) );
XNOR2X1TS U8763 ( .A(n7908), .B(n7907), .Y(n7909) );
BUFX3TS U8764 ( .A(n8070), .Y(n8052) );
AOI22X1TS U8765 ( .A0(n8023), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n8052), .Y(n7910) );
OAI2BB1X1TS U8766 ( .A0N(n7911), .A1N(P_Sgf[73]), .B0(n7910), .Y(n7912) );
AOI21X1TS U8767 ( .A0(n8026), .A1(Add_result[20]), .B0(n7912), .Y(n7913) );
OAI2BB1X1TS U8768 ( .A0N(n8028), .A1N(P_Sgf[72]), .B0(n7913), .Y(n373) );
XNOR2X1TS U8769 ( .A(n7914), .B(n8484), .Y(n7915) );
INVX2TS U8770 ( .A(n7916), .Y(n7931) );
INVX2TS U8771 ( .A(n7930), .Y(n7917) );
AOI21X1TS U8772 ( .A0(n7918), .A1(n7931), .B0(n7917), .Y(n7923) );
NAND2X1TS U8773 ( .A(n7921), .B(n7920), .Y(n7922) );
XOR2X1TS U8774 ( .A(n7923), .B(n7922), .Y(n7924) );
BUFX3TS U8775 ( .A(n8069), .Y(n8054) );
AOI22X1TS U8776 ( .A0(n8023), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n8052), .Y(n7925) );
OAI2BB1X1TS U8777 ( .A0N(n8054), .A1N(P_Sgf[72]), .B0(n7925), .Y(n7926) );
AOI21X1TS U8778 ( .A0(n8026), .A1(Add_result[19]), .B0(n7926), .Y(n7927) );
OAI2BB1X1TS U8779 ( .A0N(n8028), .A1N(P_Sgf[71]), .B0(n7927), .Y(n372) );
XOR2X1TS U8780 ( .A(n7928), .B(n8465), .Y(n7929) );
NAND2X1TS U8781 ( .A(n7931), .B(n7930), .Y(n7932) );
XOR2X1TS U8782 ( .A(n7933), .B(n7932), .Y(n7934) );
AOI22X1TS U8783 ( .A0(n8023), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n8052), .Y(n7935) );
OAI2BB1X1TS U8784 ( .A0N(n8054), .A1N(P_Sgf[71]), .B0(n7935), .Y(n7936) );
AOI21X1TS U8785 ( .A0(n8026), .A1(Add_result[18]), .B0(n7936), .Y(n7937) );
OAI2BB1X1TS U8786 ( .A0N(n8028), .A1N(P_Sgf[70]), .B0(n7937), .Y(n371) );
INVX2TS U8787 ( .A(n7938), .Y(n8044) );
NAND2X1TS U8788 ( .A(n8044), .B(n7939), .Y(n7969) );
INVX2TS U8789 ( .A(n7969), .Y(n7981) );
NAND2X1TS U8790 ( .A(n7981), .B(n7941), .Y(n7959) );
XNOR2X1TS U8791 ( .A(n7942), .B(n8485), .Y(n7943) );
INVX2TS U8792 ( .A(n7944), .Y(n7947) );
INVX2TS U8793 ( .A(n7945), .Y(n7946) );
OAI21X2TS U8794 ( .A0(n7987), .A1(n7947), .B0(n7946), .Y(n7964) );
INVX2TS U8795 ( .A(n7948), .Y(n7962) );
INVX2TS U8796 ( .A(n7961), .Y(n7949) );
AOI21X1TS U8797 ( .A0(n7964), .A1(n7962), .B0(n7949), .Y(n7954) );
CLKINVX1TS U8798 ( .A(n7950), .Y(n7952) );
NAND2X1TS U8799 ( .A(n7952), .B(n7951), .Y(n7953) );
XOR2X1TS U8800 ( .A(n7954), .B(n7953), .Y(n7955) );
AOI22X1TS U8801 ( .A0(n8023), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n8052), .Y(n7956) );
OAI2BB1X1TS U8802 ( .A0N(n8054), .A1N(P_Sgf[70]), .B0(n7956), .Y(n7957) );
AOI21X1TS U8803 ( .A0(n8026), .A1(Add_result[17]), .B0(n7957), .Y(n7958) );
OAI2BB1X1TS U8804 ( .A0N(n8028), .A1N(P_Sgf[69]), .B0(n7958), .Y(n370) );
XOR2X1TS U8805 ( .A(n7959), .B(n8466), .Y(n7960) );
NAND2X1TS U8806 ( .A(n7962), .B(n7961), .Y(n7963) );
XNOR2X1TS U8807 ( .A(n7964), .B(n7963), .Y(n7965) );
AOI22X1TS U8808 ( .A0(n8023), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n8052), .Y(n7966) );
OAI2BB1X1TS U8809 ( .A0N(n8054), .A1N(P_Sgf[69]), .B0(n7966), .Y(n7967) );
AOI21X1TS U8810 ( .A0(n8026), .A1(Add_result[16]), .B0(n7967), .Y(n7968) );
OAI2BB1X1TS U8811 ( .A0N(n8028), .A1N(P_Sgf[68]), .B0(n7968), .Y(n369) );
XNOR2X1TS U8812 ( .A(n7970), .B(n8486), .Y(n7971) );
INVX2TS U8813 ( .A(n7972), .Y(n7974) );
NAND2X1TS U8814 ( .A(n7974), .B(n7973), .Y(n7975) );
XNOR2X1TS U8815 ( .A(n7976), .B(n7975), .Y(n7977) );
AOI22X1TS U8816 ( .A0(n8023), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n8052), .Y(n7978) );
OAI2BB1X1TS U8817 ( .A0N(n8054), .A1N(P_Sgf[68]), .B0(n7978), .Y(n7979) );
AOI21X1TS U8818 ( .A0(n8026), .A1(Add_result[15]), .B0(n7979), .Y(n7980) );
OAI2BB1X1TS U8819 ( .A0N(n8028), .A1N(P_Sgf[67]), .B0(n7980), .Y(n368) );
XNOR2X1TS U8820 ( .A(n7981), .B(n8469), .Y(n7982) );
INVX2TS U8821 ( .A(n7983), .Y(n7985) );
NAND2X1TS U8822 ( .A(n7985), .B(n7984), .Y(n7986) );
XOR2X1TS U8823 ( .A(n7987), .B(n7986), .Y(n7989) );
AOI22X1TS U8824 ( .A0(n8023), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n8052), .Y(n7990) );
OAI2BB1X1TS U8825 ( .A0N(n8054), .A1N(P_Sgf[67]), .B0(n7990), .Y(n7991) );
AOI21X1TS U8826 ( .A0(n8026), .A1(Add_result[14]), .B0(n7991), .Y(n7992) );
OAI2BB1X1TS U8827 ( .A0N(n8028), .A1N(P_Sgf[66]), .B0(n7992), .Y(n367) );
NAND2X1TS U8828 ( .A(n8044), .B(n7994), .Y(n8015) );
XNOR2X1TS U8829 ( .A(n7995), .B(n8487), .Y(n7996) );
INVX6TS U8830 ( .A(n7997), .Y(n8346) );
AOI21X4TS U8831 ( .A0(n8346), .A1(n7999), .B0(n7998), .Y(n8087) );
INVX2TS U8832 ( .A(n8000), .Y(n8003) );
INVX2TS U8833 ( .A(n8001), .Y(n8002) );
AOI21X4TS U8834 ( .A0(n8103), .A1(n8003), .B0(n8002), .Y(n8032) );
INVX2TS U8835 ( .A(n8032), .Y(n8050) );
AOI21X4TS U8836 ( .A0(n8050), .A1(n8005), .B0(n8004), .Y(n8021) );
NAND2X1TS U8837 ( .A(n8008), .B(n8007), .Y(n8009) );
CLKMX2X2TS U8838 ( .A(P_Sgf[65]), .B(n8011), .S0(n8133), .Y(n486) );
AOI22X1TS U8839 ( .A0(n8023), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n8052), .Y(n8012) );
OAI2BB1X1TS U8840 ( .A0N(n8054), .A1N(P_Sgf[66]), .B0(n8012), .Y(n8013) );
AOI21X1TS U8841 ( .A0(n8026), .A1(Add_result[13]), .B0(n8013), .Y(n8014) );
OAI2BB1X1TS U8842 ( .A0N(n8028), .A1N(P_Sgf[65]), .B0(n8014), .Y(n366) );
XOR2X1TS U8843 ( .A(n8015), .B(n8467), .Y(n8016) );
NAND2X1TS U8844 ( .A(n8019), .B(n8018), .Y(n8020) );
XOR2X1TS U8845 ( .A(n8021), .B(n8020), .Y(n8022) );
AOI22X1TS U8846 ( .A0(n8023), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n8052), .Y(n8024) );
OAI2BB1X1TS U8847 ( .A0N(n8054), .A1N(P_Sgf[65]), .B0(n8024), .Y(n8025) );
AOI21X1TS U8848 ( .A0(n8026), .A1(Add_result[12]), .B0(n8025), .Y(n8027) );
OAI2BB1X1TS U8849 ( .A0N(n8028), .A1N(P_Sgf[64]), .B0(n8027), .Y(n365) );
NAND2X1TS U8850 ( .A(n8044), .B(Sgf_normalized_result[10]), .Y(n8029) );
XOR2X1TS U8851 ( .A(n8029), .B(n8482), .Y(n8031) );
NAND2X1TS U8852 ( .A(n8035), .B(n8034), .Y(n8036) );
XNOR2X1TS U8853 ( .A(n8037), .B(n8036), .Y(n8038) );
BUFX3TS U8854 ( .A(n8039), .Y(n8158) );
BUFX3TS U8855 ( .A(n8178), .Y(n8155) );
AOI22X1TS U8856 ( .A0(n8155), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n8040), .Y(n8041) );
OAI2BB1X1TS U8857 ( .A0N(n8054), .A1N(P_Sgf[64]), .B0(n8041), .Y(n8042) );
AOI21X1TS U8858 ( .A0(n8158), .A1(Add_result[11]), .B0(n8042), .Y(n8043) );
OAI2BB1X1TS U8859 ( .A0N(n8183), .A1N(P_Sgf[63]), .B0(n8043), .Y(n364) );
XNOR2X1TS U8860 ( .A(n8044), .B(n8459), .Y(n8045) );
INVX2TS U8861 ( .A(n8046), .Y(n8048) );
NAND2X1TS U8862 ( .A(n8048), .B(n8047), .Y(n8049) );
XNOR2X1TS U8863 ( .A(n8050), .B(n8049), .Y(n8051) );
AOI22X1TS U8864 ( .A0(n8155), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n8052), .Y(n8053) );
OAI2BB1X1TS U8865 ( .A0N(n8054), .A1N(P_Sgf[63]), .B0(n8053), .Y(n8055) );
AOI21X1TS U8866 ( .A0(n8158), .A1(Add_result[10]), .B0(n8055), .Y(n8056) );
OAI2BB1X1TS U8867 ( .A0N(n8183), .A1N(P_Sgf[62]), .B0(n8056), .Y(n363) );
NOR2X1TS U8868 ( .A(n8097), .B(n8058), .Y(n8074) );
NAND2X1TS U8869 ( .A(n8074), .B(Sgf_normalized_result[8]), .Y(n8059) );
XOR2X1TS U8870 ( .A(n8059), .B(n8483), .Y(n8060) );
NAND2X1TS U8871 ( .A(n8065), .B(n8064), .Y(n8066) );
BUFX3TS U8872 ( .A(n8069), .Y(n8180) );
BUFX3TS U8873 ( .A(n8070), .Y(n8177) );
AOI22X1TS U8874 ( .A0(n8155), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n8177), .Y(n8071) );
OAI2BB1X1TS U8875 ( .A0N(n8180), .A1N(P_Sgf[62]), .B0(n8071), .Y(n8072) );
AOI21X1TS U8876 ( .A0(n8158), .A1(Add_result[9]), .B0(n8072), .Y(n8073) );
OAI2BB1X1TS U8877 ( .A0N(n8183), .A1N(P_Sgf[61]), .B0(n8073), .Y(n362) );
XNOR2X1TS U8878 ( .A(n8074), .B(n8460), .Y(n8075) );
NAND2X1TS U8879 ( .A(n8078), .B(n8077), .Y(n8079) );
XOR2X1TS U8880 ( .A(n8080), .B(n8079), .Y(n8081) );
AOI22X1TS U8881 ( .A0(n8155), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n8177), .Y(n8082) );
OAI2BB1X1TS U8882 ( .A0N(n8180), .A1N(P_Sgf[61]), .B0(n8082), .Y(n8083) );
AOI21X1TS U8883 ( .A0(n8158), .A1(Add_result[8]), .B0(n8083), .Y(n8084) );
OAI2BB1X1TS U8884 ( .A0N(n7899), .A1N(P_Sgf[60]), .B0(n8084), .Y(n361) );
XNOR2X1TS U8885 ( .A(n8085), .B(n8488), .Y(n8086) );
NAND2X1TS U8886 ( .A(n8090), .B(n8089), .Y(n8091) );
XNOR2X1TS U8887 ( .A(n8092), .B(n8091), .Y(n8093) );
AOI22X1TS U8888 ( .A0(n8155), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n8177), .Y(n8094) );
OAI2BB1X1TS U8889 ( .A0N(n8180), .A1N(P_Sgf[60]), .B0(n8094), .Y(n8095) );
AOI21X1TS U8890 ( .A0(n8158), .A1(Add_result[7]), .B0(n8095), .Y(n8096) );
OAI2BB1X1TS U8891 ( .A0N(n7545), .A1N(P_Sgf[59]), .B0(n8096), .Y(n360) );
XOR2X1TS U8892 ( .A(n8097), .B(n8468), .Y(n8098) );
INVX2TS U8893 ( .A(n8099), .Y(n8101) );
NAND2X1TS U8894 ( .A(n8101), .B(n8100), .Y(n8102) );
XNOR2X1TS U8895 ( .A(n8103), .B(n8102), .Y(n8104) );
AOI22X1TS U8896 ( .A0(n8155), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n8177), .Y(n8105) );
OAI2BB1X1TS U8897 ( .A0N(n8180), .A1N(P_Sgf[59]), .B0(n8105), .Y(n8106) );
AOI21X1TS U8898 ( .A0(n8158), .A1(Add_result[6]), .B0(n8106), .Y(n8107) );
OAI2BB1X1TS U8899 ( .A0N(n7545), .A1N(P_Sgf[58]), .B0(n8107), .Y(n359) );
XOR2X1TS U8900 ( .A(n8109), .B(Sgf_normalized_result[5]), .Y(n8110) );
INVX2TS U8901 ( .A(n8111), .Y(n8114) );
INVX2TS U8902 ( .A(n8112), .Y(n8113) );
AOI21X4TS U8903 ( .A0(n8346), .A1(n8114), .B0(n8113), .Y(n8139) );
INVX2TS U8904 ( .A(n8139), .Y(n8153) );
AOI21X2TS U8905 ( .A0(n8153), .A1(n8116), .B0(n8115), .Y(n8132) );
OAI21X1TS U8906 ( .A0(n8132), .A1(n8128), .B0(n8129), .Y(n8121) );
NAND2X1TS U8907 ( .A(n8119), .B(n8118), .Y(n8120) );
XNOR2X1TS U8908 ( .A(n8121), .B(n8120), .Y(n8122) );
CLKMX2X2TS U8909 ( .A(P_Sgf[57]), .B(n8122), .S0(n8133), .Y(n478) );
AOI22X1TS U8910 ( .A0(n8155), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n8177), .Y(n8123) );
OAI2BB1X1TS U8911 ( .A0N(n8180), .A1N(P_Sgf[58]), .B0(n8123), .Y(n8124) );
AOI21X1TS U8912 ( .A0(n8158), .A1(Add_result[5]), .B0(n8124), .Y(n8125) );
OAI2BB1X1TS U8913 ( .A0N(n7545), .A1N(P_Sgf[57]), .B0(n8125), .Y(n358) );
XNOR2X1TS U8914 ( .A(n8126), .B(Sgf_normalized_result[4]), .Y(n8127) );
NAND2X1TS U8915 ( .A(n8130), .B(n8129), .Y(n8131) );
XOR2X1TS U8916 ( .A(n8132), .B(n8131), .Y(n8134) );
AOI22X1TS U8917 ( .A0(n8155), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n8177), .Y(n8135) );
OAI2BB1X1TS U8918 ( .A0N(n8180), .A1N(P_Sgf[57]), .B0(n8135), .Y(n8136) );
AOI21X1TS U8919 ( .A0(n8158), .A1(Add_result[4]), .B0(n8136), .Y(n8137) );
OAI2BB1X1TS U8920 ( .A0N(n8183), .A1N(P_Sgf[56]), .B0(n8137), .Y(n357) );
XNOR2X1TS U8921 ( .A(n8489), .B(Sgf_normalized_result[2]), .Y(n8138) );
NAND2X1TS U8922 ( .A(n8142), .B(n8141), .Y(n8143) );
XNOR2X1TS U8923 ( .A(n8144), .B(n8143), .Y(n8145) );
AOI22X1TS U8924 ( .A0(n8155), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n8177), .Y(n8146) );
OAI2BB1X1TS U8925 ( .A0N(n8180), .A1N(P_Sgf[56]), .B0(n8146), .Y(n8147) );
AOI21X1TS U8926 ( .A0(n8158), .A1(Add_result[3]), .B0(n8147), .Y(n8148) );
OAI2BB1X1TS U8927 ( .A0N(n7545), .A1N(P_Sgf[55]), .B0(n8148), .Y(n356) );
NAND2X1TS U8928 ( .A(n8151), .B(n8150), .Y(n8152) );
XNOR2X1TS U8929 ( .A(n8153), .B(n8152), .Y(n8154) );
AOI22X1TS U8930 ( .A0(n8155), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n8177), .Y(n8156) );
OAI2BB1X1TS U8931 ( .A0N(n8180), .A1N(P_Sgf[55]), .B0(n8156), .Y(n8157) );
AOI21X1TS U8932 ( .A0(n8158), .A1(Add_result[2]), .B0(n8157), .Y(n8159) );
OAI2BB1X1TS U8933 ( .A0N(n8183), .A1N(P_Sgf[54]), .B0(n8159), .Y(n355) );
AOI21X2TS U8934 ( .A0(n8346), .A1(n8161), .B0(n8160), .Y(n8175) );
NAND2X1TS U8935 ( .A(n8164), .B(n8163), .Y(n8165) );
XNOR2X1TS U8936 ( .A(n8166), .B(n8165), .Y(n8167) );
AOI22X1TS U8937 ( .A0(n8178), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n8177), .Y(n8168) );
OAI2BB1X1TS U8938 ( .A0N(n8180), .A1N(P_Sgf[54]), .B0(n8168), .Y(n8169) );
AOI21X1TS U8939 ( .A0(n8039), .A1(Add_result[1]), .B0(n8169), .Y(n8170) );
OAI2BB1X1TS U8940 ( .A0N(n8183), .A1N(P_Sgf[53]), .B0(n8170), .Y(n354) );
INVX2TS U8941 ( .A(n8171), .Y(n8173) );
NAND2X1TS U8942 ( .A(n8173), .B(n8172), .Y(n8174) );
XOR2X1TS U8943 ( .A(n8175), .B(n8174), .Y(n8176) );
AOI22X1TS U8944 ( .A0(n8178), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n8177), .Y(n8179) );
OAI2BB1X1TS U8945 ( .A0N(n8180), .A1N(P_Sgf[53]), .B0(n8179), .Y(n8181) );
AOI21X1TS U8946 ( .A0(n8039), .A1(Add_result[0]), .B0(n8181), .Y(n8182) );
OAI2BB1X1TS U8947 ( .A0N(P_Sgf[52]), .A1N(n8183), .B0(n8182), .Y(n353) );
AHHCONX2TS U8948 ( .A(Sgf_normalized_result[52]), .CI(n8184), .CON(n8185),
.S(n7532) );
INVX2TS U8949 ( .A(n8185), .Y(n8187) );
OR2X1TS U8950 ( .A(n8193), .B(Sgf_operation_ODD1_Q_right[27]), .Y(n8195) );
CLKAND2X2TS U8951 ( .A(n8195), .B(n8194), .Y(n8196) );
NAND2X1TS U8952 ( .A(n986), .B(n8197), .Y(n8199) );
XNOR2X1TS U8953 ( .A(n8199), .B(n8198), .Y(n8200) );
NAND2X1TS U8954 ( .A(n781), .B(n8201), .Y(n8203) );
INVX2TS U8955 ( .A(n8202), .Y(n8206) );
XNOR2X1TS U8956 ( .A(n8203), .B(n8206), .Y(n8204) );
AOI21X1TS U8957 ( .A0(n8206), .A1(n781), .B0(n8205), .Y(n8209) );
NAND2X1TS U8958 ( .A(n731), .B(n8207), .Y(n8208) );
XOR2X1TS U8959 ( .A(n8209), .B(n8208), .Y(n8210) );
NAND2X1TS U8960 ( .A(n991), .B(n8211), .Y(n8212) );
XNOR2X1TS U8961 ( .A(n8213), .B(n8212), .Y(n8214) );
INVX2TS U8962 ( .A(n8215), .Y(n8220) );
NAND2X1TS U8963 ( .A(n987), .B(n8216), .Y(n8217) );
XNOR2X1TS U8964 ( .A(n8220), .B(n8217), .Y(n8218) );
AOI21X1TS U8965 ( .A0(n8220), .A1(n987), .B0(n8219), .Y(n8223) );
NAND2X1TS U8966 ( .A(n990), .B(n8221), .Y(n8222) );
XOR2X1TS U8967 ( .A(n8223), .B(n8222), .Y(n8225) );
INVX2TS U8968 ( .A(n8226), .Y(n8238) );
NAND2X1TS U8969 ( .A(n8227), .B(n8230), .Y(n8228) );
XOR2X1TS U8970 ( .A(n8238), .B(n8228), .Y(n8229) );
NAND2X1TS U8971 ( .A(n988), .B(n8232), .Y(n8233) );
XNOR2X1TS U8972 ( .A(n8234), .B(n8233), .Y(n8235) );
OAI21X1TS U8973 ( .A0(n8238), .A1(n8237), .B0(n8236), .Y(n8243) );
NAND2X1TS U8974 ( .A(n4284), .B(n8239), .Y(n8240) );
XNOR2X1TS U8975 ( .A(n8243), .B(n8240), .Y(n8241) );
AOI21X1TS U8976 ( .A0(n8243), .A1(n4284), .B0(n8242), .Y(n8246) );
NAND2X1TS U8977 ( .A(n989), .B(n8244), .Y(n8245) );
XOR2X1TS U8978 ( .A(n8246), .B(n8245), .Y(n8247) );
INVX2TS U8979 ( .A(n8248), .Y(n8309) );
INVX2TS U8980 ( .A(n8249), .Y(n8254) );
NAND2X1TS U8981 ( .A(n8254), .B(n8252), .Y(n8250) );
XNOR2X1TS U8982 ( .A(n8309), .B(n8250), .Y(n8251) );
INVX2TS U8983 ( .A(n8252), .Y(n8253) );
AOI21X1TS U8984 ( .A0(n8309), .A1(n8254), .B0(n8253), .Y(n8259) );
INVX2TS U8985 ( .A(n8255), .Y(n8257) );
NAND2X1TS U8986 ( .A(n8257), .B(n8256), .Y(n8258) );
XOR2X1TS U8987 ( .A(n8259), .B(n8258), .Y(n8260) );
OAI21X2TS U8988 ( .A0(n8305), .A1(n8263), .B0(n8262), .Y(n8272) );
INVX2TS U8989 ( .A(n8264), .Y(n8274) );
INVX2TS U8990 ( .A(n8273), .Y(n8265) );
AOI21X1TS U8991 ( .A0(n8272), .A1(n8274), .B0(n8265), .Y(n8270) );
NAND2X1TS U8992 ( .A(n8268), .B(n8267), .Y(n8269) );
XOR2X1TS U8993 ( .A(n8270), .B(n8269), .Y(n8271) );
INVX2TS U8994 ( .A(n8272), .Y(n8326) );
NAND2X1TS U8995 ( .A(n8274), .B(n8273), .Y(n8275) );
XOR2X1TS U8996 ( .A(n8326), .B(n8275), .Y(n8276) );
INVX2TS U8997 ( .A(n8278), .Y(n8279) );
OAI21X1TS U8998 ( .A0(n8305), .A1(n8280), .B0(n8279), .Y(n8292) );
INVX2TS U8999 ( .A(n8281), .Y(n8290) );
INVX2TS U9000 ( .A(n8289), .Y(n8282) );
AOI21X1TS U9001 ( .A0(n8292), .A1(n8290), .B0(n8282), .Y(n8287) );
NAND2X1TS U9002 ( .A(n8285), .B(n8284), .Y(n8286) );
XOR2X1TS U9003 ( .A(n8287), .B(n8286), .Y(n8288) );
NAND2X1TS U9004 ( .A(n8290), .B(n8289), .Y(n8291) );
XNOR2X1TS U9005 ( .A(n8292), .B(n8291), .Y(n8294) );
NAND2X1TS U9006 ( .A(n8297), .B(n8296), .Y(n8298) );
XNOR2X1TS U9007 ( .A(n8299), .B(n8298), .Y(n8300) );
NAND2X1TS U9008 ( .A(n8303), .B(n8302), .Y(n8304) );
XOR2X1TS U9009 ( .A(n8305), .B(n8304), .Y(n8306) );
AOI21X1TS U9010 ( .A0(n8309), .A1(n8308), .B0(n8307), .Y(n8320) );
NAND2X1TS U9011 ( .A(n8312), .B(n8311), .Y(n8313) );
XNOR2X1TS U9012 ( .A(n8314), .B(n8313), .Y(n8315) );
INVX2TS U9013 ( .A(n8316), .Y(n8318) );
NAND2X1TS U9014 ( .A(n8318), .B(n8317), .Y(n8319) );
XOR2X1TS U9015 ( .A(n8320), .B(n8319), .Y(n8321) );
INVX2TS U9016 ( .A(n8322), .Y(n8325) );
INVX2TS U9017 ( .A(n8323), .Y(n8324) );
INVX2TS U9018 ( .A(n8327), .Y(n8332) );
NAND2X1TS U9019 ( .A(n8332), .B(n8330), .Y(n8328) );
XNOR2X1TS U9020 ( .A(n8333), .B(n8328), .Y(n8329) );
INVX2TS U9021 ( .A(n8330), .Y(n8331) );
AOI21X1TS U9022 ( .A0(n8333), .A1(n8332), .B0(n8331), .Y(n8338) );
NAND2X1TS U9023 ( .A(n8336), .B(n8335), .Y(n8337) );
XOR2X1TS U9024 ( .A(n8338), .B(n8337), .Y(n8339) );
INVX2TS U9025 ( .A(n8340), .Y(n8345) );
NAND2X1TS U9026 ( .A(n8345), .B(n8343), .Y(n8341) );
XNOR2X1TS U9027 ( .A(n8346), .B(n8341), .Y(n8342) );
INVX2TS U9028 ( .A(n8343), .Y(n8344) );
AOI21X1TS U9029 ( .A0(n8346), .A1(n8345), .B0(n8344), .Y(n8351) );
NAND2X1TS U9030 ( .A(n8349), .B(n8348), .Y(n8350) );
XOR2X1TS U9031 ( .A(n8351), .B(n8350), .Y(n8352) );
NAND2X1TS U9032 ( .A(n8427), .B(n8471), .Y(n710) );
NOR2BX1TS U9033 ( .AN(exp_oper_result[11]), .B(n8471), .Y(S_Oper_A_exp[11])
);
CLKMX2X2TS U9034 ( .A(Op_MX[57]), .B(exp_oper_result[5]), .S0(n847), .Y(
S_Oper_A_exp[5]) );
CLKMX2X2TS U9035 ( .A(Op_MX[53]), .B(exp_oper_result[1]), .S0(n846), .Y(
S_Oper_A_exp[1]) );
NAND4BX1TS U9036 ( .AN(n8356), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n8357) );
NAND4BX1TS U9037 ( .AN(n8357), .B(Exp_module_Data_S[9]), .C(
Exp_module_Data_S[8]), .D(Exp_module_Data_S[7]), .Y(n8358) );
NAND3BX1TS U9038 ( .AN(Exp_module_Data_S[10]), .B(n8430), .C(n8358), .Y(
n8359) );
OAI22X1TS U9039 ( .A0(Exp_module_Data_S[11]), .A1(n8359), .B0(n8430), .B1(
n8491), .Y(n352) );
AO22X1TS U9040 ( .A0(n8360), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n8364), .Y(n349) );
AO22X1TS U9041 ( .A0(n8439), .A1(Sgf_normalized_result[23]), .B0(
final_result_ieee[23]), .B1(n8364), .Y(n328) );
AO22X1TS U9042 ( .A0(n8439), .A1(Sgf_normalized_result[24]), .B0(
final_result_ieee[24]), .B1(n8364), .Y(n327) );
AO22X1TS U9043 ( .A0(n8439), .A1(Sgf_normalized_result[25]), .B0(
final_result_ieee[25]), .B1(n8364), .Y(n326) );
AO22X1TS U9044 ( .A0(n8439), .A1(Sgf_normalized_result[26]), .B0(
final_result_ieee[26]), .B1(n8364), .Y(n325) );
AO22X1TS U9045 ( .A0(n8439), .A1(Sgf_normalized_result[27]), .B0(
final_result_ieee[27]), .B1(n8364), .Y(n324) );
AO22X1TS U9046 ( .A0(n8439), .A1(Sgf_normalized_result[28]), .B0(
final_result_ieee[28]), .B1(n8364), .Y(n323) );
AO22X1TS U9047 ( .A0(n8439), .A1(Sgf_normalized_result[29]), .B0(
final_result_ieee[29]), .B1(n8364), .Y(n322) );
AO22X1TS U9048 ( .A0(n8439), .A1(Sgf_normalized_result[30]), .B0(
final_result_ieee[30]), .B1(n8364), .Y(n321) );
AO22X1TS U9049 ( .A0(n8365), .A1(Data_MY[63]), .B0(n7504), .B1(Op_MY[63]),
.Y(n715) );
AOI21X1TS U9050 ( .A0(FS_Module_state_reg[2]), .A1(n8367), .B0(n8366), .Y(
n8370) );
NOR4X1TS U9051 ( .A(n830), .B(n855), .C(n902), .D(n5213), .Y(n8380) );
NOR4X1TS U9052 ( .A(Op_MY[34]), .B(Op_MY[33]), .C(n852), .D(n849), .Y(n8379)
);
NAND4XLTS U9053 ( .A(n8381), .B(n8380), .C(n8379), .D(n807), .Y(n8401) );
NOR4X1TS U9054 ( .A(Op_MY[19]), .B(Op_MY[15]), .C(Op_MY[13]), .D(Op_MY[10]),
.Y(n8384) );
NOR4X1TS U9055 ( .A(Op_MY[24]), .B(Op_MY[18]), .C(Op_MY[9]), .D(Op_MY[7]),
.Y(n8383) );
NOR4X1TS U9056 ( .A(Op_MY[12]), .B(Op_MY[6]), .C(Op_MY[1]), .D(Op_MY[4]),
.Y(n8382) );
NAND4XLTS U9057 ( .A(n8384), .B(n8383), .C(n8382), .D(n810), .Y(n8400) );
NOR4X1TS U9058 ( .A(Op_MY[38]), .B(Op_MY[37]), .C(Op_MY[36]), .D(n832), .Y(
n8390) );
NOR4X1TS U9059 ( .A(Op_MY[42]), .B(Op_MY[41]), .C(Op_MY[40]), .D(n828), .Y(
n8389) );
NOR4X1TS U9060 ( .A(Op_MY[46]), .B(Op_MY[45]), .C(Op_MY[44]), .D(n840), .Y(
n8388) );
NOR4X1TS U9061 ( .A(n8386), .B(Op_MY[49]), .C(Op_MY[48]), .D(Op_MY[47]), .Y(
n8387) );
NAND4XLTS U9062 ( .A(n8390), .B(n8389), .C(n8388), .D(n8387), .Y(n8399) );
NOR4X1TS U9063 ( .A(Op_MY[57]), .B(Op_MY[56]), .C(Op_MY[55]), .D(Op_MY[54]),
.Y(n8397) );
NOR4X1TS U9064 ( .A(Op_MY[61]), .B(Op_MY[60]), .C(Op_MY[59]), .D(Op_MY[58]),
.Y(n8396) );
NAND4XLTS U9065 ( .A(n8397), .B(n8396), .C(n8395), .D(n8394), .Y(n8398) );
OR4X2TS U9066 ( .A(n8401), .B(n8400), .C(n8399), .D(n8398), .Y(n8431) );
NOR4X1TS U9067 ( .A(Op_MX[24]), .B(Op_MX[23]), .C(Op_MX[22]), .D(n8402), .Y(
n8406) );
NAND4XLTS U9068 ( .A(n8407), .B(n8406), .C(n777), .D(n8405), .Y(n8426) );
NOR4X1TS U9069 ( .A(Op_MX[49]), .B(Op_MX[43]), .C(Op_MX[31]), .D(Op_MX[33]),
.Y(n8411) );
NOR4X1TS U9070 ( .A(Op_MX[48]), .B(Op_MX[42]), .C(Op_MX[30]), .D(Op_MX[37]),
.Y(n8410) );
NOR4X1TS U9071 ( .A(Op_MX[46]), .B(Op_MX[40]), .C(Op_MX[28]), .D(Op_MX[36]),
.Y(n8409) );
NAND4XLTS U9072 ( .A(n8411), .B(n8410), .C(n8409), .D(n8408), .Y(n8425) );
NOR4X1TS U9073 ( .A(Op_MX[19]), .B(n8412), .C(Op_MX[4]), .D(Op_MX[0]), .Y(
n8418) );
NOR4X1TS U9074 ( .A(Op_MX[17]), .B(Op_MX[13]), .C(Op_MX[10]), .D(n8413), .Y(
n8417) );
NOR4X1TS U9075 ( .A(Op_MX[15]), .B(Op_MX[12]), .C(Op_MX[5]), .D(Op_MX[3]),
.Y(n8416) );
NOR4X1TS U9076 ( .A(Op_MX[11]), .B(n842), .C(Op_MX[7]), .D(n8414), .Y(n8415)
);
NAND4XLTS U9077 ( .A(n8418), .B(n8417), .C(n8416), .D(n8415), .Y(n8424) );
NOR4X1TS U9078 ( .A(Op_MX[57]), .B(Op_MX[56]), .C(Op_MX[55]), .D(Op_MX[54]),
.Y(n8422) );
NOR4X1TS U9079 ( .A(Op_MX[61]), .B(Op_MX[60]), .C(Op_MX[59]), .D(Op_MX[58]),
.Y(n8421) );
NAND4XLTS U9080 ( .A(n8422), .B(n8421), .C(n8420), .D(n8419), .Y(n8423) );
OR4X2TS U9081 ( .A(n8426), .B(n8425), .C(n8424), .D(n8423), .Y(n8429) );
AOI32X1TS U9082 ( .A0(n8431), .A1(n8430), .A2(n8429), .B0(n8428), .B1(n8427),
.Y(n581) );
INVX2TS U9083 ( .A(n8443), .Y(n8438) );
OA22X1TS U9084 ( .A0(n8441), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n8440), .Y(n299) );
OA22X1TS U9085 ( .A0(n8441), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n8440), .Y(n297) );
OA22X1TS U9086 ( .A0(n8441), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n8440), .Y(n296) );
OA22X1TS U9087 ( .A0(n8441), .A1(final_result_ieee[56]), .B0(
exp_oper_result[4]), .B1(n8440), .Y(n295) );
OA22X1TS U9088 ( .A0(n8443), .A1(final_result_ieee[61]), .B0(
exp_oper_result[9]), .B1(n8442), .Y(n290) );
OA22X1TS U9089 ( .A0(n8443), .A1(final_result_ieee[62]), .B0(
exp_oper_result[10]), .B1(n8442), .Y(n289) );
CMPR42X1TS U9090 ( .A(mult_x_24_n1087), .B(mult_x_24_n703), .C(
mult_x_24_n1428), .D(mult_x_24_n1401), .ICI(mult_x_24_n700), .S(
mult_x_24_n698), .ICO(mult_x_24_n696), .CO(mult_x_24_n697) );
initial $sdf_annotate("FPU_Multiplication_Function_KOA_1STAGE_syn.sdf");
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbspiflash.v
//
// Project: A Set of Wishbone Controlled SPI Flash Controllers
//
// Purpose: Access a Quad SPI flash via a WISHBONE interface. This
// includes both read and write (and erase) commands to the SPI
// flash. All read/write commands are accomplished using the
// high speed (4-bit) interface. Further, the device will be
// left/kept in the 4-bit read interface mode between accesses,
// for a minimum read latency.
//
// Wishbone Registers (See spec sheet for more detail):
// 0: local config(r) / erase commands(w) / deep power down cmds / etc.
// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
// { last_erased_sector, 14'h00 } if (WIP)
// else { current_sector_being_erased, 14'h00 }
// current if write in progress, last if written
// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
// 1: Configuration register
// 2: Status register (R/w)
// 3: Read ID (read only)
// (19 bits): Data (R/w, but expect writes to take a while)
//
// This core has been deprecated. All of my new projects are using one of
// my universal flash controllers now: qflexpress, dualflexpress, or spixpress.
// These can be found in my https://github.com/ZipCPU/qspiflash repository.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
//
// This file is part of the set of Wishbone controlled SPI flash controllers
// project
//
// The Wishbone SPI flash controller project is free software (firmware):
// you can redistribute it and/or modify it under the terms of the GNU Lesser
// General Public License as published by the Free Software Foundation, either
// version 3 of the License, or (at your option) any later version.
//
// The Wishbone SPI flash controller project is distributed in the hope
// that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this program. (It's in the $(ROOT)/doc directory. Run make
// with no target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: LGPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/lgpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
//
`default_nettype none
//
`define WBQSPI_RESET 5'd0
`define WBQSPI_RESET_QUADMODE 5'd1
`define WBQSPI_IDLE 5'd2
`define WBQSPI_RDIDLE 5'd3 // Idle, but in fast read mode
`define WBQSPI_WBDECODE 5'd4
`define WBQSPI_RD_DUMMY 5'd5
`define WBQSPI_QRD_ADDRESS 5'd6
`define WBQSPI_QRD_DUMMY 5'd7
`define WBQSPI_READ_CMD 5'd8
`define WBQSPI_READ_DATA 5'd9
`define WBQSPI_WAIT_TIL_RDIDLE 5'd10
`define WBQSPI_READ_ID_CMD 5'd11
`define WBQSPI_READ_ID 5'd12
`define WBQSPI_READ_STATUS 5'd13
`define WBQSPI_READ_CONFIG 5'd14
`define WBQSPI_WAIT_TIL_IDLE 5'd15
//
//
`define WBQSPI_WAIT_WIP_CLEAR 5'd16
`define WBQSPI_CHECK_WIP_CLEAR 5'd17
`define WBQSPI_CHECK_WIP_DONE 5'd18
`define WBQSPI_WEN 5'd19
`define WBQSPI_PP 5'd20 // Program page
`define WBQSPI_QPP 5'd21 // Program page, 4 bit mode
`define WBQSPI_WR_DATA 5'd22
`define WBQSPI_WR_BUS_CYCLE 5'd23
`define WBQSPI_WRITE_STATUS 5'd24
`define WBQSPI_WRITE_CONFIG 5'd25
`define WBQSPI_ERASE_WEN 5'd26
`define WBQSPI_ERASE_CMD 5'd27
`define WBQSPI_ERASE_BLOCK 5'd28
`define WBQSPI_CLEAR_STATUS 5'd29
`define WBQSPI_IDLE_CHECK_WIP 5'd30
//
module wbqspiflash(i_clk,
// Internal wishbone connections
i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
i_wb_addr, i_wb_data,
// Wishbone return values
o_wb_ack, o_wb_stall, o_wb_data,
// Quad Spi connections to the external device
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
o_interrupt);
parameter ADDRESS_WIDTH=22;
parameter [0:0] OPT_READ_ONLY = 1'b0;
localparam AW = ADDRESS_WIDTH-2;
input wire i_clk;
// Wishbone, inputs first
input wire i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
input wire [(AW-1):0] i_wb_addr;
input wire [31:0] i_wb_data;
// then outputs
output reg o_wb_ack;
output reg o_wb_stall;
output reg [31:0] o_wb_data;
// Quad SPI control wires
output wire o_qspi_sck, o_qspi_cs_n;
output wire [1:0] o_qspi_mod;
output wire [3:0] o_qspi_dat;
input wire [3:0] i_qspi_dat;
// Interrupt line
output reg o_interrupt;
// output wire [31:0] o_debug;
reg spi_wr, spi_hold, spi_spd, spi_dir;
reg [31:0] spi_in;
reg [1:0] spi_len;
wire [31:0] spi_out;
wire spi_valid, spi_busy;
wire w_qspi_sck, w_qspi_cs_n;
wire [3:0] w_qspi_dat;
wire [1:0] w_qspi_mod;
// wire [22:0] spi_dbg;
llqspi lldriver(i_clk,
spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
spi_out, spi_valid, spi_busy,
w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
i_qspi_dat);
// Erase status tracking
reg write_in_progress, write_protect;
reg [(ADDRESS_WIDTH-17):0] erased_sector;
reg dirty_sector;
initial begin
write_in_progress = 1'b0;
erased_sector = 0;
dirty_sector = 1'b1;
write_protect = 1'b1;
end
wire [23:0] w_wb_addr;
generate
if (ADDRESS_WIDTH>=24)
assign w_wb_addr = { i_wb_addr[21:0], 2'b00 };
else
assign w_wb_addr = { {(24-ADDRESS_WIDTH){1'b0}}, i_wb_addr, 2'b00 };
endgenerate
// Repeat for spif_addr
reg [(ADDRESS_WIDTH-3):0] spif_addr;
wire [23:0] w_spif_addr;
generate
if (ADDRESS_WIDTH>=24)
assign w_spif_addr = { spif_addr[21:0], 2'b00 };
else
assign w_spif_addr = { {(24-ADDRESS_WIDTH){1'b0}}, spif_addr, 2'b00 };
endgenerate
reg [7:0] last_status;
reg [9:0] reset_counter;
reg quad_mode_enabled;
reg spif_cmd, spif_override;
reg [31:0] spif_data;
reg [4:0] state;
reg spif_ctrl, spif_req;
reg alt_cmd, alt_ctrl;
wire [(ADDRESS_WIDTH-17):0] spif_sector;
assign spif_sector = spif_addr[(AW-1):14];
// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
initial state = `WBQSPI_RESET;
initial o_wb_ack = 1'b0;
initial o_wb_stall = 1'b1;
initial spi_wr = 1'b0;
initial spi_len = 2'b00;
initial quad_mode_enabled = 1'b0;
initial o_interrupt = 1'b0;
initial spif_override = 1'b1;
initial spif_ctrl = 1'b0;
always @(posedge i_clk)
begin
spif_override <= 1'b0;
alt_cmd <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n
alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too
if (state == `WBQSPI_RESET)
begin
// From a reset, we should
// Enable the Quad I/O mode
// Disable the Write protection bits in the status register
// Chip should already be up and running, so we can start
// immediately ....
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_wr <= 1'b0;
spi_hold <= 1'b0;
spi_spd <= 1'b0;
spi_dir <= 1'b0;
last_status <= 8'h00;
state <= `WBQSPI_RESET_QUADMODE;
spif_req <= 1'b0;
spif_override <= 1'b1;
last_status <= 8'h00; //
reset_counter <= 10'h3fc; //
// This guarantees that we aren't starting in quad
// I/O mode, where the FPGA configuration scripts may
// have left us.
end else if (state == `WBQSPI_RESET_QUADMODE)
begin
// Okay, so here's the problem: we don't know whether or not
// the Xilinx loader started us up in Quad Read I/O idle mode.
// So, thus we need to toggle the clock and CS_n, with fewer
// clocks than are necessary to transmit a word.
//
// Not ready to handle the bus yet, so stall any requests
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
// Do something ...
if (reset_counter == 10'h00)
begin
spif_override <= 1'b0;
state <= `WBQSPI_IDLE;
// Find out if we can use Quad I/O mode ...
state <= `WBQSPI_READ_CONFIG;
spi_wr <= 1'b1;
spi_len <= 2'b01;
spi_in <= { 8'h35, 24'h00};
end else begin
reset_counter <= reset_counter - 10'h1;
spif_override <= 1'b1;
end
end else if (state == `WBQSPI_IDLE)
begin
o_interrupt <= 1'b0;
o_wb_stall <= 1'b0;
o_wb_ack <= 1'b0;
spif_cmd <= i_wb_we;
spif_addr <= i_wb_addr;
spif_data <= i_wb_data;
spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
spi_hold <= 1'b0;
spi_spd <= 1'b0;
spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
// Data register access
if (i_wb_data_stb)
begin
if ((OPT_READ_ONLY)&&(i_wb_we)) // Write request
begin
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
end else if (i_wb_we) // Request to write a page
begin
if((!write_protect)&&(!write_in_progress))
begin // 00
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_WEN;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end else if (write_protect)
begin // whether or not write-in_progress ...
// Do nothing on a write protect
// violation
//
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
end else begin // write is in progress, wait
// for it to complete
state <= `WBQSPI_WAIT_WIP_CLEAR;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
end else if (!write_in_progress)
begin // Read access, normal mode(s)
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_wr <= 1'b1; // Write cmd to device
if (quad_mode_enabled)
begin
spi_in <= { 8'heb, w_wb_addr };
state <= `WBQSPI_QRD_ADDRESS;
spi_len <= 2'b00; // single byte, cmd only
end else begin
spi_in <= { 8'h0b, w_wb_addr };
state <= `WBQSPI_RD_DUMMY;
spi_len <= 2'b11; // cmd+addr,32bits
end
end else if (!OPT_READ_ONLY) begin
// A write is in progress ... need to stall
// the bus until the write is complete.
state <= `WBQSPI_WAIT_WIP_CLEAR;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
end else if ((OPT_READ_ONLY)&&(i_wb_ctrl_stb)&&(i_wb_we))
begin
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
end else if ((i_wb_ctrl_stb)&&(i_wb_we))
begin
o_wb_stall <= 1'b1;
case(i_wb_addr[1:0])
2'b00: begin // Erase command register
write_protect <= !i_wb_data[28];
o_wb_stall <= 1'b0;
if((i_wb_data[31])&&(!write_in_progress))
begin
// Command an erase--ack it immediately
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
if ((i_wb_data[31])&&(!write_protect))
begin
spi_wr <= 1'b1;
spi_len <= 2'b00;
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_ERASE_CMD;
o_wb_stall <= 1'b1;
end
end else if (i_wb_data[31])
begin
state <= `WBQSPI_WAIT_WIP_CLEAR;
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b1;
end else begin
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
end end
2'b01: begin
// Write the configuration register
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b1;
// Need to send a write enable command first
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_WRITE_CONFIG;
end
2'b10: begin
// Write the status register
o_wb_ack <= 1'b1; // Ack immediately
o_wb_stall <= 1'b1; // Stall other cmds
// Need to send a write enable command first
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_WRITE_STATUS;
end
2'b11: begin // Write the ID register??? makes no sense
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
end
endcase
end else if (i_wb_ctrl_stb) // &&(!i_wb_we))
begin
case(i_wb_addr[1:0])
2'b00: begin // Read local register
if (write_in_progress) // Read status
begin// register, is write still in progress?
state <= `WBQSPI_READ_STATUS;
spi_wr <= 1'b1;
spi_len <= 2'b01;// 8 bits out, 8 bits in
spi_in <= { 8'h05, 24'h00};
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end else begin // Return w/o talking to device
o_wb_ack <= 1'b1;
o_wb_stall <= 1'b0;
o_wb_data <= { write_in_progress,
dirty_sector, spi_busy,
~write_protect,
quad_mode_enabled,
{(29-ADDRESS_WIDTH){1'b0}},
erased_sector, 14'h000 };
end end
2'b01: begin // Read configuration register
state <= `WBQSPI_READ_CONFIG;
spi_wr <= 1'b1;
spi_len <= 2'b01;
spi_in <= { 8'h35, 24'h00};
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
2'b10: begin // Read status register
state <= `WBQSPI_READ_STATUS;
spi_wr <= 1'b1;
spi_len <= 2'b01; // 8 bits out, 8 bits in
spi_in <= { 8'h05, 24'h00};
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
2'b11: begin // Read ID register
state <= `WBQSPI_READ_ID_CMD;
spi_wr <= 1'b1;
spi_len <= 2'b00;
spi_in <= { 8'h9f, 24'h00};
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
endcase
end else if ((!OPT_READ_ONLY)&&(!i_wb_cyc)&&(write_in_progress))
begin
state <= `WBQSPI_IDLE_CHECK_WIP;
spi_wr <= 1'b1;
spi_len <= 2'b01; // 8 bits out, 8 bits in
spi_in <= { 8'h05, 24'h00};
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
end else if (state == `WBQSPI_RDIDLE)
begin
spi_wr <= 1'b0;
o_wb_stall <= 1'b0;
o_wb_ack <= 1'b0;
spif_cmd <= i_wb_we;
spif_addr <= i_wb_addr;
spif_data <= i_wb_data;
spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
spi_hold <= 1'b0;
spi_spd<= 1'b1;
spi_dir <= 1'b0; // Write (for now)
if ((i_wb_data_stb)&&(!i_wb_we))
begin // Continue our read ... send the new address / mode
o_wb_stall <= 1'b1;
spi_wr <= 1'b1;
spi_len <= 2'b10; // Write address, but not mode byte
spi_in <= { w_wb_addr, 8'ha0 };
state <= `WBQSPI_QRD_DUMMY;
end else if((i_wb_ctrl_stb)&&(!i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
begin
// A local read that doesn't touch the device, so leave
// the device in its current state
o_wb_stall <= 1'b0;
o_wb_ack <= 1'b1;
o_wb_data <= { write_in_progress,
dirty_sector, spi_busy,
~write_protect,
quad_mode_enabled,
{(29-ADDRESS_WIDTH){1'b0}},
erased_sector, 14'h000 };
end else if(((i_wb_ctrl_stb)||(i_wb_data_stb)))
begin // Need to release the device from quad mode for all else
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_wr <= 1'b1;
spi_len <= 2'b11;
spi_in <= 32'h00;
state <= `WBQSPI_WBDECODE;
end
end else if (state == `WBQSPI_WBDECODE)
begin
// We were in quad SPI read mode, and had to get out.
// Now we've got a command (not data read) to read and
// execute. Accomplish what we would've done while in the
// IDLE state here, save only that we don't have to worry
// about data reads, and we need to operate on a stored
// version of the bus command
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
spi_hold <= 1'b0;
spi_spd <= 1'b0;
spi_dir <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // only in full idle ...
begin
// Data register access
if (!spif_ctrl)
begin
if ((OPT_READ_ONLY)&&(spif_cmd)) // Request to write a page
begin
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
state <= `WBQSPI_IDLE;
end else if (spif_cmd)
begin
if((!write_protect)&&(!write_in_progress))
begin // 00
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_WEN;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end else if (write_protect)
begin // whether or not write-in_progress ...
// Do nothing on a write protect
// violation
//
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
state <= `WBQSPI_IDLE;
end else begin // write is in progress, wait
// for it to complete
state <= `WBQSPI_WAIT_WIP_CLEAR;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
// end else if (!write_in_progress) // always true
// but ... we wouldn't get here on a normal read access
end else begin
// Something's wrong, we should never
// get here
// Attempt to go to idle to recover
state <= `WBQSPI_IDLE;
end
end else if ((OPT_READ_ONLY)&&(spif_ctrl)&&(spif_cmd))
begin
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
state <= `WBQSPI_IDLE;
end else if ((spif_ctrl)&&(spif_cmd)) begin
o_wb_stall <= 1'b1;
case(spif_addr[1:0])
2'b00: begin // Erase command register
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
state <= `WBQSPI_IDLE;
write_protect <= ~spif_data[28];
// Are we commanding an erase?
// We're in read mode, writes cannot
// be in progress, so ...
if (spif_data[31]) // Command an erase
begin
// Since we're not going back
// to IDLE, we must stall the
// bus here
o_wb_stall <= 1'b1;
spi_wr <= 1'b1;
spi_len <= 2'b00;
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_ERASE_CMD;
end end
2'b01: begin
// Write the configuration register
o_wb_ack <= spif_req;
o_wb_stall <= 1'b1;
// Need to send a write enable command first
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_WRITE_CONFIG;
end
2'b10: begin
// Write the status register
o_wb_ack <= spif_req; // Ack immediately
o_wb_stall <= 1'b1; // Stall other cmds
// Need to send a write enable command first
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_WRITE_STATUS;
end
2'b11: begin // Write the ID register??? makes no sense
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
state <= `WBQSPI_IDLE;
end
endcase
end else begin // on (!spif_we)
case(spif_addr[1:0])
2'b00: begin // Read local register
// Nonsense case--would've done this
// already
state <= `WBQSPI_IDLE;
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
end
2'b01: begin // Read configuration register
state <= `WBQSPI_READ_CONFIG;
spi_wr <= 1'b1;
spi_len <= 2'b01;
spi_in <= { 8'h35, 24'h00};
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
2'b10: begin // Read status register
state <= `WBQSPI_READ_STATUS;
spi_wr <= 1'b1;
spi_len <= 2'b01; // 8 bits out, 8 bits in
spi_in <= { 8'h05, 24'h00};
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
2'b11: begin // Read ID register
state <= `WBQSPI_READ_ID_CMD;
spi_wr <= 1'b1;
spi_len <= 2'b00;
spi_in <= { 8'h9f, 24'h00};
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
endcase
end
end
//
//
// READ DATA section: for both data and commands
//
end else if (state == `WBQSPI_RD_DUMMY)
begin
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_wr <= 1'b1; // Non-stop
// Need to read one byte of dummy data,
// just to consume 8 clocks
spi_in <= { 8'h00, 24'h00 };
spi_len <= 2'b00; // Read 8 bits
spi_spd <= 1'b0;
spi_hold <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((!spi_busy)&&(!o_qspi_cs_n))
// Our command was accepted
state <= `WBQSPI_READ_CMD;
end else if (state == `WBQSPI_QRD_ADDRESS)
begin
// We come in here immediately upon issuing a QRD read
// command (8-bits), but we have to pause to give the
// address (24-bits) and mode (8-bits) in quad speed.
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_wr <= 1'b1; // Non-stop
spi_in <= { w_spif_addr, 8'ha0 };
spi_len <= 2'b10; // Write address, not mode byte
spi_spd <= 1'b1;
spi_dir <= 1'b0; // Still writing
spi_hold <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((!spi_busy)&&(spi_spd))
// Our command was accepted
state <= `WBQSPI_QRD_DUMMY;
end else if (state == `WBQSPI_QRD_DUMMY)
begin
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_wr <= 1'b1; // Non-stop
spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
spi_len <= 2'b10; // Write 24 bits
spi_spd <= 1'b1;
spi_dir <= 1'b0; // Still writing
spi_hold <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((!spi_busy)&&(spi_in[31:28] == 4'ha))
// Our command was accepted
state <= `WBQSPI_READ_CMD;
end else if (state == `WBQSPI_READ_CMD)
begin // Issue our first command to read 32 bits.
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_wr <= 1'b1;
spi_in <= { 8'hff, 24'h00 }; // Empty
spi_len <= 2'b11; // Read 32 bits
spi_dir <= 1'b1; // Now reading
spi_hold <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((spi_valid)&&(spi_len == 2'b11))
state <= `WBQSPI_READ_DATA;
end else if (state == `WBQSPI_READ_DATA)
begin
// Pipelined read support
spi_wr <=((i_wb_data_stb)&&(!i_wb_we)&&(i_wb_addr== (spif_addr+1)))&&(spif_req);
spi_in <= 32'h00;
spi_len <= 2'b11;
// Don't adjust the speed here, it was set in the setup
spi_dir <= 1'b1; // Now we get to read
// Don't let the device go to idle until the bus cycle ends.
// This actually prevents a *really* nasty race condition,
// where the strobe comes in after the lower level device
// has decided to stop waiting. The write is then issued,
// but no one is listening. By leaving the device open,
// the device is kept in a state where a valid strobe
// here will be useful. Of course, we don't accept
// all commands, just reads. Further, the strobe needs
// to be high for two clocks cycles without changing
// anything on the bus--one for us to notice it and pull
// our head out of the sand, and a second for whoever
// owns the bus to realize their command went through.
spi_hold <= 1'b1;
spif_req<= (spif_req) && (i_wb_cyc);
if ((spi_valid)&&(!spi_in[31]))
begin // Single pulse acknowledge and write data out
o_wb_ack <= spif_req;
o_wb_stall <= (!spi_wr);
// adjust endian-ness to match the PC
o_wb_data <= spi_out;
state <= (spi_wr)?`WBQSPI_READ_DATA
: ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
spif_req <= spi_wr;
spi_hold <= (!spi_wr);
if (spi_wr)
spif_addr <= i_wb_addr;
end else if ((!spif_req)||(!i_wb_cyc))
begin // FAIL SAFE: If the bus cycle ends, forget why we're
// here, just go back to idle
state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
spi_hold <= 1'b0;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end else begin
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
end
end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
begin // Wait 'til idle, but then go to fast read idle instead of full
spi_wr <= 1'b0; // idle
spi_hold <= 1'b0;
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spif_req <= 1'b0;
if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Wait for a full
begin // clearing of the SPI port before moving on
state <= `WBQSPI_RDIDLE;
o_wb_stall <= 1'b0;
o_wb_ack <= 1'b0;// Shouldn't be acking anything here
end
end else if (state == `WBQSPI_READ_ID_CMD)
begin // We came into here immediately after issuing a 0x9f command
// Now we need to read 32 bits of data. Result should be
// 0x0102154d (8'h manufacture ID, 16'h device ID, followed
// by the number of extended bytes available 8'h4d).
o_wb_ack <= 1'b0;
o_wb_stall<= 1'b1;
spi_wr <= 1'b1; // No data to send, but need four bytes, since
spi_len <= 2'b11; // 32 bits of data are ... useful
spi_in <= 32'h00; // Irrelevant
spi_spd <= 1'b0; // Slow speed
spi_dir <= 1'b1; // Reading
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
if ((!spi_busy)&&(!o_qspi_cs_n)&&(spi_len == 2'b11))
// Our command was accepted, now go read the result
state <= `WBQSPI_READ_ID;
end else if (state == `WBQSPI_READ_ID)
begin
o_wb_ack <= 1'b0; // Assuming we're still waiting
o_wb_stall <= 1'b1;
spi_wr <= 1'b0; // No more writes, we've already written the cmd
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
// Here, we just wait until the result comes back
// The problem is, the result may be the previous result.
// So we use spi_len as an indicator
spi_len <= 2'b00;
if((spi_valid)&&(spi_len==2'b00))
begin // Put the results out as soon as possible
o_wb_data <= spi_out[31:0];
o_wb_ack <= spif_req;
spif_req <= 1'b0;
end else if ((!spi_busy)&&(o_qspi_cs_n))
begin
state <= `WBQSPI_IDLE;
o_wb_stall <= 1'b0;
end
end else if (state == `WBQSPI_READ_STATUS)
begin // We enter after the command has been given, for now just
// read and return
spi_wr <= 1'b0;
o_wb_ack <= 1'b0;
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
if (spi_valid)
begin
o_wb_ack <= spif_req;
o_wb_stall <= 1'b1;
spif_req <= 1'b0;
last_status <= spi_out[7:0];
write_in_progress <= spi_out[0];
if (spif_addr[1:0] == 2'b00) // Local read, checking
begin // status, 'cause we're writing
o_wb_data <= { spi_out[0],
dirty_sector, spi_busy,
~write_protect,
quad_mode_enabled,
{(29-ADDRESS_WIDTH){1'b0}},
erased_sector, 14'h000 };
end else begin
o_wb_data <= { 24'h00, spi_out[7:0] };
end
end
if ((!spi_busy)&&(!spi_wr))
state <= `WBQSPI_IDLE;
end else if (state == `WBQSPI_READ_CONFIG)
begin // We enter after the command has been given, for now just
// read and return
spi_wr <= 1'b0;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
if (spi_valid)
begin
o_wb_data <= { 24'h00, spi_out[7:0] };
quad_mode_enabled <= spi_out[1];
end
if ((!spi_busy)&&(!spi_wr))
begin
state <= `WBQSPI_IDLE;
o_wb_ack <= spif_req;
o_wb_stall <= 1'b0;
spif_req <= 1'b0;
end
//
//
// Write/erase data section
//
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WAIT_WIP_CLEAR))
begin
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spi_wr <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if (!spi_busy)
begin
spi_wr <= 1'b1;
spi_in <= { 8'h05, 24'h0000 };
spi_hold <= 1'b1;
spi_len <= 2'b01; // 16 bits write, so we can read 8
state <= `WBQSPI_CHECK_WIP_CLEAR;
spi_spd <= 1'b0; // Slow speed
spi_dir <= 1'b0;
end
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CHECK_WIP_CLEAR))
begin
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
// Repeat as often as necessary until we are clear
spi_wr <= 1'b1;
spi_in <= 32'h0000; // Values here are actually irrelevant
spi_hold <= 1'b1;
spi_len <= 2'b00; // One byte at a time
spi_spd <= 1'b0; // Slow speed
spi_dir <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((spi_valid)&&(!spi_out[0]))
begin
state <= `WBQSPI_CHECK_WIP_DONE;
spi_wr <= 1'b0;
spi_hold <= 1'b0;
write_in_progress <= 1'b0;
last_status <= spi_out[7:0];
end
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CHECK_WIP_DONE))
begin
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
// Let's let the SPI port come back to a full idle,
// and the chip select line go low before continuing
spi_wr <= 1'b0;
spi_len <= 2'b00;
spi_hold <= 1'b0;
spi_spd <= 1'b0; // Slow speed
spi_dir <= 1'b0;
spif_req<= (spif_req) && (i_wb_cyc);
if ((o_qspi_cs_n)&&(!spi_busy)) // Chip select line is high, we can continue
begin
spi_wr <= 1'b0;
spi_hold <= 1'b0;
casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
4'b00??: begin // Read data from ... somewhere
spi_wr <= 1'b1; // Write cmd to device
if (quad_mode_enabled)
begin
spi_in <= { 8'heb, w_spif_addr };
state <= `WBQSPI_QRD_ADDRESS;
// spi_len <= 2'b00; // single byte, cmd only
end else begin
spi_in <= { 8'h0b, w_spif_addr };
state <= `WBQSPI_RD_DUMMY;
spi_len <= 2'b11; // Send cmd and addr
end end
4'b10??: begin // Write data to ... anywhere
spi_wr <= 1'b1;
spi_len <= 2'b00; // 8 bits
// Send a write enable command
spi_in <= { 8'h06, 24'h00 };
state <= `WBQSPI_WEN;
end
4'b0110: begin // Read status register
state <= `WBQSPI_READ_STATUS;
spi_wr <= 1'b1;
spi_len <= 2'b01; // 8 bits out, 8 bits in
spi_in <= { 8'h05, 24'h00};
end
4'b0111: begin
state <= `WBQSPI_READ_ID_CMD;
spi_wr <= 1'b1;
spi_len <= 2'b00;
spi_in <= { 8'h9f, 24'h00};
end
default: begin //
o_wb_stall <= 1'b1;
o_wb_ack <= spif_req;
state <= `WBQSPI_WAIT_TIL_IDLE;
end
endcase
// spif_cmd <= i_wb_we;
// spif_addr <= i_wb_addr;
// spif_data <= i_wb_data;
// spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
// spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
end
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WEN))
begin // We came here after issuing a write enable command
spi_wr <= 1'b0;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spif_req<= (spif_req) && (i_wb_cyc);
if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Let's come to a full stop
state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
// state <= `WBQSPI_PP;
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_PP))
begin // We come here under a full stop / full port idle mode
// Issue our command immediately
spi_wr <= 1'b1;
spi_in <= { 8'h02, w_spif_addr };
spi_len <= 2'b11;
spi_hold <= 1'b1;
spi_spd <= 1'b0;
spi_dir <= 1'b0; // Writing
spif_req<= (spif_req) && (i_wb_cyc);
// Once we get busy, move on
if (spi_busy)
state <= `WBQSPI_WR_DATA;
if (spif_sector == erased_sector)
dirty_sector <= 1'b1;
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_QPP))
begin // We come here under a full stop / full port idle mode
// Issue our command immediately
spi_wr <= 1'b1;
spi_in <= { 8'h32, w_spif_addr };
spi_len <= 2'b11;
spi_hold <= 1'b1;
spi_spd <= 1'b0;
spi_dir <= 1'b0; // Writing
spif_req<= (spif_req) && (i_wb_cyc);
// Once we get busy, move on
if (spi_busy)
begin
// spi_wr is irrelevant here ...
// Set the speed value once, but wait til we get busy
// to do so.
spi_spd <= 1'b1;
state <= `WBQSPI_WR_DATA;
end
if (spif_sector == erased_sector)
dirty_sector <= 1'b1;
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WR_DATA))
begin
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spi_wr <= 1'b1; // write without waiting
spi_in <= spif_data;
spi_len <= 2'b11; // Write 4 bytes
spi_hold <= 1'b1;
if (!spi_busy)
begin
o_wb_ack <= spif_req; // Ack when command given
state <= `WBQSPI_WR_BUS_CYCLE;
end
spif_req<= (spif_req) && (i_wb_cyc);
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WR_BUS_CYCLE))
begin
o_wb_ack <= 1'b0; // Turn off our ack and stall flags
o_wb_stall <= 1'b1;
spi_wr <= 1'b0;
spi_hold <= 1'b1;
write_in_progress <= 1'b1;
spif_req<= (spif_req) && (i_wb_cyc);
if (!i_wb_cyc)
begin
state <= `WBQSPI_WAIT_TIL_IDLE;
spi_hold <= 1'b0;
end else if (spi_wr)
begin // Give the SPI a chance to get busy on the last write
// Do nothing here.
end else if ((spif_req)&&(i_wb_data_stb)&&(i_wb_we)
&&(i_wb_addr == (spif_addr+1))
&&(i_wb_addr[(AW-1):6]==spif_addr[(AW-1):6]))
begin
spif_cmd <= 1'b1;
spif_data <= i_wb_data;
spif_addr <= i_wb_addr;
spif_ctrl <= 1'b0;
spif_req<= 1'b1;
// We'll keep the bus stalled on this request
// for a while
state <= `WBQSPI_WR_DATA;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b0;
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(!o_wb_ack)) // Writing out of bounds
begin
spi_hold <= 1'b0;
spi_wr <= 1'b0;
state <= `WBQSPI_WAIT_TIL_IDLE;
end // Otherwise we stay here
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WRITE_CONFIG))
begin // We enter immediately after commanding a WEN
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_len <= 2'b10;
spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
spi_wr <= 1'b0;
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
if ((!spi_busy)&&(!spi_wr))
begin
spi_wr <= 1'b1;
state <= `WBQSPI_WAIT_TIL_IDLE;
write_in_progress <= 1'b1;
quad_mode_enabled <= spif_data[1];
end
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WRITE_STATUS))
begin // We enter immediately after commanding a WEN
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_len <= 2'b01;
spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
// last_status <= i_wb_data[7:0]; // We'll read this in a moment
spi_wr <= 1'b0;
spi_hold <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
if ((!spi_busy)&&(!spi_wr))
begin
spi_wr <= 1'b1;
last_status <= spif_data[7:0];
write_in_progress <= 1'b1;
if(((last_status[6])||(last_status[5]))
&&((!spif_data[6])&&(!spif_data[5])))
state <= `WBQSPI_CLEAR_STATUS;
else
state <= `WBQSPI_WAIT_TIL_IDLE;
end
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_ERASE_CMD))
begin // Know that WIP is clear on entry, WEN has just been commanded
spi_wr <= 1'b0;
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
spi_hold <= 1'b0;
spi_spd <= 1'b0;
spi_dir <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
// Here's the erase command
spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
spi_len <= 2'b11; // 32 bit write
// together with setting our copy of the WIP bit
write_in_progress <= 1'b1;
// keeping track of which sector we just erased
erased_sector <= spif_data[(AW-1):14];
// and marking this erase sector as no longer dirty
dirty_sector <= 1'b0;
// Wait for a full stop before issuing this command
if ((!spi_busy)&&(!spi_wr)&&(o_qspi_cs_n))
begin // When our command is accepted, move to the next state
spi_wr <= 1'b1;
state <= `WBQSPI_ERASE_BLOCK;
end
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_ERASE_BLOCK))
begin
spi_wr <= 1'b0;
spi_hold <= 1'b0;
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
// When the port clears, we can head back to idle
// No ack necessary, we ackd before getting
// here.
if ((!spi_busy)&&(!spi_wr))
state <= `WBQSPI_IDLE;
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CLEAR_STATUS))
begin // Issue a clear status command
spi_wr <= 1'b1;
spi_hold <= 1'b0;
spi_len <= 2'b00; // 8 bit command
spi_in <= { 8'h30, 24'h00 };
spi_spd <= 1'b0;
spi_dir <= 1'b0;
last_status[6:5] <= 2'b00;
spif_req <= (spif_req) && (i_wb_cyc);
if ((spi_wr)&&(!spi_busy))
state <= `WBQSPI_WAIT_TIL_IDLE;
end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_IDLE_CHECK_WIP))
begin // We are now in read status register mode
// No bus commands have (yet) been given
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spif_req <= (spif_req) && (i_wb_cyc);
// Stay in this mode unless/until we get a command, or
// the write is over
spi_wr <= (((!i_wb_cyc)||((!i_wb_data_stb)&&(!i_wb_ctrl_stb)))
&&(write_in_progress));
spi_len <= 2'b00; // 8 bit reads
spi_spd <= 1'b0; // SPI, not quad
spi_dir <= 1'b1; // Read
if (spi_valid)
begin
write_in_progress <= spi_out[0];
if ((!spi_out[0])&&(write_in_progress))
o_interrupt <= 1'b1;
end else
o_interrupt <= 1'b0;
if ((!spi_wr)&&(!spi_busy)&&(o_qspi_cs_n))
begin // We can now go to idle and process a command
o_wb_stall <= 1'b0;
o_wb_ack <= 1'b0;
state <= `WBQSPI_IDLE;
end
end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
begin
spi_wr <= 1'b0;
spi_hold <= 1'b0;
o_wb_stall <= 1'b1;
o_wb_ack <= 1'b0;
spif_req <= 1'b0;
if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Wait for a full
begin // clearing of the SPI port before moving on
state <= `WBQSPI_IDLE;
o_wb_stall <= 1'b0;
o_wb_ack <= 1'b0; // Shouldn't be acking anything here
end
end
end
// Command and control during the reset sequence
assign o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n;
assign o_qspi_sck = (spif_override)?alt_ctrl:w_qspi_sck;
assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod;
assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat;
endmodule
`default_nettype none
//
`define QSPI_IDLE 3'h0
`define QSPI_START 3'h1
`define QSPI_BITS 3'h2
`define QSPI_READY 3'h3
`define QSPI_HOLDING 3'h4
`define QSPI_STOP 3'h5
`define QSPI_STOP_B 3'h6
// Modes
`define QSPI_MOD_SPI 2'b00
`define QSPI_MOD_QOUT 2'b10
`define QSPI_MOD_QIN 2'b11
// Which level of formal proofs will we be doing? As a component, or a
// top-level?
`ifdef LLQSPI_TOP
`define ASSUME assume
`else
`define ASSUME assert
`endif
//
module llqspi(i_clk,
// Module interface
i_wr, i_hold, i_word, i_len, i_spd, i_dir,
o_word, o_valid, o_busy,
// QSPI interface
o_sck, o_cs_n, o_mod, o_dat, i_dat);
input wire i_clk;
// Chip interface
// Can send info
// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
// i_word = { 1'b0, 32'info to send },
// i_len = # of bytes in word-1
input wire i_wr, i_hold;
input wire [31:0] i_word;
input wire [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
input wire i_spd; // 0 -> normal QPI, 1 -> QSPI
input wire i_dir; // 0 -> read, 1 -> write to SPI
output reg [31:0] o_word;
output reg o_valid, o_busy;
// Interface with the QSPI lines
output reg o_sck;
output reg o_cs_n;
output reg [1:0] o_mod;
output reg [3:0] o_dat;
input wire [3:0] i_dat;
// output wire [22:0] o_dbg;
// assign o_dbg = { state, spi_len,
// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
// Timing:
//
// Tick Clk BSY/WR CS_n BIT/MO STATE
// 0 1 0/0 1 -
// 1 1 0/1 1 -
// 2 1 1/0 0 - QSPI_START
// 3 0 1/0 0 - QSPI_START
// 4 0 1/0 0 0 QSPI_BITS
// 5 1 1/0 0 0 QSPI_BITS
// 6 0 1/0 0 1 QSPI_BITS
// 7 1 1/0 0 1 QSPI_BITS
// 8 0 1/0 0 2 QSPI_BITS
// 9 1 1/0 0 2 QSPI_BITS
// 10 0 1/0 0 3 QSPI_BITS
// 11 1 1/0 0 3 QSPI_BITS
// 12 0 1/0 0 4 QSPI_BITS
// 13 1 1/0 0 4 QSPI_BITS
// 14 0 1/0 0 5 QSPI_BITS
// 15 1 1/0 0 5 QSPI_BITS
// 16 0 1/0 0 6 QSPI_BITS
// 17 1 1/1 0 6 QSPI_BITS
// 18 0 1/1 0 7 QSPI_READY
// 19 1 0/1 0 7 QSPI_READY
// 20 0 1/0/V 0 8 QSPI_BITS
// 21 1 1/0 0 8 QSPI_BITS
// 22 0 1/0 0 9 QSPI_BITS
// 23 1 1/0 0 9 QSPI_BITS
// 24 0 1/0 0 10 QSPI_BITS
// 25 1 1/0 0 10 QSPI_BITS
// 26 0 1/0 0 11 QSPI_BITS
// 27 1 1/0 0 11 QSPI_BITS
// 28 0 1/0 0 12 QSPI_BITS
// 29 1 1/0 0 12 QSPI_BITS
// 30 0 1/0 0 13 QSPI_BITS
// 31 1 1/0 0 13 QSPI_BITS
// 32 0 1/0 0 14 QSPI_BITS
// 33 1 1/0 0 14 QSPI_BITS
// 34 0 1/0 0 15 QSPI_READY
// 35 1 1/0 0 15 QSPI_READY
// 36 1 1/0/V 0 - QSPI_STOP
// 37 1 1/0 0 - QSPI_STOPB
// 38 1 1/0 1 - QSPI_IDLE
// 39 1 0/0 1 -
// Now, let's switch from single bit to quad mode
// 40 1 0/0 1 - QSPI_IDLE
// 41 1 0/1 1 - QSPI_IDLE
// 42 1 1/0 0 - QSPI_START
// 43 0 1/0 0 - QSPI_START
// 44 0 1/0 0 0 QSPI_BITS
// 45 1 1/0 0 0 QSPI_BITS
// 46 0 1/0 0 1 QSPI_BITS
// 47 1 1/0 0 1 QSPI_BITS
// 48 0 1/0 0 2 QSPI_BITS
// 49 1 1/0 0 2 QSPI_BITS
// 50 0 1/0 0 3 QSPI_BITS
// 51 1 1/0 0 3 QSPI_BITS
// 52 0 1/0 0 4 QSPI_BITS
// 53 1 1/0 0 4 QSPI_BITS
// 54 0 1/0 0 5 QSPI_BITS
// 55 1 1/0 0 5 QSPI_BITS
// 56 0 1/0 0 6 QSPI_BITS
// 57 1 1/1/QR 0 6 QSPI_BITS
// 58 0 1/1/QR 0 7 QSPI_READY
// 59 1 0/1/QR 0 7 QSPI_READY
// 60 0 1/0/?/V 0 8-11 QSPI_BITS
// 61 1 1/0/? 0 8-11 QSPI_BITS
// 62 0 1/0/? 0 12-15 QSPI_BITS
// 63 1 1/0/? 0 12-15 QSPI_BITS
// 64 1 1/0/?/V 0 - QSPI_STOP
// 65 1 1/0/? 0 - QSPI_STOPB
// 66 1 1/0/? 1 - QSPI_IDLE
// 67 1 0/0 1 - QSPI_IDLE
// Now let's try something entirely in Quad read mode, from the
// beginning
// 68 1 0/1/QR 1 - QSPI_IDLE
// 69 1 1/0 0 - QSPI_START
// 70 0 1/0 0 - QSPI_START
// 71 0 1/0 0 0-3 QSPI_BITS
// 72 1 1/0 0 0-3 QSPI_BITS
// 73 0 1/1/QR 0 4-7 QSPI_BITS
// 74 1 0/1/QR 0 4-7 QSPI_BITS
// 75 0 1/?/?/V 0 8-11 QSPI_BITS
// 76 1 1/?/? 0 8-11 QSPI_BITS
// 77 0 1/1/QR 0 12-15 QSPI_BITS
// 78 1 0/1/QR 0 12-15 QSPI_BITS
// 79 0 1/?/?/V 0 16-19 QSPI_BITS
// 80 1 1/0 0 16-19 QSPI_BITS
// 81 0 1/0 0 20-23 QSPI_BITS
// 82 1 1/0 0 20-23 QSPI_BITS
// 83 1 1/0/V 0 - QSPI_STOP
// 84 1 1/0 0 - QSPI_STOPB
// 85 1 1/0 1 - QSPI_IDLE
// 86 1 0/0 1 - QSPI_IDLE
wire i_miso;
assign i_miso = i_dat[1];
reg r_spd, r_dir;
reg [5:0] spi_len;
reg [31:0] r_word;
reg [30:0] r_input;
reg [2:0] state;
initial state = `QSPI_IDLE;
initial o_sck = 1'b1;
initial o_cs_n = 1'b1;
initial o_dat = 4'hd;
initial o_valid = 1'b0;
initial o_busy = 1'b0;
initial r_input = 31'h000;
initial o_mod = `QSPI_MOD_SPI;
initial o_word = 0;
always @(posedge i_clk)
if ((state == `QSPI_IDLE)&&(o_sck))
begin
o_cs_n <= 1'b1;
o_valid <= 1'b0;
o_busy <= 1'b0;
o_mod <= `QSPI_MOD_SPI;
r_word <= i_word;
r_spd <= i_spd;
r_dir <= i_dir;
if ((i_wr)&&(!o_busy))
begin
state <= `QSPI_START;
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
o_cs_n <= 1'b0;
// o_sck <= 1'b1;
o_busy <= 1'b1;
end
end else if (state == `QSPI_START)
begin // We come in here with sck high, stay here 'til sck is low
o_sck <= 1'b0;
if (o_sck == 1'b0)
begin
state <= `QSPI_BITS;
spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
if (r_spd)
r_word <= { r_word[27:0], 4'h0 };
else
r_word <= { r_word[30:0], 1'b0 };
end
o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
o_cs_n <= 1'b0;
o_busy <= 1'b1;
o_valid <= 1'b0;
if (r_spd)
o_dat <= r_word[31:28];
else
o_dat <= { 3'b110, r_word[31] };
end else if (!o_sck)
begin
o_sck <= 1'b1;
o_busy <= ((state != `QSPI_READY)||(!i_wr));
o_valid <= 1'b0;
end else if (state == `QSPI_BITS)
begin
// Should enter into here with at least a spi_len
// of one, perhaps more
o_sck <= 1'b0;
o_busy <= 1'b1;
if (r_spd)
begin
o_dat <= r_word[31:28];
r_word <= { r_word[27:0], 4'h0 };
spi_len <= spi_len - 6'h4;
if (spi_len == 6'h4)
state <= `QSPI_READY;
end else begin
o_dat <= { 3'b110, r_word[31] };
r_word <= { r_word[30:0], 1'b0 };
spi_len <= spi_len - 6'h1;
if (spi_len == 6'h1)
state <= `QSPI_READY;
end
o_valid <= 1'b0;
if (!o_mod[1])
r_input <= { r_input[29:0], i_miso };
else if (o_mod[1])
r_input <= { r_input[26:0], i_dat };
end else if (state == `QSPI_READY)
begin
o_valid <= 1'b0;
o_cs_n <= 1'b0;
o_busy <= 1'b1;
// This is the state on the last clock (both low and
// high clocks) of the data. Data is valid during
// this state. Here we chose to either STOP or
// continue and transmit more.
o_sck <= (i_hold); // No clocks while holding
r_spd <= i_spd;
r_dir <= i_dir;
if (i_spd)
begin
r_word <= { i_word[27:0], 4'h0 };
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h4;
end else begin
r_word <= { i_word[30:0], 1'b0 };
spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h1;
end
if((!o_busy)&&(i_wr))// Acknowledge a new request
begin
state <= `QSPI_BITS;
o_busy <= 1'b1;
o_sck <= 1'b0;
// Read the new request off the bus
// Set up the first bits on the bus
o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
if (i_spd)
o_dat <= i_word[31:28];
else
o_dat <= { 3'b110, i_word[31] };
end else begin
o_sck <= 1'b1;
state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
o_busy <= (!i_hold);
end
// Read a bit upon any transition
o_valid <= 1'b1;
if (!o_mod[1])
begin
r_input <= { r_input[29:0], i_miso };
o_word <= { r_input[30:0], i_miso };
end else if (o_mod[1])
begin
r_input <= { r_input[26:0], i_dat };
o_word <= { r_input[27:0], i_dat };
end
end else if (state == `QSPI_HOLDING)
begin
// We need this state so that the o_valid signal
// can get strobed with our last result. Otherwise
// we could just sit in READY waiting for a new command.
//
// Incidentally, the change producing this state was
// the result of a nasty race condition. See the
// commends in wbqspiflash for more details.
//
o_valid <= 1'b0;
o_cs_n <= 1'b0;
o_busy <= 1'b0;
r_spd <= i_spd;
r_dir <= i_dir;
if (i_spd)
begin
r_word <= { i_word[27:0], 4'h0 };
spi_len<= { 1'b0, i_len, 3'b100 };
end else begin
r_word <= { i_word[30:0], 1'b0 };
spi_len<= { 1'b0, i_len, 3'b111 };
end
if((!o_busy)&&(i_wr))// Acknowledge a new request
begin
state <= `QSPI_BITS;
o_busy <= 1'b1;
o_sck <= 1'b0;
// Read the new request off the bus
// Set up the first bits on the bus
o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
if (i_spd)
o_dat <= i_word[31:28];
else
o_dat <= { 3'b110, i_word[31] };
end else begin
o_sck <= 1'b1;
state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
o_busy <= (!i_hold);
end
end else if (state == `QSPI_STOP)
begin
o_sck <= 1'b1; // Stop the clock
o_valid <= 1'b0; // Output may have just been valid, but no more
o_busy <= 1'b1; // Still busy till port is clear
state <= `QSPI_STOP_B;
o_mod <= `QSPI_MOD_SPI;
end else if (state == `QSPI_STOP_B)
begin
o_cs_n <= 1'b1;
o_sck <= 1'b1;
// Do I need this????
// spi_len <= 3; // Minimum CS high time before next cmd
state <= `QSPI_IDLE;
o_valid <= 1'b0;
o_busy <= 1'b1;
o_mod <= `QSPI_MOD_SPI;
end else begin // Invalid states, should never get here
state <= `QSPI_STOP;
o_valid <= 1'b0;
o_busy <= 1'b1;
o_cs_n <= 1'b1;
o_sck <= 1'b1;
o_mod <= `QSPI_MOD_SPI;
o_dat <= 4'hd;
end
`ifdef FORMAL
reg prev_i_clk, past_valid;
initial `ASSUME(i_clk == 1'b0);
initial prev_i_clk = 1;
always @($global_clock)
begin
prev_i_clk <= i_clk;
`ASSUME(i_clk != prev_i_clk);
end
reg past_valid;
initial past_valid = 1'b0;
always @(posedge i_clk)
past_valid <= 1'b1;
/*
always @(*)
if (!$stable(i_spd))
assert($rose(i_clk));
*/
always @(posedge i_clk) begin
if ((past_valid)&&($past(i_wr))&&($past(o_busy)))
begin
// any time i_wr and o_busy are true, nothing changes
// of spd, len, word or dir
`ASSUME(i_wr);
`ASSUME(i_spd == $past(i_spd));
`ASSUME(i_len == $past(i_len));
`ASSUME(i_word == $past(i_word));
`ASSUME(i_dir == $past(i_dir));
`ASSUME(i_hold == $past(i_hold));
end
if ((past_valid)&&($past(i_wr))&&($past(o_busy))&&($past(state == `QSPI_IDLE)))
assert($past(state)==state);
if (i_hold == $past(i_hold))
assert($stable(i_hold));
end
always @(*) begin
if (o_mod == `QSPI_MOD_QOUT)
`ASSUME(i_dat == o_dat);
if (o_mod == `QSPI_MOD_SPI)
`ASSUME(i_dat[3:2] == 2'b11);
if (o_mod == `QSPI_MOD_SPI)
`ASSUME(i_dat[0] == o_dat[0]);
end
initial `ASSUME(i_wr == 1'b0);
initial `ASSUME(i_word == 0);
always @($global_clock)
if (!$rose(i_clk))
begin
`ASSUME($stable(i_wr));
//
`ASSUME($stable(i_len));
`ASSUME($stable(i_dir));
`ASSUME($stable(i_spd));
`ASSUME($stable(i_word));
//
`ASSUME($stable(i_hold));
end
always @($global_clock)
if (!$fell(o_sck))
assume($stable(i_dat));
// This is ... not as believable. There might be a delay here.
// For now, we'll just assume (not necessarily true) that the
// output
always @(posedge i_clk)
if (past_valid)
`ASSUME( (i_dat == $past(i_dat)) || (o_sck != $past(o_sck)) );
reg f_last_sck;
always @(posedge i_clk)
f_last_sck <= o_sck;
reg [31:0] f_shiftreg, f_goal;
initial f_shiftreg = 0;
initial f_goal = 0;
always @(posedge i_clk)
if ((o_sck)&&(!f_last_sck))
begin
if (o_mod == `QSPI_MOD_QOUT)
f_shiftreg <= { f_shiftreg[28:0], o_dat };
else if (o_mod == `QSPI_MOD_SPI)
f_shiftreg <= { f_shiftreg[30:0], o_dat[0] };
end
reg [5:0] f_nsent, f_vsent;
reg [2:0] f_nbits_r;
wire [5:0] f_nbits;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
begin
f_goal <= i_word;
f_nbits_r <= { 1'b0, i_len } + 3'h1;
end
assign f_nbits = { f_nbits_r, 3'b000 };
always @(posedge i_clk)
if ((!o_sck)||(!o_cs_n))
assert(f_nbits != 0);
always @(posedge i_clk)
if (o_cs_n)
f_nsent <= 0;
else if ((!o_busy)&&(i_wr))
f_nsent <= 0;
else if ((!f_last_sck)&&(o_sck))
begin
if (o_mod == `QSPI_MOD_SPI)
f_nsent <= f_nsent + 6'h1;
else
f_nsent <= f_nsent + 6'h4;
end
always @(posedge i_clk)
if (o_cs_n)
f_vsent <= 0;
else
f_vsent <= f_nsent;
always @(posedge i_clk)
if ((!o_cs_n)&&(state == `QSPI_BITS)&&(!o_sck))
begin
if (o_mod != `QSPI_MOD_SPI)
assert(f_nsent + spi_len + 6'h4 == f_nbits);
else
assert(f_nsent + spi_len + 6'h1 == f_nbits);
end
always @(posedge i_clk)
assert((o_busy)||(f_goal[(f_nbits-1):0] == f_shiftreg[(f_nbits-1):0]));
always @(posedge i_clk) begin
// We are only ever in one of three speed modes, fourth mode
// isn't allowed
assert( (o_mod == `QSPI_MOD_SPI)
||(o_mod == `QSPI_MOD_QIN)
||(o_mod == `QSPI_MOD_QOUT));
if ((past_valid)&&($past(i_wr))&&(!$past(o_busy)))
begin
// Any accepted request leaves us in an active state
assert(!o_cs_n);
// Any accepted request allows us to set our speed
assert(r_spd == $past(i_spd));
end
// We're either busy, or idle with the clock high
// or pausing (upon a request) mid-transaction
assert((o_busy)
||((state == `QSPI_IDLE)&&(o_sck)&&(o_cs_n))
||((state == `QSPI_READY)&&(o_sck)&&(!o_cs_n))
||((state == `QSPI_HOLDING)&&(o_sck)&&(!o_cs_n))
);
// Anytime CS is idle, SCK is high
if (o_cs_n)
assert(o_sck);
// What can we assert about i_hold?
// When i_hold is asserted before a transaction completes,
// the transaction will "hold" and wait for a next input.
// i.e. the clock will stop
// First assert that o_busy will be deasserted any time the
// currently requested word has been sent
//
//if ((($past(i_wr))||(i_hold))
// &&(f_nsent == f_nbits)&&(!o_sck)&&(!o_cs_n))
// assert(!o_busy);
// First, assert of i_hold that !o_busy will be set.
if ((past_valid)&&($past(i_hold))&&(f_nsent == f_nbits)&&(!o_cs_n))
begin
assert((!o_busy)||(o_sck));
end
if ((past_valid)&&($past(i_hold))&&(!$past(i_wr))
&&(!$past(o_busy))&&(!$past(o_cs_n)))
begin
assert(!o_cs_n);
assert($past(o_sck)==o_sck);
end
// DATA only changes on the falling edge of SCK
if ((past_valid)&&(o_sck))
assert(o_dat==$past(o_dat));
// Valid is only ever true for one clock
if ((past_valid)&&(o_valid))
assert(!$past(o_valid));
// Valid is only ever true after receiving a full number of bits
if ((past_valid)&&(o_valid))
begin
if ((!$past(i_wr))||($past(o_busy)))
assert(f_nsent == f_nbits);
end
// In SPI mode, the top bits of o_dat are always 3'b110
//
// This should be true, but there's a problem holding this
// true
// assert( (o_mod != `QSPI_MOD_SPI)||(o_dat[3:1] == 3'b110) );
// Either valid is true (this clock), or our output word is
// identical to what it was on the last clock
if (past_valid)
assert((o_valid) || (o_word == $past(o_word)));
end
`endif
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_SYMBOL_V
`define SKY130_FD_SC_LS__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_SYMBOL_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 11
(* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "system_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "system_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDT\
H=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_11_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="adders,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a75tlftg256-2l,HLS_INPUT_CLOCK=3.250000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.365667,HLS_SYN_LAT=1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=236,HLS_SYN_LUT=87}" *)
module adders (
ap_clk,
ap_rst,
in1,
in2,
in3,
ap_return
);
parameter ap_ST_fsm_state1 = 2'd1;
parameter ap_ST_fsm_state2 = 2'd2;
input ap_clk;
input ap_rst;
input [31:0] in1;
input [31:0] in2;
input [31:0] in3;
output [31:0] ap_return;
wire [31:0] tmp1_fu_42_p2;
reg [31:0] tmp1_reg_53;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire ap_CS_fsm_state2;
reg [1:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
tmp1_reg_53 <= tmp1_fu_42_p2;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_return = (tmp1_reg_53 + in2);
assign tmp1_fu_42_p2 = (in1 + in3);
endmodule //adders
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_SYMBOL_V
`define SKY130_FD_SC_HS__NAND3B_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_4_V
`define SKY130_FD_SC_MS__A21BOI_4_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_4_V
|
/**
* bsg_fpu_sticky.v
*
* @author tommy
*
* It calculates the sticky bit for given input and shift amount.
*
* Sometimes, the mantissa with lower exponent needs to be shifted right to
* aligned with the other mantissa. Due to finite precision, the shifted
* mantissa loses lower bits by the amount that was shifted. Sticky bit
* captures if any one of the lower bits that was shifted out was 1, so that
* this could be used for deciding whether to round up or not.
*
*/
`include "bsg_defines.v"
module bsg_fpu_sticky
#(parameter `BSG_INV_PARAM(width_p))
(
input [width_p-1:0] i // input
, input [`BSG_WIDTH(width_p)-1:0] shamt_i // shift amount
, output logic sticky_o
);
logic [width_p-1:0] scan_out;
bsg_scan #(
.width_p(width_p)
,.or_p(1)
,.lo_to_hi_p(1)
) scan0 (
.i(i)
,.o(scan_out)
);
// answer
logic [width_p:0] answer;
assign answer = {scan_out, 1'b0};
// final output
assign sticky_o = shamt_i > width_p
? answer[width_p]
: answer[shamt_i];
endmodule
`BSG_ABSTRACT_MODULE(bsg_fpu_sticky)
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: frac_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altsyncram CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" DEVICE_FAMILY="Cyclone II" ENABLE_RUNTIME_MOD="NO" INIT_FILE="qrom.hex" NUMWORDS_A=16 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=4 address_a clock0 q_a
//VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = M4K 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
module frac_rom_altsyncram
(
address_a,
clock0,
q_a) /* synthesis synthesis_clearbox=1 */;
input [3:0] address_a;
input clock0;
output [7:0] q_a;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_ram_block1a_0portadataout;
wire [0:0] wire_ram_block1a_1portadataout;
wire [0:0] wire_ram_block1a_2portadataout;
wire [0:0] wire_ram_block1a_3portadataout;
wire [0:0] wire_ram_block1a_4portadataout;
wire [0:0] wire_ram_block1a_5portadataout;
wire [0:0] wire_ram_block1a_6portadataout;
wire [0:0] wire_ram_block1a_7portadataout;
wire [3:0] address_a_wire;
cycloneii_ram_block ram_block1a_0
(
.clk0(clock0),
.portaaddr({address_a_wire[3:0]}),
.portadataout(wire_ram_block1a_0portadataout[0:0]),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_0.connectivity_checking = "OFF",
ram_block1a_0.init_file = "qrom.hex",
ram_block1a_0.init_file_layout = "port_a",
ram_block1a_0.logical_ram_name = "ALTSYNCRAM",
ram_block1a_0.mem_init0 = 16'hDE9F,
ram_block1a_0.operation_mode = "rom",
ram_block1a_0.port_a_address_width = 4,
ram_block1a_0.port_a_data_out_clear = "none",
ram_block1a_0.port_a_data_out_clock = "clock0",
ram_block1a_0.port_a_data_width = 1,
ram_block1a_0.port_a_disable_ce_on_input_registers = "on",
ram_block1a_0.port_a_disable_ce_on_output_registers = "on",
ram_block1a_0.port_a_first_address = 0,
ram_block1a_0.port_a_first_bit_number = 0,
ram_block1a_0.port_a_last_address = 15,
ram_block1a_0.port_a_logical_ram_depth = 16,
ram_block1a_0.port_a_logical_ram_width = 8,
ram_block1a_0.ram_block_type = "AUTO",
ram_block1a_0.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_1
(
.clk0(clock0),
.portaaddr({address_a_wire[3:0]}),
.portadataout(wire_ram_block1a_1portadataout[0:0]),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_1.connectivity_checking = "OFF",
ram_block1a_1.init_file = "qrom.hex",
ram_block1a_1.init_file_layout = "port_a",
ram_block1a_1.logical_ram_name = "ALTSYNCRAM",
ram_block1a_1.mem_init0 = 16'hB4BB,
ram_block1a_1.operation_mode = "rom",
ram_block1a_1.port_a_address_width = 4,
ram_block1a_1.port_a_data_out_clear = "none",
ram_block1a_1.port_a_data_out_clock = "clock0",
ram_block1a_1.port_a_data_width = 1,
ram_block1a_1.port_a_disable_ce_on_input_registers = "on",
ram_block1a_1.port_a_disable_ce_on_output_registers = "on",
ram_block1a_1.port_a_first_address = 0,
ram_block1a_1.port_a_first_bit_number = 1,
ram_block1a_1.port_a_last_address = 15,
ram_block1a_1.port_a_logical_ram_depth = 16,
ram_block1a_1.port_a_logical_ram_width = 8,
ram_block1a_1.ram_block_type = "AUTO",
ram_block1a_1.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_2
(
.clk0(clock0),
.portaaddr({address_a_wire[3:0]}),
.portadataout(wire_ram_block1a_2portadataout[0:0]),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_2.connectivity_checking = "OFF",
ram_block1a_2.init_file = "qrom.hex",
ram_block1a_2.init_file_layout = "port_a",
ram_block1a_2.logical_ram_name = "ALTSYNCRAM",
ram_block1a_2.mem_init0 = 16'h8DCF,
ram_block1a_2.operation_mode = "rom",
ram_block1a_2.port_a_address_width = 4,
ram_block1a_2.port_a_data_out_clear = "none",
ram_block1a_2.port_a_data_out_clock = "clock0",
ram_block1a_2.port_a_data_width = 1,
ram_block1a_2.port_a_disable_ce_on_input_registers = "on",
ram_block1a_2.port_a_disable_ce_on_output_registers = "on",
ram_block1a_2.port_a_first_address = 0,
ram_block1a_2.port_a_first_bit_number = 2,
ram_block1a_2.port_a_last_address = 15,
ram_block1a_2.port_a_logical_ram_depth = 16,
ram_block1a_2.port_a_logical_ram_width = 8,
ram_block1a_2.ram_block_type = "AUTO",
ram_block1a_2.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_3
(
.clk0(clock0),
.portaaddr({address_a_wire[3:0]}),
.portadataout(wire_ram_block1a_3portadataout[0:0]),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_3.connectivity_checking = "OFF",
ram_block1a_3.init_file = "qrom.hex",
ram_block1a_3.init_file_layout = "port_a",
ram_block1a_3.logical_ram_name = "ALTSYNCRAM",
ram_block1a_3.mem_init0 = 16'h83AB,
ram_block1a_3.operation_mode = "rom",
ram_block1a_3.port_a_address_width = 4,
ram_block1a_3.port_a_data_out_clear = "none",
ram_block1a_3.port_a_data_out_clock = "clock0",
ram_block1a_3.port_a_data_width = 1,
ram_block1a_3.port_a_disable_ce_on_input_registers = "on",
ram_block1a_3.port_a_disable_ce_on_output_registers = "on",
ram_block1a_3.port_a_first_address = 0,
ram_block1a_3.port_a_first_bit_number = 3,
ram_block1a_3.port_a_last_address = 15,
ram_block1a_3.port_a_logical_ram_depth = 16,
ram_block1a_3.port_a_logical_ram_width = 8,
ram_block1a_3.ram_block_type = "AUTO",
ram_block1a_3.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_4
(
.clk0(clock0),
.portaaddr({address_a_wire[3:0]}),
.portadataout(wire_ram_block1a_4portadataout[0:0]),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_4.connectivity_checking = "OFF",
ram_block1a_4.init_file = "qrom.hex",
ram_block1a_4.init_file_layout = "port_a",
ram_block1a_4.logical_ram_name = "ALTSYNCRAM",
ram_block1a_4.mem_init0 = 16'h7F9F,
ram_block1a_4.operation_mode = "rom",
ram_block1a_4.port_a_address_width = 4,
ram_block1a_4.port_a_data_out_clear = "none",
ram_block1a_4.port_a_data_out_clock = "clock0",
ram_block1a_4.port_a_data_width = 1,
ram_block1a_4.port_a_disable_ce_on_input_registers = "on",
ram_block1a_4.port_a_disable_ce_on_output_registers = "on",
ram_block1a_4.port_a_first_address = 0,
ram_block1a_4.port_a_first_bit_number = 4,
ram_block1a_4.port_a_last_address = 15,
ram_block1a_4.port_a_logical_ram_depth = 16,
ram_block1a_4.port_a_logical_ram_width = 8,
ram_block1a_4.ram_block_type = "AUTO",
ram_block1a_4.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_5
(
.clk0(clock0),
.portaaddr({address_a_wire[3:0]}),
.portadataout(wire_ram_block1a_5portadataout[0:0]),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_5.connectivity_checking = "OFF",
ram_block1a_5.init_file = "qrom.hex",
ram_block1a_5.init_file_layout = "port_a",
ram_block1a_5.logical_ram_name = "ALTSYNCRAM",
ram_block1a_5.mem_init0 = 16'h007B,
ram_block1a_5.operation_mode = "rom",
ram_block1a_5.port_a_address_width = 4,
ram_block1a_5.port_a_data_out_clear = "none",
ram_block1a_5.port_a_data_out_clock = "clock0",
ram_block1a_5.port_a_data_width = 1,
ram_block1a_5.port_a_disable_ce_on_input_registers = "on",
ram_block1a_5.port_a_disable_ce_on_output_registers = "on",
ram_block1a_5.port_a_first_address = 0,
ram_block1a_5.port_a_first_bit_number = 5,
ram_block1a_5.port_a_last_address = 15,
ram_block1a_5.port_a_logical_ram_depth = 16,
ram_block1a_5.port_a_logical_ram_width = 8,
ram_block1a_5.ram_block_type = "AUTO",
ram_block1a_5.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_6
(
.clk0(clock0),
.portaaddr({address_a_wire[3:0]}),
.portadataout(wire_ram_block1a_6portadataout[0:0]),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_6.connectivity_checking = "OFF",
ram_block1a_6.init_file = "qrom.hex",
ram_block1a_6.init_file_layout = "port_a",
ram_block1a_6.logical_ram_name = "ALTSYNCRAM",
ram_block1a_6.mem_init0 = 16'h0007,
ram_block1a_6.operation_mode = "rom",
ram_block1a_6.port_a_address_width = 4,
ram_block1a_6.port_a_data_out_clear = "none",
ram_block1a_6.port_a_data_out_clock = "clock0",
ram_block1a_6.port_a_data_width = 1,
ram_block1a_6.port_a_disable_ce_on_input_registers = "on",
ram_block1a_6.port_a_disable_ce_on_output_registers = "on",
ram_block1a_6.port_a_first_address = 0,
ram_block1a_6.port_a_first_bit_number = 6,
ram_block1a_6.port_a_last_address = 15,
ram_block1a_6.port_a_logical_ram_depth = 16,
ram_block1a_6.port_a_logical_ram_width = 8,
ram_block1a_6.ram_block_type = "AUTO",
ram_block1a_6.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_7
(
.clk0(clock0),
.portaaddr({address_a_wire[3:0]}),
.portadataout(wire_ram_block1a_7portadataout[0:0]),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_7.connectivity_checking = "OFF",
ram_block1a_7.init_file = "qrom.hex",
ram_block1a_7.init_file_layout = "port_a",
ram_block1a_7.logical_ram_name = "ALTSYNCRAM",
ram_block1a_7.mem_init0 = 16'h0001,
ram_block1a_7.operation_mode = "rom",
ram_block1a_7.port_a_address_width = 4,
ram_block1a_7.port_a_data_out_clear = "none",
ram_block1a_7.port_a_data_out_clock = "clock0",
ram_block1a_7.port_a_data_width = 1,
ram_block1a_7.port_a_disable_ce_on_input_registers = "on",
ram_block1a_7.port_a_disable_ce_on_output_registers = "on",
ram_block1a_7.port_a_first_address = 0,
ram_block1a_7.port_a_first_bit_number = 7,
ram_block1a_7.port_a_last_address = 15,
ram_block1a_7.port_a_logical_ram_depth = 16,
ram_block1a_7.port_a_logical_ram_width = 8,
ram_block1a_7.ram_block_type = "AUTO",
ram_block1a_7.lpm_type = "cycloneii_ram_block";
assign
address_a_wire = address_a,
q_a = {wire_ram_block1a_7portadataout[0], wire_ram_block1a_6portadataout[0], wire_ram_block1a_5portadataout[0], wire_ram_block1a_4portadataout[0], wire_ram_block1a_3portadataout[0], wire_ram_block1a_2portadataout[0], wire_ram_block1a_1portadataout[0], wire_ram_block1a_0portadataout[0]};
endmodule //frac_rom_altsyncram
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module frac_rom (
address,
clock,
q)/* synthesis synthesis_clearbox = 1 */;
input [3:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
frac_rom_altsyncram frac_rom_altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "qrom.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "4"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "qrom.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL "address[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL frac_rom_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2018/11/07 $
// $Author: psgswbuild $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gthe4_cpll_cal_tx # (
parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter C_FREERUN_FREQUENCY = 100,
parameter REVISION = 2,
parameter C_PCIE_ENABLE = "FALSE",
parameter C_PCIE_CORECLK_FREQ = 250
)(
// control signals
input wire [17:0] TXOUTCLK_PERIOD_IN,
input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
input wire [17:0] CNT_TOL_IN,
input wire [15:0] FREQ_COUNT_WINDOW_IN,
// User Interface
input wire RESET_IN,
input wire CLK_IN,
input wire [1:0] USER_TXPLLCLKSEL,
input wire USER_TXPROGDIVRESET_IN,
output reg USER_TXPRGDIVRESETDONE_OUT,
input wire [2:0] USER_TXOUTCLKSEL_IN,
input wire USER_TXOUTCLK_BUFG_CE_IN,
input wire USER_TXOUTCLK_BUFG_CLR_IN,
output reg USER_CPLLLOCK_OUT,
// Debug Interface
output wire CPLL_CAL_FAIL,
output wire CPLL_CAL_DONE,
output wire [15:0] DEBUG_OUT,
output wire [17:0] CAL_FREQ_CNT,
input [3:0] REPEAT_RESET_LIMIT,
// GT Interface
input wire GTHE4_TXOUTCLK_IN,
input wire GTHE4_CPLLLOCK_IN,
output wire GTHE4_CPLLRESET_OUT,
output wire GTHE4_CPLLPD_OUT,
output reg GTHE4_TXPROGDIVRESET_OUT,
output reg [2:0] GTHE4_TXOUTCLKSEL_OUT,
input wire GTHE4_TXPRGDIVRESETDONE_IN,
output wire [9:0] GTHE4_CHANNEL_DRPADDR_OUT,
output wire [15:0] GTHE4_CHANNEL_DRPDI_OUT,
output wire GTHE4_CHANNEL_DRPEN_OUT,
output wire GTHE4_CHANNEL_DRPWE_OUT,
input wire GTHE4_CHANNEL_DRPRDY_IN,
input wire [15:0] GTHE4_CHANNEL_DRPDO_IN,
output wire DONE
);
//DRP FSM
localparam DRP_WAIT = 0;
localparam DRP_READ = 1;
localparam DRP_READ_ACK = 2;
localparam DRP_MODIFY = 3;
localparam DRP_WRITE = 4;
localparam DRP_WRITE_ACK = 5;
localparam DRP_DONE = 6;
localparam RESET = 0;
localparam READ_X0E1 = 1;
localparam CHECK_X0E1_STATUS = 2;
localparam READ_PROGCLK_SEL = 3;
localparam SAVE_PROGCLK_SEL = 4;
localparam READ_X079 = 5;
localparam CHECK_X079_STATUS = 6;
localparam READ_PROGDIV_CFG = 7;
localparam SAVE_PROGDIV_CFG = 8;
localparam READ_X0E1_BEFORE_PROGCLK_SEL_MOD = 9;
localparam MODIFY_PROGCLK_SEL = 10;
localparam MODIFY_PROGDIV = 11;
localparam MODIFY_TXOUTCLK_SEL = 12;
localparam ASSERT_CPLLPD = 13;
localparam DEASSERT_CPLLPD = 14;
localparam ASSERT_CPLLRESET = 15;
localparam DEASSERT_CPLLRESET = 16;
localparam WAIT_GTCPLLLOCK = 17;
localparam ASSERT_PROGDIVRESET = 18;
localparam WAIT_PRGDIVRESETDONE = 19;
localparam CHECK_FREQ = 20;
localparam RESTORE_READ_X0E1 = 21;
localparam RESTORE_READ_X079 = 22;
localparam RESTORE_PROGDIV = 23;
localparam RESTORE_PROGCLK_SEL = 24;
localparam CLEAR_FLAG_x0E1 = 25;
localparam CLEAR_FLAG_x079 = 26;
localparam WAIT_GTCPLLLOCK2 = 27;
localparam ASSERT_PROGDIVRESET2 = 28;
localparam WAIT_PRGDIVRESETDONE2= 29;
localparam CAL_FAIL = 30;
localparam CAL_DONE = 31;
reg [31:0] cpll_cal_state = 31'd0;
wire [4:0] cpll_cal_state_bin;
reg [6:0] drp_state = 7'd1;
wire drp_done;
reg [9:0] daddr = 10'd0;
reg [15:0] di = 16'd0;
wire drdy;
wire [15:0] dout;
reg den = 1'b0;
reg dwe = 1'b0;
reg wr = 1'b0;
reg rd = 1'b0;
reg [15:0] di_msk;
reg [15:0] mask;
reg [24:0] wait_ctr;
reg [3:0] repeat_ctr;
reg [15:0] progclk_sel_store = 16'd0;
reg [15:0] progdiv_cfg_store = 16'd0;
reg fboost_store = 1'b0;
reg mask_user_in = 1'b0;
reg cpllreset_int = 1'b0;
reg cpllpd_int = 1'b0;
reg txprogdivreset_int = 1'b0;
reg [2:0] txoutclksel_int = 3'b000;
reg cal_fail_store = 1'b0;
reg [15:0] x0e1_store = 16'd0;
reg status_store = 1'b0;
wire den_i;
wire dwe_i;
//All these need to be based on CLK_IN frequency (free_run)
localparam [24:0] SYNTH_WAIT_ASSERT_CPLLRESET = (1000 * C_FREERUN_FREQUENCY ); // 1 ms
localparam [24:0] SYNTH_WAIT_CPLLLOCK = (1000 * C_FREERUN_FREQUENCY ); // 1 ms
localparam [24:0] SYNTH_WAIT_DEASSERT_CPLLRESET = (100 * C_FREERUN_FREQUENCY ); // 100 us
localparam [24:0] SIM_WAIT_ASSERT_CPLLRESET = SYNTH_WAIT_ASSERT_CPLLRESET/10;
localparam [24:0] SIM_WAIT_CPLLLOCK = SYNTH_WAIT_CPLLLOCK/10;
localparam [24:0] SIM_WAIT_DEASSERT_CPLLRESET = SYNTH_WAIT_DEASSERT_CPLLRESET/10;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [4:0] WAIT_WIDTH_PROGDIVRESET = 5'd25; // >= 100 ns
localparam [24:0] WAIT_ASSERT_CPLLRESET =
//pragma translate_off
(SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_CPLLRESET :
//pragma translate_on
SYNTH_WAIT_ASSERT_CPLLRESET;
localparam [4:0] WAIT_ASSERT_CPLLPD = 5'd25; // >= 100 ns
localparam [24:0] WAIT_DEASSERT_CPLLRESET =
//pragma translate_off
(SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_DEASSERT_CPLLRESET :
//pragma translate_on
SYNTH_WAIT_DEASSERT_CPLLRESET;
localparam [24:0] WAIT_CPLLLOCK =
//pragma translate_off
(SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_CPLLLOCK :
//pragma translate_on
SYNTH_WAIT_CPLLLOCK;
localparam [1:0] MOD_PROGCLK_SEL = 2'b10;
localparam [15:0] MOD_PROGDIV_CFG = 16'hE062; //divider 20
localparam [2:0] MOD_TXOUTCLK_SEL = 3'b101;
localparam [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C;
localparam [9:0] ADDR_TX_PROGDIV_CFG = 10'h03E; // GTH /GTY addresses are different (003E in GTH; 0057 in GTY)
localparam [9:0] ADDR_X0E1 = 10'h0E1;
localparam [9:0] ADDR_X079 = 10'h079;
// Drive TXOUTCLK with BUFG_GT-buffered source clock, divider = 1
wire txoutclkmon;
//assign txoutclkmon = GTHE4_TXOUTCLK_IN;
BUFG_GT bufg_gt_txoutclkmon_inst (
.CE (USER_TXOUTCLK_BUFG_CE_IN),
.CEMASK (1'b1),
.CLR (USER_TXOUTCLK_BUFG_CLR_IN),
.CLRMASK (1'b1),
.DIV (3'b000),
.I (GTHE4_TXOUTCLK_IN),
.O (txoutclkmon)
);
wire gthe4_cplllock_sync;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_cplllock_inst (
.clk_in (CLK_IN),
.i_in (GTHE4_CPLLLOCK_IN),
.o_out (gthe4_cplllock_sync)
);
wire user_txprogdivreset_sync;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
.clk_in (CLK_IN),
.i_in (USER_TXPROGDIVRESET_IN),
.o_out (user_txprogdivreset_sync)
);
wire gthe4_txprgdivresetdone_sync;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
.clk_in (CLK_IN),
.i_in (GTHE4_TXPRGDIVRESETDONE_IN),
.o_out (gthe4_txprgdivresetdone_sync)
);
wire [2:0] user_txoutclksel_sync;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[0]),
.o_out (user_txoutclksel_sync[0])
);
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[1]),
.o_out (user_txoutclksel_sync[1])
);
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[2]),
.o_out (user_txoutclksel_sync[2])
);
assign GTHE4_CPLLRESET_OUT = cpllreset_int;
assign GTHE4_CPLLPD_OUT = cpllpd_int;
always @(posedge CLK_IN) begin
if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | RESET_IN)
USER_CPLLLOCK_OUT <= 1'b0;
else
USER_CPLLLOCK_OUT <= gthe4_cplllock_sync;
end
generate if (C_PCIE_ENABLE)
begin : pcie_txoutclksel
always @(*) begin
GTHE4_TXOUTCLKSEL_OUT <= mask_user_in ? txoutclksel_int : USER_TXOUTCLKSEL_IN;
GTHE4_TXPROGDIVRESET_OUT <= mask_user_in ? txprogdivreset_int : USER_TXPROGDIVRESET_IN;
end
end
else begin : non_pcie_txoutclksel
always @(posedge CLK_IN) begin
if (mask_user_in)
GTHE4_TXPROGDIVRESET_OUT <= txprogdivreset_int;
else
GTHE4_TXPROGDIVRESET_OUT <= user_txprogdivreset_sync;
end
always @(posedge CLK_IN) begin
if (mask_user_in)
GTHE4_TXOUTCLKSEL_OUT <= txoutclksel_int;
else
GTHE4_TXOUTCLKSEL_OUT <= user_txoutclksel_sync;
end
end
endgenerate
always @(posedge CLK_IN) begin
if (mask_user_in)
USER_TXPRGDIVRESETDONE_OUT <= 1'b0;
else
USER_TXPRGDIVRESETDONE_OUT <= gthe4_txprgdivresetdone_sync;
end
// frequency counter for txoutclk
wire [17:0] txoutclk_freq_cnt;
reg freq_counter_rst = 1'b1;
wire freq_cnt_done;
gtwizard_ultrascale_v1_7_1_gthe4_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
(
.freq_cnt_o(txoutclk_freq_cnt),
.done_o(freq_cnt_done),
.rst_i(freq_counter_rst),
.test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
.ref_clk_i(CLK_IN),
.test_clk_i(txoutclkmon)
);
//Debug signals
assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gthe4_cplllock_sync,1'b0,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
assign CAL_FREQ_CNT = txoutclk_freq_cnt;
assign DONE = cpll_cal_state[CAL_DONE] | cpll_cal_state[RESET];
//pragma translate_off
generate if (C_SIM_CPLL_CAL_BYPASS == 1'b1)
begin: gen_sim_cpll_cal_bypass_gthe4
//CPLL CAL FSM for simulation
always @(posedge CLK_IN) begin
if (RESET_IN) begin
cpll_cal_state <= 0;
cpll_cal_state[RESET] <= 1'b1;
cpllreset_int <= 1'b0;
cpllpd_int <= 1'b0;
txprogdivreset_int <= 1'b0;
mask_user_in <= 1'b0;
wr <= 1'b0;
rd <= 1'b0;
end
else begin
cpll_cal_state <= 0;
case(1'b1) // synthesis parallel_case full_case
cpll_cal_state[RESET]:
begin
wait_ctr <= 25'd0;
repeat_ctr <= 4'd0;
mask_user_in <= 1'b1;
di_msk <= 16'b0000_0000_0000_0000;
cpll_cal_state[READ_X0E1] <= 1'b1;
end
cpll_cal_state[READ_X0E1]:
begin
mask_user_in <= 1'b1;
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
status_store <= dout[15];
cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
end
else
cpll_cal_state[READ_X0E1] <= 1'b1;
end
cpll_cal_state[CHECK_X0E1_STATUS]:
begin
if (status_store)
cpll_cal_state[READ_X079] <= 1'b1;
else
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
end
cpll_cal_state[READ_PROGCLK_SEL]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progclk_sel_store <= dout;
cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
end
end
cpll_cal_state[SAVE_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[READ_X079] <= 1'b1;
end
else begin
cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
end
di_msk <= {1'b1,progclk_sel_store[14:0]};
end
cpll_cal_state[READ_X079]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
status_store <= dout[15];
cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
end
else begin
cpll_cal_state[READ_X079] <= 1'b1;
end
end
cpll_cal_state[CHECK_X079_STATUS]:
begin
if (status_store)
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
else
cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
end
cpll_cal_state[READ_PROGDIV_CFG]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progdiv_cfg_store <= {1'b1,dout[14:0]};
cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
end
else begin
cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
end
end
cpll_cal_state[SAVE_PROGDIV_CFG]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
end
else begin
cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
end
di_msk <= progdiv_cfg_store;
end
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
x0e1_store <= dout;
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
end
end
cpll_cal_state[MODIFY_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
end
else begin
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
end
di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
end
cpll_cal_state[MODIFY_PROGDIV]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
wait_ctr <= 25'd0;
end
di_msk<= MOD_PROGDIV_CFG;
end
cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
begin
cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
end
cpll_cal_state[ASSERT_CPLLRESET]:
begin
cpllreset_int <= 1'b1;
freq_counter_rst <= 1'b1;
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
wait_ctr <= 25'd0;
end
cpll_cal_state[DEASSERT_CPLLRESET]:
begin
if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
end
else begin
cpllreset_int <= 1'b0;
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
wait_ctr <= 16'd0;
end
end
cpll_cal_state[WAIT_GTCPLLLOCK]:
begin
if(!gthe4_cplllock_sync) begin
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
end
end
cpll_cal_state[RESTORE_READ_X0E1]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progclk_sel_store <= dout;
cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
end else begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
end
end
cpll_cal_state[RESTORE_READ_X079]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progdiv_cfg_store <= dout;
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
end else begin
cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
end
end
cpll_cal_state[RESTORE_PROGDIV]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
end
di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
end
cpll_cal_state[RESTORE_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
end
di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]};
end
cpll_cal_state[CLEAR_FLAG_x0E1]:
begin
//set [15] to 0
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
end
else begin
cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
end
// clear
di_msk <= 16'h0000;
end
cpll_cal_state[CLEAR_FLAG_x079]:
begin
//set [15] to 0
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
end
else begin
cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
end
// clear
di_msk <= 16'h0000;
end
cpll_cal_state[WAIT_GTCPLLLOCK2]:
begin
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
if(!gthe4_cplllock_sync)
cal_fail_store <= 1'b1;
else
cal_fail_store <= cal_fail_store;
end
cpll_cal_state[ASSERT_PROGDIVRESET2]:
begin
if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
wait_ctr <= wait_ctr + 1'b1;
txprogdivreset_int <= 1'b1;
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
end
else begin
txprogdivreset_int <= 1'b0;
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
begin
if (gthe4_txprgdivresetdone_sync) begin
if (cal_fail_store)
cpll_cal_state[CAL_FAIL] <= 1'b1;
else
cpll_cal_state[CAL_DONE] <= 1'b1;
end
else begin
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
end
end
cpll_cal_state[CAL_FAIL]:
begin
cpll_cal_state[CAL_FAIL] <= 1'b1;
mask_user_in <= 1'b0;
end
cpll_cal_state[CAL_DONE]:
begin
cpll_cal_state[CAL_DONE] <= 1'b1;
mask_user_in <= 1'b0;
end
endcase
end
end // always block
end
else
begin: gen_cpll_cal_gthe4
//pragma translate_on
//CPLL CAL FSM
always @(posedge CLK_IN) begin
if (RESET_IN) begin
cpll_cal_state <= 0;
cpll_cal_state[RESET] <= 1'b1;
cpllreset_int <= 1'b0;
cpllpd_int <= 1'b0;
txprogdivreset_int <= 1'b0;
mask_user_in <= 1'b0;
wr <= 1'b0;
rd <= 1'b0;
end
else begin
cpll_cal_state <= 0;
case(1'b1) // synthesis parallel_case full_case
cpll_cal_state[RESET]:
begin
wait_ctr <= 25'd0;
repeat_ctr <= 4'd0;
mask_user_in <= 1'b1;
di_msk <= 16'b0000_0000_0000_0000;
cpll_cal_state[READ_X0E1] <= 1'b1;
end
cpll_cal_state[READ_X0E1]:
begin
mask_user_in <= 1'b1;
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
status_store <= dout[15];
cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
end
else
cpll_cal_state[READ_X0E1] <= 1'b1;
end
cpll_cal_state[CHECK_X0E1_STATUS]:
begin
if (status_store)
cpll_cal_state[READ_X079] <= 1'b1;
else
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
end
cpll_cal_state[READ_PROGCLK_SEL]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progclk_sel_store <= dout;
cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
end
end
cpll_cal_state[SAVE_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[READ_X079] <= 1'b1;
end
else begin
cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
end
di_msk <= {1'b1,progclk_sel_store[14:0]};
end
cpll_cal_state[READ_X079]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
status_store <= dout[15];
cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
end
else begin
cpll_cal_state[READ_X079] <= 1'b1;
end
end
cpll_cal_state[CHECK_X079_STATUS]:
begin
if (status_store)
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
else
cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
end
cpll_cal_state[READ_PROGDIV_CFG]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progdiv_cfg_store <= {1'b1,dout[14:0]};
cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
end
else begin
cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
end
end
cpll_cal_state[SAVE_PROGDIV_CFG]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
end
else begin
cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
end
di_msk <= progdiv_cfg_store;
end
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
x0e1_store <= dout;
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
end
end
cpll_cal_state[MODIFY_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
end
else begin
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
end
di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
end
cpll_cal_state[MODIFY_PROGDIV]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
wait_ctr <= 25'd0;
end
di_msk<= MOD_PROGDIV_CFG;
end
cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
begin
cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
end
cpll_cal_state[ASSERT_CPLLPD]:
begin
if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
end
else begin
cpllpd_int <= 1'b1;
cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[DEASSERT_CPLLPD]:
begin
if (wait_ctr < SYNTH_WAIT_DEASSERT_CPLLRESET) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
end
else begin
cpllpd_int <= 1'b0;
cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
wait_ctr <= 16'd0;
freq_counter_rst <= 1'b1;
end
end
cpll_cal_state[ASSERT_CPLLRESET]:
begin
if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
end
else begin
cpllreset_int <= 1'b1;
freq_counter_rst <= 1'b1;
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[DEASSERT_CPLLRESET]:
begin
if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
end
else begin
cpllreset_int <= 1'b0;
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
wait_ctr <= 16'd0;
end
end
cpll_cal_state[WAIT_GTCPLLLOCK]:
begin
if(wait_ctr < WAIT_CPLLLOCK) begin
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
wait_ctr <= wait_ctr + 1'b1;
end
else begin
cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
wait_ctr <= 16'd0;
end
end
cpll_cal_state[ASSERT_PROGDIVRESET]:
begin
if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
wait_ctr <= wait_ctr + 1'b1;
txprogdivreset_int <= 1'b1;
cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
end
else begin
txprogdivreset_int <= 1'b0;
cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[WAIT_PRGDIVRESETDONE]:
begin
if (gthe4_txprgdivresetdone_sync) begin
cpll_cal_state[CHECK_FREQ] <= 1'b1;
freq_counter_rst <= 1'b0;
end
else begin
cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
end
end
cpll_cal_state[CHECK_FREQ]:
begin
if(freq_cnt_done) begin
if ((txoutclk_freq_cnt >= (TXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (txoutclk_freq_cnt <= (TXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
cal_fail_store <= 1'b0;
end
else begin
if (repeat_ctr < REPEAT_RESET_LIMIT) begin
cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
repeat_ctr <= repeat_ctr + 1'b1;
end
else begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
cal_fail_store <= 1'b1;
end
end
end
else
cpll_cal_state[CHECK_FREQ] <= 1'b1;
end
cpll_cal_state[RESTORE_READ_X0E1]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progclk_sel_store <= dout;
cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
end else begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
end
end
cpll_cal_state[RESTORE_READ_X079]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progdiv_cfg_store <= dout;
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
end else begin
cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
end
end
cpll_cal_state[RESTORE_PROGDIV]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
end
di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
end
cpll_cal_state[RESTORE_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
end
di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]};
end
cpll_cal_state[CLEAR_FLAG_x0E1]:
begin
//set [15] to 0
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
end
else begin
cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
end
// clear
di_msk <= 16'h0000;
end
cpll_cal_state[CLEAR_FLAG_x079]:
begin
//set [15] to 0
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
end
else begin
cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
end
// clear
di_msk <= 16'h0000;
end
cpll_cal_state[WAIT_GTCPLLLOCK2]:
begin
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
if(!gthe4_cplllock_sync)
cal_fail_store <= 1'b1;
else
cal_fail_store <= cal_fail_store;
end
cpll_cal_state[ASSERT_PROGDIVRESET2]:
begin
if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
wait_ctr <= wait_ctr + 1'b1;
txprogdivreset_int <= 1'b1;
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
end
else begin
txprogdivreset_int <= 1'b0;
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
begin
if (gthe4_txprgdivresetdone_sync) begin
if (cal_fail_store)
cpll_cal_state[CAL_FAIL] <= 1'b1;
else
cpll_cal_state[CAL_DONE] <= 1'b1;
end
else begin
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
end
end
cpll_cal_state[CAL_FAIL]:
begin
cpll_cal_state[CAL_FAIL] <= 1'b1;
mask_user_in <= 1'b0;
end
cpll_cal_state[CAL_DONE]:
begin
cpll_cal_state[CAL_DONE] <= 1'b1;
mask_user_in <= 1'b0;
end
endcase
end
end // always block
//pragma translate_off
end
endgenerate
//pragma translate_on
always @(posedge CLK_IN) begin
if (cpll_cal_state[RESET])
txoutclksel_int <= 3'b0;
else if (cpll_cal_state[MODIFY_TXOUTCLK_SEL])
txoutclksel_int <= MOD_TXOUTCLK_SEL;
end
always @(posedge CLK_IN) begin
if (cpll_cal_state[RESET]) begin
daddr <= 10'h000;
mask <= 16'b1111_1111_1111_1111;
end
else if (cpll_cal_state[READ_X0E1] | cpll_cal_state[SAVE_PROGCLK_SEL] | cpll_cal_state[RESTORE_READ_X0E1] | cpll_cal_state[CLEAR_FLAG_x0E1] | cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]) begin
daddr <= ADDR_X0E1;
end
else if (cpll_cal_state[READ_X079] | cpll_cal_state[SAVE_PROGDIV_CFG] | cpll_cal_state[RESTORE_READ_X079] | cpll_cal_state[CLEAR_FLAG_x079]) begin
daddr <= ADDR_X079;
end
else if (cpll_cal_state[READ_PROGCLK_SEL] | cpll_cal_state[MODIFY_PROGCLK_SEL] | cpll_cal_state[RESTORE_PROGCLK_SEL]) begin
daddr <= ADDR_TX_PROGCLK_SEL;
end
else if (cpll_cal_state[READ_PROGDIV_CFG] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
daddr <= ADDR_TX_PROGDIV_CFG;
end
end
assign drp_done = drp_state[DRP_DONE];
assign GTHE4_CHANNEL_DRPEN_OUT = den;
assign GTHE4_CHANNEL_DRPWE_OUT = dwe;
assign GTHE4_CHANNEL_DRPADDR_OUT = daddr;
assign GTHE4_CHANNEL_DRPDI_OUT = di;
assign drdy = GTHE4_CHANNEL_DRPRDY_IN;
assign dout = GTHE4_CHANNEL_DRPDO_IN;
always @(posedge CLK_IN or posedge RESET_IN) begin
if (RESET_IN) begin
den <= 1'b0;
dwe <= 1'b0;
di <= 16'h0000;
drp_state <= 0;
drp_state[DRP_WAIT] <= 1'b1;
end
else begin
drp_state <= 0;
case (1'b1) // synthesis parallel_case full_case
drp_state[DRP_WAIT]:
begin
if (rd) drp_state[DRP_READ] <= 1'b1;
else if (wr) drp_state[DRP_WRITE] <= 1'b1;
else drp_state[DRP_WAIT] <= 1'b1;
end
drp_state[DRP_READ]:
begin
den <= 1'b1;
drp_state[DRP_READ_ACK] <= 1'b1;
end
drp_state[DRP_READ_ACK]:
begin
den <= 1'b0;
if (drdy == 1'b1) begin
if (rd) drp_state[DRP_DONE] <= 1'b1;
else drp_state[DRP_MODIFY] <= 1'b1;
end
else drp_state[DRP_READ_ACK] <= 1'b1;
end
drp_state[DRP_MODIFY]:
begin
drp_state[DRP_WRITE] <= 1'b1;
end
drp_state[DRP_WRITE]:
begin
den <= 1'b1;
dwe <= 1'b1;
di <= di_msk;
drp_state[DRP_WRITE_ACK] <= 1'b1;
end
drp_state[DRP_WRITE_ACK]:
begin
den <= 1'b0;
dwe <= 1'b0;
if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
else drp_state[DRP_WRITE_ACK] <= 1'b1;
end
drp_state[DRP_DONE]:
begin
drp_state[DRP_WAIT] <= 1'b1;
end
endcase
end
end
//debug logic - convert one hot state to binary
genvar i,j;
generate
for (j=0; j<5; j=j+1)
begin : jl
wire [32-1:0] tmp_mask;
for (i=0; i<32; i=i+1)
begin : il
assign tmp_mask[i] = i[j];
end
assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
end
endgenerate
endmodule //CPLL_CAL
|
/***********************************************************************
File: cfg.v
Rev: 3.0.0
This is the user configurable options file for Xilinx's PCI Logicore.
Copyright (c) 2003 Xilinx, Inc. All rights reserved.
***********************************************************************/
`define MEMORY 1'b0
`define IO 1'b1
`define DISABLE 1'b0
`define ENABLE 1'b1
`define PREFETCH 1'b1
`define NOFETCH 1'b0
`define IO_PREFETCH 1'b1
`define TYPE00 2'b00
`define TYPE01 2'b01
`define TYPE10 2'b10
`define IO_TYPE 2'b11
// BAR sizes in bytes
`define SIZE2G 32'h8000_0000
`define SIZE1G 32'hc000_0000
`define SIZE512M 32'he000_0000
`define SIZE256M 32'hf000_0000
`define SIZE128M 32'hf800_0000
`define SIZE64M 32'hfc00_0000
`define SIZE32M 32'hfe00_0000
`define SIZE16M 32'hff00_0000
`define SIZE8M 32'hff80_0000
`define SIZE4M 32'hffc0_0000
`define SIZE2M 32'hffe0_0000
`define SIZE1M 32'hfff0_0000
`define SIZE512K 32'hfff8_0000
`define SIZE256K 32'hfffc_0000
`define SIZE128K 32'hfffe_0000
`define SIZE64K 32'hffff_0000
`define SIZE32K 32'hffff_8000
`define SIZE16K 32'hffff_c000
`define SIZE8K 32'hffff_e000
`define SIZE4K 32'hffff_f000
`define SIZE2K 32'hffff_f800
`define SIZE1K 32'hffff_fc00
`define SIZE512 32'hffff_fe00
`define SIZE256 32'hffff_ff00
`define SIZE128 32'hffff_ff80
`define SIZE64 32'hffff_ffc0
`define SIZE32 32'hffff_ffe0
`define SIZE16 32'hffff_fff0
module cfg ( CFG );
// Declare the port directions.
output [255:0] CFG;
/*************************************************************/
/* Configure Device, Vendor ID, Class Code, and Revision ID */
/*************************************************************/
// Device ID and Vendor ID
assign CFG[151:120] = 32'h0001_FEED ;
// Class Code and Revision ID
assign CFG[183:152] = 32'h02000000 ;
/*************************************************************/
/* Configure Subsystem ID and SubVendor ID */
/*************************************************************/
// Subsystem ID and Subvendor ID
assign CFG[215:184] = 32'h0000_FEED ;
// External Subsystem ID and Subvendor ID
assign CFG[114] = `DISABLE ;
/*************************************************************/
/* Configure Base Address Registers */
/*************************************************************/
// BAR0
assign CFG[0] = `ENABLE ;
assign CFG[32:1] = `SIZE128M ;
assign CFG[33] = `NOFETCH ;
assign CFG[35:34] = `TYPE00 ;
assign CFG[36] = `MEMORY ;
// BAR1
assign CFG[37] = `DISABLE ;
assign CFG[69:38] = `SIZE2G ;
assign CFG[70] = `NOFETCH ;
assign CFG[72:71] = `TYPE00 ;
assign CFG[73] = `MEMORY ;
// BAR2
assign CFG[74] = `DISABLE ;
assign CFG[106:75] = `SIZE2G ;
assign CFG[107] = `NOFETCH ;
assign CFG[109:108] = `TYPE00 ;
assign CFG[110] = `MEMORY ;
/*************************************************************/
/* Configure MAX_LAT MIN_GNT */
/*************************************************************/
assign CFG[231:224] = 8'h00 ;
assign CFG[223:216] = 8'h00 ;
/************************************************************/
/* Configure other PCI options */
/************************************************************/
// Latency Timer Enable
assign CFG[112] = `ENABLE ;
// Interrupt Enable
assign CFG[113] = `ENABLE ;
/************************************************************/
/* For advanced users only. */
/************************************************************/
// Capability List Enable
assign CFG[116] = `DISABLE ;
// Capability List Pointer
assign CFG[239:232] = 8'h00 ;
// User Config Space Enable
assign CFG[118] = `DISABLE ;
// Interrupt Acknowledge
assign CFG[240] = `DISABLE ;
/*****************************************************/
/* Do not modify any of the following settings! */
/*****************************************************/
// Obsolete
assign CFG[111] = `DISABLE ;
// Obsolete
assign CFG[117] = `DISABLE ;
// Obsolete
assign CFG[119] = `DISABLE ;
// Enable 66 MHz
assign CFG[244] = `DISABLE ;
assign CFG[254:245] = 10'b0010000000;
// Do Not Modify
assign CFG[115] = `DISABLE ;
assign CFG[241] = `DISABLE ;
assign CFG[242] = `DISABLE ;
assign CFG[243] = `DISABLE ;
assign CFG[255] = `DISABLE ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_2_V
`define SKY130_FD_SC_HS__DFRBP_2_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrbp_2 (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrbp_2 (
RESET_B,
CLK ,
D ,
Q ,
Q_N
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_2_V
|
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Filename: axi_4lite_ipif_wrapper.v
// Version: v1.00.a
// Description: A simple wrapper to convert between simple generics and
// those used in the axi_ipif block
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_cmb"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port "*_i"
// device pins: "*_pin"
// ports: - Names begin with Uppercase
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>
//-----------------------------------------------------------------------------
module axi4_lite_ipif_wrapper #(
parameter C_BASE_ADDRESS = 32'h00,
parameter C_ADDR_RANGE_SIZE = 32'h7FF
) (
//System signals
input s_axi_aclk,
input s_axi_aresetn,
input [31:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input s_axi_wvalid,
output s_axi_wready,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
input [31:0] s_axi_araddr,
input s_axi_arvalid,
output s_axi_arready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rvalid,
input s_axi_rready,
// Controls to the IP/Ipif modules
output bus2ip_clk,
output bus2ip_reset,
output [31:0] bus2ip_addr,
output bus2ip_cs,
output bus2ip_rdce,
output bus2ip_wrce,
output [31:0] bus2ip_data,
input [31:0] ip2bus_data,
input ip2bus_wrack,
input ip2bus_rdack,
input ip2bus_error
);
// Stats 200-3FF, MAC 400-5FF, INTC 600-6FF, ADR 700-7FF
parameter C_BASE_ADDRESS_TEMAC = C_BASE_ADDRESS;
parameter C_HIGH_ADDRESS_TEMAC = C_BASE_ADDRESS + C_ADDR_RANGE_SIZE;
wire bus2ip_cs_int;
wire bus2ip_rdce_int;
wire bus2ip_wrce_int;
wire bus2ip_resetn;
wire ip2bus_rdack_comb;
wire ip2bus_wrack_comb;
reg local_wrack;
reg local_rdack;
reg cs_edge_reg;
assign bus2ip_reset = !bus2ip_resetn;
assign bus2ip_cs = bus2ip_cs_int;
assign bus2ip_rdce = bus2ip_rdce_int;
assign bus2ip_wrce = bus2ip_wrce_int;
// The axi_ipif_wrapper can only handle address ranges which are a power of 2 in size and
// the address range base address must be aligned to the same power of 2. For example
// with a C_ADDR_RANGE_SIZE of 0x7FF the base address could be 0x000, 0x800, 0x1000 etc.
// The TEMAC address range is 0x200-0x7FF with 0x0-0x1FF being reserved. Since the TEMAC
// doesn't use the 0x0-0x1FF range logic has been included to automatically ACK this range.
axi_lite_ipif #(
.C_S_AXI_MIN_SIZE (C_ADDR_RANGE_SIZE),
.C_DPHASE_TIMEOUT (16),
.C_NUM_ADDRESS_RANGES (1),
.C_TOTAL_NUM_CE (1),
.C_ARD_ADDR_RANGE_ARRAY ({C_BASE_ADDRESS_TEMAC, C_HIGH_ADDRESS_TEMAC}),
.C_ARD_NUM_CE_ARRAY ({8'd1}),
.C_FAMILY ("virtex6")
) axi_lite_top (
//System signals
.S_AXI_ACLK (s_axi_aclk),
.S_AXI_ARESETN (s_axi_aresetn),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWVALID (s_axi_awvalid),
.S_AXI_AWREADY (s_axi_awready),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (4'd0),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
.S_AXI_BRESP (s_axi_bresp),
.S_AXI_BVALID (s_axi_bvalid),
.S_AXI_BREADY (s_axi_bready),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARVALID (s_axi_arvalid),
.S_AXI_ARREADY (s_axi_arready),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Controls to the IP/ipif
.Bus2IP_Clk (bus2ip_clk),
.Bus2IP_Resetn (bus2ip_resetn),
.Bus2IP_Addr (bus2ip_addr),
.Bus2IP_RNW (),
.Bus2IP_BE (),
.Bus2IP_CS (bus2ip_cs_int),
.Bus2IP_RdCE (bus2ip_rdce_int),
.Bus2IP_WrCE (bus2ip_wrce_int),
.Bus2IP_Data (bus2ip_data),
.IP2Bus_Data (ip2bus_data),
.IP2Bus_WrAck (ip2bus_wrack_comb),
.IP2Bus_RdAck (ip2bus_rdack_comb),
.IP2Bus_Error (ip2bus_error)
);
// if the address range is 0x0 to 0x1ff then need to acknowledge locally
// as this address space is not used by the temac
always @(posedge bus2ip_clk)
begin
if (!bus2ip_resetn) begin
local_wrack <= 1'b0;
local_rdack <= 1'b0;
cs_edge_reg <= 1'b0;
end
else begin
cs_edge_reg <= bus2ip_cs_int;
if (bus2ip_addr[31:9] == 0 & (bus2ip_cs_int & !cs_edge_reg)) begin
if (bus2ip_rdce_int)
local_rdack <= 1'b1;
if (bus2ip_wrce_int)
local_wrack <= 1'b1;
end
else begin
local_wrack <= 1'b0;
local_rdack <= 1'b0;
end
end
end
assign ip2bus_rdack_comb = local_rdack | ip2bus_rdack;
assign ip2bus_wrack_comb = local_wrack | ip2bus_wrack;
endmodule
|
/*
Testbench for Average Filter
By Hsiang-Yi Chung
February, 2016
*/
`timescale 1 ns / 1 ps
module tb_avg_filter;
reg [11:0] in;
reg [10:0] dummy;
reg clk;
wire out_ready;
wire [11:0] out1;
wire [11:0] out2;
reg [16:0] test;
reg [5:0] i,j;
reg [16:0] tb_result1, tb_result2;
Average_Filter filter (.in(in), .clk(clk), .reset_n(1'b1), .out_ready(out_ready), .out1(out1), .out2(out2));
initial begin
test = 0;
for (j = 0; j < 16; j = j + 1) begin
for (i = 0; i < 16; i = i + 1) begin
in = $random;
test = test + in;
if(i == 7) begin
tb_result1 = test >> 3;
test = 0;
end else if (i == 15) begin
tb_result2 = test >> 3;
test = 0;
end
if(out_ready) begin
if((tb_result1 == out1) && (tb_result2 == out2))
$display("Correct: tb_result1 = %d, Out1 = %d, tb_result2 = %d, Out2 = %d. ", tb_result1, out1, tb_result2, out2);
else
$display("Error: tb_result1 = %d, Out1 = %d, tb_result2 = %d, Out2 = %d. ", tb_result1, out1, tb_result2, out2);
end
@(posedge clk);
@(posedge clk);
end
end
#1000 $finish;
end
initial begin
clk = 0;
forever #25 clk = ~clk; //50ns clock period (twice the 10Mhz ADC sampling rate)
end
endmodule
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This latency aware read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post reads until the length register
reaches a value of zero. When all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
*/
// altera message_off 10230
module latency_aware_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire too_many_pending_reads;
reg too_many_pending_reads_d1;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// control logic
assign too_many_pending_reads = (fifo_used + reads_pending) >= (FIFODEPTH - 4);
assign master_read = (length != 0) & (too_many_pending_reads_d1 == 0);
assign increment_address = (length != 0) & (too_many_pending_reads_d1 == 0) & (master_waitrequest == 0);
assign control_done = (reads_pending == 0) & (length == 0); // master done posting reads and all reads have returned
assign control_early_done = (length == 0); // if you need all the pending reads to return then use 'control_done' instead of this signal
always @ (posedge clk)
begin
if (reset == 1)
begin
too_many_pending_reads_d1 <= 0;
end
else
begin
too_many_pending_reads_d1 <= too_many_pending_reads;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + 1;
end
else
begin
reads_pending <= reads_pending; // a read was posted, but another returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // read was not posted but a read returned
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_SYMBOL_V
`define SKY130_FD_SC_HVL__XOR2_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xor2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_SYMBOL_V
|
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