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//
// Copyright (C) 2015-2019 Markus Hiienkari <[email protected]>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`include "lat_tester_includes.v"
`define TRUE 1'b1
`define FALSE 1'b0
`define HI 1'b1
`define LO 1'b0
`define HSYNC_POL `LO
`define VSYNC_POL `LO
`define V_MULTMODE_1X 3'd0
`define V_MULTMODE_2X 3'd1
`define V_MULTMODE_3X 3'd2
`define V_MULTMODE_4X 3'd3
`define V_MULTMODE_5X 3'd4
`define PCLK_MUX_1X 2'd0
`define PCLK_MUX_2X 2'd2
`define PCLK_MUX_3X 2'd2
`define PCLK_MUX_4X 2'd3
`define PCLK_MUX_5X 2'd3
`define H_MULTMODE_FULLWIDTH 2'h0
`define H_MULTMODE_ASPECTFIX 2'h1
`define H_MULTMODE_OPTIMIZED 2'h2
`define H_MULTMODE_OPTIMIZED_1X 2'h3
`define SCANLINES_HYBR_CONTR_LOW 2'h1
`define SCANLINES_HYBR_CONTR_MED 2'h2
`define SCANLINES_HYBR_CONTR_HIGH 2'h3
`define VSYNCGEN_LEN 6
`define VSYNCGEN_GENMID_BIT 0
`define VSYNCGEN_CHOPMID_BIT 1
`define FID_ODD 1'b0
`define FID_EVEN 1'b1
`define MIN_VALID_LINES 256 //power of 2 optimization -> ignore lower bits with comparison
`define DBLFRAME_THOLD 5
`define FALSE_FIELD (fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] & (FID_in == `FID_EVEN))
`define HSYNC_LEADING_EDGE ((HSYNC_in_L == `HI) & (HSYNC_in == `LO))
`define VSYNC_LEADING_EDGE ((VSYNC_in_L == `HI) & (VSYNC_in == `LO))
`define PP_PL_START 1
`define PP_HS_VS_DE_START 2
`define PP_ENABLES_START 2
`define PP_RGB_START 4
//`define PP_RLPF_PL_START_EARLY // set if start with 2
`define PP_RLPF_PL_START `PP_RGB_START // minimum 2
`define PP_RLPF_PL_LENGTH 3 // counted from aquisition
`define PP_SLGEN_PL_LENGTH 5
`define PP_LT_BORDER_GEN_LENGTH 1 // lt_box / border_mask gen
`define PP_RLPF_PL_END (`PP_RLPF_PL_START+`PP_RLPF_PL_LENGTH)
`define PP_SLGEN_PL_END (`PP_RLPF_PL_END+`PP_SLGEN_PL_LENGTH)
`define PP_PIPELINE_LENGTH (`PP_SLGEN_PL_END+`PP_LT_BORDER_GEN_LENGTH-1'b1)
module scanconverter (
input reset_n,
input [7:0] R_in,
input [7:0] G_in,
input [7:0] B_in,
input FID_in,
input VSYNC_in,
input HSYNC_in,
input PCLK_in,
input clk27,
input enable_sc,
input [31:0] h_config,
input [31:0] h_config2,
input [31:0] v_config,
input [31:0] misc_config,
input [31:0] sl_config,
input [31:0] sl_config2,
output PCLK_out,
output reg [7:0] R_out,
output reg [7:0] G_out,
output reg [7:0] B_out,
output reg HSYNC_out,
output reg VSYNC_out,
output reg DE_out,
output h_unstable,
output reg [1:0] fpga_vsyncgen,
output pll_lock_lost,
output reg [10:0] vmax,
output reg [10:0] vmax_tvp,
output reg [19:0] pcnt_frame,
output ilace_flag,
output vsync_flag,
input lt_active,
input [1:0] lt_mode,
output reg [10:0] xpos,
output reg [10:0] ypos,
input pll_areset,
input pll_scanclk,
input pll_scanclkena,
input pll_configupdate,
input pll_scandata,
output pll_scandone,
output pll_activeclock
);
//clock-related signals and registers
wire pclk_act;
wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
wire [1:0] pclk_mux_sel;
wire pll_lock;
reg pll_clkswitch;
//RGB signals®isters: 8 bits per component -> 16.7M colors
wire [7:0] R_act, G_act, B_act;
wire [7:0] R_lbuf, G_lbuf, B_lbuf;
reg [7:0] R_in_L, G_in_L, B_in_L, R_in_LL, G_in_LL, B_in_LL, R_in_LLL, G_in_LLL, B_in_LLL, R_1x, G_1x, B_1x;
//H+V syncs + data enable signals®isters
wire HSYNC_act, VSYNC_act, DE_act;
reg HSYNC_in_L, VSYNC_in_L;
reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x;
reg VSYNC_1x, VSYNC_2x, VSYNC_3x, VSYNC_4x, VSYNC_5x;
reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x, DE_3x_prev4x;
//registers indicating line/frame change and field type
reg FID_cur, FID_last, FID_prev, FID_1x;
reg frame_change, frame_change_longpulse, line_change;
//H+V counters
reg [11:0] linebuf_hoffset_pp; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
wire [11:0] linebuf_hoffset_act;
wire [11:0] hcnt_act;
reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_2x_opt, hcnt_3x_opt, hcnt_3x_lace_ref, hcnt_4x_opt, hcnt_5x_opt, hcnt_5x_hscomp;
reg [2:0] hcnt_2x_opt_ctr, hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
wire [10:0] vcnt_act;
reg [10:0] vcnt_tvp, vcnt_1x, vcnt_2x, vcnt_3x, vcnt_4x, vcnt_5x; //max. 2047
//other counters
wire [2:0] line_id_act, col_id_act;
reg [11:0] hmax[0:1];
reg [11:0] hmax_3x;
reg line_idx;
reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
reg [2:0] line_out_idx_5x;
reg [23:0] warn_h_unstable, warn_pll_lock_lost;
// post-processing pipeline
reg HSYNC_pp[1:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg VSYNC_pp[1:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg DE_pp[1:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg [7:0] R_pp[3:`PP_PIPELINE_LENGTH], G_pp[3:`PP_PIPELINE_LENGTH], B_pp[3:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg [11:0] hcnt_pp /* synthesis ramstyle = "logic" */;
reg [10:0] vcnt_pp /* synthesis ramstyle = "logic" */;
reg rlpf_trigger_r[1:`PP_RLPF_PL_START-1] /* synthesis ramstyle = "logic" */;
reg [7:0] R_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1], G_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1], B_prev_pp[`PP_RLPF_PL_START:`PP_RLPF_PL_END-1] /* synthesis ramstyle = "logic" */;
reg [2:0] line_id_pp[1:`PP_SLGEN_PL_END-5], col_id_pp[1:`PP_SLGEN_PL_END-5] /* synthesis ramstyle = "logic" */;
reg draw_sl_pp[`PP_SLGEN_PL_END-4:`PP_SLGEN_PL_END-1] /* synthesis ramstyle = "logic" */;
reg border_enable_pp[2:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
reg lt_box_enable_pp[2:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
//helper registers for sampling at synchronized clock edges
reg pclk_1x_prev3x;
reg [1:0] pclk_3x_cnt;
reg pclk_1x_prev4x;
reg [1:0] pclk_4x_cnt;
reg pclk_1x_prev5x;
reg pclk_1x_prevprev5x;
reg [2:0] pclk_5x_cnt;
//configuration registers
reg [10:0] H_ACTIVE; //max. 2047
reg [9:0] H_AVIDSTART; //max. 1023
reg [10:0] V_ACTIVE; //max. 2047
reg [7:0] V_AVIDSTART; //max. 255
reg [7:0] H_SYNCLEN;
reg [2:0] V_SYNCLEN;
reg [5:0] V_MASK;
reg [2:0] V_MULTMODE;
reg [1:0] H_MULTMODE;
reg [10:0] H_MASK;
reg [9:0] H_OPT_STARTOFF;
reg [2:0] H_OPT_SCALE;
reg [2:0] H_OPT_SAMPLE_MULT;
reg [2:0] H_OPT_SAMPLE_SEL;
reg [9:0] H_L5BORDER;
reg [9:0] H_L3BORDER;
reg [11:0] H_L3_OPT_START;
reg [3:0] X_MASK_BR;
reg [2:0] X_MASK_COLOR;
reg [5:0] X_REV_LPF_STR;
reg [3:0] SL_L_STR[4:0] /* synthesis ramstyle = "logic" */;
reg [3:0] SL_C_STR[5:0] /* synthesis ramstyle = "logic" */;
reg [4:0] SL_HYBRSTR;
reg [4:0] SL_L_OVERLAY;
reg [5:0] SL_C_OVERLAY;
reg SL_METHOD;
reg SL_NO_ALTERN;
reg SL_ALTIV;
reg X_REV_LPF_ENABLE;
reg X_PANASONIC_HACK;
// constants for each frame to be calculated off config-registers
reg CALC_CONSTS;
reg [11:0] H_AVIDSTOP;
reg [10:0] V_AVIDSTOP;
reg [10:0] H_AVIDMASK_START;
reg [11:0] H_AVIDMASK_STOP;
reg [7:0] V_AVIDMASK_START;
reg [10:0] V_AVIDMASK_STOP;
reg [11:0] LT_POS_TOPLEFT_BOX_H_STOP;
reg [11:0] LT_POS_TOPLEFT_BOX_V_STOP;
reg [11:0] LT_POS_CENTER_BOX_H_START;
reg [11:0] LT_POS_CENTER_BOX_H_STOP;
reg [11:0] LT_POS_CENTER_BOX_V_START;
reg [11:0] LT_POS_CENTER_BOX_V_STOP;
reg [11:0] LT_POS_BOTTOMRIGHT_H_START;
reg [10:0] LT_POS_BOTTOMRIGHT_V_START;
//clk27 related registers
reg VSYNC_in_cc_L, VSYNC_in_cc_LL, VSYNC_in_cc_LLL;
reg [21:0] clk27_ctr; // min. 6.5Hz
reg [2:0] dbl_frame_ctr;
reg frame_change_longpulse_cc_L, frame_change_longpulse_cc_LL, frame_change_longpulse_cc_LLL;
reg [19:0] pcnt_ctr;
assign pclk_1x = PCLK_in;
assign PCLK_out = pclk_act;
assign ilace_flag = (FID_cur != FID_last);
//Scanline generation
reg [8:0] Y_rb_tmp;
reg [9:0] Y;
wire [8:0] Y_sl_hybr_ref_pre, R_sl_hybr_ref_pre, G_sl_hybr_ref_pre, B_sl_hybr_ref_pre;
lpm_mult_4_hybr_ref_pre Y_sl_hybr_ref_pre_u
(
.clock(pclk_act),
.dataa(Y[9:2]),
.datab(SL_HYBRSTR),
.result(Y_sl_hybr_ref_pre)
);
lpm_mult_4_hybr_ref_pre R_sl_hybr_ref_pre_u
(
.clock(pclk_act),
.dataa(R_pp[`PP_RLPF_PL_END]),
.datab(SL_HYBRSTR),
.result(R_sl_hybr_ref_pre)
);
lpm_mult_4_hybr_ref_pre G_sl_hybr_ref_pre_u
(
.clock(pclk_act),
.dataa(G_pp[`PP_RLPF_PL_END]),
.datab(SL_HYBRSTR),
.result(G_sl_hybr_ref_pre)
);
lpm_mult_4_hybr_ref_pre B_sl_hybr_ref_pre_u
(
.clock(pclk_act),
.dataa(B_pp[`PP_RLPF_PL_END]),
.datab(SL_HYBRSTR),
.result(B_sl_hybr_ref_pre)
);
wire [8:0] Y_sl_hybr_ref, R_sl_hybr_ref, G_sl_hybr_ref, B_sl_hybr_ref;
lpm_mult_4_hybr_ref Y_sl_hybr_ref_u
(
.clock(pclk_act),
.dataa(Y_sl_hybr_ref_pre),
.datab(sl_str_tmp),
.result(Y_sl_hybr_ref)
);
lpm_mult_4_hybr_ref R_sl_hybr_ref_u
(
.clock(pclk_act),
.dataa(R_sl_hybr_ref_pre),
.datab(sl_str_tmp),
.result(R_sl_hybr_ref)
);
lpm_mult_4_hybr_ref G_sl_hybr_ref_u
(
.clock(pclk_act),
.dataa(G_sl_hybr_ref_pre),
.datab(sl_str_tmp),
.result(G_sl_hybr_ref)
);
lpm_mult_4_hybr_ref B_sl_hybr_ref_u
(
.clock(pclk_act),
.dataa(B_sl_hybr_ref_pre),
.datab(sl_str_tmp),
.result(B_sl_hybr_ref)
);
reg [7:0] sl_str, sl_str_tmp, Y_sl_str, R_sl_str, G_sl_str, B_sl_str;
reg [7:0] R_sl_sub, G_sl_sub, B_sl_sub;
wire [7:0] R_sl_mult, G_sl_mult, B_sl_mult;
lpm_mult_4_sl R_sl_mult_u
(
.clock(pclk_act),
.dataa(R_pp[`PP_SLGEN_PL_END-2]),
.datab(~Y_sl_str),
.result(R_sl_mult)
);
lpm_mult_4_sl G_sl_mult_u
(
.clock(pclk_act),
.dataa(G_pp[`PP_SLGEN_PL_END-2]),
.datab(~Y_sl_str),
.result(G_sl_mult)
);
lpm_mult_4_sl B_sl_mult_u
(
.clock(pclk_act),
.dataa(B_pp[`PP_SLGEN_PL_END-2]),
.datab(~Y_sl_str),
.result(B_sl_mult)
);
//Reverse LPF
wire rlpf_trigger_act;
reg signed [14:0] R_diff_s15_pre, G_diff_s15_pre, B_diff_s15_pre, R_diff_s15, G_diff_s15, B_diff_s15;
reg signed [10:0] R_rlpf_result, G_rlpf_result, B_rlpf_result;
function [7:0] apply_reverse_lpf;
input [7:0] data_prev;
input signed [14:0] diff;
reg signed [10:0] result;
begin
// result = ({3'b0,data_prev,4'b0} - diff) >>> 4;
result = {3'b0,data_prev} + ~diff[14:4]; // allow for a small error to reduce adder length
apply_reverse_lpf = result[10] ? 8'h00 : |result[9:8] ? 8'hFF : result[7:0];
end
endfunction
//Mux for active data selection
//
//List of critical signals:
// [RGB]_act, DE_act, HSYNC_act, VSYNC_act
//
//Non-critical signals and inactive clock combinations filtered out in SDC
always @(*)
case (V_MULTMODE)
default: begin //`V_MULTMODE_1X
R_act = R_1x;
G_act = G_1x;
B_act = B_1x;
HSYNC_act = HSYNC_1x;
VSYNC_act = VSYNC_1x;
DE_act = DE_1x;
line_id_act = {2'b00, vcnt_1x[0]};
hcnt_act = hcnt_1x;
vcnt_act = vcnt_1x;
pclk_mux_sel = `PCLK_MUX_1X;
linebuf_hoffset_act = 0;
col_id_act = {2'b00, hcnt_1x[0]};
rlpf_trigger_act = 1'b1;
end
`V_MULTMODE_2X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
HSYNC_act = HSYNC_2x;
VSYNC_act = VSYNC_2x;
DE_act = DE_2x;
line_id_act = SL_NO_ALTERN ? {2'b0, {line_out_idx_2x[0]+FID_1x}} : {1'b0, line_out_idx_2x};
hcnt_act = hcnt_2x;
vcnt_act = vcnt_2x;
case (H_MULTMODE)
default: begin //`H_MULTMODE_FULLWIDTH
pclk_mux_sel = `PCLK_MUX_2X;
linebuf_hoffset_act = hcnt_2x;
col_id_act = {2'b00, hcnt_2x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_OPTIMIZED_1X: begin
pclk_mux_sel = `PCLK_MUX_1X; //special case: pclk bypass to enable 2x native sampling
linebuf_hoffset_act = hcnt_2x_opt;
col_id_act = {2'b00, hcnt_2x[1]};
rlpf_trigger_act = (hcnt_2x_opt_ctr == 0);
end
`H_MULTMODE_OPTIMIZED: begin
pclk_mux_sel = `PCLK_MUX_2X;
linebuf_hoffset_act = hcnt_2x_opt;
col_id_act = hcnt_2x_opt_ctr;
rlpf_trigger_act = (hcnt_2x_opt_ctr == 0);
end
endcase
end
`V_MULTMODE_3X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
HSYNC_act = HSYNC_3x;
VSYNC_act = VSYNC_3x;
DE_act = DE_3x;
line_id_act = {1'b0, line_out_idx_3x};
vcnt_act = vcnt_3x;
case (H_MULTMODE)
default: begin //`H_MULTMODE_FULLWIDTH
pclk_mux_sel = `PCLK_MUX_3X;
linebuf_hoffset_act = hcnt_3x;
hcnt_act = hcnt_3x;
col_id_act = {2'b00, hcnt_3x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_ASPECTFIX: begin
pclk_mux_sel = `PCLK_MUX_4X;
linebuf_hoffset_act = hcnt_4x_aspfix;
hcnt_act = hcnt_4x_aspfix;
col_id_act = {2'b00, hcnt_4x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_OPTIMIZED: begin
pclk_mux_sel = `PCLK_MUX_3X;
linebuf_hoffset_act = hcnt_3x_opt;
hcnt_act = hcnt_3x;
col_id_act = hcnt_3x_opt_ctr;
rlpf_trigger_act = (hcnt_3x_opt_ctr == 0);
end
endcase
end
`V_MULTMODE_4X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
HSYNC_act = HSYNC_4x;
VSYNC_act = VSYNC_4x;
DE_act = DE_4x;
line_id_act = SL_NO_ALTERN ? {1'b0, {line_out_idx_4x+{FID_1x, 1'b0}}} : {1'b0, line_out_idx_4x};
hcnt_act = hcnt_4x;
vcnt_act = vcnt_4x;
pclk_mux_sel = `PCLK_MUX_4X;
case (H_MULTMODE)
default: begin //`H_MULTMODE_FULLWIDTH
linebuf_hoffset_act = hcnt_4x;
col_id_act = {2'b00, hcnt_4x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_OPTIMIZED: begin
linebuf_hoffset_act = hcnt_4x_opt;
col_id_act = hcnt_4x_opt_ctr;
rlpf_trigger_act = (hcnt_4x_opt_ctr == 0);
end
endcase
end
`V_MULTMODE_5X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
HSYNC_act = HSYNC_5x;
VSYNC_act = VSYNC_5x;
DE_act = DE_5x;
line_id_act = line_out_idx_5x;
hcnt_act = hcnt_5x;
vcnt_act = vcnt_5x;
pclk_mux_sel = `PCLK_MUX_5X;
case (H_MULTMODE)
default: begin //`H_MULTMODE_FULLWIDTH
linebuf_hoffset_act = hcnt_5x_hscomp;
col_id_act = {2'b00, hcnt_5x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_OPTIMIZED: begin
linebuf_hoffset_act = hcnt_5x_opt;
col_id_act = hcnt_5x_opt_ctr;
rlpf_trigger_act = (hcnt_5x_opt_ctr == 0);
end
endcase
end
endcase
pll_2x pll_pclk (
.areset(pll_areset),
.clkswitch(pll_clkswitch),
.configupdate(pll_configupdate),
.inclk0(clk27), // set videogen clock to primary (power-on default) since both reference clocks must be running during switchover
.inclk1(PCLK_in), // is the secondary input clock fully compensated?
.scanclk(pll_scanclk),
.scanclkena(pll_scanclkena),
.scandata(pll_scandata),
.activeclock(pll_activeclock),
.c0(pclk_2x), // pclk_3x in secondary config
.c1(pclk_5x), // pclk_4x in secondary config
.locked(pll_lock),
.scandataout(),
.scandone(pll_scandone)
);
assign pclk_3x = pclk_2x;
assign pclk_4x = pclk_5x;
cycloneive_clkctrl clkctrl1 (
.clkselect(enable_sc ? pclk_mux_sel : 2'h2),
.ena(1'b1),
.inclk({pclk_5x, pclk_2x, 1'b0, pclk_1x}), // fitter forbids using both clk27 and pclk_1x here since they're on opposite sides
.outclk(pclk_act)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "falling edge",
clkctrl1.lpm_type = "cycloneive_clkctrl";
wire [11:0] linebuf_rdaddr = linebuf_hoffset_pp-H_AVIDSTART;
wire [11:0] linebuf_wraddr = hcnt_1x-H_AVIDSTART;
//TODO: add secondary buffers for interlaced signals with alternative field order
linebuf linebuf_rgb (
.data({R_in_L, G_in_L, B_in_L}),
.rdaddress ( {~line_idx, linebuf_rdaddr[10:0]} ),
.rdclock ( pclk_act ),
.wraddress( {line_idx, linebuf_wraddr[10:0]} ),
.wrclock ( pclk_1x ),
.wren ( !linebuf_wraddr[11] ),
.q ( {R_lbuf, G_lbuf, B_lbuf} )
);
//Postprocess pipeline
//
// Latency with respect to h_cnt/v_cnt before 1st stage:
// line_id, col_id: 0 cycles
// HSYNC, VSYNC, DE: 1 cycle
// RGB: 2 cycles
//
// Pipeline structure
// | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 |
// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
// | RADDR | | | | | | | | | | | |
// | | LBUF | LBUF | | | | | | | | | |
// | | | | RLPF | RLPF | RLPF | | | | | | |
// | | | | | Y | Y | | | | | | |
// | | | | | | | SLG | SLG | SLG | SLG | SLG | |
// | | | | | | | | | | | | MASK |
// | | | | | | | | | | | | LTBOX |
integer pp_idx;
always @(posedge pclk_act)
begin
line_id_pp[`PP_PL_START] <= SL_ALTIV ? {2'b00, vcnt_act[0]} : line_id_act;
col_id_pp[`PP_PL_START] <= col_id_act;
for(pp_idx = `PP_PL_START+1; pp_idx <= `PP_SLGEN_PL_END-5; pp_idx = pp_idx+1) begin
line_id_pp[pp_idx] <= line_id_pp[pp_idx-1];
col_id_pp[pp_idx] <= col_id_pp[pp_idx-1];
end
hcnt_pp <= hcnt_act;
vcnt_pp <= vcnt_act;
linebuf_hoffset_pp <= linebuf_hoffset_act;
xpos <= hcnt_pp - H_AVIDSTART;
ypos <= vcnt_pp - V_AVIDSTART;
border_enable_pp[`PP_ENABLES_START] <= ((hcnt_pp < H_AVIDMASK_START) | (hcnt_pp >= H_AVIDMASK_STOP) | (vcnt_pp < V_AVIDMASK_START) | (vcnt_pp >= V_AVIDMASK_STOP));
case (lt_mode)
default: begin
lt_box_enable_pp[`PP_ENABLES_START] <= 0;
end
`LT_POS_TOPLEFT: begin
lt_box_enable_pp[`PP_ENABLES_START] <= ((hcnt_pp < LT_POS_TOPLEFT_BOX_H_STOP) && (vcnt_pp < LT_POS_TOPLEFT_BOX_V_STOP)) ? 1'b1 : 1'b0;
end
`LT_POS_CENTER: begin
lt_box_enable_pp[`PP_ENABLES_START] <= ((hcnt_pp >= LT_POS_CENTER_BOX_H_START) && (hcnt_pp < LT_POS_CENTER_BOX_H_STOP) && (vcnt_pp >= LT_POS_CENTER_BOX_V_START) && (vcnt_pp < LT_POS_CENTER_BOX_V_STOP)) ? 1'b1 : 1'b0;
end
`LT_POS_BOTTOMRIGHT: begin
lt_box_enable_pp[`PP_ENABLES_START] <= ((hcnt_pp >= LT_POS_BOTTOMRIGHT_H_START) && (vcnt_pp >= LT_POS_BOTTOMRIGHT_V_START)) ? 1'b1 : 1'b0;
end
endcase
for(pp_idx = `PP_ENABLES_START+1; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
lt_box_enable_pp[pp_idx] <= lt_box_enable_pp[pp_idx-1];
border_enable_pp[pp_idx] <= border_enable_pp[pp_idx-1];
end
HSYNC_pp[`PP_HS_VS_DE_START] <= HSYNC_act;
VSYNC_pp[`PP_HS_VS_DE_START] <= VSYNC_act;
DE_pp[`PP_HS_VS_DE_START] <= DE_act;
for(pp_idx = `PP_HS_VS_DE_START+1; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
HSYNC_pp[pp_idx] <= HSYNC_pp[pp_idx-1];
VSYNC_pp[pp_idx] <= VSYNC_pp[pp_idx-1];
DE_pp[pp_idx] <= DE_pp[pp_idx-1];
end
HSYNC_out <= HSYNC_pp[`PP_PIPELINE_LENGTH];
VSYNC_out <= VSYNC_pp[`PP_PIPELINE_LENGTH];
DE_out <= DE_pp[`PP_PIPELINE_LENGTH];
// get RGB and delay it
R_pp[`PP_RGB_START] <= R_act;
G_pp[`PP_RGB_START] <= G_act;
B_pp[`PP_RGB_START] <= B_act;
for(pp_idx = `PP_RGB_START+1; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx + 1) begin
R_pp[pp_idx] <= R_pp[pp_idx-1];
G_pp[pp_idx] <= G_pp[pp_idx-1];
B_pp[pp_idx] <= B_pp[pp_idx-1];
end
R_out <= R_pp[`PP_PIPELINE_LENGTH];
G_out <= G_pp[`PP_PIPELINE_LENGTH];
B_out <= B_pp[`PP_PIPELINE_LENGTH];
// reverse LPF ...
rlpf_trigger_r[`PP_PL_START] <= rlpf_trigger_act;
for(pp_idx = `PP_PL_START+1; pp_idx <= `PP_RLPF_PL_START-1; pp_idx = pp_idx + 1)
rlpf_trigger_r[pp_idx] <= rlpf_trigger_r[pp_idx-1];
// Optimized modes repeat pixels. Save previous pixel only when linebuffer offset changes.
if (rlpf_trigger_r[`PP_RLPF_PL_START-1]) begin
`ifdef PP_RLPF_PL_START_EARLY
R_prev_pp[`PP_RLPF_PL_START] <= R_act;
G_prev_pp[`PP_RLPF_PL_START] <= G_act;
B_prev_pp[`PP_RLPF_PL_START] <= B_act;
`else
R_prev_pp[`PP_RLPF_PL_START] <= R_pp[`PP_RLPF_PL_START];
G_prev_pp[`PP_RLPF_PL_START] <= G_pp[`PP_RLPF_PL_START];
B_prev_pp[`PP_RLPF_PL_START] <= B_pp[`PP_RLPF_PL_START];
`endif
end
for(pp_idx = `PP_RLPF_PL_START+1; pp_idx <= `PP_RLPF_PL_END-1; pp_idx = pp_idx + 1) begin
R_prev_pp[pp_idx] <= R_prev_pp[pp_idx-1];
G_prev_pp[pp_idx] <= G_prev_pp[pp_idx-1];
B_prev_pp[pp_idx] <= B_prev_pp[pp_idx-1];
end
// ... step 1
`ifdef PP_RLPF_PL_START_EARLY
R_diff_s15_pre <= (R_prev_pp[`PP_RLPF_PL_START] - R_act);
G_diff_s15_pre <= (G_prev_pp[`PP_RLPF_PL_START] - G_act);
B_diff_s15_pre <= (B_prev_pp[`PP_RLPF_PL_START] - B_act);
`else
R_diff_s15_pre <= (R_prev_pp[`PP_RLPF_PL_START] - R_pp[`PP_RLPF_PL_START]);
G_diff_s15_pre <= (G_prev_pp[`PP_RLPF_PL_START] - G_pp[`PP_RLPF_PL_START]);
B_diff_s15_pre <= (B_prev_pp[`PP_RLPF_PL_START] - B_pp[`PP_RLPF_PL_START]);
`endif
// ... step 2
// R_diff_s15, G_diff_s15, B_diff_s15 are outputs of multiplier IPs 12 pp-stage delay)
R_diff_s15 <= (R_diff_s15_pre * X_REV_LPF_STR);
G_diff_s15 <= (G_diff_s15_pre * X_REV_LPF_STR);
B_diff_s15 <= (B_diff_s15_pre * X_REV_LPF_STR);
// ... step 3
if (X_REV_LPF_ENABLE) begin
R_pp[`PP_RLPF_PL_END] <= apply_reverse_lpf(R_prev_pp[`PP_RLPF_PL_END-1], R_diff_s15);
G_pp[`PP_RLPF_PL_END] <= apply_reverse_lpf(G_prev_pp[`PP_RLPF_PL_END-1], G_diff_s15);
B_pp[`PP_RLPF_PL_END] <= apply_reverse_lpf(B_prev_pp[`PP_RLPF_PL_END-1], B_diff_s15);
end
// calculate Y (based on non-reverseLPF values to keep pipeline length a bit lower)
Y_rb_tmp <= {1'b0,R_pp[`PP_RLPF_PL_END-2]} + {1'b0,B_pp[`PP_RLPF_PL_END-2]};
Y <= {1'b0,Y_rb_tmp} + {1'b0,G_pp[`PP_RLPF_PL_END-1],1'b0};
// modify scanline strength (3 pp-stages)
// ... step 1/3
// Y_sl_hybr_ref_tmp, R_sl_hybr_ref_tmp, G_sl_hybr_ref_tmp, B_sl_hybr_ref_tmp are outputs of multiplier IPs (1 pp-stage delay)
if (|(SL_L_OVERLAY & (5'h1<<line_id_pp[`PP_SLGEN_PL_END-5]))) begin
sl_str_tmp <= ((SL_L_STR[line_id_pp[`PP_SLGEN_PL_END-5]]+8'h01)<<4)-1'b1;
draw_sl_pp[`PP_SLGEN_PL_END-4] <= 1'b1;
end else if (|(SL_C_OVERLAY & (6'h1<<col_id_pp[`PP_SLGEN_PL_END-5]))) begin
sl_str_tmp <= ((SL_C_STR[col_id_pp[`PP_SLGEN_PL_END-5]]+8'h01)<<4)-1'b1;
draw_sl_pp[`PP_SLGEN_PL_END-4] <= 1'b1;
end else begin
draw_sl_pp[`PP_SLGEN_PL_END-4] <= 1'b0;
end
for(pp_idx = `PP_SLGEN_PL_END-3; pp_idx <= `PP_SLGEN_PL_END-1; pp_idx = pp_idx + 1) begin
draw_sl_pp[pp_idx] <= draw_sl_pp[pp_idx-1];
end
// ... step 2/3
// Y_sl_hybr_ref,R_sl_hybr_ref,G_sl_hybr_ref,B_sl_hybr_ref are outputs of multiplier IPs (1 pp-stage delay)
sl_str <= sl_str_tmp;
// ... step 3/3
Y_sl_str <= {1'b0,sl_str} < Y_sl_hybr_ref ? 8'h0 : sl_str - Y_sl_hybr_ref[7:0];
R_sl_str <= {1'b0,sl_str} < R_sl_hybr_ref ? 8'h0 : sl_str - R_sl_hybr_ref[7:0];
G_sl_str <= {1'b0,sl_str} < G_sl_hybr_ref ? 8'h0 : sl_str - G_sl_hybr_ref[7:0];
B_sl_str <= {1'b0,sl_str} < B_sl_hybr_ref ? 8'h0 : sl_str - B_sl_hybr_ref[7:0];
// perform scanline generation (1 pp-stage)
// R_sl_mult, G_sl_mult and B_sl_mult are registered outputs of IP blocks (1 pp-stage delay)
R_sl_sub <= (R_pp[`PP_SLGEN_PL_END-2] > R_sl_str) ? (R_pp[`PP_SLGEN_PL_END-2]-R_sl_str) : 8'h00;
G_sl_sub <= (G_pp[`PP_SLGEN_PL_END-2] > G_sl_str) ? (G_pp[`PP_SLGEN_PL_END-2]-G_sl_str) : 8'h00;
B_sl_sub <= (B_pp[`PP_SLGEN_PL_END-2] > B_sl_str) ? (B_pp[`PP_SLGEN_PL_END-2]-B_sl_str) : 8'h00;
// draw scanline (1 pp-stage)
if (draw_sl_pp[`PP_SLGEN_PL_END-1]) begin
R_pp[`PP_SLGEN_PL_END] <= SL_METHOD ? R_sl_sub : R_sl_mult;
G_pp[`PP_SLGEN_PL_END] <= SL_METHOD ? G_sl_sub : G_sl_mult;
B_pp[`PP_SLGEN_PL_END] <= SL_METHOD ? B_sl_sub : B_sl_mult;
end
// apply LT box / mask
if (lt_active) begin
R_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
G_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
B_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
end else if (border_enable_pp[`PP_PIPELINE_LENGTH]) begin
R_out <= X_MASK_COLOR[2] ? {2{X_MASK_BR}} : 8'h00;
G_out <= X_MASK_COLOR[1] ? {2{X_MASK_BR}} : 8'h00;
B_out <= X_MASK_COLOR[0] ? {2{X_MASK_BR}} : 8'h00;
end
end
//Generate a warning signal from horizontal instability or PLL sync loss
always @(posedge pclk_1x or negedge reset_n)
begin
if (!reset_n) begin
warn_h_unstable <= 1'b0;
warn_pll_lock_lost <= 1'b0;
end else begin
if (hmax[0] != hmax[1])
warn_h_unstable <= 1;
else if (warn_h_unstable != 0)
warn_h_unstable <= warn_h_unstable + 1'b1;
if ((V_MULTMODE > `V_MULTMODE_1X) & ~pll_lock)
warn_pll_lock_lost <= 1;
else if (warn_pll_lock_lost != 0)
warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1;
end
end
assign h_unstable = (warn_h_unstable != 0);
assign pll_lock_lost = (warn_pll_lock_lost != 0);
//Detect if TVP7002 is skipping VSYNCs. This occurs for interlaced signals fed via digital sync inputs,
//causing TVP7002 not to regenerate VSYNC for even field. Moreover, if leading edges of HSYNC and VSYNC are
//too far from each other for odd field, no VSYNC is regenerated at all. This can be avoided by disabling
//doubled sampling rates ("AV3 interlacefix") and/or minimizing VSYNC delay induced by RC filter on PCB.
//However, TVP7002 datasheet warns that HSYNC/VSYNC should not change simultaneously, so leaving out the
//filter may lead to stability issues and is not recommended. A combination of 220ohm resistor and 1nF
//capacitor seems to be optimal for 480i/576i, including doubled sampling rates.
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n) begin
fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] <= 1'b0;
VSYNC_in_cc_L <= 1'b0;
VSYNC_in_cc_LL <= 1'b0;
VSYNC_in_cc_LLL <= 1'b0;
clk27_ctr <= 0;
dbl_frame_ctr <= 0;
end else begin
if ((VSYNC_in_cc_LLL == `HI) && (VSYNC_in_cc_LL == `LO)) begin
// If calculated refresh rate is between 22Hz and 44Hz, assume TVP7002 has skipped a vsync
if ((clk27_ctr >= (27000000/44)) && (clk27_ctr <= (27000000/22)) && (dbl_frame_ctr < `DBLFRAME_THOLD))
dbl_frame_ctr <= dbl_frame_ctr + 1'b1;
else if ((clk27_ctr < (27000000/44)) && (dbl_frame_ctr > 0))
dbl_frame_ctr <= dbl_frame_ctr - 1'b1;
clk27_ctr <= 0;
end else if (clk27_ctr < (27000000/10)) begin //prevent overflow
clk27_ctr <= clk27_ctr + 1'b1;
end
if (dbl_frame_ctr == 0)
fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] <= 1'b0;
else if (dbl_frame_ctr == `DBLFRAME_THOLD)
fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] <= 1'b1;
VSYNC_in_cc_L <= VSYNC_in;
VSYNC_in_cc_LL <= VSYNC_in_cc_L;
VSYNC_in_cc_LLL <= VSYNC_in_cc_LL;
end
end
//Calculate exact vertical frequency
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n) begin
frame_change_longpulse_cc_L <= 1'b0;
frame_change_longpulse_cc_LL <= 1'b0;
frame_change_longpulse_cc_LLL <= 1'b0;
pcnt_ctr <= 1;
pcnt_frame <= 1;
end else begin
if (frame_change_longpulse_cc_LL & !frame_change_longpulse_cc_LLL) begin
pcnt_ctr <= 1;
pcnt_frame <= pcnt_ctr;
end else if (pcnt_ctr < 20'hfffff) begin
pcnt_ctr <= pcnt_ctr + 1'b1;
end
frame_change_longpulse_cc_L <= frame_change_longpulse;
frame_change_longpulse_cc_LL <= frame_change_longpulse_cc_L;
frame_change_longpulse_cc_LLL <= frame_change_longpulse_cc_LL;
end
end
// Control PLL reference clock switchover
always @(posedge clk27)
begin
pll_clkswitch <= (pll_activeclock != enable_sc);
end
//Forward status flag to CPU
assign vsync_flag = ~VSYNC_in_cc_LL;
wire [11:0] H_L5BORDER_1920_tmp = (11'd1920-h_config[10:0]);
wire [11:0] H_L5BORDER_1600_tmp = (11'd1600-h_config[10:0]);
//Buffer the inputs using input pixel clock and generate 1x signals
always @(posedge pclk_1x or negedge reset_n)
begin
if (!reset_n) begin
hcnt_1x <= 0;
vcnt_1x <= 0;
vcnt_tvp <= 0;
hmax[0] <= 0;
hmax[1] <= 0;
vmax <= 0;
vmax_tvp <= 0;
line_idx <= 0;
FID_cur <= 1'b0;
FID_last <= 1'b0;
line_change <= 1'b0;
frame_change <= 1'b0;
frame_change_longpulse <= 1'b0;
fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= 1'b0;
H_MULTMODE <= 0;
V_MULTMODE <= 0;
end else begin
if (`HSYNC_LEADING_EDGE) begin
hcnt_1x <= 0;
hmax[line_idx] <= hcnt_1x;
line_idx <= line_idx ^ 1'b1;
line_change <= 1'b1;
end else begin
hcnt_1x <= hcnt_1x + 1'b1;
line_change <= 1'b0;
end
if (`HSYNC_LEADING_EDGE) begin
if (`VSYNC_LEADING_EDGE) begin // non-interlace frame or odd field (interlace) start
FID_cur <= `FID_ODD;
FID_last <= FID_cur;
vcnt_1x <= 0;
frame_change <= 1'b1;
vmax <= vcnt_1x;
vcnt_tvp <= 0;
vmax_tvp <= vcnt_tvp;
end else begin
vcnt_1x <= vcnt_1x + 1'b1;
vcnt_tvp <= vcnt_tvp + 1'b1;
end
end else if (`VSYNC_LEADING_EDGE) begin // even field (interlace) start
if (!`FALSE_FIELD) begin
FID_cur <= `FID_EVEN;
FID_last <= FID_cur;
vcnt_1x <= 11'h7ff; // -1 for 11 bit word
frame_change <= 1'b1;
//vmax <= vcnt_1x;
end
vcnt_tvp <= 0;
vmax_tvp <= vcnt_tvp;
end else if ((fpga_vsyncgen[`VSYNCGEN_GENMID_BIT]) && (vcnt_tvp == (vmax_tvp>>1)) && (hcnt_1x == (hmax[~line_idx]>>1))) begin //VSM=1
FID_cur <= `FID_EVEN;
FID_last <= FID_cur;
vcnt_1x <= 11'h7ff; // -1 for 11 bit word
frame_change <= 1'b1;
//vmax <= vcnt_1x;
end else
frame_change <= 1'b0;
if (`VSYNC_LEADING_EDGE) begin
FID_prev <= FID_in;
// detect non-interlaced signal with consecutive even field signaling (TVP7002 detects it as interlaced with analog sync inputs).
// FID is updated at leading edge of VSYNC
if (FID_in == FID_prev)
fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= `FALSE;
else if (FID_in == `FID_EVEN) // TVP7002 falsely indicates field change with (vcnt < active_lines)
fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= (vcnt_tvp < `MIN_VALID_LINES);
end
if (frame_change) begin
//Read configuration data from CPU
H_MULTMODE <= h_config[31:30]; // Horizontal scaling mode
V_MULTMODE <= v_config[31:29]; // Line multiply mode
H_SYNCLEN <= h_config[27:20]; // Horizontal sync length (0...255)
H_AVIDSTART <= h_config[19:11] + h_config[27:20]; // Horizontal sync+backporch length (0...1023)
H_ACTIVE <= h_config[10:0]; // Horizontal active length (0...2047)
V_SYNCLEN <= v_config[21:19]; // Vertical sync length (0...7)
V_AVIDSTART <= v_config[18:11] + v_config[21:19]; // Vertical sync+backporch length (0...255)
V_ACTIVE <= v_config[10:0]; // Vertical active length (0...2047)
H_MASK <= h_config2[29:19];
V_MASK <= v_config[27:22];
// H_L5BORDER <= h_config[29] ? (11'd1920-h_config[10:0])/2 : (11'd1600-h_config[10:0])/2;
H_L5BORDER <= h_config[29] ? H_L5BORDER_1920_tmp[10:1] : H_L5BORDER_1600_tmp[10:1];
// For Line3x 240x360
H_L3BORDER <= h_config[28] ? H_L5BORDER_1920_tmp[10:1] : 10'd0;
H_L3_OPT_START <= h_config2[15:13] + (h_config[28] ? 7'd90 : 7'd0);
H_OPT_SCALE <= h_config2[18:16];
H_OPT_SAMPLE_SEL <= h_config2[15:13];
H_OPT_SAMPLE_MULT <= h_config2[12:10];
H_OPT_STARTOFF <= h_config2[9:0];
X_PANASONIC_HACK <= misc_config[12];
X_REV_LPF_ENABLE <= (misc_config[11:7] != 5'b00000);
X_REV_LPF_STR <= (misc_config[11:7] + 6'd16);
X_MASK_COLOR <= misc_config[6:4];
X_MASK_BR <= misc_config[3:0];
SL_NO_ALTERN <= sl_config[31];
SL_METHOD <= sl_config[30];
SL_HYBRSTR <= sl_config[29:25];
SL_L_OVERLAY <= sl_config[24:20];
SL_L_STR[4] <= sl_config[19:16];
SL_L_STR[3] <= sl_config[15:12];
SL_L_STR[2] <= sl_config[11:8];
SL_L_STR[1] <= sl_config[7:4];
SL_L_STR[0] <= sl_config[3:0];
SL_ALTIV <= sl_config2[31];
SL_C_OVERLAY <= sl_config2[29:24];
SL_C_STR[5] <= sl_config2[23:20];
SL_C_STR[4] <= sl_config2[19:16];
SL_C_STR[3] <= sl_config2[15:12];
SL_C_STR[2] <= sl_config2[11:8];
SL_C_STR[1] <= sl_config2[7:4];
SL_C_STR[0] <= sl_config2[3:0];
CALC_CONSTS <= 1'b1;
end
// generate long pulse for hz counter
if (frame_change)
frame_change_longpulse <= 1'b1;
else if (vcnt_1x > 0)
frame_change_longpulse <= 1'b0;
if (CALC_CONSTS) begin
H_AVIDSTOP <= H_AVIDSTART+H_ACTIVE;
V_AVIDSTOP <= V_AVIDSTART+V_ACTIVE;
H_AVIDMASK_START <= H_AVIDSTART+H_MASK;
H_AVIDMASK_STOP <= H_AVIDSTART+H_ACTIVE-H_MASK;
V_AVIDMASK_START <= V_AVIDSTART+V_MASK;
V_AVIDMASK_STOP <= V_AVIDSTART+V_ACTIVE-V_MASK;
LT_POS_TOPLEFT_BOX_H_STOP <= H_AVIDSTART+(H_ACTIVE/`LT_WIDTH_DIV);
LT_POS_TOPLEFT_BOX_V_STOP <= V_AVIDSTART+(V_ACTIVE/`LT_HEIGHT_DIV);
LT_POS_CENTER_BOX_H_START <= H_AVIDSTART+(H_ACTIVE/2'h2)-(H_ACTIVE/(`LT_WIDTH_DIV*2'h2));
LT_POS_CENTER_BOX_H_STOP <= H_AVIDSTART+(H_ACTIVE/2'h2)+(H_ACTIVE/(`LT_WIDTH_DIV*2'h2));
LT_POS_CENTER_BOX_V_START <= V_AVIDSTART+(V_ACTIVE/2'h2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2'h2));
LT_POS_CENTER_BOX_V_STOP <= V_AVIDSTART+(V_ACTIVE/2'h2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2'h2));
LT_POS_BOTTOMRIGHT_H_START <= H_AVIDSTART+H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV);
LT_POS_BOTTOMRIGHT_V_START <= V_AVIDSTART+V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV);
CALC_CONSTS <= 1'b0;
end
R_in_L <= R_in;
G_in_L <= G_in;
B_in_L <= B_in;
HSYNC_in_L <= HSYNC_in;
VSYNC_in_L <= VSYNC_in;
// Add two delay stages to match linebuf delay
R_in_LL <= R_in_L;
G_in_LL <= G_in_L;
B_in_LL <= B_in_L;
R_in_LLL <= R_in_LL;
G_in_LLL <= G_in_LL;
B_in_LLL <= B_in_LL;
R_1x <= R_in_LLL;
G_1x <= G_in_LLL;
B_1x <= B_in_LLL;
HSYNC_1x <= (hcnt_1x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
if (FID_cur == `FID_ODD)
VSYNC_1x <= (vcnt_1x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
else
VSYNC_1x <= (((vcnt_1x+1'b1) < V_SYNCLEN) | ((vcnt_1x+1'b1 == V_SYNCLEN) & (hcnt_1x <= (hmax[~line_idx]>>1)))) ? `VSYNC_POL : ~`VSYNC_POL;
DE_1x <= ((hcnt_1x >= H_AVIDSTART) & (hcnt_1x < H_AVIDSTOP)) & ((vcnt_1x >= V_AVIDSTART) & (vcnt_1x < V_AVIDSTOP));
FID_1x <= FID_cur;
end
end
//Generate 2x signals for linedouble
always @(posedge pclk_2x or negedge reset_n)
begin
if (!reset_n) begin
hcnt_2x <= 0;
vcnt_2x <= 0;
line_out_idx_2x <= 0;
end else begin
if ((pclk_1x == 1'b1) & (line_change | frame_change)) begin //aligned with negedge of pclk_1x
hcnt_2x <= 0;
hcnt_2x_opt <= H_OPT_SAMPLE_SEL;
hcnt_2x_opt_ctr <= 0;
line_out_idx_2x <= 0;
if (frame_change)
vcnt_2x <= 11'h7ff; // -1 for 11 bit word
else if (line_change & (FID_cur == `FID_ODD))
vcnt_2x <= vcnt_2x + 1'b1;
end else if (hcnt_2x == hmax[~line_idx]) begin
hcnt_2x <= 0;
line_out_idx_2x <= line_out_idx_2x + 1'b1;
hcnt_2x_opt <= H_OPT_SAMPLE_SEL;
hcnt_2x_opt_ctr <= 0;
if (FID_cur == `FID_EVEN)
vcnt_2x <= vcnt_2x + 1'b1;
end else begin
hcnt_2x <= hcnt_2x + 1'b1;
if (hcnt_2x >= H_OPT_STARTOFF) begin
if (hcnt_2x_opt_ctr == H_OPT_SCALE-1'b1) begin
hcnt_2x_opt <= hcnt_2x_opt + H_OPT_SAMPLE_MULT;
hcnt_2x_opt_ctr <= 0;
end else
hcnt_2x_opt_ctr <= hcnt_2x_opt_ctr + 1'b1;
end
end
HSYNC_2x <= (hcnt_2x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
VSYNC_2x <= (vcnt_2x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
DE_2x <= ((hcnt_2x >= H_AVIDSTART) & (hcnt_2x < ((X_PANASONIC_HACK & (vcnt_2x == V_AVIDSTOP-1'b1) & (line_out_idx_2x==2'h1)) ? (H_AVIDSTOP-12'd98) : H_AVIDSTOP))) & ((vcnt_2x >= V_AVIDSTART) & (vcnt_2x < V_AVIDSTOP));
end
end
always @(posedge pclk_3x or negedge reset_n)
begin
if (!reset_n) begin
hcnt_3x <= 0;
vcnt_3x <= 0;
line_out_idx_3x <= 0;
end else begin
if ((pclk_3x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x
if (!(frame_change & (FID_cur == `FID_EVEN))) begin
hcnt_3x <= 0;
hcnt_3x_opt <= H_L3_OPT_START;
hcnt_3x_opt_ctr <= 0;
line_out_idx_3x <= 0;
end
if (frame_change)
vcnt_3x <= -11'b1-FID_cur;
else if (line_change)
vcnt_3x <= vcnt_3x + 1'b1;
end else if (hcnt_3x == hmax_3x) begin
hcnt_3x <= 0;
line_out_idx_3x <= line_out_idx_3x + 1'b1;
hcnt_3x_opt <= H_L3_OPT_START;
hcnt_3x_opt_ctr <= 0;
end else begin
hcnt_3x <= hcnt_3x + 1'b1;
if (hcnt_3x >= H_OPT_STARTOFF) begin
if (hcnt_3x_opt_ctr == H_OPT_SCALE-1'b1) begin
hcnt_3x_opt <= hcnt_3x_opt + H_OPT_SAMPLE_MULT;
hcnt_3x_opt_ctr <= 0;
end else
hcnt_3x_opt_ctr <= hcnt_3x_opt_ctr + 1'b1;
end
end
//track pclk_3x alignment to pclk_1x rising edge (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
if (((pclk_1x_prev3x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_cnt == 2'h2))
pclk_3x_cnt <= 0;
else
pclk_3x_cnt <= pclk_3x_cnt + 1'b1;
pclk_1x_prev3x <= pclk_1x;
hmax_3x <= hmax[~line_idx];
hcnt_3x_lace_ref <= (hmax_3x>>1)+1'b1;
HSYNC_3x <= (hcnt_3x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
if (FID_cur == `FID_ODD)
VSYNC_3x <= (vcnt_3x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
else begin
if ((vcnt_3x+1'b1 == 11'd0) & (line_out_idx_3x == 1) & (hcnt_3x == hcnt_3x_lace_ref))
VSYNC_3x <= `VSYNC_POL;
else if ((vcnt_3x+1'b1 == V_SYNCLEN) & (line_out_idx_3x == 1) & (hcnt_3x == hcnt_3x_lace_ref))
VSYNC_3x <= ~`VSYNC_POL;
end
DE_3x <= ((hcnt_3x >= H_AVIDSTART-H_L3BORDER) & (hcnt_3x < H_AVIDSTOP+H_L3BORDER)) & ((vcnt_3x >= V_AVIDSTART) & (vcnt_3x < V_AVIDSTOP));
end
end
always @(posedge pclk_4x or negedge reset_n)
begin
if (!reset_n) begin
hcnt_4x <= 0;
vcnt_4x <= 0;
line_out_idx_4x <= 0;
end else begin
// TODO: better implementation
if ((DE_3x == 1) & (DE_3x_prev4x == 0))
hcnt_4x_aspfix <= hcnt_3x - 12'd160;
else
hcnt_4x_aspfix <= hcnt_4x_aspfix + 1'b1;
DE_3x_prev4x <= DE_3x;
if ((pclk_4x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x
hcnt_4x <= 0;
hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
hcnt_4x_opt_ctr <= 0;
line_out_idx_4x <= 0;
if (frame_change)
vcnt_4x <= 11'h7ff; // -1 for 11 bit word
else if (line_change & (FID_cur == `FID_ODD))
vcnt_4x <= vcnt_4x + 1'b1;
end else if (hcnt_4x == hmax[~line_idx]) begin
hcnt_4x <= 0;
line_out_idx_4x <= line_out_idx_4x + 1'b1;
hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
hcnt_4x_opt_ctr <= 0;
if ((FID_cur == `FID_EVEN) && (line_out_idx_4x == 1))
vcnt_4x <= vcnt_4x + 1'b1;
end else begin
hcnt_4x <= hcnt_4x + 1'b1;
if (hcnt_4x >= H_OPT_STARTOFF) begin
if (hcnt_4x_opt_ctr == H_OPT_SCALE-1'b1) begin
hcnt_4x_opt <= hcnt_4x_opt + H_OPT_SAMPLE_MULT;
hcnt_4x_opt_ctr <= 0;
end else
hcnt_4x_opt_ctr <= hcnt_4x_opt_ctr + 1'b1;
end
end
//track pclk_4x alignment to pclk_1x rising edge (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
if (((pclk_1x_prev4x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_4x_cnt == 2'h3))
pclk_4x_cnt <= 0;
else
pclk_4x_cnt <= pclk_4x_cnt + 1'b1;
pclk_1x_prev4x <= pclk_1x;
HSYNC_4x <= (hcnt_4x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
VSYNC_4x <= (vcnt_4x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
DE_4x <= ((hcnt_4x >= H_AVIDSTART) & (hcnt_4x < H_AVIDSTOP)) & ((vcnt_4x >= V_AVIDSTART) & (vcnt_4x < V_AVIDSTOP));
end
end
always @(posedge pclk_5x or negedge reset_n)
begin
if (!reset_n) begin
hcnt_5x <= 0;
vcnt_5x <= 0;
line_out_idx_5x <= 0;
end else begin
if ((pclk_5x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x
hcnt_5x <= 0;
hcnt_5x_opt <= H_OPT_SAMPLE_SEL + 11'd120;
hcnt_5x_opt_ctr <= 0;
line_out_idx_5x <= 0;
if (frame_change)
vcnt_5x <= 11'h7ff; // -1 for 11 bit word
else if (line_change)
vcnt_5x <= vcnt_5x + 1'b1;
end else if (hcnt_5x == hmax[~line_idx]) begin
hcnt_5x <= 0;
line_out_idx_5x <= line_out_idx_5x + 1'b1;
hcnt_5x_opt <= H_OPT_SAMPLE_SEL + 11'd120;
hcnt_5x_opt_ctr <= 0;
end else begin
hcnt_5x <= hcnt_5x + 1'b1;
if (hcnt_5x >= H_OPT_STARTOFF) begin
if (hcnt_5x_opt_ctr == H_OPT_SCALE-1'b1) begin
hcnt_5x_opt <= hcnt_5x_opt + H_OPT_SAMPLE_MULT;
hcnt_5x_opt_ctr <= 0;
end else
hcnt_5x_opt_ctr <= hcnt_5x_opt_ctr + 1'b1;
end
end
//track pclk_5x alignment to pclk_1x rising edge (pclk_1x=1 @ 144deg & pclk_1x=0 @ 216deg & pclk_1x=0 @ 288deg)
if (((pclk_1x_prevprev5x == 1'b1) & (pclk_1x_prev5x == 1'b0)) | (pclk_5x_cnt == 3'h4))
pclk_5x_cnt <= 0;
else
pclk_5x_cnt <= pclk_5x_cnt + 1'b1;
pclk_1x_prev5x <= pclk_1x;
pclk_1x_prevprev5x <= pclk_1x_prev5x;
hcnt_5x_hscomp <= hcnt_5x + 11'd121;
HSYNC_5x <= (hcnt_5x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
VSYNC_5x <= (vcnt_5x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
DE_5x <= ((hcnt_5x >= H_AVIDSTART-H_L5BORDER) & (hcnt_5x < H_AVIDSTOP+H_L5BORDER)) & ((vcnt_5x >= V_AVIDSTART) & (vcnt_5x < V_AVIDSTOP));
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_8_V
`define SKY130_FD_SC_LP__NAND2_8_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_8_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:51:49 01/30/2016
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu #(parameter B = 32)
(
input wire signed [B-1:0] op1,
input wire signed [B-1:0] op2,
input wire [3:0] alu_control,
output wire [B-1:0] result,
output wire zero
);
assign result = (alu_control == 4'b0000) ? op1 + op2 : //ADD
(alu_control == 4'b0001) ? op1 - op2 : //SUB
(alu_control == 4'b0010) ? op1 & op2 : //AND
(alu_control == 4'b0011) ? op1 | op2 : //OR
(alu_control == 4'b0100) ? op1 ^ op2 : //XOR
(alu_control == 4'b0101) ? ~(op1 | op2) : //NOR
(alu_control == 4'b0110) ? op1 < op2 : //SLT
(alu_control == 4'b0111) ? op1 << op2[10:6] : //SLL
(alu_control == 4'b1000) ? op1 >> op2[10:6] : //SRL
(alu_control == 4'b1001) ? {$signed(op1) >>> op2[10:6]} : //SRA
(alu_control == 4'b1010) ? op2 << op1 : //SLLV
(alu_control == 4'b1011) ? op2 >> op1 : //SRLV
(alu_control == 4'b1100) ? {$signed(op2) >>> op1} : //SRAV
(alu_control == 4'b1101) ? {op2[15:0],16'b00000000_00000000} : //LUI
32'b11111111_11111111_11111111_11111111;
assign zero = (result == 0) ? 1'b1 : 1'b0;
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: Link Controller
-- Description: Control de enlace de entrada. Una instancia de este
modulo esta ligada a cada puerto de entrada del router
con excepcion del puerto del elemento de procesamiento.
Sus tareas son:
Recepcion de nuevos paquetes al router. Para cada
paquete el modulo Link Controller inicia el proceso
de solicitud de un puerto de salida. Ademas se
encarga de almacenar los flits de un paquete en el
buffer asociado al puerto de entrada donde se
encuentra.
Una vez obtenido el permiso de uso de un puerto de
salida, envia todos los flits del paquete al puerto
correspondiente.
La negociacion del uso de un puerto de salida se lleva a
a cabo con los modulos "Planificador de Salida".
-- Dependencies: -- system.vh
-- router_route_planner.v
-- algoritmo de encaminamiento *
-- router_link_controller_control_unit.v
-- Parameters: -- PORT_DIR: Direccion del puerto de entrada
conectado a este modulo {x+, y+
x-, y-}.
-- X_LOCAL: Direccion en dimension "x" del nodo
en la red.
-- Y_LOCAL: Direccion en dimension "y" del nodo
en la red.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 05 de Junio 2015: Creacion
-- 10 de Junio 2015: * puerto de entrada -- x_buffer_din
-- y_buffer_din
* cambio en instancia de unidad de control.
* se agrega mux para seleccionar entre
direccion {x,y} desde el canal de entrada o
la cola de paquetes.
*/
`include "system.vh"
module link_controller #(
parameter PORT_DIR = `X_POS,
parameter X_LOCAL = 2,
parameter Y_LOCAL = 2,
parameter X_WIDTH = 2,
parameter Y_WIDTH = 2
)
(
input wire clk,
input wire reset,
// -- input -------------------------------------------------- >>>>>
input wire transfer_strobe_din,
input wire header_field_din,
input wire done_field_din,
input wire done_buffer_din,
input wire [`ADDR_FIELD-1:0] x_field_din,
input wire [`ADDR_FIELD-1:0] y_field_din,
input wire [`ADDR_FIELD-1:0] x_buffer_din,
input wire [`ADDR_FIELD-1:0] y_buffer_din,
// -- output ------------------------------------------------- >>>>>
output wire write_strobe_dout,
output wire read_strobe_dout,
output wire credit_out_dout,
output wire [3:0] request_vector_dout
);
/*
-- Instancia :: Unidad de Control de Control de Enlace
-- Descripcion: Implementacion de maquinas de estado para el control de
las operaciones de recepcion denuevos paquetes y la
transferencia de paquetes a puertos de salida del
router.
*/
// -- Link Controller :: Unidad de Control (FSM) ------------- >>>>>
wire routing_source;
wire routing_strobe;
link_controller_control_unit unidad_de_control_LC
(
.clk (clk),
.reset (reset),
// -- inputs ----------------------------------------- >>>>>
.header_field_din (header_field_din),
.transfer_strobe_din(transfer_strobe_din),
// -- outputs ---------------------------------------- >>>>>
.write_strobe_dout (write_strobe_dout),
.read_strobe_dout (read_strobe_dout),
.routing_source_dout(routing_source),
.routing_strobe_dout(routing_strobe),
.credit_out_dout (credit_out_dout)
);
/*
-- Instancia :: Planificador de Ruta
-- Descripcion: Wrapper para algortimos de calculo de ruta. El wrapper
incluye un multiplexor para la seleccion del origen de
la direccion del nodo destino. La direccion se puede
obtener de manera directa de la slineas del canal de
entrada al router o de la salida de la cola de
almacenamiento de flits ligada al control de enlace.
Los multiplexores descritos por medio de la señal
"routing_source" selecciones si se tomaran los datos
de ruteo desde el canal de entrada o desde el buffer
de paquetes.
*/
// -- Mux Selector de origen de direccion {x,y} -------------- >>>>>
wire [`ADDR_FIELD-1:0] x_addr;
wire [`ADDR_FIELD-1:0] y_addr;
assign x_addr = (routing_source) ? x_buffer_din : x_field_din;
assign y_addr = (routing_source) ? y_buffer_din : y_field_din;
wire done_tag;
assign done_tag = (routing_source) ? done_buffer_din : done_field_din;
// -- Planificador de Ruta ----------------------------------- >>>>>
wire [3:0] request_vector;
route_planner
#(
.PORT_DIR (PORT_DIR),
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH)
)
route_planner
(
// -- inputs ----------------------------------------- >>>>>
.done_field_din (done_tag),
.x_field_din (x_addr),
.y_field_din (y_addr),
// -- outputs ---------------------------------------- >>>>>
.request_vector_dout (request_vector)
);
/*
-- Registro
-- Descripcion: Registro para el bloqueo de peticiones de puerto de
salida para un paquete entrante. Este registro funciona
la unica etapa de segmentado del router.
*/
// -- Registro de Peticion en Curso -------------------------- >>>>>
reg [3:0] request_vector_reg = 4'h0;
always @(posedge clk)
if (transfer_strobe_din)
request_vector_reg <= 4'h0;
else
if (routing_strobe)
request_vector_reg <= request_vector;
assign request_vector_dout = request_vector_reg;
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
link_controller
#( .PORT_DIR (PORT_DIR),
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH)
)
controlador_de_enlace
(
.clk (clk),
.reset (reset),
// -- input -------------------------------------------------- >>>>>
.transfer_strobe_din(transfer_strobe_din),
.header_field_din (header_field_din),
.done_field_din (done_field_din),
.done_buffer_din (done_buffer_din),
.x_field_din (x_field_din),
.y_field_din (y_field_din),
.x_buffer_din (x_buffer_din),
.y_buffer_din (y_buffer_din),
// -- output ------------------------------------------------- >>>>>
.write_strobe_dout (write_strobe_dout),
.read_strobe_dout (read_strobe_dout),
.credit_out_dout (credit_out_dout),
.request_vector_dout(request_vector_dout)
);
*/ |
`timescale 1 ns / 1 ps
`include "axi_spi_master_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module axi_spi_master_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
// Generator : SpinalHDL v1.1.5 git head : 0310b2489a097f2b9de5535e02192d9ddd2764ae
// Date : 15/04/2019, 21:20:08
// Component : Memory
module Memory (
input io_enable,
input io_mem_valid,
input io_mem_instr,
input [3:0] io_mem_wstrb,
input [31:0] io_mem_wdata,
input [15:0] io_mem_addr,
output [31:0] io_mem_rdata,
output io_mem_ready,
input clk,
input reset);
wire [31:0] _zz_1;
wire [31:0] _zz_2;
wire [3:0] _zz_3;
wire _zz_4;
reg [31:0] rdata;
reg ready;
wire [13:0] addr;
reg [7:0] memory_1_symbol0 [0:1024*10];
reg [7:0] memory_1_symbol1 [0:1024*10];
reg [7:0] memory_1_symbol2 [0:1024*10];
reg [7:0] memory_1_symbol3 [0:1024*10];
assign _zz_2 = io_mem_wdata;
assign _zz_3 = io_mem_wstrb;
assign _zz_4 = (io_enable && io_mem_valid);
initial begin
$readmemb("Memory.v_toplevel_memory_1_symbol0.bin",memory_1_symbol0);
$readmemb("Memory.v_toplevel_memory_1_symbol1.bin",memory_1_symbol1);
$readmemb("Memory.v_toplevel_memory_1_symbol2.bin",memory_1_symbol2);
$readmemb("Memory.v_toplevel_memory_1_symbol3.bin",memory_1_symbol3);
end
always @ (posedge clk) begin
if(_zz_3[0] && _zz_4) begin
memory_1_symbol0[addr] <= _zz_2[7 : 0];
end
if(_zz_3[1] && _zz_4) begin
memory_1_symbol1[addr] <= _zz_2[15 : 8];
end
if(_zz_3[2] && _zz_4) begin
memory_1_symbol2[addr] <= _zz_2[23 : 16];
end
if(_zz_3[3] && _zz_4) begin
memory_1_symbol3[addr] <= _zz_2[31 : 24];
end
end
assign _zz_1[7 : 0] = memory_1_symbol0[addr];
assign _zz_1[15 : 8] = memory_1_symbol1[addr];
assign _zz_1[23 : 16] = memory_1_symbol2[addr];
assign _zz_1[31 : 24] = memory_1_symbol3[addr];
assign addr = (io_mem_addr >>> 2);
always @ (*) begin
if((io_enable && io_mem_valid))begin
rdata = _zz_1;
ready = 1'b1;
end else begin
rdata = (32'b00000000000000000000000000000000);
ready = 1'b0;
end
end
assign io_mem_ready = ready;
assign io_mem_rdata = rdata;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V |
/*******************************************************************
date:2016/3/30
designer:ZhaiShaoMin
module name :tb_arbiter_for_dcache
moduel function : check errors in arbiter_for_dcache
********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_dcache();
//input
reg clk;
reg rst;
reg dcache_done_access;
reg v_dc_download;
reg [143:0] dc_download_flits;
reg v_cpu;
reg [67:0] cpu_access_flits;
reg v_m_d_areg;
reg [143:0] m_d_areg_flits;
//output
wire [143:0] flits_dc;
wire v_flits_dc;
wire re_dc_download_flits;
wire re_cpu_access_flits;
wire re_m_d_areg_flits;
wire cpu_done_access;
wire dc_download_done_access;
wire m_d_areg_done_access;
//instante design
arbiter_for_dcache(//input
.clk(clk),
.rst(rst),
.dcache_done_access(dcache_done_access),
.v_dc_download(v_dc_download),
.dc_download_flits(dc_download_flits),
.v_cpu(v_cpu),
.cpu_access_flits(cpu_access_flits),
.v_m_d_areg(v_m_d_areg),
.m_d_areg_flits(m_d_areg_flits),
//output
.flits_dc(flits_dc),
.v_flits_dc(v_flits_dc),
.re_dc_download_flits(re_dc_download_flits),
.re_cpu_access_flits(re_cpu_access_flits),
.re_m_d_areg_flits(re_m_d_areg_flits),
.cpu_done_access(cpu_done_access),
.dc_download_done_access(dc_download_done_access),
.m_d_areg_done_access(m_d_areg_done_access)
);
integer log_file;
//initial inputs
initial
begin
clk=1'b0;
rst=1'b1;
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
log_file=$fopen("log_arbiter_for_dcache");
end
`define clk_step #14;
always #7 clk=~clk;
//////////////////////////////////////////////////////////////
////////////////BEGIN TEST!///////////////////////////////////
initial begin
`clk_step
$display("begin test!");
$fdisplay("begin test!");
rst=1'b1;
/////////////////////////////////////////////////
///////////////first case: all valid ///////////
//// m_d_flits win,due to priority3 was reset to 3'b001!
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
///dcache has processed m_d_flits ,due to RR it will be turn of cpu access
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
//dcache has processed dc_download flits, due to RR now it's turn of dc_download
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
//////////////////////////////////////////////////////////////////////
///////////2nd case:both cpu access and dc_download flit are valid////
///////turn of cpu due to RR
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
///turn of dc access
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
//////////////////////////////////////////////////////////////////
////////3rd case: cpu and mem valid///////////////////////////////
///////turn of mem due to RR
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
///turn of cpu access
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
/////////////////////////////////////////////////////////////////
///////// 4th case: dc and mem are valid/////////////////////////
/// turn of mem
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
///turn of dc access
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
//////////////////////////////////////////////////////////////////
/////////5th case :only dc valid//////////////////////////////////
///turn of dc access
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b1;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
/////////////////////////////////////////////////////////////////
/////////6th case: only cpu valid////////////////////////////////
///turn of dc access
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b1;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
/////////////////////////////////////////////////////////
///////////////////7th case :only mem valid//////////////
///turn of dc access
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b1;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
////////////////////////////////////////////////////////////
//////////////8th case: nothing comes //////////////////////
///turn of dc access
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b0;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
dcache_done_access=1'b1;
v_dc_download=1'b0;
dc_download_flits=144'hc0de_1234_c1de_5678_c2de_1234_c3de_5678_c4de;
v_cpu=1'b0;
cpu_access_flits=68'h01234c0de5678c0de;
v_m_d_areg=1'b0;
m_d_areg_flits=144'h1234_c0de_5678_c1de_1234_c2de_5678_c3de_1234;
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
end
endmodule
|
// -----------------------------------------------------------------------------
// FILE NAME : Wu_Manber_shifter.v
// DEPARTMENT : Computer Engineering
// AUTHOR : Ashik Poojari
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2016-09-18 Ashik Poojari
// -----------------------------------------------------------------------------
// KEYWORDS : General file searching keywords, leave blank if none.
// -----------------------------------------------------------------------------
// PURPOSE : Short description of functionality
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
// e.g.DATA_WIDTH [32,16] : width of the data : 32 :
// NO_OF_MSGS : no of hexadecimal digit
// MSG_WIDTH : hexadecimal width is 4
// SHIFT_DATA_WIDTH : data width of shift register
// NO_OF_MSGS=16, MSG_WIDTH=8, B=3, PATTERN_WIDTH=6,
// SHIFT_DATA_WIDTH=MSG_WIDTH*(PATTERN_WIDTH-B+1),
// SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),
//DATA_DUMP_WIDTH=PATTERN_WIDTH+B,
// DATA_WIDTH=MSG_WIDTH*(NO_OF_MSGS+DATA_DUMP_WIDTH),
// POINTER_WIDTH=$clog2(DATA_WIDTH);
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy : Asynchronous
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Scan Methodology :
// Instantiations :
// Synthesizable (y/n) : y
// Other :
// -FHDR------------------------------------------------------------------------
module shifter #(parameter NO_OF_MSGS=8, MSG_WIDTH=4, B=3, PATTERN_WIDTH=6,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1)+1,DATA_WIDTH=2*NO_OF_MSGS*MSG_WIDTH,NOS_SHIFTER=2*NO_OF_MSGS,
POINTER_WIDTH=$clog2(NOS_SHIFTER),MAX_PAT_SZ=22)
( input clk,
input Reset,
input input_ready,
input [DATA_WIDTH-1:0] data_in,
input [SHIFT_WIDTH-1:0] shift_count,
output reg [MSG_WIDTH*PATTERN_WIDTH-1:0] data_out,
output reg [POINTER_WIDTH-1:0] pointer,
output reg [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa,
output reg datald);
wire [POINTER_WIDTH-1:0] tmp_pointer;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] data_out_wire[NOS_SHIFTER-1:0];
wire [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa_wr [NOS_SHIFTER-1:0];
reg start;
always@(posedge clk)
begin
if (Reset) begin
pointer <= 0;
data_out <= 0;
data_nfa <= 0;
start <= 0;
datald <= 1;
end
else begin
if(input_ready == 1) begin
start <= 1;
end
if (start == 1) begin
pointer <=tmp_pointer;
data_out <= data_out_wire[tmp_pointer];
data_nfa <= data_nfa_wr[tmp_pointer];
if(tmp_pointer > NO_OF_MSGS)
datald <= 0;
else
datald <= 1;
end
end
end
assign tmp_pointer = pointer + {{(POINTER_WIDTH-SHIFT_WIDTH){1'b0}},shift_count};
generate
genvar i;
for(i=0;i<NOS_SHIFTER;i=i+1)
begin: muxshift
if(NOS_SHIFTER-i < PATTERN_WIDTH)
assign data_out_wire[i] = {data_in[MSG_WIDTH*(NOS_SHIFTER-i)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(PATTERN_WIDTH-(NOS_SHIFTER-i))]};
else
assign data_out_wire[i] = data_in[DATA_WIDTH-MSG_WIDTH*i-1: DATA_WIDTH-MSG_WIDTH*(i+PATTERN_WIDTH)];
end
endgenerate
generate
genvar j;
for(j=0;j<NOS_SHIFTER;j=j+1)
begin: muxnfa
if(NOS_SHIFTER-j < MAX_PAT_SZ)
assign data_nfa_wr[j] = {data_in[MSG_WIDTH*(NOS_SHIFTER-j)-1:0],data_in[DATA_WIDTH-1: DATA_WIDTH-MSG_WIDTH*(MAX_PAT_SZ-(NOS_SHIFTER-j))]};
else
assign data_nfa_wr[j] = data_in[DATA_WIDTH-MSG_WIDTH*j-1: DATA_WIDTH-MSG_WIDTH*(j+MAX_PAT_SZ)];
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLRBN_PP_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrbn (
RESET_B,
D ,
GATE_N ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_SYMBOL_V
`define SKY130_FD_SC_LS__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_SYMBOL_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~((^test_expr) ^ (^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if ((^(test_expr)) != 1'b1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression does not exhibit odd parity");
end
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_SANITY_ON) begin //sanity coverage
if (test_expr != prev_test_expr) begin
ovl_cover_t("test_expr_change covered");
end
prev_test_expr <= test_expr;
end //sanity coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
`endif
end
end //always
`endif // OVL_COVER_ON
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 15:32:52 -0400 (Wed, 18 May 2011) $
`ifdef BSV_WARN_REGFILE_ADDR_RANGE
`else
`define BSV_WARN_REGFILE_ADDR_RANGE 0
`endif
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Multi-ported Register File
module RegFile(CLK,
ADDR_IN, D_IN, WE,
ADDR_1, D_OUT_1,
ADDR_2, D_OUT_2,
ADDR_3, D_OUT_3,
ADDR_4, D_OUT_4,
ADDR_5, D_OUT_5
);
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
input CLK;
input [addr_width - 1 : 0] ADDR_IN;
input [data_width - 1 : 0] D_IN;
input WE;
input [addr_width - 1 : 0] ADDR_1;
output [data_width - 1 : 0] D_OUT_1;
input [addr_width - 1 : 0] ADDR_2;
output [data_width - 1 : 0] D_OUT_2;
input [addr_width - 1 : 0] ADDR_3;
output [data_width - 1 : 0] D_OUT_3;
input [addr_width - 1 : 0] ADDR_4;
output [data_width - 1 : 0] D_OUT_4;
input [addr_width - 1 : 0] ADDR_5;
output [data_width - 1 : 0] D_OUT_5;
reg [data_width - 1 : 0] arr[lo:hi];
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : init_block
integer i; // temporary for generate reset value
for (i = lo; i <= hi; i = i + 1) begin
arr[i] = {((data_width + 1)/2){2'b10}} ;
end
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK)
begin
if (WE)
arr[ADDR_IN] <= `BSV_ASSIGNMENT_DELAY D_IN;
end // always@ (posedge CLK)
assign D_OUT_1 = arr[ADDR_1];
assign D_OUT_2 = arr[ADDR_2];
assign D_OUT_3 = arr[ADDR_3];
assign D_OUT_4 = arr[ADDR_4];
assign D_OUT_5 = arr[ADDR_5];
// synopsys translate_off
always@(posedge CLK)
begin : runtime_check
reg enable_check;
enable_check = `BSV_WARN_REGFILE_ADDR_RANGE ;
if ( enable_check )
begin
if (( ADDR_1 < lo ) || (ADDR_1 > hi) )
$display( "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", ADDR_1 ) ;
if (( ADDR_2 < lo ) || (ADDR_2 > hi) )
$display( "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", ADDR_2 ) ;
if (( ADDR_3 < lo ) || (ADDR_3 > hi) )
$display( "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", ADDR_3 ) ;
if (( ADDR_4 < lo ) || (ADDR_4 > hi) )
$display( "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", ADDR_4 ) ;
if (( ADDR_5 < lo ) || (ADDR_5 > hi) )
$display( "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", ADDR_5 ) ;
if ( WE && ( ADDR_IN < lo ) || (ADDR_IN > hi) )
$display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ;
end
end
// synopsys translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood$l_pp$PG (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_2_V
`define SKY130_FD_SC_HD__A32O_2_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_2_V
|
module module3(clk_, rst_, bar, foo);
input clk_;
input rst_;
input [1:0] bar;
output [1:0] foo;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1;
parameter poser_width_out = 0+1-0+1;
parameter poser_grid_width = 2;
parameter poser_grid_depth = 1;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 2'b00 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar };
wire [poser_width_out-1:0] poser_outputs;
assign { foo } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:gigantic_mux:1.0
// IP Revision: 1
(* X_CORE_INFO = "bd_350b_g_inst_0_gigantic_mux,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_g_inst_0,bd_350b_g_inst_0_gigantic_mux,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_g_inst_0,bd_350b_g_inst_0_gigantic_mux,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=gigantic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_MUX_0_HAS_BRESP=1,C_MUX_0_HAS_RRESP=1,C_MUX_0_HAS_LOCK=1,C_MUX_0_HAS_PROT=1,C_MUX_0_HAS_CACHE=1,C_MUX_0_HAS_QOS=1,C_MUX_0_HAS_REGION=1,C_MUX_0_HAS_BURST=1,C_MUX_0_HAS_WSTRB=1,C_MUX_0_HAS_TSTRB=1,C_MUX_0_HAS_TKEEP=1,C_MUX_1_HAS_BRESP=1,C_MUX_1_HAS_RRESP=1,C_MUX_1_HAS_LOCK=1,C_MUX_1_HAS_P\
ROT=1,C_MUX_1_HAS_CACHE=1,C_MUX_1_HAS_QOS=1,C_MUX_1_HAS_REGION=1,C_MUX_1_HAS_BURST=1,C_MUX_1_HAS_WSTRB=1,C_MUX_1_HAS_TSTRB=1,C_MUX_1_HAS_TKEEP=1,C_MUX_2_HAS_BRESP=1,C_MUX_2_HAS_RRESP=1,C_MUX_2_HAS_LOCK=1,C_MUX_2_HAS_PROT=1,C_MUX_2_HAS_CACHE=1,C_MUX_2_HAS_QOS=1,C_MUX_2_HAS_REGION=1,C_MUX_2_HAS_BURST=1,C_MUX_2_HAS_WSTRB=1,C_MUX_2_HAS_TSTRB=1,C_MUX_2_HAS_TKEEP=1,C_MUX_3_HAS_BRESP=1,C_MUX_3_HAS_RRESP=1,C_MUX_3_HAS_LOCK=1,C_MUX_3_HAS_PROT=1,C_MUX_3_HAS_CACHE=1,C_MUX_3_HAS_QOS=1,C_MUX_3_HAS_REGION=1,C\
_MUX_3_HAS_BURST=1,C_MUX_3_HAS_WSTRB=1,C_MUX_3_HAS_TSTRB=1,C_MUX_3_HAS_TKEEP=1,C_NUM_MONITOR_SLOTS=2,C_SLOT_0_TXN_CNTR_EN=1,C_SLOT_1_TXN_CNTR_EN=1,C_SLOT_2_TXN_CNTR_EN=1,C_SLOT_3_TXN_CNTR_EN=1,C_SLOT_4_TXN_CNTR_EN=1,C_SLOT_5_TXN_CNTR_EN=1,C_SLOT_6_TXN_CNTR_EN=1,C_SLOT_7_TXN_CNTR_EN=1,C_SLOT_8_TXN_CNTR_EN=1,C_SLOT_9_TXN_CNTR_EN=1,C_SLOT_10_TXN_CNTR_EN=1,C_SLOT_11_TXN_CNTR_EN=1,C_SLOT_12_TXN_CNTR_EN=1,C_SLOT_13_TXN_CNTR_EN=1,C_SLOT_14_TXN_CNTR_EN=1,C_SLOT_15_TXN_CNTR_EN=1,C_SLOT_0_MAX_RD_BURSTS=1,\
C_SLOT_0_MAX_WR_BURSTS=1,C_SLOT_1_MAX_RD_BURSTS=1,C_SLOT_1_MAX_WR_BURSTS=1,C_SLOT_2_MAX_RD_BURSTS=5,C_SLOT_2_MAX_WR_BURSTS=5,C_SLOT_3_MAX_RD_BURSTS=5,C_SLOT_3_MAX_WR_BURSTS=5,C_SLOT_4_MAX_RD_BURSTS=5,C_SLOT_4_MAX_WR_BURSTS=5,C_SLOT_5_MAX_RD_BURSTS=5,C_SLOT_5_MAX_WR_BURSTS=5,C_SLOT_6_MAX_RD_BURSTS=5,C_SLOT_6_MAX_WR_BURSTS=5,C_SLOT_7_MAX_RD_BURSTS=5,C_SLOT_7_MAX_WR_BURSTS=5,C_SLOT_8_MAX_RD_BURSTS=5,C_SLOT_8_MAX_WR_BURSTS=5,C_SLOT_9_MAX_RD_BURSTS=5,C_SLOT_9_MAX_WR_BURSTS=5,C_SLOT_10_MAX_RD_BURSTS=5\
,C_SLOT_10_MAX_WR_BURSTS=5,C_SLOT_11_MAX_RD_BURSTS=5,C_SLOT_11_MAX_WR_BURSTS=5,C_SLOT_12_MAX_RD_BURSTS=5,C_SLOT_12_MAX_WR_BURSTS=5,C_SLOT_13_MAX_RD_BURSTS=5,C_SLOT_13_MAX_WR_BURSTS=5,C_SLOT_14_MAX_RD_BURSTS=5,C_SLOT_14_MAX_WR_BURSTS=5,C_SLOT_15_MAX_RD_BURSTS=5,C_SLOT_15_MAX_WR_BURSTS=5,C_SLOT_0_HAS_BRESP=1,C_SLOT_0_HAS_RRESP=1,C_SLOT_0_HAS_LOCK=0,C_SLOT_0_HAS_PROT=0,C_SLOT_0_HAS_CACHE=0,C_SLOT_0_HAS_QOS=0,C_SLOT_0_HAS_REGION=0,C_SLOT_0_HAS_BURST=0,C_SLOT_0_HAS_WSTRB=1,C_SLOT_0_HAS_TSTRB=1,C_SLOT\
_0_HAS_TKEEP=1,C_SLOT_1_HAS_BRESP=1,C_SLOT_1_HAS_RRESP=1,C_SLOT_1_HAS_LOCK=1,C_SLOT_1_HAS_PROT=1,C_SLOT_1_HAS_CACHE=1,C_SLOT_1_HAS_QOS=1,C_SLOT_1_HAS_REGION=0,C_SLOT_1_HAS_BURST=1,C_SLOT_1_HAS_WSTRB=1,C_SLOT_1_HAS_TSTRB=1,C_SLOT_1_HAS_TKEEP=1,C_SLOT_2_HAS_BRESP=1,C_SLOT_2_HAS_RRESP=1,C_SLOT_2_HAS_LOCK=1,C_SLOT_2_HAS_PROT=1,C_SLOT_2_HAS_CACHE=1,C_SLOT_2_HAS_QOS=1,C_SLOT_2_HAS_REGION=1,C_SLOT_2_HAS_BURST=1,C_SLOT_2_HAS_WSTRB=1,C_SLOT_2_HAS_TSTRB=1,C_SLOT_2_HAS_TKEEP=1,C_SLOT_3_HAS_BRESP=1,C_SLOT_3\
_HAS_RRESP=1,C_SLOT_3_HAS_LOCK=1,C_SLOT_3_HAS_PROT=1,C_SLOT_3_HAS_CACHE=1,C_SLOT_3_HAS_QOS=1,C_SLOT_3_HAS_REGION=1,C_SLOT_3_HAS_BURST=1,C_SLOT_3_HAS_WSTRB=1,C_SLOT_3_HAS_TSTRB=1,C_SLOT_3_HAS_TKEEP=1,C_SLOT_4_HAS_BRESP=1,C_SLOT_4_HAS_RRESP=1,C_SLOT_4_HAS_LOCK=1,C_SLOT_4_HAS_PROT=1,C_SLOT_4_HAS_CACHE=1,C_SLOT_4_HAS_QOS=1,C_SLOT_4_HAS_REGION=1,C_SLOT_4_HAS_BURST=1,C_SLOT_4_HAS_WSTRB=1,C_SLOT_4_HAS_TSTRB=1,C_SLOT_4_HAS_TKEEP=1,C_SLOT_5_HAS_BRESP=1,C_SLOT_5_HAS_RRESP=1,C_SLOT_5_HAS_LOCK=1,C_SLOT_5_HA\
S_PROT=1,C_SLOT_5_HAS_CACHE=1,C_SLOT_5_HAS_QOS=1,C_SLOT_5_HAS_REGION=1,C_SLOT_5_HAS_BURST=1,C_SLOT_5_HAS_WSTRB=1,C_SLOT_5_HAS_TSTRB=1,C_SLOT_5_HAS_TKEEP=1,C_SLOT_6_HAS_BRESP=1,C_SLOT_6_HAS_RRESP=1,C_SLOT_6_HAS_LOCK=1,C_SLOT_6_HAS_PROT=1,C_SLOT_6_HAS_CACHE=1,C_SLOT_6_HAS_QOS=1,C_SLOT_6_HAS_REGION=1,C_SLOT_6_HAS_BURST=1,C_SLOT_6_HAS_WSTRB=1,C_SLOT_6_HAS_TSTRB=1,C_SLOT_6_HAS_TKEEP=1,C_SLOT_7_HAS_BRESP=1,C_SLOT_7_HAS_RRESP=1,C_SLOT_7_HAS_LOCK=1,C_SLOT_7_HAS_PROT=1,C_SLOT_7_HAS_CACHE=1,C_SLOT_7_HAS_Q\
OS=1,C_SLOT_7_HAS_REGION=1,C_SLOT_7_HAS_BURST=1,C_SLOT_7_HAS_WSTRB=1,C_SLOT_7_HAS_TSTRB=1,C_SLOT_7_HAS_TKEEP=1,C_SLOT_8_HAS_BRESP=1,C_SLOT_8_HAS_RRESP=1,C_SLOT_8_HAS_LOCK=1,C_SLOT_8_HAS_PROT=1,C_SLOT_8_HAS_CACHE=1,C_SLOT_8_HAS_QOS=1,C_SLOT_8_HAS_REGION=1,C_SLOT_8_HAS_BURST=1,C_SLOT_8_HAS_WSTRB=1,C_SLOT_8_HAS_TSTRB=1,C_SLOT_8_HAS_TKEEP=1,C_SLOT_9_HAS_BRESP=1,C_SLOT_9_HAS_RRESP=1,C_SLOT_9_HAS_LOCK=1,C_SLOT_9_HAS_PROT=1,C_SLOT_9_HAS_CACHE=1,C_SLOT_9_HAS_QOS=1,C_SLOT_9_HAS_REGION=1,C_SLOT_9_HAS_BURS\
T=1,C_SLOT_9_HAS_WSTRB=1,C_SLOT_9_HAS_TSTRB=1,C_SLOT_9_HAS_TKEEP=1,C_SLOT_10_HAS_BRESP=1,C_SLOT_10_HAS_RRESP=1,C_SLOT_10_HAS_LOCK=1,C_SLOT_10_HAS_PROT=1,C_SLOT_10_HAS_CACHE=1,C_SLOT_10_HAS_QOS=1,C_SLOT_10_HAS_REGION=1,C_SLOT_10_HAS_BURST=1,C_SLOT_10_HAS_WSTRB=1,C_SLOT_10_HAS_TSTRB=1,C_SLOT_10_HAS_TKEEP=1,C_SLOT_11_HAS_BRESP=1,C_SLOT_11_HAS_RRESP=1,C_SLOT_11_HAS_LOCK=1,C_SLOT_11_HAS_PROT=1,C_SLOT_11_HAS_CACHE=1,C_SLOT_11_HAS_QOS=1,C_SLOT_11_HAS_REGION=1,C_SLOT_11_HAS_BURST=1,C_SLOT_11_HAS_WSTRB=1\
,C_SLOT_11_HAS_TSTRB=1,C_SLOT_11_HAS_TKEEP=1,C_SLOT_12_HAS_BRESP=1,C_SLOT_12_HAS_RRESP=1,C_SLOT_12_HAS_LOCK=1,C_SLOT_12_HAS_PROT=1,C_SLOT_12_HAS_CACHE=1,C_SLOT_12_HAS_QOS=1,C_SLOT_12_HAS_REGION=1,C_SLOT_12_HAS_BURST=1,C_SLOT_12_HAS_WSTRB=1,C_SLOT_12_HAS_TSTRB=1,C_SLOT_12_HAS_TKEEP=1,C_SLOT_13_HAS_BRESP=1,C_SLOT_13_HAS_RRESP=1,C_SLOT_13_HAS_LOCK=1,C_SLOT_13_HAS_PROT=1,C_SLOT_13_HAS_CACHE=1,C_SLOT_13_HAS_QOS=1,C_SLOT_13_HAS_REGION=1,C_SLOT_13_HAS_BURST=1,C_SLOT_13_HAS_WSTRB=1,C_SLOT_13_HAS_TSTRB=1\
,C_SLOT_13_HAS_TKEEP=1,C_SLOT_14_HAS_BRESP=1,C_SLOT_14_HAS_RRESP=1,C_SLOT_14_HAS_LOCK=1,C_SLOT_14_HAS_PROT=1,C_SLOT_14_HAS_CACHE=1,C_SLOT_14_HAS_QOS=1,C_SLOT_14_HAS_REGION=1,C_SLOT_14_HAS_BURST=1,C_SLOT_14_HAS_WSTRB=1,C_SLOT_14_HAS_TSTRB=1,C_SLOT_14_HAS_TKEEP=1,C_SLOT_15_HAS_BRESP=1,C_SLOT_15_HAS_RRESP=1,C_SLOT_15_HAS_LOCK=1,C_SLOT_15_HAS_PROT=1,C_SLOT_15_HAS_CACHE=1,C_SLOT_15_HAS_QOS=1,C_SLOT_15_HAS_REGION=1,C_SLOT_15_HAS_BURST=1,C_SLOT_15_HAS_WSTRB=1,C_SLOT_15_HAS_TSTRB=1,C_SLOT_0_HAS_TREADY=1\
,C_SLOT_1_HAS_TREADY=1,C_SLOT_2_HAS_TREADY=1,C_SLOT_3_HAS_TREADY=1,C_SLOT_4_HAS_TREADY=1,C_SLOT_5_HAS_TREADY=1,C_SLOT_6_HAS_TREADY=1,C_SLOT_7_HAS_TREADY=1,C_SLOT_8_HAS_TREADY=1,C_SLOT_9_HAS_TREADY=1,C_SLOT_10_HAS_TREADY=1,C_SLOT_11_HAS_TREADY=1,C_SLOT_12_HAS_TREADY=1,C_SLOT_13_HAS_TREADY=1,C_SLOT_14_HAS_TREADY=1,C_SLOT_15_HAS_TREADY=1,C_SLOT_15_HAS_TKEEP=1,C_MUX_0_AXI_AWUSER_WIDTH=1,C_MUX_0_AXI_WUSER_WIDTH=1,C_MUX_0_AXI_BUSER_WIDTH=1,C_MUX_0_AXI_ARUSER_WIDTH=1,C_MUX_0_AXI_RUSER_WIDTH=1,C_MUX_1_A\
XI_AWUSER_WIDTH=1,C_MUX_1_AXI_WUSER_WIDTH=1,C_MUX_1_AXI_BUSER_WIDTH=1,C_MUX_1_AXI_ARUSER_WIDTH=1,C_MUX_1_AXI_RUSER_WIDTH=1,C_MUX_2_AXI_AWUSER_WIDTH=1,C_MUX_2_AXI_WUSER_WIDTH=1,C_MUX_2_AXI_BUSER_WIDTH=1,C_MUX_2_AXI_ARUSER_WIDTH=1,C_MUX_2_AXI_RUSER_WIDTH=1,C_MUX_3_AXI_AWUSER_WIDTH=1,C_MUX_3_AXI_WUSER_WIDTH=1,C_MUX_3_AXI_BUSER_WIDTH=1,C_MUX_3_AXI_RUSER_WIDTH=1,C_MUX_3_AXI_ARUSER_WIDTH=1,C_SLOT_0_AXI_AWUSER_WIDTH=0,C_SLOT_0_AXI_WUSER_WIDTH=0,C_SLOT_0_AXI_BUSER_WIDTH=0,C_SLOT_0_AXI_ARUSER_WIDTH=0,C_S\
LOT_0_AXI_RUSER_WIDTH=0,C_SLOT_1_AXI_AWUSER_WIDTH=0,C_SLOT_1_AXI_WUSER_WIDTH=0,C_SLOT_1_AXI_BUSER_WIDTH=0,C_SLOT_1_AXI_ARUSER_WIDTH=0,C_SLOT_1_AXI_RUSER_WIDTH=0,C_SLOT_2_AXI_AWUSER_WIDTH=1,C_SLOT_2_AXI_WUSER_WIDTH=1,C_SLOT_2_AXI_BUSER_WIDTH=1,C_SLOT_2_AXI_ARUSER_WIDTH=1,C_SLOT_2_AXI_RUSER_WIDTH=1,C_SLOT_3_AXI_AWUSER_WIDTH=1,C_SLOT_3_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_BUSER_WIDTH=1,C_SLOT_3_AXI_ARUSER_WIDTH=1,C_SLOT_4_AXI_AWUSER_WIDTH=1,C_SLOT_4_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_RUSER_WIDTH=1,C_SLOT_4_A\
XI_BUSER_WIDTH=1,C_SLOT_4_AXI_ARUSER_WIDTH=1,C_SLOT_4_AXI_RUSER_WIDTH=1,C_SLOT_5_AXI_AWUSER_WIDTH=1,C_SLOT_5_AXI_WUSER_WIDTH=1,C_SLOT_5_AXI_BUSER_WIDTH=1,C_SLOT_5_AXI_ARUSER_WIDTH=1,C_SLOT_5_AXI_RUSER_WIDTH=1,C_SLOT_6_AXI_AWUSER_WIDTH=1,C_SLOT_6_AXI_WUSER_WIDTH=1,C_SLOT_6_AXI_BUSER_WIDTH=1,C_SLOT_6_AXI_ARUSER_WIDTH=1,C_SLOT_6_AXI_RUSER_WIDTH=1,C_SLOT_7_AXI_AWUSER_WIDTH=1,C_SLOT_7_AXI_WUSER_WIDTH=1,C_SLOT_7_AXI_BUSER_WIDTH=1,C_SLOT_7_AXI_ARUSER_WIDTH=1,C_SLOT_7_AXI_RUSER_WIDTH=1,C_SLOT_8_AXI_AWUS\
ER_WIDTH=1,C_SLOT_8_AXI_WUSER_WIDTH=1,C_SLOT_8_AXI_BUSER_WIDTH=1,C_SLOT_8_AXI_ARUSER_WIDTH=1,C_SLOT_8_AXI_RUSER_WIDTH=1,C_SLOT_9_AXI_AWUSER_WIDTH=1,C_SLOT_9_AXI_WUSER_WIDTH=1,C_SLOT_9_AXI_BUSER_WIDTH=1,C_SLOT_9_AXI_ARUSER_WIDTH=1,C_SLOT_9_AXI_RUSER_WIDTH=1,C_SLOT_10_AXI_AWUSER_WIDTH=1,C_SLOT_10_AXI_WUSER_WIDTH=1,C_SLOT_10_AXI_BUSER_WIDTH=1,C_SLOT_10_AXI_ARUSER_WIDTH=1,C_SLOT_10_AXI_RUSER_WIDTH=1,C_SLOT_11_AXI_AWUSER_WIDTH=1,C_SLOT_11_AXI_WUSER_WIDTH=1,C_SLOT_11_AXI_BUSER_WIDTH=1,C_SLOT_11_AXI_AR\
USER_WIDTH=1,C_SLOT_11_AXI_RUSER_WIDTH=1,C_SLOT_12_AXI_AWUSER_WIDTH=1,C_SLOT_12_AXI_WUSER_WIDTH=1,C_SLOT_12_AXI_BUSER_WIDTH=1,C_SLOT_12_AXI_ARUSER_WIDTH=1,C_SLOT_12_AXI_RUSER_WIDTH=1,C_SLOT_13_AXI_AWUSER_WIDTH=1,C_SLOT_13_AXI_WUSER_WIDTH=1,C_SLOT_13_AXI_BUSER_WIDTH=1,C_SLOT_13_AXI_ARUSER_WIDTH=1,C_SLOT_13_AXI_RUSER_WIDTH=1,C_SLOT_14_AXI_AWUSER_WIDTH=1,C_SLOT_14_AXI_WUSER_WIDTH=1,C_SLOT_14_AXI_BUSER_WIDTH=1,C_SLOT_14_AXI_ARUSER_WIDTH=1,C_SLOT_14_AXI_RUSER_WIDTH=1,C_SLOT_15_AXI_AWUSER_WIDTH=1,C_SL\
OT_15_AXI_WUSER_WIDTH=1,C_SLOT_15_AXI_BUSER_WIDTH=1,C_SLOT_15_AXI_ARUSER_WIDTH=1,C_SLOT_15_AXI_RUSER_WIDTH=1,C_EN_GIGAMUX=false,C_MUX_LEVEL=1,C_AXI_CH_SEL=ALL,C_SYNC_EN=false,C_SLOT_0_AXI_CH_SEL=ALL,C_SLOT_1_AXI_CH_SEL=ALL,C_SLOT_2_AXI_CH_SEL=ALL,C_SLOT_3_AXI_CH_SEL=ALL,C_SLOT_4_AXI_CH_SEL=ALL,C_SLOT_5_AXI_CH_SEL=ALL,C_SLOT_6_AXI_CH_SEL=ALL,C_SLOT_7_AXI_CH_SEL=ALL,C_SLOT_8_AXI_CH_SEL=ALL,C_SLOT_9_AXI_CH_SEL=ALL,C_SLOT_10_AXI_CH_SEL=ALL,C_SLOT_11_AXI_CH_SEL=ALL,C_SLOT_12_AXI_CH_SEL=ALL,C_SLOT_13_\
AXI_CH_SEL=ALL,C_SLOT_14_AXI_CH_SEL=ALL,C_SLOT_15_AXI_CH_SEL=ALL,C_SLOT_0_AXI_AW_SEL=1,C_SLOT_1_AXI_AW_SEL=1,C_SLOT_2_AXI_AW_SEL=1,C_SLOT_3_AXI_AW_SEL=1,C_SLOT_4_AXI_AW_SEL=1,C_SLOT_5_AXI_AW_SEL=1,C_SLOT_6_AXI_AW_SEL=1,C_SLOT_7_AXI_AW_SEL=1,C_SLOT_8_AXI_AW_SEL=1,C_SLOT_9_AXI_AW_SEL=1,C_SLOT_10_AXI_AW_SEL=1,C_SLOT_11_AXI_AW_SEL=1,C_SLOT_12_AXI_AW_SEL=1,C_SLOT_13_AXI_AW_SEL=1,C_SLOT_14_AXI_AW_SEL=1,C_SLOT_15_AXI_AW_SEL=1,C_SLOT_0_AXI_AR_SEL=1,C_SLOT_1_AXI_AR_SEL=1,C_SLOT_2_AXI_AR_SEL=1,C_SLOT_3_AX\
I_AR_SEL=1,C_SLOT_4_AXI_AR_SEL=1,C_SLOT_5_AXI_AR_SEL=1,C_SLOT_6_AXI_AR_SEL=1,C_SLOT_7_AXI_AR_SEL=1,C_SLOT_8_AXI_AR_SEL=1,C_SLOT_9_AXI_AR_SEL=1,C_SLOT_10_AXI_AR_SEL=1,C_SLOT_11_AXI_AR_SEL=1,C_SLOT_12_AXI_AR_SEL=1,C_SLOT_13_AXI_AR_SEL=1,C_SLOT_14_AXI_AR_SEL=1,C_SLOT_15_AXI_AR_SEL=1,C_SLOT_0_AXI_W_SEL=1,C_SLOT_1_AXI_W_SEL=1,C_SLOT_2_AXI_W_SEL=1,C_SLOT_3_AXI_W_SEL=1,C_SLOT_4_AXI_W_SEL=1,C_SLOT_5_AXI_W_SEL=1,C_SLOT_6_AXI_W_SEL=1,C_SLOT_7_AXI_W_SEL=1,C_SLOT_8_AXI_W_SEL=1,C_SLOT_9_AXI_W_SEL=1,C_SLOT_10\
_AXI_W_SEL=1,C_SLOT_11_AXI_W_SEL=1,C_SLOT_12_AXI_W_SEL=1,C_SLOT_13_AXI_W_SEL=1,C_SLOT_14_AXI_W_SEL=1,C_SLOT_15_AXI_W_SEL=1,C_SLOT_0_AXI_R_SEL=1,C_SLOT_1_AXI_R_SEL=1,C_SLOT_2_AXI_R_SEL=1,C_SLOT_3_AXI_R_SEL=1,C_SLOT_4_AXI_R_SEL=1,C_SLOT_5_AXI_R_SEL=1,C_SLOT_6_AXI_R_SEL=1,C_SLOT_7_AXI_R_SEL=1,C_SLOT_8_AXI_R_SEL=1,C_SLOT_9_AXI_R_SEL=1,C_SLOT_10_AXI_R_SEL=1,C_SLOT_11_AXI_R_SEL=1,C_SLOT_12_AXI_R_SEL=1,C_SLOT_13_AXI_R_SEL=1,C_SLOT_14_AXI_R_SEL=1,C_SLOT_15_AXI_R_SEL=1,C_SLOT_0_AXI_B_SEL=1,C_SLOT_1_AXI_B\
_SEL=1,C_SLOT_2_AXI_B_SEL=1,C_SLOT_3_AXI_B_SEL=1,C_SLOT_4_AXI_B_SEL=1,C_SLOT_5_AXI_B_SEL=1,C_SLOT_6_AXI_B_SEL=1,C_SLOT_7_AXI_B_SEL=1,C_SLOT_8_AXI_B_SEL=1,C_SLOT_9_AXI_B_SEL=1,C_SLOT_10_AXI_B_SEL=1,C_SLOT_11_AXI_B_SEL=1,C_SLOT_12_AXI_B_SEL=1,C_SLOT_13_AXI_B_SEL=1,C_SLOT_14_AXI_B_SEL=1,C_SLOT_15_AXI_B_SEL=1,C_SLOT_0_MON_MODE=FT,C_SLOT_1_MON_MODE=FT,C_SLOT_2_MON_MODE=RT,C_SLOT_3_MON_MODE=RT,C_SLOT_4_MON_MODE=RT,C_SLOT_5_MON_MODE=RT,C_SLOT_6_MON_MODE=RT,C_SLOT_7_MON_MODE=RT,C_SLOT_8_MON_MODE=RT,C_SL\
OT_9_MON_MODE=RT,C_SLOT_10_MON_MODE=RT,C_SLOT_11_MON_MODE=RT,C_SLOT_12_MON_MODE=RT,C_SLOT_13_MON_MODE=RT,C_SLOT_14_MON_MODE=RT,C_SLOT_15_MON_MODE=RT,C_SLOT_0_AXI_AXLEN_WIDTH=8,C_SLOT_0_AXI_AXLOCK_WIDTH=1,C_SLOT_1_AXI_AXLEN_WIDTH=8,C_SLOT_1_AXI_AXLOCK_WIDTH=1,C_SLOT_2_AXI_AXLEN_WIDTH=8,C_SLOT_2_AXI_AXLOCK_WIDTH=1,C_SLOT_3_AXI_AXLEN_WIDTH=8,C_SLOT_3_AXI_AXLOCK_WIDTH=1,C_SLOT_4_AXI_AXLEN_WIDTH=8,C_SLOT_4_AXI_AXLOCK_WIDTH=1,C_SLOT_5_AXI_AXLEN_WIDTH=8,C_SLOT_5_AXI_AXLOCK_WIDTH=1,C_SLOT_6_AXI_AXLEN_WI\
DTH=8,C_SLOT_6_AXI_AXLOCK_WIDTH=1,C_SLOT_7_AXI_AXLEN_WIDTH=8,C_SLOT_7_AXI_AXLOCK_WIDTH=1,C_SLOT_8_AXI_AXLEN_WIDTH=8,C_SLOT_8_AXI_AXLOCK_WIDTH=1,C_SLOT_9_AXI_AXLEN_WIDTH=8,C_SLOT_9_AXI_AXLOCK_WIDTH=1,C_SLOT_10_AXI_AXLEN_WIDTH=8,C_SLOT_10_AXI_AXLOCK_WIDTH=1,C_SLOT_11_AXI_AXLEN_WIDTH=8,C_SLOT_11_AXI_AXLOCK_WIDTH=1,C_SLOT_12_AXI_AXLEN_WIDTH=8,C_SLOT_12_AXI_AXLOCK_WIDTH=1,C_SLOT_13_AXI_AXLEN_WIDTH=8,C_SLOT_13_AXI_AXLOCK_WIDTH=1,C_SLOT_14_AXI_AXLEN_WIDTH=8,C_SLOT_14_AXI_AXLOCK_WIDTH=1,C_SLOT_15_AXI_AX\
LEN_WIDTH=8,C_SLOT_15_AXI_AXLOCK_WIDTH=1,C_MUX_0_AXI_AXLEN_WIDTH=8,C_MUX_0_AXI_AXLOCK_WIDTH=1,C_MUX_1_AXI_AXLEN_WIDTH=8,C_MUX_1_AXI_AXLOCK_WIDTH=1,C_MUX_2_AXI_AXLEN_WIDTH=8,C_MUX_2_AXI_AXLOCK_WIDTH=1,C_MUX_3_AXI_AXLEN_WIDTH=8,C_MUX_3_AXI_AXLOCK_WIDTH=1,C_MUX_0_AXI_ID_WIDTH=4,C_MUX_0_AXI_ADDR_WIDTH=32,C_MUX_0_AXI_DATA_WIDTH=32,C_MUX_0_AXI_PROTOCOL=AXI4,C_MUX_0_AXIS_TDATA_WIDTH=32,C_MUX_0_AXIS_TID_WIDTH=1,C_MUX_0_AXIS_TDEST_WIDTH=1,C_MUX_0_AXIS_TUSER_WIDTH=1,C_MUX_1_AXI_ID_WIDTH=4,C_MUX_1_AXI_ADDR\
_WIDTH=32,C_MUX_1_AXI_DATA_WIDTH=32,C_MUX_1_AXI_PROTOCOL=AXI4,C_MUX_1_AXIS_TDATA_WIDTH=32,C_MUX_1_AXIS_TID_WIDTH=1,C_MUX_1_AXIS_TDEST_WIDTH=1,C_MUX_1_AXIS_TUSER_WIDTH=1,C_MUX_2_AXI_ID_WIDTH=4,C_MUX_2_AXI_ADDR_WIDTH=32,C_MUX_2_AXI_DATA_WIDTH=32,C_MUX_2_AXI_PROTOCOL=AXI4,C_MUX_2_AXIS_TDATA_WIDTH=32,C_MUX_2_AXIS_TID_WIDTH=1,C_MUX_2_AXIS_TDEST_WIDTH=1,C_MUX_2_AXIS_TUSER_WIDTH=1,C_MUX_3_AXI_ID_WIDTH=4,C_MUX_3_AXI_ADDR_WIDTH=32,C_MUX_3_AXI_DATA_WIDTH=32,C_MUX_3_AXI_PROTOCOL=AXI4,C_MUX_3_AXIS_TDATA_WID\
TH=32,C_MUX_3_AXIS_TID_WIDTH=1,C_MUX_3_AXIS_TDEST_WIDTH=1,C_MUX_3_AXIS_TUSER_WIDTH=1,C_NUM_OF_PROBES=0,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_W\
IDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE\
50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_P\
ROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_W\
IDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1\
,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PRO\
BE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_\
WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=\
1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PR\
OBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263\
_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH\
=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_P\
ROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE34\
2_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,C_PROBE354_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE368_WIDT\
H=1,C_PROBE369_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE371_WIDTH=1,C_PROBE372_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE394_WIDTH=1,C_\
PROBE395_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE397_WIDTH=1,C_PROBE398_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE4\
21_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE424_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE447_WID\
TH=1,C_PROBE448_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE450_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE453_WIDTH=1,C_PROBE454_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE473_WIDTH=1,C\
_PROBE474_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE476_WIDTH=1,C_PROBE477_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE\
500_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE503_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE511_WIDTH=1,C_MUX_PROBE0_WIDTH=1,C_MUX_PROBE1_WIDTH=1,C_MUX_PROBE2_WIDTH=1,C_MUX_PROBE3_WIDTH=1,C_MUX_PROBE4_WIDTH=1,C_MUX_PROBE5_WIDTH=1,C_MUX_PROBE6_WIDTH=1,C_MUX_PROBE7_WIDTH=1,C_MUX_PROBE8_WIDTH=1,C_MUX_PROBE9_WIDTH=1,C_MUX_PROBE10_WIDTH=1,C_MUX_PROBE11_WIDTH=1,C_MUX_PROBE12_WIDTH=1,C_M\
UX_PROBE13_WIDTH=1,C_MUX_PROBE14_WIDTH=1,C_MUX_PROBE15_WIDTH=1,C_MUX_PROBE16_WIDTH=1,C_MUX_PROBE17_WIDTH=1,C_MUX_PROBE18_WIDTH=1,C_MUX_PROBE19_WIDTH=1,C_MUX_PROBE20_WIDTH=1,C_MUX_PROBE21_WIDTH=1,C_MUX_PROBE22_WIDTH=1,C_MUX_PROBE23_WIDTH=1,C_MUX_PROBE24_WIDTH=1,C_MUX_PROBE25_WIDTH=1,C_MUX_PROBE26_WIDTH=1,C_MUX_PROBE27_WIDTH=1,C_MUX_PROBE28_WIDTH=1,C_MUX_PROBE29_WIDTH=1,C_MUX_PROBE30_WIDTH=1,C_MUX_PROBE31_WIDTH=1,C_MUX_PROBE32_WIDTH=1,C_MUX_PROBE33_WIDTH=1,C_MUX_PROBE34_WIDTH=1,C_MUX_PROBE35_WIDTH\
=1,C_MUX_PROBE36_WIDTH=1,C_MUX_PROBE37_WIDTH=1,C_MUX_PROBE38_WIDTH=1,C_MUX_PROBE39_WIDTH=1,C_MUX_PROBE40_WIDTH=1,C_MUX_PROBE41_WIDTH=1,C_MUX_PROBE42_WIDTH=1,C_MUX_PROBE43_WIDTH=1,C_MUX_PROBE44_WIDTH=1,C_MUX_PROBE45_WIDTH=1,C_MUX_PROBE46_WIDTH=1,C_MUX_PROBE47_WIDTH=1,C_MUX_PROBE48_WIDTH=1,C_MUX_PROBE49_WIDTH=1,C_MUX_PROBE50_WIDTH=1,C_MUX_PROBE51_WIDTH=1,C_MUX_PROBE52_WIDTH=1,C_MUX_PROBE53_WIDTH=1,C_MUX_PROBE54_WIDTH=1,C_MUX_PROBE55_WIDTH=1,C_MUX_PROBE56_WIDTH=1,C_MUX_PROBE57_WIDTH=1,C_MUX_PROBE58\
_WIDTH=1,C_MUX_PROBE59_WIDTH=1,C_MUX_PROBE60_WIDTH=1,C_MUX_PROBE61_WIDTH=1,C_MUX_PROBE62_WIDTH=1,C_MUX_PROBE63_WIDTH=1,C_MUX_PROBE64_WIDTH=1,C_MUX_PROBE65_WIDTH=1,C_MUX_PROBE66_WIDTH=1,C_MUX_PROBE67_WIDTH=1,C_MUX_PROBE68_WIDTH=1,C_MUX_PROBE69_WIDTH=1,C_MUX_PROBE70_WIDTH=1,C_MUX_PROBE71_WIDTH=1,C_MUX_PROBE72_WIDTH=1,C_MUX_PROBE73_WIDTH=1,C_MUX_PROBE74_WIDTH=1,C_MUX_PROBE75_WIDTH=1,C_MUX_PROBE76_WIDTH=1,C_MUX_PROBE77_WIDTH=1,C_MUX_PROBE78_WIDTH=1,C_MUX_PROBE79_WIDTH=1,C_MUX_PROBE80_WIDTH=1,C_MUX_P\
ROBE81_WIDTH=1,C_MUX_PROBE82_WIDTH=1,C_MUX_PROBE83_WIDTH=1,C_MUX_PROBE84_WIDTH=1,C_MUX_PROBE85_WIDTH=1,C_MUX_PROBE86_WIDTH=1,C_MUX_PROBE87_WIDTH=1,C_MUX_PROBE88_WIDTH=1,C_MUX_PROBE89_WIDTH=1,C_MUX_PROBE90_WIDTH=1,C_MUX_PROBE91_WIDTH=1,C_MUX_PROBE92_WIDTH=1,C_MUX_PROBE93_WIDTH=1,C_MUX_PROBE94_WIDTH=1,C_MUX_PROBE95_WIDTH=1,C_MUX_PROBE96_WIDTH=1,C_MUX_PROBE97_WIDTH=1,C_MUX_PROBE98_WIDTH=1,C_MUX_PROBE99_WIDTH=1,C_MUX_PROBE100_WIDTH=1,C_MUX_PROBE101_WIDTH=1,C_MUX_PROBE102_WIDTH=1,C_MUX_PROBE103_WIDTH\
=1,C_MUX_PROBE104_WIDTH=1,C_MUX_PROBE105_WIDTH=1,C_MUX_PROBE106_WIDTH=1,C_MUX_PROBE107_WIDTH=1,C_MUX_PROBE108_WIDTH=1,C_MUX_PROBE109_WIDTH=1,C_MUX_PROBE110_WIDTH=1,C_MUX_PROBE111_WIDTH=1,C_MUX_PROBE112_WIDTH=1,C_MUX_PROBE113_WIDTH=1,C_MUX_PROBE114_WIDTH=1,C_MUX_PROBE115_WIDTH=1,C_MUX_PROBE116_WIDTH=1,C_MUX_PROBE117_WIDTH=1,C_MUX_PROBE118_WIDTH=1,C_MUX_PROBE119_WIDTH=1,C_MUX_PROBE120_WIDTH=1,C_MUX_PROBE121_WIDTH=1,C_MUX_PROBE122_WIDTH=1,C_MUX_PROBE123_WIDTH=1,C_MUX_PROBE124_WIDTH=1,C_MUX_PROBE125\
_WIDTH=1,C_MUX_PROBE126_WIDTH=1,C_MUX_PROBE127_WIDTH=1,C_SLOT_0_AXI_ADDR_WIDTH=9,C_SLOT_0_AXI_DATA_WIDTH=32,C_SLOT_0_AXI_ID_WIDTH=0,C_SLOT_0_AXI_PROTOCOL=AXI4LITE,C_SLOT_0_AXIS_TDATA_WIDTH=32,C_SLOT_0_AXIS_TID_WIDTH=1,C_SLOT_0_AXIS_TDEST_WIDTH=1,C_SLOT_0_AXIS_TUSER_WIDTH=1,C_SLOT_1_AXI_ADDR_WIDTH=16,C_SLOT_1_AXI_DATA_WIDTH=32,C_SLOT_1_AXI_ID_WIDTH=12,C_SLOT_1_AXI_PROTOCOL=AXI4,C_SLOT_1_AXIS_TDATA_WIDTH=32,C_SLOT_1_AXIS_TID_WIDTH=1,C_SLOT_1_AXIS_TDEST_WIDTH=1,C_SLOT_1_AXIS_TUSER_WIDTH=1,C_SLOT_2_\
AXI_ADDR_WIDTH=32,C_SLOT_2_AXI_DATA_WIDTH=32,C_SLOT_2_AXI_ID_WIDTH=1,C_SLOT_2_AXI_PROTOCOL=AXI4,C_SLOT_2_AXIS_TDATA_WIDTH=32,C_SLOT_2_AXIS_TID_WIDTH=1,C_SLOT_2_AXIS_TDEST_WIDTH=1,C_SLOT_2_AXIS_TUSER_WIDTH=1,C_SLOT_3_AXI_ADDR_WIDTH=32,C_SLOT_3_AXI_DATA_WIDTH=32,C_SLOT_3_AXI_ID_WIDTH=1,C_SLOT_3_AXI_PROTOCOL=AXI4,C_SLOT_3_AXIS_TDATA_WIDTH=32,C_SLOT_3_AXIS_TID_WIDTH=1,C_SLOT_3_AXIS_TDEST_WIDTH=1,C_SLOT_3_AXIS_TUSER_WIDTH=1,C_SLOT_4_AXI_ADDR_WIDTH=32,C_SLOT_4_AXI_DATA_WIDTH=32,C_SLOT_4_AXI_ID_WIDTH=1\
,C_SLOT_4_AXI_PROTOCOL=AXI4,C_SLOT_4_AXIS_TDATA_WIDTH=32,C_SLOT_4_AXIS_TID_WIDTH=1,C_SLOT_4_AXIS_TDEST_WIDTH=1,C_SLOT_4_AXIS_TUSER_WIDTH=1,C_SLOT_5_AXI_ADDR_WIDTH=32,C_SLOT_5_AXI_DATA_WIDTH=32,C_SLOT_5_AXI_ID_WIDTH=1,C_SLOT_5_AXI_PROTOCOL=AXI4,C_SLOT_5_AXIS_TDATA_WIDTH=32,C_SLOT_5_AXIS_TID_WIDTH=1,C_SLOT_5_AXIS_TDEST_WIDTH=1,C_SLOT_5_AXIS_TUSER_WIDTH=1,C_SLOT_6_AXI_ADDR_WIDTH=32,C_SLOT_6_AXI_DATA_WIDTH=32,C_SLOT_6_AXI_ID_WIDTH=1,C_SLOT_6_AXI_PROTOCOL=AXI4,C_SLOT_6_AXIS_TDATA_WIDTH=32,C_SLOT_6_AX\
IS_TID_WIDTH=1,C_SLOT_6_AXIS_TDEST_WIDTH=1,C_SLOT_6_AXIS_TUSER_WIDTH=1,C_SLOT_7_AXI_ADDR_WIDTH=32,C_SLOT_7_AXI_DATA_WIDTH=32,C_SLOT_7_AXI_ID_WIDTH=1,C_SLOT_7_AXI_PROTOCOL=AXI4,C_SLOT_7_AXIS_TDATA_WIDTH=32,C_SLOT_7_AXIS_TID_WIDTH=1,C_SLOT_7_AXIS_TDEST_WIDTH=1,C_SLOT_7_AXIS_TUSER_WIDTH=1,C_SLOT_8_AXI_ADDR_WIDTH=32,C_SLOT_8_AXI_DATA_WIDTH=32,C_SLOT_8_AXI_ID_WIDTH=1,C_SLOT_8_AXI_PROTOCOL=AXI4,C_SLOT_8_AXIS_TDATA_WIDTH=32,C_SLOT_8_AXIS_TID_WIDTH=1,C_SLOT_8_AXIS_TDEST_WIDTH=1,C_SLOT_8_AXIS_TUSER_WIDTH\
=1,C_SLOT_9_AXI_ADDR_WIDTH=32,C_SLOT_9_AXI_DATA_WIDTH=32,C_SLOT_9_AXI_ID_WIDTH=1,C_SLOT_9_AXI_PROTOCOL=AXI4,C_SLOT_9_AXIS_TDATA_WIDTH=32,C_SLOT_9_AXIS_TID_WIDTH=1,C_SLOT_9_AXIS_TDEST_WIDTH=1,C_SLOT_9_AXIS_TUSER_WIDTH=1,C_SLOT_10_AXI_ADDR_WIDTH=32,C_SLOT_10_AXI_DATA_WIDTH=32,C_SLOT_10_AXI_ID_WIDTH=1,C_SLOT_10_AXI_PROTOCOL=AXI4,C_SLOT_10_AXIS_TDATA_WIDTH=32,C_SLOT_10_AXIS_TID_WIDTH=1,C_SLOT_10_AXIS_TDEST_WIDTH=1,C_SLOT_10_AXIS_TUSER_WIDTH=1,C_SLOT_11_AXI_ADDR_WIDTH=32,C_SLOT_11_AXI_DATA_WIDTH=32,C\
_SLOT_11_AXI_ID_WIDTH=1,C_SLOT_11_AXI_PROTOCOL=AXI4,C_SLOT_11_AXIS_TDATA_WIDTH=32,C_SLOT_11_AXIS_TID_WIDTH=1,C_SLOT_11_AXIS_TDEST_WIDTH=1,C_SLOT_11_AXIS_TUSER_WIDTH=1,C_SLOT_12_AXI_ADDR_WIDTH=32,C_SLOT_12_AXI_DATA_WIDTH=32,C_SLOT_12_AXI_ID_WIDTH=1,C_SLOT_12_AXI_PROTOCOL=AXI4,C_SLOT_12_AXIS_TDATA_WIDTH=32,C_SLOT_12_AXIS_TID_WIDTH=1,C_SLOT_12_AXIS_TDEST_WIDTH=1,C_SLOT_12_AXIS_TUSER_WIDTH=1,C_SLOT_13_AXI_ADDR_WIDTH=32,C_SLOT_13_AXI_DATA_WIDTH=32,C_SLOT_13_AXI_ID_WIDTH=1,C_SLOT_13_AXI_PROTOCOL=AXI4,\
C_SLOT_13_AXIS_TDATA_WIDTH=32,C_SLOT_13_AXIS_TID_WIDTH=1,C_SLOT_13_AXIS_TDEST_WIDTH=1,C_SLOT_13_AXIS_TUSER_WIDTH=1,C_SLOT_14_AXI_ADDR_WIDTH=32,C_SLOT_14_AXI_DATA_WIDTH=32,C_SLOT_14_AXI_ID_WIDTH=1,C_SLOT_14_AXI_PROTOCOL=AXI4,C_SLOT_14_AXIS_TDATA_WIDTH=32,C_SLOT_14_AXIS_TID_WIDTH=1,C_SLOT_14_AXIS_TDEST_WIDTH=1,C_SLOT_14_AXIS_TUSER_WIDTH=1,C_SLOT_15_AXI_ADDR_WIDTH=32,C_SLOT_15_AXI_DATA_WIDTH=32,C_SLOT_15_AXI_ID_WIDTH=1,C_SLOT_15_AXI_PROTOCOL=AXI4,C_SLOT_15_AXIS_TDATA_WIDTH=32,C_SLOT_15_AXIS_TID_WID\
TH=1,C_SLOT_15_AXIS_TDEST_WIDTH=1,C_SLOT_15_AXIS_TUSER_WIDTH=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_g_inst_0 (
aclk,
aresetn,
m_slot_0_axi_b_cnt,
m_slot_0_axi_r_cnt,
m_slot_1_axi_b_cnt,
m_slot_1_axi_r_cnt,
m_slot_0_axi_aw_cnt,
m_slot_0_axi_ar_cnt,
m_slot_1_axi_aw_cnt,
m_slot_1_axi_ar_cnt,
slot_0_axi_awaddr,
slot_0_axi_awvalid,
slot_0_axi_awready,
slot_0_axi_wdata,
slot_0_axi_wstrb,
slot_0_axi_wvalid,
slot_0_axi_wready,
slot_0_axi_bresp,
slot_0_axi_bvalid,
slot_0_axi_bready,
slot_0_axi_araddr,
slot_0_axi_arvalid,
slot_0_axi_arready,
slot_0_axi_rdata,
slot_0_axi_rresp,
slot_0_axi_rvalid,
slot_0_axi_rready,
slot_1_axi_awid,
slot_1_axi_awaddr,
slot_1_axi_awprot,
slot_1_axi_awlen,
slot_1_axi_awsize,
slot_1_axi_awburst,
slot_1_axi_awcache,
slot_1_axi_awlock,
slot_1_axi_awvalid,
slot_1_axi_awready,
slot_1_axi_wdata,
slot_1_axi_wstrb,
slot_1_axi_wlast,
slot_1_axi_wvalid,
slot_1_axi_wready,
slot_1_axi_bid,
slot_1_axi_bresp,
slot_1_axi_bvalid,
slot_1_axi_bready,
slot_1_axi_arid,
slot_1_axi_araddr,
slot_1_axi_arlen,
slot_1_axi_arsize,
slot_1_axi_arburst,
slot_1_axi_arcache,
slot_1_axi_arprot,
slot_1_axi_arlock,
slot_1_axi_arvalid,
slot_1_axi_arready,
slot_1_axi_rid,
slot_1_axi_rdata,
slot_1_axi_rresp,
slot_1_axi_rlast,
slot_1_axi_rvalid,
slot_1_axi_rready,
m_slot_0_axi_awaddr,
m_slot_0_axi_awvalid,
m_slot_0_axi_awready,
m_slot_0_axi_wdata,
m_slot_0_axi_wstrb,
m_slot_0_axi_wvalid,
m_slot_0_axi_wready,
m_slot_0_axi_bresp,
m_slot_0_axi_bvalid,
m_slot_0_axi_bready,
m_slot_0_axi_araddr,
m_slot_0_axi_arvalid,
m_slot_0_axi_arready,
m_slot_0_axi_rdata,
m_slot_0_axi_rresp,
m_slot_0_axi_rvalid,
m_slot_0_axi_rready,
m_slot_1_axi_awid,
m_slot_1_axi_awaddr,
m_slot_1_axi_awprot,
m_slot_1_axi_awlen,
m_slot_1_axi_awsize,
m_slot_1_axi_awburst,
m_slot_1_axi_awcache,
m_slot_1_axi_awlock,
m_slot_1_axi_awvalid,
m_slot_1_axi_awready,
m_slot_1_axi_wdata,
m_slot_1_axi_wstrb,
m_slot_1_axi_wlast,
m_slot_1_axi_wvalid,
m_slot_1_axi_wready,
m_slot_1_axi_bid,
m_slot_1_axi_bresp,
m_slot_1_axi_bvalid,
m_slot_1_axi_bready,
m_slot_1_axi_arid,
m_slot_1_axi_araddr,
m_slot_1_axi_arlen,
m_slot_1_axi_arsize,
m_slot_1_axi_arburst,
m_slot_1_axi_arcache,
m_slot_1_axi_arprot,
m_slot_1_axi_arlock,
m_slot_1_axi_arvalid,
m_slot_1_axi_arready,
m_slot_1_axi_rid,
m_slot_1_axi_rdata,
m_slot_1_axi_rresp,
m_slot_1_axi_rlast,
m_slot_1_axi_rvalid,
m_slot_1_axi_rready,
slot_1_axi_awqos,
slot_1_axi_arqos,
m_slot_1_axi_awqos,
m_slot_1_axi_arqos
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 signal_reset RST" *)
input wire aresetn;
output wire [1 : 0] m_slot_0_axi_b_cnt;
output wire [1 : 0] m_slot_0_axi_r_cnt;
output wire [1 : 0] m_slot_1_axi_b_cnt;
output wire [1 : 0] m_slot_1_axi_r_cnt;
output wire [1 : 0] m_slot_0_axi_aw_cnt;
output wire [1 : 0] m_slot_0_axi_ar_cnt;
output wire [1 : 0] m_slot_1_axi_aw_cnt;
output wire [1 : 0] m_slot_1_axi_ar_cnt;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi AWADDR" *)
input wire [8 : 0] slot_0_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi AWVALID" *)
input wire slot_0_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi AWREADY" *)
input wire slot_0_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi WDATA" *)
input wire [31 : 0] slot_0_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi WSTRB" *)
input wire [3 : 0] slot_0_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi WVALID" *)
input wire slot_0_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi WREADY" *)
input wire slot_0_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi BRESP" *)
input wire [1 : 0] slot_0_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi BVALID" *)
input wire slot_0_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi BREADY" *)
input wire slot_0_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi ARADDR" *)
input wire [8 : 0] slot_0_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi ARVALID" *)
input wire slot_0_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi ARREADY" *)
input wire slot_0_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi RDATA" *)
input wire [31 : 0] slot_0_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi RRESP" *)
input wire [1 : 0] slot_0_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi RVALID" *)
input wire slot_0_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi RREADY" *)
input wire slot_0_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWID" *)
input wire [11 : 0] slot_1_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWADDR" *)
input wire [15 : 0] slot_1_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWPROT" *)
input wire [2 : 0] slot_1_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWLEN" *)
input wire [7 : 0] slot_1_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWSIZE" *)
input wire [2 : 0] slot_1_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWBURST" *)
input wire [1 : 0] slot_1_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWCACHE" *)
input wire [3 : 0] slot_1_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWLOCK" *)
input wire [0 : 0] slot_1_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWVALID" *)
input wire slot_1_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWREADY" *)
input wire slot_1_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi WDATA" *)
input wire [31 : 0] slot_1_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi WSTRB" *)
input wire [3 : 0] slot_1_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi WLAST" *)
input wire slot_1_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi WVALID" *)
input wire slot_1_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi WREADY" *)
input wire slot_1_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi BID" *)
input wire [11 : 0] slot_1_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi BRESP" *)
input wire [1 : 0] slot_1_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi BVALID" *)
input wire slot_1_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi BREADY" *)
input wire slot_1_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARID" *)
input wire [11 : 0] slot_1_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARADDR" *)
input wire [15 : 0] slot_1_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARLEN" *)
input wire [7 : 0] slot_1_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARSIZE" *)
input wire [2 : 0] slot_1_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARBURST" *)
input wire [1 : 0] slot_1_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARCACHE" *)
input wire [3 : 0] slot_1_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARPROT" *)
input wire [2 : 0] slot_1_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARLOCK" *)
input wire [0 : 0] slot_1_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARVALID" *)
input wire slot_1_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARREADY" *)
input wire slot_1_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi RID" *)
input wire [11 : 0] slot_1_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi RDATA" *)
input wire [31 : 0] slot_1_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi RRESP" *)
input wire [1 : 0] slot_1_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi RLAST" *)
input wire slot_1_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi RVALID" *)
input wire slot_1_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi RREADY" *)
input wire slot_1_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi AWADDR" *)
output wire [8 : 0] m_slot_0_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi AWVALID" *)
output wire m_slot_0_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi AWREADY" *)
output wire m_slot_0_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi WDATA" *)
output wire [31 : 0] m_slot_0_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi WSTRB" *)
output wire [3 : 0] m_slot_0_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi WVALID" *)
output wire m_slot_0_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi WREADY" *)
output wire m_slot_0_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi BRESP" *)
output wire [1 : 0] m_slot_0_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi BVALID" *)
output wire m_slot_0_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi BREADY" *)
output wire m_slot_0_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi ARADDR" *)
output wire [8 : 0] m_slot_0_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi ARVALID" *)
output wire m_slot_0_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi ARREADY" *)
output wire m_slot_0_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi RDATA" *)
output wire [31 : 0] m_slot_0_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi RRESP" *)
output wire [1 : 0] m_slot_0_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi RVALID" *)
output wire m_slot_0_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi RREADY" *)
output wire m_slot_0_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWID" *)
output wire [11 : 0] m_slot_1_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWADDR" *)
output wire [15 : 0] m_slot_1_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWPROT" *)
output wire [2 : 0] m_slot_1_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWLEN" *)
output wire [7 : 0] m_slot_1_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWSIZE" *)
output wire [2 : 0] m_slot_1_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWBURST" *)
output wire [1 : 0] m_slot_1_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWCACHE" *)
output wire [3 : 0] m_slot_1_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWLOCK" *)
output wire [0 : 0] m_slot_1_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWVALID" *)
output wire m_slot_1_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWREADY" *)
output wire m_slot_1_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi WDATA" *)
output wire [31 : 0] m_slot_1_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi WSTRB" *)
output wire [3 : 0] m_slot_1_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi WLAST" *)
output wire m_slot_1_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi WVALID" *)
output wire m_slot_1_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi WREADY" *)
output wire m_slot_1_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi BID" *)
output wire [11 : 0] m_slot_1_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi BRESP" *)
output wire [1 : 0] m_slot_1_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi BVALID" *)
output wire m_slot_1_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi BREADY" *)
output wire m_slot_1_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARID" *)
output wire [11 : 0] m_slot_1_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARADDR" *)
output wire [15 : 0] m_slot_1_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARLEN" *)
output wire [7 : 0] m_slot_1_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARSIZE" *)
output wire [2 : 0] m_slot_1_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARBURST" *)
output wire [1 : 0] m_slot_1_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARCACHE" *)
output wire [3 : 0] m_slot_1_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARPROT" *)
output wire [2 : 0] m_slot_1_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARLOCK" *)
output wire [0 : 0] m_slot_1_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARVALID" *)
output wire m_slot_1_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARREADY" *)
output wire m_slot_1_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi RID" *)
output wire [11 : 0] m_slot_1_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi RDATA" *)
output wire [31 : 0] m_slot_1_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi RRESP" *)
output wire [1 : 0] m_slot_1_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi RLAST" *)
output wire m_slot_1_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi RVALID" *)
output wire m_slot_1_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi RREADY" *)
output wire m_slot_1_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWQOS" *)
input wire [3 : 0] slot_1_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi ARQOS" *)
input wire [3 : 0] slot_1_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWQOS" *)
output wire [3 : 0] m_slot_1_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi ARQOS" *)
output wire [3 : 0] m_slot_1_axi_arqos;
bd_350b_g_inst_0_gigantic_mux #(
.C_MUX_0_HAS_BRESP(1),
.C_MUX_0_HAS_RRESP(1),
.C_MUX_0_HAS_LOCK(1),
.C_MUX_0_HAS_PROT(1),
.C_MUX_0_HAS_CACHE(1),
.C_MUX_0_HAS_QOS(1),
.C_MUX_0_HAS_REGION(1),
.C_MUX_0_HAS_BURST(1),
.C_MUX_0_HAS_WSTRB(1),
.C_MUX_0_HAS_TSTRB(1),
.C_MUX_0_HAS_TKEEP(1),
.C_MUX_1_HAS_BRESP(1),
.C_MUX_1_HAS_RRESP(1),
.C_MUX_1_HAS_LOCK(1),
.C_MUX_1_HAS_PROT(1),
.C_MUX_1_HAS_CACHE(1),
.C_MUX_1_HAS_QOS(1),
.C_MUX_1_HAS_REGION(1),
.C_MUX_1_HAS_BURST(1),
.C_MUX_1_HAS_WSTRB(1),
.C_MUX_1_HAS_TSTRB(1),
.C_MUX_1_HAS_TKEEP(1),
.C_MUX_2_HAS_BRESP(1),
.C_MUX_2_HAS_RRESP(1),
.C_MUX_2_HAS_LOCK(1),
.C_MUX_2_HAS_PROT(1),
.C_MUX_2_HAS_CACHE(1),
.C_MUX_2_HAS_QOS(1),
.C_MUX_2_HAS_REGION(1),
.C_MUX_2_HAS_BURST(1),
.C_MUX_2_HAS_WSTRB(1),
.C_MUX_2_HAS_TSTRB(1),
.C_MUX_2_HAS_TKEEP(1),
.C_MUX_3_HAS_BRESP(1),
.C_MUX_3_HAS_RRESP(1),
.C_MUX_3_HAS_LOCK(1),
.C_MUX_3_HAS_PROT(1),
.C_MUX_3_HAS_CACHE(1),
.C_MUX_3_HAS_QOS(1),
.C_MUX_3_HAS_REGION(1),
.C_MUX_3_HAS_BURST(1),
.C_MUX_3_HAS_WSTRB(1),
.C_MUX_3_HAS_TSTRB(1),
.C_MUX_3_HAS_TKEEP(1),
.C_NUM_MONITOR_SLOTS(2),
.C_SLOT_0_TXN_CNTR_EN(1),
.C_SLOT_1_TXN_CNTR_EN(1),
.C_SLOT_2_TXN_CNTR_EN(1),
.C_SLOT_3_TXN_CNTR_EN(1),
.C_SLOT_4_TXN_CNTR_EN(1),
.C_SLOT_5_TXN_CNTR_EN(1),
.C_SLOT_6_TXN_CNTR_EN(1),
.C_SLOT_7_TXN_CNTR_EN(1),
.C_SLOT_8_TXN_CNTR_EN(1),
.C_SLOT_9_TXN_CNTR_EN(1),
.C_SLOT_10_TXN_CNTR_EN(1),
.C_SLOT_11_TXN_CNTR_EN(1),
.C_SLOT_12_TXN_CNTR_EN(1),
.C_SLOT_13_TXN_CNTR_EN(1),
.C_SLOT_14_TXN_CNTR_EN(1),
.C_SLOT_15_TXN_CNTR_EN(1),
.C_SLOT_0_MAX_RD_BURSTS(1),
.C_SLOT_0_MAX_WR_BURSTS(1),
.C_SLOT_1_MAX_RD_BURSTS(1),
.C_SLOT_1_MAX_WR_BURSTS(1),
.C_SLOT_2_MAX_RD_BURSTS(5),
.C_SLOT_2_MAX_WR_BURSTS(5),
.C_SLOT_3_MAX_RD_BURSTS(5),
.C_SLOT_3_MAX_WR_BURSTS(5),
.C_SLOT_4_MAX_RD_BURSTS(5),
.C_SLOT_4_MAX_WR_BURSTS(5),
.C_SLOT_5_MAX_RD_BURSTS(5),
.C_SLOT_5_MAX_WR_BURSTS(5),
.C_SLOT_6_MAX_RD_BURSTS(5),
.C_SLOT_6_MAX_WR_BURSTS(5),
.C_SLOT_7_MAX_RD_BURSTS(5),
.C_SLOT_7_MAX_WR_BURSTS(5),
.C_SLOT_8_MAX_RD_BURSTS(5),
.C_SLOT_8_MAX_WR_BURSTS(5),
.C_SLOT_9_MAX_RD_BURSTS(5),
.C_SLOT_9_MAX_WR_BURSTS(5),
.C_SLOT_10_MAX_RD_BURSTS(5),
.C_SLOT_10_MAX_WR_BURSTS(5),
.C_SLOT_11_MAX_RD_BURSTS(5),
.C_SLOT_11_MAX_WR_BURSTS(5),
.C_SLOT_12_MAX_RD_BURSTS(5),
.C_SLOT_12_MAX_WR_BURSTS(5),
.C_SLOT_13_MAX_RD_BURSTS(5),
.C_SLOT_13_MAX_WR_BURSTS(5),
.C_SLOT_14_MAX_RD_BURSTS(5),
.C_SLOT_14_MAX_WR_BURSTS(5),
.C_SLOT_15_MAX_RD_BURSTS(5),
.C_SLOT_15_MAX_WR_BURSTS(5),
.C_SLOT_0_HAS_BRESP(1),
.C_SLOT_0_HAS_RRESP(1),
.C_SLOT_0_HAS_LOCK(0),
.C_SLOT_0_HAS_PROT(0),
.C_SLOT_0_HAS_CACHE(0),
.C_SLOT_0_HAS_QOS(0),
.C_SLOT_0_HAS_REGION(0),
.C_SLOT_0_HAS_BURST(0),
.C_SLOT_0_HAS_WSTRB(1),
.C_SLOT_0_HAS_TSTRB(1),
.C_SLOT_0_HAS_TKEEP(1),
.C_SLOT_1_HAS_BRESP(1),
.C_SLOT_1_HAS_RRESP(1),
.C_SLOT_1_HAS_LOCK(1),
.C_SLOT_1_HAS_PROT(1),
.C_SLOT_1_HAS_CACHE(1),
.C_SLOT_1_HAS_QOS(1),
.C_SLOT_1_HAS_REGION(0),
.C_SLOT_1_HAS_BURST(1),
.C_SLOT_1_HAS_WSTRB(1),
.C_SLOT_1_HAS_TSTRB(1),
.C_SLOT_1_HAS_TKEEP(1),
.C_SLOT_2_HAS_BRESP(1),
.C_SLOT_2_HAS_RRESP(1),
.C_SLOT_2_HAS_LOCK(1),
.C_SLOT_2_HAS_PROT(1),
.C_SLOT_2_HAS_CACHE(1),
.C_SLOT_2_HAS_QOS(1),
.C_SLOT_2_HAS_REGION(1),
.C_SLOT_2_HAS_BURST(1),
.C_SLOT_2_HAS_WSTRB(1),
.C_SLOT_2_HAS_TSTRB(1),
.C_SLOT_2_HAS_TKEEP(1),
.C_SLOT_3_HAS_BRESP(1),
.C_SLOT_3_HAS_RRESP(1),
.C_SLOT_3_HAS_LOCK(1),
.C_SLOT_3_HAS_PROT(1),
.C_SLOT_3_HAS_CACHE(1),
.C_SLOT_3_HAS_QOS(1),
.C_SLOT_3_HAS_REGION(1),
.C_SLOT_3_HAS_BURST(1),
.C_SLOT_3_HAS_WSTRB(1),
.C_SLOT_3_HAS_TSTRB(1),
.C_SLOT_3_HAS_TKEEP(1),
.C_SLOT_4_HAS_BRESP(1),
.C_SLOT_4_HAS_RRESP(1),
.C_SLOT_4_HAS_LOCK(1),
.C_SLOT_4_HAS_PROT(1),
.C_SLOT_4_HAS_CACHE(1),
.C_SLOT_4_HAS_QOS(1),
.C_SLOT_4_HAS_REGION(1),
.C_SLOT_4_HAS_BURST(1),
.C_SLOT_4_HAS_WSTRB(1),
.C_SLOT_4_HAS_TSTRB(1),
.C_SLOT_4_HAS_TKEEP(1),
.C_SLOT_5_HAS_BRESP(1),
.C_SLOT_5_HAS_RRESP(1),
.C_SLOT_5_HAS_LOCK(1),
.C_SLOT_5_HAS_PROT(1),
.C_SLOT_5_HAS_CACHE(1),
.C_SLOT_5_HAS_QOS(1),
.C_SLOT_5_HAS_REGION(1),
.C_SLOT_5_HAS_BURST(1),
.C_SLOT_5_HAS_WSTRB(1),
.C_SLOT_5_HAS_TSTRB(1),
.C_SLOT_5_HAS_TKEEP(1),
.C_SLOT_6_HAS_BRESP(1),
.C_SLOT_6_HAS_RRESP(1),
.C_SLOT_6_HAS_LOCK(1),
.C_SLOT_6_HAS_PROT(1),
.C_SLOT_6_HAS_CACHE(1),
.C_SLOT_6_HAS_QOS(1),
.C_SLOT_6_HAS_REGION(1),
.C_SLOT_6_HAS_BURST(1),
.C_SLOT_6_HAS_WSTRB(1),
.C_SLOT_6_HAS_TSTRB(1),
.C_SLOT_6_HAS_TKEEP(1),
.C_SLOT_7_HAS_BRESP(1),
.C_SLOT_7_HAS_RRESP(1),
.C_SLOT_7_HAS_LOCK(1),
.C_SLOT_7_HAS_PROT(1),
.C_SLOT_7_HAS_CACHE(1),
.C_SLOT_7_HAS_QOS(1),
.C_SLOT_7_HAS_REGION(1),
.C_SLOT_7_HAS_BURST(1),
.C_SLOT_7_HAS_WSTRB(1),
.C_SLOT_7_HAS_TSTRB(1),
.C_SLOT_7_HAS_TKEEP(1),
.C_SLOT_8_HAS_BRESP(1),
.C_SLOT_8_HAS_RRESP(1),
.C_SLOT_8_HAS_LOCK(1),
.C_SLOT_8_HAS_PROT(1),
.C_SLOT_8_HAS_CACHE(1),
.C_SLOT_8_HAS_QOS(1),
.C_SLOT_8_HAS_REGION(1),
.C_SLOT_8_HAS_BURST(1),
.C_SLOT_8_HAS_WSTRB(1),
.C_SLOT_8_HAS_TSTRB(1),
.C_SLOT_8_HAS_TKEEP(1),
.C_SLOT_9_HAS_BRESP(1),
.C_SLOT_9_HAS_RRESP(1),
.C_SLOT_9_HAS_LOCK(1),
.C_SLOT_9_HAS_PROT(1),
.C_SLOT_9_HAS_CACHE(1),
.C_SLOT_9_HAS_QOS(1),
.C_SLOT_9_HAS_REGION(1),
.C_SLOT_9_HAS_BURST(1),
.C_SLOT_9_HAS_WSTRB(1),
.C_SLOT_9_HAS_TSTRB(1),
.C_SLOT_9_HAS_TKEEP(1),
.C_SLOT_10_HAS_BRESP(1),
.C_SLOT_10_HAS_RRESP(1),
.C_SLOT_10_HAS_LOCK(1),
.C_SLOT_10_HAS_PROT(1),
.C_SLOT_10_HAS_CACHE(1),
.C_SLOT_10_HAS_QOS(1),
.C_SLOT_10_HAS_REGION(1),
.C_SLOT_10_HAS_BURST(1),
.C_SLOT_10_HAS_WSTRB(1),
.C_SLOT_10_HAS_TSTRB(1),
.C_SLOT_10_HAS_TKEEP(1),
.C_SLOT_11_HAS_BRESP(1),
.C_SLOT_11_HAS_RRESP(1),
.C_SLOT_11_HAS_LOCK(1),
.C_SLOT_11_HAS_PROT(1),
.C_SLOT_11_HAS_CACHE(1),
.C_SLOT_11_HAS_QOS(1),
.C_SLOT_11_HAS_REGION(1),
.C_SLOT_11_HAS_BURST(1),
.C_SLOT_11_HAS_WSTRB(1),
.C_SLOT_11_HAS_TSTRB(1),
.C_SLOT_11_HAS_TKEEP(1),
.C_SLOT_12_HAS_BRESP(1),
.C_SLOT_12_HAS_RRESP(1),
.C_SLOT_12_HAS_LOCK(1),
.C_SLOT_12_HAS_PROT(1),
.C_SLOT_12_HAS_CACHE(1),
.C_SLOT_12_HAS_QOS(1),
.C_SLOT_12_HAS_REGION(1),
.C_SLOT_12_HAS_BURST(1),
.C_SLOT_12_HAS_WSTRB(1),
.C_SLOT_12_HAS_TSTRB(1),
.C_SLOT_12_HAS_TKEEP(1),
.C_SLOT_13_HAS_BRESP(1),
.C_SLOT_13_HAS_RRESP(1),
.C_SLOT_13_HAS_LOCK(1),
.C_SLOT_13_HAS_PROT(1),
.C_SLOT_13_HAS_CACHE(1),
.C_SLOT_13_HAS_QOS(1),
.C_SLOT_13_HAS_REGION(1),
.C_SLOT_13_HAS_BURST(1),
.C_SLOT_13_HAS_WSTRB(1),
.C_SLOT_13_HAS_TSTRB(1),
.C_SLOT_13_HAS_TKEEP(1),
.C_SLOT_14_HAS_BRESP(1),
.C_SLOT_14_HAS_RRESP(1),
.C_SLOT_14_HAS_LOCK(1),
.C_SLOT_14_HAS_PROT(1),
.C_SLOT_14_HAS_CACHE(1),
.C_SLOT_14_HAS_QOS(1),
.C_SLOT_14_HAS_REGION(1),
.C_SLOT_14_HAS_BURST(1),
.C_SLOT_14_HAS_WSTRB(1),
.C_SLOT_14_HAS_TSTRB(1),
.C_SLOT_14_HAS_TKEEP(1),
.C_SLOT_15_HAS_BRESP(1),
.C_SLOT_15_HAS_RRESP(1),
.C_SLOT_15_HAS_LOCK(1),
.C_SLOT_15_HAS_PROT(1),
.C_SLOT_15_HAS_CACHE(1),
.C_SLOT_15_HAS_QOS(1),
.C_SLOT_15_HAS_REGION(1),
.C_SLOT_15_HAS_BURST(1),
.C_SLOT_15_HAS_WSTRB(1),
.C_SLOT_15_HAS_TSTRB(1),
.C_SLOT_0_HAS_TREADY(1),
.C_SLOT_1_HAS_TREADY(1),
.C_SLOT_2_HAS_TREADY(1),
.C_SLOT_3_HAS_TREADY(1),
.C_SLOT_4_HAS_TREADY(1),
.C_SLOT_5_HAS_TREADY(1),
.C_SLOT_6_HAS_TREADY(1),
.C_SLOT_7_HAS_TREADY(1),
.C_SLOT_8_HAS_TREADY(1),
.C_SLOT_9_HAS_TREADY(1),
.C_SLOT_10_HAS_TREADY(1),
.C_SLOT_11_HAS_TREADY(1),
.C_SLOT_12_HAS_TREADY(1),
.C_SLOT_13_HAS_TREADY(1),
.C_SLOT_14_HAS_TREADY(1),
.C_SLOT_15_HAS_TREADY(1),
.C_SLOT_15_HAS_TKEEP(1),
.C_MUX_0_AXI_AWUSER_WIDTH(1),
.C_MUX_0_AXI_WUSER_WIDTH(1),
.C_MUX_0_AXI_BUSER_WIDTH(1),
.C_MUX_0_AXI_ARUSER_WIDTH(1),
.C_MUX_0_AXI_RUSER_WIDTH(1),
.C_MUX_1_AXI_AWUSER_WIDTH(1),
.C_MUX_1_AXI_WUSER_WIDTH(1),
.C_MUX_1_AXI_BUSER_WIDTH(1),
.C_MUX_1_AXI_ARUSER_WIDTH(1),
.C_MUX_1_AXI_RUSER_WIDTH(1),
.C_MUX_2_AXI_AWUSER_WIDTH(1),
.C_MUX_2_AXI_WUSER_WIDTH(1),
.C_MUX_2_AXI_BUSER_WIDTH(1),
.C_MUX_2_AXI_ARUSER_WIDTH(1),
.C_MUX_2_AXI_RUSER_WIDTH(1),
.C_MUX_3_AXI_AWUSER_WIDTH(1),
.C_MUX_3_AXI_WUSER_WIDTH(1),
.C_MUX_3_AXI_BUSER_WIDTH(1),
.C_MUX_3_AXI_RUSER_WIDTH(1),
.C_MUX_3_AXI_ARUSER_WIDTH(1),
.C_SLOT_0_AXI_AWUSER_WIDTH(0),
.C_SLOT_0_AXI_WUSER_WIDTH(0),
.C_SLOT_0_AXI_BUSER_WIDTH(0),
.C_SLOT_0_AXI_ARUSER_WIDTH(0),
.C_SLOT_0_AXI_RUSER_WIDTH(0),
.C_SLOT_1_AXI_AWUSER_WIDTH(0),
.C_SLOT_1_AXI_WUSER_WIDTH(0),
.C_SLOT_1_AXI_BUSER_WIDTH(0),
.C_SLOT_1_AXI_ARUSER_WIDTH(0),
.C_SLOT_1_AXI_RUSER_WIDTH(0),
.C_SLOT_2_AXI_AWUSER_WIDTH(1),
.C_SLOT_2_AXI_WUSER_WIDTH(1),
.C_SLOT_2_AXI_BUSER_WIDTH(1),
.C_SLOT_2_AXI_ARUSER_WIDTH(1),
.C_SLOT_2_AXI_RUSER_WIDTH(1),
.C_SLOT_3_AXI_AWUSER_WIDTH(1),
.C_SLOT_3_AXI_WUSER_WIDTH(1),
.C_SLOT_3_AXI_BUSER_WIDTH(1),
.C_SLOT_3_AXI_ARUSER_WIDTH(1),
.C_SLOT_4_AXI_AWUSER_WIDTH(1),
.C_SLOT_4_AXI_WUSER_WIDTH(1),
.C_SLOT_3_AXI_RUSER_WIDTH(1),
.C_SLOT_4_AXI_BUSER_WIDTH(1),
.C_SLOT_4_AXI_ARUSER_WIDTH(1),
.C_SLOT_4_AXI_RUSER_WIDTH(1),
.C_SLOT_5_AXI_AWUSER_WIDTH(1),
.C_SLOT_5_AXI_WUSER_WIDTH(1),
.C_SLOT_5_AXI_BUSER_WIDTH(1),
.C_SLOT_5_AXI_ARUSER_WIDTH(1),
.C_SLOT_5_AXI_RUSER_WIDTH(1),
.C_SLOT_6_AXI_AWUSER_WIDTH(1),
.C_SLOT_6_AXI_WUSER_WIDTH(1),
.C_SLOT_6_AXI_BUSER_WIDTH(1),
.C_SLOT_6_AXI_ARUSER_WIDTH(1),
.C_SLOT_6_AXI_RUSER_WIDTH(1),
.C_SLOT_7_AXI_AWUSER_WIDTH(1),
.C_SLOT_7_AXI_WUSER_WIDTH(1),
.C_SLOT_7_AXI_BUSER_WIDTH(1),
.C_SLOT_7_AXI_ARUSER_WIDTH(1),
.C_SLOT_7_AXI_RUSER_WIDTH(1),
.C_SLOT_8_AXI_AWUSER_WIDTH(1),
.C_SLOT_8_AXI_WUSER_WIDTH(1),
.C_SLOT_8_AXI_BUSER_WIDTH(1),
.C_SLOT_8_AXI_ARUSER_WIDTH(1),
.C_SLOT_8_AXI_RUSER_WIDTH(1),
.C_SLOT_9_AXI_AWUSER_WIDTH(1),
.C_SLOT_9_AXI_WUSER_WIDTH(1),
.C_SLOT_9_AXI_BUSER_WIDTH(1),
.C_SLOT_9_AXI_ARUSER_WIDTH(1),
.C_SLOT_9_AXI_RUSER_WIDTH(1),
.C_SLOT_10_AXI_AWUSER_WIDTH(1),
.C_SLOT_10_AXI_WUSER_WIDTH(1),
.C_SLOT_10_AXI_BUSER_WIDTH(1),
.C_SLOT_10_AXI_ARUSER_WIDTH(1),
.C_SLOT_10_AXI_RUSER_WIDTH(1),
.C_SLOT_11_AXI_AWUSER_WIDTH(1),
.C_SLOT_11_AXI_WUSER_WIDTH(1),
.C_SLOT_11_AXI_BUSER_WIDTH(1),
.C_SLOT_11_AXI_ARUSER_WIDTH(1),
.C_SLOT_11_AXI_RUSER_WIDTH(1),
.C_SLOT_12_AXI_AWUSER_WIDTH(1),
.C_SLOT_12_AXI_WUSER_WIDTH(1),
.C_SLOT_12_AXI_BUSER_WIDTH(1),
.C_SLOT_12_AXI_ARUSER_WIDTH(1),
.C_SLOT_12_AXI_RUSER_WIDTH(1),
.C_SLOT_13_AXI_AWUSER_WIDTH(1),
.C_SLOT_13_AXI_WUSER_WIDTH(1),
.C_SLOT_13_AXI_BUSER_WIDTH(1),
.C_SLOT_13_AXI_ARUSER_WIDTH(1),
.C_SLOT_13_AXI_RUSER_WIDTH(1),
.C_SLOT_14_AXI_AWUSER_WIDTH(1),
.C_SLOT_14_AXI_WUSER_WIDTH(1),
.C_SLOT_14_AXI_BUSER_WIDTH(1),
.C_SLOT_14_AXI_ARUSER_WIDTH(1),
.C_SLOT_14_AXI_RUSER_WIDTH(1),
.C_SLOT_15_AXI_AWUSER_WIDTH(1),
.C_SLOT_15_AXI_WUSER_WIDTH(1),
.C_SLOT_15_AXI_BUSER_WIDTH(1),
.C_SLOT_15_AXI_ARUSER_WIDTH(1),
.C_SLOT_15_AXI_RUSER_WIDTH(1),
.C_EN_GIGAMUX(1'B0),
.C_MUX_LEVEL(1),
.C_AXI_CH_SEL("ALL"),
.C_SYNC_EN(1'B0),
.C_SLOT_0_AXI_CH_SEL("ALL"),
.C_SLOT_1_AXI_CH_SEL("ALL"),
.C_SLOT_2_AXI_CH_SEL("ALL"),
.C_SLOT_3_AXI_CH_SEL("ALL"),
.C_SLOT_4_AXI_CH_SEL("ALL"),
.C_SLOT_5_AXI_CH_SEL("ALL"),
.C_SLOT_6_AXI_CH_SEL("ALL"),
.C_SLOT_7_AXI_CH_SEL("ALL"),
.C_SLOT_8_AXI_CH_SEL("ALL"),
.C_SLOT_9_AXI_CH_SEL("ALL"),
.C_SLOT_10_AXI_CH_SEL("ALL"),
.C_SLOT_11_AXI_CH_SEL("ALL"),
.C_SLOT_12_AXI_CH_SEL("ALL"),
.C_SLOT_13_AXI_CH_SEL("ALL"),
.C_SLOT_14_AXI_CH_SEL("ALL"),
.C_SLOT_15_AXI_CH_SEL("ALL"),
.C_SLOT_0_AXI_AW_SEL("1"),
.C_SLOT_1_AXI_AW_SEL("1"),
.C_SLOT_2_AXI_AW_SEL("1"),
.C_SLOT_3_AXI_AW_SEL("1"),
.C_SLOT_4_AXI_AW_SEL("1"),
.C_SLOT_5_AXI_AW_SEL("1"),
.C_SLOT_6_AXI_AW_SEL("1"),
.C_SLOT_7_AXI_AW_SEL("1"),
.C_SLOT_8_AXI_AW_SEL("1"),
.C_SLOT_9_AXI_AW_SEL("1"),
.C_SLOT_10_AXI_AW_SEL("1"),
.C_SLOT_11_AXI_AW_SEL("1"),
.C_SLOT_12_AXI_AW_SEL("1"),
.C_SLOT_13_AXI_AW_SEL("1"),
.C_SLOT_14_AXI_AW_SEL("1"),
.C_SLOT_15_AXI_AW_SEL("1"),
.C_SLOT_0_AXI_AR_SEL("1"),
.C_SLOT_1_AXI_AR_SEL("1"),
.C_SLOT_2_AXI_AR_SEL("1"),
.C_SLOT_3_AXI_AR_SEL("1"),
.C_SLOT_4_AXI_AR_SEL("1"),
.C_SLOT_5_AXI_AR_SEL("1"),
.C_SLOT_6_AXI_AR_SEL("1"),
.C_SLOT_7_AXI_AR_SEL("1"),
.C_SLOT_8_AXI_AR_SEL("1"),
.C_SLOT_9_AXI_AR_SEL("1"),
.C_SLOT_10_AXI_AR_SEL("1"),
.C_SLOT_11_AXI_AR_SEL("1"),
.C_SLOT_12_AXI_AR_SEL("1"),
.C_SLOT_13_AXI_AR_SEL("1"),
.C_SLOT_14_AXI_AR_SEL("1"),
.C_SLOT_15_AXI_AR_SEL("1"),
.C_SLOT_0_AXI_W_SEL("1"),
.C_SLOT_1_AXI_W_SEL("1"),
.C_SLOT_2_AXI_W_SEL("1"),
.C_SLOT_3_AXI_W_SEL("1"),
.C_SLOT_4_AXI_W_SEL("1"),
.C_SLOT_5_AXI_W_SEL("1"),
.C_SLOT_6_AXI_W_SEL("1"),
.C_SLOT_7_AXI_W_SEL("1"),
.C_SLOT_8_AXI_W_SEL("1"),
.C_SLOT_9_AXI_W_SEL("1"),
.C_SLOT_10_AXI_W_SEL("1"),
.C_SLOT_11_AXI_W_SEL("1"),
.C_SLOT_12_AXI_W_SEL("1"),
.C_SLOT_13_AXI_W_SEL("1"),
.C_SLOT_14_AXI_W_SEL("1"),
.C_SLOT_15_AXI_W_SEL("1"),
.C_SLOT_0_AXI_R_SEL("1"),
.C_SLOT_1_AXI_R_SEL("1"),
.C_SLOT_2_AXI_R_SEL("1"),
.C_SLOT_3_AXI_R_SEL("1"),
.C_SLOT_4_AXI_R_SEL("1"),
.C_SLOT_5_AXI_R_SEL("1"),
.C_SLOT_6_AXI_R_SEL("1"),
.C_SLOT_7_AXI_R_SEL("1"),
.C_SLOT_8_AXI_R_SEL("1"),
.C_SLOT_9_AXI_R_SEL("1"),
.C_SLOT_10_AXI_R_SEL("1"),
.C_SLOT_11_AXI_R_SEL("1"),
.C_SLOT_12_AXI_R_SEL("1"),
.C_SLOT_13_AXI_R_SEL("1"),
.C_SLOT_14_AXI_R_SEL("1"),
.C_SLOT_15_AXI_R_SEL("1"),
.C_SLOT_0_AXI_B_SEL("1"),
.C_SLOT_1_AXI_B_SEL("1"),
.C_SLOT_2_AXI_B_SEL("1"),
.C_SLOT_3_AXI_B_SEL("1"),
.C_SLOT_4_AXI_B_SEL("1"),
.C_SLOT_5_AXI_B_SEL("1"),
.C_SLOT_6_AXI_B_SEL("1"),
.C_SLOT_7_AXI_B_SEL("1"),
.C_SLOT_8_AXI_B_SEL("1"),
.C_SLOT_9_AXI_B_SEL("1"),
.C_SLOT_10_AXI_B_SEL("1"),
.C_SLOT_11_AXI_B_SEL("1"),
.C_SLOT_12_AXI_B_SEL("1"),
.C_SLOT_13_AXI_B_SEL("1"),
.C_SLOT_14_AXI_B_SEL("1"),
.C_SLOT_15_AXI_B_SEL("1"),
.C_SLOT_0_MON_MODE("FT"),
.C_SLOT_1_MON_MODE("FT"),
.C_SLOT_2_MON_MODE("RT"),
.C_SLOT_3_MON_MODE("RT"),
.C_SLOT_4_MON_MODE("RT"),
.C_SLOT_5_MON_MODE("RT"),
.C_SLOT_6_MON_MODE("RT"),
.C_SLOT_7_MON_MODE("RT"),
.C_SLOT_8_MON_MODE("RT"),
.C_SLOT_9_MON_MODE("RT"),
.C_SLOT_10_MON_MODE("RT"),
.C_SLOT_11_MON_MODE("RT"),
.C_SLOT_12_MON_MODE("RT"),
.C_SLOT_13_MON_MODE("RT"),
.C_SLOT_14_MON_MODE("RT"),
.C_SLOT_15_MON_MODE("RT"),
.C_SLOT_0_AXI_AXLEN_WIDTH(8),
.C_SLOT_0_AXI_AXLOCK_WIDTH(1),
.C_SLOT_1_AXI_AXLEN_WIDTH(8),
.C_SLOT_1_AXI_AXLOCK_WIDTH(1),
.C_SLOT_2_AXI_AXLEN_WIDTH(8),
.C_SLOT_2_AXI_AXLOCK_WIDTH(1),
.C_SLOT_3_AXI_AXLEN_WIDTH(8),
.C_SLOT_3_AXI_AXLOCK_WIDTH(1),
.C_SLOT_4_AXI_AXLEN_WIDTH(8),
.C_SLOT_4_AXI_AXLOCK_WIDTH(1),
.C_SLOT_5_AXI_AXLEN_WIDTH(8),
.C_SLOT_5_AXI_AXLOCK_WIDTH(1),
.C_SLOT_6_AXI_AXLEN_WIDTH(8),
.C_SLOT_6_AXI_AXLOCK_WIDTH(1),
.C_SLOT_7_AXI_AXLEN_WIDTH(8),
.C_SLOT_7_AXI_AXLOCK_WIDTH(1),
.C_SLOT_8_AXI_AXLEN_WIDTH(8),
.C_SLOT_8_AXI_AXLOCK_WIDTH(1),
.C_SLOT_9_AXI_AXLEN_WIDTH(8),
.C_SLOT_9_AXI_AXLOCK_WIDTH(1),
.C_SLOT_10_AXI_AXLEN_WIDTH(8),
.C_SLOT_10_AXI_AXLOCK_WIDTH(1),
.C_SLOT_11_AXI_AXLEN_WIDTH(8),
.C_SLOT_11_AXI_AXLOCK_WIDTH(1),
.C_SLOT_12_AXI_AXLEN_WIDTH(8),
.C_SLOT_12_AXI_AXLOCK_WIDTH(1),
.C_SLOT_13_AXI_AXLEN_WIDTH(8),
.C_SLOT_13_AXI_AXLOCK_WIDTH(1),
.C_SLOT_14_AXI_AXLEN_WIDTH(8),
.C_SLOT_14_AXI_AXLOCK_WIDTH(1),
.C_SLOT_15_AXI_AXLEN_WIDTH(8),
.C_SLOT_15_AXI_AXLOCK_WIDTH(1),
.C_MUX_0_AXI_AXLEN_WIDTH(8),
.C_MUX_0_AXI_AXLOCK_WIDTH(1),
.C_MUX_1_AXI_AXLEN_WIDTH(8),
.C_MUX_1_AXI_AXLOCK_WIDTH(1),
.C_MUX_2_AXI_AXLEN_WIDTH(8),
.C_MUX_2_AXI_AXLOCK_WIDTH(1),
.C_MUX_3_AXI_AXLEN_WIDTH(8),
.C_MUX_3_AXI_AXLOCK_WIDTH(1),
.C_MUX_0_AXI_ID_WIDTH(4),
.C_MUX_0_AXI_ADDR_WIDTH(32),
.C_MUX_0_AXI_DATA_WIDTH(32),
.C_MUX_0_AXI_PROTOCOL("AXI4"),
.C_MUX_0_AXIS_TDATA_WIDTH(32),
.C_MUX_0_AXIS_TID_WIDTH(1),
.C_MUX_0_AXIS_TDEST_WIDTH(1),
.C_MUX_0_AXIS_TUSER_WIDTH(1),
.C_MUX_1_AXI_ID_WIDTH(4),
.C_MUX_1_AXI_ADDR_WIDTH(32),
.C_MUX_1_AXI_DATA_WIDTH(32),
.C_MUX_1_AXI_PROTOCOL("AXI4"),
.C_MUX_1_AXIS_TDATA_WIDTH(32),
.C_MUX_1_AXIS_TID_WIDTH(1),
.C_MUX_1_AXIS_TDEST_WIDTH(1),
.C_MUX_1_AXIS_TUSER_WIDTH(1),
.C_MUX_2_AXI_ID_WIDTH(4),
.C_MUX_2_AXI_ADDR_WIDTH(32),
.C_MUX_2_AXI_DATA_WIDTH(32),
.C_MUX_2_AXI_PROTOCOL("AXI4"),
.C_MUX_2_AXIS_TDATA_WIDTH(32),
.C_MUX_2_AXIS_TID_WIDTH(1),
.C_MUX_2_AXIS_TDEST_WIDTH(1),
.C_MUX_2_AXIS_TUSER_WIDTH(1),
.C_MUX_3_AXI_ID_WIDTH(4),
.C_MUX_3_AXI_ADDR_WIDTH(32),
.C_MUX_3_AXI_DATA_WIDTH(32),
.C_MUX_3_AXI_PROTOCOL("AXI4"),
.C_MUX_3_AXIS_TDATA_WIDTH(32),
.C_MUX_3_AXIS_TID_WIDTH(1),
.C_MUX_3_AXIS_TDEST_WIDTH(1),
.C_MUX_3_AXIS_TUSER_WIDTH(1),
.C_NUM_OF_PROBES(0),
.C_PROBE0_WIDTH(1),
.C_PROBE1_WIDTH(1),
.C_PROBE2_WIDTH(1),
.C_PROBE3_WIDTH(1),
.C_PROBE4_WIDTH(1),
.C_PROBE5_WIDTH(1),
.C_PROBE6_WIDTH(1),
.C_PROBE7_WIDTH(1),
.C_PROBE8_WIDTH(1),
.C_PROBE9_WIDTH(1),
.C_PROBE10_WIDTH(1),
.C_PROBE11_WIDTH(1),
.C_PROBE12_WIDTH(1),
.C_PROBE13_WIDTH(1),
.C_PROBE14_WIDTH(1),
.C_PROBE15_WIDTH(1),
.C_PROBE16_WIDTH(1),
.C_PROBE17_WIDTH(1),
.C_PROBE18_WIDTH(1),
.C_PROBE19_WIDTH(1),
.C_PROBE20_WIDTH(1),
.C_PROBE21_WIDTH(1),
.C_PROBE22_WIDTH(1),
.C_PROBE23_WIDTH(1),
.C_PROBE24_WIDTH(1),
.C_PROBE25_WIDTH(1),
.C_PROBE26_WIDTH(1),
.C_PROBE27_WIDTH(1),
.C_PROBE28_WIDTH(1),
.C_PROBE29_WIDTH(1),
.C_PROBE30_WIDTH(1),
.C_PROBE31_WIDTH(1),
.C_PROBE32_WIDTH(1),
.C_PROBE33_WIDTH(1),
.C_PROBE34_WIDTH(1),
.C_PROBE35_WIDTH(1),
.C_PROBE36_WIDTH(1),
.C_PROBE37_WIDTH(1),
.C_PROBE38_WIDTH(1),
.C_PROBE39_WIDTH(1),
.C_PROBE40_WIDTH(1),
.C_PROBE41_WIDTH(1),
.C_PROBE42_WIDTH(1),
.C_PROBE43_WIDTH(1),
.C_PROBE44_WIDTH(1),
.C_PROBE45_WIDTH(1),
.C_PROBE46_WIDTH(1),
.C_PROBE47_WIDTH(1),
.C_PROBE48_WIDTH(1),
.C_PROBE49_WIDTH(1),
.C_PROBE50_WIDTH(1),
.C_PROBE51_WIDTH(1),
.C_PROBE52_WIDTH(1),
.C_PROBE53_WIDTH(1),
.C_PROBE54_WIDTH(1),
.C_PROBE55_WIDTH(1),
.C_PROBE56_WIDTH(1),
.C_PROBE57_WIDTH(1),
.C_PROBE58_WIDTH(1),
.C_PROBE59_WIDTH(1),
.C_PROBE60_WIDTH(1),
.C_PROBE61_WIDTH(1),
.C_PROBE62_WIDTH(1),
.C_PROBE63_WIDTH(1),
.C_PROBE64_WIDTH(1),
.C_PROBE65_WIDTH(1),
.C_PROBE66_WIDTH(1),
.C_PROBE67_WIDTH(1),
.C_PROBE68_WIDTH(1),
.C_PROBE69_WIDTH(1),
.C_PROBE70_WIDTH(1),
.C_PROBE71_WIDTH(1),
.C_PROBE72_WIDTH(1),
.C_PROBE73_WIDTH(1),
.C_PROBE74_WIDTH(1),
.C_PROBE75_WIDTH(1),
.C_PROBE76_WIDTH(1),
.C_PROBE77_WIDTH(1),
.C_PROBE78_WIDTH(1),
.C_PROBE79_WIDTH(1),
.C_PROBE80_WIDTH(1),
.C_PROBE81_WIDTH(1),
.C_PROBE82_WIDTH(1),
.C_PROBE83_WIDTH(1),
.C_PROBE84_WIDTH(1),
.C_PROBE85_WIDTH(1),
.C_PROBE86_WIDTH(1),
.C_PROBE87_WIDTH(1),
.C_PROBE88_WIDTH(1),
.C_PROBE89_WIDTH(1),
.C_PROBE90_WIDTH(1),
.C_PROBE91_WIDTH(1),
.C_PROBE92_WIDTH(1),
.C_PROBE93_WIDTH(1),
.C_PROBE94_WIDTH(1),
.C_PROBE95_WIDTH(1),
.C_PROBE96_WIDTH(1),
.C_PROBE97_WIDTH(1),
.C_PROBE98_WIDTH(1),
.C_PROBE99_WIDTH(1),
.C_PROBE100_WIDTH(1),
.C_PROBE101_WIDTH(1),
.C_PROBE102_WIDTH(1),
.C_PROBE103_WIDTH(1),
.C_PROBE104_WIDTH(1),
.C_PROBE105_WIDTH(1),
.C_PROBE106_WIDTH(1),
.C_PROBE107_WIDTH(1),
.C_PROBE108_WIDTH(1),
.C_PROBE109_WIDTH(1),
.C_PROBE110_WIDTH(1),
.C_PROBE111_WIDTH(1),
.C_PROBE112_WIDTH(1),
.C_PROBE113_WIDTH(1),
.C_PROBE114_WIDTH(1),
.C_PROBE115_WIDTH(1),
.C_PROBE116_WIDTH(1),
.C_PROBE117_WIDTH(1),
.C_PROBE118_WIDTH(1),
.C_PROBE119_WIDTH(1),
.C_PROBE120_WIDTH(1),
.C_PROBE121_WIDTH(1),
.C_PROBE122_WIDTH(1),
.C_PROBE123_WIDTH(1),
.C_PROBE124_WIDTH(1),
.C_PROBE125_WIDTH(1),
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.C_MUX_PROBE125_WIDTH(1),
.C_MUX_PROBE126_WIDTH(1),
.C_MUX_PROBE127_WIDTH(1),
.C_SLOT_0_AXI_ADDR_WIDTH(9),
.C_SLOT_0_AXI_DATA_WIDTH(32),
.C_SLOT_0_AXI_ID_WIDTH(0),
.C_SLOT_0_AXI_PROTOCOL("AXI4LITE"),
.C_SLOT_0_AXIS_TDATA_WIDTH(32),
.C_SLOT_0_AXIS_TID_WIDTH(1),
.C_SLOT_0_AXIS_TDEST_WIDTH(1),
.C_SLOT_0_AXIS_TUSER_WIDTH(1),
.C_SLOT_1_AXI_ADDR_WIDTH(16),
.C_SLOT_1_AXI_DATA_WIDTH(32),
.C_SLOT_1_AXI_ID_WIDTH(12),
.C_SLOT_1_AXI_PROTOCOL("AXI4"),
.C_SLOT_1_AXIS_TDATA_WIDTH(32),
.C_SLOT_1_AXIS_TID_WIDTH(1),
.C_SLOT_1_AXIS_TDEST_WIDTH(1),
.C_SLOT_1_AXIS_TUSER_WIDTH(1),
.C_SLOT_2_AXI_ADDR_WIDTH(32),
.C_SLOT_2_AXI_DATA_WIDTH(32),
.C_SLOT_2_AXI_ID_WIDTH(1),
.C_SLOT_2_AXI_PROTOCOL("AXI4"),
.C_SLOT_2_AXIS_TDATA_WIDTH(32),
.C_SLOT_2_AXIS_TID_WIDTH(1),
.C_SLOT_2_AXIS_TDEST_WIDTH(1),
.C_SLOT_2_AXIS_TUSER_WIDTH(1),
.C_SLOT_3_AXI_ADDR_WIDTH(32),
.C_SLOT_3_AXI_DATA_WIDTH(32),
.C_SLOT_3_AXI_ID_WIDTH(1),
.C_SLOT_3_AXI_PROTOCOL("AXI4"),
.C_SLOT_3_AXIS_TDATA_WIDTH(32),
.C_SLOT_3_AXIS_TID_WIDTH(1),
.C_SLOT_3_AXIS_TDEST_WIDTH(1),
.C_SLOT_3_AXIS_TUSER_WIDTH(1),
.C_SLOT_4_AXI_ADDR_WIDTH(32),
.C_SLOT_4_AXI_DATA_WIDTH(32),
.C_SLOT_4_AXI_ID_WIDTH(1),
.C_SLOT_4_AXI_PROTOCOL("AXI4"),
.C_SLOT_4_AXIS_TDATA_WIDTH(32),
.C_SLOT_4_AXIS_TID_WIDTH(1),
.C_SLOT_4_AXIS_TDEST_WIDTH(1),
.C_SLOT_4_AXIS_TUSER_WIDTH(1),
.C_SLOT_5_AXI_ADDR_WIDTH(32),
.C_SLOT_5_AXI_DATA_WIDTH(32),
.C_SLOT_5_AXI_ID_WIDTH(1),
.C_SLOT_5_AXI_PROTOCOL("AXI4"),
.C_SLOT_5_AXIS_TDATA_WIDTH(32),
.C_SLOT_5_AXIS_TID_WIDTH(1),
.C_SLOT_5_AXIS_TDEST_WIDTH(1),
.C_SLOT_5_AXIS_TUSER_WIDTH(1),
.C_SLOT_6_AXI_ADDR_WIDTH(32),
.C_SLOT_6_AXI_DATA_WIDTH(32),
.C_SLOT_6_AXI_ID_WIDTH(1),
.C_SLOT_6_AXI_PROTOCOL("AXI4"),
.C_SLOT_6_AXIS_TDATA_WIDTH(32),
.C_SLOT_6_AXIS_TID_WIDTH(1),
.C_SLOT_6_AXIS_TDEST_WIDTH(1),
.C_SLOT_6_AXIS_TUSER_WIDTH(1),
.C_SLOT_7_AXI_ADDR_WIDTH(32),
.C_SLOT_7_AXI_DATA_WIDTH(32),
.C_SLOT_7_AXI_ID_WIDTH(1),
.C_SLOT_7_AXI_PROTOCOL("AXI4"),
.C_SLOT_7_AXIS_TDATA_WIDTH(32),
.C_SLOT_7_AXIS_TID_WIDTH(1),
.C_SLOT_7_AXIS_TDEST_WIDTH(1),
.C_SLOT_7_AXIS_TUSER_WIDTH(1),
.C_SLOT_8_AXI_ADDR_WIDTH(32),
.C_SLOT_8_AXI_DATA_WIDTH(32),
.C_SLOT_8_AXI_ID_WIDTH(1),
.C_SLOT_8_AXI_PROTOCOL("AXI4"),
.C_SLOT_8_AXIS_TDATA_WIDTH(32),
.C_SLOT_8_AXIS_TID_WIDTH(1),
.C_SLOT_8_AXIS_TDEST_WIDTH(1),
.C_SLOT_8_AXIS_TUSER_WIDTH(1),
.C_SLOT_9_AXI_ADDR_WIDTH(32),
.C_SLOT_9_AXI_DATA_WIDTH(32),
.C_SLOT_9_AXI_ID_WIDTH(1),
.C_SLOT_9_AXI_PROTOCOL("AXI4"),
.C_SLOT_9_AXIS_TDATA_WIDTH(32),
.C_SLOT_9_AXIS_TID_WIDTH(1),
.C_SLOT_9_AXIS_TDEST_WIDTH(1),
.C_SLOT_9_AXIS_TUSER_WIDTH(1),
.C_SLOT_10_AXI_ADDR_WIDTH(32),
.C_SLOT_10_AXI_DATA_WIDTH(32),
.C_SLOT_10_AXI_ID_WIDTH(1),
.C_SLOT_10_AXI_PROTOCOL("AXI4"),
.C_SLOT_10_AXIS_TDATA_WIDTH(32),
.C_SLOT_10_AXIS_TID_WIDTH(1),
.C_SLOT_10_AXIS_TDEST_WIDTH(1),
.C_SLOT_10_AXIS_TUSER_WIDTH(1),
.C_SLOT_11_AXI_ADDR_WIDTH(32),
.C_SLOT_11_AXI_DATA_WIDTH(32),
.C_SLOT_11_AXI_ID_WIDTH(1),
.C_SLOT_11_AXI_PROTOCOL("AXI4"),
.C_SLOT_11_AXIS_TDATA_WIDTH(32),
.C_SLOT_11_AXIS_TID_WIDTH(1),
.C_SLOT_11_AXIS_TDEST_WIDTH(1),
.C_SLOT_11_AXIS_TUSER_WIDTH(1),
.C_SLOT_12_AXI_ADDR_WIDTH(32),
.C_SLOT_12_AXI_DATA_WIDTH(32),
.C_SLOT_12_AXI_ID_WIDTH(1),
.C_SLOT_12_AXI_PROTOCOL("AXI4"),
.C_SLOT_12_AXIS_TDATA_WIDTH(32),
.C_SLOT_12_AXIS_TID_WIDTH(1),
.C_SLOT_12_AXIS_TDEST_WIDTH(1),
.C_SLOT_12_AXIS_TUSER_WIDTH(1),
.C_SLOT_13_AXI_ADDR_WIDTH(32),
.C_SLOT_13_AXI_DATA_WIDTH(32),
.C_SLOT_13_AXI_ID_WIDTH(1),
.C_SLOT_13_AXI_PROTOCOL("AXI4"),
.C_SLOT_13_AXIS_TDATA_WIDTH(32),
.C_SLOT_13_AXIS_TID_WIDTH(1),
.C_SLOT_13_AXIS_TDEST_WIDTH(1),
.C_SLOT_13_AXIS_TUSER_WIDTH(1),
.C_SLOT_14_AXI_ADDR_WIDTH(32),
.C_SLOT_14_AXI_DATA_WIDTH(32),
.C_SLOT_14_AXI_ID_WIDTH(1),
.C_SLOT_14_AXI_PROTOCOL("AXI4"),
.C_SLOT_14_AXIS_TDATA_WIDTH(32),
.C_SLOT_14_AXIS_TID_WIDTH(1),
.C_SLOT_14_AXIS_TDEST_WIDTH(1),
.C_SLOT_14_AXIS_TUSER_WIDTH(1),
.C_SLOT_15_AXI_ADDR_WIDTH(32),
.C_SLOT_15_AXI_DATA_WIDTH(32),
.C_SLOT_15_AXI_ID_WIDTH(1),
.C_SLOT_15_AXI_PROTOCOL("AXI4"),
.C_SLOT_15_AXIS_TDATA_WIDTH(32),
.C_SLOT_15_AXIS_TID_WIDTH(1),
.C_SLOT_15_AXIS_TDEST_WIDTH(1),
.C_SLOT_15_AXIS_TUSER_WIDTH(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.probe0(1'B0),
.probe1(1'B0),
.probe2(1'B0),
.probe3(1'B0),
.probe4(1'B0),
.probe5(1'B0),
.probe6(1'B0),
.probe7(1'B0),
.probe8(1'B0),
.probe9(1'B0),
.probe10(1'B0),
.probe11(1'B0),
.probe12(1'B0),
.probe13(1'B0),
.probe14(1'B0),
.probe15(1'B0),
.probe16(1'B0),
.probe17(1'B0),
.probe18(1'B0),
.probe19(1'B0),
.probe20(1'B0),
.probe21(1'B0),
.probe22(1'B0),
.probe23(1'B0),
.probe24(1'B0),
.probe25(1'B0),
.probe26(1'B0),
.probe27(1'B0),
.probe28(1'B0),
.probe29(1'B0),
.probe30(1'B0),
.probe31(1'B0),
.probe32(1'B0),
.probe33(1'B0),
.probe34(1'B0),
.probe35(1'B0),
.probe36(1'B0),
.probe37(1'B0),
.probe38(1'B0),
.probe39(1'B0),
.probe40(1'B0),
.probe41(1'B0),
.probe42(1'B0),
.probe43(1'B0),
.probe44(1'B0),
.probe45(1'B0),
.probe46(1'B0),
.probe47(1'B0),
.probe48(1'B0),
.probe49(1'B0),
.probe50(1'B0),
.probe51(1'B0),
.probe52(1'B0),
.probe53(1'B0),
.probe54(1'B0),
.probe55(1'B0),
.probe56(1'B0),
.probe57(1'B0),
.probe58(1'B0),
.probe59(1'B0),
.probe60(1'B0),
.probe61(1'B0),
.probe62(1'B0),
.probe63(1'B0),
.probe64(1'B0),
.probe65(1'B0),
.probe66(1'B0),
.probe67(1'B0),
.probe68(1'B0),
.probe69(1'B0),
.probe70(1'B0),
.probe71(1'B0),
.probe72(1'B0),
.probe73(1'B0),
.probe74(1'B0),
.probe75(1'B0),
.probe76(1'B0),
.probe77(1'B0),
.probe78(1'B0),
.probe79(1'B0),
.probe80(1'B0),
.probe81(1'B0),
.probe82(1'B0),
.probe83(1'B0),
.probe84(1'B0),
.probe85(1'B0),
.probe86(1'B0),
.probe87(1'B0),
.probe88(1'B0),
.probe89(1'B0),
.probe90(1'B0),
.probe91(1'B0),
.probe92(1'B0),
.probe93(1'B0),
.probe94(1'B0),
.probe95(1'B0),
.probe96(1'B0),
.probe97(1'B0),
.probe98(1'B0),
.probe99(1'B0),
.probe100(1'B0),
.probe101(1'B0),
.probe102(1'B0),
.probe103(1'B0),
.probe104(1'B0),
.probe105(1'B0),
.probe106(1'B0),
.probe107(1'B0),
.probe108(1'B0),
.probe109(1'B0),
.probe110(1'B0),
.probe111(1'B0),
.probe112(1'B0),
.probe113(1'B0),
.probe114(1'B0),
.probe115(1'B0),
.probe116(1'B0),
.probe117(1'B0),
.probe118(1'B0),
.probe119(1'B0),
.probe120(1'B0),
.probe121(1'B0),
.probe122(1'B0),
.probe123(1'B0),
.probe124(1'B0),
.probe125(1'B0),
.probe126(1'B0),
.probe127(1'B0),
.probe128(1'B0),
.probe129(1'B0),
.probe130(1'B0),
.probe131(1'B0),
.probe132(1'B0),
.probe133(1'B0),
.probe134(1'B0),
.probe135(1'B0),
.probe136(1'B0),
.probe137(1'B0),
.probe138(1'B0),
.probe139(1'B0),
.probe140(1'B0),
.probe141(1'B0),
.probe142(1'B0),
.probe143(1'B0),
.probe144(1'B0),
.probe145(1'B0),
.probe146(1'B0),
.probe147(1'B0),
.probe148(1'B0),
.probe149(1'B0),
.probe150(1'B0),
.probe151(1'B0),
.probe152(1'B0),
.probe153(1'B0),
.probe154(1'B0),
.probe155(1'B0),
.probe156(1'B0),
.probe157(1'B0),
.probe158(1'B0),
.probe159(1'B0),
.probe160(1'B0),
.probe161(1'B0),
.probe162(1'B0),
.probe163(1'B0),
.probe164(1'B0),
.probe165(1'B0),
.probe166(1'B0),
.probe167(1'B0),
.probe168(1'B0),
.probe169(1'B0),
.probe170(1'B0),
.probe171(1'B0),
.probe172(1'B0),
.probe173(1'B0),
.probe174(1'B0),
.probe175(1'B0),
.probe176(1'B0),
.probe177(1'B0),
.probe178(1'B0),
.probe179(1'B0),
.probe180(1'B0),
.probe181(1'B0),
.probe182(1'B0),
.probe183(1'B0),
.probe184(1'B0),
.probe185(1'B0),
.probe186(1'B0),
.probe187(1'B0),
.probe188(1'B0),
.probe189(1'B0),
.probe190(1'B0),
.probe191(1'B0),
.probe192(1'B0),
.probe193(1'B0),
.probe194(1'B0),
.probe195(1'B0),
.probe196(1'B0),
.probe197(1'B0),
.probe198(1'B0),
.probe199(1'B0),
.probe200(1'B0),
.probe201(1'B0),
.probe202(1'B0),
.probe203(1'B0),
.probe204(1'B0),
.probe205(1'B0),
.probe206(1'B0),
.probe207(1'B0),
.probe208(1'B0),
.probe209(1'B0),
.probe210(1'B0),
.probe211(1'B0),
.probe212(1'B0),
.probe213(1'B0),
.probe214(1'B0),
.probe215(1'B0),
.probe216(1'B0),
.probe217(1'B0),
.probe218(1'B0),
.probe219(1'B0),
.probe220(1'B0),
.probe221(1'B0),
.probe222(1'B0),
.probe223(1'B0),
.probe224(1'B0),
.probe225(1'B0),
.probe226(1'B0),
.probe227(1'B0),
.probe228(1'B0),
.probe229(1'B0),
.probe230(1'B0),
.probe231(1'B0),
.probe232(1'B0),
.probe233(1'B0),
.probe234(1'B0),
.probe235(1'B0),
.probe236(1'B0),
.probe237(1'B0),
.probe238(1'B0),
.probe239(1'B0),
.probe240(1'B0),
.probe241(1'B0),
.probe242(1'B0),
.probe243(1'B0),
.probe244(1'B0),
.probe245(1'B0),
.probe246(1'B0),
.probe247(1'B0),
.probe248(1'B0),
.probe249(1'B0),
.probe250(1'B0),
.probe251(1'B0),
.probe252(1'B0),
.probe253(1'B0),
.probe254(1'B0),
.probe255(1'B0),
.probe256(1'B0),
.probe257(1'B0),
.probe258(1'B0),
.probe259(1'B0),
.probe260(1'B0),
.probe261(1'B0),
.probe262(1'B0),
.probe263(1'B0),
.probe264(1'B0),
.probe265(1'B0),
.probe266(1'B0),
.probe267(1'B0),
.probe268(1'B0),
.probe269(1'B0),
.probe270(1'B0),
.probe271(1'B0),
.probe272(1'B0),
.probe273(1'B0),
.probe274(1'B0),
.probe275(1'B0),
.probe276(1'B0),
.probe277(1'B0),
.probe278(1'B0),
.probe279(1'B0),
.probe280(1'B0),
.probe281(1'B0),
.probe282(1'B0),
.probe283(1'B0),
.probe284(1'B0),
.probe285(1'B0),
.probe286(1'B0),
.probe287(1'B0),
.probe288(1'B0),
.probe289(1'B0),
.probe290(1'B0),
.probe291(1'B0),
.probe292(1'B0),
.probe293(1'B0),
.probe294(1'B0),
.probe295(1'B0),
.probe296(1'B0),
.probe297(1'B0),
.probe298(1'B0),
.probe299(1'B0),
.probe300(1'B0),
.probe301(1'B0),
.probe302(1'B0),
.probe303(1'B0),
.probe304(1'B0),
.probe305(1'B0),
.probe306(1'B0),
.probe307(1'B0),
.probe308(1'B0),
.probe309(1'B0),
.probe310(1'B0),
.probe311(1'B0),
.probe312(1'B0),
.probe313(1'B0),
.probe314(1'B0),
.probe315(1'B0),
.probe316(1'B0),
.probe317(1'B0),
.probe318(1'B0),
.probe319(1'B0),
.probe320(1'B0),
.probe321(1'B0),
.probe322(1'B0),
.probe323(1'B0),
.probe324(1'B0),
.probe325(1'B0),
.probe326(1'B0),
.probe327(1'B0),
.probe328(1'B0),
.probe329(1'B0),
.probe330(1'B0),
.probe331(1'B0),
.probe332(1'B0),
.probe333(1'B0),
.probe334(1'B0),
.probe335(1'B0),
.probe336(1'B0),
.probe337(1'B0),
.probe338(1'B0),
.probe339(1'B0),
.probe340(1'B0),
.probe341(1'B0),
.probe342(1'B0),
.probe343(1'B0),
.probe344(1'B0),
.probe345(1'B0),
.probe346(1'B0),
.probe347(1'B0),
.probe348(1'B0),
.probe349(1'B0),
.probe350(1'B0),
.probe351(1'B0),
.probe352(1'B0),
.probe353(1'B0),
.probe354(1'B0),
.probe355(1'B0),
.probe356(1'B0),
.probe357(1'B0),
.probe358(1'B0),
.probe359(1'B0),
.probe360(1'B0),
.probe361(1'B0),
.probe362(1'B0),
.probe363(1'B0),
.probe364(1'B0),
.probe365(1'B0),
.probe366(1'B0),
.probe367(1'B0),
.probe368(1'B0),
.probe369(1'B0),
.probe370(1'B0),
.probe371(1'B0),
.probe372(1'B0),
.probe373(1'B0),
.probe374(1'B0),
.probe375(1'B0),
.probe376(1'B0),
.probe377(1'B0),
.probe378(1'B0),
.probe379(1'B0),
.probe380(1'B0),
.probe381(1'B0),
.probe382(1'B0),
.probe383(1'B0),
.probe384(1'B0),
.probe385(1'B0),
.probe386(1'B0),
.probe387(1'B0),
.probe388(1'B0),
.probe389(1'B0),
.probe390(1'B0),
.probe391(1'B0),
.probe392(1'B0),
.probe393(1'B0),
.probe394(1'B0),
.probe395(1'B0),
.probe396(1'B0),
.probe397(1'B0),
.probe398(1'B0),
.probe399(1'B0),
.probe400(1'B0),
.probe401(1'B0),
.probe402(1'B0),
.probe403(1'B0),
.probe404(1'B0),
.probe405(1'B0),
.probe406(1'B0),
.probe407(1'B0),
.probe408(1'B0),
.probe409(1'B0),
.probe410(1'B0),
.probe411(1'B0),
.probe412(1'B0),
.probe413(1'B0),
.probe414(1'B0),
.probe415(1'B0),
.probe416(1'B0),
.probe417(1'B0),
.probe418(1'B0),
.probe419(1'B0),
.probe420(1'B0),
.probe421(1'B0),
.probe422(1'B0),
.probe423(1'B0),
.probe424(1'B0),
.probe425(1'B0),
.probe426(1'B0),
.probe427(1'B0),
.probe428(1'B0),
.probe429(1'B0),
.probe430(1'B0),
.probe431(1'B0),
.probe432(1'B0),
.probe433(1'B0),
.probe434(1'B0),
.probe435(1'B0),
.probe436(1'B0),
.probe437(1'B0),
.probe438(1'B0),
.probe439(1'B0),
.probe440(1'B0),
.probe441(1'B0),
.probe442(1'B0),
.probe443(1'B0),
.probe444(1'B0),
.probe445(1'B0),
.probe446(1'B0),
.probe447(1'B0),
.probe448(1'B0),
.probe449(1'B0),
.probe450(1'B0),
.probe451(1'B0),
.probe452(1'B0),
.probe453(1'B0),
.probe454(1'B0),
.probe455(1'B0),
.probe456(1'B0),
.probe457(1'B0),
.probe458(1'B0),
.probe459(1'B0),
.probe460(1'B0),
.probe461(1'B0),
.probe462(1'B0),
.probe463(1'B0),
.probe464(1'B0),
.probe465(1'B0),
.probe466(1'B0),
.probe467(1'B0),
.probe468(1'B0),
.probe469(1'B0),
.probe470(1'B0),
.probe471(1'B0),
.probe472(1'B0),
.probe473(1'B0),
.probe474(1'B0),
.probe475(1'B0),
.probe476(1'B0),
.probe477(1'B0),
.probe478(1'B0),
.probe479(1'B0),
.probe480(1'B0),
.probe481(1'B0),
.probe482(1'B0),
.probe483(1'B0),
.probe484(1'B0),
.probe485(1'B0),
.probe486(1'B0),
.probe487(1'B0),
.probe488(1'B0),
.probe489(1'B0),
.probe490(1'B0),
.probe491(1'B0),
.probe492(1'B0),
.probe493(1'B0),
.probe494(1'B0),
.probe495(1'B0),
.probe496(1'B0),
.probe497(1'B0),
.probe498(1'B0),
.probe499(1'B0),
.probe500(1'B0),
.probe501(1'B0),
.probe502(1'B0),
.probe503(1'B0),
.probe504(1'B0),
.probe505(1'B0),
.probe506(1'B0),
.probe507(1'B0),
.probe508(1'B0),
.probe509(1'B0),
.probe510(1'B0),
.probe511(1'B0),
.probe_out0(),
.probe_out1(),
.probe_out2(),
.probe_out3(),
.probe_out4(),
.probe_out5(),
.probe_out6(),
.probe_out7(),
.probe_out8(),
.probe_out9(),
.probe_out10(),
.probe_out11(),
.probe_out12(),
.probe_out13(),
.probe_out14(),
.probe_out15(),
.probe_out16(),
.probe_out17(),
.probe_out18(),
.probe_out19(),
.probe_out20(),
.probe_out21(),
.probe_out22(),
.probe_out23(),
.probe_out24(),
.probe_out25(),
.probe_out26(),
.probe_out27(),
.probe_out28(),
.probe_out29(),
.probe_out30(),
.probe_out31(),
.probe_out32(),
.probe_out33(),
.probe_out34(),
.probe_out35(),
.probe_out36(),
.probe_out37(),
.probe_out38(),
.probe_out39(),
.probe_out40(),
.probe_out41(),
.probe_out42(),
.probe_out43(),
.probe_out44(),
.probe_out45(),
.probe_out46(),
.probe_out47(),
.probe_out48(),
.probe_out49(),
.probe_out50(),
.probe_out51(),
.probe_out52(),
.probe_out53(),
.probe_out54(),
.probe_out55(),
.probe_out56(),
.probe_out57(),
.probe_out58(),
.probe_out59(),
.probe_out60(),
.probe_out61(),
.probe_out62(),
.probe_out63(),
.probe_out64(),
.probe_out65(),
.probe_out66(),
.probe_out67(),
.probe_out68(),
.probe_out69(),
.probe_out70(),
.probe_out71(),
.probe_out72(),
.probe_out73(),
.probe_out74(),
.probe_out75(),
.probe_out76(),
.probe_out77(),
.probe_out78(),
.probe_out79(),
.probe_out80(),
.probe_out81(),
.probe_out82(),
.probe_out83(),
.probe_out84(),
.probe_out85(),
.probe_out86(),
.probe_out87(),
.probe_out88(),
.probe_out89(),
.probe_out90(),
.probe_out91(),
.probe_out92(),
.probe_out93(),
.probe_out94(),
.probe_out95(),
.probe_out96(),
.probe_out97(),
.probe_out98(),
.probe_out99(),
.probe_out100(),
.probe_out101(),
.probe_out102(),
.probe_out103(),
.probe_out104(),
.probe_out105(),
.probe_out106(),
.probe_out107(),
.probe_out108(),
.probe_out109(),
.probe_out110(),
.probe_out111(),
.probe_out112(),
.probe_out113(),
.probe_out114(),
.probe_out115(),
.probe_out116(),
.probe_out117(),
.probe_out118(),
.probe_out119(),
.probe_out120(),
.probe_out121(),
.probe_out122(),
.probe_out123(),
.probe_out124(),
.probe_out125(),
.probe_out126(),
.probe_out127(),
.m_slot_0_axi_b_cnt(m_slot_0_axi_b_cnt),
.m_slot_0_axi_r_cnt(m_slot_0_axi_r_cnt),
.m_slot_1_axi_b_cnt(m_slot_1_axi_b_cnt),
.m_slot_1_axi_r_cnt(m_slot_1_axi_r_cnt),
.m_slot_2_axi_b_cnt(),
.m_slot_2_axi_r_cnt(),
.m_slot_3_axi_b_cnt(),
.m_slot_3_axi_r_cnt(),
.m_slot_4_axi_b_cnt(),
.m_slot_4_axi_r_cnt(),
.m_slot_5_axi_b_cnt(),
.m_slot_5_axi_r_cnt(),
.m_slot_6_axi_b_cnt(),
.m_slot_6_axi_r_cnt(),
.m_slot_7_axi_b_cnt(),
.m_slot_7_axi_r_cnt(),
.m_slot_8_axi_b_cnt(),
.m_slot_8_axi_r_cnt(),
.m_slot_9_axi_b_cnt(),
.m_slot_9_axi_r_cnt(),
.m_slot_10_axi_b_cnt(),
.m_slot_10_axi_r_cnt(),
.m_slot_11_axi_b_cnt(),
.m_slot_11_axi_r_cnt(),
.m_slot_12_axi_b_cnt(),
.m_slot_12_axi_r_cnt(),
.m_slot_13_axi_b_cnt(),
.m_slot_13_axi_r_cnt(),
.m_slot_14_axi_b_cnt(),
.m_slot_14_axi_r_cnt(),
.m_slot_15_axi_b_cnt(),
.m_slot_15_axi_r_cnt(),
.m_slot_0_axi_aw_cnt(m_slot_0_axi_aw_cnt),
.m_slot_0_axi_ar_cnt(m_slot_0_axi_ar_cnt),
.m_slot_1_axi_aw_cnt(m_slot_1_axi_aw_cnt),
.m_slot_1_axi_ar_cnt(m_slot_1_axi_ar_cnt),
.m_slot_2_axi_aw_cnt(),
.m_slot_2_axi_ar_cnt(),
.m_slot_3_axi_aw_cnt(),
.m_slot_3_axi_ar_cnt(),
.m_slot_4_axi_aw_cnt(),
.m_slot_4_axi_ar_cnt(),
.m_slot_5_axi_aw_cnt(),
.m_slot_5_axi_ar_cnt(),
.m_slot_6_axi_aw_cnt(),
.m_slot_6_axi_ar_cnt(),
.m_slot_7_axi_aw_cnt(),
.m_slot_7_axi_ar_cnt(),
.m_slot_8_axi_aw_cnt(),
.m_slot_8_axi_ar_cnt(),
.m_slot_9_axi_aw_cnt(),
.m_slot_9_axi_ar_cnt(),
.m_slot_10_axi_aw_cnt(),
.m_slot_10_axi_ar_cnt(),
.m_slot_11_axi_aw_cnt(),
.m_slot_11_axi_ar_cnt(),
.m_slot_12_axi_aw_cnt(),
.m_slot_12_axi_ar_cnt(),
.m_slot_13_axi_aw_cnt(),
.m_slot_13_axi_ar_cnt(),
.m_slot_14_axi_aw_cnt(),
.m_slot_14_axi_ar_cnt(),
.m_slot_15_axi_aw_cnt(),
.m_slot_15_axi_ar_cnt(),
.slot_0_axi_awid(1'B0),
.slot_0_axi_awaddr(slot_0_axi_awaddr),
.slot_0_axi_awprot(3'B0),
.slot_0_axi_awlen(8'B0),
.slot_0_axi_awsize(3'B0),
.slot_0_axi_awburst(2'B0),
.slot_0_axi_awcache(3),
.slot_0_axi_awlock(1'B0),
.slot_0_axi_awvalid(slot_0_axi_awvalid),
.slot_0_axi_awready(slot_0_axi_awready),
.slot_0_axi_wdata(slot_0_axi_wdata),
.slot_0_axi_wstrb(slot_0_axi_wstrb),
.slot_0_axi_wlast(1'B0),
.slot_0_axi_wvalid(slot_0_axi_wvalid),
.slot_0_axi_wready(slot_0_axi_wready),
.slot_0_axi_bid(1'B0),
.slot_0_axi_bresp(slot_0_axi_bresp),
.slot_0_axi_bvalid(slot_0_axi_bvalid),
.slot_0_axi_bready(slot_0_axi_bready),
.slot_0_axi_arid(1'B0),
.slot_0_axi_araddr(slot_0_axi_araddr),
.slot_0_axi_arlen(8'B0),
.slot_0_axi_arsize(3'B0),
.slot_0_axi_arburst(2'B1),
.slot_0_axi_arcache(3),
.slot_0_axi_arprot(3'B0),
.slot_0_axi_arlock(1'B0),
.slot_0_axi_arvalid(slot_0_axi_arvalid),
.slot_0_axi_arready(slot_0_axi_arready),
.slot_0_axi_rid(1'B0),
.slot_0_axi_rdata(slot_0_axi_rdata),
.slot_0_axi_rresp(slot_0_axi_rresp),
.slot_0_axi_rlast(1'B0),
.slot_0_axi_rvalid(slot_0_axi_rvalid),
.slot_0_axi_rready(slot_0_axi_rready),
.slot_0_axis_tvalid(1'B0),
.slot_0_axis_tready(1'B0),
.slot_0_axis_tdata(32'B0),
.slot_0_axis_tstrb(4'B0),
.slot_0_axis_tkeep(4'B0),
.slot_0_axis_tlast(1'B0),
.slot_0_axis_tid(1'B0),
.slot_0_axis_tdest(1'B0),
.slot_0_axis_tuser(1'B0),
.slot_1_axi_awid(slot_1_axi_awid),
.slot_1_axi_awaddr(slot_1_axi_awaddr),
.slot_1_axi_awprot(slot_1_axi_awprot),
.slot_1_axi_awlen(slot_1_axi_awlen),
.slot_1_axi_awsize(slot_1_axi_awsize),
.slot_1_axi_awburst(slot_1_axi_awburst),
.slot_1_axi_awcache(slot_1_axi_awcache),
.slot_1_axi_awlock(slot_1_axi_awlock),
.slot_1_axi_awvalid(slot_1_axi_awvalid),
.slot_1_axi_awready(slot_1_axi_awready),
.slot_1_axi_wdata(slot_1_axi_wdata),
.slot_1_axi_wstrb(slot_1_axi_wstrb),
.slot_1_axi_wlast(slot_1_axi_wlast),
.slot_1_axi_wvalid(slot_1_axi_wvalid),
.slot_1_axi_wready(slot_1_axi_wready),
.slot_1_axi_bid(slot_1_axi_bid),
.slot_1_axi_bresp(slot_1_axi_bresp),
.slot_1_axi_bvalid(slot_1_axi_bvalid),
.slot_1_axi_bready(slot_1_axi_bready),
.slot_1_axi_arid(slot_1_axi_arid),
.slot_1_axi_araddr(slot_1_axi_araddr),
.slot_1_axi_arlen(slot_1_axi_arlen),
.slot_1_axi_arsize(slot_1_axi_arsize),
.slot_1_axi_arburst(slot_1_axi_arburst),
.slot_1_axi_arcache(slot_1_axi_arcache),
.slot_1_axi_arprot(slot_1_axi_arprot),
.slot_1_axi_arlock(slot_1_axi_arlock),
.slot_1_axi_arvalid(slot_1_axi_arvalid),
.slot_1_axi_arready(slot_1_axi_arready),
.slot_1_axi_rid(slot_1_axi_rid),
.slot_1_axi_rdata(slot_1_axi_rdata),
.slot_1_axi_rresp(slot_1_axi_rresp),
.slot_1_axi_rlast(slot_1_axi_rlast),
.slot_1_axi_rvalid(slot_1_axi_rvalid),
.slot_1_axi_rready(slot_1_axi_rready),
.slot_1_axis_tvalid(1'B0),
.slot_1_axis_tready(1'B0),
.slot_1_axis_tdata(32'B0),
.slot_1_axis_tstrb(4'B0),
.slot_1_axis_tkeep(4'B0),
.slot_1_axis_tlast(1'B0),
.slot_1_axis_tid(1'B0),
.slot_1_axis_tdest(1'B0),
.slot_1_axis_tuser(1'B0),
.slot_2_axi_awid(1'B0),
.slot_2_axi_awaddr(32'B0),
.slot_2_axi_awprot(3'B0),
.slot_2_axi_awlen(8'B0),
.slot_2_axi_awsize(3'B0),
.slot_2_axi_awburst(2'B1),
.slot_2_axi_awcache(3),
.slot_2_axi_awlock(1'B0),
.slot_2_axi_awvalid(1'B0),
.slot_2_axi_awready(1'B0),
.slot_2_axi_wdata(32'B0),
.slot_2_axi_wstrb(4'B0),
.slot_2_axi_wlast(1'B0),
.slot_2_axi_wvalid(1'B0),
.slot_2_axi_wready(1'B0),
.slot_2_axi_bid(1'B0),
.slot_2_axi_bresp(2'B0),
.slot_2_axi_bvalid(1'B0),
.slot_2_axi_bready(1'B0),
.slot_2_axi_arid(1'B0),
.slot_2_axi_araddr(32'B0),
.slot_2_axi_arlen(8'B0),
.slot_2_axi_arsize(3'B0),
.slot_2_axi_arburst(2'B1),
.slot_2_axi_arcache(3),
.slot_2_axi_arprot(3'B0),
.slot_2_axi_arlock(1'B0),
.slot_2_axi_arvalid(1'B0),
.slot_2_axi_arready(1'B0),
.slot_2_axi_rid(1'B0),
.slot_2_axi_rdata(32'B0),
.slot_2_axi_rresp(2'B0),
.slot_2_axi_rlast(1'B0),
.slot_2_axi_rvalid(1'B0),
.slot_2_axi_rready(1'B0),
.slot_2_axis_tvalid(1'B0),
.slot_2_axis_tready(1'B0),
.slot_2_axis_tdata(32'B0),
.slot_2_axis_tstrb(4'B0),
.slot_2_axis_tkeep(4'B0),
.slot_2_axis_tlast(1'B0),
.slot_2_axis_tid(1'B0),
.slot_2_axis_tdest(1'B0),
.slot_2_axis_tuser(1'B0),
.slot_3_axi_awid(1'B0),
.slot_3_axi_awaddr(32'B0),
.slot_3_axi_awprot(3'B0),
.slot_3_axi_awlen(8'B0),
.slot_3_axi_awsize(3'B0),
.slot_3_axi_awburst(2'B1),
.slot_3_axi_awcache(3),
.slot_3_axi_awlock(1'B0),
.slot_3_axi_awvalid(1'B0),
.slot_3_axi_awready(1'B0),
.slot_3_axi_wdata(32'B0),
.slot_3_axi_wstrb(4'B0),
.slot_3_axi_wlast(1'B0),
.slot_3_axi_wvalid(1'B0),
.slot_3_axi_wready(1'B0),
.slot_3_axi_bid(1'B0),
.slot_3_axi_bresp(2'B0),
.slot_3_axi_bvalid(1'B0),
.slot_3_axi_bready(1'B0),
.slot_3_axi_arid(1'B0),
.slot_3_axi_araddr(32'B0),
.slot_3_axi_arlen(8'B0),
.slot_3_axi_arsize(3'B0),
.slot_3_axi_arburst(2'B1),
.slot_3_axi_arcache(3),
.slot_3_axi_arprot(3'B0),
.slot_3_axi_arlock(1'B0),
.slot_3_axi_arvalid(1'B0),
.slot_3_axi_arready(1'B0),
.slot_3_axi_rid(1'B0),
.slot_3_axi_rdata(32'B0),
.slot_3_axi_rresp(2'B0),
.slot_3_axi_rlast(1'B0),
.slot_3_axi_rvalid(1'B0),
.slot_3_axi_rready(1'B0),
.slot_3_axis_tvalid(1'B0),
.slot_3_axis_tready(1'B0),
.slot_3_axis_tdata(32'B0),
.slot_3_axis_tstrb(4'B0),
.slot_3_axis_tkeep(4'B0),
.slot_3_axis_tlast(1'B0),
.slot_3_axis_tid(1'B0),
.slot_3_axis_tdest(1'B0),
.slot_3_axis_tuser(1'B0),
.slot_4_axi_awid(1'B0),
.slot_4_axi_awaddr(32'B0),
.slot_4_axi_awprot(3'B0),
.slot_4_axi_awlen(8'B0),
.slot_4_axi_awsize(3'B0),
.slot_4_axi_awburst(2'B1),
.slot_4_axi_awcache(3),
.slot_4_axi_awlock(1'B0),
.slot_4_axi_awvalid(1'B0),
.slot_4_axi_awready(1'B0),
.slot_4_axi_wdata(32'B0),
.slot_4_axi_wstrb(4'B0),
.slot_4_axi_wlast(1'B0),
.slot_4_axi_wvalid(1'B0),
.slot_4_axi_wready(1'B0),
.slot_4_axi_bid(1'B0),
.slot_4_axi_bresp(2'B0),
.slot_4_axi_bvalid(1'B0),
.slot_4_axi_bready(1'B0),
.slot_4_axi_arid(1'B0),
.slot_4_axi_araddr(32'B0),
.slot_4_axi_arlen(8'B0),
.slot_4_axi_arsize(3'B0),
.slot_4_axi_arburst(2'B1),
.slot_4_axi_arcache(3),
.slot_4_axi_arprot(3'B0),
.slot_4_axi_arlock(1'B0),
.slot_4_axi_arvalid(1'B0),
.slot_4_axi_arready(1'B0),
.slot_4_axi_rid(1'B0),
.slot_4_axi_rdata(32'B0),
.slot_4_axi_rresp(2'B0),
.slot_4_axi_rlast(1'B0),
.slot_4_axi_rvalid(1'B0),
.slot_4_axi_rready(1'B0),
.slot_4_axis_tvalid(1'B0),
.slot_4_axis_tready(1'B0),
.slot_4_axis_tdata(32'B0),
.slot_4_axis_tstrb(4'B0),
.slot_4_axis_tkeep(4'B0),
.slot_4_axis_tlast(1'B0),
.slot_4_axis_tid(1'B0),
.slot_4_axis_tdest(1'B0),
.slot_4_axis_tuser(1'B0),
.slot_5_axi_awid(1'B0),
.slot_5_axi_awaddr(32'B0),
.slot_5_axi_awprot(3'B0),
.slot_5_axi_awlen(8'B0),
.slot_5_axi_awsize(3'B0),
.slot_5_axi_awburst(2'B1),
.slot_5_axi_awcache(3),
.slot_5_axi_awlock(1'B0),
.slot_5_axi_awvalid(1'B0),
.slot_5_axi_awready(1'B0),
.slot_5_axi_wdata(32'B0),
.slot_5_axi_wstrb(4'B0),
.slot_5_axi_wlast(1'B0),
.slot_5_axi_wvalid(1'B0),
.slot_5_axi_wready(1'B0),
.slot_5_axi_bid(1'B0),
.slot_5_axi_bresp(2'B0),
.slot_5_axi_bvalid(1'B0),
.slot_5_axi_bready(1'B0),
.slot_5_axi_arid(1'B0),
.slot_5_axi_araddr(32'B0),
.slot_5_axi_arlen(8'B0),
.slot_5_axi_arsize(3'B0),
.slot_5_axi_arburst(2'B1),
.slot_5_axi_arcache(3),
.slot_5_axi_arprot(3'B0),
.slot_5_axi_arlock(1'B0),
.slot_5_axi_arvalid(1'B0),
.slot_5_axi_arready(1'B0),
.slot_5_axi_rid(1'B0),
.slot_5_axi_rdata(32'B0),
.slot_5_axi_rresp(2'B0),
.slot_5_axi_rlast(1'B0),
.slot_5_axi_rvalid(1'B0),
.slot_5_axi_rready(1'B0),
.slot_5_axis_tvalid(1'B0),
.slot_5_axis_tready(1'B0),
.slot_5_axis_tdata(32'B0),
.slot_5_axis_tstrb(4'B0),
.slot_5_axis_tkeep(4'B0),
.slot_5_axis_tlast(1'B0),
.slot_5_axis_tid(1'B0),
.slot_5_axis_tdest(1'B0),
.slot_5_axis_tuser(1'B0),
.slot_6_axi_awid(1'B0),
.slot_6_axi_awaddr(32'B0),
.slot_6_axi_awprot(3'B0),
.slot_6_axi_awlen(8'B0),
.slot_6_axi_awsize(3'B0),
.slot_6_axi_awburst(2'B1),
.slot_6_axi_awcache(3),
.slot_6_axi_awlock(1'B0),
.slot_6_axi_awvalid(1'B0),
.slot_6_axi_awready(1'B0),
.slot_6_axi_wdata(32'B0),
.slot_6_axi_wstrb(4'B0),
.slot_6_axi_wlast(1'B0),
.slot_6_axi_wvalid(1'B0),
.slot_6_axi_wready(1'B0),
.slot_6_axi_bid(1'B0),
.slot_6_axi_bresp(2'B0),
.slot_6_axi_bvalid(1'B0),
.slot_6_axi_bready(1'B0),
.slot_6_axi_arid(1'B0),
.slot_6_axi_araddr(32'B0),
.slot_6_axi_arlen(8'B0),
.slot_6_axi_arsize(3'B0),
.slot_6_axi_arburst(2'B1),
.slot_6_axi_arcache(3),
.slot_6_axi_arprot(3'B0),
.slot_6_axi_arlock(1'B0),
.slot_6_axi_arvalid(1'B0),
.slot_6_axi_arready(1'B0),
.slot_6_axi_rid(1'B0),
.slot_6_axi_rdata(32'B0),
.slot_6_axi_rresp(2'B0),
.slot_6_axi_rlast(1'B0),
.slot_6_axi_rvalid(1'B0),
.slot_6_axi_rready(1'B0),
.slot_6_axis_tvalid(1'B0),
.slot_6_axis_tready(1'B0),
.slot_6_axis_tdata(32'B0),
.slot_6_axis_tstrb(4'B0),
.slot_6_axis_tkeep(4'B0),
.slot_6_axis_tlast(1'B0),
.slot_6_axis_tid(1'B0),
.slot_6_axis_tdest(1'B0),
.slot_6_axis_tuser(1'B0),
.slot_7_axi_awid(1'B0),
.slot_7_axi_awaddr(32'B0),
.slot_7_axi_awprot(3'B0),
.slot_7_axi_awlen(8'B0),
.slot_7_axi_awsize(3'B0),
.slot_7_axi_awburst(2'B1),
.slot_7_axi_awcache(3),
.slot_7_axi_awlock(1'B0),
.slot_7_axi_awvalid(1'B0),
.slot_7_axi_awready(1'B0),
.slot_7_axi_wdata(32'B0),
.slot_7_axi_wstrb(4'B0),
.slot_7_axi_wlast(1'B0),
.slot_7_axi_wvalid(1'B0),
.slot_7_axi_wready(1'B0),
.slot_7_axi_bid(1'B0),
.slot_7_axi_bresp(2'B0),
.slot_7_axi_bvalid(1'B0),
.slot_7_axi_bready(1'B0),
.slot_7_axi_arid(1'B0),
.slot_7_axi_araddr(32'B0),
.slot_7_axi_arlen(8'B0),
.slot_7_axi_arsize(3'B0),
.slot_7_axi_arburst(2'B0),
.slot_7_axi_arcache(3),
.slot_7_axi_arprot(3'B0),
.slot_7_axi_arlock(1'B0),
.slot_7_axi_arvalid(1'B0),
.slot_7_axi_arready(1'B0),
.slot_7_axi_rid(1'B0),
.slot_7_axi_rdata(32'B0),
.slot_7_axi_rresp(2'B0),
.slot_7_axi_rlast(1'B0),
.slot_7_axi_rvalid(1'B0),
.slot_7_axi_rready(1'B0),
.slot_7_axis_tvalid(1'B0),
.slot_7_axis_tready(1'B0),
.slot_7_axis_tdata(32'B0),
.slot_7_axis_tstrb(4'B0),
.slot_7_axis_tkeep(4'B0),
.slot_7_axis_tlast(1'B0),
.slot_7_axis_tid(1'B0),
.slot_7_axis_tdest(1'B0),
.slot_7_axis_tuser(1'B0),
.slot_8_axi_awid(1'B0),
.slot_8_axi_awaddr(32'B0),
.slot_8_axi_awprot(3'B0),
.slot_8_axi_awlen(8'B0),
.slot_8_axi_awsize(3'B0),
.slot_8_axi_awburst(2'B1),
.slot_8_axi_awcache(3),
.slot_8_axi_awlock(1'B0),
.slot_8_axi_awvalid(1'B0),
.slot_8_axi_awready(1'B0),
.slot_8_axi_wdata(32'B0),
.slot_8_axi_wstrb(4'B0),
.slot_8_axi_wlast(1'B0),
.slot_8_axi_wvalid(1'B0),
.slot_8_axi_wready(1'B0),
.slot_8_axi_bid(1'B0),
.slot_8_axi_bresp(2'B0),
.slot_8_axi_bvalid(1'B0),
.slot_8_axi_bready(1'B0),
.slot_8_axi_arid(1'B0),
.slot_8_axi_araddr(32'B0),
.slot_8_axi_arlen(8'B0),
.slot_8_axi_arsize(3'B0),
.slot_8_axi_arburst(2'B1),
.slot_8_axi_arcache(3),
.slot_8_axi_arprot(3'B0),
.slot_8_axi_arlock(1'B0),
.slot_8_axi_arvalid(1'B0),
.slot_8_axi_arready(1'B0),
.slot_8_axi_rid(1'B0),
.slot_8_axi_rdata(32'B0),
.slot_8_axi_rresp(2'B0),
.slot_8_axi_rlast(1'B0),
.slot_8_axi_rvalid(1'B0),
.slot_8_axi_rready(1'B0),
.slot_8_axis_tvalid(1'B0),
.slot_8_axis_tready(1'B0),
.slot_8_axis_tdata(32'B0),
.slot_8_axis_tstrb(4'B0),
.slot_8_axis_tkeep(4'B0),
.slot_8_axis_tlast(1'B0),
.slot_8_axis_tid(1'B0),
.slot_8_axis_tdest(1'B0),
.slot_8_axis_tuser(1'B0),
.slot_9_axi_awid(1'B0),
.slot_9_axi_awaddr(32'B0),
.slot_9_axi_awprot(3'B0),
.slot_9_axi_awlen(8'B0),
.slot_9_axi_awsize(3'B0),
.slot_9_axi_awburst(2'B1),
.slot_9_axi_awcache(3),
.slot_9_axi_awlock(1'B0),
.slot_9_axi_awvalid(1'B0),
.slot_9_axi_awready(1'B0),
.slot_9_axi_wdata(32'B0),
.slot_9_axi_wstrb(3'B0),
.slot_9_axi_wlast(1'B0),
.slot_9_axi_wvalid(1'B0),
.slot_9_axi_wready(1'B0),
.slot_9_axi_bid(1'B0),
.slot_9_axi_bresp(2'B0),
.slot_9_axi_bvalid(1'B0),
.slot_9_axi_bready(1'B0),
.slot_9_axi_arid(1'B0),
.slot_9_axi_araddr(32'B0),
.slot_9_axi_arlen(8'B0),
.slot_9_axi_arsize(3'B0),
.slot_9_axi_arburst(2'B1),
.slot_9_axi_arcache(3),
.slot_9_axi_arprot(3'B0),
.slot_9_axi_arlock(1'B0),
.slot_9_axi_arvalid(1'B0),
.slot_9_axi_arready(1'B0),
.slot_9_axi_rid(1'B0),
.slot_9_axi_rdata(32'B0),
.slot_9_axi_rresp(2'B0),
.slot_9_axi_rlast(1'B0),
.slot_9_axi_rvalid(1'B0),
.slot_9_axi_rready(1'B0),
.slot_9_axis_tvalid(1'B0),
.slot_9_axis_tready(1'B0),
.slot_9_axis_tdata(32'B0),
.slot_9_axis_tstrb(3'B0),
.slot_9_axis_tkeep(3'B0),
.slot_9_axis_tlast(1'B0),
.slot_9_axis_tid(1'B0),
.slot_9_axis_tdest(1'B0),
.slot_9_axis_tuser(1'B0),
.slot_10_axi_awid(1'B0),
.slot_10_axi_awaddr(32'B0),
.slot_10_axi_awprot(3'B0),
.slot_10_axi_awlen(8'B0),
.slot_10_axi_awsize(3'B0),
.slot_10_axi_awburst(2'B1),
.slot_10_axi_awcache(3),
.slot_10_axi_awlock(1'B0),
.slot_10_axi_awvalid(1'B0),
.slot_10_axi_awready(1'B0),
.slot_10_axi_wdata(32'B0),
.slot_10_axi_wstrb(4'B0),
.slot_10_axi_wlast(1'B0),
.slot_10_axi_wvalid(1'B0),
.slot_10_axi_wready(1'B0),
.slot_10_axi_bid(1'B0),
.slot_10_axi_bresp(2'B0),
.slot_10_axi_bvalid(1'B0),
.slot_10_axi_bready(1'B0),
.slot_10_axi_arid(1'B0),
.slot_10_axi_araddr(32'B0),
.slot_10_axi_arlen(8'B0),
.slot_10_axi_arsize(3'B0),
.slot_10_axi_arburst(2'B1),
.slot_10_axi_arcache(3),
.slot_10_axi_arprot(3'B0),
.slot_10_axi_arlock(1'B0),
.slot_10_axi_arvalid(1'B0),
.slot_10_axi_arready(1'B0),
.slot_10_axi_rid(1'B0),
.slot_10_axi_rdata(32'B0),
.slot_10_axi_rresp(2'B0),
.slot_10_axi_rlast(1'B0),
.slot_10_axi_rvalid(1'B0),
.slot_10_axi_rready(1'B0),
.slot_10_axis_tvalid(1'B0),
.slot_10_axis_tready(1'B0),
.slot_10_axis_tdata(32'B0),
.slot_10_axis_tstrb(4'B0),
.slot_10_axis_tkeep(4'B0),
.slot_10_axis_tlast(1'B0),
.slot_10_axis_tid(1'B0),
.slot_10_axis_tdest(1'B0),
.slot_10_axis_tuser(1'B0),
.slot_11_axi_awid(1'B0),
.slot_11_axi_awaddr(32'B0),
.slot_11_axi_awprot(3'B0),
.slot_11_axi_awlen(8'B0),
.slot_11_axi_awsize(3'B0),
.slot_11_axi_awburst(2'B1),
.slot_11_axi_awcache(3),
.slot_11_axi_awlock(1'B0),
.slot_11_axi_awvalid(1'B0),
.slot_11_axi_awready(1'B0),
.slot_11_axi_wdata(32'B0),
.slot_11_axi_wstrb(4'B0),
.slot_11_axi_wlast(1'B0),
.slot_11_axi_wvalid(1'B0),
.slot_11_axi_wready(1'B0),
.slot_11_axi_bid(1'B0),
.slot_11_axi_bresp(2'B0),
.slot_11_axi_bvalid(1'B0),
.slot_11_axi_bready(1'B0),
.slot_11_axi_arid(1'B0),
.slot_11_axi_araddr(32'B0),
.slot_11_axi_arlen(8'B0),
.slot_11_axi_arsize(3'B0),
.slot_11_axi_arburst(2'B1),
.slot_11_axi_arcache(3),
.slot_11_axi_arprot(3'B0),
.slot_11_axi_arlock(1'B0),
.slot_11_axi_arvalid(1'B0),
.slot_11_axi_arready(1'B0),
.slot_11_axi_rid(1'B0),
.slot_11_axi_rdata(32'B0),
.slot_11_axi_rresp(2'B0),
.slot_11_axi_rlast(1'B0),
.slot_11_axi_rvalid(1'B0),
.slot_11_axi_rready(1'B0),
.slot_11_axis_tvalid(1'B0),
.slot_11_axis_tready(1'B0),
.slot_11_axis_tdata(32'B0),
.slot_11_axis_tstrb(4'B0),
.slot_11_axis_tkeep(4'B0),
.slot_11_axis_tlast(1'B0),
.slot_11_axis_tid(1'B0),
.slot_11_axis_tdest(1'B0),
.slot_11_axis_tuser(1'B0),
.slot_12_axi_awid(1'B0),
.slot_12_axi_awaddr(32'B0),
.slot_12_axi_awprot(3'B0),
.slot_12_axi_awlen(8'B0),
.slot_12_axi_awsize(3'B0),
.slot_12_axi_awburst(2'B1),
.slot_12_axi_awcache(3),
.slot_12_axi_awlock(1'B0),
.slot_12_axi_awvalid(1'B0),
.slot_12_axi_awready(1'B0),
.slot_12_axi_wdata(32'B0),
.slot_12_axi_wstrb(4'B0),
.slot_12_axi_wlast(1'B0),
.slot_12_axi_wvalid(1'B0),
.slot_12_axi_wready(1'B0),
.slot_12_axi_bid(1'B0),
.slot_12_axi_bresp(2'B0),
.slot_12_axi_bvalid(1'B0),
.slot_12_axi_bready(1'B0),
.slot_12_axi_arid(1'B0),
.slot_12_axi_araddr(32'B0),
.slot_12_axi_arlen(8'B0),
.slot_12_axi_arsize(3'B0),
.slot_12_axi_arburst(2'B1),
.slot_12_axi_arcache(3),
.slot_12_axi_arprot(3'B0),
.slot_12_axi_arlock(1'B0),
.slot_12_axi_arvalid(1'B0),
.slot_12_axi_arready(1'B0),
.slot_12_axi_rid(1'B0),
.slot_12_axi_rdata(32'B0),
.slot_12_axi_rresp(2'B0),
.slot_12_axi_rlast(1'B0),
.slot_12_axi_rvalid(1'B0),
.slot_12_axi_rready(1'B0),
.slot_12_axis_tvalid(1'B0),
.slot_12_axis_tready(1'B0),
.slot_12_axis_tdata(32'B0),
.slot_12_axis_tstrb(4'B0),
.slot_12_axis_tkeep(4'B0),
.slot_12_axis_tlast(1'B0),
.slot_12_axis_tid(1'B0),
.slot_12_axis_tdest(1'B0),
.slot_12_axis_tuser(1'B0),
.slot_13_axi_awid(1'B0),
.slot_13_axi_awaddr(32'B0),
.slot_13_axi_awprot(3'B0),
.slot_13_axi_awlen(8'B0),
.slot_13_axi_awsize(3'B0),
.slot_13_axi_awburst(2'B1),
.slot_13_axi_awcache(3),
.slot_13_axi_awlock(1'B0),
.slot_13_axi_awvalid(1'B0),
.slot_13_axi_awready(1'B0),
.slot_13_axi_wdata(32'B0),
.slot_13_axi_wstrb(4'B0),
.slot_13_axi_wlast(1'B0),
.slot_13_axi_wvalid(1'B0),
.slot_13_axi_wready(1'B0),
.slot_13_axi_bid(1'B0),
.slot_13_axi_bresp(2'B0),
.slot_13_axi_bvalid(1'B0),
.slot_13_axi_bready(1'B0),
.slot_13_axi_arid(1'B0),
.slot_13_axi_araddr(32'B0),
.slot_13_axi_arlen(8'B0),
.slot_13_axi_arsize(3'B0),
.slot_13_axi_arburst(2'B1),
.slot_13_axi_arcache(3),
.slot_13_axi_arprot(3'B0),
.slot_13_axi_arlock(1'B0),
.slot_13_axi_arvalid(1'B0),
.slot_13_axi_arready(1'B0),
.slot_13_axi_rid(1'B0),
.slot_13_axi_rdata(32'B0),
.slot_13_axi_rresp(2'B0),
.slot_13_axi_rlast(1'B0),
.slot_13_axi_rvalid(1'B0),
.slot_13_axi_rready(1'B0),
.slot_13_axis_tvalid(1'B0),
.slot_13_axis_tready(1'B0),
.slot_13_axis_tdata(32'B0),
.slot_13_axis_tstrb(4'B0),
.slot_13_axis_tkeep(4'B0),
.slot_13_axis_tlast(1'B0),
.slot_13_axis_tid(1'B0),
.slot_13_axis_tdest(1'B0),
.slot_13_axis_tuser(1'B0),
.slot_14_axi_awid(1'B0),
.slot_14_axi_awaddr(32'B0),
.slot_14_axi_awprot(3'B0),
.slot_14_axi_awlen(8'B0),
.slot_14_axi_awsize(3'B0),
.slot_14_axi_awburst(2'B0),
.slot_14_axi_awcache(3),
.slot_14_axi_awlock(1'B0),
.slot_14_axi_awvalid(1'B0),
.slot_14_axi_awready(1'B0),
.slot_14_axi_wdata(32'B0),
.slot_14_axi_wstrb(4'B0),
.slot_14_axi_wlast(1'B0),
.slot_14_axi_wvalid(1'B0),
.slot_14_axi_wready(1'B0),
.slot_14_axi_bid(1'B0),
.slot_14_axi_bresp(2'B0),
.slot_14_axi_bvalid(1'B0),
.slot_14_axi_bready(1'B0),
.slot_14_axi_arid(1'B0),
.slot_14_axi_araddr(32'B0),
.slot_14_axi_arlen(8'B0),
.slot_14_axi_arsize(3'B0),
.slot_14_axi_arburst(2'B0),
.slot_14_axi_arcache(3),
.slot_14_axi_arprot(3'B0),
.slot_14_axi_arlock(1'B0),
.slot_14_axi_arvalid(1'B0),
.slot_14_axi_arready(1'B0),
.slot_14_axi_rid(1'B0),
.slot_14_axi_rdata(32'B0),
.slot_14_axi_rresp(2'B0),
.slot_14_axi_rlast(1'B0),
.slot_14_axi_rvalid(1'B0),
.slot_14_axi_rready(1'B0),
.slot_14_axis_tvalid(1'B0),
.slot_14_axis_tready(1'B0),
.slot_14_axis_tdata(32'B0),
.slot_14_axis_tstrb(4'B0),
.slot_14_axis_tkeep(4'B0),
.slot_14_axis_tlast(1'B0),
.slot_14_axis_tid(1'B0),
.slot_14_axis_tdest(1'B0),
.slot_14_axis_tuser(1'B0),
.slot_15_axi_awid(1'B0),
.slot_15_axi_awaddr(32'B0),
.slot_15_axi_awprot(3'B0),
.slot_15_axi_awlen(8'B0),
.slot_15_axi_awsize(3'B0),
.slot_15_axi_awburst(2'B0),
.slot_15_axi_awcache(3),
.slot_15_axi_awlock(1'B0),
.slot_15_axi_awvalid(1'B0),
.slot_15_axi_awready(1'B0),
.slot_15_axi_wdata(32'B0),
.slot_15_axi_wstrb(4'B0),
.slot_15_axi_wlast(1'B0),
.slot_15_axi_wvalid(1'B0),
.slot_15_axi_wready(1'B0),
.slot_15_axi_bid(1'B0),
.slot_15_axi_bresp(2'B0),
.slot_15_axi_bvalid(1'B0),
.slot_15_axi_bready(1'B0),
.slot_15_axi_arid(1'B0),
.slot_15_axi_araddr(32'B0),
.slot_15_axi_arlen(8'B0),
.slot_15_axi_arsize(3'B0),
.slot_15_axi_arburst(2'B1),
.slot_15_axi_arcache(3),
.slot_15_axi_arprot(3'B0),
.slot_15_axi_arlock(1'B0),
.slot_15_axi_arvalid(1'B0),
.slot_15_axi_arready(1'B0),
.slot_15_axi_rid(1'B0),
.slot_15_axi_rdata(32'B0),
.slot_15_axi_rresp(2'B0),
.slot_15_axi_rlast(1'B0),
.slot_15_axi_rvalid(1'B0),
.slot_15_axi_rready(1'B0),
.slot_15_axis_tvalid(1'B0),
.slot_15_axis_tready(1'B0),
.slot_15_axis_tdata(32'B0),
.slot_15_axis_tstrb(4'B0),
.slot_15_axis_tkeep(4'B0),
.slot_15_axis_tlast(1'B0),
.slot_15_axis_tid(1'B0),
.slot_15_axis_tdest(1'B0),
.slot_15_axis_tuser(1'B0),
.m_slot_0_axi_awid(),
.m_slot_0_axi_awaddr(m_slot_0_axi_awaddr),
.m_slot_0_axi_awprot(),
.m_slot_0_axi_awlen(),
.m_slot_0_axi_awsize(),
.m_slot_0_axi_awburst(),
.m_slot_0_axi_awcache(),
.m_slot_0_axi_awlock(),
.m_slot_0_axi_awvalid(m_slot_0_axi_awvalid),
.m_slot_0_axi_awready(m_slot_0_axi_awready),
.m_slot_0_axi_wdata(m_slot_0_axi_wdata),
.m_slot_0_axi_wstrb(m_slot_0_axi_wstrb),
.m_slot_0_axi_wlast(),
.m_slot_0_axi_wvalid(m_slot_0_axi_wvalid),
.m_slot_0_axi_wready(m_slot_0_axi_wready),
.m_slot_0_axi_bid(),
.m_slot_0_axi_bresp(m_slot_0_axi_bresp),
.m_slot_0_axi_bvalid(m_slot_0_axi_bvalid),
.m_slot_0_axi_bready(m_slot_0_axi_bready),
.m_slot_0_axi_arid(),
.m_slot_0_axi_araddr(m_slot_0_axi_araddr),
.m_slot_0_axi_arlen(),
.m_slot_0_axi_arsize(),
.m_slot_0_axi_arburst(),
.m_slot_0_axi_arcache(),
.m_slot_0_axi_arprot(),
.m_slot_0_axi_arlock(),
.m_slot_0_axi_arvalid(m_slot_0_axi_arvalid),
.m_slot_0_axi_arready(m_slot_0_axi_arready),
.m_slot_0_axi_rid(),
.m_slot_0_axi_rdata(m_slot_0_axi_rdata),
.m_slot_0_axi_rresp(m_slot_0_axi_rresp),
.m_slot_0_axi_rlast(),
.m_slot_0_axi_rvalid(m_slot_0_axi_rvalid),
.m_slot_0_axi_rready(m_slot_0_axi_rready),
.m_slot_0_axis_tvalid(),
.m_slot_0_axis_tready(),
.m_slot_0_axis_tdata(),
.m_slot_0_axis_tstrb(),
.m_slot_0_axis_tkeep(),
.m_slot_0_axis_tlast(),
.m_slot_0_axis_tid(),
.m_slot_0_axis_tdest(),
.m_slot_0_axis_tuser(),
.m_slot_1_axi_awid(m_slot_1_axi_awid),
.m_slot_1_axi_awaddr(m_slot_1_axi_awaddr),
.m_slot_1_axi_awprot(m_slot_1_axi_awprot),
.m_slot_1_axi_awlen(m_slot_1_axi_awlen),
.m_slot_1_axi_awsize(m_slot_1_axi_awsize),
.m_slot_1_axi_awburst(m_slot_1_axi_awburst),
.m_slot_1_axi_awcache(m_slot_1_axi_awcache),
.m_slot_1_axi_awlock(m_slot_1_axi_awlock),
.m_slot_1_axi_awvalid(m_slot_1_axi_awvalid),
.m_slot_1_axi_awready(m_slot_1_axi_awready),
.m_slot_1_axi_wdata(m_slot_1_axi_wdata),
.m_slot_1_axi_wstrb(m_slot_1_axi_wstrb),
.m_slot_1_axi_wlast(m_slot_1_axi_wlast),
.m_slot_1_axi_wvalid(m_slot_1_axi_wvalid),
.m_slot_1_axi_wready(m_slot_1_axi_wready),
.m_slot_1_axi_bid(m_slot_1_axi_bid),
.m_slot_1_axi_bresp(m_slot_1_axi_bresp),
.m_slot_1_axi_bvalid(m_slot_1_axi_bvalid),
.m_slot_1_axi_bready(m_slot_1_axi_bready),
.m_slot_1_axi_arid(m_slot_1_axi_arid),
.m_slot_1_axi_araddr(m_slot_1_axi_araddr),
.m_slot_1_axi_arlen(m_slot_1_axi_arlen),
.m_slot_1_axi_arsize(m_slot_1_axi_arsize),
.m_slot_1_axi_arburst(m_slot_1_axi_arburst),
.m_slot_1_axi_arcache(m_slot_1_axi_arcache),
.m_slot_1_axi_arprot(m_slot_1_axi_arprot),
.m_slot_1_axi_arlock(m_slot_1_axi_arlock),
.m_slot_1_axi_arvalid(m_slot_1_axi_arvalid),
.m_slot_1_axi_arready(m_slot_1_axi_arready),
.m_slot_1_axi_rid(m_slot_1_axi_rid),
.m_slot_1_axi_rdata(m_slot_1_axi_rdata),
.m_slot_1_axi_rresp(m_slot_1_axi_rresp),
.m_slot_1_axi_rlast(m_slot_1_axi_rlast),
.m_slot_1_axi_rvalid(m_slot_1_axi_rvalid),
.m_slot_1_axi_rready(m_slot_1_axi_rready),
.m_slot_1_axis_tvalid(),
.m_slot_1_axis_tready(),
.m_slot_1_axis_tdata(),
.m_slot_1_axis_tstrb(),
.m_slot_1_axis_tkeep(),
.m_slot_1_axis_tlast(),
.m_slot_1_axis_tid(),
.m_slot_1_axis_tdest(),
.m_slot_1_axis_tuser(),
.m_slot_2_axi_awid(),
.m_slot_2_axi_awaddr(),
.m_slot_2_axi_awprot(),
.m_slot_2_axi_awlen(),
.m_slot_2_axi_awsize(),
.m_slot_2_axi_awburst(),
.m_slot_2_axi_awcache(),
.m_slot_2_axi_awlock(),
.m_slot_2_axi_awvalid(),
.m_slot_2_axi_awready(),
.m_slot_2_axi_wdata(),
.m_slot_2_axi_wstrb(),
.m_slot_2_axi_wlast(),
.m_slot_2_axi_wvalid(),
.m_slot_2_axi_wready(),
.m_slot_2_axi_bid(),
.m_slot_2_axi_bresp(),
.m_slot_2_axi_bvalid(),
.m_slot_2_axi_bready(),
.m_slot_2_axi_arid(),
.m_slot_2_axi_araddr(),
.m_slot_2_axi_arlen(),
.m_slot_2_axi_arsize(),
.m_slot_2_axi_arburst(),
.m_slot_2_axi_arcache(),
.m_slot_2_axi_arprot(),
.m_slot_2_axi_arlock(),
.m_slot_2_axi_arvalid(),
.m_slot_2_axi_arready(),
.m_slot_2_axi_rid(),
.m_slot_2_axi_rdata(),
.m_slot_2_axi_rresp(),
.m_slot_2_axi_rlast(),
.m_slot_2_axi_rvalid(),
.m_slot_2_axi_rready(),
.m_slot_2_axis_tvalid(),
.m_slot_2_axis_tready(),
.m_slot_2_axis_tdata(),
.m_slot_2_axis_tstrb(),
.m_slot_2_axis_tkeep(),
.m_slot_2_axis_tlast(),
.m_slot_2_axis_tid(),
.m_slot_2_axis_tdest(),
.m_slot_2_axis_tuser(),
.m_slot_3_axi_awid(),
.m_slot_3_axi_awaddr(),
.m_slot_3_axi_awprot(),
.m_slot_3_axi_awlen(),
.m_slot_3_axi_awsize(),
.m_slot_3_axi_awburst(),
.m_slot_3_axi_awcache(),
.m_slot_3_axi_awlock(),
.m_slot_3_axi_awvalid(),
.m_slot_3_axi_awready(),
.m_slot_3_axi_wdata(),
.m_slot_3_axi_wstrb(),
.m_slot_3_axi_wlast(),
.m_slot_3_axi_wvalid(),
.m_slot_3_axi_wready(),
.m_slot_3_axi_bid(),
.m_slot_3_axi_bresp(),
.m_slot_3_axi_bvalid(),
.m_slot_3_axi_bready(),
.m_slot_3_axi_arid(),
.m_slot_3_axi_araddr(),
.m_slot_3_axi_arlen(),
.m_slot_3_axi_arsize(),
.m_slot_3_axi_arburst(),
.m_slot_3_axi_arcache(),
.m_slot_3_axi_arprot(),
.m_slot_3_axi_arlock(),
.m_slot_3_axi_arvalid(),
.m_slot_3_axi_arready(),
.m_slot_3_axi_rid(),
.m_slot_3_axi_rdata(),
.m_slot_3_axi_rresp(),
.m_slot_3_axi_rlast(),
.m_slot_3_axi_rvalid(),
.m_slot_3_axi_rready(),
.m_slot_3_axis_tvalid(),
.m_slot_3_axis_tready(),
.m_slot_3_axis_tdata(),
.m_slot_3_axis_tstrb(),
.m_slot_3_axis_tkeep(),
.m_slot_3_axis_tlast(),
.m_slot_3_axis_tid(),
.m_slot_3_axis_tdest(),
.m_slot_3_axis_tuser(),
.m_slot_4_axi_awid(),
.m_slot_4_axi_awaddr(),
.m_slot_4_axi_awprot(),
.m_slot_4_axi_awlen(),
.m_slot_4_axi_awsize(),
.m_slot_4_axi_awburst(),
.m_slot_4_axi_awcache(),
.m_slot_4_axi_awlock(),
.m_slot_4_axi_awvalid(),
.m_slot_4_axi_awready(),
.m_slot_4_axi_wdata(),
.m_slot_4_axi_wstrb(),
.m_slot_4_axi_wlast(),
.m_slot_4_axi_wvalid(),
.m_slot_4_axi_wready(),
.m_slot_4_axi_bid(),
.m_slot_4_axi_bresp(),
.m_slot_4_axi_bvalid(),
.m_slot_4_axi_bready(),
.m_slot_4_axi_arid(),
.m_slot_4_axi_araddr(),
.m_slot_4_axi_arlen(),
.m_slot_4_axi_arsize(),
.m_slot_4_axi_arburst(),
.m_slot_4_axi_arcache(),
.m_slot_4_axi_arprot(),
.m_slot_4_axi_arlock(),
.m_slot_4_axi_arvalid(),
.m_slot_4_axi_arready(),
.m_slot_4_axi_rid(),
.m_slot_4_axi_rdata(),
.m_slot_4_axi_rresp(),
.m_slot_4_axi_rlast(),
.m_slot_4_axi_rvalid(),
.m_slot_4_axi_rready(),
.m_slot_4_axis_tvalid(),
.m_slot_4_axis_tready(),
.m_slot_4_axis_tdata(),
.m_slot_4_axis_tstrb(),
.m_slot_4_axis_tkeep(),
.m_slot_4_axis_tlast(),
.m_slot_4_axis_tid(),
.m_slot_4_axis_tdest(),
.m_slot_4_axis_tuser(),
.m_slot_5_axi_awid(),
.m_slot_5_axi_awaddr(),
.m_slot_5_axi_awprot(),
.m_slot_5_axi_awlen(),
.m_slot_5_axi_awsize(),
.m_slot_5_axi_awburst(),
.m_slot_5_axi_awcache(),
.m_slot_5_axi_awlock(),
.m_slot_5_axi_awvalid(),
.m_slot_5_axi_awready(),
.m_slot_5_axi_wdata(),
.m_slot_5_axi_wstrb(),
.m_slot_5_axi_wlast(),
.m_slot_5_axi_wvalid(),
.m_slot_5_axi_wready(),
.m_slot_5_axi_bid(),
.m_slot_5_axi_bresp(),
.m_slot_5_axi_bvalid(),
.m_slot_5_axi_bready(),
.m_slot_5_axi_arid(),
.m_slot_5_axi_araddr(),
.m_slot_5_axi_arlen(),
.m_slot_5_axi_arsize(),
.m_slot_5_axi_arburst(),
.m_slot_5_axi_arcache(),
.m_slot_5_axi_arprot(),
.m_slot_5_axi_arlock(),
.m_slot_5_axi_arvalid(),
.m_slot_5_axi_arready(),
.m_slot_5_axi_rid(),
.m_slot_5_axi_rdata(),
.m_slot_5_axi_rresp(),
.m_slot_5_axi_rlast(),
.m_slot_5_axi_rvalid(),
.m_slot_5_axi_rready(),
.m_slot_5_axis_tvalid(),
.m_slot_5_axis_tready(),
.m_slot_5_axis_tdata(),
.m_slot_5_axis_tstrb(),
.m_slot_5_axis_tkeep(),
.m_slot_5_axis_tlast(),
.m_slot_5_axis_tid(),
.m_slot_5_axis_tdest(),
.m_slot_5_axis_tuser(),
.m_slot_6_axi_awid(),
.m_slot_6_axi_awaddr(),
.m_slot_6_axi_awprot(),
.m_slot_6_axi_awlen(),
.m_slot_6_axi_awsize(),
.m_slot_6_axi_awburst(),
.m_slot_6_axi_awcache(),
.m_slot_6_axi_awlock(),
.m_slot_6_axi_awvalid(),
.m_slot_6_axi_awready(),
.m_slot_6_axi_wdata(),
.m_slot_6_axi_wstrb(),
.m_slot_6_axi_wlast(),
.m_slot_6_axi_wvalid(),
.m_slot_6_axi_wready(),
.m_slot_6_axi_bid(),
.m_slot_6_axi_bresp(),
.m_slot_6_axi_bvalid(),
.m_slot_6_axi_bready(),
.m_slot_6_axi_arid(),
.m_slot_6_axi_araddr(),
.m_slot_6_axi_arlen(),
.m_slot_6_axi_arsize(),
.m_slot_6_axi_arburst(),
.m_slot_6_axi_arcache(),
.m_slot_6_axi_arprot(),
.m_slot_6_axi_arlock(),
.m_slot_6_axi_arvalid(),
.m_slot_6_axi_arready(),
.m_slot_6_axi_rid(),
.m_slot_6_axi_rdata(),
.m_slot_6_axi_rresp(),
.m_slot_6_axi_rlast(),
.m_slot_6_axi_rvalid(),
.m_slot_6_axi_rready(),
.m_slot_6_axis_tvalid(),
.m_slot_6_axis_tready(),
.m_slot_6_axis_tdata(),
.m_slot_6_axis_tstrb(),
.m_slot_6_axis_tkeep(),
.m_slot_6_axis_tlast(),
.m_slot_6_axis_tid(),
.m_slot_6_axis_tdest(),
.m_slot_6_axis_tuser(),
.m_slot_7_axi_awid(),
.m_slot_7_axi_awaddr(),
.m_slot_7_axi_awprot(),
.m_slot_7_axi_awlen(),
.m_slot_7_axi_awsize(),
.m_slot_7_axi_awburst(),
.m_slot_7_axi_awcache(),
.m_slot_7_axi_awlock(),
.m_slot_7_axi_awvalid(),
.m_slot_7_axi_awready(),
.m_slot_7_axi_wdata(),
.m_slot_7_axi_wstrb(),
.m_slot_7_axi_wlast(),
.m_slot_7_axi_wvalid(),
.m_slot_7_axi_wready(),
.m_slot_7_axi_bid(),
.m_slot_7_axi_bresp(),
.m_slot_7_axi_bvalid(),
.m_slot_7_axi_bready(),
.m_slot_7_axi_arid(),
.m_slot_7_axi_araddr(),
.m_slot_7_axi_arlen(),
.m_slot_7_axi_arsize(),
.m_slot_7_axi_arburst(),
.m_slot_7_axi_arcache(),
.m_slot_7_axi_arprot(),
.m_slot_7_axi_arlock(),
.m_slot_7_axi_arvalid(),
.m_slot_7_axi_arready(),
.m_slot_7_axi_rid(),
.m_slot_7_axi_rdata(),
.m_slot_7_axi_rresp(),
.m_slot_7_axi_rlast(),
.m_slot_7_axi_rvalid(),
.m_slot_7_axi_rready(),
.m_slot_7_axis_tvalid(),
.m_slot_7_axis_tready(),
.m_slot_7_axis_tdata(),
.m_slot_7_axis_tstrb(),
.m_slot_7_axis_tkeep(),
.m_slot_7_axis_tlast(),
.m_slot_7_axis_tid(),
.m_slot_7_axis_tdest(),
.m_slot_7_axis_tuser(),
.m_slot_8_axi_awid(),
.m_slot_8_axi_awaddr(),
.m_slot_8_axi_awprot(),
.m_slot_8_axi_awlen(),
.m_slot_8_axi_awsize(),
.m_slot_8_axi_awburst(),
.m_slot_8_axi_awcache(),
.m_slot_8_axi_awlock(),
.m_slot_8_axi_awvalid(),
.m_slot_8_axi_awready(),
.m_slot_8_axi_wdata(),
.m_slot_8_axi_wstrb(),
.m_slot_8_axi_wlast(),
.m_slot_8_axi_wvalid(),
.m_slot_8_axi_wready(),
.m_slot_8_axi_bid(),
.m_slot_8_axi_bresp(),
.m_slot_8_axi_bvalid(),
.m_slot_8_axi_bready(),
.m_slot_8_axi_arid(),
.m_slot_8_axi_araddr(),
.m_slot_8_axi_arlen(),
.m_slot_8_axi_arsize(),
.m_slot_8_axi_arburst(),
.m_slot_8_axi_arcache(),
.m_slot_8_axi_arprot(),
.m_slot_8_axi_arlock(),
.m_slot_8_axi_arvalid(),
.m_slot_8_axi_arready(),
.m_slot_8_axi_rid(),
.m_slot_8_axi_rdata(),
.m_slot_8_axi_rresp(),
.m_slot_8_axi_rlast(),
.m_slot_8_axi_rvalid(),
.m_slot_8_axi_rready(),
.m_slot_8_axis_tvalid(),
.m_slot_8_axis_tready(),
.m_slot_8_axis_tdata(),
.m_slot_8_axis_tstrb(),
.m_slot_8_axis_tkeep(),
.m_slot_8_axis_tlast(),
.m_slot_8_axis_tid(),
.m_slot_8_axis_tdest(),
.m_slot_8_axis_tuser(),
.m_slot_9_axi_awid(),
.m_slot_9_axi_awaddr(),
.m_slot_9_axi_awprot(),
.m_slot_9_axi_awlen(),
.m_slot_9_axi_awsize(),
.m_slot_9_axi_awburst(),
.m_slot_9_axi_awcache(),
.m_slot_9_axi_awlock(),
.m_slot_9_axi_awvalid(),
.m_slot_9_axi_awready(),
.m_slot_9_axi_wdata(),
.m_slot_9_axi_wstrb(),
.m_slot_9_axi_wlast(),
.m_slot_9_axi_wvalid(),
.m_slot_9_axi_wready(),
.m_slot_9_axi_bid(),
.m_slot_9_axi_bresp(),
.m_slot_9_axi_bvalid(),
.m_slot_9_axi_bready(),
.m_slot_9_axi_arid(),
.m_slot_9_axi_araddr(),
.m_slot_9_axi_arlen(),
.m_slot_9_axi_arsize(),
.m_slot_9_axi_arburst(),
.m_slot_9_axi_arcache(),
.m_slot_9_axi_arprot(),
.m_slot_9_axi_arlock(),
.m_slot_9_axi_arvalid(),
.m_slot_9_axi_arready(),
.m_slot_9_axi_rid(),
.m_slot_9_axi_rdata(),
.m_slot_9_axi_rresp(),
.m_slot_9_axi_rlast(),
.m_slot_9_axi_rvalid(),
.m_slot_9_axi_rready(),
.m_slot_9_axis_tvalid(),
.m_slot_9_axis_tready(),
.m_slot_9_axis_tdata(),
.m_slot_9_axis_tstrb(),
.m_slot_9_axis_tkeep(),
.m_slot_9_axis_tlast(),
.m_slot_9_axis_tid(),
.m_slot_9_axis_tdest(),
.m_slot_9_axis_tuser(),
.m_slot_10_axi_awid(),
.m_slot_10_axi_awaddr(),
.m_slot_10_axi_awprot(),
.m_slot_10_axi_awlen(),
.m_slot_10_axi_awsize(),
.m_slot_10_axi_awburst(),
.m_slot_10_axi_awcache(),
.m_slot_10_axi_awlock(),
.m_slot_10_axi_awvalid(),
.m_slot_10_axi_awready(),
.m_slot_10_axi_wdata(),
.m_slot_10_axi_wstrb(),
.m_slot_10_axi_wlast(),
.m_slot_10_axi_wvalid(),
.m_slot_10_axi_wready(),
.m_slot_10_axi_bid(),
.m_slot_10_axi_bresp(),
.m_slot_10_axi_bvalid(),
.m_slot_10_axi_bready(),
.m_slot_10_axi_arid(),
.m_slot_10_axi_araddr(),
.m_slot_10_axi_arlen(),
.m_slot_10_axi_arsize(),
.m_slot_10_axi_arburst(),
.m_slot_10_axi_arcache(),
.m_slot_10_axi_arprot(),
.m_slot_10_axi_arlock(),
.m_slot_10_axi_arvalid(),
.m_slot_10_axi_arready(),
.m_slot_10_axi_rid(),
.m_slot_10_axi_rdata(),
.m_slot_10_axi_rresp(),
.m_slot_10_axi_rlast(),
.m_slot_10_axi_rvalid(),
.m_slot_10_axi_rready(),
.m_slot_10_axis_tvalid(),
.m_slot_10_axis_tready(),
.m_slot_10_axis_tdata(),
.m_slot_10_axis_tstrb(),
.m_slot_10_axis_tkeep(),
.m_slot_10_axis_tlast(),
.m_slot_10_axis_tid(),
.m_slot_10_axis_tdest(),
.m_slot_10_axis_tuser(),
.m_slot_11_axi_awid(),
.m_slot_11_axi_awaddr(),
.m_slot_11_axi_awprot(),
.m_slot_11_axi_awlen(),
.m_slot_11_axi_awsize(),
.m_slot_11_axi_awburst(),
.m_slot_11_axi_awcache(),
.m_slot_11_axi_awlock(),
.m_slot_11_axi_awvalid(),
.m_slot_11_axi_awready(),
.m_slot_11_axi_wdata(),
.m_slot_11_axi_wstrb(),
.m_slot_11_axi_wlast(),
.m_slot_11_axi_wvalid(),
.m_slot_11_axi_wready(),
.m_slot_11_axi_bid(),
.m_slot_11_axi_bresp(),
.m_slot_11_axi_bvalid(),
.m_slot_11_axi_bready(),
.m_slot_11_axi_arid(),
.m_slot_11_axi_araddr(),
.m_slot_11_axi_arlen(),
.m_slot_11_axi_arsize(),
.m_slot_11_axi_arburst(),
.m_slot_11_axi_arcache(),
.m_slot_11_axi_arprot(),
.m_slot_11_axi_arlock(),
.m_slot_11_axi_arvalid(),
.m_slot_11_axi_arready(),
.m_slot_11_axi_rid(),
.m_slot_11_axi_rdata(),
.m_slot_11_axi_rresp(),
.m_slot_11_axi_rlast(),
.m_slot_11_axi_rvalid(),
.m_slot_11_axi_rready(),
.m_slot_11_axis_tvalid(),
.m_slot_11_axis_tready(),
.m_slot_11_axis_tdata(),
.m_slot_11_axis_tstrb(),
.m_slot_11_axis_tkeep(),
.m_slot_11_axis_tlast(),
.m_slot_11_axis_tid(),
.m_slot_11_axis_tdest(),
.m_slot_11_axis_tuser(),
.m_slot_12_axi_awid(),
.m_slot_12_axi_awaddr(),
.m_slot_12_axi_awprot(),
.m_slot_12_axi_awlen(),
.m_slot_12_axi_awsize(),
.m_slot_12_axi_awburst(),
.m_slot_12_axi_awcache(),
.m_slot_12_axi_awlock(),
.m_slot_12_axi_awvalid(),
.m_slot_12_axi_awready(),
.m_slot_12_axi_wdata(),
.m_slot_12_axi_wstrb(),
.m_slot_12_axi_wlast(),
.m_slot_12_axi_wvalid(),
.m_slot_12_axi_wready(),
.m_slot_12_axi_bid(),
.m_slot_12_axi_bresp(),
.m_slot_12_axi_bvalid(),
.m_slot_12_axi_bready(),
.m_slot_12_axi_arid(),
.m_slot_12_axi_araddr(),
.m_slot_12_axi_arlen(),
.m_slot_12_axi_arsize(),
.m_slot_12_axi_arburst(),
.m_slot_12_axi_arcache(),
.m_slot_12_axi_arprot(),
.m_slot_12_axi_arlock(),
.m_slot_12_axi_arvalid(),
.m_slot_12_axi_arready(),
.m_slot_12_axi_rid(),
.m_slot_12_axi_rdata(),
.m_slot_12_axi_rresp(),
.m_slot_12_axi_rlast(),
.m_slot_12_axi_rvalid(),
.m_slot_12_axi_rready(),
.m_slot_12_axis_tvalid(),
.m_slot_12_axis_tready(),
.m_slot_12_axis_tdata(),
.m_slot_12_axis_tstrb(),
.m_slot_12_axis_tkeep(),
.m_slot_12_axis_tlast(),
.m_slot_12_axis_tid(),
.m_slot_12_axis_tdest(),
.m_slot_12_axis_tuser(),
.m_slot_13_axi_awid(),
.m_slot_13_axi_awaddr(),
.m_slot_13_axi_awprot(),
.m_slot_13_axi_awlen(),
.m_slot_13_axi_awsize(),
.m_slot_13_axi_awburst(),
.m_slot_13_axi_awcache(),
.m_slot_13_axi_awlock(),
.m_slot_13_axi_awvalid(),
.m_slot_13_axi_awready(),
.m_slot_13_axi_wdata(),
.m_slot_13_axi_wstrb(),
.m_slot_13_axi_wlast(),
.m_slot_13_axi_wvalid(),
.m_slot_13_axi_wready(),
.m_slot_13_axi_bid(),
.m_slot_13_axi_bresp(),
.m_slot_13_axi_bvalid(),
.m_slot_13_axi_bready(),
.m_slot_13_axi_arid(),
.m_slot_13_axi_araddr(),
.m_slot_13_axi_arlen(),
.m_slot_13_axi_arsize(),
.m_slot_13_axi_arburst(),
.m_slot_13_axi_arcache(),
.m_slot_13_axi_arprot(),
.m_slot_13_axi_arlock(),
.m_slot_13_axi_arvalid(),
.m_slot_13_axi_arready(),
.m_slot_13_axi_rid(),
.m_slot_13_axi_rdata(),
.m_slot_13_axi_rresp(),
.m_slot_13_axi_rlast(),
.m_slot_13_axi_rvalid(),
.m_slot_13_axi_rready(),
.m_slot_13_axis_tvalid(),
.m_slot_13_axis_tready(),
.m_slot_13_axis_tdata(),
.m_slot_13_axis_tstrb(),
.m_slot_13_axis_tkeep(),
.m_slot_13_axis_tlast(),
.m_slot_13_axis_tid(),
.m_slot_13_axis_tdest(),
.m_slot_13_axis_tuser(),
.m_slot_14_axi_awid(),
.m_slot_14_axi_awaddr(),
.m_slot_14_axi_awprot(),
.m_slot_14_axi_awlen(),
.m_slot_14_axi_awsize(),
.m_slot_14_axi_awburst(),
.m_slot_14_axi_awcache(),
.m_slot_14_axi_awlock(),
.m_slot_14_axi_awvalid(),
.m_slot_14_axi_awready(),
.m_slot_14_axi_wdata(),
.m_slot_14_axi_wstrb(),
.m_slot_14_axi_wlast(),
.m_slot_14_axi_wvalid(),
.m_slot_14_axi_wready(),
.m_slot_14_axi_bid(),
.m_slot_14_axi_bresp(),
.m_slot_14_axi_bvalid(),
.m_slot_14_axi_bready(),
.m_slot_14_axi_arid(),
.m_slot_14_axi_araddr(),
.m_slot_14_axi_arlen(),
.m_slot_14_axi_arsize(),
.m_slot_14_axi_arburst(),
.m_slot_14_axi_arcache(),
.m_slot_14_axi_arprot(),
.m_slot_14_axi_arlock(),
.m_slot_14_axi_arvalid(),
.m_slot_14_axi_arready(),
.m_slot_14_axi_rid(),
.m_slot_14_axi_rdata(),
.m_slot_14_axi_rresp(),
.m_slot_14_axi_rlast(),
.m_slot_14_axi_rvalid(),
.m_slot_14_axi_rready(),
.m_slot_14_axis_tvalid(),
.m_slot_14_axis_tready(),
.m_slot_14_axis_tdata(),
.m_slot_14_axis_tstrb(),
.m_slot_14_axis_tkeep(),
.m_slot_14_axis_tlast(),
.m_slot_14_axis_tid(),
.m_slot_14_axis_tdest(),
.m_slot_14_axis_tuser(),
.m_slot_15_axi_awid(),
.m_slot_15_axi_awaddr(),
.m_slot_15_axi_awprot(),
.m_slot_15_axi_awlen(),
.m_slot_15_axi_awsize(),
.m_slot_15_axi_awburst(),
.m_slot_15_axi_awcache(),
.m_slot_15_axi_awlock(),
.m_slot_15_axi_awvalid(),
.m_slot_15_axi_awready(),
.m_slot_15_axi_wdata(),
.m_slot_15_axi_wstrb(),
.m_slot_15_axi_wlast(),
.m_slot_15_axi_wvalid(),
.m_slot_15_axi_wready(),
.m_slot_15_axi_bid(),
.m_slot_15_axi_bresp(),
.m_slot_15_axi_bvalid(),
.m_slot_15_axi_bready(),
.m_slot_15_axi_arid(),
.m_slot_15_axi_araddr(),
.m_slot_15_axi_arlen(),
.m_slot_15_axi_arsize(),
.m_slot_15_axi_arburst(),
.m_slot_15_axi_arcache(),
.m_slot_15_axi_arprot(),
.m_slot_15_axi_arlock(),
.m_slot_15_axi_arvalid(),
.m_slot_15_axi_arready(),
.m_slot_15_axi_rid(),
.m_slot_15_axi_rdata(),
.m_slot_15_axi_rresp(),
.m_slot_15_axi_rlast(),
.m_slot_15_axi_rvalid(),
.m_slot_15_axi_rready(),
.m_slot_15_axis_tvalid(),
.m_slot_15_axis_tready(),
.m_slot_15_axis_tdata(),
.m_slot_15_axis_tstrb(),
.m_slot_15_axis_tkeep(),
.m_slot_15_axis_tlast(),
.m_slot_15_axis_tid(),
.m_slot_15_axis_tdest(),
.m_slot_15_axis_tuser(),
.mux_0_axi_awid(),
.mux_0_axi_awaddr(),
.mux_0_axi_awprot(),
.mux_0_axi_awlen(),
.mux_0_axi_awsize(),
.mux_0_axi_awburst(),
.mux_0_axi_awcache(),
.mux_0_axi_awlock(),
.mux_0_axi_awvalid(),
.mux_0_axi_awready(),
.mux_0_axi_wdata(),
.mux_0_axi_wstrb(),
.mux_0_axi_wlast(),
.mux_0_axi_wvalid(),
.mux_0_axi_wready(),
.mux_0_axi_bid(),
.mux_0_axi_bresp(),
.mux_0_axi_bvalid(),
.mux_0_axi_bready(),
.mux_0_axi_arid(),
.mux_0_axi_araddr(),
.mux_0_axi_arlen(),
.mux_0_axi_arsize(),
.mux_0_axi_arburst(),
.mux_0_axi_arcache(),
.mux_0_axi_arprot(),
.mux_0_axi_arlock(),
.mux_0_axi_arvalid(),
.mux_0_axi_arready(),
.mux_0_axi_rid(),
.mux_0_axi_rdata(),
.mux_0_axi_rresp(),
.mux_0_axi_rlast(),
.mux_0_axi_rvalid(),
.mux_0_axi_rready(),
.mux_1_axi_awid(),
.mux_1_axi_awaddr(),
.mux_1_axi_awprot(),
.mux_1_axi_awlen(),
.mux_1_axi_awsize(),
.mux_1_axi_awburst(),
.mux_1_axi_awcache(),
.mux_1_axi_awlock(),
.mux_1_axi_awvalid(),
.mux_1_axi_awready(),
.mux_1_axi_wdata(),
.mux_1_axi_wstrb(),
.mux_1_axi_wlast(),
.mux_1_axi_wvalid(),
.mux_1_axi_wready(),
.mux_1_axi_bid(),
.mux_1_axi_bresp(),
.mux_1_axi_bvalid(),
.mux_1_axi_bready(),
.mux_1_axi_arid(),
.mux_1_axi_araddr(),
.mux_1_axi_arlen(),
.mux_1_axi_arsize(),
.mux_1_axi_arburst(),
.mux_1_axi_arcache(),
.mux_1_axi_arprot(),
.mux_1_axi_arlock(),
.mux_1_axi_arvalid(),
.mux_1_axi_arready(),
.mux_1_axi_rid(),
.mux_1_axi_rdata(),
.mux_1_axi_rresp(),
.mux_1_axi_rlast(),
.mux_1_axi_rvalid(),
.mux_1_axi_rready(),
.mux_2_axi_awid(),
.mux_2_axi_awaddr(),
.mux_2_axi_awprot(),
.mux_2_axi_awlen(),
.mux_2_axi_awsize(),
.mux_2_axi_awburst(),
.mux_2_axi_awcache(),
.mux_2_axi_awlock(),
.mux_2_axi_awvalid(),
.mux_2_axi_awready(),
.mux_2_axi_wdata(),
.mux_2_axi_wstrb(),
.mux_2_axi_wlast(),
.mux_2_axi_wvalid(),
.mux_2_axi_wready(),
.mux_2_axi_bid(),
.mux_2_axi_bresp(),
.mux_2_axi_bvalid(),
.mux_2_axi_bready(),
.mux_2_axi_arid(),
.mux_2_axi_araddr(),
.mux_2_axi_arlen(),
.mux_2_axi_arsize(),
.mux_2_axi_arburst(),
.mux_2_axi_arcache(),
.mux_2_axi_arprot(),
.mux_2_axi_arlock(),
.mux_2_axi_arvalid(),
.mux_2_axi_arready(),
.mux_2_axi_rid(),
.mux_2_axi_rdata(),
.mux_2_axi_rresp(),
.mux_2_axi_rlast(),
.mux_2_axi_rvalid(),
.mux_2_axi_rready(),
.mux_3_axi_awid(),
.mux_3_axi_awaddr(),
.mux_3_axi_awprot(),
.mux_3_axi_awlen(),
.mux_3_axi_awsize(),
.mux_3_axi_awburst(),
.mux_3_axi_awcache(),
.mux_3_axi_awlock(),
.mux_3_axi_awvalid(),
.mux_3_axi_awready(),
.mux_3_axi_wdata(),
.mux_3_axi_wstrb(),
.mux_3_axi_wlast(),
.mux_3_axi_wvalid(),
.mux_3_axi_wready(),
.mux_3_axi_bid(),
.mux_3_axi_bresp(),
.mux_3_axi_bvalid(),
.mux_3_axi_bready(),
.mux_3_axi_arid(),
.mux_3_axi_araddr(),
.mux_3_axi_arlen(),
.mux_3_axi_arsize(),
.mux_3_axi_arburst(),
.mux_3_axi_arcache(),
.mux_3_axi_arprot(),
.mux_3_axi_arlock(),
.mux_3_axi_arvalid(),
.mux_3_axi_arready(),
.mux_3_axi_rid(),
.mux_3_axi_rdata(),
.mux_3_axi_rresp(),
.mux_3_axi_rlast(),
.mux_3_axi_rvalid(),
.mux_3_axi_rready(),
.mux_0_axis_tvalid(),
.mux_0_axis_tready(),
.mux_0_axis_tdata(),
.mux_0_axis_tstrb(),
.mux_0_axis_tkeep(),
.mux_0_axis_tlast(),
.mux_0_axis_tid(),
.mux_0_axis_tdest(),
.mux_0_axis_tuser(),
.mux_1_axis_tvalid(),
.mux_1_axis_tready(),
.mux_1_axis_tdata(),
.mux_1_axis_tstrb(),
.mux_1_axis_tkeep(),
.mux_1_axis_tlast(),
.mux_1_axis_tid(),
.mux_1_axis_tdest(),
.mux_1_axis_tuser(),
.mux_2_axis_tvalid(),
.mux_2_axis_tready(),
.mux_2_axis_tdata(),
.mux_2_axis_tstrb(),
.mux_2_axis_tkeep(),
.mux_2_axis_tlast(),
.mux_2_axis_tid(),
.mux_2_axis_tdest(),
.mux_2_axis_tuser(),
.mux_3_axis_tvalid(),
.mux_3_axis_tready(),
.mux_3_axis_tdata(),
.mux_3_axis_tstrb(),
.mux_3_axis_tkeep(),
.mux_3_axis_tlast(),
.mux_3_axis_tid(),
.mux_3_axis_tdest(),
.mux_3_axis_tuser(),
.sel(16'B0),
.slot_0_axi_awuser(1'B0),
.slot_0_axi_wuser(1'B0),
.slot_0_axi_buser(1'B0),
.slot_0_axi_aruser(1'B0),
.slot_0_axi_ruser(1'B0),
.slot_1_axi_awuser(1'B0),
.slot_1_axi_wuser(1'B0),
.slot_1_axi_buser(1'B0),
.slot_1_axi_aruser(1'B0),
.slot_1_axi_ruser(1'B0),
.slot_2_axi_awuser(1'B0),
.slot_2_axi_wuser(1'B0),
.slot_2_axi_buser(1'B0),
.slot_2_axi_aruser(1'B0),
.slot_2_axi_ruser(1'B0),
.slot_3_axi_awuser(1'B0),
.slot_3_axi_wuser(1'B0),
.slot_3_axi_buser(1'B0),
.slot_3_axi_aruser(1'B0),
.slot_3_axi_ruser(1'B0),
.slot_4_axi_awuser(1'B0),
.slot_4_axi_wuser(1'B0),
.slot_4_axi_buser(1'B0),
.slot_4_axi_aruser(1'B0),
.slot_4_axi_ruser(1'B0),
.slot_5_axi_awuser(1'B0),
.slot_5_axi_wuser(1'B0),
.slot_5_axi_buser(1'B0),
.slot_5_axi_aruser(1'B0),
.slot_5_axi_ruser(1'B0),
.slot_6_axi_awuser(1'B0),
.slot_6_axi_wuser(1'B0),
.slot_6_axi_buser(1'B0),
.slot_6_axi_aruser(1'B0),
.slot_6_axi_ruser(1'B0),
.slot_7_axi_awuser(1'B0),
.slot_7_axi_wuser(1'B0),
.slot_7_axi_buser(1'B0),
.slot_7_axi_aruser(1'B0),
.slot_7_axi_ruser(1'B0),
.slot_8_axi_awuser(1'B0),
.slot_8_axi_wuser(1'B0),
.slot_8_axi_buser(1'B0),
.slot_8_axi_aruser(1'B0),
.slot_8_axi_ruser(1'B0),
.slot_9_axi_awuser(1'B0),
.slot_9_axi_wuser(1'B0),
.slot_9_axi_buser(1'B0),
.slot_9_axi_aruser(1'B0),
.slot_9_axi_ruser(1'B0),
.slot_10_axi_awuser(1'B0),
.slot_10_axi_wuser(1'B0),
.slot_10_axi_buser(1'B0),
.slot_10_axi_aruser(1'B0),
.slot_10_axi_ruser(1'B0),
.slot_11_axi_awuser(1'B0),
.slot_11_axi_wuser(1'B0),
.slot_11_axi_buser(1'B0),
.slot_11_axi_aruser(1'B0),
.slot_11_axi_ruser(1'B0),
.slot_12_axi_awuser(1'B0),
.slot_12_axi_wuser(1'B0),
.slot_12_axi_buser(1'B0),
.slot_12_axi_aruser(1'B0),
.slot_12_axi_ruser(1'B0),
.slot_13_axi_awuser(1'B0),
.slot_13_axi_wuser(1'B0),
.slot_13_axi_buser(1'B0),
.slot_13_axi_aruser(1'B0),
.slot_13_axi_ruser(1'B0),
.slot_14_axi_awuser(1'B0),
.slot_14_axi_wuser(1'B0),
.slot_14_axi_buser(1'B0),
.slot_14_axi_aruser(1'B0),
.slot_14_axi_ruser(1'B0),
.slot_15_axi_awuser(1'B0),
.slot_15_axi_wuser(1'B0),
.slot_15_axi_buser(1'B0),
.slot_15_axi_aruser(1'B0),
.slot_15_axi_ruser(1'B0),
.m_slot_0_axi_awuser(),
.m_slot_0_axi_wuser(),
.m_slot_0_axi_buser(),
.m_slot_0_axi_aruser(),
.m_slot_0_axi_ruser(),
.m_slot_1_axi_awuser(),
.m_slot_1_axi_wuser(),
.m_slot_1_axi_buser(),
.m_slot_1_axi_aruser(),
.m_slot_1_axi_ruser(),
.m_slot_2_axi_awuser(),
.m_slot_2_axi_wuser(),
.m_slot_2_axi_buser(),
.m_slot_2_axi_aruser(),
.m_slot_2_axi_ruser(),
.m_slot_3_axi_awuser(),
.m_slot_3_axi_wuser(),
.m_slot_3_axi_buser(),
.m_slot_3_axi_aruser(),
.m_slot_3_axi_ruser(),
.m_slot_4_axi_awuser(),
.m_slot_4_axi_wuser(),
.m_slot_4_axi_buser(),
.m_slot_4_axi_aruser(),
.m_slot_4_axi_ruser(),
.m_slot_5_axi_awuser(),
.m_slot_5_axi_wuser(),
.m_slot_5_axi_buser(),
.m_slot_5_axi_aruser(),
.m_slot_5_axi_ruser(),
.m_slot_6_axi_awuser(),
.m_slot_6_axi_wuser(),
.m_slot_6_axi_buser(),
.m_slot_6_axi_aruser(),
.m_slot_6_axi_ruser(),
.m_slot_7_axi_awuser(),
.m_slot_7_axi_wuser(),
.m_slot_7_axi_buser(),
.m_slot_7_axi_aruser(),
.m_slot_7_axi_ruser(),
.m_slot_8_axi_awuser(),
.m_slot_8_axi_wuser(),
.m_slot_8_axi_buser(),
.m_slot_8_axi_aruser(),
.m_slot_8_axi_ruser(),
.m_slot_9_axi_awuser(),
.m_slot_9_axi_wuser(),
.m_slot_9_axi_buser(),
.m_slot_9_axi_aruser(),
.m_slot_9_axi_ruser(),
.m_slot_10_axi_awuser(),
.m_slot_10_axi_wuser(),
.m_slot_10_axi_buser(),
.m_slot_10_axi_aruser(),
.m_slot_10_axi_ruser(),
.m_slot_11_axi_awuser(),
.m_slot_11_axi_wuser(),
.m_slot_11_axi_buser(),
.m_slot_11_axi_aruser(),
.m_slot_11_axi_ruser(),
.m_slot_12_axi_awuser(),
.m_slot_12_axi_wuser(),
.m_slot_12_axi_buser(),
.m_slot_12_axi_aruser(),
.m_slot_12_axi_ruser(),
.m_slot_13_axi_awuser(),
.m_slot_13_axi_wuser(),
.m_slot_13_axi_buser(),
.m_slot_13_axi_aruser(),
.m_slot_13_axi_ruser(),
.m_slot_14_axi_awuser(),
.m_slot_14_axi_wuser(),
.m_slot_14_axi_buser(),
.m_slot_14_axi_aruser(),
.m_slot_14_axi_ruser(),
.m_slot_15_axi_awuser(),
.m_slot_15_axi_wuser(),
.m_slot_15_axi_buser(),
.m_slot_15_axi_aruser(),
.m_slot_15_axi_ruser(),
.mux_0_axi_awuser(),
.mux_0_axi_wuser(),
.mux_0_axi_buser(),
.mux_0_axi_aruser(),
.mux_0_axi_ruser(),
.mux_1_axi_awuser(),
.mux_1_axi_wuser(),
.mux_1_axi_buser(),
.mux_1_axi_aruser(),
.mux_1_axi_ruser(),
.mux_2_axi_awuser(),
.mux_2_axi_wuser(),
.mux_2_axi_buser(),
.mux_2_axi_aruser(),
.mux_2_axi_ruser(),
.mux_3_axi_awuser(),
.mux_3_axi_wuser(),
.mux_3_axi_buser(),
.mux_3_axi_aruser(),
.mux_3_axi_ruser(),
.slot_0_axi_awregion(4'B0),
.slot_0_axi_wid(1'B0),
.slot_0_axi_awqos(4'B0),
.slot_0_axi_arregion(4'B0),
.slot_0_axi_arqos(4'B0),
.slot_1_axi_awregion(4'B0),
.slot_1_axi_wid(12'B0),
.slot_1_axi_awqos(slot_1_axi_awqos),
.slot_1_axi_arregion(4'B0),
.slot_1_axi_arqos(slot_1_axi_arqos),
.slot_2_axi_awregion(4'B0),
.slot_2_axi_wid(1'B0),
.slot_2_axi_awqos(4'B0),
.slot_2_axi_arregion(4'B0),
.slot_2_axi_arqos(4'B0),
.slot_3_axi_awregion(4'B0),
.slot_3_axi_wid(1'B0),
.slot_3_axi_awqos(4'B0),
.slot_3_axi_arregion(4'B0),
.slot_3_axi_arqos(4'B0),
.slot_4_axi_awregion(4'B0),
.slot_4_axi_wid(1'B0),
.slot_4_axi_awqos(4'B0),
.slot_4_axi_arregion(4'B0),
.slot_4_axi_arqos(4'B0),
.slot_5_axi_awregion(4'B0),
.slot_5_axi_wid(1'B0),
.slot_5_axi_awqos(4'B0),
.slot_5_axi_arregion(4'B0),
.slot_5_axi_arqos(4'B0),
.slot_6_axi_awregion(4'B0),
.slot_6_axi_wid(1'B0),
.slot_6_axi_awqos(4'B0),
.slot_6_axi_arregion(4'B0),
.slot_6_axi_arqos(4'B0),
.slot_7_axi_awregion(4'B0),
.slot_7_axi_wid(1'B0),
.slot_7_axi_awqos(4'B0),
.slot_7_axi_arregion(4'B0),
.slot_7_axi_arqos(4'B0),
.slot_8_axi_awregion(4'B0),
.slot_8_axi_wid(1'B0),
.slot_8_axi_awqos(4'B0),
.slot_8_axi_arregion(4'B0),
.slot_8_axi_arqos(4'B0),
.slot_9_axi_awregion(4'B0),
.slot_9_axi_wid(1'B0),
.slot_9_axi_awqos(4'B0),
.slot_9_axi_arregion(4'B0),
.slot_9_axi_arqos(4'B0),
.slot_10_axi_awregion(4'B0),
.slot_10_axi_wid(1'B0),
.slot_10_axi_awqos(4'B0),
.slot_10_axi_arregion(4'B0),
.slot_10_axi_arqos(4'B0),
.slot_11_axi_awregion(4'B0),
.slot_11_axi_wid(1'B0),
.slot_11_axi_awqos(4'B0),
.slot_11_axi_arregion(4'B0),
.slot_11_axi_arqos(4'B0),
.slot_12_axi_awregion(4'B0),
.slot_12_axi_wid(1'B0),
.slot_12_axi_awqos(4'B0),
.slot_12_axi_arregion(4'B0),
.slot_12_axi_arqos(4'B0),
.slot_13_axi_awregion(4'B0),
.slot_13_axi_wid(1'B0),
.slot_13_axi_awqos(4'B0),
.slot_13_axi_arregion(4'B0),
.slot_13_axi_arqos(4'B0),
.slot_14_axi_awregion(4'B0),
.slot_14_axi_wid(1'B0),
.slot_14_axi_awqos(4'B0),
.slot_14_axi_arregion(4'B0),
.slot_14_axi_arqos(4'B0),
.slot_15_axi_awregion(4'B0),
.slot_15_axi_wid(1'B0),
.slot_15_axi_awqos(4'B0),
.slot_15_axi_arregion(4'B0),
.slot_15_axi_arqos(4'B0),
.m_slot_0_axi_awregion(),
.m_slot_0_axi_wid(),
.m_slot_0_axi_awqos(),
.m_slot_0_axi_arregion(),
.m_slot_0_axi_arqos(),
.m_slot_1_axi_awregion(),
.m_slot_1_axi_wid(),
.m_slot_1_axi_awqos(m_slot_1_axi_awqos),
.m_slot_1_axi_arregion(),
.m_slot_1_axi_arqos(m_slot_1_axi_arqos),
.m_slot_2_axi_awregion(),
.m_slot_2_axi_wid(),
.m_slot_2_axi_awqos(),
.m_slot_2_axi_arregion(),
.m_slot_2_axi_arqos(),
.m_slot_3_axi_awregion(),
.m_slot_3_axi_wid(),
.m_slot_3_axi_awqos(),
.m_slot_3_axi_arregion(),
.m_slot_3_axi_arqos(),
.m_slot_4_axi_awregion(),
.m_slot_4_axi_wid(),
.m_slot_4_axi_awqos(),
.m_slot_4_axi_arregion(),
.m_slot_4_axi_arqos(),
.m_slot_5_axi_awregion(),
.m_slot_5_axi_wid(),
.m_slot_5_axi_awqos(),
.m_slot_5_axi_arregion(),
.m_slot_5_axi_arqos(),
.m_slot_6_axi_awregion(),
.m_slot_6_axi_wid(),
.m_slot_6_axi_awqos(),
.m_slot_6_axi_arregion(),
.m_slot_6_axi_arqos(),
.m_slot_7_axi_awregion(),
.m_slot_7_axi_wid(),
.m_slot_7_axi_awqos(),
.m_slot_7_axi_arregion(),
.m_slot_7_axi_arqos(),
.m_slot_8_axi_awregion(),
.m_slot_8_axi_wid(),
.m_slot_8_axi_awqos(),
.m_slot_8_axi_arregion(),
.m_slot_8_axi_arqos(),
.m_slot_9_axi_awregion(),
.m_slot_9_axi_wid(),
.m_slot_9_axi_awqos(),
.m_slot_9_axi_arregion(),
.m_slot_9_axi_arqos(),
.m_slot_10_axi_awregion(),
.m_slot_10_axi_wid(),
.m_slot_10_axi_awqos(),
.m_slot_10_axi_arregion(),
.m_slot_10_axi_arqos(),
.m_slot_11_axi_awregion(),
.m_slot_11_axi_wid(),
.m_slot_11_axi_awqos(),
.m_slot_11_axi_arregion(),
.m_slot_11_axi_arqos(),
.m_slot_12_axi_awregion(),
.m_slot_12_axi_wid(),
.m_slot_12_axi_awqos(),
.m_slot_12_axi_arregion(),
.m_slot_12_axi_arqos(),
.m_slot_13_axi_awregion(),
.m_slot_13_axi_wid(),
.m_slot_13_axi_awqos(),
.m_slot_13_axi_arregion(),
.m_slot_13_axi_arqos(),
.m_slot_14_axi_awregion(),
.m_slot_14_axi_wid(),
.m_slot_14_axi_awqos(),
.m_slot_14_axi_arregion(),
.m_slot_14_axi_arqos(),
.m_slot_15_axi_awregion(),
.m_slot_15_axi_wid(),
.m_slot_15_axi_awqos(),
.m_slot_15_axi_arregion(),
.m_slot_15_axi_arqos(),
.mux_0_axi_awregion(),
.mux_0_axi_wid(),
.mux_0_axi_awqos(),
.mux_0_axi_arregion(),
.mux_0_axi_arqos(),
.mux_1_axi_awregion(),
.mux_1_axi_wid(),
.mux_1_axi_awqos(),
.mux_1_axi_arregion(),
.mux_1_axi_arqos(),
.mux_2_axi_awregion(),
.mux_2_axi_wid(),
.mux_2_axi_awqos(),
.mux_2_axi_arregion(),
.mux_2_axi_arqos(),
.mux_3_axi_awregion(),
.mux_3_axi_wid(),
.mux_3_axi_awqos(),
.mux_3_axi_arregion(),
.mux_3_axi_arqos()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_protocol_converter_v2_1_9_axi_protocol_converter,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_auto_pc_4,axi_protocol_converter_v2_1_9_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_auto_pc_4,axi_protocol_converter_v2_1_9_axi_protocol_converter,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=0,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WID\
TH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_auto_pc_4 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [11 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [11 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [11 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [11 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(0),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module basic();
// -------- Variable Section ----------
// --- User Variables ----
reg signed [31:0] A [0:4] [0:12] ;
reg signed [31:0] I ;
reg signed [31:0] J ;
reg signed [31:0] MAXX ;
reg signed [31:0] MAXY ;
// --- Control Bits ----
reg clk ;
reg [63:0] cycle_count ;
reg c_bit_00000_start ;
reg c_bit_00005_dim ;
reg c_bit_00006_00_assign ;
reg c_bit_00006_01_bubble ;
reg c_bit_00007_00_assign ;
reg c_bit_00007_01_bubble ;
reg c_bit_00010_00_assign ;
reg c_bit_00010_01_bubble ;
reg c_bit_00010_02_test_taken ;
reg c_bit_00010_02_test ;
reg c_bit_00020_00_assign ;
reg c_bit_00020_01_bubble ;
reg c_bit_00020_02_test_taken ;
reg c_bit_00020_02_test ;
reg c_bit_00030_00_assign ;
reg c_bit_00030_01_bubble ;
reg c_bit_00035_print ;
reg c_bit_00040_00_test_taken ;
reg c_bit_00040_00_test ;
reg c_bit_00040_01_assign ;
reg c_bit_00040_02_bubble ;
reg c_bit_00050_00_test_taken ;
reg c_bit_00050_00_test ;
reg c_bit_00050_01_assign ;
reg c_bit_00050_02_bubble ;
reg c_bit_00100_end ;
// -------- Initialization Section ----------
initial begin
clk =0 ;
cycle_count =0 ;
c_bit_00000_start = 1 ;
end // initial
// -------- Data Flow Section ----------
always @(posedge clk) begin // dataflow for variable A
if (c_bit_00030_00_assign == 1) begin
A[I][J] <= I + J ;
end
else
begin
end
end
always @(posedge clk) begin // dataflow for variable I
if (c_bit_00010_00_assign == 1) begin
I <= 1 ;
end
else
if (c_bit_00050_01_assign == 1) begin
I <= I + 1 ;
end
else
begin
I <= I ;
end
end
always @(posedge clk) begin // dataflow for variable J
if (c_bit_00020_00_assign == 1) begin
J <= 1 ;
end
else
if (c_bit_00040_01_assign == 1) begin
J <= J + 1 ;
end
else
begin
J <= J ;
end
end
always @(posedge clk) begin // dataflow for variable MAXX
if (c_bit_00006_00_assign == 1) begin
MAXX <= 4 ;
end
else
begin
MAXX <= MAXX ;
end
end
always @(posedge clk) begin // dataflow for variable MAXY
if (c_bit_00007_00_assign == 1) begin
MAXY <= 12 ;
end
else
begin
MAXY <= MAXY ;
end
end
// -------- I/O Section ----------
always @(posedge clk) begin
if (c_bit_00035_print == 1) begin
$display("%0s%0d%0s%0d%0s%0d","I is: ",I," J is: ",J," A(I,J) is: ",A[I][J]);
end
end
// -------- Control Flow Section ----------
always @(posedge clk) begin // control for line 00005_dim
if ( (c_bit_00000_start == 1) ) begin
c_bit_00000_start <= 0; c_bit_00005_dim <= 1 ;
end
else begin
c_bit_00005_dim <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00006_00_assign
if ( (c_bit_00005_dim == 1) ) begin
c_bit_00006_00_assign <= 1 ;
end
else begin
c_bit_00006_00_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00006_01_bubble
if ( (c_bit_00006_00_assign == 1) ) begin
c_bit_00006_01_bubble <= 1 ;
end
else begin
c_bit_00006_01_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00007_00_assign
if ( (c_bit_00006_01_bubble == 1) ) begin
c_bit_00007_00_assign <= 1 ;
end
else begin
c_bit_00007_00_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00007_01_bubble
if ( (c_bit_00007_00_assign == 1) ) begin
c_bit_00007_01_bubble <= 1 ;
end
else begin
c_bit_00007_01_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00010_00_assign
if ( (c_bit_00007_01_bubble == 1) ) begin
c_bit_00010_00_assign <= 1 ;
end
else begin
c_bit_00010_00_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00010_01_bubble
if ( (c_bit_00010_00_assign == 1) ) begin
c_bit_00010_01_bubble <= 1 ;
end
else begin
c_bit_00010_01_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00010_02_test
if ( (c_bit_00010_01_bubble == 1) ) begin
if ( (1) > 0 ) begin
if ( (I) > MAXX) begin
c_bit_00010_02_test_taken <= 1 ; c_bit_00010_02_test <=0 ;
end // loop exit, taken
else begin
c_bit_00010_02_test_taken <= 0; c_bit_00010_02_test <= 1;
end
end else begin
if ( (I) < MAXX) begin
c_bit_00010_02_test_taken <= 1 ; c_bit_00010_02_test <= 0 ;
end // loop exit, taken
else begin
c_bit_00010_02_test_taken <= 0; c_bit_00010_02_test <= 1;
end
end
end
else begin
c_bit_00010_02_test <= 0; c_bit_00010_02_test_taken <=0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00020_00_assign
if ( (c_bit_00010_02_test == 1) || (c_bit_00050_02_bubble == 1) ) begin
c_bit_00020_00_assign <= 1 ;
end
else begin
c_bit_00020_00_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00020_01_bubble
if ( (c_bit_00020_00_assign == 1) ) begin
c_bit_00020_01_bubble <= 1 ;
end
else begin
c_bit_00020_01_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00020_02_test
if ( (c_bit_00020_01_bubble == 1) ) begin
if ( (1) > 0 ) begin
if ( (J) > MAXY) begin
c_bit_00020_02_test_taken <= 1 ; c_bit_00020_02_test <=0 ;
end // loop exit, taken
else begin
c_bit_00020_02_test_taken <= 0; c_bit_00020_02_test <= 1;
end
end else begin
if ( (J) < MAXY) begin
c_bit_00020_02_test_taken <= 1 ; c_bit_00020_02_test <= 0 ;
end // loop exit, taken
else begin
c_bit_00020_02_test_taken <= 0; c_bit_00020_02_test <= 1;
end
end
end
else begin
c_bit_00020_02_test <= 0; c_bit_00020_02_test_taken <=0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00030_00_assign
if ( (c_bit_00020_02_test == 1) || (c_bit_00040_02_bubble == 1) ) begin
c_bit_00030_00_assign <= 1 ;
end
else begin
c_bit_00030_00_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00030_01_bubble
if ( (c_bit_00030_00_assign == 1) ) begin
c_bit_00030_01_bubble <= 1 ;
end
else begin
c_bit_00030_01_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00035_print
if ( (c_bit_00030_01_bubble == 1) ) begin
c_bit_00035_print <= 1 ;
end
else begin
c_bit_00035_print <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00040_00_test
if ( (c_bit_00035_print == 1) ) begin
if ( (1) > 0 ) begin
if ( (J + 1) > MAXY) begin
c_bit_00040_00_test_taken <= 1 ; c_bit_00040_00_test <=0 ;
end // loop exit, taken
else begin
c_bit_00040_00_test_taken <= 0; c_bit_00040_00_test <= 1;
end
end else begin
if ( (J + 1) < MAXY) begin
c_bit_00040_00_test_taken <= 1 ; c_bit_00040_00_test <= 0 ;
end // loop exit, taken
else begin
c_bit_00040_00_test_taken <= 0; c_bit_00040_00_test <= 1;
end
end
end
else begin
c_bit_00040_00_test <= 0; c_bit_00040_00_test_taken <=0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00040_01_assign
if ( (c_bit_00040_00_test == 1) ) begin
c_bit_00040_01_assign <= 1 ;
end
else begin
c_bit_00040_01_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00040_02_bubble
if ( (c_bit_00040_01_assign == 1) ) begin
c_bit_00040_02_bubble <= 1 ;
end
else begin
c_bit_00040_02_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00050_00_test
if ( (c_bit_00040_00_test_taken == 1) || (c_bit_00020_02_test_taken == 1) ) begin
if ( (1) > 0 ) begin
if ( (I + 1) > MAXX) begin
c_bit_00050_00_test_taken <= 1 ; c_bit_00050_00_test <=0 ;
end // loop exit, taken
else begin
c_bit_00050_00_test_taken <= 0; c_bit_00050_00_test <= 1;
end
end else begin
if ( (I + 1) < MAXX) begin
c_bit_00050_00_test_taken <= 1 ; c_bit_00050_00_test <= 0 ;
end // loop exit, taken
else begin
c_bit_00050_00_test_taken <= 0; c_bit_00050_00_test <= 1;
end
end
end
else begin
c_bit_00050_00_test <= 0; c_bit_00050_00_test_taken <=0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00050_01_assign
if ( (c_bit_00050_00_test == 1) ) begin
c_bit_00050_01_assign <= 1 ;
end
else begin
c_bit_00050_01_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00050_02_bubble
if ( (c_bit_00050_01_assign == 1) ) begin
c_bit_00050_02_bubble <= 1 ;
end
else begin
c_bit_00050_02_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00100_end
if ( (c_bit_00100_end == 1) || (c_bit_00050_00_test_taken == 1) ) begin
c_bit_00100_end <= 1 ; $finish;
end
else begin
c_bit_00100_end <= 0 ;
end
end // end @ posedge clk
// -------- Trailer Section ----------
// cycle counter
always @(posedge clk) begin
if (cycle_count > 50000) begin $display("reached maximum cycle count of 50000");
$finish;
end
else begin
cycle_count <= cycle_count + 1 ;
end
end
// clock generator
always
#1 clk = !clk ;
endmodule // basic
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__INV_PP_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_PP_BLACKBOX_V
|
/**********************************************************************
* Felix Winterstein, Imperial College London
*
* File: filtering_algorithm_top_wrapper.v
*
* Revision 1.01
* Additional Comments: distributed under a BSD license, see LICENSE.txt
*
**********************************************************************/
// wrapper for the HLS core and bus bridge
//`define REDUCE_PAR_TO_1
//`define REDUCE_PAR_TO_2
//`define CENTRE_BUFFER_ONCHIP
module filtering_algorithm_top_wrapper (
input ap_clk,
input ap_rst_n,
input ap_start,
output ap_done,
output ap_idle,
output ap_ready,
input [399:0] i_node_data_value_V_dout,
input i_node_data_value_V_empty_n,
output i_node_data_value_V_read,
output writeReq0_0,
output [511:0] writeReq_data0_0,
output [31:0] writeReq_addr0_0,
input writeAck0_0,
output readReq0_0,
output [31:0] readReq_addr0_0,
input readAck0_0,
input [511:0] readReq_data0_0,
output writeReq0_1,
output [7:0] writeReq_data0_1,
output [31:0] writeReq_addr0_1,
input writeAck0_1,
output readReq0_1,
output [31:0] readReq_addr0_1,
input readAck0_1,
input [7:0] readReq_data0_1,
output writeReq0_2,
output [95:0] writeReq_data0_2,
output [31:0] writeReq_addr0_2,
input writeAck0_2,
output readReq0_2,
output [31:0] readReq_addr0_2,
input readAck0_2,
input [95:0] readReq_data0_2,
`ifndef CENTRE_BUFFER_ONCHIP
output writeReq0_3,
output [63:0] writeReq_data0_3,
output [31:0] writeReq_addr0_3,
input writeAck0_3,
output readReq0_3,
output [31:0] readReq_addr0_3,
input readAck0_3,
input [63:0] readReq_data0_3,
output access_critical_region0,
output access_critical_region0_ap_vld,
`endif
output writeReq0_4,
output [31:0] writeReq_data0_4,
output [31:0] writeReq_addr0_4,
input writeAck0_4,
output readReq0_4,
output [31:0] readReq_addr0_4,
input readAck0_4,
input [31:0] readReq_data0_4,
`ifndef REDUCE_PAR_TO_1
output writeReq1_0,
output [511:0] writeReq_data1_0,
output [31:0] writeReq_addr1_0,
input writeAck1_0,
output readReq1_0,
output [31:0] readReq_addr1_0,
input readAck1_0,
input [511:0] readReq_data1_0,
output writeReq1_1,
output [7:0] writeReq_data1_1,
output [31:0] writeReq_addr1_1,
input writeAck1_1,
output readReq1_1,
output [31:0] readReq_addr1_1,
input readAck1_1,
input [7:0] readReq_data1_1,
output writeReq1_2,
output [95:0] writeReq_data1_2,
output [31:0] writeReq_addr1_2,
input writeAck1_2,
output readReq1_2,
output [31:0] readReq_addr1_2,
input readAck1_2,
input [95:0] readReq_data1_2,
`ifndef CENTRE_BUFFER_ONCHIP
output writeReq1_3,
output [63:0] writeReq_data1_3,
output [31:0] writeReq_addr1_3,
input writeAck1_3,
output readReq1_3,
output [31:0] readReq_addr1_3,
input readAck1_3,
input [63:0] readReq_data1_3,
output access_critical_region1,
output access_critical_region1_ap_vld,
`endif
output writeReq1_4,
output [31:0] writeReq_data1_4,
output [31:0] writeReq_addr1_4,
input writeAck1_4,
output readReq1_4,
output [31:0] readReq_addr1_4,
input readAck1_4,
input [31:0] readReq_data1_4,
`ifndef REDUCE_PAR_TO_2
output writeReq2_0,
output [511:0] writeReq_data2_0,
output [31:0] writeReq_addr2_0,
input writeAck2_0,
output readReq2_0,
output [31:0] readReq_addr2_0,
input readAck2_0,
input [511:0] readReq_data2_0,
output writeReq2_1,
output [7:0] writeReq_data2_1,
output [31:0] writeReq_addr2_1,
input writeAck2_1,
output readReq2_1,
output [31:0] readReq_addr2_1,
input readAck2_1,
input [7:0] readReq_data2_1,
output writeReq2_2,
output [95:0] writeReq_data2_2,
output [31:0] writeReq_addr2_2,
input writeAck2_2,
output readReq2_2,
output [31:0] readReq_addr2_2,
input readAck2_2,
input [95:0] readReq_data2_2,
`ifndef CENTRE_BUFFER_ONCHIP
output writeReq2_3,
output [63:0] writeReq_data2_3,
output [31:0] writeReq_addr2_3,
input writeAck2_3,
output readReq2_3,
output [31:0] readReq_addr2_3,
input readAck2_3,
input [63:0] readReq_data2_3,
output access_critical_region2,
output access_critical_region2_ap_vld,
`endif
output writeReq2_4,
output [31:0] writeReq_data2_4,
output [31:0] writeReq_addr2_4,
input writeAck2_4,
output readReq2_4,
output [31:0] readReq_addr2_4,
input readAck2_4,
input [31:0] readReq_data2_4,
output writeReq3_0,
output [511:0] writeReq_data3_0,
output [31:0] writeReq_addr3_0,
input writeAck3_0,
output readReq3_0,
output [31:0] readReq_addr3_0,
input readAck3_0,
input [511:0] readReq_data3_0,
output writeReq3_1,
output [7:0] writeReq_data3_1,
output [31:0] writeReq_addr3_1,
input writeAck3_1,
output readReq3_1,
output [31:0] readReq_addr3_1,
input readAck3_1,
input [7:0] readReq_data3_1,
output writeReq3_2,
output [95:0] writeReq_data3_2,
output [31:0] writeReq_addr3_2,
input writeAck3_2,
output readReq3_2,
output [31:0] readReq_addr3_2,
input readAck3_2,
input [95:0] readReq_data3_2,
`ifndef CENTRE_BUFFER_ONCHIP
output writeReq3_3,
output [63:0] writeReq_data3_3,
output [31:0] writeReq_addr3_3,
input writeAck3_3,
output readReq3_3,
output [31:0] readReq_addr3_3,
input readAck3_3,
input [63:0] readReq_data3_3,
output access_critical_region3,
output access_critical_region3_ap_vld,
`endif
output writeReq3_4,
output [31:0] writeReq_data3_4,
output [31:0] writeReq_addr3_4,
input writeAck3_4,
output readReq3_4,
output [31:0] readReq_addr3_4,
input readAck3_4,
input [31:0] readReq_data3_4,
`endif
`endif
input [47:0] cntr_pos_init_value_V_dout,
input cntr_pos_init_value_V_empty_n,
output cntr_pos_init_value_V_read,
input [31:0] n_V,
input [7:0] k_V,
input [31:0] l,
input [31:0] root_V_dout,
input root_V_empty_n,
output root_V_read,
output [31:0] distortion_out_V_din,
input distortion_out_V_full_n,
output distortion_out_V_write,
output [47:0] clusters_out_value_V_din,
input clusters_out_value_V_full_n,
output clusters_out_value_V_write
);
wire ddr_bus_0_0_V_req_din;
wire ddr_bus_0_0_V_req_full_n;
wire ddr_bus_0_0_V_req_write;
wire ddr_bus_0_0_V_rsp_empty_n;
wire ddr_bus_0_0_V_rsp_read;
wire [31:0] ddr_bus_0_0_V_address;
wire [511:0] ddr_bus_0_0_V_datain;
wire [511:0] ddr_bus_0_0_V_dataout;
wire [31:0] ddr_bus_0_0_V_size;
wire ddr_bus_0_1_V_req_din;
wire ddr_bus_0_1_V_req_full_n;
wire ddr_bus_0_1_V_req_write;
wire ddr_bus_0_1_V_rsp_empty_n;
wire ddr_bus_0_1_V_rsp_read;
wire [31:0] ddr_bus_0_1_V_address;
wire [7:0] ddr_bus_0_1_V_datain;
wire [7:0] ddr_bus_0_1_V_dataout;
wire [31:0] ddr_bus_0_1_V_size;
wire ddr_bus_0_2_V_req_din;
wire ddr_bus_0_2_V_req_full_n;
wire ddr_bus_0_2_V_req_write;
wire ddr_bus_0_2_V_rsp_empty_n;
wire ddr_bus_0_2_V_rsp_read;
wire [31:0] ddr_bus_0_2_V_address;
wire [95:0] ddr_bus_0_2_V_datain;
wire [95:0] ddr_bus_0_2_V_dataout;
wire [31:0] ddr_bus_0_2_V_size;
wire ddr_bus_0_3_V_req_din;
wire ddr_bus_0_3_V_req_full_n;
wire ddr_bus_0_3_V_req_write;
wire ddr_bus_0_3_V_rsp_empty_n;
wire ddr_bus_0_3_V_rsp_read;
wire [31:0] ddr_bus_0_3_V_address;
wire [63:0] ddr_bus_0_3_V_datain;
wire [63:0] ddr_bus_0_3_V_dataout;
wire [31:0] ddr_bus_0_3_V_size;
wire int_access_critical_region0;
wire int_access_critical_region0_ap_vld;
wire ddr_bus_1_0_V_req_din;
wire ddr_bus_1_0_V_req_full_n;
wire ddr_bus_1_0_V_req_write;
wire ddr_bus_1_0_V_rsp_empty_n;
wire ddr_bus_1_0_V_rsp_read;
wire [31:0] ddr_bus_1_0_V_address;
wire [511:0] ddr_bus_1_0_V_datain;
wire [511:0] ddr_bus_1_0_V_dataout;
wire [31:0] ddr_bus_1_0_V_size;
wire ddr_bus_1_1_V_req_din;
wire ddr_bus_1_1_V_req_full_n;
wire ddr_bus_1_1_V_req_write;
wire ddr_bus_1_1_V_rsp_empty_n;
wire ddr_bus_1_1_V_rsp_read;
wire [31:0] ddr_bus_1_1_V_address;
wire [7:0] ddr_bus_1_1_V_datain;
wire [7:0] ddr_bus_1_1_V_dataout;
wire [31:0] ddr_bus_1_1_V_size;
wire ddr_bus_1_2_V_req_din;
wire ddr_bus_1_2_V_req_full_n;
wire ddr_bus_1_2_V_req_write;
wire ddr_bus_1_2_V_rsp_empty_n;
wire ddr_bus_1_2_V_rsp_read;
wire [31:0] ddr_bus_1_2_V_address;
wire [95:0] ddr_bus_1_2_V_datain;
wire [95:0] ddr_bus_1_2_V_dataout;
wire [31:0] ddr_bus_1_2_V_size;
wire ddr_bus_1_3_V_req_din;
wire ddr_bus_1_3_V_req_full_n;
wire ddr_bus_1_3_V_req_write;
wire ddr_bus_1_3_V_rsp_empty_n;
wire ddr_bus_1_3_V_rsp_read;
wire [31:0] ddr_bus_1_3_V_address;
wire [63:0] ddr_bus_1_3_V_datain;
wire [63:0] ddr_bus_1_3_V_dataout;
wire [31:0] ddr_bus_1_3_V_size;
wire int_access_critical_region1;
wire int_access_critical_region1_ap_vld;
wire ddr_bus_2_0_V_req_din;
wire ddr_bus_2_0_V_req_full_n;
wire ddr_bus_2_0_V_req_write;
wire ddr_bus_2_0_V_rsp_empty_n;
wire ddr_bus_2_0_V_rsp_read;
wire [31:0] ddr_bus_2_0_V_address;
wire [511:0] ddr_bus_2_0_V_datain;
wire [511:0] ddr_bus_2_0_V_dataout;
wire [31:0] ddr_bus_2_0_V_size;
wire ddr_bus_2_1_V_req_din;
wire ddr_bus_2_1_V_req_full_n;
wire ddr_bus_2_1_V_req_write;
wire ddr_bus_2_1_V_rsp_empty_n;
wire ddr_bus_2_1_V_rsp_read;
wire [31:0] ddr_bus_2_1_V_address;
wire [7:0] ddr_bus_2_1_V_datain;
wire [7:0] ddr_bus_2_1_V_dataout;
wire [31:0] ddr_bus_2_1_V_size;
wire ddr_bus_2_2_V_req_din;
wire ddr_bus_2_2_V_req_full_n;
wire ddr_bus_2_2_V_req_write;
wire ddr_bus_2_2_V_rsp_empty_n;
wire ddr_bus_2_2_V_rsp_read;
wire [31:0] ddr_bus_2_2_V_address;
wire [95:0] ddr_bus_2_2_V_datain;
wire [95:0] ddr_bus_2_2_V_dataout;
wire [31:0] ddr_bus_2_2_V_size;
wire ddr_bus_2_3_V_req_din;
wire ddr_bus_2_3_V_req_full_n;
wire ddr_bus_2_3_V_req_write;
wire ddr_bus_2_3_V_rsp_empty_n;
wire ddr_bus_2_3_V_rsp_read;
wire [31:0] ddr_bus_2_3_V_address;
wire [63:0] ddr_bus_2_3_V_datain;
wire [63:0] ddr_bus_2_3_V_dataout;
wire [31:0] ddr_bus_2_3_V_size;
wire int_access_critical_region2;
wire int_access_critical_region2_ap_vld;
wire ddr_bus_3_0_V_req_din;
wire ddr_bus_3_0_V_req_full_n;
wire ddr_bus_3_0_V_req_write;
wire ddr_bus_3_0_V_rsp_empty_n;
wire ddr_bus_3_0_V_rsp_read;
wire [31:0] ddr_bus_3_0_V_address;
wire [511:0] ddr_bus_3_0_V_datain;
wire [511:0] ddr_bus_3_0_V_dataout;
wire [31:0] ddr_bus_3_0_V_size;
wire ddr_bus_3_1_V_req_din;
wire ddr_bus_3_1_V_req_full_n;
wire ddr_bus_3_1_V_req_write;
wire ddr_bus_3_1_V_rsp_empty_n;
wire ddr_bus_3_1_V_rsp_read;
wire [31:0] ddr_bus_3_1_V_address;
wire [7:0] ddr_bus_3_1_V_datain;
wire [7:0] ddr_bus_3_1_V_dataout;
wire [31:0] ddr_bus_3_1_V_size;
wire ddr_bus_3_2_V_req_din;
wire ddr_bus_3_2_V_req_full_n;
wire ddr_bus_3_2_V_req_write;
wire ddr_bus_3_2_V_rsp_empty_n;
wire ddr_bus_3_2_V_rsp_read;
wire [31:0] ddr_bus_3_2_V_address;
wire [95:0] ddr_bus_3_2_V_datain;
wire [95:0] ddr_bus_3_2_V_dataout;
wire [31:0] ddr_bus_3_2_V_size;
wire ddr_bus_3_3_V_req_din;
wire ddr_bus_3_3_V_req_full_n;
wire ddr_bus_3_3_V_req_write;
wire ddr_bus_3_3_V_rsp_empty_n;
wire ddr_bus_3_3_V_rsp_read;
wire [31:0] ddr_bus_3_3_V_address;
wire [63:0] ddr_bus_3_3_V_datain;
wire [63:0] ddr_bus_3_3_V_dataout;
wire [31:0] ddr_bus_3_3_V_size;
wire int_access_critical_region3;
wire int_access_critical_region3_ap_vld;
wire freelist_bus_0_1_V_req_din;
wire freelist_bus_0_1_V_req_full_n;
wire freelist_bus_0_1_V_req_write;
wire freelist_bus_0_1_V_rsp_empty_n;
wire freelist_bus_0_1_V_rsp_read;
wire [31:0] freelist_bus_0_1_V_address;
wire [31:0] freelist_bus_0_1_V_datain;
wire [31:0] freelist_bus_0_1_V_dataout;
wire [31:0] freelist_bus_0_1_V_size;
wire freelist_bus_1_1_V_req_din;
wire freelist_bus_1_1_V_req_full_n;
wire freelist_bus_1_1_V_req_write;
wire freelist_bus_1_1_V_rsp_empty_n;
wire freelist_bus_1_1_V_rsp_read;
wire [31:0] freelist_bus_1_1_V_address;
wire [31:0] freelist_bus_1_1_V_datain;
wire [31:0] freelist_bus_1_1_V_dataout;
wire [31:0] freelist_bus_1_1_V_size;
wire freelist_bus_2_1_V_req_din;
wire freelist_bus_2_1_V_req_full_n;
wire freelist_bus_2_1_V_req_write;
wire freelist_bus_2_1_V_rsp_empty_n;
wire freelist_bus_2_1_V_rsp_read;
wire [31:0] freelist_bus_2_1_V_address;
wire [31:0] freelist_bus_2_1_V_datain;
wire [31:0] freelist_bus_2_1_V_dataout;
wire [31:0] freelist_bus_2_1_V_size;
wire freelist_bus_3_1_V_req_din;
wire freelist_bus_3_1_V_req_full_n;
wire freelist_bus_3_1_V_req_write;
wire freelist_bus_3_1_V_rsp_empty_n;
wire freelist_bus_3_1_V_rsp_read;
wire [31:0] freelist_bus_3_1_V_address;
wire [31:0] freelist_bus_3_1_V_datain;
wire [31:0] freelist_bus_3_1_V_dataout;
wire [31:0] freelist_bus_3_1_V_size;
filtering_algorithm_top filtering_algorithm_top_U (
.ap_clk (ap_clk),
.ap_rst_n (ap_rst_n),
.ap_start (ap_start),
.ap_done (ap_done),
.ap_idle (ap_idle),
.ap_ready (ap_ready),
.i_node_data_value_V_dout (i_node_data_value_V_dout),
.i_node_data_value_V_empty_n (i_node_data_value_V_empty_n),
.i_node_data_value_V_read (i_node_data_value_V_read),
.ddr_bus_0_0_value_V_req_din (ddr_bus_0_0_V_req_din),
.ddr_bus_0_0_value_V_req_full_n (ddr_bus_0_0_V_req_full_n),
.ddr_bus_0_0_value_V_req_write (ddr_bus_0_0_V_req_write),
.ddr_bus_0_0_value_V_rsp_empty_n (ddr_bus_0_0_V_rsp_empty_n),
.ddr_bus_0_0_value_V_rsp_read (ddr_bus_0_0_V_rsp_read),
.ddr_bus_0_0_value_V_address (ddr_bus_0_0_V_address),
.ddr_bus_0_0_value_V_datain (ddr_bus_0_0_V_datain),
.ddr_bus_0_0_value_V_dataout (ddr_bus_0_0_V_dataout),
.ddr_bus_0_0_value_V_size (ddr_bus_0_0_V_size),
.ddr_bus_0_1_V_req_din (ddr_bus_0_1_V_req_din),
.ddr_bus_0_1_V_req_full_n (ddr_bus_0_1_V_req_full_n),
.ddr_bus_0_1_V_req_write (ddr_bus_0_1_V_req_write),
.ddr_bus_0_1_V_rsp_empty_n (ddr_bus_0_1_V_rsp_empty_n),
.ddr_bus_0_1_V_rsp_read (ddr_bus_0_1_V_rsp_read),
.ddr_bus_0_1_V_address (ddr_bus_0_1_V_address),
.ddr_bus_0_1_V_datain (ddr_bus_0_1_V_datain),
.ddr_bus_0_1_V_dataout (ddr_bus_0_1_V_dataout),
.ddr_bus_0_1_V_size (ddr_bus_0_1_V_size),
.ddr_bus_0_2_value_V_req_din (ddr_bus_0_2_V_req_din),
.ddr_bus_0_2_value_V_req_full_n (ddr_bus_0_2_V_req_full_n),
.ddr_bus_0_2_value_V_req_write (ddr_bus_0_2_V_req_write),
.ddr_bus_0_2_value_V_rsp_empty_n (ddr_bus_0_2_V_rsp_empty_n),
.ddr_bus_0_2_value_V_rsp_read (ddr_bus_0_2_V_rsp_read),
.ddr_bus_0_2_value_V_address (ddr_bus_0_2_V_address),
.ddr_bus_0_2_value_V_datain (ddr_bus_0_2_V_datain),
.ddr_bus_0_2_value_V_dataout (ddr_bus_0_2_V_dataout),
.ddr_bus_0_2_value_V_size (ddr_bus_0_2_V_size),
.ddr_bus_0_3_V_req_din (ddr_bus_0_3_V_req_din),
.ddr_bus_0_3_V_req_full_n (ddr_bus_0_3_V_req_full_n),
.ddr_bus_0_3_V_req_write (ddr_bus_0_3_V_req_write),
.ddr_bus_0_3_V_rsp_empty_n (ddr_bus_0_3_V_rsp_empty_n),
.ddr_bus_0_3_V_rsp_read (ddr_bus_0_3_V_rsp_read),
.ddr_bus_0_3_V_address (ddr_bus_0_3_V_address),
.ddr_bus_0_3_V_datain (ddr_bus_0_3_V_datain),
.ddr_bus_0_3_V_dataout (ddr_bus_0_3_V_dataout),
.ddr_bus_0_3_V_size (ddr_bus_0_3_V_size),
.access_critical_region0 (access_critical_region0),
.access_critical_region0_ap_vld (access_critical_region0_ap_vld),
.ddr_bus_1_0_value_V_req_din (ddr_bus_1_0_V_req_din),
.ddr_bus_1_0_value_V_req_full_n (ddr_bus_1_0_V_req_full_n),
.ddr_bus_1_0_value_V_req_write (ddr_bus_1_0_V_req_write),
.ddr_bus_1_0_value_V_rsp_empty_n (ddr_bus_1_0_V_rsp_empty_n),
.ddr_bus_1_0_value_V_rsp_read (ddr_bus_1_0_V_rsp_read),
.ddr_bus_1_0_value_V_address (ddr_bus_1_0_V_address),
.ddr_bus_1_0_value_V_datain (ddr_bus_1_0_V_datain),
.ddr_bus_1_0_value_V_dataout (ddr_bus_1_0_V_dataout),
.ddr_bus_1_0_value_V_size (ddr_bus_1_0_V_size),
.ddr_bus_1_1_V_req_din (ddr_bus_1_1_V_req_din),
.ddr_bus_1_1_V_req_full_n (ddr_bus_1_1_V_req_full_n),
.ddr_bus_1_1_V_req_write (ddr_bus_1_1_V_req_write),
.ddr_bus_1_1_V_rsp_empty_n (ddr_bus_1_1_V_rsp_empty_n),
.ddr_bus_1_1_V_rsp_read (ddr_bus_1_1_V_rsp_read),
.ddr_bus_1_1_V_address (ddr_bus_1_1_V_address),
.ddr_bus_1_1_V_datain (ddr_bus_1_1_V_datain),
.ddr_bus_1_1_V_dataout (ddr_bus_1_1_V_dataout),
.ddr_bus_1_1_V_size (ddr_bus_1_1_V_size),
.ddr_bus_1_2_value_V_req_din (ddr_bus_1_2_V_req_din),
.ddr_bus_1_2_value_V_req_full_n (ddr_bus_1_2_V_req_full_n),
.ddr_bus_1_2_value_V_req_write (ddr_bus_1_2_V_req_write),
.ddr_bus_1_2_value_V_rsp_empty_n (ddr_bus_1_2_V_rsp_empty_n),
.ddr_bus_1_2_value_V_rsp_read (ddr_bus_1_2_V_rsp_read),
.ddr_bus_1_2_value_V_address (ddr_bus_1_2_V_address),
.ddr_bus_1_2_value_V_datain (ddr_bus_1_2_V_datain),
.ddr_bus_1_2_value_V_dataout (ddr_bus_1_2_V_dataout),
.ddr_bus_1_2_value_V_size (ddr_bus_1_2_V_size),
.ddr_bus_1_3_V_req_din (ddr_bus_1_3_V_req_din),
.ddr_bus_1_3_V_req_full_n (ddr_bus_1_3_V_req_full_n),
.ddr_bus_1_3_V_req_write (ddr_bus_1_3_V_req_write),
.ddr_bus_1_3_V_rsp_empty_n (ddr_bus_1_3_V_rsp_empty_n),
.ddr_bus_1_3_V_rsp_read (ddr_bus_1_3_V_rsp_read),
.ddr_bus_1_3_V_address (ddr_bus_1_3_V_address),
.ddr_bus_1_3_V_datain (ddr_bus_1_3_V_datain),
.ddr_bus_1_3_V_dataout (ddr_bus_1_3_V_dataout),
.ddr_bus_1_3_V_size (ddr_bus_1_3_V_size),
`ifndef REDUCE_PAR_TO_1
.access_critical_region1 (access_critical_region1),
.access_critical_region1_ap_vld (access_critical_region1_ap_vld),
`endif
.ddr_bus_2_0_value_V_req_din (ddr_bus_2_0_V_req_din),
.ddr_bus_2_0_value_V_req_full_n (ddr_bus_2_0_V_req_full_n),
.ddr_bus_2_0_value_V_req_write (ddr_bus_2_0_V_req_write),
.ddr_bus_2_0_value_V_rsp_empty_n (ddr_bus_2_0_V_rsp_empty_n),
.ddr_bus_2_0_value_V_rsp_read (ddr_bus_2_0_V_rsp_read),
.ddr_bus_2_0_value_V_address (ddr_bus_2_0_V_address),
.ddr_bus_2_0_value_V_datain (ddr_bus_2_0_V_datain),
.ddr_bus_2_0_value_V_dataout (ddr_bus_2_0_V_dataout),
.ddr_bus_2_0_value_V_size (ddr_bus_2_0_V_size),
.ddr_bus_2_1_V_req_din (ddr_bus_2_1_V_req_din),
.ddr_bus_2_1_V_req_full_n (ddr_bus_2_1_V_req_full_n),
.ddr_bus_2_1_V_req_write (ddr_bus_2_1_V_req_write),
.ddr_bus_2_1_V_rsp_empty_n (ddr_bus_2_1_V_rsp_empty_n),
.ddr_bus_2_1_V_rsp_read (ddr_bus_2_1_V_rsp_read),
.ddr_bus_2_1_V_address (ddr_bus_2_1_V_address),
.ddr_bus_2_1_V_datain (ddr_bus_2_1_V_datain),
.ddr_bus_2_1_V_dataout (ddr_bus_2_1_V_dataout),
.ddr_bus_2_1_V_size (ddr_bus_2_1_V_size),
.ddr_bus_2_2_value_V_req_din (ddr_bus_2_2_V_req_din),
.ddr_bus_2_2_value_V_req_full_n (ddr_bus_2_2_V_req_full_n),
.ddr_bus_2_2_value_V_req_write (ddr_bus_2_2_V_req_write),
.ddr_bus_2_2_value_V_rsp_empty_n (ddr_bus_2_2_V_rsp_empty_n),
.ddr_bus_2_2_value_V_rsp_read (ddr_bus_2_2_V_rsp_read),
.ddr_bus_2_2_value_V_address (ddr_bus_2_2_V_address),
.ddr_bus_2_2_value_V_datain (ddr_bus_2_2_V_datain),
.ddr_bus_2_2_value_V_dataout (ddr_bus_2_2_V_dataout),
.ddr_bus_2_2_value_V_size (ddr_bus_2_2_V_size),
.ddr_bus_2_3_V_req_din (ddr_bus_2_3_V_req_din),
.ddr_bus_2_3_V_req_full_n (ddr_bus_2_3_V_req_full_n),
.ddr_bus_2_3_V_req_write (ddr_bus_2_3_V_req_write),
.ddr_bus_2_3_V_rsp_empty_n (ddr_bus_2_3_V_rsp_empty_n),
.ddr_bus_2_3_V_rsp_read (ddr_bus_2_3_V_rsp_read),
.ddr_bus_2_3_V_address (ddr_bus_2_3_V_address),
.ddr_bus_2_3_V_datain (ddr_bus_2_3_V_datain),
.ddr_bus_2_3_V_dataout (ddr_bus_2_3_V_dataout),
.ddr_bus_2_3_V_size (ddr_bus_2_3_V_size),
`ifndef REDUCE_PAR_TO_2
`ifndef REDUCE_PAR_TO_1
.access_critical_region2 (access_critical_region2),
.access_critical_region2_ap_vld (access_critical_region2_ap_vld),
`endif
`endif
.ddr_bus_3_0_value_V_req_din (ddr_bus_3_0_V_req_din),
.ddr_bus_3_0_value_V_req_full_n (ddr_bus_3_0_V_req_full_n),
.ddr_bus_3_0_value_V_req_write (ddr_bus_3_0_V_req_write),
.ddr_bus_3_0_value_V_rsp_empty_n (ddr_bus_3_0_V_rsp_empty_n),
.ddr_bus_3_0_value_V_rsp_read (ddr_bus_3_0_V_rsp_read),
.ddr_bus_3_0_value_V_address (ddr_bus_3_0_V_address),
.ddr_bus_3_0_value_V_datain (ddr_bus_3_0_V_datain),
.ddr_bus_3_0_value_V_dataout (ddr_bus_3_0_V_dataout),
.ddr_bus_3_0_value_V_size (ddr_bus_3_0_V_size),
.ddr_bus_3_1_V_req_din (ddr_bus_3_1_V_req_din),
.ddr_bus_3_1_V_req_full_n (ddr_bus_3_1_V_req_full_n),
.ddr_bus_3_1_V_req_write (ddr_bus_3_1_V_req_write),
.ddr_bus_3_1_V_rsp_empty_n (ddr_bus_3_1_V_rsp_empty_n),
.ddr_bus_3_1_V_rsp_read (ddr_bus_3_1_V_rsp_read),
.ddr_bus_3_1_V_address (ddr_bus_3_1_V_address),
.ddr_bus_3_1_V_datain (ddr_bus_3_1_V_datain),
.ddr_bus_3_1_V_dataout (ddr_bus_3_1_V_dataout),
.ddr_bus_3_1_V_size (ddr_bus_3_1_V_size),
.ddr_bus_3_2_value_V_req_din (ddr_bus_3_2_V_req_din),
.ddr_bus_3_2_value_V_req_full_n (ddr_bus_3_2_V_req_full_n),
.ddr_bus_3_2_value_V_req_write (ddr_bus_3_2_V_req_write),
.ddr_bus_3_2_value_V_rsp_empty_n (ddr_bus_3_2_V_rsp_empty_n),
.ddr_bus_3_2_value_V_rsp_read (ddr_bus_3_2_V_rsp_read),
.ddr_bus_3_2_value_V_address (ddr_bus_3_2_V_address),
.ddr_bus_3_2_value_V_datain (ddr_bus_3_2_V_datain),
.ddr_bus_3_2_value_V_dataout (ddr_bus_3_2_V_dataout),
.ddr_bus_3_2_value_V_size (ddr_bus_3_2_V_size),
.ddr_bus_3_3_V_req_din (ddr_bus_3_3_V_req_din),
.ddr_bus_3_3_V_req_full_n (ddr_bus_3_3_V_req_full_n),
.ddr_bus_3_3_V_req_write (ddr_bus_3_3_V_req_write),
.ddr_bus_3_3_V_rsp_empty_n (ddr_bus_3_3_V_rsp_empty_n),
.ddr_bus_3_3_V_rsp_read (ddr_bus_3_3_V_rsp_read),
.ddr_bus_3_3_V_address (ddr_bus_3_3_V_address),
.ddr_bus_3_3_V_datain (ddr_bus_3_3_V_datain),
.ddr_bus_3_3_V_dataout (ddr_bus_3_3_V_dataout),
.ddr_bus_3_3_V_size (ddr_bus_3_3_V_size),
`ifndef REDUCE_PAR_TO_2
`ifndef REDUCE_PAR_TO_1
.access_critical_region3 (access_critical_region3),
.access_critical_region3_ap_vld (access_critical_region3_ap_vld),
`endif
`endif
.freelist_bus_0_1_V_req_din (freelist_bus_0_1_V_req_din),
.freelist_bus_0_1_V_req_full_n (freelist_bus_0_1_V_req_full_n),
.freelist_bus_0_1_V_req_write (freelist_bus_0_1_V_req_write),
.freelist_bus_0_1_V_rsp_empty_n (freelist_bus_0_1_V_rsp_empty_n),
.freelist_bus_0_1_V_rsp_read (freelist_bus_0_1_V_rsp_read),
.freelist_bus_0_1_V_address (freelist_bus_0_1_V_address),
.freelist_bus_0_1_V_datain (freelist_bus_0_1_V_datain),
.freelist_bus_0_1_V_dataout (freelist_bus_0_1_V_dataout),
.freelist_bus_0_1_V_size (freelist_bus_0_1_V_size),
.freelist_bus_1_1_V_req_din (freelist_bus_1_1_V_req_din),
.freelist_bus_1_1_V_req_full_n (freelist_bus_1_1_V_req_full_n),
.freelist_bus_1_1_V_req_write (freelist_bus_1_1_V_req_write),
.freelist_bus_1_1_V_rsp_empty_n (freelist_bus_1_1_V_rsp_empty_n),
.freelist_bus_1_1_V_rsp_read (freelist_bus_1_1_V_rsp_read),
.freelist_bus_1_1_V_address (freelist_bus_1_1_V_address),
.freelist_bus_1_1_V_datain (freelist_bus_1_1_V_datain),
.freelist_bus_1_1_V_dataout (freelist_bus_1_1_V_dataout),
.freelist_bus_1_1_V_size (freelist_bus_1_1_V_size),
.freelist_bus_2_1_V_req_din (freelist_bus_2_1_V_req_din),
.freelist_bus_2_1_V_req_full_n (freelist_bus_2_1_V_req_full_n),
.freelist_bus_2_1_V_req_write (freelist_bus_2_1_V_req_write),
.freelist_bus_2_1_V_rsp_empty_n (freelist_bus_2_1_V_rsp_empty_n),
.freelist_bus_2_1_V_rsp_read (freelist_bus_2_1_V_rsp_read),
.freelist_bus_2_1_V_address (freelist_bus_2_1_V_address),
.freelist_bus_2_1_V_datain (freelist_bus_2_1_V_datain),
.freelist_bus_2_1_V_dataout (freelist_bus_2_1_V_dataout),
.freelist_bus_2_1_V_size (freelist_bus_2_1_V_size),
.freelist_bus_3_1_V_req_din (freelist_bus_3_1_V_req_din),
.freelist_bus_3_1_V_req_full_n (freelist_bus_3_1_V_req_full_n),
.freelist_bus_3_1_V_req_write (freelist_bus_3_1_V_req_write),
.freelist_bus_3_1_V_rsp_empty_n (freelist_bus_3_1_V_rsp_empty_n),
.freelist_bus_3_1_V_rsp_read (freelist_bus_3_1_V_rsp_read),
.freelist_bus_3_1_V_address (freelist_bus_3_1_V_address),
.freelist_bus_3_1_V_datain (freelist_bus_3_1_V_datain),
.freelist_bus_3_1_V_dataout (freelist_bus_3_1_V_dataout),
.freelist_bus_3_1_V_size (freelist_bus_3_1_V_size),
.cntr_pos_init_value_V_dout (cntr_pos_init_value_V_dout),
.cntr_pos_init_value_V_empty_n (cntr_pos_init_value_V_empty_n),
.cntr_pos_init_value_V_read (cntr_pos_init_value_V_read),
.n_V (n_V),
.k_V (k_V),
.l (l),
.root_V_dout (root_V_dout),
.root_V_empty_n (root_V_empty_n),
.root_V_read (root_V_read),
.distortion_out_V_din (distortion_out_V_din),
.distortion_out_V_full_n (distortion_out_V_full_n),
.distortion_out_V_write (distortion_out_V_write),
.clusters_out_value_V_din (clusters_out_value_V_din),
.clusters_out_value_V_full_n (clusters_out_value_V_full_n),
.clusters_out_value_V_write (clusters_out_value_V_write)
);
bus_bridge #(
.DATA_WIDTH ( 512 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U0_0 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_0_0_V_rsp_empty_n),
.rsp_full_n (ddr_bus_0_0_V_req_full_n),
.req_write (ddr_bus_0_0_V_req_write),
.req_din (ddr_bus_0_0_V_req_din),
.rsp_read (ddr_bus_0_0_V_rsp_read),
.address (ddr_bus_0_0_V_address),
.size (ddr_bus_0_0_V_size),
.dataout (ddr_bus_0_0_V_dataout),
.datain (ddr_bus_0_0_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq0_0),
.writeReq_data (writeReq_data0_0),
.writeReq_addr (writeReq_addr0_0),
.writeAck (writeAck0_0),
.readReq (readReq0_0),
.readReq_addr (readReq_addr0_0),
.readAck (readAck0_0),
.readReq_data (readReq_data0_0)
);
bus_bridge #(
.DATA_WIDTH ( 8 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U0_1 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_0_1_V_rsp_empty_n),
.rsp_full_n (ddr_bus_0_1_V_req_full_n),
.req_write (ddr_bus_0_1_V_req_write),
.req_din (ddr_bus_0_1_V_req_din),
.rsp_read (ddr_bus_0_1_V_rsp_read),
.address (ddr_bus_0_1_V_address),
.size (ddr_bus_0_1_V_size),
.dataout (ddr_bus_0_1_V_dataout),
.datain (ddr_bus_0_1_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq0_1),
.writeReq_data (writeReq_data0_1),
.writeReq_addr (writeReq_addr0_1),
.writeAck (writeAck0_1),
.readReq (readReq0_1),
.readReq_addr (readReq_addr0_1),
.readAck (readAck0_1),
.readReq_data (readReq_data0_1)
);
bus_bridge #(
.DATA_WIDTH ( 96 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U0_2 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_0_2_V_rsp_empty_n),
.rsp_full_n (ddr_bus_0_2_V_req_full_n),
.req_write (ddr_bus_0_2_V_req_write),
.req_din (ddr_bus_0_2_V_req_din),
.rsp_read (ddr_bus_0_2_V_rsp_read),
.address (ddr_bus_0_2_V_address),
.size (ddr_bus_0_2_V_size),
.dataout (ddr_bus_0_2_V_dataout),
.datain (ddr_bus_0_2_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq0_2),
.writeReq_data (writeReq_data0_2),
.writeReq_addr (writeReq_addr0_2),
.writeAck (writeAck0_2),
.readReq (readReq0_2),
.readReq_addr (readReq_addr0_2),
.readAck (readAck0_2),
.readReq_data (readReq_data0_2)
);
bus_bridge #(
.DATA_WIDTH ( 32 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U0_4 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (freelist_bus_0_1_V_rsp_empty_n),
.rsp_full_n (freelist_bus_0_1_V_req_full_n),
.req_write (freelist_bus_0_1_V_req_write),
.req_din (freelist_bus_0_1_V_req_din),
.rsp_read (freelist_bus_0_1_V_rsp_read),
.address (freelist_bus_0_1_V_address),
.size (freelist_bus_0_1_V_size),
.dataout (freelist_bus_0_1_V_dataout),
.datain (freelist_bus_0_1_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq0_4),
.writeReq_data (writeReq_data0_4),
.writeReq_addr (writeReq_addr0_4),
.writeAck (writeAck0_4),
.readReq (readReq0_4),
.readReq_addr (readReq_addr0_4),
.readAck (readAck0_4),
.readReq_data (readReq_data0_4)
);
`ifndef CENTRE_BUFFER_ONCHIP
bus_bridge #(
.DATA_WIDTH ( 64 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U0_3 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_0_3_V_rsp_empty_n),
.rsp_full_n (ddr_bus_0_3_V_req_full_n),
.req_write (ddr_bus_0_3_V_req_write),
.req_din (ddr_bus_0_3_V_req_din),
.rsp_read (ddr_bus_0_3_V_rsp_read),
.address (ddr_bus_0_3_V_address),
.size (ddr_bus_0_3_V_size),
.dataout (ddr_bus_0_3_V_dataout),
.datain (ddr_bus_0_3_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq0_3),
.writeReq_data (writeReq_data0_3),
.writeReq_addr (writeReq_addr0_3),
.writeAck (writeAck0_3),
.readReq (readReq0_3),
.readReq_addr (readReq_addr0_3),
.readAck (readAck0_3),
.readReq_data (readReq_data0_3)
);
`endif
`ifndef REDUCE_PAR_TO_1
bus_bridge #(
.DATA_WIDTH ( 512 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U1_0 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_1_0_V_rsp_empty_n),
.rsp_full_n (ddr_bus_1_0_V_req_full_n),
.req_write (ddr_bus_1_0_V_req_write),
.req_din (ddr_bus_1_0_V_req_din),
.rsp_read (ddr_bus_1_0_V_rsp_read),
.address (ddr_bus_1_0_V_address),
.size (ddr_bus_1_0_V_size),
.dataout (ddr_bus_1_0_V_dataout),
.datain (ddr_bus_1_0_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq1_0),
.writeReq_data (writeReq_data1_0),
.writeReq_addr (writeReq_addr1_0),
.writeAck (writeAck1_0),
.readReq (readReq1_0),
.readReq_addr (readReq_addr1_0),
.readAck (readAck1_0),
.readReq_data (readReq_data1_0)
);
bus_bridge #(
.DATA_WIDTH ( 8 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U1_1 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_1_1_V_rsp_empty_n),
.rsp_full_n (ddr_bus_1_1_V_req_full_n),
.req_write (ddr_bus_1_1_V_req_write),
.req_din (ddr_bus_1_1_V_req_din),
.rsp_read (ddr_bus_1_1_V_rsp_read),
.address (ddr_bus_1_1_V_address),
.size (ddr_bus_1_1_V_size),
.dataout (ddr_bus_1_1_V_dataout),
.datain (ddr_bus_1_1_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq1_1),
.writeReq_data (writeReq_data1_1),
.writeReq_addr (writeReq_addr1_1),
.writeAck (writeAck1_1),
.readReq (readReq1_1),
.readReq_addr (readReq_addr1_1),
.readAck (readAck1_1),
.readReq_data (readReq_data1_1)
);
bus_bridge #(
.DATA_WIDTH ( 96 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U1_2 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_1_2_V_rsp_empty_n),
.rsp_full_n (ddr_bus_1_2_V_req_full_n),
.req_write (ddr_bus_1_2_V_req_write),
.req_din (ddr_bus_1_2_V_req_din),
.rsp_read (ddr_bus_1_2_V_rsp_read),
.address (ddr_bus_1_2_V_address),
.size (ddr_bus_1_2_V_size),
.dataout (ddr_bus_1_2_V_dataout),
.datain (ddr_bus_1_2_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq1_2),
.writeReq_data (writeReq_data1_2),
.writeReq_addr (writeReq_addr1_2),
.writeAck (writeAck1_2),
.readReq (readReq1_2),
.readReq_addr (readReq_addr1_2),
.readAck (readAck1_2),
.readReq_data (readReq_data1_2)
);
bus_bridge #(
.DATA_WIDTH ( 32 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U1_4 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (freelist_bus_1_1_V_rsp_empty_n),
.rsp_full_n (freelist_bus_1_1_V_req_full_n),
.req_write (freelist_bus_1_1_V_req_write),
.req_din (freelist_bus_1_1_V_req_din),
.rsp_read (freelist_bus_1_1_V_rsp_read),
.address (freelist_bus_1_1_V_address),
.size (freelist_bus_1_1_V_size),
.dataout (freelist_bus_1_1_V_dataout),
.datain (freelist_bus_1_1_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq1_4),
.writeReq_data (writeReq_data1_4),
.writeReq_addr (writeReq_addr1_4),
.writeAck (writeAck1_4),
.readReq (readReq1_4),
.readReq_addr (readReq_addr1_4),
.readAck (readAck1_4),
.readReq_data (readReq_data1_4)
);
`ifndef CENTRE_BUFFER_ONCHIP
bus_bridge #(
.DATA_WIDTH ( 64 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U1_3 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_1_3_V_rsp_empty_n),
.rsp_full_n (ddr_bus_1_3_V_req_full_n),
.req_write (ddr_bus_1_3_V_req_write),
.req_din (ddr_bus_1_3_V_req_din),
.rsp_read (ddr_bus_1_3_V_rsp_read),
.address (ddr_bus_1_3_V_address),
.size (ddr_bus_1_3_V_size),
.dataout (ddr_bus_1_3_V_dataout),
.datain (ddr_bus_1_3_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq1_3),
.writeReq_data (writeReq_data1_3),
.writeReq_addr (writeReq_addr1_3),
.writeAck (writeAck1_3),
.readReq (readReq1_3),
.readReq_addr (readReq_addr1_3),
.readAck (readAck1_3),
.readReq_data (readReq_data1_3)
);
`endif
`ifndef REDUCE_PAR_TO_2
bus_bridge #(
.DATA_WIDTH ( 512 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U2_0 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_2_0_V_rsp_empty_n),
.rsp_full_n (ddr_bus_2_0_V_req_full_n),
.req_write (ddr_bus_2_0_V_req_write),
.req_din (ddr_bus_2_0_V_req_din),
.rsp_read (ddr_bus_2_0_V_rsp_read),
.address (ddr_bus_2_0_V_address),
.size (ddr_bus_2_0_V_size),
.dataout (ddr_bus_2_0_V_dataout),
.datain (ddr_bus_2_0_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq2_0),
.writeReq_data (writeReq_data2_0),
.writeReq_addr (writeReq_addr2_0),
.writeAck (writeAck2_0),
.readReq (readReq2_0),
.readReq_addr (readReq_addr2_0),
.readAck (readAck2_0),
.readReq_data (readReq_data2_0)
);
bus_bridge #(
.DATA_WIDTH ( 8 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U2_1 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_2_1_V_rsp_empty_n),
.rsp_full_n (ddr_bus_2_1_V_req_full_n),
.req_write (ddr_bus_2_1_V_req_write),
.req_din (ddr_bus_2_1_V_req_din),
.rsp_read (ddr_bus_2_1_V_rsp_read),
.address (ddr_bus_2_1_V_address),
.size (ddr_bus_2_1_V_size),
.dataout (ddr_bus_2_1_V_dataout),
.datain (ddr_bus_2_1_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq2_1),
.writeReq_data (writeReq_data2_1),
.writeReq_addr (writeReq_addr2_1),
.writeAck (writeAck2_1),
.readReq (readReq2_1),
.readReq_addr (readReq_addr2_1),
.readAck (readAck2_1),
.readReq_data (readReq_data2_1)
);
bus_bridge #(
.DATA_WIDTH ( 96 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U2_2 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_2_2_V_rsp_empty_n),
.rsp_full_n (ddr_bus_2_2_V_req_full_n),
.req_write (ddr_bus_2_2_V_req_write),
.req_din (ddr_bus_2_2_V_req_din),
.rsp_read (ddr_bus_2_2_V_rsp_read),
.address (ddr_bus_2_2_V_address),
.size (ddr_bus_2_2_V_size),
.dataout (ddr_bus_2_2_V_dataout),
.datain (ddr_bus_2_2_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq2_2),
.writeReq_data (writeReq_data2_2),
.writeReq_addr (writeReq_addr2_2),
.writeAck (writeAck2_2),
.readReq (readReq2_2),
.readReq_addr (readReq_addr2_2),
.readAck (readAck2_2),
.readReq_data (readReq_data2_2)
);
bus_bridge #(
.DATA_WIDTH ( 32 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U2_4 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (freelist_bus_2_1_V_rsp_empty_n),
.rsp_full_n (freelist_bus_2_1_V_req_full_n),
.req_write (freelist_bus_2_1_V_req_write),
.req_din (freelist_bus_2_1_V_req_din),
.rsp_read (freelist_bus_2_1_V_rsp_read),
.address (freelist_bus_2_1_V_address),
.size (freelist_bus_2_1_V_size),
.dataout (freelist_bus_2_1_V_dataout),
.datain (freelist_bus_2_1_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq2_4),
.writeReq_data (writeReq_data2_4),
.writeReq_addr (writeReq_addr2_4),
.writeAck (writeAck2_4),
.readReq (readReq2_4),
.readReq_addr (readReq_addr2_4),
.readAck (readAck2_4),
.readReq_data (readReq_data2_4)
);
`ifndef CENTRE_BUFFER_ONCHIP
bus_bridge #(
.DATA_WIDTH ( 64 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U2_3 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_2_3_V_rsp_empty_n),
.rsp_full_n (ddr_bus_2_3_V_req_full_n),
.req_write (ddr_bus_2_3_V_req_write),
.req_din (ddr_bus_2_3_V_req_din),
.rsp_read (ddr_bus_2_3_V_rsp_read),
.address (ddr_bus_2_3_V_address),
.size (ddr_bus_2_3_V_size),
.dataout (ddr_bus_2_3_V_dataout),
.datain (ddr_bus_2_3_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq2_3),
.writeReq_data (writeReq_data2_3),
.writeReq_addr (writeReq_addr2_3),
.writeAck (writeAck2_3),
.readReq (readReq2_3),
.readReq_addr (readReq_addr2_3),
.readAck (readAck2_3),
.readReq_data (readReq_data2_3)
);
`endif
bus_bridge #(
.DATA_WIDTH ( 512 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U3_0 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_3_0_V_rsp_empty_n),
.rsp_full_n (ddr_bus_3_0_V_req_full_n),
.req_write (ddr_bus_3_0_V_req_write),
.req_din (ddr_bus_3_0_V_req_din),
.rsp_read (ddr_bus_3_0_V_rsp_read),
.address (ddr_bus_3_0_V_address),
.size (ddr_bus_3_0_V_size),
.dataout (ddr_bus_3_0_V_dataout),
.datain (ddr_bus_3_0_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq3_0),
.writeReq_data (writeReq_data3_0),
.writeReq_addr (writeReq_addr3_0),
.writeAck (writeAck3_0),
.readReq (readReq3_0),
.readReq_addr (readReq_addr3_0),
.readAck (readAck3_0),
.readReq_data (readReq_data3_0)
);
bus_bridge #(
.DATA_WIDTH ( 8 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U3_1 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_3_1_V_rsp_empty_n),
.rsp_full_n (ddr_bus_3_1_V_req_full_n),
.req_write (ddr_bus_3_1_V_req_write),
.req_din (ddr_bus_3_1_V_req_din),
.rsp_read (ddr_bus_3_1_V_rsp_read),
.address (ddr_bus_3_1_V_address),
.size (ddr_bus_3_1_V_size),
.dataout (ddr_bus_3_1_V_dataout),
.datain (ddr_bus_3_1_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq3_1),
.writeReq_data (writeReq_data3_1),
.writeReq_addr (writeReq_addr3_1),
.writeAck (writeAck3_1),
.readReq (readReq3_1),
.readReq_addr (readReq_addr3_1),
.readAck (readAck3_1),
.readReq_data (readReq_data3_1)
);
bus_bridge #(
.DATA_WIDTH ( 96 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U3_2 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_3_2_V_rsp_empty_n),
.rsp_full_n (ddr_bus_3_2_V_req_full_n),
.req_write (ddr_bus_3_2_V_req_write),
.req_din (ddr_bus_3_2_V_req_din),
.rsp_read (ddr_bus_3_2_V_rsp_read),
.address (ddr_bus_3_2_V_address),
.size (ddr_bus_3_2_V_size),
.dataout (ddr_bus_3_2_V_dataout),
.datain (ddr_bus_3_2_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq3_2),
.writeReq_data (writeReq_data3_2),
.writeReq_addr (writeReq_addr3_2),
.writeAck (writeAck3_2),
.readReq (readReq3_2),
.readReq_addr (readReq_addr3_2),
.readAck (readAck3_2),
.readReq_data (readReq_data3_2)
);
bus_bridge #(
.DATA_WIDTH ( 32 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U3_4 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (freelist_bus_3_1_V_rsp_empty_n),
.rsp_full_n (freelist_bus_3_1_V_req_full_n),
.req_write (freelist_bus_3_1_V_req_write),
.req_din (freelist_bus_3_1_V_req_din),
.rsp_read (freelist_bus_3_1_V_rsp_read),
.address (freelist_bus_3_1_V_address),
.size (freelist_bus_3_1_V_size),
.dataout (freelist_bus_3_1_V_dataout),
.datain (freelist_bus_3_1_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq3_4),
.writeReq_data (writeReq_data3_4),
.writeReq_addr (writeReq_addr3_4),
.writeAck (writeAck3_4),
.readReq (readReq3_4),
.readReq_addr (readReq_addr3_4),
.readAck (readAck3_4),
.readReq_data (readReq_data3_4)
);
`ifndef CENTRE_BUFFER_ONCHIP
bus_bridge #(
.DATA_WIDTH ( 64 ),
.ADDR_WIDTH ( 32 )
)
bus_bridge_U3_3 (
.clk (ap_clk),
.rst_n (ap_rst_n),
// interface to the HLS core
.rsp_empty_n (ddr_bus_3_3_V_rsp_empty_n),
.rsp_full_n (ddr_bus_3_3_V_req_full_n),
.req_write (ddr_bus_3_3_V_req_write),
.req_din (ddr_bus_3_3_V_req_din),
.rsp_read (ddr_bus_3_3_V_rsp_read),
.address (ddr_bus_3_3_V_address),
.size (ddr_bus_3_3_V_size),
.dataout (ddr_bus_3_3_V_dataout),
.datain (ddr_bus_3_3_V_datain),
// req/resp/write interface to leap
.writeReq (writeReq3_3),
.writeReq_data (writeReq_data3_3),
.writeReq_addr (writeReq_addr3_3),
.writeAck (writeAck3_3),
.readReq (readReq3_3),
.readReq_addr (readReq_addr3_3),
.readAck (readAck3_3),
.readReq_data (readReq_data3_3)
);
`endif
`endif
`endif
endmodule
|
`define simu
//
module TOP_SYS(
clk100,rstn,
// uart
TXD,RXD,
// DDR2
DDR2DQ,
DDR2DQS_N,
DDR2DQS_P,
DDR2ADDR,
DDR2BA,
DDR2RAS_N,
DDR2CAS_N,
DDR2WE_N,
DDR2CK_P,
DDR2CK_N,
DDR2CKE,
DDR2CS_N,
DDR2DM,
DDR2ODT,
// spi flash
sdin,sdout,sdwp,sdhld,sdcs,sdreset,
// gpio it87xx
gpioA,gpioB,
// ethernet
PhyMdc,
PhyMdio,
PhyRstn,
PhyCrs,
PhyRxErr,
PhyRxd,
PhyTxEn,
PhyTxd,
PhyClk50Mhz,
// tiny spi
miso,
mosi,
sclk,
aclInt1,
aclInt2,
debug
);
input clk100;
input rstn;
output TXD;
wire [6:0] gpio_in;
inout wire [15:0] DDR2DQ;
inout wire [1:0] DDR2DQS_N;
inout wire [1:0] DDR2DQS_P;
output wire [12:0] DDR2ADDR;
output wire [2:0] DDR2BA;
output wire DDR2RAS_N;
output wire DDR2CAS_N;
output wire DDR2WE_N;
output wire DDR2CK_P;
output wire DDR2CK_N;
output wire DDR2CKE;
output wire DDR2CS_N;
output wire [1:0] DDR2DM;
output wire DDR2ODT;
input RXD;
output sdout,sdwp,sdhld,sdcs;
input sdin;
inout [7:0] gpioA,gpioB;
//input extWAIT;
output reg sdreset;
// tiny spi
output mosi;
input miso;
output sclk;
input aclInt1,aclInt2;
// ethernet
output PhyMdc;
inout PhyMdio;
wire PhyMdio_t;
wire PhyMdio_o;
wire PhyMdio_i;
wire int_net;
output PhyRstn;
output PhyCrs;
input PhyRxErr;
input [1:0] PhyRxd;
output PhyTxEn;
output [1:0] PhyTxd;
output reg PhyClk50Mhz;
output reg [3:0] debug;
wire [4:0] debug_int;
wire rmii2mac_tx_clk;
wire rmii2mac_rx_clk;
wire rmii2mac_crs;
wire rmii2mac_rx_dv;
wire [3:0] rmii2mac_rxd;
wire rmii2mac_col;
wire rmii2mac_rx_er;
wire mac2rmii_tx_en;
wire [3:0] mac2rmii_txd;
wire mac2rmii_tx_er;
// axi cpu bus
wire [31:0] M_AXI_AW, M_AXI_AR;
wire M_AXI_AWVALID,M_AXI_ARVALID,M_AXI_WVALID,M_AXI_RREADY;
wire M_AXI_AWREADY,M_AXI_ARREADY,M_AXI_WREADY,M_AXI_RVALID,M_AXI_RLAST,M_AXI_WLAST;
wire [31:0] M_AXI_R;
wire [31:0] M_AXI_W;
wire [3:0] M_AXI_WSTRB;
wire [1:0] M_AXI_ARBURST;
wire [7:0] M_AXI_ARLEN;
wire [2:0] M_AXI_ARSIZE;
wire [1:0] M_AXI_AWBURST;
wire [7:0] M_AXI_AWLEN;
wire [2:0] M_AXI_AWSIZE;
// axi ram bus
wire [31:0] S_AXI_AW_ram, S_AXI_AR_ram;
wire S_AXI_AWVALID_ram,S_AXI_ARVALID_ram,S_AXI_WVALID_ram,S_AXI_RREADY_ram;
wire S_AXI_AWREADY_ram,S_AXI_ARREADY_ram,S_AXI_WREADY_ram,S_AXI_RVALID_ram,S_AXI_RLAST_ram,S_AXI_WLAST_ram;
wire [31:0] S_AXI_R_ram;
wire [31:0] S_AXI_W_ram;
wire [3:0] S_AXI_WSTRB_ram;
wire [1:0] S_AXI_ARBURST_ram;
wire [7:0] S_AXI_ARLEN_ram;
wire [2:0] S_AXI_ARSIZE_ram;
wire [1:0] S_AXI_AWBURST_ram;
wire [7:0] S_AXI_AWLEN_ram;
wire [2:0] S_AXI_AWSIZE_ram;
// axi rom bus
wire [31:0] S_AXI_AW_rom, S_AXI_AR_rom;
wire S_AXI_AWVALID_rom,S_AXI_ARVALID_rom,S_AXI_WVALID_rom,S_AXI_RREADY_rom;
wire S_AXI_AWREADY_rom,S_AXI_ARREADY_rom,S_AXI_WREADY_rom,S_AXI_RVALID_rom,S_AXI_RLAST_rom,S_AXI_WLAST_rom;
wire [31:0] S_AXI_R_rom;
wire [31:0] S_AXI_W_rom;
wire [3:0] S_AXI_WSTRB_rom;
wire [1:0] S_AXI_ARBURST_rom;
wire [7:0] S_AXI_ARLEN_rom;
wire [2:0] S_AXI_ARSIZE_rom;
wire [1:0] S_AXI_AWBURST_rom;
wire [7:0] S_AXI_AWLEN_rom;
wire [2:0] S_AXI_AWSIZE_rom;
// axi net bus
wire [31:0] S_AXI_AW_net, S_AXI_AR_net;
wire S_AXI_AWVALID_net,S_AXI_ARVALID_net,S_AXI_WVALID_net,S_AXI_RREADY_net;
wire S_AXI_AWREADY_net,S_AXI_ARREADY_net,S_AXI_WREADY_net,S_AXI_RVALID_net,S_AXI_RLAST_net,S_AXI_WLAST_net;
wire [31:0] S_AXI_R_net;
wire [31:0] S_AXI_W_net;
wire [3:0] S_AXI_WSTRB_net;
wire [1:0] S_AXI_ARBURST_net;
wire [7:0] S_AXI_ARLEN_net;
wire [2:0] S_AXI_ARSIZE_net;
wire [1:0] S_AXI_AWBURST_net;
wire [7:0] S_AXI_AWLEN_net;
wire [2:0] S_AXI_AWSIZE_net;
// axi io bus
wire [31:0] M_IO_AXI_AW, M_IO_AXI_AR;
wire M_IO_AXI_AWVALID,M_IO_AXI_ARVALID,M_IO_AXI_WVALID,M_IO_AXI_RREADY;
wire M_IO_AXI_AWREADY,M_IO_AXI_ARREADY,M_IO_AXI_WREADY,M_IO_AXI_RVALID,M_IO_AXI_RLAST,M_IO_AXI_WLAST;
wire [31:0] M_IO_AXI_R;
wire [31:0] M_IO_AXI_W;
wire [3:0] M_IO_AXI_WSTRB;
wire [1:0] M_IO_AXI_ARBURST;
wire [3:0] M_IO_AXI_ARLEN;
wire [2:0] M_IO_AXI_ARSIZE;
wire [1:0] M_IO_AXI_AWBURST;
wire [7:0] M_IO_AXI_AWLEN;
wire [2:0] M_IO_AXI_AWSIZE;
wire [15:0] extDBo,extDBt;
wire [7:0] gpioA_dir,gpioB_dir,gpioA_out,gpioB_out;
wire [31:0] romA,romQ;
wire int_pic,iack;
wire [7:0] ivect;
wire clk;
wire clk200;
wire dram_rst_out;
wire ui_clk_sync_rst;
wire init_calib_complete;
wire rstn_ddr;
wire locked;
assign gpio_in = 0;
clk_wiz_0 i_clk_wiz_0
(.clk_in1(clk100),
.clk_out1(),
.clk_out2(),
.clk_out3(clk200),
.locked(locked)
);
always @(posedge clk200) debug <= debug_int[3:0];
RSTGEN rstgen(.CLK(clk200), .RST_X_I(~(~rstn | dram_rst_out)), .RST_X_O(rstn_ddr));
assign dram_rst_out = (ui_clk_sync_rst | ~init_calib_complete);
STARTUPE2 #(
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
)
STARTUPE2_inst (
.CFGCLK(), // 1-bit output: Configuration main clock output
.CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output
.EOS(), // 1-bit output: Active high output signal indicating the End Of Startup.
.PREQ(), // 1-bit output: PROGRAM request to fabric output
.CLK(1'b0), // 1-bit input: User start-up clock input
.GSR(1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
.GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
.KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
.PACK(1'b0), // 1-bit input: PROGRAM acknowledge input
.USRCCLKO(sdclk), // 1-bit input: User CCLK input
.USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input
.USRDONEO(1'b1), // 1-bit input: User DONE pin output control
.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output
);
v586 v586 (
.m00_AXI_RSTN(rstn_ddr),.m00_AXI_CLK(clk),
// axi interface 32bit
.m00_AXI_AWADDR(M_AXI_AW), .m00_AXI_AWVALID(M_AXI_AWVALID), .m00_AXI_AWREADY(M_AXI_AWREADY),
.m00_AXI_AWBURST(M_AXI_AWBURST), .m00_AXI_AWLEN(M_AXI_AWLEN), .m00_AXI_AWSIZE(M_AXI_AWSIZE),
.m00_AXI_WDATA(M_AXI_W), .m00_AXI_WVALID(M_AXI_WVALID), .m00_AXI_WREADY(M_AXI_WREADY), .m00_AXI_WSTRB(M_AXI_WSTRB), .m00_AXI_WLAST(M_AXI_WLAST),
.m00_AXI_ARADDR(M_AXI_AR), .m00_AXI_ARVALID(M_AXI_ARVALID), .m00_AXI_ARREADY(M_AXI_ARREADY),
.m00_AXI_ARBURST(M_AXI_ARBURST), .m00_AXI_ARLEN(M_AXI_ARLEN), .m00_AXI_ARSIZE(M_AXI_ARSIZE),
.m00_AXI_RDATA(M_AXI_R), .m00_AXI_RVALID(M_AXI_RVALID), .m00_AXI_RREADY(M_AXI_RREADY), .m00_AXI_RLAST(M_AXI_RLAST),
.m00_AXI_BVALID(1'b1),.m00_AXI_BREADY(M_AXI_BREADY),
// axi io interface 32bit
.m01_AXI_AWADDR(M_IO_AXI_AW), .m01_AXI_AWVALID(M_IO_AXI_AWVALID), .m01_AXI_AWREADY(M_IO_AXI_AWREADY),
.m01_AXI_AWBURST(M_IO_AXI_AWBURST), .m01_AXI_AWLEN(M_IO_AXI_AWLEN), .m01_AXI_AWSIZE(M_IO_AXI_AWSIZE),
.m01_AXI_WDATA(M_IO_AXI_W), .m01_AXI_WVALID(M_IO_AXI_WVALID), .m01_AXI_WREADY(M_IO_AXI_WREADY), .m01_AXI_WSTRB(M_IO_AXI_WSTRB), .m01_AXI_WLAST(M_IO_AXI_WLAST),
.m01_AXI_ARADDR(M_IO_AXI_AR), .m01_AXI_ARVALID(M_IO_AXI_ARVALID), .m01_AXI_ARREADY(M_IO_AXI_ARREADY),
.m01_AXI_ARBURST(M_IO_AXI_ARBURST), .m01_AXI_ARLEN(M_IO_AXI_ARLEN), .m01_AXI_ARSIZE(M_IO_AXI_ARSIZE),
.m01_AXI_RDATA(M_IO_AXI_R), .m01_AXI_RVALID(M_IO_AXI_RVALID), .m01_AXI_RREADY(M_IO_AXI_RREADY), .m01_AXI_RLAST(M_IO_AXI_RLAST),
.m01_AXI_BVALID(1'b1),.m01_AXI_BREADY(M_IO_AXI_BREADY),
// interrupts
.int_pic(int_pic),.ivect(ivect),.iack(iack), .debug(debug_int)
);
ddr_axi i_ddr_axi (
// Inouts
.ddr2_dq(DDR2DQ),
.ddr2_dqs_n(DDR2DQS_N),
.ddr2_dqs_p(DDR2DQS_P),
// Outputs
.ddr2_addr(DDR2ADDR),
.ddr2_ba(DDR2BA),
.ddr2_ras_n(DDR2RAS_N),
.ddr2_cas_n(DDR2CAS_N),
.ddr2_we_n(DDR2WE_N),
.ddr2_ck_p(DDR2CK_P),
.ddr2_ck_n(DDR2CK_N),
.ddr2_cke(DDR2CKE),
.ddr2_cs_n(DDR2CS_N),
.ddr2_dm(DDR2DM),
.ddr2_odt(DDR2ODT),
// Inputs
// Single-ended system clock
.sys_clk_i(clk200),
// Single-ended iodelayctrl clk (reference clock)
.clk_ref_i(clk200),
// user interface signals
.ui_clk(clk),
.ui_clk_sync_rst(ui_clk_sync_rst),
.mmcm_locked(),
.aresetn(rstn),
.app_sr_req(0),
.app_ref_req(0),
.app_zq_req(0),
.app_sr_active(),
.app_ref_ack(),
.app_zq_ack(),
// AXI
// AW CHANNEL
.s_axi_awid(4'b00),
.s_axi_awaddr(S_AXI_AW_ram),
.s_axi_awlen(S_AXI_AWLEN_ram),
.s_axi_awsize(S_AXI_AWSIZE_ram),
.s_axi_awburst(S_AXI_AWBURST_ram),
.s_axi_awlock(1'b0),
.s_axi_awcache(4'h0),
.s_axi_awprot(3'h0),
.s_axi_awqos(4'h0),
.s_axi_awvalid(S_AXI_AWVALID_ram),
.s_axi_awready(S_AXI_AWREADY_ram),
// W CHANNEL
.s_axi_wdata(S_AXI_W_ram),
.s_axi_wstrb(S_AXI_WSTRB_ram),
.s_axi_wlast(S_AXI_WLAST_ram),
.s_axi_wvalid(S_AXI_WVALID_ram),
.s_axi_wready(S_AXI_WREADY_ram),
// B CHANNEL
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b1),
// AR CHANNEL
.s_axi_arid(4'b0),
.s_axi_araddr(S_AXI_AR_ram),
.s_axi_arlen(S_AXI_ARLEN_ram),
.s_axi_arsize(S_AXI_ARSIZE_ram),
.s_axi_arburst(S_AXI_ARBURST_ram),
.s_axi_arlock(1'b0),
.s_axi_arcache(4'h0),
.s_axi_arprot(3'h0),
.s_axi_arqos(4'h0),
.s_axi_arvalid(S_AXI_ARVALID_ram),
.s_axi_arready(S_AXI_ARREADY_ram),
// R CHANNEL
.s_axi_rid(),
.s_axi_rdata(S_AXI_R_ram),
.s_axi_rresp(),
.s_axi_rlast(S_AXI_RLAST_ram),
.s_axi_rvalid(S_AXI_RVALID_ram),
.s_axi_rready(S_AXI_RREADY_ram),
.init_calib_complete(init_calib_complete),
.sys_rst(~locked)
);
axi_rom bootrom (
.clk(clk),
.rstn(rstn_ddr),
.axi_ARVALID(S_AXI_ARVALID_rom),
.axi_ARREADY(S_AXI_ARREADY_rom),
.axi_AR(S_AXI_AR_rom),
.axi_ARBURST(S_AXI_ARBURST_rom),
.axi_ARLEN(S_AXI_ARLEN_rom),
.axi_RLAST(S_AXI_RLAST_rom),
.axi_R(S_AXI_R_rom),
.axi_RVALID(S_AXI_RVALID_rom),
.axi_RREADY(S_AXI_RREADY_rom)
);
axi_ethernetlite_0 i_etherlite (
.s_axi_aclk(clk),
.s_axi_aresetn(rstn_ddr),
.ip2intc_irpt(int_net),
.s_axi_awid(4'b000),
.s_axi_awaddr(S_AXI_AW_net[12:0]),
.s_axi_awlen(S_AXI_AWLEN_net),
.s_axi_awsize(S_AXI_AWSIZE_net),
.s_axi_awburst(S_AXI_AWBURST_net),
.s_axi_awcache(4'b0000),
.s_axi_awvalid(S_AXI_AWVALID_net),
.s_axi_awready(S_AXI_AWREADY_net),
.s_axi_wdata(S_AXI_W_net),
.s_axi_wstrb(S_AXI_WSTRB_net),
.s_axi_wlast(S_AXI_WLAST_net),
.s_axi_wvalid(S_AXI_WVALID_net),
.s_axi_wready(S_AXI_WREADY_net),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b1),
.s_axi_arid(4'b0),
.s_axi_araddr(S_AXI_AR_net[12:0]),
.s_axi_arlen(S_AXI_ARLEN_net),
.s_axi_arsize(S_AXI_ARSIZE_net),
.s_axi_arburst(S_AXI_ARBURST_net),
.s_axi_arcache(4'b0),
.s_axi_arvalid(S_AXI_ARVALID_net),
.s_axi_arready(S_AXI_ARREADY_net),
.s_axi_rid(),
.s_axi_rdata(S_AXI_R_net),
.s_axi_rresp(),
.s_axi_rlast(S_AXI_RLAST_net),
.s_axi_rvalid(S_AXI_RVALID_net),
.s_axi_rready(S_AXI_RREADY_net),
// to RMII converter
.phy_tx_clk(rmii2mac_tx_clk),
.phy_rx_clk(rmii2mac_rx_clk),
.phy_crs(rmii2mac_crs),
.phy_dv(rmii2mac_rx_dv),
.phy_rx_data(rmii2mac_rxd),
.phy_tx_data(mac2rmii_txd),
.phy_col(rmii2mac_col),
.phy_rx_er(rmii2mac_rx_er),
.phy_tx_en(mac2rmii_tx_en),
//.phy_tx_data(PhyTxd),
.phy_rst_n(PhyRstn),
.phy_mdio_i(PhyMdio_i),
.phy_mdio_o(PhyMdio_o),
.phy_mdio_t(PhyMdio_t),
.phy_mdc(PhyMdc)
);
IOBUF i_iobuf_mdio(
.O(PhyMdio_i),
.IO(PhyMdio),
.I(PhyMdio_o),
.T(PhyMdio_t));
axi_crossbar_0 i_axi_crossbar_0 (
.aclk(clk),
.aresetn(rstn_ddr),
.m_axi_awaddr({S_AXI_AW_net,S_AXI_AW_rom,S_AXI_AW_ram}),
.m_axi_awlen({S_AXI_AWLEN_net,S_AXI_AWLEN_rom,S_AXI_AWLEN_ram}),
.m_axi_awsize({S_AXI_AWSIZE_net,S_AXI_AWSIZE_rom,S_AXI_AWSIZE_ram}),
.m_axi_awburst({S_AXI_AWBURST_net,S_AXI_AWBURST_rom,S_AXI_AWBURST_ram}),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid({S_AXI_AWVALID_net,S_AXI_AWVALID_rom,S_AXI_AWVALID_ram}),
.m_axi_awready({S_AXI_AWREADY_net,1'b1,S_AXI_AWREADY_ram}),
.m_axi_wdata({S_AXI_W_net,S_AXI_W_rom,S_AXI_W_ram}),
.m_axi_wstrb({S_AXI_WSTRB_net,S_AXI_WSTRB_rom,S_AXI_WSTRB_ram}),
.m_axi_wlast({S_AXI_WLAST_net,S_AXI_WLAST_rom,S_AXI_WLAST_ram}),
.m_axi_wuser(),
.m_axi_wvalid({S_AXI_WVALID_net,S_AXI_WVALID_rom,S_AXI_WVALID_ram}),
.m_axi_wready({S_AXI_WREADY_net,1'b1,S_AXI_WREADY_ram}),
.m_axi_bresp(0),
.m_axi_buser(0),
.m_axi_bvalid(3'b111),
.m_axi_bready(),
.m_axi_araddr({S_AXI_AR_net,S_AXI_AR_rom,S_AXI_AR_ram}),
.m_axi_arlen({S_AXI_ARLEN_net,S_AXI_ARLEN_rom,S_AXI_ARLEN_ram}),
.m_axi_arsize({S_AXI_ARSIZE_net,S_AXI_ARSIZE_rom,S_AXI_ARSIZE_ram}),
.m_axi_arburst({S_AXI_ARBURST_net,S_AXI_ARBURST_rom,S_AXI_ARBURST_ram}),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid({S_AXI_ARVALID_net,S_AXI_ARVALID_rom,S_AXI_ARVALID_ram}),
.m_axi_arready({S_AXI_ARREADY_net,S_AXI_ARREADY_rom,S_AXI_ARREADY_ram}),
.m_axi_rdata({S_AXI_R_net,S_AXI_R_rom,S_AXI_R_ram}),
.m_axi_rresp(6'b0),
.m_axi_rlast({S_AXI_RLAST_net,S_AXI_RLAST_rom,S_AXI_RLAST_ram}),
.m_axi_ruser(12'b0),
.m_axi_rvalid({S_AXI_RVALID_net,S_AXI_RVALID_rom,S_AXI_RVALID_ram}),
.m_axi_rready({S_AXI_RREADY_net,S_AXI_RREADY_rom,S_AXI_RREADY_ram}),
.s_axi_awaddr(M_AXI_AW), .s_axi_awvalid(M_AXI_AWVALID), .s_axi_awready(M_AXI_AWREADY),
.s_axi_awburst(M_AXI_AWBURST), .s_axi_awlen(M_AXI_AWLEN), .s_axi_awsize(M_AXI_AWSIZE),
.s_axi_wdata(M_AXI_W), .s_axi_wvalid(M_AXI_WVALID), .s_axi_wready(M_AXI_WREADY), .s_axi_wstrb(M_AXI_WSTRB), .s_axi_wlast(M_AXI_WLAST),
.s_axi_araddr(M_AXI_AR), .s_axi_arvalid(M_AXI_ARVALID), .s_axi_arready(M_AXI_ARREADY),
.s_axi_arburst(M_AXI_ARBURST), .s_axi_arlen(M_AXI_ARLEN), .s_axi_arsize(M_AXI_ARSIZE),
.s_axi_rdata(M_AXI_R), .s_axi_rvalid(M_AXI_RVALID), .s_axi_rready(M_AXI_RREADY), .s_axi_rlast(M_AXI_RLAST),
.s_axi_bvalid(),.s_axi_bready(1'b1),
.s_axi_arlock(0), .s_axi_arcache(0),.s_axi_arprot(0), .s_axi_arqos(0), .s_axi_aruser(0),
.s_axi_awlock(0), .s_axi_awcache(0),.s_axi_awprot(0), .s_axi_awqos(0), .s_axi_awuser(0),
.s_axi_wuser(0)
);
always @(posedge clk) if (rstn_ddr == 0) sdreset <=1; else sdreset <=0;
always @(posedge clk) if (rstn_ddr == 0) PhyClk50Mhz <=0; else PhyClk50Mhz <=~PhyClk50Mhz;
assign gpioA[0] = (gpioA_dir[0] == 0) ? 1'bz : gpioA_out[0];
assign gpioA[1] = (gpioA_dir[1] == 0) ? 1'bz : gpioA_out[1];
assign gpioA[2] = (gpioA_dir[2] == 0) ? 1'bz : gpioA_out[2];
assign gpioA[3] = (gpioA_dir[3] == 0) ? 1'bz : gpioA_out[3];
assign gpioA[4] = (gpioA_dir[4] == 0) ? 1'bz : gpioA_out[4];
assign gpioA[5] = (gpioA_dir[5] == 0) ? 1'bz : gpioA_out[5];
assign gpioA[6] = (gpioA_dir[6] == 0) ? 1'bz : gpioA_out[6];
assign gpioA[7] = (gpioA_dir[7] == 0) ? 1'bz : gpioA_out[7];
assign gpioB[0] = (gpioB_dir[0] == 0) ? 1'bz : gpioB_out[0];
assign gpioB[1] = (gpioB_dir[1] == 0) ? 1'bz : gpioB_out[1];
assign gpioB[2] = (gpioB_dir[2] == 0) ? 1'bz : gpioB_out[2];
assign gpioB[3] = (gpioB_dir[3] == 0) ? 1'bz : gpioB_out[3];
assign gpioB[4] = (gpioB_dir[4] == 0) ? 1'bz : gpioB_out[4];
assign gpioB[5] = (gpioB_dir[5] == 0) ? 1'bz : gpioB_out[5];
assign gpioB[6] = (gpioB_dir[6] == 0) ? 1'bz : gpioB_out[6];
assign gpioB[7] = (gpioB_dir[7] == 0) ? 1'bz : gpioB_out[7];
assign sdwp = 1'b1;
assign sdhld = 1'b1;
periph i_periph (
.s00_AXI_RSTN(rstn_ddr),
.s00_AXI_CLK(clk),
.cfg(gpio_in[6:0]),
// spi
.spi_mosi(sdout),
.spi_miso(sdin),
.spi_clk(sdclk),
.spi_cs(sdcs),
// tiny spi
.mosi(mosi),
.miso(miso),
.sclk(sclk),
// interrupts
.int_pic(int_pic),
.iack(iack),
.ivect(ivect),
.int_bus({aclInt2,aclInt1,int_net,1'b0}),
// gpio
.gpioA_in(gpioA),.gpioB_in(gpioB),
.gpioA_out(gpioA_out),.gpioB_out(gpioB_out),
.gpioA_dir(gpioA_dir),.gpioB_dir(gpioB_dir),
//uart
.RXD(RXD),
.TXD(TXD),
// AXI4 IO 32 BIT BUS
.s00_AXI_AWADDR(M_IO_AXI_AW),
.s00_AXI_AWVALID(M_IO_AXI_AWVALID),
.s00_AXI_AWREADY(M_IO_AXI_AWREADY),
.s00_AXI_AWBURST(M_IO_AXI_AWBURST),
.s00_AXI_AWLEN(M_IO_AXI_AWLEN),
.s00_AXI_AWSIZE(M_IO_AXI_AWSIZE),
.s00_AXI_ARADDR(M_IO_AXI_AR),
.s00_AXI_ARVALID(M_IO_AXI_ARVALID),
.s00_AXI_ARREADY(M_IO_AXI_ARREADY),
.s00_AXI_ARBURST(M_IO_AXI_ARBURST),
.s00_AXI_ARLEN(M_IO_AXI_ARLEN),
.s00_AXI_ARSIZE(M_IO_AXI_ARSIZE),
.s00_AXI_WDATA(M_IO_AXI_W),
.s00_AXI_WVALID(M_IO_AXI_WVALID),
.s00_AXI_WREADY(M_IO_AXI_WREADY),
.s00_AXI_WSTRB(M_IO_AXI_WSTRB),
.s00_AXI_WLAST(M_IO_AXI_WLAST),
.s00_AXI_RDATA(M_IO_AXI_R),
.s00_AXI_RVALID(M_IO_AXI_RVALID),
.s00_AXI_RREADY(M_IO_AXI_RREADY),
.s00_AXI_RLAST(M_IO_AXI_RLAST),
.s00_AXI_BVALID(),
.s00_AXI_BREADY(1'b1)
);
`ifndef simu
mii_to_rmii_0 mii_to_rmii_i (
.rst_n(PhyRstn),
.ref_clk(PhyClk50Mhz),
// to/from mac
.mac2rmii_tx_en(mac2rmii_tx_en),
.mac2rmii_txd(mac2rmii_txd),
.mac2rmii_tx_er(mac2rmii_tx_er),
.rmii2mac_tx_clk(rmii2mac_tx_clk),
.rmii2mac_rx_clk(rmii2mac_rx_clk),
.rmii2mac_col(rmii2mac_col),
.rmii2mac_crs(rmii2mac_crs),
.rmii2mac_rx_dv(rmii2mac_rx_dv),
.rmii2mac_rx_er(rmii2mac_rx_er),
.rmii2mac_rxd(rmii2mac_rxd),
// external connections
.phy2rmii_crs_dv(PhyCrs),
.phy2rmii_rx_er(PhyRxErr),
.phy2rmii_rxd(PhyRxd),
.rmii2phy_txd(PhyTxd),
.rmii2phy_tx_en(PhyTxEn)
);
`endif
endmodule
|
Require Import ExtLib.Structures.Applicative.
Require Import Temporal.DiscreteLogic.
Require Import ChargeCore.Tactics.Tactics.
Set Implicit Arguments.
Set Strict Implicit.
Definition lift1 {T U : Type} {F : Type -> Type}
{Ap : Applicative.Applicative F}
(f : T -> U) (x : F T) : F U :=
Applicative.ap (Applicative.pure f) x.
Definition lift2 {T U V : Type} {F : Type -> Type}
{Ap : Applicative.Applicative F}
(f : T -> U -> V) (x : F T) (y : F U) : F V :=
Applicative.ap (lift1 (F:=F) f x) y.
(*
Class Arith (T : Type) : Type :=
{ plus : T -> T -> T
; minus : T -> T -> T
; mult : T -> T -> T
}.
Instance Arith_nat : Arith nat :=
{ plus := Nat.add
; minus := Nat.sub
; mult := Nat.mul
}.
Instance Arith_lift {T U} {A : Arith T} : Arith (U -> T) :=
{ plus := fun a b x => plus (a x) (b x)
; minus := fun a b x => minus (a x) (b x)
; mult := fun a b x => mult (a x) (b x)
}.
*)
Record State : Type :=
{ x : nat }.
Definition Sys : TraceProp State :=
now (lift2 eq x (pure 1))
//\\ always (starts (lift2 eq (pre x) (post x))).
(** TODO: Move **)
Definition beforeProp (P : StateProp State) (Q : ActionProp State) : Prop :=
before State P -|- Q.
Definition beforeVal {T} (P : StateVal State T) (Q : ActionVal State T)
: Prop :=
forall st st', P st = Q st st'.
Theorem beforeProp_lift2 {T U} (f : T -> U -> Prop) x y x' y'
: beforeVal x x' -> beforeVal y y' ->
beforeProp (lift2 f x y) (lift2 f x' y').
Proof.
unfold beforeVal, beforeProp.
simpl. intros.
unfold before.
split.
Transparent ILInsts.ILFun_Ops.
{ do 3 red. simpl. destruct t0.
rewrite <- H. rewrite <- H0. auto. }
{ do 3 red. simpl. destruct t0.
rewrite <- H. rewrite <- H0. auto. }
Qed.
Theorem beforeVal_pre {T} (get : State -> T) :
beforeVal get (pre get).
Proof. red. reflexivity. Qed.
Theorem beforeVal_pure {T} (x : T) :
beforeVal (pure x) (pure x).
Proof. red. reflexivity. Qed.
Require Import Coq.Classes.Morphisms.
Notation "[] e" := (always e) (at level 30).
Goal |-- Sys -->> [] (now (lift2 eq x (pure 1))).
Proof.
unfold Sys.
charge_intros.
eapply hybrid_induction.
{ charge_assumption. }
{ charge_assumption. }
{ apply always_tauto.
rewrite <- curry.
rewrite now_starts_discretely_and.
rewrite next_now.
rewrite starts_impl.
eapply starts_tauto.
unfold before, after, pre, post. simpl.
destruct 2; congruence. }
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_1_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_1_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv5sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd2_1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkdlyinv5sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkdlyinv5sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_1_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: SDRAM_PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module SDRAM_PLL (
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [0:0] sub_wire2 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c0 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "-167",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "SDRAM_PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-167"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_PLL.ppf TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module spi_addressing (
input clk,
input rst,
// SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
// Register interface signals
output [5:0] reg_addr,
output write,
output new_req,
output [7:0] write_value,
input [7:0] read_value,
output in_transaction
);
wire spi_done;
wire [7:0] spi_dout;
wire frame_start, frame_end;
wire spi_miso_m;
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(read_value),
.dout(spi_dout),
.frame_start(frame_start),
.frame_end(frame_end)
);
localparam STATE_SIZE = 2;
localparam IDLE = 0,
ADDR = 1,
WRITE = 2,
READ = 3;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [7:0] write_value_d, write_value_q;
reg write_d, write_q;
reg auto_inc_d, auto_inc_q;
reg [5:0] reg_addr_d, reg_addr_q;
reg new_req_d, new_req_q;
reg first_write_d, first_write_q;
assign reg_addr = reg_addr_q;
assign write = write_q;
assign new_req = new_req_q;
assign write_value = write_value_q;
assign spi_miso = !spi_ss ? spi_miso_m : 1'bZ;
assign in_transaction = !spi_ss;
always @(*) begin
write_value_d = write_value_q;
write_d = write_q;
auto_inc_d = auto_inc_q;
reg_addr_d = reg_addr_q;
new_req_d = 1'b0;
state_d = state_q;
first_write_d = first_write_q;
case (state_q)
IDLE: begin
if (frame_start)
state_d = ADDR;
end
ADDR: begin
if (spi_done) begin
first_write_d = 1'b1;
{write_d, auto_inc_d, reg_addr_d} = spi_dout;
if (spi_dout[7]) begin
state_d = WRITE;
end else begin
state_d = READ;
new_req_d = 1'b1;
end
end
end
WRITE: begin
if (spi_done) begin
first_write_d = 1'b0;
if (auto_inc_q && !first_write_q)
reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
write_value_d = spi_dout;
end
end
READ: begin
if (spi_done) begin
if (auto_inc_q)
reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
end
end
default: state_d = IDLE;
endcase
if (frame_end)
state_d = IDLE;
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
write_value_q <= write_value_d;
write_q <= write_d;
auto_inc_q <= auto_inc_d;
reg_addr_q <= reg_addr_d;
new_req_q <= new_req_d;
first_write_q <= first_write_d;
end
endmodule
|
`include "config.inc"
module configuration(
input clock,
input DCVideoConfig dcVideoConfig,
inout _480p_active_n,
input forceVGAMode,
input force_generate,
output reg line_doubler,
output reg [3:0] clock_config_S,
output reg config_changed
);
reg prev_mode = 1'b0;
reg mode = 1'b0;
reg _480p_active_n_reg = 1'bz;
assign _480p_active_n = _480p_active_n_reg;
always @(posedge clock) begin
if (prev_mode != mode) begin
config_changed <= 1'b1;
end else begin
config_changed <= 1'b0;
end
if (force_generate || forceVGAMode || ~_480p_active_n) begin
clock_config_S <= dcVideoConfig.ICS644_settings_p;
line_doubler <= 1'b0;
mode <= 1'b1;
end else begin
clock_config_S <= dcVideoConfig.ICS644_settings_i;
line_doubler <= 1'b1;
mode <= 1'b0;
end
_480p_active_n_reg <= forceVGAMode ? 1'b0 : 1'bz;
prev_mode <= mode;
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_FUNCTIONAL_PP_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
`define AUTOTB_DUT adder
`define AUTOTB_DUT_INST AESL_inst_adder
`define AUTOTB_TOP apatb_adder_top
`define AUTOTB_LAT_RESULT_FILE "adder.result.lat.rb"
`define AUTOTB_PER_RESULT_TRANS_FILE "adder.performance.result.transaction.xml"
`define AUTOTB_TOP_INST AESL_inst_apatb_adder_top
`define AUTOTB_MAX_ALLOW_LATENCY 15000000
`define AUTOTB_TRANSACTION_NUM 1
`define AUTOTB_CLOCK_PERIOD 10.000000
`define LENGTH_a 1
`define LENGTH_b 1
`define LENGTH_c 1
`define AESL_DEPTH_a 1
`define AESL_DEPTH_b 1
`define AESL_DEPTH_c 1
`define AUTOTB_TVIN_a "./c.adder.autotvin_a.dat"
`define AUTOTB_TVIN_b "./c.adder.autotvin_b.dat"
`define AUTOTB_TVIN_a_out_wrapc "./rtl.adder.autotvin_a.dat"
`define AUTOTB_TVIN_b_out_wrapc "./rtl.adder.autotvin_b.dat"
`define AUTOTB_TVOUT_c "./c.adder.autotvout_c.dat"
`define AUTOTB_TVOUT_c_out_wrapc "./impl_rtl.adder.autotvout_c.dat"
module `AUTOTB_TOP;
task read_token;
input integer fp;
output reg [199 : 0] token;
reg [7:0] c;
reg intoken;
reg done;
begin
token = "";
intoken = 0;
done = 0;
while (!done) begin
c = $fgetc(fp);
if (c == 8'hff) begin // EOF
done = 1;
end
else if (c == " " || c == "\011" || c == "\012" || c == "\015") begin // blank
if (intoken) begin
done = 1;
end
end
else begin // valid character
intoken = 1;
token = (token << 8) | c;
end
end
end
endtask
task post_check;
input integer fp1;
input integer fp2;
reg [199 : 0] token1;
reg [199 : 0] token2;
reg [199 : 0] golden;
reg [199 : 0] result;
integer ret;
begin
read_token(fp1, token1);
read_token(fp2, token2);
if (token1 != "[[[runtime]]]" || token2 != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1);
read_token(fp2, token2);
while (token1 != "[[[/runtime]]]" && token2 != "[[[/runtime]]]") begin
if (token1 != "[[transaction]]" || token2 != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1); // skip transaction number
read_token(fp2, token2); // skip transaction number
read_token(fp1, token1);
read_token(fp2, token2);
while(token1 != "[[/transaction]]" && token2 != "[[/transaction]]") begin
ret = $sscanf(token1, "0x%x", golden);
if (ret != 1) begin
$display("Failed to parse token!");
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
ret = $sscanf(token2, "0x%x", result);
if (ret != 1) begin
$display("Failed to parse token!");
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
if(golden != result) begin
$display("%x (expected) vs. %x (actual) - mismatch", golden, result);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1);
read_token(fp2, token2);
end
read_token(fp1, token1);
read_token(fp2, token2);
end
end
endtask
reg AESL_clock;
reg rst;
reg start;
reg ce;
reg continue;
wire AESL_start;
wire AESL_reset;
wire AESL_ce;
wire AESL_ready;
wire AESL_idle;
wire AESL_continue;
wire AESL_done;
reg AESL_done_delay = 0;
reg AESL_done_delay2 = 0;
reg AESL_ready_delay = 0;
wire ready;
wire ready_wire;
reg [31 : 0] AESL_mLatCnterIn [0 : `AUTOTB_TRANSACTION_NUM + 1];
reg [31 : 0] AESL_mLatCnterIn_addr;
reg [31 : 0] AESL_mLatCnterOut [0 : `AUTOTB_TRANSACTION_NUM + 1];
reg [31 : 0] AESL_mLatCnterOut_addr ;
reg [31 : 0] AESL_clk_counter ;
wire s_axi_AXI_CTRL_AWVALID;
wire s_axi_AXI_CTRL_AWREADY;
wire [5 : 0] s_axi_AXI_CTRL_AWADDR;
wire s_axi_AXI_CTRL_WVALID;
wire s_axi_AXI_CTRL_WREADY;
wire [31 : 0] s_axi_AXI_CTRL_WDATA;
wire [3 : 0] s_axi_AXI_CTRL_WSTRB;
wire s_axi_AXI_CTRL_ARVALID;
wire s_axi_AXI_CTRL_ARREADY;
wire [5 : 0] s_axi_AXI_CTRL_ARADDR;
wire s_axi_AXI_CTRL_RVALID;
wire s_axi_AXI_CTRL_RREADY;
wire [31 : 0] s_axi_AXI_CTRL_RDATA;
wire [1 : 0] s_axi_AXI_CTRL_RRESP;
wire s_axi_AXI_CTRL_BVALID;
wire s_axi_AXI_CTRL_BREADY;
wire [1 : 0] s_axi_AXI_CTRL_BRESP;
wire ap_clk;
wire ap_rst_n;
wire interrupt;
integer done_cnt = 0;
integer AESL_ready_cnt = 0;
integer ready_cnt = 0;
reg ready_initial;
reg ready_initial_n;
reg ready_last_n;
reg ready_delay_last_n;
reg done_delay_last_n;
reg interface_done = 0;
wire AXI_CTRL_read_data_finish;
wire AXI_CTRL_write_data_finish;
wire AESL_slave_start;
wire AESL_slave_write_start_in;
wire AESL_slave_write_start_finish;
reg AESL_slave_ready;
wire AESL_slave_output_done;
reg ready_rise = 0;
reg start_rise = 0;
reg slave_start_status = 0;
reg slave_done_status = 0;
`AUTOTB_DUT `AUTOTB_DUT_INST(
.s_axi_AXI_CTRL_AWVALID(s_axi_AXI_CTRL_AWVALID),
.s_axi_AXI_CTRL_AWREADY(s_axi_AXI_CTRL_AWREADY),
.s_axi_AXI_CTRL_AWADDR(s_axi_AXI_CTRL_AWADDR),
.s_axi_AXI_CTRL_WVALID(s_axi_AXI_CTRL_WVALID),
.s_axi_AXI_CTRL_WREADY(s_axi_AXI_CTRL_WREADY),
.s_axi_AXI_CTRL_WDATA(s_axi_AXI_CTRL_WDATA),
.s_axi_AXI_CTRL_WSTRB(s_axi_AXI_CTRL_WSTRB),
.s_axi_AXI_CTRL_ARVALID(s_axi_AXI_CTRL_ARVALID),
.s_axi_AXI_CTRL_ARREADY(s_axi_AXI_CTRL_ARREADY),
.s_axi_AXI_CTRL_ARADDR(s_axi_AXI_CTRL_ARADDR),
.s_axi_AXI_CTRL_RVALID(s_axi_AXI_CTRL_RVALID),
.s_axi_AXI_CTRL_RREADY(s_axi_AXI_CTRL_RREADY),
.s_axi_AXI_CTRL_RDATA(s_axi_AXI_CTRL_RDATA),
.s_axi_AXI_CTRL_RRESP(s_axi_AXI_CTRL_RRESP),
.s_axi_AXI_CTRL_BVALID(s_axi_AXI_CTRL_BVALID),
.s_axi_AXI_CTRL_BREADY(s_axi_AXI_CTRL_BREADY),
.s_axi_AXI_CTRL_BRESP(s_axi_AXI_CTRL_BRESP),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
// Assignment for control signal
assign ap_clk = AESL_clock;
assign ap_rst_n = AESL_reset;
assign ap_rst_n_n = ~AESL_reset;
assign AESL_reset = rst;
assign AESL_start = start;
assign AESL_ce = ce;
assign AESL_continue = continue;
assign AESL_slave_write_start_in = slave_start_status & AXI_CTRL_write_data_finish;
assign AESL_slave_start = AESL_slave_write_start_finish;
assign AESL_done = slave_done_status & AXI_CTRL_read_data_finish;
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
slave_start_status <= 1;
end
else begin
if (AESL_start == 1 ) begin
start_rise = 1;
end
if (start_rise == 1 && AESL_done == 1 ) begin
slave_start_status <= 1;
end
if (AESL_slave_write_start_in == 1) begin
slave_start_status <= 0;
start_rise = 0;
end
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
else begin
if (AESL_ready == 1 ) begin
ready_rise = 1;
end
if (ready_rise == 1 && AESL_done_delay == 1 ) begin
AESL_slave_ready <= 1;
end
if (AESL_slave_ready == 1) begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
end
end
always @ (posedge AESL_clock)
begin
if (AESL_done == 1) begin
slave_done_status <= 0;
end
else if (AESL_slave_output_done == 1 ) begin
slave_done_status <= 1;
end
end
AESL_axi_slave_AXI_CTRL AESL_AXI_SLAVE_AXI_CTRL(
.clk (AESL_clock),
.reset (AESL_reset),
.TRAN_s_axi_AXI_CTRL_AWADDR (s_axi_AXI_CTRL_AWADDR),
.TRAN_s_axi_AXI_CTRL_AWVALID (s_axi_AXI_CTRL_AWVALID),
.TRAN_s_axi_AXI_CTRL_AWREADY (s_axi_AXI_CTRL_AWREADY),
.TRAN_s_axi_AXI_CTRL_WVALID (s_axi_AXI_CTRL_WVALID),
.TRAN_s_axi_AXI_CTRL_WREADY (s_axi_AXI_CTRL_WREADY),
.TRAN_s_axi_AXI_CTRL_WDATA (s_axi_AXI_CTRL_WDATA),
.TRAN_s_axi_AXI_CTRL_WSTRB (s_axi_AXI_CTRL_WSTRB),
.TRAN_s_axi_AXI_CTRL_ARADDR (s_axi_AXI_CTRL_ARADDR),
.TRAN_s_axi_AXI_CTRL_ARVALID (s_axi_AXI_CTRL_ARVALID),
.TRAN_s_axi_AXI_CTRL_ARREADY (s_axi_AXI_CTRL_ARREADY),
.TRAN_s_axi_AXI_CTRL_RVALID (s_axi_AXI_CTRL_RVALID),
.TRAN_s_axi_AXI_CTRL_RREADY (s_axi_AXI_CTRL_RREADY),
.TRAN_s_axi_AXI_CTRL_RDATA (s_axi_AXI_CTRL_RDATA),
.TRAN_s_axi_AXI_CTRL_RRESP (s_axi_AXI_CTRL_RRESP),
.TRAN_s_axi_AXI_CTRL_BVALID (s_axi_AXI_CTRL_BVALID),
.TRAN_s_axi_AXI_CTRL_BREADY (s_axi_AXI_CTRL_BREADY),
.TRAN_s_axi_AXI_CTRL_BRESP (s_axi_AXI_CTRL_BRESP),
.TRAN_AXI_CTRL_read_data_finish(AXI_CTRL_read_data_finish),
.TRAN_AXI_CTRL_write_data_finish(AXI_CTRL_write_data_finish),
.TRAN_AXI_CTRL_ready_out (AESL_ready),
.TRAN_AXI_CTRL_ready_in (AESL_slave_ready),
.TRAN_AXI_CTRL_done_out (AESL_slave_output_done),
.TRAN_AXI_CTRL_idle_out (AESL_idle),
.TRAN_AXI_CTRL_write_start_in (AESL_slave_write_start_in),
.TRAN_AXI_CTRL_write_start_finish (AESL_slave_write_start_finish),
.TRAN_AXI_CTRL_transaction_done_in (AESL_done_delay),
.TRAN_AXI_CTRL_interrupt (interrupt),
.TRAN_AXI_CTRL_start_in (AESL_slave_start)
);
initial begin : generate_AESL_ready_cnt_proc
AESL_ready_cnt = 0;
wait(AESL_reset === 1);
while(AESL_ready_cnt != `AUTOTB_TRANSACTION_NUM) begin
while(AESL_ready !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
AESL_ready_cnt = AESL_ready_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
end
initial begin : generate_ready_cnt_proc
ready_cnt = 0;
wait(AESL_reset === 1);
while(ready_cnt != `AUTOTB_TRANSACTION_NUM) begin
while(ready !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
ready_cnt = ready_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
end
initial begin : generate_done_cnt_proc
integer fp1;
integer fp2;
done_cnt = 0;
wait(AESL_reset === 1);
while(done_cnt != `AUTOTB_TRANSACTION_NUM) begin
while(AESL_done !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
done_cnt = done_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
@(posedge AESL_clock);
# 0.4;
$display("Simulation Passed.");
$finish;
end
initial fork
AESL_clock = 0;
forever #(`AUTOTB_CLOCK_PERIOD/2) AESL_clock = ~AESL_clock;
join
initial begin : initial_process
integer rand;
rst = 0;
# 100;
repeat(3) @(posedge AESL_clock);
rst = 1;
end
initial begin : start_process
integer rand;
start = 0;
ce = 1;
wait(AESL_reset === 1);
@(posedge AESL_clock);
start <= 1;
while(done_cnt != `AUTOTB_TRANSACTION_NUM) begin
@(posedge AESL_clock);
end
start <= 0;
end
always @(AESL_done)
begin
if(done_cnt < `AUTOTB_TRANSACTION_NUM - 1)
continue = AESL_done;
else
continue = 0;
end
initial begin : ready_initial_process
ready_initial = 0;
wait (AESL_start === 1);
ready_initial = 1;
@(posedge AESL_clock);
ready_initial = 0;
end
initial begin : ready_last_n_process
ready_last_n = 1;
wait(ready_cnt == `AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
ready_last_n <= 0;
end
assign ready = (ready_initial | AESL_done_delay);
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
ready_delay_last_n = 0;
else
ready_delay_last_n <= ready_last_n;
end
assign ready_wire = (ready_initial | AESL_done_delay);
initial begin : done_delay_last_n_process
done_delay_last_n = 1;
while(done_cnt != `AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
# 0.1;
done_delay_last_n = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_done_delay <= 0;
AESL_done_delay2 <= 0;
end
else begin
AESL_done_delay <= AESL_done & done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
interface_done = 0;
else begin
# 0.01;
if(ready === 1 && ready_cnt > 0 && ready_cnt < `AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else if(AESL_done_delay === 1 && done_cnt == `AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else
interface_done = 0;
end
end
// Write "[[[runtime]]]" and "[[[/runtime]]]" for output-only transactor
initial begin : write_output_transactor_c_runtime_process
integer fp;
fp = $fopen(`AUTOTB_TVOUT_c_out_wrapc, "w");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_c_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[runtime]]]");
$fclose(fp);
wait(done_cnt == `AUTOTB_TRANSACTION_NUM)
repeat(2) @(posedge AESL_clock);
# 0.2;
fp = $fopen(`AUTOTB_TVOUT_c_out_wrapc, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_c_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[/runtime]]]");
$fclose(fp);
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_clk_counter <= 0;
end
else begin
AESL_clk_counter = AESL_clk_counter + 1;
end
end
always @ (posedge AESL_clock or negedge AESL_reset) begin
if(AESL_reset === 0)
begin
AESL_mLatCnterOut_addr = 0;
AESL_mLatCnterOut[AESL_mLatCnterOut_addr] = AESL_clk_counter + 1;
end
else if (AESL_done && AESL_mLatCnterOut_addr < `AUTOTB_TRANSACTION_NUM + 1) begin
AESL_mLatCnterOut[AESL_mLatCnterOut_addr] = AESL_clk_counter;
AESL_mLatCnterOut_addr = AESL_mLatCnterOut_addr + 1;
end
end
always @ (posedge AESL_clock or negedge AESL_reset) begin
if(AESL_reset === 0)
begin
AESL_mLatCnterIn_addr = 0;
end
else if (AESL_slave_write_start_finish && AESL_mLatCnterIn_addr < `AUTOTB_TRANSACTION_NUM + 1) begin
AESL_mLatCnterIn[AESL_mLatCnterIn_addr] = AESL_clk_counter;
AESL_mLatCnterIn_addr = AESL_mLatCnterIn_addr + 1;
end
end
initial begin : performance_check
integer transaction_counter;
integer i;
integer fp;
integer latthistime;
integer lattotal;
integer latmax;
integer latmin;
integer thrthistime;
integer thrtotal;
integer thrmax;
integer thrmin;
integer lataver;
integer thraver;
reg [31 : 0] lat_array [0 : `AUTOTB_TRANSACTION_NUM];
reg [31 : 0] thr_array [0 : `AUTOTB_TRANSACTION_NUM];
i = 0;
lattotal = 0;
latmax = 0;
latmin = 32'h 7fffffff;
lataver = 0;
thrtotal = 0;
thrmax = 0;
thrmin = 32'h 7fffffff;
thraver = 0;
@(negedge AESL_clock);
@(posedge AESL_reset);
while (done_cnt != `AUTOTB_TRANSACTION_NUM) begin
@(posedge AESL_clock);
end
#0.001
latmax = 0;
latmin = 0;
lataver = 0;
thrmax = 0;
thrmin = 0;
thraver = 0;
fp = $fopen(`AUTOTB_LAT_RESULT_FILE, "w");
$fdisplay(fp, "$MAX_LATENCY = \"%0d\"", latmax);
$fdisplay(fp, "$MIN_LATENCY = \"%0d\"", latmin);
$fdisplay(fp, "$AVER_LATENCY = \"%0d\"", lataver);
$fdisplay(fp, "$MAX_THROUGHPUT = \"%0d\"", latmax);
$fdisplay(fp, "$MIN_THROUGHPUT = \"%0d\"", latmin);
$fdisplay(fp, "$AVER_THROUGHPUT = \"%0d\"", lataver);
$fclose(fp);
fp = $fopen(`AUTOTB_PER_RESULT_TRANS_FILE, "w");
$fdisplay (fp,"%20s%16s%16s","","latency","interval");
for (i = 0; i < AESL_mLatCnterOut_addr; i = i + 1) begin
$fdisplay (fp,"transaction%8d: 0 0",i );
end
$fclose(fp);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O2BB2A_PP_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_LP_V
`define SKY130_FD_SC_LP__DLXBP_LP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbp_lp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbp_lp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_LP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_LP_V
`define SKY130_FD_SC_LP__DLXTP_LP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtp_lp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtp_lp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_LP_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : bd_mig_7series_0_0_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module bd_mig_7series_0_0_mig #
(
parameter RST_ACT_LOW = 1,
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DQ_CNT_WIDTH = 4,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 2,
// # of DM (data mask)
parameter DQ_WIDTH = 16,
// # of DQ (data)
parameter DQS_WIDTH = 2,
parameter DQS_CNT_WIDTH = 1,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter DATA_WIDTH = 16,
parameter ECC_TEST = "OFF",
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
//Possible Parameters
//1.BANK_ROW_COLUMN : Address mapping is
// in form of Bank Row Column.
//2.ROW_BANK_COLUMN : Address mapping is
// in the form of Row Bank Column.
//3.TG_TEST : Scrambles Address bits
// for distributed Addressing.
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ODT_WIDTH = 1,
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 1,
// # = 1, When Chip Select (CS#) output is enabled
// = 0, When Chip Select (CS#) output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
parameter PHY_CONTROL_MASTER_BANK = 0,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
parameter MEM_DENSITY = "1Gb",
// Indicates the density of the Memory part
// Added for the sake of Vivado simulations
parameter MEM_SPEEDGRADE = "25E",
// Indicates the Speed grade of Memory Part
// Added for the sake of Vivado simulations
parameter MEM_DEVICE_WIDTH = 16,
// Indicates the device width of the Memory Part
// Added for the sake of Vivado simulations
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 4,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter OUTPUT_DRV = "HIGH",
// Output Drive Strength (Extended Mode Register).
// # = "HIGH" - FULL,
// = "LOW" - REDUCED.
parameter RTT_NOM = "50",
// RTT (Nominal) (Extended Mode Register).
// = "150" - 150 Ohms,
// = "75" - 75 Ohms,
// = "50" - 50 Ohms.
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 10000,
// Input Clock Period
parameter CLKFBOUT_MULT = 10,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_PHASE = 0.0,
// Phase for PLL output clock (CLKOUT0)
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 4,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 64,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 8,
// VCO output divisor for PLL output clock (CLKOUT3)
parameter MMCM_VCO = 1200,
// Max Freq (MHz) of MMCM VCO
parameter MMCM_MULT_F = 9,
// write MMCM VCO multiplier
parameter MMCM_DIVCLK_DIVIDE = 1,
// write MMCM VCO divisor
parameter MMCM_CLKOUT0_EN = "FALSE",
// "TRUE" - MMCM output clock (CLKOUT0) is enabled
// "FALSE" - MMCM output clock (CLKOUT0) is disabled
parameter MMCM_CLKOUT1_EN = "FALSE",
// "TRUE" - MMCM output clock (CLKOUT1) is enabled
// "FALSE" - MMCM output clock (CLKOUT1) is disabled
parameter MMCM_CLKOUT2_EN = "FALSE",
// "TRUE" - MMCM output clock (CLKOUT2) is enabled
// "FALSE" - MMCM output clock (CLKOUT2) is disabled
parameter MMCM_CLKOUT3_EN = "FALSE",
// "TRUE" - MMCM output clock (CLKOUT3) is enabled
// "FALSE" - MMCM output clock (CLKOUT3) is disabled
parameter MMCM_CLKOUT4_EN = "FALSE",
// "TRUE" - MMCM output clock (CLKOUT4) is enabled
// "FALSE" - MMCM output clock (CLKOUT4) is disabled
parameter MMCM_CLKOUT0_DIVIDE = 1.000,
// VCO output divisor for MMCM output clock (CLKOUT0)
parameter MMCM_CLKOUT1_DIVIDE = 1,
// VCO output divisor for MMCM output clock (CLKOUT1)
parameter MMCM_CLKOUT2_DIVIDE = 1,
// VCO output divisor for MMCM output clock (CLKOUT2)
parameter MMCM_CLKOUT3_DIVIDE = 1,
// VCO output divisor for MMCM output clock (CLKOUT3)
parameter MMCM_CLKOUT4_DIVIDE = 1,
// VCO output divisor for MMCM output clock (CLKOUT4)
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tCKE = 7500,
// memory tCKE paramter in pS
parameter tFAW = 45000,
// memory tRAW paramter in pS.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter in pS.
parameter tRAS = 40000,
// memory tRAS paramter in pS.
parameter tRCD = 15000,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 127500,
// memory tRFC paramter in pS.
parameter tRP = 12500,
// memory tRP paramter in pS.
parameter tRRD = 10000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b0101,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'hFFC_3F7_FFF_3FE,
parameter PHY_1_BITLANES = 48'h000_000_000_000,
parameter PHY_2_BITLANES = 48'h000_000_000_000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_03,
parameter ADDR_MAP
= 192'h000_000_000_010_033_01A_019_032_03A_034_018_036_012_011_017_015,
parameter BANK_MAP = 36'h013_016_01B,
parameter CAS_MAP = 12'h039,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_038,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_035,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_037,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h014,
parameter WE_MAP = 12'h03B,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02_00,
parameter DATA0_MAP = 96'h008_004_009_007_005_001_006_003,
parameter DATA1_MAP = 96'h022_028_020_024_027_025_026_021,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_029_002,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter DATA_IO_IDLE_PWRDWN = "ON",
// # = "ON", "OFF"
parameter BANK_TYPE = "HR_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "HR_LP",
// # = "HP_LP", "HR_LP", "DEFAULT"
parameter CKE_ODT_AUX = "FALSE",
parameter USER_REFRESH = "OFF",
parameter WRLVL = "OFF",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "NORM",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IODELAY_GRP0 = "BD_MIG_7SERIES_0_0_IODELAY_MIG0",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (200MHz).
parameter SYSCLK_TYPE = "NO_BUFFER",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "NO_BUFFER",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter CMD_PIPE_PLUS1 = "ON",
// add pipeline stage between MC and PHY
parameter DRAM_TYPE = "DDR2",
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 4000,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "TRUE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
parameter UI_EXTRA_CLOCKS = "TRUE",
// Generates extra clocks as
// 1/2, 1/4 and 1/8 of fabrick clock.
// Valid for DDR2/DDR3 AXI interfaces
// based on GUI selection
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_MEM_SIZE = "134217728",
// Address Space required for this component
parameter C_S_AXI_ADDR_WIDTH = 32,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_MC_nCK_PER_CLK = 2,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
// "WRITE_PRIORITY", "WRITE_PRIORITY_REG"
parameter C_S_AXI_REG_EN0 = 20'h00000,
// C_S_AXI_REG_EN0[00] = Reserved
// C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE
parameter C_S_AXI_REG_EN1 = 20'h00000,
// Instatiates register slices after the upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
// 7 => ADDRESS = Optimized for address channel
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Base address of AXI4 Memory Mapped bus.
parameter C_ECC_ONOFF_RESET_VALUE = 1,
// Controls ECC on/off value at startup/reset
parameter C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Temparature monitor parameter
//***************************************************************************
parameter TEMP_MON_CONTROL = "INTERNAL"
// # = "INTERNAL", "EXTERNAL"
// parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr2_dq,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
inout [DQS_WIDTH-1:0] ddr2_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr2_addr,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CK_WIDTH-1:0] ddr2_ck_p,
output [CK_WIDTH-1:0] ddr2_ck_n,
output [CKE_WIDTH-1:0] ddr2_cke,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n,
output [DM_WIDTH-1:0] ddr2_dm,
output [ODT_WIDTH-1:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output ui_addn_clk_0,
output ui_addn_clk_1,
output ui_addn_clk_2,
output ui_addn_clk_3,
output ui_addn_clk_4,
output mmcm_locked,
input aresetn,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
localparam RANK_WIDTH = clogb2(RANKS);
localparam ECC_WIDTH = (ECC == "OFF")?
0 : (DATA_WIDTH <= 4)?
4 : (DATA_WIDTH <= 10)?
5 : (DATA_WIDTH <= 26)?
6 : (DATA_WIDTH <= 57)?
7 : (DATA_WIDTH <= 120)?
8 : (DATA_WIDTH <= 247)?
9 : 10;
localparam DATA_BUF_OFFSET_WIDTH = 1;
localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH
+ DATA_BUF_OFFSET_WIDTH;
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam TEMP_MON_EN = (SIMULATION == "FALSE") ? "ON" : "OFF";
// Enable or disable the temp monitor module
localparam tTEMPSAMPLE = 10000000; // sample every 10 us
localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock
localparam TAPSPERKCLK = 56;
// Wire declarations
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
wire clk;
wire [1:0] clk_ref;
wire [1:0] iodelay_ctrl_rdy;
wire clk_ref_in;
wire sys_rst_o;
wire clk_div2;
wire rst_div2;
wire freq_refclk ;
wire mem_refclk ;
wire pll_lock ;
wire sync_pulse;
wire mmcm_ps_clk;
wire poc_sample_pd;
wire psen;
wire psincdec;
wire psdone;
wire iddr_rst;
wire ref_dll_lock;
wire rst_phaser_ref;
wire pll_locked;
wire rst;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;
wire ddr2_reset_n;
wire ddr2_parity;
// AXI CTRL port
wire s_axi_ctrl_awvalid;
wire s_axi_ctrl_awready;
wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr;
// Slave Interface Write Data Ports
wire s_axi_ctrl_wvalid;
wire s_axi_ctrl_wready;
wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata;
// Slave Interface Write Response Ports
wire s_axi_ctrl_bvalid;
wire s_axi_ctrl_bready;
wire [1:0] s_axi_ctrl_bresp;
// Slave Interface Read Address Ports
wire s_axi_ctrl_arvalid;
wire s_axi_ctrl_arready;
wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr;
// Slave Interface Read Data Ports
wire s_axi_ctrl_rvalid;
wire s_axi_ctrl_rready;
wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata;
wire [1:0] s_axi_ctrl_rresp;
// Interrupt output
wire interrupt;
wire sys_clk_p;
wire sys_clk_n;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire [11:0] device_temp;
wire [11:0] device_temp_i;
// Debug port signals
wire dbg_idel_down_all;
wire dbg_idel_down_cpt;
wire dbg_idel_up_all;
wire dbg_idel_up_cpt;
wire dbg_sel_all_idel_cpt;
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
wire dbg_sel_pi_incdec;
wire [DQS_CNT_WIDTH:0] dbg_byte_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire [5:0] dbg_pi_counter_read_val;
wire [8:0] dbg_po_counter_read_val;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;
wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;
wire [255:0] dbg_calib_top;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;
wire [(6*RANKS)-1:0] dbg_rd_data_offset;
wire [255:0] dbg_phy_rdlvl;
wire [99:0] dbg_phy_wrcal;
wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;
wire [255:0] dbg_phy_wrlvl;
wire [255:0] dbg_phy_init;
wire [255:0] dbg_prbs_rdlvl;
wire [255:0] dbg_dqs_found_cal;
wire dbg_pi_phaselock_start;
wire dbg_pi_phaselocked_done;
wire dbg_pi_phaselock_err;
wire dbg_pi_dqsfound_start;
wire dbg_pi_dqsfound_done;
wire dbg_pi_dqsfound_err;
wire dbg_wrcal_start;
wire dbg_wrcal_done;
wire dbg_wrcal_err;
wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;
wire [11:0] dbg_pi_phase_locked_phy4lanes;
wire dbg_oclkdelay_calib_start;
wire dbg_oclkdelay_calib_done;
wire [255:0] dbg_phy_oclkdelay_cal;
wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;
wire dbg_rddata_valid;
wire [1:0] dbg_rdlvl_done;
wire [1:0] dbg_rdlvl_err;
wire [1:0] dbg_rdlvl_start;
wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;
wire [5:0] dbg_tap_cnt_during_wrlvl;
wire dbg_wl_edge_detect_valid;
wire dbg_wrlvl_done;
wire dbg_wrlvl_err;
wire dbg_wrlvl_start;
reg [63:0] dbg_rddata_r;
reg dbg_rddata_valid_r;
wire [53:0] ocal_tap_cnt;
wire [4:0] dbg_dqs;
wire [8:0] dbg_bit;
wire [8:0] rd_data_edge_detect_r;
wire [53:0] wl_po_fine_cnt;
wire [26:0] wl_po_coarse_cnt;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;
wire [5:0] dbg_data_offset;
wire [5:0] dbg_data_offset_1;
wire [5:0] dbg_data_offset_2;
wire [390:0] ddr2_ila_wrpath_int;
wire [1023:0] ddr2_ila_rdpath_int;
wire [119:0] ddr2_ila_basic_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;
//***************************************************************************
assign ui_clk = clk;
assign ui_clk_sync_rst = rst;
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
assign clk_ref_p = 1'b0;
assign clk_ref_n = 1'b0;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v4_0_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP0 (IODELAY_GRP0),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
.clk_ref (clk_ref),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.sys_rst (sys_rst)
);
mig_7series_v4_0_clk_ibuf #
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_ddr2_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
// Temperature monitoring logic
generate
if (TEMP_MON_EN == "ON") begin: temp_mon_enabled
mig_7series_v4_0_tempmon #
(
.TCQ (TCQ),
.TEMP_MON_CONTROL (TEMP_MON_CONTROL),
.XADC_CLK_PERIOD (XADC_CLK_PERIOD),
.tTEMPSAMPLE (tTEMPSAMPLE)
)
u_tempmon
(
.clk (clk),
.xadc_clk (clk_ref[0]),
.rst (rst),
.device_temp_i (device_temp_i),
.device_temp (device_temp)
);
end else begin: temp_mon_disabled
assign device_temp = 'b0;
end
endgenerate
mig_7series_v4_0_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.UI_EXTRA_CLOCKS (UI_EXTRA_CLOCKS),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.MMCM_VCO (MMCM_VCO),
.MMCM_MULT_F (MMCM_MULT_F),
.MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
.MMCM_CLKOUT0_EN (MMCM_CLKOUT0_EN),
.MMCM_CLKOUT1_EN (MMCM_CLKOUT1_EN),
.MMCM_CLKOUT2_EN (MMCM_CLKOUT2_EN),
.MMCM_CLKOUT3_EN (MMCM_CLKOUT3_EN),
.MMCM_CLKOUT4_EN (MMCM_CLKOUT4_EN),
.MMCM_CLKOUT0_DIVIDE (MMCM_CLKOUT0_DIVIDE),
.MMCM_CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE),
.MMCM_CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE),
.MMCM_CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE),
.MMCM_CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW),
.tCK (tCK),
.MEM_TYPE (DRAM_TYPE)
)
u_ddr2_infrastructure
(
// Outputs
.rstdiv0 (rst),
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
// .auxout_clk (),
.ui_addn_clk_0 (ui_addn_clk_0),
.ui_addn_clk_1 (ui_addn_clk_1),
.ui_addn_clk_2 (ui_addn_clk_2),
.ui_addn_clk_3 (ui_addn_clk_3),
.ui_addn_clk_4 (ui_addn_clk_4),
.pll_locked (pll_locked),
.mmcm_locked (mmcm_locked),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.psen (psen),
.psincdec (psincdec),
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v4_0_memc_ui_top_axi #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.IODELAY_GRP0 (IODELAY_GRP0),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.CL (CL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.IDELAY_ADJ ("OFF"),
.FINE_PER_BIT ("OFF"),
.CENTER_COMP_MODE ("OFF"),
.PI_VAL_ADJ ("OFF"),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S_AXI_BASEADDR),
.C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE),
.C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB ("FALSE"),
.FPGA_VOLT_TYPE ("N")
)
u_memc_ui_top_axi
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_locked),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.psen (psen),
.psincdec (psincdec),
.rst (rst),
.rst_phaser_ref (rst_phaser_ref),
.ref_dll_lock (ref_dll_lock),
// Memory interface ports
.ddr_dq (ddr2_dq),
.ddr_dqs_n (ddr2_dqs_n),
.ddr_dqs (ddr2_dqs_p),
.ddr_addr (ddr2_addr),
.ddr_ba (ddr2_ba),
.ddr_cas_n (ddr2_cas_n),
.ddr_ck_n (ddr2_ck_n),
.ddr_ck (ddr2_ck_p),
.ddr_cke (ddr2_cke),
.ddr_cs_n (ddr2_cs_n),
.ddr_dm (ddr2_dm),
.ddr_odt (ddr2_odt),
.ddr_ras_n (ddr2_ras_n),
.ddr_reset_n (ddr2_reset_n),
.ddr_parity (ddr2_parity),
.ddr_we_n (ddr2_we_n),
.bank_mach_next (bank_mach_next),
// Application interface ports
.app_ecc_multiple_err_o (),
.app_ecc_single_err (),
.device_temp (device_temp),
.calib_tap_req (),
.calib_tap_load (1'b0),
.calib_tap_addr (7'b0),
.calib_tap_val (8'b0),
.calib_tap_load_done (1'b0),
// Debug logic ports
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.aresetn (aresetn),
.app_sr_req (1'b0),
.app_sr_active (app_sr_active),
.app_ref_req (1'b0),
.app_ref_ack (app_ref_ack),
.app_zq_req (1'b0),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// AXI CTRL port
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
.s_axi_ctrl_awready (s_axi_ctrl_awready),
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
// Slave Interface Write Data Ports
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
.s_axi_ctrl_wready (s_axi_ctrl_wready),
.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
// Slave Interface Write Response Ports
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
.s_axi_ctrl_bready (s_axi_ctrl_bready),
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),
// Slave Interface Read Address Ports
.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
.s_axi_ctrl_arready (s_axi_ctrl_arready),
.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
// Slave Interface Read Data Ports
.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
.s_axi_ctrl_rready (s_axi_ctrl_rready),
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
// Interrupt output
.interrupt (interrupt),
.init_calib_complete (init_calib_complete),
.dbg_poc (dbg_poc)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
assign dbg_byte_sel = 'd0;
assign dbg_sel_pi_incdec = 1'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
assign dbg_sel_po_incdec = 'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_PP_BLACKBOX_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_2_V
`define SKY130_FD_SC_MS__NOR3_2_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_2_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length Encoder, intermediate results ////
//// ////
//// - Translate DC and AC coeff. into: ////
//// 1) zero-run-length ////
//// 2) bit-size for amplitude ////
//// 3) amplitude ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rle1.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rle1.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rle1(clk, rst, ena, go, din, rlen, size, amp, den, dcterm);
//
// parameters
//
//
// inputs & outputs
//
input clk; // system clock
input rst; // asynchronous reset
input ena; // clock enable
input go;
input [11:0] din; // data input
output [ 3:0] rlen; // run-length
output [ 3:0] size; // size (or category)
output [11:0] amp; // amplitude
output den; // data output enable
output dcterm; // DC-term (start of new block)
reg [ 3:0] rlen, size;
reg [11:0] amp;
reg den, dcterm;
//
// variables
//
reg [5:0] sample_cnt;
reg [3:0] zero_cnt;
wire is_zero;
reg state;
parameter dc = 1'b0;
parameter ac = 1'b1;
//
// module body
//
//
// function declarations
//
// Function abs; absolute value
function [10:0] abs;
input [11:0] a;
begin
if (a[11])
abs = (~a[10:0]) +11'h1;
else
abs = a[10:0];
end
endfunction
// Function cat, calculates category for Din
function [3:0] cat;
input [11:0] a;
reg [10:0] tmp;
begin
// get absolute value
tmp = abs(a);
// determine category
casex(tmp) // synopsys full_case parallel_case
11'b1??_????_???? : cat = 4'hb; // 1024..2047
11'b01?_????_???? : cat = 4'ha; // 512..1023
11'b001_????_???? : cat = 4'h9; // 256.. 511
11'b000_1???_???? : cat = 4'h8; // 128.. 255
11'b000_01??_???? : cat = 4'h7; // 64.. 127
11'b000_001?_???? : cat = 4'h6; // 32.. 63
11'b000_0001_???? : cat = 4'h5; // 16.. 31
11'b000_0000_1??? : cat = 4'h4; // 8.. 15
11'b000_0000_01?? : cat = 4'h3; // 4.. 7
11'b000_0000_001? : cat = 4'h2; // 2.. 3
11'b000_0000_0001 : cat = 4'h1; // 1
11'b000_0000_0000 : cat = 4'h0; // 0 (DC only)
endcase
end
endfunction
// Function modamp, calculate additional bits per category
function [10:0] rem;
input [11:0] a;
reg [10:0] tmp, tmp_rem;
begin
tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0];
if(0)
begin
// get absolute value
tmp = abs(a);
casex(tmp) // synopsys full_case parallel_case
11'b1??_????_???? : rem = tmp_rem & 11'b111_1111_1111;
11'b01?_????_???? : rem = tmp_rem & 11'b011_1111_1111;
11'b001_????_???? : rem = tmp_rem & 11'b001_1111_1111;
11'b000_1???_???? : rem = tmp_rem & 11'b000_1111_1111;
11'b000_01??_???? : rem = tmp_rem & 11'b000_0111_1111;
11'b000_001?_???? : rem = tmp_rem & 11'b000_0011_1111;
11'b000_0001_???? : rem = tmp_rem & 11'b000_0001_1111;
11'b000_0000_1??? : rem = tmp_rem & 11'b000_0000_1111;
11'b000_0000_01?? : rem = tmp_rem & 11'b000_0000_0111;
11'b000_0000_001? : rem = tmp_rem & 11'b000_0000_0011;
11'b000_0000_0001 : rem = tmp_rem & 11'b000_0000_0001;
11'b000_0000_0000 : rem = tmp_rem & 11'b000_0000_0000;
endcase
end
else
rem = tmp_rem;
end
endfunction
// detect zero
assign is_zero = ~|din;
// assign dout
always @(posedge clk)
if (ena)
amp <= #1 rem(din);
// generate sample counter
always @(posedge clk)
if (ena)
if (go)
sample_cnt <= #1 1; // count AC-terms, 'go=1' is sample-zero
else
sample_cnt <= #1 sample_cnt +1;
// generate zero counter
always @(posedge clk)
if (ena)
if (is_zero)
zero_cnt <= #1 zero_cnt +1;
else
zero_cnt <= #1 0;
// statemachine, create intermediate results
always @(posedge clk or negedge rst)
if(!rst)
begin
state <= #1 dc;
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
else if (ena)
case (state) // synopsys full_case parallel_case
dc:
begin
rlen <= #1 0;
size <= #1 cat(din);
if(go)
begin
state <= #1 ac;
den <= #1 1'b1;
dcterm <= #1 1'b1;
end
else
begin
state <= #1 dc;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
end
ac:
if(&sample_cnt) // finished current block
begin
state <= #1 dc;
if (is_zero) // last sample zero? send EOB
begin
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
else
begin
rlen <= #1 zero_cnt;
size <= #1 cat(din);
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
end
else
begin
state <= #1 ac;
rlen <= #1 zero_cnt;
dcterm <= #1 1'b0;
if (is_zero)
begin
size <= #1 0;
den <= #1 &zero_cnt;
end
else
begin
size <= #1 cat(din);
den <= #1 1'b1;
end
end
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A31OI_BEHAVIORAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31OI_BEHAVIORAL_V |
/*
* In The Name Of God
* ========================================
* [] File Name : cache_ctl.v
*
* [] Creation Date : 04-03-2015
*
* [] Last Modified : Mon 30 Mar 2015 06:37:53 PM IRDT
*
* [] Created By : Parham Alvani ([email protected])
* =======================================
*/
`timescale 1 ns/100 ps
module cache_ctl (enable, clk, index, word, comp,
write, tag_in, data_in, valid_in,
rst, hit, dirty, tag_out,
data_out, valid);
input clk;
input enable;
input [0:3] index;
input [0:1] word;
input comp;
input write;
input [0:4] tag_in;
input [0:15] data_in;
input valid_in;
input rst;
output reg hit;
output reg dirty;
output reg [0:4] tag_out;
output reg [0:15] data_out;
output reg valid;
reg cache_en;
reg cache_rst;
reg [0:3] cache_index;
reg [0:1] cache_word;
reg cache_cmp;
reg cache_wr;
reg [0:4] cache_tag_in;
reg [0:15] cache_in;
reg cache_valid_in;
wire cache_hit;
wire cache_dirty_out;
wire [0:4] cache_tag_out;
wire [0:15] cache_out;
wire cache_valid_out;
wire cache_ack;
cache cache_ins(cache_en, cache_index, cache_word, cache_cmp, cache_wr, cache_tag_in,
cache_in, cache_valid_in, cache_rst, cache_hit, cache_dirty_out,
cache_tag_out, cache_out, cache_valid_out, cache_ack);
always @ (posedge clk) begin
if (enable) begin
cache_rst = rst;
cache_word = word;
cache_index = index;
cache_cmp = comp;
cache_wr = write;
cache_tag_in = tag_in;
cache_in = data_in;
cache_valid_in = valid_in;
cache_en = 1'b1;
wait (cache_ack) begin
hit = cache_hit;
dirty = cache_dirty_out;
tag_out = cache_tag_out;
valid = cache_valid_out;
data_out = cache_out;
end
end else begin
cache_en = 1'b0;
end
end
always @ (negedge clk) begin
cache_en = 1'b0;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: tlu_pib.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: Performance Instrumentation Block
// Performance monitoring 2 of the 9 possible events
// can be tracked per thread
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "tlu.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module tlu_pib (/*AUTOARG*/
// input
ifu_tlu_imiss_e, ifu_tlu_immu_miss_m, ifu_tlu_thrid_d,
ifu_tlu_sraddr_d, ifu_tlu_rsr_inst_d, // ifu_tlu_wsr_inst_d,
ifu_tlu_l2imiss, tlu_tcc_inst_w, lsu_tlu_wsr_inst_e,
ffu_tlu_fpu_tid, ffu_tlu_fpu_cmplt,
lsu_tlu_dmmu_miss_g, lsu_tlu_dcache_miss_w2, lsu_tlu_l2_dmiss,
lsu_tlu_stb_full_w2, exu_tlu_wsr_data_m, // tlu_tickcmp_sel,
tlu_hpstate_priv, tlu_thread_inst_vld_g, tlu_wsr_inst_nq_g,
tlu_full_flush_pipe_w2, tlu_pstate_priv, tlu_thread_wsel_g,
tlu_pib_rsr_data_e, tlu_hpstate_enb, ifu_tlu_flush_fd_w,
//
// reset was modified to abide to the Niagara reset methodology
rclk, arst_l, grst_l, si, se, // tlu_rst_l, rst_tri_en,
// output
// tlu_pcr_ut_e, tlu_pcr_st_e,
pib_picl_wrap, pich_wrap_flg, pich_onebelow_flg, pich_twobelow_flg,
tlu_pic_onebelow_e, tlu_pic_twobelow_e, pib_priv_act_trap_m,
tlu_wsr_data_w, tlu_pcr_ut, tlu_pcr_st, tlu_pic_wrap_e, so);
// Input section
// Events generated by IFU
input ifu_tlu_imiss_e; // icache misses -- New interface
input ifu_tlu_immu_miss_m; // itlb misses
input [1:0] ifu_tlu_thrid_d; // thread id For instruction complete
input [`TLU_THRD_NUM-1:0] tlu_thread_inst_vld_g; // For instruction complete
input [`TLU_THRD_NUM-1:0] tlu_thread_wsel_g; // thread of instruction fetched
input [`TLU_THRD_NUM-1:0] ifu_tlu_l2imiss; // l2 imiss -- new interface
// ASR register read/write requests
input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d;
input ifu_tlu_rsr_inst_d; // valid rd sr(st/pr)
// input ifu_tlu_wsr_inst_d; // valid wr sr(st/pr)
input lsu_tlu_wsr_inst_e; // valid wr sr(st/pr)
// input tlu_wsr_inst_g; // valid wr sr(st/pr)
// modified for timing
input tlu_wsr_inst_nq_g; // valid wr sr(st/pr)
input [`TLU_ASR_DATA_WIDTH-1:0] exu_tlu_wsr_data_m; // pr/st data to irf.
// modified due to timing
// input [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // this was the tlu_exu_rsr_data_e
// LSU generated events - also include L2 miss
input [`TLU_THRD_NUM-1:0] lsu_tlu_dcache_miss_w2; // dcache miss -- new interface
input [`TLU_THRD_NUM-1:0] lsu_tlu_l2_dmiss; // l2 dmisses -- new interface
input [`TLU_THRD_NUM-1:0] lsu_tlu_stb_full_w2; // store buffer full -- new interface
input lsu_tlu_dmmu_miss_g; // dtlb misses
// FFU generated events - also include L2 miss
input [1:0] ffu_tlu_fpu_tid; // ThrdID for the FF instr_cmplt -- new
input ffu_tlu_fpu_cmplt; // FF instru complete -- new
// TLU information for event filtering
//
input [`TLU_THRD_NUM-1:0] tlu_pstate_priv; // supervisor privilege information
input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;// hypervisor privilege information
input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb; // hyperlite enabling
input tlu_tcc_inst_w; // For instruction complete
input tlu_full_flush_pipe_w2; // For instruction complete
input ifu_tlu_flush_fd_w; // For instruction complete
// Global signals
input rclk;
//
// reset was modified to abide to the Niagara reset methodology
// input reset;
// input tlu_rst_l;
input grst_l; // global reset - active log
input arst_l; // global reset - active log
input si; // global scan-in
input se; // global scan-out
// input rst_tri_en; // global reset - active log
// output section
// modified to make inst vld overflow trap precies
// output [`TLU_THRD_NUM-1:0] pib_pic_wrap; // pic register wrap transition
// output pib_rst_l; // local unit reset - active low
output [`TLU_THRD_NUM-1:0] pib_picl_wrap; // pic register wrap transition
output [`TLU_THRD_NUM-1:0] pich_wrap_flg; // pic register wrap transition
output [`TLU_THRD_NUM-1:0] pich_onebelow_flg; // pic register wrap transition
output [`TLU_THRD_NUM-1:0] pich_twobelow_flg; // pic register wrap transition
// output [`TLU_THRD_NUM-1:0] pich_threebelow_flg; // pic register wrap transition
// modified due to timing fixes
output [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // rsr data register data
output tlu_pic_onebelow_e, tlu_pic_twobelow_e, tlu_pic_wrap_e;
//
// modified for bug 5436 - Niagara 2.0
output [`TLU_THRD_NUM-1:0] tlu_pcr_ut;
output [`TLU_THRD_NUM-1:0] tlu_pcr_st;
wire tlu_pcr_ut_e, tlu_pcr_st_e;
//
// output [`TLU_THRD_NUM-1:0] pib_priv_act_trap; // access privilege violation for pics
output [`TLU_THRD_NUM-1:0] pib_priv_act_trap_m; // access privilege violation for pics
// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_e; // Add in the final muxing of pib asr data
output [`TLU_ASR_DATA_WIDTH-1:0] tlu_wsr_data_w; // flopped version of exu_tlu_wsr_data_m
// output [47:0] tlu_ifu_trappc_w2; // temporary for timing
// output [47:0] tlu_ifu_trapnpc_w2; // temporary for timing
output so; // global scan-out
//==============================================================================
// Local signal defines
//==============================================================================
// decoded address for pcr and pic
wire pcr_rw_e, pcr_rw_m, pcr_rw_g; // pcr_rw_d,
wire pic_priv_rw_e, pic_priv_rw_m, pic_priv_rw_g; // pic_priv_rw_d,
wire pic_npriv_rw_e, pic_npriv_rw_m, pic_npriv_rw_g;// pic_npriv_rw_d,
//
// read/write to pcr, evq and pic
wire [`TLU_THRD_NUM-1:0] wsr_thread_inst_g;
wire [`TLU_THRD_NUM-1:0] update_picl_sel, update_picl_wrap_en;
wire [`TLU_THRD_NUM-1:0] picl_cnt_wrap_datain;
wire [`TLU_THRD_NUM-1:0] update_pich_sel, update_pich_wrap_en;
wire [`TLU_THRD_NUM-1:0] pich_cnt_wrap_datain;
wire [`TLU_THRD_NUM-1:0] update_evq_sel;
wire [`TLU_THRD_NUM-1:0] wsr_pcr_sel;
wire [`TLU_THRD_NUM-1:0] wsr_pic_sel;
wire [`TLU_THRD_NUM-1:0] update_pich_ovf;
wire [`TLU_THRD_NUM-1:0] update_picl_ovf;
wire [`TLU_THRD_NUM-1:0] inst_vld_w2;
wire tcc_inst_w2;
//
// added for bug 2919
wire [`TLU_THRD_NUM-1:0] pic_update_ctl;
wire [1:0] pic_update_sel_ctr;
wire [1:0] pic_update_sel_incr;
//
// modified for timing
// wire [`TLU_ASR_ADDR_WIDTH-1:0] pib_sraddr_d;
wire [`TLU_ASR_ADDR_WIDTH-1:0] pib_sraddr_e;
wire tlu_rsr_inst_e, tlu_wsr_inst_e;
//
// picl masks
wire [`PICL_MASK_WIDTH-1:0] picl_mask0, picl_mask1, picl_mask2, picl_mask3;
wire [`PICL_MASK_WIDTH-1:0] picl_event0, picl_event1, picl_event2, picl_event3;
// added for bug2332
// wire incr_pich_onehot;
// pic counters
wire [`TLU_THRD_NUM-1:0] incr_pich;
wire [`TLU_THRD_NUM-1:0] pich_mux_sel;
wire [`TLU_THRD_NUM-1:0] pich_cnt_wrap;
wire [`TLU_THRD_NUM-1:0] picl_cnt_wrap;
wire [`TLU_THRD_NUM-2:0] thread_rsel_d;
wire [`TLU_THRD_NUM-2:0] thread_rsel_e;
wire [`TLU_THRD_NUM-1:0] pic_onebelow_e, pic_twobelow_e, pic_wrap_e;
wire [`PIB_PIC_CNT_WIDTH-1:0] picl_cnt0, picl_cnt1, picl_cnt2, picl_cnt3;
wire [`PIB_PIC_CNT_WIDTH-1:0] picl_cnt_din, picl_cnt_sum;
wire [`PIB_PIC_CNT_WIDTH-1:0] picl_wsr_data;
wire [`PIB_PIC_CNT_WIDTH-1:0] update_picl0_data, update_picl1_data;
wire [`PIB_PIC_CNT_WIDTH-1:0] update_picl2_data, update_picl3_data;
wire [`PIB_PIC_CNT_WIDTH-1:0] pich_cnt0, pich_cnt1, pich_cnt2, pich_cnt3;
wire [`PIB_PIC_CNT_WIDTH-1:0] pich_cnt_din, pich_cnt_sum;
wire [`PIB_PIC_CNT_WIDTH-1:0] pich_wsr_data;
wire [`PIB_PIC_CNT_WIDTH-1:0] update_pich0_data, update_pich1_data;
wire [`PIB_PIC_CNT_WIDTH-1:0] update_pich2_data, update_pich3_data;
wire [`TLU_ASR_DATA_WIDTH-1:0] pic_rdata_e;
wire [`TLU_ASR_DATA_WIDTH-1:0] pcr_rdata_e;
wire [`PIB_PCR_WIDTH-1:0] pcr_reg_rdata_e;
wire [`PIB_PCR_WIDTH-1:0] pcr_wdata_in;
wire [`TLU_THRD_NUM-1:0] picl_ovf_wdata_in;
wire [`TLU_THRD_NUM-1:0] pich_ovf_wdata_in;
// experiment
wire [`TLU_THRD_NUM-1:0] pich_fourbelow_din;
wire [`TLU_THRD_NUM-1:0] pich_fourbelow_flg;
// wire [`TLU_THRD_NUM-1:0] pich_threebelow_flg;
// modified due to timing
// wire [2:0] rsr_data_sel_e;
wire [1:0] rsr_data_sel_e;
// picl evqs
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0, picl_evq1, picl_evq2, picl_evq3;
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0_sum, picl_evq1_sum;
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq2_sum, picl_evq3_sum;
wire [`PIB_EVQ_CNT_WIDTH-1:0] update_evq0_data, update_evq1_data;
wire [`PIB_EVQ_CNT_WIDTH-1:0] update_evq2_data, update_evq3_data;
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq_din;
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0_din, picl_evq1_din;
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq2_din, picl_evq3_din;
wire [`TLU_THRD_NUM-1:0] incr_evq_din, incr_evq;
// pcr registers
wire [`PIB_PCR_WIDTH-1:0] pcr0, pcr1, pcr2, pcr3;
//
wire local_rst; // local active high reset
wire local_rst_l; // local active high reset
// counting enable indicator
wire [`TLU_THRD_NUM-1:0] pic_cnt_en, pic_cnt_en_w2;
//
// staged icache and itlb misses
wire imiss_m, imiss_g;
wire immu_miss_g;
//
// threaded icache, itlb, and dtlb misses
wire [`TLU_THRD_NUM-1:0] imiss_thread_g;
wire [`TLU_THRD_NUM-1:0] immu_miss_thread_g;
wire [`TLU_THRD_NUM-1:0] dmmu_miss_thread_g;
wire [`TLU_THRD_NUM-1:0] fpu_cmplt_thread;
//
// clock rename
wire clk;
//==============================================================================
// Code starts here
//==============================================================================
// reset
dffrl_async dffrl_local_rst_l(
.din (grst_l),
.clk (clk),
.rst_l(arst_l),
.q (local_rst_l),
.se (se),
.si (),
.so ()
);
assign local_rst = ~local_rst_l;
// assign pib_rst_l = local_rst_l;
// assign local_rst = ~tlu_rst_l;
//
// rename clock
assign clk = rclk;
//
// privilege action trap due to user access of pic register when
// PRIV bit is set in pcr
// modified for timing fixes
/*
assign pib_priv_act_trap = (pic_npriv_rw_g ) &
((pcr0[`PIB_PCR_PRIV] & tlu_thread_inst_vld_g[0]) &
~tlu_pstate_priv[0]) |
((pcr1[`PIB_PCR_PRIV] & tlu_thread_inst_vld_g[1]) &
~tlu_pstate_priv[1]) |
((pcr2[`PIB_PCR_PRIV] & tlu_thread_inst_vld_g[2]) &
~tlu_pstate_priv[2]) |
((pcr3[`PIB_PCR_PRIV] & tlu_thread_inst_vld_g[3]) &
~tlu_pstate_priv[3]);
*/
assign pib_priv_act_trap_m[0] = pic_npriv_rw_m & pcr0[`PIB_PCR_PRIV];
assign pib_priv_act_trap_m[1] = pic_npriv_rw_m & pcr1[`PIB_PCR_PRIV];
assign pib_priv_act_trap_m[2] = pic_npriv_rw_m & pcr2[`PIB_PCR_PRIV];
assign pib_priv_act_trap_m[3] = pic_npriv_rw_m & pcr3[`PIB_PCR_PRIV];
//
// staging the exu_tlu_wsr_data_w signal for timing
//
dff_s #(`TLU_ASR_DATA_WIDTH) dff_tlu_wsr_data_w (
.din (exu_tlu_wsr_data_m[`TLU_ASR_DATA_WIDTH-1:0]),
.q (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
//================================
// address decode for PCR and PICs
//================================
// added and modified for timing
// assign pib_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0] =
// ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0];
dff_s #(`TLU_ASR_ADDR_WIDTH) dff_pib_sraddr_e (
.din (ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0]),
.q (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
dffr_s dffr_tlu_rsr_inst_e (
.din (ifu_tlu_rsr_inst_d),
.q (tlu_rsr_inst_e),
.rst (local_rst),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// modified for timing
/*
dffr_s dffr_tlu_wsr_inst_e (
.din (ifu_tlu_wsr_inst_d),
.q (tlu_wsr_inst_e),
.rst (local_rst),
.clk (clk),
.se (se),
.si (),
.so ()
);
*/
assign tlu_wsr_inst_e = lsu_tlu_wsr_inst_e;
//
assign pcr_rw_e =
(pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PCR_ASR_ADDR);
assign pic_priv_rw_e =
(pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_PRIV_ADDR);
assign pic_npriv_rw_e =
(pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_NPRIV_ADDR) &
(tlu_rsr_inst_e | tlu_wsr_inst_e);
//
// staging of the ASR decoded controls
//
// staging from d to e stage
// deleted for timing
/*
dff_s dff_pcr_rw_d_e (
.din (pcr_rw_d),
.q (pcr_rw_e),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_pic_priv_rw_d_e (
.din (pic_priv_rw_d),
.q (pic_priv_rw_e),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_pic_npriv_rw_d_e (
.din (pic_npriv_rw_d),
.q (pic_npriv_rw_e),
.clk (clk),
.se (se),
.si (),
.so ()
);
*/
//
// staging from e to m stage
dff_s dff_pcr_rw_e_m (
.din (pcr_rw_e),
.q (pcr_rw_m),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_pic_priv_rw_e_m (
.din (pic_priv_rw_e),
.q (pic_priv_rw_m),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_pic_npriv_rw_e_m (
.din (pic_npriv_rw_e),
.q (pic_npriv_rw_m),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_imiss_e_m (
.din (ifu_tlu_imiss_e),
.q (imiss_m),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// staging from m to g stage
dff_s dff_pcr_rw_m_g (
.din (pcr_rw_m),
.q (pcr_rw_g),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_pic_priv_rw_m_g (
.din (pic_priv_rw_m),
.q (pic_priv_rw_g),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_pic_npriv_rw_m_g (
.din (pic_npriv_rw_m),
.q (pic_npriv_rw_g),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_imiss_m_g (
.din (imiss_m),
.q (imiss_g),
.clk (clk),
.se (se),
.si (),
.so ()
);
dff_s dff_immu_miss_m_g (
.din (ifu_tlu_immu_miss_m),
.q (immu_miss_g),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
//=========================
// update for PCR registers
//=========================
//
assign wsr_thread_inst_g[0] =
tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[0];
assign wsr_thread_inst_g[1] =
tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[1];
assign wsr_thread_inst_g[2] =
tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[2];
assign wsr_thread_inst_g[3] =
tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[3];
//
// extracting the relevant bits from the wsr data bus
assign pcr_wdata_in =
{tlu_wsr_data_w[`WSR_PCR_CH_OVF:`WSR_PCR_CL_OVF],
tlu_wsr_data_w[`WSR_PCR_SL_HI:`WSR_PCR_SL_LO],
tlu_wsr_data_w[`WSR_PCR_UT:`WSR_PCR_PRIV]};
//
// thread 0
assign wsr_pcr_sel[0] = wsr_thread_inst_g[0] & pcr_rw_g;
assign update_picl_ovf[0] =
(wsr_thread_inst_g[0] & pcr_rw_g) |
(picl_cnt_wrap[0] ^ picl_cnt0[`PIB_PIC_CNT_WIDTH-1]);
assign update_pich_ovf[0] =
(wsr_thread_inst_g[0] & pcr_rw_g) |
(pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]);
//
// modified for bug 2291
dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr0 (
// .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),
.din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),
.q (pcr0[`PIB_PCR_WIDTH-3:0]),
.rst (local_rst),
.en (wsr_pcr_sel[0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
mux2ds mux_pcr0_picl_ovf (
.in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),
.in1(picl_cnt_wrap[0] ^ picl_cnt0[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[0]),
.sel1(~wsr_pcr_sel[0]),
.dout(picl_ovf_wdata_in[0])
);
// added for the new bug 2588
dffre_s dffre_pcr0_picl_ovf (
.din (picl_ovf_wdata_in[0]),
.q (pcr0[`PIB_PCR_CL_OVF]),
.clk (clk),
.en (update_picl_ovf[0]),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
mux2ds mux_pcr0_pich_ovf (
.in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),
.in1(pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[0]),
.sel1(~wsr_pcr_sel[0]),
.dout(pich_ovf_wdata_in[0])
);
dffre_s dffre_pcr0_pich_ovf (
.din (pich_ovf_wdata_in[0]),
.q (pcr0[`PIB_PCR_CH_OVF]),
.clk (clk),
.en (update_pich_ovf[0]),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
//
// thread 1
assign wsr_pcr_sel[1] = wsr_thread_inst_g[1] & pcr_rw_g;
assign update_picl_ovf[1] =
(wsr_thread_inst_g[1] & pcr_rw_g) |
(picl_cnt_wrap[1] ^ picl_cnt1[`PIB_PIC_CNT_WIDTH-1]);
assign update_pich_ovf[1] =
(wsr_thread_inst_g[1] & pcr_rw_g) |
(pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]);
dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr1 (
// .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),
.din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),
.q (pcr1[`PIB_PCR_WIDTH-3:0]),
.rst (local_rst),
.en (wsr_pcr_sel[1]),
.clk (clk),
.se (se),
.si (),
.so ()
);
mux2ds mux_pcr1_picl_ovf (
.in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),
.in1(picl_cnt_wrap[1] ^ picl_cnt1[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[1]),
.sel1(~wsr_pcr_sel[1]),
.dout(picl_ovf_wdata_in[1])
);
// added for the new bug 2588
dffre_s dffre_pcr1_picl_ovf (
.din (picl_ovf_wdata_in[1]),
.q (pcr1[`PIB_PCR_CL_OVF]),
.clk (clk),
.en (update_picl_ovf[1]),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
mux2ds mux_pcr1_pich_ovf (
.in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),
.in1(pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[1]),
.sel1(~wsr_pcr_sel[1]),
.dout(pich_ovf_wdata_in[1])
);
dffre_s dffre_pcr1_pich_ovf (
.din (pich_ovf_wdata_in[1]),
.q (pcr1[`PIB_PCR_CH_OVF]),
.clk (clk),
.en (update_pich_ovf[1]),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
//
// thread 2
assign wsr_pcr_sel[2] = wsr_thread_inst_g[2] & pcr_rw_g;
assign update_picl_ovf[2] =
(wsr_thread_inst_g[2] & pcr_rw_g) |
(picl_cnt_wrap[2] ^ picl_cnt2[`PIB_PIC_CNT_WIDTH-1]);
assign update_pich_ovf[2] =
(wsr_thread_inst_g[2] & pcr_rw_g) |
(pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]);
dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr2 (
// .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),
.din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),
.q (pcr2[`PIB_PCR_WIDTH-3:0]),
.rst (local_rst),
.en (wsr_pcr_sel[2]),
.clk (clk),
.se (se),
.si (),
.so ()
);
mux2ds mux_pcr2_picl_ovf (
.in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),
.in1(picl_cnt_wrap[2] ^ picl_cnt2[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[2]),
.sel1(~wsr_pcr_sel[2]),
.dout(picl_ovf_wdata_in[2])
);
// added for the new bug 2588
dffre_s dffre_pcr2_picl_ovf (
.din (picl_ovf_wdata_in[2]),
.q (pcr2[`PIB_PCR_CL_OVF]),
.clk (clk),
.en (update_picl_ovf[2]),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
mux2ds mux_pcr2_pich_ovf (
.in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),
.in1(pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[2]),
.sel1(~wsr_pcr_sel[2]),
.dout(pich_ovf_wdata_in[2])
);
dffre_s dffre_pcr2_pich_ovf (
.din (pich_ovf_wdata_in[2]),
.q (pcr2[`PIB_PCR_CH_OVF]),
.clk (clk),
.en (update_pich_ovf[2]),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
//
// thread 3
assign wsr_pcr_sel[3] = wsr_thread_inst_g[3] & pcr_rw_g;
assign update_picl_ovf[3] =
(wsr_thread_inst_g[3] & pcr_rw_g) |
(picl_cnt_wrap[3] ^ picl_cnt3[`PIB_PIC_CNT_WIDTH-1]);
assign update_pich_ovf[3] =
(wsr_thread_inst_g[3] & pcr_rw_g) |
(pich_cnt_wrap[3] ^ pich_cnt3[`PIB_PIC_CNT_WIDTH-1]);
dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr3 (
// .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),
.din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),
.q (pcr3[`PIB_PCR_WIDTH-3:0]),
.rst (local_rst),
.en (wsr_pcr_sel[3]),
.clk (clk),
.se (se),
.si (),
.so ()
);
mux2ds mux_pcr3_picl_ovf (
.in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),
.in1(picl_cnt_wrap[3] ^ picl_cnt3[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[3]),
.sel1(~wsr_pcr_sel[3]),
.dout(picl_ovf_wdata_in[3])
);
// added for the new bug 2588
dffre_s dffre_pcr3_picl_ovf (
.din (picl_ovf_wdata_in[3]),
.q (pcr3[`PIB_PCR_CL_OVF]),
.clk (clk),
.en (update_picl_ovf[3]),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
mux2ds mux_pcr3_pich_ovf (
.in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),
.in1(pich_cnt_wrap[3] ^ pich_cnt3[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[3]),
.sel1(~wsr_pcr_sel[3]),
.dout(pich_ovf_wdata_in[3])
);
dffre_s dffre_pcr3_pich_ovf (
.din (pich_ovf_wdata_in[3]),
.q (pcr3[`PIB_PCR_CH_OVF]),
.clk (clk),
.en (update_pich_ovf[3]),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
//
//====================
// threading of events
//====================
//
// icache misses
assign imiss_thread_g[0] = imiss_g & tlu_thread_wsel_g[0];
assign imiss_thread_g[1] = imiss_g & tlu_thread_wsel_g[1];
assign imiss_thread_g[2] = imiss_g & tlu_thread_wsel_g[2];
assign imiss_thread_g[3] = imiss_g & tlu_thread_wsel_g[3];
//
// itlb misses
assign immu_miss_thread_g[0] = immu_miss_g & tlu_thread_wsel_g[0];
assign immu_miss_thread_g[1] = immu_miss_g & tlu_thread_wsel_g[1];
assign immu_miss_thread_g[2] = immu_miss_g & tlu_thread_wsel_g[2];
assign immu_miss_thread_g[3] = immu_miss_g & tlu_thread_wsel_g[3];
//
// dtlb misses
assign dmmu_miss_thread_g[0] = lsu_tlu_dmmu_miss_g & tlu_thread_wsel_g[0];
assign dmmu_miss_thread_g[1] = lsu_tlu_dmmu_miss_g & tlu_thread_wsel_g[1];
assign dmmu_miss_thread_g[2] = lsu_tlu_dmmu_miss_g & tlu_thread_wsel_g[2];
assign dmmu_miss_thread_g[3] = lsu_tlu_dmmu_miss_g & tlu_thread_wsel_g[3];
//
// itlb misses
assign fpu_cmplt_thread[0] =
ffu_tlu_fpu_cmplt & (~ffu_tlu_fpu_tid[0] & ~ffu_tlu_fpu_tid[1]);
assign fpu_cmplt_thread[1] =
ffu_tlu_fpu_cmplt & (ffu_tlu_fpu_tid[0] & ~ffu_tlu_fpu_tid[1]);
assign fpu_cmplt_thread[2] =
ffu_tlu_fpu_cmplt & (~ffu_tlu_fpu_tid[0] & ffu_tlu_fpu_tid[1]);
assign fpu_cmplt_thread[3] =
ffu_tlu_fpu_cmplt & (ffu_tlu_fpu_tid[0] & ffu_tlu_fpu_tid[1]);
//====================
// assigning of events
//====================
//
// thread 0
assign picl_event0[`PICL_MASK_SB_FULL] = lsu_tlu_stb_full_w2[0];
assign picl_event0[`PICL_MASK_FP_INST] = fpu_cmplt_thread[0];
assign picl_event0[`PICL_MASK_IC_MISS] = imiss_thread_g[0];
assign picl_event0[`PICL_MASK_DC_MISS] = lsu_tlu_dcache_miss_w2[0];
assign picl_event0[`PICL_MASK_ITLB_MISS] = immu_miss_thread_g[0];
assign picl_event0[`PICL_MASK_DTLB_MISS] = dmmu_miss_thread_g[0];
assign picl_event0[`PICL_MASK_L2_IMISS] = ifu_tlu_l2imiss[0];
assign picl_event0[`PICL_MASK_L2_DMISS] = lsu_tlu_l2_dmiss[0];
//
// thread 1
assign picl_event1[`PICL_MASK_SB_FULL] = lsu_tlu_stb_full_w2[1];
assign picl_event1[`PICL_MASK_FP_INST] = fpu_cmplt_thread[1];
assign picl_event1[`PICL_MASK_IC_MISS] = imiss_thread_g[1];
assign picl_event1[`PICL_MASK_DC_MISS] = lsu_tlu_dcache_miss_w2[1];
assign picl_event1[`PICL_MASK_ITLB_MISS] = immu_miss_thread_g[1];
assign picl_event1[`PICL_MASK_DTLB_MISS] = dmmu_miss_thread_g[1];
assign picl_event1[`PICL_MASK_L2_IMISS] = ifu_tlu_l2imiss[1];
assign picl_event1[`PICL_MASK_L2_DMISS] = lsu_tlu_l2_dmiss[1];
//
// thread 2
assign picl_event2[`PICL_MASK_SB_FULL] = lsu_tlu_stb_full_w2[2];
assign picl_event2[`PICL_MASK_FP_INST] = fpu_cmplt_thread[2];
assign picl_event2[`PICL_MASK_IC_MISS] = imiss_thread_g[2];
assign picl_event2[`PICL_MASK_DC_MISS] = lsu_tlu_dcache_miss_w2[2];
assign picl_event2[`PICL_MASK_ITLB_MISS] = immu_miss_thread_g[2];
assign picl_event2[`PICL_MASK_DTLB_MISS] = dmmu_miss_thread_g[2];
assign picl_event2[`PICL_MASK_L2_IMISS] = ifu_tlu_l2imiss[2];
assign picl_event2[`PICL_MASK_L2_DMISS] = lsu_tlu_l2_dmiss[2];
//
// thread 3
assign picl_event3[`PICL_MASK_SB_FULL] = lsu_tlu_stb_full_w2[3];
assign picl_event3[`PICL_MASK_FP_INST] = fpu_cmplt_thread[3];
assign picl_event3[`PICL_MASK_IC_MISS] = imiss_thread_g[3];
assign picl_event3[`PICL_MASK_DC_MISS] = lsu_tlu_dcache_miss_w2[3];
assign picl_event3[`PICL_MASK_ITLB_MISS] = immu_miss_thread_g[3];
assign picl_event3[`PICL_MASK_DTLB_MISS] = dmmu_miss_thread_g[3];
assign picl_event3[`PICL_MASK_L2_IMISS] = ifu_tlu_l2imiss[3];
assign picl_event3[`PICL_MASK_L2_DMISS] = lsu_tlu_l2_dmiss[3];
//======================
// decode for PIC events
//======================
//
// thread 0
assign pic_cnt_en[0] =
(~tlu_hpstate_priv[0] & ~tlu_pstate_priv[0] & pcr0[`PIB_PCR_UT]) |
(~tlu_hpstate_enb[0] & tlu_hpstate_priv[0] & pcr0[`PIB_PCR_ST]) |
(tlu_hpstate_enb[0] & tlu_pstate_priv[0] & ~tlu_hpstate_priv[0] &
pcr0[`PIB_PCR_ST]);
//
// picl mask decodes
assign picl_mask0[`PICL_MASK_SB_FULL] =
((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_SB_FULL_CNT) &
pic_cnt_en[0]);
assign picl_mask0[`PICL_MASK_FP_INST] =
((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_FP_INST_CNT) &
pic_cnt_en[0]);
assign picl_mask0[`PICL_MASK_IC_MISS] =
((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_IC_MISS_CNT) &
pic_cnt_en[0]);
assign picl_mask0[`PICL_MASK_DC_MISS] =
((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DC_MISS_CNT) &
pic_cnt_en[0]);
assign picl_mask0[`PICL_MASK_ITLB_MISS] =
((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_ITLB_MISS_CNT) &
pic_cnt_en[0]);
assign picl_mask0[`PICL_MASK_DTLB_MISS] =
((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DTLB_MISS_CNT) &
pic_cnt_en[0]);
assign picl_mask0[`PICL_MASK_L2_IMISS] =
((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_IMISS_CNT) &
pic_cnt_en[0]);
assign picl_mask0[`PICL_MASK_L2_DMISS] =
((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_DMISS_CNT) &
pic_cnt_en[0]);
//
// thread 1
assign pic_cnt_en[1] =
(~tlu_hpstate_priv[1] & ~tlu_pstate_priv[1] & pcr1[`PIB_PCR_UT]) |
(~tlu_hpstate_enb[1] & tlu_hpstate_priv[1] & pcr1[`PIB_PCR_ST]) |
(tlu_hpstate_enb[1] & tlu_pstate_priv[1] & ~tlu_hpstate_priv[1] &
pcr1[`PIB_PCR_ST]);
//
// picl mask decodes
assign picl_mask1[`PICL_MASK_SB_FULL] =
((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_SB_FULL_CNT) &
pic_cnt_en[1]);
assign picl_mask1[`PICL_MASK_FP_INST] =
((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_FP_INST_CNT) &
pic_cnt_en[1]);
assign picl_mask1[`PICL_MASK_IC_MISS] =
((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_IC_MISS_CNT) &
pic_cnt_en[1]);
assign picl_mask1[`PICL_MASK_DC_MISS] =
((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DC_MISS_CNT) &
pic_cnt_en[1]);
assign picl_mask1[`PICL_MASK_ITLB_MISS] =
((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_ITLB_MISS_CNT) &
pic_cnt_en[1]);
assign picl_mask1[`PICL_MASK_DTLB_MISS] =
((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DTLB_MISS_CNT) &
pic_cnt_en[1]);
assign picl_mask1[`PICL_MASK_L2_IMISS] =
((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_IMISS_CNT) &
pic_cnt_en[1]);
assign picl_mask1[`PICL_MASK_L2_DMISS] =
((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_DMISS_CNT) &
pic_cnt_en[1]);
//
// thread 2
assign pic_cnt_en[2] =
(~tlu_hpstate_priv[2] & ~tlu_pstate_priv[2] & pcr2[`PIB_PCR_UT]) |
(~tlu_hpstate_enb[2] & tlu_hpstate_priv[2] & pcr2[`PIB_PCR_ST]) |
(tlu_hpstate_enb[2] & tlu_pstate_priv[2] & ~tlu_hpstate_priv[2] &
pcr2[`PIB_PCR_ST]);
//
// picl mask decodes
assign picl_mask2[`PICL_MASK_SB_FULL] =
((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_SB_FULL_CNT) &
pic_cnt_en[2]);
assign picl_mask2[`PICL_MASK_FP_INST] =
((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_FP_INST_CNT) &
pic_cnt_en[2]);
assign picl_mask2[`PICL_MASK_IC_MISS] =
((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_IC_MISS_CNT) &
pic_cnt_en[2]);
assign picl_mask2[`PICL_MASK_DC_MISS] =
((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DC_MISS_CNT) &
pic_cnt_en[2]);
assign picl_mask2[`PICL_MASK_ITLB_MISS] =
((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_ITLB_MISS_CNT) &
pic_cnt_en[2]);
assign picl_mask2[`PICL_MASK_DTLB_MISS] =
((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DTLB_MISS_CNT) &
pic_cnt_en[2]);
assign picl_mask2[`PICL_MASK_L2_IMISS] =
((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_IMISS_CNT) &
pic_cnt_en[2]);
assign picl_mask2[`PICL_MASK_L2_DMISS] =
((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_DMISS_CNT) &
pic_cnt_en[2]);
//
// thread 3
assign pic_cnt_en[3] =
(~tlu_hpstate_priv[3] & ~tlu_pstate_priv[3] & pcr3[`PIB_PCR_UT]) |
(~tlu_hpstate_enb[3] & tlu_hpstate_priv[3] & pcr3[`PIB_PCR_ST]) |
(tlu_hpstate_enb[3] & tlu_pstate_priv[3] & ~tlu_hpstate_priv[3] &
pcr3[`PIB_PCR_ST]);
//
// added for timing
dff_s #(`TLU_THRD_NUM) dff_pic_cnt_en_w2 (
.din (pic_cnt_en[`TLU_THRD_NUM-1:0]),
.q (pic_cnt_en_w2[`TLU_THRD_NUM-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// picl mask decodes
assign picl_mask3[`PICL_MASK_SB_FULL] =
((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_SB_FULL_CNT) &
pic_cnt_en[3]);
assign picl_mask3[`PICL_MASK_FP_INST] =
((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_FP_INST_CNT) &
pic_cnt_en[3]);
assign picl_mask3[`PICL_MASK_IC_MISS] =
((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_IC_MISS_CNT) &
pic_cnt_en[3]);
assign picl_mask3[`PICL_MASK_DC_MISS] =
((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DC_MISS_CNT) &
pic_cnt_en[3]);
assign picl_mask3[`PICL_MASK_ITLB_MISS] =
((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_ITLB_MISS_CNT) &
pic_cnt_en[3]);
assign picl_mask3[`PICL_MASK_DTLB_MISS] =
((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DTLB_MISS_CNT) &
pic_cnt_en[3]);
assign picl_mask3[`PICL_MASK_L2_IMISS] =
((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_IMISS_CNT) &
pic_cnt_en[3]);
assign picl_mask3[`PICL_MASK_L2_DMISS] =
((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_DMISS_CNT) &
pic_cnt_en[3]);
//==================================================================
// update the picls - could be sperated into a dp block if needed
//==================================================================
// added for bug 2919
// rrobin scheduler to choose thread to update
dffr_s #(2) dffr_pic_update_sel_ctr (
.din (pic_update_sel_incr[1:0]),
.q (pic_update_sel_ctr[1:0]),
.rst (local_rst),
.clk (clk),
.se (se),
.si (),
.so ()
);
assign pic_update_sel_incr[1:0] =
pic_update_sel_ctr[1:0] + 2'b01;
assign pic_update_ctl[0] =
~|(pic_update_sel_incr[1:0]);
assign pic_update_ctl[1] =
~pic_update_sel_incr[1] & pic_update_sel_incr[0];
assign pic_update_ctl[2] =
pic_update_sel_incr[1] & ~pic_update_sel_incr[0];
assign pic_update_ctl[3] =
&(pic_update_sel_incr[1:0]);
//
// EVQs for PICL
//
// masking events for increment for picl evq update
assign incr_evq_din[0] =
(|(picl_mask0[`PICL_MASK_WIDTH-1:0] &
picl_event0[`PICL_MASK_WIDTH-1:0]));
assign incr_evq_din[1] =
(|(picl_mask1[`PICL_MASK_WIDTH-1:0] &
picl_event1[`PICL_MASK_WIDTH-1:0]));
assign incr_evq_din[2] =
(|(picl_mask2[`PICL_MASK_WIDTH-1:0] &
picl_event2[`PICL_MASK_WIDTH-1:0]));
assign incr_evq_din[3] =
(|(picl_mask3[`PICL_MASK_WIDTH-1:0] &
picl_event3[`PICL_MASK_WIDTH-1:0]));
//
// added due to timing
dff_s #(`TLU_THRD_NUM) dff_incr_evq (
.din (incr_evq_din[`TLU_THRD_NUM-1:0]),
.q (incr_evq[`TLU_THRD_NUM-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// constructing controls to update the picl_evq
assign update_evq_sel[0] = (local_rst | pic_update_ctl[0] | incr_evq[0]);
assign update_evq_sel[1] = (local_rst | pic_update_ctl[1] | incr_evq[1]);
assign update_evq_sel[2] = (local_rst | pic_update_ctl[2] | incr_evq[2]);
assign update_evq_sel[3] = (local_rst | pic_update_ctl[3] | incr_evq[3]);
//
// increment evq count for each thread
// thread 0
tlu_addern_32 #(`PIB_EVQ_CNT_WIDTH,1) picl_evq0_adder (
.din (picl_evq0[`PIB_EVQ_CNT_WIDTH-1:0]),
.incr (1'b1),
.sum (picl_evq0_sum[`PIB_EVQ_CNT_WIDTH-1:0])
) ;
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_update_evq0_data (
.in0 ({`PIB_EVQ_CNT_WIDTH{1'b0}}),
.in1 (picl_evq0_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (local_rst | pic_update_ctl[0]),
.sel1 (~(local_rst | pic_update_ctl[0])),
.dout (update_evq0_data[`PIB_EVQ_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_EVQ_CNT_WIDTH) dff_picl_evq0 (
.din (update_evq0_data[`PIB_EVQ_CNT_WIDTH-1:0]),
.q (picl_evq0[`PIB_EVQ_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_evq_sel[0]),
.se (se),
.si (),
.so ()
);
//
// thread 1
tlu_addern_32 #(`PIB_EVQ_CNT_WIDTH,1) picl_evq1_adder (
.din (picl_evq1[`PIB_EVQ_CNT_WIDTH-1:0]),
.incr (1'b1),
.sum (picl_evq1_sum[`PIB_EVQ_CNT_WIDTH-1:0])
) ;
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_update_evq1_data (
.in0 ({`PIB_EVQ_CNT_WIDTH{1'b0}}),
.in1 (picl_evq1_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (local_rst | pic_update_ctl[1]),
.sel1 (~(local_rst | pic_update_ctl[1])),
.dout (update_evq1_data[`PIB_EVQ_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_EVQ_CNT_WIDTH) dff_picl_evq1 (
.din (update_evq1_data[`PIB_EVQ_CNT_WIDTH-1:0]),
.q (picl_evq1[`PIB_EVQ_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_evq_sel[1]),
.se (se),
.si (),
.so ()
);
//
// thread 2
tlu_addern_32 #(`PIB_EVQ_CNT_WIDTH,1) picl_evq2_adder (
.din (picl_evq2[`PIB_EVQ_CNT_WIDTH-1:0]),
.incr (1'b1),
.sum (picl_evq2_sum[`PIB_EVQ_CNT_WIDTH-1:0])
) ;
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_update_evq2_data (
.in0 ({`PIB_EVQ_CNT_WIDTH{1'b0}}),
.in1 (picl_evq2_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (local_rst | pic_update_ctl[2]),
.sel1 (~(local_rst | pic_update_ctl[2])),
.dout (update_evq2_data[`PIB_EVQ_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_EVQ_CNT_WIDTH) dff_picl_evq2 (
.din (update_evq2_data[`PIB_EVQ_CNT_WIDTH-1:0]),
.q (picl_evq2[`PIB_EVQ_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_evq_sel[2]),
.se (se),
.si (),
.so ()
);
//
// thread 3
tlu_addern_32 #(`PIB_EVQ_CNT_WIDTH,1) picl_evq3_adder (
.din (picl_evq3[`PIB_EVQ_CNT_WIDTH-1:0]),
.incr (1'b1),
.sum (picl_evq3_sum[`PIB_EVQ_CNT_WIDTH-1:0])
) ;
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_update_evq3_data (
.in0 ({`PIB_EVQ_CNT_WIDTH{1'b0}}),
.in1 (picl_evq3_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (local_rst | pic_update_ctl[3]),
.sel1 (~(local_rst | pic_update_ctl[3])),
.dout (update_evq3_data[`PIB_EVQ_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_EVQ_CNT_WIDTH) dff_picl_evq3 (
.din (update_evq3_data[`PIB_EVQ_CNT_WIDTH-1:0]),
.q (picl_evq3[`PIB_EVQ_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_evq_sel[3]),
.se (se),
.si (),
.so ()
);
//
// selelcting the thread for incrementing for picl
//
mux4ds #(`PIB_PIC_CNT_WIDTH) mux_picl_cnt_din (
.in0 (picl_cnt0[`PIB_PIC_CNT_WIDTH-1:0]),
.in1 (picl_cnt1[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (picl_cnt2[`PIB_PIC_CNT_WIDTH-1:0]),
.in3 (picl_cnt3[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (pic_update_ctl[0]),
.sel1 (pic_update_ctl[1]),
.sel2 (pic_update_ctl[2]),
.sel3 (pic_update_ctl[3]),
.dout (picl_cnt_din[`PIB_PIC_CNT_WIDTH-1:0])
);
//
// selecting the correct input for incrementing the picl
// thread0
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq0_din (
.in0 (picl_evq0_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
.in1 (picl_evq0[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (incr_evq[0]),
.sel1 (~incr_evq[0]),
.dout (picl_evq0_din[`PIB_EVQ_CNT_WIDTH-1:0])
);
//
// thread1
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq1_din (
.in0 (picl_evq1_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
.in1 (picl_evq1[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (incr_evq[1]),
.sel1 (~incr_evq[1]),
.dout (picl_evq1_din[`PIB_EVQ_CNT_WIDTH-1:0])
);
//
// thread2
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq2_din (
.in0 (picl_evq2_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
.in1 (picl_evq2[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (incr_evq[2]),
.sel1 (~incr_evq[2]),
.dout (picl_evq2_din[`PIB_EVQ_CNT_WIDTH-1:0])
);
//
// thread3
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq3_din (
.in0 (picl_evq3_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
.in1 (picl_evq3[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (incr_evq[3]),
.sel1 (~incr_evq[3]),
.dout (picl_evq3_din[`PIB_EVQ_CNT_WIDTH-1:0])
);
//
mux4ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq_din (
.in0 (picl_evq0_din[`PIB_EVQ_CNT_WIDTH-1:0]),
.in1 (picl_evq1_din[`PIB_EVQ_CNT_WIDTH-1:0]),
.in2 (picl_evq2_din[`PIB_EVQ_CNT_WIDTH-1:0]),
.in3 (picl_evq3_din[`PIB_EVQ_CNT_WIDTH-1:0]),
.sel0 (pic_update_ctl[0]),
.sel1 (pic_update_ctl[1]),
.sel2 (pic_update_ctl[2]),
.sel3 (pic_update_ctl[3]),
.dout (picl_evq_din[`PIB_EVQ_CNT_WIDTH-1:0])
);
//
// picl incrementor - shared between four threads
//
tlu_addern_32 #(`PIB_PIC_CNT_WIDTH,`PIB_EVQ_CNT_WIDTH) picl_adder (
.din (picl_cnt_din[`PIB_PIC_CNT_WIDTH-1:0]),
.incr (picl_evq_din[`PIB_EVQ_CNT_WIDTH-1:0]),
.sum (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0])
) ;
//
// construction mux selects for picl update
assign wsr_pic_sel[0] = wsr_thread_inst_g[0] & (pic_npriv_rw_g | pic_priv_rw_g);
assign wsr_pic_sel[1] = wsr_thread_inst_g[1] & (pic_npriv_rw_g | pic_priv_rw_g);
assign wsr_pic_sel[2] = wsr_thread_inst_g[2] & (pic_npriv_rw_g | pic_priv_rw_g);
assign wsr_pic_sel[3] = wsr_thread_inst_g[3] & (pic_npriv_rw_g | pic_priv_rw_g);
assign update_picl_sel[0] = (local_rst | pic_update_ctl[0] | wsr_pic_sel[0]);
assign update_picl_sel[1] = (local_rst | pic_update_ctl[1] | wsr_pic_sel[1]);
assign update_picl_sel[2] = (local_rst | pic_update_ctl[2] | wsr_pic_sel[2]);
assign update_picl_sel[3] = (local_rst | pic_update_ctl[3] | wsr_pic_sel[3]);
// constructing the selects to choose to update the pich wrap - added for bug 2588
assign update_picl_wrap_en[0] =
update_picl_sel[0] | wsr_pcr_sel[0];
assign update_picl_wrap_en[1] =
update_picl_sel[1] | wsr_pcr_sel[1];
assign update_picl_wrap_en[2] =
update_picl_sel[2] | wsr_pcr_sel[2];
assign update_picl_wrap_en[3] =
update_picl_sel[3] | wsr_pcr_sel[3];
//
// extracting the wsr_data information to update the picls
//
assign picl_wsr_data = {1'b0, tlu_wsr_data_w[`PIB_PICL_CNT_HI:`PIB_PICL_CNT_LO]};
//
// selecting the data for picl update
// thread 0
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_picl0_data (
.in0 ({`PIB_PIC_CNT_WIDTH{1'b0}}),
.in1 (picl_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (local_rst),
.sel1 (wsr_pic_sel[0] & ~local_rst),
.sel2 (~(wsr_pic_sel[0] | local_rst)),
.dout (update_picl0_data[`PIB_PIC_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_picl_cnt0 (
.din (update_picl0_data[`PIB_PIC_CNT_WIDTH-1:0]),
.q (picl_cnt0[`PIB_PIC_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_picl_sel[0]),
.se (se),
.si (),
.so ()
);
//
// thread 1
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_picl1_data (
.in0 ({`PIB_PIC_CNT_WIDTH{1'b0}}),
.in1 (picl_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (local_rst),
.sel1 (wsr_pic_sel[1] & ~local_rst),
.sel2 (~(wsr_pic_sel[1] | local_rst)),
.dout (update_picl1_data[`PIB_PIC_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_picl_cnt1 (
.din (update_picl1_data[`PIB_PIC_CNT_WIDTH-1:0]),
.q (picl_cnt1[`PIB_PIC_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_picl_sel[1]),
.se (se),
.si (),
.so ()
);
//
// thread 2
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_picl2_data (
.in0 ({`PIB_PIC_CNT_WIDTH{1'b0}}),
.in1 (picl_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (local_rst),
.sel1 (wsr_pic_sel[2] & ~local_rst),
.sel2 (~(wsr_pic_sel[2] | local_rst)),
.dout (update_picl2_data[`PIB_PIC_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_picl_cnt2 (
.din (update_picl2_data[`PIB_PIC_CNT_WIDTH-1:0]),
.q (picl_cnt2[`PIB_PIC_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_picl_sel[2]),
.se (se),
.si (),
.so ()
);
//
// thread 3
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_picl3_data (
.in0 ({`PIB_PIC_CNT_WIDTH{1'b0}}),
.in1 (picl_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (local_rst),
.sel1 (wsr_pic_sel[3] & ~local_rst),
.sel2 (~(wsr_pic_sel[3] | local_rst)),
.dout (update_picl3_data[`PIB_PIC_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_picl_cnt3 (
.din (update_picl3_data[`PIB_PIC_CNT_WIDTH-1:0]),
.q (picl_cnt3[`PIB_PIC_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_picl_sel[3]),
.se (se),
.si (),
.so ()
);
//==================================================================
// update the pichs - could be sperated into a dp block if needed
//==================================================================
//
dffr_s #(`TLU_THRD_NUM) dffr_inst_vld_w2 (
.din (tlu_thread_inst_vld_g[`TLU_THRD_NUM-1:0]),
.q (inst_vld_w2[`TLU_THRD_NUM-1:0]),
.clk (clk),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
//
// added for bug 4395
dffr_s dffr_tcc_inst_w2 (
.din (tlu_tcc_inst_w),
.q (tcc_inst_w2),
.clk (clk),
.rst (local_rst),
.se (se),
.si (),
.so ()
);
//
// modified for bug 4478
assign incr_pich[0] = pic_cnt_en_w2[0] & inst_vld_w2[0] &
(~tlu_full_flush_pipe_w2 | tcc_inst_w2);
assign incr_pich[1] = pic_cnt_en_w2[1] & inst_vld_w2[1] &
(~tlu_full_flush_pipe_w2 | tcc_inst_w2);
assign incr_pich[2] = pic_cnt_en_w2[2] & inst_vld_w2[2] &
(~tlu_full_flush_pipe_w2 | tcc_inst_w2);
assign incr_pich[3] = pic_cnt_en_w2[3] & inst_vld_w2[3] &
(~tlu_full_flush_pipe_w2 | tcc_inst_w2);
assign pich_mux_sel[0] = pic_cnt_en_w2[0] & inst_vld_w2[0];
assign pich_mux_sel[1] = pic_cnt_en_w2[1] & inst_vld_w2[1];
assign pich_mux_sel[2] = pic_cnt_en_w2[2] & inst_vld_w2[2];
assign pich_mux_sel[3] = pic_cnt_en_w2[3] & inst_vld_w2[3];
// added for to make inst count overflow trap precise.
// added for bug 4314
assign pich_wrap_flg[0] =
(pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]) & pic_cnt_en_w2[0];
assign pich_wrap_flg[1] =
(pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]) & pic_cnt_en_w2[1];
assign pich_wrap_flg[2] =
(pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]) & pic_cnt_en_w2[2];
assign pich_wrap_flg[3] =
(pich_cnt_wrap[3] ^ pich_cnt3[`PIB_PIC_CNT_WIDTH-1]) & pic_cnt_en_w2[3];
// modified for bug 4270
// pic experiment
assign pich_fourbelow_din[0] =
(&pich_cnt0[`PIB_PIC_CNT_WIDTH-2:2]) & pic_cnt_en_w2[0];
assign pich_fourbelow_din[1] =
(&pich_cnt1[`PIB_PIC_CNT_WIDTH-2:2]) & pic_cnt_en_w2[1];
assign pich_fourbelow_din[2] =
(&pich_cnt2[`PIB_PIC_CNT_WIDTH-2:2]) & pic_cnt_en_w2[2];
assign pich_fourbelow_din[3] =
(&pich_cnt3[`PIB_PIC_CNT_WIDTH-2:2]) & pic_cnt_en_w2[3];
//
dff_s #(`TLU_THRD_NUM) dff_pich_fourbelow_flg (
.din (pich_fourbelow_din[`TLU_THRD_NUM-1:0]),
.q (pich_fourbelow_flg[`TLU_THRD_NUM-1:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
// modified for bug 4270
assign pich_onebelow_flg[0] =
(pich_fourbelow_flg[0] & pich_cnt0[1] & pich_cnt0[0]) & pic_cnt_en_w2[0];
assign pich_onebelow_flg[1] =
(pich_fourbelow_flg[1] & pich_cnt1[1] & pich_cnt1[0]) & pic_cnt_en_w2[1];
assign pich_onebelow_flg[2] =
(pich_fourbelow_flg[2] & pich_cnt2[1] & pich_cnt2[0]) & pic_cnt_en_w2[2];
assign pich_onebelow_flg[3] =
(pich_fourbelow_flg[3] & pich_cnt3[1] & pich_cnt3[0]) & pic_cnt_en_w2[3];
//
assign pich_twobelow_flg[0] =
(pich_fourbelow_flg[0] & pich_cnt0[1] & ~pich_cnt0[0]) & pic_cnt_en_w2[0];
assign pich_twobelow_flg[1] =
(pich_fourbelow_flg[1] & pich_cnt1[1] & ~pich_cnt1[0]) & pic_cnt_en_w2[1];
assign pich_twobelow_flg[2] =
(pich_fourbelow_flg[2] & pich_cnt2[1] & ~pich_cnt2[0]) & pic_cnt_en_w2[2];
assign pich_twobelow_flg[3] =
(pich_fourbelow_flg[3] & pich_cnt3[1] & ~pich_cnt3[0]) & pic_cnt_en_w2[3];
//
/*
assign pich_threebelow_flg[0] =
(pich_fourbelow_flg[0] & ~pich_cnt0[1] & pich_cnt0[0]) & pic_cnt_en_w2[0];
assign pich_threebelow_flg[1] =
(pich_fourbelow_flg[1] & ~pich_cnt1[1] & pich_cnt1[0]) & pic_cnt_en_w2[1];
assign pich_threebelow_flg[2] =
(pich_fourbelow_flg[2] & ~pich_cnt2[1] & pich_cnt2[0]) & pic_cnt_en_w2[2];
assign pich_threebelow_flg[3] =
(pich_fourbelow_flg[3] & ~pich_cnt3[1] & pich_cnt3[0]) & pic_cnt_en_w2[3];
*/
//
// added for bug 4836
assign pic_twobelow_e[0] =
pich_mux_sel[0]? (pich_fourbelow_flg[0] & ~pich_cnt0[1] & pich_cnt0[0]):
(pich_fourbelow_flg[0] & pich_cnt0[1] & ~pich_cnt0[0]);
assign pic_twobelow_e[1] =
pich_mux_sel[1]? (pich_fourbelow_flg[1] & ~pich_cnt1[1] & pich_cnt1[0]):
(pich_fourbelow_flg[1] & pich_cnt1[1] & ~pich_cnt1[0]);
assign pic_twobelow_e[2] =
pich_mux_sel[2]? (pich_fourbelow_flg[2] & ~pich_cnt2[1] & pich_cnt2[0]):
(pich_fourbelow_flg[2] & pich_cnt2[1] & ~pich_cnt2[0]);
assign pic_twobelow_e[3] =
pich_mux_sel[3]? (pich_fourbelow_flg[3] & ~pich_cnt3[1] & pich_cnt3[0]):
(pich_fourbelow_flg[3] & pich_cnt3[1] & ~pich_cnt3[0]);
assign tlu_pic_twobelow_e =
(thread_rsel_e[0]) ? pic_twobelow_e[0]:
(thread_rsel_e[1]) ? pic_twobelow_e[1]:
(thread_rsel_e[2]) ? pic_twobelow_e[2]:
pic_twobelow_e[3];
//
assign pic_onebelow_e[0] =
pich_mux_sel[0]? (pich_fourbelow_flg[0] & pich_cnt0[1] & ~pich_cnt0[0]):
(pich_fourbelow_flg[0] & pich_cnt0[1] & pich_cnt0[0]);
assign pic_onebelow_e[1] =
pich_mux_sel[1]? (pich_fourbelow_flg[1] & pich_cnt1[1] & ~pich_cnt1[0]):
(pich_fourbelow_flg[1] & pich_cnt1[1] & pich_cnt1[0]);
assign pic_onebelow_e[2] =
pich_mux_sel[2]? (pich_fourbelow_flg[2] & pich_cnt2[1] & ~pich_cnt2[0]):
(pich_fourbelow_flg[2] & pich_cnt2[1] & pich_cnt2[0]);
assign pic_onebelow_e[3] =
pich_mux_sel[3]? (pich_fourbelow_flg[3] & pich_cnt3[1] & ~pich_cnt3[0]):
(pich_fourbelow_flg[3] & pich_cnt3[1] & pich_cnt3[0]);
assign tlu_pic_onebelow_e =
(thread_rsel_e[0]) ? pic_onebelow_e[0]:
(thread_rsel_e[1]) ? pic_onebelow_e[1]:
(thread_rsel_e[2]) ? pic_onebelow_e[2]:
pic_onebelow_e[3];
//
assign pic_wrap_e[0] =
pich_mux_sel[0]? (pich_fourbelow_flg[0] & pich_cnt0[1] & pich_cnt0[0]):
(pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]);
assign pic_wrap_e[1] =
pich_mux_sel[1]? (pich_fourbelow_flg[1] & pich_cnt1[1] & pich_cnt1[0]):
(pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]);
assign pic_wrap_e[2] =
pich_mux_sel[2]? (pich_fourbelow_flg[2] & pich_cnt2[1] & pich_cnt2[0]):
(pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]);
assign pic_wrap_e[3] =
pich_mux_sel[3]? (pich_fourbelow_flg[3] & pich_cnt3[1] & pich_cnt3[0]):
(pich_cnt_wrap[3] ^ pich_cnt3[`PIB_PIC_CNT_WIDTH-1]);
assign tlu_pic_wrap_e =
(thread_rsel_e[0]) ? pic_wrap_e[0]:
(thread_rsel_e[1]) ? pic_wrap_e[1]:
(thread_rsel_e[2]) ? pic_wrap_e[2]:
pic_wrap_e[3];
//
//
// modified for bug 5436: Niagara 2.0
assign tlu_pcr_ut[0] = pcr0[`PIB_PCR_UT];
assign tlu_pcr_ut[1] = pcr1[`PIB_PCR_UT];
assign tlu_pcr_ut[2] = pcr2[`PIB_PCR_UT];
assign tlu_pcr_ut[3] = pcr3[`PIB_PCR_UT];
//
assign tlu_pcr_st[0] = pcr0[`PIB_PCR_ST];
assign tlu_pcr_st[1] = pcr1[`PIB_PCR_ST];
assign tlu_pcr_st[2] = pcr2[`PIB_PCR_ST];
assign tlu_pcr_st[3] = pcr3[`PIB_PCR_ST];
assign tlu_pcr_ut_e =
(thread_rsel_e[0]) ? pcr0[`PIB_PCR_UT]:
(thread_rsel_e[1]) ? pcr1[`PIB_PCR_UT]:
(thread_rsel_e[2]) ? pcr2[`PIB_PCR_UT]:
pcr3[`PIB_PCR_UT];
assign tlu_pcr_st_e =
(thread_rsel_e[0]) ? pcr0[`PIB_PCR_ST]:
(thread_rsel_e[1]) ? pcr1[`PIB_PCR_ST]:
(thread_rsel_e[2]) ? pcr2[`PIB_PCR_ST]:
pcr3[`PIB_PCR_ST];
// reporting over-flow trap - needed to be precise, therefore
// bypassing tlb-miss traps
//
// selelcting the thread for incrementing for pich
// added for bug2332
//
// one-hot mux change
assign pich_cnt_din[`PIB_PIC_CNT_WIDTH-1:0] =
(pich_mux_sel[1])? pich_cnt1[`PIB_PIC_CNT_WIDTH-1:0]:
(pich_mux_sel[2])? pich_cnt2[`PIB_PIC_CNT_WIDTH-1:0]:
(pich_mux_sel[3])? pich_cnt3[`PIB_PIC_CNT_WIDTH-1:0]:
pich_cnt0[`PIB_PIC_CNT_WIDTH-1:0];
/*
assign incr_pich_onehot = ~(|incr_pich[3:1]) | rst_tri_en;
mux4ds #(`PIB_PIC_CNT_WIDTH) mux_pich_cnt_din (
.in0 (pich_cnt0[`PIB_PIC_CNT_WIDTH-1:0]),
.in1 (pich_cnt1[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (pich_cnt2[`PIB_PIC_CNT_WIDTH-1:0]),
.in3 (pich_cnt3[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (incr_pich_onehot),
.sel1 (incr_pich[1] & ~rst_tri_en),
.sel2 (incr_pich[2] & ~rst_tri_en),
.sel3 (incr_pich[3] & ~rst_tri_en),
.dout (pich_cnt_din[`PIB_PIC_CNT_WIDTH-1:0])
);
*/
//
// pich incrementor - shared between four threads
//
tlu_addern_32 #(`PIB_PIC_CNT_WIDTH,1) pich_adder (
.din (pich_cnt_din[`PIB_PIC_CNT_WIDTH-1:0]),
.incr (1'b1),
.sum (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0])
) ;
//
// extracting the wsr_data information to update the picls
//
assign pich_wsr_data = {1'b0, tlu_wsr_data_w[`PIB_PICH_CNT_HI:`PIB_PICH_CNT_LO]};
// constructing the selects to choose to update the pich
assign update_pich_sel[0] = (local_rst | incr_pich[0] | wsr_pic_sel[0]);
assign update_pich_sel[1] = (local_rst | incr_pich[1] | wsr_pic_sel[1]);
assign update_pich_sel[2] = (local_rst | incr_pich[2] | wsr_pic_sel[2]);
assign update_pich_sel[3] = (local_rst | incr_pich[3] | wsr_pic_sel[3]);
// constructing the selects to choose to update the pich wrap
assign update_pich_wrap_en[0] =
update_pich_sel[0] | wsr_pcr_sel[0];
assign update_pich_wrap_en[1] =
update_pich_sel[1] | wsr_pcr_sel[1];
assign update_pich_wrap_en[2] =
update_pich_sel[2] | wsr_pcr_sel[2];
assign update_pich_wrap_en[3] =
update_pich_sel[3] | wsr_pcr_sel[3];
//
// selecting the data for pich update
// thread 0
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_pich0_data (
.in0 ({`PIB_PIC_CNT_WIDTH{1'b0}}),
.in1 (pich_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (local_rst),
.sel1 (wsr_pic_sel[0] & ~local_rst),
.sel2 (~(wsr_pic_sel[0] | local_rst)),
.dout (update_pich0_data[`PIB_PIC_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_pich_cnt0 (
.din (update_pich0_data[`PIB_PIC_CNT_WIDTH-1:0]),
.q (pich_cnt0[`PIB_PIC_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_pich_sel[0]),
.se (se),
.si (),
.so ()
);
//
// thread 1
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_pich1_data (
.in0 ({`PIB_PIC_CNT_WIDTH{1'b0}}),
.in1 (pich_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (local_rst),
.sel1 (wsr_pic_sel[1] & ~local_rst),
.sel2 (~(wsr_pic_sel[1] | local_rst)),
.dout (update_pich1_data[`PIB_PIC_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_pich_cnt1 (
.din (update_pich1_data[`PIB_PIC_CNT_WIDTH-1:0]),
.q (pich_cnt1[`PIB_PIC_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_pich_sel[1]),
.se (se),
.si (),
.so ()
);
//
// thread 2
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_pich2_data (
.in0 ({`PIB_PIC_CNT_WIDTH{1'b0}}),
.in1 (pich_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (local_rst),
.sel1 (wsr_pic_sel[2] & ~local_rst),
.sel2 (~(wsr_pic_sel[2] | local_rst)),
.dout (update_pich2_data[`PIB_PIC_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_pich_cnt2 (
.din (update_pich2_data[`PIB_PIC_CNT_WIDTH-1:0]),
.q (pich_cnt2[`PIB_PIC_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_pich_sel[2]),
.se (se),
.si (),
.so ()
);
//
// thread 3
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_pich3_data (
.in0 ({`PIB_PIC_CNT_WIDTH{1'b0}}),
.in1 (pich_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
.in2 (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
.sel0 (local_rst),
.sel1 (wsr_pic_sel[3] & ~local_rst),
.sel2 (~(wsr_pic_sel[3] | local_rst)),
.dout (update_pich3_data[`PIB_PIC_CNT_WIDTH-1:0])
);
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_pich_cnt3 (
.din (update_pich3_data[`PIB_PIC_CNT_WIDTH-1:0]),
.q (pich_cnt3[`PIB_PIC_CNT_WIDTH-1:0]),
.clk (clk),
.en (update_pich_sel[3]),
.se (se),
.si (),
.so ()
);
//==========================
// reading the PCRs and PICs
//==========================
// decoding the thread information for rsr instruction from IFU
// modified due to timing
/*
assign thread_rsel_e[0] = ~(|ifu_tlu_thrid_e[1:0]);
assign thread_rsel_e[1] = ~ifu_tlu_thrid_e[1] & ifu_tlu_thrid_e[0];
assign thread_rsel_e[2] = ifu_tlu_thrid_e[1] & ~ifu_tlu_thrid_e[0];
assign thread_rsel_e[3] = (&ifu_tlu_thrid_e[1:0]);
*/
assign thread_rsel_d[0] = ~(|ifu_tlu_thrid_d[1:0]);
assign thread_rsel_d[1] = ~ifu_tlu_thrid_d[1] & ifu_tlu_thrid_d[0];
assign thread_rsel_d[2] = ifu_tlu_thrid_d[1] & ~ifu_tlu_thrid_d[0];
// assign thread_rsel_d[3] = (&ifu_tlu_thrid_d[1:0]);
//
dff_s #(`TLU_THRD_NUM-1) dff_thread_rsel_e (
.din (thread_rsel_d[`TLU_THRD_NUM-2:0]),
.q (thread_rsel_e[`TLU_THRD_NUM-2:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
// selecting the correct pic for rdpr
// modified to avoid rte failure
assign pic_rdata_e[`TLU_ASR_DATA_WIDTH-1:0] =
(thread_rsel_e[0])?
{pich_cnt0[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt0[`PIB_PIC_CNT_WIDTH-2:0]}:
(thread_rsel_e[1])?
{pich_cnt1[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt1[`PIB_PIC_CNT_WIDTH-2:0]}:
(thread_rsel_e[2])?
{pich_cnt2[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt2[`PIB_PIC_CNT_WIDTH-2:0]}:
{pich_cnt3[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt3[`PIB_PIC_CNT_WIDTH-2:0]};
/*
mux4ds #(`TLU_ASR_DATA_WIDTH) mux_pic_rdata (
.in0 ({pich_cnt0[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt0[`PIB_PIC_CNT_WIDTH-2:0]}),
.in1 ({pich_cnt1[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt1[`PIB_PIC_CNT_WIDTH-2:0]}),
.in2 ({pich_cnt2[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt2[`PIB_PIC_CNT_WIDTH-2:0]}),
.in3 ({pich_cnt3[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt3[`PIB_PIC_CNT_WIDTH-2:0]}),
.sel0 (thread_rsel_e[0]),
.sel1 (thread_rsel_e[1]),
.sel2 (thread_rsel_e[2]),
.sel3 (thread_rsel_e[3]),
.dout (pic_rdata_e[`TLU_ASR_DATA_WIDTH-1:0])
);
// selecting the correct pcr for rdpr
// modified for bug 2391
mux4ds #(`TLU_ASR_DATA_WIDTH) mux_pcr_rdata (
.in0 ({58'b0,pcr0[`PIB_PCR_WIDTH-1:0]}),
.in1 ({58'b0,pcr1[`PIB_PCR_WIDTH-1:0]}),
.in2 ({58'b0,pcr2[`PIB_PCR_WIDTH-1:0]}),
.in3 ({58'b0,pcr3[`PIB_PCR_WIDTH-1:0]}),
.sel0 (thread_rsel_e[0]),
.sel1 (thread_rsel_e[1]),
.sel2 (thread_rsel_e[2]),
.sel3 (thread_rsel_e[3]),
.dout (pcr_rdata_e[`TLU_ASR_DATA_WIDTH-1:0])
);
mux4ds #(`PIB_PCR_WIDTH) mux_pcr_rdata (
.in0 (pcr0[`PIB_PCR_WIDTH-1:0]),
.in1 (pcr1[`PIB_PCR_WIDTH-1:0]),
.in2 (pcr2[`PIB_PCR_WIDTH-1:0]),
.in3 (pcr3[`PIB_PCR_WIDTH-1:0]),
.sel0 (thread_rsel_e[0]),
.sel1 (thread_rsel_e[1]),
.sel2 (thread_rsel_e[2]),
.sel3 (thread_rsel_e[3]),
.dout (pcr_reg_rdata_e[`PIB_PCR_WIDTH-1:0])
);
*/
assign pcr_reg_rdata_e[`PIB_PCR_WIDTH-1:0] =
(thread_rsel_e[0])? pcr0[`PIB_PCR_WIDTH-1:0]:
(thread_rsel_e[1])? pcr1[`PIB_PCR_WIDTH-1:0]:
(thread_rsel_e[2])? pcr2[`PIB_PCR_WIDTH-1:0]:
pcr3[`PIB_PCR_WIDTH-1:0];
assign pcr_rdata_e[`TLU_ASR_DATA_WIDTH-1:0] =
{54'b0, // rsvd bits
pcr_reg_rdata_e[`PIB_PCR_CH_OVF:`PIB_PCR_CL_OVF],
1'b0, // rsvd bit
pcr_reg_rdata_e[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO],
1'b0, // rsvd bit
pcr_reg_rdata_e[`PIB_PCR_UT:`PIB_PCR_PRIV]};
// constructing the mux select for the output mux for rsr inst
assign rsr_data_sel_e[0] = pcr_rw_e;
assign rsr_data_sel_e[1] = ~pcr_rw_e;
// modified due to timing
// assign rsr_data_sel_e[1] = ~pcr_rw_e & (pic_npriv_rw_e | pic_priv_rw_e);
// assign rsr_data_sel_e[2] = ~(|rsr_data_sel_e[1:0]);
/*
mux3ds #(`TLU_ASR_DATA_WIDTH) mux_exu_rsr_data_e (
.in0(pcr_rdata_e[`TLU_ASR_DATA_WIDTH-1:0]),
.in1(pic_rdata_e[`TLU_ASR_DATA_WIDTH-1:0]),
.in2(tlu_pib_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0]),
.sel0(rsr_data_sel_e[0]),
.sel1(rsr_data_sel_e[1]),
.sel2(rsr_data_sel_e[2]),
.dout(tlu_exu_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0])
);
*/
mux2ds #(`TLU_ASR_DATA_WIDTH) mux_tlu_pib_rsr_data_e (
.in0(pcr_rdata_e[`TLU_ASR_DATA_WIDTH-1:0]),
.in1(pic_rdata_e[`TLU_ASR_DATA_WIDTH-1:0]),
.sel0(rsr_data_sel_e[0]),
.sel1(rsr_data_sel_e[1]),
.dout(tlu_pib_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0])
);
//==========================
// over_flow trap
//==========================
// staged the wrap bit for comparison
//
// thread 0 - modified for bug 3937
mux2ds mux_picl_cnt_wrap_datain_0 (
.in0(picl_cnt0[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]),
.in1(picl_cnt0[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[0]),
.sel1(~wsr_pcr_sel[0]),
.dout(picl_cnt_wrap_datain[0])
);
mux2ds mux_pich_cnt_wrap_datain_0 (
.in0(pich_cnt0[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]),
.in1(pich_cnt0[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[0]),
.sel1(~wsr_pcr_sel[0]),
.dout(pich_cnt_wrap_datain[0])
);
/*
assign picl_cnt_wrap_datain[0] =
(picl_cnt0[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]);
assign pich_cnt_wrap_datain[0] =
(pich_cnt0[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]);
*/
dffre_s dffre_picl0_wrap (
.din (picl_cnt_wrap_datain[0]),
.q (picl_cnt_wrap[0]),
.clk (clk),
.en (update_picl_wrap_en[0]),
.rst (local_rst | wsr_pic_sel[0]),
.se (se),
.si (),
.so ()
);
dffre_s dffre_pich0_wrap (
.din (pich_cnt_wrap_datain[0]),
.q (pich_cnt_wrap[0]),
.clk (clk),
.en (update_pich_wrap_en[0]),
.rst (local_rst | wsr_pic_sel[0]),
.se (se),
.si (),
.so ()
);
//
// thread 1 - modified for bug 3937
mux2ds mux_picl_cnt_wrap_datain_1 (
.in0(picl_cnt1[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]),
.in1(picl_cnt1[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[1]),
.sel1(~wsr_pcr_sel[1]),
.dout(picl_cnt_wrap_datain[1])
);
mux2ds mux_pich_cnt_wrap_datain_1 (
.in0(pich_cnt1[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]),
.in1(pich_cnt1[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[1]),
.sel1(~wsr_pcr_sel[1]),
.dout(pich_cnt_wrap_datain[1])
);
/*
assign picl_cnt_wrap_datain[1] =
(picl_cnt1[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]);
assign pich_cnt_wrap_datain[1] =
(pich_cnt1[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]);
*/
dffre_s dffre_picl1_wrap (
.din (picl_cnt_wrap_datain[1]),
.q (picl_cnt_wrap[1]),
.clk (clk),
.en (update_picl_wrap_en[1]),
.rst (local_rst | wsr_pic_sel[1]),
.se (se),
.si (),
.so ()
);
dffre_s dffre_pich1_wrap (
.din (pich_cnt_wrap_datain[1]),
.q (pich_cnt_wrap[1]),
.clk (clk),
.en (update_pich_wrap_en[1]),
.rst (local_rst | wsr_pic_sel[1]),
.se (se),
.si (),
.so ()
);
//
// thread 2 - modified for bug 3937
mux2ds mux_picl_cnt_wrap_datain_2 (
.in0(picl_cnt2[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]),
.in1(picl_cnt2[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[2]),
.sel1(~wsr_pcr_sel[2]),
.dout(picl_cnt_wrap_datain[2])
);
mux2ds mux_pich_cnt_wrap_datain_2 (
.in0(pich_cnt2[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]),
.in1(pich_cnt2[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[2]),
.sel1(~wsr_pcr_sel[2]),
.dout(pich_cnt_wrap_datain[2])
);
/*
assign picl_cnt_wrap_datain[2] =
(picl_cnt2[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]);
assign pich_cnt_wrap_datain[2] =
(pich_cnt2[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]);
*/
dffre_s dffre_picl2_wrap (
.din (picl_cnt_wrap_datain[2]),
.q (picl_cnt_wrap[2]),
.clk (clk),
.en (update_picl_wrap_en[2]),
.rst (local_rst | wsr_pic_sel[2]),
.se (se),
.si (),
.so ()
);
dffre_s dffre_pich2_wrap (
.din (pich_cnt_wrap_datain[2]),
.q (pich_cnt_wrap[2]),
.clk (clk),
.en (update_pich_wrap_en[2]),
.rst (local_rst | wsr_pic_sel[2]),
.se (se),
.si (),
.so ()
);
//
// thread 3 - modified for bug 3937
mux2ds mux_picl_cnt_wrap_datain_3 (
.in0(picl_cnt3[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]),
.in1(picl_cnt3[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[3]),
.sel1(~wsr_pcr_sel[3]),
.dout(picl_cnt_wrap_datain[3])
);
mux2ds mux_pich_cnt_wrap_datain_3 (
.in0(pich_cnt3[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]),
.in1(pich_cnt3[`PIB_PIC_CNT_WIDTH-1]),
.sel0(wsr_pcr_sel[3]),
.sel1(~wsr_pcr_sel[3]),
.dout(pich_cnt_wrap_datain[3])
);
/*
assign picl_cnt_wrap_datain[3] =
(picl_cnt3[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]);
assign pich_cnt_wrap_datain[3] =
(pich_cnt3[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]);
*/
dffre_s dffre_picl3_wrap (
.din (picl_cnt_wrap_datain[3]),
.q (picl_cnt_wrap[3]),
.clk (clk),
.en (update_picl_wrap_en[3]),
.rst (local_rst | wsr_pic_sel[3]),
.se (se),
.si (),
.so ()
);
dffre_s dffre_pich3_wrap (
.din (pich_cnt_wrap_datain[3]),
.q (pich_cnt_wrap[3]),
.clk (clk),
.en (update_pich_wrap_en[3]),
.rst (local_rst | wsr_pic_sel[3]),
.se (se),
.si (),
.so ()
);
//
// generating the over-flow (0->1) to be set in sftint[15]
assign pib_picl_wrap[0] =
((picl_cnt_wrap[0] ^ picl_cnt0[`PIB_PIC_CNT_WIDTH-1]) & incr_evq[0]);
assign pib_picl_wrap[1] =
((picl_cnt_wrap[1] ^ picl_cnt1[`PIB_PIC_CNT_WIDTH-1]) & incr_evq[1]);
assign pib_picl_wrap[2] =
((picl_cnt_wrap[2] ^ picl_cnt2[`PIB_PIC_CNT_WIDTH-1]) & incr_evq[2]);
assign pib_picl_wrap[3] =
((picl_cnt_wrap[3] ^ picl_cnt3[`PIB_PIC_CNT_WIDTH-1]) & incr_evq[3]);
//
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1 const
// RDY_predict_req O 1
// predict_rsp O 64
// RDY_bp_train O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// predict_req_pc I 64 reg
// predict_rsp_is_i32_not_i16 I 1
// predict_rsp_instr I 32
// bp_train_pc I 64
// bp_train_is_i32_not_i16 I 1
// bp_train_instr I 32
// bp_train_cf_info I 195
// EN_reset I 1
// EN_predict_req I 1
// EN_bp_train I 1
//
// Combinational paths from inputs to outputs:
// (predict_rsp_is_i32_not_i16, predict_rsp_instr) -> predict_rsp
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBranch_Predictor(CLK,
RST_N,
EN_reset,
RDY_reset,
predict_req_pc,
EN_predict_req,
RDY_predict_req,
predict_rsp_is_i32_not_i16,
predict_rsp_instr,
predict_rsp,
bp_train_pc,
bp_train_is_i32_not_i16,
bp_train_instr,
bp_train_cf_info,
EN_bp_train,
RDY_bp_train);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method predict_req
input [63 : 0] predict_req_pc;
input EN_predict_req;
output RDY_predict_req;
// value method predict_rsp
input predict_rsp_is_i32_not_i16;
input [31 : 0] predict_rsp_instr;
output [63 : 0] predict_rsp;
// action method bp_train
input [63 : 0] bp_train_pc;
input bp_train_is_i32_not_i16;
input [31 : 0] bp_train_instr;
input [194 : 0] bp_train_cf_info;
input EN_bp_train;
output RDY_bp_train;
// signals for module outputs
wire [63 : 0] predict_rsp;
wire RDY_bp_train, RDY_predict_req, RDY_reset;
// register rg_index
reg [8 : 0] rg_index;
wire [8 : 0] rg_index$D_IN;
wire rg_index$EN;
// register rg_pc
reg [63 : 0] rg_pc;
wire [63 : 0] rg_pc$D_IN;
wire rg_pc$EN;
// register rg_ras
reg [1023 : 0] rg_ras;
wire [1023 : 0] rg_ras$D_IN;
wire rg_ras$EN;
// register rg_resetting
reg rg_resetting;
wire rg_resetting$D_IN, rg_resetting$EN;
// ports of submodule btb_bramcore2
wire [117 : 0] btb_bramcore2$DIA, btb_bramcore2$DIB, btb_bramcore2$DOA;
wire [8 : 0] btb_bramcore2$ADDRA, btb_bramcore2$ADDRB;
wire btb_bramcore2$ENA,
btb_bramcore2$ENB,
btb_bramcore2$WEA,
btb_bramcore2$WEB;
// ports of submodule rf_btb_fsms
wire [8 : 0] rf_btb_fsms$ADDR_1,
rf_btb_fsms$ADDR_2,
rf_btb_fsms$ADDR_3,
rf_btb_fsms$ADDR_4,
rf_btb_fsms$ADDR_5,
rf_btb_fsms$ADDR_IN;
wire [1 : 0] rf_btb_fsms$D_IN, rf_btb_fsms$D_OUT_1;
wire rf_btb_fsms$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset,
CAN_FIRE_bp_train,
CAN_FIRE_predict_req,
CAN_FIRE_reset,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_bp_train,
WILL_FIRE_predict_req,
WILL_FIRE_reset;
// inputs to muxes for submodule ports
reg [1 : 0] MUX_rf_btb_fsms$upd_2__VAL_1;
wire [117 : 0] MUX_btb_bramcore2$b_put_3__VAL_1;
wire [8 : 0] MUX_rg_index$write_1__VAL_2;
wire MUX_btb_bramcore2$b_put_1__SEL_1;
// remaining internal signals
reg [63 : 0] _theResult_____1_fst__h7498,
_theResult_____1_fst__h7542,
pred_PC__h7403;
reg [1 : 0] _theResult_____1_snd__h7499, _theResult_____1_snd__h7543;
wire [1023 : 0] IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d208,
IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d210;
wire [959 : 0] IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d204;
wire [63 : 0] _theResult_____1__h2383,
_theResult_____1_fst__h7431,
_theResult____h2382,
pred_pc__h3338,
pred_pc__h3340,
ret_pc___1__h4093,
ret_pc__h4055;
wire [1 : 0] _theResult_____1_snd__h7432;
wire IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d173,
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176,
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d197,
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d189,
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d190,
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d199,
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148,
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d149,
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157,
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d68,
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d83,
IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d50,
IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d51,
IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d78,
IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d86,
NOT_bp_train_instr_BITS_11_TO_7_16_EQ_bp_train_ETC___d194,
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1000__ETC___d125,
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1001__ETC___d130,
NOT_predict_rsp_instr_BITS_11_TO_7_8_EQ_predic_ETC___d80,
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153,
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d196,
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_O_ETC___d168,
bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144,
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26,
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d82,
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30;
// action method reset
assign RDY_reset = 1'd1 ;
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// action method predict_req
assign RDY_predict_req = !rg_resetting ;
assign CAN_FIRE_predict_req = !rg_resetting ;
assign WILL_FIRE_predict_req = EN_predict_req ;
// value method predict_rsp
assign predict_rsp =
(_theResult_____1__h2383 == 64'hFFFFFFFFFFFFFFFF) ?
pred_pc__h3340 :
_theResult_____1__h2383 ;
// action method bp_train
assign RDY_bp_train = 1'd1 ;
assign CAN_FIRE_bp_train = 1'd1 ;
assign WILL_FIRE_bp_train = EN_bp_train ;
// submodule btb_bramcore2
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd118),
.MEMSIZE(10'd512)) btb_bramcore2(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(btb_bramcore2$ADDRA),
.ADDRB(btb_bramcore2$ADDRB),
.DIA(btb_bramcore2$DIA),
.DIB(btb_bramcore2$DIB),
.WEA(btb_bramcore2$WEA),
.WEB(btb_bramcore2$WEB),
.ENA(btb_bramcore2$ENA),
.ENB(btb_bramcore2$ENB),
.DOA(btb_bramcore2$DOA),
.DOB());
// submodule rf_btb_fsms
RegFile #(.addr_width(32'd9),
.data_width(32'd2),
.lo(9'h0),
.hi(9'd511)) rf_btb_fsms(.CLK(CLK),
.ADDR_1(rf_btb_fsms$ADDR_1),
.ADDR_2(rf_btb_fsms$ADDR_2),
.ADDR_3(rf_btb_fsms$ADDR_3),
.ADDR_4(rf_btb_fsms$ADDR_4),
.ADDR_5(rf_btb_fsms$ADDR_5),
.ADDR_IN(rf_btb_fsms$ADDR_IN),
.D_IN(rf_btb_fsms$D_IN),
.WE(rf_btb_fsms$WE),
.D_OUT_1(rf_btb_fsms$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = rg_resetting ;
assign WILL_FIRE_RL_rl_reset = rg_resetting && !EN_bp_train ;
// inputs to muxes for submodule ports
assign MUX_btb_bramcore2$b_put_1__SEL_1 =
EN_bp_train && pred_PC__h7403 != 64'hFFFFFFFFFFFFFFFF ;
assign MUX_btb_bramcore2$b_put_3__VAL_1 =
{ 1'd1, bp_train_cf_info[192:139], pred_PC__h7403[63:1] } ;
always@(bp_train_cf_info or
rf_btb_fsms$D_OUT_1 or _theResult_____1_snd__h7432)
begin
case (bp_train_cf_info[194:193])
2'd0: MUX_rf_btb_fsms$upd_2__VAL_1 = _theResult_____1_snd__h7432;
2'd1, 2'd2: MUX_rf_btb_fsms$upd_2__VAL_1 = 2'b11;
2'd3: MUX_rf_btb_fsms$upd_2__VAL_1 = rf_btb_fsms$D_OUT_1;
endcase
end
assign MUX_rg_index$write_1__VAL_2 = rg_index + 9'd1 ;
// register rg_index
assign rg_index$D_IN = EN_reset ? 9'd0 : MUX_rg_index$write_1__VAL_2 ;
assign rg_index$EN = WILL_FIRE_RL_rl_reset || EN_reset ;
// register rg_pc
assign rg_pc$D_IN = predict_req_pc ;
assign rg_pc$EN = EN_predict_req ;
// register rg_ras
assign rg_ras$D_IN =
(IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d149 ||
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157 &&
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148 &&
(IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d173 ||
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176)) ?
IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d208 :
IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d210 ;
assign rg_ras$EN = EN_bp_train ;
// register rg_resetting
assign rg_resetting$D_IN = EN_reset ;
assign rg_resetting$EN =
WILL_FIRE_RL_rl_reset && rg_index == 9'd511 || EN_reset ;
// submodule btb_bramcore2
assign btb_bramcore2$ADDRA = predict_req_pc[9:1] ;
assign btb_bramcore2$ADDRB =
MUX_btb_bramcore2$b_put_1__SEL_1 ?
bp_train_cf_info[138:130] :
rg_index ;
assign btb_bramcore2$DIA =
118'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign btb_bramcore2$DIB =
MUX_btb_bramcore2$b_put_1__SEL_1 ?
MUX_btb_bramcore2$b_put_3__VAL_1 :
118'd0 ;
assign btb_bramcore2$WEA = 1'd0 ;
assign btb_bramcore2$WEB = 1'd1 ;
assign btb_bramcore2$ENA = EN_predict_req ;
assign btb_bramcore2$ENB =
EN_bp_train && pred_PC__h7403 != 64'hFFFFFFFFFFFFFFFF ||
WILL_FIRE_RL_rl_reset ;
// submodule rf_btb_fsms
assign rf_btb_fsms$ADDR_1 = bp_train_cf_info[138:130] ;
assign rf_btb_fsms$ADDR_2 = 9'h0 ;
assign rf_btb_fsms$ADDR_3 = 9'h0 ;
assign rf_btb_fsms$ADDR_4 = 9'h0 ;
assign rf_btb_fsms$ADDR_5 = 9'h0 ;
assign rf_btb_fsms$ADDR_IN =
MUX_btb_bramcore2$b_put_1__SEL_1 ?
bp_train_cf_info[138:130] :
rg_index ;
assign rf_btb_fsms$D_IN =
MUX_btb_bramcore2$b_put_1__SEL_1 ?
MUX_rf_btb_fsms$upd_2__VAL_1 :
2'b0 ;
assign rf_btb_fsms$WE =
EN_bp_train && pred_PC__h7403 != 64'hFFFFFFFFFFFFFFFF ||
WILL_FIRE_RL_rl_reset ;
// remaining internal signals
assign IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d204 =
(IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d190 &&
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157 &&
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d199) ?
rg_ras[1023:64] :
rg_ras[959:0] ;
assign IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d208 =
{ IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d204,
bp_train_is_i32_not_i16 ? ret_pc__h4055 : ret_pc___1__h4093 } ;
assign IF_IF_bp_train_is_i32_not_i16_THEN_NOT_bp_trai_ETC___d210 =
(IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d190 &&
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157 &&
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d199) ?
{ 64'hFFFFFFFFFFFFFFFF, rg_ras[1023:64] } :
rg_ras ;
assign IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d173 =
(bp_train_is_i32_not_i16 ||
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01) ?
bp_train_instr[19:15] != 5'd1 &&
bp_train_instr[19:15] != 5'd5 :
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_O_ETC___d168 ?
bp_train_instr[11:7] != 5'd1 &&
bp_train_instr[11:7] != 5'd5 :
bp_train_instr[19:15] != 5'd1 &&
bp_train_instr[19:15] != 5'd5) ;
assign IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176 =
(bp_train_is_i32_not_i16 ||
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01) ?
bp_train_instr[19:15] == 5'd1 ||
bp_train_instr[19:15] == 5'd5 :
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_O_ETC___d168 ?
bp_train_instr[11:7] == 5'd1 ||
bp_train_instr[11:7] == 5'd5 :
bp_train_instr[19:15] == 5'd1 ||
bp_train_instr[19:15] == 5'd5) ;
assign IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d197 =
(bp_train_is_i32_not_i16 ||
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01) ?
NOT_bp_train_instr_BITS_11_TO_7_16_EQ_bp_train_ETC___d194 :
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d196 ;
assign IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d189 =
bp_train_is_i32_not_i16 ?
bp_train_instr[11:7] != 5'd1 && bp_train_instr[11:7] != 5'd5 :
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01 ||
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 ||
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1001__ETC___d130 &&
bp_train_instr[11:7] != 5'd1 &&
bp_train_instr[11:7] != 5'd5 ;
assign IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d190 =
(bp_train_is_i32_not_i16 ?
bp_train_instr[6:0] != 7'b1101111 :
(bp_train_instr[15:13] != 3'b101 ||
bp_train_instr[1:0] != 2'b01) &&
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 ||
bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 ||
bp_train_instr[6:0] != 7'b1101111)) ||
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d189 ;
assign IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d199 =
IF_bp_train_is_i32_not_i16_THEN_NOT_bp_train_i_ETC___d189 &&
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176 ||
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148 &&
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d176 &&
IF_bp_train_is_i32_not_i16_OR_bp_train_instr_B_ETC___d197 ;
assign IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148 =
bp_train_is_i32_not_i16 ?
bp_train_instr[11:7] == 5'd1 || bp_train_instr[11:7] == 5'd5 :
(bp_train_instr[15:13] != 3'b101 ||
bp_train_instr[1:0] != 2'b01) &&
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1000__ETC___d125 &&
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 ||
bp_train_instr[11:7] == 5'd1 ||
bp_train_instr[11:7] == 5'd5) ;
assign IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d149 =
(bp_train_is_i32_not_i16 ?
bp_train_instr[6:0] == 7'b1101111 :
bp_train_instr[15:13] == 3'b101 &&
bp_train_instr[1:0] == 2'b01 ||
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1000__ETC___d125 &&
NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1001__ETC___d130 &&
bp_train_instr[6:0] == 7'b1101111) &&
IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d148 ;
assign IF_bp_train_is_i32_not_i16_THEN_bp_train_instr_ETC___d157 =
bp_train_is_i32_not_i16 ?
bp_train_instr[6:0] == 7'b1100111 :
(bp_train_instr[15:13] != 3'b101 ||
bp_train_instr[1:0] != 2'b01) &&
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 ||
bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 ||
bp_train_instr[6:0] == 7'b1100111) ;
assign IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d68 =
(predict_rsp_is_i32_not_i16 ||
predict_rsp_instr[15:13] == 3'b101 &&
predict_rsp_instr[1:0] == 2'b01) ?
predict_rsp_instr[19:15] == 5'd1 ||
predict_rsp_instr[19:15] == 5'd5 :
(((predict_rsp_instr[15:12] == 4'b1000 ||
predict_rsp_instr[15:12] == 4'b1001) &&
predict_rsp_instr[11:7] != 5'd0 &&
predict_rsp_instr[6:2] == 5'd0 &&
predict_rsp_instr[1:0] == 2'b10) ?
predict_rsp_instr[11:7] == 5'd1 ||
predict_rsp_instr[11:7] == 5'd5 :
predict_rsp_instr[19:15] == 5'd1 ||
predict_rsp_instr[19:15] == 5'd5) ;
assign IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d83 =
(predict_rsp_is_i32_not_i16 ||
predict_rsp_instr[15:13] == 3'b101 &&
predict_rsp_instr[1:0] == 2'b01) ?
NOT_predict_rsp_instr_BITS_11_TO_7_8_EQ_predic_ETC___d80 :
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d82 ;
assign IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d50 =
predict_rsp_is_i32_not_i16 ?
predict_rsp_instr[11:7] != 5'd1 &&
predict_rsp_instr[11:7] != 5'd5 :
predict_rsp_instr[15:13] == 3'b101 &&
predict_rsp_instr[1:0] == 2'b01 ||
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 ||
(predict_rsp_instr[15:12] != 4'b1001 ||
predict_rsp_instr[11:7] == 5'd0 ||
predict_rsp_instr[6:2] != 5'd0 ||
predict_rsp_instr[1:0] != 2'b10) &&
predict_rsp_instr[11:7] != 5'd1 &&
predict_rsp_instr[11:7] != 5'd5 ;
assign IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d51 =
(predict_rsp_is_i32_not_i16 ?
predict_rsp_instr[6:0] != 7'b1101111 :
(predict_rsp_instr[15:13] != 3'b101 ||
predict_rsp_instr[1:0] != 2'b01) &&
(predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 ||
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 ||
predict_rsp_instr[6:0] != 7'b1101111)) ||
IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d50 ;
assign IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d78 =
(predict_rsp_is_i32_not_i16 ?
predict_rsp_instr[11:7] == 5'd1 ||
predict_rsp_instr[11:7] == 5'd5 :
(predict_rsp_instr[15:13] != 3'b101 ||
predict_rsp_instr[1:0] != 2'b01) &&
(predict_rsp_instr[15:12] != 4'b1000 ||
predict_rsp_instr[11:7] == 5'd0 ||
predict_rsp_instr[6:2] != 5'd0 ||
predict_rsp_instr[1:0] != 2'b10) &&
(predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 ||
predict_rsp_instr[11:7] == 5'd1 ||
predict_rsp_instr[11:7] == 5'd5)) &&
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d68 ;
assign IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d86 =
(predict_rsp_is_i32_not_i16 ?
predict_rsp_instr[6:0] == 7'b1100111 :
(predict_rsp_instr[15:13] != 3'b101 ||
predict_rsp_instr[1:0] != 2'b01) &&
(predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 ||
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 ||
predict_rsp_instr[6:0] == 7'b1100111)) &&
(IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d50 &&
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d68 ||
IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d78 &&
IF_predict_rsp_is_i32_not_i16_OR_predict_rsp_i_ETC___d83) ;
assign NOT_bp_train_instr_BITS_11_TO_7_16_EQ_bp_train_ETC___d194 =
bp_train_instr[11:7] != bp_train_instr[19:15] ;
assign NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1000__ETC___d125 =
bp_train_instr[15:12] != 4'b1000 ||
bp_train_instr[11:7] == 5'd0 ||
bp_train_instr[6:2] != 5'd0 ||
bp_train_instr[1:0] != 2'b10 ;
assign NOT_bp_train_instr_BITS_15_TO_12_13_EQ_0b1001__ETC___d130 =
bp_train_instr[15:12] != 4'b1001 ||
bp_train_instr[11:7] == 5'd0 ||
bp_train_instr[6:2] != 5'd0 ||
bp_train_instr[1:0] != 2'b10 ;
assign NOT_predict_rsp_instr_BITS_11_TO_7_8_EQ_predic_ETC___d80 =
predict_rsp_instr[11:7] != predict_rsp_instr[19:15] ;
assign _theResult_____1__h2383 =
(_theResult____h2382 == 64'hFFFFFFFFFFFFFFFF &&
btb_bramcore2$DOA[117] &&
btb_bramcore2$DOA[116:63] == rg_pc[63:10]) ?
pred_pc__h3338 :
_theResult____h2382 ;
assign _theResult_____1_fst__h7431 =
bp_train_cf_info[128] ?
_theResult_____1_fst__h7498 :
_theResult_____1_fst__h7542 ;
assign _theResult_____1_snd__h7432 =
bp_train_cf_info[128] ?
_theResult_____1_snd__h7499 :
_theResult_____1_snd__h7543 ;
assign _theResult____h2382 =
(IF_predict_rsp_is_i32_not_i16_THEN_NOT_predict_ETC___d51 &&
IF_predict_rsp_is_i32_not_i16_THEN_predict_rsp_ETC___d86) ?
rg_ras[63:0] :
64'hFFFFFFFFFFFFFFFF ;
assign bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 =
bp_train_instr[15:12] == 4'b1000 &&
bp_train_instr[11:7] != 5'd0 &&
bp_train_instr[6:2] == 5'd0 &&
bp_train_instr[1:0] == 2'b10 ;
assign bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d196 =
bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_A_ETC___d153 ||
(bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 ?
bp_train_instr[11:7] != 5'd1 :
NOT_bp_train_instr_BITS_11_TO_7_16_EQ_bp_train_ETC___d194) ;
assign bp_train_instr_BITS_15_TO_12_13_EQ_0b1000_14_O_ETC___d168 =
(bp_train_instr[15:12] == 4'b1000 ||
bp_train_instr[15:12] == 4'b1001) &&
bp_train_instr[11:7] != 5'd0 &&
bp_train_instr[6:2] == 5'd0 &&
bp_train_instr[1:0] == 2'b10 ;
assign bp_train_instr_BITS_15_TO_12_13_EQ_0b1001_26_A_ETC___d144 =
bp_train_instr[15:12] == 4'b1001 &&
bp_train_instr[11:7] != 5'd0 &&
bp_train_instr[6:2] == 5'd0 &&
bp_train_instr[1:0] == 2'b10 ;
assign pred_pc__h3338 = { btb_bramcore2$DOA[62:0], 1'b0 } ;
assign pred_pc__h3340 =
rg_pc + (predict_rsp_is_i32_not_i16 ? 64'd4 : 64'd2) ;
assign predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 =
predict_rsp_instr[15:12] == 4'b1000 &&
predict_rsp_instr[11:7] != 5'd0 &&
predict_rsp_instr[6:2] == 5'd0 &&
predict_rsp_instr[1:0] == 2'b10 ;
assign predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d82 =
predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1000_7__ETC___d26 ||
(predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 ?
predict_rsp_instr[11:7] != 5'd1 :
NOT_predict_rsp_instr_BITS_11_TO_7_8_EQ_predic_ETC___d80) ;
assign predict_rsp_instr_BITS_15_TO_12_6_EQ_0b1001_7__ETC___d30 =
predict_rsp_instr[15:12] == 4'b1001 &&
predict_rsp_instr[11:7] != 5'd0 &&
predict_rsp_instr[6:2] == 5'd0 &&
predict_rsp_instr[1:0] == 2'b10 ;
assign ret_pc___1__h4093 = bp_train_pc + 64'd2 ;
assign ret_pc__h4055 = bp_train_pc + 64'd4 ;
always@(rf_btb_fsms$D_OUT_1 or bp_train_cf_info)
begin
case (rf_btb_fsms$D_OUT_1)
2'b0: _theResult_____1_fst__h7498 = bp_train_cf_info[127:64];
2'b01, 2'b10, 2'b11:
_theResult_____1_fst__h7498 = bp_train_cf_info[63:0];
endcase
end
always@(rf_btb_fsms$D_OUT_1 or bp_train_cf_info)
begin
case (rf_btb_fsms$D_OUT_1)
2'b0, 2'b01, 2'b10:
_theResult_____1_fst__h7542 = bp_train_cf_info[127:64];
2'b11: _theResult_____1_fst__h7542 = bp_train_cf_info[63:0];
endcase
end
always@(bp_train_cf_info or _theResult_____1_fst__h7431)
begin
case (bp_train_cf_info[194:193])
2'd0: pred_PC__h7403 = _theResult_____1_fst__h7431;
2'd1, 2'd2: pred_PC__h7403 = bp_train_cf_info[63:0];
2'd3: pred_PC__h7403 = 64'hFFFFFFFFFFFFFFFF;
endcase
end
always@(rf_btb_fsms$D_OUT_1)
begin
case (rf_btb_fsms$D_OUT_1)
2'b0, 2'b01: _theResult_____1_snd__h7543 = 2'b0;
2'b10: _theResult_____1_snd__h7543 = 2'b01;
2'b11: _theResult_____1_snd__h7543 = 2'b10;
endcase
end
always@(rf_btb_fsms$D_OUT_1)
begin
case (rf_btb_fsms$D_OUT_1)
2'b0: _theResult_____1_snd__h7499 = 2'b01;
2'b01: _theResult_____1_snd__h7499 = 2'b10;
2'b10, 2'b11: _theResult_____1_snd__h7499 = 2'b11;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_index <= `BSV_ASSIGNMENT_DELAY 9'd0;
rg_ras <= `BSV_ASSIGNMENT_DELAY
1024'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (rg_index$EN) rg_index <= `BSV_ASSIGNMENT_DELAY rg_index$D_IN;
if (rg_ras$EN) rg_ras <= `BSV_ASSIGNMENT_DELAY rg_ras$D_IN;
if (rg_resetting$EN)
rg_resetting <= `BSV_ASSIGNMENT_DELAY rg_resetting$D_IN;
end
if (rg_pc$EN) rg_pc <= `BSV_ASSIGNMENT_DELAY rg_pc$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_index = 9'h0AA;
rg_pc = 64'hAAAAAAAAAAAAAAAA;
rg_ras =
1024'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_resetting = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkBranch_Predictor
|
module FSM_Ctrol (
input RST, // Reset maestro
input CLK, // Reloj maestro
input STM, // Iniciar multiplicacion
output reg ENpH, // Habilitaciones Rp Alto
output reg ENpL, // Habilitaciones Rp Bajo
output reg ENa, // Habilitaciones Ra
output reg ENr, // Habilitaciones Rr
output reg SEL, // Selector Mux
output reg EOM // Fin de multiplicacion
);
reg[2:0] Qp,Qn;
always @ *
begin : Combinacional
case (Qp)
3'b000 : begin // Idle
if (STM)
Qn = 3'b001;
else
Qn = Qp;
ENpH = 1'b0;
ENpL = 1'b0;
ENa = 1'b0;
ENr = 1'b0;
SEL = 1'b0;
EOM = 1'b1;
end
3'b001 : begin
Qn = 3'b010;
ENpH = 1'b1;
ENpL = 1'b0;
ENa = 1'b0;
ENr = 1'b0;
SEL = 1'b0;
EOM = 1'b0;
end
3'b010 : begin
Qn = 3'b011;
ENpH = 1'b0;
ENpL = 1'b1;
ENa = 1'b1;
ENr = 1'b0;
SEL = 1'b0;
EOM = 1'b0;
end
3'b011 : begin
Qn = 3'b000;
ENpH = 1'b0;
ENpL = 1'b0;
ENa = 1'b1;
ENr = 1'b1;
SEL = 1'b1;
EOM = 1'b0;
end
// 3'b100 : begin
// Qn = 3'b000;
// ENpH = 1'b0;
// ENpL = 1'b0;
// ENa = 1'b0;
// ENr = 1'b1;
// SEL = 1'b0;
// end
endcase
end
always @ (posedge RST or posedge CLK)
begin : Secuencial
if (RST)
Qp <= 0;
else
Qp <= Qn;
end
endmodule
|
// file: clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// _____clk____12.727______0.000______50.0______285.078____281.140
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________125____________0.010
`timescale 1ps/1ps
module clk_gen_clk_wiz
(// Clock in ports
input clk125,
// Clock out ports
output clk,
// Status and control signals
output clk_locked
);
// Input buffering
//------------------------------------
wire clk125_clk_gen;
wire clk_in2_clk_gen;
IBUF clkin1_ibufg
(.O (clk125_clk_gen),
.I (clk125));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_clk_gen;
wire clk_out2_clk_gen;
wire clk_out3_clk_gen;
wire clk_out4_clk_gen;
wire clk_out5_clk_gen;
wire clk_out6_clk_gen;
wire clk_out7_clk_gen;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clk_locked_int;
wire clkfbout_clk_gen;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (6),
.CLKFBOUT_MULT_F (53.375),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (87.375),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (8.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_gen),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_clk_gen),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_clk_gen),
.CLKIN1 (clk125_clk_gen),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (clk_locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign clk_locked = clk_locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (clk),
.I (clk_clk_gen));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_2_V
`define SKY130_FD_SC_HD__SDFRTP_2_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_2_V
|
`timescale 1ns/1ns
module usb_tx_stuff
(input c,
input d,
input d_empty,
output d_req,
output q,
input q_req,
output q_empty);
localparam ST_IDLE = 4'd0;
localparam ST_READ = 4'd1;
localparam ST_STUFF = 4'd2;
localparam ST_DONE = 4'd3;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire [2:0] ones_count;
wire [2:0] done_cnt; // hold the DONE state for a full two bits for downstream
wire done_cnt_rst;
r #(3) done_cnt_r
(.c(c), .rst(done_cnt_rst), .en(1'b1), .d(done_cnt+1'b1), .q(done_cnt));
// todo: clean this up. it got ugly.
always @* begin
case (state)
ST_IDLE:
if (~d_empty) ctrl = { ST_READ , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_READ:
if (d_empty) ctrl = { ST_DONE , 5'b00010 };
else if (q_req)
if (ones_count == 3'd5 & d == 1'b1)
ctrl = { ST_STUFF, 5'b00110 };
else ctrl = { ST_READ , 5'b00011 };
else ctrl = { ST_READ , 5'b00000 };
ST_STUFF:
if (d_empty) ctrl = { ST_DONE , 5'b00011 };
else if (q_req) ctrl = { ST_READ , 5'b00001 };
else ctrl = { ST_STUFF, 5'b00100 };
ST_DONE:
if (done_cnt == 3'h7) ctrl = { ST_IDLE , 5'b00000 };
else ctrl = { ST_DONE , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign d_req = ctrl[0];
assign done_cnt_rst = ctrl[1];
wire supress_empty = ctrl[2];
r #(3, 3'd0) ones_count_r
(.c(c), .rst(state == ST_IDLE | (q_req & d == 1'b0) | state == ST_STUFF),
.en(q_req & d == 1'b1),
.d(ones_count + 1'b1), .q(ones_count));
wire nrzi;
wire next_nrzi = (state == ST_STUFF) ? ~nrzi : (d ? nrzi : ~nrzi);
r #(1, 1'b1) nrzi_r
(.c(c), .rst(state == ST_IDLE), .en(state != ST_IDLE & q_req),
.d(next_nrzi), .q(nrzi));
assign q = nrzi;
assign q_empty = d_empty & ~supress_empty;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__OR3B_FUNCTIONAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_FUNCTIONAL_PP_V |
`timescale 1ns/1ns
module arbiter_tb();
// Request bundles are composed by:
// * request_bundle[2] :: hit_x
// * request_bundle[1] :: hit_y
// * request_bundle[0] :: request
reg [2:0] pe_request_bundle;
reg [2:0] north_request_bundle;
reg [2:0] east_request_bundle;
// Configuration bundles are composed by:
// * cfg_bundle[2] :: mux_ctrl[1]
// * cfg_bundle[1] :: mux_ctrl[0]
// * cfg_bundle[0] :: toggle
wire [1:0] pe_cfg_bundle;
wire [2:0] south_cfg_bundle;
wire [2:0] west_cfg_bundle;
// ACK that a request from the PE has been accepted
wire r2pe_ack;
// localparam
localparam MUX_EAST = 3'b011;
localparam MUX_NORTH = 3'b001;
localparam MUX_PE = 3'b101;
localparam MUX_NULL = 3'b000;
localparam WEST = 3'b011;
localparam SOUTH = 3'b101;
localparam PE = 3'b111;
localparam NULL = 3'b000;
arbitro UUT(
// Request bundles are composed by:
// * request_bundle[2] :: hit_x
// * request_bundle[1] :: hit_y
// * request_bundle[0] :: request
.pe_request_bundle (pe_request_bundle),
.north_request_bundle (north_request_bundle),
.east_request_bundle (east_request_bundle),
// Configuration bundles are composed by:
// * cfg_bundle[2] :: mux_ctrl[1]
// * cfg_bundle[1] :: mux_ctrl[0]
// * cfg_bundle[0] :: toggle
.pe_cfg_bundle (pe_cfg_bundle),
.south_cfg_bundle (south_cfg_bundle),
.west_cfg_bundle (west_cfg_bundle),
// ACK that a request from the PE has been accepted
.r2pe_ack (r2pe_ack)
);
// stimuli
initial
begin
// initial values
pe_request_bundle = 0;
north_request_bundle = 0;
east_request_bundle = 0;
// stimuli
#(30);
// out of stability period
north_request_bundle = WEST;
#(20);
north_request_bundle = NULL;
#(20);
north_request_bundle = SOUTH;
#(20);
north_request_bundle = PE;
#(20);
north_request_bundle = NULL;
// Done with North
// Start PE request
pe_request_bundle = WEST;
#(20);
pe_request_bundle = SOUTH;
#(20);
pe_request_bundle = SOUTH | WEST;
#(20);
pe_request_bundle = NULL;
#(20)
// Done with PE
// Start South request
east_request_bundle = WEST;
#(20);
east_request_bundle = SOUTH;
#(20);
east_request_bundle = PE;
#(20);
east_request_bundle = NULL;
#(20);
// Done with South
// Multiple Petition
north_request_bundle = WEST;
east_request_bundle = SOUTH;
#(20);
north_request_bundle = NULL;
east_request_bundle = NULL;
#(20);
north_request_bundle = WEST;
east_request_bundle = WEST;
#(20);
north_request_bundle = NULL;
east_request_bundle = NULL;
#(20);
north_request_bundle = SOUTH;
east_request_bundle = SOUTH;
pe_request_bundle = WEST;
#(20);
north_request_bundle = SOUTH;
east_request_bundle = WEST;
pe_request_bundle = WEST;
#(20);
north_request_bundle = PE;
east_request_bundle = WEST;
pe_request_bundle = WEST;
#(20);
north_request_bundle = SOUTH;
east_request_bundle = PE;
pe_request_bundle = WEST;
#(20);
north_request_bundle = NULL;
east_request_bundle = NULL;
pe_request_bundle = NULL;
#(20);
// Done with Multiple
#(200);
$finish;
end
endmodule //arbiter_tb
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_SYMBOL_V
`define SKY130_FD_SC_HVL__BUF_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__buf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND2B_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand2b (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_BLACKBOX_V
|
/**
* decoder_complex_tb.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module decoder_complex_tb;
/* inputs and control signals */
reg [7:0] opcode;
reg clk;
/* output signal */
wire [5:0] rom_offset;
/* unit under testing */
decoder_complex uut (
.opcode(opcode),
.rom_offset(rom_offset)
);
initial begin
/* signal initialization */
opcode = 0;
clk = 0;
/* finish simulation */
#1000 $finish;
end
always
#50 clk = ~clk;
always @(posedge clk)
opcode = opcode + 1'b1;
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
/* Generated by Yosys 0.7 (git sha1 61f6811, gcc 5.4.0-6ubuntu1~16.04.4 -O2 -fstack-protector-strong -fPIC -Os) */
(* top = 1 *)
(* src = "harder2_multi.v:2" *)
module harder2_multi(A, B, C, D, E, F, valid);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire _34_;
wire _35_;
wire _36_;
wire _37_;
wire _38_;
wire _39_;
wire _40_;
wire _41_;
wire _42_;
wire _43_;
wire _44_;
(* src = "harder2_multi.v:3" *)
input A;
(* src = "harder2_multi.v:3" *)
input B;
(* src = "harder2_multi.v:3" *)
input C;
(* src = "harder2_multi.v:3" *)
input D;
(* src = "harder2_multi.v:3" *)
input E;
(* src = "harder2_multi.v:3" *)
input F;
(* src = "harder2_multi.v:9" *)
wire [7:0] total_value;
(* src = "harder2_multi.v:4" *)
output valid;
assign _43_ = C & D;
assign _44_ = _43_ ^ A;
assign _00_ = ~E;
assign _01_ = ~(C | D);
assign _02_ = ~(_01_ | _00_);
assign _03_ = ~(_02_ & _44_);
assign _04_ = ~(A ^ B);
assign _05_ = ~(A & D);
assign _06_ = _05_ & C;
assign _07_ = _06_ ^ _04_;
assign _08_ = _07_ | _00_;
assign _09_ = _08_ & _03_;
assign _10_ = ~D;
assign _11_ = ~B;
assign _12_ = A | _11_;
assign _13_ = A & _11_;
assign _14_ = ~((_13_ | C) & _12_);
assign _15_ = _14_ & _10_;
assign _16_ = ~(_14_ | _10_);
assign _17_ = A & B;
assign _18_ = ~(_17_ & C);
assign _19_ = ~((_18_ & _16_) | _15_);
assign _20_ = _19_ ^ _00_;
assign _21_ = _20_ ^ _09_;
assign _22_ = ~F;
assign _23_ = _03_ & E;
assign _24_ = _23_ ^ _07_;
assign _25_ = E ? _43_ : _01_;
assign _26_ = ~(_02_ | _44_);
assign _27_ = _26_ & _25_;
assign _28_ = ~((_27_ & _24_) | _22_);
assign _29_ = _28_ | _21_;
assign _30_ = _14_ | _10_;
assign _31_ = A | B;
assign _32_ = ~((_17_ | C) & _31_);
assign _33_ = ~((_32_ & _30_) | (_43_ & A));
assign _34_ = ~((_19_ & E) | _33_);
assign _35_ = ~((_20_ | _09_) & _34_);
assign _36_ = _26_ | _25_;
assign _37_ = ~((_36_ | _24_) & _22_);
assign _38_ = _37_ & _35_;
assign _39_ = A | _10_;
assign _40_ = _39_ | _22_;
assign _41_ = E ? C : _11_;
assign _42_ = _41_ | _40_;
assign valid = ~((_38_ & _29_) | _42_);
assign total_value[1:0] = { E, 1'b0 };
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// valid O 1
// addr O 64 reg
// cword O 64
// st_amo_val O 64
// exc O 1
// exc_code O 4 reg
// RDY_server_flush_request_put O 1 reg
// RDY_server_flush_response_get O 1
// RDY_tlb_flush O 1 const
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_op I 2
// req_f3 I 3
// req_amo_funct7 I 7 reg
// req_addr I 64
// req_st_value I 64
// req_priv I 2 reg
// req_sstatus_SUM I 1 reg
// req_mstatus_MXR I 1 reg
// req_satp I 64 reg
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_set_verbosity I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
// EN_server_flush_request_put I 1
// EN_server_flush_response_get I 1
// EN_tlb_flush I 1
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMMU_Cache(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_op,
req_f3,
req_amo_funct7,
req_addr,
req_st_value,
req_priv,
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
EN_req,
valid,
addr,
cword,
st_amo_val,
exc,
exc_code,
EN_server_flush_request_put,
RDY_server_flush_request_put,
EN_server_flush_response_get,
RDY_server_flush_response_get,
EN_tlb_flush,
RDY_tlb_flush,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
parameter [0 : 0] dmem_not_imem = 1'b0;
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [1 : 0] req_op;
input [2 : 0] req_f3;
input [6 : 0] req_amo_funct7;
input [63 : 0] req_addr;
input [63 : 0] req_st_value;
input [1 : 0] req_priv;
input req_sstatus_SUM;
input req_mstatus_MXR;
input [63 : 0] req_satp;
input EN_req;
// value method valid
output valid;
// value method addr
output [63 : 0] addr;
// value method cword
output [63 : 0] cword;
// value method st_amo_val
output [63 : 0] st_amo_val;
// value method exc
output exc;
// value method exc_code
output [3 : 0] exc_code;
// action method server_flush_request_put
input EN_server_flush_request_put;
output RDY_server_flush_request_put;
// action method server_flush_response_get
input EN_server_flush_response_get;
output RDY_server_flush_response_get;
// action method tlb_flush
input EN_tlb_flush;
output RDY_tlb_flush;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
reg [63 : 0] cword;
wire [63 : 0] addr,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value,
st_amo_val;
wire [7 : 0] mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [3 : 0] exc_code,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] mem_master_arburst, mem_master_awburst;
wire RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_server_flush_request_put,
RDY_server_flush_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_verbosity,
RDY_set_watch_tohost,
RDY_tlb_flush,
exc,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid,
valid;
// inlined wires
wire [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1,
ctr_wr_rsps_pending_crg$port1__write_1,
ctr_wr_rsps_pending_crg$port2__read,
ctr_wr_rsps_pending_crg$port3__read;
wire ctr_wr_rsps_pending_crg$EN_port2__write, dw_valid$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register ctr_wr_rsps_pending_crg
reg [3 : 0] ctr_wr_rsps_pending_crg;
wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
wire ctr_wr_rsps_pending_crg$EN;
// register rg_addr
reg [63 : 0] rg_addr;
wire [63 : 0] rg_addr$D_IN;
wire rg_addr$EN;
// register rg_amo_funct7
reg [6 : 0] rg_amo_funct7;
wire [6 : 0] rg_amo_funct7$D_IN;
wire rg_amo_funct7$EN;
// register rg_cset_cword_in_cache
reg [8 : 0] rg_cset_cword_in_cache;
wire [8 : 0] rg_cset_cword_in_cache$D_IN;
wire rg_cset_cword_in_cache$EN;
// register rg_cset_in_cache
reg [5 : 0] rg_cset_in_cache;
wire [5 : 0] rg_cset_in_cache$D_IN;
wire rg_cset_in_cache$EN;
// register rg_ddr4_ready
reg rg_ddr4_ready;
wire rg_ddr4_ready$D_IN, rg_ddr4_ready$EN;
// register rg_error_during_refill
reg rg_error_during_refill;
wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;
// register rg_exc_code
reg [3 : 0] rg_exc_code;
reg [3 : 0] rg_exc_code$D_IN;
wire rg_exc_code$EN;
// register rg_f3
reg [2 : 0] rg_f3;
wire [2 : 0] rg_f3$D_IN;
wire rg_f3$EN;
// register rg_ld_val
reg [63 : 0] rg_ld_val;
reg [63 : 0] rg_ld_val$D_IN;
wire rg_ld_val$EN;
// register rg_lower_word32
reg [31 : 0] rg_lower_word32;
wire [31 : 0] rg_lower_word32$D_IN;
wire rg_lower_word32$EN;
// register rg_lower_word32_full
reg rg_lower_word32_full;
wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;
// register rg_lrsc_pa
reg [63 : 0] rg_lrsc_pa;
wire [63 : 0] rg_lrsc_pa$D_IN;
wire rg_lrsc_pa$EN;
// register rg_lrsc_valid
reg rg_lrsc_valid;
wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;
// register rg_mstatus_MXR
reg rg_mstatus_MXR;
wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;
// register rg_op
reg [1 : 0] rg_op;
wire [1 : 0] rg_op$D_IN;
wire rg_op$EN;
// register rg_pa
reg [63 : 0] rg_pa;
wire [63 : 0] rg_pa$D_IN;
wire rg_pa$EN;
// register rg_priv
reg [1 : 0] rg_priv;
wire [1 : 0] rg_priv$D_IN;
wire rg_priv$EN;
// register rg_pte_pa
reg [63 : 0] rg_pte_pa;
reg [63 : 0] rg_pte_pa$D_IN;
wire rg_pte_pa$EN;
// register rg_satp
reg [63 : 0] rg_satp;
wire [63 : 0] rg_satp$D_IN;
wire rg_satp$EN;
// register rg_sstatus_SUM
reg rg_sstatus_SUM;
wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;
// register rg_st_amo_val
reg [63 : 0] rg_st_amo_val;
wire [63 : 0] rg_st_amo_val$D_IN;
wire rg_st_amo_val$EN;
// register rg_state
reg [4 : 0] rg_state;
reg [4 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_tohost_addr
reg [63 : 0] rg_tohost_addr;
wire [63 : 0] rg_tohost_addr$D_IN;
wire rg_tohost_addr$EN;
// register rg_tohost_value
reg [63 : 0] rg_tohost_value;
wire [63 : 0] rg_tohost_value$D_IN;
wire rg_tohost_value$EN;
// register rg_victim_way
reg rg_victim_way;
wire rg_victim_way$D_IN, rg_victim_way$EN;
// register rg_watch_tohost
reg rg_watch_tohost;
wire rg_watch_tohost$D_IN, rg_watch_tohost$EN;
// register rg_wr_rsp_err
reg rg_wr_rsp_err;
wire rg_wr_rsp_err$D_IN, rg_wr_rsp_err$EN;
// ports of submodule f_fabric_write_reqs
reg [130 : 0] f_fabric_write_reqs$D_IN;
wire [130 : 0] f_fabric_write_reqs$D_OUT;
wire f_fabric_write_reqs$CLR,
f_fabric_write_reqs$DEQ,
f_fabric_write_reqs$EMPTY_N,
f_fabric_write_reqs$ENQ,
f_fabric_write_reqs$FULL_N;
// ports of submodule f_pte_writebacks
wire [127 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT;
wire f_pte_writebacks$CLR,
f_pte_writebacks$DEQ,
f_pte_writebacks$EMPTY_N,
f_pte_writebacks$ENQ,
f_pte_writebacks$FULL_N;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule master_xactor_f_rd_addr
reg [96 : 0] master_xactor_f_rd_addr$D_IN;
wire [96 : 0] master_xactor_f_rd_addr$D_OUT;
wire master_xactor_f_rd_addr$CLR,
master_xactor_f_rd_addr$DEQ,
master_xactor_f_rd_addr$EMPTY_N,
master_xactor_f_rd_addr$ENQ,
master_xactor_f_rd_addr$FULL_N;
// ports of submodule master_xactor_f_rd_data
wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
wire master_xactor_f_rd_data$CLR,
master_xactor_f_rd_data$DEQ,
master_xactor_f_rd_data$EMPTY_N,
master_xactor_f_rd_data$ENQ,
master_xactor_f_rd_data$FULL_N;
// ports of submodule master_xactor_f_wr_addr
wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
wire master_xactor_f_wr_addr$CLR,
master_xactor_f_wr_addr$DEQ,
master_xactor_f_wr_addr$EMPTY_N,
master_xactor_f_wr_addr$ENQ,
master_xactor_f_wr_addr$FULL_N;
// ports of submodule master_xactor_f_wr_data
wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
wire master_xactor_f_wr_data$CLR,
master_xactor_f_wr_data$DEQ,
master_xactor_f_wr_data$EMPTY_N,
master_xactor_f_wr_data$ENQ,
master_xactor_f_wr_data$FULL_N;
// ports of submodule master_xactor_f_wr_resp
wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
wire master_xactor_f_wr_resp$CLR,
master_xactor_f_wr_resp$DEQ,
master_xactor_f_wr_resp$EMPTY_N,
master_xactor_f_wr_resp$ENQ,
master_xactor_f_wr_resp$FULL_N;
// ports of submodule ram_cword_set
reg [127 : 0] ram_cword_set$DIB;
reg [8 : 0] ram_cword_set$ADDRB;
wire [127 : 0] ram_cword_set$DIA, ram_cword_set$DOB;
wire [8 : 0] ram_cword_set$ADDRA;
wire ram_cword_set$ENA,
ram_cword_set$ENB,
ram_cword_set$WEA,
ram_cword_set$WEB;
// ports of submodule ram_state_and_ctag_cset
wire [105 : 0] ram_state_and_ctag_cset$DIA,
ram_state_and_ctag_cset$DIB,
ram_state_and_ctag_cset$DOB;
wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
wire ram_state_and_ctag_cset$ENA,
ram_state_and_ctag_cset$ENB,
ram_state_and_ctag_cset$WEA,
ram_state_and_ctag_cset$WEB;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
wire soc_map$m_is_mem_addr;
// ports of submodule tlb
reg [1 : 0] tlb$insert_level;
wire [130 : 0] tlb$lookup;
wire [63 : 0] tlb$insert_pte, tlb$insert_pte_pa;
wire [26 : 0] tlb$insert_vpn, tlb$lookup_vpn;
wire [15 : 0] tlb$insert_asid, tlb$lookup_asid;
wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup;
// rule scheduling signals
wire CAN_FIRE_RL_rl_ST_AMO_response,
CAN_FIRE_RL_rl_cache_refill_rsps_loop,
CAN_FIRE_RL_rl_discard_write_rsp,
CAN_FIRE_RL_rl_drive_exception_rsp,
CAN_FIRE_RL_rl_fabric_send_write_req,
CAN_FIRE_RL_rl_io_AMO_SC_req,
CAN_FIRE_RL_rl_io_AMO_op_req,
CAN_FIRE_RL_rl_io_AMO_read_rsp,
CAN_FIRE_RL_rl_io_read_req,
CAN_FIRE_RL_rl_io_read_rsp,
CAN_FIRE_RL_rl_io_write_req,
CAN_FIRE_RL_rl_maintain_io_read_rsp,
CAN_FIRE_RL_rl_probe_and_immed_rsp,
CAN_FIRE_RL_rl_ptw_level_0,
CAN_FIRE_RL_rl_ptw_level_1,
CAN_FIRE_RL_rl_ptw_level_2,
CAN_FIRE_RL_rl_rereq,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_start_cache_refill,
CAN_FIRE_RL_rl_start_reset,
CAN_FIRE_RL_rl_start_tlb_refill,
CAN_FIRE_RL_rl_writeback_updated_PTE,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_req,
CAN_FIRE_server_flush_request_put,
CAN_FIRE_server_flush_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_tlb_flush,
WILL_FIRE_RL_rl_ST_AMO_response,
WILL_FIRE_RL_rl_cache_refill_rsps_loop,
WILL_FIRE_RL_rl_discard_write_rsp,
WILL_FIRE_RL_rl_drive_exception_rsp,
WILL_FIRE_RL_rl_fabric_send_write_req,
WILL_FIRE_RL_rl_io_AMO_SC_req,
WILL_FIRE_RL_rl_io_AMO_op_req,
WILL_FIRE_RL_rl_io_AMO_read_rsp,
WILL_FIRE_RL_rl_io_read_req,
WILL_FIRE_RL_rl_io_read_rsp,
WILL_FIRE_RL_rl_io_write_req,
WILL_FIRE_RL_rl_maintain_io_read_rsp,
WILL_FIRE_RL_rl_probe_and_immed_rsp,
WILL_FIRE_RL_rl_ptw_level_0,
WILL_FIRE_RL_rl_ptw_level_1,
WILL_FIRE_RL_rl_ptw_level_2,
WILL_FIRE_RL_rl_rereq,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_start_cache_refill,
WILL_FIRE_RL_rl_start_reset,
WILL_FIRE_RL_rl_start_tlb_refill,
WILL_FIRE_RL_rl_writeback_updated_PTE,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_req,
WILL_FIRE_server_flush_request_put,
WILL_FIRE_server_flush_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_tlb_flush;
// inputs to muxes for submodule ports
wire [130 : 0] MUX_f_fabric_write_reqs$enq_1__VAL_1,
MUX_f_fabric_write_reqs$enq_1__VAL_2,
MUX_f_fabric_write_reqs$enq_1__VAL_3,
MUX_f_fabric_write_reqs$enq_1__VAL_4;
wire [127 : 0] MUX_ram_cword_set$a_put_3__VAL_1,
MUX_ram_cword_set$a_put_3__VAL_2;
wire [105 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
MUX_master_xactor_f_rd_addr$enq_1__VAL_2,
MUX_master_xactor_f_rd_addr$enq_1__VAL_3,
MUX_master_xactor_f_rd_addr$enq_1__VAL_4,
MUX_master_xactor_f_rd_addr$enq_1__VAL_5;
wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
MUX_rg_ld_val$write_1__VAL_2;
wire [8 : 0] MUX_ram_cword_set$b_put_2__VAL_2,
MUX_ram_cword_set$b_put_2__VAL_4;
wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
wire [4 : 0] MUX_rg_state$write_1__VAL_11,
MUX_rg_state$write_1__VAL_13,
MUX_rg_state$write_1__VAL_14,
MUX_rg_state$write_1__VAL_15,
MUX_rg_state$write_1__VAL_17,
MUX_rg_state$write_1__VAL_2,
MUX_rg_state$write_1__VAL_4;
wire [3 : 0] MUX_rg_exc_code$write_1__VAL_1, MUX_rg_exc_code$write_1__VAL_5;
wire MUX_dw_output_ld_val$wset_1__SEL_1,
MUX_dw_output_ld_val$wset_1__SEL_2,
MUX_dw_output_ld_val$wset_1__SEL_4,
MUX_dw_valid$wset_1__SEL_2,
MUX_f_fabric_write_reqs$enq_1__SEL_2,
MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
MUX_master_xactor_f_rd_addr$enq_1__SEL_2,
MUX_master_xactor_f_rd_addr$enq_1__SEL_3,
MUX_ram_cword_set$a_put_1__SEL_1,
MUX_ram_cword_set$b_put_1__SEL_2,
MUX_ram_cword_set$b_put_2__SEL_1,
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1,
MUX_rg_error_during_refill$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_2,
MUX_rg_exc_code$write_1__SEL_3,
MUX_rg_exc_code$write_1__SEL_5,
MUX_rg_exc_code$write_1__SEL_6,
MUX_rg_exc_code$write_1__SEL_7,
MUX_rg_exc_code$write_1__SEL_8,
MUX_rg_ld_val$write_1__SEL_2,
MUX_rg_lrsc_valid$write_1__SEL_2,
MUX_rg_state$write_1__SEL_11,
MUX_rg_state$write_1__SEL_17,
MUX_rg_state$write_1__SEL_18,
MUX_rg_state$write_1__SEL_3,
MUX_tlb$insert_1__SEL_1,
MUX_tlb$insert_1__SEL_2,
MUX_tlb$insert_1__SEL_3,
MUX_tlb$insert_1__SEL_4;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4526;
reg [31 : 0] v__h4621;
reg [31 : 0] v__h4747;
reg [31 : 0] v__h21325;
reg [31 : 0] v__h25029;
reg [31 : 0] v__h43514;
reg [31 : 0] v__h28547;
reg [31 : 0] v__h29498;
reg [31 : 0] v__h29236;
reg [31 : 0] v__h29801;
reg [31 : 0] v__h29918;
reg [31 : 0] v__h29418;
reg [31 : 0] v__h30591;
reg [31 : 0] v__h30332;
reg [31 : 0] v__h31011;
reg [31 : 0] v__h30894;
reg [31 : 0] v__h30511;
reg [31 : 0] v__h31524;
reg [31 : 0] v__h31604;
reg [31 : 0] v__h31695;
reg [31 : 0] v__h31444;
reg [31 : 0] v__h31831;
reg [31 : 0] v__h32639;
reg [31 : 0] v__h32877;
reg [31 : 0] v__h43437;
reg [31 : 0] v__h35556;
reg [31 : 0] v__h35889;
reg [31 : 0] v__h36984;
reg [31 : 0] v__h37112;
reg [31 : 0] v__h37205;
reg [31 : 0] v__h37285;
reg [31 : 0] v__h37512;
reg [31 : 0] v__h37648;
reg [31 : 0] v__h37929;
reg [31 : 0] v__h38111;
reg [31 : 0] v__h40357;
reg [31 : 0] v__h38212;
reg [31 : 0] v__h40958;
reg [31 : 0] v__h41000;
reg [31 : 0] v__h4061;
reg [31 : 0] v__h41354;
reg [31 : 0] v__h43050;
reg [31 : 0] v__h4055;
reg [31 : 0] v__h4520;
reg [31 : 0] v__h4615;
reg [31 : 0] v__h4741;
reg [31 : 0] v__h21319;
reg [31 : 0] v__h25023;
reg [31 : 0] v__h28541;
reg [31 : 0] v__h29230;
reg [31 : 0] v__h29412;
reg [31 : 0] v__h29492;
reg [31 : 0] v__h29795;
reg [31 : 0] v__h29912;
reg [31 : 0] v__h30326;
reg [31 : 0] v__h30505;
reg [31 : 0] v__h30585;
reg [31 : 0] v__h30888;
reg [31 : 0] v__h31005;
reg [31 : 0] v__h31438;
reg [31 : 0] v__h31518;
reg [31 : 0] v__h31598;
reg [31 : 0] v__h31689;
reg [31 : 0] v__h31825;
reg [31 : 0] v__h32633;
reg [31 : 0] v__h32871;
reg [31 : 0] v__h35550;
reg [31 : 0] v__h35883;
reg [31 : 0] v__h36978;
reg [31 : 0] v__h37106;
reg [31 : 0] v__h37199;
reg [31 : 0] v__h37279;
reg [31 : 0] v__h37506;
reg [31 : 0] v__h37642;
reg [31 : 0] v__h37923;
reg [31 : 0] v__h38105;
reg [31 : 0] v__h38206;
reg [31 : 0] v__h40351;
reg [31 : 0] v__h40952;
reg [31 : 0] v__h40994;
reg [31 : 0] v__h41348;
reg [31 : 0] v__h43044;
reg [31 : 0] v__h43431;
reg [31 : 0] v__h43508;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result0077_0x4_re_ETC__q51,
CASE_rg_addr_BITS_2_TO_0_0x0_result1153_0x4_re_ETC__q30,
CASE_rg_addr_BITS_2_TO_0_0x0_result6776_0x4_re_ETC__q35,
CASE_rg_addr_BITS_2_TO_0_0x0_result6841_0x4_re_ETC__q36,
CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_21_EQ__ETC__q53,
CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q31,
CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q34,
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759,
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768,
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827,
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1235,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1227,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628,
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654,
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715,
_theResult_____2__h25547,
_theResult_____2__h38282,
_theResult___fst__h6574,
ld_val__h35996,
mem_req_wr_data_wdata__h3063,
n__h22516,
n__h25409,
new_ld_val__h38242,
old_cword__h22505,
w1__h25539,
w1__h38270,
w1__h38274;
reg [7 : 0] mem_req_wr_data_wstrb__h3064;
reg [2 : 0] value__h37822, x__h2890;
reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29,
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324,
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249,
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263,
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279,
IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339;
wire [63 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d779,
IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d847,
IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d778,
IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d846,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_1_E_ETC___d662,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1355,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647,
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784,
IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d856,
_theResult___fst__h6160,
_theResult___fst__h6231,
_theResult___snd_fst__h3071,
_theResult___snd_fst__h6162,
_theResult___snd_fst__h6233,
_theResult___snd_fst__h6803,
cline_fabric_addr__h31880,
lev_0_pte_pa__h30623,
lev_0_pte_pa_w64_fa__h30625,
lev_1_PTN_pa__h29528,
lev_1_pte_pa__h29530,
lev_1_pte_pa_w64_fa__h29532,
lev_2_pte_pa__h28596,
lev_2_pte_pa_w64_fa__h28598,
new_st_val__h25251,
new_st_val__h25551,
new_st_val__h25642,
new_st_val__h26622,
new_st_val__h26626,
new_st_val__h26630,
new_st_val__h26634,
new_st_val__h26639,
new_st_val__h26645,
new_st_val__h26650,
new_st_val__h38286,
new_st_val__h38377,
new_st_val__h40237,
new_st_val__h40241,
new_st_val__h40245,
new_st_val__h40249,
new_st_val__h40254,
new_st_val__h40260,
new_st_val__h40265,
new_value__h24131,
new_value__h7718,
pa___1__h6580,
pa___1__h6629,
pa___1__h6698,
pte___1__h6852,
pte___1__h6880,
pte___2__h6572,
result__h20421,
result__h20449,
result__h20477,
result__h20505,
result__h20533,
result__h20561,
result__h20589,
result__h20617,
result__h20662,
result__h20690,
result__h20718,
result__h20746,
result__h20774,
result__h20802,
result__h20830,
result__h20858,
result__h20903,
result__h20931,
result__h20959,
result__h20987,
result__h21028,
result__h21056,
result__h21084,
result__h21112,
result__h21153,
result__h21181,
result__h21220,
result__h21248,
result__h36065,
result__h36095,
result__h36122,
result__h36149,
result__h36176,
result__h36203,
result__h36230,
result__h36257,
result__h36301,
result__h36328,
result__h36355,
result__h36382,
result__h36409,
result__h36436,
result__h36463,
result__h36490,
result__h36534,
result__h36561,
result__h36588,
result__h36615,
result__h36655,
result__h36682,
result__h36709,
result__h36736,
result__h36776,
result__h36803,
result__h36841,
result__h36868,
result__h38465,
result__h39373,
result__h39401,
result__h39429,
result__h39457,
result__h39485,
result__h39513,
result__h39541,
result__h39586,
result__h39614,
result__h39642,
result__h39670,
result__h39698,
result__h39726,
result__h39754,
result__h39782,
result__h39827,
result__h39855,
result__h39883,
result__h39911,
result__h39952,
result__h39980,
result__h40008,
result__h40036,
result__h40077,
result__h40105,
result__h40144,
result__h40172,
satp_pa__h1890,
value__h6897,
vpn_0_pa__h30622,
vpn_1_pa__h29529,
vpn_2_pa__h28595,
w1___1__h25610,
w1___1__h38345,
w2___1__h38346,
w2__h38276,
word64__h7596,
x1_avValue_pa__h6062,
x__h21714,
x__h38265,
x__h7735,
y__h14065,
y__h7736,
y__h7750;
wire [55 : 0] x__h29603, x__h4883, x__h6583, x__h6632, x__h6701;
wire [31 : 0] IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32,
ld_val5996_BITS_31_TO_0__q39,
ld_val5996_BITS_63_TO_32__q46,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10,
rg_st_amo_val_BITS_31_TO_0__q33,
w18270_BITS_31_TO_0__q52,
word64596_BITS_31_TO_0__q17,
word64596_BITS_63_TO_32__q24;
wire [15 : 0] ld_val5996_BITS_15_TO_0__q38,
ld_val5996_BITS_31_TO_16__q42,
ld_val5996_BITS_47_TO_32__q45,
ld_val5996_BITS_63_TO_48__q49,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13,
word64596_BITS_15_TO_0__q16,
word64596_BITS_31_TO_16__q20,
word64596_BITS_47_TO_32__q23,
word64596_BITS_63_TO_48__q27;
wire [7 : 0] ld_val5996_BITS_15_TO_8__q40,
ld_val5996_BITS_23_TO_16__q41,
ld_val5996_BITS_31_TO_24__q43,
ld_val5996_BITS_39_TO_32__q44,
ld_val5996_BITS_47_TO_40__q47,
ld_val5996_BITS_55_TO_48__q48,
ld_val5996_BITS_63_TO_56__q50,
ld_val5996_BITS_7_TO_0__q37,
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4,
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7,
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11,
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14,
strobe64__h3007,
strobe64__h3009,
strobe64__h3011,
word64596_BITS_15_TO_8__q18,
word64596_BITS_23_TO_16__q19,
word64596_BITS_31_TO_24__q21,
word64596_BITS_39_TO_32__q22,
word64596_BITS_47_TO_40__q25,
word64596_BITS_55_TO_48__q26,
word64596_BITS_63_TO_56__q28,
word64596_BITS_7_TO_0__q15;
wire [5 : 0] shift_bits__h2857;
wire [4 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d441,
IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d443,
IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d442,
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d445;
wire [3 : 0] access_exc_code__h2635,
b__h28501,
exc_code___1__h6472,
x1_avValue_exc_code__h6063;
wire [1 : 0] tmp__h32016, tmp__h32017;
wire IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d334,
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_NOT_ETC___d255,
IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d348,
IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d347,
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485,
NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d323,
NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d329,
NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d333,
NOT_cfg_verbosity_read__1_ULE_2_106___d1107,
NOT_cfg_verbosity_read__1_ULT_2_49___d450,
NOT_dmem_not_imem_28_AND_rg_op_13_EQ_0_14_OR_r_ETC___d385,
NOT_dmem_not_imem_28_OR_NOT_rg_op_13_EQ_0_14_1_ETC___d135,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d479,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d675,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d687,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d692,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d700,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d709,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d722,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d859,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d877,
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d923,
NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d1028,
NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d965,
NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d1034,
NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d972,
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236,
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235,
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d265,
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d285,
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d346,
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d487,
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690,
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d697,
NOT_req_f3_BITS_1_TO_0_440_EQ_0b0_441_442_AND__ETC___d1461,
NOT_rg_op_13_EQ_0_14_15_AND_NOT_rg_op_13_EQ_2__ETC___d436,
NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719,
NOT_rg_op_13_EQ_1_66_93_AND_ram_state_and_ctag_ETC___d706,
NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d717,
NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d880,
NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d886,
NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d892,
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d392,
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d415,
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d453,
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d669,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d169,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d397,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d412,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d465,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d472,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d475,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d481,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d502,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d508,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d509,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d683,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d689,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d694,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d702,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d711,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d724,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d855,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d861,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d867,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d879,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d884,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d890,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d896,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d897,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d902,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d909,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d914,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d920,
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d925,
NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150,
NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d166,
cfg_verbosity_read__1_ULE_1___d42,
dmem_not_imem_AND_rg_op_13_EQ_0_14_OR_rg_op_13_ETC___d387,
dmem_not_imem_OR_NOT_rg_op_13_EQ_0_14_15_AND_N_ETC___d127,
lrsc_result__h21704,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1007,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1015,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1050,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1060,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981,
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991,
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211,
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205,
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d484,
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d495,
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673,
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d916,
req_f3_BITS_1_TO_0_440_EQ_0b0_441_OR_req_f3_BI_ETC___d1470,
rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b10_20_AND_ETC___d680,
rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b1_88_OR_I_ETC___d344,
rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271,
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d431,
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d468,
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d489,
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d499,
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d503,
rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d497,
rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d720,
rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d850,
rg_op_13_EQ_2_16_AND_rg_amo_funct7_18_BITS_6_T_ETC___d287,
rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144,
rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d157,
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153,
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d352,
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d400,
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422,
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d439,
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d440,
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d458,
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d461,
rg_priv_6_ULE_0b1___d87,
rg_state_1_EQ_13_155_AND_rg_op_13_EQ_0_14_OR_r_ETC___d1157,
tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133,
tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394,
y__h6398;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas ;
// value method addr
assign addr = rg_addr ;
// value method cword
always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
ld_val__h35996 or
MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h38242 or
MUX_dw_valid$wset_1__SEL_2 or
MUX_dw_output_ld_val$wset_1__VAL_3 or
MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_1: cword = ld_val__h35996;
MUX_dw_output_ld_val$wset_1__SEL_2: cword = new_ld_val__h38242;
MUX_dw_valid$wset_1__SEL_2: cword = MUX_dw_output_ld_val$wset_1__VAL_3;
MUX_dw_output_ld_val$wset_1__SEL_4: cword = rg_ld_val;
default: cword = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// value method st_amo_val
assign st_amo_val = MUX_dw_valid$wset_1__SEL_2 ? 64'd0 : rg_st_amo_val ;
// value method exc
assign exc = rg_state == 5'd4 ;
// value method exc_code
assign exc_code = rg_exc_code ;
// action method server_flush_request_put
assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;
// action method server_flush_response_get
assign RDY_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;
// action method tlb_flush
assign RDY_tlb_flush = 1'd1 ;
assign CAN_FIRE_tlb_flush = 1'd1 ;
assign WILL_FIRE_tlb_flush = EN_tlb_flush ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
// value method mem_master_m_awid
assign mem_master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
// value method mem_master_m_awlen
assign mem_master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
// value method mem_master_m_awsize
assign mem_master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
// value method mem_master_m_awburst
assign mem_master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
// value method mem_master_m_awlock
assign mem_master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
// value method mem_master_m_awcache
assign mem_master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
// value method mem_master_m_awprot
assign mem_master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
// value method mem_master_m_awqos
assign mem_master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
// value method mem_master_m_awregion
assign mem_master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
// value method mem_master_m_wdata
assign mem_master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
// value method mem_master_m_wlast
assign mem_master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = master_xactor_f_wr_resp$FULL_N ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
// value method mem_master_m_arid
assign mem_master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;
// value method mem_master_m_araddr
assign mem_master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
// value method mem_master_m_arlen
assign mem_master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
// value method mem_master_m_arsize
assign mem_master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
// value method mem_master_m_arburst
assign mem_master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
// value method mem_master_m_arlock
assign mem_master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
// value method mem_master_m_arcache
assign mem_master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
// value method mem_master_m_arprot
assign mem_master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
// value method mem_master_m_arqos
assign mem_master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
// value method mem_master_m_arregion
assign mem_master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = master_xactor_f_rd_data$FULL_N ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = rg_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = rg_wr_rsp_err ? 8'd1 : 8'd0 ;
// submodule f_fabric_write_reqs
FIFO2 #(.width(32'd131), .guarded(1'd1)) f_fabric_write_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fabric_write_reqs$D_IN),
.ENQ(f_fabric_write_reqs$ENQ),
.DEQ(f_fabric_write_reqs$DEQ),
.CLR(f_fabric_write_reqs$CLR),
.D_OUT(f_fabric_write_reqs$D_OUT),
.FULL_N(f_fabric_write_reqs$FULL_N),
.EMPTY_N(f_fabric_write_reqs$EMPTY_N));
// submodule f_pte_writebacks
FIFO2 #(.width(32'd128), .guarded(1'd1)) f_pte_writebacks(.RST(RST_N),
.CLK(CLK),
.D_IN(f_pte_writebacks$D_IN),
.ENQ(f_pte_writebacks$ENQ),
.DEQ(f_pte_writebacks$DEQ),
.CLR(f_pte_writebacks$CLR),
.D_OUT(f_pte_writebacks$D_OUT),
.FULL_N(f_pte_writebacks$FULL_N),
.EMPTY_N(f_pte_writebacks$EMPTY_N));
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule master_xactor_f_rd_addr
FIFO2 #(.width(32'd97), .guarded(1'd1)) master_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_addr$D_IN),
.ENQ(master_xactor_f_rd_addr$ENQ),
.DEQ(master_xactor_f_rd_addr$DEQ),
.CLR(master_xactor_f_rd_addr$CLR),
.D_OUT(master_xactor_f_rd_addr$D_OUT),
.FULL_N(master_xactor_f_rd_addr$FULL_N),
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
// submodule master_xactor_f_rd_data
FIFO2 #(.width(32'd71), .guarded(1'd1)) master_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_data$D_IN),
.ENQ(master_xactor_f_rd_data$ENQ),
.DEQ(master_xactor_f_rd_data$DEQ),
.CLR(master_xactor_f_rd_data$CLR),
.D_OUT(master_xactor_f_rd_data$D_OUT),
.FULL_N(master_xactor_f_rd_data$FULL_N),
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
// submodule master_xactor_f_wr_addr
FIFO2 #(.width(32'd97), .guarded(1'd1)) master_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_addr$D_IN),
.ENQ(master_xactor_f_wr_addr$ENQ),
.DEQ(master_xactor_f_wr_addr$DEQ),
.CLR(master_xactor_f_wr_addr$CLR),
.D_OUT(master_xactor_f_wr_addr$D_OUT),
.FULL_N(master_xactor_f_wr_addr$FULL_N),
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
// submodule master_xactor_f_wr_data
FIFO2 #(.width(32'd73), .guarded(1'd1)) master_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_data$D_IN),
.ENQ(master_xactor_f_wr_data$ENQ),
.DEQ(master_xactor_f_wr_data$DEQ),
.CLR(master_xactor_f_wr_data$CLR),
.D_OUT(master_xactor_f_wr_data$D_OUT),
.FULL_N(master_xactor_f_wr_data$FULL_N),
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
// submodule master_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(1'd1)) master_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_resp$D_IN),
.ENQ(master_xactor_f_wr_resp$ENQ),
.DEQ(master_xactor_f_wr_resp$DEQ),
.CLR(master_xactor_f_wr_resp$CLR),
.D_OUT(master_xactor_f_wr_resp$D_OUT),
.FULL_N(master_xactor_f_wr_resp$FULL_N),
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
// submodule ram_cword_set
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd128),
.MEMSIZE(10'd512)) ram_cword_set(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_cword_set$ADDRA),
.ADDRB(ram_cword_set$ADDRB),
.DIA(ram_cword_set$DIA),
.DIB(ram_cword_set$DIB),
.WEA(ram_cword_set$WEA),
.WEB(ram_cword_set$WEB),
.ENA(ram_cword_set$ENA),
.ENB(ram_cword_set$ENB),
.DOA(),
.DOB(ram_cword_set$DOB));
// submodule ram_state_and_ctag_cset
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd6),
.DATA_WIDTH(32'd106),
.MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_state_and_ctag_cset$ADDRA),
.ADDRB(ram_state_and_ctag_cset$ADDRB),
.DIA(ram_state_and_ctag_cset$DIA),
.DIB(ram_state_and_ctag_cset$DIB),
.WEA(ram_state_and_ctag_cset$WEA),
.WEB(ram_state_and_ctag_cset$WEB),
.ENA(ram_state_and_ctag_cset$ENA),
.ENB(ram_state_and_ctag_cset$ENB),
.DOA(),
.DOB(ram_state_and_ctag_cset$DOB));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(soc_map$m_is_mem_addr),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// submodule tlb
mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK),
.RST_N(RST_N),
.insert_asid(tlb$insert_asid),
.insert_level(tlb$insert_level),
.insert_pte(tlb$insert_pte),
.insert_pte_pa(tlb$insert_pte_pa),
.insert_vpn(tlb$insert_vpn),
.lookup_asid(tlb$lookup_asid),
.lookup_vpn(tlb$lookup_vpn),
.EN_flush(tlb$EN_flush),
.EN_insert(tlb$EN_insert),
.RDY_flush(),
.lookup(tlb$lookup),
.RDY_lookup(tlb$RDY_lookup),
.RDY_insert(tlb$RDY_insert));
// rule RL_rl_fabric_send_write_req
assign CAN_FIRE_RL_rl_fabric_send_write_req =
ctr_wr_rsps_pending_crg != 4'd15 &&
f_fabric_write_reqs$EMPTY_N &&
master_xactor_f_wr_addr$FULL_N &&
master_xactor_f_wr_data$FULL_N &&
rg_ddr4_ready ;
assign WILL_FIRE_RL_rl_fabric_send_write_req =
CAN_FIRE_RL_rl_fabric_send_write_req ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = WILL_FIRE_RL_rl_reset ;
assign WILL_FIRE_RL_rl_reset =
(rg_cset_in_cache != 6'd63 ||
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
rg_state == 5'd1 ;
// rule RL_rl_probe_and_immed_rsp
assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
(cfg_verbosity_read__1_ULE_1___d42 || tlb$RDY_lookup) &&
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup) &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d352 &&
rg_ddr4_ready &&
rg_state == 5'd3 ;
assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
CAN_FIRE_RL_rl_probe_and_immed_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_start_tlb_refill
assign CAN_FIRE_RL_rl_start_tlb_refill =
master_xactor_f_rd_addr$FULL_N && rg_state == 5'd5 &&
b__h28501 == 4'd0 ;
assign WILL_FIRE_RL_rl_start_tlb_refill =
CAN_FIRE_RL_rl_start_tlb_refill && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_ptw_level_2
assign CAN_FIRE_RL_rl_ptw_level_2 =
master_xactor_f_rd_data$EMPTY_N &&
NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d965 &&
rg_state == 5'd6 ;
assign WILL_FIRE_RL_rl_ptw_level_2 =
CAN_FIRE_RL_rl_ptw_level_2 && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_ptw_level_1
assign CAN_FIRE_RL_rl_ptw_level_1 =
master_xactor_f_rd_data$EMPTY_N &&
NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d1028 &&
rg_state == 5'd7 ;
assign WILL_FIRE_RL_rl_ptw_level_1 =
CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_ptw_level_0
assign CAN_FIRE_RL_rl_ptw_level_0 =
master_xactor_f_rd_data$EMPTY_N &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5] ||
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ||
tlb$RDY_insert) &&
rg_state == 5'd8 ;
assign WILL_FIRE_RL_rl_ptw_level_0 =
CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_start_cache_refill
assign CAN_FIRE_RL_rl_start_cache_refill =
master_xactor_f_rd_addr$FULL_N && rg_state == 5'd9 &&
b__h28501 == 4'd0 ;
assign WILL_FIRE_RL_rl_start_cache_refill =
CAN_FIRE_RL_rl_start_cache_refill &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_cache_refill_rsps_loop
assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd10 ;
assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_rereq
assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ;
assign WILL_FIRE_RL_rl_rereq =
CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;
// rule RL_rl_ST_AMO_response
assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ;
assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;
// rule RL_rl_io_read_req
assign CAN_FIRE_RL_rl_io_read_req =
master_xactor_f_rd_addr$FULL_N &&
rg_state_1_EQ_13_155_AND_rg_op_13_EQ_0_14_OR_r_ETC___d1157 ;
assign WILL_FIRE_RL_rl_io_read_req =
CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_read_rsp
assign CAN_FIRE_RL_rl_io_read_rsp =
master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd14 ;
assign WILL_FIRE_RL_rl_io_read_rsp =
CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_maintain_io_read_rsp
assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ;
assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
CAN_FIRE_RL_rl_maintain_io_read_rsp ;
// rule RL_rl_io_write_req
assign CAN_FIRE_RL_rl_io_write_req =
f_fabric_write_reqs$FULL_N && rg_state == 5'd13 &&
rg_op == 2'd1 ;
assign WILL_FIRE_RL_rl_io_write_req =
CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_SC_req
assign CAN_FIRE_RL_rl_io_AMO_SC_req =
rg_state == 5'd13 && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_SC_req =
CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_op_req
assign CAN_FIRE_RL_rl_io_AMO_op_req =
master_xactor_f_rd_addr$FULL_N && rg_state == 5'd13 &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] != 5'b00010 &&
rg_amo_funct7[6:2] != 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_op_req =
CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_writeback_updated_PTE
assign CAN_FIRE_RL_rl_writeback_updated_PTE =
f_pte_writebacks$EMPTY_N && f_fabric_write_reqs$FULL_N ;
assign WILL_FIRE_RL_rl_writeback_updated_PTE =
CAN_FIRE_RL_rl_writeback_updated_PTE &&
!WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!WILL_FIRE_RL_rl_io_write_req &&
!WILL_FIRE_RL_rl_probe_and_immed_rsp ;
// rule RL_rl_io_AMO_read_rsp
assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
master_xactor_f_rd_data$EMPTY_N &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
f_fabric_write_reqs$FULL_N) &&
rg_state == 5'd16 ;
assign WILL_FIRE_RL_rl_io_AMO_read_rsp =
CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_discard_write_rsp
assign CAN_FIRE_RL_rl_discard_write_rsp =
b__h28501 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_discard_write_rsp =
CAN_FIRE_RL_rl_discard_write_rsp ;
// rule RL_rl_drive_exception_rsp
assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
// rule RL_rl_start_reset
assign CAN_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_3 ;
assign WILL_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_dw_output_ld_val$wset_1__SEL_1 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_4 =
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign MUX_dw_valid$wset_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d509 ;
assign MUX_f_fabric_write_reqs$enq_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d855 ;
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
!master_xactor_f_rd_data$D_OUT[5] &&
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ;
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_2 =
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
!master_xactor_f_rd_data$D_OUT[5] &&
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ;
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_3 =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
assign MUX_ram_cword_set$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_ram_cword_set$b_put_1__SEL_2 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] != 3'd7 ;
assign MUX_ram_cword_set$b_put_2__SEL_1 =
EN_req &&
req_f3_BITS_1_TO_0_440_EQ_0b0_441_OR_req_f3_BI_ETC___d1470 ;
assign MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_rg_error_during_refill$write_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_1 =
EN_req &&
NOT_req_f3_BITS_1_TO_0_440_EQ_0b0_441_442_AND__ETC___d1461 ;
assign MUX_rg_exc_code$write_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_3 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_5 =
WILL_FIRE_RL_rl_ptw_level_0 &&
(!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5] ||
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ||
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) ;
assign MUX_rg_exc_code$write_1__SEL_6 =
WILL_FIRE_RL_rl_ptw_level_1 &&
NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d1034 ;
assign MUX_rg_exc_code$write_1__SEL_7 =
WILL_FIRE_RL_rl_ptw_level_2 &&
NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d972 ;
assign MUX_rg_exc_code$write_1__SEL_8 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ;
assign MUX_rg_ld_val$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d711 ;
assign MUX_rg_lrsc_valid$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d502 ;
assign MUX_rg_state$write_1__SEL_3 =
f_reset_reqs$EMPTY_N && rg_state != 5'd1 ;
assign MUX_rg_state$write_1__SEL_11 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd7 ;
assign MUX_rg_state$write_1__SEL_17 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d440 ;
assign MUX_rg_state$write_1__SEL_18 =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign MUX_tlb$insert_1__SEL_1 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 ;
assign MUX_tlb$insert_1__SEL_2 =
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1015 ;
assign MUX_tlb$insert_1__SEL_3 =
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1050 ;
assign MUX_tlb$insert_1__SEL_4 =
WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) ;
assign MUX_dw_output_ld_val$wset_1__VAL_3 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
new_value__h7718 :
new_value__h24131 ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_1 = { rg_f3, rg_pa, x__h38265 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_2 =
{ rg_f3,
x1_avValue_pa__h6062,
IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d856 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_3 =
{ 3'b011, f_pte_writebacks$D_OUT } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_4 =
{ rg_f3, rg_pa, rg_st_amo_val } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
{ 4'd0, lev_1_pte_pa_w64_fa__h29532, 29'd851968 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
{ 4'd0, lev_0_pte_pa_w64_fa__h30625, 29'd851968 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_3 =
{ 4'd0, rg_pa, 8'd0, value__h37822, 18'd65536 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_4 =
{ 4'd0, lev_2_pte_pa_w64_fa__h28598, 29'd851968 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_5 =
{ 4'd0, cline_fabric_addr__h31880, 29'd15532032 } ;
assign MUX_ram_cword_set$a_put_3__VAL_1 =
rg_victim_way ?
{ master_xactor_f_rd_data$D_OUT[66:3],
ram_cword_set$DOB[63:0] } :
{ ram_cword_set$DOB[127:64],
master_xactor_f_rd_data$D_OUT[66:3] } ;
assign MUX_ram_cword_set$a_put_3__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
{ IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d778,
IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d779 } :
{ IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d846,
IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d847 } ;
assign MUX_ram_cword_set$b_put_2__VAL_2 = rg_cset_cword_in_cache + 9'd1 ;
assign MUX_ram_cword_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ;
assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 =
{ rg_victim_way || ram_state_and_ctag_cset$DOB[105],
rg_victim_way ?
rg_pa[63:12] :
ram_state_and_ctag_cset$DOB[104:53],
!rg_victim_way || ram_state_and_ctag_cset$DOB[52],
rg_victim_way ?
ram_state_and_ctag_cset$DOB[51:0] :
rg_pa[63:12] } ;
assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ;
assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
assign MUX_rg_exc_code$write_1__VAL_5 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
exc_code___1__h6472 :
access_exc_code__h2635 ;
assign MUX_rg_ld_val$write_1__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
x__h21714 :
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 ;
assign MUX_rg_state$write_1__VAL_2 =
NOT_req_f3_BITS_1_TO_0_440_EQ_0b0_441_442_AND__ETC___d1461 ?
5'd4 :
5'd3 ;
assign MUX_rg_state$write_1__VAL_4 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ? 5'd15 : 5'd4 ;
assign MUX_rg_state$write_1__VAL_11 =
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) ?
5'd4 :
5'd11 ;
assign MUX_rg_state$write_1__VAL_13 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
((!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5] ||
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4]) ?
5'd4 :
5'd11) :
5'd4 ;
assign MUX_rg_state$write_1__VAL_14 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
((!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5]) ?
5'd4 :
((!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4]) ?
5'd8 :
((master_xactor_f_rd_data$D_OUT[21:13] == 9'd0) ?
5'd11 :
5'd4))) :
5'd4 ;
assign MUX_rg_state$write_1__VAL_15 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
((!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5]) ?
5'd4 :
((!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4]) ?
5'd7 :
((master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) ?
5'd4 :
5'd11))) :
5'd4 ;
assign MUX_rg_state$write_1__VAL_17 =
(rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
!tlb$lookup[130]) ?
5'd5 :
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d445 ;
// inlined wires
assign dw_valid$whas =
(WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_read_rsp) &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d509 ||
WILL_FIRE_RL_rl_drive_exception_rsp ||
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign ctr_wr_rsps_pending_crg$port0__write_1 =
ctr_wr_rsps_pending_crg + 4'd1 ;
assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h28501 - 4'd1 ;
assign ctr_wr_rsps_pending_crg$port2__read =
CAN_FIRE_RL_rl_discard_write_rsp ?
ctr_wr_rsps_pending_crg$port1__write_1 :
b__h28501 ;
assign ctr_wr_rsps_pending_crg$EN_port2__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign ctr_wr_rsps_pending_crg$port3__read =
ctr_wr_rsps_pending_crg$EN_port2__write ?
4'd0 :
ctr_wr_rsps_pending_crg$port2__read ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register ctr_wr_rsps_pending_crg
assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register rg_addr
assign rg_addr$D_IN = req_addr ;
assign rg_addr$EN = EN_req ;
// register rg_amo_funct7
assign rg_amo_funct7$D_IN = req_amo_funct7 ;
assign rg_amo_funct7$EN = EN_req ;
// register rg_cset_cword_in_cache
assign rg_cset_cword_in_cache$D_IN =
MUX_ram_cword_set$b_put_1__SEL_2 ?
MUX_ram_cword_set$b_put_2__VAL_2 :
MUX_ram_cword_set$b_put_2__VAL_4 ;
assign rg_cset_cword_in_cache$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] != 3'd7 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_cset_in_cache
assign rg_cset_in_cache$D_IN =
WILL_FIRE_RL_rl_reset ?
MUX_rg_cset_in_cache$write_1__VAL_1 :
6'd0 ;
assign rg_cset_in_cache$EN =
WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;
// register rg_ddr4_ready
assign rg_ddr4_ready$D_IN = 1'd1 ;
assign rg_ddr4_ready$EN = EN_ma_ddr4_ready ;
// register rg_error_during_refill
assign rg_error_during_refill$D_IN =
MUX_rg_error_during_refill$write_1__SEL_1 ;
assign rg_error_during_refill$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_exc_code
always@(MUX_rg_exc_code$write_1__SEL_1 or
MUX_rg_exc_code$write_1__VAL_1 or
MUX_rg_exc_code$write_1__SEL_2 or
MUX_rg_exc_code$write_1__SEL_3 or
MUX_rg_error_during_refill$write_1__SEL_1 or
access_exc_code__h2635 or
MUX_rg_exc_code$write_1__SEL_5 or
MUX_rg_exc_code$write_1__VAL_5 or
MUX_rg_exc_code$write_1__SEL_6 or
MUX_rg_exc_code$write_1__SEL_7 or
MUX_rg_exc_code$write_1__SEL_8 or x1_avValue_exc_code__h6063)
case (1'b1)
MUX_rg_exc_code$write_1__SEL_1:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
MUX_rg_error_during_refill$write_1__SEL_1:
rg_exc_code$D_IN = access_exc_code__h2635;
MUX_rg_exc_code$write_1__SEL_5:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
MUX_rg_exc_code$write_1__SEL_6:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
MUX_rg_exc_code$write_1__SEL_7:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
MUX_rg_exc_code$write_1__SEL_8:
rg_exc_code$D_IN = x1_avValue_exc_code__h6063;
default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign rg_exc_code$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
EN_req &&
NOT_req_f3_BITS_1_TO_0_440_EQ_0b0_441_442_AND__ETC___d1461 ||
WILL_FIRE_RL_rl_ptw_level_2 &&
NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d972 ||
WILL_FIRE_RL_rl_ptw_level_1 &&
NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d1034 ||
WILL_FIRE_RL_rl_ptw_level_0 &&
(!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5] ||
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ||
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) ;
// register rg_f3
assign rg_f3$D_IN = req_f3 ;
assign rg_f3$EN = EN_req ;
// register rg_ld_val
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h38242 or
MUX_rg_ld_val$write_1__SEL_2 or
MUX_rg_ld_val$write_1__VAL_2 or
WILL_FIRE_RL_rl_io_read_rsp or
ld_val__h35996 or WILL_FIRE_RL_rl_io_AMO_SC_req)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h38242;
MUX_rg_ld_val$write_1__SEL_2:
rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h35996;
WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_ld_val$EN =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d711 ||
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_SC_req ;
// register rg_lower_word32
assign rg_lower_word32$D_IN = 32'h0 ;
assign rg_lower_word32$EN = 1'b0 ;
// register rg_lower_word32_full
assign rg_lower_word32_full$D_IN = 1'd0 ;
assign rg_lower_word32_full$EN =
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_lrsc_pa
assign rg_lrsc_pa$D_IN = soc_map$m_is_mem_addr_addr ;
assign rg_lrsc_pa$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d683 ;
// register rg_lrsc_valid
assign rg_lrsc_valid$D_IN =
MUX_rg_lrsc_valid$write_1__SEL_2 &&
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d503 ;
assign rg_lrsc_valid$EN =
WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d502 ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_mstatus_MXR
assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ;
assign rg_mstatus_MXR$EN = EN_req ;
// register rg_op
assign rg_op$D_IN = req_op ;
assign rg_op$EN = EN_req ;
// register rg_pa
assign rg_pa$D_IN = EN_req ? req_addr : soc_map$m_is_mem_addr_addr ;
assign rg_pa$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d465 ||
EN_req ;
// register rg_priv
assign rg_priv$D_IN = req_priv ;
assign rg_priv$EN = EN_req ;
// register rg_pte_pa
always@(MUX_master_xactor_f_rd_addr$enq_1__SEL_1 or
lev_1_pte_pa__h29530 or
MUX_master_xactor_f_rd_addr$enq_1__SEL_2 or
lev_0_pte_pa__h30623 or
WILL_FIRE_RL_rl_start_tlb_refill or lev_2_pte_pa__h28596)
begin
case (1'b1) // synopsys parallel_case
MUX_master_xactor_f_rd_addr$enq_1__SEL_1:
rg_pte_pa$D_IN = lev_1_pte_pa__h29530;
MUX_master_xactor_f_rd_addr$enq_1__SEL_2:
rg_pte_pa$D_IN = lev_0_pte_pa__h30623;
WILL_FIRE_RL_rl_start_tlb_refill: rg_pte_pa$D_IN = lev_2_pte_pa__h28596;
default: rg_pte_pa$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_pte_pa$EN =
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
!master_xactor_f_rd_data$D_OUT[5] &&
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ||
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
!master_xactor_f_rd_data$D_OUT[5] &&
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ||
WILL_FIRE_RL_rl_start_tlb_refill ;
// register rg_satp
assign rg_satp$D_IN = req_satp ;
assign rg_satp$EN = EN_req ;
// register rg_sstatus_SUM
assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ;
assign rg_sstatus_SUM$EN = EN_req ;
// register rg_st_amo_val
assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h25251 ;
assign rg_st_amo_val$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d925 ||
EN_req ;
// register rg_state
always@(EN_tlb_flush or
EN_req or
MUX_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_rl_start_reset or
WILL_FIRE_RL_rl_io_AMO_read_rsp or
MUX_rg_state$write_1__VAL_4 or
WILL_FIRE_RL_rl_io_AMO_op_req or
WILL_FIRE_RL_rl_io_AMO_SC_req or
WILL_FIRE_RL_rl_io_write_req or
WILL_FIRE_RL_rl_io_read_rsp or
WILL_FIRE_RL_rl_io_read_req or
WILL_FIRE_RL_rl_rereq or
MUX_rg_state$write_1__SEL_11 or
MUX_rg_state$write_1__VAL_11 or
WILL_FIRE_RL_rl_start_cache_refill or
WILL_FIRE_RL_rl_ptw_level_0 or
MUX_rg_state$write_1__VAL_13 or
WILL_FIRE_RL_rl_ptw_level_1 or
MUX_rg_state$write_1__VAL_14 or
WILL_FIRE_RL_rl_ptw_level_2 or
MUX_rg_state$write_1__VAL_15 or
WILL_FIRE_RL_rl_start_tlb_refill or
MUX_rg_state$write_1__SEL_17 or
MUX_rg_state$write_1__VAL_17 or MUX_rg_state$write_1__SEL_18)
case (1'b1)
EN_tlb_flush: rg_state$D_IN = 5'd2;
EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1;
WILL_FIRE_RL_rl_io_AMO_read_rsp:
rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16;
WILL_FIRE_RL_rl_io_AMO_SC_req || WILL_FIRE_RL_rl_io_write_req:
rg_state$D_IN = 5'd12;
WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14;
WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3;
MUX_rg_state$write_1__SEL_11:
rg_state$D_IN = MUX_rg_state$write_1__VAL_11;
WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10;
WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_13;
WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_14;
WILL_FIRE_RL_rl_ptw_level_2: rg_state$D_IN = MUX_rg_state$write_1__VAL_15;
WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 5'd6;
MUX_rg_state$write_1__SEL_17:
rg_state$D_IN = MUX_rg_state$write_1__VAL_17;
MUX_rg_state$write_1__SEL_18: rg_state$D_IN = 5'd2;
default: rg_state$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign rg_state$EN =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd7 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d440 ||
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_ptw_level_2 ||
WILL_FIRE_RL_rl_ptw_level_1 ||
WILL_FIRE_RL_rl_ptw_level_0 ||
EN_req ||
WILL_FIRE_RL_rl_start_reset ||
EN_tlb_flush ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_tlb_refill ||
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_io_AMO_SC_req ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_io_AMO_op_req ;
// register rg_tohost_addr
assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ;
assign rg_tohost_addr$EN = EN_set_watch_tohost ;
// register rg_tohost_value
assign rg_tohost_value$D_IN = rg_st_amo_val ;
assign rg_tohost_value$EN =
WILL_FIRE_RL_rl_ST_AMO_response && rg_watch_tohost &&
rg_pa == rg_tohost_addr &&
rg_st_amo_val != 64'd0 ;
// register rg_victim_way
assign rg_victim_way$D_IN = tmp__h32017[0] ;
assign rg_victim_way$EN = WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_watch_tohost
assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ;
assign rg_watch_tohost$EN = EN_set_watch_tohost ;
// register rg_wr_rsp_err
assign rg_wr_rsp_err$D_IN = 1'd1 ;
assign rg_wr_rsp_err$EN =
WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ;
// submodule f_fabric_write_reqs
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_1 or
MUX_f_fabric_write_reqs$enq_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_2 or
WILL_FIRE_RL_rl_writeback_updated_PTE or
MUX_f_fabric_write_reqs$enq_1__VAL_3 or
WILL_FIRE_RL_rl_io_write_req or
MUX_f_fabric_write_reqs$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_1;
MUX_f_fabric_write_reqs$enq_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_2;
WILL_FIRE_RL_rl_writeback_updated_PTE:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_3;
WILL_FIRE_RL_rl_io_write_req:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_4;
default: f_fabric_write_reqs$D_IN =
131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_fabric_write_reqs$ENQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d855 ||
WILL_FIRE_RL_rl_writeback_updated_PTE ||
WILL_FIRE_RL_rl_io_write_req ;
assign f_fabric_write_reqs$DEQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign f_fabric_write_reqs$CLR = 1'b0 ;
// submodule f_pte_writebacks
assign f_pte_writebacks$D_IN = { tlb$lookup[63:0], value__h6897 } ;
assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ;
assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ;
assign f_pte_writebacks$CLR = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
assign f_reset_reqs$ENQ =
EN_server_reset_request_put || EN_server_flush_request_put ;
assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_18 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
assign f_reset_rsps$ENQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign f_reset_rsps$DEQ =
EN_server_flush_response_get || EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule master_xactor_f_rd_addr
always@(MUX_master_xactor_f_rd_addr$enq_1__SEL_1 or
MUX_master_xactor_f_rd_addr$enq_1__VAL_1 or
MUX_master_xactor_f_rd_addr$enq_1__SEL_2 or
MUX_master_xactor_f_rd_addr$enq_1__VAL_2 or
MUX_master_xactor_f_rd_addr$enq_1__SEL_3 or
MUX_master_xactor_f_rd_addr$enq_1__VAL_3 or
WILL_FIRE_RL_rl_start_tlb_refill or
MUX_master_xactor_f_rd_addr$enq_1__VAL_4 or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_master_xactor_f_rd_addr$enq_1__VAL_5)
begin
case (1'b1) // synopsys parallel_case
MUX_master_xactor_f_rd_addr$enq_1__SEL_1:
master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__VAL_1;
MUX_master_xactor_f_rd_addr$enq_1__SEL_2:
master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
MUX_master_xactor_f_rd_addr$enq_1__SEL_3:
master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__VAL_3;
WILL_FIRE_RL_rl_start_tlb_refill:
master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__VAL_4;
WILL_FIRE_RL_rl_start_cache_refill:
master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__VAL_5;
default: master_xactor_f_rd_addr$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign master_xactor_f_rd_addr$ENQ =
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
!master_xactor_f_rd_data$D_OUT[5] &&
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ||
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
!master_xactor_f_rd_data$D_OUT[5] &&
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] ||
WILL_FIRE_RL_rl_io_AMO_op_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_start_tlb_refill ||
WILL_FIRE_RL_rl_start_cache_refill ;
assign master_xactor_f_rd_addr$DEQ =
master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
assign master_xactor_f_rd_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_rd_data
assign master_xactor_f_rd_data$D_IN =
{ mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast } ;
assign master_xactor_f_rd_data$ENQ =
mem_master_rvalid && master_xactor_f_rd_data$FULL_N ;
assign master_xactor_f_rd_data$DEQ =
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop ||
WILL_FIRE_RL_rl_ptw_level_0 ||
WILL_FIRE_RL_rl_ptw_level_1 ||
WILL_FIRE_RL_rl_ptw_level_2 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp ;
assign master_xactor_f_rd_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_addr
assign master_xactor_f_wr_addr$D_IN =
{ 4'd0,
f_fabric_write_reqs$D_OUT[127:64],
8'd0,
x__h2890,
18'd65536 } ;
assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_addr$DEQ =
master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
assign master_xactor_f_wr_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_data
assign master_xactor_f_wr_data$D_IN =
{ mem_req_wr_data_wdata__h3063,
mem_req_wr_data_wstrb__h3064,
1'd1 } ;
assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_data$DEQ =
master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
assign master_xactor_f_wr_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_resp
assign master_xactor_f_wr_resp$D_IN = { mem_master_bid, mem_master_bresp } ;
assign master_xactor_f_wr_resp$ENQ =
mem_master_bvalid && master_xactor_f_wr_resp$FULL_N ;
assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_discard_write_rsp ;
assign master_xactor_f_wr_resp$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule ram_cword_set
assign ram_cword_set$ADDRA =
MUX_ram_cword_set$a_put_1__SEL_1 ?
rg_cset_cword_in_cache :
rg_addr[11:3] ;
always@(MUX_ram_cword_set$b_put_2__SEL_1 or
req_addr or
MUX_ram_cword_set$b_put_1__SEL_2 or
MUX_ram_cword_set$b_put_2__VAL_2 or
WILL_FIRE_RL_rl_rereq or
rg_addr or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_ram_cword_set$b_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_cword_set$b_put_2__SEL_1: ram_cword_set$ADDRB = req_addr[11:3];
MUX_ram_cword_set$b_put_1__SEL_2:
ram_cword_set$ADDRB = MUX_ram_cword_set$b_put_2__VAL_2;
WILL_FIRE_RL_rl_rereq: ram_cword_set$ADDRB = rg_addr[11:3];
WILL_FIRE_RL_rl_start_cache_refill:
ram_cword_set$ADDRB = MUX_ram_cword_set$b_put_2__VAL_4;
default: ram_cword_set$ADDRB = 9'b010101010 /* unspecified value */ ;
endcase
end
assign ram_cword_set$DIA =
MUX_ram_cword_set$a_put_1__SEL_1 ?
MUX_ram_cword_set$a_put_3__VAL_1 :
MUX_ram_cword_set$a_put_3__VAL_2 ;
always@(MUX_ram_cword_set$b_put_2__SEL_1 or
MUX_ram_cword_set$b_put_1__SEL_2 or
WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_cword_set$b_put_2__SEL_1:
ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
MUX_ram_cword_set$b_put_1__SEL_2:
ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_rereq:
ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_start_cache_refill:
ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
default: ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign ram_cword_set$WEA = 1'd1 ;
assign ram_cword_set$WEB = 1'd0 ;
assign ram_cword_set$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d724 ;
assign ram_cword_set$ENB =
EN_req &&
req_f3_BITS_1_TO_0_440_EQ_0b0_441_OR_req_f3_BI_ETC___d1470 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] != 3'd7 ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule ram_state_and_ctag_cset
assign ram_state_and_ctag_cset$ADDRA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
rg_addr[11:6] :
rg_cset_in_cache ;
assign ram_state_and_ctag_cset$ADDRB =
MUX_ram_cword_set$b_put_2__SEL_1 ?
req_addr[11:6] :
rg_addr[11:6] ;
assign ram_state_and_ctag_cset$DIA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
106'h15555555555554AAAAAAAAAAAAA ;
assign ram_state_and_ctag_cset$DIB =
MUX_ram_cword_set$b_put_2__SEL_1 ?
106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign ram_state_and_ctag_cset$WEA = 1'd1 ;
assign ram_state_and_ctag_cset$WEB = 1'd0 ;
assign ram_state_and_ctag_cset$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_reset ;
assign ram_state_and_ctag_cset$ENB =
EN_req &&
req_f3_BITS_1_TO_0_440_EQ_0b0_441_OR_req_f3_BI_ETC___d1470 ||
WILL_FIRE_RL_rl_rereq ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr =
(rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8) ?
_theResult___fst__h6160 :
rg_addr ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// submodule tlb
assign tlb$insert_asid = rg_satp[59:44] ;
always@(MUX_tlb$insert_1__SEL_1 or
tlb$lookup or
MUX_tlb$insert_1__SEL_2 or
MUX_tlb$insert_1__SEL_3 or MUX_tlb$insert_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[65:64];
MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd2;
MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd1;
MUX_tlb$insert_1__SEL_4: tlb$insert_level = 2'd0;
default: tlb$insert_level = 2'b10 /* unspecified value */ ;
endcase
end
assign tlb$insert_pte =
(MUX_tlb$insert_1__SEL_2 || MUX_tlb$insert_1__SEL_3 ||
MUX_tlb$insert_1__SEL_4) ?
master_xactor_f_rd_data$D_OUT[66:3] :
value__h6897 ;
assign tlb$insert_pte_pa =
MUX_tlb$insert_1__SEL_1 ? tlb$lookup[63:0] : rg_pte_pa ;
assign tlb$insert_vpn = rg_addr[38:12] ;
assign tlb$lookup_asid = rg_satp[59:44] ;
assign tlb$lookup_vpn = rg_addr[38:12] ;
assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ;
assign tlb$EN_insert =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 ||
WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1015 ||
WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1050 ||
WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) ;
// remaining internal signals
assign IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d334 =
(x1_avValue_pa__h6062[2:0] == 3'h0) ?
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 :
NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d333 ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d441 =
((!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211)) ?
5'd9 :
5'd12 ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d779 =
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ?
n__h22516 :
ram_cword_set$DOB[63:0] ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d847 =
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ?
n__h25409 :
ram_cword_set$DOB[63:0] ;
assign IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d778 =
(ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ?
n__h22516 :
ram_cword_set$DOB[127:64] ;
assign IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d846 =
(ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ?
n__h25409 :
ram_cword_set$DOB[127:64] ;
assign IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_1_E_ETC___d662 =
(rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
assign IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1355 =
(rg_addr[2:0] == 3'h0) ? ld_val__h35996 : 64'd0 ;
assign IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_NOT_ETC___d255 =
(rg_addr[2:0] == 3'h0) ?
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 :
rg_addr[2:0] != 3'h4 ||
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 ;
assign IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647 =
(rg_addr[2:0] == 3'h0) ? word64__h7596 : 64'd0 ;
assign IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32 =
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654[31:0] ;
assign IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 =
(rg_f3 == 3'b010) ?
{ {32{rg_st_amo_val_BITS_31_TO_0__q33[31]}},
rg_st_amo_val_BITS_31_TO_0__q33 } :
rg_st_amo_val ;
assign IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d348 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d265 :
IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d347 ;
assign IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d443 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
5'd9 :
IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d442 ;
assign IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d347 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_op_13_EQ_2_16_AND_rg_amo_funct7_18_BITS_6_T_ETC___d287 :
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d346 ;
assign IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d442 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
5'd12 :
IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d441 ;
assign IF_rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d856 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_st_amo_val :
new_st_val__h25251 ;
assign IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d445 =
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ?
5'd4 :
((dmem_not_imem && !soc_map$m_is_mem_addr) ?
5'd13 :
IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d443) ;
assign IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 =
x1_avValue_pa__h6062 == rg_lrsc_pa ;
assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d323 =
x1_avValue_pa__h6062[2:0] != 3'h7 ||
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 ;
assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d329 =
x1_avValue_pa__h6062[2:0] != 3'h6 ||
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 ;
assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d333 =
x1_avValue_pa__h6062[2:0] != 3'h4 ||
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 ;
assign NOT_cfg_verbosity_read__1_ULE_2_106___d1107 = cfg_verbosity > 4'd2 ;
assign NOT_cfg_verbosity_read__1_ULT_2_49___d450 = cfg_verbosity >= 4'd2 ;
assign NOT_dmem_not_imem_28_AND_rg_op_13_EQ_0_14_OR_r_ETC___d385 =
!dmem_not_imem &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
tlb$lookup[69] ;
assign NOT_dmem_not_imem_28_OR_NOT_rg_op_13_EQ_0_14_1_ETC___d135 =
!dmem_not_imem ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
!tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d479 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 &&
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d675 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d687 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d692 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d700 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d697 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d709 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
NOT_rg_op_13_EQ_1_66_93_AND_ram_state_and_ctag_ETC___d706) ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d722 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d720 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d859 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d877 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d923 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719 ;
assign NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d1028 =
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5] ||
((!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4]) ?
master_xactor_f_rd_addr$FULL_N :
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
tlb$RDY_insert) ;
assign NOT_master_xactor_f_rd_data_first__41_BITS_2_T_ETC___d965 =
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5] ||
((!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4]) ?
master_xactor_f_rd_addr$FULL_N :
master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
tlb$RDY_insert) ;
assign NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d1034 =
!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5] ||
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign NOT_master_xactor_f_rd_data_first__41_BIT_3_45_ETC___d972 =
!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5] ||
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
(master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) ||
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 =
!ram_state_and_ctag_cset$DOB[105] || !rg_priv_6_ULE_0b1___d87 ||
rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup ;
assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 =
!ram_state_and_ctag_cset$DOB[52] || !rg_priv_6_ULE_0b1___d87 ||
rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup ;
assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d265 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 ;
assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d285 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ||
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ||
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279) &&
(ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ||
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279) ;
assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d346 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ||
f_fabric_write_reqs$FULL_N &&
rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b1_88_OR_I_ETC___d344 ;
assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d487 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 ;
assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d697 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_req_f3_BITS_1_TO_0_440_EQ_0b0_441_442_AND__ETC___d1461 =
req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
(req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
(req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
assign NOT_rg_op_13_EQ_0_14_15_AND_NOT_rg_op_13_EQ_2__ETC___d436 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) ;
assign NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
assign NOT_rg_op_13_EQ_1_66_93_AND_ram_state_and_ctag_ETC___d706 =
rg_op != 2'd1 &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
assign NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d717 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
assign NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d880 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) &&
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 ;
assign NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d886 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690 ;
assign NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d892 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d392 =
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
(NOT_dmem_not_imem_28_AND_rg_op_13_EQ_0_14_OR_r_ETC___d385 ||
dmem_not_imem_AND_rg_op_13_EQ_0_14_OR_rg_op_13_ETC___d387 ||
dmem_not_imem && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
tlb$lookup[68]) ;
assign NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d415 =
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
dmem_not_imem &&
tlb$lookup[68] ;
assign NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d453 =
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
tlb$lookup[72] &&
!pte___2__h6572[7] &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
assign NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d669 =
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
(!dmem_not_imem && tlb$lookup[69] ||
dmem_not_imem &&
tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133) ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d169 =
!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d157 ||
NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d166 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350 =
(NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d169 ||
tlb$RDY_insert && tlb$RDY_lookup && f_pte_writebacks$FULL_N) &&
(dmem_not_imem && !soc_map$m_is_mem_addr ||
IF_rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_ETC___d348) ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d397 =
!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130] &&
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d392 &&
tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d412 =
!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d157 ||
NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d166 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 =
!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d392 &&
tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d465 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d472 =
!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
(rg_priv != 2'b0 || tlb$lookup[70]) &&
(rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d468 &&
tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d475 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d472 &&
dmem_not_imem &&
!soc_map$m_is_mem_addr &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d481 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d479 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d502 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d499 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d508 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d464 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d503 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h21704) ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d509 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d508 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 =
!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d669 &&
tlb$lookup[72] ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d675 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d683 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b10_20_AND_ETC___d680 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d689 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d687 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d694 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d692 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d702 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d672 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d700 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 =
!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
!tlb$lookup[130] ||
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d415 &&
tlb$lookup[72] &&
tlb$lookup[73] ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d711 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d709 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d724 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d722 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d850 ||
NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719) ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d855 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d861 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d859 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d867 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
rg_lrsc_valid &&
!rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
!rg_lrsc_valid &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d879 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d877 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d884 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d880 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d884 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d890 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d886 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d896 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d892 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d897 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d896 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d902 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h21704 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d902 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d909 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d690 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d914 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d914 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d920 =
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d916 ;
assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d925 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d705 &&
NOT_dmem_not_imem_28_OR_soc_map_m_is_mem_addr__ETC___d923 ;
assign NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150 =
!tlb$lookup[72] ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
!tlb$lookup[73] ;
assign NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d166 =
!tlb$lookup[72] || !tlb$lookup[73] || pte___2__h6572[7] ||
rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ;
assign _theResult___fst__h6160 =
tlb$lookup[130] ? _theResult___fst__h6231 : rg_addr ;
assign _theResult___fst__h6231 =
(rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 ||
NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150) ?
rg_addr :
_theResult___fst__h6574 ;
assign _theResult___snd_fst__h3071 =
f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h2857 ;
assign _theResult___snd_fst__h6162 =
tlb$lookup[130] ?
_theResult___snd_fst__h6233 :
tlb$lookup[129:66] ;
assign _theResult___snd_fst__h6233 =
(rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 ||
NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150) ?
tlb$lookup[129:66] :
_theResult___snd_fst__h6803 ;
assign _theResult___snd_fst__h6803 =
(!pte___2__h6572[7] && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ?
pte___1__h6880 :
pte___2__h6572 ;
assign access_exc_code__h2635 =
dmem_not_imem ?
((rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd5 :
4'd7) :
4'd1 ;
assign b__h28501 =
CAN_FIRE_RL_rl_fabric_send_write_req ?
ctr_wr_rsps_pending_crg$port0__write_1 :
ctr_wr_rsps_pending_crg ;
assign cfg_verbosity_read__1_ULE_1___d42 = cfg_verbosity <= 4'd1 ;
assign cline_fabric_addr__h31880 = { rg_pa[63:6], 6'd0 } ;
assign dmem_not_imem_AND_rg_op_13_EQ_0_14_OR_rg_op_13_ETC___d387 =
dmem_not_imem &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133 ;
assign dmem_not_imem_OR_NOT_rg_op_13_EQ_0_14_15_AND_N_ETC___d127 =
dmem_not_imem ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
!tlb$lookup[69] ;
assign exc_code___1__h6472 = x1_avValue_exc_code__h6063 ;
assign ld_val5996_BITS_15_TO_0__q38 = ld_val__h35996[15:0] ;
assign ld_val5996_BITS_15_TO_8__q40 = ld_val__h35996[15:8] ;
assign ld_val5996_BITS_23_TO_16__q41 = ld_val__h35996[23:16] ;
assign ld_val5996_BITS_31_TO_0__q39 = ld_val__h35996[31:0] ;
assign ld_val5996_BITS_31_TO_16__q42 = ld_val__h35996[31:16] ;
assign ld_val5996_BITS_31_TO_24__q43 = ld_val__h35996[31:24] ;
assign ld_val5996_BITS_39_TO_32__q44 = ld_val__h35996[39:32] ;
assign ld_val5996_BITS_47_TO_32__q45 = ld_val__h35996[47:32] ;
assign ld_val5996_BITS_47_TO_40__q47 = ld_val__h35996[47:40] ;
assign ld_val5996_BITS_55_TO_48__q48 = ld_val__h35996[55:48] ;
assign ld_val5996_BITS_63_TO_32__q46 = ld_val__h35996[63:32] ;
assign ld_val5996_BITS_63_TO_48__q49 = ld_val__h35996[63:48] ;
assign ld_val5996_BITS_63_TO_56__q50 = ld_val__h35996[63:56] ;
assign ld_val5996_BITS_7_TO_0__q37 = ld_val__h35996[7:0] ;
assign lev_0_pte_pa__h30623 = lev_1_PTN_pa__h29528 + vpn_0_pa__h30622 ;
assign lev_0_pte_pa_w64_fa__h30625 = { lev_0_pte_pa__h30623[63:3], 3'b0 } ;
assign lev_1_PTN_pa__h29528 = { 8'd0, x__h29603 } ;
assign lev_1_pte_pa__h29530 = lev_1_PTN_pa__h29528 + vpn_1_pa__h29529 ;
assign lev_1_pte_pa_w64_fa__h29532 = { lev_1_pte_pa__h29530[63:3], 3'b0 } ;
assign lev_2_pte_pa__h28596 = satp_pa__h1890 + vpn_2_pa__h28595 ;
assign lev_2_pte_pa_w64_fa__h28598 = { lev_2_pte_pa__h28596[63:3], 3'b0 } ;
assign lrsc_result__h21704 =
!rg_lrsc_valid ||
!rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271 ;
assign master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 =
master_xactor_f_rd_data$D_OUT[10:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 =
master_xactor_f_rd_data$D_OUT[18:11] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 =
master_xactor_f_rd_data$D_OUT[18:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 =
master_xactor_f_rd_data$D_OUT[26:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6 =
master_xactor_f_rd_data$D_OUT[34:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7 =
master_xactor_f_rd_data$D_OUT[34:27] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 =
master_xactor_f_rd_data$D_OUT[34:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 =
master_xactor_f_rd_data$D_OUT[42:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 =
master_xactor_f_rd_data$D_OUT[50:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 =
master_xactor_f_rd_data$D_OUT[50:43] ;
assign master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 =
master_xactor_f_rd_data$D_OUT[58:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 =
master_xactor_f_rd_data$D_OUT[66:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 =
master_xactor_f_rd_data$D_OUT[66:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 =
master_xactor_f_rd_data$D_OUT[66:59] ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1007 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
(master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1015 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
master_xactor_f_rd_data$D_OUT[30:22] == 9'd0 &&
master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
master_xactor_f_rd_data$D_OUT[30:22] == 9'd0 &&
master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1050 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1060 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
(!master_xactor_f_rd_data$D_OUT[3] ||
!master_xactor_f_rd_data$D_OUT[4] &&
master_xactor_f_rd_data$D_OUT[5]) &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991 =
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
!master_xactor_f_rd_data$D_OUT[5] &&
!master_xactor_f_rd_data$D_OUT[6] &&
!master_xactor_f_rd_data$D_OUT[4] &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign new_st_val__h25251 =
(rg_f3 == 3'b010) ?
new_st_val__h25551 :
_theResult_____2__h25547 ;
assign new_st_val__h25551 = { 32'd0, _theResult_____2__h25547[31:0] } ;
assign new_st_val__h25642 =
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 +
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ;
assign new_st_val__h26622 = w1__h25539 ^ w2__h38276 ;
assign new_st_val__h26626 = w1__h25539 & w2__h38276 ;
assign new_st_val__h26630 = w1__h25539 | w2__h38276 ;
assign new_st_val__h26634 =
(w1__h25539 < w2__h38276) ? w1__h25539 : w2__h38276 ;
assign new_st_val__h26639 =
(w1__h25539 <= w2__h38276) ? w2__h38276 : w1__h25539 ;
assign new_st_val__h26645 =
((IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 ^
64'h8000000000000000) <
(IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ^
64'h8000000000000000)) ?
w1__h25539 :
w2__h38276 ;
assign new_st_val__h26650 =
((IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 ^
64'h8000000000000000) <=
(IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ^
64'h8000000000000000)) ?
w2__h38276 :
w1__h25539 ;
assign new_st_val__h38286 = { 32'd0, _theResult_____2__h38282[31:0] } ;
assign new_st_val__h38377 =
new_ld_val__h38242 +
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ;
assign new_st_val__h40237 = w1__h38274 ^ w2__h38276 ;
assign new_st_val__h40241 = w1__h38274 & w2__h38276 ;
assign new_st_val__h40245 = w1__h38274 | w2__h38276 ;
assign new_st_val__h40249 =
(w1__h38274 < w2__h38276) ? w1__h38274 : w2__h38276 ;
assign new_st_val__h40254 =
(w1__h38274 <= w2__h38276) ? w2__h38276 : w1__h38274 ;
assign new_st_val__h40260 =
((new_ld_val__h38242 ^ 64'h8000000000000000) <
(IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ^
64'h8000000000000000)) ?
w1__h38274 :
w2__h38276 ;
assign new_st_val__h40265 =
((new_ld_val__h38242 ^ 64'h8000000000000000) <=
(IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_rg_st_amo_val_ETC___d784 ^
64'h8000000000000000)) ?
w2__h38276 :
w1__h38274 ;
assign new_value__h24131 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
64'd1 :
CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_21_EQ__ETC__q53 ;
assign new_value__h7718 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
word64__h7596 :
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 ;
assign pa___1__h6580 = { 8'd0, x__h6583 } ;
assign pa___1__h6629 = { 8'd0, x__h6632 } ;
assign pa___1__h6698 = { 8'd0, x__h6701 } ;
assign pte___1__h6852 = { tlb$lookup[129:73], 1'd1, tlb$lookup[71:66] } ;
assign pte___1__h6880 =
{ pte___2__h6572[63:8], 1'd1, pte___2__h6572[6:0] } ;
assign pte___2__h6572 =
tlb$lookup[72] ? tlb$lookup[129:66] : pte___1__h6852 ;
assign ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 =
ram_state_and_ctag_cset$DOB[104:53] ==
x1_avValue_pa__h6062[63:12] ;
assign ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 =
ram_state_and_ctag_cset$DOB[51:0] ==
x1_avValue_pa__h6062[63:12] ;
assign ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d484 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ;
assign ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d495 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 ;
assign ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d673 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d916 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) &&
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 &&
!cfg_verbosity_read__1_ULE_1___d42 ;
assign req_f3_BITS_1_TO_0_440_EQ_0b0_441_OR_req_f3_BI_ETC___d1470 =
req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
assign result__h20421 =
{ {56{word64596_BITS_7_TO_0__q15[7]}},
word64596_BITS_7_TO_0__q15 } ;
assign result__h20449 =
{ {56{word64596_BITS_15_TO_8__q18[7]}},
word64596_BITS_15_TO_8__q18 } ;
assign result__h20477 =
{ {56{word64596_BITS_23_TO_16__q19[7]}},
word64596_BITS_23_TO_16__q19 } ;
assign result__h20505 =
{ {56{word64596_BITS_31_TO_24__q21[7]}},
word64596_BITS_31_TO_24__q21 } ;
assign result__h20533 =
{ {56{word64596_BITS_39_TO_32__q22[7]}},
word64596_BITS_39_TO_32__q22 } ;
assign result__h20561 =
{ {56{word64596_BITS_47_TO_40__q25[7]}},
word64596_BITS_47_TO_40__q25 } ;
assign result__h20589 =
{ {56{word64596_BITS_55_TO_48__q26[7]}},
word64596_BITS_55_TO_48__q26 } ;
assign result__h20617 =
{ {56{word64596_BITS_63_TO_56__q28[7]}},
word64596_BITS_63_TO_56__q28 } ;
assign result__h20662 = { 56'd0, word64__h7596[7:0] } ;
assign result__h20690 = { 56'd0, word64__h7596[15:8] } ;
assign result__h20718 = { 56'd0, word64__h7596[23:16] } ;
assign result__h20746 = { 56'd0, word64__h7596[31:24] } ;
assign result__h20774 = { 56'd0, word64__h7596[39:32] } ;
assign result__h20802 = { 56'd0, word64__h7596[47:40] } ;
assign result__h20830 = { 56'd0, word64__h7596[55:48] } ;
assign result__h20858 = { 56'd0, word64__h7596[63:56] } ;
assign result__h20903 =
{ {48{word64596_BITS_15_TO_0__q16[15]}},
word64596_BITS_15_TO_0__q16 } ;
assign result__h20931 =
{ {48{word64596_BITS_31_TO_16__q20[15]}},
word64596_BITS_31_TO_16__q20 } ;
assign result__h20959 =
{ {48{word64596_BITS_47_TO_32__q23[15]}},
word64596_BITS_47_TO_32__q23 } ;
assign result__h20987 =
{ {48{word64596_BITS_63_TO_48__q27[15]}},
word64596_BITS_63_TO_48__q27 } ;
assign result__h21028 = { 48'd0, word64__h7596[15:0] } ;
assign result__h21056 = { 48'd0, word64__h7596[31:16] } ;
assign result__h21084 = { 48'd0, word64__h7596[47:32] } ;
assign result__h21112 = { 48'd0, word64__h7596[63:48] } ;
assign result__h21153 =
{ {32{word64596_BITS_31_TO_0__q17[31]}},
word64596_BITS_31_TO_0__q17 } ;
assign result__h21181 =
{ {32{word64596_BITS_63_TO_32__q24[31]}},
word64596_BITS_63_TO_32__q24 } ;
assign result__h21220 = { 32'd0, word64__h7596[31:0] } ;
assign result__h21248 = { 32'd0, word64__h7596[63:32] } ;
assign result__h36065 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1[7]}},
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 } ;
assign result__h36095 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4[7]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 } ;
assign result__h36122 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5[7]}},
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 } ;
assign result__h36149 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7[7]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7 } ;
assign result__h36176 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8[7]}},
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 } ;
assign result__h36203 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11[7]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 } ;
assign result__h36230 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12[7]}},
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 } ;
assign result__h36257 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14[7]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 } ;
assign result__h36301 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
assign result__h36328 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
assign result__h36355 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
assign result__h36382 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
assign result__h36409 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
assign result__h36436 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
assign result__h36463 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
assign result__h36490 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
assign result__h36534 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2[15]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 } ;
assign result__h36561 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6[15]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6 } ;
assign result__h36588 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9[15]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 } ;
assign result__h36615 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13[15]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 } ;
assign result__h36655 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
assign result__h36682 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
assign result__h36709 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
assign result__h36736 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
assign result__h36776 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3[31]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 } ;
assign result__h36803 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10[31]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 } ;
assign result__h36841 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
assign result__h36868 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
assign result__h38465 =
{ {56{ld_val5996_BITS_7_TO_0__q37[7]}},
ld_val5996_BITS_7_TO_0__q37 } ;
assign result__h39373 =
{ {56{ld_val5996_BITS_15_TO_8__q40[7]}},
ld_val5996_BITS_15_TO_8__q40 } ;
assign result__h39401 =
{ {56{ld_val5996_BITS_23_TO_16__q41[7]}},
ld_val5996_BITS_23_TO_16__q41 } ;
assign result__h39429 =
{ {56{ld_val5996_BITS_31_TO_24__q43[7]}},
ld_val5996_BITS_31_TO_24__q43 } ;
assign result__h39457 =
{ {56{ld_val5996_BITS_39_TO_32__q44[7]}},
ld_val5996_BITS_39_TO_32__q44 } ;
assign result__h39485 =
{ {56{ld_val5996_BITS_47_TO_40__q47[7]}},
ld_val5996_BITS_47_TO_40__q47 } ;
assign result__h39513 =
{ {56{ld_val5996_BITS_55_TO_48__q48[7]}},
ld_val5996_BITS_55_TO_48__q48 } ;
assign result__h39541 =
{ {56{ld_val5996_BITS_63_TO_56__q50[7]}},
ld_val5996_BITS_63_TO_56__q50 } ;
assign result__h39586 = { 56'd0, ld_val__h35996[7:0] } ;
assign result__h39614 = { 56'd0, ld_val__h35996[15:8] } ;
assign result__h39642 = { 56'd0, ld_val__h35996[23:16] } ;
assign result__h39670 = { 56'd0, ld_val__h35996[31:24] } ;
assign result__h39698 = { 56'd0, ld_val__h35996[39:32] } ;
assign result__h39726 = { 56'd0, ld_val__h35996[47:40] } ;
assign result__h39754 = { 56'd0, ld_val__h35996[55:48] } ;
assign result__h39782 = { 56'd0, ld_val__h35996[63:56] } ;
assign result__h39827 =
{ {48{ld_val5996_BITS_15_TO_0__q38[15]}},
ld_val5996_BITS_15_TO_0__q38 } ;
assign result__h39855 =
{ {48{ld_val5996_BITS_31_TO_16__q42[15]}},
ld_val5996_BITS_31_TO_16__q42 } ;
assign result__h39883 =
{ {48{ld_val5996_BITS_47_TO_32__q45[15]}},
ld_val5996_BITS_47_TO_32__q45 } ;
assign result__h39911 =
{ {48{ld_val5996_BITS_63_TO_48__q49[15]}},
ld_val5996_BITS_63_TO_48__q49 } ;
assign result__h39952 = { 48'd0, ld_val__h35996[15:0] } ;
assign result__h39980 = { 48'd0, ld_val__h35996[31:16] } ;
assign result__h40008 = { 48'd0, ld_val__h35996[47:32] } ;
assign result__h40036 = { 48'd0, ld_val__h35996[63:48] } ;
assign result__h40077 =
{ {32{ld_val5996_BITS_31_TO_0__q39[31]}},
ld_val5996_BITS_31_TO_0__q39 } ;
assign result__h40105 =
{ {32{ld_val5996_BITS_63_TO_32__q46[31]}},
ld_val5996_BITS_63_TO_32__q46 } ;
assign result__h40144 = { 32'd0, ld_val__h35996[31:0] } ;
assign result__h40172 = { 32'd0, ld_val__h35996[63:32] } ;
assign rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b10_20_AND_ETC___d680 =
rg_amo_funct7[6:2] == 5'b00010 &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
assign rg_amo_funct7_18_BITS_6_TO_2_19_EQ_0b1_88_OR_I_ETC___d344 =
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ||
IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339) &&
(ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 ||
IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339) ;
assign rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271 =
rg_lrsc_pa == x1_avValue_pa__h6062 ;
assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d431 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d468 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133 ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
tlb$lookup[68] ;
assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d489 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d484 ||
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d487) ;
assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d499 =
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d489 ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d497 ;
assign rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d503 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211) ;
assign rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d497 =
rg_op == 2'd1 &&
IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_T_ETC___d485 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__00_BIT_52_01_A_ETC___d495 ;
assign rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d720 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_13_EQ_2_16_17_OR_NOT_rg_amo_funct7_1_ETC___d717 ||
NOT_rg_op_13_EQ_1_66_93_AND_NOT_rg_op_13_EQ_2__ETC___d719 ;
assign rg_op_13_EQ_1_66_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d850 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid &&
rg_lrsc_pa_70_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d271) ;
assign rg_op_13_EQ_2_16_AND_rg_amo_funct7_18_BITS_6_T_ETC___d287 =
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h21704 ||
f_fabric_write_reqs$FULL_N &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d285 ;
assign rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 =
rg_priv == 2'b0 && !tlb$lookup[70] ||
rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM ||
dmem_not_imem_OR_NOT_rg_op_13_EQ_0_14_15_AND_N_ETC___d127 &&
NOT_dmem_not_imem_28_OR_NOT_rg_op_13_EQ_0_14_1_ETC___d135 &&
(!dmem_not_imem || rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
!tlb$lookup[68]) ;
assign rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d157 =
rg_priv == 2'b0 && !tlb$lookup[70] ||
rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM ||
!dmem_not_imem ||
!tlb$lookup[68] ;
assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 =
rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
tlb$lookup[130] &&
(rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 ||
NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150) ;
assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d352 =
rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
!tlb$lookup[130] ||
(rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ?
tlb$RDY_lookup :
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350) ;
assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d400 =
rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
(rg_priv_6_EQ_0b0_03_AND_NOT_tlb_lookup_rg_satp_ETC___d144 ||
NOT_tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_ad_ETC___d150) &&
tlb$lookup[130] ;
assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 =
rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
tlb$lookup[130] &&
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d415 &&
tlb$lookup[72] &&
tlb$lookup[73] &&
!pte___2__h6572[7] &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d439 =
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d153 ||
dmem_not_imem && !soc_map$m_is_mem_addr ||
rg_op_13_EQ_0_14_OR_rg_op_13_EQ_2_16_AND_rg_am_ETC___d431 ||
NOT_rg_op_13_EQ_0_14_15_AND_NOT_rg_op_13_EQ_2__ETC___d436 ;
assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d440 =
rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
!tlb$lookup[130] ||
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d439 ;
assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d458 =
rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8 &&
tlb$lookup[130] &&
NOT_rg_priv_6_EQ_0b0_03_78_OR_tlb_lookup_rg_sa_ETC___d453 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450 &&
dmem_not_imem &&
tlb$lookup[68] &&
tlb$lookup[73] ;
assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d461 =
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450 &&
(!dmem_not_imem || !tlb$lookup[68] || !tlb$lookup[73]) ;
assign rg_priv_6_ULE_0b1___d87 = rg_priv <= 2'b01 ;
assign rg_st_amo_val_BITS_31_TO_0__q33 = rg_st_amo_val[31:0] ;
assign rg_state_1_EQ_13_155_AND_rg_op_13_EQ_0_14_OR_r_ETC___d1157 =
rg_state == 5'd13 &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
b__h28501 == 4'd0 ;
assign satp_pa__h1890 = { 8'd0, x__h4883 } ;
assign shift_bits__h2857 = { f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ;
assign strobe64__h3007 = 8'b00000001 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h3009 = 8'b00000011 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h3011 = 8'b00001111 << f_fabric_write_reqs$D_OUT[66:64] ;
assign tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d133 =
tlb$lookup[67] | y__h6398 ;
assign tlb_lookup_rg_satp_9_BITS_59_TO_44_6_rg_addr_7_ETC___d394 =
tlb$lookup[72] &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
tlb$lookup[73]) ;
assign tmp__h32016 = { 1'd0, rg_victim_way } ;
assign tmp__h32017 = tmp__h32016 + 2'd1 ;
assign value__h6897 =
(rg_priv_6_ULE_0b1___d87 && rg_satp[63:60] == 4'd8) ?
_theResult___snd_fst__h6162 :
tlb$lookup[129:66] ;
assign vpn_0_pa__h30622 = { 52'd0, rg_addr[20:12], 3'd0 } ;
assign vpn_1_pa__h29529 = { 52'd0, rg_addr[29:21], 3'd0 } ;
assign vpn_2_pa__h28595 = { 52'd0, rg_addr[38:30], 3'd0 } ;
assign w18270_BITS_31_TO_0__q52 = w1__h38270[31:0] ;
assign w1___1__h25610 =
{ 32'd0,
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654[31:0] } ;
assign w1___1__h38345 = { 32'd0, w1__h38270[31:0] } ;
assign w2___1__h38346 = { 32'd0, rg_st_amo_val[31:0] } ;
assign w2__h38276 = (rg_f3 == 3'b010) ? w2___1__h38346 : rg_st_amo_val ;
assign word64596_BITS_15_TO_0__q16 = word64__h7596[15:0] ;
assign word64596_BITS_15_TO_8__q18 = word64__h7596[15:8] ;
assign word64596_BITS_23_TO_16__q19 = word64__h7596[23:16] ;
assign word64596_BITS_31_TO_0__q17 = word64__h7596[31:0] ;
assign word64596_BITS_31_TO_16__q20 = word64__h7596[31:16] ;
assign word64596_BITS_31_TO_24__q21 = word64__h7596[31:24] ;
assign word64596_BITS_39_TO_32__q22 = word64__h7596[39:32] ;
assign word64596_BITS_47_TO_32__q23 = word64__h7596[47:32] ;
assign word64596_BITS_47_TO_40__q25 = word64__h7596[47:40] ;
assign word64596_BITS_55_TO_48__q26 = word64__h7596[55:48] ;
assign word64596_BITS_63_TO_32__q24 = word64__h7596[63:32] ;
assign word64596_BITS_63_TO_48__q27 = word64__h7596[63:48] ;
assign word64596_BITS_63_TO_56__q28 = word64__h7596[63:56] ;
assign word64596_BITS_7_TO_0__q15 = word64__h7596[7:0] ;
assign word64__h7596 = x__h7735 | y__h7736 ;
assign x1_avValue_exc_code__h6063 =
dmem_not_imem ?
((rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd13 :
4'd15) :
4'd12 ;
assign x1_avValue_pa__h6062 = soc_map$m_is_mem_addr_addr ;
assign x__h21714 = { 63'd0, lrsc_result__h21704 } ;
assign x__h29603 = { master_xactor_f_rd_data$D_OUT[56:13], 12'b0 } ;
assign x__h38265 =
(rg_f3 == 3'b010) ?
new_st_val__h38286 :
_theResult_____2__h38282 ;
assign x__h4883 = { rg_satp[43:0], 12'b0 } ;
assign x__h6583 = { tlb$lookup[119:76], rg_addr[11:0] } ;
assign x__h6632 = { tlb$lookup[119:85], rg_addr[20:0] } ;
assign x__h6701 = { tlb$lookup[119:94], rg_addr[29:0] } ;
assign x__h7735 = ram_cword_set$DOB[63:0] & y__h7750 ;
assign y__h14065 =
{64{ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211}} ;
assign y__h6398 = rg_mstatus_MXR & tlb$lookup[69] ;
assign y__h7736 = ram_cword_set$DOB[127:64] & y__h14065 ;
assign y__h7750 =
{64{ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__00_BITS_51_TO__ETC___d205}} ;
always@(f_fabric_write_reqs$D_OUT)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0: x__h2890 = 3'b0;
2'b01: x__h2890 = 3'b001;
2'b10: x__h2890 = 3'b010;
2'b11: x__h2890 = 3'b011;
endcase
end
always@(rg_f3)
begin
case (rg_f3[1:0])
2'b0: value__h37822 = 3'b0;
2'b01: value__h37822 = 3'b001;
2'b10: value__h37822 = 3'b010;
2'd3: value__h37822 = 3'b011;
endcase
end
always@(tlb$lookup or
rg_addr or pa___1__h6580 or pa___1__h6629 or pa___1__h6698)
begin
case (tlb$lookup[65:64])
2'd0: _theResult___fst__h6574 = pa___1__h6580;
2'd1: _theResult___fst__h6574 = pa___1__h6629;
2'd2: _theResult___fst__h6574 = pa___1__h6698;
2'd3: _theResult___fst__h6574 = rg_addr;
endcase
end
always@(f_fabric_write_reqs$D_OUT or
strobe64__h3007 or strobe64__h3009 or strobe64__h3011)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0: mem_req_wr_data_wstrb__h3064 = strobe64__h3007;
2'b01: mem_req_wr_data_wstrb__h3064 = strobe64__h3009;
2'b10: mem_req_wr_data_wstrb__h3064 = strobe64__h3011;
2'b11: mem_req_wr_data_wstrb__h3064 = 8'b11111111;
endcase
end
always@(f_fabric_write_reqs$D_OUT or _theResult___snd_fst__h3071)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h3063 = _theResult___snd_fst__h3071;
2'd3: mem_req_wr_data_wdata__h3063 = f_fabric_write_reqs$D_OUT[63:0];
endcase
end
always@(ram_state_and_ctag_cset$DOB or
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211 or
ram_cword_set$DOB)
begin
case (ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__00_BITS_104_TO_ETC___d211)
1'd0: old_cword__h22505 = ram_cword_set$DOB[63:0];
1'd1: old_cword__h22505 = ram_cword_set$DOB[127:64];
endcase
end
always@(rg_f3 or
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 or
rg_priv_6_ULE_0b1___d87 or rg_satp or tlb$RDY_lookup)
begin
case (rg_f3)
3'b0, 3'b001, 3'b010:
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279 =
!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup;
default: IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b1_42_OR_ETC___d279 =
rg_f3 == 3'b011 ||
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
endcase
end
always@(rg_addr or
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 or
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236)
begin
case (rg_addr[2:0])
3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241 =
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
3'd7:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241 =
rg_addr[2:0] != 3'h7 ||
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
endcase
end
always@(rg_addr or
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 or
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236)
begin
case (rg_addr[2:0])
3'h0, 3'h2, 3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249 =
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249 =
rg_addr[2:0] != 3'h6 ||
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
endcase
end
always@(rg_f3 or
rg_addr or
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 or
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_NOT_ETC___d255)
begin
case (rg_f3)
3'b0, 3'b100:
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d241;
3'b001, 3'b101:
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_OR_rg_ad_ETC___d249;
3'b010, 3'b110:
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_NOT_ETC___d255;
default: IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263 =
rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 ||
NOT_ram_state_and_ctag_cset_b_read__00_BIT_52__ETC___d235 &&
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
endcase
end
always@(rg_amo_funct7 or
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263)
begin
case (rg_amo_funct7[6:2])
5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100:
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 =
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263;
default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29 =
rg_amo_funct7[6:2] != 5'b10100 ||
IF_rg_f3_17_EQ_0b0_18_OR_rg_f3_17_EQ_0b100_19__ETC___d263;
endcase
end
always@(x1_avValue_pa__h6062 or
NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d329 or
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29)
begin
case (x1_avValue_pa__h6062[2:0])
3'h0, 3'h2, 3'h4:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330 =
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29;
default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330 =
NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d329;
endcase
end
always@(x1_avValue_pa__h6062 or
NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d323 or
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29)
begin
case (x1_avValue_pa__h6062[2:0])
3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324 =
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29;
3'd7:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324 =
NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS__ETC___d323;
endcase
end
always@(rg_f3 or
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236 or
rg_priv_6_ULE_0b1___d87 or
rg_satp or
tlb$RDY_lookup or
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324 or
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330 or
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d334 or
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29)
begin
case (rg_f3)
3'b0:
IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup) &&
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d324;
3'b001:
IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup) &&
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d330;
3'b010:
IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$RDY_lookup) &&
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d334;
3'b011:
IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_17_ETC__q29;
default: IF_rg_f3_17_EQ_0b0_18_THEN_NOT_rg_priv_6_ULE_0_ETC___d339 =
NOT_ram_state_and_ctag_cset_b_read__00_BIT_105_ETC___d236;
endcase
end
always@(rg_addr or
result__h20421 or
result__h20449 or
result__h20477 or
result__h20505 or
result__h20533 or
result__h20561 or result__h20589 or result__h20617)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
result__h20421;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
result__h20449;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
result__h20477;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
result__h20505;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
result__h20533;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
result__h20561;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
result__h20589;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 =
result__h20617;
endcase
end
always@(rg_addr or
result__h20662 or
result__h20690 or
result__h20718 or
result__h20746 or
result__h20774 or
result__h20802 or result__h20830 or result__h20858)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
result__h20662;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
result__h20690;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
result__h20718;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
result__h20746;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
result__h20774;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
result__h20802;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
result__h20830;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 =
result__h20858;
endcase
end
always@(rg_addr or
result__h20903 or
result__h20931 or result__h20959 or result__h20987)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
result__h20903;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
result__h20931;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
result__h20959;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
result__h20987;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 =
64'd0;
endcase
end
always@(rg_addr or
result__h21028 or
result__h21056 or result__h21084 or result__h21112)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
result__h21028;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
result__h21056;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
result__h21084;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
result__h21112;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 =
64'd0;
endcase
end
always@(rg_addr or result__h21220 or result__h21248)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646 =
result__h21220;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646 =
result__h21248;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646 =
64'd0;
endcase
end
always@(rg_addr or result__h21153 or result__h21181)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1153_0x4_re_ETC__q30 =
result__h21153;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1153_0x4_re_ETC__q30 =
result__h21181;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1153_0x4_re_ETC__q30 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1153_0x4_re_ETC__q30 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646)
begin
case (rg_f3)
3'b0:
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600;
3'b001:
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628;
3'b010:
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1153_0x4_re_ETC__q30;
3'b011:
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647;
3'b100:
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616;
3'b101:
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636;
3'b110:
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646;
3'd7: IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC___d654 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 or
w1___1__h25610 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646)
begin
case (rg_f3)
3'b0:
w1__h25539 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600;
3'b001:
w1__h25539 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628;
3'b010: w1__h25539 = w1___1__h25610;
3'b011:
w1__h25539 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647;
3'b100:
w1__h25539 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616;
3'b101:
w1__h25539 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636;
3'b110:
w1__h25539 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646;
3'd7: w1__h25539 = 64'd0;
endcase
end
always@(x1_avValue_pa__h6062 or old_cword__h22505 or rg_st_amo_val)
begin
case (x1_avValue_pa__h6062[2:0])
3'h0:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
{ old_cword__h22505[63:16], rg_st_amo_val[15:0] };
3'h2:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
{ old_cword__h22505[63:32],
rg_st_amo_val[15:0],
old_cword__h22505[15:0] };
3'h4:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
{ old_cword__h22505[63:48],
rg_st_amo_val[15:0],
old_cword__h22505[31:0] };
3'h6:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
{ rg_st_amo_val[15:0], old_cword__h22505[47:0] };
default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 =
old_cword__h22505;
endcase
end
always@(x1_avValue_pa__h6062 or old_cword__h22505 or rg_st_amo_val)
begin
case (x1_avValue_pa__h6062[2:0])
3'h0:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
{ old_cword__h22505[63:8], rg_st_amo_val[7:0] };
3'h1:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
{ old_cword__h22505[63:16],
rg_st_amo_val[7:0],
old_cword__h22505[7:0] };
3'h2:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
{ old_cword__h22505[63:24],
rg_st_amo_val[7:0],
old_cword__h22505[15:0] };
3'h3:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
{ old_cword__h22505[63:32],
rg_st_amo_val[7:0],
old_cword__h22505[23:0] };
3'h4:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
{ old_cword__h22505[63:40],
rg_st_amo_val[7:0],
old_cword__h22505[31:0] };
3'h5:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
{ old_cword__h22505[63:48],
rg_st_amo_val[7:0],
old_cword__h22505[39:0] };
3'h6:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
{ old_cword__h22505[63:56],
rg_st_amo_val[7:0],
old_cword__h22505[47:0] };
3'h7:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 =
{ rg_st_amo_val[7:0], old_cword__h22505[55:0] };
endcase
end
always@(x1_avValue_pa__h6062 or old_cword__h22505 or rg_st_amo_val)
begin
case (x1_avValue_pa__h6062[2:0])
3'h0:
CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
{ old_cword__h22505[63:32], rg_st_amo_val[31:0] };
3'h4:
CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
{ rg_st_amo_val[31:0], old_cword__h22505[31:0] };
default: CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
old_cword__h22505;
endcase
end
always@(rg_f3 or
old_cword__h22505 or
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759 or
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768 or
CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q31 or
rg_st_amo_val)
begin
case (rg_f3)
3'b0:
n__h22516 =
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d759;
3'b001:
n__h22516 =
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d768;
3'b010:
n__h22516 = CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q31;
3'b011: n__h22516 = rg_st_amo_val;
default: n__h22516 = old_cword__h22505;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628 or
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646)
begin
case (rg_f3)
3'b0:
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d600;
3'b001:
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d628;
3'b010:
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
{ {32{IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32[31]}},
IF_rg_f3_17_EQ_0b0_18_THEN_IF_rg_addr_7_BITS_2_ETC__q32 };
3'b011:
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_ram_ETC___d647;
3'b100:
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d616;
3'b101:
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d636;
3'b110:
IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d646;
3'd7: IF_rg_f3_17_EQ_0b10_50_THEN_SEXT_IF_rg_f3_17_E_ETC___d715 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h26650 or
new_st_val__h25642 or
w2__h38276 or
new_st_val__h26622 or
new_st_val__h26630 or
new_st_val__h26626 or
new_st_val__h26645 or new_st_val__h26634 or new_st_val__h26639)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h25547 = new_st_val__h25642;
5'b00001: _theResult_____2__h25547 = w2__h38276;
5'b00100: _theResult_____2__h25547 = new_st_val__h26622;
5'b01000: _theResult_____2__h25547 = new_st_val__h26630;
5'b01100: _theResult_____2__h25547 = new_st_val__h26626;
5'b10000: _theResult_____2__h25547 = new_st_val__h26645;
5'b11000: _theResult_____2__h25547 = new_st_val__h26634;
5'b11100: _theResult_____2__h25547 = new_st_val__h26639;
default: _theResult_____2__h25547 = new_st_val__h26650;
endcase
end
always@(x1_avValue_pa__h6062 or old_cword__h22505 or new_st_val__h25251)
begin
case (x1_avValue_pa__h6062[2:0])
3'h0:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
{ old_cword__h22505[63:16], new_st_val__h25251[15:0] };
3'h2:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
{ old_cword__h22505[63:32],
new_st_val__h25251[15:0],
old_cword__h22505[15:0] };
3'h4:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
{ old_cword__h22505[63:48],
new_st_val__h25251[15:0],
old_cword__h22505[31:0] };
3'h6:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
{ new_st_val__h25251[15:0], old_cword__h22505[47:0] };
default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 =
old_cword__h22505;
endcase
end
always@(x1_avValue_pa__h6062 or old_cword__h22505 or new_st_val__h25251)
begin
case (x1_avValue_pa__h6062[2:0])
3'h0:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
{ old_cword__h22505[63:8], new_st_val__h25251[7:0] };
3'h1:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
{ old_cword__h22505[63:16],
new_st_val__h25251[7:0],
old_cword__h22505[7:0] };
3'h2:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
{ old_cword__h22505[63:24],
new_st_val__h25251[7:0],
old_cword__h22505[15:0] };
3'h3:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
{ old_cword__h22505[63:32],
new_st_val__h25251[7:0],
old_cword__h22505[23:0] };
3'h4:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
{ old_cword__h22505[63:40],
new_st_val__h25251[7:0],
old_cword__h22505[31:0] };
3'h5:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
{ old_cword__h22505[63:48],
new_st_val__h25251[7:0],
old_cword__h22505[39:0] };
3'h6:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
{ old_cword__h22505[63:56],
new_st_val__h25251[7:0],
old_cword__h22505[47:0] };
3'h7:
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 =
{ new_st_val__h25251[7:0], old_cword__h22505[55:0] };
endcase
end
always@(x1_avValue_pa__h6062 or old_cword__h22505 or new_st_val__h25251)
begin
case (x1_avValue_pa__h6062[2:0])
3'h0:
CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
{ old_cword__h22505[63:32], new_st_val__h25251[31:0] };
3'h4:
CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
{ new_st_val__h25251[31:0], old_cword__h22505[31:0] };
default: CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
old_cword__h22505;
endcase
end
always@(rg_f3 or
old_cword__h22505 or
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827 or
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836 or
CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q34 or
new_st_val__h25251)
begin
case (rg_f3)
3'b0:
n__h25409 =
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d827;
3'b001:
n__h25409 =
IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_6_ETC___d836;
3'b010:
n__h25409 = CASE_x1_avValue_pa062_BITS_2_TO_0_0x0_old_cwor_ETC__q34;
3'b011: n__h25409 = new_st_val__h25251;
default: n__h25409 = old_cword__h22505;
endcase
end
always@(rg_addr or
result__h36655 or
result__h36682 or result__h36709 or result__h36736)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1235 =
result__h36655;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1235 =
result__h36682;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1235 =
result__h36709;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1235 =
result__h36736;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1235 =
64'd0;
endcase
end
always@(rg_addr or
result__h36534 or
result__h36561 or result__h36588 or result__h36615)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1227 =
result__h36534;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1227 =
result__h36561;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1227 =
result__h36588;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1227 =
result__h36615;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1227 =
64'd0;
endcase
end
always@(rg_addr or
result__h36301 or
result__h36328 or
result__h36355 or
result__h36382 or
result__h36409 or
result__h36436 or result__h36463 or result__h36490)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 =
result__h36301;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 =
result__h36328;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 =
result__h36355;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 =
result__h36382;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 =
result__h36409;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 =
result__h36436;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 =
result__h36463;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 =
result__h36490;
endcase
end
always@(rg_addr or
result__h36065 or
result__h36095 or
result__h36122 or
result__h36149 or
result__h36176 or
result__h36203 or result__h36230 or result__h36257)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 =
result__h36065;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 =
result__h36095;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 =
result__h36122;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 =
result__h36149;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 =
result__h36176;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 =
result__h36203;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 =
result__h36230;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 =
result__h36257;
endcase
end
always@(rg_addr or result__h36776 or result__h36803)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result6776_0x4_re_ETC__q35 =
result__h36776;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result6776_0x4_re_ETC__q35 =
result__h36803;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result6776_0x4_re_ETC__q35 =
64'd0;
endcase
end
always@(rg_addr or result__h36841 or result__h36868)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result6841_0x4_re_ETC__q36 =
result__h36841;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result6841_0x4_re_ETC__q36 =
result__h36868;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result6841_0x4_re_ETC__q36 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1227 or
CASE_rg_addr_BITS_2_TO_0_0x0_result6776_0x4_re_ETC__q35 or
rg_addr or
master_xactor_f_rd_data$D_OUT or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1235 or
CASE_rg_addr_BITS_2_TO_0_0x0_result6841_0x4_re_ETC__q36)
begin
case (rg_f3)
3'b0:
ld_val__h35996 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1199;
3'b001:
ld_val__h35996 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1227;
3'b010:
ld_val__h35996 =
CASE_rg_addr_BITS_2_TO_0_0x0_result6776_0x4_re_ETC__q35;
3'b011:
ld_val__h35996 =
(rg_addr[2:0] == 3'h0) ?
master_xactor_f_rd_data$D_OUT[66:3] :
64'd0;
3'b100:
ld_val__h35996 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1215;
3'b101:
ld_val__h35996 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1235;
3'b110:
ld_val__h35996 =
CASE_rg_addr_BITS_2_TO_0_0x0_result6841_0x4_re_ETC__q36;
3'd7: ld_val__h35996 = 64'd0;
endcase
end
always@(rg_addr or result__h40144 or result__h40172)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354 =
result__h40144;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354 =
result__h40172;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354 =
64'd0;
endcase
end
always@(rg_addr or
result__h39952 or
result__h39980 or result__h40008 or result__h40036)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344 =
result__h39952;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344 =
result__h39980;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344 =
result__h40008;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344 =
result__h40036;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344 =
64'd0;
endcase
end
always@(rg_addr or
result__h39827 or
result__h39855 or result__h39883 or result__h39911)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336 =
result__h39827;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336 =
result__h39855;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336 =
result__h39883;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336 =
result__h39911;
default: IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336 =
64'd0;
endcase
end
always@(rg_addr or
result__h38465 or
result__h39373 or
result__h39401 or
result__h39429 or
result__h39457 or
result__h39485 or result__h39513 or result__h39541)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 =
result__h38465;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 =
result__h39373;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 =
result__h39401;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 =
result__h39429;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 =
result__h39457;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 =
result__h39485;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 =
result__h39513;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 =
result__h39541;
endcase
end
always@(rg_addr or
result__h39586 or
result__h39614 or
result__h39642 or
result__h39670 or
result__h39698 or
result__h39726 or result__h39754 or result__h39782)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 =
result__h39586;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 =
result__h39614;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 =
result__h39642;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 =
result__h39670;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 =
result__h39698;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 =
result__h39726;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 =
result__h39754;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 =
result__h39782;
endcase
end
always@(rg_addr or result__h40077 or result__h40105)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result0077_0x4_re_ETC__q51 =
result__h40077;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result0077_0x4_re_ETC__q51 =
result__h40105;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result0077_0x4_re_ETC__q51 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336 or
CASE_rg_addr_BITS_2_TO_0_0x0_result0077_0x4_re_ETC__q51 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1355 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354)
begin
case (rg_f3)
3'b0:
w1__h38270 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308;
3'b001:
w1__h38270 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336;
3'b010:
w1__h38270 =
CASE_rg_addr_BITS_2_TO_0_0x0_result0077_0x4_re_ETC__q51;
3'b011:
w1__h38270 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1355;
3'b100:
w1__h38270 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324;
3'b101:
w1__h38270 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344;
3'b110:
w1__h38270 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354;
3'd7: w1__h38270 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336 or
w1___1__h38345 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1355 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354)
begin
case (rg_f3)
3'b0:
w1__h38274 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308;
3'b001:
w1__h38274 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336;
3'b010: w1__h38274 = w1___1__h38345;
3'b011:
w1__h38274 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1355;
3'b100:
w1__h38274 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324;
3'b101:
w1__h38274 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344;
3'b110:
w1__h38274 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354;
3'd7: w1__h38274 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336 or
w18270_BITS_31_TO_0__q52 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1355 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344 or
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354)
begin
case (rg_f3)
3'b0:
new_ld_val__h38242 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1308;
3'b001:
new_ld_val__h38242 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_SEX_ETC___d1336;
3'b010:
new_ld_val__h38242 =
{ {32{w18270_BITS_31_TO_0__q52[31]}},
w18270_BITS_31_TO_0__q52 };
3'b011:
new_ld_val__h38242 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_IF__ETC___d1355;
3'b100:
new_ld_val__h38242 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1324;
3'b101:
new_ld_val__h38242 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1344;
3'b110:
new_ld_val__h38242 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_0_C_ETC___d1354;
3'd7: new_ld_val__h38242 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h40265 or
new_st_val__h38377 or
w2__h38276 or
new_st_val__h40237 or
new_st_val__h40245 or
new_st_val__h40241 or
new_st_val__h40260 or new_st_val__h40249 or new_st_val__h40254)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h38282 = new_st_val__h38377;
5'b00001: _theResult_____2__h38282 = w2__h38276;
5'b00100: _theResult_____2__h38282 = new_st_val__h40237;
5'b01000: _theResult_____2__h38282 = new_st_val__h40245;
5'b01100: _theResult_____2__h38282 = new_st_val__h40241;
5'b10000: _theResult_____2__h38282 = new_st_val__h40260;
5'b11000: _theResult_____2__h38282 = new_st_val__h40249;
5'b11100: _theResult_____2__h38282 = new_st_val__h40254;
default: _theResult_____2__h38282 = new_st_val__h40265;
endcase
end
always@(rg_f3 or IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_1_E_ETC___d662)
begin
case (rg_f3)
3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_21_EQ__ETC__q53 =
IF_rg_addr_7_BITS_2_TO_0_21_EQ_0x0_22_THEN_1_E_ETC___d662;
3'd7: CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_21_EQ__ETC__q53 = 64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0;
rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0;
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000;
rg_tohost_value <= `BSV_ASSIGNMENT_DELAY 64'd0;
rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_wr_rsp_err <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (ctr_wr_rsps_pending_crg$EN)
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
ctr_wr_rsps_pending_crg$D_IN;
if (rg_cset_in_cache$EN)
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
if (rg_ddr4_ready$EN)
rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY rg_ddr4_ready$D_IN;
if (rg_lower_word32_full$EN)
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
rg_lower_word32_full$D_IN;
if (rg_lrsc_valid$EN)
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (rg_tohost_addr$EN)
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN;
if (rg_tohost_value$EN)
rg_tohost_value <= `BSV_ASSIGNMENT_DELAY rg_tohost_value$D_IN;
if (rg_watch_tohost$EN)
rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN;
if (rg_wr_rsp_err$EN)
rg_wr_rsp_err <= `BSV_ASSIGNMENT_DELAY rg_wr_rsp_err$D_IN;
end
if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
if (rg_amo_funct7$EN)
rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
if (rg_cset_cword_in_cache$EN)
rg_cset_cword_in_cache <= `BSV_ASSIGNMENT_DELAY
rg_cset_cword_in_cache$D_IN;
if (rg_error_during_refill$EN)
rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
rg_error_during_refill$D_IN;
if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
if (rg_lower_word32$EN)
rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
if (rg_mstatus_MXR$EN)
rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN;
if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN;
if (rg_sstatus_SUM$EN)
rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
if (rg_st_amo_val$EN)
rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
if (rg_victim_way$EN)
rg_victim_way <= `BSV_ASSIGNMENT_DELAY rg_victim_way$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
ctr_wr_rsps_pending_crg = 4'hA;
rg_addr = 64'hAAAAAAAAAAAAAAAA;
rg_amo_funct7 = 7'h2A;
rg_cset_cword_in_cache = 9'h0AA;
rg_cset_in_cache = 6'h2A;
rg_ddr4_ready = 1'h0;
rg_error_during_refill = 1'h0;
rg_exc_code = 4'hA;
rg_f3 = 3'h2;
rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
rg_lower_word32 = 32'hAAAAAAAA;
rg_lower_word32_full = 1'h0;
rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA;
rg_lrsc_valid = 1'h0;
rg_mstatus_MXR = 1'h0;
rg_op = 2'h2;
rg_pa = 64'hAAAAAAAAAAAAAAAA;
rg_priv = 2'h2;
rg_pte_pa = 64'hAAAAAAAAAAAAAAAA;
rg_satp = 64'hAAAAAAAAAAAAAAAA;
rg_sstatus_SUM = 1'h0;
rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
rg_state = 5'h0A;
rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA;
rg_tohost_value = 64'hAAAAAAAAAAAAAAAA;
rg_victim_way = 1'h0;
rg_watch_tohost = 1'h0;
rg_wr_rsp_err = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", f_fabric_write_reqs$D_OUT[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", x__h2890);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", mem_req_wr_data_wdata__h3063);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", mem_req_wr_data_wstrb__h3064);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
begin
v__h4526 = $stime;
#0;
end
v__h4520 = v__h4526 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4520,
"D_MMU_Cache",
$signed(32'd64),
$signed(32'd2));
else
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4520,
"I_MMU_Cache",
$signed(32'd64),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
!cfg_verbosity_read__1_ULE_1___d42 &&
f_reset_reqs$D_OUT)
begin
v__h4621 = $stime;
#0;
end
v__h4615 = v__h4621 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
!cfg_verbosity_read__1_ULE_1___d42 &&
f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: Flushed", v__h4615, "D_MMU_Cache");
else
$display("%0d: %s.rl_reset: Flushed", v__h4615, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h4747 = $stime;
#0;
end
v__h4741 = v__h4747 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4741,
"D_MMU_Cache",
rg_addr);
else
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4741,
"I_MMU_Cache",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
rg_satp[63:60] != 4'd0)
$display(" Priv:%0d SATP:{mode %0d asid %0h pa %0h} VA:%0h.%0h.%0h",
rg_priv,
rg_satp[63:60],
rg_satp[59:44],
satp_pa__h1890,
rg_addr[29:21],
rg_addr[20:12],
rg_addr[11:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}",
rg_addr[63:12],
rg_addr[11:6],
rg_addr[5:3],
rg_addr[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" CSet 0x%0x: (state, tag):", rg_addr[11:6]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
ram_state_and_ctag_cset$DOB[52])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
!ram_state_and_ctag_cset$DOB[52])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
ram_state_and_ctag_cset$DOB[52])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
!ram_state_and_ctag_cset$DOB[52])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
ram_state_and_ctag_cset$DOB[105])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
!ram_state_and_ctag_cset$DOB[105])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
ram_state_and_ctag_cset$DOB[105])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[104:53]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
!ram_state_and_ctag_cset$DOB[105])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" 0x%0x", ram_cword_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" 0x%0x", ram_cword_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" TLB result: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("VM_Xlate_Result { ", "outcome: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d397)
$write("VM_XLATE_OK");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d400)
$write("VM_XLATE_EXCEPTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
rg_priv_6_ULE_0b1___d87 &&
rg_satp[63:60] == 4'd8 &&
!tlb$lookup[130])
$write("VM_XLATE_TLB_MISS");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", x1_avValue_pa__h6062);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", x1_avValue_exc_code__h6063);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "pte_modified: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d412)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "pte: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", value__h6897, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$display(" fa_record_pte_A_D_updates:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("TLB_Lookup_Result { ", "hit: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(", ", "pte: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("'h%h", tlb$lookup[129:66]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(", ", "pte_level: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("'h%h", tlb$lookup[65:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(", ", "pte_pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("'h%h", tlb$lookup[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("VM_Xlate_Result { ", "outcome: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d458)
$write("VM_XLATE_OK");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d461)
$write("VM_XLATE_EXCEPTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(", ", "pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("'h%h", x1_avValue_pa__h6062);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("'h%h", x1_avValue_exc_code__h6063);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(", ", "pte_modified: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d461)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d458)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write(", ", "pte: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("'h%h", value__h6897, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BITS_63_TO_6_ETC___d422 &&
NOT_cfg_verbosity_read__1_ULT_2_49___d450)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d475)
$display(" => IO_REQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d481)
$display(" ASSERTION ERROR: fn_test_cache_hit_or_miss: multiple hits in set at [%0d] and [%0d]",
$signed(32'd1),
1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677)
begin
v__h21325 = $stime;
#0;
end
v__h21319 = v__h21325 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h21319,
"D_MMU_Cache",
rg_addr,
word64__h7596,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h21319,
"I_MMU_Cache",
rg_addr,
word64__h7596,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d689)
$display(" AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6062);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d677)
$display(" Read-hit: addr 0x%0h word64 0x%0h",
rg_addr,
word64__h7596);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d694)
$display(" Read Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d702)
$display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
rg_lrsc_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d861)
$display(" ST: cancelling LR/SC reservation for PA",
x1_avValue_pa__h6062);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d867)
$display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
rg_lrsc_pa,
x1_avValue_pa__h6062);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873)
$display(" AMO SC: fail due to invalid LR/SC reservation");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d879)
$display(" AMO SC result = %0d", lrsc_result__h21704);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
$display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h",
x1_avValue_pa__h6062,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d779);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d778);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d885)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d890)
$display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h",
x1_avValue_pa__h6062,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d897)
$display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d897)
$display(" => rl_write_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903)
begin
v__h25029 = $stime;
#0;
end
v__h25023 = v__h25029 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h25023,
"D_MMU_Cache",
rg_addr,
64'd1,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h25023,
"I_MMU_Cache",
rg_addr,
64'd1,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d903)
$display(" AMO SC: Fail response for addr 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d909)
$display(" AMO Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
rg_addr,
rg_amo_funct7,
rg_f3,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$display(" PA 0x%0h ", x1_avValue_pa__h6062);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$display(" Cache word64 0x%0h, load-result 0x%0h",
word64__h7596,
word64__h7596);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$display(" 0x%0h op 0x%0h -> 0x%0h",
word64__h7596,
word64__h7596,
new_st_val__h25251);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__00_BIT__ETC___d847);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__00_BIT_105__ETC___d846);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d915)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!rg_priv_6_ULE_0b1___d87 || rg_satp[63:60] != 4'd8 ||
tlb$lookup[130]) &&
NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d920)
$display(" AMO_op: cancelling LR/SC reservation for PA",
x1_avValue_pa__h6062);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_ddr4_ready)
begin
v__h43514 = $stime;
#0;
end
v__h43508 = v__h43514 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_ddr4_ready)
$display("%0d: %m.ma_ddr4_ready: Enabling MMU_Cache", v__h43508);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h28547 = $stime;
#0;
end
v__h28541 = v__h28547 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE",
v__h28541,
"D_MMU_Cache",
rg_addr);
else
$display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE",
v__h28541,
"I_MMU_Cache",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", lev_2_pte_pa_w64_fa__h28598);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_tlb_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
begin
v__h29498 = $stime;
#0;
end
v__h29492 = v__h29498 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h29492,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa,
exc_code___1__h6472);
else
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h29492,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa,
exc_code___1__h6472);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
begin
v__h29236 = $stime;
#0;
end
v__h29230 = v__h29236 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
if (dmem_not_imem)
$display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1",
v__h29230,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1",
v__h29230,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$display(" Req for level 1 PTE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", lev_1_pte_pa_w64_fa__h29532);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1007)
begin
v__h29801 = $stime;
#0;
end
v__h29795 = v__h29801 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1007)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h",
v__h29795,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h",
v__h29795,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
(master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0))
$display(" Invalid PTE: PPN[1] or PPN[0] is not zero; page fault %0d",
exc_code___1__h6472);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019)
begin
v__h29918 = $stime;
#0;
end
v__h29912 = v__h29918 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage",
v__h29912,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage",
v__h29912,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1019)
$display(" Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h29528);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h29418 = $stime;
#0;
end
v__h29412 = v__h29418 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_2 &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h29412,
"D_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h2635);
else
$display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h29412,
"I_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h2635);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
begin
v__h30591 = $stime;
#0;
end
v__h30585 = v__h30591 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h30585,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa,
exc_code___1__h6472);
else
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h30585,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa,
exc_code___1__h6472);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
begin
v__h30332 = $stime;
#0;
end
v__h30326 = v__h30332 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
if (dmem_not_imem)
$display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
v__h30326,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
v__h30326,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$display(" Req for level 0 PTE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", lev_0_pte_pa_w64_fa__h30625);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054)
begin
v__h31011 = $stime;
#0;
end
v__h31005 = v__h31011 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
v__h31005,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
v__h31005,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1054)
$display(" Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h29528);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1060)
begin
v__h30894 = $stime;
#0;
end
v__h30888 = v__h30894 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1060)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
v__h30888,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
v__h30888,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
master_xactor_f_rd_data$D_OUT[3] &&
(master_xactor_f_rd_data$D_OUT[4] ||
!master_xactor_f_rd_data$D_OUT[5]) &&
(master_xactor_f_rd_data$D_OUT[6] ||
master_xactor_f_rd_data$D_OUT[4]) &&
master_xactor_f_rd_data$D_OUT[21:13] != 9'd0)
$display(" Invalid PTE: PPN [0] is not zero; page fault %0d",
exc_code___1__h6472);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h30511 = $stime;
#0;
end
v__h30505 = v__h30511 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_1 &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h30505,
"D_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h2635);
else
$display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h30505,
"I_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h2635);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
begin
v__h31524 = $stime;
#0;
end
v__h31518 = v__h31524 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d981)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h31518,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa,
exc_code___1__h6472);
else
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
v__h31518,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa,
exc_code___1__h6472);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
begin
v__h31604 = $stime;
#0;
end
v__h31598 = v__h31604 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d991)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
v__h31598,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa,
exc_code___1__h6472);
else
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
v__h31598,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa,
exc_code___1__h6472);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085)
begin
v__h31695 = $stime;
#0;
end
v__h31689 = v__h31695 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
v__h31689,
"D_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
else
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
v__h31689,
"I_MMU_Cache",
rg_addr,
master_xactor_f_rd_data$D_OUT[66:3],
rg_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data_first__41_BITS_2_TO_1__ETC___d1085)
$display(" Addr Space page pa: 0x%0h", lev_1_PTN_pa__h29528);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h31444 = $stime;
#0;
end
v__h31438 = v__h31444 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_level_0 &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h31438,
"D_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h2635);
else
$display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
v__h31438,
"I_MMU_Cache",
rg_addr,
rg_pte_pa,
access_exc_code__h2635);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h31831 = $stime;
#0;
end
v__h31825 = v__h31831 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_start_cache_refill: ",
v__h31825,
"D_MMU_Cache");
else
$display("%0d: %s.rl_start_cache_refill: ",
v__h31825,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", cline_fabric_addr__h31880);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 8'd7);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$display(" Victim way %0d; => CACHE_REFILL", tmp__h32017[0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
begin
v__h32639 = $stime;
#0;
end
v__h32633 = v__h32639 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h32633,
"D_MMU_Cache");
else
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h32633,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h32877 = $stime;
#0;
end
v__h32871 = v__h32877 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h32871,
"D_MMU_Cache",
access_exc_code__h2635);
else
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h32871,
"I_MMU_Cache",
access_exc_code__h2635);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd7 &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) &&
!cfg_verbosity_read__1_ULE_1___d42)
$display(" => MODULE_EXCEPTION_RSP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd7 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!rg_error_during_refill &&
!cfg_verbosity_read__1_ULE_1___d42)
$display(" => CACHE_REREQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$display(" Updating Cache cword_set 0x%0h, cword_in_cline %0d) old => new",
rg_cset_cword_in_cache,
rg_cset_cword_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_cset_cword_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(" 0x%0x", ram_cword_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(" 0x%0x", ram_cword_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_cset_cword_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(" 0x%0x",
rg_victim_way ?
ram_cword_set$DOB[63:0] :
master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write(" 0x%0x",
rg_victim_way ?
master_xactor_f_rd_data$D_OUT[66:3] :
ram_cword_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_106___d1107)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__1_ULE_1___d42)
$display(" fa_req_ram_B tagCSet [0x%0x] cword_set [0x%0d]",
rg_addr[11:6],
rg_addr[11:3]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_watch_tohost)
begin
v__h43437 = $stime;
#0;
end
v__h43431 = v__h43437 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_watch_tohost)
$display("%0d: %m.set_watch_tohost: watch %0d, addr %0h",
v__h43431,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
begin
v__h35556 = $stime;
#0;
end
v__h35550 = v__h35556 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h35550,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h35550,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", value__h37822);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
begin
v__h35889 = $stime;
#0;
end
v__h35883 = v__h35889 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h35883,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h35883,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h36984 = $stime;
#0;
end
v__h36978 = v__h36984 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h36978,
"D_MMU_Cache",
rg_addr,
ld_val__h35996);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h36978,
"I_MMU_Cache",
rg_addr,
ld_val__h35996);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h37112 = $stime;
#0;
end
v__h37106 = v__h37112 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h37106,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h37106,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h37205 = $stime;
#0;
end
v__h37199 = v__h37205 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h37199,
"D_MMU_Cache",
rg_addr,
rg_ld_val);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h37199,
"I_MMU_Cache",
rg_addr,
rg_ld_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__1_ULE_1___d42)
begin
v__h37285 = $stime;
#0;
end
v__h37279 = v__h37285 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h37279,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h37279,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__1_ULE_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__1_ULE_1___d42)
begin
v__h37512 = $stime;
#0;
end
v__h37506 = v__h37512 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h37506,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h37506,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__1_ULE_1___d42)
$display(" FAIL due to I/O address.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__1_ULE_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
begin
v__h37648 = $stime;
#0;
end
v__h37642 = v__h37648 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h37642,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h37642,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", value__h37822);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h37929 = $stime;
#0;
end
v__h37923 = v__h37929 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h37923,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h37923,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h38111 = $stime;
#0;
end
v__h38105 = v__h38111 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h38105,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h38105,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h40357 = $stime;
#0;
end
v__h40351 = v__h40357 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h40351,
"D_MMU_Cache",
rg_addr,
new_ld_val__h38242);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h40351,
"I_MMU_Cache",
rg_addr,
new_ld_val__h38242);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h38212 = $stime;
#0;
end
v__h38206 = v__h38212 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h38206,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h38206,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
begin
v__h40958 = $stime;
#0;
end
v__h40952 = v__h40958 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h40952,
"D_MMU_Cache",
$unsigned(b__h28501));
else
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h40952,
"I_MMU_Cache",
$unsigned(b__h28501));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
!cfg_verbosity_read__1_ULE_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
begin
v__h41000 = $stime;
#0;
end
v__h40994 = v__h41000 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
if (dmem_not_imem)
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h40994,
"D_MMU_Cache");
else
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h40994,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
begin
v__h4061 = $stime;
#0;
end
v__h4055 = v__h4061 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
if (dmem_not_imem)
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h4055,
"D_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd64),
$signed(32'd8));
else
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h4055,
"I_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd64),
$signed(32'd8));
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
begin
v__h41354 = $stime;
#0;
end
v__h41348 = v__h41354 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
$write("%0d: %m.req: op:", v__h41348);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_op == 2'd0)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_op == 2'd1)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_op != 2'd0 &&
req_op != 2'd1)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(" f3:%0d addr:0x%0h st_value:0x%0h",
req_f3,
req_addr,
req_st_value,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42) $write(" priv:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_priv == 2'b0)
$write("U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_priv == 2'b01)
$write("S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_priv == 2'b11)
$write("M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42 && req_priv != 2'b0 &&
req_priv != 2'b01 &&
req_priv != 2'b11)
$write("RESERVED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && !cfg_verbosity_read__1_ULE_1___d42)
$display(" amo_funct7 = 0x%0h", req_amo_funct7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req &&
req_f3_BITS_1_TO_0_440_EQ_0b0_441_OR_req_f3_BI_ETC___d1470 &&
!cfg_verbosity_read__1_ULE_1___d42)
$display(" fa_req_ram_B tagCSet [0x%0x] cword_set [0x%0d]",
req_addr[11:6],
req_addr[11:3]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_tlb_flush && !cfg_verbosity_read__1_ULE_1___d42)
begin
v__h43050 = $stime;
#0;
end
v__h43044 = v__h43050 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_tlb_flush && !cfg_verbosity_read__1_ULE_1___d42)
if (dmem_not_imem)
$display("%0d: %s.tlb_flush", v__h43044, "D_MMU_Cache");
else
$display("%0d: %s.tlb_flush", v__h43044, "I_MMU_Cache");
end
// synopsys translate_on
endmodule // mkMMU_Cache
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05:18:23 04/20/2015
// Design Name:
// Module Name: pc_test_circuit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pc_test_circuit(
output [6:0] segdisp,
output [3:0] sel,
// output countornotdisp,
// output countindisp,
// output countin2disp,
input btnup,
input btndown,
input btnleft,
input btnright,
input btnrst,
input clock,
input [7:0] datain
);
wire btnupint, btndownint, btnleftint, btnrightint, btnrstint;
wire [15:0] curpc;
wire [15:0] dataint;
wire aloadint;
wire countornot;
wire countin;
// wire countin2;
wire slowclk2;
// Clock Slower for debouncer circuit.
wire slowclk;
clock_slower #(.WIDTH(19)) slowed_clock(.y(slowclk), .clk(clock));
// Clock Slower for counter circuit. ~1Hz
wire slowclk3;
clock_slower #(.WIDTH(26)) slowed_clock3(.y(slowclk3), .clk(clock));
// Debouncer for five different inputs.
debouncer up(.y(btnupint), .x(btnup), .clk(clock), .clken(slowclk));
debouncer down(.y(btndownint), .x(btndown), .clk(clock), .clken(slowclk));
debouncer left(.y(btnleftint), .x(btnleft), .clk(clock), .clken(slowclk));
debouncer right(.y(btnrightint), .x(btnright), .clk(clock), .clken(slowclk));
debouncer reset(.y(btnrstint), .x(btnrst), .clk(clock), .clken(slowclk));
// Wrap Program Counter
// Load Data
assign dataint = (btnleftint)?({datain,curpc[7:0]}):({curpc[15:8],datain});
assign aloadint = (btnleftint || btnrightint)?(1'b1):(1'b0);
// Use DFF for count and stop.
dff cntornot(.q(countornot), .data(countin), .clk(clock), .reset(btndownint), .set(btnupint));
assign countin = countornot;
// or outor(countin, btnupint, countin2);
// and inneroutand(countin2, ~btndownint, countornot);
// For viewing countornot
// assign countornotdisp = countornot;
// assign countindisp = countin;
// assign countin2disp = countin2;
and andpc_count(slowclk2, slowclk3, countornot);
pc_param #(.SIZE(16)) mypc(.Q(curpc), .clk(clock), .aload(aloadint), .D(dataint), .en(slowclk2), .rst(~btnrstint));
// Seven Segment Display Wrapper
seven_seg_wrapper segwrapper(.segdisplay(segdisp), .segselect(sel), .pcval(curpc), .clock(clock), .enable(slowclk));
endmodule
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module RAM_64Kx8(
SRAM_A,
SRAM_WE_X,
SRAM_OE_X,
SRAM_IO_A,
SRAM_CE_A_X,
SRAM_LB_A_X,
SRAM_UB_A_X,
SRAM_IO_B,
SRAM_CE_B_X,
SRAM_LB_B_X,
SRAM_UB_B_X,
i_addr,
i_enable_x,
i_write_x,
i_data,
o_data);
output [17:0] SRAM_A;
output SRAM_WE_X;
output SRAM_OE_X;
inout [15:0] SRAM_IO_A;
output SRAM_CE_A_X;
output SRAM_LB_A_X;
output SRAM_UB_A_X;
inout [15:0] SRAM_IO_B;
output SRAM_CE_B_X;
output SRAM_LB_B_X;
output SRAM_UB_B_X;
input [15:0] i_addr;
input i_enable_x;
input i_write_x;
input [ 7:0] i_data;
output [ 7:0] o_data;
assign SRAM_A = { 2'b00, i_addr };
assign SRAM_WE_X = i_enable_x | i_write_x;
assign SRAM_OE_X = i_enable_x | !i_write_x;
assign SRAM_IO_A = SRAM_WE_X ? 16'hzzzz : { 8'h00, i_data };
assign SRAM_CE_A_X = i_enable_x;
assign SRAM_LB_A_X = i_enable_x;
assign SRAM_UB_A_X = 1'b1;
assign SRAM_IO_B = 16'hffff;
assign SRAM_CE_B_X = 1'b1;
assign SRAM_LB_B_X = 1'b1;
assign SRAM_UB_B_X = 1'b1;
assign o_data = SRAM_WE_X ? SRAM_IO_A[7:0] : 8'h00;
endmodule // module RAM_64Kx8
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_BLACKBOX_V
`define SKY130_FD_SC_LP__O21A_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21a (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_BLACKBOX_V
|
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 32
module j1b(input wire clk,
input wire resetq,
output wire uart0_wr,
output wire uart0_rd,
output wire [7:0] uart_w,
input wire uart0_valid,
input wire [7:0] uart0_data
);
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
reg [31:0] mem_din;
wire [31:0] dout;
wire [31:0] io_din;
wire [12:0] code_addr;
reg [15:0] insn;
wire [12:0] codeaddr = {1'b0, code_addr[12:1]};
reg [31:0] ram[0:8191] /* verilator public_flat */;
always @(posedge clk) begin
// $display("pc=%x", code_addr * 2);
insn <= code_addr[0] ? ram[codeaddr][31:16] : ram[codeaddr][15:0];
if (mem_wr)
ram[mem_addr[14:2]] <= dout;
mem_din <= ram[mem_addr[14:2]];
end
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.mem_din(mem_din),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn(insn));
// ###### IO SIGNALS ####################################
reg io_wr_, io_rd_;
/* verilator lint_off UNUSED */
reg [31:0] dout_;
reg [15:0] io_addr_;
/* verilator lint_on UNUSED */
always @(posedge clk) begin
{io_rd_, io_wr_, dout_} <= {io_rd, io_wr, dout};
if (io_rd | io_wr)
io_addr_ <= mem_addr;
end
// ###### UART ##########################################
assign uart0_wr = io_wr_ & io_addr_[12];
assign uart0_rd = io_rd_ & io_addr_[12];
assign uart_w = dout_[7:0];
// always @(posedge clk) begin
// if (uart0_wr)
// $display("--- out %x %c", uart_w, uart_w);
// if (uart0_rd)
// $display("--- in %x %c", uart0_data, uart0_data);
// end
// ###### IO PORTS ######################################
/* bit READ WRITE
1000 12 UART RX UART TX
2000 13 misc.in
*/
assign io_din =
(io_addr_[12] ? {24'd0, uart0_data} : 32'd0) |
(io_addr_[13] ? {28'd0, 1'b0, 1'b0, uart0_valid, 1'b1} : 32'd0);
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_hart0_server_reset_request_put O 1 reg
// hart0_server_reset_response_get O 1 reg
// RDY_hart0_server_reset_response_get O 1 reg
// imem_master_awvalid O 1 reg
// imem_master_awid O 4 reg
// imem_master_awaddr O 64 reg
// imem_master_awlen O 8 reg
// imem_master_awsize O 3 reg
// imem_master_awburst O 2 reg
// imem_master_awlock O 1 reg
// imem_master_awcache O 4 reg
// imem_master_awprot O 3 reg
// imem_master_awqos O 4 reg
// imem_master_awregion O 4 reg
// imem_master_wvalid O 1 reg
// imem_master_wdata O 64 reg
// imem_master_wstrb O 8 reg
// imem_master_wlast O 1 reg
// imem_master_bready O 1 reg
// imem_master_arvalid O 1 reg
// imem_master_arid O 4 reg
// imem_master_araddr O 64 reg
// imem_master_arlen O 8 reg
// imem_master_arsize O 3 reg
// imem_master_arburst O 2 reg
// imem_master_arlock O 1 reg
// imem_master_arcache O 4 reg
// imem_master_arprot O 3 reg
// imem_master_arqos O 4 reg
// imem_master_arregion O 4 reg
// imem_master_rready O 1 reg
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// dma_server_awready O 1 const
// dma_server_wready O 1 const
// dma_server_bvalid O 1 const
// dma_server_bid O 6 const
// dma_server_bresp O 2 const
// dma_server_arready O 1 const
// dma_server_rvalid O 1 const
// dma_server_rid O 6 const
// dma_server_rdata O 512 const
// dma_server_rresp O 2 const
// dma_server_rlast O 1 const
// RDY_set_verbosity O 1 const
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// hart0_server_reset_request_put I 1 reg
// imem_master_awready I 1
// imem_master_wready I 1
// imem_master_bvalid I 1
// imem_master_bid I 4 reg
// imem_master_bresp I 2 reg
// imem_master_arready I 1
// imem_master_rvalid I 1
// imem_master_rid I 4 reg
// imem_master_rdata I 64 reg
// imem_master_rresp I 2 reg
// imem_master_rlast I 1 reg
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// dma_server_awvalid I 1 unused
// dma_server_awid I 6 unused
// dma_server_awaddr I 64 unused
// dma_server_awlen I 8 unused
// dma_server_awsize I 3 unused
// dma_server_awburst I 2 unused
// dma_server_awlock I 1 unused
// dma_server_awcache I 4 unused
// dma_server_awprot I 3 unused
// dma_server_awqos I 4 unused
// dma_server_awregion I 4 unused
// dma_server_wvalid I 1 unused
// dma_server_wdata I 512 unused
// dma_server_wstrb I 64 unused
// dma_server_wlast I 1 unused
// dma_server_bready I 1 unused
// dma_server_arvalid I 1 unused
// dma_server_arid I 6 unused
// dma_server_araddr I 64 unused
// dma_server_arlen I 8 unused
// dma_server_arsize I 3 unused
// dma_server_arburst I 2 unused
// dma_server_arlock I 1 unused
// dma_server_arcache I 4 unused
// dma_server_arprot I 3 unused
// dma_server_arqos I 4 unused
// dma_server_arregion I 4 unused
// dma_server_rready I 1 unused
// m_external_interrupt_req_set_not_clear I 1 reg
// s_external_interrupt_req_set_not_clear I 1 reg
// software_interrupt_req_set_not_clear I 1 reg
// timer_interrupt_req_set_not_clear I 1 reg
// nmi_req_set_not_clear I 1
// set_verbosity_verbosity I 4 reg
// set_verbosity_logdelay I 64 reg
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_hart0_server_reset_request_put I 1
// EN_set_verbosity I 1
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
// EN_hart0_server_reset_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCPU(CLK,
RST_N,
hart0_server_reset_request_put,
EN_hart0_server_reset_request_put,
RDY_hart0_server_reset_request_put,
EN_hart0_server_reset_response_get,
hart0_server_reset_response_get,
RDY_hart0_server_reset_response_get,
imem_master_awvalid,
imem_master_awid,
imem_master_awaddr,
imem_master_awlen,
imem_master_awsize,
imem_master_awburst,
imem_master_awlock,
imem_master_awcache,
imem_master_awprot,
imem_master_awqos,
imem_master_awregion,
imem_master_awready,
imem_master_wvalid,
imem_master_wdata,
imem_master_wstrb,
imem_master_wlast,
imem_master_wready,
imem_master_bvalid,
imem_master_bid,
imem_master_bresp,
imem_master_bready,
imem_master_arvalid,
imem_master_arid,
imem_master_araddr,
imem_master_arlen,
imem_master_arsize,
imem_master_arburst,
imem_master_arlock,
imem_master_arcache,
imem_master_arprot,
imem_master_arqos,
imem_master_arregion,
imem_master_arready,
imem_master_rvalid,
imem_master_rid,
imem_master_rdata,
imem_master_rresp,
imem_master_rlast,
imem_master_rready,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready,
dma_server_awvalid,
dma_server_awid,
dma_server_awaddr,
dma_server_awlen,
dma_server_awsize,
dma_server_awburst,
dma_server_awlock,
dma_server_awcache,
dma_server_awprot,
dma_server_awqos,
dma_server_awregion,
dma_server_awready,
dma_server_wvalid,
dma_server_wdata,
dma_server_wstrb,
dma_server_wlast,
dma_server_wready,
dma_server_bvalid,
dma_server_bid,
dma_server_bresp,
dma_server_bready,
dma_server_arvalid,
dma_server_arid,
dma_server_araddr,
dma_server_arlen,
dma_server_arsize,
dma_server_arburst,
dma_server_arlock,
dma_server_arcache,
dma_server_arprot,
dma_server_arqos,
dma_server_arregion,
dma_server_arready,
dma_server_rvalid,
dma_server_rid,
dma_server_rdata,
dma_server_rresp,
dma_server_rlast,
dma_server_rready,
m_external_interrupt_req_set_not_clear,
s_external_interrupt_req_set_not_clear,
software_interrupt_req_set_not_clear,
timer_interrupt_req_set_not_clear,
nmi_req_set_not_clear,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
input CLK;
input RST_N;
// action method hart0_server_reset_request_put
input hart0_server_reset_request_put;
input EN_hart0_server_reset_request_put;
output RDY_hart0_server_reset_request_put;
// actionvalue method hart0_server_reset_response_get
input EN_hart0_server_reset_response_get;
output hart0_server_reset_response_get;
output RDY_hart0_server_reset_response_get;
// value method imem_master_m_awvalid
output imem_master_awvalid;
// value method imem_master_m_awid
output [3 : 0] imem_master_awid;
// value method imem_master_m_awaddr
output [63 : 0] imem_master_awaddr;
// value method imem_master_m_awlen
output [7 : 0] imem_master_awlen;
// value method imem_master_m_awsize
output [2 : 0] imem_master_awsize;
// value method imem_master_m_awburst
output [1 : 0] imem_master_awburst;
// value method imem_master_m_awlock
output imem_master_awlock;
// value method imem_master_m_awcache
output [3 : 0] imem_master_awcache;
// value method imem_master_m_awprot
output [2 : 0] imem_master_awprot;
// value method imem_master_m_awqos
output [3 : 0] imem_master_awqos;
// value method imem_master_m_awregion
output [3 : 0] imem_master_awregion;
// value method imem_master_m_awuser
// action method imem_master_m_awready
input imem_master_awready;
// value method imem_master_m_wvalid
output imem_master_wvalid;
// value method imem_master_m_wdata
output [63 : 0] imem_master_wdata;
// value method imem_master_m_wstrb
output [7 : 0] imem_master_wstrb;
// value method imem_master_m_wlast
output imem_master_wlast;
// value method imem_master_m_wuser
// action method imem_master_m_wready
input imem_master_wready;
// action method imem_master_m_bvalid
input imem_master_bvalid;
input [3 : 0] imem_master_bid;
input [1 : 0] imem_master_bresp;
// value method imem_master_m_bready
output imem_master_bready;
// value method imem_master_m_arvalid
output imem_master_arvalid;
// value method imem_master_m_arid
output [3 : 0] imem_master_arid;
// value method imem_master_m_araddr
output [63 : 0] imem_master_araddr;
// value method imem_master_m_arlen
output [7 : 0] imem_master_arlen;
// value method imem_master_m_arsize
output [2 : 0] imem_master_arsize;
// value method imem_master_m_arburst
output [1 : 0] imem_master_arburst;
// value method imem_master_m_arlock
output imem_master_arlock;
// value method imem_master_m_arcache
output [3 : 0] imem_master_arcache;
// value method imem_master_m_arprot
output [2 : 0] imem_master_arprot;
// value method imem_master_m_arqos
output [3 : 0] imem_master_arqos;
// value method imem_master_m_arregion
output [3 : 0] imem_master_arregion;
// value method imem_master_m_aruser
// action method imem_master_m_arready
input imem_master_arready;
// action method imem_master_m_rvalid
input imem_master_rvalid;
input [3 : 0] imem_master_rid;
input [63 : 0] imem_master_rdata;
input [1 : 0] imem_master_rresp;
input imem_master_rlast;
// value method imem_master_m_rready
output imem_master_rready;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// action method dma_server_m_awvalid
input dma_server_awvalid;
input [5 : 0] dma_server_awid;
input [63 : 0] dma_server_awaddr;
input [7 : 0] dma_server_awlen;
input [2 : 0] dma_server_awsize;
input [1 : 0] dma_server_awburst;
input dma_server_awlock;
input [3 : 0] dma_server_awcache;
input [2 : 0] dma_server_awprot;
input [3 : 0] dma_server_awqos;
input [3 : 0] dma_server_awregion;
// value method dma_server_m_awready
output dma_server_awready;
// action method dma_server_m_wvalid
input dma_server_wvalid;
input [511 : 0] dma_server_wdata;
input [63 : 0] dma_server_wstrb;
input dma_server_wlast;
// value method dma_server_m_wready
output dma_server_wready;
// value method dma_server_m_bvalid
output dma_server_bvalid;
// value method dma_server_m_bid
output [5 : 0] dma_server_bid;
// value method dma_server_m_bresp
output [1 : 0] dma_server_bresp;
// value method dma_server_m_buser
// action method dma_server_m_bready
input dma_server_bready;
// action method dma_server_m_arvalid
input dma_server_arvalid;
input [5 : 0] dma_server_arid;
input [63 : 0] dma_server_araddr;
input [7 : 0] dma_server_arlen;
input [2 : 0] dma_server_arsize;
input [1 : 0] dma_server_arburst;
input dma_server_arlock;
input [3 : 0] dma_server_arcache;
input [2 : 0] dma_server_arprot;
input [3 : 0] dma_server_arqos;
input [3 : 0] dma_server_arregion;
// value method dma_server_m_arready
output dma_server_arready;
// value method dma_server_m_rvalid
output dma_server_rvalid;
// value method dma_server_m_rid
output [5 : 0] dma_server_rid;
// value method dma_server_m_rdata
output [511 : 0] dma_server_rdata;
// value method dma_server_m_rresp
output [1 : 0] dma_server_rresp;
// value method dma_server_m_rlast
output dma_server_rlast;
// value method dma_server_m_ruser
// action method dma_server_m_rready
input dma_server_rready;
// action method m_external_interrupt_req
input m_external_interrupt_req_set_not_clear;
// action method s_external_interrupt_req
input s_external_interrupt_req_set_not_clear;
// action method software_interrupt_req
input software_interrupt_req_set_not_clear;
// action method timer_interrupt_req
input timer_interrupt_req_set_not_clear;
// action method nmi_req
input nmi_req_set_not_clear;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] imem_master_araddr,
imem_master_awaddr,
imem_master_wdata,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value;
wire [7 : 0] imem_master_arlen,
imem_master_awlen,
imem_master_wstrb,
mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [5 : 0] dma_server_bid, dma_server_rid;
wire [3 : 0] imem_master_arcache,
imem_master_arid,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awid,
imem_master_awqos,
imem_master_awregion,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize,
mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] dma_server_bresp,
dma_server_rresp,
imem_master_arburst,
imem_master_awburst,
mem_master_arburst,
mem_master_awburst;
wire RDY_hart0_server_reset_request_put,
RDY_hart0_server_reset_response_get,
RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_set_verbosity,
RDY_set_watch_tohost,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready,
hart0_server_reset_response_get,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid;
// register cfg_logdelay
reg [63 : 0] cfg_logdelay;
wire [63 : 0] cfg_logdelay$D_IN;
wire cfg_logdelay$EN;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register imem_rg_cache_addr
reg [31 : 0] imem_rg_cache_addr;
reg [31 : 0] imem_rg_cache_addr$D_IN;
wire imem_rg_cache_addr$EN;
// register imem_rg_cache_b16
reg [15 : 0] imem_rg_cache_b16;
wire [15 : 0] imem_rg_cache_b16$D_IN;
wire imem_rg_cache_b16$EN;
// register imem_rg_f3
reg [2 : 0] imem_rg_f3;
wire [2 : 0] imem_rg_f3$D_IN;
wire imem_rg_f3$EN;
// register imem_rg_mstatus_MXR
reg imem_rg_mstatus_MXR;
wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;
// register imem_rg_pc
reg [31 : 0] imem_rg_pc;
reg [31 : 0] imem_rg_pc$D_IN;
wire imem_rg_pc$EN;
// register imem_rg_priv
reg [1 : 0] imem_rg_priv;
wire [1 : 0] imem_rg_priv$D_IN;
wire imem_rg_priv$EN;
// register imem_rg_satp
reg [31 : 0] imem_rg_satp;
wire [31 : 0] imem_rg_satp$D_IN;
wire imem_rg_satp$EN;
// register imem_rg_sstatus_SUM
reg imem_rg_sstatus_SUM;
wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;
// register imem_rg_tval
reg [31 : 0] imem_rg_tval;
reg [31 : 0] imem_rg_tval$D_IN;
wire imem_rg_tval$EN;
// register rg_csr_pc
reg [31 : 0] rg_csr_pc;
wire [31 : 0] rg_csr_pc$D_IN;
wire rg_csr_pc$EN;
// register rg_csr_val1
reg [31 : 0] rg_csr_val1;
wire [31 : 0] rg_csr_val1$D_IN;
wire rg_csr_val1$EN;
// register rg_cur_priv
reg [1 : 0] rg_cur_priv;
reg [1 : 0] rg_cur_priv$D_IN;
wire rg_cur_priv$EN;
// register rg_epoch
reg [1 : 0] rg_epoch;
reg [1 : 0] rg_epoch$D_IN;
wire rg_epoch$EN;
// register rg_mstatus_MXR
reg rg_mstatus_MXR;
wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;
// register rg_next_pc
reg [31 : 0] rg_next_pc;
reg [31 : 0] rg_next_pc$D_IN;
wire rg_next_pc$EN;
// register rg_run_on_reset
reg rg_run_on_reset;
wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;
// register rg_sstatus_SUM
reg rg_sstatus_SUM;
wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;
// register rg_start_CPI_cycles
reg [63 : 0] rg_start_CPI_cycles;
wire [63 : 0] rg_start_CPI_cycles$D_IN;
wire rg_start_CPI_cycles$EN;
// register rg_start_CPI_instrs
reg [63 : 0] rg_start_CPI_instrs;
wire [63 : 0] rg_start_CPI_instrs$D_IN;
wire rg_start_CPI_instrs$EN;
// register rg_state
reg [3 : 0] rg_state;
reg [3 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_trap_info
reg [67 : 0] rg_trap_info;
reg [67 : 0] rg_trap_info$D_IN;
wire rg_trap_info$EN;
// register rg_trap_instr
reg [31 : 0] rg_trap_instr;
wire [31 : 0] rg_trap_instr$D_IN;
wire rg_trap_instr$EN;
// register rg_trap_interrupt
reg rg_trap_interrupt;
wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;
// register stage1_rg_full
reg stage1_rg_full;
reg stage1_rg_full$D_IN;
wire stage1_rg_full$EN;
// register stage1_rg_stage_input
reg [305 : 0] stage1_rg_stage_input;
wire [305 : 0] stage1_rg_stage_input$D_IN;
wire stage1_rg_stage_input$EN;
// register stage2_rg_full
reg stage2_rg_full;
reg stage2_rg_full$D_IN;
wire stage2_rg_full$EN;
// register stage2_rg_resetting
reg stage2_rg_resetting;
wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;
// register stage2_rg_stage2
reg [168 : 0] stage2_rg_stage2;
wire [168 : 0] stage2_rg_stage2$D_IN;
wire stage2_rg_stage2$EN;
// register stage3_rg_full
reg stage3_rg_full;
reg stage3_rg_full$D_IN;
wire stage3_rg_full$EN;
// register stage3_rg_stage3
reg [103 : 0] stage3_rg_stage3;
wire [103 : 0] stage3_rg_stage3$D_IN;
wire stage3_rg_stage3$EN;
// register stageD_rg_data
reg [137 : 0] stageD_rg_data;
wire [137 : 0] stageD_rg_data$D_IN;
wire stageD_rg_data$EN;
// register stageD_rg_full
reg stageD_rg_full;
reg stageD_rg_full$D_IN;
wire stageD_rg_full$EN;
// register stageF_rg_epoch
reg [1 : 0] stageF_rg_epoch;
reg [1 : 0] stageF_rg_epoch$D_IN;
wire stageF_rg_epoch$EN;
// register stageF_rg_full
reg stageF_rg_full;
reg stageF_rg_full$D_IN;
wire stageF_rg_full$EN;
// register stageF_rg_priv
reg [1 : 0] stageF_rg_priv;
wire [1 : 0] stageF_rg_priv$D_IN;
wire stageF_rg_priv$EN;
// ports of submodule csr_regfile
reg [1 : 0] csr_regfile$csr_ret_actions_from_priv;
wire [97 : 0] csr_regfile$csr_trap_actions;
wire [65 : 0] csr_regfile$csr_ret_actions;
wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret;
wire [32 : 0] csr_regfile$read_csr;
wire [31 : 0] csr_regfile$csr_trap_actions_pc,
csr_regfile$csr_trap_actions_xtval,
csr_regfile$mav_csr_write_word,
csr_regfile$read_mstatus,
csr_regfile$read_satp;
wire [27 : 0] csr_regfile$read_misa;
wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
csr_regfile$access_permitted_2_csr_addr,
csr_regfile$csr_counter_read_fault_csr_addr,
csr_regfile$mav_csr_write_csr_addr,
csr_regfile$mav_read_csr_csr_addr,
csr_regfile$read_csr_csr_addr,
csr_regfile$read_csr_port2_csr_addr;
wire [4 : 0] csr_regfile$interrupt_pending;
wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
wire [1 : 0] csr_regfile$access_permitted_1_priv,
csr_regfile$access_permitted_2_priv,
csr_regfile$csr_counter_read_fault_priv,
csr_regfile$csr_trap_actions_from_priv,
csr_regfile$interrupt_pending_cur_priv;
wire csr_regfile$EN_csr_minstret_incr,
csr_regfile$EN_csr_ret_actions,
csr_regfile$EN_csr_trap_actions,
csr_regfile$EN_debug,
csr_regfile$EN_mav_csr_write,
csr_regfile$EN_mav_read_csr,
csr_regfile$EN_server_reset_request_put,
csr_regfile$EN_server_reset_response_get,
csr_regfile$RDY_server_reset_request_put,
csr_regfile$RDY_server_reset_response_get,
csr_regfile$access_permitted_1,
csr_regfile$access_permitted_1_read_not_write,
csr_regfile$access_permitted_2,
csr_regfile$access_permitted_2_read_not_write,
csr_regfile$csr_trap_actions_interrupt,
csr_regfile$csr_trap_actions_nmi,
csr_regfile$m_external_interrupt_req_set_not_clear,
csr_regfile$nmi_pending,
csr_regfile$nmi_req_set_not_clear,
csr_regfile$s_external_interrupt_req_set_not_clear,
csr_regfile$software_interrupt_req_set_not_clear,
csr_regfile$timer_interrupt_req_set_not_clear,
csr_regfile$wfi_resume;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule gpr_regfile
wire [31 : 0] gpr_regfile$read_rs1,
gpr_regfile$read_rs2,
gpr_regfile$write_rd_rd_val;
wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
gpr_regfile$read_rs1_rs1,
gpr_regfile$read_rs2_rs2,
gpr_regfile$write_rd_rd;
wire gpr_regfile$EN_server_reset_request_put,
gpr_regfile$EN_server_reset_response_get,
gpr_regfile$EN_write_rd,
gpr_regfile$RDY_server_reset_request_put,
gpr_regfile$RDY_server_reset_response_get;
// ports of submodule near_mem
reg [31 : 0] near_mem$imem_req_addr;
wire [511 : 0] near_mem$dma_server_rdata, near_mem$dma_server_wdata;
wire [63 : 0] near_mem$dma_server_araddr,
near_mem$dma_server_awaddr,
near_mem$dma_server_wstrb,
near_mem$dmem_req_store_value,
near_mem$dmem_word64,
near_mem$imem_master_araddr,
near_mem$imem_master_awaddr,
near_mem$imem_master_rdata,
near_mem$imem_master_wdata,
near_mem$mem_master_araddr,
near_mem$mem_master_awaddr,
near_mem$mem_master_rdata,
near_mem$mem_master_wdata,
near_mem$mv_tohost_value,
near_mem$set_watch_tohost_tohost_addr;
wire [31 : 0] near_mem$dmem_req_addr,
near_mem$dmem_req_satp,
near_mem$imem_instr,
near_mem$imem_pc,
near_mem$imem_req_satp;
wire [7 : 0] near_mem$dma_server_arlen,
near_mem$dma_server_awlen,
near_mem$imem_master_arlen,
near_mem$imem_master_awlen,
near_mem$imem_master_wstrb,
near_mem$mem_master_arlen,
near_mem$mem_master_awlen,
near_mem$mem_master_wstrb,
near_mem$mv_status,
near_mem$server_fence_request_put;
wire [5 : 0] near_mem$dma_server_arid,
near_mem$dma_server_awid,
near_mem$dma_server_bid,
near_mem$dma_server_rid;
wire [3 : 0] near_mem$dma_server_arcache,
near_mem$dma_server_arqos,
near_mem$dma_server_arregion,
near_mem$dma_server_awcache,
near_mem$dma_server_awqos,
near_mem$dma_server_awregion,
near_mem$dmem_exc_code,
near_mem$imem_exc_code,
near_mem$imem_master_arcache,
near_mem$imem_master_arid,
near_mem$imem_master_arqos,
near_mem$imem_master_arregion,
near_mem$imem_master_awcache,
near_mem$imem_master_awid,
near_mem$imem_master_awqos,
near_mem$imem_master_awregion,
near_mem$imem_master_bid,
near_mem$imem_master_rid,
near_mem$mem_master_arcache,
near_mem$mem_master_arid,
near_mem$mem_master_arqos,
near_mem$mem_master_arregion,
near_mem$mem_master_awcache,
near_mem$mem_master_awid,
near_mem$mem_master_awqos,
near_mem$mem_master_awregion,
near_mem$mem_master_bid,
near_mem$mem_master_rid;
wire [2 : 0] near_mem$dma_server_arprot,
near_mem$dma_server_arsize,
near_mem$dma_server_awprot,
near_mem$dma_server_awsize,
near_mem$dmem_req_f3,
near_mem$imem_master_arprot,
near_mem$imem_master_arsize,
near_mem$imem_master_awprot,
near_mem$imem_master_awsize,
near_mem$imem_req_f3,
near_mem$mem_master_arprot,
near_mem$mem_master_arsize,
near_mem$mem_master_awprot,
near_mem$mem_master_awsize;
wire [1 : 0] near_mem$dma_server_arburst,
near_mem$dma_server_awburst,
near_mem$dma_server_bresp,
near_mem$dma_server_rresp,
near_mem$dmem_req_priv,
near_mem$imem_master_arburst,
near_mem$imem_master_awburst,
near_mem$imem_master_bresp,
near_mem$imem_master_rresp,
near_mem$imem_req_priv,
near_mem$mem_master_arburst,
near_mem$mem_master_awburst,
near_mem$mem_master_bresp,
near_mem$mem_master_rresp;
wire near_mem$EN_dmem_req,
near_mem$EN_imem_req,
near_mem$EN_ma_ddr4_ready,
near_mem$EN_server_fence_i_request_put,
near_mem$EN_server_fence_i_response_get,
near_mem$EN_server_fence_request_put,
near_mem$EN_server_fence_response_get,
near_mem$EN_server_reset_request_put,
near_mem$EN_server_reset_response_get,
near_mem$EN_set_watch_tohost,
near_mem$RDY_server_fence_i_request_put,
near_mem$RDY_server_fence_i_response_get,
near_mem$RDY_server_fence_request_put,
near_mem$RDY_server_fence_response_get,
near_mem$RDY_server_reset_request_put,
near_mem$RDY_server_reset_response_get,
near_mem$dma_server_arlock,
near_mem$dma_server_arready,
near_mem$dma_server_arvalid,
near_mem$dma_server_awlock,
near_mem$dma_server_awready,
near_mem$dma_server_awvalid,
near_mem$dma_server_bready,
near_mem$dma_server_bvalid,
near_mem$dma_server_rlast,
near_mem$dma_server_rready,
near_mem$dma_server_rvalid,
near_mem$dma_server_wlast,
near_mem$dma_server_wready,
near_mem$dma_server_wvalid,
near_mem$dmem_exc,
near_mem$dmem_req_mstatus_MXR,
near_mem$dmem_req_op,
near_mem$dmem_req_sstatus_SUM,
near_mem$dmem_valid,
near_mem$imem_exc,
near_mem$imem_is_i32_not_i16,
near_mem$imem_master_arlock,
near_mem$imem_master_arready,
near_mem$imem_master_arvalid,
near_mem$imem_master_awlock,
near_mem$imem_master_awready,
near_mem$imem_master_awvalid,
near_mem$imem_master_bready,
near_mem$imem_master_bvalid,
near_mem$imem_master_rlast,
near_mem$imem_master_rready,
near_mem$imem_master_rvalid,
near_mem$imem_master_wlast,
near_mem$imem_master_wready,
near_mem$imem_master_wvalid,
near_mem$imem_req_mstatus_MXR,
near_mem$imem_req_sstatus_SUM,
near_mem$imem_valid,
near_mem$mem_master_arlock,
near_mem$mem_master_arready,
near_mem$mem_master_arvalid,
near_mem$mem_master_awlock,
near_mem$mem_master_awready,
near_mem$mem_master_awvalid,
near_mem$mem_master_bready,
near_mem$mem_master_bvalid,
near_mem$mem_master_rlast,
near_mem$mem_master_rready,
near_mem$mem_master_rvalid,
near_mem$mem_master_wlast,
near_mem$mem_master_wready,
near_mem$mem_master_wvalid,
near_mem$set_watch_tohost_watch_tohost;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_pc_reset_value;
// ports of submodule stage1_f_reset_reqs
wire stage1_f_reset_reqs$CLR,
stage1_f_reset_reqs$DEQ,
stage1_f_reset_reqs$EMPTY_N,
stage1_f_reset_reqs$ENQ,
stage1_f_reset_reqs$FULL_N;
// ports of submodule stage1_f_reset_rsps
wire stage1_f_reset_rsps$CLR,
stage1_f_reset_rsps$DEQ,
stage1_f_reset_rsps$EMPTY_N,
stage1_f_reset_rsps$ENQ,
stage1_f_reset_rsps$FULL_N;
// ports of submodule stage2_f_reset_reqs
wire stage2_f_reset_reqs$CLR,
stage2_f_reset_reqs$DEQ,
stage2_f_reset_reqs$EMPTY_N,
stage2_f_reset_reqs$ENQ,
stage2_f_reset_reqs$FULL_N;
// ports of submodule stage2_f_reset_rsps
wire stage2_f_reset_rsps$CLR,
stage2_f_reset_rsps$DEQ,
stage2_f_reset_rsps$EMPTY_N,
stage2_f_reset_rsps$ENQ,
stage2_f_reset_rsps$FULL_N;
// ports of submodule stage3_f_reset_reqs
wire stage3_f_reset_reqs$CLR,
stage3_f_reset_reqs$DEQ,
stage3_f_reset_reqs$EMPTY_N,
stage3_f_reset_reqs$ENQ,
stage3_f_reset_reqs$FULL_N;
// ports of submodule stage3_f_reset_rsps
wire stage3_f_reset_rsps$CLR,
stage3_f_reset_rsps$DEQ,
stage3_f_reset_rsps$EMPTY_N,
stage3_f_reset_rsps$ENQ,
stage3_f_reset_rsps$FULL_N;
// ports of submodule stageD_f_reset_reqs
wire stageD_f_reset_reqs$CLR,
stageD_f_reset_reqs$DEQ,
stageD_f_reset_reqs$EMPTY_N,
stageD_f_reset_reqs$ENQ,
stageD_f_reset_reqs$FULL_N;
// ports of submodule stageD_f_reset_rsps
wire stageD_f_reset_rsps$CLR,
stageD_f_reset_rsps$DEQ,
stageD_f_reset_rsps$EMPTY_N,
stageD_f_reset_rsps$ENQ,
stageD_f_reset_rsps$FULL_N;
// ports of submodule stageF_branch_predictor
reg [31 : 0] stageF_branch_predictor$predict_req_pc;
wire [98 : 0] stageF_branch_predictor$bp_train_cf_info;
wire [31 : 0] stageF_branch_predictor$bp_train_instr,
stageF_branch_predictor$bp_train_pc,
stageF_branch_predictor$predict_rsp,
stageF_branch_predictor$predict_rsp_instr;
wire stageF_branch_predictor$EN_bp_train,
stageF_branch_predictor$EN_predict_req,
stageF_branch_predictor$EN_reset,
stageF_branch_predictor$RDY_predict_req,
stageF_branch_predictor$bp_train_is_i32_not_i16,
stageF_branch_predictor$predict_rsp_is_i32_not_i16;
// ports of submodule stageF_f_reset_reqs
wire stageF_f_reset_reqs$CLR,
stageF_f_reset_reqs$DEQ,
stageF_f_reset_reqs$EMPTY_N,
stageF_f_reset_reqs$ENQ,
stageF_f_reset_reqs$FULL_N;
// ports of submodule stageF_f_reset_rsps
wire stageF_f_reset_rsps$CLR,
stageF_f_reset_rsps$DEQ,
stageF_f_reset_rsps$EMPTY_N,
stageF_f_reset_rsps$ENQ,
stageF_f_reset_rsps$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_imem_rl_assert_fail,
CAN_FIRE_RL_imem_rl_fetch_next_32b,
CAN_FIRE_RL_rl_WFI_resume,
CAN_FIRE_RL_rl_finish_FENCE,
CAN_FIRE_RL_rl_finish_FENCE_I,
CAN_FIRE_RL_rl_pipe,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_RL_rl_reset_from_WFI,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_RL_rl_show_pipe,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
CAN_FIRE_RL_rl_stage1_CSRR_W,
CAN_FIRE_RL_rl_stage1_CSRR_W_2,
CAN_FIRE_RL_rl_stage1_FENCE,
CAN_FIRE_RL_rl_stage1_FENCE_I,
CAN_FIRE_RL_rl_stage1_WFI,
CAN_FIRE_RL_rl_stage1_interrupt,
CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
CAN_FIRE_RL_rl_stage1_trap,
CAN_FIRE_RL_rl_stage1_xRET,
CAN_FIRE_RL_rl_stage2_nonpipe,
CAN_FIRE_RL_rl_trap,
CAN_FIRE_RL_rl_trap_fetch,
CAN_FIRE_RL_stage1_rl_reset,
CAN_FIRE_RL_stage2_rl_reset_begin,
CAN_FIRE_RL_stage2_rl_reset_end,
CAN_FIRE_RL_stage3_rl_reset,
CAN_FIRE_RL_stageD_rl_reset,
CAN_FIRE_RL_stageF_rl_reset,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_hart0_server_reset_request_put,
CAN_FIRE_hart0_server_reset_response_get,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_nmi_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_RL_imem_rl_assert_fail,
WILL_FIRE_RL_imem_rl_fetch_next_32b,
WILL_FIRE_RL_rl_WFI_resume,
WILL_FIRE_RL_rl_finish_FENCE,
WILL_FIRE_RL_rl_finish_FENCE_I,
WILL_FIRE_RL_rl_pipe,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_RL_rl_reset_from_WFI,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_RL_rl_show_pipe,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
WILL_FIRE_RL_rl_stage1_CSRR_W,
WILL_FIRE_RL_rl_stage1_CSRR_W_2,
WILL_FIRE_RL_rl_stage1_FENCE,
WILL_FIRE_RL_rl_stage1_FENCE_I,
WILL_FIRE_RL_rl_stage1_WFI,
WILL_FIRE_RL_rl_stage1_interrupt,
WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
WILL_FIRE_RL_rl_stage1_trap,
WILL_FIRE_RL_rl_stage1_xRET,
WILL_FIRE_RL_rl_stage2_nonpipe,
WILL_FIRE_RL_rl_trap,
WILL_FIRE_RL_rl_trap_fetch,
WILL_FIRE_RL_stage1_rl_reset,
WILL_FIRE_RL_stage2_rl_reset_begin,
WILL_FIRE_RL_stage2_rl_reset_end,
WILL_FIRE_RL_stage3_rl_reset,
WILL_FIRE_RL_stageD_rl_reset,
WILL_FIRE_RL_stageF_rl_reset,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_hart0_server_reset_request_put,
WILL_FIRE_hart0_server_reset_response_get,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_nmi_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// inputs to muxes for submodule ports
reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
wire [67 : 0] MUX_rg_trap_info$write_1__VAL_1,
MUX_rg_trap_info$write_1__VAL_2,
MUX_rg_trap_info$write_1__VAL_3,
MUX_rg_trap_info$write_1__VAL_4;
wire [31 : 0] MUX_imem_rg_cache_addr$write_1__VAL_1,
MUX_imem_rg_cache_addr$write_1__VAL_2,
MUX_imem_rg_tval$write_1__VAL_1,
MUX_imem_rg_tval$write_1__VAL_2,
MUX_imem_rg_tval$write_1__VAL_3,
MUX_imem_rg_tval$write_1__VAL_4,
MUX_near_mem$imem_req_2__VAL_1,
MUX_near_mem$imem_req_2__VAL_2,
MUX_near_mem$imem_req_2__VAL_4,
MUX_rg_trap_instr$write_1__VAL_1;
wire [3 : 0] MUX_rg_state$write_1__VAL_2,
MUX_rg_state$write_1__VAL_3,
MUX_rg_state$write_1__VAL_4;
wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
MUX_gpr_regfile$write_rd_1__SEL_3,
MUX_imem_rg_cache_addr$write_1__SEL_1,
MUX_imem_rg_cache_addr$write_1__SEL_2,
MUX_rg_next_pc$write_1__SEL_1,
MUX_rg_next_pc$write_1__SEL_2,
MUX_rg_state$write_1__SEL_1,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_5,
MUX_rg_state$write_1__SEL_7,
MUX_rg_state$write_1__SEL_8,
MUX_rg_state$write_1__SEL_9,
MUX_rg_trap_info$write_1__SEL_1,
MUX_rg_trap_instr$write_1__SEL_1,
MUX_rg_trap_interrupt$write_1__SEL_1,
MUX_stage1_rg_full$write_1__VAL_2,
MUX_stage2_rg_full$write_1__VAL_2,
MUX_stageD_rg_full$write_1__VAL_2,
MUX_stageF_rg_full$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h2516;
reg [31 : 0] v__h2510;
// synopsys translate_on
// remaining internal signals
reg [31 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15,
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d640,
_theResult_____1_fst__h8891,
rs1_val__h22768,
x_out_cf_info_taken_PC__h9558,
x_out_data_to_stage2_addr__h7929,
x_out_data_to_stage2_val1__h7930,
x_out_data_to_stage3_rd_val__h7355;
reg [4 : 0] x_out_data_to_stage3_rd__h7354;
reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q3,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q10,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q11,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q9,
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q12,
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4,
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412,
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d415,
alu_outputs_exc_code__h8498;
reg [1 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q16,
CASE_stage2_rg_stage2_BITS_102_TO_101_0_2_1_IF_ETC__q5,
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500;
reg CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q7,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8,
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263,
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316;
wire [127 : 0] csr_regfile_read_csr_mcycle__3_MINUS_rg_start__ETC___d1548;
wire [63 : 0] _theResult____h21609,
cpi__h21611,
cpifrac__h21612,
delta_CPI_cycles__h21607,
delta_CPI_instrs___1__h21644,
delta_CPI_instrs__h21608,
x__h21610;
wire [31 : 0] IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1095,
IF_csr_regfile_read_csr_rg_trap_instr_545_BITS_ETC___d1598,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d947,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d949,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d951,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d952,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d954,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d955,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d956,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d958,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d959,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d960,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d962,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d963,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d964,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d965,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d966,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d967,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d968,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d969,
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d970,
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1096,
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d641,
SEXT_stage1_rg_stage_input_88_BITS_87_TO_76_80___d528,
_theResult_____1_fst__h8884,
_theResult_____1_fst__h8919,
_theResult____h5412,
_theResult___snd__h9864,
addr_of_b32___1__h17506,
addr_of_b32___1__h20531,
addr_of_b32___1__h28726,
addr_of_b32__h17387,
addr_of_b32__h20412,
addr_of_b32__h28607,
alu_outputs___1_addr__h8084,
alu_outputs___1_addr__h8290,
alu_outputs___1_val1__h8187,
alu_outputs___1_val1__h8223,
alu_outputs___1_val1__h8483,
alu_outputs_cf_info_fallthru_PC__h9549,
alu_outputs_cf_info_taken_PC__h9550,
branch_target__h8061,
d_instr__h15539,
data_to_stage2_addr__h7919,
eaddr__h8260,
fall_through_pc__h7869,
instr___1__h10091,
instr__h10256,
instr__h10401,
instr__h10593,
instr__h10788,
instr__h11017,
instr__h11360,
instr__h11750,
instr__h11866,
instr__h11931,
instr__h12248,
instr__h12586,
instr__h12770,
instr__h12899,
instr__h13336,
instr__h13508,
instr__h13681,
instr__h13874,
instr__h14067,
instr__h14184,
instr__h14362,
instr__h14481,
instr__h14576,
instr__h14712,
instr__h14848,
instr__h14984,
instr__h15322,
instr_out___1__h15541,
instr_out___1__h15563,
next_pc___1__h9189,
next_pc__h7870,
next_pc__h8090,
next_pc__h8117,
next_pc__h9186,
rd_val___1__h8872,
rd_val___1__h8880,
rd_val___1__h8887,
rd_val___1__h8894,
rd_val___1__h8901,
rd_val___1__h8908,
rd_val__h7771,
rd_val__h7845,
rd_val__h8230,
rd_val__h8244,
rd_val__h9761,
rd_val__h9812,
rd_val__h9834,
rs1_val__h22085,
rs1_val_bypassed__h5141,
rs2_val__h8057,
trap_info_tval__h9386,
val__h7773,
val__h7847,
value__h9431,
x_out_cf_info_fallthru_PC__h9557,
x_out_data_to_stage1_instr__h10055,
x_out_data_to_stage2_val2__h7931,
x_out_next_pc__h7886,
y__h23037;
wire [20 : 0] SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798,
decoded_instr_imm21_UJ__h19083,
stage1_rg_stage_input_BITS_30_TO_10__q2;
wire [19 : 0] imm20__h12638;
wire [12 : 0] SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827,
decoded_instr_imm13_SB__h19081,
stage1_rg_stage_input_BITS_63_TO_51__q1;
wire [11 : 0] decoded_instr_imm12_S__h19080,
imm12__h10257,
imm12__h10594,
imm12__h12510,
imm12__h13134,
imm12__h13349,
imm12__h13545,
imm12__h13890,
offset__h10964,
stage1_rg_stage_input_BITS_75_TO_64__q6,
stage1_rg_stage_input_BITS_87_TO_76__q14;
wire [9 : 0] decoded_instr_funct10__h19078,
nzimm10__h13132,
nzimm10__h13347;
wire [8 : 0] offset__h11875;
wire [7 : 0] offset__h10129;
wire [6 : 0] offset__h10536;
wire [5 : 0] imm6__h12508;
wire [4 : 0] data_to_stage2_rd__h7918,
offset_BITS_4_TO_0___h10525,
offset_BITS_4_TO_0___h10956,
rd__h10596,
rs1__h10595,
shamt__h8174,
x_out_data_to_stage2_rd__h7928;
wire [3 : 0] IF_NOT_stage1_rg_stage_input_88_BITS_112_TO_11_ETC___d370,
IF_rg_cur_priv_4_EQ_0b11_84_AND_stage1_rg_stag_ETC___d398,
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418,
alu_outputs___1_exc_code__h8479,
cur_verbosity__h3701,
x_exc_code__h29000,
x_out_trap_info_exc_code__h9391;
wire [1 : 0] IF_NOT_near_mem_dmem_valid__16_32_OR_NOT_near__ETC___d173,
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559,
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122,
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177,
IF_stage2_rg_stage2_00_BITS_102_TO_101_01_EQ_0_ETC___d121,
new_epoch__h16901;
wire IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1311,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1314,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1413,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1461,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1501,
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1344,
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378,
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d252,
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d254,
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d256,
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d310,
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d321,
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d357,
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d359,
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d1296,
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192,
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194,
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362,
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d1359,
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52,
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304,
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d145,
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1303,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1307,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1316,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1325,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1347,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1368,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1395,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1410,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1520,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1078,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1092,
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1111,
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118,
NOT_rg_next_pc_609_BITS_1_TO_0_610_EQ_0b0_611__ETC___d1617,
NOT_rg_run_on_reset_250_251_OR_imem_rg_pc_BITS_ETC___d1258,
NOT_soc_map_m_pc_reset_value__270_BITS_1_TO_0__ETC___d1285,
NOT_stage1_rg_full_87_66_OR_stage1_rg_stage_in_ETC___d1340,
NOT_stage1_rg_full_87_66_OR_stage1_rg_stage_in_ETC___d1342,
NOT_stage1_rg_stage_input_88_BITS_112_TO_110_1_ETC___d289,
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d1663,
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d1667,
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328,
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d491,
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d503,
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d507,
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d513,
NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1484,
csr_regfile_RDY_server_reset_request_put__224__ETC___d1236,
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1464,
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1468,
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1471,
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1475,
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1510,
csr_regfile_read_misa__2_BIT_2_34_AND_stageD_r_ETC___d812,
csr_regfile_read_misa__2_BIT_2_34_AND_stageD_r_ETC___d818,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1115,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1254,
imem_rg_pc_BITS_31_TO_2_4_EQ_imem_rg_cache_add_ETC___d1070,
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17,
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1123,
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125,
near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_072___d1073,
near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d1220,
rg_cur_priv_4_EQ_0b11_84_OR_rg_cur_priv_4_EQ_0_ETC___d396,
rg_state_3_EQ_12_0_AND_csr_regfile_wfi_resume__ETC___d1654,
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524,
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1634,
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1643,
rg_state_3_EQ_3_327_AND_stage3_rg_full_0_OR_NO_ETC___d1337,
rg_state_3_EQ_5_658_AND_NOT_stageF_rg_full_100_ETC___d1659,
rg_state_3_EQ_8_606_AND_NOT_stageF_rg_full_100_ETC___d1607,
rg_trap_info_534_BITS_67_TO_36_535_EQ_csr_regf_ETC___d1544,
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365,
stage1_rg_stage_input_88_BITS_112_TO_110_17_EQ_ETC___d343,
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d1299,
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190,
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208,
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d672,
stage3_rg_full_0_OR_NOT_IF_stage2_rg_full_9_TH_ETC___d1335,
stageF_f_reset_rsps_i_notEmpty__244_AND_stageD_ETC___d1264,
stageF_rg_full_100_AND_near_mem_imem_valid_AND_ETC___d1132;
// action method hart0_server_reset_request_put
assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_hart0_server_reset_request_put =
EN_hart0_server_reset_request_put ;
// actionvalue method hart0_server_reset_response_get
assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_server_reset_response_get =
EN_hart0_server_reset_response_get ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = near_mem$imem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = near_mem$imem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = near_mem$imem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = near_mem$imem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = near_mem$imem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = near_mem$imem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = near_mem$imem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = near_mem$imem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = near_mem$imem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = near_mem$imem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = near_mem$imem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = near_mem$imem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = near_mem$imem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = near_mem$imem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = near_mem$imem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = near_mem$imem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = near_mem$imem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = near_mem$imem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = near_mem$imem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = near_mem$imem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = near_mem$imem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = near_mem$imem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = near_mem$imem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = near_mem$imem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = near_mem$imem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = near_mem$imem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = near_mem$imem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = near_mem$imem_master_rready ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = near_mem$mem_master_awvalid ;
// value method mem_master_m_awid
assign mem_master_awid = near_mem$mem_master_awid ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = near_mem$mem_master_awaddr ;
// value method mem_master_m_awlen
assign mem_master_awlen = near_mem$mem_master_awlen ;
// value method mem_master_m_awsize
assign mem_master_awsize = near_mem$mem_master_awsize ;
// value method mem_master_m_awburst
assign mem_master_awburst = near_mem$mem_master_awburst ;
// value method mem_master_m_awlock
assign mem_master_awlock = near_mem$mem_master_awlock ;
// value method mem_master_m_awcache
assign mem_master_awcache = near_mem$mem_master_awcache ;
// value method mem_master_m_awprot
assign mem_master_awprot = near_mem$mem_master_awprot ;
// value method mem_master_m_awqos
assign mem_master_awqos = near_mem$mem_master_awqos ;
// value method mem_master_m_awregion
assign mem_master_awregion = near_mem$mem_master_awregion ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = near_mem$mem_master_wvalid ;
// value method mem_master_m_wdata
assign mem_master_wdata = near_mem$mem_master_wdata ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = near_mem$mem_master_wstrb ;
// value method mem_master_m_wlast
assign mem_master_wlast = near_mem$mem_master_wlast ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = near_mem$mem_master_bready ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = near_mem$mem_master_arvalid ;
// value method mem_master_m_arid
assign mem_master_arid = near_mem$mem_master_arid ;
// value method mem_master_m_araddr
assign mem_master_araddr = near_mem$mem_master_araddr ;
// value method mem_master_m_arlen
assign mem_master_arlen = near_mem$mem_master_arlen ;
// value method mem_master_m_arsize
assign mem_master_arsize = near_mem$mem_master_arsize ;
// value method mem_master_m_arburst
assign mem_master_arburst = near_mem$mem_master_arburst ;
// value method mem_master_m_arlock
assign mem_master_arlock = near_mem$mem_master_arlock ;
// value method mem_master_m_arcache
assign mem_master_arcache = near_mem$mem_master_arcache ;
// value method mem_master_m_arprot
assign mem_master_arprot = near_mem$mem_master_arprot ;
// value method mem_master_m_arqos
assign mem_master_arqos = near_mem$mem_master_arqos ;
// value method mem_master_m_arregion
assign mem_master_arregion = near_mem$mem_master_arregion ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = near_mem$mem_master_rready ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = near_mem$dma_server_awready ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = near_mem$dma_server_wready ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = near_mem$dma_server_bvalid ;
// value method dma_server_m_bid
assign dma_server_bid = near_mem$dma_server_bid ;
// value method dma_server_m_bresp
assign dma_server_bresp = near_mem$dma_server_bresp ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = near_mem$dma_server_arready ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = near_mem$dma_server_rvalid ;
// value method dma_server_m_rid
assign dma_server_rid = near_mem$dma_server_rid ;
// value method dma_server_m_rdata
assign dma_server_rdata = near_mem$dma_server_rdata ;
// value method dma_server_m_rresp
assign dma_server_rresp = near_mem$dma_server_rresp ;
// value method dma_server_m_rlast
assign dma_server_rlast = near_mem$dma_server_rlast ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = near_mem$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = near_mem$mv_status ;
// submodule csr_regfile
mkCSR_RegFile csr_regfile(.CLK(CLK),
.RST_N(RST_N),
.access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
.access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
.access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
.access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
.access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
.access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
.csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
.csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
.csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
.csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
.csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
.csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
.csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
.csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
.csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
.interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
.m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
.mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
.mav_csr_write_word(csr_regfile$mav_csr_write_word),
.mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
.nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
.read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
.read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
.s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
.software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
.EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
.EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
.EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
.EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
.EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
.EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
.EN_debug(csr_regfile$EN_debug),
.RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
.read_csr(csr_regfile$read_csr),
.read_csr_port2(),
.mav_read_csr(),
.mav_csr_write(),
.read_misa(csr_regfile$read_misa),
.read_mstatus(csr_regfile$read_mstatus),
.read_ustatus(),
.read_satp(csr_regfile$read_satp),
.csr_trap_actions(csr_regfile$csr_trap_actions),
.RDY_csr_trap_actions(),
.csr_ret_actions(csr_regfile$csr_ret_actions),
.RDY_csr_ret_actions(),
.read_csr_minstret(csr_regfile$read_csr_minstret),
.read_csr_mcycle(csr_regfile$read_csr_mcycle),
.read_csr_mtime(),
.access_permitted_1(csr_regfile$access_permitted_1),
.access_permitted_2(csr_regfile$access_permitted_2),
.csr_counter_read_fault(),
.csr_mip_read(),
.interrupt_pending(csr_regfile$interrupt_pending),
.wfi_resume(csr_regfile$wfi_resume),
.nmi_pending(csr_regfile$nmi_pending),
.RDY_debug());
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule gpr_regfile
mkGPR_RegFile gpr_regfile(.CLK(CLK),
.RST_N(RST_N),
.read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
.read_rs1_rs1(gpr_regfile$read_rs1_rs1),
.read_rs2_rs2(gpr_regfile$read_rs2_rs2),
.write_rd_rd(gpr_regfile$write_rd_rd),
.write_rd_rd_val(gpr_regfile$write_rd_rd_val),
.EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
.EN_write_rd(gpr_regfile$EN_write_rd),
.RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
.read_rs1(gpr_regfile$read_rs1),
.read_rs1_port2(),
.read_rs2(gpr_regfile$read_rs2));
// submodule near_mem
mkNear_Mem near_mem(.CLK(CLK),
.RST_N(RST_N),
.dma_server_araddr(near_mem$dma_server_araddr),
.dma_server_arburst(near_mem$dma_server_arburst),
.dma_server_arcache(near_mem$dma_server_arcache),
.dma_server_arid(near_mem$dma_server_arid),
.dma_server_arlen(near_mem$dma_server_arlen),
.dma_server_arlock(near_mem$dma_server_arlock),
.dma_server_arprot(near_mem$dma_server_arprot),
.dma_server_arqos(near_mem$dma_server_arqos),
.dma_server_arregion(near_mem$dma_server_arregion),
.dma_server_arsize(near_mem$dma_server_arsize),
.dma_server_arvalid(near_mem$dma_server_arvalid),
.dma_server_awaddr(near_mem$dma_server_awaddr),
.dma_server_awburst(near_mem$dma_server_awburst),
.dma_server_awcache(near_mem$dma_server_awcache),
.dma_server_awid(near_mem$dma_server_awid),
.dma_server_awlen(near_mem$dma_server_awlen),
.dma_server_awlock(near_mem$dma_server_awlock),
.dma_server_awprot(near_mem$dma_server_awprot),
.dma_server_awqos(near_mem$dma_server_awqos),
.dma_server_awregion(near_mem$dma_server_awregion),
.dma_server_awsize(near_mem$dma_server_awsize),
.dma_server_awvalid(near_mem$dma_server_awvalid),
.dma_server_bready(near_mem$dma_server_bready),
.dma_server_rready(near_mem$dma_server_rready),
.dma_server_wdata(near_mem$dma_server_wdata),
.dma_server_wlast(near_mem$dma_server_wlast),
.dma_server_wstrb(near_mem$dma_server_wstrb),
.dma_server_wvalid(near_mem$dma_server_wvalid),
.dmem_req_addr(near_mem$dmem_req_addr),
.dmem_req_f3(near_mem$dmem_req_f3),
.dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
.dmem_req_op(near_mem$dmem_req_op),
.dmem_req_priv(near_mem$dmem_req_priv),
.dmem_req_satp(near_mem$dmem_req_satp),
.dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
.dmem_req_store_value(near_mem$dmem_req_store_value),
.imem_master_arready(near_mem$imem_master_arready),
.imem_master_awready(near_mem$imem_master_awready),
.imem_master_bid(near_mem$imem_master_bid),
.imem_master_bresp(near_mem$imem_master_bresp),
.imem_master_bvalid(near_mem$imem_master_bvalid),
.imem_master_rdata(near_mem$imem_master_rdata),
.imem_master_rid(near_mem$imem_master_rid),
.imem_master_rlast(near_mem$imem_master_rlast),
.imem_master_rresp(near_mem$imem_master_rresp),
.imem_master_rvalid(near_mem$imem_master_rvalid),
.imem_master_wready(near_mem$imem_master_wready),
.imem_req_addr(near_mem$imem_req_addr),
.imem_req_f3(near_mem$imem_req_f3),
.imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
.imem_req_priv(near_mem$imem_req_priv),
.imem_req_satp(near_mem$imem_req_satp),
.imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
.mem_master_arready(near_mem$mem_master_arready),
.mem_master_awready(near_mem$mem_master_awready),
.mem_master_bid(near_mem$mem_master_bid),
.mem_master_bresp(near_mem$mem_master_bresp),
.mem_master_bvalid(near_mem$mem_master_bvalid),
.mem_master_rdata(near_mem$mem_master_rdata),
.mem_master_rid(near_mem$mem_master_rid),
.mem_master_rlast(near_mem$mem_master_rlast),
.mem_master_rresp(near_mem$mem_master_rresp),
.mem_master_rvalid(near_mem$mem_master_rvalid),
.mem_master_wready(near_mem$mem_master_wready),
.server_fence_request_put(near_mem$server_fence_request_put),
.set_watch_tohost_tohost_addr(near_mem$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(near_mem$set_watch_tohost_watch_tohost),
.EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
.EN_imem_req(near_mem$EN_imem_req),
.EN_dmem_req(near_mem$EN_dmem_req),
.EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
.EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
.EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
.EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
.EN_set_watch_tohost(near_mem$EN_set_watch_tohost),
.EN_ma_ddr4_ready(near_mem$EN_ma_ddr4_ready),
.RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
.imem_valid(near_mem$imem_valid),
.imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
.imem_pc(near_mem$imem_pc),
.imem_instr(near_mem$imem_instr),
.imem_exc(near_mem$imem_exc),
.imem_exc_code(near_mem$imem_exc_code),
.imem_tval(),
.imem_master_awvalid(near_mem$imem_master_awvalid),
.imem_master_awid(near_mem$imem_master_awid),
.imem_master_awaddr(near_mem$imem_master_awaddr),
.imem_master_awlen(near_mem$imem_master_awlen),
.imem_master_awsize(near_mem$imem_master_awsize),
.imem_master_awburst(near_mem$imem_master_awburst),
.imem_master_awlock(near_mem$imem_master_awlock),
.imem_master_awcache(near_mem$imem_master_awcache),
.imem_master_awprot(near_mem$imem_master_awprot),
.imem_master_awqos(near_mem$imem_master_awqos),
.imem_master_awregion(near_mem$imem_master_awregion),
.imem_master_wvalid(near_mem$imem_master_wvalid),
.imem_master_wdata(near_mem$imem_master_wdata),
.imem_master_wstrb(near_mem$imem_master_wstrb),
.imem_master_wlast(near_mem$imem_master_wlast),
.imem_master_bready(near_mem$imem_master_bready),
.imem_master_arvalid(near_mem$imem_master_arvalid),
.imem_master_arid(near_mem$imem_master_arid),
.imem_master_araddr(near_mem$imem_master_araddr),
.imem_master_arlen(near_mem$imem_master_arlen),
.imem_master_arsize(near_mem$imem_master_arsize),
.imem_master_arburst(near_mem$imem_master_arburst),
.imem_master_arlock(near_mem$imem_master_arlock),
.imem_master_arcache(near_mem$imem_master_arcache),
.imem_master_arprot(near_mem$imem_master_arprot),
.imem_master_arqos(near_mem$imem_master_arqos),
.imem_master_arregion(near_mem$imem_master_arregion),
.imem_master_rready(near_mem$imem_master_rready),
.dmem_valid(near_mem$dmem_valid),
.dmem_word64(near_mem$dmem_word64),
.dmem_st_amo_val(),
.dmem_exc(near_mem$dmem_exc),
.dmem_exc_code(near_mem$dmem_exc_code),
.mem_master_awvalid(near_mem$mem_master_awvalid),
.mem_master_awid(near_mem$mem_master_awid),
.mem_master_awaddr(near_mem$mem_master_awaddr),
.mem_master_awlen(near_mem$mem_master_awlen),
.mem_master_awsize(near_mem$mem_master_awsize),
.mem_master_awburst(near_mem$mem_master_awburst),
.mem_master_awlock(near_mem$mem_master_awlock),
.mem_master_awcache(near_mem$mem_master_awcache),
.mem_master_awprot(near_mem$mem_master_awprot),
.mem_master_awqos(near_mem$mem_master_awqos),
.mem_master_awregion(near_mem$mem_master_awregion),
.mem_master_wvalid(near_mem$mem_master_wvalid),
.mem_master_wdata(near_mem$mem_master_wdata),
.mem_master_wstrb(near_mem$mem_master_wstrb),
.mem_master_wlast(near_mem$mem_master_wlast),
.mem_master_bready(near_mem$mem_master_bready),
.mem_master_arvalid(near_mem$mem_master_arvalid),
.mem_master_arid(near_mem$mem_master_arid),
.mem_master_araddr(near_mem$mem_master_araddr),
.mem_master_arlen(near_mem$mem_master_arlen),
.mem_master_arsize(near_mem$mem_master_arsize),
.mem_master_arburst(near_mem$mem_master_arburst),
.mem_master_arlock(near_mem$mem_master_arlock),
.mem_master_arcache(near_mem$mem_master_arcache),
.mem_master_arprot(near_mem$mem_master_arprot),
.mem_master_arqos(near_mem$mem_master_arqos),
.mem_master_arregion(near_mem$mem_master_arregion),
.mem_master_rready(near_mem$mem_master_rready),
.RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put),
.RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get),
.RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put),
.RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get),
.dma_server_awready(near_mem$dma_server_awready),
.dma_server_wready(near_mem$dma_server_wready),
.dma_server_bvalid(near_mem$dma_server_bvalid),
.dma_server_bid(near_mem$dma_server_bid),
.dma_server_bresp(near_mem$dma_server_bresp),
.dma_server_arready(near_mem$dma_server_arready),
.dma_server_rvalid(near_mem$dma_server_rvalid),
.dma_server_rid(near_mem$dma_server_rid),
.dma_server_rdata(near_mem$dma_server_rdata),
.dma_server_rresp(near_mem$dma_server_rresp),
.dma_server_rlast(near_mem$dma_server_rlast),
.RDY_set_watch_tohost(),
.mv_tohost_value(near_mem$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(near_mem$mv_status));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(soc_map$m_pc_reset_value),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// submodule stage1_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_reqs$ENQ),
.DEQ(stage1_f_reset_reqs$DEQ),
.CLR(stage1_f_reset_reqs$CLR),
.FULL_N(stage1_f_reset_reqs$FULL_N),
.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));
// submodule stage1_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_rsps$ENQ),
.DEQ(stage1_f_reset_rsps$DEQ),
.CLR(stage1_f_reset_rsps$CLR),
.FULL_N(stage1_f_reset_rsps$FULL_N),
.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));
// submodule stage2_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_reqs$ENQ),
.DEQ(stage2_f_reset_reqs$DEQ),
.CLR(stage2_f_reset_reqs$CLR),
.FULL_N(stage2_f_reset_reqs$FULL_N),
.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));
// submodule stage2_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_rsps$ENQ),
.DEQ(stage2_f_reset_rsps$DEQ),
.CLR(stage2_f_reset_rsps$CLR),
.FULL_N(stage2_f_reset_rsps$FULL_N),
.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));
// submodule stage3_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_reqs$ENQ),
.DEQ(stage3_f_reset_reqs$DEQ),
.CLR(stage3_f_reset_reqs$CLR),
.FULL_N(stage3_f_reset_reqs$FULL_N),
.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));
// submodule stage3_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_rsps$ENQ),
.DEQ(stage3_f_reset_rsps$DEQ),
.CLR(stage3_f_reset_rsps$CLR),
.FULL_N(stage3_f_reset_rsps$FULL_N),
.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));
// submodule stageD_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stageD_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_reqs$ENQ),
.DEQ(stageD_f_reset_reqs$DEQ),
.CLR(stageD_f_reset_reqs$CLR),
.FULL_N(stageD_f_reset_reqs$FULL_N),
.EMPTY_N(stageD_f_reset_reqs$EMPTY_N));
// submodule stageD_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stageD_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_rsps$ENQ),
.DEQ(stageD_f_reset_rsps$DEQ),
.CLR(stageD_f_reset_rsps$CLR),
.FULL_N(stageD_f_reset_rsps$FULL_N),
.EMPTY_N(stageD_f_reset_rsps$EMPTY_N));
// submodule stageF_branch_predictor
mkBranch_Predictor stageF_branch_predictor(.CLK(CLK),
.RST_N(RST_N),
.bp_train_cf_info(stageF_branch_predictor$bp_train_cf_info),
.bp_train_instr(stageF_branch_predictor$bp_train_instr),
.bp_train_is_i32_not_i16(stageF_branch_predictor$bp_train_is_i32_not_i16),
.bp_train_pc(stageF_branch_predictor$bp_train_pc),
.predict_req_pc(stageF_branch_predictor$predict_req_pc),
.predict_rsp_instr(stageF_branch_predictor$predict_rsp_instr),
.predict_rsp_is_i32_not_i16(stageF_branch_predictor$predict_rsp_is_i32_not_i16),
.EN_reset(stageF_branch_predictor$EN_reset),
.EN_predict_req(stageF_branch_predictor$EN_predict_req),
.EN_bp_train(stageF_branch_predictor$EN_bp_train),
.RDY_reset(),
.RDY_predict_req(stageF_branch_predictor$RDY_predict_req),
.predict_rsp(stageF_branch_predictor$predict_rsp),
.RDY_bp_train());
// submodule stageF_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stageF_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_reqs$ENQ),
.DEQ(stageF_f_reset_reqs$DEQ),
.CLR(stageF_f_reset_reqs$CLR),
.FULL_N(stageF_f_reset_reqs$FULL_N),
.EMPTY_N(stageF_f_reset_reqs$EMPTY_N));
// submodule stageF_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stageF_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_rsps$ENQ),
.DEQ(stageF_f_reset_rsps$DEQ),
.CLR(stageF_f_reset_rsps$CLR),
.FULL_N(stageF_f_reset_rsps$FULL_N),
.EMPTY_N(stageF_f_reset_rsps$EMPTY_N));
// rule RL_rl_show_pipe
assign CAN_FIRE_RL_rl_show_pipe =
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 &&
rg_state != 4'd0 &&
rg_state != 4'd1 &&
rg_state != 4'd12 ;
assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;
// rule RL_rl_stage2_nonpipe
assign CAN_FIRE_RL_rl_stage2_nonpipe =
rg_state == 4'd3 && !stage3_rg_full &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd3 ;
assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;
// rule RL_rl_stage1_trap
assign CAN_FIRE_RL_rl_stage1_trap =
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd12 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;
// rule RL_rl_trap
assign CAN_FIRE_RL_rl_trap =
rg_state == 4'd4 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;
// rule RL_rl_stage1_CSRR_W
assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
// rule RL_rl_stage1_CSRR_W_2
assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
// rule RL_rl_stage1_CSRR_S_or_C
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C =
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd4 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C =
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C ;
// rule RL_rl_stage1_CSRR_S_or_C_2
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
// rule RL_rl_stage1_restart_after_csrrx
assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1254 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_3_EQ_8_606_AND_NOT_stageF_rg_full_100_ETC___d1607 ;
assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;
// rule RL_rl_stage1_xRET
assign CAN_FIRE_RL_rl_stage1_xRET =
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524 &&
(IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd8 ||
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd9 ||
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd10) &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;
// rule RL_rl_stage1_FENCE_I
assign CAN_FIRE_RL_rl_stage1_FENCE_I =
near_mem$RDY_server_fence_i_request_put &&
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1634 ;
assign WILL_FIRE_RL_rl_stage1_FENCE_I = CAN_FIRE_RL_rl_stage1_FENCE_I ;
// rule RL_rl_finish_FENCE_I
assign CAN_FIRE_RL_rl_finish_FENCE_I =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1254 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_server_fence_i_response_get &&
rg_state == 4'd9 ;
assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;
// rule RL_rl_stage1_FENCE
assign CAN_FIRE_RL_rl_stage1_FENCE =
near_mem$RDY_server_fence_request_put &&
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1643 ;
assign WILL_FIRE_RL_rl_stage1_FENCE = CAN_FIRE_RL_rl_stage1_FENCE ;
// rule RL_rl_finish_FENCE
assign CAN_FIRE_RL_rl_finish_FENCE =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1254 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_server_fence_response_get &&
rg_state == 4'd10 ;
assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;
// rule RL_rl_stage1_WFI
assign CAN_FIRE_RL_rl_stage1_WFI =
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd11 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign WILL_FIRE_RL_rl_stage1_WFI = CAN_FIRE_RL_rl_stage1_WFI ;
// rule RL_rl_WFI_resume
assign CAN_FIRE_RL_rl_WFI_resume =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1254 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_3_EQ_12_0_AND_csr_regfile_wfi_resume__ETC___d1654 ;
assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;
// rule RL_rl_reset_from_WFI
assign CAN_FIRE_RL_rl_reset_from_WFI =
rg_state == 4'd12 && f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_5 ;
// rule RL_rl_trap_fetch
assign CAN_FIRE_RL_rl_trap_fetch =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1254 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_3_EQ_5_658_AND_NOT_stageF_rg_full_100_ETC___d1659 ;
assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;
// rule RL_rl_stage1_interrupt
assign CAN_FIRE_RL_rl_stage1_interrupt =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
rg_state == 4'd3 &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d1667 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ;
// rule RL_imem_rl_assert_fail
assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete =
gpr_regfile$RDY_server_reset_response_get &&
near_mem$RDY_server_reset_response_get &&
csr_regfile$RDY_server_reset_response_get &&
stageF_f_reset_rsps_i_notEmpty__244_AND_stageD_ETC___d1264 &&
rg_state == 4'd1 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_pipe
assign CAN_FIRE_RL_rl_pipe =
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1314 ||
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1325) &&
rg_state_3_EQ_3_327_AND_stage3_rg_full_0_OR_NO_ETC___d1337 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1347 ;
assign WILL_FIRE_RL_rl_pipe =
CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start =
gpr_regfile$RDY_server_reset_request_put &&
near_mem$RDY_server_reset_request_put &&
csr_regfile_RDY_server_reset_request_put__224__ETC___d1236 &&
rg_state == 4'd0 ;
assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;
// rule RL_imem_rl_fetch_next_32b
assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
imem_rg_pc[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[17:16] == 2'b11 ;
assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
CAN_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_stage3_rl_reset
assign CAN_FIRE_RL_stage3_rl_reset =
stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;
// rule RL_stage2_rl_reset_end
assign CAN_FIRE_RL_stage2_rl_reset_end =
stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ;
assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;
// rule RL_stage2_rl_reset_begin
assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;
// rule RL_stage1_rl_reset
assign CAN_FIRE_RL_stage1_rl_reset =
stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;
// rule RL_stageD_rl_reset
assign CAN_FIRE_RL_stageD_rl_reset =
stageD_f_reset_reqs$EMPTY_N && stageD_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageD_rl_reset = CAN_FIRE_RL_stageD_rl_reset ;
// rule RL_stageF_rl_reset
assign CAN_FIRE_RL_stageF_rl_reset =
stageF_f_reset_reqs$EMPTY_N && stageF_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageF_rl_reset = CAN_FIRE_RL_stageF_rl_reset ;
// inputs to muxes for submodule ports
assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ;
assign MUX_gpr_regfile$write_rd_1__SEL_3 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ;
assign MUX_imem_rg_cache_addr$write_1__SEL_1 =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
assign MUX_imem_rg_cache_addr$write_1__SEL_2 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ;
assign MUX_rg_next_pc$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1410 ;
assign MUX_rg_next_pc$write_1__SEL_2 =
WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ;
assign MUX_rg_state$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1461 ;
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset_complete &&
!WILL_FIRE_RL_imem_rl_fetch_next_32b ;
assign MUX_rg_state$write_1__SEL_5 =
CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;
assign MUX_rg_state$write_1__SEL_7 =
WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign MUX_rg_state$write_1__SEL_8 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
assign MUX_rg_state$write_1__SEL_9 =
WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
assign MUX_rg_state$write_1__SEL_10 =
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd3 ;
assign MUX_rg_trap_info$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ;
assign MUX_rg_trap_instr$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ;
assign MUX_rg_trap_interrupt$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
always@(rg_trap_instr or
csr_regfile$read_csr or
y__h23037 or
IF_csr_regfile_read_csr_rg_trap_instr_545_BITS_ETC___d1598)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b110:
MUX_csr_regfile$mav_csr_write_2__VAL_2 =
IF_csr_regfile_read_csr_rg_trap_instr_545_BITS_ETC___d1598;
default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
csr_regfile$read_csr[31:0] & y__h23037;
endcase
end
assign MUX_imem_rg_cache_addr$write_1__VAL_1 =
(near_mem$imem_valid && !near_mem$imem_exc) ?
near_mem$imem_pc :
32'h00000001 ;
assign MUX_imem_rg_cache_addr$write_1__VAL_2 =
near_mem$imem_exc ? 32'h00000001 : near_mem$imem_pc ;
assign MUX_imem_rg_tval$write_1__VAL_1 =
(NOT_soc_map_m_pc_reset_value__270_BITS_1_TO_0__ETC___d1285 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h17506 :
soc_map$m_pc_reset_value[31:0] ;
assign MUX_imem_rg_tval$write_1__VAL_2 =
(NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1484 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h20531 :
stageF_branch_predictor$predict_rsp ;
assign MUX_imem_rg_tval$write_1__VAL_3 =
(NOT_rg_next_pc_609_BITS_1_TO_0_610_EQ_0b0_611__ETC___d1617 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h28726 :
rg_next_pc ;
assign MUX_imem_rg_tval$write_1__VAL_4 = near_mem$imem_pc + 32'd4 ;
assign MUX_near_mem$imem_req_2__VAL_1 =
(NOT_soc_map_m_pc_reset_value__270_BITS_1_TO_0__ETC___d1285 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h17506 :
addr_of_b32__h17387 ;
assign MUX_near_mem$imem_req_2__VAL_2 =
(NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1484 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h20531 :
addr_of_b32__h20412 ;
assign MUX_near_mem$imem_req_2__VAL_4 =
(NOT_rg_next_pc_609_BITS_1_TO_0_610_EQ_0b0_611__ETC___d1617 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h28726 :
addr_of_b32__h28607 ;
assign MUX_rg_state$write_1__VAL_2 = rg_run_on_reset ? 4'd3 : 4'd2 ;
assign MUX_rg_state$write_1__VAL_3 =
csr_regfile$access_permitted_1 ? 4'd8 : 4'd4 ;
assign MUX_rg_state$write_1__VAL_4 =
csr_regfile$access_permitted_2 ? 4'd8 : 4'd4 ;
assign MUX_rg_trap_info$write_1__VAL_1 =
{ stage1_rg_stage_input[305:274], 4'd2, value__h9431 } ;
assign MUX_rg_trap_info$write_1__VAL_2 =
{ stage2_rg_stage2[166:135],
near_mem$dmem_exc_code,
stage2_rg_stage2[95:64] } ;
assign MUX_rg_trap_info$write_1__VAL_3 =
{ stage1_rg_stage_input[305:274],
stage1_rg_stage_input[268] ?
stage1_rg_stage_input[267:232] :
{ alu_outputs_exc_code__h8498, trap_info_tval__h9386 } } ;
assign MUX_rg_trap_info$write_1__VAL_4 =
{ stage1_rg_stage_input[305:274], x_exc_code__h29000, 32'd0 } ;
assign MUX_rg_trap_instr$write_1__VAL_1 = stage1_rg_stage_input[231:200] ;
assign MUX_stage1_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1413 &&
stageD_rg_full ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1501 ;
assign MUX_stage2_rg_full$write_1__VAL_2 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1307 ?
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 :
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd2 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd0 ;
assign MUX_stageD_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1311 &&
stageD_rg_full ;
assign MUX_stageF_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 ?
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1510 :
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1311 &&
stageD_rg_full ||
!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118) &&
stageF_rg_full ;
// register cfg_logdelay
assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
assign cfg_logdelay$EN = EN_set_verbosity ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register imem_rg_cache_addr
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_cache_addr$write_1__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_imem_rg_cache_addr$write_1__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
near_mem$imem_pc or MUX_rg_state$write_1__SEL_7)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_cache_addr$D_IN = near_mem$imem_pc;
MUX_rg_state$write_1__SEL_7:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_1;
default: imem_rg_cache_addr$D_IN =
32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_cache_addr$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_cache_b16
assign imem_rg_cache_b16$D_IN = near_mem$imem_instr[31:16] ;
assign imem_rg_cache_b16$EN =
MUX_rg_state$write_1__SEL_7 && near_mem$imem_valid &&
!near_mem$imem_exc ||
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
near_mem$imem_valid &&
!near_mem$imem_exc ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 &&
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1475 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register imem_rg_f3
assign imem_rg_f3$D_IN = 3'b010 ;
assign imem_rg_f3$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_mstatus_MXR
assign imem_rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign imem_rg_mstatus_MXR$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_pc
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0];
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_pc$D_IN = stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7: imem_rg_pc$D_IN = rg_next_pc;
default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_pc$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_priv
assign imem_rg_priv$D_IN = rg_cur_priv ;
assign imem_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_satp
assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
assign imem_rg_satp$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_sstatus_SUM
assign imem_rg_sstatus_SUM$D_IN = 1'd0 ;
assign imem_rg_sstatus_SUM$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_tval
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_tval$write_1__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_imem_rg_tval$write_1__VAL_2 or
MUX_rg_state$write_1__SEL_7 or
MUX_imem_rg_tval$write_1__VAL_3 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_2;
MUX_rg_state$write_1__SEL_7:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_3;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_4;
default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_tval$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register rg_csr_pc
assign rg_csr_pc$D_IN = stage1_rg_stage_input[305:274] ;
assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_csr_val1
assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h7930 ;
assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_cur_priv
always@(WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or
csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_trap:
rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
WILL_FIRE_RL_rl_stage1_xRET:
rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32];
WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_cur_priv$EN =
WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_epoch
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
new_epoch__h16901 or
MUX_rg_state$write_1__SEL_7 or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
rg_epoch$D_IN = new_epoch__h16901;
MUX_rg_state$write_1__SEL_7: rg_epoch$D_IN = new_epoch__h16901;
WILL_FIRE_RL_rl_reset_start: rg_epoch$D_IN = 2'd0;
default: rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mstatus_MXR
assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_next_pc
always@(MUX_rg_next_pc$write_1__SEL_1 or
x_out_next_pc__h7886 or
MUX_rg_next_pc$write_1__SEL_2 or
WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h7886;
MUX_rg_next_pc$write_1__SEL_2: rg_next_pc$D_IN = x_out_next_pc__h7886;
WILL_FIRE_RL_rl_trap:
rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66];
WILL_FIRE_RL_rl_stage1_xRET:
rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34];
default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_next_pc$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1410 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_xRET ;
// register rg_run_on_reset
assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ;
// register rg_sstatus_SUM
assign rg_sstatus_SUM$D_IN = 1'd0 ;
assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_start_CPI_cycles
assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
assign rg_start_CPI_cycles$EN = MUX_imem_rg_cache_addr$write_1__SEL_1 ;
// register rg_start_CPI_instrs
assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
assign rg_start_CPI_instrs$EN = MUX_imem_rg_cache_addr$write_1__SEL_1 ;
// register rg_state
always@(WILL_FIRE_RL_rl_reset_complete or
MUX_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
MUX_rg_state$write_1__VAL_4 or
WILL_FIRE_RL_rl_reset_from_WFI or
WILL_FIRE_RL_rl_reset_start or
MUX_rg_state$write_1__SEL_7 or
MUX_rg_state$write_1__SEL_8 or
MUX_rg_state$write_1__SEL_1 or
MUX_rg_state$write_1__SEL_9 or
WILL_FIRE_RL_rl_stage1_CSRR_W or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
WILL_FIRE_RL_rl_stage1_FENCE_I or
WILL_FIRE_RL_rl_stage1_FENCE or WILL_FIRE_RL_rl_stage1_WFI)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_reset_complete:
rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_CSRR_W_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd3;
MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4;
MUX_rg_state$write_1__SEL_1 || MUX_rg_state$write_1__SEL_9:
rg_state$D_IN = 4'd5;
WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd6;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd7;
WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9;
WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10;
WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12;
default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1461 ||
WILL_FIRE_RL_rl_reset_complete ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
WILL_FIRE_RL_rl_reset_from_WFI ||
WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_WFI ;
// register rg_trap_info
always@(MUX_rg_trap_info$write_1__SEL_1 or
MUX_rg_trap_info$write_1__VAL_1 or
WILL_FIRE_RL_rl_stage2_nonpipe or
MUX_rg_trap_info$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_trap or
MUX_rg_trap_info$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_trap_info$write_1__SEL_1:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
WILL_FIRE_RL_rl_stage2_nonpipe:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_trap:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_interrupt:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
default: rg_trap_info$D_IN =
68'hAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_trap_info$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register rg_trap_instr
assign rg_trap_instr$D_IN =
MUX_rg_trap_instr$write_1__SEL_1 ?
stage1_rg_stage_input[231:200] :
stage2_rg_stage2[134:103] ;
assign rg_trap_instr$EN =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
// register rg_trap_interrupt
assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
assign rg_trap_interrupt$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register stage1_rg_full
always@(WILL_FIRE_RL_stage1_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stage1_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stage1_rg_full$D_IN = 1'd0;
default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage1_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stage1_rl_reset ;
// register stage1_rg_stage_input
assign stage1_rg_stage_input$D_IN =
{ stageD_rg_data[137:106],
stageD_rg_data[103:102],
stageD_rg_data[105:104],
stageD_rg_data[101:64],
_theResult____h5412,
stageD_rg_data[47:0],
_theResult____h5412[6:0],
_theResult____h5412[11:7],
_theResult____h5412[19:15],
_theResult____h5412[24:20],
_theResult____h5412[31:27],
_theResult____h5412[31:20],
_theResult____h5412[14:12],
_theResult____h5412[31:27],
_theResult____h5412[31:25],
decoded_instr_funct10__h19078,
_theResult____h5412[31:20],
decoded_instr_imm12_S__h19080,
decoded_instr_imm13_SB__h19081,
_theResult____h5412[31:12],
decoded_instr_imm21_UJ__h19083,
_theResult____h5412[27:20],
_theResult____h5412[26:25] } ;
assign stage1_rg_stage_input$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1413 &&
stageD_rg_full ;
// register stage2_rg_full
always@(stage2_f_reset_reqs$EMPTY_N or
WILL_FIRE_RL_rl_pipe or
MUX_stage2_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or WILL_FIRE_RL_rl_trap)
case (1'b1)
stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap:
stage2_rg_full$D_IN = 1'd0;
default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage2_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap ||
stage2_f_reset_reqs$EMPTY_N ;
// register stage2_rg_resetting
assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ;
assign stage2_rg_resetting$EN =
WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ;
// register stage2_rg_stage2
assign stage2_rg_stage2$D_IN =
{ rg_cur_priv,
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[231:200],
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559,
x_out_data_to_stage2_rd__h7928,
x_out_data_to_stage2_addr__h7929,
x_out_data_to_stage2_val1__h7930,
x_out_data_to_stage2_val2__h7931 } ;
assign stage2_rg_stage2$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 ;
// register stage3_rg_full
always@(WILL_FIRE_RL_stage3_rl_reset or
WILL_FIRE_RL_rl_pipe or
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 or
MUX_imem_rg_cache_addr$write_1__SEL_1)
case (1'b1)
WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage3_rg_full$D_IN =
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2;
MUX_imem_rg_cache_addr$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0;
default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage3_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stage3_rl_reset ;
// register stage3_rg_stage3
assign stage3_rg_stage3$D_IN =
{ stage2_rg_stage2[166:103],
stage2_rg_stage2[168:167],
stage2_rg_stage2[102:101] == 2'd0 ||
near_mem$dmem_valid && !near_mem$dmem_exc,
x_out_data_to_stage3_rd__h7354,
x_out_data_to_stage3_rd_val__h7355 } ;
assign stage3_rg_stage3$EN =
WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd2 ;
// register stageD_rg_data
assign stageD_rg_data$D_IN =
{ imem_rg_pc,
stageF_rg_epoch,
stageF_rg_priv,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1078 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11,
near_mem$imem_exc,
near_mem$imem_exc_code,
imem_rg_tval,
d_instr__h15539,
stageF_branch_predictor$predict_rsp } ;
assign stageD_rg_data$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 ;
// register stageD_rg_full
always@(WILL_FIRE_RL_stageD_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageD_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stageD_rl_reset: stageD_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageD_rg_full$D_IN = MUX_stageD_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stageD_rg_full$D_IN = 1'd0;
default: stageD_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageD_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stageD_rl_reset ;
// register stageF_rg_epoch
always@(WILL_FIRE_RL_stageF_rl_reset or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_rg_epoch or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
new_epoch__h16901 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_epoch$D_IN = 2'd0;
MUX_imem_rg_cache_addr$write_1__SEL_2:
stageF_rg_epoch$D_IN = stageF_rg_epoch;
MUX_imem_rg_cache_addr$write_1__SEL_1:
stageF_rg_epoch$D_IN = new_epoch__h16901;
WILL_FIRE_RL_rl_trap_fetch: stageF_rg_epoch$D_IN = new_epoch__h16901;
WILL_FIRE_RL_rl_WFI_resume: stageF_rg_epoch$D_IN = new_epoch__h16901;
WILL_FIRE_RL_rl_finish_FENCE: stageF_rg_epoch$D_IN = new_epoch__h16901;
WILL_FIRE_RL_rl_finish_FENCE_I: stageF_rg_epoch$D_IN = new_epoch__h16901;
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_epoch$D_IN = new_epoch__h16901;
default: stageF_rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stageF_rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_stageF_rl_reset ;
// register stageF_rg_full
always@(WILL_FIRE_RL_stageF_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageF_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageF_rg_full$D_IN = MUX_stageF_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_full$D_IN = 1'd1;
default: stageF_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageF_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stageF_rl_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register stageF_rg_priv
assign stageF_rg_priv$D_IN = rg_cur_priv ;
assign stageF_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// submodule csr_regfile
assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_2_read_not_write =
rs1_val__h22768 == 32'd0 ;
assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
always@(IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418)
begin
case (IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418)
4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b11;
4'd9: csr_regfile$csr_ret_actions_from_priv = 2'b01;
default: csr_regfile$csr_ret_actions_from_priv = 2'b0;
endcase
end
assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[35:32] ;
assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
assign csr_regfile$csr_trap_actions_interrupt =
rg_trap_interrupt && !csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_nmi =
rg_trap_interrupt && csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_pc = rg_trap_info[67:36] ;
assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[31:0] ;
assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
assign csr_regfile$m_external_interrupt_req_set_not_clear =
m_external_interrupt_req_set_not_clear ;
assign csr_regfile$mav_csr_write_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$mav_csr_write_word =
MUX_csr_regfile$mav_csr_write_1__SEL_1 ?
rs1_val__h22085 :
MUX_csr_regfile$mav_csr_write_2__VAL_2 ;
assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ;
assign csr_regfile$s_external_interrupt_req_set_not_clear =
s_external_interrupt_req_set_not_clear ;
assign csr_regfile$software_interrupt_req_set_not_clear =
software_interrupt_req_set_not_clear ;
assign csr_regfile$timer_interrupt_req_set_not_clear =
timer_interrupt_req_set_not_clear ;
assign csr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign csr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign csr_regfile$EN_mav_read_csr = 1'b0 ;
assign csr_regfile$EN_mav_csr_write =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
rg_trap_instr[19:15] != 5'd0 ;
assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_csr_minstret_incr =
WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd2 ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_debug = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
assign f_reset_reqs$DEQ =
gpr_regfile$RDY_server_reset_request_put &&
near_mem$RDY_server_reset_request_put &&
csr_regfile_RDY_server_reset_request_put__224__ETC___d1236 &&
rg_state == 4'd0 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = rg_run_on_reset ;
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ;
assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule gpr_regfile
assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
assign gpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
assign gpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
assign gpr_regfile$write_rd_rd =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_3) ?
rg_trap_instr[11:7] :
stage3_rg_stage3[36:32] ;
assign gpr_regfile$write_rd_rd_val =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_3) ?
csr_regfile$read_csr[31:0] :
stage3_rg_stage3[31:0] ;
assign gpr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign gpr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign gpr_regfile$EN_write_rd =
WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ;
// submodule near_mem
assign near_mem$dma_server_araddr = dma_server_araddr ;
assign near_mem$dma_server_arburst = dma_server_arburst ;
assign near_mem$dma_server_arcache = dma_server_arcache ;
assign near_mem$dma_server_arid = dma_server_arid ;
assign near_mem$dma_server_arlen = dma_server_arlen ;
assign near_mem$dma_server_arlock = dma_server_arlock ;
assign near_mem$dma_server_arprot = dma_server_arprot ;
assign near_mem$dma_server_arqos = dma_server_arqos ;
assign near_mem$dma_server_arregion = dma_server_arregion ;
assign near_mem$dma_server_arsize = dma_server_arsize ;
assign near_mem$dma_server_arvalid = dma_server_arvalid ;
assign near_mem$dma_server_awaddr = dma_server_awaddr ;
assign near_mem$dma_server_awburst = dma_server_awburst ;
assign near_mem$dma_server_awcache = dma_server_awcache ;
assign near_mem$dma_server_awid = dma_server_awid ;
assign near_mem$dma_server_awlen = dma_server_awlen ;
assign near_mem$dma_server_awlock = dma_server_awlock ;
assign near_mem$dma_server_awprot = dma_server_awprot ;
assign near_mem$dma_server_awqos = dma_server_awqos ;
assign near_mem$dma_server_awregion = dma_server_awregion ;
assign near_mem$dma_server_awsize = dma_server_awsize ;
assign near_mem$dma_server_awvalid = dma_server_awvalid ;
assign near_mem$dma_server_bready = dma_server_bready ;
assign near_mem$dma_server_rready = dma_server_rready ;
assign near_mem$dma_server_wdata = dma_server_wdata ;
assign near_mem$dma_server_wlast = dma_server_wlast ;
assign near_mem$dma_server_wstrb = dma_server_wstrb ;
assign near_mem$dma_server_wvalid = dma_server_wvalid ;
assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h7929 ;
assign near_mem$dmem_req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
assign near_mem$dmem_req_op =
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 !=
2'd1 ;
assign near_mem$dmem_req_priv =
csr_regfile$read_mstatus[17] ?
csr_regfile$read_mstatus[12:11] :
rg_cur_priv ;
assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
assign near_mem$dmem_req_sstatus_SUM = 1'd0 ;
assign near_mem$dmem_req_store_value =
{ 32'd0, x_out_data_to_stage2_val2__h7931 } ;
assign near_mem$imem_master_arready = imem_master_arready ;
assign near_mem$imem_master_awready = imem_master_awready ;
assign near_mem$imem_master_bid = imem_master_bid ;
assign near_mem$imem_master_bresp = imem_master_bresp ;
assign near_mem$imem_master_bvalid = imem_master_bvalid ;
assign near_mem$imem_master_rdata = imem_master_rdata ;
assign near_mem$imem_master_rid = imem_master_rid ;
assign near_mem$imem_master_rlast = imem_master_rlast ;
assign near_mem$imem_master_rresp = imem_master_rresp ;
assign near_mem$imem_master_rvalid = imem_master_rvalid ;
assign near_mem$imem_master_wready = imem_master_wready ;
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_near_mem$imem_req_2__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_near_mem$imem_req_2__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4 or
MUX_rg_state$write_1__SEL_7 or MUX_near_mem$imem_req_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
near_mem$imem_req_addr = MUX_imem_rg_tval$write_1__VAL_4;
MUX_rg_state$write_1__SEL_7:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_4;
default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign near_mem$imem_req_f3 =
WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
assign near_mem$imem_req_mstatus_MXR =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_rg_state$write_1__SEL_7) ?
csr_regfile$read_mstatus[19] :
imem_rg_mstatus_MXR ;
assign near_mem$imem_req_priv =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_rg_state$write_1__SEL_7) ?
rg_cur_priv :
imem_rg_priv ;
assign near_mem$imem_req_satp =
WILL_FIRE_RL_imem_rl_fetch_next_32b ?
imem_rg_satp :
csr_regfile$read_satp ;
assign near_mem$imem_req_sstatus_SUM =
WILL_FIRE_RL_imem_rl_fetch_next_32b && imem_rg_sstatus_SUM ;
assign near_mem$mem_master_arready = mem_master_arready ;
assign near_mem$mem_master_awready = mem_master_awready ;
assign near_mem$mem_master_bid = mem_master_bid ;
assign near_mem$mem_master_bresp = mem_master_bresp ;
assign near_mem$mem_master_bvalid = mem_master_bvalid ;
assign near_mem$mem_master_rdata = mem_master_rdata ;
assign near_mem$mem_master_rid = mem_master_rid ;
assign near_mem$mem_master_rlast = mem_master_rlast ;
assign near_mem$mem_master_rresp = mem_master_rresp ;
assign near_mem$mem_master_rvalid = mem_master_rvalid ;
assign near_mem$mem_master_wready = mem_master_wready ;
assign near_mem$server_fence_request_put =
8'b10101010 /* unspecified value */ ;
assign near_mem$set_watch_tohost_tohost_addr =
set_watch_tohost_tohost_addr ;
assign near_mem$set_watch_tohost_watch_tohost =
set_watch_tohost_watch_tohost ;
assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ;
assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ;
assign near_mem$EN_imem_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign near_mem$EN_dmem_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 &&
(IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 ==
2'd1 ||
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 ==
2'd2) ;
assign near_mem$EN_server_fence_i_request_put =
CAN_FIRE_RL_rl_stage1_FENCE_I ;
assign near_mem$EN_server_fence_i_response_get =
CAN_FIRE_RL_rl_finish_FENCE_I ;
assign near_mem$EN_server_fence_request_put = CAN_FIRE_RL_rl_stage1_FENCE ;
assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
assign near_mem$EN_set_watch_tohost = EN_set_watch_tohost ;
assign near_mem$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// submodule stage1_f_reset_reqs
assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_reqs$CLR = 1'b0 ;
// submodule stage1_f_reset_rsps
assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage1_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_f_reset_reqs
assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ;
assign stage2_f_reset_reqs$CLR = 1'b0 ;
// submodule stage2_f_reset_rsps
assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage2_f_reset_rsps$CLR = 1'b0 ;
// submodule stage3_f_reset_reqs
assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_reqs$CLR = 1'b0 ;
// submodule stage3_f_reset_rsps
assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage3_f_reset_rsps$CLR = 1'b0 ;
// submodule stageD_f_reset_reqs
assign stageD_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageD_f_reset_reqs$DEQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_reqs$CLR = 1'b0 ;
// submodule stageD_f_reset_rsps
assign stageD_f_reset_rsps$ENQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageD_f_reset_rsps$CLR = 1'b0 ;
// submodule stageF_branch_predictor
assign stageF_branch_predictor$bp_train_cf_info =
(stage1_rg_full &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0) ?
{ IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500,
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263,
alu_outputs_cf_info_fallthru_PC__h9549,
alu_outputs_cf_info_taken_PC__h9550 } :
99'h6AAAAAAAAAAAAAAAAAAAAAAAA ;
assign stageF_branch_predictor$bp_train_instr = d_instr__h15539 ;
assign stageF_branch_predictor$bp_train_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1078 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign stageF_branch_predictor$bp_train_pc = imem_rg_pc ;
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
stageF_branch_predictor$predict_req_pc =
soc_map$m_pc_reset_value[31:0];
MUX_imem_rg_cache_addr$write_1__SEL_2:
stageF_branch_predictor$predict_req_pc =
stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7:
stageF_branch_predictor$predict_req_pc = rg_next_pc;
default: stageF_branch_predictor$predict_req_pc =
32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign stageF_branch_predictor$predict_rsp_instr = d_instr__h15539 ;
assign stageF_branch_predictor$predict_rsp_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1078 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign stageF_branch_predictor$EN_reset = 1'b0 ;
assign stageF_branch_predictor$EN_predict_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign stageF_branch_predictor$EN_bp_train =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 ;
// submodule stageF_f_reset_reqs
assign stageF_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageF_f_reset_reqs$DEQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_reqs$CLR = 1'b0 ;
// submodule stageF_f_reset_rsps
assign stageF_f_reset_rsps$ENQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageF_f_reset_rsps$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 =
next_pc__h7870 == stage1_rg_stage_input[183:152] ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1311 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1307 ?
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
!IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118) :
stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1314 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1311 &&
stageD_rg_full ||
!stageF_rg_full ||
!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1413 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1307 ?
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 ||
!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125 :
!stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 =
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1413 ||
!stageD_rg_full) &&
stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1461 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
!IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1473 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 &&
(csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1468 ||
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719) ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1501 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1307 ?
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1344 :
stage1_rg_full ;
assign IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1095 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1092 ?
{ 16'b0,
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ?
near_mem$imem_instr[31:16] :
imem_rg_cache_b16 } :
near_mem$imem_instr ;
assign IF_NOT_near_mem_dmem_valid__16_32_OR_NOT_near__ETC___d173 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) ?
((stage2_rg_stage2[100:96] == 5'd0) ? 2'd0 : 2'd1) :
2'd0 ;
assign IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1344 =
!IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118) ;
assign IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 =
IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 ||
!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125 ;
assign IF_NOT_stage1_rg_stage_input_88_BITS_112_TO_11_ETC___d370 =
NOT_stage1_rg_stage_input_88_BITS_112_TO_110_1_ETC___d289 ?
4'd12 :
4'd1 ;
assign IF_csr_regfile_read_csr_rg_trap_instr_545_BITS_ETC___d1598 =
csr_regfile$read_csr[31:0] | rs1_val__h22768 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d947 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:42] == 6'b100011 &&
stageD_rg_data[38:37] == 2'b0) ?
instr__h14984 :
((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
stageD_rg_data[47:44] == 4'b1001 &&
stageD_rg_data[43:39] == 5'd0 &&
stageD_rg_data[38:34] == 5'd0) ?
instr__h15322 :
32'h0) ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d949 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:42] == 6'b100011 &&
stageD_rg_data[38:37] == 2'b10) ?
instr__h14712 :
((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:42] == 6'b100011 &&
stageD_rg_data[38:37] == 2'b01) ?
instr__h14848 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d947) ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d951 =
(csr_regfile_read_misa__2_BIT_2_34_AND_stageD_r_ETC___d818 &&
stageD_rg_data[38:34] != 5'd0) ?
instr__h14481 :
((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:42] == 6'b100011 &&
stageD_rg_data[38:37] == 2'b11) ?
instr__h14576 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d949) ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d952 =
(csr_regfile_read_misa__2_BIT_2_34_AND_stageD_r_ETC___d812 &&
stageD_rg_data[38:34] != 5'd0) ?
instr__h14362 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d951 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d954 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b100 &&
stageD_rg_data[43:42] == 2'b01 &&
imm6__h12508 != 6'd0 &&
!stageD_rg_data[44]) ?
instr__h14067 :
((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b100 &&
stageD_rg_data[43:42] == 2'b10) ?
instr__h14184 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d952) ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d955 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b100 &&
stageD_rg_data[43:42] == 2'b0 &&
imm6__h12508 != 6'd0 &&
!stageD_rg_data[44]) ?
instr__h13874 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d954 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d956 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
stageD_rg_data[47:45] == 3'b0 &&
stageD_rg_data[43:39] != 5'd0 &&
imm6__h12508 != 6'd0 &&
!stageD_rg_data[44]) ?
instr__h13681 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d955 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d958 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b011 &&
stageD_rg_data[43:39] == 5'd2 &&
nzimm10__h13132 != 10'd0) ?
instr__h13336 :
((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b0 &&
stageD_rg_data[47:45] == 3'b0 &&
nzimm10__h13347 != 10'd0) ?
instr__h13508 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d956) ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d959 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b0 &&
stageD_rg_data[43:39] != 5'd0 &&
imm6__h12508 != 6'd0 ||
csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b0 &&
stageD_rg_data[43:39] == 5'd0 &&
imm6__h12508 == 6'd0) ?
instr__h12899 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d958 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d960 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b011 &&
stageD_rg_data[43:39] != 5'd0 &&
stageD_rg_data[43:39] != 5'd2 &&
imm6__h12508 != 6'd0) ?
instr__h12770 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d959 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d962 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b111) ?
instr__h12248 :
((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b010 &&
stageD_rg_data[43:39] != 5'd0) ?
instr__h12586 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d960) ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d963 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b110) ?
instr__h11931 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d962 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d964 =
(csr_regfile_read_misa__2_BIT_2_34_AND_stageD_r_ETC___d818 &&
stageD_rg_data[38:34] == 5'd0) ?
instr__h11866 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d963 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d965 =
(csr_regfile_read_misa__2_BIT_2_34_AND_stageD_r_ETC___d812 &&
stageD_rg_data[38:34] == 5'd0) ?
instr__h11750 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d964 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d966 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b001) ?
instr__h11360 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d965 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d967 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
stageD_rg_data[47:45] == 3'b101) ?
instr__h11017 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d966 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d968 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b0 &&
stageD_rg_data[47:45] == 3'b110) ?
instr__h10788 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d967 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d969 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b0 &&
stageD_rg_data[47:45] == 3'b010) ?
instr__h10593 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d968 ;
assign IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d970 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
stageD_rg_data[47:45] == 3'b110) ?
instr__h10401 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d969 ;
assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1096 =
(imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] != 2'b11) ?
instr_out___1__h15563 :
IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1095 ;
assign IF_rg_cur_priv_4_EQ_0b11_84_AND_stage1_rg_stag_ETC___d398 =
(rg_cur_priv == 2'b11 &&
stage1_rg_stage_input[87:76] == 12'b001100000010) ?
4'd8 :
(rg_cur_priv_4_EQ_0b11_84_OR_rg_cur_priv_4_EQ_0_ETC___d396 ?
4'd11 :
4'd12) ;
assign IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 =
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ?
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q16 :
2'd0 ;
assign IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d252 =
rs1_val_bypassed__h5141 == rs2_val__h8057 ;
assign IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d254 =
(rs1_val_bypassed__h5141 ^ 32'h80000000) <
(rs2_val__h8057 ^ 32'h80000000) ;
assign IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d256 =
rs1_val_bypassed__h5141 < rs2_val__h8057 ;
assign IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d310 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 :
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
stage1_rg_stage_input[81] :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q7) ;
assign IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d321 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 ;
assign IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d357 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'b0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316 :
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
!stage1_rg_stage_input[81] :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8) ;
assign IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d359 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'b0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 :
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ;
assign IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d641 =
((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
alu_outputs___1_val1__h8187 :
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d640 ;
assign IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 =
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ?
(stage1_rg_stage_input[268] ?
4'd12 :
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d415) :
4'd0 ;
assign IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 =
stage2_rg_full ?
IF_stage2_rg_stage2_00_BITS_102_TO_101_01_EQ_0_ETC___d121 :
2'd0 ;
assign IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d1296 =
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 ==
2'd1 &&
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194) ||
stage1_rg_stage_input[268] ||
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d310 &&
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d321 ;
assign IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 =
stage2_rg_full ?
CASE_stage2_rg_stage2_BITS_102_TO_101_0_2_1_IF_ETC__q5 :
2'd0 ;
assign IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192 =
stage2_rg_stage2[100:96] == stage1_rg_stage_input[139:135] ;
assign IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194 =
stage2_rg_stage2[100:96] == stage1_rg_stage_input[134:130] ;
assign IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362 =
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 ==
2'd1 &&
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194) ||
!stage1_rg_stage_input[268] &&
(IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d357 ||
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d359) ;
assign IF_stage2_rg_stage2_00_BITS_102_TO_101_01_EQ_0_ETC___d121 =
(stage2_rg_stage2[102:101] == 2'd0) ?
2'd2 :
(near_mem$dmem_valid ?
(near_mem$dmem_exc ? 2'd3 : 2'd2) :
2'd1) ;
assign NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d1359 =
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 &&
(stage2_rg_stage2[102:101] == 2'd0 ||
near_mem$dmem_valid && !near_mem$dmem_exc) ;
assign NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 =
cur_verbosity__h3701 > 4'd1 ;
assign NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304 =
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 !=
2'd1 ||
!IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192 &&
!IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194) &&
!stage1_rg_stage_input[268] &&
(IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d357 ||
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d359) ;
assign NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d145 =
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd3 &&
(stage2_rg_stage2[102:101] == 2'd0 ||
near_mem$dmem_valid && !near_mem$dmem_exc) ;
assign NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 =
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 !=
2'd1 ||
!IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192 &&
!IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194) &&
(stage1_rg_stage_input[268] ||
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d310 &&
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d321) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1303 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d1299) &&
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd2 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd0) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1307 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1303 &&
stage1_rg_full &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1316 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d1296 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1316 &&
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd2 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd0) &&
stage1_rg_full &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1325 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1318 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
!IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 ||
(imem_rg_pc[1:0] == 2'b0 || near_mem$imem_exc ||
!imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1347 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
NOT_stage1_rg_full_87_66_OR_stage1_rg_stage_in_ETC___d1340 ||
NOT_stage1_rg_full_87_66_OR_stage1_rg_stage_in_ETC___d1342 ||
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1344 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd0 ||
stage3_rg_full ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1368 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd2 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd0) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1316 &&
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd2 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd0) &&
stage1_rg_full &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1395 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1410 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 &&
!IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1520 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
!stage1_rg_stage_input[268] &&
(IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d357 ||
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d359) ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1078 =
imem_rg_pc[1:0] != 2'b0 &&
imem_rg_pc_BITS_31_TO_2_4_EQ_imem_rg_cache_add_ETC___d1070 &&
near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_072___d1073 &&
imem_rg_cache_b16[1:0] == 2'b11 ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1092 =
imem_rg_pc[1:0] != 2'b0 &&
(imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[17:16] != 2'b11 ||
imem_rg_pc_BITS_31_TO_2_4_EQ_imem_rg_cache_add_ETC___d1070 &&
imem_rg_cache_b16[1:0] != 2'b11) ;
assign NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1111 =
!near_mem$imem_exc &&
(imem_rg_pc[1:0] == 2'b0 ||
!imem_rg_pc_BITS_31_TO_2_4_EQ_imem_rg_cache_add_ETC___d1070 ||
!near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_072___d1073 ||
imem_rg_cache_b16[1:0] != 2'b11) &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[1:0] != 2'b11) ;
assign NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118 =
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1111 &&
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1115 &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[1:0] == 2'b11) ;
assign NOT_rg_next_pc_609_BITS_1_TO_0_610_EQ_0b0_611__ETC___d1617 =
rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h28607 == near_mem$imem_pc ;
assign NOT_rg_run_on_reset_250_251_OR_imem_rg_pc_BITS_ETC___d1258 =
!rg_run_on_reset ||
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1254 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign NOT_soc_map_m_pc_reset_value__270_BITS_1_TO_0__ETC___d1285 =
soc_map$m_pc_reset_value[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h17387 == near_mem$imem_pc ;
assign NOT_stage1_rg_full_87_66_OR_stage1_rg_stage_in_ETC___d1340 =
(!stage1_rg_full ||
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d1296 ||
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd0) &&
(!stage1_rg_full ||
!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) ;
assign NOT_stage1_rg_full_87_66_OR_stage1_rg_stage_in_ETC___d1342 =
(!stage1_rg_full ||
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d1296) &&
(!stage1_rg_full ||
!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) ;
assign NOT_stage1_rg_stage_input_88_BITS_112_TO_110_1_ETC___d289 =
(stage1_rg_stage_input[112:110] != 3'b0 ||
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[230]) &&
(stage1_rg_stage_input[112:110] != 3'b0 ||
stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[230]) &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ;
assign NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d1663 =
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 ||
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 ;
assign NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d1667 =
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d1663 &&
stage1_rg_full &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324) &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd0 &&
!stage3_rg_full ;
assign NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 =
!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 !=
2'd1 ||
!IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192 &&
!IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194 ;
assign NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d491 =
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd1 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd2 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd3 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd4 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd5 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd6 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd7 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd8 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd9 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd10 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd11 ;
assign NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d503 =
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 ==
2'd3 ;
assign NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d507 =
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 ==
2'd0 ;
assign NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d513 =
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 !=
2'd3 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 !=
2'd0 ;
assign NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1484 =
stageF_branch_predictor$predict_rsp[1:0] != 2'b0 &&
near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h20412 == near_mem$imem_pc ;
assign SEXT_stage1_rg_stage_input_88_BITS_87_TO_76_80___d528 =
{ {20{stage1_rg_stage_input_BITS_87_TO_76__q14[11]}},
stage1_rg_stage_input_BITS_87_TO_76__q14 } ;
assign SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798 =
{ {9{offset__h10964[11]}}, offset__h10964 } ;
assign SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827 =
{ {4{offset__h11875[8]}}, offset__h11875 } ;
assign _theResult_____1_fst__h8884 =
(stage1_rg_stage_input[112:110] == 3'b0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[230]) ?
rd_val___1__h8880 :
_theResult_____1_fst__h8891 ;
assign _theResult_____1_fst__h8919 =
rs1_val_bypassed__h5141 & _theResult___snd__h9864 ;
assign _theResult____h21609 =
(delta_CPI_instrs__h21608 == 64'd0) ?
delta_CPI_instrs___1__h21644 :
delta_CPI_instrs__h21608 ;
assign _theResult____h5412 = x_out_data_to_stage1_instr__h10055 ;
assign _theResult___snd__h9864 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
SEXT_stage1_rg_stage_input_88_BITS_87_TO_76_80___d528 :
rs2_val__h8057 ;
assign addr_of_b32___1__h17506 = addr_of_b32__h17387 + 32'd4 ;
assign addr_of_b32___1__h20531 = addr_of_b32__h20412 + 32'd4 ;
assign addr_of_b32___1__h28726 = addr_of_b32__h28607 + 32'd4 ;
assign addr_of_b32__h17387 = { soc_map$m_pc_reset_value[31:2], 2'd0 } ;
assign addr_of_b32__h20412 =
{ stageF_branch_predictor$predict_rsp[31:2], 2'd0 } ;
assign addr_of_b32__h28607 = { rg_next_pc[31:2], 2'd0 } ;
assign alu_outputs___1_addr__h8084 =
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 ?
branch_target__h8061 :
x_out_cf_info_fallthru_PC__h9557 ;
assign alu_outputs___1_addr__h8290 =
rs1_val_bypassed__h5141 +
{ {20{stage1_rg_stage_input_BITS_75_TO_64__q6[11]}},
stage1_rg_stage_input_BITS_75_TO_64__q6 } ;
assign alu_outputs___1_exc_code__h8479 =
(stage1_rg_stage_input[112:110] == 3'b0) ?
((stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0) ?
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 :
4'd2) :
4'd2 ;
assign alu_outputs___1_val1__h8187 =
(stage1_rg_stage_input[112:110] == 3'b001) ?
rd_val__h9761 :
(stage1_rg_stage_input[230] ? rd_val__h9834 : rd_val__h9812) ;
assign alu_outputs___1_val1__h8223 =
(stage1_rg_stage_input[112:110] == 3'b0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[230])) ?
rd_val___1__h8872 :
_theResult_____1_fst__h8884 ;
assign alu_outputs___1_val1__h8483 =
stage1_rg_stage_input[112] ?
{ 27'd0, stage1_rg_stage_input[139:135] } :
rs1_val_bypassed__h5141 ;
assign alu_outputs_cf_info_fallthru_PC__h9549 =
x_out_cf_info_fallthru_PC__h9557 ;
assign alu_outputs_cf_info_taken_PC__h9550 = x_out_cf_info_taken_PC__h9558 ;
assign branch_target__h8061 =
stage1_rg_stage_input[305:274] +
{ {19{stage1_rg_stage_input_BITS_63_TO_51__q1[12]}},
stage1_rg_stage_input_BITS_63_TO_51__q1 } ;
assign cpi__h21611 = x__h21610 / 64'd10 ;
assign cpifrac__h21612 = x__h21610 % 64'd10 ;
assign csr_regfile_RDY_server_reset_request_put__224__ETC___d1236 =
csr_regfile$RDY_server_reset_request_put &&
f_reset_reqs$EMPTY_N &&
stageF_f_reset_reqs$FULL_N &&
stageD_f_reset_reqs$FULL_N &&
stage1_f_reset_reqs$FULL_N &&
stage2_f_reset_reqs$FULL_N &&
stage3_f_reset_reqs$FULL_N ;
assign csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1464 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324) ;
assign csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1468 =
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1464 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd2 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd0 ||
!stage1_rg_full ||
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d1296 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1471 =
(csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1468 ||
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719) &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1475 =
(csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1468 ||
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719) &&
!near_mem$imem_exc ;
assign csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1510 =
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1468 ||
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1311 &&
stageD_rg_full ;
assign csr_regfile_read_csr_mcycle__3_MINUS_rg_start__ETC___d1548 =
delta_CPI_cycles__h21607 * 64'd10 ;
assign csr_regfile_read_misa__2_BIT_2_34_AND_stageD_r_ETC___d812 =
csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
stageD_rg_data[47:44] == 4'b1000 &&
stageD_rg_data[43:39] != 5'd0 ;
assign csr_regfile_read_misa__2_BIT_2_34_AND_stageD_r_ETC___d818 =
csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
stageD_rg_data[47:44] == 4'b1001 &&
stageD_rg_data[43:39] != 5'd0 ;
assign cur_verbosity__h3701 =
(csr_regfile$read_csr_minstret < cfg_logdelay) ?
4'd0 :
cfg_verbosity ;
assign d_instr__h15539 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1078 ?
instr_out___1__h15541 :
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1096 ;
assign data_to_stage2_addr__h7919 = x_out_data_to_stage2_addr__h7929 ;
assign data_to_stage2_rd__h7918 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
5'd0 :
stage1_rg_stage_input[144:140] ;
assign decoded_instr_funct10__h19078 =
{ _theResult____h5412[31:25], _theResult____h5412[14:12] } ;
assign decoded_instr_imm12_S__h19080 =
{ _theResult____h5412[31:25], _theResult____h5412[11:7] } ;
assign decoded_instr_imm13_SB__h19081 =
{ _theResult____h5412[31],
_theResult____h5412[7],
_theResult____h5412[30:25],
_theResult____h5412[11:8],
1'b0 } ;
assign decoded_instr_imm21_UJ__h19083 =
{ _theResult____h5412[31],
_theResult____h5412[19:12],
_theResult____h5412[20],
_theResult____h5412[30:21],
1'b0 } ;
assign delta_CPI_cycles__h21607 =
csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
assign delta_CPI_instrs___1__h21644 = delta_CPI_instrs__h21608 + 64'd1 ;
assign delta_CPI_instrs__h21608 =
csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
assign eaddr__h8260 =
rs1_val_bypassed__h5141 +
SEXT_stage1_rg_stage_input_88_BITS_87_TO_76_80___d528 ;
assign fall_through_pc__h7869 =
stage1_rg_stage_input[305:274] +
(stage1_rg_stage_input[269] ? 32'd4 : 32'd2) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1115 =
imem_rg_pc[1:0] == 2'b0 ||
(!imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[17:16] == 2'b11) &&
(!imem_rg_pc_BITS_31_TO_2_4_EQ_imem_rg_cache_add_ETC___d1070 ||
imem_rg_cache_b16[1:0] == 2'b11) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1254 =
imem_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
near_mem$imem_exc ||
!imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ;
assign imem_rg_pc_BITS_31_TO_2_4_EQ_imem_rg_cache_add_ETC___d1070 =
imem_rg_pc[31:2] == imem_rg_cache_addr[31:2] ;
assign imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 =
imem_rg_pc[31:2] == near_mem$imem_pc[31:2] ;
assign imm12__h10257 = { 4'd0, offset__h10129 } ;
assign imm12__h10594 = { 5'd0, offset__h10536 } ;
assign imm12__h12510 = { {6{imm6__h12508[5]}}, imm6__h12508 } ;
assign imm12__h13134 = { {2{nzimm10__h13132[9]}}, nzimm10__h13132 } ;
assign imm12__h13349 = { 2'd0, nzimm10__h13347 } ;
assign imm12__h13545 = { 7'b0, stageD_rg_data[38:34] } ;
assign imm12__h13890 = { 7'b0100000, stageD_rg_data[38:34] } ;
assign imm20__h12638 = { {14{imm6__h12508[5]}}, imm6__h12508 } ;
assign imm6__h12508 = { stageD_rg_data[44], stageD_rg_data[38:34] } ;
assign instr___1__h10091 =
(csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
stageD_rg_data[43:39] != 5'd0 &&
stageD_rg_data[47:45] == 3'b010) ?
instr__h10256 :
IF_csr_regfile_read_misa__2_BIT_2_34_AND_stage_ETC___d970 ;
assign instr__h10256 =
{ imm12__h10257, 8'd18, stageD_rg_data[43:39], 7'b0000011 } ;
assign instr__h10401 =
{ 4'd0,
stageD_rg_data[40:39],
stageD_rg_data[44],
stageD_rg_data[38:34],
8'd18,
offset_BITS_4_TO_0___h10525,
7'b0100011 } ;
assign instr__h10593 =
{ imm12__h10594, rs1__h10595, 3'b010, rd__h10596, 7'b0000011 } ;
assign instr__h10788 =
{ 5'd0,
stageD_rg_data[37],
stageD_rg_data[44],
rd__h10596,
rs1__h10595,
3'b010,
offset_BITS_4_TO_0___h10956,
7'b0100011 } ;
assign instr__h11017 =
{ SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798[20],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798[10:1],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798[11],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798[19:12],
12'd111 } ;
assign instr__h11360 =
{ SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798[20],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798[10:1],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798[11],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d798[19:12],
12'd239 } ;
assign instr__h11750 = { 12'd0, stageD_rg_data[43:39], 15'd103 } ;
assign instr__h11866 = { 12'd0, stageD_rg_data[43:39], 15'd231 } ;
assign instr__h11931 =
{ SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827[12],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827[10:5],
5'd0,
rs1__h10595,
3'b0,
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827[4:1],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827[11],
7'b1100011 } ;
assign instr__h12248 =
{ SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827[12],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827[10:5],
5'd0,
rs1__h10595,
3'b001,
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827[4:1],
SEXT_stageD_rg_data_29_BIT_44_46_CONCAT_stageD_ETC___d827[11],
7'b1100011 } ;
assign instr__h12586 =
{ imm12__h12510, 8'd0, stageD_rg_data[43:39], 7'b0010011 } ;
assign instr__h12770 =
{ imm20__h12638, stageD_rg_data[43:39], 7'b0110111 } ;
assign instr__h12899 =
{ imm12__h12510,
stageD_rg_data[43:39],
3'b0,
stageD_rg_data[43:39],
7'b0010011 } ;
assign instr__h13336 =
{ imm12__h13134,
stageD_rg_data[43:39],
3'b0,
stageD_rg_data[43:39],
7'b0010011 } ;
assign instr__h13508 = { imm12__h13349, 8'd16, rd__h10596, 7'b0010011 } ;
assign instr__h13681 =
{ imm12__h13545,
stageD_rg_data[43:39],
3'b001,
stageD_rg_data[43:39],
7'b0010011 } ;
assign instr__h13874 =
{ imm12__h13545, rs1__h10595, 3'b101, rs1__h10595, 7'b0010011 } ;
assign instr__h14067 =
{ imm12__h13890, rs1__h10595, 3'b101, rs1__h10595, 7'b0010011 } ;
assign instr__h14184 =
{ imm12__h12510, rs1__h10595, 3'b111, rs1__h10595, 7'b0010011 } ;
assign instr__h14362 =
{ 7'b0,
stageD_rg_data[38:34],
8'd0,
stageD_rg_data[43:39],
7'b0110011 } ;
assign instr__h14481 =
{ 7'b0,
stageD_rg_data[38:34],
stageD_rg_data[43:39],
3'b0,
stageD_rg_data[43:39],
7'b0110011 } ;
assign instr__h14576 =
{ 7'b0,
rd__h10596,
rs1__h10595,
3'b111,
rs1__h10595,
7'b0110011 } ;
assign instr__h14712 =
{ 7'b0,
rd__h10596,
rs1__h10595,
3'b110,
rs1__h10595,
7'b0110011 } ;
assign instr__h14848 =
{ 7'b0,
rd__h10596,
rs1__h10595,
3'b100,
rs1__h10595,
7'b0110011 } ;
assign instr__h14984 =
{ 7'b0100000,
rd__h10596,
rs1__h10595,
3'b0,
rs1__h10595,
7'b0110011 } ;
assign instr__h15322 =
{ 12'b000000000001,
stageD_rg_data[43:39],
3'b0,
stageD_rg_data[43:39],
7'b1110011 } ;
assign instr_out___1__h15541 =
{ near_mem$imem_instr[15:0], imem_rg_cache_b16 } ;
assign instr_out___1__h15563 = { 16'b0, near_mem$imem_instr[15:0] } ;
assign near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1123 =
near_mem$imem_exc ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1078 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125 =
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1123 ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1092 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_31_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] != 2'b11 ;
assign near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_072___d1073 =
near_mem$imem_pc == imem_rg_pc + 32'd2 ;
assign near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d1220 =
near_mem$imem_valid && near_mem$imem_exc &&
near_mem$imem_exc_code != 4'd0 &&
near_mem$imem_exc_code != 4'd1 &&
near_mem$imem_exc_code != 4'd2 &&
near_mem$imem_exc_code != 4'd3 &&
near_mem$imem_exc_code != 4'd4 &&
near_mem$imem_exc_code != 4'd5 &&
near_mem$imem_exc_code != 4'd6 &&
near_mem$imem_exc_code != 4'd7 &&
near_mem$imem_exc_code != 4'd8 &&
near_mem$imem_exc_code != 4'd9 &&
near_mem$imem_exc_code != 4'd11 &&
near_mem$imem_exc_code != 4'd12 &&
near_mem$imem_exc_code != 4'd13 &&
near_mem$imem_exc_code != 4'd15 ;
assign new_epoch__h16901 = rg_epoch + 2'd1 ;
assign next_pc___1__h9189 = stage1_rg_stage_input[305:274] + 32'd2 ;
assign next_pc__h7870 = x_out_next_pc__h7886 ;
assign next_pc__h8090 =
stage1_rg_stage_input[305:274] +
{ {11{stage1_rg_stage_input_BITS_30_TO_10__q2[20]}},
stage1_rg_stage_input_BITS_30_TO_10__q2 } ;
assign next_pc__h8117 = { eaddr__h8260[31:1], 1'd0 } ;
assign next_pc__h9186 = stage1_rg_stage_input[305:274] + 32'd4 ;
assign nzimm10__h13132 =
{ stageD_rg_data[44],
stageD_rg_data[36:35],
stageD_rg_data[37],
stageD_rg_data[34],
stageD_rg_data[38],
4'b0 } ;
assign nzimm10__h13347 =
{ stageD_rg_data[42:39],
stageD_rg_data[44:43],
stageD_rg_data[37],
stageD_rg_data[38],
2'b0 } ;
assign offset_BITS_4_TO_0___h10525 = { stageD_rg_data[43:41], 2'b0 } ;
assign offset_BITS_4_TO_0___h10956 =
{ stageD_rg_data[43:42], stageD_rg_data[38], 2'b0 } ;
assign offset__h10129 =
{ stageD_rg_data[35:34],
stageD_rg_data[44],
stageD_rg_data[38:36],
2'b0 } ;
assign offset__h10536 =
{ stageD_rg_data[37],
stageD_rg_data[44:42],
stageD_rg_data[38],
2'b0 } ;
assign offset__h10964 =
{ stageD_rg_data[44],
stageD_rg_data[40],
stageD_rg_data[42:41],
stageD_rg_data[38],
stageD_rg_data[39],
stageD_rg_data[34],
stageD_rg_data[43],
stageD_rg_data[37:35],
1'b0 } ;
assign offset__h11875 =
{ stageD_rg_data[44],
stageD_rg_data[38:37],
stageD_rg_data[34],
stageD_rg_data[43:42],
stageD_rg_data[36:35],
1'b0 } ;
assign rd__h10596 = { 2'b01, stageD_rg_data[36:34] } ;
assign rd_val___1__h8872 =
rs1_val_bypassed__h5141 + _theResult___snd__h9864 ;
assign rd_val___1__h8880 =
rs1_val_bypassed__h5141 - _theResult___snd__h9864 ;
assign rd_val___1__h8887 =
((rs1_val_bypassed__h5141 ^ 32'h80000000) <
(_theResult___snd__h9864 ^ 32'h80000000)) ?
32'd1 :
32'd0 ;
assign rd_val___1__h8894 =
(rs1_val_bypassed__h5141 < _theResult___snd__h9864) ?
32'd1 :
32'd0 ;
assign rd_val___1__h8901 =
rs1_val_bypassed__h5141 ^ _theResult___snd__h9864 ;
assign rd_val___1__h8908 =
rs1_val_bypassed__h5141 | _theResult___snd__h9864 ;
assign rd_val__h7771 =
(stage3_rg_full && stage3_rg_stage3[37] &&
stage3_rg_stage3[36:32] == stage1_rg_stage_input[139:135]) ?
stage3_rg_stage3[31:0] :
gpr_regfile$read_rs1 ;
assign rd_val__h7845 =
(stage3_rg_full && stage3_rg_stage3[37] &&
stage3_rg_stage3[36:32] == stage1_rg_stage_input[134:130]) ?
stage3_rg_stage3[31:0] :
gpr_regfile$read_rs2 ;
assign rd_val__h8230 = { stage1_rg_stage_input[50:31], 12'h0 } ;
assign rd_val__h8244 = stage1_rg_stage_input[305:274] + rd_val__h8230 ;
assign rd_val__h9761 = rs1_val_bypassed__h5141 << shamt__h8174 ;
assign rd_val__h9812 = rs1_val_bypassed__h5141 >> shamt__h8174 ;
assign rd_val__h9834 =
rs1_val_bypassed__h5141 >> shamt__h8174 |
~(32'hFFFFFFFF >> shamt__h8174) &
{32{rs1_val_bypassed__h5141[31]}} ;
assign rg_cur_priv_4_EQ_0b11_84_OR_rg_cur_priv_4_EQ_0_ETC___d396 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
stage1_rg_stage_input[87:76] == 12'b000100000101 ;
assign rg_state_3_EQ_12_0_AND_csr_regfile_wfi_resume__ETC___d1654 =
rg_state == 4'd12 && csr_regfile$wfi_resume &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524 =
rg_state == 4'd3 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1520 &&
!stage3_rg_full &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 ==
2'd0 &&
stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 ;
assign rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1634 =
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd6 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1643 =
rg_state_3_EQ_3_327_AND_NOT_csr_regfile_interr_ETC___d1524 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd5 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign rg_state_3_EQ_3_327_AND_stage3_rg_full_0_OR_NO_ETC___d1337 =
rg_state == 4'd3 &&
(stage3_rg_full ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd0 ||
stage1_rg_full ||
stageD_rg_full ||
stageF_rg_full) &&
(stage3_rg_full ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd3) &&
stage3_rg_full_0_OR_NOT_IF_stage2_rg_full_9_TH_ETC___d1335 ;
assign rg_state_3_EQ_5_658_AND_NOT_stageF_rg_full_100_ETC___d1659 =
rg_state == 4'd5 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign rg_state_3_EQ_8_606_AND_NOT_stageF_rg_full_100_ETC___d1607 =
rg_state == 4'd8 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125) ;
assign rg_trap_info_534_BITS_67_TO_36_535_EQ_csr_regf_ETC___d1544 =
rg_trap_info[67:36] == csr_regfile$csr_trap_actions[97:66] ;
assign rs1__h10595 = { 2'b01, stageD_rg_data[41:39] } ;
assign rs1_val__h22085 =
(rg_trap_instr[14:12] == 3'b001) ?
rg_csr_val1 :
{ 27'd0, rg_trap_instr[19:15] } ;
assign rs1_val_bypassed__h5141 =
(stage1_rg_stage_input[139:135] == 5'd0) ? 32'd0 : val__h7773 ;
assign rs2_val__h8057 =
(stage1_rg_stage_input[134:130] == 5'd0) ? 32'd0 : val__h7847 ;
assign shamt__h8174 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
stage1_rg_stage_input[80:76] :
rs2_val__h8057[4:0] ;
assign stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365 =
stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) ;
assign stage1_rg_stage_input_88_BITS_112_TO_110_17_EQ_ETC___d343 =
stage1_rg_stage_input[112:110] == 3'b0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[230]) ||
stage1_rg_stage_input[112:110] == 3'b0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[230] ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111 ;
assign stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d1299 =
(stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d1296 ||
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 ==
4'd0) &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) ;
assign stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 =
stage1_rg_stage_input[271:270] == rg_epoch ;
assign stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208 =
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 ==
2'd1 &&
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194) ;
assign stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d672 =
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd0 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd1 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd2 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd3 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd4 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd5 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd6 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd7 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd8 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd9 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd10 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 !=
4'd11 ;
assign stage1_rg_stage_input_BITS_30_TO_10__q2 =
stage1_rg_stage_input[30:10] ;
assign stage1_rg_stage_input_BITS_63_TO_51__q1 =
stage1_rg_stage_input[63:51] ;
assign stage1_rg_stage_input_BITS_75_TO_64__q6 =
stage1_rg_stage_input[75:64] ;
assign stage1_rg_stage_input_BITS_87_TO_76__q14 =
stage1_rg_stage_input[87:76] ;
assign stage3_rg_full_0_OR_NOT_IF_stage2_rg_full_9_TH_ETC___d1335 =
stage3_rg_full ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 !=
2'd0 ||
!stage1_rg_full ||
!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362 ;
assign stageF_f_reset_rsps_i_notEmpty__244_AND_stageD_ETC___d1264 =
stageF_f_reset_rsps$EMPTY_N && stageD_f_reset_rsps$EMPTY_N &&
stage1_f_reset_rsps$EMPTY_N &&
stage2_f_reset_rsps$EMPTY_N &&
stage3_f_reset_rsps$EMPTY_N &&
f_reset_rsps$FULL_N &&
NOT_rg_run_on_reset_250_251_OR_imem_rg_pc_BITS_ETC___d1258 ;
assign stageF_rg_full_100_AND_near_mem_imem_valid_AND_ETC___d1132 =
stageF_rg_full && near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125 &&
!near_mem$imem_exc ;
assign trap_info_tval__h9386 =
(stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'b0 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] != 12'b0 &&
stage1_rg_stage_input[87:76] != 12'b000000000001)) ?
(stage1_rg_stage_input[269] ?
stage1_rg_stage_input[231:200] :
{ 16'd0, stage1_rg_stage_input[199:184] }) :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 ;
assign val__h7773 =
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 ==
2'd2 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d192) ?
stage2_rg_stage2[63:32] :
rd_val__h7771 ;
assign val__h7847 =
(IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 ==
2'd2 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d194) ?
stage2_rg_stage2[63:32] :
rd_val__h7845 ;
assign value__h9431 =
stage1_rg_stage_input[268] ?
stage1_rg_stage_input[263:232] :
trap_info_tval__h9386 ;
assign x__h21610 =
csr_regfile_read_csr_mcycle__3_MINUS_rg_start__ETC___d1548[63:0] /
_theResult____h21609 ;
assign x_exc_code__h29000 =
(csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
csr_regfile$interrupt_pending[3:0] :
4'd0 ;
assign x_out_cf_info_fallthru_PC__h9557 =
stage1_rg_stage_input[269] ?
next_pc__h9186 :
next_pc___1__h9189 ;
assign x_out_data_to_stage1_instr__h10055 =
stageD_rg_data[101] ? stageD_rg_data[63:32] : instr___1__h10091 ;
assign x_out_data_to_stage2_rd__h7928 =
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ?
data_to_stage2_rd__h7918 :
5'd0 ;
assign x_out_data_to_stage2_val2__h7931 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
branch_target__h8061 :
rs2_val__h8057 ;
assign x_out_next_pc__h7886 =
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d359 ?
data_to_stage2_addr__h7919 :
fall_through_pc__h7869 ;
assign x_out_trap_info_exc_code__h9391 =
stage1_rg_stage_input[268] ?
stage1_rg_stage_input[267:264] :
alu_outputs_exc_code__h8498 ;
assign y__h23037 = ~rs1_val__h22768 ;
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[102:101])
2'd0, 2'd1: x_out_data_to_stage3_rd__h7354 = stage2_rg_stage2[100:96];
default: x_out_data_to_stage3_rd__h7354 = 5'd0;
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_word64)
begin
case (stage2_rg_stage2[102:101])
2'd0: x_out_data_to_stage3_rd_val__h7355 = stage2_rg_stage2[63:32];
2'd1: x_out_data_to_stage3_rd_val__h7355 = near_mem$dmem_word64[31:0];
default: x_out_data_to_stage3_rd_val__h7355 = stage2_rg_stage2[63:32];
endcase
end
always@(rg_trap_instr or rg_csr_val1)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b011: rs1_val__h22768 = rg_csr_val1;
default: rs1_val__h22768 = { 27'd0, rg_trap_instr[19:15] };
endcase
end
always@(rg_cur_priv)
begin
case (rg_cur_priv)
2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd8;
2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd9;
default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd11;
endcase
end
always@(stage1_rg_stage_input or CASE_rg_cur_priv_0b0_8_0b1_9_11__q3)
begin
case (stage1_rg_stage_input[87:76])
12'b0:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 =
CASE_rg_cur_priv_0b0_8_0b1_9_11__q3;
12'b000000000001:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 = 4'd3;
default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 = 4'd2;
endcase
end
always@(stage1_rg_stage_input or alu_outputs___1_exc_code__h8479)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011,
7'b0001111,
7'b0010011,
7'b0010111,
7'b0100011,
7'b0110011,
7'b0110111,
7'b1100011:
alu_outputs_exc_code__h8498 = 4'd2;
7'b1100111, 7'b1101111: alu_outputs_exc_code__h8498 = 4'd0;
7'b1110011:
alu_outputs_exc_code__h8498 = alu_outputs___1_exc_code__h8479;
default: alu_outputs_exc_code__h8498 = 4'd2;
endcase
end
always@(stage2_rg_stage2 or
IF_NOT_near_mem_dmem_valid__16_32_OR_NOT_near__ETC___d173)
begin
case (stage2_rg_stage2[102:101])
2'd0: CASE_stage2_rg_stage2_BITS_102_TO_101_0_2_1_IF_ETC__q5 = 2'd2;
2'd1:
CASE_stage2_rg_stage2_BITS_102_TO_101_0_2_1_IF_ETC__q5 =
IF_NOT_near_mem_dmem_valid__16_32_OR_NOT_near__ETC___d173;
default: CASE_stage2_rg_stage2_BITS_102_TO_101_0_2_1_IF_ETC__q5 = 2'd0;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d256 or
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d252 or
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d254)
begin
case (stage1_rg_stage_input[112:110])
3'b0:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316 =
!IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d252;
3'b001:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316 =
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d252;
3'b100:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316 =
!IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d254;
3'b101:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316 =
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d254;
3'b110:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316 =
!IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d256;
default: IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d316 =
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d256;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d256 or
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d252 or
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d254)
begin
case (stage1_rg_stage_input[112:110])
3'b0:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 =
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d252;
3'b001:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 =
!IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d252;
3'b100:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 =
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d254;
3'b101:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 =
!IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d254;
3'b110:
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 =
IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d256;
default: IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 =
stage1_rg_stage_input[112:110] == 3'b111 &&
!IF_stage1_rg_stage_input_88_BITS_139_TO_135_91_ETC___d256;
endcase
end
always@(stage1_rg_stage_input or
NOT_stage1_rg_stage_input_88_BITS_112_TO_110_1_ETC___d289)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q7 =
NOT_stage1_rg_stage_input_88_BITS_112_TO_110_1_ETC___d289;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q7 =
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
((stage1_rg_stage_input[151:145] == 7'b0000011) ?
stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 :
stage1_rg_stage_input[151:145] != 7'b0100011 ||
stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010);
endcase
end
always@(stage1_rg_stage_input or
stage1_rg_stage_input_88_BITS_112_TO_110_17_EQ_ETC___d343)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8 =
stage1_rg_stage_input_88_BITS_112_TO_110_17_EQ_ETC___d343;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8 =
stage1_rg_stage_input[151:145] == 7'b0110111 ||
stage1_rg_stage_input[151:145] == 7'b0010111 ||
((stage1_rg_stage_input[151:145] == 7'b0000011) ?
stage1_rg_stage_input[112:110] == 3'b0 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b010 :
stage1_rg_stage_input[151:145] == 7'b0100011 &&
(stage1_rg_stage_input[112:110] == 3'b0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b010));
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b0, 3'b001, 3'b010, 3'b100, 3'b101:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q9 = 4'd1;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q9 = 4'd12;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b0: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q10 = 4'd5;
3'b001: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q10 = 4'd6;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q10 =
4'd12;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b0, 3'b001, 3'b010:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q11 = 4'd1;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q11 =
4'd12;
endcase
end
always@(stage1_rg_stage_input or
IF_rg_cur_priv_4_EQ_0b11_84_AND_stage1_rg_stag_ETC___d398)
begin
case (stage1_rg_stage_input[87:76])
12'b0, 12'b000000000001:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q12 = 4'd12;
default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q12 =
IF_rg_cur_priv_4_EQ_0b11_84_AND_stage1_rg_stag_ETC___d398;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q12)
begin
case (stage1_rg_stage_input[112:110])
3'b0:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13 =
(stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0) ?
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q12 :
4'd12;
3'b001, 3'b101:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13 = 4'd3;
3'b010, 3'b011, 3'b110, 3'b111:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13 = 4'd4;
3'd4: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13 = 4'd12;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q9 or
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q10 or
IF_NOT_stage1_rg_stage_input_88_BITS_112_TO_11_ETC___d370 or
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q11 or
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412 =
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q9;
7'b0001111:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412 =
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q10;
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412 =
IF_NOT_stage1_rg_stage_input_88_BITS_112_TO_11_ETC___d370;
7'b0010111, 7'b0110111:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412 = 4'd1;
7'b0100011:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412 =
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q11;
7'b1110011:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412 =
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13;
default: IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412 =
4'd12;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412 or
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d415 =
(stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111) ?
4'd12 :
(IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263 ?
4'd2 :
4'd1);
7'b1100111, 7'b1101111:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d415 = 4'd2;
default: IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d415 =
((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
(stage1_rg_stage_input[81] ? 4'd12 : 4'd1) :
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d412;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011:
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 = 2'd0;
7'b1100111:
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 = 2'd2;
7'b1101111:
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 = 2'd1;
default: IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 =
2'd3;
endcase
end
always@(stage1_rg_stage_input or
alu_outputs___1_addr__h8290 or
eaddr__h8260 or
alu_outputs___1_addr__h8084 or next_pc__h8117 or next_pc__h8090)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011: x_out_data_to_stage2_addr__h7929 = eaddr__h8260;
7'b1100011:
x_out_data_to_stage2_addr__h7929 = alu_outputs___1_addr__h8084;
7'b1100111: x_out_data_to_stage2_addr__h7929 = next_pc__h8117;
7'b1101111: x_out_data_to_stage2_addr__h7929 = next_pc__h8090;
default: x_out_data_to_stage2_addr__h7929 = alu_outputs___1_addr__h8290;
endcase
end
always@(stage1_rg_stage_input or
next_pc__h8117 or branch_target__h8061 or next_pc__h8090)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011: x_out_cf_info_taken_PC__h9558 = branch_target__h8061;
7'b1101111: x_out_cf_info_taken_PC__h9558 = next_pc__h8090;
default: x_out_cf_info_taken_PC__h9558 = next_pc__h8117;
endcase
end
always@(stage1_rg_stage_input or data_to_stage2_addr__h7919)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
data_to_stage2_addr__h7919;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
(stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'b0 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
stage1_rg_stage_input[87:76] == 12'b000000000001) ?
stage1_rg_stage_input[305:274] :
32'd0;
endcase
end
always@(stage1_rg_stage_input or
_theResult_____1_fst__h8919 or
rd_val___1__h8887 or
rd_val___1__h8894 or rd_val___1__h8901 or rd_val___1__h8908)
begin
case (stage1_rg_stage_input[112:110])
3'b010: _theResult_____1_fst__h8891 = rd_val___1__h8887;
3'b011: _theResult_____1_fst__h8891 = rd_val___1__h8894;
3'b100: _theResult_____1_fst__h8891 = rd_val___1__h8901;
3'b110: _theResult_____1_fst__h8891 = rd_val___1__h8908;
default: _theResult_____1_fst__h8891 = _theResult_____1_fst__h8919;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q16 = 2'd1;
7'b0010011,
7'b0010111,
7'b0110011,
7'b0110111,
7'b1100011,
7'b1100111,
7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q16 = 2'd0;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q16 = 2'd2;
endcase
end
always@(stage1_rg_stage_input or
alu_outputs___1_val1__h8483 or
alu_outputs___1_val1__h8223 or rd_val__h8244 or rd_val__h8230)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d640 =
alu_outputs___1_val1__h8223;
7'b0010111:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d640 =
rd_val__h8244;
7'b0110111:
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d640 =
rd_val__h8230;
default: IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d640 =
alu_outputs___1_val1__h8483;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d641 or
x_out_cf_info_fallthru_PC__h9557)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
x_out_data_to_stage2_val1__h7930 = x_out_cf_info_fallthru_PC__h9557;
default: x_out_data_to_stage2_val1__h7930 =
IF_stage1_rg_stage_input_88_BITS_151_TO_145_15_ETC___d641;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY 2'd0;
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_logdelay$EN)
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (imem_rg_cache_addr$EN)
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_addr$D_IN;
if (rg_cur_priv$EN)
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
if (rg_run_on_reset$EN)
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (stage1_rg_full$EN)
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
if (stage2_rg_full$EN)
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
if (stage2_rg_resetting$EN)
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
stage2_rg_resetting$D_IN;
if (stage3_rg_full$EN)
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
if (stageD_rg_full$EN)
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY stageD_rg_full$D_IN;
if (stageF_rg_epoch$EN)
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY stageF_rg_epoch$D_IN;
if (stageF_rg_full$EN)
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY stageF_rg_full$D_IN;
end
if (imem_rg_cache_b16$EN)
imem_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_b16$D_IN;
if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
if (imem_rg_mstatus_MXR$EN)
imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
if (imem_rg_priv$EN)
imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
if (imem_rg_satp$EN)
imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
if (imem_rg_sstatus_SUM$EN)
imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
if (imem_rg_tval$EN)
imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
if (rg_epoch$EN) rg_epoch <= `BSV_ASSIGNMENT_DELAY rg_epoch$D_IN;
if (rg_mstatus_MXR$EN)
rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
if (rg_sstatus_SUM$EN)
rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
if (rg_start_CPI_cycles$EN)
rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
if (rg_start_CPI_instrs$EN)
rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
if (rg_trap_info$EN)
rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
if (rg_trap_instr$EN)
rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
if (rg_trap_interrupt$EN)
rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
if (stage1_rg_stage_input$EN)
stage1_rg_stage_input <= `BSV_ASSIGNMENT_DELAY
stage1_rg_stage_input$D_IN;
if (stage2_rg_stage2$EN)
stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
if (stage3_rg_stage3$EN)
stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
if (stageD_rg_data$EN)
stageD_rg_data <= `BSV_ASSIGNMENT_DELAY stageD_rg_data$D_IN;
if (stageF_rg_priv$EN)
stageF_rg_priv <= `BSV_ASSIGNMENT_DELAY stageF_rg_priv$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
cfg_verbosity = 4'hA;
imem_rg_cache_addr = 32'hAAAAAAAA;
imem_rg_cache_b16 = 16'hAAAA;
imem_rg_f3 = 3'h2;
imem_rg_mstatus_MXR = 1'h0;
imem_rg_pc = 32'hAAAAAAAA;
imem_rg_priv = 2'h2;
imem_rg_satp = 32'hAAAAAAAA;
imem_rg_sstatus_SUM = 1'h0;
imem_rg_tval = 32'hAAAAAAAA;
rg_csr_pc = 32'hAAAAAAAA;
rg_csr_val1 = 32'hAAAAAAAA;
rg_cur_priv = 2'h2;
rg_epoch = 2'h2;
rg_mstatus_MXR = 1'h0;
rg_next_pc = 32'hAAAAAAAA;
rg_run_on_reset = 1'h0;
rg_sstatus_SUM = 1'h0;
rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
rg_state = 4'hA;
rg_trap_info = 68'hAAAAAAAAAAAAAAAAA;
rg_trap_instr = 32'hAAAAAAAA;
rg_trap_interrupt = 1'h0;
stage1_rg_full = 1'h0;
stage1_rg_stage_input =
306'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage2_rg_full = 1'h0;
stage2_rg_resetting = 1'h0;
stage2_rg_stage2 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage3_rg_full = 1'h0;
stage3_rg_stage3 = 104'hAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_data = 138'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_full = 1'h0;
stageF_rg_epoch = 2'h2;
stageF_rg_full = 1'h0;
stageF_rg_priv = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x epoch:%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_cur_priv,
csr_regfile$read_mstatus,
rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write("MStatus{",
"sd:%0d",
csr_regfile$read_mstatus[14:13] == 2'h3 ||
csr_regfile$read_mstatus[16:15] == 2'h3);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
$write(" sxl:%0d uxl:%0d", 2'd0, 2'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tw:%0d", csr_regfile$read_mstatus[21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" sum:%0d", csr_regfile$read_mstatus[18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" spp:%0d", csr_regfile$read_mstatus[8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" pies:%0d_%0d%0d",
csr_regfile$read_mstatus[7],
csr_regfile$read_mstatus[5],
csr_regfile$read_mstatus[4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" ies:%0d_%0d%0d",
csr_regfile$read_mstatus[3],
csr_regfile$read_mstatus[1],
csr_regfile$read_mstatus[0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage3_rg_full || !stage3_rg_stage3[37]))
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[37])
$write("Rd %0d ",
stage3_rg_stage3[36:32],
"rd_val:%h",
stage3_rg_stage3[31:0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage2: pc 0x%08h instr 0x%08h priv %0d",
stage2_rg_stage2[166:135],
stage2_rg_stage2[134:103],
stage2_rg_stage2[168:167]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("Output_Stage2", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[166:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("Output_Stage2", " NONPIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("Output_Stage2", " PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[166:135],
stage2_rg_stage2[134:103],
stage2_rg_stage2[168:167]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3 &&
stage2_rg_stage2[102:101] != 2'd0 &&
(!near_mem$dmem_valid || near_mem$dmem_exc))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d145)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h7354,
x_out_data_to_stage3_rd_val__h7355);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("'h%h", stage2_rg_stage2[166:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("'h%h", near_mem$dmem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("'h%h", stage2_rg_stage2[95:64], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("'h%h", stage2_rg_stage2[166:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("'h%h", near_mem$dmem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd3)
$write("'h%h", stage2_rg_stage2[95:64], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd1 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 == 2'd0)
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 != 2'd0)
$write("Rd %0d ", stage2_rg_stage2[100:96]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 == 2'd1)
$write("-");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 != 2'd0 &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d177 != 2'd1)
$write("rd_val:%h", stage2_rg_stage2[63:32]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage1: pc 0x%08h instr 0x%08h priv %0d",
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[231:200],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("Output_Stage1",
" BUSY pc:%h",
stage1_rg_stage_input[305:274]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("Output_Stage1",
" NONPIPE: pc:%h",
stage1_rg_stage_input[305:274]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("Output_Stage1");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
$write("Output_Stage1", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd0)
$write("CONTROL_DISCARD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd1)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd2)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd3)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd4)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd5)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd6)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd7)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd8)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd9)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd10)
$write("CONTROL_URET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd11)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d491)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d503)
$write("{", "CF_None");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d507)
$write("{", "BR ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d513)
$write("{");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d503)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d507)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 == 2'd1)
$write("JAL [%h->%h/%h]",
stage1_rg_stage_input[305:274],
x_out_cf_info_taken_PC__h9558,
x_out_cf_info_fallthru_PC__h9557);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d500 == 2'd2)
$write("JALR [%h->%h/%h]",
stage1_rg_stage_input[305:274],
x_out_cf_info_taken_PC__h9558,
x_out_cf_info_fallthru_PC__h9557);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d503)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d507)
if (stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_88_BITS_112_TO_110_17_ETC___d263)
$write("taken ");
else
$write("fallthru ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d513)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d503)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d507)
$write("[%h->%h %h]",
stage1_rg_stage_input[305:274],
x_out_cf_info_fallthru_PC__h9557,
x_out_cf_info_taken_PC__h9558);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d513)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[231:200],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 == 2'd0)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 == 2'd1)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d362) &&
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 != 2'd0 &&
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 != 2'd1)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h7928);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h7929,
x_out_data_to_stage2_val1__h7930,
x_out_data_to_stage2_val2__h7931);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd0)
$write("CONTROL_DISCARD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd1)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd2)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd3)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd4)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd5)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd6)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd7)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd8)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd9)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd10)
$write("CONTROL_URET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd11)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d672)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("'h%h", stage1_rg_stage_input[305:274]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("'h%h", x_out_trap_info_exc_code__h9391);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 &&
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d324)
$write("'h%h", value__h9431, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_87_AND_NOT_stage1_rg_stage_inpu_ETC___d365)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d208)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
!IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719)
$write("\n redirect next_pc:%h", x_out_next_pc__h7886);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_88_BITS_271_TO_270_8_ETC___d328 &&
IF_IF_stage1_rg_stage_input_88_BITS_151_TO_145_ETC___d719)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageD: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
stageD_rg_data[137:106],
x_out_data_to_stage1_instr__h10055,
stageD_rg_data[103:102],
stageD_rg_data[105:104]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[137:106],
stageD_rg_data[103:102],
stageD_rg_data[105:104]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[137:106],
stageD_rg_data[103:102],
stageD_rg_data[105:104]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[100] &&
stageD_rg_data[101])
$write(" instr_C:%0h", stageD_rg_data[47:32]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[100] &&
!stageD_rg_data[101])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
$write(" instr:%0h pred_pc:%0h",
x_out_data_to_stage1_instr__h10055,
stageD_rg_data[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[100] &&
stageD_rg_data[99:96] != 4'd0 &&
stageD_rg_data[99:96] != 4'd1 &&
stageD_rg_data[99:96] != 4'd2 &&
stageD_rg_data[99:96] != 4'd3 &&
stageD_rg_data[99:96] != 4'd4 &&
stageD_rg_data[99:96] != 4'd5 &&
stageD_rg_data[99:96] != 4'd6 &&
stageD_rg_data[99:96] != 4'd7 &&
stageD_rg_data[99:96] != 4'd8 &&
stageD_rg_data[99:96] != 4'd9 &&
stageD_rg_data[99:96] != 4'd11 &&
stageD_rg_data[99:96] != 4'd12 &&
stageD_rg_data[99:96] != 4'd13 &&
stageD_rg_data[99:96] != 4'd15)
$write("unknown trap Exc_Code %d", stageD_rg_data[99:96]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
$write(" tval %0h", stageD_rg_data[95:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageF: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
imem_rg_pc,
d_instr__h15539,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageF");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118))
$write(" BUSY: pc:%h", imem_rg_pc);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125)
$write("data_to_StageD {pc:%h priv:%0d epoch:%0d",
imem_rg_pc,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_100_AND_near_mem_imem_valid_AND_ETC___d1132)
$write(" instr:%h pred_pc:%h",
d_instr__h15539,
stageF_branch_predictor$predict_rsp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d1220)
$write("unknown trap Exc_Code %d", near_mem$imem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_100_AND_near_mem_imem_valid_AND_ETC___d1132)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d1118))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d1125)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage2_nonpipe &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage2_nonpipe -> CPU_TRAP",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_trap &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_534_BITS_67_TO_36_535_EQ_csr_regf_ETC___d1544)
$display("%0d: %m.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x",
csr_regfile$read_csr_mcycle,
csr_regfile$csr_trap_actions[97:66],
rg_trap_instr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_534_BITS_67_TO_36_535_EQ_csr_regf_ETC___d1544)
$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
cpi__h21611,
cpifrac__h21612,
delta_CPI_cycles__h21607,
_theResult____h21609);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_534_BITS_67_TO_36_535_EQ_csr_regf_ETC___d1544)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
(cur_verbosity__h3701 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_trap_info[67:36],
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3701 != 4'd0)
$display(" mcause:0x%0h epc 0x%0h tval:0x%0h next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
csr_regfile$csr_trap_actions[33:2],
rg_trap_info[67:36],
rg_trap_info[31:0],
csr_regfile$csr_trap_actions[97:66],
csr_regfile$csr_trap_actions[1:0],
csr_regfile$csr_trap_actions[65:34]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
(cur_verbosity__h3701 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h22085,
rg_trap_instr[31:20],
csr_regfile$read_csr[31:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
!csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h22085,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_CSRR_S_or_C",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
(cur_verbosity__h3701 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h22768,
rg_trap_instr[31:20],
csr_regfile$read_csr[31:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
!csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h22768,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_restart_after_csrrx",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h16901,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h16901);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
(cur_verbosity__h3701 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[231:200],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3701 != 4'd0)
$display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d",
csr_regfile$csr_ret_actions[65:34],
csr_regfile$csr_ret_actions[31:0],
csr_regfile$csr_ret_actions[33:32]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
(cur_verbosity__h3701 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[231:200],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h16901,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h16901);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
(cur_verbosity__h3701 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[231:200],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h16901,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h16901);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
(cur_verbosity__h3701 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[231:200],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" CPU.rl_stage1_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h16901,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h16901);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_from_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h16901,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h16901);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_interrupt &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
if (WILL_FIRE_RL_imem_rl_assert_fail)
begin
v__h2516 = $stime;
#0;
end
v__h2510 = v__h2516 / 32'd10;
if (WILL_FIRE_RL_imem_rl_assert_fail)
$display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
v__h2510);
if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
csr_regfile$read_csr_mcycle,
soc_map$m_pc_reset_value[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
soc_map$m_pc_reset_value[31:0],
new_epoch__h16901,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
soc_map$m_pc_reset_value[31:0],
rg_cur_priv,
rg_epoch,
new_epoch__h16901);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
stage3_rg_stage3[36:32],
stage3_rg_stage3[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" S3.enq: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[166:135],
stage2_rg_stage2[134:103],
stage2_rg_stage2[168:167]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 &&
stage2_rg_stage2[102:101] != 2'd0 &&
(!near_mem$dmem_valid || near_mem$dmem_exc))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d1359)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h7354,
x_out_data_to_stage3_rd_val__h7355);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_9_THEN_IF_stage2_rg_stage2_0_ETC___d122 == 2'd2 &&
(cur_verbosity__h3701 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage2_rg_stage2[166:135],
stage2_rg_stage2[134:103],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1368 &&
stage1_rg_full &&
(!stage1_rg_stage_input_88_BITS_271_TO_270_89_EQ_ETC___d190 ||
NOT_IF_stage2_rg_full_9_THEN_IF_stage2_rg_stag_ETC___d1304) &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 == 4'd0 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" rl_pipe: Discarding stage1 due to redirection");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1395)
$write(" CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1395)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[305:274],
stage1_rg_stage_input[231:200],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1395)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 != 4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 &&
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 == 2'd0)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 != 4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 &&
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 == 2'd1)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1375 &&
IF_stage1_rg_stage_input_88_BITS_271_TO_270_89_ETC___d418 != 4'd0 &&
IF_NOT_stage1_rg_full_87_66_OR_NOT_stage1_rg_s_ETC___d1378 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52 &&
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 != 2'd0 &&
IF_stage1_rg_full_87_THEN_IF_stage1_rg_stage_i_ETC___d559 != 2'd1)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1395)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h7928);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1395)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h7929,
x_out_data_to_stage2_val1__h7930,
x_out_data_to_stage2_val2__h7931);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1395)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1413 &&
stageD_rg_full &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" CPU_Stage1.enq: 0x%08h", stageD_rg_data[137:106]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 &&
NOT_IF_csr_regfile_read_csr_minstret__6_ULT_cf_ETC___d52)
$display(" CPU_StageD.enq (Data_StageF_to_StageD)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 &&
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1471)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
stageF_branch_predictor$predict_rsp,
stageF_rg_epoch,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 &&
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1471)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1454 &&
csr_regfile_interrupt_pending_rg_cur_priv_4_29_ETC___d1471)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$write("CPU: Bluespec RISC-V Flute v3.0");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
end
// synopsys translate_on
endmodule // mkCPU
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:14:21 06/30/2015
// Design Name:
// Module Name: ps2_mouse_kempston
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2_mouse_kempston (
input wire clk,
input wire rst_n,
inout wire clkps2,
inout wire dataps2,
//---------------------------------
input wire [15:0] a,
input wire iorq_n,
input wire rd_n,
output wire [7:0] kmouse_dout,
output wire oe_n_kmouse,
//---------------------------------
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire [7:0] din,
output wire [7:0] mousedata_dout,
output wire oe_n_mousedata,
output reg [7:0] mousestatus_dout,
output wire oe_n_mousestatus
);
parameter MOUSEDATA = 8'h09;
parameter MOUSESTATUS = 8'h0A;
assign oe_n_mousedata = ~(zxuno_addr == MOUSEDATA && zxuno_regrd == 1'b1);
assign oe_n_mousestatus = ~(zxuno_addr == MOUSESTATUS && zxuno_regrd == 1'b1);
wire [7:0] mousedata;
wire [7:0] kmouse_x, kmouse_y, kmouse_buttons;
wire ps2busy;
wire ps2error;
wire nuevo_evento;
wire [1:0] state_out;
assign mousedata_dout = mousedata;
wire kmouse_x_req_n = ~(!iorq_n && !rd_n && a[7:0]==8'hDF && a[8]==1'b1 && a[9]==1'b1 && a[10]==1'b0);
wire kmouse_y_req_n = ~(!iorq_n && !rd_n && a[7:0]==8'hDF && a[8]==1'b1 && a[9]==1'b1 && a[10]==1'b1);
wire kmouse_butt_req_n = ~(!iorq_n && !rd_n && a[7:0]==8'hDF && a[8]==1'b0);
assign kmouse_dout = (kmouse_x_req_n==1'b0)? kmouse_x :
(kmouse_y_req_n==1'b0)? kmouse_y :
(kmouse_butt_req_n==1'b0)? kmouse_buttons :
8'hZZ;
assign oe_n_kmouse = kmouse_x_req_n & kmouse_y_req_n & kmouse_butt_req_n;
/*
| BSY | 0 | 0 | 0 | ERR | 0 | 0 | DATA_AVL |
*/
reg reading_mousestatus = 1'b0;
always @(posedge clk) begin
mousestatus_dout[7:1] <= {ps2busy, 3'b000, ps2error, 2'b00};
if (nuevo_evento == 1'b1)
mousestatus_dout[0] <= 1'b1;
if (oe_n_mousestatus == 1'b0)
reading_mousestatus <= 1'b1;
else if (reading_mousestatus == 1'b1) begin
mousestatus_dout[0] <= 1'b0;
reading_mousestatus <= 1'b0;
end
end
ps2_port lectura_de_raton (
.clk(clk),
.enable_rcv(~ps2busy),
.kb_or_mouse(1'b1),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.kb_interrupt(nuevo_evento),
.scancode(mousedata),
.released(),
.extended()
);
ps2mouse_to_kmouse traductor_raton (
.clk(clk),
.rst_n(rst_n),
.data(mousedata),
.data_valid(nuevo_evento),
.kmouse_x(kmouse_x),
.kmouse_y(kmouse_y),
.kmouse_buttons(kmouse_buttons)
);
ps2_host_to_kb escritura_a_raton (
.clk(clk),
.ps2clk_ext(clkps2),
.ps2data_ext(dataps2),
.data(din),
.dataload(zxuno_addr == MOUSEDATA && zxuno_regwr== 1'b1),
.ps2busy(ps2busy),
.ps2error(ps2error)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_HVL__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_hvl__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_MUX_4TO2_TB_V
|
//*****************************************************************************
//(c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : qdr_phy_write_control_io.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:36:30 $
// \ \ / \ Date Created : Nov 11, 2008
// \___\/\___\
//
//Device: 7 Series
//Design: QDRII+ SRAM
//
//Purpose:
// This module
// 1. Instantiates the I/O modules for generating the addresses and control
// signals for memory
//
//Revision History:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_phy_write_control_io #(
parameter BURST_LEN = 4, //Burst Length
parameter ADDR_WIDTH = 19, //Address Width
parameter TCQ = 100 //Register Delay
)
(
input clk, //main system half freq clk
input rst_clk, //main write path reset
input wr_cmd0, //wr command 0
input wr_cmd1, //wr command 1
input [ADDR_WIDTH-1:0] wr_addr0, //wr address 0
input [ADDR_WIDTH-1:0] wr_addr1, //wr address 1
input rd_cmd0, //rd command 0
input rd_cmd1, //rd command 1
input [ADDR_WIDTH-1:0] rd_addr0, //rd address 0
input [ADDR_WIDTH-1:0] rd_addr1, //rd address 1
input [1:0] init_rd_cmd, //init sm rd command
input [1:0] init_wr_cmd, //init sm wr command
input [ADDR_WIDTH-1:0] init_wr_addr0, //init sm wr address0
input [ADDR_WIDTH-1:0] init_wr_addr1, //init sm wr address1
input [ADDR_WIDTH-1:0] init_rd_addr0, //init sm rd address0
input [ADDR_WIDTH-1:0] init_rd_addr1, //init sm rd address1
input cal_done, //calibration done
output reg [1:0] int_rd_cmd_n, //internal rd cmd
output reg [1:0] int_wr_cmd_n, //internal rd cmd
output reg [ADDR_WIDTH-1:0] iob_addr_rise0, //OSERDES addr rise0
output reg [ADDR_WIDTH-1:0] iob_addr_fall0, //OSERDES addr fall0
output reg [ADDR_WIDTH-1:0] iob_addr_rise1, //OSERDES addr rise1
output reg [ADDR_WIDTH-1:0] iob_addr_fall1, //OSERDES addr fall1
output wire [1:0] dbg_phy_wr_cmd_n,//cs debug - wr command
output wire [ADDR_WIDTH*4-1:0] dbg_phy_addr, //cs debug - address
output wire [1:0] dbg_phy_rd_cmd_n //cs debug - rd command
);
//Wire Declarations
wire mux_rd_cmd0;
wire mux_rd_cmd1;
wire mux_wr_cmd0;
wire mux_wr_cmd1;
wire [ADDR_WIDTH-1:0] rd_addr0_r;
wire [ADDR_WIDTH-1:0] rd_addr1_r;
wire [ADDR_WIDTH-1:0] wr_addr0_r;
wire [ADDR_WIDTH-1:0] wr_addr1_r;
reg [ADDR_WIDTH-1:0] wr_addr1_2r;
//Test Signals for Chipscope
assign dbg_phy_wr_cmd_n = int_wr_cmd_n;
assign dbg_phy_rd_cmd_n = int_rd_cmd_n;
assign dbg_phy_addr = {iob_addr_rise0, iob_addr_fall0,
iob_addr_rise1, iob_addr_fall1};
//In BL4 mode, writes should only be driven out on the falling edge, if we
//have a command on port 0 (rising edge) move it to port 1 (falling edge)
//Tie off the rising edge
wire [ADDR_WIDTH-1:0] mv_wr_addr0 = (BURST_LEN == 4) ? {ADDR_WIDTH{1'b0}} : wr_addr0;
wire [ADDR_WIDTH-1:0] mv_wr_addr1 = (BURST_LEN == 4) ? wr_addr0 : wr_addr1;
wire [ADDR_WIDTH-1:0] mv_rd_addr1 = (BURST_LEN == 4) ? {ADDR_WIDTH{1'b0}} : rd_addr1;
//Select the correct address either from the user or from the init state
//machine based on if calibration is complete
assign rd_addr0_r = (cal_done) ? rd_addr0 : init_rd_addr0;
assign rd_addr1_r = (cal_done) ? mv_rd_addr1 : init_rd_addr1;
assign wr_addr0_r = (cal_done) ? mv_wr_addr0 : init_wr_addr0;
assign wr_addr1_r = (cal_done) ? mv_wr_addr1 : init_wr_addr1;
always @(posedge clk)
begin
wr_addr1_2r <= #TCQ wr_addr1_r;
end
always @ (posedge clk)
begin
//Select the correct input to the oserdes based on the burst mode
iob_addr_rise0 <=#TCQ (BURST_LEN == 4) ? rd_addr0_r : wr_addr1_2r;
iob_addr_fall0 <=#TCQ (BURST_LEN == 4) ? rd_addr0_r : rd_addr0_r;
iob_addr_rise1 <=#TCQ (BURST_LEN == 4) ? wr_addr1_r : wr_addr0_r;
iob_addr_fall1 <=#TCQ (BURST_LEN == 4) ? wr_addr1_r : rd_addr1_r;
end
//In BL4 mode, writes should only be driven out on the falling edge, if we
//have a command on port 0 (rising edge) move it to port 1 (falling edge)
//Tie off the rising edge
wire mv_wr_cmd0 = (BURST_LEN == 4) ? 1'b0 : wr_cmd0;
wire mv_wr_cmd1 = (BURST_LEN == 4) ? wr_cmd0 : wr_cmd1;
wire mv_rd_cmd1 = (BURST_LEN == 4) ? 1'b0 : rd_cmd1;
//Select the command from the user or from the init state machine based
//on if calibration is complete.
//from the init state machine the high bit 1, corresponds to a write on the
//rising edge of the clock as is "_cmd0"
assign mux_rd_cmd0 = (cal_done) ? rd_cmd0 : init_rd_cmd[0];
assign mux_rd_cmd1 = (cal_done) ? mv_rd_cmd1 : init_rd_cmd[1];
assign mux_wr_cmd0 = (cal_done) ? mv_wr_cmd0 : init_wr_cmd[0];
assign mux_wr_cmd1 = (cal_done) ? mv_wr_cmd1 : init_wr_cmd[1];
//Invert the commands to be used on the memory interface as active low.. NOP issued until clocks are stable
always @ (posedge clk)
begin
if (rst_clk) begin
int_rd_cmd_n <=#TCQ 2'b11;
int_wr_cmd_n <=#TCQ 2'b11;
end else begin
int_rd_cmd_n <=#TCQ {~mux_rd_cmd1, ~mux_rd_cmd0};
int_wr_cmd_n <=#TCQ {~mux_wr_cmd1, ~mux_wr_cmd0};
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BA_BLACKBOX_V
`define SKY130_FD_SC_MS__O21BA_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BA_BLACKBOX_V
|
// bsg_nonsynth_clock_gen_plusarg
//
// This module is a basic non-synthesizable clock generator. This module is
// designed to be used with VCS and can be changed at runtime rather than
// compile time. To set the speed of the clock, add the following flag when
// executing the simulation binary:
//
// ./simv +clock-period=<period>
//
// If no flag is added to the simulation, the clock period will default to the
// value of default_clk_per_p.
//
`include "bsg_defines.v"
module bsg_nonsynth_clock_gen_plusarg #( parameter `BSG_INV_PARAM(default_clk_per_p) )
(
output logic o
);
`ifndef VERILATOR
// We start logic hi so the first pos-edge occurs at T=<clk_per>. The first
// negative edge will occur at T=<clk_per>/2.
logic clk_lo = 1'b1;
initial begin
// Here we grab the clock_period from the command line plusarg and generate
// the clock signal. If the plusarg doesn't exist, the value is unchanged
// and no error/warning is issued.
integer clock_period = default_clk_per_p;
$value$plusargs("clock-period=%d", clock_period);
$display("[INFO - %L]: Clock Period = %d", clock_period);
forever #(clock_period/2.0) clk_lo = ~clk_lo;
end
// Assign clock to output port
assign o = clk_lo;
`else
initial begin
$error("bsg_nonsynth_clock_gen_plusarg is not supported in Verilator due to delay statement (#)");
end
`endif
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_clock_gen_plusarg)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O22AI_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o22ai (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CONB_FUNCTIONAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_ms__udp_pwrgood_pp_p.v"
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_ms__udp_pwrgood_pp_g.v"
`celldefine
module sky130_fd_sc_ms__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_ms__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_ms__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_DIV2.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2006/06/22 09:01:42 Administrator
// no message
//
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_DIV2 (
input Reset,
input IN,
output reg OUT
);
always @ (posedge IN or posedge Reset)
if (Reset)
OUT <=0;
else
OUT <=!OUT;
endmodule |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_tagctlrep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_tagctlrep(/*AUTOARG*/
// Outputs
sctag_scdata_set_c2, sctag_scdata_way_sel_c2,
sctag_scdata_col_offset_c2, sctag_scdata_rd_wr_c2,
sctag_scdata_word_en_c2, sctag_scdata_fbrd_c3,
sctag_scdata_fb_hit_c3,
// Inputs
scdata_set_c2, scdata_way_sel_c2, scdata_col_offset_c2,
scdata_rd_wr_c2, scdata_word_en_c2, scdata_fbrd_c3,
scdata_fb_hit_c3
);
input [9:0] scdata_set_c2; // Left
input [11:0] scdata_way_sel_c2;
input [3:0] scdata_col_offset_c2;
input scdata_rd_wr_c2;
input [15:0] scdata_word_en_c2;
input scdata_fbrd_c3;
input scdata_fb_hit_c3;
output [9:0] sctag_scdata_set_c2; // Right
output [11:0] sctag_scdata_way_sel_c2; // Right
output [3:0] sctag_scdata_col_offset_c2; // Right
output sctag_scdata_rd_wr_c2; // Right
output [15:0] sctag_scdata_word_en_c2; // Right
output sctag_scdata_fbrd_c3; // Right
output sctag_scdata_fb_hit_c3; // Right
// 46 control bits.
assign sctag_scdata_fb_hit_c3 = scdata_fb_hit_c3;
assign sctag_scdata_fbrd_c3 = scdata_fbrd_c3 ;
assign sctag_scdata_word_en_c2 = scdata_word_en_c2;
assign sctag_scdata_rd_wr_c2 = scdata_rd_wr_c2 ;
assign sctag_scdata_col_offset_c2 = scdata_col_offset_c2 ;
assign sctag_scdata_way_sel_c2 = scdata_way_sel_c2;
assign sctag_scdata_set_c2 = scdata_set_c2 ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFRTP_SYMBOL_V
/**
* srsdfrtp: Scan flop with sleep mode, inverted reset, non-inverted
* clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_1_V
`define SKY130_FD_SC_HS__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfstp_1 (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfstp_1 (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_1_V
|
module x (/*AUTOARG*/
// Inputs
MIERHW, MBOOTH_P, CEIopMADH_E_D2_R, CEIopMAZH_E_D2_R, DDATAH, DIV2HI, HI_R, MCLA, MCLASH,
MULTSHCYC, MULTUSCYC, HI_P
);
input [18:0] MIERHW;
integer i;
integer MTEMP1;
integer MTEMP2;
input MBOOTH_P;
input CEIopMADH_E_D2_R;
input CEIopMAZH_E_D2_R;
input DDATAH;
input DIV2HI;
input HI_R;
input MCLA;
input MCLASH;
input MULTSHCYC;
input MULTUSCYC;
input HI_P;
/*AUTOREG*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
always @(/*AUTOSENSE*/MIERHW) begin
for (i=0; i<=5; i=i+1) begin
MTEMP1[3:0] = {MIERHW[i*3+3],
MIERHW[i*3+2],
MIERHW[i*3+1],
MIERHW[i*3+0]};
casex (MTEMP1)
4'b0000: MTEMP2 = 4'b0101; // +0
4'b0001: MTEMP2 = 4'b0001; // +1
4'b0010: MTEMP2 = 4'b0001; // +1
4'b0011: MTEMP2 = 4'b0010; // +2
4'b0100: MTEMP2 = 4'b0010; // +2
4'b0101: MTEMP2 = 4'b0100; // +3
4'b0110: MTEMP2 = 4'b0100; // +3
4'b0111: MTEMP2 = 4'b1000; // +4
4'b1000: MTEMP2 = 4'b0111; // -4
4'b1001: MTEMP2 = 4'b1011; // -3
4'b1010: MTEMP2 = 4'b1011; // -3
4'b1011: MTEMP2 = 4'b1101; // -2
4'b1100: MTEMP2 = 4'b1101; // -2
4'b1101: MTEMP2 = 4'b1110; // -1
4'b1110: MTEMP2 = 4'b1110; // -1
4'b1111: MTEMP2 = 4'b1010; // -0
endcase
end
{MBOOTH_P[i*4+3],
MBOOTH_P[i*4+2],
MBOOTH_P[i*4+1],
MBOOTH_P[i*4+0]} = MTEMP2[3:0];
end
// always @(/*AUTOnotSENSE*/
// __CEIopMADH_E_D2_R or __CEIopMAZH_E_D2_R or __DIV2HI or
// __MULTUSCYC or __MULTSHCYC or
// __DDATAH or __HI_R or __MCLA or __MCLASH) begin
// always @(/*AUTOSENSE*/DDATAH or HI_R or MCLA or MCLASH) begin
`define DMCLASH MCLASH
`define DCONST 1'b1
always @(/*AUTOSENSE*/CEIopMADH_E_D2_R or CEIopMAZH_E_D2_R or DDATAH or DIV2HI or MCLA or MCLASH
or MULTSHCYC or MULTUSCYC) begin
case (1'b1)
CEIopMADH_E_D2_R: HI_P = MCLA;
CEIopMAZH_E_D2_R: HI_P = MCLA;
DIV2HI: HI_P = DDATAH;
MULTUSCYC: HI_P = MCLA;
MULTSHCYC: HI_P = `DMCLASH;
default: HI_P = `DCONST;
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036 10762
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
module alt_mem_ddrx_rank_timer #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_REG_GRANT = 0,
CFG_RANK_TIMER_OUTPUT_REG = 0,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 0,
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 0,
T_PARAM_WR_TO_WR_WIDTH = 0,
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 0,
T_PARAM_WR_TO_RD_WIDTH = 0,
T_PARAM_WR_TO_RD_BC_WIDTH = 0,
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_RD_WIDTH = 0,
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_WR_WIDTH = 0,
T_PARAM_RD_TO_WR_BC_WIDTH = 0,
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Configurations
cfg_burst_length,
// Timing parameters
t_param_four_act_to_act,
t_param_act_to_act_diff_bank,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
// Arbiter Interface
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_activate,
bg_do_precharge,
bg_to_chip,
bg_effective_size,
bg_interrupt_ready,
// Command Generator Interface
cmd_gen_chipsel,
// TBP Interface
tbp_chipsel,
tbp_load,
// Sideband Interface
stall_chip,
can_activate,
can_precharge,
can_read,
can_write
);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
input [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
input [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
input [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
input [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
input [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
input [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
input [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
input [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
input [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
input [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
input [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
input bg_interrupt_ready;
input [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
input [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
output [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
output [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
output [CFG_CTL_TBP_NUM - 1 : 0] can_read;
output [CFG_CTL_TBP_NUM - 1 : 0] can_write;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
localparam RANK_TIMER_COUNTER_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 4 : 3) : ((CFG_REG_GRANT) ? 3 : 2);
localparam RANK_TIMER_TFAW_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 2 : 1) : ((CFG_REG_GRANT) ? 1 : 0);
localparam ENABLE_BETTER_TRRD_EFFICIENCY = 1; // ONLY set to '1' when CFG_RANK_TIMER_OUTPUT_REG is enabled, else it will fail
wire one = 1'b1;
wire zero = 1'b0;
// Timing Parameter Comparison Logic
reg less_than_1_act_to_act_diff_bank;
reg less_than_2_act_to_act_diff_bank;
reg less_than_3_act_to_act_diff_bank;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
reg less_than_1_rd_to_rd;
reg less_than_1_rd_to_wr;
reg less_than_1_wr_to_wr;
reg less_than_1_wr_to_rd;
reg less_than_1_rd_to_wr_bc;
reg less_than_1_wr_to_rd_bc;
reg less_than_1_rd_to_rd_diff_chip;
reg less_than_1_rd_to_wr_diff_chip;
reg less_than_1_wr_to_wr_diff_chip;
reg less_than_1_wr_to_rd_diff_chip;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_wr_to_rd_bc;
reg less_than_2_rd_to_rd_diff_chip;
reg less_than_2_rd_to_wr_diff_chip;
reg less_than_2_wr_to_wr_diff_chip;
reg less_than_2_wr_to_rd_diff_chip;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_wr_to_rd_bc;
reg less_than_3_rd_to_rd_diff_chip;
reg less_than_3_rd_to_wr_diff_chip;
reg less_than_3_wr_to_wr_diff_chip;
reg less_than_3_wr_to_rd_diff_chip;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_wr_to_rd_bc;
reg less_than_4_rd_to_rd_diff_chip;
reg less_than_4_rd_to_wr_diff_chip;
reg less_than_4_wr_to_wr_diff_chip;
reg less_than_4_wr_to_rd_diff_chip;
reg more_than_2_rd_to_rd;
reg more_than_2_rd_to_wr;
reg more_than_2_wr_to_wr;
reg more_than_2_wr_to_rd;
reg more_than_2_rd_to_wr_bc;
reg more_than_2_wr_to_rd_bc;
reg more_than_2_rd_to_rd_diff_chip;
reg more_than_2_rd_to_wr_diff_chip;
reg more_than_2_wr_to_wr_diff_chip;
reg more_than_2_wr_to_rd_diff_chip;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_wr_to_rd_bc;
reg more_than_3_rd_to_rd_diff_chip;
reg more_than_3_rd_to_wr_diff_chip;
reg more_than_3_wr_to_wr_diff_chip;
reg more_than_3_wr_to_rd_diff_chip;
reg less_than_xn1_act_to_act_diff_bank;
reg less_than_xn1_rd_to_rd;
reg less_than_xn1_rd_to_wr;
reg less_than_xn1_wr_to_wr;
reg less_than_xn1_wr_to_rd;
reg less_than_xn1_rd_to_wr_bc;
reg less_than_xn1_wr_to_rd_bc;
reg less_than_xn1_rd_to_rd_diff_chip;
reg less_than_xn1_rd_to_wr_diff_chip;
reg less_than_xn1_wr_to_wr_diff_chip;
reg less_than_xn1_wr_to_rd_diff_chip;
reg less_than_x0_act_to_act_diff_bank;
reg less_than_x0_rd_to_rd;
reg less_than_x0_rd_to_wr;
reg less_than_x0_wr_to_wr;
reg less_than_x0_wr_to_rd;
reg less_than_x0_rd_to_wr_bc;
reg less_than_x0_wr_to_rd_bc;
reg less_than_x0_rd_to_rd_diff_chip;
reg less_than_x0_rd_to_wr_diff_chip;
reg less_than_x0_wr_to_wr_diff_chip;
reg less_than_x0_wr_to_rd_diff_chip;
reg less_than_x1_act_to_act_diff_bank;
reg less_than_x1_rd_to_rd;
reg less_than_x1_rd_to_wr;
reg less_than_x1_wr_to_wr;
reg less_than_x1_wr_to_rd;
reg less_than_x1_rd_to_wr_bc;
reg less_than_x1_wr_to_rd_bc;
reg less_than_x1_rd_to_rd_diff_chip;
reg less_than_x1_rd_to_wr_diff_chip;
reg less_than_x1_wr_to_wr_diff_chip;
reg less_than_x1_wr_to_rd_diff_chip;
reg more_than_x0_rd_to_rd;
reg more_than_x0_rd_to_wr;
reg more_than_x0_wr_to_wr;
reg more_than_x0_wr_to_rd;
reg more_than_x0_rd_to_wr_bc;
reg more_than_x0_wr_to_rd_bc;
reg more_than_x0_rd_to_rd_diff_chip;
reg more_than_x0_rd_to_wr_diff_chip;
reg more_than_x0_wr_to_wr_diff_chip;
reg more_than_x0_wr_to_rd_diff_chip;
// Input
reg int_do_activate;
reg int_do_precharge;
reg int_do_burst_chop;
reg int_do_burst_terminate;
reg int_do_write;
reg int_do_read;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_r;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_c;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_interrupt_ready;
// Activate Monitor
localparam ACTIVATE_COUNTER_WIDTH = T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH;
localparam ACTIVATE_COMMAND_WIDTH = 3;
localparam NUM_OF_TFAW_SHIFT_REG = 2 ** T_PARAM_FOUR_ACT_TO_ACT_WIDTH;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_ready;
wire [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_count [CFG_MEM_IF_CHIP - 1 : 0];
// Read/Write Monitor
localparam IDLE = 2'b00;
localparam WR = 2'b01;
localparam RD = 2'b10;
localparam RDWR_COUNTER_WIDTH = (T_PARAM_RD_TO_WR_WIDTH > T_PARAM_WR_TO_RD_WIDTH) ? T_PARAM_RD_TO_WR_WIDTH : T_PARAM_WR_TO_RD_WIDTH;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] max_local_burst_size;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr_combi;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip_combi;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd_combi;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip_combi;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip;
reg [CFG_MEM_IF_CHIP - 1 : 0] read_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] write_ready;
// Precharge Monitor
reg [CFG_MEM_IF_CHIP - 1 : 0] pch_ready;
// Output
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_write;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_write;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] sel_act_tfaw_shift_out_point;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input
//
//--------------------------------------------------------------------------------------------------------
// Do activate
always @ (*)
begin
int_do_activate = |bg_do_activate;
end
// Do precharge
always @ (*)
begin
int_do_precharge = |bg_do_precharge;
end
//Do burst chop
always @ (*)
begin
int_do_burst_chop = |bg_do_burst_chop;
end
//Do burst terminate
always @ (*)
begin
int_do_burst_terminate = |bg_do_burst_terminate;
end
// Do write
always @ (*)
begin
int_do_write = |bg_do_write;
end
// Do read
always @ (*)
begin
int_do_read = |bg_do_read;
end
// To chip
always @ (*)
begin
// _r for row command and _c for column command
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
int_to_chip_c = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_r = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
else if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
int_to_chip_r = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_c = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
end
// Effective size
always @ (*)
begin
int_effective_size = bg_effective_size;
end
// Interrupt ready
always @ (*)
begin
int_interrupt_ready = bg_interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output
//
//--------------------------------------------------------------------------------------------------------
generate
genvar x_cs;
for (x_cs = 0; x_cs < CFG_CTL_TBP_NUM;x_cs = x_cs + 1)
begin : can_logic_per_chip
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] chip_addr;
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG && tbp_load [x_cs])
begin
chip_addr = cmd_gen_chipsel;
end
else
begin
chip_addr = tbp_chipsel [(x_cs + 1) * CFG_MEM_IF_CS_WIDTH - 1 : x_cs * CFG_MEM_IF_CS_WIDTH];
end
end
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
always @ (*)
begin
can_activate [x_cs] = int_can_activate [x_cs] ;
can_precharge [x_cs] = int_can_precharge [x_cs] ;
can_read [x_cs] = int_can_read [x_cs] & int_interrupt_ready;
can_write [x_cs] = int_can_write [x_cs] & int_interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_activate [x_cs] <= 1'b0;
end
else if (int_do_activate && int_to_chip_r [chip_addr] && !ENABLE_BETTER_TRRD_EFFICIENCY)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
int_can_activate [x_cs] <= act_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
int_can_precharge [x_cs] <= pch_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_read [x_cs] <= 1'b0;
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_x0_wr_to_rd_bc)
begin
int_can_read [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_x0_wr_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_x0_rd_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else
begin
int_can_read [x_cs] <= read_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_write [x_cs] <= 1'b0;
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_x0_rd_to_wr_bc)
begin
int_can_write [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_x0_rd_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_x0_wr_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else
begin
int_can_write [x_cs] <= write_ready [chip_addr];
end
end
end
end
else
begin
// Can activate
always @ (*)
begin
can_activate [x_cs] = act_ready [chip_addr];
end
// Can precharge
always @ (*)
begin
can_precharge [x_cs] = pch_ready [chip_addr];
end
// Can read
always @ (*)
begin
can_read [x_cs] = read_ready [chip_addr];
end
// Can write
always @ (*)
begin
can_write [x_cs] = write_ready [chip_addr];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Output
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 1)
less_than_1_act_to_act_diff_bank <= 1'b1;
else
less_than_1_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
if (t_param_four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 1)
less_than_1_rd_to_rd <= 1'b1;
else
less_than_1_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 1)
less_than_1_rd_to_wr <= 1'b1;
else
less_than_1_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 1)
less_than_1_wr_to_wr <= 1'b1;
else
less_than_1_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 1)
less_than_1_wr_to_rd <= 1'b1;
else
less_than_1_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 1)
less_than_1_rd_to_wr_bc <= 1'b1;
else
less_than_1_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 1)
less_than_1_wr_to_rd_bc <= 1'b1;
else
less_than_1_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 1)
less_than_1_rd_to_rd_diff_chip <= 1'b1;
else
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 1)
less_than_1_rd_to_wr_diff_chip <= 1'b1;
else
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 1)
less_than_1_wr_to_wr_diff_chip <= 1'b1;
else
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 1)
less_than_1_wr_to_rd_diff_chip <= 1'b1;
else
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 2)
less_than_2_wr_to_rd_bc <= 1'b1;
else
less_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 2)
less_than_2_rd_to_rd_diff_chip <= 1'b1;
else
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 2)
less_than_2_rd_to_wr_diff_chip <= 1'b1;
else
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 2)
less_than_2_wr_to_wr_diff_chip <= 1'b1;
else
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 2)
less_than_2_wr_to_rd_diff_chip <= 1'b1;
else
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 3)
less_than_3_wr_to_rd_bc <= 1'b1;
else
less_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 3)
less_than_3_rd_to_rd_diff_chip <= 1'b1;
else
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 3)
less_than_3_rd_to_wr_diff_chip <= 1'b1;
else
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 3)
less_than_3_wr_to_wr_diff_chip <= 1'b1;
else
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 3)
less_than_3_wr_to_rd_diff_chip <= 1'b1;
else
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 4)
less_than_4_wr_to_rd_bc <= 1'b1;
else
less_than_4_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 4)
less_than_4_rd_to_rd_diff_chip <= 1'b1;
else
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 4)
less_than_4_rd_to_wr_diff_chip <= 1'b1;
else
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 4)
less_than_4_wr_to_wr_diff_chip <= 1'b1;
else
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 4)
less_than_4_wr_to_rd_diff_chip <= 1'b1;
else
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 2)
more_than_2_rd_to_rd <= 1'b1;
else
more_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 2)
more_than_2_rd_to_wr <= 1'b1;
else
more_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 2)
more_than_2_wr_to_wr <= 1'b1;
else
more_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 2)
more_than_2_wr_to_rd <= 1'b1;
else
more_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 2)
more_than_2_rd_to_wr_bc <= 1'b1;
else
more_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 2)
more_than_2_wr_to_rd_bc <= 1'b1;
else
more_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 2)
more_than_2_rd_to_rd_diff_chip <= 1'b1;
else
more_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 2)
more_than_2_rd_to_wr_diff_chip <= 1'b1;
else
more_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 2)
more_than_2_wr_to_wr_diff_chip <= 1'b1;
else
more_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 2)
more_than_2_wr_to_rd_diff_chip <= 1'b1;
else
more_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 3)
more_than_3_wr_to_rd_bc <= 1'b1;
else
more_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 3)
more_than_3_rd_to_rd_diff_chip <= 1'b1;
else
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 3)
more_than_3_rd_to_wr_diff_chip <= 1'b1;
else
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 3)
more_than_3_wr_to_wr_diff_chip <= 1'b1;
else
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 3)
more_than_3_wr_to_rd_diff_chip <= 1'b1;
else
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
generate
begin
if (CFG_REG_GRANT)
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_3_rd_to_rd;
less_than_x0_rd_to_wr = less_than_3_rd_to_wr;
less_than_x0_wr_to_wr = less_than_3_wr_to_wr;
less_than_x0_wr_to_rd = less_than_3_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_4_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_4_rd_to_rd;
less_than_x1_rd_to_wr = less_than_4_rd_to_wr;
less_than_x1_wr_to_wr = less_than_4_wr_to_wr;
less_than_x1_wr_to_rd = less_than_4_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_4_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_4_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_4_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_4_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_4_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_4_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
end
always @ (*)
begin
more_than_x0_rd_to_rd = more_than_3_rd_to_rd;
more_than_x0_rd_to_wr = more_than_3_rd_to_wr;
more_than_x0_wr_to_wr = more_than_3_wr_to_wr;
more_than_x0_wr_to_rd = more_than_3_wr_to_rd;
more_than_x0_rd_to_wr_bc = more_than_3_rd_to_wr_bc;
more_than_x0_wr_to_rd_bc = more_than_3_wr_to_rd_bc;
more_than_x0_rd_to_rd_diff_chip = more_than_3_rd_to_rd_diff_chip;
more_than_x0_rd_to_wr_diff_chip = more_than_3_rd_to_wr_diff_chip;
more_than_x0_wr_to_wr_diff_chip = more_than_3_wr_to_wr_diff_chip;
more_than_x0_wr_to_rd_diff_chip = more_than_3_wr_to_rd_diff_chip;
end
end
else
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_1_rd_to_rd;
less_than_x0_rd_to_wr = less_than_1_rd_to_wr;
less_than_x0_wr_to_wr = less_than_1_wr_to_wr;
less_than_x0_wr_to_rd = less_than_1_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_2_rd_to_rd;
less_than_x1_rd_to_wr = less_than_2_rd_to_wr;
less_than_x1_wr_to_wr = less_than_2_wr_to_wr;
less_than_x1_wr_to_rd = less_than_2_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
end
end
always @ (*)
begin
more_than_x0_rd_to_rd = more_than_2_rd_to_rd;
more_than_x0_rd_to_wr = more_than_2_rd_to_wr;
more_than_x0_wr_to_wr = more_than_2_wr_to_wr;
more_than_x0_wr_to_rd = more_than_2_wr_to_rd;
more_than_x0_rd_to_wr_bc = more_than_2_rd_to_wr_bc;
more_than_x0_wr_to_rd_bc = more_than_2_wr_to_rd_bc;
more_than_x0_rd_to_rd_diff_chip = more_than_2_rd_to_rd_diff_chip;
more_than_x0_rd_to_wr_diff_chip = more_than_2_rd_to_wr_diff_chip;
more_than_x0_wr_to_wr_diff_chip = more_than_2_wr_to_wr_diff_chip;
more_than_x0_wr_to_rd_diff_chip = more_than_2_wr_to_rd_diff_chip;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Activate Monitor
//
// Monitors the following rank timing parameters:
//
// - tFAW, four activate window, only four activate is allowed in a specific timing window
// - tRRD, activate to activate different bank
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sel_act_tfaw_shift_out_point <= 0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET + 1;
end
else
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET;
end
end
end
generate
genvar t_cs;
genvar t_tfaw;
for (t_cs = 0;t_cs < CFG_MEM_IF_CHIP;t_cs = t_cs + 1)
begin : act_monitor_per_chip
//----------------------------------------------------------------------------------------------------
// tFAW Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_cnt;
reg [NUM_OF_TFAW_SHIFT_REG - 1 : 0] act_tfaw_shift_reg;
assign act_tfaw_cmd_count [t_cs] = act_tfaw_cmd_cnt;
// Shift register to keep track of tFAW
// Shift in -> n, n-1, n-2, n-3.......4, 3 -> Shift out
// Shift in '1' when there is an activate else shift in '0'
// Shift out every clock cycles
always @ (*)
begin
act_tfaw_shift_reg [2] <= 1'b0;
act_tfaw_shift_reg [1] <= 1'b0;
act_tfaw_shift_reg [0] <= 1'b0;
end
// Shift register [3]
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [3] <= 1'b0;
end
else
begin
// Shift in '1' if there is an activate
// else shift in '0'
if (int_do_activate && int_to_chip_r [t_cs])
act_tfaw_shift_reg [3] <= 1'b1;
else
act_tfaw_shift_reg [3] <= 1'b0;
end
end
// Shift register [n : 3]
for (t_tfaw = 4;t_tfaw < NUM_OF_TFAW_SHIFT_REG;t_tfaw = t_tfaw + 1)
begin : tfaw_shift_register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [t_tfaw] <= 1'b0;
end
else
begin
act_tfaw_shift_reg [t_tfaw] <= act_tfaw_shift_reg [t_tfaw - 1];
end
end
end
// Activate command counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_cmd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt;
else
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt + 1'b1;
end
else if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt - 1'b1;
end
end
// tFAW ready signal
always @ (*)
begin
// If tFAW is lesser than 4, this means we can do back-to-back activate without tFAW constraint
if (less_than_4_four_act_to_act)
begin
act_tfaw_ready_combi [t_cs] = 1'b1;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs] && act_tfaw_cmd_cnt == 3'd3)
act_tfaw_ready_combi [t_cs] = 1'b0;
else if (act_tfaw_cmd_cnt < 3'd4)
act_tfaw_ready_combi [t_cs] = 1'b1;
else
act_tfaw_ready_combi [t_cs] = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_ready [t_cs] <= 1'b0;
end
else
begin
act_tfaw_ready [t_cs] <= act_tfaw_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// tRRD Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_trrd_cnt;
// tRRD counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET - 1;
end
else
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET;
end
end
else if (act_trrd_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
begin
act_trrd_cnt <= act_trrd_cnt + 1'b1;
end
end
end
// tRRD monitor
always @ (*)
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (!ENABLE_BETTER_TRRD_EFFICIENCY && less_than_x0_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else if (ENABLE_BETTER_TRRD_EFFICIENCY && less_than_xn1_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
else if (act_trrd_cnt >= t_param_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_ready [t_cs] <= 1'b0;
end
else
begin
act_trrd_ready [t_cs] <= act_trrd_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// Overall activate ready
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [t_cs])
begin
act_ready [t_cs] = 1'b0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_ready [t_cs] = act_trrd_ready_combi [t_cs] & act_tfaw_ready_combi [t_cs];
end
else
begin
act_ready [t_cs] = act_trrd_ready [t_cs] & act_tfaw_ready [t_cs];
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Activate Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read/Write Monitor
//
// Monitors the following rank timing parameters:
//
// - Write to read timing parameter (tWTR)
// - Read to write timing parameter
//
// Missing Features:
//
// - Burst interrupt
// - Burst terminate
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Effective Timing Parameters
// Only when burst interrupt option is enabled
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (*)
begin
if (int_do_burst_chop)
begin
effective_rd_to_wr_combi = t_param_rd_to_wr_bc;
effective_rd_to_wr_diff_chip_combi = t_param_rd_to_wr_diff_chip;
effective_wr_to_rd_combi = t_param_wr_to_rd_bc;
effective_wr_to_rd_diff_chip_combi = t_param_wr_to_rd_diff_chip;
end
else if (int_do_burst_terminate)
begin
if (t_param_rd_to_wr > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_combi = t_param_rd_to_wr - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_combi = 1'b1;
if (t_param_rd_to_wr_diff_chip > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_diff_chip_combi = t_param_rd_to_wr_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_diff_chip_combi = 1'b1;
if (t_param_wr_to_rd > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_combi = t_param_wr_to_rd - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_combi = 1'b1;
if (t_param_wr_to_rd_diff_chip > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_diff_chip_combi = t_param_wr_to_rd_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_diff_chip_combi = 1'b1;
end
else
begin
effective_rd_to_wr_combi = effective_rd_to_wr;
effective_rd_to_wr_diff_chip_combi = effective_rd_to_wr_diff_chip;
effective_wr_to_rd_combi = effective_wr_to_rd;
effective_wr_to_rd_diff_chip_combi = effective_wr_to_rd_diff_chip;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
effective_rd_to_wr <= 0;
effective_rd_to_wr_diff_chip <= 0;
effective_wr_to_rd <= 0;
effective_wr_to_rd_diff_chip <= 0;
end
else
begin
effective_rd_to_wr <= effective_rd_to_wr_combi;
effective_rd_to_wr_diff_chip <= effective_rd_to_wr_diff_chip_combi;
effective_wr_to_rd <= effective_wr_to_rd_combi;
effective_wr_to_rd_diff_chip <= effective_wr_to_rd_diff_chip_combi;
end
end
//----------------------------------------------------------------------------------------------------
// Read / Write State Machine
//----------------------------------------------------------------------------------------------------
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : rdwr_monitor_per_chip
reg [1 : 0] rdwr_state;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_diff_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_diff_chip;
reg int_do_read_this_chip;
reg int_do_write_this_chip;
reg int_do_read_diff_chip;
reg int_do_write_diff_chip;
reg doing_burst_chop;
reg doing_burst_terminate;
reg int_read_ready;
reg int_write_ready;
// Do read/write to this/different chip
always @ (*)
begin
if (int_do_read)
begin
if (int_to_chip_c [s_cs])
begin
int_do_read_this_chip = 1'b1;
int_do_read_diff_chip = 1'b0;
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b1;
end
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b0;
end
end
always @ (*)
begin
if (int_do_write)
begin
if (int_to_chip_c [s_cs])
begin
int_do_write_this_chip = 1'b1;
int_do_write_diff_chip = 1'b0;
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b1;
end
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b0;
end
end
// Read write counter to this chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_this_chip <= 0;
write_cnt_this_chip <= 0;
end
else
begin
if (int_do_read_this_chip)
read_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_this_chip <= read_cnt_this_chip + 1'b1;
if (int_do_write_this_chip)
write_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_this_chip <= write_cnt_this_chip + 1'b1;
end
end
// Read write counter to different chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_diff_chip <= 0;
write_cnt_diff_chip <= 0;
end
else
begin
if (int_do_read_diff_chip)
read_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_diff_chip <= read_cnt_diff_chip + 1'b1;
if (int_do_write_diff_chip)
write_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_diff_chip <= write_cnt_diff_chip + 1'b1;
end
end
// Doing burst chop signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_chop <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
begin
if (int_do_burst_chop)
doing_burst_chop <= 1'b1;
else
doing_burst_chop <= 1'b0;
end
end
end
// Doing burst terminate signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
doing_burst_terminate <= 1'b0;
else if (int_do_burst_terminate && int_to_chip_c [s_cs]) // to current chip only
doing_burst_terminate <= 1'b1;
end
end
// Register comparison logic for better fMAX
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (less_than_x1_rd_to_rd)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (less_than_x1_rd_to_wr)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (t_param_rd_to_rd - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (read_cnt_this_chip >= (t_param_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (less_than_x1_rd_to_rd_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (less_than_x1_rd_to_wr_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (t_param_rd_to_rd_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (read_cnt_diff_chip >= (t_param_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (less_than_x1_wr_to_wr)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (less_than_x1_wr_to_rd)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (t_param_wr_to_wr - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (write_cnt_this_chip >= (t_param_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (less_than_x1_wr_to_wr_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (less_than_x1_wr_to_rd_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (t_param_wr_to_wr_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (write_cnt_diff_chip >= (t_param_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (t_param_rd_to_wr <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (effective_rd_to_wr_combi - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (t_param_rd_to_wr_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (effective_rd_to_wr_diff_chip_combi - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (t_param_wr_to_rd <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (effective_wr_to_rd_combi - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (t_param_wr_to_rd_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (effective_wr_to_rd_diff_chip_combi - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
// Read write monitor state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b0;
int_write_ready <= 1'b0;
end
else
begin
case (rdwr_state)
IDLE :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b1;
int_write_ready <= 1'b1;
end
end
WR :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
RD :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
default :
rdwr_state <= IDLE;
endcase
end
end
// Assign read/write ready signal to top
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [s_cs])
begin
read_ready [s_cs] = 1'b0;
write_ready [s_cs] = 1'b0;
end
else
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
read_ready [s_cs] = int_read_ready;
write_ready [s_cs] = int_write_ready;
end
else
begin
read_ready [s_cs] = int_read_ready & int_interrupt_ready;
write_ready [s_cs] = int_write_ready & int_interrupt_ready;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Read/Write Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : pch_monitor_per_chip
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [u_cs])
pch_ready [u_cs] = 1'b0;
else
pch_ready [u_cs] = one;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(**************************************************************)
(* FSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable Setoid DecidableTypeEx FSetFacts.
(** First, a version for Weak Sets in functorial presentation *)
Module WDecide_fun (E : DecidableType)(Import M : WSfun E).
Module F := FSetFacts.WFacts_fun E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the FSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module FSetLogicalFacts.
Export Decidable.
Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isn't decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End FSetLogicalFacts.
Import FSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module FSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** remove logical hypothesis inter-dependencies (fix #2136). *)
Ltac no_logical_interdep :=
match goal with
| H : ?P |- _ =>
match type of P with
| Prop =>
match goal with H' : context [ H ] |- _ => clear dependent H' end
| _ => fail
end; no_logical_interdep
| _ => idtac
end.
Ltac abstract_term t :=
tryif (is_var t) then fail "no need to abstract a variable"
else (let x := fresh "x" in set (x := t) in *; try clearbody x).
Ltac abstract_elements :=
repeat
(match goal with
| |- context [ singleton ?t ] => abstract_term t
| _ : context [ singleton ?t ] |- _ => abstract_term t
| |- context [ add ?t _ ] => abstract_term t
| _ : context [ add ?t _ ] |- _ => abstract_term t
| |- context [ remove ?t _ ] => abstract_term t
| _ : context [ remove ?t _ ] |- _ => abstract_term t
| |- context [ In ?t _ ] => abstract_term t
| _ : context [ In ?t _ ] |- _ => abstract_term t
end).
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-FSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive FSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Type) (x y : S),
FSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
FSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
FSet_elt_Prop (In x s)
| True_elt_prop :
FSet_elt_Prop True
| False_elt_prop :
FSet_elt_Prop False
| conj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
FSet_elt_Prop P ->
FSet_elt_Prop (~ P).
Inductive FSet_Prop : Prop -> Prop :=
| elt_FSet_Prop : forall P,
FSet_elt_Prop P ->
FSet_Prop P
| Empty_FSet_Prop : forall s,
FSet_Prop (Empty s)
| Subset_FSet_Prop : forall s1 s2,
FSet_Prop (Subset s1 s2)
| Equal_FSet_Prop : forall s1 s2,
FSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
#[global]
Hint Constructors FSet_elt_Prop FSet_Prop : FSet_Prop.
Ltac discard_nonFSet :=
repeat (
match goal with
| H : context [ @Logic.eq ?T ?x ?y ] |- _ =>
tryif (change T with E.t in H) then fail
else tryif (change T with t in H) then fail
else clear H
| H : ?P |- _ =>
tryif prop (FSet_Prop P) holds by
(auto 100 with FSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [FSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
Lemma eq_refl_iff (x : E.t) : E.eq x x <-> True.
Proof.
now split.
Qed.
Hint Rewrite eq_refl_iff : set_eq_simpl.
(** ** Decidability of FSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [FSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
#[global]
Hint Resolve dec_In dec_eq : FSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
| H : forall x : ?T, _ |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substFSet :=
repeat (
match goal with
| H: E.eq ?x ?x |- _ => clear H
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end);
autorewrite with set_eq_simpl in *.
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_FSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec := progress substFSet; intuition fsetdec_rec.
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
autorewrite with set_eq_simpl in *;
inst_FSet_hypotheses;
autorewrite with set_simpl set_eq_simpl in *;
push not in * using FSet_decidability;
substFSet;
assert_decidability;
auto;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End FSetDecideAuxiliary.
Import FSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** We don't care about the value of elements : complex ones are
abstracted as new variables (avoiding potential dependencies,
see bug #2464) *)
abstract_elements;
(** We remove dependencies to logical hypothesis. This way,
later "clear" will work nicely (see bug #2136) *)
no_logical_interdep;
(** Now we decompose conjunctions, which will allow the
[discard_nonFSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonFSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [FSet_elt_Prop], noting
that any [FSet_elt_Prop] is decidable. *)
pull not using FSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
tryif prop (FSet_elt_Prop P) holds by
(auto 100 with FSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module FSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_add_In : forall x y s,
In x (add y s) ->
~ E.eq x y ->
In x s.
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
Lemma test_baydemir :
forall (f : t -> t),
forall (s : t),
forall (x y : elt),
In x (add y (f s)) ->
~ E.eq x y ->
In x (f s).
Proof.
fsetdec.
Qed.
End FSetDecideTestCases.
End WDecide_fun.
Require Import FSetInterface.
(** Now comes variants for self-contained weak sets and for full sets.
For these variants, only one argument is necessary. Thanks to
the subtyping [WS<=S], the [Decide] functor which is meant to be
used on modules [(M:S)] can simply be an alias of [WDecide]. *)
Module WDecide (M:WS) := !WDecide_fun M.E M.
Module Decide := WDecide.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_TB_V
`define SKY130_FD_SC_HS__XNOR2_TB_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xnor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam Michael
// Date: 10/15/2015
// Summary: Iterates through the RAM addresses, sending each to UART until it
// reaches NumberOfChars
//////////////////////////////////////////////////////////////////////////////////
module SendChars(NumberOfChars, Clock, Reset, Start, tx_full, uartClock, RAMAddress, Transmitting, write_to_uart);
input [5:0] NumberOfChars;
input Clock, Reset, Start, tx_full, uartClock;
output reg [5:0] RAMAddress;
output reg Transmitting, write_to_uart;
reg [1:0] specialCharacter;
parameter [5:0] newline = 6'd32;
parameter [5:0] carriagereturn = 6'd33;
always @ (posedge Clock)
if (Reset == 1) begin write_to_uart <= 1'b0; RAMAddress <= 6'd0; specialCharacter <= 2'd0; Transmitting <= 1'b0; end
else if (Start == 1'b1 && Transmitting == 1'b0) begin Transmitting <= 1'b1; write_to_uart <= 1; end
else case ({tx_full, Transmitting, uartClock, specialCharacter})
5'b01100: begin
write_to_uart <= 1;
if (RAMAddress+2>NumberOfChars) begin RAMAddress <= newline; specialCharacter <= 2'd1; end
else RAMAddress <= RAMAddress + 1'b1;
end
5'b01101: begin
write_to_uart <= 1;
RAMAddress <= carriagereturn;
specialCharacter <= 2'd2;
end
5'b01110: begin
write_to_uart <= 0;
Transmitting <= 1'b0;
RAMAddress <= 6'd0;
specialCharacter <= 2'd0;
end
default: begin
write_to_uart <= 1'b0;
end
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFXBP_PP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_SYMBOL_V
`define SKY130_FD_SC_MS__O21AI_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_BLACKBOX_V
`define SKY130_FD_SC_LP__O2BB2A_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_BLACKBOX_V
|
``
source sfr_gen.tcl
proc verilog_width_decl { width } {
if {$width==1} {
return ""
} else {
``[`$width`-1:0] ``
}
return [tgpp::getProcOutput]
}
proc decl_hardware_update_port { bf_name props } {
dict with props {
if {[is_updated_by_hardware $props]} {
if { $set_by_hardware && $cleared_by_hardware} {
dict set ::hw_update_ports $bf_name $props``
input wire `verilog_width_decl $width`sfr_`$bf_name`_wr,
input wire sfr_`$bf_name`_wren,
``
} else {
if {$cleared_by_hardware} {
set action "clear"
dict set ::hw_clear_ports $bf_name $props
} else {
set action "set"
dict set ::hw_set_ports $bf_name $props
}``
input wire sfr_`$bf_name`_`$action`,
``
}
}
if {$read_sensitive} {
dict set ::hw_read_sens_ports $bf_name $props``
output reg sfr_`$bf_name`_read,
`` }
if {$write_sensitive} {
dict set ::hw_write_sens_ports $bf_name $props``
output reg sfr_`$bf_name`_write,
`` }
}
return [string range [tgpp::getProcOutput] 0 end-1]
}
proc sfr_apb_module { sfrs {custom_clock 0} {latched_read 1} } {
set clock PCLK
if { $custom_clock } {
set clock i_clk
set clock_en i_apb_clk_en
}
set hasContainers 0
set hasHardwareUpdate 0
set ::hw_update_ports [dict create]
set ::hw_set_ports [dict create]
set ::hw_clear_ports [dict create]
set ::hw_read_sens_ports [dict create]
set ::hw_write_sens_ports [dict create]
``
/*
`bitfield_to_string $sfrs`
*/
module `dict get $sfrs name`_apbif (
//SFRs read values
``dict for {sfr_name sfr_props} [dict get $sfrs bitfields] {
if {[is_container $sfr_props]} { #declare each bitfield separately
set hasContainers 1
dict for {bf_name bf_props} [dict get $sfr_props bitfields] {
if {[is_updated_by_hardware $bf_props]} {set hasHardwareUpdate 1}
dict with bf_props {``
output reg `verilog_width_decl $width`sfr_`${sfr_name}_$name`,
`` }
}
} else {
if {[is_updated_by_hardware $bf_props]} {set hasHardwareUpdate 1}
dict with sfr_props {``
output reg `verilog_width_decl $width`sfr_`$name`,
`` }
}
}``
``if {$hasHardwareUpdate} {``//signals for SFRs updated by hardware or read/write sensitive``}
dict for {sfr_name sfr_props} [dict get $sfrs bitfields] {
if {[is_container $sfr_props]} { #declare each bitfield separately
dict for {bf_name bf_props} [dict get $sfr_props bitfields] {
```decl_hardware_update_port ${sfr_name}_$bf_name $bf_props```
}
} else {
```decl_hardware_update_port $sfr_name $sfr_props```
}
}``
//APB inputs
``if {$custom_clock} {``
input wire `$clock`,
input wire `$clock_en`,
``} else {``
input wire PCLK,
``}``
input wire PRESETn,
input wire PSEL,
input wire [11:0] PADDR,
input wire PENABLE,
input wire PWRITE,
input wire [3:0] PSTRB,
input wire [31:0] PWDATA,
//APB outputs
output reg [31:0] PRDATA,
output reg PREADY,
output reg PSLVERR
);
``if {$hasContainers} {``
//bitfields mapping to full SFR words
`` dict for {sfr_name sfr_props} [dict get $sfrs bitfields] {
if {[is_container $sfr_props]} {
set sep " "
set paddingStr ""
set width [dict get $sfr_props width]
set padding [expr [dict get $sfr_props bitfields_width]%32]
if {$padding} {
set paddingStr "\{[expr 32-$padding]\{1'b0\}\}"
set sep ","
}
``
wire `verilog_width_decl $width` sfr_`$sfr_name` = {`$paddingStr`
``
set bf_names [lreverse [dict keys [dict get $sfr_props bitfields]]]
foreach bf_name $bf_names {
set bf_props [dict get $sfr_props bitfields $bf_name]
`` `$sep`sfr_`$sfr_name`_`$bf_name`
``
set sep ","
}
``};
``
}
}
}
set width [dict get $sfrs width]
``
wire sfr_valid_access = PSEL & (PADDR < `expr ($width+7)/8`);
assign PSLVERR = 1'b0;
assign PREADY = 1'b1;
wire sfr_write_access = sfr_valid_access & PENABLE & PWRITE``if {$custom_clock} {`` & `$clock_en```}``;
``
set register_PRDATA 0
if {$latched_read} {
set enable_guard ""
} else {
if {$hasHardwareUpdate} {
set register_PRDATA 1
}
if {$register_PRDATA} {
set eq <=
set sensitivity "posedge $clock, negedge PRESETn"
set enable_guard ""
} else {
set eq =
set sensitivity "*"
set enable_guard "& PENABLE "
}
}
``
wire sfr_read_access = sfr_valid_access `$enable_guard`& ~PWRITE;
``
if {$register_PRDATA || $latched_read} {``
wire sfr_read_access_1st_cycle = sfr_read_access & ~PENABLE;
wire sfr_read_access_2nd_cycle = sfr_read_access & PENABLE;
``}
if {$latched_read} {``
reg [9:0] word_address;
always @(posedge i_clk) if(i_apb_clk_en) word_address <= PADDR[11:2];
``} else {``
wire [9:0] word_address = PADDR[11:2];
``}``
//////////////////////////////////////////////////////////////////////////////////////////////////
// Read registers
//////////////////////////////////////////////////////////////////////////////////////////////////
``
set sens_ports ""
set sep ""
set sens_ports_cnt 0
set apb ""
if {$latched_read} {set apb _apb}
foreach p [dict keys $::hw_read_sens_ports] {
append sens_ports "${sep}sfr_${p}_read$apb"
set sep ","
incr sens_ports_cnt
}
set sep ""
foreach p [dict keys $::hw_write_sens_ports] {
append sens_ports "${sep}sfr_${p}_write"
set sep ","
incr sens_ports_cnt
}
if {$latched_read} {``
reg read_gate;//high during 1 cycle of i_clk
always @(posedge i_clk) begin
read_gate <= i_apb_clk_en & sfr_read_access_1st_cycle;
end
reg [31:0] sfr_read_value;
always @* begin
if(read_gate) PRDATA = sfr_read_value;
end
``dict for {sfr_name sfr_props} [dict get $sfrs bitfields] {
set sens_read [dict exists $::hw_read_sens_ports $sfr_name]
if {$sens_read} {``
reg sfr_`$sfr_name`_read_apb;
always @* sfr_`$sfr_name`_read = read_gate & sfr_`$sfr_name`_read_apb;
`` }
}``
always @* begin
sfr_read_value = 32'hDEADBEEF;
{`$sens_ports`} = {`$sens_ports_cnt`{1'b0}};
if (sfr_read_access) begin
case(word_address)
``dict for {sfr_name sfr_props} [dict get $sfrs bitfields] {
set words [expr [dict get $sfr_props width]/32]
set range ""
for {set word 0} {$word<$words} {incr word} {
set word_address [expr [dict get $sfr_props offset]/32+$word]
set sens_read [dict exists $::hw_read_sens_ports $sfr_name]
set sens_write [dict exists $::hw_write_sens_ports $sfr_name]
if {$words>1} {set range "\[$word*32+:32\]"}
`` `$word_address`: ``if {$sens_read || $sens_write} {``begin
sfr_read_value = sfr_`$sfr_name``$range`;
``
#TODO: handle sens ports within bitfields, currently we support only full reg sens ports
if {$sens_read} {``
sfr_`$sfr_name`_read_apb = 1'b1;
`` }
if {$sens_write} {``
sfr_`$sfr_name`_write = 1'b1;
`` }``
end``} else {``sfr_read_value = sfr_`$sfr_name``$range`;``}``
`` }
}``
endcase
end
end
``} else {``
always @(`$sensitivity`) begin
``
if {$register_PRDATA} {``
if (~PRESETn) begin
PRDATA <= 32'hDEADBEEF;
`` if {$sens_ports_cnt} {``
{`$sens_ports`} <= {`$sens_ports_cnt`{1'b0}};
`` }``
end else if (sfr_read_access_1st_cycle) begin
``} else {``
PRDATA = 32'hDEADBEEF;
`` if {$sens_ports_cnt} {``
{`$sens_ports`} = {`$sens_ports_cnt`{1'b0}};
`` }``
if (sfr_read_access) begin
``}``
case(word_address)
``dict for {sfr_name sfr_props} [dict get $sfrs bitfields] {
set words [expr [dict get $sfr_props width]/32]
set range ""
for {set word 0} {$word<$words} {incr word} {
set word_address [expr [dict get $sfr_props offset]/32+$word]
if {$words>1} {set range "\[$word*32+:32\]"}
`` `$word_address`: PRDATA `$eq` sfr_`$sfr_name``$range`;``
#TODO: handle sens ports within bitfields, currently we support only full reg sens ports
if {[dict exists $::hw_read_sens_ports $sfr_name]} {``sfr_`$sfr_name`_read `$eq` 1'b1;``}
if {[dict exists $::hw_write_sens_ports $sfr_name]} {``sfr_`$sfr_name`_write `$eq` 1'b1;``}``
`` }
}``
endcase
end ``if {$register_PRDATA} {``else if(~sfr_read_access_2nd_cycle) begin
PRDATA <= 32'hDEADBEEF;
{`$sens_ports`} <= {`$sens_ports_cnt`{1'b0}};
end ``}``
end
``}``
//////////////////////////////////////////////////////////////////////////////////////////////////
// Write registers
//////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge `$clock` or negedge PRESETn) begin
if(~PRESETn) begin
``dict for {sfr_name sfr_props} [dict get $sfrs bitfields] {
if {[is_container $sfr_props]} {
dict for {bf_name bf_props} [dict get $sfr_props bitfields] {
set reset_value [dict get $bf_props reset_value]
if {$reset_value!=""} {
`` sfr_`$sfr_name`_`$bf_name` <= `$reset_value`;
`` }
}
} else {
set reset_value [dict get $sfr_props reset_value]
if {$reset_value!=""} {
`` sfr_`$sfr_name` <= `$reset_value`;
`` }
}
}``
end else begin
if(sfr_write_access) begin
case(word_address)
``dict for {sfr_name sfr_props} [dict get $sfrs bitfields] {
set words [expr [dict get $sfr_props width]/32]
set word_base ""
for {set word 0} {$word<$words} {incr word} {
#TODO: handle write sens ports
set word_address [expr [dict get $sfr_props offset]/32+$word]
if {$words>1} {set word_base "$word*32+"}
`` `$word_address`: begin
``
for {set lane 0} {$lane<4} {incr lane} {
if {[is_container $sfr_props]} {
set lane_base [expr $word *32 + $lane *8]
set lane_limit [expr $lane_base + 8]
dict for {bf_name bf_props} [dict get $sfr_props bitfields] {
set width [dict get $bf_props width]
set offset [expr [dict get $bf_props offset]+[dict get $sfr_props offset]]
set lane_limited_offset $offset
if {$lane_base>$lane_limited_offset} {set lane_limited_offset $lane_base}
set lane_limited_width [expr $offset+$width-$lane_base]
if {$lane_limited_width>$width} {set lane_limited_width $width}
if {$lane_limited_width>8} {set lane_limited_width 8}
set offset_in_lane [expr $lane_limited_offset % 8]
if {(![dict get $bf_props read_only]) && ($lane_limited_width>0)} {
#if (PSTRB[`$lane`]) sfr_`$sfr_name`_`$bf_name`[`$lane_limited_offset`+:`$lane_limited_width`] <= PWDATA[`$lane`*8+`$offset_in_lane`+:`$lane_limited_width`];
`` if (PSTRB[`$lane`]) sfr_`$sfr_name`_`$bf_name` <= PWDATA[`$lane`*8+`$offset_in_lane`+:`$lane_limited_width`];
`` }
}
} else {
if {![dict get $sfr_props read_only]} {
`` if (PSTRB[`$lane`]) sfr_`$sfr_name`[`$word_base``$lane`*8+:8] <= PWDATA[`$lane`*8+:8];
`` }
}
}``
end
`` }
}``
endcase
end``if {$hasHardwareUpdate} {`` else begin //hardware set or clear (priority to software)
//TODO: ::hw_set_ports
//TODO: ::hw_clear_ports
end
`` dict for {bf_name props} $::hw_update_ports {
if {![dict get $props read_only]} {``
//WARNING: this bit is updated by hardware and not read only
`` }``
if (sfr_`$bf_name`_wren) sfr_`$bf_name` <= sfr_`$bf_name`_wr;
`` }
``
end
`` }``
end
endmodule
``
return [tgpp::getProcOutput]
}
``
`sfr_apb_module $trng_sfrs 1 1`
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog wrapper for lpflow_clkinvkapwr with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkinvkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* I2C
*/
input wire i2c_scl_i,
output wire i2c_scl_o,
output wire i2c_scl_t,
input wire i2c_sda_i,
output wire i2c_sda_o,
output wire i2c_sda_t,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// XFCP UART interface
wire [7:0] xfcp_uart_interface_down_tdata;
wire xfcp_uart_interface_down_tvalid;
wire xfcp_uart_interface_down_tready;
wire xfcp_uart_interface_down_tlast;
wire xfcp_uart_interface_down_tuser;
wire [7:0] xfcp_uart_interface_up_tdata;
wire xfcp_uart_interface_up_tvalid;
wire xfcp_uart_interface_up_tready;
wire xfcp_uart_interface_up_tlast;
wire xfcp_uart_interface_up_tuser;
xfcp_interface_uart
xfcp_interface_uart_inst (
.clk(clk),
.rst(rst),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.down_xfcp_in_tdata(xfcp_uart_interface_up_tdata),
.down_xfcp_in_tvalid(xfcp_uart_interface_up_tvalid),
.down_xfcp_in_tready(xfcp_uart_interface_up_tready),
.down_xfcp_in_tlast(xfcp_uart_interface_up_tlast),
.down_xfcp_in_tuser(xfcp_uart_interface_up_tuser),
.down_xfcp_out_tdata(xfcp_uart_interface_down_tdata),
.down_xfcp_out_tvalid(xfcp_uart_interface_down_tvalid),
.down_xfcp_out_tready(xfcp_uart_interface_down_tready),
.down_xfcp_out_tlast(xfcp_uart_interface_down_tlast),
.down_xfcp_out_tuser(xfcp_uart_interface_down_tuser),
.prescale(125000000/(115200*8))
);
// XFCP Ethernet interface
wire [7:0] xfcp_udp_interface_down_tdata;
wire xfcp_udp_interface_down_tvalid;
wire xfcp_udp_interface_down_tready;
wire xfcp_udp_interface_down_tlast;
wire xfcp_udp_interface_down_tuser;
wire [7:0] xfcp_udp_interface_up_tdata;
wire xfcp_udp_interface_up_tvalid;
wire xfcp_udp_interface_up_tready;
wire xfcp_udp_interface_up_tlast;
wire xfcp_udp_interface_up_tuser;
// AXI between MAC and Ethernet modules
wire [7:0] rx_eth_axis_tdata;
wire rx_eth_axis_tvalid;
wire rx_eth_axis_tready;
wire rx_eth_axis_tlast;
wire rx_eth_axis_tuser;
wire [7:0] tx_eth_axis_tdata;
wire tx_eth_axis_tvalid;
wire tx_eth_axis_tready;
wire tx_eth_axis_tlast;
wire tx_eth_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [15:0] local_port = 16'd14000;
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
assign phy_reset_n = ~rst;
assign led = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_eth_axis_tdata),
.tx_axis_tvalid(tx_eth_axis_tvalid),
.tx_axis_tready(tx_eth_axis_tready),
.tx_axis_tlast(tx_eth_axis_tlast),
.tx_axis_tuser(tx_eth_axis_tuser),
.rx_axis_tdata(rx_eth_axis_tdata),
.rx_axis_tvalid(rx_eth_axis_tvalid),
.rx_axis_tready(rx_eth_axis_tready),
.rx_axis_tlast(rx_eth_axis_tlast),
.rx_axis_tuser(rx_eth_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
xfcp_interface_udp
xfcp_interface_udp_inst (
.clk(clk),
.rst(rst),
.s_eth_axis_tdata(rx_eth_axis_tdata),
.s_eth_axis_tvalid(rx_eth_axis_tvalid),
.s_eth_axis_tready(rx_eth_axis_tready),
.s_eth_axis_tlast(rx_eth_axis_tlast),
.s_eth_axis_tuser(rx_eth_axis_tuser),
.m_eth_axis_tdata(tx_eth_axis_tdata),
.m_eth_axis_tvalid(tx_eth_axis_tvalid),
.m_eth_axis_tready(tx_eth_axis_tready),
.m_eth_axis_tlast(tx_eth_axis_tlast),
.m_eth_axis_tuser(tx_eth_axis_tuser),
.down_xfcp_in_tdata(xfcp_udp_interface_up_tdata),
.down_xfcp_in_tvalid(xfcp_udp_interface_up_tvalid),
.down_xfcp_in_tready(xfcp_udp_interface_up_tready),
.down_xfcp_in_tlast(xfcp_udp_interface_up_tlast),
.down_xfcp_in_tuser(xfcp_udp_interface_up_tuser),
.down_xfcp_out_tdata(xfcp_udp_interface_down_tdata),
.down_xfcp_out_tvalid(xfcp_udp_interface_down_tvalid),
.down_xfcp_out_tready(xfcp_udp_interface_down_tready),
.down_xfcp_out_tlast(xfcp_udp_interface_down_tlast),
.down_xfcp_out_tuser(xfcp_udp_interface_down_tuser),
.local_mac(local_mac),
.local_ip(local_ip),
.local_port(local_port),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask)
);
// XFCP 2x1 switch
wire [7:0] xfcp_interface_switch_down_tdata;
wire xfcp_interface_switch_down_tvalid;
wire xfcp_interface_switch_down_tready;
wire xfcp_interface_switch_down_tlast;
wire xfcp_interface_switch_down_tuser;
wire [7:0] xfcp_interface_switch_up_tdata;
wire xfcp_interface_switch_up_tvalid;
wire xfcp_interface_switch_up_tready;
wire xfcp_interface_switch_up_tlast;
wire xfcp_interface_switch_up_tuser;
xfcp_arb #(
.PORTS(2)
)
xfcp_interface_arb_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata({xfcp_udp_interface_down_tdata, xfcp_uart_interface_down_tdata}),
.up_xfcp_in_tvalid({xfcp_udp_interface_down_tvalid, xfcp_uart_interface_down_tvalid}),
.up_xfcp_in_tready({xfcp_udp_interface_down_tready, xfcp_uart_interface_down_tready}),
.up_xfcp_in_tlast({xfcp_udp_interface_down_tlast, xfcp_uart_interface_down_tlast}),
.up_xfcp_in_tuser({xfcp_udp_interface_down_tuser, xfcp_uart_interface_down_tuser}),
.up_xfcp_out_tdata({xfcp_udp_interface_up_tdata, xfcp_uart_interface_up_tdata}),
.up_xfcp_out_tvalid({xfcp_udp_interface_up_tvalid, xfcp_uart_interface_up_tvalid}),
.up_xfcp_out_tready({xfcp_udp_interface_up_tready, xfcp_uart_interface_up_tready}),
.up_xfcp_out_tlast({xfcp_udp_interface_up_tlast, xfcp_uart_interface_up_tlast}),
.up_xfcp_out_tuser({xfcp_udp_interface_up_tuser, xfcp_uart_interface_up_tuser}),
.down_xfcp_in_tdata(xfcp_interface_switch_up_tdata),
.down_xfcp_in_tvalid(xfcp_interface_switch_up_tvalid),
.down_xfcp_in_tready(xfcp_interface_switch_up_tready),
.down_xfcp_in_tlast(xfcp_interface_switch_up_tlast),
.down_xfcp_in_tuser(xfcp_interface_switch_up_tuser),
.down_xfcp_out_tdata(xfcp_interface_switch_down_tdata),
.down_xfcp_out_tvalid(xfcp_interface_switch_down_tvalid),
.down_xfcp_out_tready(xfcp_interface_switch_down_tready),
.down_xfcp_out_tlast(xfcp_interface_switch_down_tlast),
.down_xfcp_out_tuser(xfcp_interface_switch_down_tuser)
);
// XFCP 1x4 switch
wire [7:0] xfcp_switch_port_0_down_tdata;
wire xfcp_switch_port_0_down_tvalid;
wire xfcp_switch_port_0_down_tready;
wire xfcp_switch_port_0_down_tlast;
wire xfcp_switch_port_0_down_tuser;
wire [7:0] xfcp_switch_port_0_up_tdata;
wire xfcp_switch_port_0_up_tvalid;
wire xfcp_switch_port_0_up_tready;
wire xfcp_switch_port_0_up_tlast;
wire xfcp_switch_port_0_up_tuser;
wire [7:0] xfcp_switch_port_1_down_tdata;
wire xfcp_switch_port_1_down_tvalid;
wire xfcp_switch_port_1_down_tready;
wire xfcp_switch_port_1_down_tlast;
wire xfcp_switch_port_1_down_tuser;
wire [7:0] xfcp_switch_port_1_up_tdata;
wire xfcp_switch_port_1_up_tvalid;
wire xfcp_switch_port_1_up_tready;
wire xfcp_switch_port_1_up_tlast;
wire xfcp_switch_port_1_up_tuser;
wire [7:0] xfcp_switch_port_2_down_tdata;
wire xfcp_switch_port_2_down_tvalid;
wire xfcp_switch_port_2_down_tready;
wire xfcp_switch_port_2_down_tlast;
wire xfcp_switch_port_2_down_tuser;
wire [7:0] xfcp_switch_port_2_up_tdata;
wire xfcp_switch_port_2_up_tvalid;
wire xfcp_switch_port_2_up_tready;
wire xfcp_switch_port_2_up_tlast;
wire xfcp_switch_port_2_up_tuser;
wire [7:0] xfcp_switch_port_3_down_tdata;
wire xfcp_switch_port_3_down_tvalid;
wire xfcp_switch_port_3_down_tready;
wire xfcp_switch_port_3_down_tlast;
wire xfcp_switch_port_3_down_tuser;
wire [7:0] xfcp_switch_port_3_up_tdata;
wire xfcp_switch_port_3_up_tvalid;
wire xfcp_switch_port_3_up_tready;
wire xfcp_switch_port_3_up_tlast;
wire xfcp_switch_port_3_up_tuser;
xfcp_switch #(
.PORTS(4),
.XFCP_ID_TYPE(16'h0100),
.XFCP_ID_STR("XFCP switch"),
.XFCP_EXT_ID(0),
.XFCP_EXT_ID_STR("NexysVideo")
)
xfcp_switch_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_interface_switch_down_tdata),
.up_xfcp_in_tvalid(xfcp_interface_switch_down_tvalid),
.up_xfcp_in_tready(xfcp_interface_switch_down_tready),
.up_xfcp_in_tlast(xfcp_interface_switch_down_tlast),
.up_xfcp_in_tuser(xfcp_interface_switch_down_tuser),
.up_xfcp_out_tdata(xfcp_interface_switch_up_tdata),
.up_xfcp_out_tvalid(xfcp_interface_switch_up_tvalid),
.up_xfcp_out_tready(xfcp_interface_switch_up_tready),
.up_xfcp_out_tlast(xfcp_interface_switch_up_tlast),
.up_xfcp_out_tuser(xfcp_interface_switch_up_tuser),
.down_xfcp_in_tdata( {xfcp_switch_port_3_up_tdata, xfcp_switch_port_2_up_tdata, xfcp_switch_port_1_up_tdata, xfcp_switch_port_0_up_tdata }),
.down_xfcp_in_tvalid( {xfcp_switch_port_3_up_tvalid, xfcp_switch_port_2_up_tvalid, xfcp_switch_port_1_up_tvalid, xfcp_switch_port_0_up_tvalid }),
.down_xfcp_in_tready( {xfcp_switch_port_3_up_tready, xfcp_switch_port_2_up_tready, xfcp_switch_port_1_up_tready, xfcp_switch_port_0_up_tready }),
.down_xfcp_in_tlast( {xfcp_switch_port_3_up_tlast, xfcp_switch_port_2_up_tlast, xfcp_switch_port_1_up_tlast, xfcp_switch_port_0_up_tlast }),
.down_xfcp_in_tuser( {xfcp_switch_port_3_up_tuser, xfcp_switch_port_2_up_tuser, xfcp_switch_port_1_up_tuser, xfcp_switch_port_0_up_tuser }),
.down_xfcp_out_tdata( {xfcp_switch_port_3_down_tdata, xfcp_switch_port_2_down_tdata, xfcp_switch_port_1_down_tdata, xfcp_switch_port_0_down_tdata }),
.down_xfcp_out_tvalid({xfcp_switch_port_3_down_tvalid, xfcp_switch_port_2_down_tvalid, xfcp_switch_port_1_down_tvalid, xfcp_switch_port_0_down_tvalid}),
.down_xfcp_out_tready({xfcp_switch_port_3_down_tready, xfcp_switch_port_2_down_tready, xfcp_switch_port_1_down_tready, xfcp_switch_port_0_down_tready}),
.down_xfcp_out_tlast( {xfcp_switch_port_3_down_tlast, xfcp_switch_port_2_down_tlast, xfcp_switch_port_1_down_tlast, xfcp_switch_port_0_down_tlast }),
.down_xfcp_out_tuser( {xfcp_switch_port_3_down_tuser, xfcp_switch_port_2_down_tuser, xfcp_switch_port_1_down_tuser, xfcp_switch_port_0_down_tuser })
);
// XFCP WB RAM 0
wire [7:0] ram_0_wb_adr_i;
wire [31:0] ram_0_wb_dat_i;
wire [31:0] ram_0_wb_dat_o;
wire ram_0_wb_we_i;
wire [3:0] ram_0_wb_sel_i;
wire ram_0_wb_stb_i;
wire ram_0_wb_ack_o;
wire ram_0_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 0"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_0 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_0_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_0_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_0_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_0_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_0_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_0_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_0_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_0_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_0_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_0_up_tuser),
.wb_adr_o(ram_0_wb_adr_i),
.wb_dat_i(ram_0_wb_dat_o),
.wb_dat_o(ram_0_wb_dat_i),
.wb_we_o(ram_0_wb_we_i),
.wb_sel_o(ram_0_wb_sel_i),
.wb_stb_o(ram_0_wb_stb_i),
.wb_ack_i(ram_0_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_0_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_0_inst (
.clk(clk),
.adr_i(ram_0_wb_adr_i),
.dat_i(ram_0_wb_dat_i),
.dat_o(ram_0_wb_dat_o),
.we_i(ram_0_wb_we_i),
.sel_i(ram_0_wb_sel_i),
.stb_i(ram_0_wb_stb_i),
.ack_o(ram_0_wb_ack_o),
.cyc_i(ram_0_wb_cyc_i)
);
// XFCP WB RAM 1
wire [7:0] ram_1_wb_adr_i;
wire [31:0] ram_1_wb_dat_i;
wire [31:0] ram_1_wb_dat_o;
wire ram_1_wb_we_i;
wire [3:0] ram_1_wb_sel_i;
wire ram_1_wb_stb_i;
wire ram_1_wb_ack_o;
wire ram_1_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 1"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_1 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_1_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_1_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_1_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_1_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_1_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_1_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_1_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_1_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_1_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_1_up_tuser),
.wb_adr_o(ram_1_wb_adr_i),
.wb_dat_i(ram_1_wb_dat_o),
.wb_dat_o(ram_1_wb_dat_i),
.wb_we_o(ram_1_wb_we_i),
.wb_sel_o(ram_1_wb_sel_i),
.wb_stb_o(ram_1_wb_stb_i),
.wb_ack_i(ram_1_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_1_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_1_inst (
.clk(clk),
.adr_i(ram_1_wb_adr_i),
.dat_i(ram_1_wb_dat_i),
.dat_o(ram_1_wb_dat_o),
.we_i(ram_1_wb_we_i),
.sel_i(ram_1_wb_sel_i),
.stb_i(ram_1_wb_stb_i),
.ack_o(ram_1_wb_ack_o),
.cyc_i(ram_1_wb_cyc_i)
);
// XFCP WB RAM 2
wire [7:0] ram_2_wb_adr_i;
wire [31:0] ram_2_wb_dat_i;
wire [31:0] ram_2_wb_dat_o;
wire ram_2_wb_we_i;
wire [3:0] ram_2_wb_sel_i;
wire ram_2_wb_stb_i;
wire ram_2_wb_ack_o;
wire ram_2_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 2"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_2 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_2_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_2_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_2_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_2_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_2_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_2_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_2_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_2_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_2_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_2_up_tuser),
.wb_adr_o(ram_2_wb_adr_i),
.wb_dat_i(ram_2_wb_dat_o),
.wb_dat_o(ram_2_wb_dat_i),
.wb_we_o(ram_2_wb_we_i),
.wb_sel_o(ram_2_wb_sel_i),
.wb_stb_o(ram_2_wb_stb_i),
.wb_ack_i(ram_2_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_2_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_2_inst (
.clk(clk),
.adr_i(ram_2_wb_adr_i),
.dat_i(ram_2_wb_dat_i),
.dat_o(ram_2_wb_dat_o),
.we_i(ram_2_wb_we_i),
.sel_i(ram_2_wb_sel_i),
.stb_i(ram_2_wb_stb_i),
.ack_o(ram_2_wb_ack_o),
.cyc_i(ram_2_wb_cyc_i)
);
// XFCP I2C Master
xfcp_mod_i2c_master #(
.XFCP_ID_STR("XFCP I2C Master"),
.DEFAULT_PRESCALE(125000000/(400000*4))
)
i2c_master_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_3_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_3_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_3_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_3_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_3_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_3_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_3_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_3_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_3_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_3_up_tuser),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_1_V
`define SKY130_FD_SC_HDLL__CLKINV_1_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_1_V
|
//-----------------------------------------------------------------------------
// system_nfa_accept_samples_generic_hw_top_4_wrapper.v
//-----------------------------------------------------------------------------
module system_nfa_accept_samples_generic_hw_top_4_wrapper
(
aclk,
aresetn,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
nfa_finals_buckets_MPLB_Clk,
nfa_finals_buckets_MPLB_Rst,
nfa_finals_buckets_M_request,
nfa_finals_buckets_M_priority,
nfa_finals_buckets_M_busLock,
nfa_finals_buckets_M_RNW,
nfa_finals_buckets_M_BE,
nfa_finals_buckets_M_MSize,
nfa_finals_buckets_M_size,
nfa_finals_buckets_M_type,
nfa_finals_buckets_M_TAttribute,
nfa_finals_buckets_M_lockErr,
nfa_finals_buckets_M_abort,
nfa_finals_buckets_M_UABus,
nfa_finals_buckets_M_ABus,
nfa_finals_buckets_M_wrDBus,
nfa_finals_buckets_M_wrBurst,
nfa_finals_buckets_M_rdBurst,
nfa_finals_buckets_PLB_MAddrAck,
nfa_finals_buckets_PLB_MSSize,
nfa_finals_buckets_PLB_MRearbitrate,
nfa_finals_buckets_PLB_MTimeout,
nfa_finals_buckets_PLB_MBusy,
nfa_finals_buckets_PLB_MRdErr,
nfa_finals_buckets_PLB_MWrErr,
nfa_finals_buckets_PLB_MIRQ,
nfa_finals_buckets_PLB_MRdDBus,
nfa_finals_buckets_PLB_MRdWdAddr,
nfa_finals_buckets_PLB_MRdDAck,
nfa_finals_buckets_PLB_MRdBTerm,
nfa_finals_buckets_PLB_MWrDAck,
nfa_finals_buckets_PLB_MWrBTerm,
nfa_forward_buckets_MPLB_Clk,
nfa_forward_buckets_MPLB_Rst,
nfa_forward_buckets_M_request,
nfa_forward_buckets_M_priority,
nfa_forward_buckets_M_busLock,
nfa_forward_buckets_M_RNW,
nfa_forward_buckets_M_BE,
nfa_forward_buckets_M_MSize,
nfa_forward_buckets_M_size,
nfa_forward_buckets_M_type,
nfa_forward_buckets_M_TAttribute,
nfa_forward_buckets_M_lockErr,
nfa_forward_buckets_M_abort,
nfa_forward_buckets_M_UABus,
nfa_forward_buckets_M_ABus,
nfa_forward_buckets_M_wrDBus,
nfa_forward_buckets_M_wrBurst,
nfa_forward_buckets_M_rdBurst,
nfa_forward_buckets_PLB_MAddrAck,
nfa_forward_buckets_PLB_MSSize,
nfa_forward_buckets_PLB_MRearbitrate,
nfa_forward_buckets_PLB_MTimeout,
nfa_forward_buckets_PLB_MBusy,
nfa_forward_buckets_PLB_MRdErr,
nfa_forward_buckets_PLB_MWrErr,
nfa_forward_buckets_PLB_MIRQ,
nfa_forward_buckets_PLB_MRdDBus,
nfa_forward_buckets_PLB_MRdWdAddr,
nfa_forward_buckets_PLB_MRdDAck,
nfa_forward_buckets_PLB_MRdBTerm,
nfa_forward_buckets_PLB_MWrDAck,
nfa_forward_buckets_PLB_MWrBTerm,
nfa_initials_buckets_MPLB_Clk,
nfa_initials_buckets_MPLB_Rst,
nfa_initials_buckets_M_request,
nfa_initials_buckets_M_priority,
nfa_initials_buckets_M_busLock,
nfa_initials_buckets_M_RNW,
nfa_initials_buckets_M_BE,
nfa_initials_buckets_M_MSize,
nfa_initials_buckets_M_size,
nfa_initials_buckets_M_type,
nfa_initials_buckets_M_TAttribute,
nfa_initials_buckets_M_lockErr,
nfa_initials_buckets_M_abort,
nfa_initials_buckets_M_UABus,
nfa_initials_buckets_M_ABus,
nfa_initials_buckets_M_wrDBus,
nfa_initials_buckets_M_wrBurst,
nfa_initials_buckets_M_rdBurst,
nfa_initials_buckets_PLB_MAddrAck,
nfa_initials_buckets_PLB_MSSize,
nfa_initials_buckets_PLB_MRearbitrate,
nfa_initials_buckets_PLB_MTimeout,
nfa_initials_buckets_PLB_MBusy,
nfa_initials_buckets_PLB_MRdErr,
nfa_initials_buckets_PLB_MWrErr,
nfa_initials_buckets_PLB_MIRQ,
nfa_initials_buckets_PLB_MRdDBus,
nfa_initials_buckets_PLB_MRdWdAddr,
nfa_initials_buckets_PLB_MRdDAck,
nfa_initials_buckets_PLB_MRdBTerm,
nfa_initials_buckets_PLB_MWrDAck,
nfa_initials_buckets_PLB_MWrBTerm,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ
);
input aclk;
input aresetn;
input indices_MPLB_Clk;
input indices_MPLB_Rst;
output indices_M_request;
output [0:1] indices_M_priority;
output indices_M_busLock;
output indices_M_RNW;
output [0:7] indices_M_BE;
output [0:1] indices_M_MSize;
output [0:3] indices_M_size;
output [0:2] indices_M_type;
output [0:15] indices_M_TAttribute;
output indices_M_lockErr;
output indices_M_abort;
output [0:31] indices_M_UABus;
output [0:31] indices_M_ABus;
output [0:63] indices_M_wrDBus;
output indices_M_wrBurst;
output indices_M_rdBurst;
input indices_PLB_MAddrAck;
input [0:1] indices_PLB_MSSize;
input indices_PLB_MRearbitrate;
input indices_PLB_MTimeout;
input indices_PLB_MBusy;
input indices_PLB_MRdErr;
input indices_PLB_MWrErr;
input indices_PLB_MIRQ;
input [0:63] indices_PLB_MRdDBus;
input [0:3] indices_PLB_MRdWdAddr;
input indices_PLB_MRdDAck;
input indices_PLB_MRdBTerm;
input indices_PLB_MWrDAck;
input indices_PLB_MWrBTerm;
input nfa_finals_buckets_MPLB_Clk;
input nfa_finals_buckets_MPLB_Rst;
output nfa_finals_buckets_M_request;
output [0:1] nfa_finals_buckets_M_priority;
output nfa_finals_buckets_M_busLock;
output nfa_finals_buckets_M_RNW;
output [0:7] nfa_finals_buckets_M_BE;
output [0:1] nfa_finals_buckets_M_MSize;
output [0:3] nfa_finals_buckets_M_size;
output [0:2] nfa_finals_buckets_M_type;
output [0:15] nfa_finals_buckets_M_TAttribute;
output nfa_finals_buckets_M_lockErr;
output nfa_finals_buckets_M_abort;
output [0:31] nfa_finals_buckets_M_UABus;
output [0:31] nfa_finals_buckets_M_ABus;
output [0:63] nfa_finals_buckets_M_wrDBus;
output nfa_finals_buckets_M_wrBurst;
output nfa_finals_buckets_M_rdBurst;
input nfa_finals_buckets_PLB_MAddrAck;
input [0:1] nfa_finals_buckets_PLB_MSSize;
input nfa_finals_buckets_PLB_MRearbitrate;
input nfa_finals_buckets_PLB_MTimeout;
input nfa_finals_buckets_PLB_MBusy;
input nfa_finals_buckets_PLB_MRdErr;
input nfa_finals_buckets_PLB_MWrErr;
input nfa_finals_buckets_PLB_MIRQ;
input [0:63] nfa_finals_buckets_PLB_MRdDBus;
input [0:3] nfa_finals_buckets_PLB_MRdWdAddr;
input nfa_finals_buckets_PLB_MRdDAck;
input nfa_finals_buckets_PLB_MRdBTerm;
input nfa_finals_buckets_PLB_MWrDAck;
input nfa_finals_buckets_PLB_MWrBTerm;
input nfa_forward_buckets_MPLB_Clk;
input nfa_forward_buckets_MPLB_Rst;
output nfa_forward_buckets_M_request;
output [0:1] nfa_forward_buckets_M_priority;
output nfa_forward_buckets_M_busLock;
output nfa_forward_buckets_M_RNW;
output [0:7] nfa_forward_buckets_M_BE;
output [0:1] nfa_forward_buckets_M_MSize;
output [0:3] nfa_forward_buckets_M_size;
output [0:2] nfa_forward_buckets_M_type;
output [0:15] nfa_forward_buckets_M_TAttribute;
output nfa_forward_buckets_M_lockErr;
output nfa_forward_buckets_M_abort;
output [0:31] nfa_forward_buckets_M_UABus;
output [0:31] nfa_forward_buckets_M_ABus;
output [0:63] nfa_forward_buckets_M_wrDBus;
output nfa_forward_buckets_M_wrBurst;
output nfa_forward_buckets_M_rdBurst;
input nfa_forward_buckets_PLB_MAddrAck;
input [0:1] nfa_forward_buckets_PLB_MSSize;
input nfa_forward_buckets_PLB_MRearbitrate;
input nfa_forward_buckets_PLB_MTimeout;
input nfa_forward_buckets_PLB_MBusy;
input nfa_forward_buckets_PLB_MRdErr;
input nfa_forward_buckets_PLB_MWrErr;
input nfa_forward_buckets_PLB_MIRQ;
input [0:63] nfa_forward_buckets_PLB_MRdDBus;
input [0:3] nfa_forward_buckets_PLB_MRdWdAddr;
input nfa_forward_buckets_PLB_MRdDAck;
input nfa_forward_buckets_PLB_MRdBTerm;
input nfa_forward_buckets_PLB_MWrDAck;
input nfa_forward_buckets_PLB_MWrBTerm;
input nfa_initials_buckets_MPLB_Clk;
input nfa_initials_buckets_MPLB_Rst;
output nfa_initials_buckets_M_request;
output [0:1] nfa_initials_buckets_M_priority;
output nfa_initials_buckets_M_busLock;
output nfa_initials_buckets_M_RNW;
output [0:7] nfa_initials_buckets_M_BE;
output [0:1] nfa_initials_buckets_M_MSize;
output [0:3] nfa_initials_buckets_M_size;
output [0:2] nfa_initials_buckets_M_type;
output [0:15] nfa_initials_buckets_M_TAttribute;
output nfa_initials_buckets_M_lockErr;
output nfa_initials_buckets_M_abort;
output [0:31] nfa_initials_buckets_M_UABus;
output [0:31] nfa_initials_buckets_M_ABus;
output [0:63] nfa_initials_buckets_M_wrDBus;
output nfa_initials_buckets_M_wrBurst;
output nfa_initials_buckets_M_rdBurst;
input nfa_initials_buckets_PLB_MAddrAck;
input [0:1] nfa_initials_buckets_PLB_MSSize;
input nfa_initials_buckets_PLB_MRearbitrate;
input nfa_initials_buckets_PLB_MTimeout;
input nfa_initials_buckets_PLB_MBusy;
input nfa_initials_buckets_PLB_MRdErr;
input nfa_initials_buckets_PLB_MWrErr;
input nfa_initials_buckets_PLB_MIRQ;
input [0:63] nfa_initials_buckets_PLB_MRdDBus;
input [0:3] nfa_initials_buckets_PLB_MRdWdAddr;
input nfa_initials_buckets_PLB_MRdDAck;
input nfa_initials_buckets_PLB_MRdBTerm;
input nfa_initials_buckets_PLB_MWrDAck;
input nfa_initials_buckets_PLB_MWrBTerm;
input sample_buffer_MPLB_Clk;
input sample_buffer_MPLB_Rst;
output sample_buffer_M_request;
output [0:1] sample_buffer_M_priority;
output sample_buffer_M_busLock;
output sample_buffer_M_RNW;
output [0:7] sample_buffer_M_BE;
output [0:1] sample_buffer_M_MSize;
output [0:3] sample_buffer_M_size;
output [0:2] sample_buffer_M_type;
output [0:15] sample_buffer_M_TAttribute;
output sample_buffer_M_lockErr;
output sample_buffer_M_abort;
output [0:31] sample_buffer_M_UABus;
output [0:31] sample_buffer_M_ABus;
output [0:63] sample_buffer_M_wrDBus;
output sample_buffer_M_wrBurst;
output sample_buffer_M_rdBurst;
input sample_buffer_PLB_MAddrAck;
input [0:1] sample_buffer_PLB_MSSize;
input sample_buffer_PLB_MRearbitrate;
input sample_buffer_PLB_MTimeout;
input sample_buffer_PLB_MBusy;
input sample_buffer_PLB_MRdErr;
input sample_buffer_PLB_MWrErr;
input sample_buffer_PLB_MIRQ;
input [0:63] sample_buffer_PLB_MRdDBus;
input [0:3] sample_buffer_PLB_MRdWdAddr;
input sample_buffer_PLB_MRdDAck;
input sample_buffer_PLB_MRdBTerm;
input sample_buffer_PLB_MWrDAck;
input sample_buffer_PLB_MWrBTerm;
input splb_slv0_SPLB_Clk;
input splb_slv0_SPLB_Rst;
input [0:31] splb_slv0_PLB_ABus;
input [0:31] splb_slv0_PLB_UABus;
input splb_slv0_PLB_PAValid;
input splb_slv0_PLB_SAValid;
input splb_slv0_PLB_rdPrim;
input splb_slv0_PLB_wrPrim;
input [0:2] splb_slv0_PLB_masterID;
input splb_slv0_PLB_abort;
input splb_slv0_PLB_busLock;
input splb_slv0_PLB_RNW;
input [0:7] splb_slv0_PLB_BE;
input [0:1] splb_slv0_PLB_MSize;
input [0:3] splb_slv0_PLB_size;
input [0:2] splb_slv0_PLB_type;
input splb_slv0_PLB_lockErr;
input [0:63] splb_slv0_PLB_wrDBus;
input splb_slv0_PLB_wrBurst;
input splb_slv0_PLB_rdBurst;
input splb_slv0_PLB_wrPendReq;
input splb_slv0_PLB_rdPendReq;
input [0:1] splb_slv0_PLB_wrPendPri;
input [0:1] splb_slv0_PLB_rdPendPri;
input [0:1] splb_slv0_PLB_reqPri;
input [0:15] splb_slv0_PLB_TAttribute;
output splb_slv0_Sl_addrAck;
output [0:1] splb_slv0_Sl_SSize;
output splb_slv0_Sl_wait;
output splb_slv0_Sl_rearbitrate;
output splb_slv0_Sl_wrDAck;
output splb_slv0_Sl_wrComp;
output splb_slv0_Sl_wrBTerm;
output [0:63] splb_slv0_Sl_rdDBus;
output [0:3] splb_slv0_Sl_rdWdAddr;
output splb_slv0_Sl_rdDAck;
output splb_slv0_Sl_rdComp;
output splb_slv0_Sl_rdBTerm;
output [0:5] splb_slv0_Sl_MBusy;
output [0:5] splb_slv0_Sl_MWrErr;
output [0:5] splb_slv0_Sl_MRdErr;
output [0:5] splb_slv0_Sl_MIRQ;
nfa_accept_samples_generic_hw_top
#(
.RESET_ACTIVE_LOW ( 1 ),
.C_indices_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_indices_AWIDTH ( 32 ),
.C_indices_DWIDTH ( 64 ),
.C_indices_NATIVE_DWIDTH ( 64 ),
.C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_finals_buckets_AWIDTH ( 32 ),
.C_nfa_finals_buckets_DWIDTH ( 64 ),
.C_nfa_finals_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_forward_buckets_AWIDTH ( 32 ),
.C_nfa_forward_buckets_DWIDTH ( 64 ),
.C_nfa_forward_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_initials_buckets_AWIDTH ( 32 ),
.C_nfa_initials_buckets_DWIDTH ( 64 ),
.C_nfa_initials_buckets_NATIVE_DWIDTH ( 64 ),
.C_sample_buffer_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_sample_buffer_AWIDTH ( 32 ),
.C_sample_buffer_DWIDTH ( 64 ),
.C_sample_buffer_NATIVE_DWIDTH ( 64 ),
.C_SPLB_SLV0_BASEADDR ( 32'hD4000000 ),
.C_SPLB_SLV0_HIGHADDR ( 32'hD40000FF ),
.C_SPLB_SLV0_AWIDTH ( 32 ),
.C_SPLB_SLV0_DWIDTH ( 64 ),
.C_SPLB_SLV0_NUM_MASTERS ( 6 ),
.C_SPLB_SLV0_MID_WIDTH ( 3 ),
.C_SPLB_SLV0_NATIVE_DWIDTH ( 32 ),
.C_SPLB_SLV0_P2P ( 0 ),
.C_SPLB_SLV0_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SLV0_SMALLEST_MASTER ( 32 ),
.C_SPLB_SLV0_INCLUDE_DPHASE_TIMER ( 0 )
)
nfa_accept_samples_generic_hw_top_4 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.indices_MPLB_Clk ( indices_MPLB_Clk ),
.indices_MPLB_Rst ( indices_MPLB_Rst ),
.indices_M_request ( indices_M_request ),
.indices_M_priority ( indices_M_priority ),
.indices_M_busLock ( indices_M_busLock ),
.indices_M_RNW ( indices_M_RNW ),
.indices_M_BE ( indices_M_BE ),
.indices_M_MSize ( indices_M_MSize ),
.indices_M_size ( indices_M_size ),
.indices_M_type ( indices_M_type ),
.indices_M_TAttribute ( indices_M_TAttribute ),
.indices_M_lockErr ( indices_M_lockErr ),
.indices_M_abort ( indices_M_abort ),
.indices_M_UABus ( indices_M_UABus ),
.indices_M_ABus ( indices_M_ABus ),
.indices_M_wrDBus ( indices_M_wrDBus ),
.indices_M_wrBurst ( indices_M_wrBurst ),
.indices_M_rdBurst ( indices_M_rdBurst ),
.indices_PLB_MAddrAck ( indices_PLB_MAddrAck ),
.indices_PLB_MSSize ( indices_PLB_MSSize ),
.indices_PLB_MRearbitrate ( indices_PLB_MRearbitrate ),
.indices_PLB_MTimeout ( indices_PLB_MTimeout ),
.indices_PLB_MBusy ( indices_PLB_MBusy ),
.indices_PLB_MRdErr ( indices_PLB_MRdErr ),
.indices_PLB_MWrErr ( indices_PLB_MWrErr ),
.indices_PLB_MIRQ ( indices_PLB_MIRQ ),
.indices_PLB_MRdDBus ( indices_PLB_MRdDBus ),
.indices_PLB_MRdWdAddr ( indices_PLB_MRdWdAddr ),
.indices_PLB_MRdDAck ( indices_PLB_MRdDAck ),
.indices_PLB_MRdBTerm ( indices_PLB_MRdBTerm ),
.indices_PLB_MWrDAck ( indices_PLB_MWrDAck ),
.indices_PLB_MWrBTerm ( indices_PLB_MWrBTerm ),
.nfa_finals_buckets_MPLB_Clk ( nfa_finals_buckets_MPLB_Clk ),
.nfa_finals_buckets_MPLB_Rst ( nfa_finals_buckets_MPLB_Rst ),
.nfa_finals_buckets_M_request ( nfa_finals_buckets_M_request ),
.nfa_finals_buckets_M_priority ( nfa_finals_buckets_M_priority ),
.nfa_finals_buckets_M_busLock ( nfa_finals_buckets_M_busLock ),
.nfa_finals_buckets_M_RNW ( nfa_finals_buckets_M_RNW ),
.nfa_finals_buckets_M_BE ( nfa_finals_buckets_M_BE ),
.nfa_finals_buckets_M_MSize ( nfa_finals_buckets_M_MSize ),
.nfa_finals_buckets_M_size ( nfa_finals_buckets_M_size ),
.nfa_finals_buckets_M_type ( nfa_finals_buckets_M_type ),
.nfa_finals_buckets_M_TAttribute ( nfa_finals_buckets_M_TAttribute ),
.nfa_finals_buckets_M_lockErr ( nfa_finals_buckets_M_lockErr ),
.nfa_finals_buckets_M_abort ( nfa_finals_buckets_M_abort ),
.nfa_finals_buckets_M_UABus ( nfa_finals_buckets_M_UABus ),
.nfa_finals_buckets_M_ABus ( nfa_finals_buckets_M_ABus ),
.nfa_finals_buckets_M_wrDBus ( nfa_finals_buckets_M_wrDBus ),
.nfa_finals_buckets_M_wrBurst ( nfa_finals_buckets_M_wrBurst ),
.nfa_finals_buckets_M_rdBurst ( nfa_finals_buckets_M_rdBurst ),
.nfa_finals_buckets_PLB_MAddrAck ( nfa_finals_buckets_PLB_MAddrAck ),
.nfa_finals_buckets_PLB_MSSize ( nfa_finals_buckets_PLB_MSSize ),
.nfa_finals_buckets_PLB_MRearbitrate ( nfa_finals_buckets_PLB_MRearbitrate ),
.nfa_finals_buckets_PLB_MTimeout ( nfa_finals_buckets_PLB_MTimeout ),
.nfa_finals_buckets_PLB_MBusy ( nfa_finals_buckets_PLB_MBusy ),
.nfa_finals_buckets_PLB_MRdErr ( nfa_finals_buckets_PLB_MRdErr ),
.nfa_finals_buckets_PLB_MWrErr ( nfa_finals_buckets_PLB_MWrErr ),
.nfa_finals_buckets_PLB_MIRQ ( nfa_finals_buckets_PLB_MIRQ ),
.nfa_finals_buckets_PLB_MRdDBus ( nfa_finals_buckets_PLB_MRdDBus ),
.nfa_finals_buckets_PLB_MRdWdAddr ( nfa_finals_buckets_PLB_MRdWdAddr ),
.nfa_finals_buckets_PLB_MRdDAck ( nfa_finals_buckets_PLB_MRdDAck ),
.nfa_finals_buckets_PLB_MRdBTerm ( nfa_finals_buckets_PLB_MRdBTerm ),
.nfa_finals_buckets_PLB_MWrDAck ( nfa_finals_buckets_PLB_MWrDAck ),
.nfa_finals_buckets_PLB_MWrBTerm ( nfa_finals_buckets_PLB_MWrBTerm ),
.nfa_forward_buckets_MPLB_Clk ( nfa_forward_buckets_MPLB_Clk ),
.nfa_forward_buckets_MPLB_Rst ( nfa_forward_buckets_MPLB_Rst ),
.nfa_forward_buckets_M_request ( nfa_forward_buckets_M_request ),
.nfa_forward_buckets_M_priority ( nfa_forward_buckets_M_priority ),
.nfa_forward_buckets_M_busLock ( nfa_forward_buckets_M_busLock ),
.nfa_forward_buckets_M_RNW ( nfa_forward_buckets_M_RNW ),
.nfa_forward_buckets_M_BE ( nfa_forward_buckets_M_BE ),
.nfa_forward_buckets_M_MSize ( nfa_forward_buckets_M_MSize ),
.nfa_forward_buckets_M_size ( nfa_forward_buckets_M_size ),
.nfa_forward_buckets_M_type ( nfa_forward_buckets_M_type ),
.nfa_forward_buckets_M_TAttribute ( nfa_forward_buckets_M_TAttribute ),
.nfa_forward_buckets_M_lockErr ( nfa_forward_buckets_M_lockErr ),
.nfa_forward_buckets_M_abort ( nfa_forward_buckets_M_abort ),
.nfa_forward_buckets_M_UABus ( nfa_forward_buckets_M_UABus ),
.nfa_forward_buckets_M_ABus ( nfa_forward_buckets_M_ABus ),
.nfa_forward_buckets_M_wrDBus ( nfa_forward_buckets_M_wrDBus ),
.nfa_forward_buckets_M_wrBurst ( nfa_forward_buckets_M_wrBurst ),
.nfa_forward_buckets_M_rdBurst ( nfa_forward_buckets_M_rdBurst ),
.nfa_forward_buckets_PLB_MAddrAck ( nfa_forward_buckets_PLB_MAddrAck ),
.nfa_forward_buckets_PLB_MSSize ( nfa_forward_buckets_PLB_MSSize ),
.nfa_forward_buckets_PLB_MRearbitrate ( nfa_forward_buckets_PLB_MRearbitrate ),
.nfa_forward_buckets_PLB_MTimeout ( nfa_forward_buckets_PLB_MTimeout ),
.nfa_forward_buckets_PLB_MBusy ( nfa_forward_buckets_PLB_MBusy ),
.nfa_forward_buckets_PLB_MRdErr ( nfa_forward_buckets_PLB_MRdErr ),
.nfa_forward_buckets_PLB_MWrErr ( nfa_forward_buckets_PLB_MWrErr ),
.nfa_forward_buckets_PLB_MIRQ ( nfa_forward_buckets_PLB_MIRQ ),
.nfa_forward_buckets_PLB_MRdDBus ( nfa_forward_buckets_PLB_MRdDBus ),
.nfa_forward_buckets_PLB_MRdWdAddr ( nfa_forward_buckets_PLB_MRdWdAddr ),
.nfa_forward_buckets_PLB_MRdDAck ( nfa_forward_buckets_PLB_MRdDAck ),
.nfa_forward_buckets_PLB_MRdBTerm ( nfa_forward_buckets_PLB_MRdBTerm ),
.nfa_forward_buckets_PLB_MWrDAck ( nfa_forward_buckets_PLB_MWrDAck ),
.nfa_forward_buckets_PLB_MWrBTerm ( nfa_forward_buckets_PLB_MWrBTerm ),
.nfa_initials_buckets_MPLB_Clk ( nfa_initials_buckets_MPLB_Clk ),
.nfa_initials_buckets_MPLB_Rst ( nfa_initials_buckets_MPLB_Rst ),
.nfa_initials_buckets_M_request ( nfa_initials_buckets_M_request ),
.nfa_initials_buckets_M_priority ( nfa_initials_buckets_M_priority ),
.nfa_initials_buckets_M_busLock ( nfa_initials_buckets_M_busLock ),
.nfa_initials_buckets_M_RNW ( nfa_initials_buckets_M_RNW ),
.nfa_initials_buckets_M_BE ( nfa_initials_buckets_M_BE ),
.nfa_initials_buckets_M_MSize ( nfa_initials_buckets_M_MSize ),
.nfa_initials_buckets_M_size ( nfa_initials_buckets_M_size ),
.nfa_initials_buckets_M_type ( nfa_initials_buckets_M_type ),
.nfa_initials_buckets_M_TAttribute ( nfa_initials_buckets_M_TAttribute ),
.nfa_initials_buckets_M_lockErr ( nfa_initials_buckets_M_lockErr ),
.nfa_initials_buckets_M_abort ( nfa_initials_buckets_M_abort ),
.nfa_initials_buckets_M_UABus ( nfa_initials_buckets_M_UABus ),
.nfa_initials_buckets_M_ABus ( nfa_initials_buckets_M_ABus ),
.nfa_initials_buckets_M_wrDBus ( nfa_initials_buckets_M_wrDBus ),
.nfa_initials_buckets_M_wrBurst ( nfa_initials_buckets_M_wrBurst ),
.nfa_initials_buckets_M_rdBurst ( nfa_initials_buckets_M_rdBurst ),
.nfa_initials_buckets_PLB_MAddrAck ( nfa_initials_buckets_PLB_MAddrAck ),
.nfa_initials_buckets_PLB_MSSize ( nfa_initials_buckets_PLB_MSSize ),
.nfa_initials_buckets_PLB_MRearbitrate ( nfa_initials_buckets_PLB_MRearbitrate ),
.nfa_initials_buckets_PLB_MTimeout ( nfa_initials_buckets_PLB_MTimeout ),
.nfa_initials_buckets_PLB_MBusy ( nfa_initials_buckets_PLB_MBusy ),
.nfa_initials_buckets_PLB_MRdErr ( nfa_initials_buckets_PLB_MRdErr ),
.nfa_initials_buckets_PLB_MWrErr ( nfa_initials_buckets_PLB_MWrErr ),
.nfa_initials_buckets_PLB_MIRQ ( nfa_initials_buckets_PLB_MIRQ ),
.nfa_initials_buckets_PLB_MRdDBus ( nfa_initials_buckets_PLB_MRdDBus ),
.nfa_initials_buckets_PLB_MRdWdAddr ( nfa_initials_buckets_PLB_MRdWdAddr ),
.nfa_initials_buckets_PLB_MRdDAck ( nfa_initials_buckets_PLB_MRdDAck ),
.nfa_initials_buckets_PLB_MRdBTerm ( nfa_initials_buckets_PLB_MRdBTerm ),
.nfa_initials_buckets_PLB_MWrDAck ( nfa_initials_buckets_PLB_MWrDAck ),
.nfa_initials_buckets_PLB_MWrBTerm ( nfa_initials_buckets_PLB_MWrBTerm ),
.sample_buffer_MPLB_Clk ( sample_buffer_MPLB_Clk ),
.sample_buffer_MPLB_Rst ( sample_buffer_MPLB_Rst ),
.sample_buffer_M_request ( sample_buffer_M_request ),
.sample_buffer_M_priority ( sample_buffer_M_priority ),
.sample_buffer_M_busLock ( sample_buffer_M_busLock ),
.sample_buffer_M_RNW ( sample_buffer_M_RNW ),
.sample_buffer_M_BE ( sample_buffer_M_BE ),
.sample_buffer_M_MSize ( sample_buffer_M_MSize ),
.sample_buffer_M_size ( sample_buffer_M_size ),
.sample_buffer_M_type ( sample_buffer_M_type ),
.sample_buffer_M_TAttribute ( sample_buffer_M_TAttribute ),
.sample_buffer_M_lockErr ( sample_buffer_M_lockErr ),
.sample_buffer_M_abort ( sample_buffer_M_abort ),
.sample_buffer_M_UABus ( sample_buffer_M_UABus ),
.sample_buffer_M_ABus ( sample_buffer_M_ABus ),
.sample_buffer_M_wrDBus ( sample_buffer_M_wrDBus ),
.sample_buffer_M_wrBurst ( sample_buffer_M_wrBurst ),
.sample_buffer_M_rdBurst ( sample_buffer_M_rdBurst ),
.sample_buffer_PLB_MAddrAck ( sample_buffer_PLB_MAddrAck ),
.sample_buffer_PLB_MSSize ( sample_buffer_PLB_MSSize ),
.sample_buffer_PLB_MRearbitrate ( sample_buffer_PLB_MRearbitrate ),
.sample_buffer_PLB_MTimeout ( sample_buffer_PLB_MTimeout ),
.sample_buffer_PLB_MBusy ( sample_buffer_PLB_MBusy ),
.sample_buffer_PLB_MRdErr ( sample_buffer_PLB_MRdErr ),
.sample_buffer_PLB_MWrErr ( sample_buffer_PLB_MWrErr ),
.sample_buffer_PLB_MIRQ ( sample_buffer_PLB_MIRQ ),
.sample_buffer_PLB_MRdDBus ( sample_buffer_PLB_MRdDBus ),
.sample_buffer_PLB_MRdWdAddr ( sample_buffer_PLB_MRdWdAddr ),
.sample_buffer_PLB_MRdDAck ( sample_buffer_PLB_MRdDAck ),
.sample_buffer_PLB_MRdBTerm ( sample_buffer_PLB_MRdBTerm ),
.sample_buffer_PLB_MWrDAck ( sample_buffer_PLB_MWrDAck ),
.sample_buffer_PLB_MWrBTerm ( sample_buffer_PLB_MWrBTerm ),
.splb_slv0_SPLB_Clk ( splb_slv0_SPLB_Clk ),
.splb_slv0_SPLB_Rst ( splb_slv0_SPLB_Rst ),
.splb_slv0_PLB_ABus ( splb_slv0_PLB_ABus ),
.splb_slv0_PLB_UABus ( splb_slv0_PLB_UABus ),
.splb_slv0_PLB_PAValid ( splb_slv0_PLB_PAValid ),
.splb_slv0_PLB_SAValid ( splb_slv0_PLB_SAValid ),
.splb_slv0_PLB_rdPrim ( splb_slv0_PLB_rdPrim ),
.splb_slv0_PLB_wrPrim ( splb_slv0_PLB_wrPrim ),
.splb_slv0_PLB_masterID ( splb_slv0_PLB_masterID ),
.splb_slv0_PLB_abort ( splb_slv0_PLB_abort ),
.splb_slv0_PLB_busLock ( splb_slv0_PLB_busLock ),
.splb_slv0_PLB_RNW ( splb_slv0_PLB_RNW ),
.splb_slv0_PLB_BE ( splb_slv0_PLB_BE ),
.splb_slv0_PLB_MSize ( splb_slv0_PLB_MSize ),
.splb_slv0_PLB_size ( splb_slv0_PLB_size ),
.splb_slv0_PLB_type ( splb_slv0_PLB_type ),
.splb_slv0_PLB_lockErr ( splb_slv0_PLB_lockErr ),
.splb_slv0_PLB_wrDBus ( splb_slv0_PLB_wrDBus ),
.splb_slv0_PLB_wrBurst ( splb_slv0_PLB_wrBurst ),
.splb_slv0_PLB_rdBurst ( splb_slv0_PLB_rdBurst ),
.splb_slv0_PLB_wrPendReq ( splb_slv0_PLB_wrPendReq ),
.splb_slv0_PLB_rdPendReq ( splb_slv0_PLB_rdPendReq ),
.splb_slv0_PLB_wrPendPri ( splb_slv0_PLB_wrPendPri ),
.splb_slv0_PLB_rdPendPri ( splb_slv0_PLB_rdPendPri ),
.splb_slv0_PLB_reqPri ( splb_slv0_PLB_reqPri ),
.splb_slv0_PLB_TAttribute ( splb_slv0_PLB_TAttribute ),
.splb_slv0_Sl_addrAck ( splb_slv0_Sl_addrAck ),
.splb_slv0_Sl_SSize ( splb_slv0_Sl_SSize ),
.splb_slv0_Sl_wait ( splb_slv0_Sl_wait ),
.splb_slv0_Sl_rearbitrate ( splb_slv0_Sl_rearbitrate ),
.splb_slv0_Sl_wrDAck ( splb_slv0_Sl_wrDAck ),
.splb_slv0_Sl_wrComp ( splb_slv0_Sl_wrComp ),
.splb_slv0_Sl_wrBTerm ( splb_slv0_Sl_wrBTerm ),
.splb_slv0_Sl_rdDBus ( splb_slv0_Sl_rdDBus ),
.splb_slv0_Sl_rdWdAddr ( splb_slv0_Sl_rdWdAddr ),
.splb_slv0_Sl_rdDAck ( splb_slv0_Sl_rdDAck ),
.splb_slv0_Sl_rdComp ( splb_slv0_Sl_rdComp ),
.splb_slv0_Sl_rdBTerm ( splb_slv0_Sl_rdBTerm ),
.splb_slv0_Sl_MBusy ( splb_slv0_Sl_MBusy ),
.splb_slv0_Sl_MWrErr ( splb_slv0_Sl_MWrErr ),
.splb_slv0_Sl_MRdErr ( splb_slv0_Sl_MRdErr ),
.splb_slv0_Sl_MIRQ ( splb_slv0_Sl_MIRQ )
);
endmodule
|
// File: DEMUX1_4_DMS_TBV.v
// Generated by MyHDL 0.10
// Date: Sun Sep 23 18:24:21 2018
`timescale 1ns/10ps
module DEMUX1_4_DMS_TBV (
);
// myHDL -> testbench for module `DEMUX1_4_DMS`
reg x = 0;
wire y0;
wire y1;
reg s0 = 0;
reg s1 = 0;
wire y2;
wire y3;
wire [17:0] xTV;
wire [17:0] s0TV;
wire [17:0] s1TV;
wire DEMUX1_4_DMS0_0_s0_y2y3_WIRE;
wire DEMUX1_4_DMS0_0_s0_y0y1_WIRE;
assign xTV = 18'd87399;
assign s0TV = 18'd52982;
assign s1TV = 18'd16277;
always @(x, y0, s1, s0, y3, y2, y1) begin: DEMUX1_4_DMS_TBV_PRINT_DATA
$write("%h", x);
$write(" ");
$write("%h", s0);
$write(" ");
$write("%h", s1);
$write(" ");
$write("%h", y0);
$write(" ");
$write("%h", y1);
$write(" ");
$write("%h", y2);
$write(" ");
$write("%h", y3);
$write("\n");
end
assign DEMUX1_4_DMS0_0_s0_y0y1_WIRE = ((!s1) && x);
assign DEMUX1_4_DMS0_0_s0_y2y3_WIRE = (s1 && x);
assign y0 = ((!s0) && DEMUX1_4_DMS0_0_s0_y0y1_WIRE);
assign y1 = (s0 && DEMUX1_4_DMS0_0_s0_y0y1_WIRE);
assign y2 = ((!s0) && DEMUX1_4_DMS0_0_s0_y2y3_WIRE);
assign y3 = (s0 && DEMUX1_4_DMS0_0_s0_y2y3_WIRE);
initial begin: DEMUX1_4_DMS_TBV_STIMULES
integer i;
for (i=0; i<18; i=i+1) begin
x <= xTV[i];
s0 <= s0TV[i];
s1 <= s1TV[i];
# 1;
end
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-----------------------------------------------------------------------------------------------------------------------------
// Filename : cabac_binarization.v
// Author : chewein
// Created : 2014-9-9
// Description : syntax element binarization
//
// $Id$
//-----------------------------------------------------------------------------------------------------------------------------
`include "enc_defines.v"
module cabac_binarization(
//input
clk ,
rst_n ,
cabac_start_i ,
slice_type_i ,
mb_x_total_i ,
mb_y_total_i ,
mb_x_i ,
mb_y_i ,
param_qp_i ,// QP
sao_i ,
luma_mode_i ,
chroma_mode_i ,
inter_cu_part_size_i ,
merge_flag_i ,
merge_idx_i ,
cu_split_flag_i ,
cu_skip_flag_i ,
luma_cbf_i ,
cr_cbf_i ,
cb_cbf_i ,
lcu_qp_i ,
cu_mvd_i ,
// mvd_idx_i ,
coeff_data_i ,
table_build_end_i ,
no_bit_flag_i ,
//output
slice_init_flag_o ,
cu_luma_mode_ren_o ,
cu_luma_mode_raddr_o ,
cu_chroma_mode_ren_o ,
cu_chroma_mode_raddr_o ,
cu_mvd_ren_o ,
cu_mvd_raddr_o ,
cu_coeff_raddr_o ,
cu_coeff_ren_o ,
cabac_mb_done_o ,
cabac_slice_done_o ,
coeff_type_o ,
binary_pair_0_o ,
binary_pair_1_o ,
binary_pair_2_o ,
binary_pair_3_o ,
binary_pair_valid_num_o ,
cabac_curr_state_o
);
// -----------------------------------------------------------------------------------------------------------------------------
//
// INPUT and OUTPUT DECLARATION
//
// -----------------------------------------------------------------------------------------------------------------------------
//ctrl info
input clk ; // clock signal
input rst_n ; // reset signal, low active
input cabac_start_i ; // cabac start signal, pulse signal
input slice_type_i ; // slice type, (`SLICE_TYPE_I):1, (`SLICE_TYPE_P):0
input [(`PIC_X_WIDTH)-1:0] mb_x_total_i ; // mb_x_total_i
input [(`PIC_Y_WIDTH)-1:0] mb_y_total_i ; // mb_y_total_i
input [(`PIC_X_WIDTH)-1:0] mb_x_i ; // mb_x_i
input [(`PIC_Y_WIDTH)-1:0] mb_y_i ; // mb_y_i
input [5:0] param_qp_i ; // QP
// sao IF
input [61:0] sao_i ; // {merge_top,merge_left,{sao_type,sao_subIdx,sao_offsetx4}{chroma,luma}}
//intra info
input [23:0] luma_mode_i ; // intra luma mode , 6 bits for each 8x8 cu in z-scan , 64x64 = [5:0]
input [23:0] chroma_mode_i ; // intra luma mode , 6 bits for each 4x4 cu in z-scan , the first 4x4 cu is [1535:1531]
//inter info
input [(`INTER_CU_INFO_LEN)-1:0] inter_cu_part_size_i ; // inter partition size ,INTER_CU_INFO_LEN = 170
input [ 84:0] merge_flag_i ;
input [255:0] merge_idx_i ;
// split and skip info
input [84:0] cu_split_flag_i ; // cu split flag,[0]:64x64, [1:4]:32x32, [5:20]:16x16,[6:84]:8x8 , if not split into 8x8 , should be equal zero , cu_luma_mode_left_0_w
input [84:0] cu_skip_flag_i ; // cu skip flag,[0]:64x64, [1:4]:32x32, [5:20]:16x16,[6:84]:8x8
// cbf info
input [`LCU_SIZE*`LCU_SIZE/16-1:0] luma_cbf_i ; // z-scan, reverse order , 256 bits , [0] is the last 4x4 cu ,[255] is the first 4x4 cu
input [`LCU_SIZE*`LCU_SIZE/16-1:0] cr_cbf_i ; // z-scan, reverse order , 64 bits ,
input [`LCU_SIZE*`LCU_SIZE/16-1:0] cb_cbf_i ; // z-scan, reverse order , 64 bits ,
input [ 5:0] lcu_qp_i ; // lcu of qp
// mvd and coeff
input [(2*`MVD_WIDTH) :0] cu_mvd_i ; // // {mvd_idx,mvd_x & mvd_y} , FMV_WIDTH = 10
//input [383:0] mvd_idx_i ;
input [255:0] coeff_data_i ; // coeff data of a 4x4 block,a coeff is 16 bits
// controller signals
input table_build_end_i ; // table build end flag
input no_bit_flag_i ;
output slice_init_flag_o ; // slice init flag
output cu_luma_mode_ren_o ;
output [ 5:0] cu_luma_mode_raddr_o ;
output cu_chroma_mode_ren_o ;
output [ 3:0] cu_chroma_mode_raddr_o ;
output cu_mvd_ren_o ;
output [ 5:0] cu_mvd_raddr_o ; // address of inter mvd
output cu_coeff_ren_o ; // read coefficient enable
output [ 8:0] cu_coeff_raddr_o ; // address of coefficient
output cabac_mb_done_o ; // LCU done flag
output cabac_slice_done_o ; // slice done flag
output [1:0] coeff_type_o ;
output [10:0] binary_pair_0_o ; // binary pair {coding_mode , bin , ctx_idx(xxx_xxxxxx)}
output [10:0] binary_pair_1_o ; // binary pair {coding_mode , bin , ctx_idx(xxx_xxxxxx)}
output [10:0] binary_pair_2_o ; // binary pair {coding_mode , bin , ctx_idx(xxx_xxxxxx)}
output [10:0] binary_pair_3_o ; // binary pair {coding_mode , bin , ctx_idx(xxx_xxxxxx)}
output [2:0] binary_pair_valid_num_o;
output [3:0] cabac_curr_state_o ;
reg [10:0] binary_pair_0_o ;
reg [10:0] binary_pair_1_o ;
reg [10:0] binary_pair_2_o ;
reg [10:0] binary_pair_3_o ;
reg [2:0] binary_pair_valid_num_o;
reg slice_init_flag_o ; // slice init flag
reg cu_luma_mode_ren_o ;
reg [ 5:0] cu_luma_mode_raddr_o ;
reg cu_chroma_mode_ren_o ;
reg [ 3:0] cu_chroma_mode_raddr_o ;
// -----------------------------------------------------------------------------------------------------------------------------
//
// parameter declaration
//
// -----------------------------------------------------------------------------------------------------------------------------
parameter CU_64x64 = 4'd0 ,
CU_32x32 = 4'd1 ,
CU_16x16 = 4'd2 ,
CU_8x8 = 4'd3 ,
LCU_IDLE = 4'd4 ,
CU_SPLIT = 4'd5 ,
LCU_END = 4'd6 ,
LCU_INIT = 4'd7 ,
LCU_SAO = 4'd8 ;
// -----------------------------------------------------------------------------------------------------------------------------
//
// wire declaration
//
// -----------------------------------------------------------------------------------------------------------------------------
wire cu_done_w ;
// for an cu
wire cu_start_w ;
wire [6:0] cu_idx_w ;
wire [1:0] cu_depth_w ; // 0:64x64 1:32x32 2:16x16 3:8x8
wire cu_sub_div_w ; // 1 bit for a cu , 1: split but not encoding, 0: not split but encoding
wire cu_slice_type_w ; // 1 bit for a cu , 1: I ,0:P
wire cu_skip_flag_w ;
wire [ 1:0] cu_inter_part_mode_w ; // 2 bit for a cu , 8x8 cu only support 2Nx2N
wire [ 3:0] cu_merge_flag_w ; // 1 bit for a cu
wire [15:0] cu_merge_idx_w ; // 4 bit for a cu
wire [23:0] cu_luma_pred_mode_w ; // 6 bits for a 8x8 cu
wire [ 5:0] cu_chroma_pred_mode_w ; // 6 bits for a 8x8 cu
wire [ 3:0] cu_cbf_y_w ; // z-scan for sub cu ,[3] is the first sub cu
wire [ 3:0] cu_cbf_u_w ; // z-scan for sub cu ,[3] is the first sub cu
wire [ 3:0] cu_cbf_v_w ; // z-scan for sub cu ,[3] is the first sub cu
wire [5:0] cu_qp_curr_w ;
wire last_cu_flag_w ;
// top and left data
wire [1:0] cu_depth_left_w ;
wire [1:0] cu_depth_top_w ;
wire cu_skip_top_flag_w ;
wire cu_skip_left_flag_w ;
wire [23:0] cu_luma_pred_top_mode_w ;
wire [23:0] cu_luma_pred_left_mode_w ;
wire [5:0] cu_qp_last_w ;
wire cu_qp_nocoded_w ;
// mvd data
reg [(4*`MVD_WIDTH+5):0] mb_mvd_rdata_r ; // Inter mvd read data
// coeff data
wire [1:0] coeff_type_w ;
wire [`COEFF_WIDTH*16-1:0] tq_rdata_w ; // coeff data tq read data
wire tq_ren_w ; // read coefficient enable
wire [ 8:0] tq_raddr_w ; // address of coefficient
wire cu_qp_coded_flag_w ;
wire [10:0] cu_binary_pair_0_w ;
wire [10:0] cu_binary_pair_1_w ;
wire [10:0] cu_binary_pair_2_w ;
wire [10:0] cu_binary_pair_3_w ;
wire [ 2:0] cu_binary_pair_valid_num_w ;
// -----------------------------------------------------------------------------------------------------------------------------
//
// reg declaration : calculation cu address
//
// -----------------------------------------------------------------------------------------------------------------------------
reg [3:0] lcu_curr_state_r ;
reg [3:0] lcu_next_state_r ;
reg cu_done_r ;
reg [6:0] cu_idx_r ;
reg cu_split_flag_r ;
reg [1:0] cu_depth_r ;
wire [6:0] cu_idx_minus1_w ; // cu index minus 1
wire [6:0] cu_idx_minus5_w ; // cu index minus 5
wire [6:0] cu_idx_minus21_w ; // cu index minus 21
wire [6:0] cu_idx_plus1_w ; // cu index plus 1
wire [6:0] cu_idx_deep_plus1_w ; // cu index of deep depth plus 1
wire [6:0] cu_idx_shift1_w ; // cu_idx_r << 1;
wire [6:0] cu_idx_shift1_plus1_w ; // (cu_idx_r<<1)+1
assign cu_idx_minus1_w = cu_idx_r - 7'd1 ;
assign cu_idx_minus5_w = cu_idx_r - 7'd5 ;
assign cu_idx_minus21_w = cu_idx_r - 7'd21 ;
assign cu_idx_plus1_w = cu_idx_r + 7'd1 ;
assign cu_idx_deep_plus1_w = (cu_idx_r<<2) + 7'd1 ;
assign cu_idx_shift1_w = cu_idx_r << 1 ;
assign cu_idx_shift1_plus1_w = cu_idx_shift1_w + 7'd1 ;
// cu_done_r
always @* begin
case(lcu_curr_state_r)
LCU_IDLE: cu_done_r = 1'd0 ;
CU_SPLIT: cu_done_r = 1'd1 ;
CU_64x64,
CU_32x32,
CU_16x16,
CU_8x8 : cu_done_r = cu_done_w ;
LCU_END : cu_done_r = 1'd0 ;
default : cu_done_r = 1'd0 ;
endcase
end
// cu_idx_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
cu_idx_r <= 0;
else if(cu_done_r) begin
if(lcu_curr_state_r==CU_SPLIT) begin
if(cu_split_flag_r)
cu_idx_r <= cu_idx_deep_plus1_w;
else
cu_idx_r <= cu_idx_r;
end
else begin
case(cu_depth_r)
2'b00: begin
cu_idx_r <= 'd0;
end
2'b01: begin
if(cu_idx_minus1_w[1:0]==2'd3)
cu_idx_r <= 'd0;
else
cu_idx_r <= cu_idx_plus1_w;
end
2'b10: begin
if(cu_idx_minus5_w[3:0]=='d15)
cu_idx_r <= 'd0;
else if(cu_idx_minus5_w[1:0]==2'd3) begin
cu_idx_r <= (cu_idx_r >> 2);
end
else begin
cu_idx_r <= cu_idx_plus1_w;
end
end
2'b11: begin
if(cu_idx_minus21_w[5:0]==6'd63)
cu_idx_r <= 'd0;
else if(cu_idx_minus21_w[3:0]==4'd15)
cu_idx_r <= (cu_idx_minus21_w >> 4) + 'd2;
else if(cu_idx_minus21_w[1:0]==2'd3)
cu_idx_r <= (cu_idx_minus21_w >> 2) + 'd6;
else
cu_idx_r <= cu_idx_plus1_w;
end
endcase
end
end
else begin
cu_idx_r <= cu_idx_r;
end
end
// cu_split_flag_r
always @* begin
if(slice_type_i) begin
case(cu_idx_r)
7'd0 : cu_split_flag_r = cu_split_flag_i[0 ];
7'd1 : cu_split_flag_r = cu_split_flag_i[1 ];
7'd2 : cu_split_flag_r = cu_split_flag_i[2 ];
7'd3 : cu_split_flag_r = cu_split_flag_i[3 ];
7'd4 : cu_split_flag_r = cu_split_flag_i[4 ];
7'd5 : cu_split_flag_r = cu_split_flag_i[5 ];
7'd6 : cu_split_flag_r = cu_split_flag_i[6 ];
7'd7 : cu_split_flag_r = cu_split_flag_i[7 ];
7'd8 : cu_split_flag_r = cu_split_flag_i[8 ];
7'd9 : cu_split_flag_r = cu_split_flag_i[9 ];
7'd10 : cu_split_flag_r = cu_split_flag_i[10];
7'd11 : cu_split_flag_r = cu_split_flag_i[11];
7'd12 : cu_split_flag_r = cu_split_flag_i[12];
7'd13 : cu_split_flag_r = cu_split_flag_i[13];
7'd14 : cu_split_flag_r = cu_split_flag_i[14];
7'd15 : cu_split_flag_r = cu_split_flag_i[15];
7'd16 : cu_split_flag_r = cu_split_flag_i[16];
7'd17 : cu_split_flag_r = cu_split_flag_i[17];
7'd18 : cu_split_flag_r = cu_split_flag_i[18];
7'd19 : cu_split_flag_r = cu_split_flag_i[19];
7'd20 : cu_split_flag_r = cu_split_flag_i[20];
7'd21 : cu_split_flag_r = cu_split_flag_i[21];
7'd22 : cu_split_flag_r = cu_split_flag_i[22];
7'd23 : cu_split_flag_r = cu_split_flag_i[23];
7'd24 : cu_split_flag_r = cu_split_flag_i[24];
7'd25 : cu_split_flag_r = cu_split_flag_i[25];
7'd26 : cu_split_flag_r = cu_split_flag_i[26];
7'd27 : cu_split_flag_r = cu_split_flag_i[27];
7'd28 : cu_split_flag_r = cu_split_flag_i[28];
7'd29 : cu_split_flag_r = cu_split_flag_i[29];
7'd30 : cu_split_flag_r = cu_split_flag_i[30];
7'd31 : cu_split_flag_r = cu_split_flag_i[31];
7'd32 : cu_split_flag_r = cu_split_flag_i[32];
7'd33 : cu_split_flag_r = cu_split_flag_i[33];
7'd34 : cu_split_flag_r = cu_split_flag_i[34];
7'd35 : cu_split_flag_r = cu_split_flag_i[35];
7'd36 : cu_split_flag_r = cu_split_flag_i[36];
7'd37 : cu_split_flag_r = cu_split_flag_i[37];
7'd38 : cu_split_flag_r = cu_split_flag_i[38];
7'd39 : cu_split_flag_r = cu_split_flag_i[39];
7'd40 : cu_split_flag_r = cu_split_flag_i[40];
7'd41 : cu_split_flag_r = cu_split_flag_i[41];
7'd42 : cu_split_flag_r = cu_split_flag_i[42];
7'd43 : cu_split_flag_r = cu_split_flag_i[43];
7'd44 : cu_split_flag_r = cu_split_flag_i[44];
7'd45 : cu_split_flag_r = cu_split_flag_i[45];
7'd46 : cu_split_flag_r = cu_split_flag_i[46];
7'd47 : cu_split_flag_r = cu_split_flag_i[47];
7'd48 : cu_split_flag_r = cu_split_flag_i[48];
7'd49 : cu_split_flag_r = cu_split_flag_i[49];
7'd50 : cu_split_flag_r = cu_split_flag_i[50];
7'd51 : cu_split_flag_r = cu_split_flag_i[51];
7'd52 : cu_split_flag_r = cu_split_flag_i[52];
7'd53 : cu_split_flag_r = cu_split_flag_i[53];
7'd54 : cu_split_flag_r = cu_split_flag_i[54];
7'd55 : cu_split_flag_r = cu_split_flag_i[55];
7'd56 : cu_split_flag_r = cu_split_flag_i[56];
7'd57 : cu_split_flag_r = cu_split_flag_i[57];
7'd58 : cu_split_flag_r = cu_split_flag_i[58];
7'd59 : cu_split_flag_r = cu_split_flag_i[59];
7'd60 : cu_split_flag_r = cu_split_flag_i[60];
7'd61 : cu_split_flag_r = cu_split_flag_i[61];
7'd62 : cu_split_flag_r = cu_split_flag_i[62];
7'd63 : cu_split_flag_r = cu_split_flag_i[63];
7'd64 : cu_split_flag_r = cu_split_flag_i[64];
7'd65 : cu_split_flag_r = cu_split_flag_i[65];
7'd66 : cu_split_flag_r = cu_split_flag_i[66];
7'd67 : cu_split_flag_r = cu_split_flag_i[67];
7'd68 : cu_split_flag_r = cu_split_flag_i[68];
7'd69 : cu_split_flag_r = cu_split_flag_i[69];
7'd70 : cu_split_flag_r = cu_split_flag_i[70];
7'd71 : cu_split_flag_r = cu_split_flag_i[71];
7'd72 : cu_split_flag_r = cu_split_flag_i[72];
7'd73 : cu_split_flag_r = cu_split_flag_i[73];
7'd74 : cu_split_flag_r = cu_split_flag_i[74];
7'd75 : cu_split_flag_r = cu_split_flag_i[75];
7'd76 : cu_split_flag_r = cu_split_flag_i[76];
7'd77 : cu_split_flag_r = cu_split_flag_i[77];
7'd78 : cu_split_flag_r = cu_split_flag_i[78];
7'd79 : cu_split_flag_r = cu_split_flag_i[79];
7'd80 : cu_split_flag_r = cu_split_flag_i[80];
7'd81 : cu_split_flag_r = cu_split_flag_i[81];
7'd82 : cu_split_flag_r = cu_split_flag_i[82];
7'd83 : cu_split_flag_r = cu_split_flag_i[83];
7'd84 : cu_split_flag_r = cu_split_flag_i[84];
default : cu_split_flag_r = 1'b0 ;
endcase
end
else begin
case(cu_idx_r)
7'd0 : cu_split_flag_r = (inter_cu_part_size_i[ 1:0 ]==2'd3 ) ;
7'd1 : cu_split_flag_r = (inter_cu_part_size_i[ 3:2 ]==2'd3 ) ;
7'd2 : cu_split_flag_r = (inter_cu_part_size_i[ 5:4 ]==2'd3 ) ;
7'd3 : cu_split_flag_r = (inter_cu_part_size_i[ 7:6 ]==2'd3 ) ;
7'd4 : cu_split_flag_r = (inter_cu_part_size_i[ 9:8 ]==2'd3 ) ;
7'd5 : cu_split_flag_r = (inter_cu_part_size_i[ 11:10 ]==2'd3 ) ;
7'd6 : cu_split_flag_r = (inter_cu_part_size_i[ 13:12 ]==2'd3 ) ;
7'd7 : cu_split_flag_r = (inter_cu_part_size_i[ 15:14 ]==2'd3 ) ;
7'd8 : cu_split_flag_r = (inter_cu_part_size_i[ 17:16 ]==2'd3 ) ;
7'd9 : cu_split_flag_r = (inter_cu_part_size_i[ 19:18 ]==2'd3 ) ;
7'd10 : cu_split_flag_r = (inter_cu_part_size_i[ 21:20 ]==2'd3 ) ;
7'd11 : cu_split_flag_r = (inter_cu_part_size_i[ 23:22 ]==2'd3 ) ;
7'd12 : cu_split_flag_r = (inter_cu_part_size_i[ 25:24 ]==2'd3 ) ;
7'd13 : cu_split_flag_r = (inter_cu_part_size_i[ 27:26 ]==2'd3 ) ;
7'd14 : cu_split_flag_r = (inter_cu_part_size_i[ 29:28 ]==2'd3 ) ;
7'd15 : cu_split_flag_r = (inter_cu_part_size_i[ 31:30 ]==2'd3 ) ;
7'd16 : cu_split_flag_r = (inter_cu_part_size_i[ 33:32 ]==2'd3 ) ;
7'd17 : cu_split_flag_r = (inter_cu_part_size_i[ 35:34 ]==2'd3 ) ;
7'd18 : cu_split_flag_r = (inter_cu_part_size_i[ 37:36 ]==2'd3 ) ;
7'd19 : cu_split_flag_r = (inter_cu_part_size_i[ 39:38 ]==2'd3 ) ;
7'd20 : cu_split_flag_r = (inter_cu_part_size_i[ 41:40 ]==2'd3 ) ;
7'd21 : cu_split_flag_r = (inter_cu_part_size_i[ 43:42 ]==2'd3 ) ;
7'd22 : cu_split_flag_r = (inter_cu_part_size_i[ 45:44 ]==2'd3 ) ;
7'd23 : cu_split_flag_r = (inter_cu_part_size_i[ 47:46 ]==2'd3 ) ;
7'd24 : cu_split_flag_r = (inter_cu_part_size_i[ 49:48 ]==2'd3 ) ;
7'd25 : cu_split_flag_r = (inter_cu_part_size_i[ 51:50 ]==2'd3 ) ;
7'd26 : cu_split_flag_r = (inter_cu_part_size_i[ 53:52 ]==2'd3 ) ;
7'd27 : cu_split_flag_r = (inter_cu_part_size_i[ 55:54 ]==2'd3 ) ;
7'd28 : cu_split_flag_r = (inter_cu_part_size_i[ 57:56 ]==2'd3 ) ;
7'd29 : cu_split_flag_r = (inter_cu_part_size_i[ 59:58 ]==2'd3 ) ;
7'd30 : cu_split_flag_r = (inter_cu_part_size_i[ 61:60 ]==2'd3 ) ;
7'd31 : cu_split_flag_r = (inter_cu_part_size_i[ 63:62 ]==2'd3 ) ;
7'd32 : cu_split_flag_r = (inter_cu_part_size_i[ 65:64 ]==2'd3 ) ;
7'd33 : cu_split_flag_r = (inter_cu_part_size_i[ 67:66 ]==2'd3 ) ;
7'd34 : cu_split_flag_r = (inter_cu_part_size_i[ 69:68 ]==2'd3 ) ;
7'd35 : cu_split_flag_r = (inter_cu_part_size_i[ 71:70 ]==2'd3 ) ;
7'd36 : cu_split_flag_r = (inter_cu_part_size_i[ 73:72 ]==2'd3 ) ;
7'd37 : cu_split_flag_r = (inter_cu_part_size_i[ 75:74 ]==2'd3 ) ;
7'd38 : cu_split_flag_r = (inter_cu_part_size_i[ 77:76 ]==2'd3 ) ;
7'd39 : cu_split_flag_r = (inter_cu_part_size_i[ 79:78 ]==2'd3 ) ;
7'd40 : cu_split_flag_r = (inter_cu_part_size_i[ 81:80 ]==2'd3 ) ;
7'd41 : cu_split_flag_r = (inter_cu_part_size_i[ 83:82 ]==2'd3 ) ;
7'd42 : cu_split_flag_r = (inter_cu_part_size_i[ 85:84 ]==2'd3 ) ;
7'd43 : cu_split_flag_r = (inter_cu_part_size_i[ 87:86 ]==2'd3 ) ;
7'd44 : cu_split_flag_r = (inter_cu_part_size_i[ 89:88 ]==2'd3 ) ;
7'd45 : cu_split_flag_r = (inter_cu_part_size_i[ 91:90 ]==2'd3 ) ;
7'd46 : cu_split_flag_r = (inter_cu_part_size_i[ 93:92 ]==2'd3 ) ;
7'd47 : cu_split_flag_r = (inter_cu_part_size_i[ 95:94 ]==2'd3 ) ;
7'd48 : cu_split_flag_r = (inter_cu_part_size_i[ 97:96 ]==2'd3 ) ;
7'd49 : cu_split_flag_r = (inter_cu_part_size_i[ 99:98 ]==2'd3 ) ;
7'd50 : cu_split_flag_r = (inter_cu_part_size_i[101:100]==2'd3 ) ;
7'd51 : cu_split_flag_r = (inter_cu_part_size_i[103:102]==2'd3 ) ;
7'd52 : cu_split_flag_r = (inter_cu_part_size_i[105:104]==2'd3 ) ;
7'd53 : cu_split_flag_r = (inter_cu_part_size_i[107:106]==2'd3 ) ;
7'd54 : cu_split_flag_r = (inter_cu_part_size_i[109:108]==2'd3 ) ;
7'd55 : cu_split_flag_r = (inter_cu_part_size_i[111:110]==2'd3 ) ;
7'd56 : cu_split_flag_r = (inter_cu_part_size_i[113:112]==2'd3 ) ;
7'd57 : cu_split_flag_r = (inter_cu_part_size_i[115:114]==2'd3 ) ;
7'd58 : cu_split_flag_r = (inter_cu_part_size_i[117:116]==2'd3 ) ;
7'd59 : cu_split_flag_r = (inter_cu_part_size_i[119:118]==2'd3 ) ;
7'd60 : cu_split_flag_r = (inter_cu_part_size_i[121:120]==2'd3 ) ;
7'd61 : cu_split_flag_r = (inter_cu_part_size_i[123:122]==2'd3 ) ;
7'd62 : cu_split_flag_r = (inter_cu_part_size_i[125:124]==2'd3 ) ;
7'd63 : cu_split_flag_r = (inter_cu_part_size_i[127:126]==2'd3 ) ;
7'd64 : cu_split_flag_r = (inter_cu_part_size_i[129:128]==2'd3 ) ;
7'd65 : cu_split_flag_r = (inter_cu_part_size_i[131:130]==2'd3 ) ;
7'd66 : cu_split_flag_r = (inter_cu_part_size_i[133:132]==2'd3 ) ;
7'd67 : cu_split_flag_r = (inter_cu_part_size_i[135:134]==2'd3 ) ;
7'd68 : cu_split_flag_r = (inter_cu_part_size_i[137:136]==2'd3 ) ;
7'd69 : cu_split_flag_r = (inter_cu_part_size_i[139:138]==2'd3 ) ;
7'd70 : cu_split_flag_r = (inter_cu_part_size_i[141:140]==2'd3 ) ;
7'd71 : cu_split_flag_r = (inter_cu_part_size_i[143:142]==2'd3 ) ;
7'd72 : cu_split_flag_r = (inter_cu_part_size_i[145:144]==2'd3 ) ;
7'd73 : cu_split_flag_r = (inter_cu_part_size_i[147:146]==2'd3 ) ;
7'd74 : cu_split_flag_r = (inter_cu_part_size_i[149:148]==2'd3 ) ;
7'd75 : cu_split_flag_r = (inter_cu_part_size_i[151:150]==2'd3 ) ;
7'd76 : cu_split_flag_r = (inter_cu_part_size_i[153:152]==2'd3 ) ;
7'd77 : cu_split_flag_r = (inter_cu_part_size_i[155:154]==2'd3 ) ;
7'd78 : cu_split_flag_r = (inter_cu_part_size_i[157:156]==2'd3 ) ;
7'd79 : cu_split_flag_r = (inter_cu_part_size_i[159:158]==2'd3 ) ;
7'd80 : cu_split_flag_r = (inter_cu_part_size_i[161:160]==2'd3 ) ;
7'd81 : cu_split_flag_r = (inter_cu_part_size_i[163:162]==2'd3 ) ;
7'd82 : cu_split_flag_r = (inter_cu_part_size_i[165:164]==2'd3 ) ;
7'd83 : cu_split_flag_r = (inter_cu_part_size_i[167:166]==2'd3 ) ;
7'd84 : cu_split_flag_r = (inter_cu_part_size_i[169:168]==2'd3 ) ;
default : cu_split_flag_r = 1'b0 ;
endcase
end
end
// cu_depth_r
always @* begin
if(cu_idx_r=='d0) // cu_idx_r = 0
cu_depth_r = 2'd0;
else if(cu_idx_minus1_w[6:2]=='d0) // cu_idx_r = 4 3 2 1
cu_depth_r = 2'd1;
else if(cu_idx_minus5_w[6:4]=='d0) // cu_idx_r = 20 ...5
cu_depth_r = 2'd2;
else
cu_depth_r = 2'd3;
end
// -----------------------------------------------------------------------------------------------------------------------------
//
// calculation fsm controller signals
//
// -----------------------------------------------------------------------------------------------------------------------------
reg [2:0] lcu_cyc_cnt_r ;
reg lcu_done_r ;
reg cabac_slice_done_r ;
// lcu_cyc_cnt_r delay 8 cycles
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
lcu_cyc_cnt_r <= 3'd0 ;
else if(lcu_curr_state_r==LCU_SAO)
lcu_cyc_cnt_r <= lcu_cyc_cnt_r + 1'b1;
else if (lcu_curr_state_r!=LCU_END)
lcu_cyc_cnt_r <= 3'd0 ;
else if(lcu_cyc_cnt_r==3'd7)
lcu_cyc_cnt_r <= 3'd0 ;
else
lcu_cyc_cnt_r <= lcu_cyc_cnt_r + 1'd1;
end
// lcu_done_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
lcu_done_r <= 1'b0 ;
else if(lcu_curr_state_r==LCU_END && lcu_cyc_cnt_r==3'd7)
lcu_done_r <= 1'b1;
else
lcu_done_r <= 1'b0;
end
// cabac_slice_done_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cabac_slice_done_r <= 1'b0 ;
else if(mb_x_i == mb_x_total_i && mb_y_i == mb_y_total_i && lcu_done_r)
cabac_slice_done_r <= 1'b1 ;
else
cabac_slice_done_r <= 1'b0 ;
end
// -----------------------------------------------------------------------------------------------------------------------------
//
// top fsm
//
// -----------------------------------------------------------------------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
lcu_curr_state_r <= LCU_IDLE ;
else
lcu_curr_state_r <= lcu_next_state_r;
end
// LCU next state
always @* begin
lcu_next_state_r = LCU_IDLE;
case(lcu_curr_state_r)
LCU_IDLE: begin
if(cabac_start_i&&mb_x_i==`PIC_X_WIDTH'd0 && mb_y_i==`PIC_X_WIDTH'd0)
lcu_next_state_r = LCU_INIT;
else if(cabac_start_i)begin
if(`SAO_OPEN==1)
lcu_next_state_r = LCU_SAO ;//CU_SPLIT;
else
lcu_next_state_r = CU_SPLIT;//CU_SPLIT;
end
else
lcu_next_state_r = LCU_IDLE;
end
LCU_INIT: begin
if(table_build_end_i)begin
if(`SAO_OPEN==1)
lcu_next_state_r = LCU_SAO ;//CU_SPLIT;
else
lcu_next_state_r = CU_SPLIT;//CU_SPLIT;
end
else
lcu_next_state_r = LCU_INIT;
end
LCU_SAO:begin
if(lcu_cyc_cnt_r==3'd6)
lcu_next_state_r = CU_SPLIT ;
else
lcu_next_state_r = LCU_SAO ;
end
CU_SPLIT: begin
case(cu_depth_r)
2'b00: begin //64x64
if(cu_split_flag_r)
lcu_next_state_r = CU_SPLIT;
else
lcu_next_state_r = CU_64x64;
end
2'b01: begin //32x32
if(cu_split_flag_r)
lcu_next_state_r = CU_SPLIT;
else
lcu_next_state_r = CU_32x32;
end
2'b10: begin //16x16
if(cu_split_flag_r)
lcu_next_state_r = CU_8x8 ;
else
lcu_next_state_r = CU_16x16;
end
2'b11: begin //8x8
lcu_next_state_r = CU_8x8;
end
endcase
end
CU_64x64: begin
if(cu_done_r)
lcu_next_state_r = LCU_END;
else
lcu_next_state_r = CU_64x64;
end
CU_32x32: begin
if(cu_done_r) begin
if(cu_idx_r==7'd4)
lcu_next_state_r = LCU_END;
else
lcu_next_state_r = CU_SPLIT;
end
else
lcu_next_state_r = CU_32x32 ;
end
CU_16x16: begin
if(cu_done_r) begin
if(cu_idx_r==7'd20)
lcu_next_state_r = LCU_END;
else
lcu_next_state_r = CU_SPLIT;
end
else
lcu_next_state_r = CU_16x16 ;
end
CU_8x8: begin
if(cu_done_r) begin
if(cu_idx_r==7'd84)
lcu_next_state_r = LCU_END;
else if(cu_idx_minus21_w[1:0]==2'd3)
lcu_next_state_r = CU_SPLIT;
else
lcu_next_state_r = CU_8x8;
end
else
lcu_next_state_r = CU_8x8;
end
LCU_END: begin
if(lcu_cyc_cnt_r==3'd7)
lcu_next_state_r = LCU_IDLE;
else
lcu_next_state_r = LCU_END;
end
endcase
end
// -----------------------------------------------------------------------------------------------------------------------------
//
// calculation cu_depth
//
// -----------------------------------------------------------------------------------------------------------------------------
reg [1:0] cu_depth_0_0_r , cu_depth_0_2_r , cu_depth_0_4_r , cu_depth_0_6_r ;
reg [1:0] cu_depth_2_0_r , cu_depth_2_2_r , cu_depth_2_4_r , cu_depth_2_6_r ;
reg [1:0] cu_depth_4_0_r , cu_depth_4_2_r , cu_depth_4_4_r , cu_depth_4_6_r ;
reg [1:0] cu_depth_6_0_r , cu_depth_6_2_r , cu_depth_6_4_r , cu_depth_6_6_r ;
// cu_depth_0_0_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_0_0_r = 2'd0 ;
else if(~cu_split_flag_i[1]) // 32x32 not split
cu_depth_0_0_r = 2'd1 ;
else if(~cu_split_flag_i[5]) // 16x16 not split
cu_depth_0_0_r = 2'd2 ;
else // 8x8
cu_depth_0_0_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_0_0_r = 2'd0 ;
else if(inter_cu_part_size_i[3:2]!=(`PART_SPLIT))
cu_depth_0_0_r = 2'd1 ;
else if(inter_cu_part_size_i[11:10]!=(`PART_SPLIT))
cu_depth_0_0_r = 2'd2 ;
else
cu_depth_0_0_r = 2'd3 ;
end
end
// cu_depth_0_2_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_0_2_r = 2'd0 ;
else if(~cu_split_flag_i[1]) // 32x32 not split
cu_depth_0_2_r = 2'd1 ;
else if(~cu_split_flag_i[6]) // 16x16 not split
cu_depth_0_2_r = 2'd2 ;
else // 8x8
cu_depth_0_2_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_0_2_r = 2'd0 ;
else if(inter_cu_part_size_i[3:2]!=(`PART_SPLIT))
cu_depth_0_2_r = 2'd1 ;
else if(inter_cu_part_size_i[13:12]!=(`PART_SPLIT))
cu_depth_0_2_r = 2'd2 ;
else
cu_depth_0_2_r = 2'd3 ;
end
end
// cu_depth_0_4_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_0_4_r = 2'd0 ;
else if(~cu_split_flag_i[2]) // 32x32 not split
cu_depth_0_4_r = 2'd1 ;
else if(~cu_split_flag_i[9]) // 16x16 not split
cu_depth_0_4_r = 2'd2 ;
else // 8x8
cu_depth_0_4_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_0_4_r = 2'd0 ;
else if(inter_cu_part_size_i[5:4]!=(`PART_SPLIT))
cu_depth_0_4_r = 2'd1 ;
else if(inter_cu_part_size_i[19:18]!=(`PART_SPLIT))
cu_depth_0_4_r = 2'd2 ;
else
cu_depth_0_4_r = 2'd3 ;
end
end
// cu_depth_0_6_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_0_6_r = 2'd0 ;
else if(~cu_split_flag_i[2]) // 32x32 not split
cu_depth_0_6_r = 2'd1 ;
else if(~cu_split_flag_i[10]) // 16x16 not split
cu_depth_0_6_r = 2'd2 ;
else // 8x8
cu_depth_0_6_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_0_6_r = 2'd0 ;
else if(inter_cu_part_size_i[5:4]!=(`PART_SPLIT))
cu_depth_0_6_r = 2'd1 ;
else if(inter_cu_part_size_i[21:20]!=(`PART_SPLIT))
cu_depth_0_6_r = 2'd2 ;
else
cu_depth_0_6_r = 2'd3 ;
end
end
// cu_depth_2_0_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_2_0_r = 2'd0 ;
else if(~cu_split_flag_i[1]) // 32x32 not split
cu_depth_2_0_r = 2'd1 ;
else if(~cu_split_flag_i[7]) // 16x16 not split
cu_depth_2_0_r = 2'd2 ;
else // 8x8
cu_depth_2_0_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_2_0_r = 2'd0 ;
else if(inter_cu_part_size_i[3:2]!=(`PART_SPLIT))
cu_depth_2_0_r = 2'd1 ;
else if(inter_cu_part_size_i[15:14]!=(`PART_SPLIT))
cu_depth_2_0_r = 2'd2 ;
else
cu_depth_2_0_r = 2'd3 ;
end
end
// cu_depth_2_2_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_2_2_r = 2'd0 ;
else if(~cu_split_flag_i[1]) // 32x32 not split
cu_depth_2_2_r = 2'd1 ;
else if(~cu_split_flag_i[8]) // 16x16 not split
cu_depth_2_2_r = 2'd2 ;
else // 8x8
cu_depth_2_2_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_2_2_r = 2'd0 ;
else if(inter_cu_part_size_i[3:2]!=(`PART_SPLIT))
cu_depth_2_2_r = 2'd1 ;
else if(inter_cu_part_size_i[17:16]!=(`PART_SPLIT))
cu_depth_2_2_r = 2'd2 ;
else
cu_depth_2_2_r = 2'd3 ;
end
end
// cu_depth_2_4_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_2_4_r = 2'd0 ;
else if(~cu_split_flag_i[2]) // 32x32 not split
cu_depth_2_4_r = 2'd1 ;
else if(~cu_split_flag_i[11]) // 16x16 not split
cu_depth_2_4_r = 2'd2 ;
else // 8x8
cu_depth_2_4_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_2_4_r = 2'd0 ;
else if(inter_cu_part_size_i[5:4]!=(`PART_SPLIT))
cu_depth_2_4_r = 2'd1 ;
else if(inter_cu_part_size_i[23:22]!=(`PART_SPLIT))
cu_depth_2_4_r = 2'd2 ;
else
cu_depth_2_4_r = 2'd3 ;
end
end
// cu_depth_2_6_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_2_6_r = 2'd0 ;
else if(~cu_split_flag_i[2]) // 32x32 not split
cu_depth_2_6_r = 2'd1 ;
else if(~cu_split_flag_i[12]) // 16x16 not split
cu_depth_2_6_r = 2'd2 ;
else // 8x8
cu_depth_2_6_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_2_6_r = 2'd0 ;
else if(inter_cu_part_size_i[5:4]!=(`PART_SPLIT))
cu_depth_2_6_r = 2'd1 ;
else if(inter_cu_part_size_i[25:24]!=(`PART_SPLIT))
cu_depth_2_6_r = 2'd2 ;
else
cu_depth_2_6_r = 2'd3 ;
end
end
// cu_depth_4_0_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_4_0_r = 2'd0 ;
else if(~cu_split_flag_i[3]) // 32x32 not split
cu_depth_4_0_r = 2'd1 ;
else if(~cu_split_flag_i[13]) // 16x16 not split
cu_depth_4_0_r = 2'd2 ;
else // 8x8
cu_depth_4_0_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_4_0_r = 2'd0 ;
else if(inter_cu_part_size_i[7:6]!=(`PART_SPLIT))
cu_depth_4_0_r = 2'd1 ;
else if(inter_cu_part_size_i[27:26]!=(`PART_SPLIT))
cu_depth_4_0_r = 2'd2 ;
else
cu_depth_4_0_r = 2'd3 ;
end
end
// cu_depth_4_2_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_4_2_r = 2'd0 ;
else if(~cu_split_flag_i[3]) // 32x32 not split
cu_depth_4_2_r = 2'd1 ;
else if(~cu_split_flag_i[14]) // 16x16 not split
cu_depth_4_2_r = 2'd2 ;
else // 8x8
cu_depth_4_2_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_4_2_r = 2'd0 ;
else if(inter_cu_part_size_i[7:6]!=(`PART_SPLIT))
cu_depth_4_2_r = 2'd1 ;
else if(inter_cu_part_size_i[29:28]!=(`PART_SPLIT))
cu_depth_4_2_r = 2'd2 ;
else
cu_depth_4_2_r = 2'd3 ;
end
end
// cu_depth_4_4_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_4_4_r = 2'd0 ;
else if(~cu_split_flag_i[4]) // 32x32 not split
cu_depth_4_4_r = 2'd1 ;
else if(~cu_split_flag_i[17]) // 16x16 not split
cu_depth_4_4_r = 2'd2 ;
else // 8x8
cu_depth_4_4_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_4_4_r = 2'd0 ;
else if(inter_cu_part_size_i[9:8]!=(`PART_SPLIT))
cu_depth_4_4_r = 2'd1 ;
else if(inter_cu_part_size_i[35:34]!=(`PART_SPLIT))
cu_depth_4_4_r = 2'd2 ;
else
cu_depth_4_4_r = 2'd3 ;
end
end
// cu_depth_4_6_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_4_6_r = 2'd0 ;
else if(~cu_split_flag_i[4]) // 32x32 not split
cu_depth_4_6_r = 2'd1 ;
else if(~cu_split_flag_i[18]) // 16x16 not split
cu_depth_4_6_r = 2'd2 ;
else // 8x8
cu_depth_4_6_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_4_6_r = 2'd0 ;
else if(inter_cu_part_size_i[9:8]!=(`PART_SPLIT))
cu_depth_4_6_r = 2'd1 ;
else if(inter_cu_part_size_i[37:36]!=(`PART_SPLIT))
cu_depth_4_6_r = 2'd2 ;
else
cu_depth_4_6_r = 2'd3 ;
end
end
// cu_depth_6_0_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64
cu_depth_6_0_r = 2'd0 ;
else if(~cu_split_flag_i[3]) // 32x32
cu_depth_6_0_r = 2'd1 ;
else if(~cu_split_flag_i[15]) // 16x16
cu_depth_6_0_r = 2'd2 ;
else // 8x8
cu_depth_6_0_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) // 64x64
cu_depth_6_0_r = 2'd0 ;
else if(inter_cu_part_size_i[7:6]!=(`PART_SPLIT)) // 32x32
cu_depth_6_0_r = 2'd1 ;
else if(inter_cu_part_size_i[31:30]!=(`PART_SPLIT)) // 16x16
cu_depth_6_0_r = 2'd2 ;
else // 8x8
cu_depth_6_0_r = 2'd3 ;
end
end
// cu_depth_6_2_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0])
cu_depth_6_2_r = 2'd0;
else if(~cu_split_flag_i[3])
cu_depth_6_2_r = 2'd1;
else if(~cu_split_flag_i[16])
cu_depth_6_2_r = 2'd2;
else
cu_depth_6_2_r = 2'd3;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_6_2_r = 2'd0;
else if(inter_cu_part_size_i[7:6]!=(`PART_SPLIT))
cu_depth_6_2_r = 2'd1;
else if(inter_cu_part_size_i[33:32]!=(`PART_SPLIT))
cu_depth_6_2_r = 2'd2;
else
cu_depth_6_2_r = 2'd3;
end
end
// cu_depth_6_4_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0])
cu_depth_6_4_r = 2'd0;
else if(~cu_split_flag_i[4])
cu_depth_6_4_r = 2'd1;
else if(~cu_split_flag_i[19])
cu_depth_6_4_r = 2'd2;
else
cu_depth_6_4_r = 2'd3;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_6_4_r = 2'd0;
else if(inter_cu_part_size_i[9:8]!=(`PART_SPLIT))
cu_depth_6_4_r = 2'd1;
else if(inter_cu_part_size_i[39:38]!=(`PART_SPLIT))
cu_depth_6_4_r = 2'd2;
else
cu_depth_6_4_r = 2'd3;
end
end
// cu_depth_6_6_r
always @* begin
if(slice_type_i==(`SLICE_TYPE_I)) begin
if(~cu_split_flag_i[0]) // 64x64 not split
cu_depth_6_6_r = 2'd0 ;
else if(~cu_split_flag_i[4]) // 32x32 not split
cu_depth_6_6_r = 2'd1 ;
else if(~cu_split_flag_i[20]) // 16x16 not split
cu_depth_6_6_r = 2'd2 ;
else // 8x8
cu_depth_6_6_r = 2'd3 ;
end
else begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT))
cu_depth_6_6_r = 2'd0 ;
else if(inter_cu_part_size_i[9:8]!=(`PART_SPLIT))
cu_depth_6_6_r = 2'd1 ;
else if(inter_cu_part_size_i[41:40]!=(`PART_SPLIT))
cu_depth_6_6_r = 2'd2 ;
else
cu_depth_6_6_r = 2'd3 ;
end
end
// -----------------------------------------------------------------------------------------------------------------------------
//
// calculation and store internal signals for next lcu
//
// -----------------------------------------------------------------------------------------------------------------------------
// cu_skip_left_flag
// cu_depth_left
// cu_luma_pred_left_mode
// left data
// {cu_skip_flag,cu_luma_pred_mode_w[5:0],cu_depth_left[1:0]}
reg cu_skip_left_0_r , cu_skip_left_1_r ;
reg cu_skip_left_2_r , cu_skip_left_3_r ;
reg cu_skip_left_4_r , cu_skip_left_5_r ;
reg cu_skip_left_6_r , cu_skip_left_7_r ;
reg [5:0] cu_luma_mode_left_0_r , cu_luma_mode_left_1_r ;
reg [5:0] cu_luma_mode_left_2_r , cu_luma_mode_left_3_r ;
reg [5:0] cu_luma_mode_left_4_r , cu_luma_mode_left_5_r ;
reg [5:0] cu_luma_mode_left_6_r , cu_luma_mode_left_7_r ;
reg [5:0] cu_luma_mode_left_8_r , cu_luma_mode_left_9_r ;
reg [5:0] cu_luma_mode_left_10_r, cu_luma_mode_left_11_r ;
reg [5:0] cu_luma_mode_left_12_r, cu_luma_mode_left_13_r ;
reg [5:0] cu_luma_mode_left_14_r, cu_luma_mode_left_15_r ;
reg [8:0] cu_left_0_r , cu_left_1_r ;
reg [8:0] cu_left_2_r , cu_left_3_r ;
reg [8:0] cu_left_4_r , cu_left_5_r ;
reg [8:0] cu_left_6_r , cu_left_7_r ;
reg [8:0] cu_left_8_r , cu_left_9_r ;
reg [8:0] cu_left_10_r , cu_left_11_r ;
reg [8:0] cu_left_12_r , cu_left_13_r ;
reg [8:0] cu_left_14_r , cu_left_15_r ;
reg cu_start_r ;
reg cu_start_d1_r ;
reg cu_start_d2_r ;
reg cu_start_d3_r ;
reg cu_sub_div_r ;
reg [1:0 ] cu_inter_part_size_r ;
reg [3:0 ] cu_merge_flag_r ;
reg [15:0] cu_merge_idx_r ;
reg [3:0 ] cu_cbf_y_r ;
reg [3:0 ] cu_cbf_u_r ;
reg [3:0 ] cu_cbf_v_r ;
reg cu_skip_top_flag_r ;
reg cu_skip_left_flag_r ;
reg [1:0 ] cu_depth_top_r ;
reg [1:0 ] cu_depth_left_r ;
reg last_cu_flag_r ; // the last cu in the current lcu
reg cu_mvd_ren_r ; // read mvd enable
reg [6:0 ] cu_mvd_raddr_r ; // address of mvd
reg [(4*`MVD_WIDTH)+1:0] cu_mvd_data_r ;
//reg [ 8:0] cu_mvd_idx_r ;
reg cu_qp_nocoded_r ;
reg [5:0] cu_qp_last_r ;
reg [ 5:0] cu_luma_mode_raddr_r ;
reg [ 5:0] cu_luma_top_mode_raddr_r ;
reg [ 5:0] cu_luma_left_mode_raddr_r ;
reg [23:0] cu_luma_pred_mode_r ;
reg [23:0] cu_luma_pred_top_mode_r ;
reg [23:0] cu_luma_pred_left_mode_r ;
reg [ 5:0] cu_chroma_pred_mode_r ;
// cu_skip_left_0_r cu_skip_left_1_r
always @* begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) begin // 64x64
cu_skip_left_0_r = cu_skip_flag_i[0] ;
cu_skip_left_1_r = cu_skip_flag_i[0] ;
end
else if(inter_cu_part_size_i[5:4]!=(`PART_SPLIT)) begin // 32x32
cu_skip_left_0_r = cu_skip_flag_i[2] ;
cu_skip_left_1_r = cu_skip_flag_i[2] ;
end
else if(inter_cu_part_size_i[21:20]!=(`PART_SPLIT))begin // 16x16
cu_skip_left_0_r = cu_skip_flag_i[10] ;
cu_skip_left_1_r = cu_skip_flag_i[10] ;
end
else begin // 8x8
cu_skip_left_0_r = cu_skip_flag_i[42] ;
cu_skip_left_1_r = cu_skip_flag_i[44] ;
end
end
// cu_skip_left_2_r cu_skip_left_3_r
always @* begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) begin // 64x64
cu_skip_left_2_r = cu_skip_flag_i[0] ;
cu_skip_left_3_r = cu_skip_flag_i[0] ;
end
else if(inter_cu_part_size_i[5:4]!=(`PART_SPLIT)) begin // 32x32
cu_skip_left_2_r = cu_skip_flag_i[2] ;
cu_skip_left_3_r = cu_skip_flag_i[2] ;
end
else if(inter_cu_part_size_i[25:24]!=(`PART_SPLIT))begin // 16x16
cu_skip_left_2_r = cu_skip_flag_i[12] ;
cu_skip_left_3_r = cu_skip_flag_i[12] ;
end
else begin // 8x8
cu_skip_left_2_r = cu_skip_flag_i[50] ;
cu_skip_left_3_r = cu_skip_flag_i[52] ;
end
end
// cu_skip_left_4_r cu_skip_left_5_r
always @* begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) begin // 64x64
cu_skip_left_4_r = cu_skip_flag_i[0] ;
cu_skip_left_5_r = cu_skip_flag_i[0] ;
end
else if(inter_cu_part_size_i[9:8]!=(`PART_SPLIT)) begin // 32x32
cu_skip_left_4_r = cu_skip_flag_i[4] ;
cu_skip_left_5_r = cu_skip_flag_i[4] ;
end
else if(inter_cu_part_size_i[37:36]!=(`PART_SPLIT))begin // 16x16
cu_skip_left_4_r = cu_skip_flag_i[18] ;
cu_skip_left_5_r = cu_skip_flag_i[18] ;
end
else begin // 8x8
cu_skip_left_4_r = cu_skip_flag_i[74] ;
cu_skip_left_5_r = cu_skip_flag_i[77] ;
end
end
// cu_skip_left_6_r cu_skip_left_7_r
always @* begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) begin // 64x64
cu_skip_left_6_r = cu_skip_flag_i[0] ;
cu_skip_left_7_r = cu_skip_flag_i[0] ;
end
else if(inter_cu_part_size_i[9:8]!=(`PART_SPLIT)) begin // 32x32
cu_skip_left_6_r = cu_skip_flag_i[4] ;
cu_skip_left_7_r = cu_skip_flag_i[4] ;
end
else if(inter_cu_part_size_i[41:40]!=(`PART_SPLIT))begin // 16x16
cu_skip_left_6_r = cu_skip_flag_i[20] ;
cu_skip_left_7_r = cu_skip_flag_i[20] ;
end
else begin // 8x8
cu_skip_left_6_r = cu_skip_flag_i[82] ;
cu_skip_left_7_r = cu_skip_flag_i[84] ;
end
end
// cu_luma_mode_left_0_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_0_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_0_r <= 6'd1 ;
else begin
case(cu_depth_0_6_r )
2'd0 : cu_luma_mode_left_0_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_0_r;
2'd1 : cu_luma_mode_left_0_r <= (cu_idx_r==7'd2 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_0_r;
2'd2 : cu_luma_mode_left_0_r <= (cu_idx_r==7'd10&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_0_r;
2'd3 : cu_luma_mode_left_0_r <= (cu_idx_r==7'd42&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_0_r;
endcase
end
end
// cu_luma_mode_left_1_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_1_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_1_r <= 6'd1 ;
else begin
case(cu_depth_0_6_r )
2'd0 : cu_luma_mode_left_1_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_1_r;
2'd1 : cu_luma_mode_left_1_r <= (cu_idx_r==7'd2 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_1_r;
2'd2 : cu_luma_mode_left_1_r <= (cu_idx_r==7'd10&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_1_r;
2'd3 : cu_luma_mode_left_1_r <= (cu_idx_r==7'd42&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_1_r;
endcase
end
end
// cu_luma_mode_left_2_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_2_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_2_r <= 6'd1 ;
else begin
case(cu_depth_0_6_r )
2'd0 : cu_luma_mode_left_2_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_2_r;
2'd1 : cu_luma_mode_left_2_r <= (cu_idx_r==7'd2 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_2_r;
2'd2 : cu_luma_mode_left_2_r <= (cu_idx_r==7'd10&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_2_r;
2'd3 : cu_luma_mode_left_2_r <= (cu_idx_r==7'd44&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_2_r;
endcase
end
end
// cu_luma_mode_left_3_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_3_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_3_r <= 6'd1 ;
else begin
case(cu_depth_0_6_r )
2'd0 : cu_luma_mode_left_3_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_3_r;
2'd1 : cu_luma_mode_left_3_r <= (cu_idx_r==7'd2 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_3_r;
2'd2 : cu_luma_mode_left_3_r <= (cu_idx_r==7'd10&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_3_r;
2'd3 : cu_luma_mode_left_3_r <= (cu_idx_r==7'd44&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_3_r;
endcase
end
end
// cu_luma_mode_left_4_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_4_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_4_r <= 6'd1 ;
else begin
case(cu_depth_2_6_r )
2'd0 : cu_luma_mode_left_4_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_4_r;
2'd1 : cu_luma_mode_left_4_r <= (cu_idx_r==7'd2 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_4_r;
2'd2 : cu_luma_mode_left_4_r <= (cu_idx_r==7'd12&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_4_r;
2'd3 : cu_luma_mode_left_4_r <= (cu_idx_r==7'd50&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_4_r;
endcase
end
end
// cu_luma_mode_left_5_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_5_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_5_r <= 6'd1 ;
else begin
case(cu_depth_2_6_r )
2'd0 : cu_luma_mode_left_5_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_5_r;
2'd1 : cu_luma_mode_left_5_r <= (cu_idx_r==7'd2 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_5_r;
2'd2 : cu_luma_mode_left_5_r <= (cu_idx_r==7'd12&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_5_r;
2'd3 : cu_luma_mode_left_5_r <= (cu_idx_r==7'd50&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_5_r;
endcase
end
end
// cu_luma_mode_left_6_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_6_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_6_r <= 6'd1 ;
else begin
case(cu_depth_2_6_r )
2'd0 : cu_luma_mode_left_6_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_6_r;
2'd1 : cu_luma_mode_left_6_r <= (cu_idx_r==7'd2 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_6_r;
2'd2 : cu_luma_mode_left_6_r <= (cu_idx_r==7'd12&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_6_r;
2'd3 : cu_luma_mode_left_6_r <= (cu_idx_r==7'd52&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_6_r;
endcase
end
end
// cu_luma_mode_left_7_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_7_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_7_r <= 6'd1 ;
else begin
case(cu_depth_2_6_r )
2'd0 : cu_luma_mode_left_7_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_7_r;
2'd1 : cu_luma_mode_left_7_r <= (cu_idx_r==7'd2 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_7_r;
2'd2 : cu_luma_mode_left_7_r <= (cu_idx_r==7'd12&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_7_r;
2'd3 : cu_luma_mode_left_7_r <= (cu_idx_r==7'd52&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_7_r;
endcase
end
end
// cu_luma_mode_left_8_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_8_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_8_r <= 6'd1 ;
else begin
case(cu_depth_4_6_r )
2'd0 : cu_luma_mode_left_8_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_8_r;
2'd1 : cu_luma_mode_left_8_r <= (cu_idx_r==7'd4 &&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_8_r;
2'd2 : cu_luma_mode_left_8_r <= (cu_idx_r==7'd18&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_8_r;
2'd3 : cu_luma_mode_left_8_r <= (cu_idx_r==7'd74&&cu_start_d2_r) ? luma_mode_i[17:12] :cu_luma_mode_left_8_r;
endcase
end
end
// cu_luma_mode_left_9_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_9_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_9_r <= 6'd1 ;
else begin
case(cu_depth_4_6_r )
2'd0 : cu_luma_mode_left_9_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_9_r;
2'd1 : cu_luma_mode_left_9_r <= (cu_idx_r==7'd4 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_9_r;
2'd2 : cu_luma_mode_left_9_r <= (cu_idx_r==7'd18&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_9_r;
2'd3 : cu_luma_mode_left_9_r <= (cu_idx_r==7'd74&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_9_r;
endcase
end
end
// cu_luma_mode_left_10_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_10_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_10_r <= 6'd1 ;
else begin
case(cu_depth_4_6_r )
2'd0 : cu_luma_mode_left_10_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[17:12]:cu_luma_mode_left_10_r;
2'd1 : cu_luma_mode_left_10_r <= (cu_idx_r==7'd4 &&cu_start_d2_r) ? luma_mode_i[17:12]:cu_luma_mode_left_10_r;
2'd2 : cu_luma_mode_left_10_r <= (cu_idx_r==7'd18&&cu_start_d2_r) ? luma_mode_i[17:12]:cu_luma_mode_left_10_r;
2'd3 : cu_luma_mode_left_10_r <= (cu_idx_r==7'd76&&cu_start_d2_r) ? luma_mode_i[17:12]:cu_luma_mode_left_10_r;
endcase
end
end
// cu_luma_mode_left_11_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_11_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_11_r <= 6'd1 ;
else begin
case(cu_depth_4_6_r )
2'd0 : cu_luma_mode_left_11_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ]:cu_luma_mode_left_11_r;
2'd1 : cu_luma_mode_left_11_r <= (cu_idx_r==7'd4 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ]:cu_luma_mode_left_11_r;
2'd2 : cu_luma_mode_left_11_r <= (cu_idx_r==7'd18&&cu_start_d2_r) ? luma_mode_i[ 5:0 ]:cu_luma_mode_left_11_r;
2'd3 : cu_luma_mode_left_11_r <= (cu_idx_r==7'd76&&cu_start_d2_r) ? luma_mode_i[ 5:0 ]:cu_luma_mode_left_11_r;
endcase
end
end
// cu_luma_mode_left_12_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_12_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_12_r <= 6'd1 ;
else begin
case(cu_depth_6_6_r )
2'd0 : cu_luma_mode_left_12_r <= (cu_idx_r==7'd0 &&cu_start_d2_r)? luma_mode_i[17:12] :cu_luma_mode_left_12_r;
2'd1 : cu_luma_mode_left_12_r <= (cu_idx_r==7'd4 &&cu_start_d2_r)? luma_mode_i[17:12] :cu_luma_mode_left_12_r;
2'd2 : cu_luma_mode_left_12_r <= (cu_idx_r==7'd20&&cu_start_d2_r)? luma_mode_i[17:12] :cu_luma_mode_left_12_r;
2'd3 : cu_luma_mode_left_12_r <= (cu_idx_r==7'd82&&cu_start_d2_r)? luma_mode_i[17:12] :cu_luma_mode_left_12_r;
endcase
end
end
// cu_luma_mode_left_13_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_13_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_13_r <= 6'd1 ;
else begin
case(cu_depth_6_6_r )
2'd0 : cu_luma_mode_left_13_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_13_r;
2'd1 : cu_luma_mode_left_13_r <= (cu_idx_r==7'd4 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_13_r;
2'd2 : cu_luma_mode_left_13_r <= (cu_idx_r==7'd20&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_13_r;
2'd3 : cu_luma_mode_left_13_r <= (cu_idx_r==7'd82&&cu_start_d2_r) ? luma_mode_i[ 5:0 ] :cu_luma_mode_left_13_r;
endcase
end
end
// cu_luma_mode_left_14_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_14_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_14_r <= 6'd1 ;
else begin
case(cu_depth_6_6_r )
2'd0 : cu_luma_mode_left_14_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[17:12]:cu_luma_mode_left_14_r;
2'd1 : cu_luma_mode_left_14_r <= (cu_idx_r==7'd4 &&cu_start_d2_r) ? luma_mode_i[17:12]:cu_luma_mode_left_14_r;
2'd2 : cu_luma_mode_left_14_r <= (cu_idx_r==7'd20&&cu_start_d2_r) ? luma_mode_i[17:12]:cu_luma_mode_left_14_r;
2'd3 : cu_luma_mode_left_14_r <= (cu_idx_r==7'd84&&cu_start_d2_r) ? luma_mode_i[17:12]:cu_luma_mode_left_14_r;
endcase
end
end
// cu_luma_mode_left_15_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_mode_left_15_r <= 6'd1 ;
else if(mb_x_i==mb_x_total_i&&lcu_done_r)
cu_luma_mode_left_15_r <= 6'd1 ;
else begin
case(cu_depth_6_6_r )
2'd0 : cu_luma_mode_left_15_r <= (cu_idx_r==7'd0 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ]:cu_luma_mode_left_15_r;
2'd1 : cu_luma_mode_left_15_r <= (cu_idx_r==7'd4 &&cu_start_d2_r) ? luma_mode_i[ 5:0 ]:cu_luma_mode_left_15_r;
2'd2 : cu_luma_mode_left_15_r <= (cu_idx_r==7'd20&&cu_start_d2_r) ? luma_mode_i[ 5:0 ]:cu_luma_mode_left_15_r;
2'd3 : cu_luma_mode_left_15_r <= (cu_idx_r==7'd84&&cu_start_d2_r) ? luma_mode_i[ 5:0 ]:cu_luma_mode_left_15_r;
endcase
end
end
// cu_left_0_r , cu_left_1_r ,cu_left_2_r , cu_left_3_r , cu_left_4_r , cu_left_5_r ,cu_left_6_r , cu_left_7_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cu_left_0_r <= 9'd1 ; cu_left_1_r <= 9'd1 ;
cu_left_2_r <= 9'd1 ; cu_left_3_r <= 9'd1 ;
cu_left_4_r <= 9'd1 ; cu_left_5_r <= 9'd1 ;
cu_left_6_r <= 9'd1 ; cu_left_7_r <= 9'd1 ;
cu_left_8_r <= 9'd1 ; cu_left_9_r <= 9'd1 ;
cu_left_10_r <= 9'd1 ; cu_left_11_r <= 9'd1 ;
cu_left_12_r <= 9'd1 ; cu_left_13_r <= 9'd1 ;
cu_left_14_r <= 9'd1 ; cu_left_15_r <= 9'd1 ;
end
else if(lcu_curr_state_r == LCU_END) begin
cu_left_0_r <= {cu_skip_left_0_r,cu_luma_mode_left_0_r ,cu_depth_0_6_r};
cu_left_1_r <= {cu_skip_left_0_r,cu_luma_mode_left_1_r ,cu_depth_0_6_r};
cu_left_2_r <= {cu_skip_left_1_r,cu_luma_mode_left_2_r ,cu_depth_0_6_r};
cu_left_3_r <= {cu_skip_left_1_r,cu_luma_mode_left_3_r ,cu_depth_0_6_r};
cu_left_4_r <= {cu_skip_left_2_r,cu_luma_mode_left_4_r ,cu_depth_2_6_r};
cu_left_5_r <= {cu_skip_left_2_r,cu_luma_mode_left_5_r ,cu_depth_2_6_r};
cu_left_6_r <= {cu_skip_left_3_r,cu_luma_mode_left_6_r ,cu_depth_2_6_r};
cu_left_7_r <= {cu_skip_left_3_r,cu_luma_mode_left_7_r ,cu_depth_2_6_r};
cu_left_8_r <= {cu_skip_left_4_r,cu_luma_mode_left_8_r ,cu_depth_4_6_r};
cu_left_9_r <= {cu_skip_left_4_r,cu_luma_mode_left_9_r ,cu_depth_4_6_r};
cu_left_10_r <= {cu_skip_left_5_r,cu_luma_mode_left_10_r,cu_depth_4_6_r};
cu_left_11_r <= {cu_skip_left_5_r,cu_luma_mode_left_11_r,cu_depth_4_6_r};
cu_left_12_r <= {cu_skip_left_6_r,cu_luma_mode_left_12_r,cu_depth_6_6_r};
cu_left_13_r <= {cu_skip_left_6_r,cu_luma_mode_left_13_r,cu_depth_6_6_r};
cu_left_14_r <= {cu_skip_left_7_r,cu_luma_mode_left_14_r,cu_depth_6_6_r};
cu_left_15_r <= {cu_skip_left_7_r,cu_luma_mode_left_15_r,cu_depth_6_6_r};
end
else begin
cu_left_0_r <= cu_left_0_r ; cu_left_1_r <= cu_left_1_r ;
cu_left_2_r <= cu_left_2_r ; cu_left_3_r <= cu_left_3_r ;
cu_left_4_r <= cu_left_4_r ; cu_left_5_r <= cu_left_5_r ;
cu_left_6_r <= cu_left_6_r ; cu_left_7_r <= cu_left_7_r ;
cu_left_8_r <= cu_left_8_r ; cu_left_9_r <= cu_left_9_r ;
cu_left_10_r <= cu_left_10_r; cu_left_11_r <= cu_left_11_r;
cu_left_12_r <= cu_left_12_r; cu_left_13_r <= cu_left_13_r;
cu_left_14_r <= cu_left_14_r; cu_left_15_r <= cu_left_15_r;
end
end
// cu_skip_top_flag
reg cu_skip_top_0_r , cu_skip_top_1_r ;
reg cu_skip_top_2_r , cu_skip_top_3_r ;
reg cu_skip_top_4_r , cu_skip_top_5_r ;
reg cu_skip_top_6_r , cu_skip_top_7_r ;
// cu_skip_top_0_r cu_skip_top_1_r
always @* begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) begin // 64x64
cu_skip_top_0_r = cu_skip_flag_i[0] ;
cu_skip_top_1_r = cu_skip_flag_i[0] ;
end
else if(inter_cu_part_size_i[7:6]!=(`PART_SPLIT)) begin // 32x32
cu_skip_top_0_r = cu_skip_flag_i[3] ;
cu_skip_top_1_r = cu_skip_flag_i[3] ;
end
else if(inter_cu_part_size_i[31:30]!=(`PART_SPLIT))begin // 16x16
cu_skip_top_0_r = cu_skip_flag_i[15] ;
cu_skip_top_1_r = cu_skip_flag_i[15] ;
end
else begin // 8x8
cu_skip_top_0_r = cu_skip_flag_i[63] ;
cu_skip_top_1_r = cu_skip_flag_i[64] ;
end
end
// cu_skip_top_2_r cu_skip_top_3_r
always @* begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) begin // 64x64
cu_skip_top_2_r = cu_skip_flag_i[0] ;
cu_skip_top_3_r = cu_skip_flag_i[0] ;
end
else if(inter_cu_part_size_i[7:6]!=(`PART_SPLIT)) begin // 32x32
cu_skip_top_2_r = cu_skip_flag_i[3] ;
cu_skip_top_3_r = cu_skip_flag_i[3] ;
end
else if(inter_cu_part_size_i[33:32]!=(`PART_SPLIT))begin // 16x16
cu_skip_top_2_r = cu_skip_flag_i[16] ;
cu_skip_top_3_r = cu_skip_flag_i[16] ;
end
else begin // 8x8
cu_skip_top_2_r = cu_skip_flag_i[67] ;
cu_skip_top_3_r = cu_skip_flag_i[68] ;
end
end
// cu_skip_top_4_r cu_skip_top_5_r
always @* begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) begin // 64x64
cu_skip_top_4_r = cu_skip_flag_i[0] ;
cu_skip_top_5_r = cu_skip_flag_i[0] ;
end
else if(inter_cu_part_size_i[9:8]!=(`PART_SPLIT)) begin // 32x32
cu_skip_top_4_r = cu_skip_flag_i[4] ;
cu_skip_top_5_r = cu_skip_flag_i[4] ;
end
else if(inter_cu_part_size_i[39:38]!=(`PART_SPLIT))begin // 16x16
cu_skip_top_4_r = cu_skip_flag_i[19] ;
cu_skip_top_5_r = cu_skip_flag_i[19] ;
end
else begin // 8x8
cu_skip_top_4_r = cu_skip_flag_i[79] ;
cu_skip_top_5_r = cu_skip_flag_i[80] ;
end
end
// cu_skip_top_6_r cu_skip_top_7_r
always @* begin
if(inter_cu_part_size_i[1:0]!=(`PART_SPLIT)) begin // 64x64
cu_skip_top_6_r = cu_skip_flag_i[0] ;
cu_skip_top_7_r = cu_skip_flag_i[0] ;
end
else if(inter_cu_part_size_i[9:8]!=(`PART_SPLIT)) begin // 32x32
cu_skip_top_6_r = cu_skip_flag_i[4] ;
cu_skip_top_7_r = cu_skip_flag_i[4] ;
end
else if(inter_cu_part_size_i[39:38]!=(`PART_SPLIT))begin // 16x16
cu_skip_top_6_r = cu_skip_flag_i[20] ;
cu_skip_top_7_r = cu_skip_flag_i[20] ;
end
else begin // 8x8
cu_skip_top_6_r = cu_skip_flag_i[83] ;
cu_skip_top_7_r = cu_skip_flag_i[84] ;
end
end
// -----------------------------------------------------------------------------------------------------------------------------
//
// store in memory
//
// -----------------------------------------------------------------------------------------------------------------------------
reg r_en_neigh_r ; //read memory of neighbour info enable
reg w_en_neigh_r ; //write memory of neighbour info enable
wire [15:0] r_data_neigh_mb_w ; //read data of top LCU
wire [15:0] w_data_neigh_mb_w ; //write data of top LCU
reg [15:0] r_data_neigh_mb_r ; //read data of top LCU
ram_1p #(.Addr_Width((`PIC_X_WIDTH)), .Word_Width(16))
cabac_neighbour_1p_8xMB_X_TOTAL_u0(
.clk ( clk ),
.cen_i ( 1'b0 ), // low active
.oen_i ( r_en_neigh_r ), // read enable ,low active
.wen_i ( w_en_neigh_r ), // write enable ,low active
.addr_i ( mb_x_i ), // address
.data_i ( w_data_neigh_mb_w ), // write data
.data_o ( r_data_neigh_mb_w ) // read data
);
// r_en_neigh_r
always @* begin
if(cabac_start_i)
r_en_neigh_r = !mb_y_i;
else
r_en_neigh_r = 1'b1 ;
end
// w_en_neigh_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_neigh_r <= 1'b1 ;
else if(lcu_done_r)
w_en_neigh_r <= 1'b0 ;
else
w_en_neigh_r <= 1'b1 ;
end
// w_data_neigh_mb_w
assign w_data_neigh_mb_w = {cu_depth_6_0_r ,cu_depth_6_2_r ,cu_depth_6_4_r ,cu_depth_6_6_r ,
cu_skip_top_0_r ,cu_skip_top_1_r ,cu_skip_top_2_r ,cu_skip_top_3_r ,
cu_skip_top_4_r ,cu_skip_top_5_r ,cu_skip_top_6_r ,cu_skip_top_7_r };
//r_data_neigh_mb_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_data_neigh_mb_r <= 16'd0 ;
else if(!r_en_neigh_r)
r_data_neigh_mb_r <= r_data_neigh_mb_w ;
end
// -----------------------------------------------------------------------------------------------------------------------------
//
// calculation syntax elements values based on cu_idx_r
//
// -----------------------------------------------------------------------------------------------------------------------------
// cu_start_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_start_r <= 1'b0 ;
else if(lcu_curr_state_r==CU_SPLIT && !lcu_next_state_r[2]) // split --> cu
cu_start_r <= 1'b1 ;
else if(!lcu_curr_state_r[2]&&cu_done_r&&!lcu_next_state_r[2]) // cu-->cu
cu_start_r <= 1'b1 ;
else
cu_start_r <= 1'b0 ;
end
// cu_start_d1_r cu_start_d2_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cu_start_d1_r <= 1'b0 ;
cu_start_d2_r <= 1'b0 ;
cu_start_d3_r <= 1'b0 ;
end
else begin
cu_start_d1_r <= cu_start_r ;
cu_start_d2_r <= cu_start_d1_r;
cu_start_d3_r <= cu_start_d2_r;
end
end
// cu_sub_div_r : 1 split not encoding ,0 not split but encoding
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_sub_div_r <= 1'b0 ;
else begin
case(cu_depth_r)
2'd0: cu_sub_div_r <= 1'b1 ;
2'd1: cu_sub_div_r <= 1'b0 ;
2'd2: cu_sub_div_r <= 1'b0 ;
2'd3: cu_sub_div_r <= cu_split_flag_r ;
endcase
end
end
// cu_inter_part_size_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_inter_part_size_r <= (`PART_2NX2N);
else begin
case(cu_idx_r)
7'd0 : cu_inter_part_size_r <= inter_cu_part_size_i[ 1: 0];
7'd1 : cu_inter_part_size_r <= inter_cu_part_size_i[ 3: 2];
7'd2 : cu_inter_part_size_r <= inter_cu_part_size_i[ 5: 4];
7'd3 : cu_inter_part_size_r <= inter_cu_part_size_i[ 7: 6];
7'd4 : cu_inter_part_size_r <= inter_cu_part_size_i[ 9: 8];
7'd5 : cu_inter_part_size_r <= inter_cu_part_size_i[11:10];
7'd6 : cu_inter_part_size_r <= inter_cu_part_size_i[13:12];
7'd7 : cu_inter_part_size_r <= inter_cu_part_size_i[15:14];
7'd8 : cu_inter_part_size_r <= inter_cu_part_size_i[17:16];
7'd9 : cu_inter_part_size_r <= inter_cu_part_size_i[19:18];
7'd10 : cu_inter_part_size_r <= inter_cu_part_size_i[21:20];
7'd11 : cu_inter_part_size_r <= inter_cu_part_size_i[23:22];
7'd12 : cu_inter_part_size_r <= inter_cu_part_size_i[25:24];
7'd13 : cu_inter_part_size_r <= inter_cu_part_size_i[27:26];
7'd14 : cu_inter_part_size_r <= inter_cu_part_size_i[29:28];
7'd15 : cu_inter_part_size_r <= inter_cu_part_size_i[31:30];
7'd16 : cu_inter_part_size_r <= inter_cu_part_size_i[33:32];
7'd17 : cu_inter_part_size_r <= inter_cu_part_size_i[35:34];
7'd18 : cu_inter_part_size_r <= inter_cu_part_size_i[37:36];
7'd19 : cu_inter_part_size_r <= inter_cu_part_size_i[39:38];
7'd20 : cu_inter_part_size_r <= inter_cu_part_size_i[41:40];
7'd21 : cu_inter_part_size_r <= inter_cu_part_size_i[43:42];
7'd22 : cu_inter_part_size_r <= inter_cu_part_size_i[45:44];
7'd23 : cu_inter_part_size_r <= inter_cu_part_size_i[47:46];
7'd24 : cu_inter_part_size_r <= inter_cu_part_size_i[49:48];
7'd25 : cu_inter_part_size_r <= inter_cu_part_size_i[51:50];
7'd26 : cu_inter_part_size_r <= inter_cu_part_size_i[53:52];
7'd27 : cu_inter_part_size_r <= inter_cu_part_size_i[55:54];
7'd28 : cu_inter_part_size_r <= inter_cu_part_size_i[57:56];
7'd29 : cu_inter_part_size_r <= inter_cu_part_size_i[59:58];
7'd30 : cu_inter_part_size_r <= inter_cu_part_size_i[61:60];
7'd31 : cu_inter_part_size_r <= inter_cu_part_size_i[63:62];
7'd32 : cu_inter_part_size_r <= inter_cu_part_size_i[65:64];
7'd33 : cu_inter_part_size_r <= inter_cu_part_size_i[67:66];
7'd34 : cu_inter_part_size_r <= inter_cu_part_size_i[69:68];
7'd35 : cu_inter_part_size_r <= inter_cu_part_size_i[71:70];
7'd36 : cu_inter_part_size_r <= inter_cu_part_size_i[73:72];
7'd37 : cu_inter_part_size_r <= inter_cu_part_size_i[75:74];
7'd38 : cu_inter_part_size_r <= inter_cu_part_size_i[77:76];
7'd39 : cu_inter_part_size_r <= inter_cu_part_size_i[79:78];
7'd40 : cu_inter_part_size_r <= inter_cu_part_size_i[81:80];
7'd41 : cu_inter_part_size_r <= inter_cu_part_size_i[83:82];
7'd42 : cu_inter_part_size_r <= inter_cu_part_size_i[85:84];
7'd43 : cu_inter_part_size_r <= inter_cu_part_size_i[87:86];
7'd44 : cu_inter_part_size_r <= inter_cu_part_size_i[89:88];
7'd45 : cu_inter_part_size_r <= inter_cu_part_size_i[91:90];
7'd46 : cu_inter_part_size_r <= inter_cu_part_size_i[93:92];
7'd47 : cu_inter_part_size_r <= inter_cu_part_size_i[95:94];
7'd48 : cu_inter_part_size_r <= inter_cu_part_size_i[97:96];
7'd49 : cu_inter_part_size_r <= inter_cu_part_size_i[99:98];
7'd50 : cu_inter_part_size_r <= inter_cu_part_size_i[101:100];
7'd51 : cu_inter_part_size_r <= inter_cu_part_size_i[103:102];
7'd52 : cu_inter_part_size_r <= inter_cu_part_size_i[105:104];
7'd53 : cu_inter_part_size_r <= inter_cu_part_size_i[107:106];
7'd54 : cu_inter_part_size_r <= inter_cu_part_size_i[109:108];
7'd55 : cu_inter_part_size_r <= inter_cu_part_size_i[111:110];
7'd56 : cu_inter_part_size_r <= inter_cu_part_size_i[113:112];
7'd57 : cu_inter_part_size_r <= inter_cu_part_size_i[115:114];
7'd58 : cu_inter_part_size_r <= inter_cu_part_size_i[117:116];
7'd59 : cu_inter_part_size_r <= inter_cu_part_size_i[119:118];
7'd60 : cu_inter_part_size_r <= inter_cu_part_size_i[121:120];
7'd61 : cu_inter_part_size_r <= inter_cu_part_size_i[123:122];
7'd62 : cu_inter_part_size_r <= inter_cu_part_size_i[125:124];
7'd63 : cu_inter_part_size_r <= inter_cu_part_size_i[127:126];
7'd64 : cu_inter_part_size_r <= inter_cu_part_size_i[129:128];
7'd65 : cu_inter_part_size_r <= inter_cu_part_size_i[131:130];
7'd66 : cu_inter_part_size_r <= inter_cu_part_size_i[133:132];
7'd67 : cu_inter_part_size_r <= inter_cu_part_size_i[135:134];
7'd68 : cu_inter_part_size_r <= inter_cu_part_size_i[137:136];
7'd69 : cu_inter_part_size_r <= inter_cu_part_size_i[139:138];
7'd70 : cu_inter_part_size_r <= inter_cu_part_size_i[141:140];
7'd71 : cu_inter_part_size_r <= inter_cu_part_size_i[143:142];
7'd72 : cu_inter_part_size_r <= inter_cu_part_size_i[145:144];
7'd73 : cu_inter_part_size_r <= inter_cu_part_size_i[147:146];
7'd74 : cu_inter_part_size_r <= inter_cu_part_size_i[149:148];
7'd75 : cu_inter_part_size_r <= inter_cu_part_size_i[151:150];
7'd76 : cu_inter_part_size_r <= inter_cu_part_size_i[153:152];
7'd77 : cu_inter_part_size_r <= inter_cu_part_size_i[155:154];
7'd78 : cu_inter_part_size_r <= inter_cu_part_size_i[157:156];
7'd79 : cu_inter_part_size_r <= inter_cu_part_size_i[159:158];
7'd80 : cu_inter_part_size_r <= inter_cu_part_size_i[161:160];
7'd81 : cu_inter_part_size_r <= inter_cu_part_size_i[163:162];
7'd82 : cu_inter_part_size_r <= inter_cu_part_size_i[165:164];
7'd83 : cu_inter_part_size_r <= inter_cu_part_size_i[167:166];
7'd84 : cu_inter_part_size_r <= inter_cu_part_size_i[169:168];
default: cu_inter_part_size_r <= (`PART_2NX2N) ;
endcase
end
end
// cu_merge_flag_r , cu_merge_idx_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cu_merge_flag_r <= 4'b0 ;
cu_merge_idx_r <= 12'b0 ;
end
else begin
case(cu_idx_r)
7'd0 : begin cu_merge_flag_r <= {4{merge_flag_i[84]}};cu_merge_idx_r <= {4{merge_idx_i[255:252]}}; end
7'd1 : begin cu_merge_flag_r <= {4{merge_flag_i[83]}};cu_merge_idx_r <= {4{merge_idx_i[255:252]}}; end
7'd2 : begin cu_merge_flag_r <= {4{merge_flag_i[82]}};cu_merge_idx_r <= {4{merge_idx_i[191:188]}}; end
7'd3 : begin cu_merge_flag_r <= {4{merge_flag_i[81]}};cu_merge_idx_r <= {4{merge_idx_i[127:124]}}; end
7'd4 : begin cu_merge_flag_r <= {4{merge_flag_i[80]}};cu_merge_idx_r <= {4{merge_idx_i[ 63: 60]}}; end
7'd5 : begin cu_merge_flag_r <= {4{merge_flag_i[79]}};cu_merge_idx_r <= {4{merge_idx_i[255:252]}}; end
7'd6 : begin cu_merge_flag_r <= {4{merge_flag_i[78]}};cu_merge_idx_r <= {4{merge_idx_i[239:236]}}; end
7'd7 : begin cu_merge_flag_r <= {4{merge_flag_i[77]}};cu_merge_idx_r <= {4{merge_idx_i[219:216]}}; end
7'd8 : begin cu_merge_flag_r <= {4{merge_flag_i[76]}};cu_merge_idx_r <= {4{merge_idx_i[207:204]}}; end
7'd9 : begin cu_merge_flag_r <= {4{merge_flag_i[75]}};cu_merge_idx_r <= {4{merge_idx_i[191:188]}}; end
7'd10 : begin cu_merge_flag_r <= {4{merge_flag_i[74]}};cu_merge_idx_r <= {4{merge_idx_i[175:172]}}; end
7'd11 : begin cu_merge_flag_r <= {4{merge_flag_i[73]}};cu_merge_idx_r <= {4{merge_idx_i[159:156]}}; end
7'd12 : begin cu_merge_flag_r <= {4{merge_flag_i[72]}};cu_merge_idx_r <= {4{merge_idx_i[143:140]}}; end
7'd13 : begin cu_merge_flag_r <= {4{merge_flag_i[71]}};cu_merge_idx_r <= {4{merge_idx_i[127:124]}}; end
7'd14 : begin cu_merge_flag_r <= {4{merge_flag_i[70]}};cu_merge_idx_r <= {4{merge_idx_i[111:108]}}; end
7'd15 : begin cu_merge_flag_r <= {4{merge_flag_i[69]}};cu_merge_idx_r <= {4{merge_idx_i[ 95: 92]}}; end
7'd16 : begin cu_merge_flag_r <= {4{merge_flag_i[68]}};cu_merge_idx_r <= {4{merge_idx_i[ 79: 76]}}; end
7'd17 : begin cu_merge_flag_r <= {4{merge_flag_i[67]}};cu_merge_idx_r <= {4{merge_idx_i[ 63: 60]}}; end
7'd18 : begin cu_merge_flag_r <= {4{merge_flag_i[66]}};cu_merge_idx_r <= {4{merge_idx_i[ 47: 44]}}; end
7'd19 : begin cu_merge_flag_r <= {4{merge_flag_i[65]}};cu_merge_idx_r <= {4{merge_idx_i[ 31: 28]}}; end
7'd20 : begin cu_merge_flag_r <= {4{merge_flag_i[64]}};cu_merge_idx_r <= {4{merge_idx_i[ 15: 12]}}; end
7'd21 : begin cu_merge_flag_r <= {4{merge_flag_i[63]}};cu_merge_idx_r <= {4{merge_idx_i[255:252]}}; end
7'd22 : begin cu_merge_flag_r <= {4{merge_flag_i[62]}};cu_merge_idx_r <= {4{merge_idx_i[251:248]}}; end
7'd23 : begin cu_merge_flag_r <= {4{merge_flag_i[61]}};cu_merge_idx_r <= {4{merge_idx_i[247:244]}}; end
7'd24 : begin cu_merge_flag_r <= {4{merge_flag_i[60]}};cu_merge_idx_r <= {4{merge_idx_i[243:240]}}; end
7'd25 : begin cu_merge_flag_r <= {4{merge_flag_i[59]}};cu_merge_idx_r <= {4{merge_idx_i[239:236]}}; end
7'd26 : begin cu_merge_flag_r <= {4{merge_flag_i[58]}};cu_merge_idx_r <= {4{merge_idx_i[235:232]}}; end
7'd27 : begin cu_merge_flag_r <= {4{merge_flag_i[57]}};cu_merge_idx_r <= {4{merge_idx_i[231:228]}}; end
7'd28 : begin cu_merge_flag_r <= {4{merge_flag_i[56]}};cu_merge_idx_r <= {4{merge_idx_i[227:224]}}; end
7'd29 : begin cu_merge_flag_r <= {4{merge_flag_i[55]}};cu_merge_idx_r <= {4{merge_idx_i[223:220]}}; end
7'd30 : begin cu_merge_flag_r <= {4{merge_flag_i[54]}};cu_merge_idx_r <= {4{merge_idx_i[219:216]}}; end
7'd31 : begin cu_merge_flag_r <= {4{merge_flag_i[53]}};cu_merge_idx_r <= {4{merge_idx_i[215:212]}}; end
7'd32 : begin cu_merge_flag_r <= {4{merge_flag_i[52]}};cu_merge_idx_r <= {4{merge_idx_i[211:208]}}; end
7'd33 : begin cu_merge_flag_r <= {4{merge_flag_i[51]}};cu_merge_idx_r <= {4{merge_idx_i[207:204]}}; end
7'd34 : begin cu_merge_flag_r <= {4{merge_flag_i[50]}};cu_merge_idx_r <= {4{merge_idx_i[203:200]}}; end
7'd35 : begin cu_merge_flag_r <= {4{merge_flag_i[49]}};cu_merge_idx_r <= {4{merge_idx_i[199:196]}}; end
7'd36 : begin cu_merge_flag_r <= {4{merge_flag_i[48]}};cu_merge_idx_r <= {4{merge_idx_i[195:192]}}; end
7'd37 : begin cu_merge_flag_r <= {4{merge_flag_i[47]}};cu_merge_idx_r <= {4{merge_idx_i[191:188]}}; end
7'd38 : begin cu_merge_flag_r <= {4{merge_flag_i[46]}};cu_merge_idx_r <= {4{merge_idx_i[187:184]}}; end
7'd39 : begin cu_merge_flag_r <= {4{merge_flag_i[45]}};cu_merge_idx_r <= {4{merge_idx_i[183:180]}}; end
7'd40 : begin cu_merge_flag_r <= {4{merge_flag_i[44]}};cu_merge_idx_r <= {4{merge_idx_i[179:176]}}; end
7'd41 : begin cu_merge_flag_r <= {4{merge_flag_i[43]}};cu_merge_idx_r <= {4{merge_idx_i[175:172]}}; end
7'd42 : begin cu_merge_flag_r <= {4{merge_flag_i[42]}};cu_merge_idx_r <= {4{merge_idx_i[171:168]}}; end
7'd43 : begin cu_merge_flag_r <= {4{merge_flag_i[41]}};cu_merge_idx_r <= {4{merge_idx_i[167:164]}}; end
7'd44 : begin cu_merge_flag_r <= {4{merge_flag_i[40]}};cu_merge_idx_r <= {4{merge_idx_i[163:160]}}; end
7'd45 : begin cu_merge_flag_r <= {4{merge_flag_i[39]}};cu_merge_idx_r <= {4{merge_idx_i[159:156]}}; end
7'd46 : begin cu_merge_flag_r <= {4{merge_flag_i[38]}};cu_merge_idx_r <= {4{merge_idx_i[155:152]}}; end
7'd47 : begin cu_merge_flag_r <= {4{merge_flag_i[37]}};cu_merge_idx_r <= {4{merge_idx_i[151:148]}}; end
7'd48 : begin cu_merge_flag_r <= {4{merge_flag_i[36]}};cu_merge_idx_r <= {4{merge_idx_i[147:144]}}; end
7'd49 : begin cu_merge_flag_r <= {4{merge_flag_i[35]}};cu_merge_idx_r <= {4{merge_idx_i[143:140]}}; end
7'd50 : begin cu_merge_flag_r <= {4{merge_flag_i[34]}};cu_merge_idx_r <= {4{merge_idx_i[139:136]}}; end
7'd51 : begin cu_merge_flag_r <= {4{merge_flag_i[33]}};cu_merge_idx_r <= {4{merge_idx_i[135:132]}}; end
7'd52 : begin cu_merge_flag_r <= {4{merge_flag_i[32]}};cu_merge_idx_r <= {4{merge_idx_i[131:128]}}; end
7'd53 : begin cu_merge_flag_r <= {4{merge_flag_i[31]}};cu_merge_idx_r <= {4{merge_idx_i[127:124]}}; end
7'd54 : begin cu_merge_flag_r <= {4{merge_flag_i[30]}};cu_merge_idx_r <= {4{merge_idx_i[123:120]}}; end
7'd55 : begin cu_merge_flag_r <= {4{merge_flag_i[29]}};cu_merge_idx_r <= {4{merge_idx_i[119:116]}}; end
7'd56 : begin cu_merge_flag_r <= {4{merge_flag_i[28]}};cu_merge_idx_r <= {4{merge_idx_i[115:112]}}; end
7'd57 : begin cu_merge_flag_r <= {4{merge_flag_i[27]}};cu_merge_idx_r <= {4{merge_idx_i[111:108]}}; end
7'd58 : begin cu_merge_flag_r <= {4{merge_flag_i[26]}};cu_merge_idx_r <= {4{merge_idx_i[107:104]}}; end
7'd59 : begin cu_merge_flag_r <= {4{merge_flag_i[25]}};cu_merge_idx_r <= {4{merge_idx_i[103:100]}}; end
7'd60 : begin cu_merge_flag_r <= {4{merge_flag_i[24]}};cu_merge_idx_r <= {4{merge_idx_i[ 99: 96]}}; end
7'd61 : begin cu_merge_flag_r <= {4{merge_flag_i[23]}};cu_merge_idx_r <= {4{merge_idx_i[ 95: 92]}}; end
7'd62 : begin cu_merge_flag_r <= {4{merge_flag_i[22]}};cu_merge_idx_r <= {4{merge_idx_i[ 91: 88]}}; end
7'd63 : begin cu_merge_flag_r <= {4{merge_flag_i[21]}};cu_merge_idx_r <= {4{merge_idx_i[ 87: 84]}}; end
7'd64 : begin cu_merge_flag_r <= {4{merge_flag_i[20]}};cu_merge_idx_r <= {4{merge_idx_i[ 83: 80]}}; end
7'd65 : begin cu_merge_flag_r <= {4{merge_flag_i[19]}};cu_merge_idx_r <= {4{merge_idx_i[ 79: 76]}}; end
7'd66 : begin cu_merge_flag_r <= {4{merge_flag_i[18]}};cu_merge_idx_r <= {4{merge_idx_i[ 75: 72]}}; end
7'd67 : begin cu_merge_flag_r <= {4{merge_flag_i[17]}};cu_merge_idx_r <= {4{merge_idx_i[ 71: 68]}}; end
7'd68 : begin cu_merge_flag_r <= {4{merge_flag_i[16]}};cu_merge_idx_r <= {4{merge_idx_i[ 67: 64]}}; end
7'd69 : begin cu_merge_flag_r <= {4{merge_flag_i[15]}};cu_merge_idx_r <= {4{merge_idx_i[ 63: 60]}}; end
7'd70 : begin cu_merge_flag_r <= {4{merge_flag_i[14]}};cu_merge_idx_r <= {4{merge_idx_i[ 59: 56]}}; end
7'd71 : begin cu_merge_flag_r <= {4{merge_flag_i[13]}};cu_merge_idx_r <= {4{merge_idx_i[ 55: 52]}}; end
7'd72 : begin cu_merge_flag_r <= {4{merge_flag_i[12]}};cu_merge_idx_r <= {4{merge_idx_i[ 51: 48]}}; end
7'd73 : begin cu_merge_flag_r <= {4{merge_flag_i[11]}};cu_merge_idx_r <= {4{merge_idx_i[ 47: 44]}}; end
7'd74 : begin cu_merge_flag_r <= {4{merge_flag_i[10]}};cu_merge_idx_r <= {4{merge_idx_i[ 43: 40]}}; end
7'd75 : begin cu_merge_flag_r <= {4{merge_flag_i[ 9]}};cu_merge_idx_r <= {4{merge_idx_i[ 39: 36]}}; end
7'd76 : begin cu_merge_flag_r <= {4{merge_flag_i[ 8]}};cu_merge_idx_r <= {4{merge_idx_i[ 35: 32]}}; end
7'd77 : begin cu_merge_flag_r <= {4{merge_flag_i[ 7]}};cu_merge_idx_r <= {4{merge_idx_i[ 31: 28]}}; end
7'd78 : begin cu_merge_flag_r <= {4{merge_flag_i[ 6]}};cu_merge_idx_r <= {4{merge_idx_i[ 27: 24]}}; end
7'd79 : begin cu_merge_flag_r <= {4{merge_flag_i[ 5]}};cu_merge_idx_r <= {4{merge_idx_i[ 23: 20]}}; end
7'd80 : begin cu_merge_flag_r <= {4{merge_flag_i[ 4]}};cu_merge_idx_r <= {4{merge_idx_i[ 19: 16]}}; end
7'd81 : begin cu_merge_flag_r <= {4{merge_flag_i[ 3]}};cu_merge_idx_r <= {4{merge_idx_i[ 15: 12]}}; end
7'd82 : begin cu_merge_flag_r <= {4{merge_flag_i[ 2]}};cu_merge_idx_r <= {4{merge_idx_i[ 11: 8]}}; end
7'd83 : begin cu_merge_flag_r <= {4{merge_flag_i[ 1]}};cu_merge_idx_r <= {4{merge_idx_i[ 7: 4]}}; end
7'd84 : begin cu_merge_flag_r <= {4{merge_flag_i[ 0]}};cu_merge_idx_r <= {4{merge_idx_i[ 3: 0]}}; end
default : begin cu_merge_flag_r <= 4'b0 ;cu_merge_idx_r <= 12'd0 ; end
endcase
end
end
// cu_cbf_y_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_cbf_y_r <= 4'b0 ;
else begin
case(cu_idx_r[6:0])
7'd0 : begin cu_cbf_y_r <= {!(!luma_cbf_i[255:192]),!(!luma_cbf_i[191:128]),!(!luma_cbf_i[127:64 ]),!(!luma_cbf_i[ 63:0 ])}; end // 64x64
7'd1 : begin cu_cbf_y_r <= {!(!luma_cbf_i[255:240]),!(!luma_cbf_i[239:224]),!(!luma_cbf_i[223:208]),!(!luma_cbf_i[207:192])}; end // 32x32
7'd2 : begin cu_cbf_y_r <= {!(!luma_cbf_i[191:176]),!(!luma_cbf_i[175:160]),!(!luma_cbf_i[159:144]),!(!luma_cbf_i[143:128])}; end
7'd3 : begin cu_cbf_y_r <= {!(!luma_cbf_i[127:112]),!(!luma_cbf_i[111:96 ]),!(!luma_cbf_i[ 95:80 ]),!(!luma_cbf_i[ 79:64 ])}; end
7'd4 : begin cu_cbf_y_r <= {!(!luma_cbf_i[ 63:48 ]),!(!luma_cbf_i[ 47:32 ]),!(!luma_cbf_i[ 31:16 ]),!(!luma_cbf_i[ 15:0 ])}; end
7'd5 : begin cu_cbf_y_r <= {!(!luma_cbf_i[255:252]),!(!luma_cbf_i[251:248]),!(!luma_cbf_i[247:244]),!(!luma_cbf_i[243:240])}; end // 16x16
7'd6 : begin cu_cbf_y_r <= {!(!luma_cbf_i[239:236]),!(!luma_cbf_i[235:232]),!(!luma_cbf_i[231:228]),!(!luma_cbf_i[227:224])}; end
7'd7 : begin cu_cbf_y_r <= {!(!luma_cbf_i[223:220]),!(!luma_cbf_i[219:216]),!(!luma_cbf_i[215:212]),!(!luma_cbf_i[211:208])}; end
7'd8 : begin cu_cbf_y_r <= {!(!luma_cbf_i[207:204]),!(!luma_cbf_i[203:200]),!(!luma_cbf_i[199:196]),!(!luma_cbf_i[195:192])}; end
7'd9 : begin cu_cbf_y_r <= {!(!luma_cbf_i[191:188]),!(!luma_cbf_i[187:184]),!(!luma_cbf_i[183:180]),!(!luma_cbf_i[179:176])}; end
7'd10 : begin cu_cbf_y_r <= {!(!luma_cbf_i[175:172]),!(!luma_cbf_i[171:168]),!(!luma_cbf_i[167:164]),!(!luma_cbf_i[163:160])}; end
7'd11 : begin cu_cbf_y_r <= {!(!luma_cbf_i[159:156]),!(!luma_cbf_i[155:152]),!(!luma_cbf_i[151:148]),!(!luma_cbf_i[147:144])}; end
7'd12 : begin cu_cbf_y_r <= {!(!luma_cbf_i[143:140]),!(!luma_cbf_i[139:136]),!(!luma_cbf_i[135:132]),!(!luma_cbf_i[131:128])}; end
7'd13 : begin cu_cbf_y_r <= {!(!luma_cbf_i[127:124]),!(!luma_cbf_i[123:120]),!(!luma_cbf_i[119:116]),!(!luma_cbf_i[115:112])}; end
7'd14 : begin cu_cbf_y_r <= {!(!luma_cbf_i[111:108]),!(!luma_cbf_i[107:104]),!(!luma_cbf_i[103:100]),!(!luma_cbf_i[ 99: 96])}; end
7'd15 : begin cu_cbf_y_r <= {!(!luma_cbf_i[ 95: 92]),!(!luma_cbf_i[ 91: 88]),!(!luma_cbf_i[ 87: 84]),!(!luma_cbf_i[ 83: 80])}; end
7'd16 : begin cu_cbf_y_r <= {!(!luma_cbf_i[ 79: 76]),!(!luma_cbf_i[ 75: 72]),!(!luma_cbf_i[ 71: 68]),!(!luma_cbf_i[ 67: 64])}; end
7'd17 : begin cu_cbf_y_r <= {!(!luma_cbf_i[ 63: 60]),!(!luma_cbf_i[ 59: 56]),!(!luma_cbf_i[ 55: 52]),!(!luma_cbf_i[ 51: 48])}; end
7'd18 : begin cu_cbf_y_r <= {!(!luma_cbf_i[ 47: 44]),!(!luma_cbf_i[ 43: 40]),!(!luma_cbf_i[ 39: 36]),!(!luma_cbf_i[ 35: 32])}; end
7'd19 : begin cu_cbf_y_r <= {!(!luma_cbf_i[ 31: 28]),!(!luma_cbf_i[ 27: 24]),!(!luma_cbf_i[ 23: 20]),!(!luma_cbf_i[ 19: 16])}; end
7'd20 : begin cu_cbf_y_r <= {!(!luma_cbf_i[ 15: 12]),!(!luma_cbf_i[ 11: 8]),!(!luma_cbf_i[ 7: 4]),!(!luma_cbf_i[ 3: 0])}; end
7'd21 : begin cu_cbf_y_r <= { luma_cbf_i[ 255 ], luma_cbf_i[ 254 ], luma_cbf_i[ 253 ], luma_cbf_i[ 252 ]}; end // 8x8
7'd22 : begin cu_cbf_y_r <= { luma_cbf_i[ 251 ], luma_cbf_i[ 250 ], luma_cbf_i[ 249 ], luma_cbf_i[ 248 ]}; end
7'd23 : begin cu_cbf_y_r <= { luma_cbf_i[ 247 ], luma_cbf_i[ 246 ], luma_cbf_i[ 245 ], luma_cbf_i[ 244 ]}; end
7'd24 : begin cu_cbf_y_r <= { luma_cbf_i[ 243 ], luma_cbf_i[ 242 ], luma_cbf_i[ 241 ], luma_cbf_i[ 240 ]}; end
7'd25 : begin cu_cbf_y_r <= { luma_cbf_i[ 239 ], luma_cbf_i[ 238 ], luma_cbf_i[ 237 ], luma_cbf_i[ 236 ]}; end
7'd26 : begin cu_cbf_y_r <= { luma_cbf_i[ 235 ], luma_cbf_i[ 234 ], luma_cbf_i[ 233 ], luma_cbf_i[ 232 ]}; end
7'd27 : begin cu_cbf_y_r <= { luma_cbf_i[ 231 ], luma_cbf_i[ 230 ], luma_cbf_i[ 229 ], luma_cbf_i[ 228 ]}; end
7'd28 : begin cu_cbf_y_r <= { luma_cbf_i[ 227 ], luma_cbf_i[ 226 ], luma_cbf_i[ 225 ], luma_cbf_i[ 224 ]}; end
7'd29 : begin cu_cbf_y_r <= { luma_cbf_i[ 223 ], luma_cbf_i[ 222 ], luma_cbf_i[ 221 ], luma_cbf_i[ 220 ]}; end
7'd30 : begin cu_cbf_y_r <= { luma_cbf_i[ 219 ], luma_cbf_i[ 218 ], luma_cbf_i[ 217 ], luma_cbf_i[ 216 ]}; end
7'd31 : begin cu_cbf_y_r <= { luma_cbf_i[ 215 ], luma_cbf_i[ 214 ], luma_cbf_i[ 213 ], luma_cbf_i[ 212 ]}; end
7'd32 : begin cu_cbf_y_r <= { luma_cbf_i[ 211 ], luma_cbf_i[ 210 ], luma_cbf_i[ 209 ], luma_cbf_i[ 208 ]}; end
7'd33 : begin cu_cbf_y_r <= { luma_cbf_i[ 207 ], luma_cbf_i[ 206 ], luma_cbf_i[ 205 ], luma_cbf_i[ 204 ]}; end
7'd34 : begin cu_cbf_y_r <= { luma_cbf_i[ 203 ], luma_cbf_i[ 202 ], luma_cbf_i[ 201 ], luma_cbf_i[ 200 ]}; end
7'd35 : begin cu_cbf_y_r <= { luma_cbf_i[ 199 ], luma_cbf_i[ 198 ], luma_cbf_i[ 197 ], luma_cbf_i[ 196 ]}; end
7'd36 : begin cu_cbf_y_r <= { luma_cbf_i[ 195 ], luma_cbf_i[ 194 ], luma_cbf_i[ 193 ], luma_cbf_i[ 192 ]}; end
7'd37 : begin cu_cbf_y_r <= { luma_cbf_i[ 191 ], luma_cbf_i[ 190 ], luma_cbf_i[ 189 ], luma_cbf_i[ 188 ]}; end
7'd38 : begin cu_cbf_y_r <= { luma_cbf_i[ 187 ], luma_cbf_i[ 186 ], luma_cbf_i[ 185 ], luma_cbf_i[ 184 ]}; end
7'd39 : begin cu_cbf_y_r <= { luma_cbf_i[ 183 ], luma_cbf_i[ 182 ], luma_cbf_i[ 181 ], luma_cbf_i[ 180 ]}; end
7'd40 : begin cu_cbf_y_r <= { luma_cbf_i[ 179 ], luma_cbf_i[ 178 ], luma_cbf_i[ 177 ], luma_cbf_i[ 176 ]}; end
7'd41 : begin cu_cbf_y_r <= { luma_cbf_i[ 175 ], luma_cbf_i[ 174 ], luma_cbf_i[ 173 ], luma_cbf_i[ 172 ]}; end
7'd42 : begin cu_cbf_y_r <= { luma_cbf_i[ 171 ], luma_cbf_i[ 170 ], luma_cbf_i[ 169 ], luma_cbf_i[ 168 ]}; end
7'd43 : begin cu_cbf_y_r <= { luma_cbf_i[ 167 ], luma_cbf_i[ 166 ], luma_cbf_i[ 165 ], luma_cbf_i[ 164 ]}; end
7'd44 : begin cu_cbf_y_r <= { luma_cbf_i[ 163 ], luma_cbf_i[ 162 ], luma_cbf_i[ 161 ], luma_cbf_i[ 160 ]}; end
7'd45 : begin cu_cbf_y_r <= { luma_cbf_i[ 159 ], luma_cbf_i[ 158 ], luma_cbf_i[ 157 ], luma_cbf_i[ 156 ]}; end
7'd46 : begin cu_cbf_y_r <= { luma_cbf_i[ 155 ], luma_cbf_i[ 154 ], luma_cbf_i[ 153 ], luma_cbf_i[ 152 ]}; end
7'd47 : begin cu_cbf_y_r <= { luma_cbf_i[ 151 ], luma_cbf_i[ 150 ], luma_cbf_i[ 149 ], luma_cbf_i[ 148 ]}; end
7'd48 : begin cu_cbf_y_r <= { luma_cbf_i[ 147 ], luma_cbf_i[ 146 ], luma_cbf_i[ 145 ], luma_cbf_i[ 144 ]}; end
7'd49 : begin cu_cbf_y_r <= { luma_cbf_i[ 143 ], luma_cbf_i[ 142 ], luma_cbf_i[ 141 ], luma_cbf_i[ 140 ]}; end
7'd50 : begin cu_cbf_y_r <= { luma_cbf_i[ 139 ], luma_cbf_i[ 138 ], luma_cbf_i[ 137 ], luma_cbf_i[ 136 ]}; end
7'd51 : begin cu_cbf_y_r <= { luma_cbf_i[ 135 ], luma_cbf_i[ 134 ], luma_cbf_i[ 133 ], luma_cbf_i[ 132 ]}; end
7'd52 : begin cu_cbf_y_r <= { luma_cbf_i[ 131 ], luma_cbf_i[ 130 ], luma_cbf_i[ 129 ], luma_cbf_i[ 128 ]}; end
7'd53 : begin cu_cbf_y_r <= { luma_cbf_i[ 127 ], luma_cbf_i[ 126 ], luma_cbf_i[ 125 ], luma_cbf_i[ 124 ]}; end
7'd54 : begin cu_cbf_y_r <= { luma_cbf_i[ 123 ], luma_cbf_i[ 122 ], luma_cbf_i[ 121 ], luma_cbf_i[ 120 ]}; end
7'd55 : begin cu_cbf_y_r <= { luma_cbf_i[ 119 ], luma_cbf_i[ 118 ], luma_cbf_i[ 117 ], luma_cbf_i[ 116 ]}; end
7'd56 : begin cu_cbf_y_r <= { luma_cbf_i[ 115 ], luma_cbf_i[ 114 ], luma_cbf_i[ 113 ], luma_cbf_i[ 112 ]}; end
7'd57 : begin cu_cbf_y_r <= { luma_cbf_i[ 111 ], luma_cbf_i[ 110 ], luma_cbf_i[ 109 ], luma_cbf_i[ 108 ]}; end
7'd58 : begin cu_cbf_y_r <= { luma_cbf_i[ 107 ], luma_cbf_i[ 106 ], luma_cbf_i[ 105 ], luma_cbf_i[ 104 ]}; end
7'd59 : begin cu_cbf_y_r <= { luma_cbf_i[ 103 ], luma_cbf_i[ 102 ], luma_cbf_i[ 101 ], luma_cbf_i[ 100 ]}; end
7'd60 : begin cu_cbf_y_r <= { luma_cbf_i[ 99 ], luma_cbf_i[ 98 ], luma_cbf_i[ 97 ], luma_cbf_i[ 96 ]}; end
7'd61 : begin cu_cbf_y_r <= { luma_cbf_i[ 95 ], luma_cbf_i[ 94 ], luma_cbf_i[ 93 ], luma_cbf_i[ 92 ]}; end
7'd62 : begin cu_cbf_y_r <= { luma_cbf_i[ 91 ], luma_cbf_i[ 90 ], luma_cbf_i[ 89 ], luma_cbf_i[ 88 ]}; end
7'd63 : begin cu_cbf_y_r <= { luma_cbf_i[ 87 ], luma_cbf_i[ 86 ], luma_cbf_i[ 85 ], luma_cbf_i[ 84 ]}; end
7'd64 : begin cu_cbf_y_r <= { luma_cbf_i[ 83 ], luma_cbf_i[ 82 ], luma_cbf_i[ 81 ], luma_cbf_i[ 80 ]}; end
7'd65 : begin cu_cbf_y_r <= { luma_cbf_i[ 79 ], luma_cbf_i[ 78 ], luma_cbf_i[ 77 ], luma_cbf_i[ 76 ]}; end
7'd66 : begin cu_cbf_y_r <= { luma_cbf_i[ 75 ], luma_cbf_i[ 74 ], luma_cbf_i[ 73 ], luma_cbf_i[ 72 ]}; end
7'd67 : begin cu_cbf_y_r <= { luma_cbf_i[ 71 ], luma_cbf_i[ 70 ], luma_cbf_i[ 69 ], luma_cbf_i[ 68 ]}; end
7'd68 : begin cu_cbf_y_r <= { luma_cbf_i[ 67 ], luma_cbf_i[ 66 ], luma_cbf_i[ 65 ], luma_cbf_i[ 64 ]}; end
7'd69 : begin cu_cbf_y_r <= { luma_cbf_i[ 63 ], luma_cbf_i[ 62 ], luma_cbf_i[ 61 ], luma_cbf_i[ 60 ]}; end
7'd70 : begin cu_cbf_y_r <= { luma_cbf_i[ 59 ], luma_cbf_i[ 58 ], luma_cbf_i[ 57 ], luma_cbf_i[ 56 ]}; end
7'd71 : begin cu_cbf_y_r <= { luma_cbf_i[ 55 ], luma_cbf_i[ 54 ], luma_cbf_i[ 53 ], luma_cbf_i[ 52 ]}; end
7'd72 : begin cu_cbf_y_r <= { luma_cbf_i[ 51 ], luma_cbf_i[ 50 ], luma_cbf_i[ 49 ], luma_cbf_i[ 48 ]}; end
7'd73 : begin cu_cbf_y_r <= { luma_cbf_i[ 47 ], luma_cbf_i[ 46 ], luma_cbf_i[ 45 ], luma_cbf_i[ 44 ]}; end
7'd74 : begin cu_cbf_y_r <= { luma_cbf_i[ 43 ], luma_cbf_i[ 42 ], luma_cbf_i[ 41 ], luma_cbf_i[ 40 ]}; end
7'd75 : begin cu_cbf_y_r <= { luma_cbf_i[ 39 ], luma_cbf_i[ 38 ], luma_cbf_i[ 37 ], luma_cbf_i[ 36 ]}; end
7'd76 : begin cu_cbf_y_r <= { luma_cbf_i[ 35 ], luma_cbf_i[ 34 ], luma_cbf_i[ 33 ], luma_cbf_i[ 32 ]}; end
7'd77 : begin cu_cbf_y_r <= { luma_cbf_i[ 31 ], luma_cbf_i[ 30 ], luma_cbf_i[ 29 ], luma_cbf_i[ 28 ]}; end
7'd78 : begin cu_cbf_y_r <= { luma_cbf_i[ 27 ], luma_cbf_i[ 26 ], luma_cbf_i[ 25 ], luma_cbf_i[ 24 ]}; end
7'd79 : begin cu_cbf_y_r <= { luma_cbf_i[ 23 ], luma_cbf_i[ 22 ], luma_cbf_i[ 21 ], luma_cbf_i[ 20 ]}; end
7'd80 : begin cu_cbf_y_r <= { luma_cbf_i[ 19 ], luma_cbf_i[ 18 ], luma_cbf_i[ 17 ], luma_cbf_i[ 16 ]}; end
7'd81 : begin cu_cbf_y_r <= { luma_cbf_i[ 15 ], luma_cbf_i[ 14 ], luma_cbf_i[ 13 ], luma_cbf_i[ 12 ]}; end
7'd82 : begin cu_cbf_y_r <= { luma_cbf_i[ 11 ], luma_cbf_i[ 10 ], luma_cbf_i[ 9 ], luma_cbf_i[ 8 ]}; end
7'd83 : begin cu_cbf_y_r <= { luma_cbf_i[ 7 ], luma_cbf_i[ 6 ], luma_cbf_i[ 5 ], luma_cbf_i[ 4 ]}; end
7'd84 : begin cu_cbf_y_r <= { luma_cbf_i[ 3 ], luma_cbf_i[ 2 ], luma_cbf_i[ 1 ], luma_cbf_i[ 0 ]}; end
default : begin cu_cbf_y_r <= 4'b0 ; end
endcase
end
end
// cu_cbf_u_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_cbf_u_r <= 4'b0 ;
else begin
case(cu_idx_r[6:0])
7'd0 : begin cu_cbf_u_r <= {!(!cb_cbf_i[255:192]),!(!cb_cbf_i[191:128]),!(!cb_cbf_i[127:64 ]),!(!cb_cbf_i[ 63:0 ])}; end // 64x64
7'd1 : begin cu_cbf_u_r <= {!(!cb_cbf_i[255:240]),!(!cb_cbf_i[239:224]),!(!cb_cbf_i[223:208]),!(!cb_cbf_i[207:192])}; end // 32x32
7'd2 : begin cu_cbf_u_r <= {!(!cb_cbf_i[191:176]),!(!cb_cbf_i[175:160]),!(!cb_cbf_i[159:144]),!(!cb_cbf_i[143:128])}; end
7'd3 : begin cu_cbf_u_r <= {!(!cb_cbf_i[127:112]),!(!cb_cbf_i[111:96 ]),!(!cb_cbf_i[ 95:80 ]),!(!cb_cbf_i[ 79:64 ])}; end
7'd4 : begin cu_cbf_u_r <= {!(!cb_cbf_i[ 63:48 ]),!(!cb_cbf_i[ 47:32 ]),!(!cb_cbf_i[ 31:16 ]),!(!cb_cbf_i[ 15:0 ])}; end
7'd5 : begin cu_cbf_u_r <= {!(!cb_cbf_i[255:252]),!(!cb_cbf_i[251:248]),!(!cb_cbf_i[247:244]),!(!cb_cbf_i[243:240])}; end // 16x16
7'd6 : begin cu_cbf_u_r <= {!(!cb_cbf_i[239:236]),!(!cb_cbf_i[235:232]),!(!cb_cbf_i[231:228]),!(!cb_cbf_i[227:224])}; end
7'd7 : begin cu_cbf_u_r <= {!(!cb_cbf_i[223:220]),!(!cb_cbf_i[219:216]),!(!cb_cbf_i[215:212]),!(!cb_cbf_i[211:208])}; end
7'd8 : begin cu_cbf_u_r <= {!(!cb_cbf_i[207:204]),!(!cb_cbf_i[203:200]),!(!cb_cbf_i[199:196]),!(!cb_cbf_i[195:192])}; end
7'd9 : begin cu_cbf_u_r <= {!(!cb_cbf_i[191:188]),!(!cb_cbf_i[187:184]),!(!cb_cbf_i[183:180]),!(!cb_cbf_i[179:176])}; end
7'd10 : begin cu_cbf_u_r <= {!(!cb_cbf_i[175:172]),!(!cb_cbf_i[171:168]),!(!cb_cbf_i[167:164]),!(!cb_cbf_i[163:160])}; end
7'd11 : begin cu_cbf_u_r <= {!(!cb_cbf_i[159:156]),!(!cb_cbf_i[155:152]),!(!cb_cbf_i[151:148]),!(!cb_cbf_i[147:144])}; end
7'd12 : begin cu_cbf_u_r <= {!(!cb_cbf_i[143:140]),!(!cb_cbf_i[139:136]),!(!cb_cbf_i[135:132]),!(!cb_cbf_i[131:128])}; end
7'd13 : begin cu_cbf_u_r <= {!(!cb_cbf_i[127:124]),!(!cb_cbf_i[123:120]),!(!cb_cbf_i[119:116]),!(!cb_cbf_i[115:112])}; end
7'd14 : begin cu_cbf_u_r <= {!(!cb_cbf_i[111:108]),!(!cb_cbf_i[107:104]),!(!cb_cbf_i[103:100]),!(!cb_cbf_i[ 99: 96])}; end
7'd15 : begin cu_cbf_u_r <= {!(!cb_cbf_i[ 95: 92]),!(!cb_cbf_i[ 91: 88]),!(!cb_cbf_i[ 87: 84]),!(!cb_cbf_i[ 83: 80])}; end
7'd16 : begin cu_cbf_u_r <= {!(!cb_cbf_i[ 79: 76]),!(!cb_cbf_i[ 75: 72]),!(!cb_cbf_i[ 71: 68]),!(!cb_cbf_i[ 67: 64])}; end
7'd17 : begin cu_cbf_u_r <= {!(!cb_cbf_i[ 63: 60]),!(!cb_cbf_i[ 59: 56]),!(!cb_cbf_i[ 55: 52]),!(!cb_cbf_i[ 51: 48])}; end
7'd18 : begin cu_cbf_u_r <= {!(!cb_cbf_i[ 47: 44]),!(!cb_cbf_i[ 43: 40]),!(!cb_cbf_i[ 39: 36]),!(!cb_cbf_i[ 35: 32])}; end
7'd19 : begin cu_cbf_u_r <= {!(!cb_cbf_i[ 31: 28]),!(!cb_cbf_i[ 27: 24]),!(!cb_cbf_i[ 23: 20]),!(!cb_cbf_i[ 19: 16])}; end
7'd20 : begin cu_cbf_u_r <= {!(!cb_cbf_i[ 15: 12]),!(!cb_cbf_i[ 11: 8]),!(!cb_cbf_i[ 7: 4]),!(!cb_cbf_i[ 3: 0])}; end
7'd21 : begin cu_cbf_u_r <= { cb_cbf_i[ 255 ], cb_cbf_i[ 254 ], cb_cbf_i[ 253 ], cb_cbf_i[ 252 ]}; end // 8x8
7'd22 : begin cu_cbf_u_r <= { cb_cbf_i[ 251 ], cb_cbf_i[ 250 ], cb_cbf_i[ 249 ], cb_cbf_i[ 248 ]}; end
7'd23 : begin cu_cbf_u_r <= { cb_cbf_i[ 247 ], cb_cbf_i[ 246 ], cb_cbf_i[ 245 ], cb_cbf_i[ 244 ]}; end
7'd24 : begin cu_cbf_u_r <= { cb_cbf_i[ 243 ], cb_cbf_i[ 242 ], cb_cbf_i[ 241 ], cb_cbf_i[ 240 ]}; end
7'd25 : begin cu_cbf_u_r <= { cb_cbf_i[ 239 ], cb_cbf_i[ 238 ], cb_cbf_i[ 237 ], cb_cbf_i[ 236 ]}; end
7'd26 : begin cu_cbf_u_r <= { cb_cbf_i[ 235 ], cb_cbf_i[ 234 ], cb_cbf_i[ 233 ], cb_cbf_i[ 232 ]}; end
7'd27 : begin cu_cbf_u_r <= { cb_cbf_i[ 231 ], cb_cbf_i[ 230 ], cb_cbf_i[ 229 ], cb_cbf_i[ 228 ]}; end
7'd28 : begin cu_cbf_u_r <= { cb_cbf_i[ 227 ], cb_cbf_i[ 226 ], cb_cbf_i[ 225 ], cb_cbf_i[ 224 ]}; end
7'd29 : begin cu_cbf_u_r <= { cb_cbf_i[ 223 ], cb_cbf_i[ 222 ], cb_cbf_i[ 221 ], cb_cbf_i[ 220 ]}; end
7'd30 : begin cu_cbf_u_r <= { cb_cbf_i[ 219 ], cb_cbf_i[ 218 ], cb_cbf_i[ 217 ], cb_cbf_i[ 216 ]}; end
7'd31 : begin cu_cbf_u_r <= { cb_cbf_i[ 215 ], cb_cbf_i[ 214 ], cb_cbf_i[ 213 ], cb_cbf_i[ 212 ]}; end
7'd32 : begin cu_cbf_u_r <= { cb_cbf_i[ 211 ], cb_cbf_i[ 210 ], cb_cbf_i[ 209 ], cb_cbf_i[ 208 ]}; end
7'd33 : begin cu_cbf_u_r <= { cb_cbf_i[ 207 ], cb_cbf_i[ 206 ], cb_cbf_i[ 205 ], cb_cbf_i[ 204 ]}; end
7'd34 : begin cu_cbf_u_r <= { cb_cbf_i[ 203 ], cb_cbf_i[ 202 ], cb_cbf_i[ 201 ], cb_cbf_i[ 200 ]}; end
7'd35 : begin cu_cbf_u_r <= { cb_cbf_i[ 199 ], cb_cbf_i[ 198 ], cb_cbf_i[ 197 ], cb_cbf_i[ 196 ]}; end
7'd36 : begin cu_cbf_u_r <= { cb_cbf_i[ 195 ], cb_cbf_i[ 194 ], cb_cbf_i[ 193 ], cb_cbf_i[ 192 ]}; end
7'd37 : begin cu_cbf_u_r <= { cb_cbf_i[ 191 ], cb_cbf_i[ 190 ], cb_cbf_i[ 189 ], cb_cbf_i[ 188 ]}; end
7'd38 : begin cu_cbf_u_r <= { cb_cbf_i[ 187 ], cb_cbf_i[ 186 ], cb_cbf_i[ 185 ], cb_cbf_i[ 184 ]}; end
7'd39 : begin cu_cbf_u_r <= { cb_cbf_i[ 183 ], cb_cbf_i[ 182 ], cb_cbf_i[ 181 ], cb_cbf_i[ 180 ]}; end
7'd40 : begin cu_cbf_u_r <= { cb_cbf_i[ 179 ], cb_cbf_i[ 178 ], cb_cbf_i[ 177 ], cb_cbf_i[ 176 ]}; end
7'd41 : begin cu_cbf_u_r <= { cb_cbf_i[ 175 ], cb_cbf_i[ 174 ], cb_cbf_i[ 173 ], cb_cbf_i[ 172 ]}; end
7'd42 : begin cu_cbf_u_r <= { cb_cbf_i[ 171 ], cb_cbf_i[ 170 ], cb_cbf_i[ 169 ], cb_cbf_i[ 168 ]}; end
7'd43 : begin cu_cbf_u_r <= { cb_cbf_i[ 167 ], cb_cbf_i[ 166 ], cb_cbf_i[ 165 ], cb_cbf_i[ 164 ]}; end
7'd44 : begin cu_cbf_u_r <= { cb_cbf_i[ 163 ], cb_cbf_i[ 162 ], cb_cbf_i[ 161 ], cb_cbf_i[ 160 ]}; end
7'd45 : begin cu_cbf_u_r <= { cb_cbf_i[ 159 ], cb_cbf_i[ 158 ], cb_cbf_i[ 157 ], cb_cbf_i[ 156 ]}; end
7'd46 : begin cu_cbf_u_r <= { cb_cbf_i[ 155 ], cb_cbf_i[ 154 ], cb_cbf_i[ 153 ], cb_cbf_i[ 152 ]}; end
7'd47 : begin cu_cbf_u_r <= { cb_cbf_i[ 151 ], cb_cbf_i[ 150 ], cb_cbf_i[ 149 ], cb_cbf_i[ 148 ]}; end
7'd48 : begin cu_cbf_u_r <= { cb_cbf_i[ 147 ], cb_cbf_i[ 146 ], cb_cbf_i[ 145 ], cb_cbf_i[ 144 ]}; end
7'd49 : begin cu_cbf_u_r <= { cb_cbf_i[ 143 ], cb_cbf_i[ 142 ], cb_cbf_i[ 141 ], cb_cbf_i[ 140 ]}; end
7'd50 : begin cu_cbf_u_r <= { cb_cbf_i[ 139 ], cb_cbf_i[ 138 ], cb_cbf_i[ 137 ], cb_cbf_i[ 136 ]}; end
7'd51 : begin cu_cbf_u_r <= { cb_cbf_i[ 135 ], cb_cbf_i[ 134 ], cb_cbf_i[ 133 ], cb_cbf_i[ 132 ]}; end
7'd52 : begin cu_cbf_u_r <= { cb_cbf_i[ 131 ], cb_cbf_i[ 130 ], cb_cbf_i[ 129 ], cb_cbf_i[ 128 ]}; end
7'd53 : begin cu_cbf_u_r <= { cb_cbf_i[ 127 ], cb_cbf_i[ 126 ], cb_cbf_i[ 125 ], cb_cbf_i[ 124 ]}; end
7'd54 : begin cu_cbf_u_r <= { cb_cbf_i[ 123 ], cb_cbf_i[ 122 ], cb_cbf_i[ 121 ], cb_cbf_i[ 120 ]}; end
7'd55 : begin cu_cbf_u_r <= { cb_cbf_i[ 119 ], cb_cbf_i[ 118 ], cb_cbf_i[ 117 ], cb_cbf_i[ 116 ]}; end
7'd56 : begin cu_cbf_u_r <= { cb_cbf_i[ 115 ], cb_cbf_i[ 114 ], cb_cbf_i[ 113 ], cb_cbf_i[ 112 ]}; end
7'd57 : begin cu_cbf_u_r <= { cb_cbf_i[ 111 ], cb_cbf_i[ 110 ], cb_cbf_i[ 109 ], cb_cbf_i[ 108 ]}; end
7'd58 : begin cu_cbf_u_r <= { cb_cbf_i[ 107 ], cb_cbf_i[ 106 ], cb_cbf_i[ 105 ], cb_cbf_i[ 104 ]}; end
7'd59 : begin cu_cbf_u_r <= { cb_cbf_i[ 103 ], cb_cbf_i[ 102 ], cb_cbf_i[ 101 ], cb_cbf_i[ 100 ]}; end
7'd60 : begin cu_cbf_u_r <= { cb_cbf_i[ 99 ], cb_cbf_i[ 98 ], cb_cbf_i[ 97 ], cb_cbf_i[ 96 ]}; end
7'd61 : begin cu_cbf_u_r <= { cb_cbf_i[ 95 ], cb_cbf_i[ 94 ], cb_cbf_i[ 93 ], cb_cbf_i[ 92 ]}; end
7'd62 : begin cu_cbf_u_r <= { cb_cbf_i[ 91 ], cb_cbf_i[ 90 ], cb_cbf_i[ 89 ], cb_cbf_i[ 88 ]}; end
7'd63 : begin cu_cbf_u_r <= { cb_cbf_i[ 87 ], cb_cbf_i[ 86 ], cb_cbf_i[ 85 ], cb_cbf_i[ 84 ]}; end
7'd64 : begin cu_cbf_u_r <= { cb_cbf_i[ 83 ], cb_cbf_i[ 82 ], cb_cbf_i[ 81 ], cb_cbf_i[ 80 ]}; end
7'd65 : begin cu_cbf_u_r <= { cb_cbf_i[ 79 ], cb_cbf_i[ 78 ], cb_cbf_i[ 77 ], cb_cbf_i[ 76 ]}; end
7'd66 : begin cu_cbf_u_r <= { cb_cbf_i[ 75 ], cb_cbf_i[ 74 ], cb_cbf_i[ 73 ], cb_cbf_i[ 72 ]}; end
7'd67 : begin cu_cbf_u_r <= { cb_cbf_i[ 71 ], cb_cbf_i[ 70 ], cb_cbf_i[ 69 ], cb_cbf_i[ 68 ]}; end
7'd68 : begin cu_cbf_u_r <= { cb_cbf_i[ 67 ], cb_cbf_i[ 66 ], cb_cbf_i[ 65 ], cb_cbf_i[ 64 ]}; end
7'd69 : begin cu_cbf_u_r <= { cb_cbf_i[ 63 ], cb_cbf_i[ 62 ], cb_cbf_i[ 61 ], cb_cbf_i[ 60 ]}; end
7'd70 : begin cu_cbf_u_r <= { cb_cbf_i[ 59 ], cb_cbf_i[ 58 ], cb_cbf_i[ 57 ], cb_cbf_i[ 56 ]}; end
7'd71 : begin cu_cbf_u_r <= { cb_cbf_i[ 55 ], cb_cbf_i[ 54 ], cb_cbf_i[ 53 ], cb_cbf_i[ 52 ]}; end
7'd72 : begin cu_cbf_u_r <= { cb_cbf_i[ 51 ], cb_cbf_i[ 50 ], cb_cbf_i[ 49 ], cb_cbf_i[ 48 ]}; end
7'd73 : begin cu_cbf_u_r <= { cb_cbf_i[ 47 ], cb_cbf_i[ 46 ], cb_cbf_i[ 45 ], cb_cbf_i[ 44 ]}; end
7'd74 : begin cu_cbf_u_r <= { cb_cbf_i[ 43 ], cb_cbf_i[ 42 ], cb_cbf_i[ 41 ], cb_cbf_i[ 40 ]}; end
7'd75 : begin cu_cbf_u_r <= { cb_cbf_i[ 39 ], cb_cbf_i[ 38 ], cb_cbf_i[ 37 ], cb_cbf_i[ 36 ]}; end
7'd76 : begin cu_cbf_u_r <= { cb_cbf_i[ 35 ], cb_cbf_i[ 34 ], cb_cbf_i[ 33 ], cb_cbf_i[ 32 ]}; end
7'd77 : begin cu_cbf_u_r <= { cb_cbf_i[ 31 ], cb_cbf_i[ 30 ], cb_cbf_i[ 29 ], cb_cbf_i[ 28 ]}; end
7'd78 : begin cu_cbf_u_r <= { cb_cbf_i[ 27 ], cb_cbf_i[ 26 ], cb_cbf_i[ 25 ], cb_cbf_i[ 24 ]}; end
7'd79 : begin cu_cbf_u_r <= { cb_cbf_i[ 23 ], cb_cbf_i[ 22 ], cb_cbf_i[ 21 ], cb_cbf_i[ 20 ]}; end
7'd80 : begin cu_cbf_u_r <= { cb_cbf_i[ 19 ], cb_cbf_i[ 18 ], cb_cbf_i[ 17 ], cb_cbf_i[ 16 ]}; end
7'd81 : begin cu_cbf_u_r <= { cb_cbf_i[ 15 ], cb_cbf_i[ 14 ], cb_cbf_i[ 13 ], cb_cbf_i[ 12 ]}; end
7'd82 : begin cu_cbf_u_r <= { cb_cbf_i[ 11 ], cb_cbf_i[ 10 ], cb_cbf_i[ 9 ], cb_cbf_i[ 8 ]}; end
7'd83 : begin cu_cbf_u_r <= { cb_cbf_i[ 7 ], cb_cbf_i[ 6 ], cb_cbf_i[ 5 ], cb_cbf_i[ 4 ]}; end
7'd84 : begin cu_cbf_u_r <= { cb_cbf_i[ 3 ], cb_cbf_i[ 2 ], cb_cbf_i[ 1 ], cb_cbf_i[ 0 ]}; end
default : begin cu_cbf_u_r <= 4'b0 ; end
endcase
end
end
// cu_cbf_v_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_cbf_v_r <= 4'b0 ;
else begin
case(cu_idx_r[6:0])
7'd0 : begin cu_cbf_v_r <= {!(!cr_cbf_i[255:192]),!(!cr_cbf_i[191:128]),!(!cr_cbf_i[127:64 ]),!(!cr_cbf_i[ 63:0 ])}; end // 64x64
7'd1 : begin cu_cbf_v_r <= {!(!cr_cbf_i[255:240]),!(!cr_cbf_i[239:224]),!(!cr_cbf_i[223:208]),!(!cr_cbf_i[207:192])}; end // 32x32
7'd2 : begin cu_cbf_v_r <= {!(!cr_cbf_i[191:176]),!(!cr_cbf_i[175:160]),!(!cr_cbf_i[159:144]),!(!cr_cbf_i[143:128])}; end
7'd3 : begin cu_cbf_v_r <= {!(!cr_cbf_i[127:112]),!(!cr_cbf_i[111:96 ]),!(!cr_cbf_i[ 95:80 ]),!(!cr_cbf_i[ 79:64 ])}; end
7'd4 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 63:48 ]),!(!cr_cbf_i[ 47:32 ]),!(!cr_cbf_i[ 31:16 ]),!(!cr_cbf_i[ 15:0 ])}; end
7'd5 : begin cu_cbf_v_r <= {!(!cr_cbf_i[255:252]),!(!cr_cbf_i[251:248]),!(!cr_cbf_i[247:244]),!(!cr_cbf_i[243:240])}; end // 16x16
7'd6 : begin cu_cbf_v_r <= {!(!cr_cbf_i[239:236]),!(!cr_cbf_i[235:232]),!(!cr_cbf_i[231:228]),!(!cr_cbf_i[227:224])}; end
7'd7 : begin cu_cbf_v_r <= {!(!cr_cbf_i[223:220]),!(!cr_cbf_i[219:216]),!(!cr_cbf_i[215:212]),!(!cr_cbf_i[211:208])}; end
7'd8 : begin cu_cbf_v_r <= {!(!cr_cbf_i[207:204]),!(!cr_cbf_i[203:200]),!(!cr_cbf_i[199:196]),!(!cr_cbf_i[195:192])}; end
7'd9 : begin cu_cbf_v_r <= {!(!cr_cbf_i[191:188]),!(!cr_cbf_i[187:184]),!(!cr_cbf_i[183:180]),!(!cr_cbf_i[179:176])}; end
7'd10 : begin cu_cbf_v_r <= {!(!cr_cbf_i[175:172]),!(!cr_cbf_i[171:168]),!(!cr_cbf_i[167:164]),!(!cr_cbf_i[163:160])}; end
7'd11 : begin cu_cbf_v_r <= {!(!cr_cbf_i[159:156]),!(!cr_cbf_i[155:152]),!(!cr_cbf_i[151:148]),!(!cr_cbf_i[147:144])}; end
7'd12 : begin cu_cbf_v_r <= {!(!cr_cbf_i[143:140]),!(!cr_cbf_i[139:136]),!(!cr_cbf_i[135:132]),!(!cr_cbf_i[131:128])}; end
7'd13 : begin cu_cbf_v_r <= {!(!cr_cbf_i[127:124]),!(!cr_cbf_i[123:120]),!(!cr_cbf_i[119:116]),!(!cr_cbf_i[115:112])}; end
7'd14 : begin cu_cbf_v_r <= {!(!cr_cbf_i[111:108]),!(!cr_cbf_i[107:104]),!(!cr_cbf_i[103:100]),!(!cr_cbf_i[ 99: 96])}; end
7'd15 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 95: 92]),!(!cr_cbf_i[ 91: 88]),!(!cr_cbf_i[ 87: 84]),!(!cr_cbf_i[ 83: 80])}; end
7'd16 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 79: 76]),!(!cr_cbf_i[ 75: 72]),!(!cr_cbf_i[ 71: 68]),!(!cr_cbf_i[ 67: 64])}; end
7'd17 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 63: 60]),!(!cr_cbf_i[ 59: 56]),!(!cr_cbf_i[ 55: 52]),!(!cr_cbf_i[ 51: 48])}; end
7'd18 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 47: 44]),!(!cr_cbf_i[ 43: 40]),!(!cr_cbf_i[ 39: 36]),!(!cr_cbf_i[ 35: 32])}; end
7'd19 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 31: 28]),!(!cr_cbf_i[ 27: 24]),!(!cr_cbf_i[ 23: 20]),!(!cr_cbf_i[ 19: 16])}; end
7'd20 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 15: 12]),!(!cr_cbf_i[ 11: 8]),!(!cr_cbf_i[ 7: 4]),!(!cr_cbf_i[ 3: 0])}; end
7'd21 : begin cu_cbf_v_r <= { cr_cbf_i[ 255 ], cr_cbf_i[ 254 ], cr_cbf_i[ 253 ], cr_cbf_i[ 252 ]}; end // 8x8
7'd22 : begin cu_cbf_v_r <= { cr_cbf_i[ 251 ], cr_cbf_i[ 250 ], cr_cbf_i[ 249 ], cr_cbf_i[ 248 ]}; end
7'd23 : begin cu_cbf_v_r <= { cr_cbf_i[ 247 ], cr_cbf_i[ 246 ], cr_cbf_i[ 245 ], cr_cbf_i[ 244 ]}; end
7'd24 : begin cu_cbf_v_r <= { cr_cbf_i[ 243 ], cr_cbf_i[ 242 ], cr_cbf_i[ 241 ], cr_cbf_i[ 240 ]}; end
7'd25 : begin cu_cbf_v_r <= { cr_cbf_i[ 239 ], cr_cbf_i[ 238 ], cr_cbf_i[ 237 ], cr_cbf_i[ 236 ]}; end
7'd26 : begin cu_cbf_v_r <= { cr_cbf_i[ 235 ], cr_cbf_i[ 234 ], cr_cbf_i[ 233 ], cr_cbf_i[ 232 ]}; end
7'd27 : begin cu_cbf_v_r <= { cr_cbf_i[ 231 ], cr_cbf_i[ 230 ], cr_cbf_i[ 229 ], cr_cbf_i[ 228 ]}; end
7'd28 : begin cu_cbf_v_r <= { cr_cbf_i[ 227 ], cr_cbf_i[ 226 ], cr_cbf_i[ 225 ], cr_cbf_i[ 224 ]}; end
7'd29 : begin cu_cbf_v_r <= { cr_cbf_i[ 223 ], cr_cbf_i[ 222 ], cr_cbf_i[ 221 ], cr_cbf_i[ 220 ]}; end
7'd30 : begin cu_cbf_v_r <= { cr_cbf_i[ 219 ], cr_cbf_i[ 218 ], cr_cbf_i[ 217 ], cr_cbf_i[ 216 ]}; end
7'd31 : begin cu_cbf_v_r <= { cr_cbf_i[ 215 ], cr_cbf_i[ 214 ], cr_cbf_i[ 213 ], cr_cbf_i[ 212 ]}; end
7'd32 : begin cu_cbf_v_r <= { cr_cbf_i[ 211 ], cr_cbf_i[ 210 ], cr_cbf_i[ 209 ], cr_cbf_i[ 208 ]}; end
7'd33 : begin cu_cbf_v_r <= { cr_cbf_i[ 207 ], cr_cbf_i[ 206 ], cr_cbf_i[ 205 ], cr_cbf_i[ 204 ]}; end
7'd34 : begin cu_cbf_v_r <= { cr_cbf_i[ 203 ], cr_cbf_i[ 202 ], cr_cbf_i[ 201 ], cr_cbf_i[ 200 ]}; end
7'd35 : begin cu_cbf_v_r <= { cr_cbf_i[ 199 ], cr_cbf_i[ 198 ], cr_cbf_i[ 197 ], cr_cbf_i[ 196 ]}; end
7'd36 : begin cu_cbf_v_r <= { cr_cbf_i[ 195 ], cr_cbf_i[ 194 ], cr_cbf_i[ 193 ], cr_cbf_i[ 192 ]}; end
7'd37 : begin cu_cbf_v_r <= { cr_cbf_i[ 191 ], cr_cbf_i[ 190 ], cr_cbf_i[ 189 ], cr_cbf_i[ 188 ]}; end
7'd38 : begin cu_cbf_v_r <= { cr_cbf_i[ 187 ], cr_cbf_i[ 186 ], cr_cbf_i[ 185 ], cr_cbf_i[ 184 ]}; end
7'd39 : begin cu_cbf_v_r <= { cr_cbf_i[ 183 ], cr_cbf_i[ 182 ], cr_cbf_i[ 181 ], cr_cbf_i[ 180 ]}; end
7'd40 : begin cu_cbf_v_r <= { cr_cbf_i[ 179 ], cr_cbf_i[ 178 ], cr_cbf_i[ 177 ], cr_cbf_i[ 176 ]}; end
7'd41 : begin cu_cbf_v_r <= { cr_cbf_i[ 175 ], cr_cbf_i[ 174 ], cr_cbf_i[ 173 ], cr_cbf_i[ 172 ]}; end
7'd42 : begin cu_cbf_v_r <= { cr_cbf_i[ 171 ], cr_cbf_i[ 170 ], cr_cbf_i[ 169 ], cr_cbf_i[ 168 ]}; end
7'd43 : begin cu_cbf_v_r <= { cr_cbf_i[ 167 ], cr_cbf_i[ 166 ], cr_cbf_i[ 165 ], cr_cbf_i[ 164 ]}; end
7'd44 : begin cu_cbf_v_r <= { cr_cbf_i[ 163 ], cr_cbf_i[ 162 ], cr_cbf_i[ 161 ], cr_cbf_i[ 160 ]}; end
7'd45 : begin cu_cbf_v_r <= { cr_cbf_i[ 159 ], cr_cbf_i[ 158 ], cr_cbf_i[ 157 ], cr_cbf_i[ 156 ]}; end
7'd46 : begin cu_cbf_v_r <= { cr_cbf_i[ 155 ], cr_cbf_i[ 154 ], cr_cbf_i[ 153 ], cr_cbf_i[ 152 ]}; end
7'd47 : begin cu_cbf_v_r <= { cr_cbf_i[ 151 ], cr_cbf_i[ 150 ], cr_cbf_i[ 149 ], cr_cbf_i[ 148 ]}; end
7'd48 : begin cu_cbf_v_r <= { cr_cbf_i[ 147 ], cr_cbf_i[ 146 ], cr_cbf_i[ 145 ], cr_cbf_i[ 144 ]}; end
7'd49 : begin cu_cbf_v_r <= { cr_cbf_i[ 143 ], cr_cbf_i[ 142 ], cr_cbf_i[ 141 ], cr_cbf_i[ 140 ]}; end
7'd50 : begin cu_cbf_v_r <= { cr_cbf_i[ 139 ], cr_cbf_i[ 138 ], cr_cbf_i[ 137 ], cr_cbf_i[ 136 ]}; end
7'd51 : begin cu_cbf_v_r <= { cr_cbf_i[ 135 ], cr_cbf_i[ 134 ], cr_cbf_i[ 133 ], cr_cbf_i[ 132 ]}; end
7'd52 : begin cu_cbf_v_r <= { cr_cbf_i[ 131 ], cr_cbf_i[ 130 ], cr_cbf_i[ 129 ], cr_cbf_i[ 128 ]}; end
7'd53 : begin cu_cbf_v_r <= { cr_cbf_i[ 127 ], cr_cbf_i[ 126 ], cr_cbf_i[ 125 ], cr_cbf_i[ 124 ]}; end
7'd54 : begin cu_cbf_v_r <= { cr_cbf_i[ 123 ], cr_cbf_i[ 122 ], cr_cbf_i[ 121 ], cr_cbf_i[ 120 ]}; end
7'd55 : begin cu_cbf_v_r <= { cr_cbf_i[ 119 ], cr_cbf_i[ 118 ], cr_cbf_i[ 117 ], cr_cbf_i[ 116 ]}; end
7'd56 : begin cu_cbf_v_r <= { cr_cbf_i[ 115 ], cr_cbf_i[ 114 ], cr_cbf_i[ 113 ], cr_cbf_i[ 112 ]}; end
7'd57 : begin cu_cbf_v_r <= { cr_cbf_i[ 111 ], cr_cbf_i[ 110 ], cr_cbf_i[ 109 ], cr_cbf_i[ 108 ]}; end
7'd58 : begin cu_cbf_v_r <= { cr_cbf_i[ 107 ], cr_cbf_i[ 106 ], cr_cbf_i[ 105 ], cr_cbf_i[ 104 ]}; end
7'd59 : begin cu_cbf_v_r <= { cr_cbf_i[ 103 ], cr_cbf_i[ 102 ], cr_cbf_i[ 101 ], cr_cbf_i[ 100 ]}; end
7'd60 : begin cu_cbf_v_r <= { cr_cbf_i[ 99 ], cr_cbf_i[ 98 ], cr_cbf_i[ 97 ], cr_cbf_i[ 96 ]}; end
7'd61 : begin cu_cbf_v_r <= { cr_cbf_i[ 95 ], cr_cbf_i[ 94 ], cr_cbf_i[ 93 ], cr_cbf_i[ 92 ]}; end
7'd62 : begin cu_cbf_v_r <= { cr_cbf_i[ 91 ], cr_cbf_i[ 90 ], cr_cbf_i[ 89 ], cr_cbf_i[ 88 ]}; end
7'd63 : begin cu_cbf_v_r <= { cr_cbf_i[ 87 ], cr_cbf_i[ 86 ], cr_cbf_i[ 85 ], cr_cbf_i[ 84 ]}; end
7'd64 : begin cu_cbf_v_r <= { cr_cbf_i[ 83 ], cr_cbf_i[ 82 ], cr_cbf_i[ 81 ], cr_cbf_i[ 80 ]}; end
7'd65 : begin cu_cbf_v_r <= { cr_cbf_i[ 79 ], cr_cbf_i[ 78 ], cr_cbf_i[ 77 ], cr_cbf_i[ 76 ]}; end
7'd66 : begin cu_cbf_v_r <= { cr_cbf_i[ 75 ], cr_cbf_i[ 74 ], cr_cbf_i[ 73 ], cr_cbf_i[ 72 ]}; end
7'd67 : begin cu_cbf_v_r <= { cr_cbf_i[ 71 ], cr_cbf_i[ 70 ], cr_cbf_i[ 69 ], cr_cbf_i[ 68 ]}; end
7'd68 : begin cu_cbf_v_r <= { cr_cbf_i[ 67 ], cr_cbf_i[ 66 ], cr_cbf_i[ 65 ], cr_cbf_i[ 64 ]}; end
7'd69 : begin cu_cbf_v_r <= { cr_cbf_i[ 63 ], cr_cbf_i[ 62 ], cr_cbf_i[ 61 ], cr_cbf_i[ 60 ]}; end
7'd70 : begin cu_cbf_v_r <= { cr_cbf_i[ 59 ], cr_cbf_i[ 58 ], cr_cbf_i[ 57 ], cr_cbf_i[ 56 ]}; end
7'd71 : begin cu_cbf_v_r <= { cr_cbf_i[ 55 ], cr_cbf_i[ 54 ], cr_cbf_i[ 53 ], cr_cbf_i[ 52 ]}; end
7'd72 : begin cu_cbf_v_r <= { cr_cbf_i[ 51 ], cr_cbf_i[ 50 ], cr_cbf_i[ 49 ], cr_cbf_i[ 48 ]}; end
7'd73 : begin cu_cbf_v_r <= { cr_cbf_i[ 47 ], cr_cbf_i[ 46 ], cr_cbf_i[ 45 ], cr_cbf_i[ 44 ]}; end
7'd74 : begin cu_cbf_v_r <= { cr_cbf_i[ 43 ], cr_cbf_i[ 42 ], cr_cbf_i[ 41 ], cr_cbf_i[ 40 ]}; end
7'd75 : begin cu_cbf_v_r <= { cr_cbf_i[ 39 ], cr_cbf_i[ 38 ], cr_cbf_i[ 37 ], cr_cbf_i[ 36 ]}; end
7'd76 : begin cu_cbf_v_r <= { cr_cbf_i[ 35 ], cr_cbf_i[ 34 ], cr_cbf_i[ 33 ], cr_cbf_i[ 32 ]}; end
7'd77 : begin cu_cbf_v_r <= { cr_cbf_i[ 31 ], cr_cbf_i[ 30 ], cr_cbf_i[ 29 ], cr_cbf_i[ 28 ]}; end
7'd78 : begin cu_cbf_v_r <= { cr_cbf_i[ 27 ], cr_cbf_i[ 26 ], cr_cbf_i[ 25 ], cr_cbf_i[ 24 ]}; end
7'd79 : begin cu_cbf_v_r <= { cr_cbf_i[ 23 ], cr_cbf_i[ 22 ], cr_cbf_i[ 21 ], cr_cbf_i[ 20 ]}; end
7'd80 : begin cu_cbf_v_r <= { cr_cbf_i[ 19 ], cr_cbf_i[ 18 ], cr_cbf_i[ 17 ], cr_cbf_i[ 16 ]}; end
7'd81 : begin cu_cbf_v_r <= { cr_cbf_i[ 15 ], cr_cbf_i[ 14 ], cr_cbf_i[ 13 ], cr_cbf_i[ 12 ]}; end
7'd82 : begin cu_cbf_v_r <= { cr_cbf_i[ 11 ], cr_cbf_i[ 10 ], cr_cbf_i[ 9 ], cr_cbf_i[ 8 ]}; end
7'd83 : begin cu_cbf_v_r <= { cr_cbf_i[ 7 ], cr_cbf_i[ 6 ], cr_cbf_i[ 5 ], cr_cbf_i[ 4 ]}; end
7'd84 : begin cu_cbf_v_r <= { cr_cbf_i[ 3 ], cr_cbf_i[ 2 ], cr_cbf_i[ 1 ], cr_cbf_i[ 0 ]}; end
default : begin cu_cbf_v_r <= 4'b0 ; end
endcase
end
end
/*
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_cbf_u_r <= 4'b0 ;
else begin
case(cu_idx_r)
7'd0 : begin cu_cbf_u_r <= {!(!cu_cbf_i[63:48]),!(!cu_cbf_i[47:32]),!(!cu_cbf_i[31:16]),!(!cu_cbf_i[15: 0])}; end // 64x64
7'd1 : begin cu_cbf_u_r <= {!(!cu_cbf_i[63:60]),!(!cu_cbf_i[59:56]),!(!cu_cbf_i[55:52]),!(!cu_cbf_i[51:48])}; end // 32x32
7'd2 : begin cu_cbf_u_r <= {!(!cu_cbf_i[47:44]),!(!cu_cbf_i[43:40]),!(!cu_cbf_i[39:36]),!(!cu_cbf_i[35:32])}; end
7'd3 : begin cu_cbf_u_r <= {!(!cu_cbf_i[31:28]),!(!cu_cbf_i[27:24]),!(!cu_cbf_i[23:20]),!(!cu_cbf_i[19:16])}; end
7'd4 : begin cu_cbf_u_r <= {!(!cu_cbf_i[15:12]),!(!cu_cbf_i[11:8 ]),!(!cu_cbf_i[ 7:4 ]),!(!cu_cbf_i[ 3:0 ])}; end
7'd5 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 63 ]),!(!cu_cbf_i[ 62 ]),!(!cu_cbf_i[ 61 ]),!(!cu_cbf_i[ 60 ])}; end //16x16
7'd6 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 59 ]),!(!cu_cbf_i[ 58 ]),!(!cu_cbf_i[ 57 ]),!(!cu_cbf_i[ 56 ])}; end
7'd7 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 55 ]),!(!cu_cbf_i[ 54 ]),!(!cu_cbf_i[ 53 ]),!(!cu_cbf_i[ 52 ])}; end
7'd8 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 51 ]),!(!cu_cbf_i[ 50 ]),!(!cu_cbf_i[ 49 ]),!(!cu_cbf_i[ 48 ])}; end
7'd9 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 47 ]),!(!cu_cbf_i[ 46 ]),!(!cu_cbf_i[ 45 ]),!(!cu_cbf_i[ 44 ])}; end
7'd10 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 43 ]),!(!cu_cbf_i[ 42 ]),!(!cu_cbf_i[ 41 ]),!(!cu_cbf_i[ 40 ])}; end
7'd11 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 39 ]),!(!cu_cbf_i[ 38 ]),!(!cu_cbf_i[ 37 ]),!(!cu_cbf_i[ 36 ])}; end
7'd12 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 35 ]),!(!cu_cbf_i[ 34 ]),!(!cu_cbf_i[ 33 ]),!(!cu_cbf_i[ 32 ])}; end
7'd13 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 31 ]),!(!cu_cbf_i[ 30 ]),!(!cu_cbf_i[ 29 ]),!(!cu_cbf_i[ 28 ])}; end
7'd14 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 27 ]),!(!cu_cbf_i[ 26 ]),!(!cu_cbf_i[ 25 ]),!(!cu_cbf_i[ 24 ])}; end
7'd15 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 23 ]),!(!cu_cbf_i[ 22 ]),!(!cu_cbf_i[ 21 ]),!(!cu_cbf_i[ 20 ])}; end
7'd16 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 19 ]),!(!cu_cbf_i[ 18 ]),!(!cu_cbf_i[ 17 ]),!(!cu_cbf_i[ 16 ])}; end
7'd17 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 15 ]),!(!cu_cbf_i[ 14 ]),!(!cu_cbf_i[ 13 ]),!(!cu_cbf_i[ 12 ])}; end
7'd18 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 11 ]),!(!cu_cbf_i[ 10 ]),!(!cu_cbf_i[ 9 ]),!(!cu_cbf_i[ 8 ])}; end
7'd19 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 7 ]),!(!cu_cbf_i[ 6 ]),!(!cu_cbf_i[ 5 ]),!(!cu_cbf_i[ 4 ])}; end
7'd20 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 3 ]),!(!cu_cbf_i[ 2 ]),!(!cu_cbf_i[ 1 ]),!(!cu_cbf_i[ 0 ])}; end
7'd21 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 63 ]),!(!cu_cbf_i[ 63 ]),!(!cu_cbf_i[ 63 ]),!(!cu_cbf_i[ 63 ])}; end //8x8
7'd22 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 62 ]),!(!cu_cbf_i[ 62 ]),!(!cu_cbf_i[ 62 ]),!(!cu_cbf_i[ 62 ])}; end
7'd23 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 61 ]),!(!cu_cbf_i[ 61 ]),!(!cu_cbf_i[ 61 ]),!(!cu_cbf_i[ 61 ])}; end
7'd24 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 60 ]),!(!cu_cbf_i[ 60 ]),!(!cu_cbf_i[ 60 ]),!(!cu_cbf_i[ 60 ])}; end
7'd25 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 59 ]),!(!cu_cbf_i[ 59 ]),!(!cu_cbf_i[ 59 ]),!(!cu_cbf_i[ 59 ])}; end
7'd26 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 58 ]),!(!cu_cbf_i[ 58 ]),!(!cu_cbf_i[ 58 ]),!(!cu_cbf_i[ 58 ])}; end
7'd27 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 57 ]),!(!cu_cbf_i[ 57 ]),!(!cu_cbf_i[ 57 ]),!(!cu_cbf_i[ 57 ])}; end
7'd28 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 56 ]),!(!cu_cbf_i[ 56 ]),!(!cu_cbf_i[ 56 ]),!(!cu_cbf_i[ 56 ])}; end
7'd29 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 55 ]),!(!cu_cbf_i[ 55 ]),!(!cu_cbf_i[ 55 ]),!(!cu_cbf_i[ 55 ])}; end
7'd30 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 54 ]),!(!cu_cbf_i[ 54 ]),!(!cu_cbf_i[ 54 ]),!(!cu_cbf_i[ 54 ])}; end
7'd31 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 53 ]),!(!cu_cbf_i[ 53 ]),!(!cu_cbf_i[ 53 ]),!(!cu_cbf_i[ 53 ])}; end
7'd32 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 52 ]),!(!cu_cbf_i[ 52 ]),!(!cu_cbf_i[ 52 ]),!(!cu_cbf_i[ 52 ])}; end
7'd33 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 51 ]),!(!cu_cbf_i[ 51 ]),!(!cu_cbf_i[ 51 ]),!(!cu_cbf_i[ 51 ])}; end
7'd34 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 50 ]),!(!cu_cbf_i[ 50 ]),!(!cu_cbf_i[ 50 ]),!(!cu_cbf_i[ 50 ])}; end
7'd35 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 49 ]),!(!cu_cbf_i[ 49 ]),!(!cu_cbf_i[ 49 ]),!(!cu_cbf_i[ 49 ])}; end
7'd36 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 48 ]),!(!cu_cbf_i[ 48 ]),!(!cu_cbf_i[ 48 ]),!(!cu_cbf_i[ 48 ])}; end
7'd37 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 47 ]),!(!cu_cbf_i[ 47 ]),!(!cu_cbf_i[ 47 ]),!(!cu_cbf_i[ 47 ])}; end
7'd38 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 46 ]),!(!cu_cbf_i[ 46 ]),!(!cu_cbf_i[ 46 ]),!(!cu_cbf_i[ 46 ])}; end
7'd39 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 45 ]),!(!cu_cbf_i[ 45 ]),!(!cu_cbf_i[ 45 ]),!(!cu_cbf_i[ 45 ])}; end
7'd40 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 44 ]),!(!cu_cbf_i[ 44 ]),!(!cu_cbf_i[ 44 ]),!(!cu_cbf_i[ 44 ])}; end
7'd41 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 43 ]),!(!cu_cbf_i[ 43 ]),!(!cu_cbf_i[ 43 ]),!(!cu_cbf_i[ 43 ])}; end
7'd42 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 42 ]),!(!cu_cbf_i[ 42 ]),!(!cu_cbf_i[ 42 ]),!(!cu_cbf_i[ 42 ])}; end
7'd43 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 41 ]),!(!cu_cbf_i[ 41 ]),!(!cu_cbf_i[ 41 ]),!(!cu_cbf_i[ 41 ])}; end
7'd44 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 40 ]),!(!cu_cbf_i[ 40 ]),!(!cu_cbf_i[ 40 ]),!(!cu_cbf_i[ 40 ])}; end
7'd45 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 39 ]),!(!cu_cbf_i[ 39 ]),!(!cu_cbf_i[ 39 ]),!(!cu_cbf_i[ 39 ])}; end
7'd46 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 38 ]),!(!cu_cbf_i[ 38 ]),!(!cu_cbf_i[ 38 ]),!(!cu_cbf_i[ 38 ])}; end
7'd47 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 37 ]),!(!cu_cbf_i[ 37 ]),!(!cu_cbf_i[ 37 ]),!(!cu_cbf_i[ 37 ])}; end
7'd48 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 36 ]),!(!cu_cbf_i[ 36 ]),!(!cu_cbf_i[ 36 ]),!(!cu_cbf_i[ 36 ])}; end
7'd49 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 35 ]),!(!cu_cbf_i[ 35 ]),!(!cu_cbf_i[ 35 ]),!(!cu_cbf_i[ 35 ])}; end
7'd50 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 34 ]),!(!cu_cbf_i[ 34 ]),!(!cu_cbf_i[ 34 ]),!(!cu_cbf_i[ 34 ])}; end
7'd51 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 33 ]),!(!cu_cbf_i[ 33 ]),!(!cu_cbf_i[ 33 ]),!(!cu_cbf_i[ 33 ])}; end
7'd52 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 32 ]),!(!cu_cbf_i[ 32 ]),!(!cu_cbf_i[ 32 ]),!(!cu_cbf_i[ 32 ])}; end
7'd53 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 31 ]),!(!cu_cbf_i[ 31 ]),!(!cu_cbf_i[ 31 ]),!(!cu_cbf_i[ 31 ])}; end
7'd54 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 30 ]),!(!cu_cbf_i[ 30 ]),!(!cu_cbf_i[ 30 ]),!(!cu_cbf_i[ 30 ])}; end
7'd55 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 29 ]),!(!cu_cbf_i[ 29 ]),!(!cu_cbf_i[ 29 ]),!(!cu_cbf_i[ 29 ])}; end
7'd56 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 28 ]),!(!cu_cbf_i[ 28 ]),!(!cu_cbf_i[ 28 ]),!(!cu_cbf_i[ 28 ])}; end
7'd57 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 27 ]),!(!cu_cbf_i[ 27 ]),!(!cu_cbf_i[ 27 ]),!(!cu_cbf_i[ 27 ])}; end
7'd58 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 26 ]),!(!cu_cbf_i[ 26 ]),!(!cu_cbf_i[ 26 ]),!(!cu_cbf_i[ 26 ])}; end
7'd59 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 25 ]),!(!cu_cbf_i[ 25 ]),!(!cu_cbf_i[ 25 ]),!(!cu_cbf_i[ 25 ])}; end
7'd60 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 24 ]),!(!cu_cbf_i[ 24 ]),!(!cu_cbf_i[ 24 ]),!(!cu_cbf_i[ 24 ])}; end
7'd61 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 23 ]),!(!cu_cbf_i[ 23 ]),!(!cu_cbf_i[ 23 ]),!(!cu_cbf_i[ 23 ])}; end
7'd62 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 22 ]),!(!cu_cbf_i[ 22 ]),!(!cu_cbf_i[ 22 ]),!(!cu_cbf_i[ 22 ])}; end
7'd63 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 21 ]),!(!cu_cbf_i[ 21 ]),!(!cu_cbf_i[ 21 ]),!(!cu_cbf_i[ 21 ])}; end
7'd64 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 20 ]),!(!cu_cbf_i[ 20 ]),!(!cu_cbf_i[ 20 ]),!(!cu_cbf_i[ 20 ])}; end
7'd65 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 19 ]),!(!cu_cbf_i[ 19 ]),!(!cu_cbf_i[ 19 ]),!(!cu_cbf_i[ 19 ])}; end
7'd66 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 18 ]),!(!cu_cbf_i[ 18 ]),!(!cu_cbf_i[ 18 ]),!(!cu_cbf_i[ 18 ])}; end
7'd67 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 17 ]),!(!cu_cbf_i[ 17 ]),!(!cu_cbf_i[ 17 ]),!(!cu_cbf_i[ 17 ])}; end
7'd68 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 16 ]),!(!cu_cbf_i[ 16 ]),!(!cu_cbf_i[ 16 ]),!(!cu_cbf_i[ 16 ])}; end
7'd69 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 15 ]),!(!cu_cbf_i[ 15 ]),!(!cu_cbf_i[ 15 ]),!(!cu_cbf_i[ 15 ])}; end
7'd70 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 14 ]),!(!cu_cbf_i[ 14 ]),!(!cu_cbf_i[ 14 ]),!(!cu_cbf_i[ 14 ])}; end
7'd71 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 13 ]),!(!cu_cbf_i[ 13 ]),!(!cu_cbf_i[ 13 ]),!(!cu_cbf_i[ 13 ])}; end
7'd72 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 12 ]),!(!cu_cbf_i[ 12 ]),!(!cu_cbf_i[ 12 ]),!(!cu_cbf_i[ 12 ])}; end
7'd73 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 11 ]),!(!cu_cbf_i[ 11 ]),!(!cu_cbf_i[ 11 ]),!(!cu_cbf_i[ 11 ])}; end
7'd74 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 10 ]),!(!cu_cbf_i[ 10 ]),!(!cu_cbf_i[ 10 ]),!(!cu_cbf_i[ 10 ])}; end
7'd75 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 9 ]),!(!cu_cbf_i[ 9 ]),!(!cu_cbf_i[ 9 ]),!(!cu_cbf_i[ 9 ])}; end
7'd76 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 8 ]),!(!cu_cbf_i[ 8 ]),!(!cu_cbf_i[ 8 ]),!(!cu_cbf_i[ 8 ])}; end
7'd77 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 7 ]),!(!cu_cbf_i[ 7 ]),!(!cu_cbf_i[ 7 ]),!(!cu_cbf_i[ 7 ])}; end
7'd78 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 6 ]),!(!cu_cbf_i[ 6 ]),!(!cu_cbf_i[ 6 ]),!(!cu_cbf_i[ 6 ])}; end
7'd79 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 5 ]),!(!cu_cbf_i[ 5 ]),!(!cu_cbf_i[ 5 ]),!(!cu_cbf_i[ 5 ])}; end
7'd80 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 4 ]),!(!cu_cbf_i[ 4 ]),!(!cu_cbf_i[ 4 ]),!(!cu_cbf_i[ 4 ])}; end
7'd81 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 3 ]),!(!cu_cbf_i[ 3 ]),!(!cu_cbf_i[ 3 ]),!(!cu_cbf_i[ 3 ])}; end
7'd82 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 2 ]),!(!cu_cbf_i[ 2 ]),!(!cu_cbf_i[ 2 ]),!(!cu_cbf_i[ 2 ])}; end
7'd83 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 1 ]),!(!cu_cbf_i[ 1 ]),!(!cu_cbf_i[ 1 ]),!(!cu_cbf_i[ 1 ])}; end
7'd84 : begin cu_cbf_u_r <= {!(!cu_cbf_i[ 0 ]),!(!cu_cbf_i[ 0 ]),!(!cu_cbf_i[ 0 ]),!(!cu_cbf_i[ 0 ])}; end
default : begin cu_cbf_u_r <= 4'b0 ; end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_cbf_v_r <= 4'b0 ;
else begin
case(cu_idx_r)
7'd0 : begin cu_cbf_v_r <= {!(!cr_cbf_i[63:48]),!(!cr_cbf_i[47:32]),!(!cr_cbf_i[31:16]),!(!cr_cbf_i[15: 0])}; end // 64x64
7'd1 : begin cu_cbf_v_r <= {!(!cr_cbf_i[63:60]),!(!cr_cbf_i[59:56]),!(!cr_cbf_i[55:52]),!(!cr_cbf_i[51:48])}; end // 32x32
7'd2 : begin cu_cbf_v_r <= {!(!cr_cbf_i[47:44]),!(!cr_cbf_i[43:40]),!(!cr_cbf_i[39:36]),!(!cr_cbf_i[35:32])}; end
7'd3 : begin cu_cbf_v_r <= {!(!cr_cbf_i[31:28]),!(!cr_cbf_i[27:24]),!(!cr_cbf_i[23:20]),!(!cr_cbf_i[19:16])}; end
7'd4 : begin cu_cbf_v_r <= {!(!cr_cbf_i[15:12]),!(!cr_cbf_i[11:8 ]),!(!cr_cbf_i[ 7:4 ]),!(!cr_cbf_i[ 3:0 ])}; end
7'd5 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 63 ]),!(!cr_cbf_i[ 62 ]),!(!cr_cbf_i[ 61 ]),!(!cr_cbf_i[ 60 ])}; end //16x16
7'd6 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 59 ]),!(!cr_cbf_i[ 58 ]),!(!cr_cbf_i[ 57 ]),!(!cr_cbf_i[ 56 ])}; end
7'd7 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 55 ]),!(!cr_cbf_i[ 54 ]),!(!cr_cbf_i[ 53 ]),!(!cr_cbf_i[ 52 ])}; end
7'd8 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 51 ]),!(!cr_cbf_i[ 50 ]),!(!cr_cbf_i[ 49 ]),!(!cr_cbf_i[ 48 ])}; end
7'd9 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 47 ]),!(!cr_cbf_i[ 46 ]),!(!cr_cbf_i[ 45 ]),!(!cr_cbf_i[ 44 ])}; end
7'd10 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 43 ]),!(!cr_cbf_i[ 42 ]),!(!cr_cbf_i[ 41 ]),!(!cr_cbf_i[ 40 ])}; end
7'd11 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 39 ]),!(!cr_cbf_i[ 38 ]),!(!cr_cbf_i[ 37 ]),!(!cr_cbf_i[ 36 ])}; end
7'd12 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 35 ]),!(!cr_cbf_i[ 34 ]),!(!cr_cbf_i[ 33 ]),!(!cr_cbf_i[ 32 ])}; end
7'd13 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 31 ]),!(!cr_cbf_i[ 30 ]),!(!cr_cbf_i[ 29 ]),!(!cr_cbf_i[ 28 ])}; end
7'd14 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 27 ]),!(!cr_cbf_i[ 26 ]),!(!cr_cbf_i[ 25 ]),!(!cr_cbf_i[ 24 ])}; end
7'd15 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 23 ]),!(!cr_cbf_i[ 22 ]),!(!cr_cbf_i[ 21 ]),!(!cr_cbf_i[ 20 ])}; end
7'd16 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 19 ]),!(!cr_cbf_i[ 18 ]),!(!cr_cbf_i[ 17 ]),!(!cr_cbf_i[ 16 ])}; end
7'd17 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 15 ]),!(!cr_cbf_i[ 14 ]),!(!cr_cbf_i[ 13 ]),!(!cr_cbf_i[ 12 ])}; end
7'd18 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 11 ]),!(!cr_cbf_i[ 10 ]),!(!cr_cbf_i[ 9 ]),!(!cr_cbf_i[ 8 ])}; end
7'd19 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 7 ]),!(!cr_cbf_i[ 6 ]),!(!cr_cbf_i[ 5 ]),!(!cr_cbf_i[ 4 ])}; end
7'd20 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 3 ]),!(!cr_cbf_i[ 2 ]),!(!cr_cbf_i[ 1 ]),!(!cr_cbf_i[ 0 ])}; end
7'd21 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 63 ]),!(!cr_cbf_i[ 63 ]),!(!cr_cbf_i[ 63 ]),!(!cr_cbf_i[ 63 ])}; end //8x8
7'd22 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 62 ]),!(!cr_cbf_i[ 62 ]),!(!cr_cbf_i[ 62 ]),!(!cr_cbf_i[ 62 ])}; end
7'd23 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 61 ]),!(!cr_cbf_i[ 61 ]),!(!cr_cbf_i[ 61 ]),!(!cr_cbf_i[ 61 ])}; end
7'd24 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 60 ]),!(!cr_cbf_i[ 60 ]),!(!cr_cbf_i[ 60 ]),!(!cr_cbf_i[ 60 ])}; end
7'd25 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 59 ]),!(!cr_cbf_i[ 59 ]),!(!cr_cbf_i[ 59 ]),!(!cr_cbf_i[ 59 ])}; end
7'd26 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 58 ]),!(!cr_cbf_i[ 58 ]),!(!cr_cbf_i[ 58 ]),!(!cr_cbf_i[ 58 ])}; end
7'd27 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 57 ]),!(!cr_cbf_i[ 57 ]),!(!cr_cbf_i[ 57 ]),!(!cr_cbf_i[ 57 ])}; end
7'd28 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 56 ]),!(!cr_cbf_i[ 56 ]),!(!cr_cbf_i[ 56 ]),!(!cr_cbf_i[ 56 ])}; end
7'd29 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 55 ]),!(!cr_cbf_i[ 55 ]),!(!cr_cbf_i[ 55 ]),!(!cr_cbf_i[ 55 ])}; end
7'd30 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 54 ]),!(!cr_cbf_i[ 54 ]),!(!cr_cbf_i[ 54 ]),!(!cr_cbf_i[ 54 ])}; end
7'd31 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 53 ]),!(!cr_cbf_i[ 53 ]),!(!cr_cbf_i[ 53 ]),!(!cr_cbf_i[ 53 ])}; end
7'd32 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 52 ]),!(!cr_cbf_i[ 52 ]),!(!cr_cbf_i[ 52 ]),!(!cr_cbf_i[ 52 ])}; end
7'd33 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 51 ]),!(!cr_cbf_i[ 51 ]),!(!cr_cbf_i[ 51 ]),!(!cr_cbf_i[ 51 ])}; end
7'd34 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 50 ]),!(!cr_cbf_i[ 50 ]),!(!cr_cbf_i[ 50 ]),!(!cr_cbf_i[ 50 ])}; end
7'd35 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 49 ]),!(!cr_cbf_i[ 49 ]),!(!cr_cbf_i[ 49 ]),!(!cr_cbf_i[ 49 ])}; end
7'd36 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 48 ]),!(!cr_cbf_i[ 48 ]),!(!cr_cbf_i[ 48 ]),!(!cr_cbf_i[ 48 ])}; end
7'd37 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 47 ]),!(!cr_cbf_i[ 47 ]),!(!cr_cbf_i[ 47 ]),!(!cr_cbf_i[ 47 ])}; end
7'd38 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 46 ]),!(!cr_cbf_i[ 46 ]),!(!cr_cbf_i[ 46 ]),!(!cr_cbf_i[ 46 ])}; end
7'd39 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 45 ]),!(!cr_cbf_i[ 45 ]),!(!cr_cbf_i[ 45 ]),!(!cr_cbf_i[ 45 ])}; end
7'd40 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 44 ]),!(!cr_cbf_i[ 44 ]),!(!cr_cbf_i[ 44 ]),!(!cr_cbf_i[ 44 ])}; end
7'd41 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 43 ]),!(!cr_cbf_i[ 43 ]),!(!cr_cbf_i[ 43 ]),!(!cr_cbf_i[ 43 ])}; end
7'd42 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 42 ]),!(!cr_cbf_i[ 42 ]),!(!cr_cbf_i[ 42 ]),!(!cr_cbf_i[ 42 ])}; end
7'd43 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 41 ]),!(!cr_cbf_i[ 41 ]),!(!cr_cbf_i[ 41 ]),!(!cr_cbf_i[ 41 ])}; end
7'd44 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 40 ]),!(!cr_cbf_i[ 40 ]),!(!cr_cbf_i[ 40 ]),!(!cr_cbf_i[ 40 ])}; end
7'd45 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 39 ]),!(!cr_cbf_i[ 39 ]),!(!cr_cbf_i[ 39 ]),!(!cr_cbf_i[ 39 ])}; end
7'd46 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 38 ]),!(!cr_cbf_i[ 38 ]),!(!cr_cbf_i[ 38 ]),!(!cr_cbf_i[ 38 ])}; end
7'd47 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 37 ]),!(!cr_cbf_i[ 37 ]),!(!cr_cbf_i[ 37 ]),!(!cr_cbf_i[ 37 ])}; end
7'd48 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 36 ]),!(!cr_cbf_i[ 36 ]),!(!cr_cbf_i[ 36 ]),!(!cr_cbf_i[ 36 ])}; end
7'd49 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 35 ]),!(!cr_cbf_i[ 35 ]),!(!cr_cbf_i[ 35 ]),!(!cr_cbf_i[ 35 ])}; end
7'd50 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 34 ]),!(!cr_cbf_i[ 34 ]),!(!cr_cbf_i[ 34 ]),!(!cr_cbf_i[ 34 ])}; end
7'd51 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 33 ]),!(!cr_cbf_i[ 33 ]),!(!cr_cbf_i[ 33 ]),!(!cr_cbf_i[ 33 ])}; end
7'd52 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 32 ]),!(!cr_cbf_i[ 32 ]),!(!cr_cbf_i[ 32 ]),!(!cr_cbf_i[ 32 ])}; end
7'd53 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 31 ]),!(!cr_cbf_i[ 31 ]),!(!cr_cbf_i[ 31 ]),!(!cr_cbf_i[ 31 ])}; end
7'd54 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 30 ]),!(!cr_cbf_i[ 30 ]),!(!cr_cbf_i[ 30 ]),!(!cr_cbf_i[ 30 ])}; end
7'd55 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 29 ]),!(!cr_cbf_i[ 29 ]),!(!cr_cbf_i[ 29 ]),!(!cr_cbf_i[ 29 ])}; end
7'd56 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 28 ]),!(!cr_cbf_i[ 28 ]),!(!cr_cbf_i[ 28 ]),!(!cr_cbf_i[ 28 ])}; end
7'd57 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 27 ]),!(!cr_cbf_i[ 27 ]),!(!cr_cbf_i[ 27 ]),!(!cr_cbf_i[ 27 ])}; end
7'd58 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 26 ]),!(!cr_cbf_i[ 26 ]),!(!cr_cbf_i[ 26 ]),!(!cr_cbf_i[ 26 ])}; end
7'd59 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 25 ]),!(!cr_cbf_i[ 25 ]),!(!cr_cbf_i[ 25 ]),!(!cr_cbf_i[ 25 ])}; end
7'd60 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 24 ]),!(!cr_cbf_i[ 24 ]),!(!cr_cbf_i[ 24 ]),!(!cr_cbf_i[ 24 ])}; end
7'd61 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 23 ]),!(!cr_cbf_i[ 23 ]),!(!cr_cbf_i[ 23 ]),!(!cr_cbf_i[ 23 ])}; end
7'd62 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 22 ]),!(!cr_cbf_i[ 22 ]),!(!cr_cbf_i[ 22 ]),!(!cr_cbf_i[ 22 ])}; end
7'd63 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 21 ]),!(!cr_cbf_i[ 21 ]),!(!cr_cbf_i[ 21 ]),!(!cr_cbf_i[ 21 ])}; end
7'd64 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 20 ]),!(!cr_cbf_i[ 20 ]),!(!cr_cbf_i[ 20 ]),!(!cr_cbf_i[ 20 ])}; end
7'd65 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 19 ]),!(!cr_cbf_i[ 19 ]),!(!cr_cbf_i[ 19 ]),!(!cr_cbf_i[ 19 ])}; end
7'd66 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 18 ]),!(!cr_cbf_i[ 18 ]),!(!cr_cbf_i[ 18 ]),!(!cr_cbf_i[ 18 ])}; end
7'd67 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 17 ]),!(!cr_cbf_i[ 17 ]),!(!cr_cbf_i[ 17 ]),!(!cr_cbf_i[ 17 ])}; end
7'd68 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 16 ]),!(!cr_cbf_i[ 16 ]),!(!cr_cbf_i[ 16 ]),!(!cr_cbf_i[ 16 ])}; end
7'd69 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 15 ]),!(!cr_cbf_i[ 15 ]),!(!cr_cbf_i[ 15 ]),!(!cr_cbf_i[ 15 ])}; end
7'd70 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 14 ]),!(!cr_cbf_i[ 14 ]),!(!cr_cbf_i[ 14 ]),!(!cr_cbf_i[ 14 ])}; end
7'd71 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 13 ]),!(!cr_cbf_i[ 13 ]),!(!cr_cbf_i[ 13 ]),!(!cr_cbf_i[ 13 ])}; end
7'd72 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 12 ]),!(!cr_cbf_i[ 12 ]),!(!cr_cbf_i[ 12 ]),!(!cr_cbf_i[ 12 ])}; end
7'd73 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 11 ]),!(!cr_cbf_i[ 11 ]),!(!cr_cbf_i[ 11 ]),!(!cr_cbf_i[ 11 ])}; end
7'd74 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 10 ]),!(!cr_cbf_i[ 10 ]),!(!cr_cbf_i[ 10 ]),!(!cr_cbf_i[ 10 ])}; end
7'd75 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 9 ]),!(!cr_cbf_i[ 9 ]),!(!cr_cbf_i[ 9 ]),!(!cr_cbf_i[ 9 ])}; end
7'd76 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 8 ]),!(!cr_cbf_i[ 8 ]),!(!cr_cbf_i[ 8 ]),!(!cr_cbf_i[ 8 ])}; end
7'd77 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 7 ]),!(!cr_cbf_i[ 7 ]),!(!cr_cbf_i[ 7 ]),!(!cr_cbf_i[ 7 ])}; end
7'd78 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 6 ]),!(!cr_cbf_i[ 6 ]),!(!cr_cbf_i[ 6 ]),!(!cr_cbf_i[ 6 ])}; end
7'd79 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 5 ]),!(!cr_cbf_i[ 5 ]),!(!cr_cbf_i[ 5 ]),!(!cr_cbf_i[ 5 ])}; end
7'd80 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 4 ]),!(!cr_cbf_i[ 4 ]),!(!cr_cbf_i[ 4 ]),!(!cr_cbf_i[ 4 ])}; end
7'd81 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 3 ]),!(!cr_cbf_i[ 3 ]),!(!cr_cbf_i[ 3 ]),!(!cr_cbf_i[ 3 ])}; end
7'd82 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 2 ]),!(!cr_cbf_i[ 2 ]),!(!cr_cbf_i[ 2 ]),!(!cr_cbf_i[ 2 ])}; end
7'd83 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 1 ]),!(!cr_cbf_i[ 1 ]),!(!cr_cbf_i[ 1 ]),!(!cr_cbf_i[ 1 ])}; end
7'd84 : begin cu_cbf_v_r <= {!(!cr_cbf_i[ 0 ]),!(!cr_cbf_i[ 0 ]),!(!cr_cbf_i[ 0 ]),!(!cr_cbf_i[ 0 ])}; end
default : begin cu_cbf_v_r <= 4'b0 ; end
endcase
end
end
*/
// cu_depth_top_r
always @* begin
case(cu_idx_r)
7'd0 : cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[15:14]: 2'd0;
7'd1 : cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[15:14]: 2'd0;
7'd2 : cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[11:10]: 2'd0;
7'd3 : cu_depth_top_r = cu_depth_0_0_r ;
7'd4 : cu_depth_top_r = cu_depth_0_4_r ;
7'd5 : cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[15:14]: 2'd0;
7'd6 : cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[13:12]: 2'd0;
7'd7 : cu_depth_top_r = cu_depth_0_0_r ;
7'd8 : cu_depth_top_r = cu_depth_0_2_r ;
7'd9 : cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[11:10]: 2'd0;
7'd10: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[ 9:8 ]: 2'd0;
7'd11: cu_depth_top_r = cu_depth_0_4_r ;
7'd12: cu_depth_top_r = cu_depth_0_6_r ;
7'd13: cu_depth_top_r = cu_depth_2_0_r ;
7'd14: cu_depth_top_r = cu_depth_2_2_r ;
7'd15: cu_depth_top_r = cu_depth_4_0_r ;
7'd16: cu_depth_top_r = cu_depth_4_2_r ;
7'd17: cu_depth_top_r = cu_depth_2_4_r ;
7'd18: cu_depth_top_r = cu_depth_2_6_r ;
7'd19: cu_depth_top_r = cu_depth_4_4_r ;
7'd20: cu_depth_top_r = cu_depth_4_6_r ;
7'd21: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[15:14]: 2'd0;
7'd22: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[15:14]: 2'd0;
7'd23: cu_depth_top_r = r_data_neigh_mb_r[15:14] ;
7'd24: cu_depth_top_r = r_data_neigh_mb_r[15:14] ;
7'd25: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[13:12]: 2'd0;
7'd26: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[13:12]: 2'd0;
7'd27: cu_depth_top_r = r_data_neigh_mb_r[13:12] ;
7'd28: cu_depth_top_r = r_data_neigh_mb_r[13:12] ;
7'd29: cu_depth_top_r = cu_depth_0_0_r ;
7'd30: cu_depth_top_r = cu_depth_0_0_r ;
7'd31: cu_depth_top_r = cu_depth_0_0_r ;
7'd32: cu_depth_top_r = cu_depth_0_0_r ;
7'd33: cu_depth_top_r = cu_depth_0_2_r ;
7'd34: cu_depth_top_r = cu_depth_0_2_r ;
7'd35: cu_depth_top_r = cu_depth_0_2_r ;
7'd36: cu_depth_top_r = cu_depth_0_2_r ;
7'd37: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[11:10]: 2'd0;
7'd38: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[11:10]: 2'd0;
7'd39: cu_depth_top_r = r_data_neigh_mb_r[11:10] ;
7'd40: cu_depth_top_r = r_data_neigh_mb_r[11:10] ;
7'd41: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[ 9:8 ]: 2'd0;
7'd42: cu_depth_top_r = mb_y_i ? r_data_neigh_mb_r[ 9:8 ]: 2'd0;
7'd43: cu_depth_top_r = r_data_neigh_mb_r[ 9:8 ] ;
7'd44: cu_depth_top_r = r_data_neigh_mb_r[ 9:8 ] ;
7'd45: cu_depth_top_r = cu_depth_0_4_r ;
7'd46: cu_depth_top_r = cu_depth_0_4_r ;
7'd47: cu_depth_top_r = cu_depth_0_4_r ;
7'd48: cu_depth_top_r = cu_depth_0_4_r ;
7'd49: cu_depth_top_r = cu_depth_0_6_r ;
7'd50: cu_depth_top_r = cu_depth_0_6_r ;
7'd51: cu_depth_top_r = cu_depth_0_6_r ;
7'd52: cu_depth_top_r = cu_depth_0_6_r ;
7'd53: cu_depth_top_r = cu_depth_2_0_r ;
7'd54: cu_depth_top_r = cu_depth_2_0_r ;
7'd55: cu_depth_top_r = cu_depth_2_0_r ;
7'd56: cu_depth_top_r = cu_depth_2_0_r ;
7'd57: cu_depth_top_r = cu_depth_2_2_r ;
7'd58: cu_depth_top_r = cu_depth_2_2_r ;
7'd59: cu_depth_top_r = cu_depth_2_2_r ;
7'd60: cu_depth_top_r = cu_depth_2_2_r ;
7'd61: cu_depth_top_r = cu_depth_4_0_r ;
7'd62: cu_depth_top_r = cu_depth_4_0_r ;
7'd63: cu_depth_top_r = cu_depth_4_0_r ;
7'd64: cu_depth_top_r = cu_depth_4_0_r ;
7'd65: cu_depth_top_r = cu_depth_4_2_r ;
7'd66: cu_depth_top_r = cu_depth_4_2_r ;
7'd67: cu_depth_top_r = cu_depth_4_2_r ;
7'd68: cu_depth_top_r = cu_depth_4_2_r ;
7'd69: cu_depth_top_r = cu_depth_2_4_r ;
7'd70: cu_depth_top_r = cu_depth_2_4_r ;
7'd71: cu_depth_top_r = cu_depth_2_4_r ;
7'd72: cu_depth_top_r = cu_depth_2_4_r ;
7'd73: cu_depth_top_r = cu_depth_2_6_r ;
7'd74: cu_depth_top_r = cu_depth_2_6_r ;
7'd75: cu_depth_top_r = cu_depth_2_6_r ;
7'd76: cu_depth_top_r = cu_depth_2_6_r ;
7'd77: cu_depth_top_r = cu_depth_4_4_r ;
7'd78: cu_depth_top_r = cu_depth_4_4_r ;
7'd79: cu_depth_top_r = cu_depth_4_4_r ;
7'd80: cu_depth_top_r = cu_depth_4_4_r ;
7'd81: cu_depth_top_r = cu_depth_4_6_r ;
7'd82: cu_depth_top_r = cu_depth_4_6_r ;
7'd83: cu_depth_top_r = cu_depth_4_6_r ;
7'd84: cu_depth_top_r = cu_depth_4_6_r ;
default: cu_depth_top_r = 2'd0 ;
endcase
end
// cu_skip_top_flag_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cu_skip_top_flag_r <= 1'b0 ;
end
else begin
case(cu_idx_r)
7'd0 :cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[7]: 1'b0 ;
7'd1 :cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[7]: 1'b0 ;
7'd2 :cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[3]: 1'b0 ;
7'd3 :cu_skip_top_flag_r <= cu_skip_flag_i[1] ;
7'd4 :cu_skip_top_flag_r <= cu_skip_flag_i[2] ;
7'd5 :cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[7]: 1'b0 ;
7'd6 :cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[5]: 1'b0 ;
7'd7 :cu_skip_top_flag_r <= cu_skip_flag_i[5] ;
7'd8 :cu_skip_top_flag_r <= cu_skip_flag_i[6] ;
7'd9 :cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[3]: 1'b0 ;
7'd10:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[1]: 1'b0 ;
7'd11:cu_skip_top_flag_r <= cu_skip_flag_i[9] ;
7'd12:cu_skip_top_flag_r <= cu_skip_flag_i[10] ;
7'd13:cu_skip_top_flag_r <= cu_skip_flag_i[7] ;
7'd14:cu_skip_top_flag_r <= cu_skip_flag_i[8] ;
7'd15:cu_skip_top_flag_r <= cu_skip_flag_i[13] ;
7'd16:cu_skip_top_flag_r <= cu_skip_flag_i[14] ;
7'd17:cu_skip_top_flag_r <= cu_skip_flag_i[11] ;
7'd18:cu_skip_top_flag_r <= cu_skip_flag_i[12] ;
7'd19:cu_skip_top_flag_r <= cu_skip_flag_i[17] ;
7'd20:cu_skip_top_flag_r <= cu_skip_flag_i[18] ;
7'd21:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[7]: 1'b0 ;
7'd22:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[6]: 1'b0 ;
7'd23:cu_skip_top_flag_r <= cu_skip_flag_i[21] ;
7'd24:cu_skip_top_flag_r <= cu_skip_flag_i[22] ;
7'd25:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[5]: 1'b0 ;
7'd26:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[4]: 1'b0 ;
7'd27:cu_skip_top_flag_r <= cu_skip_flag_i[25] ;
7'd28:cu_skip_top_flag_r <= cu_skip_flag_i[26] ;
7'd29:cu_skip_top_flag_r <= cu_skip_flag_i[23] ;
7'd30:cu_skip_top_flag_r <= cu_skip_flag_i[24] ;
7'd31:cu_skip_top_flag_r <= cu_skip_flag_i[29] ;
7'd32:cu_skip_top_flag_r <= cu_skip_flag_i[30] ;
7'd33:cu_skip_top_flag_r <= cu_skip_flag_i[27] ;
7'd34:cu_skip_top_flag_r <= cu_skip_flag_i[28] ;
7'd35:cu_skip_top_flag_r <= cu_skip_flag_i[33] ;
7'd36:cu_skip_top_flag_r <= cu_skip_flag_i[34] ;
7'd37:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[3]: 1'b0 ;
7'd38:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[2]: 1'b0 ;
7'd39:cu_skip_top_flag_r <= cu_skip_flag_i[37] ;
7'd40:cu_skip_top_flag_r <= cu_skip_flag_i[38] ;
7'd41:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[1]: 1'b0 ;
7'd42:cu_skip_top_flag_r <= mb_y_i ? r_data_neigh_mb_r[0]: 1'b0 ;
7'd43:cu_skip_top_flag_r <= cu_skip_flag_i[41] ;
7'd44:cu_skip_top_flag_r <= cu_skip_flag_i[42] ;
7'd45:cu_skip_top_flag_r <= cu_skip_flag_i[39] ;
7'd46:cu_skip_top_flag_r <= cu_skip_flag_i[40] ;
7'd47:cu_skip_top_flag_r <= cu_skip_flag_i[45] ;
7'd48:cu_skip_top_flag_r <= cu_skip_flag_i[46] ;
7'd49:cu_skip_top_flag_r <= cu_skip_flag_i[43] ;
7'd50:cu_skip_top_flag_r <= cu_skip_flag_i[44] ;
7'd51:cu_skip_top_flag_r <= cu_skip_flag_i[49] ;
7'd52:cu_skip_top_flag_r <= cu_skip_flag_i[50] ;
7'd53:cu_skip_top_flag_r <= cu_skip_flag_i[31] ;
7'd54:cu_skip_top_flag_r <= cu_skip_flag_i[32] ;
7'd55:cu_skip_top_flag_r <= cu_skip_flag_i[53] ;
7'd56:cu_skip_top_flag_r <= cu_skip_flag_i[54] ;
7'd57:cu_skip_top_flag_r <= cu_skip_flag_i[56] ;
7'd58:cu_skip_top_flag_r <= cu_skip_flag_i[58] ;
7'd59:cu_skip_top_flag_r <= cu_skip_flag_i[57] ;
7'd60:cu_skip_top_flag_r <= cu_skip_flag_i[58] ;
7'd61:cu_skip_top_flag_r <= cu_skip_flag_i[55] ;
7'd62:cu_skip_top_flag_r <= cu_skip_flag_i[56] ;
7'd63:cu_skip_top_flag_r <= cu_skip_flag_i[61] ;
7'd64:cu_skip_top_flag_r <= cu_skip_flag_i[62] ;
7'd65:cu_skip_top_flag_r <= cu_skip_flag_i[59] ;
7'd66:cu_skip_top_flag_r <= cu_skip_flag_i[60] ;
7'd67:cu_skip_top_flag_r <= cu_skip_flag_i[65] ;
7'd68:cu_skip_top_flag_r <= cu_skip_flag_i[66] ;
7'd69:cu_skip_top_flag_r <= cu_skip_flag_i[47] ;
7'd70:cu_skip_top_flag_r <= cu_skip_flag_i[48] ;
7'd71:cu_skip_top_flag_r <= cu_skip_flag_i[69] ;
7'd72:cu_skip_top_flag_r <= cu_skip_flag_i[70] ;
7'd73:cu_skip_top_flag_r <= cu_skip_flag_i[51] ;
7'd74:cu_skip_top_flag_r <= cu_skip_flag_i[52] ;
7'd75:cu_skip_top_flag_r <= cu_skip_flag_i[73] ;
7'd76:cu_skip_top_flag_r <= cu_skip_flag_i[74] ;
7'd77:cu_skip_top_flag_r <= cu_skip_flag_i[71] ;
7'd78:cu_skip_top_flag_r <= cu_skip_flag_i[72] ;
7'd79:cu_skip_top_flag_r <= cu_skip_flag_i[77] ;
7'd80:cu_skip_top_flag_r <= cu_skip_flag_i[78] ;
7'd81:cu_skip_top_flag_r <= cu_skip_flag_i[75] ;
7'd82:cu_skip_top_flag_r <= cu_skip_flag_i[76] ;
7'd83:cu_skip_top_flag_r <= cu_skip_flag_i[81] ;
7'd84:cu_skip_top_flag_r <= cu_skip_flag_i[82] ;
default:cu_skip_top_flag_r <= 1'd0 ;
endcase
end
end
// cu_depth_left_r
always @* begin
case(cu_idx_r)
7'd0 : cu_depth_left_r = mb_x_i ? cu_left_0_r[1:0] :2'd0;
7'd1 : cu_depth_left_r = mb_x_i ? cu_left_0_r[1:0] :2'd0;
7'd2 : cu_depth_left_r = cu_depth_0_2_r ;
7'd3 : cu_depth_left_r = mb_x_i ? cu_left_8_r[1:0] :2'd0;
7'd4 : cu_depth_left_r = cu_depth_4_2_r ;
7'd5 : cu_depth_left_r = mb_x_i ? cu_left_0_r[1:0] :2'd0;
7'd6 : cu_depth_left_r = cu_depth_0_0_r ;
7'd7 : cu_depth_left_r = mb_x_i ? cu_left_4_r[1:0] :2'd0;
7'd8 : cu_depth_left_r = cu_depth_2_0_r ;
7'd9 : cu_depth_left_r = cu_depth_0_2_r ;
7'd10 : cu_depth_left_r = cu_depth_0_4_r ;
7'd11 : cu_depth_left_r = cu_depth_2_2_r ;
7'd12 : cu_depth_left_r = cu_depth_2_4_r ;
7'd13 : cu_depth_left_r = mb_x_i ? cu_left_8_r[1:0] :2'd0;
7'd14 : cu_depth_left_r = cu_depth_4_0_r ;
7'd15 : cu_depth_left_r = mb_x_i ? cu_left_12_r[1:0]:2'd0;
7'd16 : cu_depth_left_r = cu_depth_6_0_r ;
7'd17 : cu_depth_left_r = cu_depth_4_2_r ;
7'd18 : cu_depth_left_r = cu_depth_4_4_r ;
7'd19 : cu_depth_left_r = cu_depth_6_2_r ;
7'd20 : cu_depth_left_r = cu_depth_6_4_r ;
7'd21 : cu_depth_left_r = mb_x_i ? cu_left_0_r[1:0]:2'd0 ;
7'd22 : cu_depth_left_r = cu_left_0_r[1:0] ;
7'd23 : cu_depth_left_r = mb_x_i ? cu_left_0_r[1:0]:2'd0 ;
7'd24 : cu_depth_left_r = cu_left_0_r[1:0] ;
7'd25 : cu_depth_left_r = cu_depth_0_0_r ;
7'd26 : cu_depth_left_r = cu_depth_0_0_r ;
7'd27 : cu_depth_left_r = cu_depth_0_0_r ;
7'd28 : cu_depth_left_r = cu_depth_0_0_r ;
7'd29 : cu_depth_left_r = mb_x_i ? cu_left_2_r[1:0]:2'd0 ;
7'd30 : cu_depth_left_r = cu_left_2_r[1:0] ;
7'd31 : cu_depth_left_r = mb_x_i ? cu_left_2_r[1:0]:2'd0 ;
7'd32 : cu_depth_left_r = cu_left_2_r[1:0] ;
7'd33 : cu_depth_left_r = cu_depth_2_0_r ;
7'd34 : cu_depth_left_r = cu_depth_2_0_r ;
7'd35 : cu_depth_left_r = cu_depth_2_0_r ;
7'd36 : cu_depth_left_r = cu_depth_2_0_r ;
7'd37 : cu_depth_left_r = cu_depth_0_2_r ;
7'd38 : cu_depth_left_r = cu_depth_0_2_r ;
7'd39 : cu_depth_left_r = cu_depth_0_2_r ;
7'd40 : cu_depth_left_r = cu_depth_0_2_r ;
7'd41 : cu_depth_left_r = cu_depth_0_4_r ;
7'd42 : cu_depth_left_r = cu_depth_0_4_r ;
7'd43 : cu_depth_left_r = cu_depth_0_4_r ;
7'd44 : cu_depth_left_r = cu_depth_0_4_r ;
7'd45 : cu_depth_left_r = cu_depth_2_2_r ;
7'd46 : cu_depth_left_r = cu_depth_2_2_r ;
7'd47 : cu_depth_left_r = cu_depth_2_2_r ;
7'd48 : cu_depth_left_r = cu_depth_2_2_r ;
7'd49 : cu_depth_left_r = cu_depth_2_4_r ;
7'd50 : cu_depth_left_r = cu_depth_2_4_r ;
7'd51 : cu_depth_left_r = cu_depth_2_4_r ;
7'd52 : cu_depth_left_r = cu_depth_2_4_r ;
7'd53 : cu_depth_left_r = mb_x_i ? cu_left_8_r[1:0]:2'd0 ;
7'd54 : cu_depth_left_r = cu_left_8_r[1:0] ;
7'd55 : cu_depth_left_r = mb_x_i ? cu_left_8_r[1:0]:2'd0 ;
7'd56 : cu_depth_left_r = cu_left_8_r[1:0] ;
7'd57 : cu_depth_left_r = cu_depth_4_0_r ;
7'd58 : cu_depth_left_r = cu_depth_4_0_r ;
7'd59 : cu_depth_left_r = cu_depth_4_0_r ;
7'd60 : cu_depth_left_r = cu_depth_4_0_r ;
7'd61 : cu_depth_left_r = mb_x_i ? cu_left_12_r[1:0]:2'd0;
7'd62 : cu_depth_left_r = cu_left_12_r[1:0] ;
7'd63 : cu_depth_left_r = mb_x_i ? cu_left_12_r[1:0]:2'd0;
7'd64 : cu_depth_left_r = cu_left_12_r[1:0] ;
7'd65 : cu_depth_left_r = cu_depth_6_0_r ;
7'd66 : cu_depth_left_r = cu_depth_6_0_r ;
7'd67 : cu_depth_left_r = cu_depth_6_0_r ;
7'd68 : cu_depth_left_r = cu_depth_6_0_r ;
7'd69 : cu_depth_left_r = cu_depth_4_2_r ;
7'd70 : cu_depth_left_r = cu_depth_4_2_r ;
7'd71 : cu_depth_left_r = cu_depth_4_2_r ;
7'd72 : cu_depth_left_r = cu_depth_4_2_r ;
7'd73 : cu_depth_left_r = cu_depth_4_4_r ;
7'd74 : cu_depth_left_r = cu_depth_4_4_r ;
7'd75 : cu_depth_left_r = cu_depth_4_4_r ;
7'd76 : cu_depth_left_r = cu_depth_4_4_r ;
7'd77 : cu_depth_left_r = cu_depth_6_2_r ;
7'd78 : cu_depth_left_r = cu_depth_6_2_r ;
7'd79 : cu_depth_left_r = cu_depth_6_2_r ;
7'd80 : cu_depth_left_r = cu_depth_6_2_r ;
7'd81 : cu_depth_left_r = cu_depth_6_4_r ;
7'd82 : cu_depth_left_r = cu_depth_6_4_r ;
7'd83 : cu_depth_left_r = cu_depth_6_4_r ;
7'd84 : cu_depth_left_r = cu_depth_6_4_r ;
default: cu_depth_left_r = 2'd0 ;
endcase
end
// cu_skip_left_flag_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cu_skip_left_flag_r <= 1'b0 ;
end
else begin
case(cu_idx_r)
7'd0 : cu_skip_left_flag_r <= mb_x_i ? cu_left_0_r[8]:1'b0 ;
7'd1 : cu_skip_left_flag_r <= mb_x_i ? cu_left_0_r[8]:1'b0 ;
7'd2 : cu_skip_left_flag_r <= cu_skip_flag_i[1] ;
7'd3 : cu_skip_left_flag_r <= mb_x_i ? cu_left_4_r[8]:1'b0 ;
7'd4 : cu_skip_left_flag_r <= cu_skip_flag_i[3] ;
7'd5 : cu_skip_left_flag_r <= mb_x_i ? cu_left_0_r[8]:1'b0 ;
7'd6 : cu_skip_left_flag_r <= cu_skip_flag_i[5] ;
7'd7 : cu_skip_left_flag_r <= mb_x_i ? cu_left_2_r[8]:1'b0 ;
7'd8 : cu_skip_left_flag_r <= cu_skip_flag_i[7] ;
7'd9 : cu_skip_left_flag_r <= cu_skip_flag_i[6] ;
7'd10: cu_skip_left_flag_r <= cu_skip_flag_i[9] ;
7'd11: cu_skip_left_flag_r <= cu_skip_flag_i[8] ;
7'd12: cu_skip_left_flag_r <= cu_skip_flag_i[11] ;
7'd13: cu_skip_left_flag_r <= mb_x_i ? cu_left_4_r[8]:1'b0 ;
7'd14: cu_skip_left_flag_r <= cu_skip_flag_i[13] ;
7'd15: cu_skip_left_flag_r <= mb_x_i ? cu_left_6_r[8]:1'b0 ;
7'd16: cu_skip_left_flag_r <= cu_skip_flag_i[15] ;
7'd17: cu_skip_left_flag_r <= cu_skip_flag_i[14] ;
7'd18: cu_skip_left_flag_r <= cu_skip_flag_i[17] ;
7'd19: cu_skip_left_flag_r <= cu_skip_flag_i[16] ;
7'd20: cu_skip_left_flag_r <= cu_skip_flag_i[19] ;
7'd21: cu_skip_left_flag_r <= mb_x_i ? cu_left_0_r[8]:1'b0 ;
7'd22: cu_skip_left_flag_r <= cu_skip_flag_i[0 ] ;
7'd23: cu_skip_left_flag_r <= mb_x_i ? cu_left_1_r[8]:1'b0 ;
7'd24: cu_skip_left_flag_r <= cu_skip_flag_i[2 ] ;
7'd25: cu_skip_left_flag_r <= cu_skip_flag_i[3 ] ;
7'd26: cu_skip_left_flag_r <= cu_skip_flag_i[4 ] ;
7'd27: cu_skip_left_flag_r <= cu_skip_flag_i[5 ] ;
7'd28: cu_skip_left_flag_r <= cu_skip_flag_i[6 ] ;
7'd29: cu_skip_left_flag_r <= mb_x_i ? cu_left_2_r[8]:1'b0 ;
7'd30: cu_skip_left_flag_r <= cu_skip_flag_i[8 ] ;
7'd31: cu_skip_left_flag_r <= mb_x_i ? cu_left_3_r[8]:1'b0 ;
7'd32: cu_skip_left_flag_r <= cu_skip_flag_i[10] ;
7'd33: cu_skip_left_flag_r <= cu_skip_flag_i[9 ] ;
7'd34: cu_skip_left_flag_r <= cu_skip_flag_i[12] ;
7'd35: cu_skip_left_flag_r <= cu_skip_flag_i[11] ;
7'd36: cu_skip_left_flag_r <= cu_skip_flag_i[14] ;
7'd37: cu_skip_left_flag_r <= cu_skip_flag_i[5 ] ;
7'd38: cu_skip_left_flag_r <= cu_skip_flag_i[16] ;
7'd39: cu_skip_left_flag_r <= cu_skip_flag_i[7 ] ;
7'd40: cu_skip_left_flag_r <= cu_skip_flag_i[18] ;
7'd41: cu_skip_left_flag_r <= cu_skip_flag_i[17] ;
7'd42: cu_skip_left_flag_r <= cu_skip_flag_i[20] ;
7'd43: cu_skip_left_flag_r <= cu_skip_flag_i[19] ;
7'd44: cu_skip_left_flag_r <= cu_skip_flag_i[22] ;
7'd45: cu_skip_left_flag_r <= cu_skip_flag_i[13] ;
7'd46: cu_skip_left_flag_r <= cu_skip_flag_i[24] ;
7'd47: cu_skip_left_flag_r <= cu_skip_flag_i[15] ;
7'd48: cu_skip_left_flag_r <= cu_skip_flag_i[26] ;
7'd49: cu_skip_left_flag_r <= cu_skip_flag_i[25] ;
7'd50: cu_skip_left_flag_r <= cu_skip_flag_i[28] ;
7'd51: cu_skip_left_flag_r <= cu_skip_flag_i[27] ;
7'd52: cu_skip_left_flag_r <= cu_skip_flag_i[30] ;
7'd53: cu_skip_left_flag_r <= mb_x_i ? cu_left_4_r[8]:1'b0 ;
7'd54: cu_skip_left_flag_r <= cu_skip_flag_i[32] ;
7'd55: cu_skip_left_flag_r <= mb_x_i ? cu_left_5_r[8]:1'b0 ;
7'd56: cu_skip_left_flag_r <= cu_skip_flag_i[34] ;
7'd57: cu_skip_left_flag_r <= cu_skip_flag_i[33] ;
7'd58: cu_skip_left_flag_r <= cu_skip_flag_i[36] ;
7'd59: cu_skip_left_flag_r <= cu_skip_flag_i[35] ;
7'd60: cu_skip_left_flag_r <= cu_skip_flag_i[38] ;
7'd61: cu_skip_left_flag_r <= mb_x_i ? cu_left_6_r[8]:1'b0 ;
7'd62: cu_skip_left_flag_r <= cu_skip_flag_i[40] ;
7'd63: cu_skip_left_flag_r <= mb_x_i ? cu_left_7_r[8]:1'b0 ;
7'd64: cu_skip_left_flag_r <= cu_skip_flag_i[42] ;
7'd65: cu_skip_left_flag_r <= cu_skip_flag_i[41] ;
7'd66: cu_skip_left_flag_r <= cu_skip_flag_i[44] ;
7'd67: cu_skip_left_flag_r <= cu_skip_flag_i[43] ;
7'd68: cu_skip_left_flag_r <= cu_skip_flag_i[46] ;
7'd69: cu_skip_left_flag_r <= cu_skip_flag_i[37] ;
7'd70: cu_skip_left_flag_r <= cu_skip_flag_i[48] ;
7'd71: cu_skip_left_flag_r <= cu_skip_flag_i[39] ;
7'd72: cu_skip_left_flag_r <= cu_skip_flag_i[50] ;
7'd73: cu_skip_left_flag_r <= cu_skip_flag_i[49] ;
7'd74: cu_skip_left_flag_r <= cu_skip_flag_i[52] ;
7'd75: cu_skip_left_flag_r <= cu_skip_flag_i[51] ;
7'd76: cu_skip_left_flag_r <= cu_skip_flag_i[54] ;
7'd77: cu_skip_left_flag_r <= cu_skip_flag_i[45] ;
7'd78: cu_skip_left_flag_r <= cu_skip_flag_i[56] ;
7'd79: cu_skip_left_flag_r <= cu_skip_flag_i[47] ;
7'd80: cu_skip_left_flag_r <= cu_skip_flag_i[58] ;
7'd81: cu_skip_left_flag_r <= cu_skip_flag_i[57] ;
7'd82: cu_skip_left_flag_r <= cu_skip_flag_i[60] ;
7'd83: cu_skip_left_flag_r <= cu_skip_flag_i[59] ;
7'd84: cu_skip_left_flag_r <= cu_skip_flag_i[62] ;
default: cu_skip_left_flag_r <=1'b0 ;
endcase
end
end
// last_cu_flag_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
last_cu_flag_r <= 1'b0 ;
else if(cu_idx_r==7'd84)
last_cu_flag_r <= 1'b1 ;
else if( (cu_idx_r==7'd0 || cu_idx_r==7'd4 || cu_idx_r==7'd20) && cu_split_flag_r==0 )
last_cu_flag_r <= 1'b1 ;
else
last_cu_flag_r <= 1'b0 ;
end
// cu_mvd_ren_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_mvd_ren_r <= 1'b1 ;
else if(slice_type_i)
cu_mvd_ren_r <= 1'b1 ;
else if(cu_start_d1_r || cu_start_d2_r)
cu_mvd_ren_r <= 1'b0 ;
else
cu_mvd_ren_r <= 1'b1 ;
end
wire [1:0] cu_inter_part_size_temp_w = {cu_inter_part_size_r[0],cu_inter_part_size_r[1]} ;
// cu_mvd_raddr_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_mvd_raddr_r <= 7'd0 ;
else if(cu_start_r) begin
case(cu_depth_r)
2'd0: cu_mvd_raddr_r <= {2'd0,4'd0} ; // 64x64: 0000
2'd1: cu_mvd_raddr_r <= {cu_idx_minus1_w[1:0],4'b0000}; // 32x32: 000000 010000 100000 110000
2'd2: cu_mvd_raddr_r <= {cu_idx_minus5_w[3:0],2'b00 }; // 16x16: 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
2'd3: cu_mvd_raddr_r <= cu_idx_minus21_w ; // 8x8
endcase
end
else if(cu_start_d1_r)begin
case(cu_depth_r)
2'd0: cu_mvd_raddr_r <= {cu_inter_part_size_temp_w,4'd0} ; // 64x64 2NxN:+32 Nx2N:+16
2'd1: cu_mvd_raddr_r <= {cu_idx_minus1_w[1:0],cu_inter_part_size_temp_w,2'b00} ; // 32x32 2NxN:+8 Nx2N:+4 2Nx2N:+0
2'd2: cu_mvd_raddr_r <= {cu_idx_minus5_w[3:0],cu_inter_part_size_temp_w } ; // 16x16 2NxN:+2 Nx2N:+1 2Nx2N:+0
2'd3: cu_mvd_raddr_r <= cu_idx_minus21_w ; // 8x8
endcase
end
end
// cu_mvd_data_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_mvd_data_r <= 46'd0 ;
else if(cu_start_d2_r)
cu_mvd_data_r <= {23'b0,cu_mvd_i} ;
else if(cu_start_d3_r)
cu_mvd_data_r <= {cu_mvd_data_r[2*`MVD_WIDTH:0],cu_mvd_i};
end
/*
// cu_mvd_idx_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_mvd_idx_r <= 9'd0 ;
else begin
case(cu_idx_r)
7'd0 : cu_mvd_idx_r <= {mvd_idx_i[ 2:0 ],mvd_idx_i[194:192],mvd_idx_i[ 98:96 ]};
7'd1 : cu_mvd_idx_r <= {mvd_idx_i[ 2:0 ],mvd_idx_i[ 50:48 ],mvd_idx_i[ 26:24 ]};
7'd2 : cu_mvd_idx_r <= {mvd_idx_i[ 98:96 ],mvd_idx_i[146:144],mvd_idx_i[122:120]};
7'd3 : cu_mvd_idx_r <= {mvd_idx_i[194:192],mvd_idx_i[242:240],mvd_idx_i[218:216]};
7'd4 : cu_mvd_idx_r <= {mvd_idx_i[290:288],mvd_idx_i[338:336],mvd_idx_i[314:312]};
7'd5 : cu_mvd_idx_r <= {mvd_idx_i[ 2:0 ],mvd_idx_i[ 14:12 ],mvd_idx_i[ 8:6 ]};
7'd6 : cu_mvd_idx_r <= {mvd_idx_i[ 26:24 ],mvd_idx_i[ 38:36 ],mvd_idx_i[ 32:30 ]};
7'd7 : cu_mvd_idx_r <= {mvd_idx_i[ 50:48 ],mvd_idx_i[ 62:60 ],mvd_idx_i[ 56:54 ]};
7'd8 : cu_mvd_idx_r <= {mvd_idx_i[ 74:72 ],mvd_idx_i[ 86:84 ],mvd_idx_i[ 80:78 ]};
7'd9 : cu_mvd_idx_r <= {mvd_idx_i[ 98:96 ],mvd_idx_i[110:108],mvd_idx_i[104:102]};
7'd10 : cu_mvd_idx_r <= {mvd_idx_i[122:120],mvd_idx_i[134:132],mvd_idx_i[128:126]};
7'd11 : cu_mvd_idx_r <= {mvd_idx_i[146:144],mvd_idx_i[158:156],mvd_idx_i[152:150]};
7'd12 : cu_mvd_idx_r <= {mvd_idx_i[170:168],mvd_idx_i[182:180],mvd_idx_i[176:174]};
7'd13 : cu_mvd_idx_r <= {mvd_idx_i[194:192],mvd_idx_i[206:204],mvd_idx_i[200:198]};
7'd14 : cu_mvd_idx_r <= {mvd_idx_i[218:216],mvd_idx_i[230:228],mvd_idx_i[224:222]};
7'd15 : cu_mvd_idx_r <= {mvd_idx_i[242:240],mvd_idx_i[254:252],mvd_idx_i[248:246]};
7'd16 : cu_mvd_idx_r <= {mvd_idx_i[266:264],mvd_idx_i[278:276],mvd_idx_i[272:270]};
7'd17 : cu_mvd_idx_r <= {mvd_idx_i[290:288],mvd_idx_i[302:300],mvd_idx_i[296:294]};
7'd18 : cu_mvd_idx_r <= {mvd_idx_i[314:312],mvd_idx_i[326:324],mvd_idx_i[320:318]};
7'd19 : cu_mvd_idx_r <= {mvd_idx_i[338:336],mvd_idx_i[350:348],mvd_idx_i[344:342]};
7'd20 : cu_mvd_idx_r <= {mvd_idx_i[362:360],mvd_idx_i[374:372],mvd_idx_i[368:366]};
7'd21 : cu_mvd_idx_r <= {mvd_idx_i[ 2:0 ],mvd_idx_i[ 5:3 ],mvd_idx_i[ 5:3 ]};
7'd22 : cu_mvd_idx_r <= {mvd_idx_i[ 8:6 ],mvd_idx_i[ 11:9 ],mvd_idx_i[ 11:9 ]};
7'd23 : cu_mvd_idx_r <= {mvd_idx_i[ 14:12 ],mvd_idx_i[ 17:15 ],mvd_idx_i[ 17:15 ]};
7'd24 : cu_mvd_idx_r <= {mvd_idx_i[ 20:18 ],mvd_idx_i[ 23:21 ],mvd_idx_i[ 23:21 ]};
7'd25 : cu_mvd_idx_r <= {mvd_idx_i[ 26:24 ],mvd_idx_i[ 29:27 ],mvd_idx_i[ 29:27 ]};
7'd26 : cu_mvd_idx_r <= {mvd_idx_i[ 32:30 ],mvd_idx_i[ 35:33 ],mvd_idx_i[ 35:33 ]};
7'd27 : cu_mvd_idx_r <= {mvd_idx_i[ 38:36 ],mvd_idx_i[ 41:39 ],mvd_idx_i[ 41:39 ]};
7'd28 : cu_mvd_idx_r <= {mvd_idx_i[ 44:42 ],mvd_idx_i[ 47:45 ],mvd_idx_i[ 47:45 ]};
7'd29 : cu_mvd_idx_r <= {mvd_idx_i[ 50:48 ],mvd_idx_i[ 53:51 ],mvd_idx_i[ 53:51 ]};
7'd30 : cu_mvd_idx_r <= {mvd_idx_i[ 56:54 ],mvd_idx_i[ 59:57 ],mvd_idx_i[ 59:57 ]};
7'd31 : cu_mvd_idx_r <= {mvd_idx_i[ 62:60 ],mvd_idx_i[ 65:63 ],mvd_idx_i[ 65:63 ]};
7'd32 : cu_mvd_idx_r <= {mvd_idx_i[ 68:66 ],mvd_idx_i[ 71:69 ],mvd_idx_i[ 71:69 ]};
7'd33 : cu_mvd_idx_r <= {mvd_idx_i[ 74:72 ],mvd_idx_i[ 77:75 ],mvd_idx_i[ 77:75 ]};
7'd34 : cu_mvd_idx_r <= {mvd_idx_i[ 80:78 ],mvd_idx_i[ 83:81 ],mvd_idx_i[ 83:81 ]};
7'd35 : cu_mvd_idx_r <= {mvd_idx_i[ 86:84 ],mvd_idx_i[ 89:87 ],mvd_idx_i[ 89:87 ]};
7'd36 : cu_mvd_idx_r <= {mvd_idx_i[ 92:90 ],mvd_idx_i[ 95:93 ],mvd_idx_i[ 95:93 ]};
7'd37 : cu_mvd_idx_r <= {mvd_idx_i[ 98:96 ],mvd_idx_i[101:99 ],mvd_idx_i[101:99 ]};
7'd38 : cu_mvd_idx_r <= {mvd_idx_i[104:102],mvd_idx_i[107:105],mvd_idx_i[107:105]};
7'd39 : cu_mvd_idx_r <= {mvd_idx_i[110:108],mvd_idx_i[113:111],mvd_idx_i[113:111]};
7'd40 : cu_mvd_idx_r <= {mvd_idx_i[116:114],mvd_idx_i[119:117],mvd_idx_i[119:117]};
7'd41 : cu_mvd_idx_r <= {mvd_idx_i[122:120],mvd_idx_i[125:123],mvd_idx_i[125:123]};
7'd42 : cu_mvd_idx_r <= {mvd_idx_i[128:126],mvd_idx_i[131:129],mvd_idx_i[131:129]};
7'd43 : cu_mvd_idx_r <= {mvd_idx_i[134:132],mvd_idx_i[137:135],mvd_idx_i[137:135]};
7'd44 : cu_mvd_idx_r <= {mvd_idx_i[140:138],mvd_idx_i[143:141],mvd_idx_i[143:141]};
7'd45 : cu_mvd_idx_r <= {mvd_idx_i[146:144],mvd_idx_i[149:147],mvd_idx_i[149:147]};
7'd46 : cu_mvd_idx_r <= {mvd_idx_i[152:150],mvd_idx_i[155:153],mvd_idx_i[155:153]};
7'd47 : cu_mvd_idx_r <= {mvd_idx_i[158:156],mvd_idx_i[161:159],mvd_idx_i[161:159]};
7'd48 : cu_mvd_idx_r <= {mvd_idx_i[164:162],mvd_idx_i[167:165],mvd_idx_i[167:165]};
7'd49 : cu_mvd_idx_r <= {mvd_idx_i[170:168],mvd_idx_i[173:171],mvd_idx_i[173:171]};
7'd50 : cu_mvd_idx_r <= {mvd_idx_i[176:174],mvd_idx_i[179:177],mvd_idx_i[179:177]};
7'd51 : cu_mvd_idx_r <= {mvd_idx_i[182:180],mvd_idx_i[185:183],mvd_idx_i[185:183]};
7'd52 : cu_mvd_idx_r <= {mvd_idx_i[188:186],mvd_idx_i[191:189],mvd_idx_i[191:189]};
7'd53 : cu_mvd_idx_r <= {mvd_idx_i[194:192],mvd_idx_i[197:195],mvd_idx_i[197:195]};
7'd54 : cu_mvd_idx_r <= {mvd_idx_i[200:198],mvd_idx_i[203:201],mvd_idx_i[203:201]};
7'd55 : cu_mvd_idx_r <= {mvd_idx_i[206:204],mvd_idx_i[209:207],mvd_idx_i[209:207]};
7'd56 : cu_mvd_idx_r <= {mvd_idx_i[212:210],mvd_idx_i[215:213],mvd_idx_i[215:213]};
7'd57 : cu_mvd_idx_r <= {mvd_idx_i[218:216],mvd_idx_i[221:219],mvd_idx_i[221:219]};
7'd58 : cu_mvd_idx_r <= {mvd_idx_i[224:222],mvd_idx_i[227:225],mvd_idx_i[227:225]};
7'd59 : cu_mvd_idx_r <= {mvd_idx_i[230:228],mvd_idx_i[233:231],mvd_idx_i[233:231]};
7'd60 : cu_mvd_idx_r <= {mvd_idx_i[236:234],mvd_idx_i[239:237],mvd_idx_i[239:237]};
7'd61 : cu_mvd_idx_r <= {mvd_idx_i[242:240],mvd_idx_i[245:243],mvd_idx_i[245:243]};
7'd62 : cu_mvd_idx_r <= {mvd_idx_i[248:246],mvd_idx_i[251:249],mvd_idx_i[251:249]};
7'd63 : cu_mvd_idx_r <= {mvd_idx_i[254:252],mvd_idx_i[257:255],mvd_idx_i[257:255]};
7'd64 : cu_mvd_idx_r <= {mvd_idx_i[260:258],mvd_idx_i[263:261],mvd_idx_i[263:261]};
7'd65 : cu_mvd_idx_r <= {mvd_idx_i[266:264],mvd_idx_i[269:267],mvd_idx_i[269:267]};
7'd66 : cu_mvd_idx_r <= {mvd_idx_i[272:270],mvd_idx_i[275:273],mvd_idx_i[275:273]};
7'd67 : cu_mvd_idx_r <= {mvd_idx_i[278:276],mvd_idx_i[281:279],mvd_idx_i[281:279]};
7'd68 : cu_mvd_idx_r <= {mvd_idx_i[284:282],mvd_idx_i[287:285],mvd_idx_i[287:285]};
7'd69 : cu_mvd_idx_r <= {mvd_idx_i[290:288],mvd_idx_i[293:291],mvd_idx_i[293:291]};
7'd70 : cu_mvd_idx_r <= {mvd_idx_i[296:294],mvd_idx_i[299:297],mvd_idx_i[299:297]};
7'd71 : cu_mvd_idx_r <= {mvd_idx_i[302:300],mvd_idx_i[305:303],mvd_idx_i[305:303]};
7'd72 : cu_mvd_idx_r <= {mvd_idx_i[308:306],mvd_idx_i[311:309],mvd_idx_i[311:309]};
7'd73 : cu_mvd_idx_r <= {mvd_idx_i[314:312],mvd_idx_i[317:315],mvd_idx_i[317:315]};
7'd74 : cu_mvd_idx_r <= {mvd_idx_i[320:318],mvd_idx_i[323:321],mvd_idx_i[323:321]};
7'd75 : cu_mvd_idx_r <= {mvd_idx_i[326:324],mvd_idx_i[329:327],mvd_idx_i[329:327]};
7'd76 : cu_mvd_idx_r <= {mvd_idx_i[332:330],mvd_idx_i[335:333],mvd_idx_i[335:333]};
7'd77 : cu_mvd_idx_r <= {mvd_idx_i[338:336],mvd_idx_i[341:339],mvd_idx_i[341:339]};
7'd78 : cu_mvd_idx_r <= {mvd_idx_i[344:342],mvd_idx_i[347:345],mvd_idx_i[347:345]};
7'd79 : cu_mvd_idx_r <= {mvd_idx_i[350:348],mvd_idx_i[353:351],mvd_idx_i[353:351]};
7'd80 : cu_mvd_idx_r <= {mvd_idx_i[356:354],mvd_idx_i[359:357],mvd_idx_i[359:357]};
7'd81 : cu_mvd_idx_r <= {mvd_idx_i[362:360],mvd_idx_i[365:363],mvd_idx_i[365:363]};
7'd82 : cu_mvd_idx_r <= {mvd_idx_i[368:366],mvd_idx_i[371:369],mvd_idx_i[371:369]};
7'd83 : cu_mvd_idx_r <= {mvd_idx_i[374:372],mvd_idx_i[377:375],mvd_idx_i[377:375]};
7'd84 : cu_mvd_idx_r <= {mvd_idx_i[380:378],mvd_idx_i[383:381],mvd_idx_i[383:381]};
default : cu_mvd_idx_r <= 9'd0 ;
endcase
end
end
*/
// cu_qp_nocoded_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_qp_nocoded_r <= 1'b1 ;
else if(!cu_idx_r)
cu_qp_nocoded_r <= 1'b1 ;
else
cu_qp_nocoded_r <= cu_qp_coded_flag_w ;
end
// cu_qp_last_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_qp_last_r <= 6'd0 ;
else if(lcu_curr_state_r[2]&&(luma_cbf_i||cr_cbf_i||cb_cbf_i))
cu_qp_last_r <= lcu_qp_i ;
else if(mb_x_i==0 && mb_y_i ==0)
cu_qp_last_r <= param_qp_i ;
end
// mode info
// cu_luma_mode_ren_o
always @* begin
if(cu_start_r || cu_start_d1_r || cu_start_d2_r)
cu_luma_mode_ren_o = 1'b0 ;
else
cu_luma_mode_ren_o = 1'b1 ;
end
// cu_luma_mode_raddr_o
always @* begin
if(cu_start_r )
cu_luma_mode_raddr_o = cu_luma_left_mode_raddr_r ;
else if(cu_start_d1_r)
cu_luma_mode_raddr_o = cu_luma_mode_raddr_r ;
else if(cu_start_d2_r)
cu_luma_mode_raddr_o = cu_luma_top_mode_raddr_r ;
else
cu_luma_mode_raddr_o = 6'd0 ;
end
// cu_luma_mode_raddr_r
always @* begin
case(cu_idx_r)
7'd0 : cu_luma_mode_raddr_r = 6'd0 ;
7'd1 : cu_luma_mode_raddr_r = 6'd0 ;
7'd2 : cu_luma_mode_raddr_r = 6'd16 ;
7'd3 : cu_luma_mode_raddr_r = 6'd32 ;
7'd4 : cu_luma_mode_raddr_r = 6'd48 ;
7'd5 : cu_luma_mode_raddr_r = 6'd0 ;
7'd6 : cu_luma_mode_raddr_r = 6'd4 ;
7'd7 : cu_luma_mode_raddr_r = 6'd8 ;
7'd8 : cu_luma_mode_raddr_r = 6'd12 ;
7'd9 : cu_luma_mode_raddr_r = 6'd16 ;
7'd10: cu_luma_mode_raddr_r = 6'd20 ;
7'd11: cu_luma_mode_raddr_r = 6'd24 ;
7'd12: cu_luma_mode_raddr_r = 6'd28 ;
7'd13: cu_luma_mode_raddr_r = 6'd32 ;
7'd14: cu_luma_mode_raddr_r = 6'd36 ;
7'd15: cu_luma_mode_raddr_r = 6'd40 ;
7'd16: cu_luma_mode_raddr_r = 6'd44 ;
7'd17: cu_luma_mode_raddr_r = 6'd48 ;
7'd18: cu_luma_mode_raddr_r = 6'd52 ;
7'd19: cu_luma_mode_raddr_r = 6'd56 ;
7'd20: cu_luma_mode_raddr_r = 6'd60 ;
default: cu_luma_mode_raddr_r = cu_idx_r - 5'd21 ;
endcase
end
/*
always @* begin
case(cu_idx_r)
7'd0 : cu_luma_top_mode_raddr_r = 6'd0 ;
7'd1 : cu_luma_top_mode_raddr_r = 6'd0 ;
7'd2 : cu_luma_top_mode_raddr_r = 6'd0 ;
7'd3 : cu_luma_top_mode_raddr_r = 6'd10 ;
7'd4 : cu_luma_top_mode_raddr_r = 6'd26 ;
7'd5 : cu_luma_top_mode_raddr_r = 6'd0 ;
7'd6 : cu_luma_top_mode_raddr_r = 6'd0 ;
7'd7 : cu_luma_top_mode_raddr_r = 6'd2 ;
7'd8 : cu_luma_top_mode_raddr_r = 6'd6 ;
7'd9 : cu_luma_top_mode_raddr_r = 6'd0 ;
7'd10: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd11: cu_luma_top_mode_raddr_r = 6'd18 ;
7'd12: cu_luma_top_mode_raddr_r = 6'd22 ;
7'd13: cu_luma_top_mode_raddr_r = 6'd10 ;
7'd14: cu_luma_top_mode_raddr_r = 6'd14 ;
7'd15: cu_luma_top_mode_raddr_r = 6'd34 ;
7'd16: cu_luma_top_mode_raddr_r = 6'd38 ;
7'd17: cu_luma_top_mode_raddr_r = 6'd26 ;
7'd18: cu_luma_top_mode_raddr_r = 6'd30 ;
7'd19: cu_luma_top_mode_raddr_r = 6'd50 ;
7'd20: cu_luma_top_mode_raddr_r = 6'd54 ;
7'd21: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd22: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd23: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd24: cu_luma_top_mode_raddr_r = 6'd1 ;
7'd25: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd26: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd27: cu_luma_top_mode_raddr_r = 6'd4 ;
7'd28: cu_luma_top_mode_raddr_r = 6'd5 ;
7'd29: cu_luma_top_mode_raddr_r = 6'd2 ;
7'd30: cu_luma_top_mode_raddr_r = 6'd3 ;
7'd31: cu_luma_top_mode_raddr_r = 6'd8 ;
7'd32: cu_luma_top_mode_raddr_r = 6'd9 ;
7'd33: cu_luma_top_mode_raddr_r = 6'd6 ;
7'd34: cu_luma_top_mode_raddr_r = 6'd7 ;
7'd35: cu_luma_top_mode_raddr_r = 6'd12 ;
7'd36: cu_luma_top_mode_raddr_r = 6'd13 ;
7'd37: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd38: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd39: cu_luma_top_mode_raddr_r = 6'd16 ;
7'd40: cu_luma_top_mode_raddr_r = 6'd17 ;
7'd41: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd42: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd43: cu_luma_top_mode_raddr_r = 6'd20 ;
7'd44: cu_luma_top_mode_raddr_r = 6'd21 ;
7'd45: cu_luma_top_mode_raddr_r = 6'd18 ;
7'd46: cu_luma_top_mode_raddr_r = 6'd19 ;
7'd47: cu_luma_top_mode_raddr_r = 6'd24 ;
7'd48: cu_luma_top_mode_raddr_r = 6'd25 ;
7'd49: cu_luma_top_mode_raddr_r = 6'd22 ;
7'd50: cu_luma_top_mode_raddr_r = 6'd23 ;
7'd51: cu_luma_top_mode_raddr_r = 6'd28 ;
7'd52: cu_luma_top_mode_raddr_r = 6'd29 ;
7'd53: cu_luma_top_mode_raddr_r = 6'd10 ;
7'd54: cu_luma_top_mode_raddr_r = 6'd11 ;
7'd55: cu_luma_top_mode_raddr_r = 6'd32 ;
7'd56: cu_luma_top_mode_raddr_r = 6'd33 ;
7'd57: cu_luma_top_mode_raddr_r = 6'd14 ;
7'd58: cu_luma_top_mode_raddr_r = 6'd15 ;
7'd59: cu_luma_top_mode_raddr_r = 6'd36 ;
7'd60: cu_luma_top_mode_raddr_r = 6'd37 ;
7'd61: cu_luma_top_mode_raddr_r = 6'd34 ;
7'd62: cu_luma_top_mode_raddr_r = 6'd35 ;
7'd63: cu_luma_top_mode_raddr_r = 6'd40 ;
7'd64: cu_luma_top_mode_raddr_r = 6'd41 ;
7'd65: cu_luma_top_mode_raddr_r = 6'd38 ;
7'd66: cu_luma_top_mode_raddr_r = 6'd39 ;
7'd67: cu_luma_top_mode_raddr_r = 6'd44 ;
7'd68: cu_luma_top_mode_raddr_r = 6'd45 ;
7'd69: cu_luma_top_mode_raddr_r = 6'd26 ;
7'd70: cu_luma_top_mode_raddr_r = 6'd27 ;
7'd71: cu_luma_top_mode_raddr_r = 6'd48 ;
7'd72: cu_luma_top_mode_raddr_r = 6'd49 ;
7'd73: cu_luma_top_mode_raddr_r = 6'd30 ;
7'd74: cu_luma_top_mode_raddr_r = 6'd31 ;
7'd75: cu_luma_top_mode_raddr_r = 6'd52 ;
7'd76: cu_luma_top_mode_raddr_r = 6'd53 ;
7'd77: cu_luma_top_mode_raddr_r = 6'd50 ;
7'd78: cu_luma_top_mode_raddr_r = 6'd51 ;
7'd79: cu_luma_top_mode_raddr_r = 6'd56 ;
7'd80: cu_luma_top_mode_raddr_r = 6'd57 ;
7'd81: cu_luma_top_mode_raddr_r = 6'd54 ;
7'd82: cu_luma_top_mode_raddr_r = 6'd55 ;
7'd83: cu_luma_top_mode_raddr_r = 6'd60 ;
7'd84: cu_luma_top_mode_raddr_r = 6'd61 ;
default: cu_luma_top_mode_raddr_r = 6'd0 ;
endcase
end
always @* begin
case(cu_idx_r)
7'd0 : cu_luma_left_mode_raddr_r = 6'd0 ;
7'd1 : cu_luma_left_mode_raddr_r = 6'd0 ;
7'd2 : cu_luma_left_mode_raddr_r = 6'd5 ;
7'd3 : cu_luma_left_mode_raddr_r = 6'd0 ;
7'd4 : cu_luma_left_mode_raddr_r = 6'd37 ;
7'd5 : cu_luma_left_mode_raddr_r = 6'd0 ;
7'd6 : cu_luma_left_mode_raddr_r = 6'd1 ;
7'd7 : cu_luma_left_mode_raddr_r = 6'd0 ;
7'd8 : cu_luma_left_mode_raddr_r = 6'd9 ;
7'd9 : cu_luma_left_mode_raddr_r = 6'd5 ;
7'd10: cu_luma_left_mode_raddr_r = 6'd17 ;
7'd11: cu_luma_left_mode_raddr_r = 6'd13 ;
7'd12: cu_luma_left_mode_raddr_r = 6'd25 ;
7'd13: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd14: cu_luma_left_mode_raddr_r = 6'd33 ;
7'd15: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd16: cu_luma_left_mode_raddr_r = 6'd41 ;
7'd17: cu_luma_left_mode_raddr_r = 6'd37 ;
7'd18: cu_luma_left_mode_raddr_r = 6'd49 ;
7'd19: cu_luma_left_mode_raddr_r = 6'd45 ;
7'd20: cu_luma_left_mode_raddr_r = 6'd57 ;
7'd21: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd22: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd23: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd24: cu_luma_left_mode_raddr_r = 6'd2 ;
7'd25: cu_luma_left_mode_raddr_r = 6'd1 ;
7'd26: cu_luma_left_mode_raddr_r = 6'd4 ;
7'd27: cu_luma_left_mode_raddr_r = 6'd3 ;
7'd28: cu_luma_left_mode_raddr_r = 6'd6 ;
7'd29: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd30: cu_luma_left_mode_raddr_r = 6'd8 ;
7'd31: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd32: cu_luma_left_mode_raddr_r = 6'd10 ;
7'd33: cu_luma_left_mode_raddr_r = 6'd9 ;
7'd34: cu_luma_left_mode_raddr_r = 6'd12 ;
7'd35: cu_luma_left_mode_raddr_r = 6'd11 ;
7'd36: cu_luma_left_mode_raddr_r = 6'd14 ;
7'd37: cu_luma_left_mode_raddr_r = 6'd5 ;
7'd38: cu_luma_left_mode_raddr_r = 6'd16 ;
7'd39: cu_luma_left_mode_raddr_r = 6'd7 ;
7'd40: cu_luma_left_mode_raddr_r = 6'd18 ;
7'd41: cu_luma_left_mode_raddr_r = 6'd17 ;
7'd42: cu_luma_left_mode_raddr_r = 6'd20 ;
7'd43: cu_luma_left_mode_raddr_r = 6'd19 ;
7'd44: cu_luma_left_mode_raddr_r = 6'd22 ;
7'd45: cu_luma_left_mode_raddr_r = 6'd13 ;
7'd46: cu_luma_left_mode_raddr_r = 6'd24 ;
7'd47: cu_luma_left_mode_raddr_r = 6'd15 ;
7'd48: cu_luma_left_mode_raddr_r = 6'd26 ;
7'd49: cu_luma_left_mode_raddr_r = 6'd25 ;
7'd50: cu_luma_left_mode_raddr_r = 6'd28 ;
7'd51: cu_luma_left_mode_raddr_r = 6'd27 ;
7'd52: cu_luma_left_mode_raddr_r = 6'd30 ;
7'd53: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd54: cu_luma_left_mode_raddr_r = 6'd32 ;
7'd55: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd56: cu_luma_left_mode_raddr_r = 6'd34 ;
7'd57: cu_luma_left_mode_raddr_r = 6'd33 ;
7'd58: cu_luma_left_mode_raddr_r = 6'd36 ;
7'd59: cu_luma_left_mode_raddr_r = 6'd35 ;
7'd60: cu_luma_left_mode_raddr_r = 6'd38 ;
7'd61: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd62: cu_luma_left_mode_raddr_r = 6'd40 ;
7'd63: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd64: cu_luma_left_mode_raddr_r = 6'd42 ;
7'd65: cu_luma_left_mode_raddr_r = 6'd41 ;
7'd66: cu_luma_left_mode_raddr_r = 6'd44 ;
7'd67: cu_luma_left_mode_raddr_r = 6'd43 ;
7'd68: cu_luma_left_mode_raddr_r = 6'd46 ;
7'd69: cu_luma_left_mode_raddr_r = 6'd37 ;
7'd70: cu_luma_left_mode_raddr_r = 6'd48 ;
7'd71: cu_luma_left_mode_raddr_r = 6'd39 ;
7'd72: cu_luma_left_mode_raddr_r = 6'd50 ;
7'd73: cu_luma_left_mode_raddr_r = 6'd49 ;
7'd74: cu_luma_left_mode_raddr_r = 6'd52 ;
7'd75: cu_luma_left_mode_raddr_r = 6'd51 ;
7'd76: cu_luma_left_mode_raddr_r = 6'd54 ;
7'd77: cu_luma_left_mode_raddr_r = 6'd45 ;
7'd78: cu_luma_left_mode_raddr_r = 6'd56 ;
7'd79: cu_luma_left_mode_raddr_r = 6'd47 ;
7'd80: cu_luma_left_mode_raddr_r = 6'd58 ;
7'd81: cu_luma_left_mode_raddr_r = 6'd57 ;
7'd82: cu_luma_left_mode_raddr_r = 6'd60 ;
7'd83: cu_luma_left_mode_raddr_r = 6'd59 ;
7'd84: cu_luma_left_mode_raddr_r = 6'd62 ;
default: cu_luma_left_mode_raddr_r = 6'd0 ;
endcase
end
*/
// cu_luma_top_mode_raddr_r
always @* begin
case(cu_idx_r)
7'd3 : cu_luma_top_mode_raddr_r = cu_depth_2_0_r==2'd3 ? 6'd10 :(cu_depth_2_0_r==2'd2 ? 6'd8 :6'd0 );
7'd4 : cu_luma_top_mode_raddr_r = cu_depth_2_4_r==2'd3 ? 6'd26 :(cu_depth_2_4_r==2'd2 ? 6'd24:6'd16);
7'd7 : cu_luma_top_mode_raddr_r = cu_depth_0_0_r==2'd3 ? 6'd2 :6'd0 ;
7'd8 : cu_luma_top_mode_raddr_r = cu_depth_0_2_r==2'd3 ? 6'd6 :6'd4 ;
7'd11: cu_luma_top_mode_raddr_r = cu_depth_0_4_r==2'd3 ? 6'd18 :6'd16 ;
7'd12: cu_luma_top_mode_raddr_r = cu_depth_0_6_r==2'd3 ? 6'd22 :6'd20 ;
7'd13: cu_luma_top_mode_raddr_r = cu_depth_2_0_r==2'd3 ? 6'd10 :(cu_depth_2_0_r==2'd2 ? 6'd8 :6'd0 );
7'd14: cu_luma_top_mode_raddr_r = cu_depth_2_2_r==2'd3 ? 6'd14 :(cu_depth_2_2_r==2'd2 ? 6'd12:6'd0 );
7'd15: cu_luma_top_mode_raddr_r = cu_depth_4_0_r==2'd3 ? 6'd34 :6'd32 ;
7'd16: cu_luma_top_mode_raddr_r = cu_depth_4_2_r==2'd3 ? 6'd38 :6'd36 ;
7'd17: cu_luma_top_mode_raddr_r = cu_depth_2_4_r==2'd3 ? 6'd26 :(cu_depth_2_4_r==2'd2 ? 6'd24:6'd16);
7'd18: cu_luma_top_mode_raddr_r = cu_depth_2_6_r==2'd3 ? 6'd30 :(cu_depth_2_6_r==2'd2 ? 6'd28:6'd16);
7'd19: cu_luma_top_mode_raddr_r = cu_depth_4_4_r==2'd3 ? 6'd50 :6'd48 ;
7'd20: cu_luma_top_mode_raddr_r = cu_depth_4_6_r==2'd3 ? 6'd54 :6'd52 ;
7'd23: cu_luma_top_mode_raddr_r = 6'd0 ;
7'd24: cu_luma_top_mode_raddr_r = 6'd1 ;
7'd27: cu_luma_top_mode_raddr_r = 6'd4 ;
7'd28: cu_luma_top_mode_raddr_r = 6'd5 ;
7'd29: cu_luma_top_mode_raddr_r = cu_depth_0_0_r==2'd3 ? 6'd2 :6'd0 ;
7'd30: cu_luma_top_mode_raddr_r = cu_depth_0_0_r==2'd3 ? 6'd3 :6'd0 ;
7'd31: cu_luma_top_mode_raddr_r = 6'd8 ;
7'd32: cu_luma_top_mode_raddr_r = 6'd9 ;
7'd33: cu_luma_top_mode_raddr_r = cu_depth_0_2_r==2'd3 ? 6'd6 :6'd4 ;
7'd34: cu_luma_top_mode_raddr_r = cu_depth_0_2_r==2'd3 ? 6'd7 :6'd4 ;
7'd35: cu_luma_top_mode_raddr_r = 6'd12 ;
7'd36: cu_luma_top_mode_raddr_r = 6'd13 ;
7'd39: cu_luma_top_mode_raddr_r = 6'd16 ;
7'd40: cu_luma_top_mode_raddr_r = 6'd17 ;
7'd43: cu_luma_top_mode_raddr_r = 6'd20 ;
7'd44: cu_luma_top_mode_raddr_r = 6'd21 ;
7'd45: cu_luma_top_mode_raddr_r = cu_depth_0_4_r==2'd3 ? 6'd18 :6'd16 ;
7'd46: cu_luma_top_mode_raddr_r = cu_depth_0_4_r==2'd3 ? 6'd19 :6'd16 ;
7'd47: cu_luma_top_mode_raddr_r = 6'd24 ;
7'd48: cu_luma_top_mode_raddr_r = 6'd25 ;
7'd49: cu_luma_top_mode_raddr_r = cu_depth_0_6_r==2'd3 ? 6'd22 :6'd20 ;
7'd50: cu_luma_top_mode_raddr_r = cu_depth_0_6_r==2'd3 ? 6'd23 :6'd20 ;
7'd51: cu_luma_top_mode_raddr_r = 6'd28 ;
7'd52: cu_luma_top_mode_raddr_r = 6'd29 ;
7'd53: cu_luma_top_mode_raddr_r = cu_depth_2_0_r==2'd3 ? 6'd10 :(cu_depth_2_0_r==2'd2 ? 6'd8 :6'd0 );
7'd54: cu_luma_top_mode_raddr_r = cu_depth_2_0_r==2'd3 ? 6'd11 :(cu_depth_2_0_r==2'd2 ? 6'd8 :6'd0 );
7'd55: cu_luma_top_mode_raddr_r = 6'd32 ;
7'd56: cu_luma_top_mode_raddr_r = 6'd33 ;
7'd57: cu_luma_top_mode_raddr_r = cu_depth_2_2_r==2'd3 ? 6'd14 :(cu_depth_2_2_r==2'd2 ? 6'd12:6'd0 );
7'd58: cu_luma_top_mode_raddr_r = cu_depth_2_2_r==2'd3 ? 6'd15 :(cu_depth_2_2_r==2'd2 ? 6'd12:6'd0 );
7'd59: cu_luma_top_mode_raddr_r = 6'd36 ;
7'd60: cu_luma_top_mode_raddr_r = 6'd37 ;
7'd61: cu_luma_top_mode_raddr_r = cu_depth_4_0_r==2'd3 ? 6'd34 :6'd32 ;
7'd62: cu_luma_top_mode_raddr_r = cu_depth_4_0_r==2'd3 ? 6'd35 :6'd32 ;
7'd63: cu_luma_top_mode_raddr_r = 6'd40 ;
7'd64: cu_luma_top_mode_raddr_r = 6'd41 ;
7'd65: cu_luma_top_mode_raddr_r = cu_depth_4_2_r==2'd3 ? 6'd38 :6'd36 ;
7'd66: cu_luma_top_mode_raddr_r = cu_depth_4_2_r==2'd3 ? 6'd39 :6'd36 ;
7'd67: cu_luma_top_mode_raddr_r = 6'd44 ;
7'd68: cu_luma_top_mode_raddr_r = 6'd45 ;
7'd69: cu_luma_top_mode_raddr_r = cu_depth_2_4_r==2'd3 ? 6'd26 :(cu_depth_2_4_r==2'd2 ? 6'd24:6'd16);
7'd70: cu_luma_top_mode_raddr_r = cu_depth_2_4_r==2'd3 ? 6'd27 :(cu_depth_2_4_r==2'd2 ? 6'd24:6'd16);
7'd71: cu_luma_top_mode_raddr_r = 6'd48 ;
7'd72: cu_luma_top_mode_raddr_r = 6'd49 ;
7'd73: cu_luma_top_mode_raddr_r = cu_depth_2_6_r==2'd3 ? 6'd30 :(cu_depth_2_6_r==2'd2 ? 6'd28:6'd16);
7'd74: cu_luma_top_mode_raddr_r = cu_depth_2_6_r==2'd3 ? 6'd31 :(cu_depth_2_6_r==2'd2 ? 6'd28:6'd16);
7'd75: cu_luma_top_mode_raddr_r = 6'd52 ;
7'd76: cu_luma_top_mode_raddr_r = 6'd53 ;
7'd77: cu_luma_top_mode_raddr_r = cu_depth_4_4_r==2'd3 ? 6'd50 :6'd48 ;
7'd78: cu_luma_top_mode_raddr_r = cu_depth_4_4_r==2'd3 ? 6'd51 :6'd48 ;
7'd79: cu_luma_top_mode_raddr_r = 6'd56 ;
7'd80: cu_luma_top_mode_raddr_r = 6'd57 ;
7'd81: cu_luma_top_mode_raddr_r = cu_depth_4_6_r==2'd3 ? 6'd54 :6'd52 ;
7'd82: cu_luma_top_mode_raddr_r = cu_depth_4_6_r==2'd3 ? 6'd55 :6'd52 ;
7'd83: cu_luma_top_mode_raddr_r = 6'd60 ;
7'd84: cu_luma_top_mode_raddr_r = 6'd61 ;
default: cu_luma_top_mode_raddr_r = 6'd0 ;
endcase
end
// cu_luma_left_mode_raddr_r
always @* begin
case(cu_idx_r)
7'd2 : cu_luma_left_mode_raddr_r = cu_depth_0_2_r==2'd3 ? 6'd5 :(cu_depth_0_2_r==2'd2 ? 6'd4 :6'd0 );
7'd4 : cu_luma_left_mode_raddr_r = cu_depth_4_2_r==2'd3 ? 6'd37:(cu_depth_4_2_r==2'd2 ? 6'd36:6'd32);
7'd6 : cu_luma_left_mode_raddr_r = cu_depth_0_0_r==2'd3 ? 6'd1 :6'd0 ;
7'd8 : cu_luma_left_mode_raddr_r = cu_depth_2_0_r==2'd3 ? 6'd9 :6'd8 ;
7'd9 : cu_luma_left_mode_raddr_r = cu_depth_0_2_r==2'd3 ? 6'd5 :(cu_depth_0_2_r==2'd2 ? 6'd4 :6'd0 );
7'd10: cu_luma_left_mode_raddr_r = cu_depth_0_4_r==2'd3 ? 6'd17:6'd16 ;
7'd11: cu_luma_left_mode_raddr_r = cu_depth_2_2_r==2'd3 ? 6'd13:(cu_depth_2_2_r==2'd2 ? 6'd12:6'd0 );
7'd12: cu_luma_left_mode_raddr_r = cu_depth_2_4_r==2'd3 ? 6'd25:6'd24 ;
7'd14: cu_luma_left_mode_raddr_r = cu_depth_4_0_r==2'd3 ? 6'd33:6'd32 ;
7'd16: cu_luma_left_mode_raddr_r = cu_depth_6_0_r==2'd3 ? 6'd41:6'd40 ;
7'd17: cu_luma_left_mode_raddr_r = cu_depth_4_2_r==2'd3 ? 6'd37:(cu_depth_4_2_r==2'd2 ? 6'd36:6'd32);
7'd18: cu_luma_left_mode_raddr_r = cu_depth_4_4_r==2'd3 ? 6'd49:6'd48 ;
7'd19: cu_luma_left_mode_raddr_r = cu_depth_6_2_r==2'd3 ? 6'd45:(cu_depth_6_2_r==2'd2 ? 6'd44:6'd32);
7'd20: cu_luma_left_mode_raddr_r = cu_depth_6_4_r==2'd3 ? 6'd57:6'd56 ;
7'd22: cu_luma_left_mode_raddr_r = 6'd0 ;
7'd24: cu_luma_left_mode_raddr_r = 6'd2 ;
7'd25: cu_luma_left_mode_raddr_r = cu_depth_0_0_r==2'd3 ? 6'd1 :6'd0 ;
7'd26: cu_luma_left_mode_raddr_r = 6'd4 ;
7'd27: cu_luma_left_mode_raddr_r = cu_depth_0_0_r==2'd3 ? 6'd3 :6'd0 ;
7'd28: cu_luma_left_mode_raddr_r = 6'd6 ;
7'd30: cu_luma_left_mode_raddr_r = 6'd8 ;
7'd32: cu_luma_left_mode_raddr_r = 6'd10 ;
7'd33: cu_luma_left_mode_raddr_r = cu_depth_2_0_r==2'd3 ? 6'd9 :6'd8 ;
7'd34: cu_luma_left_mode_raddr_r = 6'd12 ;
7'd35: cu_luma_left_mode_raddr_r = cu_depth_2_0_r==2'd3 ? 6'd11:6'd8 ;
7'd36: cu_luma_left_mode_raddr_r = 6'd14 ;
7'd37: cu_luma_left_mode_raddr_r = cu_depth_0_2_r==2'd3 ? 6'd5 :(cu_depth_0_2_r==2'd2 ? 6'd4 :6'd0 );
7'd38: cu_luma_left_mode_raddr_r = 6'd16 ;
7'd39: cu_luma_left_mode_raddr_r = cu_depth_0_2_r==2'd3 ? 6'd7 :(cu_depth_0_2_r==2'd2 ? 6'd4 :6'd0 );
7'd40: cu_luma_left_mode_raddr_r = 6'd18 ;
7'd41: cu_luma_left_mode_raddr_r = cu_depth_0_4_r==2'd3 ? 6'd17:6'd16 ;
7'd42: cu_luma_left_mode_raddr_r = 6'd20 ;
7'd43: cu_luma_left_mode_raddr_r = cu_depth_0_4_r==2'd3 ? 6'd19:6'd16 ;
7'd44: cu_luma_left_mode_raddr_r = 6'd22 ;
7'd45: cu_luma_left_mode_raddr_r = cu_depth_2_2_r==2'd3 ? 6'd13:(cu_depth_2_2_r==2'd2 ? 6'd12:6'd0 );
7'd46: cu_luma_left_mode_raddr_r = 6'd24 ;
7'd47: cu_luma_left_mode_raddr_r = cu_depth_2_2_r==2'd3 ? 6'd15:(cu_depth_2_2_r==2'd2 ? 6'd12:6'd0 );
7'd48: cu_luma_left_mode_raddr_r = 6'd26 ;
7'd49: cu_luma_left_mode_raddr_r = cu_depth_2_4_r==2'd3 ? 6'd25:6'd24 ;
7'd50: cu_luma_left_mode_raddr_r = 6'd28 ;
7'd51: cu_luma_left_mode_raddr_r = cu_depth_2_4_r==2'd3 ? 6'd27:6'd24 ;
7'd52: cu_luma_left_mode_raddr_r = 6'd30 ;
7'd54: cu_luma_left_mode_raddr_r = 6'd32 ;
7'd56: cu_luma_left_mode_raddr_r = 6'd34 ;
7'd57: cu_luma_left_mode_raddr_r = cu_depth_4_0_r==2'd3 ? 6'd33:6'd32 ;
7'd58: cu_luma_left_mode_raddr_r = 6'd36 ;
7'd59: cu_luma_left_mode_raddr_r = cu_depth_4_0_r==2'd3 ? 6'd35:6'd32 ;
7'd60: cu_luma_left_mode_raddr_r = 6'd38 ;
7'd62: cu_luma_left_mode_raddr_r = 6'd40 ;
7'd64: cu_luma_left_mode_raddr_r = 6'd42 ;
7'd65: cu_luma_left_mode_raddr_r = cu_depth_6_0_r==2'd3 ? 6'd41:6'd40 ;
7'd66: cu_luma_left_mode_raddr_r = 6'd44 ;
7'd67: cu_luma_left_mode_raddr_r = cu_depth_6_0_r==2'd3 ? 6'd43:6'd40 ;
7'd68: cu_luma_left_mode_raddr_r = 6'd46 ;
7'd69: cu_luma_left_mode_raddr_r = cu_depth_4_2_r==2'd3 ? 6'd37:(cu_depth_4_2_r==2'd2 ? 6'd36:6'd32);
7'd70: cu_luma_left_mode_raddr_r = 6'd48 ;
7'd71: cu_luma_left_mode_raddr_r = cu_depth_4_2_r==2'd3 ? 6'd39:(cu_depth_4_2_r==2'd2 ? 6'd36:6'd32);
7'd72: cu_luma_left_mode_raddr_r = 6'd50 ;
7'd73: cu_luma_left_mode_raddr_r = cu_depth_4_4_r==2'd3 ? 6'd49:6'd48 ;
7'd74: cu_luma_left_mode_raddr_r = 6'd52 ;
7'd75: cu_luma_left_mode_raddr_r = cu_depth_4_4_r==2'd3 ? 6'd51:6'd48 ;
7'd76: cu_luma_left_mode_raddr_r = 6'd54 ;
7'd77: cu_luma_left_mode_raddr_r = cu_depth_6_2_r==2'd3 ? 6'd45:(cu_depth_6_2_r==2'd2 ? 6'd44:6'd32);
7'd78: cu_luma_left_mode_raddr_r = 6'd56 ;
7'd79: cu_luma_left_mode_raddr_r = cu_depth_6_2_r==2'd3 ? 6'd47:(cu_depth_6_2_r==2'd2 ? 6'd44:6'd32);
7'd80: cu_luma_left_mode_raddr_r = 6'd58 ;
7'd81: cu_luma_left_mode_raddr_r = cu_depth_6_4_r==2'd3 ? 6'd57:6'd56 ;
7'd82: cu_luma_left_mode_raddr_r = 6'd60 ;
7'd83: cu_luma_left_mode_raddr_r = cu_depth_6_4_r==2'd3 ? 6'd59:6'd56 ;
7'd84: cu_luma_left_mode_raddr_r = 6'd62 ;
default: cu_luma_left_mode_raddr_r = 6'd0 ;
endcase
end
// cu_chroma_mode_ren_o
always @* begin
if(cu_start_r)
cu_chroma_mode_ren_o = 1'b0 ;
else
cu_chroma_mode_ren_o = 1'b1 ;
end
// cu_chroma_mode_raddr_o
always @* begin
case(cu_idx_r)
7'd0 : cu_chroma_mode_raddr_o = 4'd0 ;
7'd1 : cu_chroma_mode_raddr_o = 4'd0 ;
7'd2 : cu_chroma_mode_raddr_o = 4'd4 ;
7'd3 : cu_chroma_mode_raddr_o = 4'd8 ;
7'd4 : cu_chroma_mode_raddr_o = 4'd12 ;
7'd5 : cu_chroma_mode_raddr_o = 4'd0 ;
7'd6 : cu_chroma_mode_raddr_o = 4'd1 ;
7'd7 : cu_chroma_mode_raddr_o = 4'd2 ;
7'd8 : cu_chroma_mode_raddr_o = 4'd3 ;
7'd9 : cu_chroma_mode_raddr_o = 4'd4 ;
7'd10: cu_chroma_mode_raddr_o = 4'd5 ;
7'd11: cu_chroma_mode_raddr_o = 4'd6 ;
7'd12: cu_chroma_mode_raddr_o = 4'd7 ;
7'd13: cu_chroma_mode_raddr_o = 4'd8 ;
7'd14: cu_chroma_mode_raddr_o = 4'd9 ;
7'd15: cu_chroma_mode_raddr_o = 4'd10 ;
7'd16: cu_chroma_mode_raddr_o = 4'd11 ;
7'd17: cu_chroma_mode_raddr_o = 4'd12 ;
7'd18: cu_chroma_mode_raddr_o = 4'd13 ;
7'd19: cu_chroma_mode_raddr_o = 4'd14 ;
7'd20: cu_chroma_mode_raddr_o = 4'd15 ;
7'd21: cu_chroma_mode_raddr_o = 4'd0 ;
7'd22: cu_chroma_mode_raddr_o = 4'd0 ;
7'd23: cu_chroma_mode_raddr_o = 4'd0 ;
7'd24: cu_chroma_mode_raddr_o = 4'd0 ;
7'd25: cu_chroma_mode_raddr_o = 4'd1 ;
7'd26: cu_chroma_mode_raddr_o = 4'd1 ;
7'd27: cu_chroma_mode_raddr_o = 4'd1 ;
7'd28: cu_chroma_mode_raddr_o = 4'd1 ;
7'd29: cu_chroma_mode_raddr_o = 4'd2 ;
7'd30: cu_chroma_mode_raddr_o = 4'd2 ;
7'd31: cu_chroma_mode_raddr_o = 4'd2 ;
7'd32: cu_chroma_mode_raddr_o = 4'd2 ;
7'd33: cu_chroma_mode_raddr_o = 4'd3 ;
7'd34: cu_chroma_mode_raddr_o = 4'd3 ;
7'd35: cu_chroma_mode_raddr_o = 4'd3 ;
7'd36: cu_chroma_mode_raddr_o = 4'd3 ;
7'd37: cu_chroma_mode_raddr_o = 4'd4 ;
7'd38: cu_chroma_mode_raddr_o = 4'd4 ;
7'd39: cu_chroma_mode_raddr_o = 4'd4 ;
7'd40: cu_chroma_mode_raddr_o = 4'd4 ;
7'd41: cu_chroma_mode_raddr_o = 4'd5 ;
7'd42: cu_chroma_mode_raddr_o = 4'd5 ;
7'd43: cu_chroma_mode_raddr_o = 4'd5 ;
7'd44: cu_chroma_mode_raddr_o = 4'd5 ;
7'd45: cu_chroma_mode_raddr_o = 4'd6 ;
7'd46: cu_chroma_mode_raddr_o = 4'd6 ;
7'd47: cu_chroma_mode_raddr_o = 4'd6 ;
7'd48: cu_chroma_mode_raddr_o = 4'd6 ;
7'd49: cu_chroma_mode_raddr_o = 4'd7 ;
7'd50: cu_chroma_mode_raddr_o = 4'd7 ;
7'd51: cu_chroma_mode_raddr_o = 4'd7 ;
7'd52: cu_chroma_mode_raddr_o = 4'd7 ;
7'd53: cu_chroma_mode_raddr_o = 4'd8 ;
7'd54: cu_chroma_mode_raddr_o = 4'd8 ;
7'd55: cu_chroma_mode_raddr_o = 4'd8 ;
7'd56: cu_chroma_mode_raddr_o = 4'd8 ;
7'd57: cu_chroma_mode_raddr_o = 4'd9 ;
7'd58: cu_chroma_mode_raddr_o = 4'd9 ;
7'd59: cu_chroma_mode_raddr_o = 4'd9 ;
7'd60: cu_chroma_mode_raddr_o = 4'd9 ;
7'd61: cu_chroma_mode_raddr_o = 4'd10 ;
7'd62: cu_chroma_mode_raddr_o = 4'd10 ;
7'd63: cu_chroma_mode_raddr_o = 4'd10 ;
7'd64: cu_chroma_mode_raddr_o = 4'd10 ;
7'd65: cu_chroma_mode_raddr_o = 4'd11 ;
7'd66: cu_chroma_mode_raddr_o = 4'd11 ;
7'd67: cu_chroma_mode_raddr_o = 4'd11 ;
7'd68: cu_chroma_mode_raddr_o = 4'd11 ;
7'd69: cu_chroma_mode_raddr_o = 4'd12 ;
7'd70: cu_chroma_mode_raddr_o = 4'd12 ;
7'd71: cu_chroma_mode_raddr_o = 4'd12 ;
7'd72: cu_chroma_mode_raddr_o = 4'd12 ;
7'd73: cu_chroma_mode_raddr_o = 4'd13 ;
7'd74: cu_chroma_mode_raddr_o = 4'd13 ;
7'd75: cu_chroma_mode_raddr_o = 4'd13 ;
7'd76: cu_chroma_mode_raddr_o = 4'd13 ;
7'd77: cu_chroma_mode_raddr_o = 4'd14 ;
7'd78: cu_chroma_mode_raddr_o = 4'd14 ;
7'd79: cu_chroma_mode_raddr_o = 4'd14 ;
7'd80: cu_chroma_mode_raddr_o = 4'd14 ;
7'd81: cu_chroma_mode_raddr_o = 4'd15 ;
7'd82: cu_chroma_mode_raddr_o = 4'd15 ;
7'd83: cu_chroma_mode_raddr_o = 4'd15 ;
7'd84: cu_chroma_mode_raddr_o = 4'd15 ;
default: cu_chroma_mode_raddr_o = 4'd0 ;
endcase
end
//cu_luma_pred_mode_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_pred_mode_r <= 6'd0 ;
else if(cu_start_d2_r)
cu_luma_pred_mode_r <= luma_mode_i ;
end
//cu_luma_pred_top_mode_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_pred_top_mode_r <= 6'd1 ;
else if(cu_start_d3_r)begin
case(cu_idx_r)
7'd0 , 7'd1 , 7'd2 , 7'd5 ,
7'd6 , 7'd9 , 7'd10, 7'd21,
7'd22, 7'd25, 7'd26, 7'd37,
7'd38, 7'd41, 7'd42 :
cu_luma_pred_top_mode_r <= 24'h041041 ;
default : cu_luma_pred_top_mode_r <= luma_mode_i ;
endcase
end
end
// cu_luma_pred_left_mode_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_luma_pred_left_mode_r <= 6'd0 ;
else if(cu_start_d1_r) begin
case(cu_idx_r)
7'd0 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_0_r ,6'd1,cu_luma_mode_left_8_r };
7'd1 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_0_r ,6'd1,cu_luma_mode_left_4_r };
7'd3 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_8_r ,6'd1,cu_luma_mode_left_12_r};
7'd5 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_0_r ,6'd1,cu_luma_mode_left_2_r };
7'd7 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_4_r ,6'd1,cu_luma_mode_left_6_r };
7'd13 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_8_r ,6'd1,cu_luma_mode_left_10_r};
7'd15 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_12_r,6'd1,cu_luma_mode_left_14_r};
7'd21 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_0_r ,6'd1,cu_luma_mode_left_1_r };
7'd23 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_2_r ,6'd1,cu_luma_mode_left_3_r };
7'd29 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_4_r ,6'd1,cu_luma_mode_left_5_r };
7'd31 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_6_r ,6'd1,cu_luma_mode_left_7_r };
7'd53 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_8_r ,6'd1,cu_luma_mode_left_9_r };
7'd55 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_10_r,6'd1,cu_luma_mode_left_11_r};
7'd61 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_12_r,6'd1,cu_luma_mode_left_13_r};
7'd63 : cu_luma_pred_left_mode_r <= { 6'd1,cu_luma_mode_left_14_r,6'd1,cu_luma_mode_left_15_r};
default: cu_luma_pred_left_mode_r <= luma_mode_i ;
endcase
end
end
// cu_chroma_pred_mode_r
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cu_chroma_pred_mode_r <= 6'd0 ;
else if(cu_start_d1_r) begin
if(cu_idx_r<7'd21)
cu_chroma_pred_mode_r <= chroma_mode_i[23:18] ;
else begin
case(cu_idx_minus21_w[1:0])
2'd0:cu_chroma_pred_mode_r <= chroma_mode_i[23:18] ;
2'd1:cu_chroma_pred_mode_r <= chroma_mode_i[17:12] ;
2'd2:cu_chroma_pred_mode_r <= chroma_mode_i[11:6 ] ;
2'd3:cu_chroma_pred_mode_r <= chroma_mode_i[ 5:0 ] ;
endcase
end
end
end
// -----------------------------------------------------------------------------------------------------------------------------
//
// binarization an cu
//
// -----------------------------------------------------------------------------------------------------------------------------
assign cu_start_w = cu_start_d3_r ;
assign cu_idx_w = cu_idx_r ;
assign cu_depth_w = cu_depth_r ;
assign cu_sub_div_w = cu_sub_div_r ;
assign cu_slice_type_w = slice_type_i ;
assign cu_inter_part_mode_w = cu_inter_part_size_r ;
assign cu_merge_flag_w = cu_merge_flag_r ;
assign cu_merge_idx_w = cu_merge_idx_r ;
assign cu_luma_pred_mode_w = cu_luma_pred_mode_r ;
assign cu_chroma_pred_mode_w = cu_chroma_pred_mode_r ;
assign cu_cbf_y_w = cu_cbf_y_r ;
assign cu_cbf_u_w = cu_cbf_u_r ;
assign cu_cbf_v_w = cu_cbf_v_r ;
assign cu_qp_curr_w = lcu_qp_i ;
assign last_cu_flag_w = last_cu_flag_r ;
assign cu_depth_left_w = cu_depth_left_r ;
assign cu_depth_top_w = cu_depth_top_r ;
assign cu_skip_top_flag_w = cu_skip_top_flag_r ;
assign cu_skip_left_flag_w = cu_skip_left_flag_r ;
assign cu_luma_pred_top_mode_w = cu_luma_pred_top_mode_r ;
assign cu_luma_pred_left_mode_w = cu_luma_pred_left_mode_r ;
assign cu_qp_last_w = cu_qp_last_r ;
assign cu_qp_nocoded_w = cu_qp_nocoded_r ;
assign tq_rdata_w = coeff_data_i ;
/*
always @* begin
case(cu_inter_part_size_r)
`PART_2NX2N : mb_mvd_rdata_r = {cu_mvd_data_r,cu_mvd_idx_r[8:6],cu_mvd_idx_r[8:6]};
`PART_2NXN : mb_mvd_rdata_r = {cu_mvd_data_r,cu_mvd_idx_r[8:6],cu_mvd_idx_r[5:3]};
`PART_NX2N : mb_mvd_rdata_r = {cu_mvd_data_r,cu_mvd_idx_r[8:6],cu_mvd_idx_r[2:0]};
`PART_SPLIT : mb_mvd_rdata_r = 50'd0 ;
endcase
end
*/
always @* begin
case(cu_inter_part_size_r)
`PART_2NX2N : mb_mvd_rdata_r = {cu_mvd_data_r[44:23],cu_mvd_data_r[21:0],2'b0,cu_mvd_data_r[45],2'b0,cu_mvd_data_r[22]};
`PART_2NXN : mb_mvd_rdata_r = {cu_mvd_data_r[44:23],cu_mvd_data_r[21:0],2'b0,cu_mvd_data_r[45],2'b0,cu_mvd_data_r[22]};
`PART_NX2N : mb_mvd_rdata_r = {cu_mvd_data_r[44:23],cu_mvd_data_r[21:0],2'b0,cu_mvd_data_r[45],2'b0,cu_mvd_data_r[22]};
`PART_SPLIT : mb_mvd_rdata_r = 50'd0;
endcase
end
cabac_binari_cu cabac_binari_cu_u0(
// input
.clk ( clk ),
.rst_n ( rst_n ),
.cu_start_i ( cu_start_w ),
.cu_idx_i ( cu_idx_w ),
.cu_depth_i ( cu_depth_w ),
.cu_split_transform_i ( cu_sub_div_w ),
.cu_slice_type_i ( cu_slice_type_w ),
.cu_skip_flag_i ( 1'b0 ),//cu_skip_flag_w
.cu_part_size_i ( cu_inter_part_mode_w ),
.cu_merge_flag_i ( cu_merge_flag_w ),
.cu_merge_idx_i ( cu_merge_idx_w ),
.cu_luma_pred_mode_i ( cu_luma_pred_mode_w ),
.cu_chroma_pred_mode_i ( cu_chroma_pred_mode_w ),
.cu_cbf_y_i ( cu_cbf_y_w ),
.cu_cbf_u_i ( cu_cbf_u_w ),
.cu_cbf_v_i ( cu_cbf_v_w ),
.cu_qp_i ( cu_qp_curr_w ),
.last_cu_flag_i ( last_cu_flag_w ),
.cu_skip_top_flag_i ( cu_skip_top_flag_w ),
.cu_skip_left_flag_i ( cu_skip_left_flag_w ),
.cu_luma_pred_top_mode_i ( cu_luma_pred_top_mode_w ),
.cu_luma_pred_left_mode_i ( cu_luma_pred_left_mode_w ),
.cu_qp_last_i ( cu_qp_last_w ),
.tq_rdata_i ( tq_rdata_w ),
.cu_mv_data_i ( mb_mvd_rdata_r ),
.cu_qp_nocoded_i ( cu_qp_nocoded_w ),
// output
.cu_done_o ( cu_done_w ),
.coeff_type_o ( coeff_type_w ),
.tq_ren_o ( tq_ren_w ),
.tq_raddr_o ( tq_raddr_w ),
.cu_qp_coded_flag_o ( cu_qp_coded_flag_w ),
.cu_binary_pair_0_o ( cu_binary_pair_0_w ),
.cu_binary_pair_1_o ( cu_binary_pair_1_w ),
.cu_binary_pair_2_o ( cu_binary_pair_2_w ),
.cu_binary_pair_3_o ( cu_binary_pair_3_w ),
.cu_binary_pair_valid_num_o(cu_binary_pair_valid_num_w )
);
// -----------------------------------------------------------------------------------------------------------------------------
//
// binarization split_flag
//
// -----------------------------------------------------------------------------------------------------------------------------
reg no_left_flag_r ;
reg no_top_flag_r ;
reg [1:0] ctx_idx_split_flag_r ;
reg [7:0] ctx_addr_split_flag_r ;
wire [10:0] ctx_pair_split_flag_w ;
//no_left_flag_r
always @* begin
if(mb_x_i=='d0) begin
case(cu_idx_r)
7'd0, 7'd1 , 7'd3 , 7'd5 ,
7'd7, 7'd13, 7'd15, 7'd21 ,
7'd23, 7'd29, 7'd31, 7'd53,
7'd55, 7'd61, 7'd63 : no_left_flag_r = 1'b1;
default: no_left_flag_r = 1'b0;
endcase
end
else
no_left_flag_r = 1'b0 ;
end
//no_top_flag_r
always @* begin
if(mb_y_i=='d0) begin
case(cu_idx_r)
7'd0 , 7'd1 , 7'd2 , 7'd5 ,
7'd6 , 7'd9 , 7'd10, 7'd21,
7'd22, 7'd25, 7'd26, 7'd37,
7'd38, 7'd41, 7'd42: no_top_flag_r = 1'b1;
default: no_top_flag_r = 1'b0;
endcase
end
else
no_top_flag_r = 1'b0 ;
end
// ctx_idx_split_flag_r
always @* begin
if(no_left_flag_r && no_top_flag_r)
ctx_idx_split_flag_r = 1'd0;
else if(!no_left_flag_r && no_top_flag_r)
ctx_idx_split_flag_r = cu_depth_left_r > cu_depth_r;
else if(no_left_flag_r && ~no_top_flag_r)
ctx_idx_split_flag_r = cu_depth_top_r > cu_depth_r;
else
ctx_idx_split_flag_r = (cu_depth_left_r > cu_depth_r) + (cu_depth_top_r > cu_depth_r);
end
always @* begin
if(ctx_idx_split_flag_r=='d2)
ctx_addr_split_flag_r = {3'd2, 5'd28}; //2
else if(ctx_idx_split_flag_r=='d1)
ctx_addr_split_flag_r = {3'd3, 5'd28}; //1
else
ctx_addr_split_flag_r = {3'd3, 5'd25}; //0
end
assign ctx_pair_split_flag_w = {2'b00, cu_split_flag_r, ctx_addr_split_flag_r};
// -----------------------------------------------------------------------------------------------------------------------------
//
// binarization terminal after a lcu was done
//
// -----------------------------------------------------------------------------------------------------------------------------
reg [ 10:0 ] ctx_pair_termianl_r ;
always @* begin
if( (mb_x_i==mb_x_total_i) && (mb_y_i==mb_y_total_i) )
ctx_pair_termianl_r = {2'b11,1'b0,1'b1,2'd0,5'd0} ;
else
ctx_pair_termianl_r = {2'b11,1'b0,1'b0,2'd0,5'd0} ;
end
// -----------------------------------------------------------------------------------------------------------------------------
//
// binarization sao
//
// -----------------------------------------------------------------------------------------------------------------------------
reg [10:0] cu_binary_sao_mergeleft_r ;
reg [10:0] cu_binary_sao_mergetop_r ;
wire [10:0] cu_binary_sao_0_w ;
wire [10:0] cu_binary_sao_1_w ;
wire [10:0] cu_binary_sao_2_w ;
wire [10:0] cu_binary_sao_3_w ;
wire [10:0] cu_binary_sao_4_w ;
wire [10:0] cu_binary_sao_5_w ;
wire [10:0] cu_binary_sao_6_w ;
wire [10:0] cu_binary_sao_7_w ;
wire allow_merge_left_w ;
wire allow_merge_top_w ;
wire [19:0] sao_luma_w ;
wire [19:0] sao_chromau_w ;
wire [19:0] sao_chromav_w ;
reg merge_left_r ;
reg merge_top_r ;
wire sao_merge_w ;
reg [19:0] sao_data_r ;
reg [ 1:0] sao_compidx_r ;
assign allow_merge_left_w = !(!mb_x_i) ;
assign allow_merge_top_w = !(!mb_y_i) ;
always @* begin
if(allow_merge_left_w) begin
cu_binary_sao_mergeleft_r = {2'b00,sao_i[60],3'd4,5'd19};
merge_left_r = sao_i[60] ;
end
else begin
cu_binary_sao_mergeleft_r = {2'b01,1'b0,8'hff };
merge_left_r = 1'b0 ;
end
end
always @*begin
if(merge_left_r==1'b0&&allow_merge_top_w) begin
cu_binary_sao_mergetop_r = {2'b00,sao_i[61],3'd4,5'd19};
merge_top_r = sao_i[61] ;
end
else begin
cu_binary_sao_mergetop_r = {2'b01,1'b0,8'hff };
merge_top_r = 1'b0 ;
end
end
assign sao_luma_w = sao_i[19:0 ] ;
assign sao_chromau_w = sao_i[39:20] ;
assign sao_chromav_w = sao_i[59:40] ;
assign sao_merge_w = merge_left_r||merge_top_r ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
sao_data_r <= 20'd0 ;
sao_compidx_r <= 2'd0 ;
end
else begin
case(lcu_cyc_cnt_r)
3'd0,3'd1:begin sao_data_r <= sao_luma_w ;sao_compidx_r <= 2'd0; end
3'd2,3'd3:begin sao_data_r <= sao_chromau_w ;sao_compidx_r <= 2'd1; end
3'd4,3'd5:begin sao_data_r <= sao_chromav_w ;sao_compidx_r <= 2'd2; end
default :begin sao_data_r <= 20'd0 ;sao_compidx_r <= 2'd0; end
endcase
end
end
cabac_binari_sao_offset cabac_binari_sao_offset_u0(
.sao_data_i (sao_data_r ),
.sao_compidx_i (sao_compidx_r ),
.sao_merge_i (sao_merge_w ),
.cu_binary_sao_0_o (cu_binary_sao_0_w ),
.cu_binary_sao_1_o (cu_binary_sao_1_w ),
.cu_binary_sao_2_o (cu_binary_sao_2_w ),
.cu_binary_sao_3_o (cu_binary_sao_3_w ),
.cu_binary_sao_4_o (cu_binary_sao_4_w ),
.cu_binary_sao_5_o (cu_binary_sao_5_w ),
.cu_binary_sao_6_o (cu_binary_sao_6_w ),
.cu_binary_sao_7_o (cu_binary_sao_7_w )
);
// -----------------------------------------------------------------------------------------------------------------------------
//
// output signals
//
// -----------------------------------------------------------------------------------------------------------------------------
assign cu_mvd_ren_o = cu_mvd_ren_r ;
assign cu_mvd_raddr_o = cu_mvd_raddr_r ;
assign cu_coeff_ren_o = tq_ren_w ;
assign cu_coeff_raddr_o = tq_raddr_w ;
assign cabac_mb_done_o = lcu_done_r ;
assign cabac_slice_done_o = cabac_slice_done_r ;
assign cabac_curr_state_o = lcu_curr_state_r ;
assign coeff_type_o = coeff_type_w ;
// slice_init_flag_o
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
slice_init_flag_o <= 0;
else if(table_build_end_i)
slice_init_flag_o <= 0;
else if(lcu_curr_state_r==LCU_INIT)
slice_init_flag_o <= 1;
else
slice_init_flag_o <= 0;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
binary_pair_0_o <= {2'b01,1'b0,8'hff} ;
binary_pair_1_o <= {2'b01,1'b0,8'hff} ;
binary_pair_2_o <= {2'b01,1'b0,8'hff} ;
binary_pair_3_o <= {2'b01,1'b0,8'hff} ;
binary_pair_valid_num_o<= 3'd0 ;
end
else begin
case(lcu_curr_state_r)
LCU_IDLE :begin
binary_pair_0_o <= {2'b01,1'b0,8'hff} ;
binary_pair_1_o <= {2'b01,1'b0,8'hff} ;
binary_pair_2_o <= {2'b01,1'b0,8'hff} ;
binary_pair_3_o <= {2'b01,1'b0,8'hff} ;
binary_pair_valid_num_o<= 3'd0 ;
end
LCU_SAO :begin
if(!lcu_cyc_cnt_r) begin
binary_pair_0_o <= cu_binary_sao_mergeleft_r ;
binary_pair_1_o <= cu_binary_sao_mergetop_r ;
binary_pair_2_o <= {2'b01,1'b0,8'hff} ;
binary_pair_3_o <= {2'b01,1'b0,8'hff} ;
binary_pair_valid_num_o<= 3'd2 ;
end
else if(lcu_cyc_cnt_r[0]) begin
binary_pair_0_o <= cu_binary_sao_0_w ;
binary_pair_1_o <= cu_binary_sao_1_w ;
binary_pair_2_o <= cu_binary_sao_2_w ;
binary_pair_3_o <= cu_binary_sao_3_w ;
binary_pair_valid_num_o<= 3'd4 ;
end
else begin
binary_pair_0_o <= cu_binary_sao_4_w ;
binary_pair_1_o <= cu_binary_sao_5_w ;
binary_pair_2_o <= cu_binary_sao_6_w ;
binary_pair_3_o <= cu_binary_sao_7_w ;
binary_pair_valid_num_o<= 3'd4 ;
end
end
CU_SPLIT : begin
binary_pair_0_o <= ctx_pair_split_flag_w ;
binary_pair_1_o <= {2'b01,1'b0,8'hff} ;
binary_pair_2_o <= {2'b01,1'b0,8'hff} ;
binary_pair_3_o <= {2'b01,1'b0,8'hff} ;
binary_pair_valid_num_o<= 3'd1 ;
end
LCU_END : begin
binary_pair_0_o <= ctx_pair_termianl_r ;
binary_pair_1_o <= {2'b01,1'b0,8'hff} ;
binary_pair_2_o <= {2'b01,1'b0,8'hff} ;
binary_pair_3_o <= {2'b01,1'b0,8'hff} ;
binary_pair_valid_num_o<= lcu_cyc_cnt_r ? 3'd0 :3'd1 ;
end
default : begin
binary_pair_0_o <= cu_binary_pair_0_w ;
binary_pair_1_o <= cu_binary_pair_1_w ;
binary_pair_2_o <= cu_binary_pair_2_w ;
binary_pair_3_o <= cu_binary_pair_3_w ;
binary_pair_valid_num_o<= cu_binary_pair_valid_num_w ;
end
endcase
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
// Device : Spartan-6
// Design Name : DDR/DDR2/DDR3/LPDDR
// Purpose : This is the simulation testbench which is used to verify the
// design. The basic clocks and resets to the interface are
// generated here. This also connects the memory interface to the
// memory model.
//*****************************************************************************
`timescale 1ps/1ps
module sim_tb_top;
// ========================================================================== //
// Parameters //
// ========================================================================== //
parameter DEBUG_EN = 0;
localparam DBG_WR_STS_WIDTH = 32;
localparam DBG_RD_STS_WIDTH = 32;
parameter C1_MEMCLK_PERIOD = 3000;
parameter C1_RST_ACT_LOW = 0;
parameter C1_INPUT_CLK_TYPE = "SINGLE_ENDED";
parameter C1_NUM_DQ_PINS = 16;
parameter C1_MEM_ADDR_WIDTH = 13;
parameter C1_MEM_BANKADDR_WIDTH = 3;
parameter C1_MEM_ADDR_ORDER = "ROW_BANK_COLUMN";
parameter C1_P0_MASK_SIZE = 4;
parameter C1_P0_DATA_PORT_SIZE = 32;
parameter C1_P1_MASK_SIZE = 4;
parameter C1_P1_DATA_PORT_SIZE = 32;
parameter C1_CALIB_SOFT_IP = "TRUE";
parameter C1_SIMULATION = "TRUE";
parameter C1_HW_TESTING = "FALSE";
parameter C3_MEMCLK_PERIOD = 3000;
parameter C3_RST_ACT_LOW = 0;
parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED";
parameter C3_NUM_DQ_PINS = 16;
parameter C3_MEM_ADDR_WIDTH = 13;
parameter C3_MEM_BANKADDR_WIDTH = 3;
parameter C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN";
parameter C3_P0_MASK_SIZE = 4;
parameter C3_P0_DATA_PORT_SIZE = 32;
parameter C3_P1_MASK_SIZE = 4;
parameter C3_P1_DATA_PORT_SIZE = 32;
parameter C3_CALIB_SOFT_IP = "TRUE";
parameter C3_SIMULATION = "TRUE";
parameter C3_HW_TESTING = "FALSE";
// ========================================================================== //
// Signal Declarations //
// ========================================================================== //
// Clocks
reg c1_sys_clk;
wire c1_sys_clk_p;
wire c1_sys_clk_n;
// System Reset
reg c1_sys_rst;
wire c1_sys_rst_i;
// Design-Top Port Map
wire [C1_MEM_ADDR_WIDTH-1:0] mcb1_dram_a;
wire [C1_MEM_BANKADDR_WIDTH-1:0] mcb1_dram_ba;
wire mcb1_dram_ck;
wire mcb1_dram_ck_n;
wire [C1_NUM_DQ_PINS-1:0] mcb1_dram_dq;
wire mcb1_dram_dqs;
wire mcb1_dram_dqs_n;
wire mcb1_dram_dm;
wire mcb1_dram_ras_n;
wire mcb1_dram_cas_n;
wire mcb1_dram_we_n;
wire mcb1_dram_cke;
wire mcb1_dram_odt;
wire mcb1_dram_reset_n;
wire mcb1_dram_udqs; // for X16 parts
wire mcb1_dram_udqs_n; // for X16 parts
wire mcb1_dram_udm; // for X16 parts
// Clocks
reg c3_sys_clk;
wire c3_sys_clk_p;
wire c3_sys_clk_n;
// System Reset
reg c3_sys_rst;
wire c3_sys_rst_i;
// Design-Top Port Map
wire [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a;
wire [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba;
wire mcb3_dram_ck;
wire mcb3_dram_ck_n;
wire [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq;
wire mcb3_dram_dqs;
wire mcb3_dram_dqs_n;
wire mcb3_dram_dm;
wire mcb3_dram_ras_n;
wire mcb3_dram_cas_n;
wire mcb3_dram_we_n;
wire mcb3_dram_cke;
wire mcb3_dram_odt;
wire mcb3_dram_reset_n;
wire mcb3_dram_udqs; // for X16 parts
wire mcb3_dram_udqs_n; // for X16 parts
wire mcb3_dram_udm; // for X16 parts
// Error & Calib Signals
wire error;
wire calib_done;
wire rzq1;
wire rzq3; wire zio1;
wire zio3;
// ========================================================================== //
// Clocks Generation //
// ========================================================================== //
initial
c1_sys_clk = 1'b0;
always
#(C1_MEMCLK_PERIOD/2) c1_sys_clk = ~c1_sys_clk;
assign c1_sys_clk_p = c1_sys_clk;
assign c1_sys_clk_n = ~c1_sys_clk;
initial
c3_sys_clk = 1'b0;
always
#(C3_MEMCLK_PERIOD/2) c3_sys_clk = ~c3_sys_clk;
assign c3_sys_clk_p = c3_sys_clk;
assign c3_sys_clk_n = ~c3_sys_clk;
// ========================================================================== //
// Reset Generation //
// ========================================================================== //
initial begin
c1_sys_rst = 1'b0;
#20000;
c1_sys_rst = 1'b1;
end
assign c1_sys_rst_i = C1_RST_ACT_LOW ? c1_sys_rst : ~c1_sys_rst;
initial begin
c3_sys_rst = 1'b0;
#20000;
c3_sys_rst = 1'b1;
end
assign c3_sys_rst_i = C3_RST_ACT_LOW ? c3_sys_rst : ~c3_sys_rst;
// ========================================================================== //
// Error Grouping //
// ========================================================================== //
// The PULLDOWN component is connected to the ZIO signal primarily to avoid the
// unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
PULLDOWN zio_pulldown1 (.O(zio1));
PULLDOWN zio_pulldown3 (.O(zio3)); PULLDOWN rzq_pulldown1 (.O(rzq1));
PULLDOWN rzq_pulldown3 (.O(rzq3));
// ========================================================================== //
// DESIGN TOP INSTANTIATION //
// ========================================================================== //
example_top #(
.C1_P0_MASK_SIZE (C1_P0_MASK_SIZE ),
.C1_P0_DATA_PORT_SIZE (C1_P0_DATA_PORT_SIZE ),
.C1_P1_MASK_SIZE (C1_P1_MASK_SIZE ),
.C1_P1_DATA_PORT_SIZE (C1_P1_DATA_PORT_SIZE ),
.C1_MEMCLK_PERIOD (C1_MEMCLK_PERIOD),
.C1_RST_ACT_LOW (C1_RST_ACT_LOW),
.C1_INPUT_CLK_TYPE (C1_INPUT_CLK_TYPE),
.DEBUG_EN (DEBUG_EN),
.C1_MEM_ADDR_ORDER (C1_MEM_ADDR_ORDER ),
.C1_NUM_DQ_PINS (C1_NUM_DQ_PINS ),
.C1_MEM_ADDR_WIDTH (C1_MEM_ADDR_WIDTH ),
.C1_MEM_BANKADDR_WIDTH (C1_MEM_BANKADDR_WIDTH),
.C1_HW_TESTING (C1_HW_TESTING),
.C1_SIMULATION (C1_SIMULATION),
.C1_CALIB_SOFT_IP (C1_CALIB_SOFT_IP ),
.C3_P0_MASK_SIZE (C3_P0_MASK_SIZE ),
.C3_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE ),
.C3_P1_MASK_SIZE (C3_P1_MASK_SIZE ),
.C3_P1_DATA_PORT_SIZE (C3_P1_DATA_PORT_SIZE ),
.C3_MEMCLK_PERIOD (C3_MEMCLK_PERIOD),
.C3_RST_ACT_LOW (C3_RST_ACT_LOW),
.C3_INPUT_CLK_TYPE (C3_INPUT_CLK_TYPE),
.C3_MEM_ADDR_ORDER (C3_MEM_ADDR_ORDER ),
.C3_NUM_DQ_PINS (C3_NUM_DQ_PINS ),
.C3_MEM_ADDR_WIDTH (C3_MEM_ADDR_WIDTH ),
.C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH),
.C3_HW_TESTING (C3_HW_TESTING),
.C3_SIMULATION (C3_SIMULATION),
.C3_CALIB_SOFT_IP (C3_CALIB_SOFT_IP )
)
design_top (
.c1_sys_clk (c1_sys_clk),
.c1_sys_rst_i (c1_sys_rst_i),
.mcb1_dram_dq (mcb1_dram_dq),
.mcb1_dram_a (mcb1_dram_a),
.mcb1_dram_ba (mcb1_dram_ba),
.mcb1_dram_ras_n (mcb1_dram_ras_n),
.mcb1_dram_cas_n (mcb1_dram_cas_n),
.mcb1_dram_we_n (mcb1_dram_we_n),
.mcb1_dram_odt (mcb1_dram_odt),
.mcb1_dram_cke (mcb1_dram_cke),
.mcb1_dram_ck (mcb1_dram_ck),
.mcb1_dram_ck_n (mcb1_dram_ck_n),
.mcb1_dram_dqs (mcb1_dram_dqs),
.mcb1_dram_dqs_n (mcb1_dram_dqs_n),
.calib_done (calib_done),
.error (error),
.mcb1_dram_udqs (mcb1_dram_udqs), // for X16 parts
.mcb1_dram_udqs_n (mcb1_dram_udqs_n), // for X16 parts
.mcb1_dram_udm (mcb1_dram_udm), // for X16 parts
.mcb1_dram_dm (mcb1_dram_dm),
.mcb1_rzq (rzq1),
.mcb1_zio (zio1),
.mcb1_dram_reset_n (mcb1_dram_reset_n),
.c3_sys_clk (c3_sys_clk),
.c3_sys_rst_i (c3_sys_rst_i),
.mcb3_dram_dq (mcb3_dram_dq),
.mcb3_dram_a (mcb3_dram_a),
.mcb3_dram_ba (mcb3_dram_ba),
.mcb3_dram_ras_n (mcb3_dram_ras_n),
.mcb3_dram_cas_n (mcb3_dram_cas_n),
.mcb3_dram_we_n (mcb3_dram_we_n),
.mcb3_dram_odt (mcb3_dram_odt),
.mcb3_dram_cke (mcb3_dram_cke),
.mcb3_dram_ck (mcb3_dram_ck),
.mcb3_dram_ck_n (mcb3_dram_ck_n),
.mcb3_dram_dqs (mcb3_dram_dqs),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n),
.mcb3_dram_udqs (mcb3_dram_udqs), // for X16 parts
.mcb3_dram_udqs_n (mcb3_dram_udqs_n), // for X16 parts
.mcb3_dram_udm (mcb3_dram_udm), // for X16 parts
.mcb3_dram_dm (mcb3_dram_dm),
.mcb3_rzq (rzq3),
.mcb3_zio (zio3),
.mcb3_dram_reset_n (mcb3_dram_reset_n)
);
// ========================================================================== //
// Memory model instances //
// ========================================================================== //
generate
if(C1_NUM_DQ_PINS == 16) begin : MEM_INST1
ddr3_model_c1 u_mem_c1(
.ck (mcb1_dram_ck),
.ck_n (mcb1_dram_ck_n),
.cke (mcb1_dram_cke),
.cs_n (1'b0),
.ras_n (mcb1_dram_ras_n),
.cas_n (mcb1_dram_cas_n),
.we_n (mcb1_dram_we_n),
.dm_tdqs ({mcb1_dram_udm,mcb1_dram_dm}),
.ba (mcb1_dram_ba),
.addr (mcb1_dram_a),
.dq (mcb1_dram_dq),
.dqs ({mcb1_dram_udqs,mcb1_dram_dqs}),
.dqs_n ({mcb1_dram_udqs_n,mcb1_dram_dqs_n}),
.tdqs_n (),
.odt (mcb1_dram_odt),
.rst_n (mcb1_dram_reset_n)
);
end else begin
ddr3_model_c1 u_mem_c1(
.ck (mcb1_dram_ck),
.ck_n (mcb1_dram_ck_n),
.cke (mcb1_dram_cke),
.cs_n (1'b0),
.ras_n (mcb1_dram_ras_n),
.cas_n (mcb1_dram_cas_n),
.we_n (mcb1_dram_we_n),
.dm_tdqs (mcb1_dram_dm),
.ba (mcb1_dram_ba),
.addr (mcb1_dram_a),
.dq (mcb1_dram_dq),
.dqs (mcb1_dram_dqs),
.dqs_n (mcb1_dram_dqs_n),
.tdqs_n (),
.odt (mcb1_dram_odt),
.rst_n (mcb1_dram_reset_n)
);
end
endgenerate
generate
if(C3_NUM_DQ_PINS == 16) begin : MEM_INST3
ddr3_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_tdqs ({mcb3_dram_udm,mcb3_dram_dm}),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs ({mcb3_dram_udqs,mcb3_dram_dqs}),
.dqs_n ({mcb3_dram_udqs_n,mcb3_dram_dqs_n}),
.tdqs_n (),
.odt (mcb3_dram_odt),
.rst_n (mcb3_dram_reset_n)
);
end else begin
ddr3_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_tdqs (mcb3_dram_dm),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs (mcb3_dram_dqs),
.dqs_n (mcb3_dram_dqs_n),
.tdqs_n (),
.odt (mcb3_dram_odt),
.rst_n (mcb3_dram_reset_n)
);
end
endgenerate
// ========================================================================== //
// Reporting the test case status
// ========================================================================== //
initial
begin : Logging
fork
begin : calibration_done
wait (calib_done);
$display("Calibration Done");
#50000000;
if (!error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
#200000000;
if (!calib_done) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:54:16 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_jtag_axi_0_0 -prefix
// DemoInterconnect_jtag_axi_0_0_ DemoInterconnect_jtag_axi_0_0_stub.v
// Design : DemoInterconnect_jtag_axi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "jtag_axi_v1_2_4_jtag_axi,Vivado 2017.3" *)
module DemoInterconnect_jtag_axi_0_0(aclk, aresetn, m_axi_awid, m_axi_awaddr,
m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot,
m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid,
m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp,
m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,m_axi_awid[0:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock,m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[0:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock,m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[0:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
module BPM_lut(lookup, scaler);
input [7:0] lookup;
output [19:0] scaler;
assign scaler =(lookup == 8'd1) ? 1000000 :
(lookup == 8'd2) ? 500000 :
(lookup == 8'd3) ? 333333 :
(lookup == 8'd4) ? 250000 :
(lookup == 8'd5) ? 200000 :
(lookup == 8'd6) ? 166667 :
(lookup == 8'd7) ? 142857 :
(lookup == 8'd8) ? 125000 :
(lookup == 8'd9) ? 111111 :
(lookup == 8'd10) ? 100000 :
(lookup == 8'd11) ? 90909 :
(lookup == 8'd12) ? 83333 :
(lookup == 8'd13) ? 76923 :
(lookup == 8'd14) ? 71429 :
(lookup == 8'd15) ? 66667 :
(lookup == 8'd16) ? 62500 :
(lookup == 8'd17) ? 58824 :
(lookup == 8'd18) ? 55556 :
(lookup == 8'd19) ? 52632 :
(lookup == 8'd20) ? 50000 :
(lookup == 8'd21) ? 47619 :
(lookup == 8'd22) ? 45455 :
(lookup == 8'd23) ? 43478 :
(lookup == 8'd24) ? 41667 :
(lookup == 8'd25) ? 40000 :
(lookup == 8'd26) ? 38462 :
(lookup == 8'd27) ? 37037 :
(lookup == 8'd28) ? 35714 :
(lookup == 8'd29) ? 34483 :
(lookup == 8'd30) ? 33333 :
(lookup == 8'd31) ? 32258 :
(lookup == 8'd32) ? 31250 :
(lookup == 8'd33) ? 30303 :
(lookup == 8'd34) ? 29412 :
(lookup == 8'd35) ? 28571 :
(lookup == 8'd36) ? 27778 :
(lookup == 8'd37) ? 27027 :
(lookup == 8'd38) ? 26316 :
(lookup == 8'd39) ? 25641 :
(lookup == 8'd40) ? 25000 :
(lookup == 8'd41) ? 24390 :
(lookup == 8'd42) ? 23810 :
(lookup == 8'd43) ? 23256 :
(lookup == 8'd44) ? 22727 :
(lookup == 8'd45) ? 22222 :
(lookup == 8'd46) ? 21739 :
(lookup == 8'd47) ? 21277 :
(lookup == 8'd48) ? 20833 :
(lookup == 8'd49) ? 20408 :
(lookup == 8'd50) ? 20000 :
(lookup == 8'd51) ? 19608 :
(lookup == 8'd52) ? 19231 :
(lookup == 8'd53) ? 18868 :
(lookup == 8'd54) ? 18519 :
(lookup == 8'd55) ? 18182 :
(lookup == 8'd56) ? 17857 :
(lookup == 8'd57) ? 17544 :
(lookup == 8'd58) ? 17241 :
(lookup == 8'd59) ? 16949 :
(lookup == 8'd60) ? 16667 :
(lookup == 8'd61) ? 16393 :
(lookup == 8'd62) ? 16129 :
(lookup == 8'd63) ? 15873 :
(lookup == 8'd64) ? 15625 :
(lookup == 8'd65) ? 15385 :
(lookup == 8'd66) ? 15152 :
(lookup == 8'd67) ? 14925 :
(lookup == 8'd68) ? 14706 :
(lookup == 8'd69) ? 14493 :
(lookup == 8'd70) ? 14286 :
(lookup == 8'd71) ? 14085 :
(lookup == 8'd72) ? 13889 :
(lookup == 8'd73) ? 13699 :
(lookup == 8'd74) ? 13514 :
(lookup == 8'd75) ? 13333 :
(lookup == 8'd76) ? 13158 :
(lookup == 8'd77) ? 12987 :
(lookup == 8'd78) ? 12821 :
(lookup == 8'd79) ? 12658 :
(lookup == 8'd80) ? 12500 :
(lookup == 8'd81) ? 12346 :
(lookup == 8'd82) ? 12195 :
(lookup == 8'd83) ? 12048 :
(lookup == 8'd84) ? 11905 :
(lookup == 8'd85) ? 11765 :
(lookup == 8'd86) ? 11628 :
(lookup == 8'd87) ? 11494 :
(lookup == 8'd88) ? 11364 :
(lookup == 8'd89) ? 11236 :
(lookup == 8'd90) ? 11111 :
(lookup == 8'd91) ? 10989 :
(lookup == 8'd92) ? 10870 :
(lookup == 8'd93) ? 10753 :
(lookup == 8'd94) ? 10638 :
(lookup == 8'd95) ? 10526 :
(lookup == 8'd96) ? 10417 :
(lookup == 8'd97) ? 10309 :
(lookup == 8'd98) ? 10204 :
(lookup == 8'd99) ? 10101 :
(lookup == 8'd100) ? 10000 :
(lookup == 8'd101) ? 9901 :
(lookup == 8'd102) ? 9804 :
(lookup == 8'd103) ? 9709 :
(lookup == 8'd104) ? 9615 :
(lookup == 8'd105) ? 9524 :
(lookup == 8'd106) ? 9434 :
(lookup == 8'd107) ? 9346 :
(lookup == 8'd108) ? 9259 :
(lookup == 8'd109) ? 9174 :
(lookup == 8'd110) ? 9091 :
(lookup == 8'd111) ? 9009 :
(lookup == 8'd112) ? 8929 :
(lookup == 8'd113) ? 8850 :
(lookup == 8'd114) ? 8772 :
(lookup == 8'd115) ? 8696 :
(lookup == 8'd116) ? 8621 :
(lookup == 8'd117) ? 8547 :
(lookup == 8'd118) ? 8475 :
(lookup == 8'd119) ? 8403 :
(lookup == 8'd120) ? 8333 :
(lookup == 8'd121) ? 8264 :
(lookup == 8'd122) ? 8197 :
(lookup == 8'd123) ? 8130 :
(lookup == 8'd124) ? 8065 :
(lookup == 8'd125) ? 8000 :
(lookup == 8'd126) ? 7937 :
(lookup == 8'd127) ? 7874 :
(lookup == 8'd128) ? 7813 :
(lookup == 8'd129) ? 7752 :
(lookup == 8'd130) ? 7692 :
(lookup == 8'd131) ? 7634 :
(lookup == 8'd132) ? 7576 :
(lookup == 8'd133) ? 7519 :
(lookup == 8'd134) ? 7463 :
(lookup == 8'd135) ? 7407 :
(lookup == 8'd136) ? 7353 :
(lookup == 8'd137) ? 7299 :
(lookup == 8'd138) ? 7246 :
(lookup == 8'd139) ? 7194 :
(lookup == 8'd140) ? 7143 :
(lookup == 8'd141) ? 7092 :
(lookup == 8'd142) ? 7042 :
(lookup == 8'd143) ? 6993 :
(lookup == 8'd144) ? 6944 :
(lookup == 8'd145) ? 6897 :
(lookup == 8'd146) ? 6849 :
(lookup == 8'd147) ? 6803 :
(lookup == 8'd148) ? 6757 :
(lookup == 8'd149) ? 6711 :
(lookup == 8'd150) ? 6667 :
(lookup == 8'd151) ? 6623 :
(lookup == 8'd152) ? 6579 :
(lookup == 8'd153) ? 6536 :
(lookup == 8'd154) ? 6494 :
(lookup == 8'd155) ? 6452 :
(lookup == 8'd156) ? 6410 :
(lookup == 8'd157) ? 6369 :
(lookup == 8'd158) ? 6329 :
(lookup == 8'd159) ? 6289 :
(lookup == 8'd160) ? 6250 :
(lookup == 8'd161) ? 6211 :
(lookup == 8'd162) ? 6173 :
(lookup == 8'd163) ? 6135 :
(lookup == 8'd164) ? 6098 :
(lookup == 8'd165) ? 6061 :
(lookup == 8'd166) ? 6024 :
(lookup == 8'd167) ? 5988 :
(lookup == 8'd168) ? 5952 :
(lookup == 8'd169) ? 5917 :
(lookup == 8'd170) ? 5882 :
(lookup == 8'd171) ? 5848 :
(lookup == 8'd172) ? 5814 :
(lookup == 8'd173) ? 5780 :
(lookup == 8'd174) ? 5747 :
(lookup == 8'd175) ? 5714 :
(lookup == 8'd176) ? 5682 :
(lookup == 8'd177) ? 5650 :
(lookup == 8'd178) ? 5618 :
(lookup == 8'd179) ? 5587 :
(lookup == 8'd180) ? 5556 :
(lookup == 8'd181) ? 5525 :
(lookup == 8'd182) ? 5495 :
(lookup == 8'd183) ? 5464 :
(lookup == 8'd184) ? 5435 :
(lookup == 8'd185) ? 5405 :
(lookup == 8'd186) ? 5376 :
(lookup == 8'd187) ? 5348 :
(lookup == 8'd188) ? 5319 :
(lookup == 8'd189) ? 5291 :
(lookup == 8'd190) ? 5263 :
(lookup == 8'd191) ? 5236 :
(lookup == 8'd192) ? 5208 :
(lookup == 8'd193) ? 5181 :
(lookup == 8'd194) ? 5155 :
(lookup == 8'd195) ? 5128 :
(lookup == 8'd196) ? 5102 :
(lookup == 8'd197) ? 5076 :
(lookup == 8'd198) ? 5051 :
(lookup == 8'd199) ? 5025 :
(lookup == 8'd200) ? 5000 :
(lookup == 8'd201) ? 4975 :
(lookup == 8'd202) ? 4950 :
(lookup == 8'd203) ? 4926 :
(lookup == 8'd204) ? 4902 :
(lookup == 8'd205) ? 4878 :
(lookup == 8'd206) ? 4854 :
(lookup == 8'd207) ? 4831 :
(lookup == 8'd208) ? 4808 :
(lookup == 8'd209) ? 4785 :
(lookup == 8'd210) ? 4762 :
(lookup == 8'd211) ? 4739 :
(lookup == 8'd212) ? 4717 :
(lookup == 8'd213) ? 4695 :
(lookup == 8'd214) ? 4673 :
(lookup == 8'd215) ? 4651 :
(lookup == 8'd216) ? 4630 :
(lookup == 8'd217) ? 4608 :
(lookup == 8'd218) ? 4587 :
(lookup == 8'd219) ? 4566 :
(lookup == 8'd220) ? 4545 :
(lookup == 8'd221) ? 4525 :
(lookup == 8'd222) ? 4505 :
(lookup == 8'd223) ? 4484 :
(lookup == 8'd224) ? 4464 :
(lookup == 8'd225) ? 4444 :
(lookup == 8'd226) ? 4425 :
(lookup == 8'd227) ? 4405 :
(lookup == 8'd228) ? 4386 :
(lookup == 8'd229) ? 4367 :
(lookup == 8'd230) ? 4348 :
(lookup == 8'd231) ? 4329 :
(lookup == 8'd232) ? 4310 :
(lookup == 8'd233) ? 4292 :
(lookup == 8'd234) ? 4274 :
(lookup == 8'd235) ? 4255 :
(lookup == 8'd236) ? 4237 :
(lookup == 8'd237) ? 4219 :
(lookup == 8'd238) ? 4202 :
(lookup == 8'd239) ? 4184 :
(lookup == 8'd240) ? 4167 :
(lookup == 8'd241) ? 4149 :
(lookup == 8'd242) ? 4132 :
(lookup == 8'd243) ? 4115 :
(lookup == 8'd244) ? 4098 :
(lookup == 8'd245) ? 4082 :
(lookup == 8'd246) ? 4065 :
(lookup == 8'd247) ? 4049 :
(lookup == 8'd248) ? 4032 :
(lookup == 8'd249) ? 4016 :
(lookup == 8'd250) ? 4000 :
(lookup == 8'd251) ? 3984 :
(lookup == 8'd252) ? 3968 :
(lookup == 8'd253) ? 3953 :
(lookup == 8'd254) ? 3937 :
(lookup == 8'd255) ? 3922 :
/*lookup undef*/ 20'hFFFFF;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVER2_BLACKBOX_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_rdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 2,
CFG_DATA_ID_WIDTH = 3, // number of buckets
CFG_LOCAL_ID_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_BUFFER_ADDR_WIDTH = 5,
CFG_MEM_IF_CS_WIDTH = 2,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_MAX_READ_CMD_NUM_WIDTH = 4, // expected in-flight read commands at a time
CFG_RDATA_RETURN_MODE = "PASSTHROUGH", // INORDER, PASSTHROUGH
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ERRCMD_FIFO_ADDR_WIDTH = 3,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 9,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 12,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_ERRCMD_FIFO_REG = 1 // set 1 to improve timing for errcmd_fifo
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration
cfg_type,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_burst_length,
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// command generator & TBP command load interface / cmd update interface
rdatap_free_id_valid,
rdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_read,
proc_size,
proc_localid,
// input interface data channel / buffer read interface
read_data_valid, // data sent to either dataid_manager, or input interface
read_data,
read_data_error,
read_data_localid,
// Arbiter issued reads interface
bg_do_read,
bg_to_chipsel,
bg_to_bank,
bg_to_row,
bg_to_column,
bg_dataid,
bg_localid,
bg_size,
bg_do_rmw_correct,
bg_do_rmw_partial,
// read data from memory interface
ecc_rdata,
ecc_rdatav,
ecc_sbe,
ecc_dbe,
ecc_code,
// ECC Error commands interface, to command generator
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
// ECC Error address interface, to ECC block
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// RMW fifo interface, to wdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_ECC_RDATA_COUNTER_REG = 0; // set to 1 to improve timing
localparam CFG_RMW_BIT_WIDTH = 1;
localparam CFG_RMW_PARTIAL_BIT_WIDTH = 1;
localparam CFG_PENDING_RD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_DATA_ID_WIDTH + CFG_RMW_BIT_WIDTH + CFG_RMW_PARTIAL_BIT_WIDTH;
localparam CFG_ERRCMD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_INT_SIZE_WIDTH + CFG_LOCAL_ID_WIDTH;
localparam CFG_INORDER_INFO_FIFO_WIDTH = CFG_INT_SIZE_WIDTH+CFG_LOCAL_ID_WIDTH;
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam CFG_RDATA_ERROR_WIDTH = 1;
localparam CFG_IN_ORDER_BUFFER_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RDATA_ERROR_WIDTH;
localparam CFG_MAX_READ_CMD_NUM = 2**CFG_MAX_READ_CMD_NUM_WIDTH;
localparam MIN_COL = 8;
localparam MIN_ROW = 12;
localparam MIN_BANK = 2;
localparam MIN_CS = 1;
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam CFG_IGNORE_NUM_BITS_COL = log2 (CFG_DWIDTH_RATIO);
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2 (CFG_LOCAL_ADDR_WIDTH);
integer j,k,m,n;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// configuration
input [CFG_PORT_WIDTH_TYPE- 1:0] cfg_type;
input [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM-1:0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length;
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// command generator & TBP command load interface / cmd update interface
output rdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_read;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
input [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
// input interface data channel
output read_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
output read_data_error;
output [CFG_LOCAL_ID_WIDTH-1:0] read_data_localid;
// Arbiter issued reads interface
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH ) -1:0] bg_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH ) -1:0] bg_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0] bg_to_row;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0] bg_to_column;
input [( CFG_DATA_ID_WIDTH ) -1:0] bg_dataid;
input [( CFG_LOCAL_ID_WIDTH ) -1:0] bg_localid;
input [( CFG_INT_SIZE_WIDTH ) -1:0] bg_size;
// read data from memory interface
input [CFG_LOCAL_DATA_WIDTH-1:0] ecc_rdata;
input ecc_rdatav;
input [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
input [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
// ECC Error commands interface, to command generator
input errcmd_ready;
output errcmd_valid;
output [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
output [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
output [CFG_LOCAL_ID_WIDTH-1:0] errcmd_localid;
// ECC Error address interface, to ECC block
output [CFG_LOCAL_ADDR_WIDTH-1:0] rdatap_rcvd_addr;
output rdatap_rcvd_cmd;
output rdatap_rcvd_corr_dropped;
// RMW fifo interface, to wdatap
output rmwfifo_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
output [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// configuration
wire [CFG_PORT_WIDTH_TYPE- 1:0] cfg_type;
wire [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// command generator & TBP command load interface / cmd update interface
reg rdatap_free_id_valid;
reg [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
// input interface data channel
reg read_data_valid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
reg read_data_error;
reg [CFG_LOCAL_ID_WIDTH-1:0] read_data_localid;
// Arbiter issued reads interface
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH ) -1:0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH ) -1:0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0] bg_to_column;
wire [( CFG_DATA_ID_WIDTH ) -1:0] bg_dataid;
wire [( CFG_LOCAL_ID_WIDTH ) -1:0] bg_localid;
wire [( CFG_INT_SIZE_WIDTH ) -1:0] bg_size;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_rmw_partial;
reg [CFG_MEM_IF_CS_WIDTH -1:0] int_bg_to_chipsel[CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_column [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_DATA_ID_WIDTH -1:0] int_bg_dataid;
reg [CFG_LOCAL_ID_WIDTH -1:0] int_bg_localid;
reg [CFG_INT_SIZE_WIDTH -1:0] int_bg_size;
// read data from memory interface
wire [CFG_LOCAL_DATA_WIDTH-1:0] ecc_rdata;
wire ecc_rdatav;
wire [CFG_ECC_MULTIPLES- 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES- 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
// ECC Error commands interface, to command generator
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] errcmd_localid;
// RMW fifo interface, to wdatap
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
reg rdatap_rcvd_cmd;
reg rdatap_rcvd_corr_dropped;
// -----------------------------
// signal declaration
// -----------------------------
wire[CFG_INT_SIZE_WIDTH-1:0] cfg_max_cmd_burstcount;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_row;
wire cmdload_valid;
reg [CFG_MAX_READ_CMD_NUM_WIDTH-1:0] cmd_counter;
reg cmd_counter_full;
wire cmd_counter_load;
wire free_id_get_ready;
wire free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0]free_id_dataid_vector;
wire allocated_put_ready;
wire allocated_put_valid;
wire int_free_id_valid;
wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_input;
wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_output;
wire pfifo_output_valid;
wire pfifo_input_ready;
wire rdata_burst_complete;
reg rdata_burst_complete_r;
reg rout_data_valid; // rout_data sent to dataid_manager
reg rout_cmd_valid; // rout_cmd sent to dataid_manager
reg rout_data_rmwfifo_valid; // rout_data sent to rmwfifo
reg rout_cmd_rmwfifo_valid; // rout_cmd sent to rmwfifo
wire rout_rmw_rmwpartial;
reg rout_data_error;
reg rout_sbecmd_valid;
reg rout_errnotify_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rout_data;
wire [CFG_DATA_ID_WIDTH-1:0] rout_data_dataid;
wire [CFG_LOCAL_ID_WIDTH-1:0] rout_data_localid;
wire [CFG_INT_SIZE_WIDTH-1:0] rout_data_burstcount;
wire [CFG_ECC_MULTIPLES- 1 : 0] rout_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rout_ecc_code;
reg pfifo_input_do_read;
reg pfifo_input_rmw;
reg pfifo_input_rmw_partial;
reg [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_input_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_input_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_input_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_input_column;
reg [CFG_DATA_ID_WIDTH-1:0] pfifo_input_dataid;
reg [CFG_LOCAL_ID_WIDTH-1:0] pfifo_input_localid;
reg [CFG_INT_SIZE_WIDTH-1:0] pfifo_input_size;
reg mux_pfifo_input_rmw [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg mux_pfifo_input_rmw_partial [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] mux_pfifo_input_chipsel [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] mux_pfifo_input_bank [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] mux_pfifo_input_row [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] mux_pfifo_input_column [CFG_AFI_INTF_PHASE_NUM -1 : 0];
wire pfifo_rmw;
wire pfifo_rmw_partial;
wire [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column;
wire [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_burst_aligned;
reg [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_chipsel_r;
reg [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_bank_r;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_row_r;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_r;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_burst_aligned_r;
wire [CFG_DATA_ID_WIDTH-1:0] pfifo_dataid;
wire [CFG_LOCAL_ID_WIDTH-1:0] pfifo_localid;
wire [CFG_INT_SIZE_WIDTH-1:0] pfifo_size;
reg [CFG_LOCAL_ADDR_WIDTH-1:0] pfifo_addr;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_current_count;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_counter;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdatavalid_count;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_burst_complete_count;
reg ecc_sbe_cmd_detected;
reg ecc_dbe_cmd_detected;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_LOCAL_ID_WIDTH-1:0] dataid_array_localid [CFG_DATAID_ARRAY_DEPTH-1:0];
wire inordr_id_data_complete;
reg inordr_id_data_complete_r;
wire inordr_id_valid;
wire inordr_id_list_valid;
wire inordr_read_data_valid;
reg inordr_read_data_valid_r;
wire [CFG_LOCAL_DATA_WIDTH-1:0] inordr_read_data;
wire inordr_read_data_error;
wire [CFG_DATA_ID_WIDTH-1:0] inordr_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] inordr_id_dataid_vector;
wire [CFG_LOCAL_ID_WIDTH-1:0] inordr_id_localid;
reg [CFG_LOCAL_ID_WIDTH-1:0] inordr_id_localid_r;
reg [CFG_INT_SIZE_WIDTH-1:0] inordr_data_counter;
reg [CFG_INT_SIZE_WIDTH-1:0] inordr_data_counter_plus_1;
wire [CFG_INT_SIZE_WIDTH-1:0] inordr_next_data_counter;
wire [CFG_INT_SIZE_WIDTH-1:0] inordr_id_expected_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_inordr_data_ready;
wire inordr_info_input_ready;
wire inordr_info_output_valid;
wire [CFG_INORDER_INFO_FIFO_WIDTH-1:0] inordr_info_input;
wire [CFG_INORDER_INFO_FIFO_WIDTH-1:0] inordr_info_output;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
wire [CFG_INT_SIZE_WIDTH-1:0] buffwrite_offset;
wire [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0] buffwrite_data;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
wire [CFG_INT_SIZE_WIDTH-1:0] buffread_offset;
wire [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0] buffread_data;
wire int_ecc_sbe;
wire int_ecc_dbe;
wire errcmd_fifo_in_cmddropped;
reg errcmd_fifo_in_cmddropped_r;
wire errcmd_fifo_in_ready;
wire errcmd_fifo_in_valid_wire;
wire [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_in_wire;
wire [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_out;
reg errcmd_fifo_in_valid;
reg [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_in;
// -----------------------------
// module definition
// -----------------------------
//
// READ DATA MAIN OUTPUT MUX
//
generate
begin : gen_rdata_output_mux
if (CFG_RDATA_RETURN_MODE == "PASSTHROUGH")
begin
always @ (*)
begin
read_data_valid = rout_data_valid;
read_data = rout_data;
read_data_error = rout_data_error;
read_data_localid = rout_data_localid;
rdatap_free_id_valid = ~cmd_counter_full;
rdatap_free_id_dataid = 0;
end
end
else
begin
always @ (*)
begin
read_data_valid = inordr_read_data_valid_r;
read_data = inordr_read_data;
read_data_error = inordr_read_data_error;
read_data_localid = inordr_id_localid_r;
rdatap_free_id_valid = ~cmd_counter_full & free_id_valid;
rdatap_free_id_dataid = free_id_dataid;
end
end
end
endgenerate
//
// RDATA_ROUTER
//
// mux to select correct burst gen output phase for read command
// assumes bg_do_read only asserted for 1 of the CFG_AFI_INTF_PHASE_NUM
genvar rdp_k;
generate
for (rdp_k = 0; rdp_k < CFG_AFI_INTF_PHASE_NUM; rdp_k = rdp_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_read [rdp_k] = bg_do_read [rdp_k];
int_bg_do_rmw_correct [rdp_k] = bg_do_rmw_correct [rdp_k];
int_bg_do_rmw_partial [rdp_k] = bg_do_rmw_partial [rdp_k];
int_bg_to_chipsel [rdp_k] = bg_to_chipsel [(((rdp_k+1)*CFG_MEM_IF_CS_WIDTH )-1):(rdp_k*CFG_MEM_IF_CS_WIDTH )];
int_bg_to_bank [rdp_k] = bg_to_bank [(((rdp_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(rdp_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [rdp_k] = bg_to_row [(((rdp_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(rdp_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_column [rdp_k] = bg_to_column [(((rdp_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(rdp_k*CFG_MEM_IF_COL_WIDTH)];
end
end
endgenerate
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
end
always @ (*)
begin
mux_pfifo_input_rmw [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_correct [0] : 0;
mux_pfifo_input_rmw_partial [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_partial [0] : 0;
mux_pfifo_input_chipsel [0] = (int_bg_do_read [0]) ? int_bg_to_chipsel [0] : 0;
mux_pfifo_input_bank [0] = (int_bg_do_read [0]) ? int_bg_to_bank [0] : 0;
mux_pfifo_input_row [0] = (int_bg_do_read [0]) ? int_bg_to_row [0] : 0;
mux_pfifo_input_column [0] = (int_bg_do_read [0]) ? int_bg_to_column [0] : 0;
end
genvar rdp_j;
generate
for (rdp_j = 1; rdp_j < CFG_AFI_INTF_PHASE_NUM; rdp_j = rdp_j + 1)
begin : gen_bg_afi_phase_mux
always @ (*)
begin
mux_pfifo_input_rmw [rdp_j] = mux_pfifo_input_rmw [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_correct [rdp_j] : 0);
mux_pfifo_input_rmw_partial [rdp_j] = mux_pfifo_input_rmw_partial [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_partial [rdp_j] : 0);
mux_pfifo_input_chipsel [rdp_j] = mux_pfifo_input_chipsel [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_chipsel [rdp_j] : 0);
mux_pfifo_input_bank [rdp_j] = mux_pfifo_input_bank [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_bank [rdp_j] : 0);
mux_pfifo_input_row [rdp_j] = mux_pfifo_input_row [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_row [rdp_j] : 0);
mux_pfifo_input_column [rdp_j] = mux_pfifo_input_column [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_column [rdp_j] : 0);
end
end
endgenerate
always @ (*)
begin
pfifo_input_do_read = |int_bg_do_read;
pfifo_input_rmw = mux_pfifo_input_rmw [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_rmw_partial = mux_pfifo_input_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_chipsel = mux_pfifo_input_chipsel [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_bank = mux_pfifo_input_bank [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_row = mux_pfifo_input_row [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_column = mux_pfifo_input_column [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_dataid = int_bg_dataid ;
pfifo_input_localid = int_bg_localid ;
pfifo_input_size = int_bg_size ;
end
// format for pfifo_input & pfifo_output must be same
assign pfifo_input = {pfifo_input_chipsel, pfifo_input_bank, pfifo_input_row, pfifo_input_column, pfifo_input_localid, pfifo_input_size, pfifo_input_rmw, pfifo_input_rmw_partial, pfifo_input_dataid};
assign {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column, pfifo_localid, pfifo_size, pfifo_rmw, pfifo_rmw_partial, pfifo_dataid} = pfifo_output;
// read data for this command has been fully received from memory
assign rdata_burst_complete = (pfifo_output_valid & (pfifo_size == ecc_rdata_current_count)) ? 1 : 0;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_PENDING_RD_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_MAX_READ_CMD_NUM_WIDTH)
)
pending_rd_fifo
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rdata_burst_complete),
.get_valid (pfifo_output_valid),
.get_data (pfifo_output),
.put_ready (pfifo_input_ready), // no back-pressure allowed
.put_valid (pfifo_input_do_read),
.put_data (pfifo_input)
);
assign cmd_counter_load = ~proc_busy & proc_load & proc_read;
assign cmdload_valid = cmd_counter_load & proc_load_dataid;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cmd_counter <= 0;
cmd_counter_full <= 1'b0;
end
else
begin
if (cmd_counter_load & rdata_burst_complete)
begin
cmd_counter <= cmd_counter;
cmd_counter_full <= cmd_counter_full;
end
else if (cmd_counter_load)
begin
cmd_counter <= cmd_counter + 1;
if (cmd_counter == {{(CFG_MAX_READ_CMD_NUM_WIDTH - 1){1'b1}}, 1'b0}) // when cmd counter is counting up to all_ones
begin
cmd_counter_full <= 1'b1;
end
else
begin
cmd_counter_full <= 1'b0;
end
end
else if (rdata_burst_complete)
begin
cmd_counter <= cmd_counter - 1;
cmd_counter_full <= 1'b0;
end
end
end
assign rout_data = ecc_rdata;
assign rout_data_dataid = pfifo_dataid;
assign rout_data_localid = pfifo_localid;
assign rout_data_burstcount = ecc_rdata_current_count;
assign rout_rmw_rmwpartial = (pfifo_rmw | pfifo_rmw_partial);
assign rout_ecc_dbe = ecc_dbe;
assign rout_ecc_code = ecc_code;
always @ (*)
begin
//rout_data_valid = 0;
//rout_cmd_valid = 0;
rout_data_rmwfifo_valid = 0;
rout_cmd_rmwfifo_valid = 0;
rout_sbecmd_valid = 0;
rout_data_error = 0;
rout_errnotify_valid = 0;
if (~cfg_enable_ecc & ~cfg_enable_no_dm)
begin
rout_data_valid = ecc_rdatav;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
end
else
begin
rout_data_rmwfifo_valid = ecc_rdatav & rout_rmw_rmwpartial;
rout_data_valid = ecc_rdatav & ~rout_rmw_rmwpartial;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
rout_cmd_rmwfifo_valid = rout_data_rmwfifo_valid & rdata_burst_complete;
rout_data_error = int_ecc_dbe;
rout_errnotify_valid = ecc_rdatav & ( int_ecc_sbe | int_ecc_dbe );
if (cfg_enable_auto_corr)
begin
rout_sbecmd_valid = rout_cmd_valid & (ecc_sbe_cmd_detected | int_ecc_sbe);
end
end
end
// rmwfifo interface
assign rmwfifo_data_valid = rout_data_rmwfifo_valid;
assign rmwfifo_data = rout_data;
assign rmwfifo_ecc_dbe = rout_ecc_dbe;
assign rmwfifo_ecc_code = rout_ecc_code;
// ecc_sbe_cmd_detected
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else if (int_ecc_sbe)
begin
ecc_sbe_cmd_detected <= 1;
end
else if (int_ecc_dbe)
begin
ecc_dbe_cmd_detected <= 1;
end
end
end
assign int_ecc_sbe = ecc_rdatav & (|ecc_sbe);
assign int_ecc_dbe = ecc_rdatav & (|ecc_dbe);
//
// ECC_RDATA counter
//
assign ecc_rdata_current_count = (CFG_ECC_RDATA_COUNTER_REG) ? ecc_rdata_counter : ecc_rdatavalid_count;
assign ecc_rdatavalid_count = (ecc_rdatav) ? ecc_rdata_counter + 1 : ecc_rdata_counter;
assign ecc_rdata_burst_complete_count = pfifo_size;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_rdata_counter <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_rdata_counter <= ecc_rdatavalid_count - ecc_rdata_burst_complete_count;
end
else
begin
ecc_rdata_counter <= ecc_rdatavalid_count;
end
end
end
assign errcmd_fifo_in_valid_wire = rout_sbecmd_valid;
assign errcmd_fifo_in_wire = {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column_burst_aligned, cfg_max_cmd_burstcount, pfifo_localid};
assign {errcmd_chipsel, errcmd_bank, errcmd_row, errcmd_column, errcmd_size, errcmd_localid} = errcmd_fifo_out;
assign errcmd_fifo_in_cmddropped = ~errcmd_fifo_in_ready & errcmd_fifo_in_valid_wire;
assign cfg_max_cmd_burstcount = (cfg_burst_length / CFG_DWIDTH_RATIO);
// DDR3, pfifo_column_burst_aligned is burst length 8 aligned
// DDR2, pfifo_column is already burst aligned
assign pfifo_column_burst_aligned = (cfg_type == `MMR_TYPE_DDR3) ? {pfifo_column[(CFG_MEM_IF_COL_WIDTH-1):3],{3{1'b0}} } : pfifo_column;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pfifo_chipsel_r <= 0;
pfifo_bank_r <= 0;
pfifo_row_r <= 0;
pfifo_column_r <= 0;
pfifo_column_burst_aligned_r <= 0;
end
else
begin
pfifo_chipsel_r <= pfifo_chipsel ;
pfifo_bank_r <= pfifo_bank ;
pfifo_row_r <= pfifo_row ;
pfifo_column_r <= pfifo_column ;
pfifo_column_burst_aligned_r <= pfifo_column_burst_aligned;
end
end
generate
if (CFG_ERRCMD_FIFO_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
errcmd_fifo_in_valid <= 1'b0;
errcmd_fifo_in <= {CFG_ERRCMD_FIFO_WIDTH{1'b0}};
end else
begin
errcmd_fifo_in_valid <= errcmd_fifo_in_valid_wire;
errcmd_fifo_in <= errcmd_fifo_in_wire;
end
end
end else // (CFG_ERRCMD_FIFO_REG == 0)
begin
always @ (*)
begin
errcmd_fifo_in_valid = errcmd_fifo_in_valid_wire;
errcmd_fifo_in = errcmd_fifo_in_wire;
end
end
endgenerate
alt_mem_ddrx_fifo
# (
.CTL_FIFO_DATA_WIDTH (CFG_ERRCMD_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH)
)
errcmd_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (errcmd_ready),
.get_valid (errcmd_valid),
.get_data (errcmd_fifo_out),
.put_ready (errcmd_fifo_in_ready),
.put_valid (errcmd_fifo_in_valid),
.put_data (errcmd_fifo_in)
);
//
// error address information for MMR's
//
// - rdatap_rcvd_addr, rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped
// - rdatap_rcvd_addr generation takes 1 cycle after an error, so need to register
// rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped to keep in sync, see SPR:362993
//
assign rdatap_rcvd_addr = pfifo_addr;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rdata_burst_complete_r <= 0;
errcmd_fifo_in_cmddropped_r <= 0;
rdatap_rcvd_cmd <= 0;
rdatap_rcvd_corr_dropped <= 0;
end
else
begin
rdata_burst_complete_r <= rdata_burst_complete;
errcmd_fifo_in_cmddropped_r <= errcmd_fifo_in_cmddropped;
rdatap_rcvd_cmd <= rdata_burst_complete;
rdatap_rcvd_corr_dropped <= errcmd_fifo_in_cmddropped;
end
end
// generate local address from chip, bank, row, column addresses
always @(*)
begin : addr_loop
pfifo_addr = 0;
// column
pfifo_addr[MIN_COL - CFG_IGNORE_NUM_BITS_COL - 1 : 0] = pfifo_column_burst_aligned_r[MIN_COL - 1 : CFG_IGNORE_NUM_BITS_COL];
for (n=MIN_COL; n<MAX_COL; n=n+1'b1) begin
if(n < cfg_col_addr_width) begin // bit of col_addr can be configured in CSR using cfg_col_addr_width
pfifo_addr[n - CFG_IGNORE_NUM_BITS_COL] = pfifo_column_burst_aligned_r[n];
end
end
// row
for (j=0; j<MIN_ROW; j=j+1'b1) begin //The purpose of using this for-loop is to get rid of "if(j < cfg_row_addr_width) begin" which causes multiplexers
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
for (j=MIN_ROW; j<MAX_ROW; j=j+1'b1) begin
if(j < cfg_row_addr_width) begin // bit of row_addr can be configured in CSR using cfg_row_addr_width
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
end
// bank
for (k=0; k<MIN_BANK; k=k+1'b1) begin //The purpose of using this for-loop is to get rid of "if(k < cfg_bank_addr_width) begin" which causes multiplexers
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
for (k=MIN_BANK; k<MAX_BANK; k=k+1'b1) begin
if(k < cfg_bank_addr_width) begin // bit of bank_addr can be configured in CSR using cfg_bank_addr_width
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
end
// cs
m = 0;
if (cfg_cs_addr_width > 1'b0) begin //if cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
for (m=0; m<MIN_CS; m=m+1'b1) begin //The purpose of using this for-loop is to get rid of "if(m < cfg_cs_addr_width) begin" which causes multiplexers
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1) begin
if(m < cfg_cs_addr_width) begin // bit of cs_addr can be configured in CSR using cfg_cs_addr_width
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
end
end
end
// pre-calculate pfifo_addr chipsel, bank, row, col bit select offsets
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cfg_addr_bitsel_chipsel <= 0;
cfg_addr_bitsel_bank <= 0;
cfg_addr_bitsel_row <= 0;
end
else
begin
//row
if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
cfg_addr_bitsel_row <= cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
cfg_addr_bitsel_row <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_row <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
// bank
if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
cfg_addr_bitsel_bank <= cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_bank <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
//chipsel
if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
end
end
//
// Everything below is for
// CFG_RDATA_RETURN_MODE == INORDER support
//
generate
begin : gen_rdata_return_inorder
if (CFG_RDATA_RETURN_MODE == "INORDER")
begin
//
// DATAID MANAGEMENT
//
genvar i;
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array
assign dataid_array_valid[i] = |(dataid_array_burstcount[i]);
// dataid_array
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
dataid_array_localid [i] <= 0;
end
else
begin
// update command
if (cmdload_valid & free_id_dataid_vector[i])
begin
dataid_array_burstcount[i] <= proc_size;
end
// writing data to buffer
if (rout_data_valid & (rout_data_dataid == i))
begin
dataid_array_data_ready[i] <= 1'b1;
dataid_array_localid[i] <= rout_data_localid;
end
// completed reading data from buffer
if (inordr_id_data_complete & inordr_id_dataid_vector[i])
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
end
end
end
// dataid_array output decode mux
always @ (*)
begin
if (inordr_id_valid & inordr_id_dataid_vector[i])
begin
mux_inordr_data_ready[i] = dataid_array_data_ready[i];
end
else
begin
mux_inordr_data_ready[i] = 1'b0;
end
end
end
assign inordr_read_data_valid = |mux_inordr_data_ready;
//
// FREE & ALLOCATED DATAID LIST
//
assign free_id_get_ready = cmdload_valid;
assign allocated_put_valid = free_id_get_ready & free_id_valid;
// list & fifo ready & valid assertion/de-assertion behavior may differ based on implementation, SPR:358527
assign free_id_valid = int_free_id_valid & inordr_info_input_ready;
assign inordr_id_valid = inordr_id_list_valid & inordr_info_output_valid;
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (free_id_get_ready),
.list_get_entry_valid (int_free_id_valid),
.list_get_entry_id (free_id_dataid),
.list_get_entry_id_vector (free_id_dataid_vector),
// ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (),
.list_put_entry_valid (inordr_id_data_complete),
.list_put_entry_id (inordr_id_dataid)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (inordr_id_data_complete),
.list_get_entry_valid (inordr_id_list_valid),
.list_get_entry_id (inordr_id_dataid),
.list_get_entry_id_vector (inordr_id_dataid_vector),
// allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (allocated_put_ready),
.list_put_entry_valid (allocated_put_valid),
.list_put_entry_id (free_id_dataid)
);
// format for inordr_info_input & inordr_info_output must be same
assign inordr_info_input = {proc_localid,proc_size};
assign {inordr_id_localid,inordr_id_expected_burstcount} = inordr_info_output;
alt_mem_ddrx_fifo
# (
.CTL_FIFO_DATA_WIDTH (CFG_INORDER_INFO_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_DATA_ID_WIDTH)
)
inordr_info_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (inordr_id_data_complete),
.get_valid (inordr_info_output_valid),
.get_data (inordr_info_output),
.put_ready (inordr_info_input_ready),
.put_valid (allocated_put_valid),
.put_data (inordr_info_input)
);
//
// IN-ORDER READ MANAGER
//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 0;
inordr_read_data_valid_r <= 0;
inordr_id_data_complete_r <= 0;
inordr_id_localid_r <= 0;
end
else
begin
if (inordr_id_data_complete)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 1;
end
else
begin
inordr_data_counter <= inordr_next_data_counter;
inordr_data_counter_plus_1 <= inordr_next_data_counter + 1;
end
inordr_id_localid_r <= inordr_id_localid;
// original signal used to read from buffer
// _r version used to pop the fifos
inordr_read_data_valid_r <= inordr_read_data_valid;
inordr_id_data_complete_r <= inordr_id_data_complete;
end
end
assign inordr_next_data_counter = (inordr_read_data_valid) ? (inordr_data_counter_plus_1) : inordr_data_counter;
assign inordr_id_data_complete = inordr_read_data_valid & (inordr_data_counter_plus_1 == inordr_id_expected_burstcount);
//
// BUFFER
//
assign buffwrite_offset = ecc_rdata_counter;
assign buffwrite_address = {rout_data_dataid,buffwrite_offset};
assign buffwrite_data = {rout_data_error,rout_data};
assign buffread_offset = inordr_data_counter;
assign buffread_address = {inordr_id_dataid,buffread_offset};
assign {inordr_read_data_error,inordr_read_data} = buffread_data;
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_IN_ORDER_BUFFER_DATA_WIDTH)
)
in_order_buffer_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (rout_data_valid),
.write_address (buffwrite_address),
.write_data (buffwrite_data),
// read interface
.read_valid (inordr_read_data_valid),
.read_address (buffread_address),
.read_data (buffread_data)
);
end
end
endgenerate
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
//
// assert
//
// - rdatap_free_id_valid XOR rdatap_allocated_put_ready must always be 1
// - CFG_BUFFER_ADDR_WIDTH must be >= CFG_INT_SIZE_WIDTH. must have enough location to store 1 dram command worth of data
// - put_ready goes low
// - ecc_rdatav is high, but pfifo_output_valid is low
// - buffer size must be dataid x max size per command
// - is rdata_burst_complete allowed to be high every cycle?
// - CFG_BUFFER_ADDR_WIDTH > CFG_DATA_ID_WIDTH
// - if cfg_enable_ecc is low, sbe, dbe, rdata error must all be low
// - if cfg_enable_auto_corr is low, rmw & rmw_partial must be low, errcmd_valid must never be high
// - cmd_counter_full & cmdload_valid
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_TB_V
`define SKY130_FD_SC_LS__A311O_TB_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a311o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_TB_V
|
//--------------------------------------------------------------------------------
// receiver.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Receives commands from the serial port. The first byte is the commands
// opcode, the following (optional) four byte are the command data.
// Commands that do not have the highest bit in their opcode set are
// considered short commands without data (1 byte long). All other commands are
// long commands which are 5 bytes long.
//
// After a full command has been received it will be kept available for 10 cycles
// on the op and data outputs. A valid command can be detected by checking if the
// execute output is set. After 10 cycles the registers will be cleared
// automatically and the receiver waits for new data from the serial port.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module receiver #(
parameter [31:0] FREQ = 100000000,
parameter [31:0] RATE = 115200,
parameter BITLENGTH = FREQ / RATE // 100M / 115200 ~= 868
)(
input wire clock,
input wire trxClock,
input wire reset,
input wire rx,
output wire [7:0] op,
output wire [31:0] data,
output reg execute
);
localparam [2:0]
INIT = 3'h0,
WAITSTOP = 3'h1,
WAITSTART = 3'h2,
WAITBEGIN = 3'h3,
READBYTE = 3'h4,
ANALYZE = 3'h5,
READY = 3'h6;
reg [9:0] counter, next_counter; // clock prescaling counter
reg [3:0] bitcount, next_bitcount; // count rxed bits of current byte
reg [2:0] bytecount, next_bytecount; // count rxed bytes of current command
reg [2:0] state, next_state; // receiver state
reg [7:0] opcode, next_opcode; // opcode byte
reg [31:0] databuf, next_databuf; // data dword
reg next_execute;
assign op = opcode;
assign data = databuf;
always @(posedge clock, posedge reset)
if (reset) state <= INIT;
else state <= next_state;
always @(posedge clock)
begin
counter <= next_counter;
bitcount <= next_bitcount;
bytecount <= next_bytecount;
databuf <= next_databuf;
opcode <= next_opcode;
execute <= next_execute;
end
always
begin
next_state = state;
next_counter = counter;
next_bitcount = bitcount;
next_bytecount = bytecount;
next_opcode = opcode;
next_databuf = databuf;
next_execute = 1'b0;
case(state)
INIT :
begin
next_counter = 0;
next_bitcount = 0;
next_bytecount = 0;
next_opcode = 0;
next_databuf = 0;
next_state = WAITSTOP;
end
WAITSTOP : // reset uart
begin
if (rx) next_state = WAITSTART;
end
WAITSTART : // wait for start bit
begin
if (!rx) next_state = WAITBEGIN;
end
WAITBEGIN : // wait for first half of start bit
begin
if (counter == (BITLENGTH / 2))
begin
next_counter = 0;
next_state = READBYTE;
end
else if (trxClock)
next_counter = counter + 1;
end
READBYTE : // receive byte
begin
if (counter == BITLENGTH)
begin
next_counter = 0;
next_bitcount = bitcount + 1;
if (bitcount == 4'h8)
begin
next_bytecount = bytecount + 1;
next_state = ANALYZE;
end
else if (bytecount == 0)
begin
next_opcode = {rx,opcode[7:1]};
next_databuf = databuf;
end
else
begin
next_opcode = opcode;
next_databuf = {rx,databuf[31:1]};
end
end
else if (trxClock)
next_counter = counter + 1;
end
ANALYZE : // check if long or short command has been fully received
begin
next_counter = 0;
next_bitcount = 0;
if (bytecount == 3'h5) // long command when 5 bytes have been received
next_state = READY;
else if (!opcode[7]) // short command when set flag not set
next_state = READY;
else next_state = WAITSTOP; // otherwise continue receiving
end
READY : // done, give 10 cycles for processing
begin
next_counter = counter + 1;
if (counter == 4'd10)
next_state = INIT;
else next_state = state;
end
endcase
next_execute = (next_state == READY);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10.03.2017 09:19:09
// Design Name:
// Module Name: sine
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sinemod(
input clkdds,
input[31:0] freq,
input signed[15:0] amp,
input signed[15:0] amp_off,
output[11:0] sin
);
wire data_valid;
reg phase_valid = 1;
wire signed[16:0] data;
wire[23:0] phase = (freq*83886)/10000;
dds_compiler_0 sine_dds(clkdds, phase_valid, phase, data_valid, data);
reg signed[16:0] amped = 16'b0;
reg signed[16:0] offseted = 16'b0;
reg signed[16:0] clipped = 16'b0;
wire signed[16:0] amp_clipped = amp > 2048 ? 2048 : amp;
always @(posedge clkdds) begin
amped <= (data * amp_clipped) / 1024; // max 2048 to -2048
offseted <= amp_off + amped;
clipped <= offseted < 0 ? 0 : offseted > 4095 ? 4095 : offseted;
end
assign sin = data_valid?clipped:0;
endmodule |
`timescale 1ns / 1ps
module Arkanoid(
input iCLK_50,
input btn_W, btn_E, btn_N, btn_S,
input [3:0] iSW,
input iROT_A, iROT_B,
output oVGA_R, oVGA_G, oVGA_B, oHS, oVS,
output [7:0] oLED
);
localparam BALL_NUM = 2;
localparam SHOT_NUM = 2;
reg clk_25;
wire middle, b_dis;
wire [4:0] p_speed;
wire [9:0] p_x, p_y, g_x, g_y;
wire reset, start, btn_r, btn_l;
wire rotary_event, rotary_right;
wire [5:0] b_radius, p_radius;
wire [1:0] b_active;
wire [2:0] g_kind;
wire g_active;
wire [BALL_NUM*10-1:0] b_x, b_y;
wire [10:0] vcounter; // 0~479
wire [11:0] hcounter; // 0~639
wire [3:0] out_back, out_paddle, out_block, out_ball, out_bmem, bm_block, out_gift;
wire [4:0] out_row, out_col, bm_row, bm_col;
wire [1:0] bm_stage, bm_func;
wire bm_ready, bm_enable;
wire st_init, st_dead;
// generate a 25Mhz clock
always @(posedge iCLK_50)
clk_25 = ~clk_25;
// Buttons
syn_edge_detect sed1(iCLK_50, reset, btn_E, btn_r);
syn_edge_detect sed2(iCLK_50, reset, btn_W, btn_l);
syn_edge_detect sed3(iCLK_50, reset, btn_S, start);
// Rotation detection
Rotation_direction r_dir(.CLK(iCLK_50), .ROT_A(iROT_A), .ROT_B(iROT_B),
.rotary_event(rotary_event), .rotary_right(rotary_right));
// Game control
// Paddle control
paddle_control pd_control(.clock(iCLK_50), .reset(reset), .enable(1'b1), .rotary_event(rotary_event),
.rotary_right(rotary_right), .speed(p_speed), .radius(p_radius), .middle(middle), .paddle_x(p_x), .paddle_y(p_y));
state_control s_control(.clock(iCLK_50), .reset(reset), .start(start), .btn_l(btn_l), .btn_r(btn_r), .iSW(iSW),
.bm_ready(bm_ready), .bm_block(bm_block),
.p_x(p_x), .p_y(p_y), .p_radius(p_radius),
.b_active(b_active), .b_radius(b_radius), .o_bx(b_x), .o_by(b_y),
.bm_enable(bm_enable), .bm_row(bm_row), .bm_col(bm_col), .bm_func(bm_func), .bm_stage(bm_stage),
.g_x(g_x), .g_y(g_y), .g_kind(g_kind), .g_active(g_active),
.middle(middle), .p_speed(p_speed), .b_dis(b_dis),
.hp(oLED[7:2]), .dead(st_dead), .init(st_init), .win(st_win));
block_memory b_mem(.clock(iCLK_50), .reset(reset), .enable(bm_enable),
.row1(bm_row), .row2(out_row), .col1(bm_col), .col2(out_col),
.func(bm_func), .stage(bm_stage), .block1(bm_block), .block2(out_bmem), .ready(bm_ready));
// Game display
draw_game d_game(.clock(clk_25), .reset(reset), .visible(visible),
.dead(st_dead), .init(st_init), .win(st_win),
.in_ball(out_ball), .in_gift(out_gift), .in_block(out_block), .in_paddle(out_paddle), .in_back(out_back), .oRGB({oVGA_R, oVGA_G, oVGA_B}));
draw_back d_back(.out(out_back), .vcounter(vcounter), .hcounter(hcounter),
.dead(st_dead), .init(st_init), .win(st_win));
draw_block d_block(.clock(clk_25), .vcounter(vcounter), .hcounter(hcounter), .block(out_bmem),
.sel_row(out_row), .sel_col(out_col), .out(out_block));
draw_ball d_ball(.out(out_ball), .vcounter(vcounter), .hcounter(hcounter), .visible(b_dis),
.xs(b_x), .ys(b_y), .active(b_active), .radius(b_radius));
draw_ball d_shot(.out(out_shot), .vcounter(vcounter), .hcounter(hcounter),
.xs(s_x), .ys(s_y), .active(s_active), .radius(4));
draw_paddle d_paddle(.vcounter(vcounter), .hcounter(hcounter),
.x(p_x), .y(p_y), .radius(p_radius), .out(out_paddle));
draw_gift d_gift(.vcounter(vcounter), .hcounter(hcounter),
.x(g_x), .y(g_y), .kind(g_kind), .active(g_active), .out(out_gift));
VGA_control vga_c(.CLK(clk_25), .reset(reset), .vcounter(vcounter), .hcounter(hcounter),
.visible(visible), .oHS(oHS), .oVS(oVS));
assign reset = btn_N;
assign oLED[1:0] = st_win ? 2'b11 : (st_dead ? 2'b01 : 2'b00);
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC TAG RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of data cache tag rams. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_tag.v,v $
// Revision 1.1 2008/05/07 22:43:21 daughtry
// Initial Demo RTL check-in
//
// Revision 1.5 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dc_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_DCTAG_W;
parameter aw = `OR1200_DCTAG;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_256x21 dc_tag0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_512x20 dc_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// Author: Yu-Sheng Lin [email protected]
module t (/*AUTOARG*/
// Outputs
state,
// Inputs
clk
);
input clk;
int cyc;
reg rstn;
output [4:0] state;
parameter real fst_gparam_real = 1.23;
localparam real fst_lparam_real = 4.56;
real fst_real = 1.23;
integer fst_integer;
bit fst_bit;
logic fst_logic;
int fst_int;
shortint fst_shortint;
longint fst_longint;
byte fst_byte;
parameter fst_parameter = 123;
localparam fst_lparam = 456;
supply0 fst_supply0;
supply1 fst_supply1;
tri0 fst_tri0;
tri1 fst_tri1;
tri fst_tri;
wire fst_wire;
Test test (/*AUTOINST*/
// Outputs
.state (state[4:0]),
// Inputs
.clk (clk),
.rstn (rstn));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
rstn <= ~'1;
end
else if (cyc<10) begin
rstn <= ~'1;
end
else if (cyc<90) begin
rstn <= ~'0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input clk,
input rstn,
output logic [4:0] state
);
logic [4:0] state_w;
logic [4:0] state_array [3];
assign state = state_array[0];
always_comb begin
state_w[4] = state_array[2][0];
state_w[3] = state_array[2][4];
state_w[2] = state_array[2][3] ^ state_array[2][0];
state_w[1] = state_array[2][2];
state_w[0] = state_array[2][1];
end
always_ff @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 3; i++)
state_array[i] <= 'b1;
end
else begin
for (int i = 0; i < 2; i++)
state_array[i] <= state_array[i+1];
state_array[2] <= state_w;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A221OI_FUNCTIONAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_FUNCTIONAL_V |
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
cpu_0_jtag_debug_module_tck the_cpu_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
cpu_0_jtag_debug_module_sysclk the_cpu_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic cpu_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam cpu_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// cpu_0_jtag_debug_module_phy.sld_instance_index = 0,
// cpu_0_jtag_debug_module_phy.sld_ir_width = 2,
// cpu_0_jtag_debug_module_phy.sld_mfg_id = 70,
// cpu_0_jtag_debug_module_phy.sld_sim_action = "",
// cpu_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// cpu_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// cpu_0_jtag_debug_module_phy.sld_type_id = 34,
// cpu_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
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