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/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ns / 1ps
module mmc3_eth_core (
input wire RESET_N,
// clocks from PLL clock buffers
input wire BUS_CLK, CLK125TX, CLK125TX90, CLK125RX,
input wire PLL_LOCKED,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS,
input wire fifo_empty,
input wire fifo_full,
input wire FIFO_NEXT,
output wire FIFO_WRITE,
output wire [31:0] FIFO_DATA,
output wire [7:0] GPIO
);
/* ------- MODULE ADREESSES ------- */
localparam GPIO_BASEADDR = 32'h1000;
localparam GPIO_HIGHADDR = 32'h101f;
/* ------- USER MODULES ------- */
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(32),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio_rx (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(GPIO)
);
wire EN;
assign EN = GPIO[0];
reg [31:0] datasource;
reg fifo_write;
assign FIFO_WRITE = !fifo_full & EN;
reg [31:0] fifo_data_out;
assign FIFO_DATA = fifo_data_out;
always @(posedge BUS_CLK)
if(!EN)
fifo_data_out <= 0;
else if(FIFO_WRITE)
fifo_data_out <= fifo_data_out + 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_TB_V
`define SKY130_FD_SC_HD__CLKINVLP_TB_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkinvlp.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkinvlp dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_TB_V
|
`include "elink_regmap.v"
module esaxi (/*autoarg*/
// Outputs
txwr_access, txwr_packet, txrd_access, txrd_packet, rxrr_wait,
s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
s_axi_wready,
// Inputs
txwr_wait, txrd_wait, rxrr_access, rxrr_packet, s_axi_aclk,
s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
s_axi_wstrb, s_axi_wvalid
);
parameter [11:0] ID = 12'h810;
parameter S_IDW = 12;
parameter PW = 104;
parameter [15:0] RETURN_ADDR = {ID,`EGROUP_RR};
parameter AW = 32;
parameter DW = 32;
/*****************************/
/*Write request for TX fifo */
/*****************************/
output txwr_access;
output [PW-1:0] txwr_packet;
input txwr_wait;
/*****************************/
/*Read request for TX fifo */
/*****************************/
output txrd_access;
output [PW-1:0] txrd_packet;
input txrd_wait;
/*****************************/
/*Read response from RX fifo */
/*****************************/
input rxrr_access;
input [PW-1:0] rxrr_packet;
output rxrr_wait;
/*****************************/
/*AXI slave interface */
/*****************************/
//Clock and reset
input s_axi_aclk;
input s_axi_aresetn;
//Read address channel
input [S_IDW-1:0] s_axi_arid; //write address ID
input [31:0] s_axi_araddr;
input [1:0] s_axi_arburst;
input [3:0] s_axi_arcache;
input [1:0] s_axi_arlock;
input [7:0] s_axi_arlen;
input [2:0] s_axi_arprot;
input [3:0] s_axi_arqos;
output s_axi_arready;
input [2:0] s_axi_arsize;
input s_axi_arvalid;
//Write address channel
input [S_IDW-1:0] s_axi_awid; //write address ID
input [31:0] s_axi_awaddr;
input [1:0] s_axi_awburst;
input [3:0] s_axi_awcache;
input [1:0] s_axi_awlock;
input [7:0] s_axi_awlen;
input [2:0] s_axi_awprot;
input [3:0] s_axi_awqos;
input [2:0] s_axi_awsize;
input s_axi_awvalid;
output s_axi_awready;
//Buffered write response channel
output [S_IDW-1:0] s_axi_bid; //write address ID
output [1:0] s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
//Read channel
output [S_IDW-1:0] s_axi_rid; //write address ID
output [31:0] s_axi_rdata;
output s_axi_rlast;
output [1:0] s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
//Write channel
input [S_IDW-1:0] s_axi_wid; //write address ID
input [31:0] s_axi_wdata;
input s_axi_wlast;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
//###################################################
//#WIRE/REG DECLARATIONS
//###################################################
reg s_axi_awready;
reg s_axi_wready;
reg s_axi_bvalid;
reg [1:0] s_axi_bresp;
reg s_axi_arready;
reg [31:0] axi_awaddr; // 32b for epiphany addr
reg [1:0] axi_awburst;
reg [2:0] axi_awsize;
reg [S_IDW-1:0] axi_bid; //what to do with this?
reg [31:0] axi_araddr;
reg [7:0] axi_arlen;
reg [1:0] axi_arburst;
reg [2:0] axi_arsize;
reg [31:0] s_axi_rdata;
reg [1:0] s_axi_rresp;
reg s_axi_rlast;
reg s_axi_rvalid;
reg [S_IDW-1:0] s_axi_rid;
reg read_active;
reg [31:0] read_addr;
reg write_active;
reg b_wait; // waiting to issue write response (unlikely?)
reg txwr_access;
reg [1:0] txwr_datamode;
reg [31:0] txwr_dstaddr;
reg [31:0] txwr_data;
reg [31:0] txwr_data_reg;
reg [31:0] txwr_dstaddr_reg;
reg [1:0] txwr_datamode_reg;
reg txrd_access;
reg [1:0] txrd_datamode;
reg [31:0] txrd_dstaddr;
reg [31:0] txrd_srcaddr; //read reaspne address
reg pre_wr_en; // delay for data alignment
reg ractive_reg; // need leading edge of active for 1st req
reg rnext;
wire last_wr_beat;
wire last_rd_beat;
wire [31:0] rxrr_mux_data;
wire [DW-1:0] rxrr_data;
//###################################################
//#PACKET TO MESH
//###################################################
//TXWR
emesh2packet e2p_txwr (
// Outputs
.packet_out (txwr_packet[PW-1:0]),
// Inputs
.access_in (txwr_access),
.write_in (1'b1),
.datamode_in (txwr_datamode[1:0]),
.ctrlmode_in (4'b0),
.dstaddr_in (txwr_dstaddr[AW-1:0]),
.data_in (txwr_data[DW-1:0]),
.srcaddr_in (32'b0)//only 32b slave write supported
);
//TXRD
emesh2packet e2p_txrd (
// Outputs
.packet_out (txrd_packet[PW-1:0]),
// Inputs
.access_in (txrd_access),
.write_in (txrd_write),
.datamode_in (txrd_datamode[1:0]),
.ctrlmode_in (4'b0),
.dstaddr_in (txrd_dstaddr[AW-1:0]),
.data_in (32'b0),
.srcaddr_in (txrd_srcaddr[AW-1:0])
);
//RXRR
packet2emesh p2e_rxrr (
// Outputs
.access_out (),
.write_out (),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (),
.data_out (rxrr_data[DW-1:0]),
.srcaddr_out (),
// Inputs
.packet_in (rxrr_packet[PW-1:0])
);
//###################################################
//#WRITE ADDRESS CHANNEL
//###################################################
assign last_wr_beat = s_axi_wready & s_axi_wvalid & s_axi_wlast;
// axi_awready is asserted when there is no write transfer in progress
always @(posedge s_axi_aclk )
begin
if(~s_axi_aresetn)
begin
s_axi_awready <= 1'b1; //TODO: why not set default as 1?
write_active <= 1'b0;
end
else
begin
// we're always ready for an address cycle if we're not doing something else
// note: might make this faster by going ready on last beat instead of after,
// but if we want the very best each channel should be fifo'd.
if( ~s_axi_awready & ~write_active & ~b_wait )
s_axi_awready <= 1'b1;
else if( s_axi_awvalid )
s_axi_awready <= 1'b0;
// the write cycle is "active" as soon as we capture an address, it
// ends on the last beat.
if( s_axi_awready & s_axi_awvalid )
write_active <= 1'b1;
else if( last_wr_beat )
write_active <= 1'b0;
end // else: !if(~s_axi_aresetn)
end // always @ (posedge s_axi_aclk )
// capture address & other aw info, update address during cycle
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
axi_bid[S_IDW-1:0] <= 'd0; // capture for write response
axi_awaddr[31:0] <= 32'd0;
axi_awsize[2:0] <= 3'd0;
axi_awburst[1:0] <= 2'd0;
end
else
begin
if( s_axi_awready & s_axi_awvalid )
begin
axi_bid[S_IDW-1:0] <= s_axi_awid[S_IDW-1:0];
axi_awaddr[31:0] <= s_axi_awaddr[31:0];
axi_awsize[2:0] <= s_axi_awsize[2:0]; // 0=byte, 1=16b, 2=32b
axi_awburst[1:0] <= s_axi_awburst[1:0]; // type, 0=fixed, 1=incr, 2=wrap
end
else if( s_axi_wvalid & s_axi_wready )
if( axi_awburst == 2'b01 )
begin //incremental burst
// the write address for all the beats in the transaction are increments by the data width.
// note: this should be based on awsize instead to support narrow bursts, i think.
axi_awaddr[31:2] <= axi_awaddr[31:2] + 30'd1;
//awaddr alignedto data width
axi_awaddr[1:0] <= 2'b0;
end // both fixed & wrapping types are treated as fixed, no update.
end // else: !if(~s_axi_aresetn)
//###################################################
//#WRITE RESPONSE CHANNEL
//###################################################
assign s_axi_bid = axi_bid;
always @ (posedge s_axi_aclk)
if(~s_axi_aresetn)
s_axi_wready <= 1'b0;
else
begin
if( last_wr_beat )
s_axi_wready <= 1'b0;
else if( write_active )
s_axi_wready <= ~txwr_wait;
end
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
s_axi_bvalid <= 1'b0;
s_axi_bresp[1:0] <= 2'b0;
b_wait <= 1'b0;
end
else
begin
if( last_wr_beat )
begin
s_axi_bvalid <= 1'b1;
s_axi_bresp[1:0] <= 2'b0; // 'okay' response
b_wait <= ~s_axi_bready; // note: assumes bready will not drop without valid?
end
else if (s_axi_bready & s_axi_bvalid)
begin
s_axi_bvalid <= 1'b0;
b_wait <= 1'b0;
end
end // else: !if( s_axi_aresetn == 1'b0 )
//###################################################
//#READ REQUEST CHANNEL
//###################################################
assign last_rd_beat = s_axi_rvalid & s_axi_rlast & s_axi_rready;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
s_axi_arready <= 1'b0;
read_active <= 1'b0;
end
else
begin
//arready
if( ~s_axi_arready & ~read_active )
s_axi_arready <= 1'b1;
else if( s_axi_arvalid )
s_axi_arready <= 1'b0;
//read_active
if( s_axi_arready & s_axi_arvalid )
read_active <= 1'b1;
else if( last_rd_beat )
read_active <= 1'b0;
end // else: !if( s_axi_aresetn == 1'b0 )
//Read address channel state machine
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
axi_araddr[31:0] <= 0;
axi_arlen <= 8'd0;
axi_arburst <= 2'd0;
axi_arsize[2:0] <= 3'b0;
s_axi_rlast <= 1'b0;
s_axi_rid[S_IDW-1:0] <= 'd0;
end
else
begin
if( s_axi_arready & s_axi_arvalid )
begin
axi_araddr[31:0] <= s_axi_araddr[31:0]; //NOTE: upper 2 bits get chopped by Zynq
axi_arlen[7:0] <= s_axi_arlen[7:0];
axi_arburst <= s_axi_arburst;
axi_arsize <= s_axi_arsize;
s_axi_rlast <= ~(|s_axi_arlen[7:0]);
s_axi_rid[S_IDW-1:0] <= s_axi_arid[S_IDW-1:0];
end
else if( s_axi_rvalid & s_axi_rready)
begin
axi_arlen[7:0] <= axi_arlen[7:0] - 1;
if(axi_arlen[7:0] == 8'd1)
s_axi_rlast <= 1'b1;
if( s_axi_arburst == 2'b01)
begin //incremental burst
// the read address for all the beats in the transaction are increments by awsize
// note: this should be based on awsize instead to support narrow bursts, i think?
axi_araddr[31:2] <= axi_araddr[31:2] + 1;//TODO: doesn;t seem right...
//araddr aligned to 4 byte boundary
axi_araddr[1:0] <= 2'b0;
//for awsize = 4 bytes (010)
end
end // if ( s_axi_rvalid & s_axi_rready)
end // else: !if( s_axi_aresetn == 1'b0 )
//###################################################
//#WRITE REQUEST
//###################################################
assign txwr_write = 1'b1;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
txwr_data_reg[31:0] <= 32'd0;
txwr_dstaddr_reg[31:0] <= 32'd0;
txwr_datamode_reg[1:0] <= 2'd0;
txwr_access <= 1'b0;
pre_wr_en <= 1'b0;
end
else
begin
pre_wr_en <= s_axi_wready & s_axi_wvalid;
txwr_access <= pre_wr_en;
txwr_datamode_reg[1:0] <= axi_awsize[1:0];
txwr_dstaddr_reg[31:2] <= axi_awaddr[31:2]; //set lsbs of address based on write strobes
if(s_axi_wstrb[0] | (axi_awsize[1:0]==2'b10))
begin
txwr_data_reg[31:0] <= s_axi_wdata[31:0];
txwr_dstaddr_reg[1:0] <= 2'd0;
end
else if(s_axi_wstrb[1])
begin
txwr_data_reg[31:0] <= {8'd0, s_axi_wdata[31:8]};
txwr_dstaddr_reg[1:0] <= 2'd1;
end
else if(s_axi_wstrb[2])
begin
txwr_data_reg[31:0] <= {16'd0, s_axi_wdata[31:16]};
txwr_dstaddr_reg[1:0] <= 2'd2;
end
else
begin
txwr_data_reg[31:0] <= {24'd0, s_axi_wdata[31:24]};
txwr_dstaddr_reg[1:0] <= 2'd3;
end
end // else: !if(~s_axi_aresetn)
//Pipeline stage!
always @( posedge s_axi_aclk )
begin
txwr_data[31:0] <= txwr_data_reg[31:0];
txwr_dstaddr[31:0] <= txwr_dstaddr_reg[31:0];
txwr_datamode[1:0] <= txwr_datamode_reg[1:0];
end
//###################################################
//#READ REQUEST (DATA CHANNEL)
//###################################################
// -- reads are performed by sending a read
// -- request out the tx port and waiting for
// -- data to come back through the rx read response port.
// --
// -- because elink reads are not generally
// -- returned in order, we will only allow
// -- one at a time.
//TODO: Fix this nonsense, need to improve performance
//Allow up to N outstanding transactions, use ID to match them up
//Need to look at txrd_wait signal
assign txrd_write = 1'b0;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
txrd_access <= 1'b0;
txrd_datamode[1:0] <= 2'd0;
txrd_dstaddr[31:0] <= 32'd0;
txrd_srcaddr[31:0] <= 32'd0;
ractive_reg <= 1'b0;
rnext <= 1'b0;
end
else
begin
ractive_reg <= read_active;
rnext <= s_axi_rvalid & s_axi_rready & ~s_axi_rlast;
txrd_access <= ( ~ractive_reg & read_active ) | rnext;
txrd_datamode[1:0] <= axi_arsize[1:0];
txrd_dstaddr[31:0] <= axi_araddr[31:0];
txrd_srcaddr[31:0] <= {RETURN_ADDR, 16'd0};
//TODO: use arid+srcaddr for out of order ?
end
//###################################################
//#READ RESPONSE (DATA CHANNEL)
//###################################################
//Read response AXI state machine
//Only one outstanding read
assign rxrr_wait = 1'b0;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
s_axi_rvalid <= 1'b0;
s_axi_rdata[31:0] <= 32'd0;
s_axi_rresp <= 2'd0;
end
else
begin
if( rxrr_access )
begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= 2'd0;
case( axi_arsize[1:0] )
2'b00: s_axi_rdata[31:0] <= {4{rxrr_data[7:0]}}; //8-bit
2'b01: s_axi_rdata[31:0] <= {2{rxrr_data[15:0]}}; //16-bit
default: s_axi_rdata[31:0] <= rxrr_data[31:0]; //32-bit
endcase // case ( axi_arsize[1:0] )
end
else if( s_axi_rready )
s_axi_rvalid <= 1'b0;
end // else: !if( s_axi_aresetn == 1'b0 )
endmodule // esaxi
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
Contributed by Fred Huettig <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
delay_clk,
up_status,
dma_dbg_data,
dma_dbg_trigger,
adc_clk,
adc_dbg_data,
adc_dbg_trigger,
adc_mon_valid,
adc_mon_data,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_CF_BUFTYPE = 0;
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
input delay_clk;
output [ 7:0] up_status;
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
output adc_clk;
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
output adc_mon_valid;
output [15:0] adc_mon_data;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel;
reg up_rwn;
reg [ 4:0] up_addr;
reg [31:0] up_wdata;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg [31:0] IP2Bus_Data;
reg IP2Bus_Error;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_adc_1c #(.C_CF_BUFTYPE(C_CF_BUFTYPE)) i_adc_1c (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_or_p (adc_data_or_p),
.adc_data_or_n (adc_data_or_n),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.up_status (up_status),
.delay_clk (delay_clk),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_clk (adc_clk),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_PP_SYMBOL_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LVPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_PP_SYMBOL_V
|
module fifo(
clk,
reset,
wr_en,
rd_en,
wr_data,
rd_data,
not_full,
not_empty,
error
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 4;
localparam FIFO_SIZE = {1'b1, {(ADDR_WIDTH){1'b0}}};
input clk;
input reset;
input wr_en;
input rd_en;
input [DATA_WIDTH-1:0] wr_data;
output [DATA_WIDTH-1:0] rd_data;
output not_full;
output not_empty;
output error;
reg [DATA_WIDTH-1:0] queue[0:FIFO_SIZE-1];
reg [ADDR_WIDTH-1:0] rd_index;
reg [ADDR_WIDTH-1:0] wr_index;
reg [ADDR_WIDTH:0] count;
// Precompute several reused things
wire [ADDR_WIDTH-1:0] next_rd_index = rd_index + 1'b1;
wire [ADDR_WIDTH-1:0] next_wr_index = wr_index + 1'b1;
wire [ADDR_WIDTH:0] increase_count = count + 1'b1;
wire [ADDR_WIDTH:0] decrease_count = count - 1'b1;
`ifdef USE_SEQUENTIAL
reg rd_buffer;
reg not_empty_buffer;
reg not_full_buffer;
always @(posedge clk)
begin
rd_buffer <= queue[rd_index];
not_empty_buffer <= |count;
not_full_buffer <= ~count[ADDR_WIDTH];
end
assign not_full = not_full_buffer;
assign not_empty = not_empty_buffer;
assign rd_data = rd_buffer;
`else
assign not_full = ~count[ADDR_WIDTH];
assign not_empty = |count;
assign rd_data = queue[rd_index];
`endif
always @(posedge clk or posedge reset)
begin
if (reset)
begin
wr_index <= 1'b0;
rd_index <= 1'b0;
count <= 1'b0;
end
else if (rd_en & wr_en)
begin
// Read and write at the same time
queue[wr_index] <= wr_data;
rd_index <= next_rd_index;
wr_index <= next_wr_index;
end
else if (wr_en)
begin
// Only write
queue[wr_index] <= wr_data;
wr_index <= next_wr_index;
count <= increase_count;
end
else if (rd_en)
begin
// Only read
rd_index <= next_rd_index;
count <= decrease_count;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_P_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_P_SYMBOL_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_P_SYMBOL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet multiplexer
*/
module eth_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame inputs
*/
input wire [S_COUNT-1:0] s_eth_hdr_valid,
output wire [S_COUNT-1:0] s_eth_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_eth_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_eth_payload_axis_tready,
input wire [S_COUNT-1:0] s_eth_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_eth_hdr_ready_reg = 0, s_eth_hdr_ready_next;
reg [S_COUNT-1:0] s_eth_payload_axis_tready_reg = 0, s_eth_payload_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_eth_payload_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_eth_payload_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_eth_payload_axis_tvalid[select_reg];
wire current_s_tready = s_eth_payload_axis_tready[select_reg];
wire current_s_tlast = s_eth_payload_axis_tlast[select_reg];
wire [ID_WIDTH-1:0] current_s_tid = s_eth_payload_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_eth_payload_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_eth_payload_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
always @* begin
select_next = select_reg;
frame_next = frame_reg;
s_eth_hdr_ready_next = 0;
s_eth_payload_axis_tready_next = 0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && !m_eth_hdr_valid && (s_eth_hdr_valid & (1 << select))) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
s_eth_hdr_ready_next = (1 << select);
m_eth_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[select*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[select*48 +: 48];
m_eth_type_next = s_eth_type[select*16 +: 16];
end
// generate ready signal on selected port
s_eth_payload_axis_tready_next = (m_eth_payload_axis_tready_int_early && frame_next) << select_next;
// pass through selected packet data
m_eth_payload_axis_tdata_int = current_s_tdata;
m_eth_payload_axis_tkeep_int = current_s_tkeep;
m_eth_payload_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_eth_payload_axis_tlast_int = current_s_tlast;
m_eth_payload_axis_tid_int = current_s_tid;
m_eth_payload_axis_tdest_int = current_s_tdest;
m_eth_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= 0;
s_eth_payload_axis_tready_reg <= 0;
m_eth_hdr_valid_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tid = ID_ENABLE ? m_eth_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
|
/*
MIT License
Copyright (c) 2016 Baard Nossum
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module tst;
reg [31:0] cyclecounter,simtocy,tx_cyclecounter;
reg load,bytercvd_dly1;
wire rxpin;
reg [7:0] d;
reg seenB;
reg base_clk;
reg rx_clk;
reg tx_clk;
reg [2:0] bitxce_tx_cnt;
reg [2:0] bitxce_rx_cnt;
reg glitchline,check_rxst1;
localparam char1 = 8'hc1, char2 = 8'h4e;
localparam SIMTOCY = 100 + 2*8*8*8*10*(1+`SUBDIV16);
localparam RXCLKSTART = 100;
localparam subdiv16 = `SUBDIV16; // From makefile
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire bytercvd; // From dut_rx of uartICE40.v
wire [7:0] q; // From dut_rx of uartICE40.v
wire [1:0] rxst; // From dut_rx of uartICE40.v
wire txbusy; // From dut_tx of uartICE40.v
wire txpin; // From dut_tx of uartICE40.v
// End of automatics
always # 20 base_clk = ~base_clk;
initial begin
$dumpfile(`TSTFILE);//"obj/tst.lxt"
$dumpvars(0,tst);
d <= 0; tx_clk <= 0; simtocy = SIMTOCY; bitxce_rx_cnt <= 0;
load <= 0; rx_clk <= 0; cyclecounter <= 0; tx_cyclecounter <= 0;
seenB <= 0; base_clk <= 0; bitxce_tx_cnt <= 0;
check_rxst1 <= 0; glitchline <= 0;
end
always @(posedge base_clk ) begin
cyclecounter <= cyclecounter+1;
if ( cyclecounter > SIMTOCY ) begin
if ( simtocy == SIMTOCY )
$display( "Simulation went off the rails" );
else
$display( "Success" );
$finish;
end
tx_clk <= ~tx_clk;
if ( cyclecounter > RXCLKSTART )
rx_clk <= ~rx_clk;
end
always @(posedge tx_clk) begin
tx_cyclecounter <= tx_cyclecounter + 1;
load <= ( tx_cyclecounter == 100 ||
tx_cyclecounter == 100 + 8*8*10*(1+`SUBDIV16) ||
tx_cyclecounter == 100 + 3*8*8*10*(1+`SUBDIV16) )
? 1'b1 : 1'b0;
if ( tx_cyclecounter == 99 ) begin
d <= char1;
end else if ( tx_cyclecounter == 150 ) begin
d <= char2;
end
if ( ( tx_cyclecounter >= 100 + 2*8*8*10*(1+`SUBDIV16) &&
tx_cyclecounter <= 103 + 2*8*8*10*(1+`SUBDIV16) )
|| ( tx_cyclecounter >= 100 + 4*8*8*10*(1+`SUBDIV16)
- 64*(1+`SUBDIV16) &&
tx_cyclecounter <= 100 + 4*8*8*10*(1+`SUBDIV16)
+ 64*(1+`SUBDIV16) + 2*64 ) )
glitchline <= 1'b1;
else
glitchline <= 1'b0;
if ( tx_cyclecounter == 100 + 2*8*8*10*(1+`SUBDIV16)
+ 4*8*(1+`SUBDIV16) ||
tx_cyclecounter >= 100 + 4*8*8*10*(1+`SUBDIV16)
+ 64*(1+`SUBDIV16) + 2*64 )
begin
check_rxst1 <= 1;
if ( rxst != 2'b00 ) // Encoding of HUNT is 2'b00.
begin
if (tx_cyclecounter == 100 + 2*8*8*10*(1+`SUBDIV16)
+ 4*8*(1+`SUBDIV16))
$display( "False start bit not rejected" );
else
$display( "Something wrong at frame error" );
$finish;
end
end else begin
check_rxst1 <= 0;
end
end
always @(posedge rx_clk) begin
bytercvd_dly1 <= bytercvd;
if ( bytercvd_dly1 ) begin
if ( seenB ) begin
if ( q != char2 ) begin
$display( "Something wrong2" );
simtocy <= cyclecounter+400;
end else begin
simtocy <= simtocy-1;
end
end else begin
if ( q != char1 ) begin
$display( "Something is wrong" );
simtocy <= cyclecounter+400;
end else begin
//$display("HERE");
seenB <= 1;
end
end
end
end
wire dummy_txpin, dummy_txbusy, dummy_bytercvd;
wire bitxce_rx, bitxce_tx, dummy_rxpin;
wire [1:0] dummy_rxst;
wire [7:0] dummy_q;
localparam adjsamplept = `BITLAX;
assign dummy_rxpin = 0;
uartICE40
#( .SUBDIV16(subdiv16), .ADJUSTSAMPLEPOINT(adjsamplept))
dut_tx
(// Outputs
.bytercvd(dummy_bytercvd),
.rxst(dummy_rxst),
.q (dummy_q[7:0]),
// Inputs
.rxpin (dummy_rxpin),
.clk (tx_clk),
.bitxce (bitxce_tx),
/*AUTOINST*/
// Outputs
.txpin (txpin),
.txbusy (txbusy),
// Inputs
.load (load),
.d (d[7:0]));
uartICE40
#( .SUBDIV16(subdiv16), .ADJUSTSAMPLEPOINT(adjsamplept))
dut_rx
(// Outputs
.txpin( dummy_txpin ),
.txbusy( dummy_txbusy ),
// Inputs
.clk (rx_clk ),
.bitxce(bitxce_rx),
.load( 1'b0 ),
.d (0),
/*AUTOINST*/
// Outputs
.bytercvd (bytercvd),
.rxst (rxst[1:0]),
.q (q[7:0]),
// Inputs
.rxpin (rxpin));
assign rxpin = ~txpin & ~glitchline;
always @(posedge tx_clk)
bitxce_tx_cnt <= bitxce_tx_cnt + 1;
always @(posedge rx_clk)
bitxce_rx_cnt <= bitxce_rx_cnt + 1;
assign bitxce_tx = bitxce_tx_cnt == 0 || `BITLAX;
assign bitxce_rx = bitxce_rx_cnt == 0 || `BITLAX;
endmodule
// Local Variables:
// verilog-library-directories:("." "src" )
// verilog-library-files:("../../../../PROJ/iCE_simlib/iCE_simlib.v" )
// verilog-library-extensions:(".v" )
// End:
|
(* Copyright (c) 2009-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import Arith.
Require Import CpdtTactics.
Set Implicit Arguments.
(* end hide *)
(** %\part{The Big Picture}
\chapter{Proving in the Large}% *)
(** It is somewhat unfortunate that the term "theorem proving" looks so much like the word "theory." Most researchers and practitioners in software assume that mechanized theorem proving is profoundly impractical. Indeed, until recently, most advances in theorem proving for higher-order logics have been largely theoretical. However, starting around the beginning of the 21st century, there was a surge in the use of proof assistants in serious verification efforts. That line of work is still quite new, but I believe it is not too soon to distill some lessons on how to work effectively with large formal proofs.
Thus, this chapter gives some tips for structuring and maintaining large Coq developments. *)
(** * Ltac Anti-Patterns *)
(** In this book, I have been following an unusual style, where proofs are not considered finished until they are %\index{fully automated proofs}%"fully automated," in a certain sense. Each such theorem is proved by a single tactic. Since Ltac is a Turing-complete programming language, it is not hard to squeeze arbitrary heuristics into single tactics, using operators like the semicolon to combine steps. In contrast, most Ltac proofs "in the wild" consist of many steps, performed by individual tactics followed by periods. Is it really worth drawing a distinction between proof steps terminated by semicolons and steps terminated by periods?
I argue that this is, in fact, a very important distinction, with serious consequences for a majority of important verification domains. The more uninteresting drudge work a proof domain involves, the more important it is to work to prove theorems with single tactics. From an automation standpoint, single-tactic proofs can be extremely effective, and automation becomes more and more critical as proofs are populated by more uninteresting detail. In this section, I will give some examples of the consequences of more common proof styles.
As a running example, consider a basic language of arithmetic expressions, an interpreter for it, and a transformation that scales up every constant in an expression. *)
Inductive exp : Set :=
| Const : nat -> exp
| Plus : exp -> exp -> exp.
Fixpoint eval (e : exp) : nat :=
match e with
| Const n => n
| Plus e1 e2 => eval e1 + eval e2
end.
Fixpoint times (k : nat) (e : exp) : exp :=
match e with
| Const n => Const (k * n)
| Plus e1 e2 => Plus (times k e1) (times k e2)
end.
(** We can write a very manual proof that [times] really implements multiplication. *)
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e.
trivial.
simpl.
rewrite IHe1.
rewrite IHe2.
rewrite mult_plus_distr_l.
trivial.
Qed.
(* begin thide *)
(** We use spaces to separate the two inductive cases, but note that these spaces have no real semantic content; Coq does not enforce that our spacing matches the real case structure of a proof. The second case mentions automatically generated hypothesis names explicitly. As a result, innocuous changes to the theorem statement can invalidate the proof. *)
Reset eval_times.
Theorem eval_times : forall k x,
eval (times k x) = k * eval x.
induction x.
trivial.
simpl.
(** %\vspace{-.15in}%[[
rewrite IHe1.
]]
<<
Error: The reference IHe1 was not found in the current environment.
>>
The inductive hypotheses are named [IHx1] and [IHx2] now, not [IHe1] and [IHe2]. *)
Abort.
(** We might decide to use a more explicit invocation of [induction] to give explicit binders for all of the names that we will reference later in the proof. *)
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e as [ | ? IHe1 ? IHe2 ].
trivial.
simpl.
rewrite IHe1.
rewrite IHe2.
rewrite mult_plus_distr_l.
trivial.
Qed.
(** We pass %\index{tactics!induction}%[induction] an%\index{intro pattern}% _intro pattern_, using a [|] character to separate instructions for the different inductive cases. Within a case, we write [?] to ask Coq to generate a name automatically, and we write an explicit name to assign that name to the corresponding new variable. It is apparent that, to use intro patterns to avoid proof brittleness, one needs to keep track of the seemingly unimportant facts of the orders in which variables are introduced. Thus, the script keeps working if we replace [e] by [x], but it has become more cluttered. Arguably, neither proof is particularly easy to follow.
That category of complaint has to do with understanding proofs as static artifacts. As with programming in general, with serious projects, it tends to be much more important to be able to support evolution of proofs as specifications change. Unstructured proofs like the above examples can be very hard to update in concert with theorem statements. For instance, consider how the last proof script plays out when we modify [times] to introduce a bug. *)
Reset times.
Fixpoint times (k : nat) (e : exp) : exp :=
match e with
| Const n => Const (1 + k * n)
| Plus e1 e2 => Plus (times k e1) (times k e2)
end.
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e as [ | ? IHe1 ? IHe2 ].
trivial.
simpl.
(** %\vspace{-.15in}%[[
rewrite IHe1.
]]
<<
Error: The reference IHe1 was not found in the current environment.
>>
*)
Abort.
(** Can you spot what went wrong, without stepping through the script step-by-step? The problem is that [trivial] never fails. Originally, [trivial] had been succeeding in proving an equality that follows by reflexivity. Our change to [times] leads to a case where that equality is no longer true. The invocation [trivial] happily leaves the false equality in place, and we continue on to the span of tactics intended for the second inductive case. Unfortunately, those tactics end up being applied to the _first_ case instead.
The problem with [trivial] could be "solved" by writing, e.g., [solve [ trivial ]] instead, so that an error is signaled early on if something unexpected happens. However, the root problem is that the syntax of a tactic invocation does not imply how many subgoals it produces. Much more confusing instances of this problem are possible. For example, if a lemma [L] is modified to take an extra hypothesis, then uses of [apply L] will generate more subgoals than before. Old unstructured proof scripts will become hopelessly jumbled, with tactics applied to inappropriate subgoals. Because of the lack of structure, there is usually relatively little to be gleaned from knowledge of the precise point in a proof script where an error is raised. *)
Reset times.
Fixpoint times (k : nat) (e : exp) : exp :=
match e with
| Const n => Const (k * n)
| Plus e1 e2 => Plus (times k e1) (times k e2)
end.
(** Many real developments try to make essentially unstructured proofs look structured by applying careful indentation conventions, idempotent case-marker tactics included solely to serve as documentation, and so on. All of these strategies suffer from the same kind of failure of abstraction that was just demonstrated. I like to say that if you find yourself caring about indentation in a proof script, it is a sign that the script is structured poorly.
We can rewrite the current proof with a single tactic. *)
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e as [ | ? IHe1 ? IHe2 ]; [
trivial
| simpl; rewrite IHe1; rewrite IHe2; rewrite mult_plus_distr_l; trivial ].
Qed.
(** We use the form of the semicolon operator that allows a different tactic to be specified for each generated subgoal. This change improves the robustness of the script: we no longer need to worry about tactics from one case being applied to a different case. Still, the proof script is not especially readable. Probably most readers would not find it helpful in explaining why the theorem is true. The same could be said for scripts using the%\index{bullets}% _bullets_ or curly braces provided by Coq 8.4, which allow code like the above to be stepped through interactively, with periods in place of the semicolons, while representing proof structure in a way that is enforced by Coq. Interactive replay of scripts becomes easier, but readability is not really helped.
The situation gets worse in considering extensions to the theorem we want to prove. Let us add multiplication nodes to our [exp] type and see how the proof fares. *)
Reset exp.
Inductive exp : Set :=
| Const : nat -> exp
| Plus : exp -> exp -> exp
| Mult : exp -> exp -> exp.
Fixpoint eval (e : exp) : nat :=
match e with
| Const n => n
| Plus e1 e2 => eval e1 + eval e2
| Mult e1 e2 => eval e1 * eval e2
end.
Fixpoint times (k : nat) (e : exp) : exp :=
match e with
| Const n => Const (k * n)
| Plus e1 e2 => Plus (times k e1) (times k e2)
| Mult e1 e2 => Mult (times k e1) e2
end.
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
(** %\vspace{-.25in}%[[
induction e as [ | ? IHe1 ? IHe2 ]; [
trivial
| simpl; rewrite IHe1; rewrite IHe2; rewrite mult_plus_distr_l; trivial ].
]]
<<
Error: Expects a disjunctive pattern with 3 branches.
>>
*)
Abort.
(** Unsurprisingly, the old proof fails, because it explicitly says that there are two inductive cases. To update the script, we must, at a minimum, remember the order in which the inductive cases are generated, so that we can insert the new case in the appropriate place. Even then, it will be painful to add the case, because we cannot walk through proof steps interactively when they occur inside an explicit set of cases. *)
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e as [ | ? IHe1 ? IHe2 | ? IHe1 ? IHe2 ]; [
trivial
| simpl; rewrite IHe1; rewrite IHe2; rewrite mult_plus_distr_l; trivial
| simpl; rewrite IHe1; rewrite mult_assoc; trivial ].
Qed.
(** Now we are in a position to see how much nicer is the style of proof that we have followed in most of this book. *)
Reset eval_times.
Hint Rewrite mult_plus_distr_l.
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e; crush.
Qed.
(* end thide *)
(** This style is motivated by a hard truth: one person's manual proof script is almost always mostly inscrutable to most everyone else. I claim that step-by-step formal proofs are a poor way of conveying information. Thus, we might as well cut out the steps and automate as much as possible.
What about the illustrative value of proofs? Most informal proofs are read to convey the big ideas of proofs. How can reading [induction e; crush] convey any big ideas? My position is that any ideas that standard automation can find are not very big after all, and the _real_ big ideas should be expressed through lemmas that are added as hints.
An example should help illustrate what I mean. Consider this function, which rewrites an expression using associativity of addition and multiplication. *)
Fixpoint reassoc (e : exp) : exp :=
match e with
| Const _ => e
| Plus e1 e2 =>
let e1' := reassoc e1 in
let e2' := reassoc e2 in
match e2' with
| Plus e21 e22 => Plus (Plus e1' e21) e22
| _ => Plus e1' e2'
end
| Mult e1 e2 =>
let e1' := reassoc e1 in
let e2' := reassoc e2 in
match e2' with
| Mult e21 e22 => Mult (Mult e1' e21) e22
| _ => Mult e1' e2'
end
end.
Theorem reassoc_correct : forall e, eval (reassoc e) = eval e.
(* begin thide *)
induction e; crush;
match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] =>
destruct E; crush
end.
(** One subgoal remains:
[[
IHe2 : eval e3 * eval e4 = eval e2
============================
eval e1 * eval e3 * eval e4 = eval e1 * eval e2
]]
The [crush] tactic does not know how to finish this goal. We could finish the proof manually. *)
rewrite <- IHe2; crush.
(** However, the proof would be easier to understand and maintain if we separated this insight into a separate lemma. *)
Abort.
Lemma rewr : forall a b c d, b * c = d -> a * b * c = a * d.
crush.
Qed.
Hint Resolve rewr.
Theorem reassoc_correct : forall e, eval (reassoc e) = eval e.
induction e; crush;
match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] =>
destruct E; crush
end.
Qed.
(* end thide *)
(** In the limit, a complicated inductive proof might rely on one hint for each inductive case. The lemma for each hint could restate the associated case. Compared to manual proof scripts, we arrive at more readable results. Scripts no longer need to depend on the order in which cases are generated. The lemmas are easier to digest separately than are fragments of tactic code, since lemma statements include complete proof contexts. Such contexts can only be extracted from monolithic manual proofs by stepping through scripts interactively.
The more common situation is that a large induction has several easy cases that automation makes short work of. In the remaining cases, automation performs some standard simplification. Among these cases, some may require quite involved proofs; such a case may deserve a hint lemma of its own, where the lemma statement may copy the simplified version of the case. Alternatively, the proof script for the main theorem may be extended with some automation code targeted at the specific case. Even such targeted scripting is more desirable than manual proving, because it may be read and understood without knowledge of a proof's hierarchical structure, case ordering, or name binding structure.
A competing alternative to the common style of Coq tactics is the%\index{declarative proof scripts}% _declarative_ style, most frequently associated today with the %\index{Isar}%Isar%~\cite{Isar}% language. A declarative proof script is very explicit about subgoal structure and introduction of local names, aiming for human readability. The coding of proof automation is taken to be outside the scope of the proof language, an assumption related to the idea that it is not worth building new automation for each serious theorem. I have shown in this book many examples of theorem-specific automation, which I believe is crucial for scaling to significant results. Declarative proof scripts make it easier to read scripts to modify them for theorem statement changes, but the alternate%\index{adaptive proof scripts}% _adaptive_ style from this book allows use of the _same_ scripts for many versions of a theorem.
Perhaps I am a pessimist for thinking that fully formal proofs will inevitably consist of details that are uninteresting to people, but it is my preference to focus on conveying proof-specific details through choice of lemmas. Additionally, adaptive Ltac scripts contain bits of automation that can be understood in isolation. For instance, in a big [repeat match] loop, each case can generally be digested separately, which is a big contrast from trying to understand the hierarchical structure of a script in a more common style. Adaptive scripts rely on variable binding, but generally only over very small scopes, whereas understanding a traditional script requires tracking the identities of local variables potentially across pages of code.
One might also wonder why it makes sense to prove all theorems automatically (in the sense of adaptive proof scripts) but not construct all programs automatically. My view there is that _program synthesis_ is a very useful idea that deserves broader application! In practice, there are difficult obstacles in the way of finding a program automatically from its specification. A typical specification is not exhaustive in its description of program properties. For instance, details of performance on particular machine architectures are often omitted. As a result, a synthesized program may be correct in some sense while suffering from deficiencies in other senses. Program synthesis research will continue to come up with ways of dealing with this problem, but the situation for theorem proving is fundamentally different. Following mathematical practice, the only property of a formal proof that we care about is which theorem it proves, and it is trivial to check this property automatically. In other words, with a simple criterion for what makes a proof acceptable, automatic search is straightforward. Of course, in practice we also care about understandability of proofs to facilitate long-term maintenance, which is just what motivates the techniques outlined above, and the next section gives some related advice. *)
(** * Debugging and Maintaining Automation *)
(** Fully automated proofs are desirable because they open up possibilities for automatic adaptation to changes of specification. A well-engineered script within a narrow domain can survive many changes to the formulation of the problem it solves. Still, as we are working with higher-order logic, most theorems fall within no obvious decidable theories. It is inevitable that most long-lived automated proofs will need updating.
Before we are ready to update our proofs, we need to write them in the first place. While fully automated scripts are most robust to changes of specification, it is hard to write every new proof directly in that form. Instead, it is useful to begin a theorem with exploratory proving and then gradually refine it into a suitable automated form.
Consider this theorem from Chapter 8, which we begin by proving in a mostly manual way, invoking [crush] after each step to discharge any low-hanging fruit. Our manual effort involves choosing which expressions to case-analyze on. *)
(* begin hide *)
Require Import MoreDep.
(* end hide *)
Theorem cfold_correct : forall t (e : exp t), expDenote e = expDenote (cfold e).
(* begin thide *)
induction e; crush.
dep_destruct (cfold e1); crush.
dep_destruct (cfold e2); crush.
dep_destruct (cfold e1); crush.
dep_destruct (cfold e2); crush.
dep_destruct (cfold e1); crush.
dep_destruct (cfold e2); crush.
dep_destruct (cfold e1); crush.
dep_destruct (expDenote e1); crush.
dep_destruct (cfold e); crush.
dep_destruct (cfold e); crush.
Qed.
(** In this complete proof, it is hard to avoid noticing a pattern. We rework the proof, abstracting over the patterns we find. *)
Reset cfold_correct.
Theorem cfold_correct : forall t (e : exp t), expDenote e = expDenote (cfold e).
induction e; crush.
(** The expression we want to destruct here turns out to be the discriminee of a [match], and we can easily enough write a tactic that destructs all such expressions. *)
Ltac t :=
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
end; crush).
t.
(** This tactic invocation discharges the whole case. It does the same on the next two cases, but it gets stuck on the fourth case. *)
t.
t.
t.
(** The subgoal's conclusion is:
[[
============================
(if expDenote e1 then expDenote (cfold e2) else expDenote (cfold e3)) =
expDenote (if expDenote e1 then cfold e2 else cfold e3)
]]
We need to expand our [t] tactic to handle this case. *)
Ltac t' :=
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
| [ |- (if ?E then _ else _) = _ ] => destruct E
end; crush).
t'.
(** Now the goal is discharged, but [t'] has no effect on the next subgoal. *)
t'.
(** A final revision of [t] finishes the proof. *)
Ltac t'' :=
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
| [ |- (if ?E then _ else _) = _ ] => destruct E
| [ |- context[match pairOut ?E with Some _ => _
| None => _ end] ] =>
dep_destruct E
end; crush).
t''.
t''.
Qed.
(** We can take the final tactic and move it into the initial part of the proof script, arriving at a nicely automated proof. *)
Reset t.
Theorem cfold_correct : forall t (e : exp t), expDenote e = expDenote (cfold e).
induction e; crush;
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
| [ |- (if ?E then _ else _) = _ ] => destruct E
| [ |- context[match pairOut ?E with Some _ => _
| None => _ end] ] =>
dep_destruct E
end; crush).
Qed.
(* end thide *)
(** Even after we put together nice automated proofs, we must deal with specification changes that can invalidate them. It is not generally possible to step through single-tactic proofs interactively. There is a command %\index{Vernacular commands!Debug On}%[Debug On] that lets us step through points in tactic execution, but the debugger tends to make counterintuitive choices of which points we would like to stop at, and per-point output is quite verbose, so most Coq users do not find this debugging mode very helpful. How are we to understand what has broken in a script that used to work?
An example helps demonstrate a useful approach. Consider what would have happened in our proof of [reassoc_correct] if we had first added an unfortunate rewriting hint. *)
Reset reassoc_correct.
Theorem confounder : forall e1 e2 e3,
eval e1 * eval e2 * eval e3 = eval e1 * (eval e2 + 1 - 1) * eval e3.
crush.
Qed.
Hint Rewrite confounder.
Theorem reassoc_correct : forall e, eval (reassoc e) = eval e.
(* begin thide *)
induction e; crush;
match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] =>
destruct E; crush
end.
(** One subgoal remains:
[[
============================
eval e1 * (eval e3 + 1 - 1) * eval e4 = eval e1 * eval e2
]]
The poorly chosen rewrite rule fired, changing the goal to a form where another hint no longer applies. Imagine that we are in the middle of a large development with many hints. How would we diagnose the problem? First, we might not be sure which case of the inductive proof has gone wrong. It is useful to separate out our automation procedure and apply it manually. *)
Restart.
Ltac t := crush; match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] =>
destruct E; crush
end.
induction e.
(** Since we see the subgoals before any simplification occurs, it is clear that we are looking at the case for constants. Our [t] makes short work of it. *)
t.
(** The next subgoal, for addition, is also discharged without trouble. *)
t.
(** The final subgoal is for multiplication, and it is here that we get stuck in the proof state summarized above. *)
t.
(** What is [t] doing to get us to this point? The %\index{tactics!info}%[info] command can help us answer this kind of question. (As of this writing, [info] is no longer functioning in the most recent Coq release, but I hope it returns.) *)
Undo.
info t.
(* begin hide *)
(* begin thide *)
Definition eir := eq_ind_r.
(* end thide *)
(* end hide *)
(** %\vspace{-.15in}%[[
== simpl in *; intuition; subst; autorewrite with core in *;
simpl in *; intuition; subst; autorewrite with core in *;
simpl in *; intuition; subst; destruct (reassoc e2).
simpl in *; intuition.
simpl in *; intuition.
simpl in *; intuition; subst; autorewrite with core in *;
refine (eq_ind_r
(fun n : nat =>
n * (eval e3 + 1 - 1) * eval e4 = eval e1 * eval e2) _ IHe1);
autorewrite with core in *; simpl in *; intuition;
subst; autorewrite with core in *; simpl in *;
intuition; subst.
]]
A detailed trace of [t]'s execution appears. Since we are using the very general [crush] tactic, many of these steps have no effect and only occur as instances of a more general strategy. We can copy-and-paste the details to see where things go wrong. *)
Undo.
(** We arbitrarily split the script into chunks. The first few seem not to do any harm. *)
simpl in *; intuition; subst; autorewrite with core in *.
simpl in *; intuition; subst; autorewrite with core in *.
simpl in *; intuition; subst; destruct (reassoc e2).
simpl in *; intuition.
simpl in *; intuition.
(** The next step is revealed as the culprit, bringing us to the final unproved subgoal. *)
simpl in *; intuition; subst; autorewrite with core in *.
(** We can split the steps further to assign blame. *)
Undo.
simpl in *.
intuition.
subst.
autorewrite with core in *.
(** It was the final of these four tactics that made the rewrite. We can find out exactly what happened. The [info] command presents hierarchical views of proof steps, and we can zoom down to a lower level of detail by applying [info] to one of the steps that appeared in the original trace. *)
Undo.
info autorewrite with core in *.
(** %\vspace{-.15in}%[[
== refine (eq_ind_r (fun n : nat => n = eval e1 * eval e2) _
(confounder (reassoc e1) e3 e4)).
]]
The way a rewrite is displayed is somewhat baroque, but we can see that theorem [confounder] is the final culprit. At this point, we could remove that hint, prove an alternate version of the key lemma [rewr], or come up with some other remedy. Fixing this kind of problem tends to be relatively easy once the problem is revealed. *)
Abort.
(* end thide *)
(** Sometimes a change to a development has undesirable performance consequences, even if it does not prevent any old proof scripts from completing. If the performance consequences are severe enough, the proof scripts can be considered broken for practical purposes.
Here is one example of a performance surprise. *)
Section slow.
Hint Resolve trans_eq.
(** The central element of the problem is the addition of transitivity as a hint. With transitivity available, it is easy for proof search to wind up exploring exponential search spaces. We also add a few other arbitrary variables and hypotheses, designed to lead to trouble later. *)
Variable A : Set.
Variables P Q R S : A -> A -> Prop.
Variable f : A -> A.
Hypothesis H1 : forall x y, P x y -> Q x y -> R x y -> f x = f y.
Hypothesis H2 : forall x y, S x y -> R x y.
(** We prove a simple lemma very quickly, using the %\index{Vernacular commands!Time}%[Time] command to measure exactly how quickly. *)
Lemma slow : forall x y, P x y -> Q x y -> S x y -> f x = f y.
Time eauto 6.
(** <<
Finished transaction in 0. secs (0.068004u,0.s)
>>
*)
Qed.
(** Now we add a different hypothesis, which is innocent enough; in fact, it is even provable as a theorem. *)
Hypothesis H3 : forall x y, x = y -> f x = f y.
Lemma slow' : forall x y, P x y -> Q x y -> S x y -> f x = f y.
Time eauto 6.
(** <<
Finished transaction in 2. secs (1.264079u,0.s)
>>
%\vspace{-.15in}%Why has the search time gone up so much? The [info] command is not much help, since it only shows the result of search, not all of the paths that turned out to be worthless. *)
(* begin thide *)
Restart.
info eauto 6.
(** %\vspace{-.15in}%[[
== intro x; intro y; intro H; intro H0; intro H4;
simple eapply trans_eq.
simple apply eq_refl.
simple eapply trans_eq.
simple apply eq_refl.
simple eapply trans_eq.
simple apply eq_refl.
simple apply H1.
eexact H.
eexact H0.
simple apply H2; eexact H4.
]]
This output does not tell us why proof search takes so long, but it does provide a clue that would be useful if we had forgotten that we added transitivity as a hint. The [eauto] tactic is applying depth-first search, and the proof script where the real action is ends up buried inside a chain of pointless invocations of transitivity, where each invocation uses reflexivity to discharge one subgoal. Each increment to the depth argument to [eauto] adds another silly use of transitivity. This wasted proof effort only adds linear time overhead, as long as proof search never makes false steps. No false steps were made before we added the new hypothesis, but somehow the addition made possible a new faulty path. To understand which paths we enabled, we can use the %\index{tactics!debug}%[debug] command. *)
Restart.
debug eauto 6.
(* begin hide *)
(* begin thide *)
Definition deeeebug := (@eq_refl, @sym_eq).
(* end thide *)
(* end hide *)
(** The output is a large proof tree. The beginning of the tree is enough to reveal what is happening:
[[
1 depth=6
1.1 depth=6 intro
1.1.1 depth=6 intro
1.1.1.1 depth=6 intro
1.1.1.1.1 depth=6 intro
1.1.1.1.1.1 depth=6 intro
1.1.1.1.1.1.1 depth=5 apply H3
1.1.1.1.1.1.1.1 depth=4 eapply trans_eq
1.1.1.1.1.1.1.1.1 depth=4 apply eq_refl
1.1.1.1.1.1.1.1.1.1 depth=3 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1 depth=3 apply eq_refl
1.1.1.1.1.1.1.1.1.1.1.1 depth=2 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.1 depth=2 apply eq_refl
1.1.1.1.1.1.1.1.1.1.1.1.1.1 depth=1 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.1.1.1 depth=1 apply eq_refl
1.1.1.1.1.1.1.1.1.1.1.1.1.1.1.1 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.1.1.2 depth=1 apply sym_eq ; trivial
1.1.1.1.1.1.1.1.1.1.1.1.1.1.2.1 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.1.1.3 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.2 depth=2 apply sym_eq ; trivial
1.1.1.1.1.1.1.1.1.1.1.1.2.1 depth=1 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.2.1.1 depth=1 apply eq_refl
1.1.1.1.1.1.1.1.1.1.1.1.2.1.1.1 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.2.1.2 depth=1 apply sym_eq ; trivial
1.1.1.1.1.1.1.1.1.1.1.1.2.1.2.1 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.2.1.3 depth=0 eapply trans_eq
]]
The first choice [eauto] makes is to apply [H3], since [H3] has the fewest hypotheses of all of the hypotheses and hints that match. However, it turns out that the single hypothesis generated is unprovable. That does not stop [eauto] from trying to prove it with an exponentially sized tree of applications of transitivity, reflexivity, and symmetry of equality. It is the children of the initial [apply H3] that account for all of the noticeable time in proof execution. In a more realistic development, we might use this output of [debug] to realize that adding transitivity as a hint was a bad idea. *)
Qed.
(* end thide *)
End slow.
(** As aggravating as the above situation may be, there is greater aggravation to be had from importing library modules with commands like %\index{Vernacular commands!Require Import}%[Require Import]. Such a command imports not just the Gallina terms from a module, but also all the hints for [auto], [eauto], and [autorewrite]. Some very recent versions of Coq include mechanisms for removing hints from databases, but the proper solution is to be very conservative in exporting hints from modules. Consider putting hints in named databases, so that they may be used only when called upon explicitly, as demonstrated in Chapter 13.
It is also easy to end up with a proof script that uses too much memory. As tactics run, they avoid generating proof terms, since serious proof search will consider many possible avenues, and we do not want to build proof terms for subproofs that end up unused. Instead, tactic execution maintains%\index{thunks}% _thunks_ (suspended computations, represented with closures), such that a tactic's proof-producing thunk is only executed when we run %\index{Vernacular commands!Qed}%[Qed]. These thunks can use up large amounts of space, such that a proof script exhausts available memory, even when we know that we could have used much less memory by forcing some thunks earlier.
The %\index{tactics!abstract}%[abstract] tactical helps us force thunks by proving some subgoals as their own lemmas. For instance, a proof [induction x; crush] can in many cases be made to use significantly less peak memory by changing it to [induction x; abstract crush]. The main limitation of [abstract] is that it can only be applied to subgoals that are proved completely, with no undetermined unification variables in their initial states. Still, many large automated proofs can realize vast memory savings via [abstract]. *)
(** * Modules *)
(** Last chapter's examples of proof by reflection demonstrate opportunities for implementing abstract proof strategies with stronger formal guarantees than can be had with Ltac scripting. Coq's _module system_ provides another tool for more rigorous development of generic theorems. This feature is inspired by the module systems found in Standard ML%~\cite{modules}% and OCaml, and the discussion that follows assumes familiarity with the basics of one of those systems.
ML modules facilitate the grouping of %\index{abstract type}%abstract types with operations over those types. Moreover, there is support for%\index{functor}% _functors_, which are functions from modules to modules. A canonical example of a functor is one that builds a data structure implementation from a module that describes a domain of keys and its associated comparison operations.
When we add modules to a base language with dependent types, it becomes possible to use modules and functors to formalize kinds of reasoning that are common in algebra. For instance, the following module signature captures the essence of the algebraic structure known as a group. A group consists of a carrier set [G], an associative binary operation [f], a left identity element [id] for [f], and an operation [i] that is a left inverse for [f].%\index{Vernacular commands!Module Type}% *)
Module Type GROUP.
Parameter G : Set.
Parameter f : G -> G -> G.
Parameter id : G.
Parameter i : G -> G.
Axiom assoc : forall a b c, f (f a b) c = f a (f b c).
Axiom ident : forall a, f id a = a.
Axiom inverse : forall a, f (i a) a = id.
End GROUP.
(** Many useful theorems hold of arbitrary groups. We capture some such theorem statements in another module signature.%\index{Vernacular commands!Declare Module}% *)
Module Type GROUP_THEOREMS.
Declare Module M : GROUP.
Axiom ident' : forall a, M.f a M.id = a.
Axiom inverse' : forall a, M.f a (M.i a) = M.id.
Axiom unique_ident : forall id', (forall a, M.f id' a = a) -> id' = M.id.
End GROUP_THEOREMS.
(** We implement generic proofs of these theorems with a functor, whose input is an arbitrary group [M]. %\index{Vernacular commands!Module}% *)
Module GroupProofs (M : GROUP) : GROUP_THEOREMS with Module M := M.
(** As in ML, Coq provides multiple options for ascribing signatures to modules. Here we use just the colon operator, which implements%\index{opaque ascription}% _opaque ascription_, hiding all details of the module not exposed by the signature. Another option is%\index{transparent ascription}% _transparent ascription_ via the [<:] operator, which checks for signature compatibility without hiding implementation details. Here we stick with opaque ascription but employ the [with] operation to add more detail to a signature, exposing just those implementation details that we need to. For instance, here we expose the underlying group representation set and operator definitions. Without such a refinement, we would get an output module proving theorems about some unknown group, which is not very useful. Also note that opaque ascription can in Coq have some undesirable consequences without analogues in ML, since not just the types but also the _definitions_ of identifiers have significance in type checking and theorem proving. *)
Module M := M.
(** To ensure that the module we are building meets the [GROUP_THEOREMS] signature, we add an extra local name for [M], the functor argument. *)
Import M.
(** It would be inconvenient to repeat the prefix [M.] everywhere in our theorem statements and proofs, so we bring all the identifiers of [M] into the local scope unqualified.
Now we are ready to prove the three theorems. The proofs are completely manual, which may seem ironic given the content of the previous sections! This illustrates another lesson, which is that short proof scripts that change infrequently may be worth leaving unautomated. It would take some effort to build suitable generic automation for these theorems about groups, so I stick with manual proof scripts to avoid distracting us from the main message of the section. We take the proofs from the Wikipedia page on elementary group theory. *)
Theorem inverse' : forall a, f a (i a) = id.
intro.
rewrite <- (ident (f a (i a))).
rewrite <- (inverse (f a (i a))) at 1.
rewrite assoc.
rewrite assoc.
rewrite <- (assoc (i a) a (i a)).
rewrite inverse.
rewrite ident.
apply inverse.
Qed.
Theorem ident' : forall a, f a id = a.
intro.
rewrite <- (inverse a).
rewrite <- assoc.
rewrite inverse'.
apply ident.
Qed.
Theorem unique_ident : forall id', (forall a, M.f id' a = a) -> id' = M.id.
intros.
rewrite <- (H id).
symmetry.
apply ident'.
Qed.
End GroupProofs.
(** We can show that the integers with [+] form a group. *)
Require Import ZArith.
Open Scope Z_scope.
Module Int.
Definition G := Z.
Definition f x y := x + y.
Definition id := 0.
Definition i x := -x.
Theorem assoc : forall a b c, f (f a b) c = f a (f b c).
unfold f; crush.
Qed.
Theorem ident : forall a, f id a = a.
unfold f, id; crush.
Qed.
Theorem inverse : forall a, f (i a) a = id.
unfold f, i, id; crush.
Qed.
End Int.
(** Next, we can produce integer-specific versions of the generic group theorems. *)
Module IntProofs := GroupProofs(Int).
Check IntProofs.unique_ident.
(** %\vspace{-.15in}% [[
IntProofs.unique_ident
: forall e' : Int.G, (forall a : Int.G, Int.f e' a = a) -> e' = Int.e
]]
Projections like [Int.G] are known to be definitionally equal to the concrete values we have assigned to them, so the above theorem yields as a trivial corollary the following more natural restatement: *)
Theorem unique_ident : forall id', (forall a, id' + a = a) -> id' = 0.
(* begin thide *)
exact IntProofs.unique_ident.
Qed.
(* end thide *)
(** As in ML, the module system provides an effective way to structure large developments. Unlike in ML, Coq modules add no expressiveness; we can implement any module as an inhabitant of a dependent record type. It is the second-class nature of modules that makes them easier to use than dependent records in many cases. Because modules may only be used in quite restricted ways, it is easier to support convenient module coding through special commands and editing modes, as the above example demonstrates. An isomorphic implementation with records would have suffered from lack of such conveniences as module subtyping and importation of the fields of a module. On the other hand, all module values must be determined statically, so modules may not be computed, e.g., within the definitions of normal functions, based on particular function parameters. *)
(** * Build Processes *)
(* begin hide *)
(* begin thide *)
Module Lib.
Module A.
End A.
Module B.
End B.
Module C.
End C.
End Lib.
Module Client.
Module D.
End D.
Module E.
End E.
End Client.
(* end thide *)
(* end hide *)
(** As in software development, large Coq projects are much more manageable when split across multiple files and when decomposed into libraries. Coq and Proof General provide very good support for these activities.
Consider a library that we will name [Lib], housed in directory <<LIB>> and split between files <<A.v>>, <<B.v>>, and <<C.v>>. A simple %\index{Makefile}%Makefile will compile the library, relying on the standard Coq tool %\index{coq\_makefile}%<<coq_makefile>> to do the hard work.
<<
MODULES := A B C
VS := $(MODULES:%=%.v)
.PHONY: coq clean
coq: Makefile.coq
$(MAKE) -f Makefile.coq
Makefile.coq: Makefile $(VS)
coq_makefile -R . Lib $(VS) -o Makefile.coq
clean:: Makefile.coq
$(MAKE) -f Makefile.coq clean
rm -f Makefile.coq
>>
The Makefile begins by defining a variable <<VS>> holding the list of filenames to be included in the project. The primary target is <<coq>>, which depends on the construction of an auxiliary Makefile called <<Makefile.coq>>. Another rule explains how to build that file. We call <<coq_makefile>>, using the <<-R>> flag to specify that files in the current directory should be considered to belong to the library [Lib]. This Makefile will build a compiled version of each module, such that <<X.v>> is compiled into <<X.vo>>.
Now code in <<B.v>> may refer to definitions in <<A.v>> after running
[[
Require Import Lib.A.
]]
%\vspace{-.15in}%Library [Lib] is presented as a module, containing a submodule [A], which contains the definitions from <<A.v>>. These are genuine modules in the sense of Coq's module system, and they may be passed to functors and so on.
The command [Require Import] is a convenient combination of two more primitive commands. The %\index{Vernacular commands!Require}%[Require] command finds the <<.vo>> file containing the named module, ensuring that the module is loaded into memory. The %\index{Vernacular commands!Import}%[Import] command loads all top-level definitions of the named module into the current namespace, and it may be used with local modules that do not have corresponding <<.vo>> files. Another command, %\index{Vernacular commands!Load}%[Load], is for inserting the contents of a named file verbatim. It is generally better to use the module-based commands, since they avoid rerunning proof scripts, and they facilitate reorganization of directory structure without the need to change code.
Now we would like to use our library from a different development, called [Client] and found in directory <<CLIENT>>, which has its own Makefile.
<<
MODULES := D E
VS := $(MODULES:%=%.v)
.PHONY: coq clean
coq: Makefile.coq
$(MAKE) -f Makefile.coq
Makefile.coq: Makefile $(VS)
coq_makefile -R LIB Lib -R . Client $(VS) -o Makefile.coq
clean:: Makefile.coq
$(MAKE) -f Makefile.coq clean
rm -f Makefile.coq
>>
We change the <<coq_makefile>> call to indicate where the library [Lib] is found. Now <<D.v>> and <<E.v>> can refer to definitions from [Lib] module [A] after running
[[
Require Import Lib.A.
]]
%\vspace{-.15in}\noindent{}%and <<E.v>> can refer to definitions from <<D.v>> by running
[[
Require Import Client.D.
]]
%\vspace{-.15in}%It can be useful to split a library into several files, but it is also inconvenient for client code to import library modules individually. We can get the best of both worlds by, for example, adding an extra source file <<Lib.v>> to [Lib]'s directory and Makefile, where that file contains just this line:%\index{Vernacular commands!Require Export}%
[[
Require Export Lib.A Lib.B Lib.C.
]]
%\vspace{-.15in}%Now client code can import all definitions from all of [Lib]'s modules simply by running
[[
Require Import Lib.
]]
%\vspace{-.15in}%The two Makefiles above share a lot of code, so, in practice, it is useful to define a common Makefile that is included by multiple library-specific Makefiles.
%\medskip%
The remaining ingredient is the proper way of editing library code files in Proof General. Recall this snippet of <<.emacs>> code from Chapter 2, which tells Proof General where to find the library associated with this book.
<<
(custom-set-variables
...
'(coq-prog-args '("-I" "/path/to/cpdt/src"))
...
)
>>
To do interactive editing of our current example, we just need to change the flags to point to the right places.
<<
(custom-set-variables
...
; '(coq-prog-args '("-I" "/path/to/cpdt/src"))
'(coq-prog-args '("-R" "LIB" "Lib" "-R" "CLIENT" "Client"))
...
)
>>
When working on multiple projects, it is useful to leave multiple versions of this setting in your <<.emacs>> file, commenting out all but one of them at any moment in time. To switch between projects, change the commenting structure and restart Emacs.
Alternatively, we can revisit the directory-local settings approach and write the following into a file <<.dir-locals.el>> in <<CLIENT>>:
<<
((coq-mode . ((coq-prog-args .
("-emacs-U" "-R" "LIB" "Lib" "-R" "CLIENT" "Client")))))
>>
A downside of this approach is that users of your code may not want to trust the arbitrary Emacs Lisp programs that you are allowed to place in such files, so that they prefer to add mappings manually.
*)
|
// nrzi_4b5b_decoder.v
`timescale 1 ns / 1 ps
module nrzi_4b5b_decoder
(
input clk80,
input reset,
input enable,
input [4:0]din,
output reg [3:0]dout,
output reg error
);
reg [4:0]d;
reg inv;
always @(posedge clk80 or posedge reset)
begin
if (reset)
begin
d <= 5'b00000;
inv <= 0;
dout <= 4'b1010;
error <= 0;
end
else
begin if (enable)
d <= inv ? din : ~din;
inv <= din[0];
case (d)
5'b01011: {dout,error} <= 5'b0000_0;
5'b10001: {dout,error} <= 5'b0001_0;
5'b00111: {dout,error} <= 5'b0010_0;
5'b00110: {dout,error} <= 5'b0011_0;
5'b10011: {dout,error} <= 5'b0100_0;
5'b10010: {dout,error} <= 5'b0101_0;
5'b10100: {dout,error} <= 5'b0110_0;
5'b10101: {dout,error} <= 5'b0111_0;
5'b00011: {dout,error} <= 5'b1000_0;
5'b00010: {dout,error} <= 5'b1001_0;
5'b00100: {dout,error} <= 5'b1010_0;
5'b00000: {dout,error} <= 5'b1010_0;
5'b00101: {dout,error} <= 5'b1011_0;
5'b01100: {dout,error} <= 5'b1100_0;
5'b01101: {dout,error} <= 5'b1101_0;
5'b01000: {dout,error} <= 5'b1110_0;
5'b01001: {dout,error} <= 5'b1111_0;
default: {dout,error} <= 5'b1010_1;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFSBP_FUNCTIONAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_FUNCTIONAL_PP_V |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 15:50:55 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_auto_pc_0_stub.v
// Design : gcd_block_design_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_usr_top.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Mon Aug 28 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module interfaces with the user. The user should provide the data
// and various commands.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_usr_top #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter BANK_WIDTH = 2,
parameter CS_BITS = 0,
parameter COL_WIDTH = 10,
parameter DQ_WIDTH = 72,
parameter DQ_PER_DQS = 8,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0,
parameter DQS_WIDTH = 9,
parameter ROW_WIDTH = 14
)
(
input clk0,
input clk90,
input rst0,
input [DQ_WIDTH-1:0] rd_data_in_rise,
input [DQ_WIDTH-1:0] rd_data_in_fall,
input [DQS_WIDTH-1:0] phy_calib_rden,
input [DQS_WIDTH-1:0] phy_calib_rden_sel,
output rd_data_valid,
output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input ctrl_af_rden,
output [2:0] af_cmd,
output [30:0] af_addr,
output af_empty,
output app_af_afull,
output [1:0] rd_ecc_error,
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
input wdf_rden,
output app_wdf_afull,
output [(2*DQ_WIDTH)-1:0] wdf_data,
output [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data
);
wire [(APPDATA_WIDTH/2)-1:0] i_rd_data_fifo_out_fall;
wire [(APPDATA_WIDTH/2)-1:0] i_rd_data_fifo_out_rise;
//***************************************************************************
assign rd_data_fifo_out = {i_rd_data_fifo_out_fall,
i_rd_data_fifo_out_rise};
// read data de-skew and ECC calculation
ddr2_usr_rd #
(
.DQ_PER_DQS (DQ_PER_DQS),
.ECC_ENABLE (ECC_ENABLE),
.APPDATA_WIDTH (APPDATA_WIDTH),
.DQS_WIDTH (DQS_WIDTH)
)
u_usr_rd
(
.clk0 (clk0),
.rst0 (rst0),
.rd_data_in_rise (rd_data_in_rise),
.rd_data_in_fall (rd_data_in_fall),
.rd_ecc_error (rd_ecc_error),
.ctrl_rden (phy_calib_rden),
.ctrl_rden_sel (phy_calib_rden_sel),
.rd_data_valid (rd_data_valid),
.rd_data_out_rise (i_rd_data_fifo_out_rise),
.rd_data_out_fall (i_rd_data_fifo_out_fall)
);
// Command/Addres FIFO
ddr2_usr_addr_fifo #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_addr_fifo
(
.clk0 (clk0),
.rst0 (rst0),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren),
.ctrl_af_rden (ctrl_af_rden),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.app_af_afull (app_af_afull)
);
ddr2_usr_wr #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.DQ_WIDTH (DQ_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_wr
(
.clk0 (clk0),
.clk90 (clk90),
.rst0 (rst0),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.wdf_rden (wdf_rden),
.app_wdf_afull (app_wdf_afull),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data)
);
endmodule |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:22 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_gpio_0_0_stub.v
// Design : zynq_design_1_axi_gpio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of top
//
// Generated
// by: wig
// on: Tue Apr 1 13:31:51 2008
// cmd: /cygdrive/c/eclipse/MIX/mix_0.pl -strip -nodelta ../noassign.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: top.v,v 1.1 2008/04/01 12:53:30 wig Exp $
// $Date: 2008/04/01 12:53:30 $
// $Log: top.v,v $
// Revision 1.1 2008/04/01 12:53:30 wig
// Added testcase noassign for optimzeassignport feature
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of top
//
// No user `defines in this module
module top
//
// Generated Module TOP
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire clk;
wire clk2_i;
wire data;
wire data2_i;
wire ready0;
wire ready1;
wire ready2_0;
wire ready2_1;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for M0
m0 M0 (
.clk2_o(clk2_i),
.clk_o(clk),
.data2_o(data2_i),
.data_o(data),
.ready0_i(ready0),
.ready1_i(ready1),
.ready2_0(ready2_0),
.ready2_1(ready2_1)
);
// End of Generated Instance Port Map for M0
// Generated Instance Port Map for N0
n0 N0 (
.clk2_i_i(clk2_i),
.clk_i(clk),
.data2_i_i(data2_i),
.data_i(data),
.ready0_o(ready0),
.ready1_o(ready1),
.ready2_0_o(ready2_0),
.ready2_1_o(ready2_1)
);
// End of Generated Instance Port Map for N0
endmodule
//
// End of Generated Module rtl of top
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog wrapper for lpflow_decapkapwr with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_decapkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_12 (
VPWR ,
KAPWR,
VGND ,
VPB ,
VNB
);
input VPWR ;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base (
.VPWR(VPWR),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_12 ();
// Voltage supply signals
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg #(
parameter fml_depth = 26,
parameter cache_depth = 14, /* 16kb cache */
parameter invalidate_bit = 26
) (
input sys_clk,
input sys_rst,
input [31:0] wb_adr_i,
input [2:0] wb_cti_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
input [3:0] wb_sel_i,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
output reg fml_we,
input fml_ack,
output [7:0] fml_sel,
output [63:0] fml_do,
input [63:0] fml_di,
/* Direct Cache Bus */
input dcb_stb,
input [fml_depth-1:0] dcb_adr,
output [63:0] dcb_dat,
output dcb_hit
);
/*
* Line length is the burst length, that is 4*64 bits, or 32 bytes
* Address split up :
*
* | TAG | INDEX | OFFSET |
* |fml_depth-1 cache_depth|cache_depth-1 5|4 0|
*
*/
wire [4:0] offset = wb_adr_i[4:0];
wire [cache_depth-1-5:0] index = wb_adr_i[cache_depth-1:5];
wire [fml_depth-cache_depth-1:0] tag = wb_adr_i[fml_depth-1:cache_depth];
wire [4:0] dcb_offset = dcb_adr[4:0];
wire [cache_depth-1-5:0] dcb_index = dcb_adr[cache_depth-1:5];
wire [fml_depth-cache_depth-1:0] dcb_tag = dcb_adr[fml_depth-1:cache_depth];
wire coincidence = tag == dcb_tag;
/*
* TAG MEMORY
*
* Addressed by index (length cache_depth-5)
* Contains valid bit + dirty bit + tag
*/
wire [cache_depth-1-5:0] tagmem_a;
reg tagmem_we;
wire [fml_depth-cache_depth-1+2:0] tagmem_di;
wire [fml_depth-cache_depth-1+2:0] tagmem_do;
wire [cache_depth-1-5:0] tagmem_a2;
wire [fml_depth-cache_depth-1+2:0] tagmem_do2;
fmlbrg_tagmem #(
.depth(cache_depth-5),
.width(fml_depth-cache_depth+2)
) tagmem (
.sys_clk(sys_clk),
.a(tagmem_a),
.we(tagmem_we),
.di(tagmem_di),
.do(tagmem_do),
.a2(tagmem_a2),
.do2(tagmem_do2)
);
reg index_load;
reg [cache_depth-1-5:0] index_r;
always @(posedge sys_clk) begin
if(index_load)
index_r <= index;
end
assign tagmem_a = index;
assign tagmem_a2 = dcb_index;
reg di_valid;
reg di_dirty;
assign tagmem_di = {di_valid, di_dirty, tag};
wire do_valid;
wire do_dirty;
wire [fml_depth-cache_depth-1:0] do_tag;
wire cache_hit;
wire do2_valid;
wire [fml_depth-cache_depth-1:0] do2_tag;
assign do_valid = tagmem_do[fml_depth-cache_depth-1+2];
assign do_dirty = tagmem_do[fml_depth-cache_depth-1+1];
assign do_tag = tagmem_do[fml_depth-cache_depth-1:0];
assign do2_valid = tagmem_do2[fml_depth-cache_depth-1+2];
assign do2_tag = tagmem_do2[fml_depth-cache_depth-1:0];
always @(posedge sys_clk)
fml_adr <= {do_tag, index, offset};
/*
* DATA MEMORY
*
* Addressed by index+offset in 64-bit words (length cache_depth-3)
* 64-bit memory with 8-bit write granularity
*/
wire [cache_depth-3-1:0] datamem_a;
wire [7:0] datamem_we;
reg [63:0] datamem_di;
wire [63:0] datamem_do;
wire [cache_depth-3-1:0] datamem_a2;
wire [63:0] datamem_do2;
fmlbrg_datamem #(
.depth(cache_depth-3)
) datamem (
.sys_clk(sys_clk),
.a(datamem_a),
.we(datamem_we),
.di(datamem_di),
.do(datamem_do),
.a2(datamem_a2),
.do2(datamem_do2)
);
reg [1:0] bcounter;
reg [1:0] bcounter_next;
always @(posedge sys_clk) begin
if(sys_rst)
bcounter <= 2'd0;
else begin
bcounter <= bcounter_next;
end
end
reg bcounter_load;
reg bcounter_en;
always @(*) begin
if(bcounter_load)
bcounter_next <= offset[4:3];
else if(bcounter_en)
bcounter_next <= bcounter + 2'd1;
else
bcounter_next <= bcounter;
end
assign datamem_a = { index_load ? index : index_r, bcounter_next };
assign datamem_a2 = {dcb_index, dcb_offset[4:3]};
reg datamem_we_wb;
reg datamem_we_fml;
assign datamem_we = ({8{datamem_we_fml}} & 8'hff)
|({8{datamem_we_wb & wb_adr_i[2]}} & {4'h0, wb_sel_i})
|({8{datamem_we_wb & ~wb_adr_i[2]}} & {wb_sel_i, 4'h0});
always @(*) begin
datamem_di = fml_di;
if(datamem_we_wb) begin
if(wb_adr_i[2]) begin
/* lower 32-bit word */
if(wb_sel_i[0])
datamem_di[7:0] = wb_dat_i[7:0];
if(wb_sel_i[1])
datamem_di[15:8] = wb_dat_i[15:8];
if(wb_sel_i[2])
datamem_di[23:16] = wb_dat_i[23:16];
if(wb_sel_i[3])
datamem_di[31:24] = wb_dat_i[31:24];
end else begin
/* upper 32-bit word */
if(wb_sel_i[0])
datamem_di[39:32] = wb_dat_i[7:0];
if(wb_sel_i[1])
datamem_di[47:40] = wb_dat_i[15:8];
if(wb_sel_i[2])
datamem_di[55:48] = wb_dat_i[23:16];
if(wb_sel_i[3])
datamem_di[63:56] = wb_dat_i[31:24];
end
end
end
assign wb_dat_o = wb_adr_i[2] ? datamem_do[31:0] : datamem_do[63:32];
assign fml_do = datamem_do;
assign fml_sel = 8'hff;
assign dcb_dat = datamem_do2;
/* FSM */
reg [fml_depth-cache_depth-1:0] tag_r;
always @(posedge sys_clk)
tag_r = tag;
assign cache_hit = do_valid & (do_tag == tag_r);
reg [3:0] state;
reg [3:0] next_state;
parameter IDLE = 4'd0;
parameter TEST_HIT = 4'd1;
parameter WRITE_HIT = 4'd2;
parameter EVICT = 4'd3;
parameter EVICT2 = 4'd4;
parameter EVICT3 = 4'd5;
parameter EVICT4 = 4'd6;
parameter REFILL = 4'd7;
parameter REFILL_WAIT = 4'd8;
parameter REFILL1 = 4'd9;
parameter REFILL2 = 4'd10;
parameter REFILL3 = 4'd11;
parameter REFILL4 = 4'd12;
parameter TEST_INVALIDATE = 4'd13;
parameter INVALIDATE = 4'd14;
always @(posedge sys_clk) begin
if(sys_rst)
state = IDLE;
else begin
//$display("state: %d -> %d", state, next_state);
state = next_state;
end
end
always @(*) begin
tagmem_we = 1'b0;
di_valid = 1'b0;
di_dirty = 1'b0;
bcounter_load = 1'b0;
bcounter_en = 1'b0;
index_load = 1'b1;
datamem_we_wb = 1'b0;
datamem_we_fml = 1'b0;
wb_ack_o = 1'b0;
fml_stb = 1'b0;
fml_we = 1'b0;
next_state = state;
case(state)
IDLE: begin
bcounter_load = 1'b1;
if(wb_cyc_i & wb_stb_i) begin
if(wb_adr_i[invalidate_bit])
next_state = TEST_INVALIDATE;
else
next_state = TEST_HIT;
end
end
TEST_HIT: begin
if(cache_hit) begin
if(wb_we_i) begin
next_state = WRITE_HIT;
end else begin
wb_ack_o = 1'b1;
next_state = IDLE;
end
end else begin
if(do_dirty)
next_state = EVICT;
else
next_state = REFILL;
end
end
WRITE_HIT: begin
di_valid = 1'b1;
di_dirty = 1'b1;
tagmem_we = 1'b1;
datamem_we_wb = 1'b1;
wb_ack_o = 1'b1;
next_state = IDLE;
end
/*
* Burst counter has already been loaded.
* Yes, we evict lines in different order depending
* on the critical word position of the cache miss
* inside the line, but who cares :)
*/
EVICT: begin
fml_stb = 1'b1;
fml_we = 1'b1;
if(fml_ack) begin
bcounter_en = 1'b1;
next_state = EVICT2;
end
end
EVICT2: begin
bcounter_en = 1'b1;
next_state = EVICT3;
end
EVICT3: begin
bcounter_en = 1'b1;
next_state = EVICT4;
end
EVICT4: begin
bcounter_en = 1'b1;
if(wb_adr_i[invalidate_bit])
next_state = INVALIDATE;
else
next_state = REFILL;
end
REFILL: begin
/* Write the tag first. This will also set the FML address. */
di_valid = 1'b1;
if(wb_we_i)
di_dirty = 1'b1;
else
di_dirty = 1'b0;
if(~(dcb_stb & coincidence)) begin
tagmem_we = 1'b1;
next_state = REFILL_WAIT;
end
end
REFILL_WAIT: next_state = REFILL1; /* one cycle latency for the FML address */
REFILL1: begin
bcounter_load = 1'b1;
fml_stb = 1'b1;
/* Asserting both
* datamem_we_fml and
* datamem_we_wb write the 64-bit word from FML
* with a 32-bit (at most) overlay from WB
*/
datamem_we_fml = 1'b1;
if(wb_we_i)
datamem_we_wb = 1'b1;
if(fml_ack)
next_state = REFILL2;
end
REFILL2: begin
/*
* For reads, the critical word has just been written to the datamem
* so by acking the cycle now we get the correct result (because the
* datamem is a write-first SRAM).
* For writes, we could have acked the cycle before but it's simpler this way.
* Otherwise, we have the case of a master releasing WE just after ACK,
* and we must add a reg to tell whether we have a read or a write in REFILL2...
*/
wb_ack_o = 1'b1;
/* Now we must use our copy of index, as the WISHBONE
* address may change.
*/
index_load = 1'b0;
datamem_we_fml = 1'b1;
bcounter_en = 1'b1;
next_state = REFILL3;
end
REFILL3: begin
index_load = 1'b0;
datamem_we_fml = 1'b1;
bcounter_en = 1'b1;
next_state = REFILL4;
end
REFILL4: begin
index_load = 1'b0;
datamem_we_fml = 1'b1;
bcounter_en = 1'b1;
next_state = IDLE;
end
TEST_INVALIDATE: begin
if(do_dirty)
next_state = EVICT;
else
next_state = INVALIDATE;
end
INVALIDATE: begin
di_valid = 1'b0;
di_dirty = 1'b0;
tagmem_we = 1'b1;
wb_ack_o = 1'b1;
next_state = IDLE;
end
endcase
end
/* Do not hit on a line being refilled */
reg dcb_can_hit;
always @(posedge sys_clk) begin
dcb_can_hit <= 1'b0;
if(dcb_stb) begin
if((state != REFILL_WAIT)
|| (state != REFILL2)
|| (state != REFILL3)
|| (state != REFILL4))
dcb_can_hit <= 1'b1;
if(~coincidence)
dcb_can_hit <= 1'b1;
end
end
reg [fml_depth-cache_depth-1:0] dcb_tag_r;
always @(posedge sys_clk)
dcb_tag_r = dcb_tag;
assign dcb_hit = dcb_can_hit & do2_valid & (do2_tag == dcb_tag_r);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_4_V
`define SKY130_FD_SC_LP__CLKBUFLP_4_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Verilog wrapper for clkbuflp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuflp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuflp_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkbuflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuflp_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkbuflp base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_4_V
|
//wbs_spi.v
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000000
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_spi
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x05
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:12
*/
`include "project_defines.v"
`include "spi_defines.v"
`include "timescale.v"
`unconnected_drive pull0
module wb_spi #(
parameter SPI_CHAR_LEN_BITS = 8
)(
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
// SPI signals
output [31:0] ss_pad_o, // slave select
//output ss_pad_o, // slave select
output sclk_pad_o, // serial clock
output mosi_pad_o, // master out slave in
input miso_pad_i // master in slave out
);
localparam SPI_MAX_CHAR = 2 ** SPI_CHAR_LEN_BITS;
localparam SPI_MAX_REG_SIZE = SPI_MAX_CHAR / 32;
//parameters
localparam SPI_CTRL = 0;
localparam SPI_CLOCK_RATE = 1;
localparam SPI_DIVIDER = 2;
localparam SPI_SS = 3;
localparam SPI_BIT_COUNT = 4;
localparam SPI_MAX_BITSIZE = 5;
localparam SPI_RX_DATA = 6;
localparam SPI_TX_DATA = ((SPI_RX_DATA) + (SPI_MAX_REG_SIZE));
//Registers/Wires
reg [31:0] divider = 100; // Divider register
reg [31:0] ctrl = 0; // Control and status register
reg [31:0] ss = 0; // Slave select register
//reg ss = 0; // Slave select register
reg [31:0] char_len= 8; // char len
wire [SPI_MAX_CHAR - 1:0] rx_data; // Rx register
wire [SPI_MAX_CHAR - 1:0] tx_data;
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire inv_clk; // invert clock
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
wire sclk;
wire [31:0] read_reg_pos;
wire [31:0] write_reg_pos;
reg [31:0] tx_data_array [(SPI_MAX_REG_SIZE - 1):0];
wire [31:0] rx_data_array [(SPI_MAX_REG_SIZE - 1):0];
integer i;
//Submodules
spi_clkgen clgen (
.clk_in (clk ),
.rst (rst ),
.go (go ),
.enable (tip ),
.last_clk (last_bit ),
.divider (divider ),
.clk_out (sclk ),
.pos_edge (pos_edge ),
.neg_edge (neg_edge )
);
spi_shift #(
.SPI_CHAR_LEN_BITS (SPI_CHAR_LEN_BITS )
) shift (
.clk (clk ),
.rst (rst ),
.len (char_len ),
.lsb (lsb ),
.go (go ),
.pos_edge (pos_edge ),
.neg_edge (neg_edge ),
.rx_negedge (rx_negedge ),
.tx_negedge (tx_negedge ),
.tip (tip ),
.last (last_bit ),
.s_clk (sclk ),
.s_in (miso_pad_i ),
.s_out (mosi_pad_o ),
.mosi_data (tx_data ),
.miso_data (rx_data )
);
//Asynchronous Logic
genvar gv;
generate
for (gv = 0; gv < SPI_MAX_REG_SIZE; gv = gv + 1) begin : wb_spi_init
assign tx_data[((gv << 5) + 31): (gv << 5)] = tx_data_array[(SPI_MAX_REG_SIZE - 1) - gv];
assign rx_data_array[(SPI_MAX_REG_SIZE - 1) - gv] = rx_data[(gv << 5) + 31: (gv << 5)];
end
endgenerate
// Address decoder
assign read_reg_valid = ((i_wbs_adr >= SPI_RX_DATA) && (i_wbs_adr < SPI_TX_DATA));
assign read_reg_pos = read_reg_valid ? (i_wbs_adr - SPI_RX_DATA): 0;
assign write_reg_valid = (i_wbs_adr >= SPI_TX_DATA) && (i_wbs_adr < (SPI_TX_DATA + (SPI_MAX_REG_SIZE)));
assign write_reg_pos = write_reg_valid ? (i_wbs_adr - SPI_TX_DATA): 0;
assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
assign go = ctrl[`SPI_CTRL_GO];
assign lsb = ctrl[`SPI_CTRL_LSB];
assign ie = ctrl[`SPI_CTRL_IE];
assign ass = ctrl[`SPI_CTRL_ASS];
assign inv_clk = ctrl[`SPI_CTRL_INV_CLK];
assign ss_pad_o = ~((ss & {32{tip & ass}}) | (ss & {32{!ass}}));
//assign ss_pad_o = ~((ss & tip & ass) | (ss & !ass));
//assign ss_pad_o = !ss;
assign sclk_pad_o = inv_clk ? ~sclk : sclk;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h00000000;
o_wbs_ack <= 0;
char_len <= 0;
ctrl <= 0;
divider <= 100;
ss <= 0;
for (i = 0; i < SPI_MAX_REG_SIZE; i = i + 1) begin
tx_data_array[i] <= i;
end
end
else begin
//interrupts
if (ie && tip && last_bit && pos_edge) begin
o_wbs_int <= 1;
end
else if (o_wbs_ack) begin
o_wbs_int <= 0;
end
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (go && last_bit && pos_edge) begin
ctrl[`SPI_CTRL_GO] <= 0;
end
if (i_wbs_stb & i_wbs_cyc & !o_wbs_ack) begin
//master is requesting somethign
if (i_wbs_we && !tip) begin
//write request
case (i_wbs_adr)
SPI_CTRL: begin
ctrl <= i_wbs_dat;
end
SPI_BIT_COUNT: begin
char_len <= i_wbs_dat;
end
SPI_DIVIDER: begin
divider <= i_wbs_dat;
end
SPI_SS: begin
//ss <= i_wbs_dat[0];
ss <= i_wbs_dat;
end
default: begin
end
endcase
if (write_reg_valid) begin
tx_data_array[write_reg_pos] <= i_wbs_dat;
end
end
else begin
//read request
case (i_wbs_adr)
SPI_CTRL: begin
o_wbs_dat <= ctrl;
end
SPI_BIT_COUNT: begin
o_wbs_dat <= char_len;
end
SPI_DIVIDER: begin
o_wbs_dat <= divider;
end
SPI_SS: begin
//o_wbs_dat <= {31'h0, ss};
o_wbs_dat <= ss;
end
SPI_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
SPI_MAX_BITSIZE: begin
o_wbs_dat <= SPI_MAX_CHAR;
end
default: begin
o_wbs_dat <= 32'bx;
end
endcase
if (read_reg_valid) begin
o_wbs_dat <= rx_data_array[read_reg_pos];
end
end
o_wbs_ack <= 1;
end
end
end
endmodule
|
// Part of NewGS project
//
// FPGA early and on-the-fly configuration, Z80 clock switch
//
// (c) 2008 NedoPC
module GS_3032(
config_n, // ACEX1K config pins
status_n, //
conf_done, //
cs, //
init_done, //
clk24in, // 24mhz in
clk20in, // 20mhz in
clkout, // clock out
clksel0, // clock select 0 (1=divide by 2, 0=no divide)
clksel1, // clock select 1 (1=clk20in, 0=clk24in)
a6,a7,a14,a15, // z80 signals
iorq_n,mreq_n, //
rd_n,wr_n, //
d7,d0, //
mema14,mema15, // signals to memories
romcs_n,ramcs0_n,
memoe_n,memwe_n,
coldres_n, // cold reset input
warmres_n, // warm reset output
clkin // input of clkout signal
);
output config_n; reg config_n;
input status_n;
input conf_done;
output cs; reg cs;
input init_done;
input clk24in;
input clk20in;
output clkout; reg clkout;
input clksel0,clksel1;
input a6,a7,a14,a15;
input iorq_n,mreq_n,rd_n,wr_n;
inout d7,d0; reg d7,d0;
output mema14,mema15; reg mema14,mema15;
output romcs_n,ramcs0_n; reg romcs_n,ramcs0_n;
output memoe_n,memwe_n; reg memoe_n,memwe_n;
input coldres_n;
output warmres_n; reg warmres_n;
input clkin;
reg int_mema14,int_mema15;
reg int_romcs_n,int_ramcs0_n;
reg int_memoe_n,int_memwe_n;
reg int_cs;
reg [1:0] memcfg; // memcfg[1]: 1 ram, 0 roms
// memcfg[0]: 0 page0, 1 page1 -> in 8000-ffff region
reg disbl; // =1 - 3032 disabled, =0 - enabled
reg was_cold_reset_n; // 1 - no cold reset, 0 - was cold reset
reg [1:0] dbout;
wire [1:0] dbin;
assign dbin[1] = d7;
assign dbin[0] = d0;
wire memcfg_write;
wire rescfg_write;
wire coldrstf_read;
wire fpgastat_read;
reg [3:0] rstcount; // counter for warm reset period
reg [2:0] disbl_sync;
// PORTS:
// {a7,a6}
// 00 - fpga ports
// 01,WR - write memcfg: d7=RAM(1)/ROM(0), d0=32k page(0/1)
// 01,RD - read cold_reset_n flag: d7=(0:was cold reset,1:no cold reset)
// 10,WR - set cold_reset_n flag & write FPGA nCONFIG: d7=1: set cold_reset_n flag, d0: nCONFIG
// 10,RD - read FPGA status: d7=nSTATUS, d0=CONF_DONE
// 11,WR - write to FPGA
// 11,RD - read from FPGA
// clock selector
clocker clk( .clk1(clk24in),
.clk2(clk20in),
.clksel(clksel1),
.divsel(clksel0),
.clkout(clkout) );
// disable control
always @(negedge config_n,posedge init_done)
begin
if( config_n==0 ) // asynchronous reset
disbl <= 0;
else // posedge of init_done, synchronous set
disbl <= 1;
end
// enabling memory control pins on request
always @*
begin
if( disbl==0 )
begin
mema14 <= int_mema14;
mema15 <= int_mema15;
romcs_n <= int_romcs_n;
ramcs0_n <= int_ramcs0_n;
memoe_n <= int_memoe_n;
memwe_n <= int_memwe_n;
cs <= int_cs;
end
else // disbl==1
begin
mema14 <= 1'bZ;
mema15 <= 1'bZ;
romcs_n <= 1'bZ;
ramcs0_n <= 1'bZ;
memoe_n <= 1'bZ;
memwe_n <= 1'bZ;
cs <= 1'bZ;
end
end
// controlling memory paging
always @*
begin
casex( {a15,a14,memcfg[1]} )
3'b00x:
{int_mema15,int_mema14,int_romcs_n,int_ramcs0_n} <= 4'b0001;
3'b01x:
{int_mema15,int_mema14,int_romcs_n,int_ramcs0_n} <= 4'b0010;
3'b1x0:
{int_mema15,int_mema14,int_romcs_n,int_ramcs0_n} <= {memcfg[0],a14,2'b01};
3'b1x1:
{int_mema15,int_mema14,int_romcs_n,int_ramcs0_n} <= {memcfg[0],a14,2'b10};
endcase
end
// controlling memory /OE, /WE
always @*
begin
int_memoe_n <= mreq_n | rd_n;
int_memwe_n <= mreq_n | wr_n;
end
// writing paging register [1:0] memcfg
assign memcfg_write = iorq_n | wr_n | a7 | ~a6; // {a7,a6}==01
always @(negedge coldres_n, posedge memcfg_write)
begin
if( coldres_n==0 ) // reset on coldres_n
memcfg <= 2'b00;
else // write on memcfg_write
memcfg <= dbin;
end
// writing nCONFIG and cold reset "register"
assign rescfg_write = iorq_n | wr_n | ~a7 | a6; // {a7,a6}==10
always @(negedge coldres_n, posedge rescfg_write)
begin
if( coldres_n==0 ) // async reset
begin
was_cold_reset_n <= 0; // there was!
config_n <= 0; // start FPGA config
end
else // sync set/load
begin
config_n <= dbin[0];
was_cold_reset_n <= dbin[1] | was_cold_reset_n;
end
end
// controlling positive CS pin to FPGA
always @*
begin
int_cs <= a7 & a6; // {a7,a6}==11
end
// reading control
assign coldrstf_read = iorq_n | rd_n | a7 | ~a6; // {a7,a6}=01
assign fpgastat_read = iorq_n | rd_n | ~a7 | a6; // {a7,a6}=10
always @*
begin
if( (coldrstf_read & fpgastat_read)==0 )
begin
d7 <= dbout[1];
d0 <= dbout[0];
end
else
begin
d7 <= 1'bZ;
d0 <= 1'bZ;
end
end
always @*
begin
casex( {coldrstf_read,fpgastat_read} )
2'b01:
dbout <= { was_cold_reset_n, 1'bX };
2'b10:
dbout <= { status_n, conf_done };
default:
dbout <= 2'bXX;
endcase
end
// warm resetter control
always @(posedge clkin)
begin
disbl_sync[2:0]={disbl_sync[1:0],disbl};
end
always @(negedge coldres_n,posedge clkin)
begin
if( coldres_n==0 ) // async reset
begin
rstcount <= (-1);
warmres_n <= 0;
end
else // posedge clkin
begin
if( disbl_sync[2]==0 && disbl_sync[1]==1 ) // positive pulse
begin
warmres_n <= 0;
rstcount <= (-1);
end
else // no disbl_sync positive pulse
begin
rstcount <= rstcount - 1;
if( |rstcount == 0 )
warmres_n <= 1'bZ;
end
end
end
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.28.12:23:35
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_6"),
.ENUM_MEM_IF_TFAW ("TFAW_12"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_4"),
.ENUM_MEM_IF_TRTP ("TRTP_4"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (104),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_TB_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_TB_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s15.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__clkdlybuf4s15 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_TB_V
|
/*
* Titor - System - PS/2 controller wrapper
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_PS2_WRAPPER
`else
`define INC_PS2_WRAPPER
`timescale 1 ns / 100 ps
module PS2(
ps2_clock,
ps2_data,
rx_data,
rx_done,
reset,
clk
);
`include "definition/Definition.v"
inout ps2_clock;
inout ps2_data;
output reg [BYTE-1:0] rx_data;
output reg rx_done;
input reset;
input clk;
localparam BITTHROUGH = 10; // the number of bits to accept including Parity and Stop
localparam STATE_IDLE = 32'd1,
STATE_RX_BIT = 32'd2;
wire devclk;
wire devclkneg;
wire [WORD-1:0] bitcount;
wire bitarc;
reg [WORD-1:0] state;
reg [BITTHROUGH-1:0] shift_in;
reg postbitarc;
reg [BYTE-1:0] clkbuf;
// Clock line conditioning
Debounce #(1*MICROS) stable (
.linein(ps2_clock),
.lineout(devclk),
.reset(reset),
.clk(clk)
);
Negedge tick (
.linein(devclk),
.lineout(devclkneg),
.reset(reset),
.clk(clk)
);
// Bit counting
Radix_Counter #(BITTHROUGH) countoff (
.carry_in((state==STATE_RX_BIT) && devclkneg),
.carry_out(bitarc),
.count(bitcount),
.reset(reset),
.clk(clk)
);
// Finite State Machine
always @(posedge clk) begin
if(reset) state <= STATE_IDLE;
else if((state==STATE_IDLE) && devclkneg) state <= STATE_RX_BIT;
else if((state==STATE_RX_BIT) && bitarc) state <= STATE_IDLE;
else state <= state;
end
// Data capture
always @(posedge clk) begin
if(reset) shift_in <= 0;
else if(devclkneg) shift_in <= {ps2_data, shift_in[BITTHROUGH-1:1]};
else shift_in <= shift_in;
if(reset) postbitarc <= 0;
else postbitarc <= bitarc;
if(reset) rx_data <= 0;
else if(postbitarc) rx_data <= shift_in;
else rx_data <= rx_data;
end
always @(posedge clk) begin
if(reset) rx_done <= 0;
else if(postbitarc) rx_done <= 1;
else rx_done <= 0;
end
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_l2t.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Local header file includes / local define
// The sctag_pcx*** signals need to be appropriately bound in the
// instantiation made in sctag.v
////////////////////////////////////////////////////////////////////////
module bw_r_l2t( /*AUTOARG*/
// Outputs
so, l2t_fuse_repair_value, l2t_fuse_repair_en, way_sel, way_sel_1,
tag_way0, tag_way1, tag_way2, tag_way3, tag_way4, tag_way5,
tag_way6, tag_way7, tag_way8, tag_way9, tag_way10, tag_way11,
// Inputs
index, bist_index, rd_en, bist_rd_en, way, bist_way, wr_en,
bist_wr_en, wrdata0, bist_wrdata0, wrdata1, bist_wrdata1,
lkup_tag_d1, rclk, fuse_l2t_wren, fuse_l2t_rid,
fuse_l2t_repair_value, fuse_l2t_repair_en, efc_sctag_fuse_clk1,
rst_tri_en, si, se, arst_l, sehold
);
// select xbar
input [9:0] index ; // from addrdp
input [9:0] bist_index ; // BIST INPUT
input rd_en ; // enable from arbctl is speculatively asserted.
input bist_rd_en ; // BIST INPUT
input [11:0] way; // way for a fill/tag write
input [11:0] bist_way;// BIST INPUT
input wr_en; // on a fill in px2 or a diag/tecc write.
input bist_wr_en ; // BIST INPUT
input [27:0] wrdata0 ; // wr tag
input [7:0] bist_wrdata0 ; // wr tag
input [27:0] wrdata1 ; // wr tag
input [7:0] bist_wrdata1 ; // wr tag
input [27:1] lkup_tag_d1 ; //ecc bits are appended to this tag.
input rclk;
// input [3:0] tag_stm ; ?? may not be needed.
input fuse_l2t_wren; //redundancy reg wr enable, qualified
input [5:0] fuse_l2t_rid; //redundancy register id <5:2> == subbank, <1:0> determines row/col red.
input [6:0] fuse_l2t_repair_value; //data in for redundancy register
input [1:0] fuse_l2t_repair_en; //enable bits to turn on redundancy
input efc_sctag_fuse_clk1;
input rst_tri_en;
input si, se;
output so;
input arst_l;
input sehold;
output [6:0] l2t_fuse_repair_value; //data out for redundancy register
output [1:0] l2t_fuse_repair_en; //enable bits out
output [11:0] way_sel; // compare outputs
output [11:0] way_sel_1; // compare outputs
output [27:0] tag_way0;
output [27:0] tag_way1;
output [27:0] tag_way2;
output [27:0] tag_way3;
output [27:0] tag_way4;
output [27:0] tag_way5;
output [27:0] tag_way6;
output [27:0] tag_way7;
output [27:0] tag_way8;
output [27:0] tag_way9;
output [27:0] tag_way10;
output [27:0] tag_way11;
reg [27:0] wrdata0_d1_l, wrdata1_d1_l ;
wire [11:0] gbl_red_bank_id;
reg [6:0] l2t_fuse_repair_value;
reg [1:0] l2t_fuse_repair_en;
wire [6:0] red_reg_q_ab, red_reg_q_89, red_reg_q_67, red_reg_q_45 ;
wire [6:0] red_reg_q_01, red_reg_q_23;
wire [1:0] red_reg_enq_ab, red_reg_enq_89, red_reg_enq_67, red_reg_enq_45 ;
wire [1:0] red_reg_enq_01, red_reg_enq_23;
wire [5:0] wr_en_subbank;
wire [27:0] tag_wrdata0_px2, tag_wrdata1_px2 ;
assign tag_wrdata0_px2 = ( bist_wr_en ) ? { bist_wrdata0[3:0],
{3{bist_wrdata0[7:0]}} } : wrdata0;
assign tag_wrdata1_px2 = ( bist_wr_en ) ? { bist_wrdata1[3:0],
{3{bist_wrdata1[7:0]}} } : wrdata1;
// Inputs that are flopped
always @(posedge rclk) begin
wrdata0_d1_l <= (sehold)? wrdata0_d1_l: ~tag_wrdata0_px2 ;
wrdata1_d1_l <= (sehold)? wrdata1_d1_l: ~tag_wrdata1_px2 ;
`ifdef INNO_MUXEX
`else
//----- PURELY FOR VERIFICATION -----------------------
if(wr_en) begin
case(way)
12'b000000000001: ;
12'b000000000010: ;
12'b000000000100: ;
12'b000000001000: ;
12'b000000010000: ;
12'b000000100000: ;
12'b000001000000: ;
12'b000010000000: ;
12'b000100000000: ;
12'b001000000000: ;
12'b010000000000: ;
12'b100000000000: ;
default:
`ifdef MODELSIM
$display("L2_TAG_ERR"," way select error %h ", way[11:0]);
`else
$error("L2_TAG_ERR"," way select error %h ", way[11:0]);
`endif
endcase
end // of if
//----- PURELY FOR VERIFICATION -----------------------
`endif
end
assign way_sel_1 = way_sel ;
assign gbl_red_bank_id[0] = ( fuse_l2t_rid[5:2] == 4'd0) ;
assign gbl_red_bank_id[1] = ( fuse_l2t_rid[5:2] == 4'd1) ;
assign gbl_red_bank_id[2] = ( fuse_l2t_rid[5:2] == 4'd2) ;
assign gbl_red_bank_id[3] = ( fuse_l2t_rid[5:2] == 4'd3) ;
assign gbl_red_bank_id[4] = ( fuse_l2t_rid[5:2] == 4'd4) ;
assign gbl_red_bank_id[5] = ( fuse_l2t_rid[5:2] == 4'd5) ;
assign gbl_red_bank_id[6] = ( fuse_l2t_rid[5:2] == 4'd6) ;
assign gbl_red_bank_id[7] = ( fuse_l2t_rid[5:2] == 4'd7) ;
assign gbl_red_bank_id[8] = ( fuse_l2t_rid[5:2] == 4'd8) ;
assign gbl_red_bank_id[9] = ( fuse_l2t_rid[5:2] == 4'd9) ;
assign gbl_red_bank_id[10] = ( fuse_l2t_rid[5:2] == 4'd10) ;
assign gbl_red_bank_id[11] = ( fuse_l2t_rid[5:2] == 4'd11) ;
//assign wr_en_subbank[0] = fuse_l2t_wren & ( |(gbl_red_bank_id[1:0]) );
//assign wr_en_subbank[1] = fuse_l2t_wren & ( |(gbl_red_bank_id[5:4]) );
//assign wr_en_subbank[2] = fuse_l2t_wren & ( |(gbl_red_bank_id[9:8]) );
//assign wr_en_subbank[3] = fuse_l2t_wren & ( |(gbl_red_bank_id[3:2]) );
//assign wr_en_subbank[4] = fuse_l2t_wren & ( |(gbl_red_bank_id[7:6]) );
//assign wr_en_subbank[5] = fuse_l2t_wren & ( |(gbl_red_bank_id[11:10]) );
// JC modified begin
// Write enable signal goes directly to subbank without any gating circuits.
assign wr_en_subbank[0] = fuse_l2t_wren;
assign wr_en_subbank[1] = fuse_l2t_wren;
assign wr_en_subbank[2] = fuse_l2t_wren;
assign wr_en_subbank[3] = fuse_l2t_wren;
assign wr_en_subbank[4] = fuse_l2t_wren;
assign wr_en_subbank[5] = fuse_l2t_wren;
// JC modified begin
always @(/*AUTOSENSE*/gbl_red_bank_id or red_reg_enq_01
or red_reg_enq_23 or red_reg_enq_45 or red_reg_enq_67
or red_reg_enq_89 or red_reg_enq_ab or red_reg_q_01
or red_reg_q_23 or red_reg_q_45 or red_reg_q_67
or red_reg_q_89 or red_reg_q_ab)begin
case(gbl_red_bank_id)
12'b000000000001: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_01[1:0], red_reg_q_01[6:0] } ;
end
12'b000000000010: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_01[1:0], red_reg_q_01[6:0] } ;
end
12'b000000000100: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_23[1:0], red_reg_q_23[6:0] } ;
end
12'b000000001000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_23[1:0], red_reg_q_23[6:0] } ;
end
12'b000000010000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_45[1:0], red_reg_q_45[6:0] } ;
end
12'b000000100000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_45[1:0], red_reg_q_45[6:0] } ;
end
12'b000001000000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_67[1:0], red_reg_q_67[6:0] } ;
end
12'b000010000000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_67[1:0], red_reg_q_67[6:0] } ;
end
12'b000100000000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_89[1:0], red_reg_q_89[6:0] } ;
end
12'b001000000000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_89[1:0], red_reg_q_89[6:0] } ;
end
12'b010000000000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_ab[1:0], red_reg_q_ab[6:0] } ;
end
12'b100000000000: begin
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
{ red_reg_enq_ab[1:0], red_reg_q_ab[6:0] } ;
end
default: begin
// JC added begin
// remove implicit latch.
{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} = 9'b0;
// JCadded end
end
endcase
end
/* bw_r_l2t_subbank AUTO_TEMPLATE (
// Outputs
.wayselect0 (way_sel[0]),
.wayselect1 (way_sel[1]),
.tag_way0 (tag_way0[27:0]),
.tag_way1 (tag_way1[27:0]),
.red_reg_q_array2(red_reg_q_01[6:0]),
.red_reg_enq_array2(red_reg_enq_01[1:0]),
// Inputs
.way (way[1:0]),
.bist_way (bist_way[1:0]),
.wd_b_l (wrdata0_d1_l[27:0]),
.lkuptag (lkup_tag_d1[27:1]),
.rclk (rclk),
.sehold (sehold),
.se (se),
.sin (),
.sout (),
.rst_tri_en (rst_tri_en),
.arst_l (arst_l),
.gbl_red_rid(fuse_l2t_rid[1:0]),
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
.fclk1 (efc_sctag_fuse_clk1),
.gbl_red_bank_id_top(gbl_red_bank_id[0]),
.gbl_red_bank_id_bottom(gbl_red_bank_id[1]),
.gbl_red_wr_en(wr_en_subbank[0]));
*/
bw_r_l2t_subbank subbank01(/*AUTOINST*/
// Outputs
.sout (), // Templated
.wayselect0(way_sel[0]), // Templated
.wayselect1(way_sel[1]), // Templated
.tag_way0 (tag_way0[27:0]), // Templated
.tag_way1 (tag_way1[27:0]), // Templated
.red_reg_q_array2(red_reg_q_01[6:0]), // Templated
.red_reg_enq_array2(red_reg_enq_01[1:0]), // Templated
// Inputs
.index (index[9:0]),
.bist_index(bist_index[9:0]),
.wr_en (wr_en),
.bist_wr_en(bist_wr_en),
.rd_en (rd_en),
.bist_rd_en(bist_rd_en),
.way (way[1:0]), // Templated
.bist_way (bist_way[1:0]), // Templated
.wd_b_l (wrdata0_d1_l[27:0]), // Templated
.lkuptag (lkup_tag_d1[27:1]), // Templated
.rclk (rclk), // Templated
.sehold (sehold), // Templated
.se (se), // Templated
.sin (), // Templated
.rst_tri_en(rst_tri_en), // Templated
.arst_l (arst_l), // Templated
.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
.fclk1 (efc_sctag_fuse_clk1), // Templated
.gbl_red_bank_id_top(gbl_red_bank_id[0]), // Templated
.gbl_red_bank_id_bottom(gbl_red_bank_id[1]), // Templated
.gbl_red_wr_en(wr_en_subbank[0])); // Templated
/* bw_r_l2t_subbank AUTO_TEMPLATE (
// Outputs
.wayselect0 (way_sel[4]),
.wayselect1 (way_sel[5]),
.tag_way0 (tag_way4[27:0]),
.tag_way1 (tag_way5[27:0]),
.red_reg_q_array2(red_reg_q_45[6:0]),
.red_reg_enq_array2(red_reg_enq_45[1:0]),
// Inputs
.way (way[5:4]),
.bist_way (bist_way[5:4]),
.wd_b_l (wrdata0_d1_l[27:0]),
.lkuptag (lkup_tag_d1[27:1]),
.rclk (rclk),
.sehold (sehold),
.se (se),
.sin (),
.sout (),
.rst_tri_en (rst_tri_en),
.arst_l (arst_l),
.gbl_red_rid(fuse_l2t_rid[1:0]),
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
.fclk1 (efc_sctag_fuse_clk1),
.gbl_red_bank_id_top(gbl_red_bank_id[4]),
.gbl_red_bank_id_bottom(gbl_red_bank_id[5]),
.gbl_red_wr_en(wr_en_subbank[1]));
*/
bw_r_l2t_subbank subbank45(/*AUTOINST*/
// Outputs
.sout (), // Templated
.wayselect0(way_sel[4]), // Templated
.wayselect1(way_sel[5]), // Templated
.tag_way0 (tag_way4[27:0]), // Templated
.tag_way1 (tag_way5[27:0]), // Templated
.red_reg_q_array2(red_reg_q_45[6:0]), // Templated
.red_reg_enq_array2(red_reg_enq_45[1:0]), // Templated
// Inputs
.index (index[9:0]),
.bist_index(bist_index[9:0]),
.wr_en (wr_en),
.bist_wr_en(bist_wr_en),
.rd_en (rd_en),
.bist_rd_en(bist_rd_en),
.way (way[5:4]), // Templated
.bist_way (bist_way[5:4]), // Templated
.wd_b_l (wrdata0_d1_l[27:0]), // Templated
.lkuptag (lkup_tag_d1[27:1]), // Templated
.rclk (rclk), // Templated
.sehold (sehold), // Templated
.se (se), // Templated
.sin (), // Templated
.rst_tri_en(rst_tri_en), // Templated
.arst_l (arst_l), // Templated
.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
.fclk1 (efc_sctag_fuse_clk1), // Templated
.gbl_red_bank_id_top(gbl_red_bank_id[4]), // Templated
.gbl_red_bank_id_bottom(gbl_red_bank_id[5]), // Templated
.gbl_red_wr_en(wr_en_subbank[1])); // Templated
/* bw_r_l2t_subbank AUTO_TEMPLATE (
// Outputs
.wayselect0 (way_sel[8]),
.wayselect1 (way_sel[9]),
.tag_way0 (tag_way8[27:0]),
.tag_way1 (tag_way9[27:0]),
.red_reg_q_array2(red_reg_q_89[6:0]),
.red_reg_enq_array2(red_reg_enq_89[1:0]),
// Inputs
.way (way[9:8]),
.bist_way (bist_way[9:8]),
.wd_b_l (wrdata0_d1_l[27:0]),
.lkuptag (lkup_tag_d1[27:1]),
.rclk (rclk),
.sehold (sehold),
.se (se),
.sin (),
.sout (),
.rst_tri_en (rst_tri_en),
.arst_l (arst_l),
.gbl_red_rid(fuse_l2t_rid[1:0]),
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
.fclk1 (efc_sctag_fuse_clk1),
.gbl_red_bank_id_top(gbl_red_bank_id[8]),
.gbl_red_bank_id_bottom(gbl_red_bank_id[9]),
.gbl_red_wr_en(wr_en_subbank[2]));
*/
bw_r_l2t_subbank subbank89(/*AUTOINST*/
// Outputs
.sout (), // Templated
.wayselect0(way_sel[8]), // Templated
.wayselect1(way_sel[9]), // Templated
.tag_way0 (tag_way8[27:0]), // Templated
.tag_way1 (tag_way9[27:0]), // Templated
.red_reg_q_array2(red_reg_q_89[6:0]), // Templated
.red_reg_enq_array2(red_reg_enq_89[1:0]), // Templated
// Inputs
.index (index[9:0]),
.bist_index(bist_index[9:0]),
.wr_en (wr_en),
.bist_wr_en(bist_wr_en),
.rd_en (rd_en),
.bist_rd_en(bist_rd_en),
.way (way[9:8]), // Templated
.bist_way (bist_way[9:8]), // Templated
.wd_b_l (wrdata0_d1_l[27:0]), // Templated
.lkuptag (lkup_tag_d1[27:1]), // Templated
.rclk (rclk), // Templated
.sehold (sehold), // Templated
.se (se), // Templated
.sin (), // Templated
.rst_tri_en(rst_tri_en), // Templated
.arst_l (arst_l), // Templated
.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
.fclk1 (efc_sctag_fuse_clk1), // Templated
.gbl_red_bank_id_top(gbl_red_bank_id[8]), // Templated
.gbl_red_bank_id_bottom(gbl_red_bank_id[9]), // Templated
.gbl_red_wr_en(wr_en_subbank[2])); // Templated
/* bw_r_l2t_subbank AUTO_TEMPLATE (
// Outputs
.wayselect0 (way_sel[2]),
.wayselect1 (way_sel[3]),
.tag_way0 (tag_way2[27:0]),
.tag_way1 (tag_way3[27:0]),
.red_reg_q_array2(red_reg_q_23[6:0]),
.red_reg_enq_array2(red_reg_enq_23[1:0]),
// Inputs
.way (way[3:2]),
.bist_way (bist_way[3:2]),
.wd_b_l (wrdata1_d1_l[27:0]),
.lkuptag (lkup_tag_d1[27:1]),
.rclk (rclk),
.sehold (sehold),
.se (se),
.sin (),
.sout (),
.rst_tri_en (rst_tri_en),
.arst_l (arst_l),
.gbl_red_rid(fuse_l2t_rid[1:0]),
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
.fclk1 (efc_sctag_fuse_clk1),
.gbl_red_bank_id_top(gbl_red_bank_id[2]),
.gbl_red_bank_id_bottom(gbl_red_bank_id[3]),
.gbl_red_wr_en(wr_en_subbank[3]));
*/
bw_r_l2t_subbank subbank23(/*AUTOINST*/
// Outputs
.sout (), // Templated
.wayselect0(way_sel[2]), // Templated
.wayselect1(way_sel[3]), // Templated
.tag_way0 (tag_way2[27:0]), // Templated
.tag_way1 (tag_way3[27:0]), // Templated
.red_reg_q_array2(red_reg_q_23[6:0]), // Templated
.red_reg_enq_array2(red_reg_enq_23[1:0]), // Templated
// Inputs
.index (index[9:0]),
.bist_index(bist_index[9:0]),
.wr_en (wr_en),
.bist_wr_en(bist_wr_en),
.rd_en (rd_en),
.bist_rd_en(bist_rd_en),
.way (way[3:2]), // Templated
.bist_way (bist_way[3:2]), // Templated
.wd_b_l (wrdata1_d1_l[27:0]), // Templated
.lkuptag (lkup_tag_d1[27:1]), // Templated
.rclk (rclk), // Templated
.sehold (sehold), // Templated
.se (se), // Templated
.sin (), // Templated
.rst_tri_en(rst_tri_en), // Templated
.arst_l (arst_l), // Templated
.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
.fclk1 (efc_sctag_fuse_clk1), // Templated
.gbl_red_bank_id_top(gbl_red_bank_id[2]), // Templated
.gbl_red_bank_id_bottom(gbl_red_bank_id[3]), // Templated
.gbl_red_wr_en(wr_en_subbank[3])); // Templated
/* bw_r_l2t_subbank AUTO_TEMPLATE (
// Outputs
.wayselect0 (way_sel[6]),
.wayselect1 (way_sel[7]),
.tag_way0 (tag_way6[27:0]),
.tag_way1 (tag_way7[27:0]),
.red_reg_q_array2(red_reg_q_67[6:0]),
.red_reg_enq_array2(red_reg_enq_67[1:0]),
// Inputs
.way (way[7:6]),
.bist_way (bist_way[7:6]),
.wd_b_l (wrdata1_d1_l[27:0]),
.lkuptag (lkup_tag_d1[27:1]),
.rclk (rclk),
.sehold (sehold),
.se (se),
.sin (),
.sout (),
.rst_tri_en (rst_tri_en),
.arst_l (arst_l),
.gbl_red_rid(fuse_l2t_rid[1:0]),
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
.fclk1 (efc_sctag_fuse_clk1),
.gbl_red_bank_id_top(gbl_red_bank_id[6]),
.gbl_red_bank_id_bottom(gbl_red_bank_id[7]),
.gbl_red_wr_en(wr_en_subbank[4]));
*/
bw_r_l2t_subbank subbank67(/*AUTOINST*/
// Outputs
.sout (), // Templated
.wayselect0(way_sel[6]), // Templated
.wayselect1(way_sel[7]), // Templated
.tag_way0(tag_way6[27:0]), // Templated
.tag_way1(tag_way7[27:0]), // Templated
.red_reg_q_array2(red_reg_q_67[6:0]), // Templated
.red_reg_enq_array2(red_reg_enq_67[1:0]), // Templated
// Inputs
.index(index[9:0]),
.bist_index(bist_index[9:0]),
.wr_en(wr_en),
.bist_wr_en(bist_wr_en),
.rd_en(rd_en),
.bist_rd_en(bist_rd_en),
.way (way[7:6]), // Templated
.bist_way(bist_way[7:6]), // Templated
.wd_b_l(wrdata1_d1_l[27:0]), // Templated
.lkuptag(lkup_tag_d1[27:1]), // Templated
.rclk (rclk), // Templated
.sehold(sehold), // Templated
.se (se), // Templated
.sin (), // Templated
.rst_tri_en(rst_tri_en), // Templated
.arst_l(arst_l), // Templated
.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
.fclk1(efc_sctag_fuse_clk1), // Templated
.gbl_red_bank_id_top(gbl_red_bank_id[6]), // Templated
.gbl_red_bank_id_bottom(gbl_red_bank_id[7]), // Templated
.gbl_red_wr_en(wr_en_subbank[4])); // Templated
/* bw_r_l2t_subbank AUTO_TEMPLATE (
// Outputs
.wayselect0 (way_sel[10]),
.wayselect1 (way_sel[11]),
.tag_way0 (tag_way10[27:0]),
.tag_way1 (tag_way11[27:0]),
.red_reg_q_array2(red_reg_q_ab[6:0]),
.red_reg_enq_array2(red_reg_enq_ab[1:0]),
// Inputs
.way (way[11:10]),
.bist_way (bist_way[11:10]),
.wd_b_l (wrdata1_d1_l[27:0]),
.lkuptag (lkup_tag_d1[27:1]),
.rclk (rclk),
.sehold (sehold),
.se (se),
.sin (),
.sout (),
.rst_tri_en (rst_tri_en),
.arst_l (arst_l),
.gbl_red_rid(fuse_l2t_rid[1:0]),
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
.fclk1 (efc_sctag_fuse_clk1),
.gbl_red_bank_id_top(gbl_red_bank_id[10]),
.gbl_red_bank_id_bottom(gbl_red_bank_id[11]),
.gbl_red_wr_en(wr_en_subbank[5]));
*/
bw_r_l2t_subbank subbankab(/*AUTOINST*/
// Outputs
.sout (), // Templated
.wayselect0(way_sel[10]), // Templated
.wayselect1(way_sel[11]), // Templated
.tag_way0(tag_way10[27:0]), // Templated
.tag_way1(tag_way11[27:0]), // Templated
.red_reg_q_array2(red_reg_q_ab[6:0]), // Templated
.red_reg_enq_array2(red_reg_enq_ab[1:0]), // Templated
// Inputs
.index(index[9:0]),
.bist_index(bist_index[9:0]),
.wr_en(wr_en),
.bist_wr_en(bist_wr_en),
.rd_en(rd_en),
.bist_rd_en(bist_rd_en),
.way (way[11:10]), // Templated
.bist_way(bist_way[11:10]), // Templated
.wd_b_l(wrdata1_d1_l[27:0]), // Templated
.lkuptag(lkup_tag_d1[27:1]), // Templated
.rclk (rclk), // Templated
.sehold(sehold), // Templated
.se (se), // Templated
.sin (), // Templated
.rst_tri_en(rst_tri_en), // Templated
.arst_l(arst_l), // Templated
.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
.fclk1(efc_sctag_fuse_clk1), // Templated
.gbl_red_bank_id_top(gbl_red_bank_id[10]), // Templated
.gbl_red_bank_id_bottom(gbl_red_bank_id[11]), // Templated
.gbl_red_wr_en(wr_en_subbank[5])); // Templated
endmodule
module bw_r_l2t_subbank(/*AUTOARG*/
// Outputs
sout, wayselect0, wayselect1, tag_way0, tag_way1,
red_reg_q_array2, red_reg_enq_array2,
// Inputs
index, bist_index, wr_en, bist_wr_en, rd_en, bist_rd_en, way,
bist_way, wd_b_l, lkuptag, rclk, sehold, se, sin, rst_tri_en,
arst_l, gbl_red_rid, gbl_red_reg_en, gbl_red_reg_d, fclk1,
gbl_red_bank_id_top, gbl_red_bank_id_bottom, gbl_red_wr_en
);
// !!! Changed gbl_red_wren to gbl_red_wr_en as it is in schematic !!!
//////////////
// INPUTS
//////////////
input [9:0] index;
input [9:0] bist_index;
input wr_en;
input bist_wr_en;
input rd_en;
input bist_rd_en;
input [1:0] way;
input [1:0] bist_way;
input [27:0] wd_b_l ; //inverted data. not flopped here
input [27:1] lkuptag; //not flopped here
input rclk;
input sehold;
input se;
input sin;
input rst_tri_en;
// not coded in the spec
// arst function
input arst_l; // redundancy registers.
input [1:0] gbl_red_rid;
input [1:0] gbl_red_reg_en;
input [6:0] gbl_red_reg_d;
input fclk1;
input gbl_red_bank_id_top;
input gbl_red_bank_id_bottom;
input gbl_red_wr_en ;
// !!! Changed gbl_red_wren to gbl_red_wr_en as it is in schematic !!!
//////////////
// OUTPUTS
//////////////
output sout;
output wayselect0;
output wayselect1;
output [27:0] tag_way0 ;
output [27:0] tag_way1 ;
output [6:0] red_reg_q_array2;
output [1:0] red_reg_enq_array2;
// !!! Taken out ssclk !!!
// !!! Registering all tag outputs including wayselect as it is how implemented in design !!!
wire temp_wayselect0; //Registering wayselect signal
wire temp_wayselect1; //Registering wayselect signal
reg wayselect0; // Registering wayselect signal
reg wayselect1; // Registering wayselect signal
reg [27:0] temp_tag_way0 ; // Registering tag read out data
reg [27:0] temp_tag_way1 ; // Registering tag read out data
// !!! Registering all tag outputs including wayselect as it is how implemented in design !!!
reg [9:0] index_d1;
reg [1:0] way_d1;
reg wren_d1, rden_d1 ;
reg [27:0] way0[1023:0] ;
reg [27:0] way1[1023:0] ;
reg [27:0] tag_way0, tag_way1 ;
// JC modified begin
// the size of row redundant register is 1 bit smaller than
// the size of column one.
reg [7:0] rid_subbank0_reg0 ;
reg [7:0] rid_subbank0_reg1 ;
// JC modified end
reg [8:0] rid_subbank0_reg2 ;
reg [8:0] rid_subbank0_reg3 ;
// JC modified begin
reg [7:0] rid_subbank1_reg0 ;
reg [7:0] rid_subbank1_reg1 ;
// JC modified end
reg [8:0] rid_subbank1_reg2 ;
reg [8:0] rid_subbank1_reg3 ;
reg [1:0] red_reg_enq_array2;
reg [6:0] red_reg_q_array2;
wire [3:0] red_reg;
////////////////////////////
// REDUNDANCY LOGIC
////////////////////////////
assign red_reg = { gbl_red_bank_id_top, gbl_red_bank_id_bottom, gbl_red_rid[1:0] };
// JC modified begin
// The following modification include
// 1. the size of row redundant register changes.
// 2. the redundant output does not gate with clock
always @(posedge fclk1 or arst_l ) begin
if(!arst_l) begin
rid_subbank0_reg0 = 8'b0 ;
rid_subbank0_reg1 = 8'b0 ;
rid_subbank0_reg2 = 9'b0 ;
rid_subbank0_reg3 = 9'b0 ;
rid_subbank1_reg0 = 8'b0 ;
rid_subbank1_reg1 = 8'b0 ;
rid_subbank1_reg2 = 9'b0 ;
rid_subbank1_reg3 = 9'b0 ;
end
else if(gbl_red_wr_en) begin
case(red_reg)
4'b1000: rid_subbank0_reg0 = {gbl_red_reg_d[5:0], gbl_red_reg_en[1:0]};
4'b1001: rid_subbank0_reg1 = {gbl_red_reg_d[5:0], gbl_red_reg_en[1:0]};
4'b1010: rid_subbank0_reg2 = {gbl_red_reg_d[6:0], gbl_red_reg_en[1:0]};
4'b1011: rid_subbank0_reg3 = {gbl_red_reg_d[6:0], gbl_red_reg_en[1:0]};
4'b0100: rid_subbank1_reg0 = {gbl_red_reg_d[5:0], gbl_red_reg_en[1:0]};
4'b0101: rid_subbank1_reg1 = {gbl_red_reg_d[5:0], gbl_red_reg_en[1:0]};
4'b0110: rid_subbank1_reg2 = {gbl_red_reg_d[6:0], gbl_red_reg_en[1:0]};
4'b0111: rid_subbank1_reg3 = {gbl_red_reg_d[6:0], gbl_red_reg_en[1:0]};
default: ; // Do nothing
endcase
end // of else if
end // of always
always @( red_reg or rid_subbank0_reg0 or rid_subbank0_reg1 or rid_subbank0_reg2 or rid_subbank0_reg3 or
rid_subbank1_reg0 or rid_subbank1_reg1 or rid_subbank1_reg2 or rid_subbank1_reg3) begin
case(red_reg)
4'b1000:
{ red_reg_q_array2, red_reg_enq_array2 } = {1'b0,rid_subbank0_reg0};
4'b1001:
{ red_reg_q_array2, red_reg_enq_array2 } = {1'b0,rid_subbank0_reg1};
4'b1010:
{ red_reg_q_array2, red_reg_enq_array2 } = rid_subbank0_reg2;
4'b1011:
{ red_reg_q_array2, red_reg_enq_array2 } = rid_subbank0_reg3;
4'b0100:
{ red_reg_q_array2, red_reg_enq_array2 } = {1'b0,rid_subbank1_reg0};
4'b0101:
{ red_reg_q_array2, red_reg_enq_array2 } = {1'b0,rid_subbank1_reg1};
4'b0110:
{ red_reg_q_array2, red_reg_enq_array2 } = rid_subbank1_reg2;
4'b0111:
{ red_reg_q_array2, red_reg_enq_array2 } = rid_subbank1_reg3;
default:
{ red_reg_q_array2, red_reg_enq_array2 } = 9'b0;
endcase
end
always @(posedge rclk) begin
index_d1 <= ( sehold) ? index_d1 :
( bist_wr_en | bist_rd_en ) ? bist_index : index ;
way_d1 <= (sehold)? way_d1 :
( bist_wr_en | bist_rd_en ) ? bist_way : way ;
wren_d1 <= ( sehold)? wren_d1 :
( bist_wr_en | wr_en ) ;
rden_d1 <= ( sehold)? rden_d1 :
( bist_rd_en | rd_en );
end
// !!! Flopping output signals !!!
always @(posedge rclk) begin
wayselect0 <= temp_wayselect0;
wayselect1 <= temp_wayselect1;
tag_way0 <= temp_tag_way0;
tag_way1 <= temp_tag_way1;
end
// !!! Flopping output signals !!!
////////////////////////////////
// COMPARE OPERATION
////////////////////////////////
// !!! Also, we are gating wayselect with rd_en so, in other cycles (write or no op)
// all wayselect signals are miss. !!!
assign temp_wayselect0 = (rden_d1) ? ( lkuptag == temp_tag_way0[27:1] ) : 0 ;
assign temp_wayselect1 = (rden_d1) ? ( lkuptag == temp_tag_way1[27:1] ) : 0 ;
////////////////////////////////
// READ OPERATION
////////////////////////////////
always @( /*AUTOSENSE*/ /*memory or*/ index_d1 or rden_d1
or rst_tri_en or wren_d1) begin
`ifdef INNO_MUXEX
`else
if(wren_d1==1'bx) begin
`ifdef MODELSIM
$display("L2_TAG_ERR"," wr en error %b ", wren_d1);
`else
$error("L2_TAG_ERR"," wr en error %b ", wren_d1);
`endif
end
`endif
if( rden_d1) begin
`ifdef INNO_MUXEX
`else
//----- PURELY FOR VERIFICATION -----------------------
if(index_d1==10'bx) begin
`ifdef MODELSIM
$display("L2_TAG_ERR"," index error %h ", index_d1[9:0]);
`else
$error("L2_TAG_ERR"," index error %h ", index_d1[9:0]);
`endif
end
//----- PURELY FOR VERIFICATION -----------------------
`endif
if( wren_d1 ) begin
temp_tag_way0 = 28'bx ;
temp_tag_way1 = 28'bx ;
end
else begin
temp_tag_way0 = way0[index_d1] ;
temp_tag_way1 = way1[index_d1] ;
end
end // of if rden_d1
else begin
// !!! When Tag is in write or no-op cycles, all output will be "0" since SAs are precharged !!!
temp_tag_way0 = 0;
temp_tag_way1 = 0;
end
end
////////////////////////////////
// WRITE OPERATION
////////////////////////////////
always @(negedge rclk ) begin
if( wren_d1 & ~rst_tri_en) begin
`ifdef INNO_MUXEX
`else
//----- PURELY FOR VERIFICATION -----------------------
if(index_d1==10'bx) begin
`ifdef MODELSIM
$display("L2_TAG_ERR"," index error %h ", index_d1[9:0]);
`else
$error("L2_TAG_ERR"," index error %h ", index_d1[9:0]);
`endif
end
//----- PURELY FOR VERIFICATION -----------------------
`endif
// !!! When Tag is in write or no-op cycles, all output will be "0" since SAs are precharged !!!
temp_tag_way0 = 0;
temp_tag_way1 = 0;
case(way_d1)
2'b01 : begin
way0[index_d1] = ~wd_b_l;
end
2'b10 : begin
way1[index_d1] = ~wd_b_l;
end
default: ;
endcase
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bg_low (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [10 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("bg_low.mif"),
.C_INIT_FILE("bg_low.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(1092),
.C_READ_DEPTH_A(1092),
.C_ADDRA_WIDTH(11),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(1092),
.C_READ_DEPTH_B(1092),
.C_ADDRB_WIDTH(11),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5912999999999999 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(11'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_pad_mux
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_pad_mux.v,v 1.2 2007/03/05 16:41:13 wig Exp $
// $Date: 2007/03/05 16:41:13 $
// $Log: avfb_pad_mux.v,v $
// Revision 1.2 2007/03/05 16:41:13 wig
// Updated testcase: remove mux_sel_p and some loose mix_logic_0/1
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_pad_mux
//
// No user `defines in this module
module avfb_pad_mux
//
// Generated module i_avfb_pad_mux
//
(
BC_RA_02_fail_i
);
// Generated Module Inputs:
input BC_RA_02_fail_i;
// Generated Wires:
wire BC_RA_02_fail_i;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire BC_RA_02_fail; // __W_PORT_SIGNAL_MAP_REQ
// __I_IN_OPEN wire [4:4] cvbs_c_tbo_1 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] cvbs_c_tbo_2 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire i2s_ws_en_out1 ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire i2s_ws_out1_in ; // __W_BAD_BRANCH
// __I_IN_OPEN wire i2s_ws_out1_out ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [5:0] iom_mux_control ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire [2:2] kl_123456a2345b_c ; // __W_BAD_BRANCH
// __I_IN_OPEN wire lfsr_out_7 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] postproc_out_b_tbo ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] rgb_c_tbo_1 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] rgb_c_tbo_2 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire scan_out_7 ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire [6:6] test_in_0 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [6:6] test_out_0 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire test_pad_oen_0 ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire [2:2] ts_adc_samples_1 ; // __W_BAD_BRANCH
// __I_OUT_OPEN wire [2:2] ts_adc_samples_2 ; // __W_BAD_BRANCH
// __I_IN_OPEN wire [4:4] ts_intsig1 ; // __W_BAD_BRANCH
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign BC_RA_02_fail = BC_RA_02_fail_i; // __I_I_BIT_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for iom_i2s_ws_out1
wire mix_dmy_open_0; //__I_OPEN_DUMMY
wire mix_dmy_open_1; //__I_OPEN_DUMMY
wire mix_dmy_open_2; //__I_OPEN_DUMMY
wire mix_dmy_open_3; //__I_OPEN_DUMMY
wire mix_dmy_open_4; //__I_OPEN_DUMMY
wire mix_dmy_open_5; //__I_OPEN_DUMMY
wire mix_dmy_open_6; //__I_OPEN_DUMMY
wire mix_dmy_open_7; //__I_OPEN_DUMMY
wire mix_dmy_open_8; //__I_OPEN_DUMMY
wire mix_dmy_open_9; //__I_OPEN_DUMMY
wire mix_dmy_open_10; //__I_OPEN_DUMMY
wire mix_dmy_open_11; //__I_OPEN_DUMMY
wire mix_dmy_open_12; //__I_OPEN_DUMMY
wire mix_dmy_open_13; //__I_OPEN_DUMMY
wire mix_dmy_open_14; //__I_OPEN_DUMMY
iom_24 iom_i2s_ws_out1 (
.dot_i({ 1'b0, lfsr_out_7, test_out_0, 1'b0, 1'b0, i2s_ws_out1_out, i2s_ws_out1_out, 1'b0, 1'b0, ts_intsig1, rgb_c_tbo_2, rgb_c_tbo_1, cvbs_c_tbo_2, cvbs_c_tbo_1, postproc_out_b_tbo, 1'b0, 1'b0, BC_RA_02_fail, scan_out_7, i2s_ws_out1_out }), // __W_PORT (x7) // __I_BIT_TO_BUSPORT (x13) // __I_COMBINE_SPLICES
.ena_i({ 1'b0, 1'b1, test_pad_oen_0, 1'b0, 1'b0, i2s_ws_en_out1, i2s_ws_en_out1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, i2s_ws_en_out1 }), // __I_BIT_TO_BUSPORT (x20) // __I_COMBINE_SPLICES
.ret_o({ mix_dmy_open_6, mix_dmy_open_5, test_in_0, ts_adc_samples_2, ts_adc_samples_1, mix_dmy_open_4, mix_dmy_open_3, mix_dmy_open_2, mix_dmy_open_1, mix_dmy_open_0, mix_dmy_open_14, mix_dmy_open_13, mix_dmy_open_12, mix_dmy_open_11, mix_dmy_open_10, kl_123456a2345b_c, mix_dmy_open_9, mix_dmy_open_8, mix_dmy_open_7, i2s_ws_out1_in }) // __W_PORT (x4) // __I_BIT_TO_BUSPORT (x16) // __I_COMBINE_SPLICES
);
// End of Generated Instance Port Map for iom_i2s_ws_out1
endmodule
//
// End of Generated Module rtl of avfb_pad_mux
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTP_SYMBOL_V
`define SKY130_FD_SC_HS__DFRTP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A41OI_PP_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_PP_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:29 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_0_0/ip_design_axi_gpio_0_0_sim_netlist.v
// Design : ip_design_axi_gpio_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_axi_gpio_0_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2017.3" *)
(* NotValidForBitStream *)
module ip_design_axi_gpio_0_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio_io_o,
gpio_io_t);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) input [1:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [1:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [1:0]gpio_io_t;
wire [1:0]gpio_io_i;
wire [1:0]gpio_io_o;
wire [1:0]gpio_io_t;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "2" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
ip_design_axi_gpio_0_0_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module ip_design_axi_gpio_0_0_GPIO_Core
(reg1,
GPIO_xferAck_i,
gpio_xferAck_Reg,
reg2,
gpio_io_o,
\gpio_io_t[0] ,
\gpio_io_t[1] ,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
bus2ip_rnw_i_reg,
s_axi_aclk,
bus2ip_reset,
Q,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
s_axi_wdata,
rst_reg,
rst_reg_0);
output [1:0]reg1;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output [1:0]reg2;
output [1:0]gpio_io_o;
output \gpio_io_t[0] ;
output \gpio_io_t[1] ;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
input bus2ip_rnw_i_reg;
input s_axi_aclk;
input bus2ip_reset;
input [1:0]Q;
input \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
input bus2ip_rnw;
input bus2ip_cs;
input [1:0]gpio_io_i;
input [3:0]s_axi_wdata;
input rst_reg;
input rst_reg_0;
wire GPIO_xferAck_i;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0 ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0 ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0 ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0 ;
wire \Not_Dual.gpio_Data_Out[0]_i_1_n_0 ;
wire \Not_Dual.gpio_Data_Out[1]_i_1_n_0 ;
wire \Not_Dual.gpio_OE[0]_i_1_n_0 ;
wire \Not_Dual.gpio_OE[1]_i_1_n_0 ;
wire [1:0]Q;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire bus2ip_rnw_i_reg;
wire [0:1]gpio_Data_In;
wire [1:0]gpio_io_i;
wire [0:1]gpio_io_i_d2;
wire [1:0]gpio_io_o;
wire \gpio_io_t[0] ;
wire \gpio_io_t[1] ;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire [1:0]reg1;
wire [1:0]reg2;
wire rst_reg;
wire rst_reg_0;
wire s_axi_aclk;
wire [3:0]s_axi_wdata;
LUT6 #(
.INIT(64'h2C2E22222C222222))
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1
(.I0(gpio_io_o[1]),
.I1(\gpio_io_t[1] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.I5(gpio_Data_In[0]),
.O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0 ));
FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0 ),
.Q(reg1[1]),
.R(bus2ip_rnw_i_reg));
LUT6 #(
.INIT(64'h2C2E22222C222222))
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1
(.I0(reg2[1]),
.I1(\gpio_io_t[1] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.I5(gpio_Data_In[0]),
.O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0 ));
FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0 ),
.Q(reg2[1]),
.R(bus2ip_rnw_i_reg));
LUT6 #(
.INIT(64'h2C2E22222C222222))
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2
(.I0(gpio_io_o[0]),
.I1(\gpio_io_t[0] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.I5(gpio_Data_In[1]),
.O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0 ));
FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0 ),
.Q(reg1[0]),
.R(bus2ip_rnw_i_reg));
LUT6 #(
.INIT(64'h2C2E22222C222222))
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1
(.I0(reg2[0]),
.I1(\gpio_io_t[0] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.I5(gpio_Data_In[1]),
.O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0 ));
FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0 ),
.Q(reg2[0]),
.R(bus2ip_rnw_i_reg));
ip_design_axi_gpio_0_0_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1]}));
FDRE \Not_Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(gpio_Data_In[0]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(gpio_Data_In[1]),
.R(1'b0));
LUT6 #(
.INIT(64'hFB08FFFFFB080000))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(s_axi_wdata[1]),
.I1(bus2ip_cs),
.I2(Q[1]),
.I3(s_axi_wdata[3]),
.I4(rst_reg),
.I5(gpio_io_o[1]),
.O(\Not_Dual.gpio_Data_Out[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFB08FFFFFB080000))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[0]),
.I1(bus2ip_cs),
.I2(Q[1]),
.I3(s_axi_wdata[2]),
.I4(rst_reg),
.I5(gpio_io_o[0]),
.O(\Not_Dual.gpio_Data_Out[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_Data_Out[0]_i_1_n_0 ),
.Q(gpio_io_o[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_Data_Out[1]_i_1_n_0 ),
.Q(gpio_io_o[0]),
.R(bus2ip_reset));
LUT6 #(
.INIT(64'hFB08FFFFFB080000))
\Not_Dual.gpio_OE[0]_i_1
(.I0(s_axi_wdata[1]),
.I1(bus2ip_cs),
.I2(Q[1]),
.I3(s_axi_wdata[3]),
.I4(rst_reg_0),
.I5(\gpio_io_t[1] ),
.O(\Not_Dual.gpio_OE[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFB08FFFFFB080000))
\Not_Dual.gpio_OE[1]_i_1
(.I0(s_axi_wdata[0]),
.I1(bus2ip_cs),
.I2(Q[1]),
.I3(s_axi_wdata[2]),
.I4(rst_reg_0),
.I5(\gpio_io_t[0] ),
.O(\Not_Dual.gpio_OE[1]_i_1_n_0 ));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE[0]_i_1_n_0 ),
.Q(\gpio_io_t[1] ),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE[1]_i_1_n_0 ),
.Q(\gpio_io_t[0] ),
.S(bus2ip_reset));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(bus2ip_reset));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h02))
iGPIO_xferAck_i_1
(.I0(bus2ip_cs),
.I1(gpio_xferAck_Reg),
.I2(GPIO_xferAck_i),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(bus2ip_reset));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module ip_design_axi_gpio_0_0_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
s_axi_wready,
s_axi_arready,
\Not_Dual.gpio_Data_Out_reg[0] ,
\Not_Dual.gpio_OE_reg[0] ,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ,
D,
Q,
s_axi_aclk,
s_axi_aresetn,
rst_reg,
bus2ip_rnw_i_reg,
\bus2ip_addr_i_reg[8] ,
ip2bus_rdack_i_D1,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
ip2bus_wrack_i_D1,
is_write_reg,
gpio_xferAck_Reg,
GPIO_xferAck_i,
reg2,
reg1);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output s_axi_wready;
output s_axi_arready;
output \Not_Dual.gpio_Data_Out_reg[0] ;
output \Not_Dual.gpio_OE_reg[0] ;
output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ;
output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ;
output [2:0]D;
input Q;
input s_axi_aclk;
input s_axi_aresetn;
input rst_reg;
input bus2ip_rnw_i_reg;
input [2:0]\bus2ip_addr_i_reg[8] ;
input ip2bus_rdack_i_D1;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input ip2bus_wrack_i_D1;
input is_write_reg;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [1:0]reg2;
input [1:0]reg1;
wire Bus_RNW_reg;
wire Bus_RNW_reg_i_1_n_0;
wire [2:0]D;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ;
wire \Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_OE_reg[0] ;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire cs_ce_clr;
wire gpio_xferAck_Reg;
wire \ip2bus_data_i_D1[30]_i_2_n_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire [1:0]reg1;
wire [1:0]reg2;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_wready;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(Q),
.I2(Bus_RNW_reg),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(Bus_RNW_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h1))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_3),
.Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_2),
.Q(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h2))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.O(ce_expnd_i_1));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_1),
.Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hEF))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arready),
.I2(s_axi_aresetn),
.O(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h8))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.O(ce_expnd_i_0));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(Q),
.I2(s_axi_aresetn),
.I3(s_axi_arready),
.I4(s_axi_wready),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFFF7))
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(gpio_xferAck_Reg),
.I3(GPIO_xferAck_i),
.O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h2))
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_3
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\bus2ip_addr_i_reg[8] [2]),
.O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAABAA))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(rst_reg),
.I1(bus2ip_rnw_i_reg),
.I2(\bus2ip_addr_i_reg[8] [0]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [2]),
.I5(\bus2ip_addr_i_reg[8] [1]),
.O(\Not_Dual.gpio_Data_Out_reg[0] ));
LUT6 #(
.INIT(64'hAAAAAAAAAABAAAAA))
\Not_Dual.gpio_OE[0]_i_2
(.I0(rst_reg),
.I1(bus2ip_rnw_i_reg),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(\bus2ip_addr_i_reg[8] [1]),
.O(\Not_Dual.gpio_OE_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000400))
\ip2bus_data_i_D1[0]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I3(Bus_RNW_reg),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(D[2]));
LUT6 #(
.INIT(64'h000F0AC000000000))
\ip2bus_data_i_D1[30]_i_1
(.I0(reg2[1]),
.I1(reg1[1]),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I5(\ip2bus_data_i_D1[30]_i_2_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h2))
\ip2bus_data_i_D1[30]_i_2
(.I0(Bus_RNW_reg),
.I1(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000F0AC000000000))
\ip2bus_data_i_D1[31]_i_1
(.I0(reg2[0]),
.I1(reg1[0]),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I5(\ip2bus_data_i_D1[30]_i_2_n_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(is_read),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(is_write_reg),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "2" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module ip_design_axi_gpio_0_0_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [1:0]gpio_io_i;
output [1:0]gpio_io_o;
output [1:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_10;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_7;
wire GPIO_xferAck_i;
wire [5:6]bus2ip_addr;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_core_1_n_11;
wire [1:0]gpio_io_i;
wire [1:0]gpio_io_o;
wire [1:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [0:31]ip2bus_data;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire [30:31]reg1;
wire [30:31]reg2;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [30:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [30];
assign s_axi_rdata[30] = \^s_axi_rdata [30];
assign s_axi_rdata[29] = \^s_axi_rdata [30];
assign s_axi_rdata[28] = \^s_axi_rdata [30];
assign s_axi_rdata[27] = \^s_axi_rdata [30];
assign s_axi_rdata[26] = \^s_axi_rdata [30];
assign s_axi_rdata[25] = \^s_axi_rdata [30];
assign s_axi_rdata[24] = \^s_axi_rdata [30];
assign s_axi_rdata[23] = \^s_axi_rdata [30];
assign s_axi_rdata[22] = \^s_axi_rdata [30];
assign s_axi_rdata[21] = \^s_axi_rdata [30];
assign s_axi_rdata[20] = \^s_axi_rdata [30];
assign s_axi_rdata[19] = \^s_axi_rdata [30];
assign s_axi_rdata[18] = \^s_axi_rdata [30];
assign s_axi_rdata[17] = \^s_axi_rdata [30];
assign s_axi_rdata[16] = \^s_axi_rdata [30];
assign s_axi_rdata[15] = \^s_axi_rdata [30];
assign s_axi_rdata[14] = \^s_axi_rdata [30];
assign s_axi_rdata[13] = \^s_axi_rdata [30];
assign s_axi_rdata[12] = \^s_axi_rdata [30];
assign s_axi_rdata[11] = \^s_axi_rdata [30];
assign s_axi_rdata[10] = \^s_axi_rdata [30];
assign s_axi_rdata[9] = \^s_axi_rdata [30];
assign s_axi_rdata[8] = \^s_axi_rdata [30];
assign s_axi_rdata[7] = \^s_axi_rdata [30];
assign s_axi_rdata[6] = \^s_axi_rdata [30];
assign s_axi_rdata[5] = \^s_axi_rdata [30];
assign s_axi_rdata[4] = \^s_axi_rdata [30];
assign s_axi_rdata[3] = \^s_axi_rdata [30];
assign s_axi_rdata[2] = \^s_axi_rdata [30];
assign s_axi_rdata[1:0] = \^s_axi_rdata [1:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
ip_design_axi_gpio_0_0_axi_lite_ipif AXI_LITE_IPIF_I
(.D({ip2bus_data[0],ip2bus_data[30],ip2bus_data[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] (AXI_LITE_IPIF_I_n_11),
.\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] (AXI_LITE_IPIF_I_n_12),
.\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_7),
.\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_10),
.Q({bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[0] ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.reg1({reg1[30],reg1[31]}),
.reg2({reg2[30],reg2[31]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [30],\^s_axi_rdata [1:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
ip_design_axi_gpio_0_0_GPIO_Core gpio_core_1
(.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (AXI_LITE_IPIF_I_n_12),
.Q({bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_11),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.\gpio_io_t[0] (gpio_io_t[0]),
.\gpio_io_t[1] (gpio_io_t[1]),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_11),
.reg1({reg1[30],reg1[31]}),
.reg2({reg2[30],reg2[31]}),
.rst_reg(AXI_LITE_IPIF_I_n_7),
.rst_reg_0(AXI_LITE_IPIF_I_n_10),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata({s_axi_wdata[31:30],s_axi_wdata[1:0]}));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_11),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module ip_design_axi_gpio_0_0_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
s_axi_rvalid,
s_axi_bvalid,
bus2ip_cs,
s_axi_wready,
s_axi_arready,
\Not_Dual.gpio_Data_Out_reg[0] ,
Q,
\Not_Dual.gpio_OE_reg[0] ,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ,
s_axi_rdata,
D,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_araddr,
s_axi_awaddr,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[0] ,
reg2,
reg1);
output bus2ip_reset;
output bus2ip_rnw;
output s_axi_rvalid;
output s_axi_bvalid;
output bus2ip_cs;
output s_axi_wready;
output s_axi_arready;
output \Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]Q;
output \Not_Dual.gpio_OE_reg[0] ;
output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ;
output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ;
output [2:0]s_axi_rdata;
output [2:0]D;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [2:0]\ip2bus_data_i_D1_reg[0] ;
input [1:0]reg2;
input [1:0]reg1;
wire [2:0]D;
wire GPIO_xferAck_i;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ;
wire \Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_OE_reg[0] ;
wire [1:0]Q;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_xferAck_Reg;
wire [2:0]\ip2bus_data_i_D1_reg[0] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire [1:0]reg1;
wire [1:0]reg2;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [2:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
ip_design_axi_gpio_0_0_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] (bus2ip_rnw),
.\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0 (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ),
.\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q(Q),
.SR(bus2ip_reset),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.reg1(reg1),
.reg2(reg2),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module ip_design_axi_gpio_0_0_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [1:0]scndry_vect_out;
input [1:0]gpio_io_i;
input s_axi_aclk;
wire [1:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire [1:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module ip_design_axi_gpio_0_0_slave_attachment
(SR,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ,
s_axi_rvalid,
s_axi_bvalid,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_wready,
s_axi_arready,
\Not_Dual.gpio_Data_Out_reg[0] ,
Q,
\Not_Dual.gpio_OE_reg[0] ,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0 ,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ,
s_axi_rdata,
D,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_araddr,
s_axi_awaddr,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[0] ,
reg2,
reg1);
output SR;
output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ;
output s_axi_rvalid;
output s_axi_bvalid;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_wready;
output s_axi_arready;
output \Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]Q;
output \Not_Dual.gpio_OE_reg[0] ;
output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0 ;
output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ;
output [2:0]s_axi_rdata;
output [2:0]D;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [2:0]\ip2bus_data_i_D1_reg[0] ;
input [1:0]reg2;
input [1:0]reg1;
wire [2:0]D;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0 ;
wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ;
wire \Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_OE_reg[0] ;
wire [1:0]Q;
wire SR;
wire [0:0]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire clear;
wire gpio_xferAck_Reg;
wire [2:0]\ip2bus_data_i_D1_reg[0] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire [3:0]plusOp;
wire [1:0]reg1;
wire [1:0]reg2;
wire rst_i_1_n_0;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [2:0]s_axi_rdata;
wire \s_axi_rdata_i[0]_i_1_n_0 ;
wire \s_axi_rdata_i[1]_i_1_n_0 ;
wire \s_axi_rdata_i[31]_i_1_n_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
ip_design_axi_gpio_0_0_address_decoder I_DECODER
(.D(D),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0 ),
.\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31] ),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q(start2),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr,Q}),
.bus2ip_rnw_i_reg(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.reg1(reg1),
.reg2(reg2),
.rst_reg(SR),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wready(s_axi_wready));
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(Q[0]),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(Q[1]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr),
.R(SR));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(s_axi_arvalid),
.Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30] ),
.R(SR));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(SR));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(rst_i_1_n_0));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rst_i_1_n_0),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(SR));
LUT4 #(
.INIT(16'hFB08))
\s_axi_rdata_i[0]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [0]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rdata[0]),
.O(\s_axi_rdata_i[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFB08))
\s_axi_rdata_i[1]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [1]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rdata[1]),
.O(\s_axi_rdata_i[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFB08))
\s_axi_rdata_i[31]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [2]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rdata[2]),
.O(\s_axi_rdata_i[31]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\s_axi_rdata_i[0]_i_1_n_0 ),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\s_axi_rdata_i[1]_i_1_n_0 ),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\s_axi_rdata_i[31]_i_1_n_0 ),
.Q(s_axi_rdata[2]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(state[0]),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(s_axi_wready),
.O(p_0_out[0]));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(\state[1]_i_3_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arready),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_1_V
`define SKY130_FD_SC_HDLL__TAPVGND2_1_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog wrapper for tapvgnd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvgnd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__tapvgnd2 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatchhv_pp_plg_s/sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:14:53 10/20/2015
// Design Name: GateLevel_PE
// Module Name: E:/IIIT-Delhi/Semester III/Courses/ELD/Assignments/PriorityEncoder/PE_test.v
// Project Name: PriorityEncoder
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: GateLevel_PE
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module PE_test;
// Inputs
reg in2;
reg in1;
reg in0;
// Outputs
wire out1;
wire out0;
// Instantiate the Unit Under Test (UUT)
Behavioral_PE uut (
.out1(out1),
.out0(out0),
.in2(in2),
.in1(in1),
.in0(in0)
);
initial begin
// Initialize Inputs
in2 = 0;
in1 = 0;
in0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in2 = 0; in1 = 0; in0 = 0;
#20;
in2 = 0; in1 = 0; in0 = 1;
#20;
in2 = 0; in1 = 1; in0 = 0;
#20;
in2 = 0; in1 = 1; in0 = 1;
#20;
in2 = 1; in1 = 0; in0 = 0;
#20;
in2 = 1; in1 = 0; in0 = 1;
#20;
in2 = 1; in1 = 1; in0 = 0;
#20;
in2 = 1; in1 = 1; in0 = 1;
#20;
end
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.ne2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.ne2_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 1);
`assert(result_empty, 0);
$finish;
end
endmodule
|
// Fetch-Issue Pipeline Register
module iss_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire enable, // Active Low enable signal
input wire[31:0] next_pc_iss_pipe_reg_i,
input wire[31:0] instr_iss_pipe_reg_i,
input wire brn_pred_iss_pipe_reg_i,
input wire[31:0] curr_pc_iss_pipe_reg_i,
input wire[31:0] next_pred_pc_iss_pipe_reg_i,
output wire[31:0] next_pc_iss_pipe_reg_o,
output wire[31:0] instr_iss_pipe_reg_o,
output wire brn_pred_iss_pipe_reg_o,
output wire[31:0] curr_pc_iss_pipe_reg_o,
output wire[31:0] next_pred_pc_iss_pipe_reg_o
);
reg [31:0] next_pc_iss_pipe_reg;
reg [31:0] instr_iss_pipe_reg;
reg brn_pred_iss_pipe_reg;
reg [31:0] curr_pc_iss_pipe_reg;
reg [31:0] next_pred_pc_iss_pipe_reg;
assign next_pc_iss_pipe_reg_o = next_pc_iss_pipe_reg;
assign instr_iss_pipe_reg_o = instr_iss_pipe_reg;
assign brn_pred_iss_pipe_reg_o = brn_pred_iss_pipe_reg;
assign curr_pc_iss_pipe_reg_o = curr_pc_iss_pipe_reg;
assign next_pred_pc_iss_pipe_reg_o = next_pred_pc_iss_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
next_pc_iss_pipe_reg <= 31'b0;
instr_iss_pipe_reg <= 31'b0;
brn_pred_iss_pipe_reg <= 31'b0;
curr_pc_iss_pipe_reg <= 31'b0;
next_pred_pc_iss_pipe_reg <= 31'b0;
end
else if (~enable)
begin
next_pc_iss_pipe_reg <= next_pc_iss_pipe_reg_i;
instr_iss_pipe_reg <= instr_iss_pipe_reg_i;
brn_pred_iss_pipe_reg <= brn_pred_iss_pipe_reg_i;
curr_pc_iss_pipe_reg <= curr_pc_iss_pipe_reg_i;
next_pred_pc_iss_pipe_reg <= next_pred_pc_iss_pipe_reg_i;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Boston University
// Engineer: Zafar M. Takhirov
//
// Create Date: 17:17:19 04/14/2013
// Design Name: VGA sprites controller
// Module Name: vga_bsprite
// Project Name: vga_display
// Target Devices: xc6slx16
// Tool versions: ISE 13.3
// Description: This project calls memory sprites to show on the screen
//
// Dependencies: game_over_mem, vga_controller
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_bsprite(hc, vc, mem_value, rom_addr, R, G, B, blank, inside_image);
input [10:0] hc, vc; // Coordinates of the current pixel
input [7:0] mem_value; // Memory value at address "rom_addr"
input blank;
output reg [14:0] rom_addr; // ROM address
output reg [2:0] R, G;
output reg [1:0] B; // RGB values outputs;
output reg inside_image;
parameter [10:0] VGA_WIDTH = 640;
parameter [10:0] VGA_HEIGHT = 480;
parameter [7:0] IMG_WIDTH = 175;
parameter [7:0] IMG_HEIGHT = 175;
parameter [3:0] SCALE = 1;
parameter [10:0] START_X = (VGA_WIDTH - (IMG_WIDTH * SCALE)) / 2;
parameter [10:0] START_Y = (VGA_HEIGHT - (IMG_HEIGHT * SCALE)) / 2;
parameter [10:0] END_X = START_X + IMG_WIDTH;
parameter [10:0] END_Y = START_Y + IMG_HEIGHT;
reg [10:0] x, y;
wire [10:0] div_hc, div_vc;
wire [11:0] mult_x1, mult_y1;
assign div_hc = hc >> (SCALE >> 1);
assign div_vc = vc >> (SCALE >> 1);
assign mult_x1 = END_X << (SCALE >> 1);
assign mult_y1 = END_Y << (SCALE >> 1);
always @ (*) begin
if (hc >= START_X & hc <= mult_x1) // make sure thath x1-x0 = image_width
x = div_hc - START_X; // offset the coordinates
else
x = 0;
if (vc >= START_Y & vc <= mult_y1) // make sure that y1-y0 = image_height
y = div_vc - START_Y; //offset the coordinates
else
y = 0;
rom_addr = y*IMG_WIDTH + x;
if (x==0 | y==0) begin // set the color output
{R,G,B} = 8'd0;
inside_image <= 1'b0;
end else begin
{R,G,B} = mem_value;
inside_image <= 1'b1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V |
//-----------------------------------------------------------------------------
//
// File Name: OUTPUT_TESTER.v
// Project: $PROJECT_NAME
// Version: 1.2
// Date: 2005-06-29
//
// Company: Xilinx, Inc.
// Contributor: Wen Ying Wei, Davy Huang
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2005 Xilinx, Inc.
// All rights reserved.
//
//-----------------------------------------------------------------------------
// OUTPUT_TESTER
// Author: Nigel Gulstone, Davy Huang
//
// Description: Monitors the output from the Tester RX interfaces and
// compares the data it receives with reference data. The
// reference data is typically the data that was given to
// the TX interface of the receiving channel
// partner. The output data and the reference data must match
// for result good to be asserted.
//-----------------------------------------------------------------------------
`timescale 1 ns / 10 ps
module OUTPUT_TESTER(
CLK,
RST,
//Dut LocalLink Interface
RX_D,
RX_REM,
RX_SOF_N,
RX_EOF_N,
RX_SRC_RDY_N,
//Dut UFC Interface
UFC_RX_DATA,
UFC_RX_REM,
UFC_RX_SOF_N,
UFC_RX_EOF_N,
UFC_RX_SRC_RDY_N,
//Reference LocalLink Interface
RX_SOF_N_REF,
RX_EOF_N_REF,
RX_REM_REF,
RX_DATA_REF,
RX_SRC_RDY_N_REF,
//Reference UFC Interface
UFC_RX_DATA_REF,
UFC_RX_REM_REF,
UFC_RX_SOF_N_REF,
UFC_RX_EOF_N_REF,
UFC_RX_SRC_RDY_N_REF,
//Comparison result
WORKING,
COMPARING,
OVERFLOW,
RESULT_GOOD,
RESULT_GOOD_PDU,
RESULT_GOOD_UFC
);
// Parameter Declarations ********************************************
parameter GLOBALDLY = 1;
parameter LL_DAT_BIT_WIDTH = 64; //16,32,64,128
parameter LL_REM_BIT_WIDTH = 3; // 1, 2, 3, 4
parameter FIFO_DEPTH = 100;
// Port Declarations ************************************************
input CLK;
input RST;
//Dut LocalLink Interface
input [0:LL_DAT_BIT_WIDTH-1] RX_D;
input [0:LL_REM_BIT_WIDTH-1] RX_REM;
input RX_SOF_N;
input RX_EOF_N;
input RX_SRC_RDY_N;
//UFC Interface //Dut UFC Interface
input [0:LL_DAT_BIT_WIDTH-1] UFC_RX_DATA;
input [0:LL_REM_BIT_WIDTH-1] UFC_RX_REM;
input UFC_RX_SOF_N;
input UFC_RX_EOF_N;
input UFC_RX_SRC_RDY_N;
//Reference LocalLink Interface
input RX_SOF_N_REF;
input RX_EOF_N_REF;
input [0:LL_REM_BIT_WIDTH-1] RX_REM_REF;
input [0:LL_DAT_BIT_WIDTH-1] RX_DATA_REF;
input RX_SRC_RDY_N_REF;
//Reference UFC Interface
input [0:LL_DAT_BIT_WIDTH-1] UFC_RX_DATA_REF;
input [0:LL_REM_BIT_WIDTH-1] UFC_RX_REM_REF;
input UFC_RX_SOF_N_REF;
input UFC_RX_EOF_N_REF;
input UFC_RX_SRC_RDY_N_REF;
//Comparison result
output WORKING;
output COMPARING;
output OVERFLOW;
output RESULT_GOOD;
output RESULT_GOOD_PDU;
output RESULT_GOOD_UFC;
// Signal Declarations ***********************************************
reg WORKING;
reg COMPARING;
reg OVERFLOW;
reg RESULT_GOOD;
reg RESULT_GOOD_PDU;
reg RESULT_GOOD_UFC;
integer dut_index;
integer ref_index;
integer dut_ufc_index;
integer ref_ufc_index;
integer shuffle;
reg [0:LL_DAT_BIT_WIDTH+1] dut_data_fifo [0:FIFO_DEPTH-1];
reg [0:LL_DAT_BIT_WIDTH+1] ref_data_fifo [0:FIFO_DEPTH-1];
reg [0:LL_DAT_BIT_WIDTH+1] dut_ufc_fifo [0:FIFO_DEPTH-1];
reg [0:LL_DAT_BIT_WIDTH+1] ref_ufc_fifo [0:FIFO_DEPTH-1];
reg [0:LL_DAT_BIT_WIDTH+1] dut_data;
reg [0:LL_DAT_BIT_WIDTH+1] ref_data;
wire [0:LL_DAT_BIT_WIDTH-1] dut_data_view;
wire [0:LL_DAT_BIT_WIDTH-1] ref_data_view;
reg [0:LL_DAT_BIT_WIDTH+1] dut_ufc_data;
reg [0:LL_DAT_BIT_WIDTH+1] ref_ufc_data;
reg inframe;
reg inframe_ref;
reg clk_detect;
reg clk_detect_p;
wire clk_detected;
integer index1;
integer index2;
integer index3;
integer index4;
wire [0:256-LL_DAT_BIT_WIDTH] zeros;
wire [0:256] RX_D_i;
wire [0:256] UFC_RX_DATA_i;
wire [0:256] RX_DATA_REF_i;
wire [0:256] UFC_RX_DATA_REF_i;
assign zeros = 0;
assign RX_D_i[0:LL_DAT_BIT_WIDTH-1] = RX_D;
assign RX_D_i[LL_DAT_BIT_WIDTH:256] = 0;
assign UFC_RX_DATA_i[0:LL_DAT_BIT_WIDTH-1] = UFC_RX_DATA;
assign UFC_RX_DATA_i[LL_DAT_BIT_WIDTH:256] = 0;
assign RX_DATA_REF_i[0:LL_DAT_BIT_WIDTH-1] = RX_DATA_REF;
assign RX_DATA_REF_i[LL_DAT_BIT_WIDTH:256] = 0;
assign UFC_RX_DATA_REF_i[0:LL_DAT_BIT_WIDTH-1] = UFC_RX_DATA_REF;
assign UFC_RX_DATA_REF_i[LL_DAT_BIT_WIDTH:256] = 0;
assign dut_data_view = dut_data[0:LL_DAT_BIT_WIDTH-1];
assign ref_data_view = ref_data[0:LL_DAT_BIT_WIDTH-1];
// Main Body of Code *************************************************
initial
fork
ref_index = 0;
dut_index = 0;
ref_ufc_index = 0;
dut_ufc_index = 0;
RESULT_GOOD_PDU = 1'b1;
RESULT_GOOD_UFC = 1'b1;
WORKING = 1'b0;
COMPARING = 1'b0;
OVERFLOW = 1'b0;
clk_detect = 1'b0;
clk_detect_p = 1'b0;
join
//A logic to detect wheather this tester starts working
always @(posedge CLK)
clk_detect <= ~clk_detect;
always @(negedge CLK)
clk_detect_p <= clk_detect;
assign clk_detected = clk_detect ^ clk_detect_p;
always @(negedge CLK)
begin
if (RST) WORKING <= 1'b0;
else WORKING <= clk_detected;
end
//Inframe logic, for handling multicycle sof and eof
always @(posedge CLK)
if(RST) inframe <= #GLOBALDLY 1'b0;
else if(!inframe) inframe <= #GLOBALDLY !RX_SRC_RDY_N & !RX_SOF_N & RX_EOF_N;
else if( inframe & !RX_SRC_RDY_N & !RX_EOF_N)
inframe <= #GLOBALDLY 1'b0;
wire inframe_full; // for single data-beat frame
assign inframe_full = inframe | !RX_SRC_RDY_N & !RX_SOF_N & !RX_EOF_N | !RX_SRC_RDY_N & !RX_SOF_N & RX_EOF_N;
//Put dut data into dut Fifo
always @(posedge CLK)
if(!RST & !RX_SRC_RDY_N)
begin
if(RX_EOF_N) dut_data[0:LL_DAT_BIT_WIDTH-1] = RX_D;
else
begin
dut_data = 0;
dut_data[0:7] = RX_D[0:7];
for(index1 = 0; index1 < LL_DAT_BIT_WIDTH/8-1; index1 = index1 + 1) begin
if(RX_REM>index1) begin
case (index1)
0: dut_data[8:15] = RX_D_i[8:15];
1: dut_data[16:23] = RX_D_i[16:23];
2: dut_data[24:31] = RX_D_i[24:31];
3: dut_data[32:39] = RX_D_i[32:39];
4: dut_data[40:47] = RX_D_i[40:47];
5: dut_data[48:55] = RX_D_i[48:55];
6: dut_data[56:63] = RX_D_i[56:63];
7: dut_data[64:71] = RX_D_i[64:71];
8: dut_data[72:79] = RX_D_i[72:79];
9: dut_data[72:79] = RX_D_i[72:79];
10: dut_data[80:87] = RX_D_i[80:87];
11: dut_data[88:95] = RX_D_i[88:95];
12: dut_data[96:103] = RX_D_i[96:103];
13: dut_data[104:111] = RX_D_i[104:111];
14: dut_data[112:119] = RX_D_i[112:119];
15: dut_data[120:127] = RX_D_i[120:127];
endcase
end
end
end
if(inframe_full)
begin
dut_data[LL_DAT_BIT_WIDTH] = RX_SOF_N & !inframe_full;
dut_data[LL_DAT_BIT_WIDTH+1] = RX_EOF_N;
dut_data_fifo[dut_index] = dut_data;
dut_index = dut_index+1;
end
end
//Put ufc data into ufc Fifo
always @(posedge CLK)
if(!RST & !UFC_RX_SRC_RDY_N)
begin
if(!UFC_RX_EOF_N)
begin
//dut_ufc_data = 64'h0000000000000000;
dut_ufc_data = 0;
dut_ufc_data[0:15] = UFC_RX_DATA[0:15];
for(index2 = 1; index2 < LL_DAT_BIT_WIDTH/8-1; index2 = index2 + 2) begin
if(UFC_RX_REM>index2) begin
case (index2)
1: dut_ufc_data[16:31] = UFC_RX_DATA_i[16:31];
3: dut_ufc_data[32:47] = UFC_RX_DATA_i[32:47];
5: dut_ufc_data[48:63] = UFC_RX_DATA_i[48:63];
7: dut_ufc_data[64:79] = UFC_RX_DATA_i[64:79];
9: dut_ufc_data[80:95] = UFC_RX_DATA_i[80:95];
11: dut_ufc_data[96:111] = UFC_RX_DATA_i[96:111];
13: dut_ufc_data[112:127] = UFC_RX_DATA_i[112:127];
endcase
end
end
end
else
begin
dut_ufc_data[0:LL_DAT_BIT_WIDTH-1] = UFC_RX_DATA;
end
dut_ufc_data[LL_DAT_BIT_WIDTH] = UFC_RX_SOF_N;
dut_ufc_data[LL_DAT_BIT_WIDTH+1] = UFC_RX_EOF_N;
dut_ufc_fifo[dut_ufc_index] = dut_ufc_data;
dut_ufc_index = dut_ufc_index + 1;
end
//Reference Inframe logic, for handling multicycle sof and eof
always @(posedge CLK)
if(RST) inframe_ref <= #GLOBALDLY 1'b0;
else if(!inframe_ref) inframe_ref <= #GLOBALDLY !RX_SRC_RDY_N_REF & !RX_SOF_N_REF & RX_EOF_N_REF;
else if( inframe_ref & !RX_SRC_RDY_N_REF & !RX_EOF_N_REF)
inframe_ref <= #GLOBALDLY 1'b0;
wire inframe_ref_full; // for single data-beat frame
assign inframe_ref_full = inframe_ref | !RX_SRC_RDY_N_REF & !RX_SOF_N_REF & !RX_EOF_N_REF | !RX_SRC_RDY_N_REF & !RX_SOF_N_REF & RX_EOF_N_REF;
//Put reference data into reference Fifo
always @(posedge CLK)
begin
if(!RST & !RX_SRC_RDY_N_REF)
begin
if(RX_EOF_N_REF) ref_data[0:LL_DAT_BIT_WIDTH-1] = RX_DATA_REF;
else
begin
//ref_data = 64'h0000000000000000;
ref_data = 0;
ref_data[0:7] = RX_DATA_REF[0:7];
for(index3 = 0; index3 < LL_DAT_BIT_WIDTH/8-1; index3 = index3 + 1) begin
if(RX_REM_REF>index3) begin
case (index3)
0: ref_data[8:15] = RX_DATA_REF_i[8:15];
1: ref_data[16:23] = RX_DATA_REF_i[16:23];
2: ref_data[24:31] = RX_DATA_REF_i[24:31];
3: ref_data[32:39] = RX_DATA_REF_i[32:39];
4: ref_data[40:47] = RX_DATA_REF_i[40:47];
5: ref_data[48:55] = RX_DATA_REF_i[48:55];
6: ref_data[56:63] = RX_DATA_REF_i[56:63];
7: ref_data[64:71] = RX_DATA_REF_i[64:71];
8: ref_data[72:79] = RX_DATA_REF_i[72:79];
9: ref_data[72:79] = RX_DATA_REF_i[72:79];
10: ref_data[80:87] = RX_DATA_REF_i[80:87];
11: ref_data[88:95] = RX_DATA_REF_i[88:95];
12: ref_data[96:103] = RX_DATA_REF_i[96:103];
13: ref_data[104:111] = RX_DATA_REF_i[104:111];
14: ref_data[112:119] = RX_DATA_REF_i[112:119];
15: ref_data[120:127] = RX_DATA_REF_i[120:127];
endcase
end
end
end
if(inframe_ref_full)
begin
ref_data[LL_DAT_BIT_WIDTH] = RX_SOF_N_REF & !inframe_ref_full;
ref_data[LL_DAT_BIT_WIDTH+1] = RX_EOF_N_REF;
ref_data_fifo[ref_index] = ref_data;
ref_index = ref_index+1;
end
end
end
//Put ufc data into ufc Fifo
always @(posedge CLK)
if(!RST & !UFC_RX_SRC_RDY_N_REF)
begin
if(!UFC_RX_EOF_N_REF)
begin
//ref_ufc_data = 64'h0000000000000000;
ref_ufc_data = 0;
ref_ufc_data[0:15] = UFC_RX_DATA_REF[0:15];
for(index4 = 1; index4 < LL_DAT_BIT_WIDTH/8-1; index4 = index4 + 2) begin
if(UFC_RX_REM_REF>index4) begin
case (index4)
1: ref_ufc_data[16:31] = UFC_RX_DATA_REF_i[16:31];
3: ref_ufc_data[32:47] = UFC_RX_DATA_REF_i[32:47];
5: ref_ufc_data[48:63] = UFC_RX_DATA_REF_i[48:63];
7: ref_ufc_data[64:79] = UFC_RX_DATA_REF_i[64:79];
9: ref_ufc_data[80:95] = UFC_RX_DATA_REF_i[80:95];
11: ref_ufc_data[96:111] = UFC_RX_DATA_REF_i[96:111];
13: ref_ufc_data[112:127] = UFC_RX_DATA_REF_i[112:127];
endcase
end
end
end
else
begin
ref_ufc_data[0:LL_DAT_BIT_WIDTH-1] = UFC_RX_DATA_REF;
end
ref_ufc_data[LL_DAT_BIT_WIDTH] = UFC_RX_SOF_N_REF;
ref_ufc_data[LL_DAT_BIT_WIDTH+1] = UFC_RX_EOF_N_REF;
ref_ufc_fifo[ref_ufc_index] = ref_ufc_data;
ref_ufc_index = ref_ufc_index + 1;
end
//Compare the data from the 2 LocalLink Fifos
always @(negedge CLK)
begin
if( ref_index >FIFO_DEPTH-1 | dut_index >FIFO_DEPTH-1 ) // overflow
begin
RESULT_GOOD_PDU = #GLOBALDLY 1'b0;
COMPARING = #GLOBALDLY 1'b0;
OVERFLOW = #GLOBALDLY 1'b1;
end
else if( ref_index>0 & dut_index>0 )
begin
COMPARING = #GLOBALDLY 1'b1;
dut_data = dut_data_fifo[0];
ref_data = ref_data_fifo[0];
if( dut_data != ref_data ) RESULT_GOOD_PDU = #GLOBALDLY 1'b0;
else RESULT_GOOD_PDU = #GLOBALDLY 1'b1;
for(shuffle=0;shuffle<dut_index;shuffle = shuffle + 1)
dut_data_fifo[shuffle] = dut_data_fifo[shuffle+1];
for(shuffle=0;shuffle<ref_index;shuffle = shuffle + 1)
ref_data_fifo[shuffle] = ref_data_fifo[shuffle+1];
dut_index = dut_index-1;
ref_index = ref_index-1;
end
else if (ref_ufc_index ==0 | dut_ufc_index ==0)
begin
COMPARING = #GLOBALDLY 1'b0;
end
end
//Compare the data from the 2 UFC Fifos
always @(negedge CLK)
begin
if( ref_ufc_index >FIFO_DEPTH-1 | dut_ufc_index >FIFO_DEPTH-1 )
begin
RESULT_GOOD_UFC = #GLOBALDLY 1'b0;
end
else if( ref_ufc_index>0 & dut_ufc_index>0 )
begin
dut_ufc_data = dut_ufc_fifo[0];
ref_ufc_data = ref_ufc_fifo[0];
if( dut_ufc_data != ref_ufc_data ) RESULT_GOOD_UFC = #GLOBALDLY 1'b0;
else RESULT_GOOD_UFC = #GLOBALDLY 1'b1;
for(shuffle=0;shuffle<dut_ufc_index;shuffle = shuffle + 1)
dut_ufc_fifo[shuffle] = dut_ufc_fifo[shuffle+1];
for(shuffle=0;shuffle<ref_ufc_index;shuffle = shuffle + 1)
ref_ufc_fifo[shuffle] = ref_ufc_fifo[shuffle+1];
dut_ufc_index = dut_ufc_index-1;
ref_ufc_index = ref_ufc_index-1;
end
end
always @(RESULT_GOOD_PDU or RESULT_GOOD_UFC)
begin
RESULT_GOOD = #GLOBALDLY RESULT_GOOD_UFC & RESULT_GOOD_PDU;
end
endmodule
//-----------------------------------------------------------------------------
// History:
// NG 5/15/03 Modified the USER_IF_TESTER to create this module
// DH 6/12/03 Added COMPARING and WORKING outputs, Make it support
// 16,32,64,128 data widths
// DH 12/17/04 Fixed in_frame_full bug that omits the SOF data beat.
//-----------------------------------------------------------------------------
// $Revision: 1.2 $
// $Date: 2004/12/27 18:12:18 $
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/cpu.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* 6502 core implementation.
***************************************************************************************************/
module cpu (
input wire clk_in, // 100MHz system clock
input wire rst_in, // reset signal
input wire ready_in, // ready signal
// Interrupt lines.
input wire nnmi_in, // /nmi interrupt signal (active low)
input wire nres_in, // /res interrupt signal (console reset, active low)
input wire nirq_in, // /irq intterupt signal (active low)
// Memory bus.
input wire [ 7:0] d_in, // data input bus
output wire [ 7:0] d_out, // data output bus
output wire [15:0] a_out, // address bus
output reg r_nw_out, // R/!W signal
// Debug support.
input wire [ 3:0] dbgreg_sel_in, // dbg reg select
input wire [ 7:0] dbgreg_in, // dbg reg write input
input wire dbgreg_wr_in, // dbg reg rd/wr select
output reg [ 7:0] dbgreg_out, // dbg reg read output
output reg brk_out // debug break signal
);
// dbgreg_sel defines. Selects register for read/write through the debugger block.
`define REGSEL_PCL 0
`define REGSEL_PCH 1
`define REGSEL_AC 2
`define REGSEL_X 3
`define REGSEL_Y 4
`define REGSEL_P 5
`define REGSEL_S 6
// Opcodes.
localparam [7:0] ADC_ABS = 8'h6D, ADC_ABSX = 8'h7D, ADC_ABSY = 8'h79, ADC_IMM = 8'h69,
ADC_INDX = 8'h61, ADC_INDY = 8'h71, ADC_ZP = 8'h65,
ADC_ZPX = 8'h75,
AND_ABS = 8'h2D, AND_ABSX = 8'h3D, AND_ABSY = 8'h39, AND_IMM = 8'h29,
AND_INDX = 8'h21, AND_INDY = 8'h31, AND_ZP = 8'h25,
AND_ZPX = 8'h35,
ASL_ABS = 8'h0E, ASL_ABSX = 8'h1E, ASL_ACC = 8'h0A, ASL_ZP = 8'h06,
ASL_ZPX = 8'h16,
BCC = 8'h90,
BCS = 8'hB0,
BEQ = 8'hF0,
BIT_ABS = 8'h2C, BIT_ZP = 8'h24,
BMI = 8'h30,
BNE = 8'hD0,
BPL = 8'h10,
BRK = 8'h00,
BVC = 8'h50,
BVS = 8'h70,
CLC = 8'h18,
CLD = 8'hD8,
CLI = 8'h58,
CLV = 8'hB8,
CMP_ABS = 8'hCD, CMP_ABSX = 8'hDD, CMP_ABSY = 8'hD9, CMP_IMM = 8'hC9,
CMP_INDX = 8'hC1, CMP_INDY = 8'hD1, CMP_ZP = 8'hC5,
CMP_ZPX = 8'hD5,
CPX_ABS = 8'hEC, CPX_IMM = 8'hE0, CPX_ZP = 8'hE4,
CPY_ABS = 8'hCC, CPY_IMM = 8'hC0, CPY_ZP = 8'hC4,
DEC_ABS = 8'hCE, DEC_ABSX = 8'hDE, DEC_ZP = 8'hC6, DEC_ZPX = 8'hD6,
DEX = 8'hCA,
DEY = 8'h88,
EOR_ABS = 8'h4D, EOR_ABSX = 8'h5D, EOR_ABSY = 8'h59, EOR_IMM = 8'h49,
EOR_INDX = 8'h41, EOR_INDY = 8'h51, EOR_ZP = 8'h45,
EOR_ZPX = 8'h55,
HLT = 8'h02,
INC_ABS = 8'hEE, INC_ABSX = 8'hFE, INC_ZP = 8'hE6, INC_ZPX = 8'hF6,
INX = 8'hE8,
INY = 8'hC8,
JMP_ABS = 8'h4C, JMP_IND = 8'h6C,
JSR = 8'h20,
LDA_ABS = 8'hAD, LDA_ABSX = 8'hBD, LDA_ABSY = 8'hB9, LDA_IMM = 8'hA9,
LDA_INDX = 8'hA1, LDA_INDY = 8'hB1, LDA_ZP = 8'hA5,
LDA_ZPX = 8'hB5,
LDX_ABS = 8'hAE, LDX_ABSY = 8'hBE, LDX_IMM = 8'hA2, LDX_ZP = 8'hA6,
LDX_ZPY = 8'hB6,
LDY_ABS = 8'hAC, LDY_ABSX = 8'hBC, LDY_IMM = 8'hA0, LDY_ZP = 8'hA4,
LDY_ZPX = 8'hB4,
LSR_ABS = 8'h4E, LSR_ABSX = 8'h5E, LSR_ACC = 8'h4A, LSR_ZP = 8'h46,
LSR_ZPX = 8'h56,
NOP = 8'hEA,
ORA_ABS = 8'h0D, ORA_ABSX = 8'h1D, ORA_ABSY = 8'h19, ORA_IMM = 8'h09,
ORA_INDX = 8'h01, ORA_INDY = 8'h11, ORA_ZP = 8'h05,
ORA_ZPX = 8'h15,
PHA = 8'h48,
PHP = 8'h08,
PLA = 8'h68,
PLP = 8'h28,
ROL_ABS = 8'h2E, ROL_ABSX = 8'h3E, ROL_ACC = 8'h2A, ROL_ZP = 8'h26,
ROL_ZPX = 8'h36,
ROR_ABS = 8'h6E, ROR_ABSX = 8'h7E, ROR_ACC = 8'h6A, ROR_ZP = 8'h66,
ROR_ZPX = 8'h76,
RTI = 8'h40,
RTS = 8'h60,
SAX_ABS = 8'h8F, SAX_INDX = 8'h83, SAX_ZP = 8'h87, SAX_ZPY = 8'h97,
SBC_ABS = 8'hED, SBC_ABSX = 8'hFD, SBC_ABSY = 8'hF9, SBC_IMM = 8'hE9,
SBC_INDX = 8'hE1, SBC_INDY = 8'hF1, SBC_ZP = 8'hE5,
SBC_ZPX = 8'hF5,
SEC = 8'h38,
SED = 8'hF8,
SEI = 8'h78,
STA_ABS = 8'h8D, STA_ABSX = 8'h9D, STA_ABSY = 8'h99, STA_INDX = 8'h81,
STA_INDY = 8'h91, STA_ZP = 8'h85, STA_ZPX = 8'h95,
STX_ABS = 8'h8E, STX_ZP = 8'h86, STX_ZPY = 8'h96,
STY_ABS = 8'h8C, STY_ZP = 8'h84, STY_ZPX = 8'h94,
TAX = 8'hAA,
TAY = 8'hA8,
TSX = 8'hBA,
TXA = 8'h8A,
TXS = 8'h9A,
TYA = 8'h98;
// Macro to check if a value is a valid opcode.
`define IS_VALID_OPCODE(op) \
(((op) == ADC_ABS ) || ((op) == ADC_ABSX) || ((op) == ADC_ABSY) || ((op) == ADC_IMM ) || \
((op) == ADC_INDX) || ((op) == ADC_INDY) || ((op) == ADC_ZP ) || ((op) == ADC_ZPX ) || \
((op) == AND_ABS ) || ((op) == AND_ABSX) || ((op) == AND_ABSY) || ((op) == AND_IMM ) || \
((op) == AND_INDX) || ((op) == AND_INDY) || ((op) == AND_ZP ) || ((op) == AND_ZPX ) || \
((op) == ASL_ABS ) || ((op) == ASL_ABSX) || ((op) == ASL_ACC ) || ((op) == ASL_ZP ) || \
((op) == ASL_ZPX ) || ((op) == BCC ) || ((op) == BCS ) || ((op) == BEQ ) || \
((op) == BIT_ABS ) || ((op) == BIT_ZP ) || ((op) == BMI ) || ((op) == BNE ) || \
((op) == BPL ) || ((op) == BRK ) || ((op) == BVC ) || ((op) == BVS ) || \
((op) == CLC ) || ((op) == CLD ) || ((op) == CLI ) || ((op) == CLV ) || \
((op) == CMP_ABS ) || ((op) == CMP_ABSX) || ((op) == CMP_ABSY) || ((op) == CMP_IMM ) || \
((op) == CMP_INDX) || ((op) == CMP_INDY) || ((op) == CMP_ZP ) || ((op) == CMP_ZPX ) || \
((op) == CPX_ABS ) || ((op) == CPX_IMM ) || ((op) == CPX_ZP ) || ((op) == CPY_ABS ) || \
((op) == CPY_IMM ) || ((op) == CPY_ZP ) || ((op) == DEC_ABS ) || ((op) == DEC_ABSX) || \
((op) == DEC_ZP ) || ((op) == DEC_ZPX ) || ((op) == DEX ) || ((op) == DEY ) || \
((op) == EOR_ABS ) || ((op) == EOR_ABSX) || ((op) == EOR_ABSY) || ((op) == EOR_IMM ) || \
((op) == EOR_INDX) || ((op) == EOR_INDY) || ((op) == EOR_ZP ) || ((op) == EOR_ZPX ) || \
((op) == HLT ) || ((op) == INC_ABS ) || ((op) == INC_ABSX) || ((op) == INC_ZP ) || \
((op) == INC_ZPX ) || ((op) == INX ) || ((op) == INY ) || ((op) == JMP_ABS ) || \
((op) == JMP_IND ) || ((op) == JSR ) || ((op) == LDA_ABS ) || ((op) == LDA_ABSX) || \
((op) == LDA_ABSY) || ((op) == LDA_IMM ) || ((op) == LDA_INDX) || ((op) == LDA_INDY) || \
((op) == LDA_ZP ) || ((op) == LDA_ZPX ) || ((op) == LDX_ABS ) || ((op) == LDX_ABSY) || \
((op) == LDX_IMM ) || ((op) == LDX_ZP ) || ((op) == LDX_ZPY ) || ((op) == LDY_ABS ) || \
((op) == LDY_ABSX) || ((op) == LDY_IMM ) || ((op) == LDY_ZP ) || ((op) == LDY_ZPX ) || \
((op) == LSR_ABS ) || ((op) == LSR_ABSX) || ((op) == LSR_ACC ) || ((op) == LSR_ZP ) || \
((op) == LSR_ZPX ) || ((op) == NOP ) || ((op) == ORA_ABS ) || ((op) == ORA_ABSX) || \
((op) == ORA_ABSY) || ((op) == ORA_IMM ) || ((op) == ORA_INDX) || ((op) == ORA_INDY) || \
((op) == ORA_ZP ) || ((op) == ORA_ZPX ) || ((op) == PHA ) || ((op) == PHP ) || \
((op) == PLA ) || ((op) == PLP ) || ((op) == ROL_ABS ) || ((op) == ROL_ABSX) || \
((op) == ROL_ACC ) || ((op) == ROL_ZP ) || ((op) == ROL_ZPX ) || ((op) == ROR_ABS ) || \
((op) == ROR_ABSX) || ((op) == ROR_ACC ) || ((op) == ROR_ZP ) || ((op) == ROR_ZPX ) || \
((op) == RTI ) || ((op) == RTS ) || ((op) == SAX_ABS ) || ((op) == SAX_INDX) || \
((op) == SAX_ZP ) || ((op) == SAX_ZPY ) || ((op) == SBC_ABS ) || ((op) == SBC_ABSX) || \
((op) == SBC_ABSY) || ((op) == SBC_IMM ) || ((op) == SBC_INDX) || ((op) == SBC_INDY) || \
((op) == SBC_ZP ) || ((op) == SBC_ZPX ) || ((op) == SEC ) || ((op) == SED ) || \
((op) == SEI ) || ((op) == STA_ABS ) || ((op) == STA_ABSX) || ((op) == STA_ABSY) || \
((op) == STA_INDX) || ((op) == STA_INDY) || ((op) == STA_ZP ) || ((op) == STA_ZPX ) || \
((op) == STX_ABS ) || ((op) == STX_ZP ) || ((op) == STX_ZPY ) || ((op) == STY_ABS ) || \
((op) == STY_ZP ) || ((op) == STY_ZPX ) || ((op) == TAX ) || ((op) == TAY ) || \
((op) == TSX ) || ((op) == TXA ) || ((op) == TXS ) || ((op) == TYA ))
// Timing generation cycle states.
localparam [2:0] T0 = 3'h0,
T1 = 3'h1,
T2 = 3'h2,
T3 = 3'h3,
T4 = 3'h4,
T5 = 3'h5,
T6 = 3'h6;
// Interrupt types.
localparam [1:0] INTERRUPT_RST = 2'h0,
INTERRUPT_NMI = 2'h1,
INTERRUPT_IRQ = 2'h2,
INTERRUPT_BRK = 2'h3;
// User registers.
reg [7:0] q_ac; // accumulator register
wire [7:0] d_ac;
reg [7:0] q_x; // x index register
wire [7:0] d_x;
reg [7:0] q_y; // y index register
wire [7:0] d_y;
// Processor status register.
wire [7:0] p; // full processor status reg, grouped from the following FFs
reg q_c; // carry flag
wire d_c;
reg q_d; // decimal mode flag
wire d_d;
reg q_i; // interrupt disable flag
wire d_i;
reg q_n; // negative flag
wire d_n;
reg q_v; // overflow flag
wire d_v;
reg q_z; // zero flag
wire d_z;
// Internal registers.
reg [7:0] q_abh; // address bus high register
wire [7:0] d_abh;
reg [7:0] q_abl; // address bus low register
wire [7:0] d_abl;
reg q_acr; // internal carry latch
reg [7:0] q_add; // adder hold register
reg [7:0] d_add;
reg [7:0] q_ai; // alu input register a
wire [7:0] d_ai;
reg [7:0] q_bi; // alu input register b
wire [7:0] d_bi;
reg [7:0] q_dl; // input data latch
wire [7:0] d_dl;
reg [7:0] q_dor; // data output register
wire [7:0] d_dor;
reg [7:0] q_ir; // instruction register
reg [7:0] d_ir;
reg [7:0] q_pch; // program counter high register
wire [7:0] d_pch;
reg [7:0] q_pcl; // program counter low register
wire [7:0] d_pcl;
reg [7:0] q_pchs; // program counter high select register
wire [7:0] d_pchs;
reg [7:0] q_pcls; // program counter low select register
wire [7:0] d_pcls;
reg [7:0] q_pd; // pre-decode register
wire [7:0] d_pd;
reg [7:0] q_s; // stack pointer register
wire [7:0] d_s;
reg [2:0] q_t; // timing cycle register
reg [2:0] d_t;
// Internal buses.
wire [7:0] adl; // ADL bus
wire [7:0] adh_in, // ADH bus
adh_out;
wire [7:0] db_in, // DB bus
db_out;
wire [7:0] sb_in, // SB bus
sb_out;
//
// Internal control signals. These names are all taken directly from the original 6502 block
// diagram.
//
wire zero_adl0;
wire zero_adl1;
wire zero_adl2;
// ADL bus drive enables.
wire add_adl; // output adder hold register to adl bus
wire dl_adl; // output dl reg to adl bus
wire pcl_adl; // output pcl reg to adl bus
wire s_adl; // output s reg to adl bus
// ADH bus drive enables.
wire dl_adh; // output dl reg to adh bus
wire pch_adh; // output pch reg to adh bus
wire zero_adh0; // output 0 to bit 0 of adh bus
wire zero_adh17; // output 0 to bits 1-7 of adh bus
// DB bus drive enables.
wire ac_db; // output ac reg to db bus
wire dl_db; // output dl reg to db bus
wire p_db; // output p reg to db bus
wire pch_db; // output pch reg to db bus
wire pcl_db; // output pcl reg to db bus
// SB bus drive enables.
wire ac_sb; // output ac reg to sb bus
wire add_sb; // output add reg to sb bus
wire x_sb; // output x reg to sb bus
wire y_sb; // output y reg to sb bus
wire s_sb; // output s reg to sb bus
// Pass MOSFET controls.
wire sb_adh; // controls sb/adh pass mosfet
wire sb_db; // controls sb/db pass mosfet
// Register LOAD controls.
wire adh_abh; // latch adh bus value in abh reg
wire adl_abl; // latch adl bus value in abl reg
wire sb_ac; // latch sb bus value in ac reg
wire adl_add; // latch adl bus value in bi reg
wire db_add; // latch db bus value in bi reg
wire invdb_add; // latch ~db value in bi reg
wire sb_add; // latch sb bus value in ai reg
wire zero_add; // latch 0 into ai reg
wire adh_pch; // latch adh bus value in pch reg
wire adl_pcl; // latch adl bus value in pcl reg
wire sb_s; // latch sb bus value in s reg
wire sb_x; // latch sb bus value in x reg
wire sb_y; // latch sb bus value in y reg
// Processor status controls.
wire acr_c; // latch acr into c status reg
wire db0_c; // latch db[0] into c status reg
wire ir5_c; // latch ir[5] into c status reg
wire db3_d; // latch db[3] into d status reg
wire ir5_d; // latch ir[5] into d status reg
wire db2_i; // latch db[2] into i status reg
wire ir5_i; // latch ir[5] into i status reg
wire db7_n; // latch db[7] into n status reg
wire avr_v; // latch avr into v status reg
wire db6_v; // latch db[6] into v status reg
wire zero_v; // latch 0 into v status reg
wire db1_z; // latch db[1] into z status reg
wire dbz_z; // latch ~|db into z status reg
// Misc. controls.
wire i_pc; // increment pc
// ALU controls, signals.
wire ands; // perform bitwise and on alu
wire eors; // perform bitwise xor on alu
wire ors; // perform bitwise or on alu
wire sums; // perform addition on alu
wire srs; // perform right bitshift
wire addc; // carry in
reg acr; // carry out
reg avr; // overflow out
//
// Ready Control.
//
wire rdy; // internal, modified ready signal.
reg q_ready; // latch external ready signal to delay 1 clk so top-level addr muxing can complete
always @(posedge clk_in)
begin
if (rst_in)
q_ready <= 1'b0;
else
q_ready <= ready_in;
end
assign rdy = ready_in && q_ready;
//
// Clock phase generation logic.
//
reg [5:0] q_clk_phase;
wire [5:0] d_clk_phase;
always @(posedge clk_in)
begin
if (rst_in)
q_clk_phase <= 6'h01;
else if (rdy)
q_clk_phase <= d_clk_phase;
// If the debugger writes a PC register, this is a partial reset: the cycle is set to
// T0, and the clock phase should be set to the beginning of the 4 clock cycle.
else if (dbgreg_wr_in && ((dbgreg_sel_in == `REGSEL_PCH) || (dbgreg_sel_in == `REGSEL_PCL)))
q_clk_phase <= 6'h01;
end
assign d_clk_phase = (q_clk_phase == 6'h37) ? 6'h00 : q_clk_phase + 6'h01;
//
// Interrupt and Reset Control.
//
reg [1:0] q_irq_sel, d_irq_sel; // interrupt selected for service
reg q_rst; // rst interrupt needs to be serviced
wire d_rst;
reg q_nres; // latch last nres input signal for falling edge detection
reg q_nmi; // nmi interrupt needs to be serviced
wire d_nmi;
reg q_nnmi; // latch last nnmi input signal for falling edge detection
reg clear_rst; // clear rst interrupt
reg clear_nmi; // clear nmi interrupt
reg force_noinc_pc; // override stage-0 PC increment
always @(posedge clk_in)
begin
if (rst_in)
begin
q_irq_sel <= INTERRUPT_RST;
q_rst <= 1'b0;
q_nres <= 1'b1;
q_nmi <= 1'b0;
q_nnmi <= 1'b1;
end
else if (q_clk_phase == 6'h00)
begin
q_irq_sel <= d_irq_sel;
q_rst <= d_rst;
q_nres <= nres_in;
q_nmi <= d_nmi;
q_nnmi <= nnmi_in;
end
end
assign d_rst = (clear_rst) ? 1'b0 :
(!nres_in && q_nres) ? 1'b1 :
q_rst;
assign d_nmi = (clear_nmi) ? 1'b0 :
(!nnmi_in && q_nnmi) ? 1'b1 :
q_nmi;
//
// Update phase-1 clocked registers.
//
always @(posedge clk_in)
begin
if (rst_in)
begin
q_ac <= 8'h00;
q_x <= 8'h00;
q_y <= 8'h00;
q_c <= 1'b0;
q_d <= 1'b0;
q_i <= 1'b0;
q_n <= 1'b0;
q_v <= 1'b0;
q_z <= 1'b0;
q_abh <= 8'h80;
q_abl <= 8'h00;
q_acr <= 1'b0;
q_ai <= 8'h00;
q_bi <= 8'h00;
q_dor <= 8'h00;
q_ir <= NOP;
q_pchs <= 8'h80;
q_pcls <= 8'h00;
q_s <= 8'hFF;
q_t <= T1;
end
else if (rdy && (q_clk_phase == 6'h00))
begin
q_ac <= d_ac;
q_x <= d_x;
q_y <= d_y;
q_c <= d_c;
q_d <= d_d;
q_i <= d_i;
q_n <= d_n;
q_v <= d_v;
q_z <= d_z;
q_abh <= d_abh;
q_abl <= d_abl;
q_acr <= acr;
q_ai <= d_ai;
q_bi <= d_bi;
q_dor <= d_dor;
q_ir <= d_ir;
q_pchs <= d_pchs;
q_pcls <= d_pcls;
q_s <= d_s;
q_t <= d_t;
end
else if (!rdy)
begin
// Update registers based on debug register write packets.
if (dbgreg_wr_in)
begin
q_ac <= (dbgreg_sel_in == `REGSEL_AC) ? dbgreg_in : q_ac;
q_x <= (dbgreg_sel_in == `REGSEL_X) ? dbgreg_in : q_x;
q_y <= (dbgreg_sel_in == `REGSEL_Y) ? dbgreg_in : q_y;
q_c <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[0] : q_c;
q_d <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[3] : q_d;
q_i <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[2] : q_i;
q_n <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[7] : q_n;
q_v <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[6] : q_v;
q_z <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[1] : q_z;
// Treat the debugger writing PC registers as a partial reset. Set the cycle to T0,
// and setup the address bus so the first opcode fill be fetched as soon as rdy is
// asserted again.
q_pchs <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_pchs;
q_pcls <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_pcls;
q_abh <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_abh;
q_abl <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_abl;
q_t <= ((dbgreg_sel_in == `REGSEL_PCH) || (dbgreg_sel_in == `REGSEL_PCL)) ? T0 : q_t;
end
end
end
//
// Update phase-2 clocked registers.
//
always @(posedge clk_in)
begin
if (rst_in)
begin
q_pcl <= 8'h00;
q_pch <= 8'h80;
q_dl <= 8'h00;
q_pd <= 8'h00;
q_add <= 8'h00;
end
else if (rdy && (q_clk_phase == 6'h1C))
begin
q_pcl <= d_pcl;
q_pch <= d_pch;
q_dl <= d_dl;
q_pd <= d_pd;
q_add <= d_add;
end
else if (!rdy && dbgreg_wr_in)
begin
// Update registers based on debug register write packets.
q_pcl <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_pcl;
q_pch <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_pch;
end
end
//
// Timing Generation Logic
//
always @*
begin
d_t = T0;
d_irq_sel = q_irq_sel;
force_noinc_pc = 1'b0;
case (q_t)
T0:
d_t = T1;
T1:
begin
// These instructions are in their last cycle but do not prefetch.
if ((q_ir == CLC) || (q_ir == CLD) || (q_ir == CLI) || (q_ir == CLV) ||
(q_ir == HLT) || (q_ir == LDA_IMM) || (q_ir == LDX_IMM) || (q_ir == LDY_IMM) ||
(q_ir == NOP) || (q_ir == SEC) || (q_ir == SED) || (q_ir == SEI) ||
(q_ir == TAX) || (q_ir == TAY) || (q_ir == TSX) || (q_ir == TXA) ||
(q_ir == TXS) || (q_ir == TYA))
begin
d_t = T0;
end
// Check for not-taken branches. These instructions must setup the not-taken PC during
// T1, and we can move to T0 of the next instruction.
else if (((q_ir == BCC) && q_c) || ((q_ir == BCS) && !q_c) ||
((q_ir == BPL) && q_n) || ((q_ir == BMI) && !q_n) ||
((q_ir == BVC) && q_v) || ((q_ir == BVS) && !q_v) ||
((q_ir == BNE) && q_z) || ((q_ir == BEQ) && !q_z))
begin
d_t = T0;
end
else
begin
d_t = T2;
end
end
T2:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_IMM) || (q_ir == AND_IMM) || (q_ir == ASL_ACC) || (q_ir == CMP_IMM) ||
(q_ir == CPX_IMM) || (q_ir == CPY_IMM) || (q_ir == DEX) || (q_ir == DEY) ||
(q_ir == EOR_IMM) || (q_ir == INX) || (q_ir == INY) || (q_ir == LSR_ACC) ||
(q_ir == ORA_IMM) || (q_ir == ROL_ACC) || (q_ir == ROR_ACC) || (q_ir == SBC_IMM))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == JMP_ABS) || (q_ir == LDA_ZP) || (q_ir == LDX_ZP) || (q_ir == LDY_ZP) ||
(q_ir == SAX_ZP) || (q_ir == STA_ZP) || (q_ir == STX_ZP) || (q_ir == STY_ZP))
begin
d_t = T0;
end
// For ops using relative absolute addressing modes, we can skip stage 3 if the result
// doesn't cross a page boundary (i.e., don't need to add 1 to the high byte).
else if (!acr && ((q_ir == ADC_ABSX) || (q_ir == ADC_ABSY) || (q_ir == AND_ABSX) ||
(q_ir == AND_ABSY) || (q_ir == CMP_ABSX) || (q_ir == CMP_ABSY) ||
(q_ir == EOR_ABSX) || (q_ir == EOR_ABSY) || (q_ir == LDA_ABSX) ||
(q_ir == LDA_ABSY) || (q_ir == ORA_ABSX) || (q_ir == ORA_ABSY) ||
(q_ir == SBC_ABSX) || (q_ir == SBC_ABSY)))
begin
d_t = T4;
end
// For relative addressing ops (branches), we can skip stage 3 if the new PC doesn't
// cross a page boundary (forward or backward).
else if ((acr == q_ai[7]) && ((q_ir == BCC) || (q_ir == BCS) || (q_ir == BEQ) ||
(q_ir == BMI) || (q_ir == BNE) || (q_ir == BPL) ||
(q_ir == BVC) || (q_ir == BVS)))
begin
d_t = T0;
end
else
begin
d_t = T3;
end
end
T3:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ZP) || (q_ir == AND_ZP) || (q_ir == BIT_ZP) || (q_ir == CMP_ZP) ||
(q_ir == CPX_ZP) || (q_ir == CPY_ZP) || (q_ir == EOR_ZP) || (q_ir == ORA_ZP) ||
(q_ir == PHA) || (q_ir == PHP) || (q_ir == SBC_ZP))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == BCC) || (q_ir == BCS) || (q_ir == BEQ) ||
(q_ir == BMI) || (q_ir == BNE) || (q_ir == BPL) ||
(q_ir == BVC) || (q_ir == BVS) || (q_ir == LDA_ABS) ||
(q_ir == LDA_ZPX) || (q_ir == LDX_ABS) || (q_ir == LDX_ZPY) ||
(q_ir == LDY_ABS) || (q_ir == LDY_ZPX) || (q_ir == PLA) ||
(q_ir == PLP) || (q_ir == SAX_ABS) || (q_ir == SAX_ZPY) ||
(q_ir == STA_ABS) || (q_ir == STA_ZPX) || (q_ir == STX_ABS) ||
(q_ir == STX_ZPY) || (q_ir == STY_ABS) || (q_ir == STY_ZPX))
begin
d_t = T0;
end
// For loads using (indirect),Y addressing modes, we can skip stage 4 if the result
// doesn't cross a page boundary (i.e., don't need to add 1 to the high byte).
else if (!acr && ((q_ir == ADC_INDY) || (q_ir == AND_INDY) || (q_ir == CMP_INDY) ||
(q_ir == EOR_INDY) || (q_ir == LDA_INDY) ||
(q_ir == ORA_INDY) || (q_ir == SBC_INDY)))
begin
d_t = T5;
end
else
begin
d_t = T4;
end
end
T4:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ABS) || (q_ir == ADC_ZPX) || (q_ir == AND_ABS) || (q_ir == AND_ZPX) ||
(q_ir == BIT_ABS) || (q_ir == CMP_ABS) || (q_ir == CMP_ZPX) || (q_ir == CPX_ABS) ||
(q_ir == CPY_ABS) || (q_ir == EOR_ABS) || (q_ir == EOR_ZPX) || (q_ir == ORA_ABS) ||
(q_ir == ORA_ZPX) || (q_ir == SBC_ABS) || (q_ir == SBC_ZPX))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == ASL_ZP) || (q_ir == DEC_ZP) || (q_ir == INC_ZP) ||
(q_ir == JMP_IND) || (q_ir == LDA_ABSX) || (q_ir == LDA_ABSY) ||
(q_ir == LDX_ABSY) || (q_ir == LDY_ABSX) || (q_ir == LSR_ZP) ||
(q_ir == ROL_ZP) || (q_ir == ROR_ZP) || (q_ir == STA_ABSX) ||
(q_ir == STA_ABSY))
begin
d_t = T0;
end
else
begin
d_t = T5;
end
end
T5:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ABSX) || (q_ir == ADC_ABSY) || (q_ir == AND_ABSX) ||
(q_ir == AND_ABSY) || (q_ir == CMP_ABSX) || (q_ir == CMP_ABSY) ||
(q_ir == EOR_ABSX) || (q_ir == EOR_ABSY) || (q_ir == ORA_ABSX) ||
(q_ir == ORA_ABSY) || (q_ir == SBC_ABSX) || (q_ir == SBC_ABSY))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == ASL_ABS) || (q_ir == ASL_ZPX) || (q_ir == DEC_ABS) ||
(q_ir == DEC_ZPX) || (q_ir == INC_ABS) || (q_ir == INC_ZPX) ||
(q_ir == JSR) || (q_ir == LDA_INDX) || (q_ir == LDA_INDY) ||
(q_ir == LSR_ABS) || (q_ir == LSR_ZPX) || (q_ir == ROL_ABS) ||
(q_ir == ROL_ZPX) || (q_ir == ROR_ABS) || (q_ir == ROR_ZPX) ||
(q_ir == RTI) || (q_ir == RTS) || (q_ir == SAX_INDX) ||
(q_ir == STA_INDX) || (q_ir == STA_INDY))
begin
d_t = T0;
end
else
begin
d_t = T6;
end
end
T6:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_INDX) || (q_ir == ADC_INDY) || (q_ir == AND_INDX) ||
(q_ir == AND_INDY) || (q_ir == CMP_INDX) || (q_ir == CMP_INDY) ||
(q_ir == EOR_INDX) || (q_ir == EOR_INDY) || (q_ir == ORA_INDX) ||
(q_ir == ORA_INDY) || (q_ir == SBC_INDX) || (q_ir == SBC_INDY))
begin
d_t = T1;
end
else
begin
d_t = T0;
end
end
endcase
// Update IR register on cycle 1, otherwise retain current IR.
if (d_t == T1)
begin
if (q_rst || q_nmi || !nirq_in)
begin
d_ir = BRK;
force_noinc_pc = 1'b1;
if (q_rst)
d_irq_sel = INTERRUPT_RST;
else if (q_nmi)
d_irq_sel = INTERRUPT_NMI;
else
d_irq_sel = INTERRUPT_IRQ;
end
else
begin
d_ir = q_pd;
d_irq_sel = INTERRUPT_BRK;
end
end
else
begin
d_ir = q_ir;
end
end
//
// Decode ROM output signals. Corresponds to 130 bit bus coming out of the Decode ROM in the
// block diagram, although the details of implementation will differ.
//
// PC and program stream controls.
reg load_prg_byte; // put PC on addr bus and increment PC (adh, adl)
reg load_prg_byte_noinc; // put PC on addr bus only (adh, adl)
reg incpc_noload; // increment PC only (-)
reg alusum_to_pch; // load pch with ai+bi (adh, sb)
reg dl_to_pch; // load pch with current data latch register (adh)
reg alusum_to_pcl; // load pcl with ai+bi (adl)
reg s_to_pcl; // load pcl with s (adl)
// Instruction-specific controls. Typically triggers the meat of a particular operation that
// occurs regardless of addressing mode.
reg adc_op; // final cycle of an adc inst (db, sb)
reg and_op; // final cycle of an and inst (db, sb)
reg asl_acc_op; // perform asl_acc inst (db, sb)
reg asl_mem_op; // perform meat of asl inst for memory addressing modes (db, sb)
reg bit_op; // final cycle of a bit inst (db, sb)
reg cmp_op; // final cycle of a cmp inst (db, sb)
reg clc_op; // clear carry bit (-)
reg cld_op; // clear decimal mode bit (-)
reg cli_op; // clear interrupt disable bit (-)
reg clv_op; // clear overflow bit (-)
reg dec_op; // perform meat of dec inst (db, sb)
reg dex_op; // final cycle of a dex inst (db, sb)
reg dey_op; // final cycle of a dey inst (db, sb)
reg eor_op; // final cycle of an eor inst (db, sb)
reg inc_op; // perform meat of inc inst (db, sb)
reg inx_op; // final cycle of an inx inst (db, sb)
reg iny_op; // final cycle of an iny inst (db, sb)
reg lda_op; // final cycle of an lda inst (db, sb)
reg ldx_op; // final cycle of an ldx inst (db, sb)
reg ldy_op; // final cycle of an ldy inst (db, sb)
reg lsr_acc_op; // perform lsr_acc inst (db, sb)
reg lsr_mem_op; // perform meat of lsr inst for memory addressing modes (db, sb)
reg ora_op; // final cycle of an ora inst (db, sb)
reg rol_acc_op; // perform rol_acc inst (db, sb)
reg rol_mem_op; // perform meat of rol inst for memory addressing modes (db, sb)
reg ror_acc_op; // perform ror_acc inst (db, sb)
reg ror_mem_op; // perform meat of ror inst for memory addressing modes (db, sb)
reg sec_op; // set carry bit (-)
reg sed_op; // set decimal mode bit (-)
reg sei_op; // set interrupt disable bit (-)
reg tax_op; // transfer ac to x (db, sb)
reg tay_op; // transfer ac to y (db, sb)
reg tsx_op; // transfer s to x (db, sb)
reg txa_op; // transfer x to z (db, sb)
reg txs_op; // transfer x to s (db, sb)
reg tya_op; // transfer y to a (db, sb)
// DOR (data output register) load controls.
reg ac_to_dor; // load current ac value into dor (db)
reg p_to_dor; // load current p value into dor (db)
reg pch_to_dor; // load current pch value into dor (db)
reg pcl_to_dor; // load current pcl value into dor (db)
reg x_to_dor; // load current x value into dor (db, sb)
reg y_to_dor; // load current y value into dor (db, sb)
// AB (address bus hold registers) load controls.
reg aluinc_to_abh; // load abh with ai+bi+1 (adh, sb)
reg alusum_to_abh; // load abh with ai+bi (adh, sb)
reg dl_to_abh; // load abh with dl (adh)
reg ff_to_abh; // load abh with 8'hff (adh)
reg one_to_abh; // load abh with 8'h01 (adh)
reg zero_to_abh; // load abh with 8'h00 (adh)
reg aluinc_to_abl; // load abl with ai+bi+1 (adl)
reg alusum_to_abl; // load abl with ai+bi (adl)
reg dl_to_abl; // load abl with dl (adl)
reg fa_to_abl; // load abl with 8'hfa (adl)
reg fb_to_abl; // load abl with 8'hfb (adl)
reg fc_to_abl; // load abl with 8'hfc (adl)
reg fd_to_abl; // load abl with 8'hfd (adl)
reg fe_to_abl; // load abl with 8'hfe (adl)
reg ff_to_abl; // load abl with 8'hff (adl)
reg s_to_abl; // load abl with s (adl)
// AI/BI (ALU input registers) load controls.
reg ac_to_ai; // load ai with ac (sb)
reg dl_to_ai; // load ai with dl (db, sb)
reg one_to_ai; // load ai with 1 (adh, sb)
reg neg1_to_ai; // load ai with -1 (sb)
reg s_to_ai; // load ai with s (sb)
reg x_to_ai; // load ai with x (sb)
reg y_to_ai; // load ai with y (sb)
reg zero_to_ai; // load ai with 0 (sb)
reg ac_to_bi; // load bi with ac (db)
reg aluinc_to_bi; // load bi with ai+bi+1 (adl)
reg alusum_to_bi; // load bi with ai+bi (adl)
reg dl_to_bi; // load bi with dl (db)
reg invdl_to_bi; // load bi with ~dl (db)
reg neg1_to_bi; // load bi with -1 (db)
reg pch_to_bi; // load bi with pch (db)
reg pcl_to_bi; // load bi with pcl (adl)
reg s_to_bi; // load bi with s (adl)
reg x_to_bi; // load bi with x (db, sb)
reg y_to_bi; // load bi with y (db, sb)
// Stack related controls.
reg aluinc_to_s; // load ai+bi+1 into s (sb)
reg alusum_to_s; // load ai+bi into s (sb)
reg dl_to_s; // load s with current data latch register (db, sb)
// Process status register controls.
reg dl_bits67_to_p; // latch bits 6 and 7 into P V and N bits (db)
reg dl_to_p; // load dl into p (db)
reg one_to_i; // used to supress irqs while processing an interrupt
// Sets all decode ROM output signals to the specified value (0 for init, X for con't care states.
`define SET_ALL_CONTROL_SIGNALS(val) \
load_prg_byte = (val); \
load_prg_byte_noinc = (val); \
incpc_noload = (val); \
alusum_to_pch = (val); \
dl_to_pch = (val); \
alusum_to_pcl = (val); \
s_to_pcl = (val); \
\
adc_op = (val); \
and_op = (val); \
asl_acc_op = (val); \
asl_mem_op = (val); \
bit_op = (val); \
cmp_op = (val); \
clc_op = (val); \
cld_op = (val); \
cli_op = (val); \
clv_op = (val); \
dec_op = (val); \
dex_op = (val); \
dey_op = (val); \
eor_op = (val); \
inc_op = (val); \
inx_op = (val); \
iny_op = (val); \
lda_op = (val); \
ldx_op = (val); \
ldy_op = (val); \
lsr_acc_op = (val); \
lsr_mem_op = (val); \
ora_op = (val); \
rol_acc_op = (val); \
rol_mem_op = (val); \
ror_acc_op = (val); \
ror_mem_op = (val); \
sec_op = (val); \
sed_op = (val); \
sei_op = (val); \
tax_op = (val); \
tay_op = (val); \
tsx_op = (val); \
txa_op = (val); \
txs_op = (val); \
tya_op = (val); \
\
ac_to_dor = (val); \
p_to_dor = (val); \
pch_to_dor = (val); \
pcl_to_dor = (val); \
x_to_dor = (val); \
y_to_dor = (val); \
\
aluinc_to_abh = (val); \
alusum_to_abh = (val); \
dl_to_abh = (val); \
ff_to_abh = (val); \
one_to_abh = (val); \
zero_to_abh = (val); \
aluinc_to_abl = (val); \
alusum_to_abl = (val); \
dl_to_abl = (val); \
fa_to_abl = (val); \
fb_to_abl = (val); \
fc_to_abl = (val); \
fd_to_abl = (val); \
fe_to_abl = (val); \
ff_to_abl = (val); \
s_to_abl = (val); \
\
ac_to_ai = (val); \
dl_to_ai = (val); \
one_to_ai = (val); \
neg1_to_ai = (val); \
s_to_ai = (val); \
x_to_ai = (val); \
y_to_ai = (val); \
zero_to_ai = (val); \
ac_to_bi = (val); \
aluinc_to_bi = (val); \
alusum_to_bi = (val); \
dl_to_bi = (val); \
invdl_to_bi = (val); \
neg1_to_bi = (val); \
pch_to_bi = (val); \
pcl_to_bi = (val); \
s_to_bi = (val); \
x_to_bi = (val); \
y_to_bi = (val); \
\
aluinc_to_s = (val); \
alusum_to_s = (val); \
dl_to_s = (val); \
\
dl_to_p = (val); \
dl_bits67_to_p = (val); \
one_to_i = (val);
//
// Decode ROM logic.
//
always @*
begin
// Default all control signals to 0.
`SET_ALL_CONTROL_SIGNALS(1'b0)
// Defaults for output signals.
r_nw_out = 1'b1;
brk_out = 1'b0;
clear_rst = 1'b0;
clear_nmi = 1'b0;
if (q_t == T0)
begin
load_prg_byte = 1'b1;
end
else if (q_t == T1)
begin
case (q_ir)
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS,
INC_ABS, JMP_ABS, JMP_IND, LDA_ABS, LDX_ABS, LDY_ABS, LSR_ABS,
ORA_ABS, ROL_ABS, ROR_ABS, SAX_ABS, SBC_ABS,
STA_ABS, STX_ABS, STY_ABS:
begin
load_prg_byte = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX, STA_ABSX:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY, LDX_ABSY,
ORA_ABSY, SBC_ABSY, STA_ABSY:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_IMM, AND_IMM, EOR_IMM, ORA_IMM:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, SBC_INDX, STA_INDX,
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX,
EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX,
LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX, SBC_ZPX,
STA_ZPX, STY_ZPX:
begin
x_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, AND_ZP, ASL_ZP, BIT_ZP, CMP_ZP, CPX_ZP, CPY_ZP, DEC_ZP,
EOR_ZP, INC_ZP, LDA_ZP, LDX_ZP, LDY_ZP, LSR_ZP, ORA_ZP,
ROL_ZP, ROR_ZP, SBC_ZP:
begin
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC:
begin
ac_to_ai = 1'b1;
ac_to_bi = 1'b1;
end
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
load_prg_byte = 1'b1;
dl_to_ai = 1'b1;
pcl_to_bi = 1'b1;
end
BRK:
begin
if (q_irq_sel == INTERRUPT_BRK)
incpc_noload = 1'b1;
pch_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
neg1_to_ai = 1'b1;
s_to_bi = 1'b1;
end
CLC:
clc_op = 1'b1;
CLD:
cld_op = 1'b1;
CLI:
cli_op = 1'b1;
CLV:
clv_op = 1'b1;
CMP_IMM, SBC_IMM:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPX_IMM:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_IMM:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEX:
begin
x_to_ai = 1'b1;
neg1_to_bi = 1'b1;
end
DEY:
begin
y_to_ai = 1'b1;
neg1_to_bi = 1'b1;
end
HLT:
begin
// The HLT instruction asks hci to deassert the rdy signal, effectively pausing the
// cpu and allowing the debug block to inspect the internal state.
brk_out = (q_clk_phase == 6'h01) && rdy;
end
INX:
begin
zero_to_ai = 1'b1;
x_to_bi = 1'b1;
end
INY:
begin
zero_to_ai = 1'b1;
y_to_bi = 1'b1;
end
JSR:
begin
incpc_noload = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
s_to_bi = 1'b1;
dl_to_s = 1'b1;
end
LDX_ZPY, SAX_ZPY, STX_ZPY:
begin
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
LDA_IMM:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_IMM:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_IMM:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
PHA:
begin
ac_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
end
PHP:
begin
p_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
end
PLA, PLP, RTI, RTS:
begin
zero_to_ai = 1'b1;
s_to_bi = 1'b1;
end
SEC:
sec_op = 1'b1;
SED:
sed_op = 1'b1;
SEI:
sei_op = 1'b1;
SAX_ZP:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STA_ZP:
begin
ac_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STX_ZP:
begin
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STY_ZP:
begin
y_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
TAX:
tax_op = 1'b1;
TAY:
tay_op = 1'b1;
TSX:
tsx_op = 1'b1;
TXA:
txa_op = 1'b1;
TXS:
txs_op = 1'b1;
TYA:
tya_op = 1'b1;
endcase
end
else if (q_t == T2)
begin
case (q_ir)
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS,
INC_ABS, LDA_ABS, LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS,
ROL_ABS, ROR_ABS, SBC_ABS,
JMP_IND:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX, STA_ABSX,
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY,
LDX_ABSY, ORA_ABSY, SBC_ABSY,
STA_ABSY:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_IMM, SBC_IMM:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, SBC_INDX, STA_INDX,
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX,
EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX,
LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX, SBC_ZPX,
LDX_ZPY:
begin
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
zero_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, AND_ZP, EOR_ZP, ORA_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
AND_IMM:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ACC:
begin
load_prg_byte = 1'b1;
asl_acc_op = 1'b1;
end
ASL_ZP, LSR_ZP, ROL_ZP, ROR_ZP:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
LSR_ACC:
begin
load_prg_byte = 1'b1;
lsr_acc_op = 1'b1;
end
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
alusum_to_pcl = 1'b1;
alusum_to_abl = 1'b1;
if (q_ai[7])
neg1_to_ai = 1'b1;
else
one_to_ai = 1'b1;
pch_to_bi = 1'b1;
end
BIT_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
dl_bits67_to_p = 1'b1;
end
BRK:
begin
pcl_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
CMP_IMM, CPX_IMM, CPY_IMM:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_ZP, SBC_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPX_ZP:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_ZP:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ZP:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
DEX:
begin
load_prg_byte = 1'b1;
dex_op = 1'b1;
end
DEY:
begin
load_prg_byte = 1'b1;
dey_op = 1'b1;
end
EOR_IMM:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ZP:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
INX:
begin
load_prg_byte = 1'b1;
inx_op = 1'b1;
end
INY:
begin
load_prg_byte = 1'b1;
iny_op = 1'b1;
end
JMP_ABS:
begin
dl_to_pch = 1'b1;
alusum_to_pcl = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
JSR:
begin
pch_to_dor = 1'b1;
neg1_to_ai = 1'b1;
end
LDA_ZP:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ZP:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ZP:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
ORA_IMM:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
PHA, PHP:
begin
load_prg_byte_noinc = 1'b1;
s_to_ai = 1'b1;
neg1_to_bi = 1'b1;
r_nw_out = 1'b0;
end
PLA, PLP:
begin
one_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
aluinc_to_s = 1'b1;
end
ROL_ACC:
begin
load_prg_byte = 1'b1;
rol_acc_op = 1'b1;
end
ROR_ACC:
begin
load_prg_byte = 1'b1;
ror_acc_op = 1'b1;
end
RTI, RTS:
begin
one_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
aluinc_to_bi = 1'b1;
end
SAX_ABS:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
SAX_ZP, STA_ZP, STX_ZP, STY_ZP:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
SAX_ZPY:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_ABS:
begin
ac_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_ZPX:
begin
ac_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STX_ABS:
begin
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STX_ZPY:
begin
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STY_ABS:
begin
y_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STY_ZPX:
begin
y_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
endcase
end
else if (q_t == T3)
begin
case (q_ir)
ADC_ABS, AND_ABS, EOR_ABS, ORA_ABS,
ADC_ZPX, AND_ZPX, EOR_ZPX, ORA_ZPX:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX,
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY,
LDX_ABSY, ORA_ABSY, SBC_ABSY:
begin
aluinc_to_abh = q_acr;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, STA_INDX, SBC_INDX:
begin
zero_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, SBC_ZP:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
AND_ZP:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS, LSR_ABS, ROL_ABS, ROR_ABS,
ASL_ZPX, LSR_ZPX, ROL_ZPX, ROR_ZPX:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ASL_ZP:
asl_mem_op = 1'b1;
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
alusum_to_pch = 1'b1;
alusum_to_abh = 1'b1;
end
BIT_ABS:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
dl_bits67_to_p = 1'b1;
end
BIT_ZP:
begin
load_prg_byte = 1'b1;
bit_op = 1'b1;
end
BRK:
begin
p_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
CMP_ABS, SBC_ABS,
CMP_ZPX, SBC_ZPX:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CMP_ZP, CPX_ZP, CPY_ZP:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CPX_ABS:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_ABS:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABS,
DEC_ZPX:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
DEC_ZP:
dec_op = 1'b1;
EOR_ZP:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABS,
INC_ZPX:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
INC_ZP:
inc_op = 1'b1;
JMP_IND:
begin
aluinc_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
JSR:
begin
pcl_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
LDA_ABS, LDA_ZPX:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ABS, LDX_ZPY:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ABS, LDY_ZPX:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
LSR_ZP:
lsr_mem_op = 1'b1;
ORA_ZP:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
PHA, PHP:
begin
load_prg_byte = 1'b1;
alusum_to_s = 1'b1;
end
PLA:
begin
load_prg_byte_noinc = 1'b1;
lda_op = 1'b1;
end
PLP:
begin
load_prg_byte_noinc = 1'b1;
dl_to_p = 1'b1;
end
ROL_ZP:
rol_mem_op = 1'b1;
ROR_ZP:
ror_mem_op = 1'b1;
RTI:
begin
aluinc_to_abl = 1'b1;
aluinc_to_bi = 1'b1;
dl_to_p = 1'b1;
end
RTS:
begin
aluinc_to_abl = 1'b1;
dl_to_s = 1'b1;
end
SAX_ABS, STA_ABS, STX_ABS, STY_ABS,
STA_ZPX, STY_ZPX,
SAX_ZPY, STX_ZPY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
STA_ABSX,
STA_ABSY:
begin
ac_to_dor = 1'b1;
aluinc_to_abh = q_acr;
end
endcase
end
else if (q_t == T4)
begin
case (q_ir)
ADC_ABS, SBC_ABS,
ADC_ZPX, SBC_ZPX:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_ABSX, AND_ABSX, EOR_ABSX, ORA_ABSX,
ADC_ABSY, AND_ABSY, EOR_ABSY, ORA_ABSY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SBC_INDX:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY:
begin
aluinc_to_abh = q_acr;
end
AND_ABS,
AND_ZPX:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS,
ASL_ZPX:
asl_mem_op = 1'b1;
ASL_ZP, DEC_ZP, INC_ZP, LSR_ZP, ROL_ZP, ROR_ZP,
STA_ABSX,
STA_ABSY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
ASL_ABSX, LSR_ABSX, ROL_ABSX, ROR_ABSX:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
BIT_ABS:
begin
load_prg_byte = 1'b1;
bit_op = 1'b1;
end
BRK:
begin
ff_to_abh = 1'b1;
r_nw_out = 1'b0;
one_to_i = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: fc_to_abl = 1'b1;
INTERRUPT_NMI: fa_to_abl = 1'b1;
INTERRUPT_IRQ, INTERRUPT_BRK: fe_to_abl = 1'b1;
endcase
end
CMP_ABS, CPX_ABS, CPY_ABS,
CMP_ZPX:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_ABSX, SBC_ABSX,
CMP_ABSY, SBC_ABSY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABS,
DEC_ZPX:
dec_op = 1'b1;
DEC_ABSX:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
EOR_ABS,
EOR_ZPX:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABS,
INC_ZPX:
inc_op = 1'b1;
INC_ABSX:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
JMP_IND:
begin
dl_to_pch = 1'b1;
alusum_to_pcl = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
JSR:
begin
load_prg_byte_noinc = 1'b1;
r_nw_out = 1'b0;
end
LDA_ABSX,
LDA_ABSY:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ABSY:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ABSX:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
LSR_ABS,
LSR_ZPX:
lsr_mem_op = 1'b1;
ORA_ABS,
ORA_ZPX:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
ROL_ABS,
ROL_ZPX:
rol_mem_op = 1'b1;
ROR_ABS,
ROR_ZPX:
ror_mem_op = 1'b1;
RTI:
begin
aluinc_to_abl = 1'b1;
dl_to_s = 1'b1;
end
RTS:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
aluinc_to_s = 1'b1;
end
SAX_INDX:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_INDX:
begin
ac_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_INDY:
begin
ac_to_dor = 1'b1;
aluinc_to_abh = q_acr;
end
endcase
end
else if (q_t == T5)
begin
case (q_ir)
ADC_ABSX, SBC_ABSX,
ADC_ABSY, SBC_ABSY:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_INDX, AND_INDX, EOR_INDX, ORA_INDX,
ADC_INDY, AND_INDY, EOR_INDY, ORA_INDY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
AND_ABSX,
AND_ABSY:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS, DEC_ABS, INC_ABS, LSR_ABS, ROL_ABS, ROR_ABS,
ASL_ZPX, DEC_ZPX, INC_ZPX, LSR_ZPX, ROL_ZPX, ROR_ZPX,
SAX_INDX, STA_INDX,
STA_INDY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
ASL_ABSX:
asl_mem_op = 1'b1;
BRK:
begin
ff_to_abh = 1'b1;
dl_to_s = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: fd_to_abl = 1'b1;
INTERRUPT_NMI: fb_to_abl = 1'b1;
INTERRUPT_IRQ, INTERRUPT_BRK: ff_to_abl = 1'b1;
endcase
end
CMP_ABSX,
CMP_ABSY:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_INDX, SBC_INDX,
CMP_INDY, SBC_INDY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABSX:
dec_op = 1'b1;
EOR_ABSX,
EOR_ABSY:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABSX:
inc_op = 1'b1;
JSR:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
alusum_to_s = 1'b1;
end
LDA_INDX,
LDA_INDY:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LSR_ABSX:
lsr_mem_op = 1'b1;
ORA_ABSX,
ORA_ABSY:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
ROL_ABSX:
rol_mem_op = 1'b1;
ROR_ABSX:
ror_mem_op = 1'b1;
RTI:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
aluinc_to_s = 1'b1;
end
RTS:
load_prg_byte = 1'b1;
endcase
end
else if (q_t == T6)
begin
case (q_ir)
ADC_INDX, SBC_INDX,
ADC_INDY, SBC_INDY:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
AND_INDX,
AND_INDY:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABSX, DEC_ABSX, INC_ABSX, LSR_ABSX, ROL_ABSX, ROR_ABSX:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
BRK:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
alusum_to_s = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: clear_rst = 1'b1;
INTERRUPT_NMI: clear_nmi = 1'b1;
endcase
end
CMP_INDX,
CMP_INDY:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
EOR_INDX,
EOR_INDY:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
ORA_INDX,
ORA_INDY:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
endcase
end
end
//
// ALU
//
always @*
begin
acr = 1'b0;
avr = 1'b0;
if (ands)
d_add = q_ai & q_bi;
else if (eors)
d_add = q_ai ^ q_bi;
else if (ors)
d_add = q_ai | q_bi;
else if (sums)
begin
{ acr, d_add } = q_ai + q_bi + addc;
avr = ((q_ai[7] ^ q_bi[7]) ^ d_add[7]) ^ acr;
end
else if (srs)
{ d_add, acr } = { addc, q_bi };
else
d_add = q_add;
end
//
// Random Control Logic
//
assign add_adl = aluinc_to_abl | aluinc_to_bi | alusum_to_abl |
alusum_to_bi | alusum_to_pcl;
assign dl_adl = dl_to_abl;
assign pcl_adl = load_prg_byte | load_prg_byte_noinc |
pcl_to_bi;
assign s_adl = s_to_abl | s_to_bi | s_to_pcl;
assign zero_adl0 = fa_to_abl | fc_to_abl | fe_to_abl;
assign zero_adl1 = fc_to_abl | fd_to_abl;
assign zero_adl2 = fa_to_abl | fb_to_abl;
assign dl_adh = dl_to_abh | dl_to_pch;
assign pch_adh = load_prg_byte | load_prg_byte_noinc;
assign zero_adh0 = zero_to_abh;
assign zero_adh17 = one_to_abh | one_to_ai | zero_to_abh;
assign ac_db = ac_to_bi | ac_to_dor;
assign dl_db = dl_to_ai | dl_to_bi |
dl_to_p | dl_to_s | invdl_to_bi |
lda_op | ldx_op | ldy_op;
assign p_db = p_to_dor;
assign pch_db = pch_to_bi | pch_to_dor;
assign pcl_db = pcl_to_dor;
assign ac_sb = ac_to_ai | tax_op | tay_op;
assign add_sb = adc_op | aluinc_to_abh |
aluinc_to_s | alusum_to_abh | alusum_to_pch |
alusum_to_s | and_op |
asl_acc_op | asl_mem_op | bit_op |
cmp_op | dec_op | dex_op |
dey_op | eor_op | inc_op |
inx_op | iny_op | lsr_acc_op |
lsr_mem_op | ora_op | rol_acc_op |
rol_mem_op | ror_acc_op | ror_mem_op;
assign x_sb = txa_op | txs_op | x_to_ai |
x_to_bi | x_to_dor;
assign y_sb = tya_op | y_to_ai | y_to_bi |
y_to_dor;
assign s_sb = s_to_ai | tsx_op;
assign sb_adh = aluinc_to_abh | alusum_to_abh | alusum_to_pch |
one_to_ai | one_to_i;
assign sb_db = adc_op |
and_op | asl_acc_op |
asl_mem_op | bit_op | cmp_op |
dl_to_s | dec_op | dex_op |
dey_op | dl_to_ai | eor_op |
inc_op | inx_op | iny_op |
lda_op | ldx_op | ldy_op |
lsr_acc_op | lsr_mem_op | one_to_i |
ora_op | rol_acc_op | rol_mem_op |
ror_acc_op | ror_mem_op | tax_op |
tay_op | tsx_op | txa_op |
tya_op | x_to_bi | x_to_dor |
y_to_bi | y_to_dor;
assign adh_abh = aluinc_to_abh | alusum_to_abh | dl_to_abh |
ff_to_abh | load_prg_byte | load_prg_byte_noinc |
one_to_abh | zero_to_abh;
assign adl_abl = aluinc_to_abl | alusum_to_abl | dl_to_abl |
fa_to_abl | fb_to_abl | fc_to_abl |
fd_to_abl | fe_to_abl | ff_to_abl |
load_prg_byte | load_prg_byte_noinc |
s_to_abl;
assign adl_add = aluinc_to_bi | alusum_to_bi | pcl_to_bi |
s_to_bi;
assign db_add = ac_to_bi | dl_to_bi |
neg1_to_bi | pch_to_bi | x_to_bi |
y_to_bi;
assign invdb_add = invdl_to_bi;
assign sb_s = aluinc_to_s | alusum_to_s | dl_to_s |
txs_op;
assign zero_add = zero_to_ai;
assign sb_ac = adc_op | and_op |
asl_acc_op | eor_op |
lda_op | lsr_acc_op | ora_op |
rol_acc_op | ror_acc_op | txa_op |
tya_op;
assign sb_add = ac_to_ai | dl_to_ai | neg1_to_ai |
one_to_ai | s_to_ai | x_to_ai |
y_to_ai;
assign adh_pch = alusum_to_pch | dl_to_pch;
assign adl_pcl = alusum_to_pcl | s_to_pcl;
assign sb_x = dex_op | inx_op | ldx_op |
tax_op | tsx_op;
assign sb_y = dey_op | iny_op | ldy_op |
tay_op;
assign acr_c = adc_op | asl_acc_op | asl_mem_op |
cmp_op | lsr_acc_op | lsr_mem_op |
rol_acc_op | rol_mem_op | ror_acc_op |
ror_mem_op;
assign db0_c = dl_to_p;
assign ir5_c = clc_op | sec_op;
assign db3_d = dl_to_p;
assign ir5_d = cld_op | sed_op;
assign db2_i = dl_to_p | one_to_i;
assign ir5_i = cli_op | sei_op;
assign db7_n = adc_op | and_op |
asl_acc_op | asl_mem_op |
cmp_op | dec_op | dex_op |
dey_op | dl_bits67_to_p | dl_to_p |
eor_op | inc_op | inx_op |
iny_op | lda_op | ldx_op |
ldy_op | lsr_acc_op | lsr_mem_op |
ora_op | rol_acc_op | rol_mem_op |
ror_acc_op | ror_mem_op | tax_op |
tay_op | tsx_op | txa_op |
tya_op;
assign avr_v = adc_op;
assign db6_v = dl_bits67_to_p | dl_to_p;
assign zero_v = clv_op;
assign db1_z = dl_to_p;
assign dbz_z = adc_op | and_op |
asl_acc_op | asl_mem_op |
bit_op | cmp_op | dec_op |
dex_op | dey_op | eor_op |
inc_op | inx_op | iny_op |
lda_op | ldx_op | ldy_op |
lsr_acc_op | lsr_mem_op | ora_op |
rol_acc_op | rol_mem_op | ror_acc_op |
ror_mem_op | tax_op | tay_op |
tsx_op | txa_op | tya_op;
assign ands = and_op | bit_op;
assign eors = eor_op;
assign ors = ora_op;
assign sums = adc_op | aluinc_to_abh | aluinc_to_abl |
aluinc_to_bi | aluinc_to_s |
alusum_to_abh | alusum_to_abl | alusum_to_bi |
alusum_to_pch | alusum_to_pcl | alusum_to_s |
asl_acc_op | asl_mem_op | cmp_op |
dec_op | dex_op | dey_op |
inc_op | inx_op | iny_op |
rol_acc_op | rol_mem_op;
assign srs = lsr_acc_op | lsr_mem_op |
ror_acc_op | ror_mem_op;
assign addc = (adc_op | rol_acc_op | rol_mem_op | ror_acc_op | ror_mem_op) ? q_c :
aluinc_to_abh | aluinc_to_abl | aluinc_to_bi |
aluinc_to_s | cmp_op |
inc_op | inx_op | iny_op;
assign i_pc = (incpc_noload | load_prg_byte) & !force_noinc_pc;
//
// Update internal buses. Use in/out to replicate pass mosfets and avoid using internal
// tristate buffers.
//
assign adh_in[7:1] = (dl_adh) ? q_dl[7:1] :
(pch_adh) ? q_pch[7:1] :
(zero_adh17) ? 7'h00 : 7'h7F;
assign adh_in[0] = (dl_adh) ? q_dl[0] :
(pch_adh) ? q_pch[0] :
(zero_adh0) ? 1'b0 : 1'b1;
assign adl[7:3] = (add_adl) ? q_add[7:3] :
(dl_adl) ? q_dl[7:3] :
(pcl_adl) ? q_pcl[7:3] :
(s_adl) ? q_s[7:3] : 5'h1F;
assign adl[2] = (add_adl) ? q_add[2] :
(dl_adl) ? q_dl[2] :
(pcl_adl) ? q_pcl[2] :
(s_adl) ? q_s[2] :
(zero_adl2) ? 1'b0 : 1'b1;
assign adl[1] = (add_adl) ? q_add[1] :
(dl_adl) ? q_dl[1] :
(pcl_adl) ? q_pcl[1] :
(s_adl) ? q_s[1] :
(zero_adl1) ? 1'b0 : 1'b1;
assign adl[0] = (add_adl) ? q_add[0] :
(dl_adl) ? q_dl[0] :
(pcl_adl) ? q_pcl[0] :
(s_adl) ? q_s[0] :
(zero_adl0) ? 1'b0 : 1'b1;
assign db_in = 8'hFF & ({8{~ac_db}} | q_ac) &
({8{~dl_db}} | q_dl) &
({8{~p_db}} | p) &
({8{~pch_db}} | q_pch) &
({8{~pcl_db}} | q_pcl);
assign sb_in = 8'hFF & ({8{~ac_sb}} | q_ac) &
({8{~add_sb}} | q_add) &
({8{~s_sb}} | q_s) &
({8{~x_sb}} | q_x) &
({8{~y_sb}} | q_y);
assign adh_out = (sb_adh & sb_db) ? (adh_in & sb_in & db_in) :
(sb_adh) ? (adh_in & sb_in) :
(adh_in);
assign db_out = (sb_db & sb_adh) ? (db_in & sb_in & adh_in) :
(sb_db) ? (db_in & sb_in) :
(db_in);
assign sb_out = (sb_adh & sb_db) ? (sb_in & db_in & adh_in) :
(sb_db) ? (sb_in & db_in) :
(sb_adh) ? (sb_in & adh_in) :
(sb_in);
//
// Assign next FF states.
//
assign d_ac = (sb_ac) ? sb_out : q_ac;
assign d_x = (sb_x) ? sb_out : q_x;
assign d_y = (sb_y) ? sb_out : q_y;
assign d_c = (acr_c) ? acr :
(db0_c) ? db_out[0] :
(ir5_c) ? q_ir[5] : q_c;
assign d_d = (db3_d) ? db_out[3] :
(ir5_d) ? q_ir[5] : q_d;
assign d_i = (db2_i) ? db_out[2] :
(ir5_i) ? q_ir[5] : q_i;
assign d_n = (db7_n) ? db_out[7] : q_n;
assign d_v = (avr_v) ? avr :
(db6_v) ? db_out[6] :
(zero_v) ? 1'b0 : q_v;
assign d_z = (db1_z) ? db_out[1] :
(dbz_z) ? ~|db_out : q_z;
assign d_abh = (adh_abh) ? adh_out : q_abh;
assign d_abl = (adl_abl) ? adl : q_abl;
assign d_ai = (sb_add) ? sb_out :
(zero_add) ? 8'h0 : q_ai;
assign d_bi = (adl_add) ? adl :
(db_add) ? db_out :
(invdb_add) ? ~db_out : q_bi;
assign d_dl = (r_nw_out) ? d_in : q_dl;
assign d_dor = db_out;
assign d_pd = (r_nw_out) ? d_in : q_pd;
assign d_s = (sb_s) ? sb_out : q_s;
assign d_pchs = (adh_pch) ? adh_out : q_pch;
assign d_pcls = (adl_pcl) ? adl : q_pcl;
assign { d_pch, d_pcl } = (i_pc) ? { q_pchs, q_pcls } + 16'h0001 : { q_pchs, q_pcls };
// Combine full processor status register.
assign p = { q_n, q_v, 1'b1, (q_irq_sel == INTERRUPT_BRK), q_d, q_i, q_z, q_c };
//
// Assign output signals.
//
assign d_out = q_dor;
assign a_out = { q_abh, q_abl };
always @*
begin
case (dbgreg_sel_in)
`REGSEL_AC: dbgreg_out = q_ac;
`REGSEL_X: dbgreg_out = q_x;
`REGSEL_Y: dbgreg_out = q_y;
`REGSEL_P: dbgreg_out = p;
`REGSEL_PCH: dbgreg_out = q_pch;
`REGSEL_PCL: dbgreg_out = q_pcl;
`REGSEL_S: dbgreg_out = q_s;
default: dbgreg_out = 8'hxx;
endcase
end
endmodule
|
module single_cycle(input clk,input enable,output LED1,output reg LED2,LED3);
reg [32:0] cnt = 0;
reg number=0;
reg start=0;
reg stop=0;
reg reset=0;
wire debug1,debug2;
single_cycle_top sc(number,reset,debug1,debug2);
always @(negedge enable,posedge stop)begin
if(stop)
start=0;
else begin
if(!enable)
start=1;
else
start=0;
end
end
always @(posedge clk)begin
cnt <= cnt + 1'b1;
end
always @(posedge cnt[4]) begin // normal is 21
if(!start) begin
number=0;
stop=0;
reset=1;
end else begin
reset=0;
number = ~number;
if(debug1&&debug2)
stop=1;
end
end
always @(debug1, debug2,start) begin
if(start) begin
LED2=~debug1;
LED3=~debug2;
end
end
assign LED1 = !number;
endmodule
module single_cycle_tp(input clk,reset,output y,z);
reg [3:0]cnt;
assign y=cnt[2];
assign z=cnt[3];
always@(negedge clk,posedge reset) begin
if(reset)
cnt<=0;
else
cnt<=cnt+1'b1;
end
endmodule
module single_cycle_top(clk,reset,debug1,debug2);
input clk;
input reset;
output reg debug1,debug2;
wire [31:0] instruction,PC;
wire [31:0] DataAdr,WriteData,ReadData;
wire Write_Enable;
memory im(PC,instruction);
datamem dm(DataAdr,WriteData,Write_Enable,ReadData,clk);
ARM proc(clk,reset,instruction,ReadData,DataAdr,WriteData,Write_Enable,PC);
always@(negedge clk,posedge reset) begin
if(reset) begin
debug1=0;
debug2=0;
end else begin
if((WriteData==8'h00000007)&(DataAdr==8'h00000014))
debug1=1;
if((WriteData==8'h00000007)&(DataAdr==8'h0000001A))
debug2=1;
end
end
endmodule |
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac.v,v $
//
// $Revision: #1 $
// $Date: 2011/08/15 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet MAC
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
clk, // Avalon slave - clock
read, // Avalon slave - read
write, // Avalon slave - write
address, // Avalon slave - address
writedata, // Avalon slave - writedata
readdata, // Avalon slave - readdata
waitrequest, // Avalon slave - waitrequest
reset, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
reset_ff_rx_clk,
reset_ff_tx_clk,
ff_rx_clk, // AtlanticII source - clk
ff_rx_data, // AtlanticII source - data
ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_rx_sop, // AtlanticII source - startofpacket
ff_rx_eop, // AtlanticII source - endofpacket
rx_err, // AtlanticII source - error
rx_err_stat, // AtlanticII source - component_specific_signal(eop)
rx_frm_type, // AtlanticII source - component_specific_signal(data)
ff_rx_rdy, // AtlanticII source - ready
ff_rx_dval, // AtlanticII source - valid
ff_rx_dsav, // AtlanticII source - component_specific_signal(data)
ff_tx_clk, // AtlanticII sink - clk
ff_tx_data, // AtlanticII sink - data
ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_tx_sop, // AtlanticII sink - startofpacket
ff_tx_eop, // AtlanticII sink - endofpacket
ff_tx_err, // AtlanticII sink - error
ff_tx_wren, // AtlanticII sink - valid
ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
ff_tx_rdy, // AtlanticII sink - ready
ff_tx_septy, // AtlanticII source - component_specific_signal(data)
tx_ff_uflow, // AtlanticII source - component_specific_signal(data)
ff_rx_a_full,
ff_rx_a_empty,
ff_tx_a_full,
ff_tx_a_empty,
xoff_gen,
xon_gen,
magic_sleep_n,
magic_wakeup,
rx_clk,
tx_clk,
gm_rx_d,
gm_rx_dv,
gm_rx_err,
gm_tx_d,
gm_tx_en,
gm_tx_err,
m_rx_d,
m_rx_en,
m_rx_err,
m_tx_d,
m_tx_en,
m_tx_err,
m_rx_crs,
m_rx_col,
eth_mode,
ena_10,
set_10,
set_1000,
mdc,
mdio_in,
mdio_out,
mdio_oen,
tx_control,
rx_control,
rgmii_in,
rgmii_out
);
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // ALTERA Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input clk; // 25MHz Host Interface Clock
input read; // Register Read Strobe
input write; // Register Write Strobe
input [7:0] address; // Register Address
input [31:0] writedata; // Write Data for Host Bus
output [31:0] readdata; // Read Data to Host Bus
output waitrequest; // Interface Busy
input reset; // Asynchronous Reset
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
input ff_rx_clk; // Transmit Local Clock
output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
output [1:0] ff_rx_mod; // Data Modulo
output ff_rx_sop; // Start of Packet
output ff_rx_eop; // End of Packet
output [5:0] rx_err; // Errored Packet Indication
output [17:0] rx_err_stat; // Packet Length and Status Word
output [3:0] rx_frm_type; // Unicast Frame Indication
input ff_rx_rdy; // PHY Application Ready
output ff_rx_dval; // Data Valid Strobe
output ff_rx_dsav; // Data Available
input ff_tx_clk; // Transmit Local Clock
input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
input [1:0] ff_tx_mod; // Data Modulo
input ff_tx_sop; // Start of Packet
input ff_tx_eop; // End of Packet
input ff_tx_err; // Errored Packet
input ff_tx_wren; // Write Enable
input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
output ff_tx_rdy; // FIFO Ready
output ff_tx_septy; // FIFO has space for at least one section
output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
output ff_rx_a_full; // Receive FIFO Almost Full
output ff_rx_a_empty; // Receive FIFO Almost Empty
output ff_tx_a_full; // Transmit FIFO Almost Full
output ff_tx_a_empty; // Transmit FIFO Almost Empty
input xoff_gen; // Xoff Pause frame generate
input xon_gen; // Xon Pause frame generate
input magic_sleep_n; // Enable Sleep Mode
output magic_wakeup; // Wake Up Request
input rx_clk; // Receive Clock
input tx_clk; // Transmit Clock
input [7:0] gm_rx_d; // GMII Receive Data
input gm_rx_dv; // GMII Receive Frame Enable
input gm_rx_err; // GMII Receive Frame Error
output [7:0] gm_tx_d; // GMII Transmit Data
output gm_tx_en; // GMII Transmit Frame Enable
output gm_tx_err; // GMII Transmit Frame Error
input [3:0] m_rx_d; // MII Receive Data
input m_rx_en; // MII Receive Frame Enable
input m_rx_err; // MII Receive Drame Error
output [3:0] m_tx_d; // MII Transmit Data
output m_tx_en; // MII Transmit Frame Enable
output m_tx_err; // MII Transmit Frame Error
input m_rx_crs; // Carrier Sense
input m_rx_col; // Collition
output eth_mode; // Ethernet Mode
output ena_10; // Enable 10Mbps Mode
input set_1000; // Gigabit Mode Enable
input set_10; // 10Mbps Mode Enable
output mdc; // 2.5MHz Inteface
input mdio_in; // MDIO Input
output mdio_out; // MDIO Output
output mdio_oen; // MDIO Output Enable
output tx_control;
output [3:0] rgmii_out;
input [3:0] rgmii_in;
input rx_control;
wire [31:0] reg_data_out;
wire reg_busy;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire ff_rx_dval;
wire ff_rx_dsav;
wire ff_tx_rdy;
wire ff_tx_septy;
wire tx_ff_uflow;
wire magic_wakeup;
wire ff_rx_a_full;
wire ff_rx_a_empty;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire [7:0] gm_tx_d;
wire gm_tx_en;
wire gm_tx_err;
wire [3:0] m_tx_d;
wire m_tx_en;
wire m_tx_err;
wire eth_mode;
wire ena_10;
wire mdc;
wire mdio_out;
wire mdio_oen;
wire tx_control;
wire [3:0] rgmii_out;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
// Reset Lines
// -----------
wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
// Programmable Reset Options
// --------------------------
generate if (USE_SYNC_RESET == 1)
begin
altera_tse_reset_synchronizer reset_sync_0 (
.clk(rx_clk),
.reset_in(reset),
.reset_out(reset_rx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_1 (
.clk(tx_clk),
.reset_in(reset),
.reset_out(reset_tx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_2 (
.clk(ff_rx_clk),
.reset_in(reset),
.reset_out(reset_ff_rx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_3 (
.clk(ff_tx_clk),
.reset_in(reset),
.reset_out(reset_ff_tx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_4 (
.clk(clk),
.reset_in(reset),
.reset_out(reset_reg_clk_int)
);
end
else
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
endgenerate
// --------------------------
altera_tse_top_gen_host top_gen_host_inst(
.reset_ff_rx_clk(reset_ff_rx_clk_int),
.reset_ff_tx_clk(reset_ff_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(1'b1),
.tx_clkena(1'b1),
.gm_rx_dv(gm_rx_dv),
.gm_rx_d(gm_rx_d),
.gm_rx_err(gm_rx_err),
.m_rx_en(m_rx_en),
.m_rx_d(m_rx_d),
.m_rx_err(m_rx_err),
.m_rx_col(m_rx_col),
.m_rx_crs(m_rx_crs),
.set_1000(set_1000),
.set_10(set_10),
.ff_rx_clk(ff_rx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_tx_clk(ff_tx_clk),
.ff_tx_wren(ff_tx_wren),
.ff_tx_data(ff_tx_data),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_crc_fwd(ff_tx_crc_fwd),
.reg_clk(clk),
.reg_addr(address),
.reg_data_in(writedata),
.reg_rd(read),
.reg_wr(write),
.mdio_in(mdio_in),
.gm_tx_en(gm_tx_en),
.gm_tx_d(gm_tx_d),
.gm_tx_err(gm_tx_err),
.m_tx_en(m_tx_en),
.m_tx_d(m_tx_d),
.m_tx_err(m_tx_err),
.eth_mode(eth_mode),
.ena_10(ena_10),
.ff_rx_dval(ff_rx_dval),
.ff_rx_data(ff_rx_data),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.ff_rx_eop(ff_rx_eop),
.ff_rx_dsav(ff_rx_dsav),
.rx_err(rx_err),
.rx_err_stat(rx_err_stat),
.rx_frm_type(rx_frm_type),
.ff_tx_rdy(ff_tx_rdy),
.ff_tx_septy(ff_tx_septy),
.tx_ff_uflow(tx_ff_uflow),
.rx_a_full(ff_rx_a_full),
.rx_a_empty(ff_rx_a_empty),
.tx_a_full(ff_tx_a_full),
.tx_a_empty(ff_tx_a_empty),
.xoff_gen(xoff_gen),
.xon_gen(xon_gen),
.reg_data_out(readdata),
.reg_busy(waitrequest),
.reg_sleepN(magic_sleep_n),
.reg_wakeup(magic_wakeup),
.mdc(mdc),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen),
.tx_control(tx_control),
.rgmii_out(rgmii_out),
.rgmii_in(rgmii_in),
.rx_control(rx_control));
defparam
top_gen_host_inst.EG_FIFO = EG_FIFO,
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
top_gen_host_inst.EG_ADDR = EG_ADDR,
top_gen_host_inst.ENA_HASH = ENA_HASH,
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
top_gen_host_inst.ING_FIFO = ING_FIFO,
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE, //1,
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE, //1,
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE, //1,
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE, //1,
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE, //0,
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
top_gen_host_inst.ING_ADDR = ING_ADDR,
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
top_gen_host_inst.INSERT_TA = INSERT_TA,
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
endmodule
|
`timescale 1 ps / 1 ps
module simple_io(
////////////HPS///////////////
input wire clk_in, // clk.clk
input wire reset_n, // reset.reset_n,
////////////FPGA///////////////
output wire [3:0] led, // fpga_led_external_connection.export
input wire [3:0] slide_sw, // slide_sw_external_connection.export
input wire [3:0] key, // fpga_key_external_connection.export
input aud_adcdat,
inout aud_bclk,
inout aud_daclrck,
inout aud_adclrck,
output aud_xck,
output adu_dacdat,
output aud_mute,
inout fpga_sd_D0,
inout fpga_sd_D1,
inout fpga_sd_D2,
inout fpga_sd_D3,
inout fpga_sd_CMD,
output fpga_sd_CLK,
output [7:0] vga_r_data,
output [7:0] vga_g_data,
output [7:0] vga_b_data,
output vga_blank,
output vga_sync,
output lcd_hsync,
output lcd_vsync,
output lcd_clk,
output lcd_de,
output lcd_pwm,
input hdmi_int
);
video_test_system u0 (
.clk_clk (clk_in), // clk.clk
.reset_reset_n (1'b1), // reset.reset_n
.video_out_vid_data ({vga_b_data[7:0], vga_g_data[7:0], vga_r_data[7:0]}), // .vid_data
.video_out_underflow (), // .underflow
.video_out_vid_datavalid (lcd_de), // .vid_datavalid
.video_out_vid_v_sync (lcd_vsync), // .vid_v_sync
.video_out_vid_h_sync (lcd_hsync), // .vid_h_sync
.video_out_vid_f (), // .vid_f
.video_out_vid_h (), // .vid_h
.video_out_vid_v (), // .vid_v
.video_clk_clk (lcd_clk) // video_clk.clk
);
assign vga_blank = 1'b1;
assign vga_sync = 1'b0;
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__XOR3_FUNCTIONAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR3_FUNCTIONAL_PP_V |
//% @file adc_cnv_sipo.v
//% @brief Drive ADC (LTC2325-16) conversion and convert Serial dataIn to Parallel dataOut.
//% @author Yuan Mei
//%
//% @param[in] NCH total number of ADC channels
//%
//% Relative time (phase) relation between cnv_n and clkff is
//% critical. One can swap D1, D2 bits in ODDR to achieve half-CLK
//% shift, or change the cnt condition number between 2 and 3 for
//% adc_clkff_oe to achieve 1-CLK shift. set_output_delay in .xdc must
//% be commensurate.
`timescale 1ns / 1ps
module adc_cnv_sipo
#(
parameter NCH = 20
)
(
input RESET,
input CLK, //% DELAY_* must be synchronous to this clock
input REFCLK, //% REFCLK (200MHz) for IDELAYCTRL
input [7:0] DELAY_CHANNEL, //% ADC data input iodelay channel selection
input [4:0] DELAY_VALUE, //% ADC data input iodelay value
input DELAY_UPDATE, //% a pulse to update the delay value
input [3:0] CLKFF_DIV,
output CLKFF_P,
output CLKFF_N,
input CLK_LPBK_P,
input CLK_LPBK_N,
output CLK_LPBK,
output CNV_N_P,
output CNV_N_N,
output CNV_N,
input [NCH-1:0] INPUTS_P,
input [NCH-1:0] INPUTS_N,
output [NCH-1:0] INPUTS_OUT,
(* ASYNC_REG = "TRUE" *)
output reg [NCH*16-1:0] DOUT,
output reg DOUT_VALID
);
localparam iodelay_group_name = "tms_iodelay_grp";
reg adc_cnv_n;
reg adc_sample_n;
wire [NCH-1:0] adc_sdin_v;
wire adc_clkff_tmp, adc_clkff_tmp1;
(* KEEP = "TRUE" *)
wire adc_clk_lpbk;
reg adc_clkff_oe;
reg [4:0] cnt;
reg [3:0] idx;
reg [15:0] sdo_v[NCH-1:0];
(* IODELAY_GROUP = iodelay_group_name *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL adc_idelayctrl_inst
(
.RDY(), // 1-bit output: Ready output
.REFCLK(REFCLK), // 1-bit input: Reference clock input
.RST(RESET) // 1-bit input: Active high reset input
);
diffiodelay
#(
.NINPUT(NCH+1),
.NOUTPUT(1),
.INPUT_DIFF_TERM("TRUE"),
.IODELAY_GROUP_NAME(iodelay_group_name)
)
adc_diffiodelay_inst
(
.RESET(RESET),
.CLK(CLK), //% DELAY_* must be synchronous to this clock
.DELAY_CHANNEL(DELAY_CHANNEL),
.DELAY_VALUE(DELAY_VALUE),
.DELAY_UPDATE(DELAY_UPDATE), //% a pulse to update the delay value
.INPUTS_OUT({adc_clk_lpbk, adc_sdin_v}),
.INPUTS_P({CLK_LPBK_P, INPUTS_P}),
.INPUTS_N({CLK_LPBK_N, INPUTS_N}),
.OUTPUTS_IN(0),
.OUTPUTS_P(),
.OUTPUTS_N()
);
assign INPUTS_OUT[NCH-1:0] = adc_sdin_v;
// clkff
clk_div
#(
.WIDTH(32),
.PBITS(4)
)
adc_clkff_div_inst
(
.RESET(RESET),
.CLK(CLK),
.DIV(CLKFF_DIV),
.CLK_DIV(adc_clkff_tmp)
);
// clock forwarding
ODDR
#(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
)
adc_clkff_forward_inst
(
.Q(adc_clkff_tmp1), // 1-bit DDR output
.C(adc_clkff_tmp), // 1-bit clock input
.CE(1), // 1-bit clock enable input
.D1(0), // 1-bit data input (positive edge)
.D2(1), // 1-bit data input (negative edge)
.R(~adc_clkff_oe), // 1-bit reset
.S(0) // 1-bit set
);
OBUFDS
#(
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
adc_clkff_obufds_inst
(
.O(CLKFF_P), // Diff_p output (connect directly to top-level port)
.OB(CLKFF_N), // Diff_n output (connect directly to top-level port)
.I(adc_clkff_tmp1) // Buffer input
);
// clk_lpbk
assign CLK_LPBK = adc_clk_lpbk;
// adc_cnv_n
OBUFDS
#(
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
adc_cnv_n_obufds_inst
(
.O(CNV_N_P), // Diff_p output (connect directly to top-level port)
.OB(CNV_N_N), // Diff_n output (connect directly to top-level port)
.I(adc_cnv_n) // Buffer input
);
assign CNV_N = adc_cnv_n;
always @ (posedge adc_clkff_tmp or posedge RESET) begin
if (RESET) begin
cnt <= 0;
adc_cnv_n <= 1;
adc_sample_n <= 1;
adc_clkff_oe <= 0;
end
else begin
cnt <= cnt + 1;
if (cnt>=19) begin
cnt <= 0;
end
adc_cnv_n <= 0;
if (0<=cnt && cnt<3) begin
adc_cnv_n <= 1;
end
adc_sample_n <= 0;
if (0<cnt && cnt<3) begin
adc_sample_n <= 1;
end
adc_clkff_oe <= 1;
if ((0<=cnt && cnt<3) || cnt>=3+16) begin // Adjust the number (2 or 3) to satisfy the external time delay.
adc_clkff_oe <= 0;
end
end
end
// sample in CLK domain
reg adc_sample_n_prev;
always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
adc_sample_n_prev <= 0;
DOUT_VALID <= 0;
end
else begin
adc_sample_n_prev <= adc_sample_n;
DOUT_VALID <= 0;
if (adc_sample_n_prev == 0 && adc_sample_n == 1) begin // rising edge
DOUT_VALID <= 1;
end
end
end
genvar i;
generate
for (i=0; i<NCH; i=i+1) begin
always @ (posedge adc_clk_lpbk or posedge adc_sample_n or posedge RESET) begin
if (RESET) begin
sdo_v[i] <= 0;
end
else begin
if (adc_sample_n) begin
idx <= 15;
end
else begin
sdo_v[i][idx] <= adc_sdin_v[i];
idx <= idx - 1;
end
end
end
// sample in CLK domain
always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
DOUT[16*i+15:16*i] <= 0;
end
else begin
if (adc_sample_n_prev == 0 && adc_sample_n == 1) begin // rising edge
DOUT[16*i+15:16*i] <= sdo_v[i];
end
end
end
end
endgenerate
endmodule // adc_cnv_sipo
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O2BB2AI_FUNCTIONAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:58:11 07/01/2012
// Design Name:
// Module Name: GPIO
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GPIO(input clk,
input rst,
input Start,
input EN,
input [31:0] P_Data,
output reg[1:0] counter_set,
output [15:0] LED_out,
output wire ledclk,
output wire ledsout,
output wire ledclrn,
output wire LEDEN,
output reg[13:0] GPIOf0
);
reg [15:0]LED;
// GPIO out use on LEDs & Counter-Controler read and write
assign LED_out = LED;
always @(negedge clk or posedge rst) begin
if(rst)begin LED <= 8'h2A; counter_set<=2'b00; end
else if(EN) {GPIOf0[13:0],LED,counter_set} <= P_Data; //Counter ch1 ch0
else begin LED <= LED; counter_set<=counter_set; end
end
LEDP2S #(.DATA_BITS(16),.DATA_COUNT_BITS(4),.DIR(0))
LEDP2S(.clk(clk),
.rst(rst),
.Start(Start),
// .PData(~LED),
.PData(LED),
.sclk(ledclk),
.sclrn(ledclrn),
.sout(ledsout),
.EN(LEDEN)
);
/* LED_P2S #(.DATA_BITS(16),.DATA_COUNT_BITS(4))
LED_P2S(clk, rst, Start,
{~{LED[0],LED[1],LED[2],LED[3],LED[4],LED[5],LED[6],LED[7],
LED[8],LED[9],LED[10],LED[11],LED[12],LED[13],LED[14],LED[15]}},
led_clk,
led_clrn,
led_sout,
LED_PEN
);
*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfsbp (
CLK ,
D ,
Q ,
Q_N ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_TB_V
`define SKY130_FD_SC_HD__SEDFXTP_TB_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sedfxtp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sedfxtp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ddr_rptr_south.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ddr_rptr_south ( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__OR2B_BEHAVIORAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or2b (
X ,
A ,
B_N
);
// Module ports
output X ;
input A ;
input B_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_BEHAVIORAL_V |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32x256.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_32x256 (
data,
rdaddress,
rdclock,
rden,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [7:0] rdaddress;
input rdclock;
input rden;
input [7:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.rden_b (rden),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK1",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL rdaddress[7..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC rden
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL wraddress[7..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2004 by Babak Falsafi and James Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),
* Carnegie Mellon University.
*
* This source file was written and maintained by Jared Smolens
* as part of the Two-Way In-Order Superscalar project for Carnegie Mellon's
* Introduction to Computer Architecture course, 18-447. The source file
* is in part derived from code originally written by Herman Schmit and
* Diana Marculescu.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* If you modify the software you must place a notice on or within any
* modified version provided or made available to any third party stating
* that you have modified the software. The notice shall include at least
* your name, address, phone number, email address and the date and purpose
* of the modification.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANYWARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
`include "mips_defines.vh"
module mips_exceptionUnit (/*AUTOARG*/
// Outputs
exception_halt, load_ex_regs, load_bva, cause, load_bva_sel,
// Inputs
pc, IBE, DBE, RI, Ov, BP, AdEL_inst, AdEL_data, AdES, CpU, clk,
rst_b
);
output wire exception_halt, load_ex_regs, load_bva;
output reg [4:0] cause;
output wire load_bva_sel;
input [31:0] pc;
input IBE, DBE, RI, Ov, BP, AdEL_inst, AdEL_data, AdES, CpU;
input clk, rst_b;
assign exception_halt = rst_b && (AdEL_inst || IBE);
assign load_ex_regs = rst_b && (IBE || DBE || RI || Ov || BP || AdEL_inst ||
AdEL_data || AdES || CpU);
assign load_bva = rst_b && (AdEL_inst || AdEL_data || AdES || IBE || DBE);
assign load_bva_sel = AdEL_data || AdES || DBE;
always @(*) begin
cause = 0;
case (1'b1)
AdEL_inst: cause = `EX_ADEL;
AdEL_data: cause = `EX_ADEL;
AdES: cause = `EX_ADES;
IBE: cause = `EX_IBE;
DBE: cause = `EX_DBE;
CpU: cause = `EX_CPU;
RI: cause = `EX_RI;
Ov: cause = `EX_OV;
BP: cause = `EX_BP;
endcase
end
// synthesis translate_off
always @(posedge clk or negedge rst_b) begin
if (rst_b) begin
// Address errors take priority over bus errors.
// Coprocessor exceptions take priority over reserved instruction
// exceptions.
// Instruction bus/address errors are fatal.
if(AdEL_inst == 1'b1)
$display(`MSG_ADEL_S, pc);
else if(AdEL_data == 1'b1)
$display(`MSG_ADEL_S, pc);
else if(AdES == 1'b1)
$display(`MSG_ADES_S, pc);
else if(IBE == 1'b1)
$display(`MSG_IBE_S, pc);
else if(DBE == 1'b1)
$display(`MSG_DBE_S, pc);
else if(CpU == 1'b1)
$display(`MSG_CPU_S, pc);
else if(RI == 1'b1)
$display(`MSG_RI_S, pc);
else if(Ov == 1'b1)
$display(`MSG_OV_S, pc);
else if(BP == 1'b1)
$display(`MSG_BP_S, pc);
end
end
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_SYMBOL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd1 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Decrementer_0_0/RAT_Decrementer_0_0_stub.v
// Design : RAT_Decrementer_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "Decrementer,Vivado 2016.4" *)
module RAT_Decrementer_0_0(I, O)
/* synthesis syn_black_box black_box_pad_pin="I[7:0],O[7:0]" */;
input [7:0]I;
output [7:0]O;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/07 17:02:53
// Design Name:
// Module Name: _3bit_binary_multiplier_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _3bit_binary_multiplier_tb(
);
parameter COUNT = 150;
parameter DELAY = 10;
parameter TIME = (COUNT * DELAY);
parameter WIDTH = 3;
reg start, clk;
reg [(WIDTH-1):0] multiplier, multiplicand;
wire [((WIDTH*2)-1):0] p;
wire done;
integer i, j, k;
_3bit_binary_multiplier #(WIDTH) DUT (start, clk, multiplier, multiplicand, p, done);
initial begin
#TIME $finish;
end
initial begin
clk = 0;
for (i = 0; i < COUNT; i = i + 1) begin
#DELAY clk = ~clk;
end
end
initial begin
start = 0;
#(DELAY/2);
#(DELAY);
for (j = 0; j < COUNT;j = j + 1) begin
#(15*DELAY) start = 1;
#DELAY start = 0;
end
end
initial begin
multiplier = 0; multiplicand = 1;
for (k = 0; k < 7; k = k + 1) begin
#(16*DELAY) multiplier = k; multiplicand = k + 1;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: mul64.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/*//////////////////////////////////////////////////////////////////////
//
// Module Name: mul64
// Description: *This block implements the multiplier used in the modular multiplier
// unit (MUL) and be shared by sparc EXU and the streaming unit (SPU).
// It is also used as the 54x54 multiplier in the FPU.
// *It takes two 64-bit unsign data and accumulated operand and do the
// 64x64 MAC operation at two cycle thruput and 5 cycle latency.
// *The mul_valid signal indicate the beginning of a new operation.
// It MUST be dis-asserted at the next cycle to have the proper 2-cycle
// latency operation in the csa array. If there are two back-to-back
// cycle operation, the first operation result will be incorrect.
// *Results are avaliable on the 5th cycle of the mul_valid as shows
//
// *Following inputs should tie to "0" when used as a 64x64 multiplier
// - areg
// - accreg
// - x2
//
// Cycle-0 | Cycle-1 | Cycle-2 | Cycle-3 | Cycle-4 | Cycle-5
// 1st * | | | |
// rs1, rs2 ^ | | | | 1st results
// valid=1 | valid=0 | * | | avaliable
// 1st | 2nd OP ^ | |
// setup | valid=1 | | |
// | 2nd | |
// | setup | |
//
*/
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_MUL
`endif
`ifdef FPGA_SYN_MUL
module mul64(rs1_l, rs2, valid, areg, accreg, x2, out, rclk, si, so, se,
mul_rst_l, mul_step);
input [63:0] rs1_l;
input [63:0] rs2;
input valid;
input [96:0] areg;
input [135:129] accreg;
input x2;
input rclk;
input si;
input se;
input mul_rst_l;
input mul_step;
output so;
output [135:0] out;
reg [135:0] myout, myout_a1, myout_a2, myout_a3;
reg [63:0] rs1_ff;
reg [64:0] rs2_ff;
reg [63:0] par1, par2;
reg [64:0] par3, par4;
reg [5:0] state;
always @(posedge rclk)
state <= {valid,state[5:1]};
always @(posedge rclk) begin
if(mul_step) begin
if(valid) begin
rs1_ff <= ~rs1_l;
rs2_ff <= x2 ? {rs2,1'b0} : {1'b0,rs2};
end else begin
rs1_ff <= {32'b0, rs1_ff[63:32]};
end
par1 <= (rs1_ff[31:0] * rs2_ff[31:0]);
par3 <= rs1_ff[31:0] * rs2_ff[64:32];
myout_a1 <= ({32'b0, myout_a1[135:32]} & {136{state[3]}}) + par1 + {par3, 32'b0} + areg;
myout <= {(myout_a1[103:97]+accreg),myout_a1[96:0],myout[63:32]};
end
end
assign out = myout;
assign so = 1'b0;
endmodule
`else
module mul64 (rs1_l, rs2, valid, areg, accreg, x2, out, rclk, si, so, se, mul_rst_l, mul_step);
input [63:0] rs1_l; // op1
input [63:0] rs2; // op2
input valid; // begin of the MUL operation
input [96:0] areg; // accumulated input for ACCUM
input [135:129] accreg; // direct input from ACCUM [135:129]
input x2; // for op1*op2*2
input rclk, si, se, mul_rst_l, mul_step;
output so;
output [135:0] out;
wire cyc1, cyc2, cyc3; // cycle stage of MUL
wire [2:0] b0, b1, b2, b3, b4, b5, b6, b7;
wire [2:0] b8, b9, b10, b11, b12, b13, b14, b15;
wire b16;
wire [63:0] op1_l, op1;
wire [81:0] a0sum, a1sum, a0s, a1s;
wire [81:4] a0cout, a1cout, a0c, a1c;
wire pcoutx2, psumx2;
wire x2_c1, x2_c2, x2_c3, x2_c2c3;
wire [98:0] psum, pcout;
wire [98:30] pcout_in, pc;
wire [98:31] psum_in, ps;
wire [96:0] ary2_cout, addin_cout;
wire [97:0] ary2_sum, addin_sum ;
wire add_cin, addin_cin, add_co31, add_co96;
wire [103:0] addout;
wire clk_enb0, clk_enb1;
wire rst;
wire clk;
wire tm_l;
assign clk = rclk;
assign rst = ~mul_rst_l;
assign tm_l = ~se;
clken_buf ckbuf_0(.clk(clk_enb0), .rclk(clk), .enb_l(~mul_step), .tmb_l(tm_l));
/////////////////////////////////////////////////////////////////////
// States count
/////////////////////////////////////////////////////////////////////
dffr cyc1_dff(.din(valid), .clk(clk_enb0), .q(cyc1), .rst(rst), .se(se), .si(), .so());
dffr cyc2_dff(.din(cyc1), .clk(clk_enb0), .q(cyc2), .rst(rst), .se(se), .si(), .so());
dffr cyc3_dff(.din(cyc2), .clk(clk_enb0), .q(cyc3), .rst(rst), .se(se), .si(), .so());
dffr x2c1_dff(.din(x2), .clk(clk_enb0), .q(x2_c1), .rst(rst), .se(se), .si(), .so());
dffr x2c2_dff(.din(x2_c1), .clk(clk_enb0), .q(x2_c2), .rst(rst), .se(se), .si(), .so());
dffr x2c3_dff(.din(x2_c2), .clk(clk_enb0), .q(x2_c3), .rst(rst), .se(se), .si(), .so());
assign x2_c2c3 = x2_c2 | x2_c3 ;
/////////////////////////////////////////////////////////////////////
// Enable flops for op1
/////////////////////////////////////////////////////////////////////
clken_buf ckbuf_1(.clk(clk_enb1), .rclk(clk), .enb_l(~(valid & mul_step)), .tmb_l(tm_l));
dff #(64) ffrs1 (.din(rs1_l[63:0]), .clk(clk_enb1), .q(op1_l[63:0]),
.se(se), .si(), .so());
assign op1[63:0] = ~op1_l[63:0];
mul_booth booth (.head (valid),
.b_in (rs2),
.b0 (b0),
.b1 (b1),
.b2 (b2),
.b3 (b3),
.b4 (b4),
.b5 (b5),
.b6 (b6),
.b7 (b7),
.b8 (b8),
.b9 (b9),
.b10 (b10),
.b11 (b11),
.b12 (b12),
.b13 (b13),
.b14 (b14),
.b15 (b15),
.b16 (b16),
.clk (clk), .se(se), .si(), .so(), .mul_step(mul_step), .tm_l(tm_l));
/////////////////////////////////////////////////////////////////////
// Two Array1 inst ary1_a0 & ary1_a1 with the ouput flops
/////////////////////////////////////////////////////////////////////
mul_array1 ary1_a0(.cout (a0cout[81:4]),
.sum (a0sum[81:0]),
.a (op1),
.b0 (b0),
.b1 (b1),
.b2 (b2),
.b3 (b3),
.b4 (b4),
.b5 (b5),
.b6 (b6),
.b7 (b7),
.b8 (3'b000),
.head (cyc1),
.bot (1'b0)); //array a is never at the bottom of 33-pp rows
dff #(78) a0cot_dff (.din(a0cout[81:4]), .clk(clk_enb0), .q(a0c[81:4]),
.se(se), .si(), .so());
dff #(82) a0sum_dff (.din(a0sum[81:0]), .clk(clk_enb0), .q(a0s[81:0]),
.se(se), .si(), .so());
mul_array1 ary1_a1(.cout (a1cout[81:4]),
.sum (a1sum[81:0]),
.a (op1),
.b0 (b8),
.b1 (b9),
.b2 (b10),
.b3 (b11),
.b4 (b12),
.b5 (b13),
.b6 (b14),
.b7 (b15),
.b8 ({1'b0,b16,1'b0}),
.head (1'b0), //array b is never at the head of 33-pp rows
.bot (cyc2));
dff #(78) a1cot_dff (.din(a1cout[81:4]), .clk(clk_enb0), .q(a1c[81:4]),
.se(se), .si(), .so());
dff #(82) a1sum_dff (.din(a1sum[81:0]), .clk(clk_enb0), .q(a1s[81:0]),
.se(se), .si(), .so());
/////////////////////////////////////////////////////////////////////
// Array2 with the reorder output mux-flops
/////////////////////////////////////////////////////////////////////
mul_array2 array2(.pcoutx2 (pcoutx2),
.psumx2 (psumx2),
.pcout (pcout[98:0]),
.psum (psum[98:0]),
.a0c (a0c[81:4]),
.a0s (a0s[81:0]),
.a1c (a1c[81:4]),
.a1s (a1s[81:0]),
.pc (pc[98:30]),
.ps (ps[98:31]),
.areg (areg[96:0]),
.bot (cyc3),
.x2 (x2_c2c3));
//// Outpput re-order muxes and flops ////
dp_mux2es #(97) ary2_cmux (.dout(ary2_cout[96:0]),
.in0(pcout[96:0]),
.in1({pcout[95:0],pcoutx2}),
.sel(x2_c2c3));
dff #(97) a2cot_dff (.din(ary2_cout[96:0]), .clk(clk_enb0), .q(addin_cout[96:0]),
.se(se), .si(), .so());
dp_mux2es #(98) ary2_smux (.dout(ary2_sum[97:0]),
.in0(psum[97:0]),
.in1({psum[96:0],psumx2}),
.sel(x2_c2c3));
dff #(98) a2sum_dff (.din(ary2_sum[97:0]), .clk(clk_enb0), .q(addin_sum[97:0]),
.se(se), .si(), .so());
//// Pseudo sum & cout logic and flops ////
assign psum_in[98:32] = psum[98:32] & {67{cyc2}} ;
assign psum_in[31] = psum[31] & x2_c2 ;
assign pcout_in[98:31] = pcout[98:31] & {68{cyc2}} ;
assign pcout_in[30] = pcout[30] & x2_c2 ;
dff #(68) psum_dff (.din(psum_in[98:31]), .clk(clk_enb0), .q(ps[98:31]),
.se(se), .si(), .so());
dff #(69) pcout_dff (.din(pcout_in[98:30]), .clk(clk_enb0), .q(pc[98:30]),
.se(se), .si(), .so());
/////////////////////////////////////////////////////////////////////
// Adder (104-bit)
/////////////////////////////////////////////////////////////////////
assign add_cin = add_co31 & cyc3 ;
assign {add_co31,addout[31:0]} = {{1'b0},addin_sum[31:0]}
+ {{1'b0},addin_cout[30:0],addin_cin} ;
assign {add_co96,addout[96:32]} = addin_sum[97:32]
+ addin_cout[96:31]
+ {{65'b0},add_co31} ;
assign addout[103:97] = accreg[135:129] + {{6'b0},add_co96} ;
/////////////////////////////////////////////////////////////////////
// Pipe adder outputs
/////////////////////////////////////////////////////////////////////
dff co31_dff (.din(add_cin), .clk(clk_enb0), .q(addin_cin),
.se(se), .si(), .so());
dff #(104) out_dff (.din(addout[103:0]), .clk(clk_enb0), .q(out[135:32]),
.se(se), .si(), .so());
dff #(32) pip_dff (.din(out[63:32]), .clk(clk_enb0), .q(out[31:0]),
.se(se), .si(), .so());
endmodule // mul64
////////////////////////////////////////////////////////////////////////
// Sub-moudle for mul64
////////////////////////////////////////////////////////////////////////
module mul_array1 ( cout, sum, a, b0, b1, b2, b3, b4, b5, b6, b7, b8,
bot, head );
input bot, head;
output [81:4] cout;
output [81:0] sum;
input [2:0] b6;
input [2:0] b3;
input [2:0] b8;
input [2:0] b2;
input [2:0] b1;
input [2:0] b7;
input [63:0] a;
input [2:0] b0;
input [2:0] b4;
input [2:0] b5;
// Buses in the design
wire [1:0] b5n;
wire [1:0] b2n;
wire [68:1] c0;
wire [69:0] s1;
wire [68:1] c1;
wire [69:0] s2;
wire [68:1] c2;
wire [70:4] s_1;
wire [69:2] s0;
wire [76:10] s_2;
wire [70:2] c_1;
wire [76:10] c_2;
wire [75:11] co;
mul_negen p1n ( .b(b5[2:0]), .n1(b5n[1]), .n0(b5n[0]));
mul_negen p0n ( .b(b2[2:0]), .n1(b2n[1]), .n0(b2n[0]));
mul_csa42 sc3_71_ ( .c(s_2[71]), .cin(co[70]), .a(c_1[70]),
.b(c_2[70]), .cout(co[71]), .sum(sum[71]), .d(s1[65]),
.carry(cout[71]));
mul_csa42 sc3_75_ ( .c(s_2[75]), .cin(co[74]), .a(1'b0),
.b(c_2[74]), .cout(co[75]), .sum(sum[75]), .d(s1[69]),
.carry(cout[75]));
mul_csa42 sc3_74_ ( .c(s_2[74]), .cin(co[73]), .a(1'b0),
.b(c_2[73]), .cout(co[74]), .sum(sum[74]), .d(s1[68]),
.carry(cout[74]));
mul_csa42 sc3_73_ ( .c(s_2[73]), .cin(co[72]), .a(1'b0),
.b(c_2[72]), .cout(co[73]), .sum(sum[73]), .d(s1[67]),
.carry(cout[73]));
mul_csa42 sc3_72_ ( .c(s_2[72]), .cin(co[71]), .a(1'b0),
.b(c_2[71]), .cout(co[72]), .sum(sum[72]), .d(s1[66]),
.carry(cout[72]));
mul_csa42 sc3_76_ ( .c(s_2[76]), .cin(co[75]), .a(1'b0),
.b(c_2[75]), .cout(), .sum(sum[76]), .d(1'b0),
.carry(cout[76]));
mul_csa42 sc3_70_ ( .c(s_2[70]), .cin(co[69]), .a(c_1[69]),
.b(c_2[69]), .cout(co[70]), .sum(sum[70]), .d(s_1[70]),
.carry(cout[70]));
mul_csa42 sc3_69_ ( .c(s_2[69]), .cin(co[68]), .a(c_1[68]),
.b(c_2[68]), .cout(co[69]), .sum(sum[69]), .d(s_1[69]),
.carry(cout[69]));
mul_csa42 sc3_68_ ( .c(s_2[68]), .cin(co[67]), .a(c_1[67]),
.b(c_2[67]), .cout(co[68]), .sum(sum[68]), .d(s_1[68]),
.carry(cout[68]));
mul_csa42 sc3_67_ ( .c(s_2[67]), .cin(co[66]), .a(c_1[66]),
.b(c_2[66]), .cout(co[67]), .sum(sum[67]), .d(s_1[67]),
.carry(cout[67]));
mul_csa42 sc3_66_ ( .c(s_2[66]), .cin(co[65]), .a(c_1[65]),
.b(c_2[65]), .cout(co[66]), .sum(sum[66]), .d(s_1[66]),
.carry(cout[66]));
mul_csa42 sc3_65_ ( .c(s_2[65]), .cin(co[64]), .a(c_1[64]),
.b(c_2[64]), .cout(co[65]), .sum(sum[65]), .d(s_1[65]),
.carry(cout[65]));
mul_csa42 sc3_64_ ( .c(s_2[64]), .cin(co[63]), .a(c_1[63]),
.b(c_2[63]), .cout(co[64]), .sum(sum[64]), .d(s_1[64]),
.carry(cout[64]));
mul_csa42 sc3_63_ ( .c(s_2[63]), .cin(co[62]), .a(c_1[62]),
.b(c_2[62]), .cout(co[63]), .sum(sum[63]), .d(s_1[63]),
.carry(cout[63]));
mul_csa42 sc3_62_ ( .c(s_2[62]), .cin(co[61]), .a(c_1[61]),
.b(c_2[61]), .cout(co[62]), .sum(sum[62]), .d(s_1[62]),
.carry(cout[62]));
mul_csa42 sc3_61_ ( .c(s_2[61]), .cin(co[60]), .a(c_1[60]),
.b(c_2[60]), .cout(co[61]), .sum(sum[61]), .d(s_1[61]),
.carry(cout[61]));
mul_csa42 sc3_60_ ( .c(s_2[60]), .cin(co[59]), .a(c_1[59]),
.b(c_2[59]), .cout(co[60]), .sum(sum[60]), .d(s_1[60]),
.carry(cout[60]));
mul_csa42 sc3_59_ ( .c(s_2[59]), .cin(co[58]), .a(c_1[58]),
.b(c_2[58]), .cout(co[59]), .sum(sum[59]), .d(s_1[59]),
.carry(cout[59]));
mul_csa42 sc3_58_ ( .c(s_2[58]), .cin(co[57]), .a(c_1[57]),
.b(c_2[57]), .cout(co[58]), .sum(sum[58]), .d(s_1[58]),
.carry(cout[58]));
mul_csa42 sc3_57_ ( .c(s_2[57]), .cin(co[56]), .a(c_1[56]),
.b(c_2[56]), .cout(co[57]), .sum(sum[57]), .d(s_1[57]),
.carry(cout[57]));
mul_csa42 sc3_56_ ( .c(s_2[56]), .cin(co[55]), .a(c_1[55]),
.b(c_2[55]), .cout(co[56]), .sum(sum[56]), .d(s_1[56]),
.carry(cout[56]));
mul_csa42 sc3_55_ ( .c(s_2[55]), .cin(co[54]), .a(c_1[54]),
.b(c_2[54]), .cout(co[55]), .sum(sum[55]), .d(s_1[55]),
.carry(cout[55]));
mul_csa42 sc3_54_ ( .c(s_2[54]), .cin(co[53]), .a(c_1[53]),
.b(c_2[53]), .cout(co[54]), .sum(sum[54]), .d(s_1[54]),
.carry(cout[54]));
mul_csa42 sc3_53_ ( .c(s_2[53]), .cin(co[52]), .a(c_1[52]),
.b(c_2[52]), .cout(co[53]), .sum(sum[53]), .d(s_1[53]),
.carry(cout[53]));
mul_csa42 sc3_52_ ( .c(s_2[52]), .cin(co[51]), .a(c_1[51]),
.b(c_2[51]), .cout(co[52]), .sum(sum[52]), .d(s_1[52]),
.carry(cout[52]));
mul_csa42 sc3_51_ ( .c(s_2[51]), .cin(co[50]), .a(c_1[50]),
.b(c_2[50]), .cout(co[51]), .sum(sum[51]), .d(s_1[51]),
.carry(cout[51]));
mul_csa42 sc3_50_ ( .c(s_2[50]), .cin(co[49]), .a(c_1[49]),
.b(c_2[49]), .cout(co[50]), .sum(sum[50]), .d(s_1[50]),
.carry(cout[50]));
mul_csa42 sc3_49_ ( .c(s_2[49]), .cin(co[48]), .a(c_1[48]),
.b(c_2[48]), .cout(co[49]), .sum(sum[49]), .d(s_1[49]),
.carry(cout[49]));
mul_csa42 sc3_48_ ( .c(s_2[48]), .cin(co[47]), .a(c_1[47]),
.b(c_2[47]), .cout(co[48]), .sum(sum[48]), .d(s_1[48]),
.carry(cout[48]));
mul_csa42 sc3_47_ ( .c(s_2[47]), .cin(co[46]), .a(c_1[46]),
.b(c_2[46]), .cout(co[47]), .sum(sum[47]), .d(s_1[47]),
.carry(cout[47]));
mul_csa42 sc3_46_ ( .c(s_2[46]), .cin(co[45]), .a(c_1[45]),
.b(c_2[45]), .cout(co[46]), .sum(sum[46]), .d(s_1[46]),
.carry(cout[46]));
mul_csa42 sc3_45_ ( .c(s_2[45]), .cin(co[44]), .a(c_1[44]),
.b(c_2[44]), .cout(co[45]), .sum(sum[45]), .d(s_1[45]),
.carry(cout[45]));
mul_csa42 sc3_44_ ( .c(s_2[44]), .cin(co[43]), .a(c_1[43]),
.b(c_2[43]), .cout(co[44]), .sum(sum[44]), .d(s_1[44]),
.carry(cout[44]));
mul_csa42 sc3_43_ ( .c(s_2[43]), .cin(co[42]), .a(c_1[42]),
.b(c_2[42]), .cout(co[43]), .sum(sum[43]), .d(s_1[43]),
.carry(cout[43]));
mul_csa42 sc3_42_ ( .c(s_2[42]), .cin(co[41]), .a(c_1[41]),
.b(c_2[41]), .cout(co[42]), .sum(sum[42]), .d(s_1[42]),
.carry(cout[42]));
mul_csa42 sc3_41_ ( .c(s_2[41]), .cin(co[40]), .a(c_1[40]),
.b(c_2[40]), .cout(co[41]), .sum(sum[41]), .d(s_1[41]),
.carry(cout[41]));
mul_csa42 sc3_40_ ( .c(s_2[40]), .cin(co[39]), .a(c_1[39]),
.b(c_2[39]), .cout(co[40]), .sum(sum[40]), .d(s_1[40]),
.carry(cout[40]));
mul_csa42 sc3_39_ ( .c(s_2[39]), .cin(co[38]), .a(c_1[38]),
.b(c_2[38]), .cout(co[39]), .sum(sum[39]), .d(s_1[39]),
.carry(cout[39]));
mul_csa42 sc3_38_ ( .c(s_2[38]), .cin(co[37]), .a(c_1[37]),
.b(c_2[37]), .cout(co[38]), .sum(sum[38]), .d(s_1[38]),
.carry(cout[38]));
mul_csa42 sc3_37_ ( .c(s_2[37]), .cin(co[36]), .a(c_1[36]),
.b(c_2[36]), .cout(co[37]), .sum(sum[37]), .d(s_1[37]),
.carry(cout[37]));
mul_csa42 sc3_36_ ( .c(s_2[36]), .cin(co[35]), .a(c_1[35]),
.b(c_2[35]), .cout(co[36]), .sum(sum[36]), .d(s_1[36]),
.carry(cout[36]));
mul_csa42 sc3_35_ ( .c(s_2[35]), .cin(co[34]), .a(c_1[34]),
.b(c_2[34]), .cout(co[35]), .sum(sum[35]), .d(s_1[35]),
.carry(cout[35]));
mul_csa42 sc3_34_ ( .c(s_2[34]), .cin(co[33]), .a(c_1[33]),
.b(c_2[33]), .cout(co[34]), .sum(sum[34]), .d(s_1[34]),
.carry(cout[34]));
mul_csa42 sc3_33_ ( .c(s_2[33]), .cin(co[32]), .a(c_1[32]),
.b(c_2[32]), .cout(co[33]), .sum(sum[33]), .d(s_1[33]),
.carry(cout[33]));
mul_csa42 sc3_32_ ( .c(s_2[32]), .cin(co[31]), .a(c_1[31]),
.b(c_2[31]), .cout(co[32]), .sum(sum[32]), .d(s_1[32]),
.carry(cout[32]));
mul_csa42 sc3_31_ ( .c(s_2[31]), .cin(co[30]), .a(c_1[30]),
.b(c_2[30]), .cout(co[31]), .sum(sum[31]), .d(s_1[31]),
.carry(cout[31]));
mul_csa42 sc3_30_ ( .c(s_2[30]), .cin(co[29]), .a(c_1[29]),
.b(c_2[29]), .cout(co[30]), .sum(sum[30]), .d(s_1[30]),
.carry(cout[30]));
mul_csa42 sc3_29_ ( .c(s_2[29]), .cin(co[28]), .a(c_1[28]),
.b(c_2[28]), .cout(co[29]), .sum(sum[29]), .d(s_1[29]),
.carry(cout[29]));
mul_csa42 sc3_28_ ( .c(s_2[28]), .cin(co[27]), .a(c_1[27]),
.b(c_2[27]), .cout(co[28]), .sum(sum[28]), .d(s_1[28]),
.carry(cout[28]));
mul_csa42 sc3_27_ ( .c(s_2[27]), .cin(co[26]), .a(c_1[26]),
.b(c_2[26]), .cout(co[27]), .sum(sum[27]), .d(s_1[27]),
.carry(cout[27]));
mul_csa42 sc3_26_ ( .c(s_2[26]), .cin(co[25]), .a(c_1[25]),
.b(c_2[25]), .cout(co[26]), .sum(sum[26]), .d(s_1[26]),
.carry(cout[26]));
mul_csa42 sc3_25_ ( .c(s_2[25]), .cin(co[24]), .a(c_1[24]),
.b(c_2[24]), .cout(co[25]), .sum(sum[25]), .d(s_1[25]),
.carry(cout[25]));
mul_csa42 sc3_24_ ( .c(s_2[24]), .cin(co[23]), .a(c_1[23]),
.b(c_2[23]), .cout(co[24]), .sum(sum[24]), .d(s_1[24]),
.carry(cout[24]));
mul_csa42 sc3_23_ ( .c(s_2[23]), .cin(co[22]), .a(c_1[22]),
.b(c_2[22]), .cout(co[23]), .sum(sum[23]), .d(s_1[23]),
.carry(cout[23]));
mul_csa42 sc3_22_ ( .c(s_2[22]), .cin(co[21]), .a(c_1[21]),
.b(c_2[21]), .cout(co[22]), .sum(sum[22]), .d(s_1[22]),
.carry(cout[22]));
mul_csa42 sc3_21_ ( .c(s_2[21]), .cin(co[20]), .a(c_1[20]),
.b(c_2[20]), .cout(co[21]), .sum(sum[21]), .d(s_1[21]),
.carry(cout[21]));
mul_csa42 sc3_20_ ( .c(s_2[20]), .cin(co[19]), .a(c_1[19]),
.b(c_2[19]), .cout(co[20]), .sum(sum[20]), .d(s_1[20]),
.carry(cout[20]));
mul_csa42 sc3_19_ ( .c(s_2[19]), .cin(co[18]), .a(c_1[18]),
.b(c_2[18]), .cout(co[19]), .sum(sum[19]), .d(s_1[19]),
.carry(cout[19]));
mul_csa42 sc3_18_ ( .c(s_2[18]), .cin(co[17]), .a(c_1[17]),
.b(c_2[17]), .cout(co[18]), .sum(sum[18]), .d(s_1[18]),
.carry(cout[18]));
mul_csa42 sc3_17_ ( .c(s_2[17]), .cin(co[16]), .a(c_1[16]),
.b(c_2[16]), .cout(co[17]), .sum(sum[17]), .d(s_1[17]),
.carry(cout[17]));
mul_csa42 sc3_16_ ( .c(s_2[16]), .cin(co[15]), .a(c_1[15]),
.b(c_2[15]), .cout(co[16]), .sum(sum[16]), .d(s_1[16]),
.carry(cout[16]));
mul_csa42 sc3_15_ ( .c(s_2[15]), .cin(co[14]), .a(c_1[14]),
.b(c_2[14]), .cout(co[15]), .sum(sum[15]), .d(s_1[15]),
.carry(cout[15]));
mul_csa42 sc3_14_ ( .c(s_2[14]), .cin(co[13]), .a(c_1[13]),
.b(c_2[13]), .cout(co[14]), .sum(sum[14]), .d(s_1[14]),
.carry(cout[14]));
mul_csa42 sc3_13_ ( .c(s_2[13]), .cin(co[12]), .a(c_1[12]),
.b(c_2[12]), .cout(co[13]), .sum(sum[13]), .d(s_1[13]),
.carry(cout[13]));
mul_csa42 sc3_12_ ( .c(s_2[12]), .cin(co[11]), .a(c_1[11]),
.b(c_2[11]), .cout(co[12]), .sum(sum[12]), .d(s_1[12]),
.carry(cout[12]));
mul_csa42 sc3_11_ ( .c(s_2[11]), .cin(1'b0),
.a(c_1[10]), .b(c_2[10]), .cout(co[11]), .sum(sum[11]),
.d(s_1[11]), .carry(cout[11]));
mul_csa32 sc2_2_70_ ( .c(c1[63]), .b(c2[57]), .a(s2[58]),
.cout(c_2[70]), .sum(s_2[70]));
mul_csa32 sc2_2_69_ ( .c(c1[62]), .b(c2[56]), .a(s2[57]),
.cout(c_2[69]), .sum(s_2[69]));
mul_csa32 sc2_2_68_ ( .c(c1[61]), .b(c2[55]), .a(s2[56]),
.cout(c_2[68]), .sum(s_2[68]));
mul_csa32 sc2_2_67_ ( .c(c1[60]), .b(c2[54]), .a(s2[55]),
.cout(c_2[67]), .sum(s_2[67]));
mul_csa32 sc2_2_66_ ( .c(c1[59]), .b(c2[53]), .a(s2[54]),
.cout(c_2[66]), .sum(s_2[66]));
mul_csa32 sc2_2_65_ ( .c(c1[58]), .b(c2[52]), .a(s2[53]),
.cout(c_2[65]), .sum(s_2[65]));
mul_csa32 sc2_2_64_ ( .c(c1[57]), .b(c2[51]), .a(s2[52]),
.cout(c_2[64]), .sum(s_2[64]));
mul_csa32 sc2_2_63_ ( .c(c1[56]), .b(c2[50]), .a(s2[51]),
.cout(c_2[63]), .sum(s_2[63]));
mul_csa32 sc2_2_62_ ( .c(c1[55]), .b(c2[49]), .a(s2[50]),
.cout(c_2[62]), .sum(s_2[62]));
mul_csa32 sc2_2_61_ ( .c(c1[54]), .b(c2[48]), .a(s2[49]),
.cout(c_2[61]), .sum(s_2[61]));
mul_csa32 sc2_2_60_ ( .c(c1[53]), .b(c2[47]), .a(s2[48]),
.cout(c_2[60]), .sum(s_2[60]));
mul_csa32 sc2_2_59_ ( .c(c1[52]), .b(c2[46]), .a(s2[47]),
.cout(c_2[59]), .sum(s_2[59]));
mul_csa32 sc2_2_58_ ( .c(c1[51]), .b(c2[45]), .a(s2[46]),
.cout(c_2[58]), .sum(s_2[58]));
mul_csa32 sc2_2_57_ ( .c(c1[50]), .b(c2[44]), .a(s2[45]),
.cout(c_2[57]), .sum(s_2[57]));
mul_csa32 sc2_2_56_ ( .c(c1[49]), .b(c2[43]), .a(s2[44]),
.cout(c_2[56]), .sum(s_2[56]));
mul_csa32 sc2_2_55_ ( .c(c1[48]), .b(c2[42]), .a(s2[43]),
.cout(c_2[55]), .sum(s_2[55]));
mul_csa32 sc2_2_54_ ( .c(c1[47]), .b(c2[41]), .a(s2[42]),
.cout(c_2[54]), .sum(s_2[54]));
mul_csa32 sc2_2_53_ ( .c(c1[46]), .b(c2[40]), .a(s2[41]),
.cout(c_2[53]), .sum(s_2[53]));
mul_csa32 sc2_2_52_ ( .c(c1[45]), .b(c2[39]), .a(s2[40]),
.cout(c_2[52]), .sum(s_2[52]));
mul_csa32 sc2_2_51_ ( .c(c1[44]), .b(c2[38]), .a(s2[39]),
.cout(c_2[51]), .sum(s_2[51]));
mul_csa32 sc2_2_50_ ( .c(c1[43]), .b(c2[37]), .a(s2[38]),
.cout(c_2[50]), .sum(s_2[50]));
mul_csa32 sc2_2_49_ ( .c(c1[42]), .b(c2[36]), .a(s2[37]),
.cout(c_2[49]), .sum(s_2[49]));
mul_csa32 sc2_2_48_ ( .c(c1[41]), .b(c2[35]), .a(s2[36]),
.cout(c_2[48]), .sum(s_2[48]));
mul_csa32 sc2_2_47_ ( .c(c1[40]), .b(c2[34]), .a(s2[35]),
.cout(c_2[47]), .sum(s_2[47]));
mul_csa32 sc2_2_46_ ( .c(c1[39]), .b(c2[33]), .a(s2[34]),
.cout(c_2[46]), .sum(s_2[46]));
mul_csa32 sc2_2_45_ ( .c(c1[38]), .b(c2[32]), .a(s2[33]),
.cout(c_2[45]), .sum(s_2[45]));
mul_csa32 sc2_2_44_ ( .c(c1[37]), .b(c2[31]), .a(s2[32]),
.cout(c_2[44]), .sum(s_2[44]));
mul_csa32 sc2_2_43_ ( .c(c1[36]), .b(c2[30]), .a(s2[31]),
.cout(c_2[43]), .sum(s_2[43]));
mul_csa32 sc2_2_42_ ( .c(c1[35]), .b(c2[29]), .a(s2[30]),
.cout(c_2[42]), .sum(s_2[42]));
mul_csa32 sc2_2_41_ ( .c(c1[34]), .b(c2[28]), .a(s2[29]),
.cout(c_2[41]), .sum(s_2[41]));
mul_csa32 sc2_2_40_ ( .c(c1[33]), .b(c2[27]), .a(s2[28]),
.cout(c_2[40]), .sum(s_2[40]));
mul_csa32 sc2_2_39_ ( .c(c1[32]), .b(c2[26]), .a(s2[27]),
.cout(c_2[39]), .sum(s_2[39]));
mul_csa32 sc2_2_38_ ( .c(c1[31]), .b(c2[25]), .a(s2[26]),
.cout(c_2[38]), .sum(s_2[38]));
mul_csa32 sc2_2_37_ ( .c(c1[30]), .b(c2[24]), .a(s2[25]),
.cout(c_2[37]), .sum(s_2[37]));
mul_csa32 sc2_2_36_ ( .c(c1[29]), .b(c2[23]), .a(s2[24]),
.cout(c_2[36]), .sum(s_2[36]));
mul_csa32 sc2_2_35_ ( .c(c1[28]), .b(c2[22]), .a(s2[23]),
.cout(c_2[35]), .sum(s_2[35]));
mul_csa32 sc2_2_34_ ( .c(c1[27]), .b(c2[21]), .a(s2[22]),
.cout(c_2[34]), .sum(s_2[34]));
mul_csa32 sc2_2_33_ ( .c(c1[26]), .b(c2[20]), .a(s2[21]),
.cout(c_2[33]), .sum(s_2[33]));
mul_csa32 sc2_2_32_ ( .c(c1[25]), .b(c2[19]), .a(s2[20]),
.cout(c_2[32]), .sum(s_2[32]));
mul_csa32 sc2_2_31_ ( .c(c1[24]), .b(c2[18]), .a(s2[19]),
.cout(c_2[31]), .sum(s_2[31]));
mul_csa32 sc2_2_30_ ( .c(c1[23]), .b(c2[17]), .a(s2[18]),
.cout(c_2[30]), .sum(s_2[30]));
mul_csa32 sc2_2_29_ ( .c(c1[22]), .b(c2[16]), .a(s2[17]),
.cout(c_2[29]), .sum(s_2[29]));
mul_csa32 sc2_2_28_ ( .c(c1[21]), .b(c2[15]), .a(s2[16]),
.cout(c_2[28]), .sum(s_2[28]));
mul_csa32 sc2_2_27_ ( .c(c1[20]), .b(c2[14]), .a(s2[15]),
.cout(c_2[27]), .sum(s_2[27]));
mul_csa32 sc2_2_26_ ( .c(c1[19]), .b(c2[13]), .a(s2[14]),
.cout(c_2[26]), .sum(s_2[26]));
mul_csa32 sc2_2_25_ ( .c(c1[18]), .b(c2[12]), .a(s2[13]),
.cout(c_2[25]), .sum(s_2[25]));
mul_csa32 sc2_2_24_ ( .c(c1[17]), .b(c2[11]), .a(s2[12]),
.cout(c_2[24]), .sum(s_2[24]));
mul_csa32 sc2_2_23_ ( .c(c1[16]), .b(c2[10]), .a(s2[11]),
.cout(c_2[23]), .sum(s_2[23]));
mul_csa32 sc2_2_22_ ( .c(c1[15]), .b(c2[9]), .a(s2[10]),
.cout(c_2[22]), .sum(s_2[22]));
mul_csa32 sc2_2_21_ ( .c(c1[14]), .b(c2[8]), .a(s2[9]),
.cout(c_2[21]), .sum(s_2[21]));
mul_csa32 sc2_2_20_ ( .c(c1[13]), .b(c2[7]), .a(s2[8]),
.cout(c_2[20]), .sum(s_2[20]));
mul_csa32 sc2_2_19_ ( .c(c1[12]), .b(c2[6]), .a(s2[7]),
.cout(c_2[19]), .sum(s_2[19]));
mul_csa32 sc2_2_18_ ( .c(c1[11]), .b(c2[5]), .a(s2[6]),
.cout(c_2[18]), .sum(s_2[18]));
mul_csa32 sc2_2_17_ ( .c(c1[10]), .b(c2[4]), .a(s2[5]),
.cout(c_2[17]), .sum(s_2[17]));
mul_csa32 sc2_2_16_ ( .c(c1[9]), .b(c2[3]), .a(s2[4]),
.cout(c_2[16]), .sum(s_2[16]));
mul_csa32 sc2_2_15_ ( .c(c1[8]), .b(c2[2]), .a(s2[3]),
.cout(c_2[15]), .sum(s_2[15]));
mul_csa32 sc2_2_14_ ( .c(c1[7]), .b(c2[1]), .a(s2[2]),
.cout(c_2[14]), .sum(s_2[14]));
mul_csa32 sc2_2_13_ ( .c(c1[6]), .b(s1[7]), .a(s2[1]),
.cout(c_2[13]), .sum(s_2[13]));
mul_csa32 sc2_2_12_ ( .c(c1[5]), .b(s1[6]), .a(s2[0]),
.cout(c_2[12]), .sum(s_2[12]));
mul_csa32 sc2_2_11_ ( .c(c1[4]), .b(s1[5]), .a(b5n[1]),
.cout(c_2[11]), .sum(s_2[11]));
mul_csa32 sc2_2_10_ ( .c(c1[3]), .b(s1[4]), .a(b5n[0]),
.cout(c_2[10]), .sum(s_2[10]));
mul_csa32 sc2_2_76_ ( .c(1'b1), .b(c2[63]), .a(s2[64]),
.cout(c_2[76]), .sum(s_2[76]));
mul_csa32 sc2_2_77_ ( .c(c_2[76]), .b(c2[64]), .a(s2[65]),
.cout(cout[77]), .sum(sum[77]));
mul_csa32 sc2_1_9_ ( .c(s1[3]), .b(c0[8]), .a(s0[9]), .cout(c_1[9]),
.sum(s_1[9]));
mul_csa32 sc2_1_8_ ( .c(s1[2]), .b(c0[7]), .a(s0[8]), .cout(c_1[8]),
.sum(s_1[8]));
mul_csa32 sc2_1_3_ ( .c(c_1[2]), .b(c0[2]), .a(s0[3]),
.cout(c_1[3]), .sum(sum[3]));
mul_csa32 sc3_10_ ( .c(s_2[10]), .b(s_1[10]), .a(c_1[9]),
.cout(cout[10]), .sum(sum[10]));
mul_csa32 sc3_9_ ( .c(c1[2]), .sum(sum[9]), .cout(cout[9]),
.a(c_1[8]), .b(s_1[9]));
mul_csa32 sc3_8_ ( .c(c1[1]), .sum(sum[8]), .cout(cout[8]),
.a(c_1[7]), .b(s_1[8]));
mul_csa32 sc2_2_71_ ( .c(c1[64]), .b(c2[58]), .a(s2[59]),
.cout(c_2[71]), .sum(s_2[71]));
mul_csa32 sc2_2_75_ ( .c(c1[68]), .b(c2[62]), .a(s2[63]),
.cout(c_2[75]), .sum(s_2[75]));
mul_csa32 sc2_2_74_ ( .c(c1[67]), .b(c2[61]), .a(s2[62]),
.cout(c_2[74]), .sum(s_2[74]));
mul_csa32 sc2_2_73_ ( .c(c1[66]), .b(c2[60]), .a(s2[61]),
.cout(c_2[73]), .sum(s_2[73]));
mul_csa32 sc2_2_72_ ( .c(c1[65]), .b(c2[59]), .a(s2[60]),
.cout(c_2[72]), .sum(s_2[72]));
mul_csa32 sc2_1_69_ ( .c(s1[63]), .sum(s_1[69]), .cout(c_1[69]),
.a(s0[69]), .b(c0[68]));
mul_csa32 sc2_1_68_ ( .c(s1[62]), .sum(s_1[68]), .cout(c_1[68]),
.a(s0[68]), .b(c0[67]));
mul_csa32 sc2_1_67_ ( .c(s1[61]), .sum(s_1[67]), .cout(c_1[67]),
.a(s0[67]), .b(c0[66]));
mul_csa32 sc2_1_66_ ( .c(s1[60]), .sum(s_1[66]), .cout(c_1[66]),
.a(s0[66]), .b(c0[65]));
mul_csa32 sc2_1_65_ ( .c(s1[59]), .sum(s_1[65]), .cout(c_1[65]),
.a(s0[65]), .b(c0[64]));
mul_csa32 sc2_1_64_ ( .c(s1[58]), .sum(s_1[64]), .cout(c_1[64]),
.a(s0[64]), .b(c0[63]));
mul_csa32 sc2_1_63_ ( .c(s1[57]), .sum(s_1[63]), .cout(c_1[63]),
.a(s0[63]), .b(c0[62]));
mul_csa32 sc2_1_62_ ( .c(s1[56]), .sum(s_1[62]), .cout(c_1[62]),
.a(s0[62]), .b(c0[61]));
mul_csa32 sc2_1_61_ ( .c(s1[55]), .sum(s_1[61]), .cout(c_1[61]),
.a(s0[61]), .b(c0[60]));
mul_csa32 sc2_1_60_ ( .c(s1[54]), .sum(s_1[60]), .cout(c_1[60]),
.a(s0[60]), .b(c0[59]));
mul_csa32 sc2_1_59_ ( .c(s1[53]), .sum(s_1[59]), .cout(c_1[59]),
.a(s0[59]), .b(c0[58]));
mul_csa32 sc2_1_58_ ( .c(s1[52]), .sum(s_1[58]), .cout(c_1[58]),
.a(s0[58]), .b(c0[57]));
mul_csa32 sc2_1_57_ ( .c(s1[51]), .sum(s_1[57]), .cout(c_1[57]),
.a(s0[57]), .b(c0[56]));
mul_csa32 sc2_1_56_ ( .c(s1[50]), .sum(s_1[56]), .cout(c_1[56]),
.a(s0[56]), .b(c0[55]));
mul_csa32 sc2_1_55_ ( .c(s1[49]), .sum(s_1[55]), .cout(c_1[55]),
.a(s0[55]), .b(c0[54]));
mul_csa32 sc2_1_54_ ( .c(s1[48]), .sum(s_1[54]), .cout(c_1[54]),
.a(s0[54]), .b(c0[53]));
mul_csa32 sc2_1_53_ ( .c(s1[47]), .sum(s_1[53]), .cout(c_1[53]),
.a(s0[53]), .b(c0[52]));
mul_csa32 sc2_1_52_ ( .c(s1[46]), .sum(s_1[52]), .cout(c_1[52]),
.a(s0[52]), .b(c0[51]));
mul_csa32 sc2_1_51_ ( .c(s1[45]), .sum(s_1[51]), .cout(c_1[51]),
.a(s0[51]), .b(c0[50]));
mul_csa32 sc2_1_50_ ( .c(s1[44]), .sum(s_1[50]), .cout(c_1[50]),
.a(s0[50]), .b(c0[49]));
mul_csa32 sc2_1_49_ ( .c(s1[43]), .sum(s_1[49]), .cout(c_1[49]),
.a(s0[49]), .b(c0[48]));
mul_csa32 sc2_1_48_ ( .c(s1[42]), .sum(s_1[48]), .cout(c_1[48]),
.a(s0[48]), .b(c0[47]));
mul_csa32 sc2_1_47_ ( .c(s1[41]), .sum(s_1[47]), .cout(c_1[47]),
.a(s0[47]), .b(c0[46]));
mul_csa32 sc2_1_46_ ( .c(s1[40]), .sum(s_1[46]), .cout(c_1[46]),
.a(s0[46]), .b(c0[45]));
mul_csa32 sc2_1_45_ ( .c(s1[39]), .sum(s_1[45]), .cout(c_1[45]),
.a(s0[45]), .b(c0[44]));
mul_csa32 sc2_1_44_ ( .c(s1[38]), .sum(s_1[44]), .cout(c_1[44]),
.a(s0[44]), .b(c0[43]));
mul_csa32 sc2_1_43_ ( .c(s1[37]), .sum(s_1[43]), .cout(c_1[43]),
.a(s0[43]), .b(c0[42]));
mul_csa32 sc2_1_42_ ( .c(s1[36]), .sum(s_1[42]), .cout(c_1[42]),
.a(s0[42]), .b(c0[41]));
mul_csa32 sc2_1_41_ ( .c(s1[35]), .sum(s_1[41]), .cout(c_1[41]),
.a(s0[41]), .b(c0[40]));
mul_csa32 sc2_1_40_ ( .c(s1[34]), .sum(s_1[40]), .cout(c_1[40]),
.a(s0[40]), .b(c0[39]));
mul_csa32 sc2_1_39_ ( .c(s1[33]), .sum(s_1[39]), .cout(c_1[39]),
.a(s0[39]), .b(c0[38]));
mul_csa32 sc2_1_38_ ( .c(s1[32]), .sum(s_1[38]), .cout(c_1[38]),
.a(s0[38]), .b(c0[37]));
mul_csa32 sc2_1_37_ ( .c(s1[31]), .sum(s_1[37]), .cout(c_1[37]),
.a(s0[37]), .b(c0[36]));
mul_csa32 sc2_1_36_ ( .c(s1[30]), .sum(s_1[36]), .cout(c_1[36]),
.a(s0[36]), .b(c0[35]));
mul_csa32 sc2_1_35_ ( .c(s1[29]), .sum(s_1[35]), .cout(c_1[35]),
.a(s0[35]), .b(c0[34]));
mul_csa32 sc2_1_34_ ( .c(s1[28]), .sum(s_1[34]), .cout(c_1[34]),
.a(s0[34]), .b(c0[33]));
mul_csa32 sc2_1_33_ ( .c(s1[27]), .sum(s_1[33]), .cout(c_1[33]),
.a(s0[33]), .b(c0[32]));
mul_csa32 sc2_1_32_ ( .c(s1[26]), .sum(s_1[32]), .cout(c_1[32]),
.a(s0[32]), .b(c0[31]));
mul_csa32 sc2_1_31_ ( .c(s1[25]), .sum(s_1[31]), .cout(c_1[31]),
.a(s0[31]), .b(c0[30]));
mul_csa32 sc2_1_30_ ( .c(s1[24]), .sum(s_1[30]), .cout(c_1[30]),
.a(s0[30]), .b(c0[29]));
mul_csa32 sc2_1_29_ ( .c(s1[23]), .sum(s_1[29]), .cout(c_1[29]),
.a(s0[29]), .b(c0[28]));
mul_csa32 sc2_1_28_ ( .c(s1[22]), .sum(s_1[28]), .cout(c_1[28]),
.a(s0[28]), .b(c0[27]));
mul_csa32 sc2_1_27_ ( .c(s1[21]), .sum(s_1[27]), .cout(c_1[27]),
.a(s0[27]), .b(c0[26]));
mul_csa32 sc2_1_26_ ( .c(s1[20]), .sum(s_1[26]), .cout(c_1[26]),
.a(s0[26]), .b(c0[25]));
mul_csa32 sc2_1_25_ ( .c(s1[19]), .sum(s_1[25]), .cout(c_1[25]),
.a(s0[25]), .b(c0[24]));
mul_csa32 sc2_1_24_ ( .c(s1[18]), .sum(s_1[24]), .cout(c_1[24]),
.a(s0[24]), .b(c0[23]));
mul_csa32 sc2_1_23_ ( .c(s1[17]), .sum(s_1[23]), .cout(c_1[23]),
.a(s0[23]), .b(c0[22]));
mul_csa32 sc2_1_22_ ( .c(s1[16]), .sum(s_1[22]), .cout(c_1[22]),
.a(s0[22]), .b(c0[21]));
mul_csa32 sc2_1_21_ ( .c(s1[15]), .sum(s_1[21]), .cout(c_1[21]),
.a(s0[21]), .b(c0[20]));
mul_csa32 sc2_1_20_ ( .c(s1[14]), .sum(s_1[20]), .cout(c_1[20]),
.a(s0[20]), .b(c0[19]));
mul_csa32 sc2_1_19_ ( .c(s1[13]), .sum(s_1[19]), .cout(c_1[19]),
.a(s0[19]), .b(c0[18]));
mul_csa32 sc2_1_18_ ( .c(s1[12]), .sum(s_1[18]), .cout(c_1[18]),
.a(s0[18]), .b(c0[17]));
mul_csa32 sc2_1_17_ ( .c(s1[11]), .sum(s_1[17]), .cout(c_1[17]),
.a(s0[17]), .b(c0[16]));
mul_csa32 sc2_1_16_ ( .c(s1[10]), .sum(s_1[16]), .cout(c_1[16]),
.a(s0[16]), .b(c0[15]));
mul_csa32 sc2_1_15_ ( .c(s1[9]), .sum(s_1[15]), .cout(c_1[15]),
.a(s0[15]), .b(c0[14]));
mul_csa32 sc2_1_14_ ( .c(s1[8]), .sum(s_1[14]), .cout(c_1[14]),
.a(s0[14]), .b(c0[13]));
mul_csa32 sc2_1_7_ ( .c(s1[1]), .b(c0[6]), .a(s0[7]), .cout(c_1[7]),
.sum(s_1[7]));
mul_csa32 sc2_1_6_ ( .c(s1[0]), .b(c0[5]), .a(s0[6]), .cout(c_1[6]),
.sum(s_1[6]));
mul_csa32 sc2_1_5_ ( .c(b2n[1]), .b(c0[4]), .a(s0[5]),
.cout(c_1[5]), .sum(s_1[5]));
mul_csa32 sc2_1_4_ ( .c(b2n[0]), .b(c0[3]), .a(s0[4]),
.cout(c_1[4]), .sum(s_1[4]));
mul_ha sc2_1_10_ ( .sum(s_1[10]), .cout(c_1[10]), .a(s0[10]),
.b(c0[9]));
mul_ha sc3_7_ ( .sum(sum[7]), .cout(cout[7]), .a(c_1[6]),
.b(s_1[7]));
mul_ha sc3_6_ ( .sum(sum[6]), .cout(cout[6]), .a(c_1[5]),
.b(s_1[6]));
mul_ha sc3_5_ ( .sum(sum[5]), .cout(cout[5]), .a(c_1[4]),
.b(s_1[5]));
mul_ha sc3_4_ ( .sum(sum[4]), .cout(cout[4]), .a(c_1[3]),
.b(s_1[4]));
mul_ha sc2_2_81_ ( .sum(sum[81]), .cout(cout[81]), .a(s2[69]),
.b(c2[68]));
mul_ha sc2_2_80_ ( .sum(sum[80]), .cout(cout[80]), .a(s2[68]),
.b(c2[67]));
mul_ha sc2_2_79_ ( .sum(sum[79]), .cout(cout[79]), .a(s2[67]),
.b(c2[66]));
mul_ha sc2_2_78_ ( .sum(sum[78]), .cout(cout[78]), .a(s2[66]),
.b(c2[65]));
mul_ha sc2_1_70_ ( .sum(s_1[70]), .cout(c_1[70]),
.a(1'b1), .b(s1[64]));
mul_ha sc2_1_2_ ( .sum(sum[2]), .cout(c_1[2]), .a(s0[2]), .b(c0[1]));
mul_ha sc2_1_13_ ( .sum(s_1[13]), .cout(c_1[13]), .a(s0[13]),
.b(c0[12]));
mul_ha sc2_1_12_ ( .sum(s_1[12]), .cout(c_1[12]), .a(s0[12]),
.b(c0[11]));
mul_ha sc2_1_11_ ( .sum(s_1[11]), .cout(c_1[11]), .a(s0[11]),
.b(c0[10]));
mul_ppgenrow3 I2 ( .head(1'b0), .bot(bot), .b2(b8[2:0]),
.b1(b7[2:0]), .b0(b6[2:0]), .a(a[63:0]), .sum(s2[69:0]),
.cout(c2[68:1]));
mul_ppgenrow3 I1 ( .head(1'b0), .bot(1'b1),
.b2(b5[2:0]), .b1(b4[2:0]), .b0(b3[2:0]), .a(a[63:0]),
.sum(s1[69:0]), .cout(c1[68:1]));
mul_ppgenrow3 I0 ( .head(head), .bot(1'b1), .b2(b2[2:0]),
.b1(b1[2:0]), .b0(b0[2:0]), .a(a[63:0]), .sum({s0[69:2],
sum[1:0]}), .cout(c0[68:1]));
endmodule // mul_array1
module mul_array2 ( pcout, pcoutx2, psum, psumx2, a0c, a0s, a1c, a1s,
areg, bot, pc, ps, x2 );
output pcoutx2, psumx2;
input bot, x2;
output [98:0] psum;
output [98:0] pcout;
input [81:4] a1c;
input [98:30] pc;
input [98:31] ps;
input [81:0] a0s;
input [96:0] areg;
input [81:0] a1s;
input [81:4] a0c;
// Buses in the design
wire [81:15] s3;
wire [81:15] c3;
wire [96:0] ain;
wire [67:20] co;
wire [82:0] s1;
wire [96:0] c2;
wire [82:0] c1;
wire [96:0] s2;
wire ainx2, s1x2, c1x2;
mul_mux2 sh_82_ ( .d1(areg[83]), .z(ain[82]), .d0(areg[82]), .s(x2));
mul_mux2 sh_68_ ( .d1(areg[69]), .z(ain[68]), .d0(areg[68]), .s(x2));
mul_mux2 sh_67_ ( .d1(areg[68]), .z(ain[67]), .d0(areg[67]), .s(x2));
mul_mux2 sh_66_ ( .d1(areg[67]), .z(ain[66]), .d0(areg[66]), .s(x2));
mul_mux2 sh_65_ ( .d1(areg[66]), .z(ain[65]), .d0(areg[65]), .s(x2));
mul_mux2 sh_64_ ( .d1(areg[65]), .z(ain[64]), .d0(areg[64]), .s(x2));
mul_mux2 sh_63_ ( .d1(areg[64]), .z(ain[63]), .d0(areg[63]), .s(x2));
mul_mux2 sh_62_ ( .d1(areg[63]), .z(ain[62]), .d0(areg[62]), .s(x2));
mul_mux2 sh_61_ ( .d1(areg[62]), .z(ain[61]), .d0(areg[61]), .s(x2));
mul_mux2 sh_60_ ( .d1(areg[61]), .z(ain[60]), .d0(areg[60]), .s(x2));
mul_mux2 sh_59_ ( .d1(areg[60]), .z(ain[59]), .d0(areg[59]), .s(x2));
mul_mux2 sh_58_ ( .d1(areg[59]), .z(ain[58]), .d0(areg[58]), .s(x2));
mul_mux2 sh_57_ ( .d1(areg[58]), .z(ain[57]), .d0(areg[57]), .s(x2));
mul_mux2 sh_56_ ( .d1(areg[57]), .z(ain[56]), .d0(areg[56]), .s(x2));
mul_mux2 sh_55_ ( .d1(areg[56]), .z(ain[55]), .d0(areg[55]), .s(x2));
mul_mux2 sh_54_ ( .d1(areg[55]), .z(ain[54]), .d0(areg[54]), .s(x2));
mul_mux2 sh_53_ ( .d1(areg[54]), .z(ain[53]), .d0(areg[53]), .s(x2));
mul_mux2 sh_52_ ( .d1(areg[53]), .z(ain[52]), .d0(areg[52]), .s(x2));
mul_mux2 sh_51_ ( .d1(areg[52]), .z(ain[51]), .d0(areg[51]), .s(x2));
mul_mux2 sh_50_ ( .d1(areg[51]), .z(ain[50]), .d0(areg[50]), .s(x2));
mul_mux2 sh_49_ ( .d1(areg[50]), .z(ain[49]), .d0(areg[49]), .s(x2));
mul_mux2 sh_48_ ( .d1(areg[49]), .z(ain[48]), .d0(areg[48]), .s(x2));
mul_mux2 sh_47_ ( .d1(areg[48]), .z(ain[47]), .d0(areg[47]), .s(x2));
mul_mux2 sh_46_ ( .d1(areg[47]), .z(ain[46]), .d0(areg[46]), .s(x2));
mul_mux2 sh_45_ ( .d1(areg[46]), .z(ain[45]), .d0(areg[45]), .s(x2));
mul_mux2 sh_44_ ( .d1(areg[45]), .z(ain[44]), .d0(areg[44]), .s(x2));
mul_mux2 sh_43_ ( .d1(areg[44]), .z(ain[43]), .d0(areg[43]), .s(x2));
mul_mux2 sh_42_ ( .d1(areg[43]), .z(ain[42]), .d0(areg[42]), .s(x2));
mul_mux2 sh_41_ ( .d1(areg[42]), .z(ain[41]), .d0(areg[41]), .s(x2));
mul_mux2 sh_40_ ( .d1(areg[41]), .z(ain[40]), .d0(areg[40]), .s(x2));
mul_mux2 sh_39_ ( .d1(areg[40]), .z(ain[39]), .d0(areg[39]), .s(x2));
mul_mux2 sh_38_ ( .d1(areg[39]), .z(ain[38]), .d0(areg[38]), .s(x2));
mul_mux2 sh_37_ ( .d1(areg[38]), .z(ain[37]), .d0(areg[37]), .s(x2));
mul_mux2 sh_36_ ( .d1(areg[37]), .z(ain[36]), .d0(areg[36]), .s(x2));
mul_mux2 sh_35_ ( .d1(areg[36]), .z(ain[35]), .d0(areg[35]), .s(x2));
mul_mux2 sh_34_ ( .d1(areg[35]), .z(ain[34]), .d0(areg[34]), .s(x2));
mul_mux2 sh_33_ ( .d1(areg[34]), .z(ain[33]), .d0(areg[33]), .s(x2));
mul_mux2 sh_32_ ( .d1(areg[33]), .z(ain[32]), .d0(areg[32]), .s(x2));
mul_mux2 sh_31_ ( .d1(areg[32]), .z(ain[31]), .d0(areg[31]), .s(x2));
mul_mux2 sh_30_ ( .d1(areg[31]), .z(ain[30]), .d0(areg[30]), .s(x2));
mul_mux2 sh_29_ ( .d1(areg[30]), .z(ain[29]), .d0(areg[29]), .s(x2));
mul_mux2 sh_28_ ( .d1(areg[29]), .z(ain[28]), .d0(areg[28]), .s(x2));
mul_mux2 sh_27_ ( .d1(areg[28]), .z(ain[27]), .d0(areg[27]), .s(x2));
mul_mux2 sh_26_ ( .d1(areg[27]), .z(ain[26]), .d0(areg[26]), .s(x2));
mul_mux2 sh_25_ ( .d1(areg[26]), .z(ain[25]), .d0(areg[25]), .s(x2));
mul_mux2 sh_24_ ( .d1(areg[25]), .z(ain[24]), .d0(areg[24]), .s(x2));
mul_mux2 sh_23_ ( .d1(areg[24]), .z(ain[23]), .d0(areg[23]), .s(x2));
mul_mux2 sh_22_ ( .d1(areg[23]), .z(ain[22]), .d0(areg[22]), .s(x2));
mul_mux2 sh_21_ ( .d1(areg[22]), .z(ain[21]), .d0(areg[21]), .s(x2));
mul_mux2 sh_20_ ( .d1(areg[21]), .z(ain[20]), .d0(areg[20]), .s(x2));
mul_mux2 sh_96_ ( .d1(1'b0), .z(ain[96]), .d0(areg[96]),
.s(x2));
mul_mux2 sh_95_ ( .d1(areg[96]), .z(ain[95]), .d0(areg[95]), .s(x2));
mul_mux2 sh_94_ ( .d1(areg[95]), .z(ain[94]), .d0(areg[94]), .s(x2));
mul_mux2 sh_93_ ( .d1(areg[94]), .z(ain[93]), .d0(areg[93]), .s(x2));
mul_mux2 sh_92_ ( .d1(areg[93]), .z(ain[92]), .d0(areg[92]), .s(x2));
mul_mux2 sh_91_ ( .d1(areg[92]), .z(ain[91]), .d0(areg[91]), .s(x2));
mul_mux2 sh_90_ ( .d1(areg[91]), .z(ain[90]), .d0(areg[90]), .s(x2));
mul_mux2 sh_89_ ( .d1(areg[90]), .z(ain[89]), .d0(areg[89]), .s(x2));
mul_mux2 sh_88_ ( .d1(areg[89]), .z(ain[88]), .d0(areg[88]), .s(x2));
mul_mux2 sh_87_ ( .d1(areg[88]), .z(ain[87]), .d0(areg[87]), .s(x2));
mul_mux2 sh_86_ ( .d1(areg[87]), .z(ain[86]), .d0(areg[86]), .s(x2));
mul_mux2 sh_85_ ( .d1(areg[86]), .z(ain[85]), .d0(areg[85]), .s(x2));
mul_mux2 sh_84_ ( .d1(areg[85]), .z(ain[84]), .d0(areg[84]), .s(x2));
mul_mux2 sh_0_ ( .d1(areg[1]), .z(ain[0]), .d0(areg[0]), .s(x2));
mul_mux2 sh_81_ ( .d1(areg[82]), .z(ain[81]), .d0(areg[81]), .s(x2));
mul_mux2 sh_80_ ( .d1(areg[81]), .z(ain[80]), .d0(areg[80]), .s(x2));
mul_mux2 sh_79_ ( .d1(areg[80]), .z(ain[79]), .d0(areg[79]), .s(x2));
mul_mux2 sh_78_ ( .d1(areg[79]), .z(ain[78]), .d0(areg[78]), .s(x2));
mul_mux2 sh_77_ ( .d1(areg[78]), .z(ain[77]), .d0(areg[77]), .s(x2));
mul_mux2 sh_76_ ( .d1(areg[77]), .z(ain[76]), .d0(areg[76]), .s(x2));
mul_mux2 sh_75_ ( .d1(areg[76]), .z(ain[75]), .d0(areg[75]), .s(x2));
mul_mux2 sh_74_ ( .d1(areg[75]), .z(ain[74]), .d0(areg[74]), .s(x2));
mul_mux2 sh_73_ ( .d1(areg[74]), .z(ain[73]), .d0(areg[73]), .s(x2));
mul_mux2 sh_72_ ( .d1(areg[73]), .z(ain[72]), .d0(areg[72]), .s(x2));
mul_mux2 sh_71_ ( .d1(areg[72]), .z(ain[71]), .d0(areg[71]), .s(x2));
mul_mux2 sh_70_ ( .d1(areg[71]), .z(ain[70]), .d0(areg[70]), .s(x2));
mul_mux2 sh_69_ ( .d1(areg[70]), .z(ain[69]), .d0(areg[69]), .s(x2));
mul_mux2 sh_19_ ( .d1(areg[20]), .z(ain[19]), .d0(areg[19]), .s(x2));
mul_mux2 sh_18_ ( .d1(areg[19]), .z(ain[18]), .d0(areg[18]), .s(x2));
mul_mux2 sh_17_ ( .d1(areg[18]), .z(ain[17]), .d0(areg[17]), .s(x2));
mul_mux2 sh_16_ ( .d1(areg[17]), .z(ain[16]), .d0(areg[16]), .s(x2));
mul_mux2 sh_15_ ( .d1(areg[16]), .z(ain[15]), .d0(areg[15]), .s(x2));
mul_mux2 sh_4_ ( .d1(areg[5]), .z(ain[4]), .d0(areg[4]), .s(x2));
mul_mux2 sh_3_ ( .d1(areg[4]), .z(ain[3]), .d0(areg[3]), .s(x2));
mul_mux2 sh_2_ ( .d1(areg[3]), .z(ain[2]), .d0(areg[2]), .s(x2));
mul_mux2 sh_1_ ( .d1(areg[2]), .z(ain[1]), .d0(areg[1]), .s(x2));
mul_mux2 shx2 ( .d1(areg[0]), .z(ainx2), .d0(1'b0),
.s(x2));
mul_mux2 sh_83_ ( .d1(areg[84]), .z(ain[83]), .d0(areg[83]), .s(x2));
mul_mux2 sh_14_ ( .d1(areg[15]), .z(ain[14]), .d0(areg[14]), .s(x2));
mul_mux2 sh_13_ ( .d1(areg[14]), .z(ain[13]), .d0(areg[13]), .s(x2));
mul_mux2 sh_12_ ( .d1(areg[13]), .z(ain[12]), .d0(areg[12]), .s(x2));
mul_mux2 sh_11_ ( .d1(areg[12]), .z(ain[11]), .d0(areg[11]), .s(x2));
mul_mux2 sh_10_ ( .d1(areg[11]), .z(ain[10]), .d0(areg[10]), .s(x2));
mul_mux2 sh_9_ ( .d1(areg[10]), .z(ain[9]), .d0(areg[9]), .s(x2));
mul_mux2 sh_8_ ( .d1(areg[9]), .z(ain[8]), .d0(areg[8]), .s(x2));
mul_mux2 sh_7_ ( .d1(areg[8]), .z(ain[7]), .d0(areg[7]), .s(x2));
mul_mux2 sh_6_ ( .d1(areg[7]), .z(ain[6]), .d0(areg[6]), .s(x2));
mul_mux2 sh_5_ ( .d1(areg[6]), .z(ain[5]), .d0(areg[5]), .s(x2));
mul_csa42 sc3_68_ ( .cin(co[67]), .d(1'b0),
.carry(c3[68]), .c(c2[67]), .b(s2[68]), .a(1'b0),
.cout(), .sum(s3[68]));
mul_csa42 sc3_67_ ( .cin(co[66]), .d(1'b0),
.carry(c3[67]), .c(c2[66]), .b(s2[67]), .a(s1[67]), .cout(co[67]),
.sum(s3[67]));
mul_csa42 sc3_66_ ( .cin(co[65]), .d(c1[65]), .carry(c3[66]),
.c(c2[65]), .b(s2[66]), .a(s1[66]), .cout(co[66]), .sum(s3[66]));
mul_csa42 sc3_65_ ( .cin(co[64]), .d(c1[64]), .carry(c3[65]),
.c(c2[64]), .b(s2[65]), .a(s1[65]), .cout(co[65]), .sum(s3[65]));
mul_csa42 sc3_64_ ( .cin(co[63]), .d(c1[63]), .carry(c3[64]),
.c(c2[63]), .b(s2[64]), .a(s1[64]), .cout(co[64]), .sum(s3[64]));
mul_csa42 sc3_63_ ( .cin(co[62]), .d(c1[62]), .carry(c3[63]),
.c(c2[62]), .b(s2[63]), .a(s1[63]), .cout(co[63]), .sum(s3[63]));
mul_csa42 sc3_62_ ( .cin(co[61]), .d(c1[61]), .carry(c3[62]),
.c(c2[61]), .b(s2[62]), .a(s1[62]), .cout(co[62]), .sum(s3[62]));
mul_csa42 sc3_61_ ( .cin(co[60]), .d(c1[60]), .carry(c3[61]),
.c(c2[60]), .b(s2[61]), .a(s1[61]), .cout(co[61]), .sum(s3[61]));
mul_csa42 sc3_60_ ( .cin(co[59]), .d(c1[59]), .carry(c3[60]),
.c(c2[59]), .b(s2[60]), .a(s1[60]), .cout(co[60]), .sum(s3[60]));
mul_csa42 sc3_59_ ( .cin(co[58]), .d(c1[58]), .carry(c3[59]),
.c(c2[58]), .b(s2[59]), .a(s1[59]), .cout(co[59]), .sum(s3[59]));
mul_csa42 sc3_58_ ( .cin(co[57]), .d(c1[57]), .carry(c3[58]),
.c(c2[57]), .b(s2[58]), .a(s1[58]), .cout(co[58]), .sum(s3[58]));
mul_csa42 sc3_57_ ( .cin(co[56]), .d(c1[56]), .carry(c3[57]),
.c(c2[56]), .b(s2[57]), .a(s1[57]), .cout(co[57]), .sum(s3[57]));
mul_csa42 sc3_56_ ( .cin(co[55]), .d(c1[55]), .carry(c3[56]),
.c(c2[55]), .b(s2[56]), .a(s1[56]), .cout(co[56]), .sum(s3[56]));
mul_csa42 sc3_55_ ( .cin(co[54]), .d(c1[54]), .carry(c3[55]),
.c(c2[54]), .b(s2[55]), .a(s1[55]), .cout(co[55]), .sum(s3[55]));
mul_csa42 sc3_54_ ( .cin(co[53]), .d(c1[53]), .carry(c3[54]),
.c(c2[53]), .b(s2[54]), .a(s1[54]), .cout(co[54]), .sum(s3[54]));
mul_csa42 sc3_53_ ( .cin(co[52]), .d(c1[52]), .carry(c3[53]),
.c(c2[52]), .b(s2[53]), .a(s1[53]), .cout(co[53]), .sum(s3[53]));
mul_csa42 sc3_52_ ( .cin(co[51]), .d(c1[51]), .carry(c3[52]),
.c(c2[51]), .b(s2[52]), .a(s1[52]), .cout(co[52]), .sum(s3[52]));
mul_csa42 sc3_51_ ( .cin(co[50]), .d(c1[50]), .carry(c3[51]),
.c(c2[50]), .b(s2[51]), .a(s1[51]), .cout(co[51]), .sum(s3[51]));
mul_csa42 sc3_50_ ( .cin(co[49]), .d(c1[49]), .carry(c3[50]),
.c(c2[49]), .b(s2[50]), .a(s1[50]), .cout(co[50]), .sum(s3[50]));
mul_csa42 sc3_49_ ( .cin(co[48]), .d(c1[48]), .carry(c3[49]),
.c(c2[48]), .b(s2[49]), .a(s1[49]), .cout(co[49]), .sum(s3[49]));
mul_csa42 sc3_48_ ( .cin(co[47]), .d(c1[47]), .carry(c3[48]),
.c(c2[47]), .b(s2[48]), .a(s1[48]), .cout(co[48]), .sum(s3[48]));
mul_csa42 sc3_47_ ( .cin(co[46]), .d(c1[46]), .carry(c3[47]),
.c(c2[46]), .b(s2[47]), .a(s1[47]), .cout(co[47]), .sum(s3[47]));
mul_csa42 sc3_46_ ( .cin(co[45]), .d(c1[45]), .carry(c3[46]),
.c(c2[45]), .b(s2[46]), .a(s1[46]), .cout(co[46]), .sum(s3[46]));
mul_csa42 sc3_45_ ( .cin(co[44]), .d(c1[44]), .carry(c3[45]),
.c(c2[44]), .b(s2[45]), .a(s1[45]), .cout(co[45]), .sum(s3[45]));
mul_csa42 sc3_44_ ( .cin(co[43]), .d(c1[43]), .carry(c3[44]),
.c(c2[43]), .b(s2[44]), .a(s1[44]), .cout(co[44]), .sum(s3[44]));
mul_csa42 sc3_43_ ( .cin(co[42]), .d(c1[42]), .carry(c3[43]),
.c(c2[42]), .b(s2[43]), .a(s1[43]), .cout(co[43]), .sum(s3[43]));
mul_csa42 sc3_42_ ( .cin(co[41]), .d(c1[41]), .carry(c3[42]),
.c(c2[41]), .b(s2[42]), .a(s1[42]), .cout(co[42]), .sum(s3[42]));
mul_csa42 sc3_41_ ( .cin(co[40]), .d(c1[40]), .carry(c3[41]),
.c(c2[40]), .b(s2[41]), .a(s1[41]), .cout(co[41]), .sum(s3[41]));
mul_csa42 sc3_40_ ( .cin(co[39]), .d(c1[39]), .carry(c3[40]),
.c(c2[39]), .b(s2[40]), .a(s1[40]), .cout(co[40]), .sum(s3[40]));
mul_csa42 sc3_39_ ( .cin(co[38]), .d(c1[38]), .carry(c3[39]),
.c(c2[38]), .b(s2[39]), .a(s1[39]), .cout(co[39]), .sum(s3[39]));
mul_csa42 sc3_38_ ( .cin(co[37]), .d(c1[37]), .carry(c3[38]),
.c(c2[37]), .b(s2[38]), .a(s1[38]), .cout(co[38]), .sum(s3[38]));
mul_csa42 sc3_37_ ( .cin(co[36]), .d(c1[36]), .carry(c3[37]),
.c(c2[36]), .b(s2[37]), .a(s1[37]), .cout(co[37]), .sum(s3[37]));
mul_csa42 sc3_36_ ( .cin(co[35]), .d(c1[35]), .carry(c3[36]),
.c(c2[35]), .b(s2[36]), .a(s1[36]), .cout(co[36]), .sum(s3[36]));
mul_csa42 sc3_35_ ( .cin(co[34]), .d(c1[34]), .carry(c3[35]),
.c(c2[34]), .b(s2[35]), .a(s1[35]), .cout(co[35]), .sum(s3[35]));
mul_csa42 sc3_34_ ( .cin(co[33]), .d(c1[33]), .carry(c3[34]),
.c(c2[33]), .b(s2[34]), .a(s1[34]), .cout(co[34]), .sum(s3[34]));
mul_csa42 sc3_33_ ( .cin(co[32]), .d(c1[32]), .carry(c3[33]),
.c(c2[32]), .b(s2[33]), .a(s1[33]), .cout(co[33]), .sum(s3[33]));
mul_csa42 sc3_32_ ( .cin(co[31]), .d(c1[31]), .carry(c3[32]),
.c(c2[31]), .b(s2[32]), .a(s1[32]), .cout(co[32]), .sum(s3[32]));
mul_csa42 sc3_31_ ( .cin(co[30]), .d(c1[30]), .carry(c3[31]),
.c(c2[30]), .b(s2[31]), .a(s1[31]), .cout(co[31]), .sum(s3[31]));
mul_csa42 sc3_30_ ( .cin(co[29]), .d(c1[29]), .carry(c3[30]),
.c(c2[29]), .b(s2[30]), .a(s1[30]), .cout(co[30]), .sum(s3[30]));
mul_csa42 sc3_29_ ( .cin(co[28]), .d(c1[28]), .carry(c3[29]),
.c(c2[28]), .b(s2[29]), .a(s1[29]), .cout(co[29]), .sum(s3[29]));
mul_csa42 sc3_28_ ( .cin(co[27]), .d(c1[27]), .carry(c3[28]),
.c(c2[27]), .b(s2[28]), .a(s1[28]), .cout(co[28]), .sum(s3[28]));
mul_csa42 sc3_27_ ( .cin(co[26]), .d(c1[26]), .carry(c3[27]),
.c(c2[26]), .b(s2[27]), .a(s1[27]), .cout(co[27]), .sum(s3[27]));
mul_csa42 sc3_26_ ( .cin(co[25]), .d(c1[25]), .carry(c3[26]),
.c(c2[25]), .b(s2[26]), .a(s1[26]), .cout(co[26]), .sum(s3[26]));
mul_csa42 sc3_25_ ( .cin(co[24]), .d(c1[24]), .carry(c3[25]),
.c(c2[24]), .b(s2[25]), .a(s1[25]), .cout(co[25]), .sum(s3[25]));
mul_csa42 sc3_24_ ( .cin(co[23]), .d(c1[23]), .carry(c3[24]),
.c(c2[23]), .b(s2[24]), .a(s1[24]), .cout(co[24]), .sum(s3[24]));
mul_csa42 sc3_23_ ( .cin(co[22]), .d(c1[22]), .carry(c3[23]),
.c(c2[22]), .b(s2[23]), .a(s1[23]), .cout(co[23]), .sum(s3[23]));
mul_csa42 sc3_22_ ( .cin(co[21]), .d(c1[21]), .carry(c3[22]),
.c(c2[21]), .b(s2[22]), .a(s1[22]), .cout(co[22]), .sum(s3[22]));
mul_csa42 sc3_21_ ( .cin(co[20]), .d(c1[20]), .carry(c3[21]),
.c(c2[20]), .b(s2[21]), .a(s1[21]), .cout(co[21]), .sum(s3[21]));
mul_csa42 sc3_20_ ( .cin(1'b0), .d(c1[19]),
.carry(c3[20]), .c(c2[19]), .b(s2[20]), .a(s1[20]), .cout(co[20]),
.sum(s3[20]));
mul_csa32 sc4_82_ ( .c(c3[81]), .b(s2[82]), .a(ain[82]),
.cout(pcout[82]), .sum(psum[82]));
mul_csa32 sc4_68_ ( .c(c3[67]), .b(s3[68]), .a(ain[68]),
.cout(pcout[68]), .sum(psum[68]));
mul_csa32 sc4_67_ ( .c(c3[66]), .b(s3[67]), .a(ain[67]),
.cout(pcout[67]), .sum(psum[67]));
mul_csa32 sc4_66_ ( .c(c3[65]), .b(s3[66]), .a(ain[66]),
.cout(pcout[66]), .sum(psum[66]));
mul_csa32 sc4_65_ ( .c(c3[64]), .b(s3[65]), .a(ain[65]),
.cout(pcout[65]), .sum(psum[65]));
mul_csa32 sc4_64_ ( .c(c3[63]), .b(s3[64]), .a(ain[64]),
.cout(pcout[64]), .sum(psum[64]));
mul_csa32 sc4_63_ ( .c(c3[62]), .b(s3[63]), .a(ain[63]),
.cout(pcout[63]), .sum(psum[63]));
mul_csa32 sc4_62_ ( .c(c3[61]), .b(s3[62]), .a(ain[62]),
.cout(pcout[62]), .sum(psum[62]));
mul_csa32 sc4_61_ ( .c(c3[60]), .b(s3[61]), .a(ain[61]),
.cout(pcout[61]), .sum(psum[61]));
mul_csa32 sc4_60_ ( .c(c3[59]), .b(s3[60]), .a(ain[60]),
.cout(pcout[60]), .sum(psum[60]));
mul_csa32 sc4_59_ ( .c(c3[58]), .b(s3[59]), .a(ain[59]),
.cout(pcout[59]), .sum(psum[59]));
mul_csa32 sc4_58_ ( .c(c3[57]), .b(s3[58]), .a(ain[58]),
.cout(pcout[58]), .sum(psum[58]));
mul_csa32 sc4_57_ ( .c(c3[56]), .b(s3[57]), .a(ain[57]),
.cout(pcout[57]), .sum(psum[57]));
mul_csa32 sc4_56_ ( .c(c3[55]), .b(s3[56]), .a(ain[56]),
.cout(pcout[56]), .sum(psum[56]));
mul_csa32 sc4_55_ ( .c(c3[54]), .b(s3[55]), .a(ain[55]),
.cout(pcout[55]), .sum(psum[55]));
mul_csa32 sc4_54_ ( .c(c3[53]), .b(s3[54]), .a(ain[54]),
.cout(pcout[54]), .sum(psum[54]));
mul_csa32 sc4_53_ ( .c(c3[52]), .b(s3[53]), .a(ain[53]),
.cout(pcout[53]), .sum(psum[53]));
mul_csa32 sc4_52_ ( .c(c3[51]), .b(s3[52]), .a(ain[52]),
.cout(pcout[52]), .sum(psum[52]));
mul_csa32 sc4_51_ ( .c(c3[50]), .b(s3[51]), .a(ain[51]),
.cout(pcout[51]), .sum(psum[51]));
mul_csa32 sc4_50_ ( .c(c3[49]), .b(s3[50]), .a(ain[50]),
.cout(pcout[50]), .sum(psum[50]));
mul_csa32 sc4_49_ ( .c(c3[48]), .b(s3[49]), .a(ain[49]),
.cout(pcout[49]), .sum(psum[49]));
mul_csa32 sc4_48_ ( .c(c3[47]), .b(s3[48]), .a(ain[48]),
.cout(pcout[48]), .sum(psum[48]));
mul_csa32 sc4_47_ ( .c(c3[46]), .b(s3[47]), .a(ain[47]),
.cout(pcout[47]), .sum(psum[47]));
mul_csa32 sc4_46_ ( .c(c3[45]), .b(s3[46]), .a(ain[46]),
.cout(pcout[46]), .sum(psum[46]));
mul_csa32 sc4_45_ ( .c(c3[44]), .b(s3[45]), .a(ain[45]),
.cout(pcout[45]), .sum(psum[45]));
mul_csa32 sc4_44_ ( .c(c3[43]), .b(s3[44]), .a(ain[44]),
.cout(pcout[44]), .sum(psum[44]));
mul_csa32 sc4_43_ ( .c(c3[42]), .b(s3[43]), .a(ain[43]),
.cout(pcout[43]), .sum(psum[43]));
mul_csa32 sc4_42_ ( .c(c3[41]), .b(s3[42]), .a(ain[42]),
.cout(pcout[42]), .sum(psum[42]));
mul_csa32 sc4_41_ ( .c(c3[40]), .b(s3[41]), .a(ain[41]),
.cout(pcout[41]), .sum(psum[41]));
mul_csa32 sc4_40_ ( .c(c3[39]), .b(s3[40]), .a(ain[40]),
.cout(pcout[40]), .sum(psum[40]));
mul_csa32 sc4_39_ ( .c(c3[38]), .b(s3[39]), .a(ain[39]),
.cout(pcout[39]), .sum(psum[39]));
mul_csa32 sc4_38_ ( .c(c3[37]), .b(s3[38]), .a(ain[38]),
.cout(pcout[38]), .sum(psum[38]));
mul_csa32 sc4_37_ ( .c(c3[36]), .b(s3[37]), .a(ain[37]),
.cout(pcout[37]), .sum(psum[37]));
mul_csa32 sc4_36_ ( .c(c3[35]), .b(s3[36]), .a(ain[36]),
.cout(pcout[36]), .sum(psum[36]));
mul_csa32 sc4_35_ ( .c(c3[34]), .b(s3[35]), .a(ain[35]),
.cout(pcout[35]), .sum(psum[35]));
mul_csa32 sc4_34_ ( .c(c3[33]), .b(s3[34]), .a(ain[34]),
.cout(pcout[34]), .sum(psum[34]));
mul_csa32 sc4_33_ ( .c(c3[32]), .b(s3[33]), .a(ain[33]),
.cout(pcout[33]), .sum(psum[33]));
mul_csa32 sc4_32_ ( .c(c3[31]), .b(s3[32]), .a(ain[32]),
.cout(pcout[32]), .sum(psum[32]));
mul_csa32 sc4_31_ ( .c(c3[30]), .b(s3[31]), .a(ain[31]),
.cout(pcout[31]), .sum(psum[31]));
mul_csa32 sc4_30_ ( .c(c3[29]), .b(s3[30]), .a(ain[30]),
.cout(pcout[30]), .sum(psum[30]));
mul_csa32 sc4_29_ ( .c(c3[28]), .b(s3[29]), .a(ain[29]),
.cout(pcout[29]), .sum(psum[29]));
mul_csa32 sc4_28_ ( .c(c3[27]), .b(s3[28]), .a(ain[28]),
.cout(pcout[28]), .sum(psum[28]));
mul_csa32 sc4_27_ ( .c(c3[26]), .b(s3[27]), .a(ain[27]),
.cout(pcout[27]), .sum(psum[27]));
mul_csa32 sc4_26_ ( .c(c3[25]), .b(s3[26]), .a(ain[26]),
.cout(pcout[26]), .sum(psum[26]));
mul_csa32 sc4_25_ ( .c(c3[24]), .b(s3[25]), .a(ain[25]),
.cout(pcout[25]), .sum(psum[25]));
mul_csa32 sc4_24_ ( .c(c3[23]), .b(s3[24]), .a(ain[24]),
.cout(pcout[24]), .sum(psum[24]));
mul_csa32 sc4_23_ ( .c(c3[22]), .b(s3[23]), .a(ain[23]),
.cout(pcout[23]), .sum(psum[23]));
mul_csa32 sc4_22_ ( .c(c3[21]), .b(s3[22]), .a(ain[22]),
.cout(pcout[22]), .sum(psum[22]));
mul_csa32 sc4_21_ ( .c(c3[20]), .b(s3[21]), .a(ain[21]),
.cout(pcout[21]), .sum(psum[21]));
mul_csa32 sc4_20_ ( .c(c3[19]), .b(s3[20]), .a(ain[20]),
.cout(pcout[20]), .sum(psum[20]));
mul_csa32 sc4_96_ ( .c(c2[95]), .b(s2[96]), .a(ain[96]),
.cout(pcout[96]), .sum(psum[96]));
mul_csa32 sc4_95_ ( .c(c2[94]), .b(s2[95]), .a(ain[95]),
.cout(pcout[95]), .sum(psum[95]));
mul_csa32 sc4_94_ ( .c(c2[93]), .b(s2[94]), .a(ain[94]),
.cout(pcout[94]), .sum(psum[94]));
mul_csa32 sc4_93_ ( .c(c2[92]), .b(s2[93]), .a(ain[93]),
.cout(pcout[93]), .sum(psum[93]));
mul_csa32 sc4_92_ ( .c(c2[91]), .b(s2[92]), .a(ain[92]),
.cout(pcout[92]), .sum(psum[92]));
mul_csa32 sc4_91_ ( .c(c2[90]), .b(s2[91]), .a(ain[91]),
.cout(pcout[91]), .sum(psum[91]));
mul_csa32 sc4_90_ ( .c(c2[89]), .b(s2[90]), .a(ain[90]),
.cout(pcout[90]), .sum(psum[90]));
mul_csa32 sc4_89_ ( .c(c2[88]), .b(s2[89]), .a(ain[89]),
.cout(pcout[89]), .sum(psum[89]));
mul_csa32 sc4_88_ ( .c(c2[87]), .b(s2[88]), .a(ain[88]),
.cout(pcout[88]), .sum(psum[88]));
mul_csa32 sc4_87_ ( .c(c2[86]), .b(s2[87]), .a(ain[87]),
.cout(pcout[87]), .sum(psum[87]));
mul_csa32 sc4_86_ ( .c(c2[85]), .b(s2[86]), .a(ain[86]),
.cout(pcout[86]), .sum(psum[86]));
mul_csa32 sc4_85_ ( .c(c2[84]), .b(s2[85]), .a(ain[85]),
.cout(pcout[85]), .sum(psum[85]));
mul_csa32 sc4_84_ ( .c(c2[83]), .b(s2[84]), .a(ain[84]),
.cout(pcout[84]), .sum(psum[84]));
mul_csa32 sc4_81_ ( .c(c3[80]), .b(s3[81]), .a(ain[81]),
.cout(pcout[81]), .sum(psum[81]));
mul_csa32 sc4_80_ ( .c(c3[79]), .b(s3[80]), .a(ain[80]),
.cout(pcout[80]), .sum(psum[80]));
mul_csa32 sc4_79_ ( .c(c3[78]), .b(s3[79]), .a(ain[79]),
.cout(pcout[79]), .sum(psum[79]));
mul_csa32 sc4_78_ ( .c(c3[77]), .b(s3[78]), .a(ain[78]),
.cout(pcout[78]), .sum(psum[78]));
mul_csa32 sc4_77_ ( .c(c3[76]), .b(s3[77]), .a(ain[77]),
.cout(pcout[77]), .sum(psum[77]));
mul_csa32 sc4_76_ ( .c(c3[75]), .b(s3[76]), .a(ain[76]),
.cout(pcout[76]), .sum(psum[76]));
mul_csa32 sc4_75_ ( .c(c3[74]), .b(s3[75]), .a(ain[75]),
.cout(pcout[75]), .sum(psum[75]));
mul_csa32 sc4_74_ ( .c(c3[73]), .b(s3[74]), .a(ain[74]),
.cout(pcout[74]), .sum(psum[74]));
mul_csa32 sc4_73_ ( .c(c3[72]), .b(s3[73]), .a(ain[73]),
.cout(pcout[73]), .sum(psum[73]));
mul_csa32 sc4_72_ ( .c(c3[71]), .b(s3[72]), .a(ain[72]),
.cout(pcout[72]), .sum(psum[72]));
mul_csa32 sc4_71_ ( .c(c3[70]), .b(s3[71]), .a(ain[71]),
.cout(pcout[71]), .sum(psum[71]));
mul_csa32 sc4_70_ ( .c(c3[69]), .b(s3[70]), .a(ain[70]),
.cout(pcout[70]), .sum(psum[70]));
mul_csa32 sc4_69_ ( .c(c3[68]), .b(s3[69]), .a(ain[69]),
.cout(pcout[69]), .sum(psum[69]));
mul_csa32 acc_4_ ( .c(c2[3]), .sum(psum[4]), .cout(pcout[4]),
.a(ain[4]), .b(s2[4]));
mul_csa32 acc_3_ ( .c(c2[2]), .sum(psum[3]), .cout(pcout[3]),
.a(ain[3]), .b(s2[3]));
mul_csa32 acc_2_ ( .c(c2[1]), .sum(psum[2]), .cout(pcout[2]),
.a(ain[2]), .b(s2[2]));
mul_csa32 acc_1_ ( .c(c2[0]), .sum(psum[1]), .cout(pcout[1]),
.a(ain[1]), .b(s2[1]));
mul_csa32 sc3_97_ ( .c(c2[96]), .sum(psum[97]), .cout(pcout[97]),
.a(a1s[81]), .b(a1c[80]));
mul_csa32 sc1_19_ ( .c(a1s[3]), .b(pc[50]), .a(ps[51]),
.cout(c1[19]), .sum(s1[19]));
mul_csa32 sc1_18_ ( .c(a1s[2]), .b(pc[49]), .a(ps[50]),
.cout(c1[18]), .sum(s1[18]));
mul_csa32 sc1_17_ ( .c(a1s[1]), .b(pc[48]), .a(ps[49]),
.cout(c1[17]), .sum(s1[17]));
mul_csa32 sc1_16_ ( .c(a1s[0]), .b(pc[47]), .a(ps[48]),
.cout(c1[16]), .sum(s1[16]));
mul_csa32 sc1_15_ ( .c(1'b0), .b(pc[46]), .a(ps[47]),
.cout(c1[15]), .sum(s1[15]));
mul_csa32 sc4_83_ ( .c(c2[82]), .b(s2[83]), .a(ain[83]),
.cout(pcout[83]), .sum(psum[83]));
mul_csa32 sc2_83_ ( .c(c1[82]), .b(a1c[66]), .a(a1s[67]),
.cout(c2[83]), .sum(s2[83]));
mul_csa32 sc2_19_ ( .c(a0c[18]), .b(a0s[19]), .a(s1[19]),
.cout(c2[19]), .sum(s2[19]));
mul_csa32 sc2_18_ ( .c(a0c[17]), .b(a0s[18]), .a(s1[18]),
.cout(c2[18]), .sum(s2[18]));
mul_csa32 sc2_17_ ( .c(a0c[16]), .b(a0s[17]), .a(s1[17]),
.cout(c2[17]), .sum(s2[17]));
mul_csa32 sc2_16_ ( .c(a0c[15]), .b(a0s[16]), .a(s1[16]),
.cout(c2[16]), .sum(s2[16]));
mul_csa32 sc2_15_ ( .c(a0c[14]), .b(a0s[15]), .a(s1[15]),
.cout(c2[15]), .sum(s2[15]));
mul_csa32 sc1_81_ ( .c(a0s[81]), .b(a1c[64]), .a(a1s[65]),
.cout(c1[81]), .sum(s1[81]));
mul_csa32 sc1_80_ ( .c(a0s[80]), .b(a1c[63]), .a(a1s[64]),
.cout(c1[80]), .sum(s1[80]));
mul_csa32 sc1_79_ ( .c(a0s[79]), .b(a1c[62]), .a(a1s[63]),
.cout(c1[79]), .sum(s1[79]));
mul_csa32 sc1_78_ ( .c(a0s[78]), .b(a1c[61]), .a(a1s[62]),
.cout(c1[78]), .sum(s1[78]));
mul_csa32 sc1_77_ ( .c(a0s[77]), .b(a1c[60]), .a(a1s[61]),
.cout(c1[77]), .sum(s1[77]));
mul_csa32 sc1_76_ ( .c(a0s[76]), .b(a1c[59]), .a(a1s[60]),
.cout(c1[76]), .sum(s1[76]));
mul_csa32 sc1_75_ ( .c(a0s[75]), .b(a1c[58]), .a(a1s[59]),
.cout(c1[75]), .sum(s1[75]));
mul_csa32 sc1_74_ ( .c(a0s[74]), .b(a1c[57]), .a(a1s[58]),
.cout(c1[74]), .sum(s1[74]));
mul_csa32 sc1_73_ ( .c(a0s[73]), .b(a1c[56]), .a(a1s[57]),
.cout(c1[73]), .sum(s1[73]));
mul_csa32 sc1_72_ ( .c(a0s[72]), .b(a1c[55]), .a(a1s[56]),
.cout(c1[72]), .sum(s1[72]));
mul_csa32 sc1_71_ ( .c(a0s[71]), .b(a1c[54]), .a(a1s[55]),
.cout(c1[71]), .sum(s1[71]));
mul_csa32 sc1_70_ ( .c(a0s[70]), .b(a1c[53]), .a(a1s[54]),
.cout(c1[70]), .sum(s1[70]));
mul_csa32 sc1_69_ ( .c(a0s[69]), .b(a1c[52]), .a(a1s[53]),
.cout(c1[69]), .sum(s1[69]));
mul_csa32 sc1_68_ ( .c(a0s[68]), .b(a1c[51]), .a(a1s[52]),
.cout(c1[68]), .sum(s1[68]));
mul_csa32 sc3_19_ ( .c(c2[18]), .b(c1[18]), .a(s2[19]),
.cout(c3[19]), .sum(s3[19]));
mul_csa32 sc3_18_ ( .c(c2[17]), .b(c1[17]), .a(s2[18]),
.cout(c3[18]), .sum(s3[18]));
mul_csa32 sc3_17_ ( .c(c2[16]), .b(c1[16]), .a(s2[17]),
.cout(c3[17]), .sum(s3[17]));
mul_csa32 sc3_16_ ( .c(c2[15]), .b(c1[15]), .a(s2[16]),
.cout(c3[16]), .sum(s3[16]));
mul_csa32 sc3_15_ ( .c(c2[14]), .b(c1[14]), .a(s2[15]),
.cout(c3[15]), .sum(s3[15]));
mul_csa32 sc1_82_ ( .c(a0c[81]), .b(a1c[65]), .a(a1s[66]),
.cout(c1[82]), .sum(s1[82]));
mul_csa32 acc_14_ ( .c(c2[13]), .sum(psum[14]), .cout(pcout[14]),
.a(ain[14]), .b(s2[14]));
mul_csa32 acc_13_ ( .c(c2[12]), .sum(psum[13]), .cout(pcout[13]),
.a(ain[13]), .b(s2[13]));
mul_csa32 acc_12_ ( .c(c2[11]), .sum(psum[12]), .cout(pcout[12]),
.a(ain[12]), .b(s2[12]));
mul_csa32 acc_11_ ( .c(c2[10]), .sum(psum[11]), .cout(pcout[11]),
.a(ain[11]), .b(s2[11]));
mul_csa32 acc_10_ ( .c(c2[9]), .sum(psum[10]), .cout(pcout[10]),
.a(ain[10]), .b(s2[10]));
mul_csa32 acc_9_ ( .c(c2[8]), .sum(psum[9]), .cout(pcout[9]),
.a(ain[9]), .b(s2[9]));
mul_csa32 acc_8_ ( .c(c2[7]), .sum(psum[8]), .cout(pcout[8]),
.a(ain[8]), .b(s2[8]));
mul_csa32 acc_7_ ( .c(c2[6]), .sum(psum[7]), .cout(pcout[7]),
.a(ain[7]), .b(s2[7]));
mul_csa32 acc_6_ ( .c(c2[5]), .sum(psum[6]), .cout(pcout[6]),
.a(ain[6]), .b(s2[6]));
mul_csa32 acc_5_ ( .c(c2[4]), .sum(psum[5]), .cout(pcout[5]),
.a(ain[5]), .b(s2[5]));
mul_csa32 sc2_67_ ( .c(a0c[66]), .b(c1[66]), .a(a0s[67]),
.cout(c2[67]), .sum(s2[67]));
mul_csa32 sc1_14_ ( .c(a0s[14]), .b(pc[45]), .a(ps[46]),
.cout(c1[14]), .sum(s1[14]));
mul_csa32 sc1_13_ ( .c(a0s[13]), .b(pc[44]), .a(ps[45]),
.cout(c1[13]), .sum(s1[13]));
mul_csa32 sc1_12_ ( .c(a0s[12]), .b(pc[43]), .a(ps[44]),
.cout(c1[12]), .sum(s1[12]));
mul_csa32 sc1_11_ ( .c(a0s[11]), .b(pc[42]), .a(ps[43]),
.cout(c1[11]), .sum(s1[11]));
mul_csa32 sc1_10_ ( .c(a0s[10]), .b(pc[41]), .a(ps[42]),
.cout(c1[10]), .sum(s1[10]));
mul_csa32 sc1_9_ ( .c(a0s[9]), .b(pc[40]), .a(ps[41]), .cout(c1[9]),
.sum(s1[9]));
mul_csa32 sc1_8_ ( .c(a0s[8]), .b(pc[39]), .a(ps[40]), .cout(c1[8]),
.sum(s1[8]));
mul_csa32 sc1_7_ ( .c(a0s[7]), .b(pc[38]), .a(ps[39]), .cout(c1[7]),
.sum(s1[7]));
mul_csa32 sc1_6_ ( .c(a0s[6]), .b(pc[37]), .a(ps[38]), .cout(c1[6]),
.sum(s1[6]));
mul_csa32 sc1_5_ ( .c(a0s[5]), .b(pc[36]), .a(ps[37]), .cout(c1[5]),
.sum(s1[5]));
mul_csa32 sc2_14_ ( .c(a0c[13]), .b(c1[13]), .a(s1[14]),
.cout(c2[14]), .sum(s2[14]));
mul_csa32 sc2_13_ ( .c(a0c[12]), .b(c1[12]), .a(s1[13]),
.cout(c2[13]), .sum(s2[13]));
mul_csa32 sc2_12_ ( .c(a0c[11]), .b(c1[11]), .a(s1[12]),
.cout(c2[12]), .sum(s2[12]));
mul_csa32 sc2_11_ ( .c(a0c[10]), .b(c1[10]), .a(s1[11]),
.cout(c2[11]), .sum(s2[11]));
mul_csa32 sc2_10_ ( .c(a0c[9]), .b(c1[9]), .a(s1[10]),
.cout(c2[10]), .sum(s2[10]));
mul_csa32 sc2_9_ ( .c(a0c[8]), .b(c1[8]), .a(s1[9]), .cout(c2[9]),
.sum(s2[9]));
mul_csa32 sc2_8_ ( .c(a0c[7]), .b(c1[7]), .a(s1[8]), .cout(c2[8]),
.sum(s2[8]));
mul_csa32 sc2_7_ ( .c(a0c[6]), .b(c1[6]), .a(s1[7]), .cout(c2[7]),
.sum(s2[7]));
mul_csa32 sc2_6_ ( .c(a0c[5]), .b(c1[5]), .a(s1[6]), .cout(c2[6]),
.sum(s2[6]));
mul_csa32 sc2_5_ ( .c(a0c[4]), .b(c1[4]), .a(s1[5]), .cout(c2[5]),
.sum(s2[5]));
mul_csa32 sc2_82_ ( .c(c2[81]), .b(c1[81]), .a(s1[82]),
.cout(c2[82]), .sum(s2[82]));
mul_csa32 sc1_4_ ( .c(a0s[4]), .b(pc[35]), .a(ps[36]), .cout(c1[4]),
.sum(s1[4]));
mul_csa32 sc1_3_ ( .c(a0s[3]), .b(pc[34]), .a(ps[35]), .cout(c1[3]),
.sum(s1[3]));
mul_csa32 sc1_2_ ( .c(a0s[2]), .b(pc[33]), .a(ps[34]), .cout(c1[2]),
.sum(s1[2]));
mul_csa32 sc1_1_ ( .c(a0s[1]), .b(pc[32]), .a(ps[33]), .cout(c1[1]),
.sum(s1[1]));
mul_csa32 sc2_66_ ( .c(a0c[65]), .b(a0s[66]), .a(a1c[49]),
.cout(c2[66]), .sum(s2[66]));
mul_csa32 sc2_65_ ( .c(a0c[64]), .b(a0s[65]), .a(a1c[48]),
.cout(c2[65]), .sum(s2[65]));
mul_csa32 sc2_64_ ( .c(a0c[63]), .b(a0s[64]), .a(a1c[47]),
.cout(c2[64]), .sum(s2[64]));
mul_csa32 sc2_63_ ( .c(a0c[62]), .b(a0s[63]), .a(a1c[46]),
.cout(c2[63]), .sum(s2[63]));
mul_csa32 sc2_62_ ( .c(a0c[61]), .b(a0s[62]), .a(a1c[45]),
.cout(c2[62]), .sum(s2[62]));
mul_csa32 sc2_61_ ( .c(a0c[60]), .b(a0s[61]), .a(a1c[44]),
.cout(c2[61]), .sum(s2[61]));
mul_csa32 sc2_60_ ( .c(a0c[59]), .b(a0s[60]), .a(a1c[43]),
.cout(c2[60]), .sum(s2[60]));
mul_csa32 sc2_59_ ( .c(a0c[58]), .b(a0s[59]), .a(a1c[42]),
.cout(c2[59]), .sum(s2[59]));
mul_csa32 sc2_58_ ( .c(a0c[57]), .b(a0s[58]), .a(a1c[41]),
.cout(c2[58]), .sum(s2[58]));
mul_csa32 sc2_57_ ( .c(a0c[56]), .b(a0s[57]), .a(a1c[40]),
.cout(c2[57]), .sum(s2[57]));
mul_csa32 sc2_56_ ( .c(a0c[55]), .b(a0s[56]), .a(a1c[39]),
.cout(c2[56]), .sum(s2[56]));
mul_csa32 sc2_55_ ( .c(a0c[54]), .b(a0s[55]), .a(a1c[38]),
.cout(c2[55]), .sum(s2[55]));
mul_csa32 sc2_54_ ( .c(a0c[53]), .b(a0s[54]), .a(a1c[37]),
.cout(c2[54]), .sum(s2[54]));
mul_csa32 sc2_53_ ( .c(a0c[52]), .b(a0s[53]), .a(a1c[36]),
.cout(c2[53]), .sum(s2[53]));
mul_csa32 sc2_52_ ( .c(a0c[51]), .b(a0s[52]), .a(a1c[35]),
.cout(c2[52]), .sum(s2[52]));
mul_csa32 sc2_51_ ( .c(a0c[50]), .b(a0s[51]), .a(a1c[34]),
.cout(c2[51]), .sum(s2[51]));
mul_csa32 sc2_50_ ( .c(a0c[49]), .b(a0s[50]), .a(a1c[33]),
.cout(c2[50]), .sum(s2[50]));
mul_csa32 sc2_49_ ( .c(a0c[48]), .b(a0s[49]), .a(a1c[32]),
.cout(c2[49]), .sum(s2[49]));
mul_csa32 sc2_48_ ( .c(a0c[47]), .b(a0s[48]), .a(a1c[31]),
.cout(c2[48]), .sum(s2[48]));
mul_csa32 sc2_47_ ( .c(a0c[46]), .b(a0s[47]), .a(a1c[30]),
.cout(c2[47]), .sum(s2[47]));
mul_csa32 sc2_46_ ( .c(a0c[45]), .b(a0s[46]), .a(a1c[29]),
.cout(c2[46]), .sum(s2[46]));
mul_csa32 sc2_45_ ( .c(a0c[44]), .b(a0s[45]), .a(a1c[28]),
.cout(c2[45]), .sum(s2[45]));
mul_csa32 sc2_44_ ( .c(a0c[43]), .b(a0s[44]), .a(a1c[27]),
.cout(c2[44]), .sum(s2[44]));
mul_csa32 sc2_43_ ( .c(a0c[42]), .b(a0s[43]), .a(a1c[26]),
.cout(c2[43]), .sum(s2[43]));
mul_csa32 sc2_42_ ( .c(a0c[41]), .b(a0s[42]), .a(a1c[25]),
.cout(c2[42]), .sum(s2[42]));
mul_csa32 sc2_41_ ( .c(a0c[40]), .b(a0s[41]), .a(a1c[24]),
.cout(c2[41]), .sum(s2[41]));
mul_csa32 sc2_40_ ( .c(a0c[39]), .b(a0s[40]), .a(a1c[23]),
.cout(c2[40]), .sum(s2[40]));
mul_csa32 sc2_39_ ( .c(a0c[38]), .b(a0s[39]), .a(a1c[22]),
.cout(c2[39]), .sum(s2[39]));
mul_csa32 sc2_38_ ( .c(a0c[37]), .b(a0s[38]), .a(a1c[21]),
.cout(c2[38]), .sum(s2[38]));
mul_csa32 sc2_37_ ( .c(a0c[36]), .b(a0s[37]), .a(a1c[20]),
.cout(c2[37]), .sum(s2[37]));
mul_csa32 sc2_36_ ( .c(a0c[35]), .b(a0s[36]), .a(a1c[19]),
.cout(c2[36]), .sum(s2[36]));
mul_csa32 sc2_35_ ( .c(a0c[34]), .b(a0s[35]), .a(a1c[18]),
.cout(c2[35]), .sum(s2[35]));
mul_csa32 sc2_34_ ( .c(a0c[33]), .b(a0s[34]), .a(a1c[17]),
.cout(c2[34]), .sum(s2[34]));
mul_csa32 sc2_33_ ( .c(a0c[32]), .b(a0s[33]), .a(a1c[16]),
.cout(c2[33]), .sum(s2[33]));
mul_csa32 sc2_32_ ( .c(a0c[31]), .b(a0s[32]), .a(a1c[15]),
.cout(c2[32]), .sum(s2[32]));
mul_csa32 sc2_31_ ( .c(a0c[30]), .b(a0s[31]), .a(a1c[14]),
.cout(c2[31]), .sum(s2[31]));
mul_csa32 sc2_30_ ( .c(a0c[29]), .b(a0s[30]), .a(a1c[13]),
.cout(c2[30]), .sum(s2[30]));
mul_csa32 sc2_29_ ( .c(a0c[28]), .b(a0s[29]), .a(a1c[12]),
.cout(c2[29]), .sum(s2[29]));
mul_csa32 sc2_28_ ( .c(a0c[27]), .b(a0s[28]), .a(a1c[11]),
.cout(c2[28]), .sum(s2[28]));
mul_csa32 sc2_27_ ( .c(a0c[26]), .b(a0s[27]), .a(a1c[10]),
.cout(c2[27]), .sum(s2[27]));
mul_csa32 sc2_26_ ( .c(a0c[25]), .b(a0s[26]), .a(a1c[9]),
.cout(c2[26]), .sum(s2[26]));
mul_csa32 sc2_25_ ( .c(a0c[24]), .b(a0s[25]), .a(a1c[8]),
.cout(c2[25]), .sum(s2[25]));
mul_csa32 sc2_24_ ( .c(a0c[23]), .b(a0s[24]), .a(a1c[7]),
.cout(c2[24]), .sum(s2[24]));
mul_csa32 sc2_23_ ( .c(a0c[22]), .b(a0s[23]), .a(a1c[6]),
.cout(c2[23]), .sum(s2[23]));
mul_csa32 sc2_22_ ( .c(a0c[21]), .b(a0s[22]), .a(a1c[5]),
.cout(c2[22]), .sum(s2[22]));
mul_csa32 sc2_21_ ( .c(a0c[20]), .b(a0s[21]), .a(a1c[4]),
.cout(c2[21]), .sum(s2[21]));
mul_csa32 sc2_20_ ( .c(a0c[19]), .b(a0s[20]), .a(1'b0),
.cout(c2[20]), .sum(s2[20]));
mul_csa32 sc1_66_ ( .c(a1s[50]), .b(pc[97]), .a(ps[98]),
.cout(c1[66]), .sum(s1[66]));
mul_csa32 sc1_65_ ( .c(a1s[49]), .b(pc[96]), .a(ps[97]),
.cout(c1[65]), .sum(s1[65]));
mul_csa32 sc1_64_ ( .c(a1s[48]), .b(pc[95]), .a(ps[96]),
.cout(c1[64]), .sum(s1[64]));
mul_csa32 sc1_63_ ( .c(a1s[47]), .b(pc[94]), .a(ps[95]),
.cout(c1[63]), .sum(s1[63]));
mul_csa32 sc1_62_ ( .c(a1s[46]), .b(pc[93]), .a(ps[94]),
.cout(c1[62]), .sum(s1[62]));
mul_csa32 sc1_61_ ( .c(a1s[45]), .b(pc[92]), .a(ps[93]),
.cout(c1[61]), .sum(s1[61]));
mul_csa32 sc1_60_ ( .c(a1s[44]), .b(pc[91]), .a(ps[92]),
.cout(c1[60]), .sum(s1[60]));
mul_csa32 sc1_59_ ( .c(a1s[43]), .b(pc[90]), .a(ps[91]),
.cout(c1[59]), .sum(s1[59]));
mul_csa32 sc1_58_ ( .c(a1s[42]), .b(pc[89]), .a(ps[90]),
.cout(c1[58]), .sum(s1[58]));
mul_csa32 sc1_57_ ( .c(a1s[41]), .b(pc[88]), .a(ps[89]),
.cout(c1[57]), .sum(s1[57]));
mul_csa32 sc1_56_ ( .c(a1s[40]), .b(pc[87]), .a(ps[88]),
.cout(c1[56]), .sum(s1[56]));
mul_csa32 sc1_55_ ( .c(a1s[39]), .b(pc[86]), .a(ps[87]),
.cout(c1[55]), .sum(s1[55]));
mul_csa32 sc1_54_ ( .c(a1s[38]), .b(pc[85]), .a(ps[86]),
.cout(c1[54]), .sum(s1[54]));
mul_csa32 sc1_53_ ( .c(a1s[37]), .b(pc[84]), .a(ps[85]),
.cout(c1[53]), .sum(s1[53]));
mul_csa32 sc1_52_ ( .c(a1s[36]), .b(pc[83]), .a(ps[84]),
.cout(c1[52]), .sum(s1[52]));
mul_csa32 sc1_51_ ( .c(a1s[35]), .b(pc[82]), .a(ps[83]),
.cout(c1[51]), .sum(s1[51]));
mul_csa32 sc1_50_ ( .c(a1s[34]), .b(pc[81]), .a(ps[82]),
.cout(c1[50]), .sum(s1[50]));
mul_csa32 sc1_49_ ( .c(a1s[33]), .b(pc[80]), .a(ps[81]),
.cout(c1[49]), .sum(s1[49]));
mul_csa32 sc1_48_ ( .c(a1s[32]), .b(pc[79]), .a(ps[80]),
.cout(c1[48]), .sum(s1[48]));
mul_csa32 sc1_47_ ( .c(a1s[31]), .b(pc[78]), .a(ps[79]),
.cout(c1[47]), .sum(s1[47]));
mul_csa32 sc1_46_ ( .c(a1s[30]), .b(pc[77]), .a(ps[78]),
.cout(c1[46]), .sum(s1[46]));
mul_csa32 sc1_45_ ( .c(a1s[29]), .b(pc[76]), .a(ps[77]),
.cout(c1[45]), .sum(s1[45]));
mul_csa32 sc1_44_ ( .c(a1s[28]), .b(pc[75]), .a(ps[76]),
.cout(c1[44]), .sum(s1[44]));
mul_csa32 sc1_43_ ( .c(a1s[27]), .b(pc[74]), .a(ps[75]),
.cout(c1[43]), .sum(s1[43]));
mul_csa32 sc1_42_ ( .c(a1s[26]), .b(pc[73]), .a(ps[74]),
.cout(c1[42]), .sum(s1[42]));
mul_csa32 sc1_41_ ( .c(a1s[25]), .b(pc[72]), .a(ps[73]),
.cout(c1[41]), .sum(s1[41]));
mul_csa32 sc1_40_ ( .c(a1s[24]), .b(pc[71]), .a(ps[72]),
.cout(c1[40]), .sum(s1[40]));
mul_csa32 sc1_39_ ( .c(a1s[23]), .b(pc[70]), .a(ps[71]),
.cout(c1[39]), .sum(s1[39]));
mul_csa32 sc1_38_ ( .c(a1s[22]), .b(pc[69]), .a(ps[70]),
.cout(c1[38]), .sum(s1[38]));
mul_csa32 sc1_37_ ( .c(a1s[21]), .b(pc[68]), .a(ps[69]),
.cout(c1[37]), .sum(s1[37]));
mul_csa32 sc1_36_ ( .c(a1s[20]), .b(pc[67]), .a(ps[68]),
.cout(c1[36]), .sum(s1[36]));
mul_csa32 sc1_35_ ( .c(a1s[19]), .b(pc[66]), .a(ps[67]),
.cout(c1[35]), .sum(s1[35]));
mul_csa32 sc1_34_ ( .c(a1s[18]), .b(pc[65]), .a(ps[66]),
.cout(c1[34]), .sum(s1[34]));
mul_csa32 sc1_33_ ( .c(a1s[17]), .b(pc[64]), .a(ps[65]),
.cout(c1[33]), .sum(s1[33]));
mul_csa32 sc1_32_ ( .c(a1s[16]), .b(pc[63]), .a(ps[64]),
.cout(c1[32]), .sum(s1[32]));
mul_csa32 sc1_31_ ( .c(a1s[15]), .b(pc[62]), .a(ps[63]),
.cout(c1[31]), .sum(s1[31]));
mul_csa32 sc1_30_ ( .c(a1s[14]), .b(pc[61]), .a(ps[62]),
.cout(c1[30]), .sum(s1[30]));
mul_csa32 sc1_29_ ( .c(a1s[13]), .b(pc[60]), .a(ps[61]),
.cout(c1[29]), .sum(s1[29]));
mul_csa32 sc1_28_ ( .c(a1s[12]), .b(pc[59]), .a(ps[60]),
.cout(c1[28]), .sum(s1[28]));
mul_csa32 sc1_27_ ( .c(a1s[11]), .b(pc[58]), .a(ps[59]),
.cout(c1[27]), .sum(s1[27]));
mul_csa32 sc1_26_ ( .c(a1s[10]), .b(pc[57]), .a(ps[58]),
.cout(c1[26]), .sum(s1[26]));
mul_csa32 sc1_25_ ( .c(a1s[9]), .b(pc[56]), .a(ps[57]),
.cout(c1[25]), .sum(s1[25]));
mul_csa32 sc1_24_ ( .c(a1s[8]), .b(pc[55]), .a(ps[56]),
.cout(c1[24]), .sum(s1[24]));
mul_csa32 sc1_23_ ( .c(a1s[7]), .b(pc[54]), .a(ps[55]),
.cout(c1[23]), .sum(s1[23]));
mul_csa32 sc1_22_ ( .c(a1s[6]), .b(pc[53]), .a(ps[54]),
.cout(c1[22]), .sum(s1[22]));
mul_csa32 sc1_21_ ( .c(a1s[5]), .b(pc[52]), .a(ps[53]),
.cout(c1[21]), .sum(s1[21]));
mul_csa32 sc1_20_ ( .c(a1s[4]), .b(pc[51]), .a(ps[52]),
.cout(c1[20]), .sum(s1[20]));
mul_csa32 sc2_81_ ( .c(a0c[80]), .b(c1[80]), .a(s1[81]),
.cout(c2[81]), .sum(s2[81]));
mul_csa32 sc2_80_ ( .c(a0c[79]), .b(c1[79]), .a(s1[80]),
.cout(c2[80]), .sum(s2[80]));
mul_csa32 sc2_79_ ( .c(a0c[78]), .b(c1[78]), .a(s1[79]),
.cout(c2[79]), .sum(s2[79]));
mul_csa32 sc2_78_ ( .c(a0c[77]), .b(c1[77]), .a(s1[78]),
.cout(c2[78]), .sum(s2[78]));
mul_csa32 sc2_77_ ( .c(a0c[76]), .b(c1[76]), .a(s1[77]),
.cout(c2[77]), .sum(s2[77]));
mul_csa32 sc2_76_ ( .c(a0c[75]), .b(c1[75]), .a(s1[76]),
.cout(c2[76]), .sum(s2[76]));
mul_csa32 sc2_75_ ( .c(a0c[74]), .b(c1[74]), .a(s1[75]),
.cout(c2[75]), .sum(s2[75]));
mul_csa32 sc2_74_ ( .c(a0c[73]), .b(c1[73]), .a(s1[74]),
.cout(c2[74]), .sum(s2[74]));
mul_csa32 sc2_73_ ( .c(a0c[72]), .b(c1[72]), .a(s1[73]),
.cout(c2[73]), .sum(s2[73]));
mul_csa32 sc2_72_ ( .c(a0c[71]), .b(c1[71]), .a(s1[72]),
.cout(c2[72]), .sum(s2[72]));
mul_csa32 sc2_71_ ( .c(a0c[70]), .b(c1[70]), .a(s1[71]),
.cout(c2[71]), .sum(s2[71]));
mul_csa32 sc2_70_ ( .c(a0c[69]), .b(c1[69]), .a(s1[70]),
.cout(c2[70]), .sum(s2[70]));
mul_csa32 sc2_69_ ( .c(a0c[68]), .b(c1[68]), .a(s1[69]),
.cout(c2[69]), .sum(s2[69]));
mul_csa32 sc2_68_ ( .c(a0c[67]), .b(c1[67]), .a(s1[68]),
.cout(c2[68]), .sum(s2[68]));
mul_csa32 acc_19_ ( .c(c3[18]), .b(s3[19]), .a(ain[19]),
.cout(pcout[19]), .sum(psum[19]));
mul_csa32 acc_18_ ( .c(c3[17]), .b(s3[18]), .a(ain[18]),
.cout(pcout[18]), .sum(psum[18]));
mul_csa32 acc_17_ ( .c(c3[16]), .b(s3[17]), .a(ain[17]),
.cout(pcout[17]), .sum(psum[17]));
mul_csa32 acc_16_ ( .c(c3[15]), .b(s3[16]), .a(ain[16]),
.cout(pcout[16]), .sum(psum[16]));
mul_csa32 acc_15_ ( .c(1'b0), .b(s3[15]), .a(ain[15]),
.cout(pcout[15]), .sum(psum[15]));
mul_csa32 sc1_0_ ( .c(a0s[0]), .sum(s1[0]), .cout(c1[0]),
.a(ps[32]), .b(pc[31]));
mul_csa32 sc1_67_ ( .c(a1c[50]), .b(pc[98]), .a(a1s[51]),
.cout(c1[67]), .sum(s1[67]));
mul_ha acc_0_ ( .sum(psum[0]), .cout(pcout[0]), .a(ain[0]),
.b(s2[0]));
mul_ha sc3_98_ ( .sum(psum[98]), .cout(pcout[98]), .a(bot),
.b(a1c[81]));
mul_ha sc2_96_ ( .b(a1c[79]), .a(a1s[80]), .cout(c2[96]),
.sum(s2[96]));
mul_ha sc2_95_ ( .b(a1c[78]), .a(a1s[79]), .cout(c2[95]),
.sum(s2[95]));
mul_ha sc2_94_ ( .b(a1c[77]), .a(a1s[78]), .cout(c2[94]),
.sum(s2[94]));
mul_ha sc2_93_ ( .b(a1c[76]), .a(a1s[77]), .cout(c2[93]),
.sum(s2[93]));
mul_ha sc2_92_ ( .b(a1c[75]), .a(a1s[76]), .cout(c2[92]),
.sum(s2[92]));
mul_ha sc2_91_ ( .b(a1c[74]), .a(a1s[75]), .cout(c2[91]),
.sum(s2[91]));
mul_ha sc2_90_ ( .b(a1c[73]), .a(a1s[74]), .cout(c2[90]),
.sum(s2[90]));
mul_ha sc2_89_ ( .b(a1c[72]), .a(a1s[73]), .cout(c2[89]),
.sum(s2[89]));
mul_ha sc2_88_ ( .b(a1c[71]), .a(a1s[72]), .cout(c2[88]),
.sum(s2[88]));
mul_ha sc2_87_ ( .b(a1c[70]), .a(a1s[71]), .cout(c2[87]),
.sum(s2[87]));
mul_ha sc2_86_ ( .b(a1c[69]), .a(a1s[70]), .cout(c2[86]),
.sum(s2[86]));
mul_ha sc2_85_ ( .b(a1c[68]), .a(a1s[69]), .cout(c2[85]),
.sum(s2[85]));
mul_ha sc2_84_ ( .b(a1c[67]), .a(a1s[68]), .cout(c2[84]),
.sum(s2[84]));
mul_ha sc3_81_ ( .b(c2[80]), .a(s2[81]), .cout(c3[81]),
.sum(s3[81]));
mul_ha sc3_80_ ( .b(c2[79]), .a(s2[80]), .cout(c3[80]),
.sum(s3[80]));
mul_ha sc3_79_ ( .b(c2[78]), .a(s2[79]), .cout(c3[79]),
.sum(s3[79]));
mul_ha sc3_78_ ( .b(c2[77]), .a(s2[78]), .cout(c3[78]),
.sum(s3[78]));
mul_ha sc3_77_ ( .b(c2[76]), .a(s2[77]), .cout(c3[77]),
.sum(s3[77]));
mul_ha sc3_76_ ( .b(c2[75]), .a(s2[76]), .cout(c3[76]),
.sum(s3[76]));
mul_ha sc3_75_ ( .b(c2[74]), .a(s2[75]), .cout(c3[75]),
.sum(s3[75]));
mul_ha sc3_74_ ( .b(c2[73]), .a(s2[74]), .cout(c3[74]),
.sum(s3[74]));
mul_ha sc3_73_ ( .b(c2[72]), .a(s2[73]), .cout(c3[73]),
.sum(s3[73]));
mul_ha sc3_72_ ( .b(c2[71]), .a(s2[72]), .cout(c3[72]),
.sum(s3[72]));
mul_ha sc3_71_ ( .b(c2[70]), .a(s2[71]), .cout(c3[71]),
.sum(s3[71]));
mul_ha sc3_70_ ( .b(c2[69]), .a(s2[70]), .cout(c3[70]),
.sum(s3[70]));
mul_ha sc3_69_ ( .b(c2[68]), .a(s2[69]), .cout(c3[69]),
.sum(s3[69]));
mul_ha accx2 ( .sum(psumx2), .cout(pcoutx2), .a(ainx2), .b(s1x2));
mul_ha sc2_4_ ( .sum(s2[4]), .cout(c2[4]), .a(s1[4]), .b(c1[3]));
mul_ha sc2_3_ ( .sum(s2[3]), .cout(c2[3]), .a(s1[3]), .b(c1[2]));
mul_ha sc2_2_ ( .sum(s2[2]), .cout(c2[2]), .a(s1[2]), .b(c1[1]));
mul_ha sc2_1_ ( .sum(s2[1]), .cout(c2[1]), .a(s1[1]), .b(c1[0]));
mul_ha sc2_0_ ( .sum(s2[0]), .cout(c2[0]), .a(s1[0]), .b(c1x2));
mul_ha sc1x2 ( .sum(s1x2), .cout(c1x2), .a(ps[31]), .b(pc[30]));
endmodule //mul_array2
module mul_csa32 (sum, cout, a, b, c);
output sum, cout;
input a, b, c;
wire x, y0, y1, y2;
assign x = a ^ b;
assign sum = c ^ x;
assign y0 = a & b ;
assign y1 = a & c ;
assign y2 = b & c ;
assign cout = y0 | y1 | y2 ;
endmodule //mul_csa32
module mul_csa42 (sum, carry, cout, a, b, c, d, cin);
output sum, carry, cout;
input a, b, c, d, cin;
wire x, y, z;
assign x = a ^ b;
assign y = c ^ d;
assign z = x ^ y;
assign sum = z ^ cin ;
assign carry = (b & ~z) | (cin & z);
assign cout = (d & ~y) | (a & y);
endmodule // mul_csa42
module mul_ha ( cout, sum, a, b );
output cout, sum;
input a, b;
assign sum = a ^ b;
assign cout = a & b ;
endmodule //mul_ha
module mul_negen ( n0, n1, b );
output n0, n1;
input [2:0] b;
assign n0 = b[2] & b[1] & ~b[0] ;
assign n1 = b[2] & b[1] & b[0] ;
endmodule //mul_negen
module mul_ppgen3lsb4 (cout, p0_l, p1_l, sum, a, b0, b1 );
output p0_l, p1_l;
output [3:0] sum;
output [3:1] cout;
input [3:0] a;
input [2:0] b0;
input [2:0] b1;
wire b0n, b0n_0, b0n_1, b1n_0, b1n_1;
wire p0_0, p0_1, p0_2, p0_3, p1_2, p1_3;
wire p0_l_0, p0_l_1, p0_l_2, p1_l_2;
assign b0n = b0n_1 | (b0n_0 & p0_0) ;
assign sum[0] = b0n_0 ^ p0_0 ;
mul_negen p0n ( .b(b0[2:0]), .n1(b0n_1), .n0(b0n_0));
mul_negen p1n ( .b(b1[2:0]), .n1(b1n_1), .n0(b1n_0));
mul_csa32 sc1_2_ ( .c(b1n_0), .sum(sum[2]), .cout(cout[2]),
.a(p0_2), .b(p1_2));
mul_csa32 sc1_3_ ( .c(b1n_1), .sum(sum[3]), .cout(cout[3]),
.a(p0_3), .b(p1_3));
mul_ha sc1_1_ ( .sum(sum[1]), .cout(cout[1]), .a(p0_1),
.b(b0n));
mul_ppgen p0_3_ ( .pm1_l(p0_l_2), .p_l(p0_l), .b(b0[2:0]), .a(a[3]),
.z(p0_3));
mul_ppgen p1_3_ ( .pm1_l(p1_l_2), .p_l(p1_l), .b(b1[2:0]), .a(a[1]),
.z(p1_3));
mul_ppgen p0_2_ ( .pm1_l(p0_l_1), .p_l(p0_l_2), .b(b0[2:0]),
.a(a[2]), .z(p0_2));
mul_ppgen p0_1_ ( .pm1_l(p0_l_0), .p_l(p0_l_1), .b(b0[2:0]),
.a(a[1]), .z(p0_1));
mul_ppgen p0_0_ ( .pm1_l(1'b1), .p_l(p0_l_0),
.b(b0[2:0]), .a(a[0]), .z(p0_0));
mul_ppgen p1_2_ ( .pm1_l(1'b1), .p_l(p1_l_2),
.b(b1[2:0]), .a(a[0]), .z(p1_2));
endmodule // mul_ppgen3lsb4
module mul_ppgen3sign ( cout, sum, am1, am2, am3, am4, b0, b1, b2,
bot, head, p0m1_l, p1m1_l, p2m1_l );
input am1, am2, am3, am4;
input bot, head, p0m1_l, p1m1_l, p2m1_l;
output [5:0] sum;
output [4:0] cout;
input [2:0] b0;
input [2:0] b2;
input [2:0] b1;
wire net37, net42, net075, net088, net0117;
wire net47, net073, net38, net0118, net078, net8, net15, net43, net48, net35;
wire p2_l_67, p2_l_66, p2_l_65, p2_l_64;
wire p1_l_65, p1_l_64;
assign sum[5] = bot & net075 ;
assign net0117 = head & net088 ;
assign net37 = ~net0117 ;
assign net42 = head ^ net088 ;
mul_ppgensign p0_64_ ( .b(b0[2:0]), .z(net47), .p_l(net088),
.pm1_l(p0m1_l));
mul_ppgensign p2_68_ ( .pm1_l(p2_l_67), .b(b2[2:0]), .z(net073),
.p_l(net075));
mul_ppgensign p1_66_ ( .pm1_l(p1_l_65), .b(b1[2:0]), .z(net38),
.p_l(net0118));
mul_ha sc1_68_ ( .b(net073), .a(1'b1), .cout(cout[4]),
.sum(sum[4]));
mul_ppgen p2_67_ ( .pm1_l(p2_l_66), .b(b2[2:0]), .a(am1), .z(net078),
.p_l(p2_l_67));
mul_ppgen p2_66_ ( .pm1_l(p2_l_65), .b(b2[2:0]), .a(am2), .z(net8),
.p_l(p2_l_66));
mul_ppgen p2_65_ ( .pm1_l(p2_l_64), .p_l(p2_l_65), .b(b2[2:0]),
.a(am3), .z(net15));
mul_ppgen p1_65_ ( .pm1_l(p1_l_64), .p_l(p1_l_65), .b(b1[2:0]),
.a(am1), .z(net43));
mul_ppgen p1_64_ ( .pm1_l(p1m1_l), .p_l(p1_l_64), .b(b1[2:0]),
.a(am2), .z(net48));
mul_ppgen p2_64_ ( .pm1_l(p2m1_l), .p_l(p2_l_64), .b(b2[2:0]),
.a(am4), .z(net35));
mul_csa32 sc1_67_ ( .c(net078), .b(net0117), .a(net0118),
.cout(cout[3]), .sum(sum[3]));
mul_csa32 sc1_66_ ( .c(net8), .b(net37), .a(net38), .cout(cout[2]),
.sum(sum[2]));
mul_csa32 sc1_65_ ( .c(net15), .b(net42), .a(net43), .cout(cout[1]),
.sum(sum[1]));
mul_csa32 sc1_64_ ( .c(net35), .b(net47), .a(net48), .cout(cout[0]),
.sum(sum[0]));
endmodule //mul_ppgen3sign
module mul_ppgen3 ( cout, p0_l, p1_l, p2_l, sum, am2, am4,
a, b0, b1, b2, p0m1_l, p1m1_l, p2m1_l );
output cout, p0_l, p1_l, p2_l, sum;
input am2, am4;
input a, p0m1_l, p1m1_l, p2m1_l;
input [2:0] b0;
input [2:0] b2;
input [2:0] b1;
wire net046, net32, net043;
mul_csa32 sc1 ( .a(net046), .b(net32), .cout(cout), .sum(sum),
.c(net043));
mul_ppgen p2 ( .pm1_l(p2m1_l), .p_l(p2_l), .b(b2[2:0]), .a(am4),
.z(net043));
mul_ppgen p1 ( .pm1_l(p1m1_l), .p_l(p1_l), .b(b1[2:0]), .a(am2),
.z(net046));
mul_ppgen p0 ( .pm1_l(p0m1_l), .p_l(p0_l), .b(b0[2:0]), .a(a),
.z(net32));
endmodule // mul_ppgen3
module mul_ppgenrow3 ( cout, sum, a, b0, b1, b2, bot, head );
output [68:1] cout;
output [69:0] sum;
input [63:0] a;
input [2:0] b2;
input [2:0] b0;
input [2:0] b1;
input bot, head;
// Buses in the design
wire [63:4] p2_l;
wire [63:3] p1_l;
wire [63:3] p0_l;
mul_ppgen3sign I2 ( .am4(a[60]), .am3(a[61]), .am2(a[62]),
.am1(a[63]), .p2m1_l(p2_l[63]), .p1m1_l(p1_l[63]),
.p0m1_l(p0_l[63]), .b2(b2[2:0]), .head(head), .bot(bot),
.sum(sum[69:64]), .cout(cout[68:64]), .b1(b1[2:0]), .b0(b0[2:0]));
mul_ppgen3 I1_63_ ( .p2_l(p2_l[63]), .b2(b2[2:0]),
.am2(a[61]), .a(a[63]), .p2m1_l(p2_l[62]),
.p1m1_l(p1_l[62]), .p0m1_l(p0_l[62]), .am4(a[59]), .sum(sum[63]),
.cout(cout[63]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[63]),
.p0_l(p0_l[63]));
mul_ppgen3 I1_62_ ( .p2_l(p2_l[62]), .b2(b2[2:0]),
.am2(a[60]), .a(a[62]), .p2m1_l(p2_l[61]),
.p1m1_l(p1_l[61]), .p0m1_l(p0_l[61]), .am4(a[58]), .sum(sum[62]),
.cout(cout[62]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[62]),
.p0_l(p0_l[62]));
mul_ppgen3 I1_61_ ( .p2_l(p2_l[61]), .b2(b2[2:0]),
.am2(a[59]), .a(a[61]), .p2m1_l(p2_l[60]),
.p1m1_l(p1_l[60]), .p0m1_l(p0_l[60]), .am4(a[57]), .sum(sum[61]),
.cout(cout[61]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[61]),
.p0_l(p0_l[61]));
mul_ppgen3 I1_60_ ( .p2_l(p2_l[60]), .b2(b2[2:0]),
.am2(a[58]), .a(a[60]), .p2m1_l(p2_l[59]),
.p1m1_l(p1_l[59]), .p0m1_l(p0_l[59]), .am4(a[56]), .sum(sum[60]),
.cout(cout[60]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[60]),
.p0_l(p0_l[60]));
mul_ppgen3 I1_59_ ( .p2_l(p2_l[59]), .b2(b2[2:0]),
.am2(a[57]), .a(a[59]), .p2m1_l(p2_l[58]),
.p1m1_l(p1_l[58]), .p0m1_l(p0_l[58]), .am4(a[55]), .sum(sum[59]),
.cout(cout[59]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[59]),
.p0_l(p0_l[59]));
mul_ppgen3 I1_58_ ( .p2_l(p2_l[58]), .b2(b2[2:0]),
.am2(a[56]), .a(a[58]), .p2m1_l(p2_l[57]),
.p1m1_l(p1_l[57]), .p0m1_l(p0_l[57]), .am4(a[54]), .sum(sum[58]),
.cout(cout[58]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[58]),
.p0_l(p0_l[58]));
mul_ppgen3 I1_57_ ( .p2_l(p2_l[57]), .b2(b2[2:0]),
.am2(a[55]), .a(a[57]), .p2m1_l(p2_l[56]),
.p1m1_l(p1_l[56]), .p0m1_l(p0_l[56]), .am4(a[53]), .sum(sum[57]),
.cout(cout[57]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[57]),
.p0_l(p0_l[57]));
mul_ppgen3 I1_56_ ( .p2_l(p2_l[56]), .b2(b2[2:0]),
.am2(a[54]), .a(a[56]), .p2m1_l(p2_l[55]),
.p1m1_l(p1_l[55]), .p0m1_l(p0_l[55]), .am4(a[52]), .sum(sum[56]),
.cout(cout[56]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[56]),
.p0_l(p0_l[56]));
mul_ppgen3 I1_55_ ( .p2_l(p2_l[55]), .b2(b2[2:0]),
.am2(a[53]), .a(a[55]), .p2m1_l(p2_l[54]),
.p1m1_l(p1_l[54]), .p0m1_l(p0_l[54]), .am4(a[51]), .sum(sum[55]),
.cout(cout[55]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[55]),
.p0_l(p0_l[55]));
mul_ppgen3 I1_54_ ( .p2_l(p2_l[54]), .b2(b2[2:0]),
.am2(a[52]), .a(a[54]), .p2m1_l(p2_l[53]),
.p1m1_l(p1_l[53]), .p0m1_l(p0_l[53]), .am4(a[50]), .sum(sum[54]),
.cout(cout[54]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[54]),
.p0_l(p0_l[54]));
mul_ppgen3 I1_53_ ( .p2_l(p2_l[53]), .b2(b2[2:0]),
.am2(a[51]), .a(a[53]), .p2m1_l(p2_l[52]),
.p1m1_l(p1_l[52]), .p0m1_l(p0_l[52]), .am4(a[49]), .sum(sum[53]),
.cout(cout[53]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[53]),
.p0_l(p0_l[53]));
mul_ppgen3 I1_52_ ( .p2_l(p2_l[52]), .b2(b2[2:0]),
.am2(a[50]), .a(a[52]), .p2m1_l(p2_l[51]),
.p1m1_l(p1_l[51]), .p0m1_l(p0_l[51]), .am4(a[48]), .sum(sum[52]),
.cout(cout[52]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[52]),
.p0_l(p0_l[52]));
mul_ppgen3 I1_51_ ( .p2_l(p2_l[51]), .b2(b2[2:0]),
.am2(a[49]), .a(a[51]), .p2m1_l(p2_l[50]),
.p1m1_l(p1_l[50]), .p0m1_l(p0_l[50]), .am4(a[47]), .sum(sum[51]),
.cout(cout[51]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[51]),
.p0_l(p0_l[51]));
mul_ppgen3 I1_50_ ( .p2_l(p2_l[50]), .b2(b2[2:0]),
.am2(a[48]), .a(a[50]), .p2m1_l(p2_l[49]),
.p1m1_l(p1_l[49]), .p0m1_l(p0_l[49]), .am4(a[46]), .sum(sum[50]),
.cout(cout[50]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[50]),
.p0_l(p0_l[50]));
mul_ppgen3 I1_49_ ( .p2_l(p2_l[49]), .b2(b2[2:0]),
.am2(a[47]), .a(a[49]), .p2m1_l(p2_l[48]),
.p1m1_l(p1_l[48]), .p0m1_l(p0_l[48]), .am4(a[45]), .sum(sum[49]),
.cout(cout[49]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[49]),
.p0_l(p0_l[49]));
mul_ppgen3 I1_48_ ( .p2_l(p2_l[48]), .b2(b2[2:0]),
.am2(a[46]), .a(a[48]), .p2m1_l(p2_l[47]),
.p1m1_l(p1_l[47]), .p0m1_l(p0_l[47]), .am4(a[44]), .sum(sum[48]),
.cout(cout[48]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[48]),
.p0_l(p0_l[48]));
mul_ppgen3 I1_47_ ( .p2_l(p2_l[47]), .b2(b2[2:0]),
.am2(a[45]), .a(a[47]), .p2m1_l(p2_l[46]),
.p1m1_l(p1_l[46]), .p0m1_l(p0_l[46]), .am4(a[43]), .sum(sum[47]),
.cout(cout[47]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[47]),
.p0_l(p0_l[47]));
mul_ppgen3 I1_46_ ( .p2_l(p2_l[46]), .b2(b2[2:0]),
.am2(a[44]), .a(a[46]), .p2m1_l(p2_l[45]),
.p1m1_l(p1_l[45]), .p0m1_l(p0_l[45]), .am4(a[42]), .sum(sum[46]),
.cout(cout[46]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[46]),
.p0_l(p0_l[46]));
mul_ppgen3 I1_45_ ( .p2_l(p2_l[45]), .b2(b2[2:0]),
.am2(a[43]), .a(a[45]), .p2m1_l(p2_l[44]),
.p1m1_l(p1_l[44]), .p0m1_l(p0_l[44]), .am4(a[41]), .sum(sum[45]),
.cout(cout[45]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[45]),
.p0_l(p0_l[45]));
mul_ppgen3 I1_44_ ( .p2_l(p2_l[44]), .b2(b2[2:0]),
.am2(a[42]), .a(a[44]), .p2m1_l(p2_l[43]),
.p1m1_l(p1_l[43]), .p0m1_l(p0_l[43]), .am4(a[40]), .sum(sum[44]),
.cout(cout[44]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[44]),
.p0_l(p0_l[44]));
mul_ppgen3 I1_43_ ( .p2_l(p2_l[43]), .b2(b2[2:0]),
.am2(a[41]), .a(a[43]), .p2m1_l(p2_l[42]),
.p1m1_l(p1_l[42]), .p0m1_l(p0_l[42]), .am4(a[39]), .sum(sum[43]),
.cout(cout[43]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[43]),
.p0_l(p0_l[43]));
mul_ppgen3 I1_42_ ( .p2_l(p2_l[42]), .b2(b2[2:0]),
.am2(a[40]), .a(a[42]), .p2m1_l(p2_l[41]),
.p1m1_l(p1_l[41]), .p0m1_l(p0_l[41]), .am4(a[38]), .sum(sum[42]),
.cout(cout[42]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[42]),
.p0_l(p0_l[42]));
mul_ppgen3 I1_41_ ( .p2_l(p2_l[41]), .b2(b2[2:0]),
.am2(a[39]), .a(a[41]), .p2m1_l(p2_l[40]),
.p1m1_l(p1_l[40]), .p0m1_l(p0_l[40]), .am4(a[37]), .sum(sum[41]),
.cout(cout[41]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[41]),
.p0_l(p0_l[41]));
mul_ppgen3 I1_40_ ( .p2_l(p2_l[40]), .b2(b2[2:0]),
.am2(a[38]), .a(a[40]), .p2m1_l(p2_l[39]),
.p1m1_l(p1_l[39]), .p0m1_l(p0_l[39]), .am4(a[36]), .sum(sum[40]),
.cout(cout[40]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[40]),
.p0_l(p0_l[40]));
mul_ppgen3 I1_39_ ( .p2_l(p2_l[39]), .b2(b2[2:0]),
.am2(a[37]), .a(a[39]), .p2m1_l(p2_l[38]),
.p1m1_l(p1_l[38]), .p0m1_l(p0_l[38]), .am4(a[35]), .sum(sum[39]),
.cout(cout[39]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[39]),
.p0_l(p0_l[39]));
mul_ppgen3 I1_38_ ( .p2_l(p2_l[38]), .b2(b2[2:0]),
.am2(a[36]), .a(a[38]), .p2m1_l(p2_l[37]),
.p1m1_l(p1_l[37]), .p0m1_l(p0_l[37]), .am4(a[34]), .sum(sum[38]),
.cout(cout[38]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[38]),
.p0_l(p0_l[38]));
mul_ppgen3 I1_37_ ( .p2_l(p2_l[37]), .b2(b2[2:0]),
.am2(a[35]), .a(a[37]), .p2m1_l(p2_l[36]),
.p1m1_l(p1_l[36]), .p0m1_l(p0_l[36]), .am4(a[33]), .sum(sum[37]),
.cout(cout[37]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[37]),
.p0_l(p0_l[37]));
mul_ppgen3 I1_36_ ( .p2_l(p2_l[36]), .b2(b2[2:0]),
.am2(a[34]), .a(a[36]), .p2m1_l(p2_l[35]),
.p1m1_l(p1_l[35]), .p0m1_l(p0_l[35]), .am4(a[32]), .sum(sum[36]),
.cout(cout[36]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[36]),
.p0_l(p0_l[36]));
mul_ppgen3 I1_35_ ( .p2_l(p2_l[35]), .b2(b2[2:0]),
.am2(a[33]), .a(a[35]), .p2m1_l(p2_l[34]),
.p1m1_l(p1_l[34]), .p0m1_l(p0_l[34]), .am4(a[31]), .sum(sum[35]),
.cout(cout[35]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[35]),
.p0_l(p0_l[35]));
mul_ppgen3 I1_34_ ( .p2_l(p2_l[34]), .b2(b2[2:0]),
.am2(a[32]), .a(a[34]), .p2m1_l(p2_l[33]),
.p1m1_l(p1_l[33]), .p0m1_l(p0_l[33]), .am4(a[30]), .sum(sum[34]),
.cout(cout[34]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[34]),
.p0_l(p0_l[34]));
mul_ppgen3 I1_33_ ( .p2_l(p2_l[33]), .b2(b2[2:0]),
.am2(a[31]), .a(a[33]), .p2m1_l(p2_l[32]),
.p1m1_l(p1_l[32]), .p0m1_l(p0_l[32]), .am4(a[29]), .sum(sum[33]),
.cout(cout[33]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[33]),
.p0_l(p0_l[33]));
mul_ppgen3 I1_32_ ( .p2_l(p2_l[32]), .b2(b2[2:0]),
.am2(a[30]), .a(a[32]), .p2m1_l(p2_l[31]),
.p1m1_l(p1_l[31]), .p0m1_l(p0_l[31]), .am4(a[28]), .sum(sum[32]),
.cout(cout[32]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[32]),
.p0_l(p0_l[32]));
mul_ppgen3 I1_31_ ( .p2_l(p2_l[31]), .b2(b2[2:0]),
.am2(a[29]), .a(a[31]), .p2m1_l(p2_l[30]),
.p1m1_l(p1_l[30]), .p0m1_l(p0_l[30]), .am4(a[27]), .sum(sum[31]),
.cout(cout[31]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[31]),
.p0_l(p0_l[31]));
mul_ppgen3 I1_30_ ( .p2_l(p2_l[30]), .b2(b2[2:0]),
.am2(a[28]), .a(a[30]), .p2m1_l(p2_l[29]),
.p1m1_l(p1_l[29]), .p0m1_l(p0_l[29]), .am4(a[26]), .sum(sum[30]),
.cout(cout[30]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[30]),
.p0_l(p0_l[30]));
mul_ppgen3 I1_29_ ( .p2_l(p2_l[29]), .b2(b2[2:0]),
.am2(a[27]), .a(a[29]), .p2m1_l(p2_l[28]),
.p1m1_l(p1_l[28]), .p0m1_l(p0_l[28]), .am4(a[25]), .sum(sum[29]),
.cout(cout[29]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[29]),
.p0_l(p0_l[29]));
mul_ppgen3 I1_28_ ( .p2_l(p2_l[28]), .b2(b2[2:0]),
.am2(a[26]), .a(a[28]), .p2m1_l(p2_l[27]),
.p1m1_l(p1_l[27]), .p0m1_l(p0_l[27]), .am4(a[24]), .sum(sum[28]),
.cout(cout[28]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[28]),
.p0_l(p0_l[28]));
mul_ppgen3 I1_27_ ( .p2_l(p2_l[27]), .b2(b2[2:0]),
.am2(a[25]), .a(a[27]), .p2m1_l(p2_l[26]),
.p1m1_l(p1_l[26]), .p0m1_l(p0_l[26]), .am4(a[23]), .sum(sum[27]),
.cout(cout[27]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[27]),
.p0_l(p0_l[27]));
mul_ppgen3 I1_26_ ( .p2_l(p2_l[26]), .b2(b2[2:0]),
.am2(a[24]), .a(a[26]), .p2m1_l(p2_l[25]),
.p1m1_l(p1_l[25]), .p0m1_l(p0_l[25]), .am4(a[22]), .sum(sum[26]),
.cout(cout[26]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[26]),
.p0_l(p0_l[26]));
mul_ppgen3 I1_25_ ( .p2_l(p2_l[25]), .b2(b2[2:0]),
.am2(a[23]), .a(a[25]), .p2m1_l(p2_l[24]),
.p1m1_l(p1_l[24]), .p0m1_l(p0_l[24]), .am4(a[21]), .sum(sum[25]),
.cout(cout[25]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[25]),
.p0_l(p0_l[25]));
mul_ppgen3 I1_24_ ( .p2_l(p2_l[24]), .b2(b2[2:0]),
.am2(a[22]), .a(a[24]), .p2m1_l(p2_l[23]),
.p1m1_l(p1_l[23]), .p0m1_l(p0_l[23]), .am4(a[20]), .sum(sum[24]),
.cout(cout[24]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[24]),
.p0_l(p0_l[24]));
mul_ppgen3 I1_23_ ( .p2_l(p2_l[23]), .b2(b2[2:0]),
.am2(a[21]), .a(a[23]), .p2m1_l(p2_l[22]),
.p1m1_l(p1_l[22]), .p0m1_l(p0_l[22]), .am4(a[19]), .sum(sum[23]),
.cout(cout[23]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[23]),
.p0_l(p0_l[23]));
mul_ppgen3 I1_22_ ( .p2_l(p2_l[22]), .b2(b2[2:0]),
.am2(a[20]), .a(a[22]), .p2m1_l(p2_l[21]),
.p1m1_l(p1_l[21]), .p0m1_l(p0_l[21]), .am4(a[18]), .sum(sum[22]),
.cout(cout[22]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[22]),
.p0_l(p0_l[22]));
mul_ppgen3 I1_21_ ( .p2_l(p2_l[21]), .b2(b2[2:0]),
.am2(a[19]), .a(a[21]), .p2m1_l(p2_l[20]),
.p1m1_l(p1_l[20]), .p0m1_l(p0_l[20]), .am4(a[17]), .sum(sum[21]),
.cout(cout[21]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[21]),
.p0_l(p0_l[21]));
mul_ppgen3 I1_20_ ( .p2_l(p2_l[20]), .b2(b2[2:0]),
.am2(a[18]), .a(a[20]), .p2m1_l(p2_l[19]),
.p1m1_l(p1_l[19]), .p0m1_l(p0_l[19]), .am4(a[16]), .sum(sum[20]),
.cout(cout[20]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[20]),
.p0_l(p0_l[20]));
mul_ppgen3 I1_19_ ( .p2_l(p2_l[19]), .b2(b2[2:0]),
.am2(a[17]), .a(a[19]), .p2m1_l(p2_l[18]),
.p1m1_l(p1_l[18]), .p0m1_l(p0_l[18]), .am4(a[15]), .sum(sum[19]),
.cout(cout[19]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[19]),
.p0_l(p0_l[19]));
mul_ppgen3 I1_18_ ( .p2_l(p2_l[18]), .b2(b2[2:0]),
.am2(a[16]), .a(a[18]), .p2m1_l(p2_l[17]),
.p1m1_l(p1_l[17]), .p0m1_l(p0_l[17]), .am4(a[14]), .sum(sum[18]),
.cout(cout[18]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[18]),
.p0_l(p0_l[18]));
mul_ppgen3 I1_17_ ( .p2_l(p2_l[17]), .b2(b2[2:0]),
.am2(a[15]), .a(a[17]), .p2m1_l(p2_l[16]),
.p1m1_l(p1_l[16]), .p0m1_l(p0_l[16]), .am4(a[13]), .sum(sum[17]),
.cout(cout[17]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[17]),
.p0_l(p0_l[17]));
mul_ppgen3 I1_16_ ( .p2_l(p2_l[16]), .b2(b2[2:0]),
.am2(a[14]), .a(a[16]), .p2m1_l(p2_l[15]),
.p1m1_l(p1_l[15]), .p0m1_l(p0_l[15]), .am4(a[12]), .sum(sum[16]),
.cout(cout[16]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[16]),
.p0_l(p0_l[16]));
mul_ppgen3 I1_15_ ( .p2_l(p2_l[15]), .b2(b2[2:0]),
.am2(a[13]), .a(a[15]), .p2m1_l(p2_l[14]),
.p1m1_l(p1_l[14]), .p0m1_l(p0_l[14]), .am4(a[11]), .sum(sum[15]),
.cout(cout[15]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[15]),
.p0_l(p0_l[15]));
mul_ppgen3 I1_14_ ( .p2_l(p2_l[14]), .b2(b2[2:0]),
.am2(a[12]), .a(a[14]), .p2m1_l(p2_l[13]),
.p1m1_l(p1_l[13]), .p0m1_l(p0_l[13]), .am4(a[10]), .sum(sum[14]),
.cout(cout[14]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[14]),
.p0_l(p0_l[14]));
mul_ppgen3 I1_13_ ( .p2_l(p2_l[13]), .b2(b2[2:0]),
.am2(a[11]), .a(a[13]), .p2m1_l(p2_l[12]),
.p1m1_l(p1_l[12]), .p0m1_l(p0_l[12]), .am4(a[9]), .sum(sum[13]),
.cout(cout[13]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[13]),
.p0_l(p0_l[13]));
mul_ppgen3 I1_12_ ( .p2_l(p2_l[12]), .b2(b2[2:0]),
.am2(a[10]), .a(a[12]), .p2m1_l(p2_l[11]),
.p1m1_l(p1_l[11]), .p0m1_l(p0_l[11]), .am4(a[8]), .sum(sum[12]),
.cout(cout[12]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[12]),
.p0_l(p0_l[12]));
mul_ppgen3 I1_11_ ( .p2_l(p2_l[11]), .b2(b2[2:0]),
.am2(a[9]), .a(a[11]), .p2m1_l(p2_l[10]),
.p1m1_l(p1_l[10]), .p0m1_l(p0_l[10]), .am4(a[7]), .sum(sum[11]),
.cout(cout[11]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[11]),
.p0_l(p0_l[11]));
mul_ppgen3 I1_10_ ( .p2_l(p2_l[10]), .b2(b2[2:0]),
.am2(a[8]), .a(a[10]), .p2m1_l(p2_l[9]),
.p1m1_l(p1_l[9]), .p0m1_l(p0_l[9]), .am4(a[6]), .sum(sum[10]),
.cout(cout[10]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[10]),
.p0_l(p0_l[10]));
mul_ppgen3 I1_9_ ( .p2_l(p2_l[9]), .b2(b2[2:0]),
.am2(a[7]), .a(a[9]), .p2m1_l(p2_l[8]),
.p1m1_l(p1_l[8]), .p0m1_l(p0_l[8]), .am4(a[5]), .sum(sum[9]),
.cout(cout[9]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[9]),
.p0_l(p0_l[9]));
mul_ppgen3 I1_8_ ( .p2_l(p2_l[8]), .b2(b2[2:0]),
.am2(a[6]), .a(a[8]), .p2m1_l(p2_l[7]),
.p1m1_l(p1_l[7]), .p0m1_l(p0_l[7]), .am4(a[4]), .sum(sum[8]),
.cout(cout[8]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[8]),
.p0_l(p0_l[8]));
mul_ppgen3 I1_7_ ( .p2_l(p2_l[7]), .b2(b2[2:0]),
.am2(a[5]), .a(a[7]), .p2m1_l(p2_l[6]),
.p1m1_l(p1_l[6]), .p0m1_l(p0_l[6]), .am4(a[3]), .sum(sum[7]),
.cout(cout[7]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[7]),
.p0_l(p0_l[7]));
mul_ppgen3 I1_6_ ( .p2_l(p2_l[6]), .b2(b2[2:0]),
.am2(a[4]), .a(a[6]), .p2m1_l(p2_l[5]),
.p1m1_l(p1_l[5]), .p0m1_l(p0_l[5]), .am4(a[2]), .sum(sum[6]),
.cout(cout[6]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[6]),
.p0_l(p0_l[6]));
mul_ppgen3 I1_5_ ( .p2_l(p2_l[5]), .b2(b2[2:0]),
.am2(a[3]), .a(a[5]), .p2m1_l(p2_l[4]),
.p1m1_l(p1_l[4]), .p0m1_l(p0_l[4]), .am4(a[1]), .sum(sum[5]),
.cout(cout[5]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[5]),
.p0_l(p0_l[5]));
mul_ppgen3 I1_4_ ( .p2_l(p2_l[4]), .b2(b2[2:0]),
.am2(a[2]), .a(a[4]), .p2m1_l(1'b1),
.p1m1_l(p1_l[3]), .p0m1_l(p0_l[3]), .am4(a[0]), .sum(sum[4]),
.cout(cout[4]), .b1(b1[2:0]), .b0(b0[2:0]), .p1_l(p1_l[4]),
.p0_l(p0_l[4]));
mul_ppgen3lsb4 I0 ( .cout(cout[3:1]), .a(a[3:0]), .sum(sum[3:0]),
.p1_l(p1_l[3]), .p0_l(p0_l[3]), .b1(b1[2:0]), .b0(b0[2:0]));
endmodule //mul_ppgenrow3
module mul_ppgensign ( p_l, z, b, pm1_l );
output p_l, z;
input pm1_l;
input [2:0] b;
assign p_l = ~(b[1] & b[2]);
assign z = b[0] ? ~pm1_l : ~p_l ;
endmodule //mul_ppgensign
module mul_ppgen ( p_l, z, a, b, pm1_l );
output p_l, z;
input a, pm1_l;
input [2:0] b;
assign p_l = ~((a ^ b[2]) & b[1]) ;
assign z = b[0] ? ~pm1_l : ~p_l ;
endmodule //mul_ppgen
module mul_mux2 ( z, d0, d1, s );
output z;
input d0, d1, s;
assign z = s ? d1 : d0 ;
endmodule // mul_mux2
module mul_booth(
head,
b_in,
b0, b1, b2, b3, b4, b5, b6, b7,
b8, b9, b10, b11, b12, b13, b14, b15, b16,
clk, se, si, so, mul_step, tm_l
);
input head; // begin of the MUL operation
input [63:0] b_in;
input clk, se, si, mul_step, tm_l;
output [2:0] b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15;
output b16;
output so;
wire [63:31] b;
wire [2:0] b0_in0, b1_in0, b2_in0, b3_in0, b4_in0, b5_in0, b6_in0, b7_in0 ;
wire [2:0] b8_in0, b9_in0, b10_in0, b11_in0, b12_in0, b13_in0, b14_in0, b15_in0 ;
wire [2:0] b0_in1, b1_in1, b2_in1, b3_in1, b4_in1, b5_in1, b6_in1, b7_in1 ;
wire [2:0] b8_in1, b9_in1, b10_in1, b11_in1, b12_in1, b13_in1, b14_in1, b15_in1 ;
wire b16_in1;
wire [2:0] b0_outmx, b1_outmx, b2_outmx, b3_outmx, b4_outmx, b5_outmx, b6_outmx;
wire [2:0] b7_outmx, b8_outmx, b9_outmx, b10_outmx, b11_outmx, b12_outmx, b13_outmx;
wire [2:0] b14_outmx, b15_outmx;
wire b16_outmx;
wire clk_enb0, clk_enb1;
mul_bodec encode0_a(
.x (1'b0),
.b (b_in[15:0]),
.b0 (b0_in0),
.b1 (b1_in0),
.b2 (b2_in0),
.b3 (b3_in0),
.b4 (b4_in0),
.b5 (b5_in0),
.b6 (b6_in0),
.b7 (b7_in0)
);
//remove 16th row since it's never the last row
//b8_in0 = 3'b010;
mul_bodec encode0_b(
.x (b_in[15]),
.b (b_in[31:16]),
.b0 (b8_in0),
.b1 (b9_in0),
.b2 (b10_in0),
.b3 (b11_in0),
.b4 (b12_in0),
.b5 (b13_in0),
.b6 (b14_in0),
.b7 (b15_in0)
);
// remove 32th row since it's never the last row
// b16_in0 = 3'b010 ;
// Pipe picked address [63:31] and hold flop
clken_buf ckbuf_0(.clk(clk_enb0), .rclk(clk), .enb_l(~mul_step), .tmb_l(tm_l));
clken_buf ckbuf_1(.clk(clk_enb1), .rclk(clk), .enb_l(~(head & mul_step)), .tmb_l(tm_l));
dff hld_dff0(.din(b_in[31]), .clk(clk_enb1), .q(b[31]),
.se(se), .si(), .so());
dff #(32) hld_dff(.din(b_in[63:32]), .clk(clk_enb1), .q(b[63:32]),
.se(se), .si(), .so());
mul_bodec encode1_a(
.x (b[31]),
.b (b[47:32]),
.b0 (b0_in1),
.b1 (b1_in1),
.b2 (b2_in1),
.b3 (b3_in1),
.b4 (b4_in1),
.b5 (b5_in1),
.b6 (b6_in1),
.b7 (b7_in1)
);
//remove 16th row since it's never the last row
//b8_in1 = 3'b010;
mul_bodec encode1_b(
.x (b[47]),
.b (b[63:48]),
.b0 (b8_in1),
.b1 (b9_in1),
.b2 (b10_in1),
.b3 (b11_in1),
.b4 (b12_in1),
.b5 (b13_in1),
.b6 (b14_in1),
.b7 (b15_in1)
);
assign b16_in1 = b[63] ;
// Select booth encoded b outputs and flop based on the cycle0 and cycle1
dp_mux2es #(3) out_mux0(.dout(b0_outmx[2:0]),
.in0(b0_in0[2:0]),
.in1(b0_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux1(.dout(b1_outmx[2:0]),
.in0(b1_in0[2:0]),
.in1(b1_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux2(.dout(b2_outmx[2:0]),
.in0(b2_in0[2:0]),
.in1(b2_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux3(.dout(b3_outmx[2:0]),
.in0(b3_in0[2:0]),
.in1(b3_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux4(.dout(b4_outmx[2:0]),
.in0(b4_in0[2:0]),
.in1(b4_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux5(.dout(b5_outmx[2:0]),
.in0(b5_in0[2:0]),
.in1(b5_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux6(.dout(b6_outmx[2:0]),
.in0(b6_in0[2:0]),
.in1(b6_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux7(.dout(b7_outmx[2:0]),
.in0(b7_in0[2:0]),
.in1(b7_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux8(.dout(b8_outmx[2:0]),
.in0(b8_in0[2:0]),
.in1(b8_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux9(.dout(b9_outmx[2:0]),
.in0(b9_in0[2:0]),
.in1(b9_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux10(.dout(b10_outmx[2:0]),
.in0(b10_in0[2:0]),
.in1(b10_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux11(.dout(b11_outmx[2:0]),
.in0(b11_in0[2:0]),
.in1(b11_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux12(.dout(b12_outmx[2:0]),
.in0(b12_in0[2:0]),
.in1(b12_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux13(.dout(b13_outmx[2:0]),
.in0(b13_in0[2:0]),
.in1(b13_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux14(.dout(b14_outmx[2:0]),
.in0(b14_in0[2:0]),
.in1(b14_in1[2:0]),
.sel(~head));
dp_mux2es #(3) out_mux15(.dout(b15_outmx[2:0]),
.in0(b15_in0[2:0]),
.in1(b15_in1[2:0]),
.sel(~head));
dp_mux2es out_mux16(.dout(b16_outmx),
.in0(1'b0),
.in1(b16_in1),
.sel(~head));
dff #(3) out_dff0 (.din(b0_outmx[2:0]), .clk(clk_enb0), .q(b0[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff1 (.din(b1_outmx[2:0]), .clk(clk_enb0), .q(b1[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff2 (.din(b2_outmx[2:0]), .clk(clk_enb0), .q(b2[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff3 (.din(b3_outmx[2:0]), .clk(clk_enb0), .q(b3[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff4 (.din(b4_outmx[2:0]), .clk(clk_enb0), .q(b4[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff5 (.din(b5_outmx[2:0]), .clk(clk_enb0), .q(b5[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff6 (.din(b6_outmx[2:0]), .clk(clk_enb0), .q(b6[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff7 (.din(b7_outmx[2:0]), .clk(clk_enb0), .q(b7[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff8 (.din(b8_outmx[2:0]), .clk(clk_enb0), .q(b8[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff9 (.din(b9_outmx[2:0]), .clk(clk_enb0), .q(b9[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff10 (.din(b10_outmx[2:0]), .clk(clk_enb0), .q(b10[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff11 (.din(b11_outmx[2:0]), .clk(clk_enb0), .q(b11[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff12 (.din(b12_outmx[2:0]), .clk(clk_enb0), .q(b12[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff13 (.din(b13_outmx[2:0]), .clk(clk_enb0), .q(b13[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff14 (.din(b14_outmx[2:0]), .clk(clk_enb0), .q(b14[2:0]),
.se(se), .si(), .so());
dff #(3) out_dff15 (.din(b15_outmx[2:0]), .clk(clk_enb0), .q(b15[2:0]),
.se(se), .si(), .so());
dff out_dff16 (.din(b16_outmx), .clk(clk_enb0), .q(b16),
.se(se), .si(), .so());
endmodule //mul_booth
module mul_bodec (x, b,
b0, b1, b2, b3, b4, b5, b6, b7);
input x;
input [15:0] b;
output [2:0] b0, b1, b2, b3, b4, b5, b6, b7;
assign b0[2] = b[1];
assign b0[1] = ~((b[1] & b[0] & x) | (~b[1] & ~b[0] & ~x)) ;
assign b0[0] = (~b[1] & b[0] & x) | (b[1] & ~b[0] & ~x) ;
assign b1[2] = b[3];
assign b1[1] = ~((b[3] & b[2] & b[1]) | (~b[3] & ~b[2] & ~b[1])) ;
assign b1[0] = (~b[3] & b[2] & b[1]) | (b[3] & ~b[2] & ~b[1]) ;
assign b2[2] = b[5];
assign b2[1] = ~((b[5] & b[4] & b[3]) | (~b[5] & ~b[4] & ~b[3])) ;
assign b2[0] = (~b[5] & b[4] & b[3]) | (b[5] & ~b[4] & ~b[3]) ;
assign b3[2] = b[7] ;
assign b3[1] = ~((b[7] & b[6] & b[5]) | (~b[7] & ~b[6] & ~b[5])) ;
assign b3[0] = (~b[7] & b[6] & b[5]) | (b[7] & ~b[6] & ~b[5]) ;
assign b4[2] = b[9] ;
assign b4[1] = ~((b[9] & b[8] & b[7]) | (~b[9] & ~b[8] & ~b[7])) ;
assign b4[0] = (~b[9] & b[8] & b[7]) | (b[9] & ~b[8] & ~b[7]) ;
assign b5[2] = b[11] ;
assign b5[1] = ~((b[11] & b[10] & b[9]) | (~b[11] & ~b[10] & ~b[9])) ;
assign b5[0] = (~b[11] & b[10] & b[9]) | (b[11] & ~b[10] & ~b[9]) ;
assign b6[2] = b[13] ;
assign b6[1] = ~((b[13] & b[12] & b[11]) | (~b[13] & ~b[12] & ~b[11])) ;
assign b6[0] = (~b[13] & b[12] & b[11]) | (b[13] & ~b[12] & ~b[11]) ;
assign b7[2] = b[15] ;
assign b7[1] = ~((b[15] & b[14] & b[13]) | (~b[15] & ~b[14] & ~b[13])) ;
assign b7[0] = (~b[15] & b[14] & b[13]) | (b[15] & ~b[14] & ~b[13]) ;
endmodule // mul_bodec
`endif
|
module EmitOneCH
(
input Transmit_CLK, //80MHz
input RX_Gate, //Transmit Enable
input [7:0] EmitDelay, //7th bit for Transmit Enable, 6:0 for Delay
input [6:0] Emit_Width, //Emit pulse width
output reg TXP,
output reg TXN
);
reg [6:0] Emit_Counter;
reg [6:0] Delay_Counter;
always @(posedge Transmit_CLK or negedge RX_Gate)
begin
if(~RX_Gate) begin
Emit_Counter <= 7'd0;
Delay_Counter <= 8'd0;
TXP <= 1'b1;
TXN <= 1'b1;
end
else
begin
if(Delay_Counter < EmitDelay[6:0] ) begin
Delay_Counter <= Delay_Counter + 1'b1;
TXP <= 1'b1;
TXN <= 1'b1;
end
else begin
if(~EmitDelay[7]) begin //enble Emit
if(Emit_Counter <Emit_Width)begin // Positive Pulse
TXP <= 1'b1;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else if(Emit_Counter <{Emit_Width,1'b0})begin // Negetive Pulse
TXP <= 1'b0;
TXN <= 1'b1;
Emit_Counter <= Emit_Counter + 1'b1;
end
/*
else if(Emit_Counter <({Emit_Width,1'b0}+Emit_Width))begin // Positive Pulse
TXP <= 1'b1;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else if(Emit_Counter <{Emit_Width,2'b0})begin // Negetive Pulse
TXP <= 1'b0;
TXN <= 1'b1;
Emit_Counter <= Emit_Counter + 1'b1;
end
*/
else if(Emit_Counter <({Emit_Width,2'b0}+Emit_Width))begin //Return to Zero (RTZ)
TXP <= 1'b0;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else begin
TXP <= 1'b1;
TXN <= 1'b1;
end
end
else begin //disable Emit
TXP <= 1'b1;
TXN <= 1'b1;
end
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_iobuf #(
parameter DATA_WIDTH = 1) (
input [(DATA_WIDTH-1):0] dio_t,
input [(DATA_WIDTH-1):0] dio_i,
output [(DATA_WIDTH-1):0] dio_o,
inout [(DATA_WIDTH-1):0] dio_p);
genvar n;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
assign dio_o[n] = dio_p[n];
assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/17/2017 08:13:16 AM
// Design Name:
// Module Name: DATA_CACHE
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DATA_CACHE #(
parameter ADDRESS_WIDTH = 32 ,
parameter DATA_WIDTH = 32 ,
parameter D_CACHE_LW_WIDTH = 3 ,
parameter D_CACHE_SW_WIDTH = 2 ,
parameter L2_BUS_WIDTH = 32 ,
parameter DATA_CACHE_LOAD_NONE = 3'b000 ,
parameter DATA_CACHE_LOAD_B_S = 3'b010 ,
parameter DATA_CACHE_LOAD_B_U = 3'b011 ,
parameter DATA_CACHE_LOAD_H_S = 3'b100 ,
parameter DATA_CACHE_LOAD_H_U = 3'b101 ,
parameter DATA_CACHE_LOAD_W = 3'b110 ,
parameter DATA_CACHE_STORE_NONE = 2'b00 ,
parameter DATA_CACHE_STORE_B = 2'b01 ,
parameter DATA_CACHE_STORE_H = 2'b10 ,
parameter DATA_CACHE_STORE_W = 2'b11 ,
parameter HIGH = 1'b1 ,
parameter LOW = 1'b0
) (
input CLK ,
input [ADDRESS_WIDTH - 1 : 0] DATA_CACHE_READ_ADDRESS ,
input [D_CACHE_LW_WIDTH - 1 : 0] DATA_CACHE_LOAD ,
input [ADDRESS_WIDTH - 1 : 0] DATA_CACHE_WRITE_ADDRESS ,
input [DATA_WIDTH - 1 : 0] DATA_CACHE_WRITE_DATA ,
input [D_CACHE_SW_WIDTH - 1 : 0] DATA_CACHE_STORE ,
output DATA_CACHE_READY ,
output [DATA_WIDTH - 1 : 0] DATA_CACHE_READ_DATA ,
// Write Data From L1 to L2 Cache
input WRITE_TO_L2_READY_DATA ,
output WRITE_TO_L2_VALID_DATA ,
output [ADDRESS_WIDTH - 2 - 1 : 0] WRITE_ADDR_TO_L2_DATA ,
output [L2_BUS_WIDTH - 1 : 0] DATA_TO_L2_DATA ,
output WRITE_CONTROL_TO_L2_DATA ,
input WRITE_COMPLETE_DATA ,
// Read Data From L2 to L1 Cache
input READ_ADDR_TO_L2_READY_DATA ,
output READ_ADDR_TO_L2_VALID_DATA ,
output [ADDRESS_WIDTH - 2 - 1 : 0] READ_ADDR_TO_L2_DATA ,
output DATA_FROM_L2_READY_DATA ,
input DATA_FROM_L2_VALID_DATA ,
input [L2_BUS_WIDTH - 1 : 0] DATA_FROM_L2_DATA
);
//////////////////------ TEST CODE ------//////////////////
reg data_cache_ready_reg ;
reg write_to_l2_valid_data_reg ;
reg [ADDRESS_WIDTH - 2 - 1 : 0] write_addr_to_l2_data_reg ;
reg [DATA_WIDTH - 1 : 0] data_to_l2_data_reg ;
reg write_control_to_l2_data_reg ;
reg read_addr_to_l2_valid_data_reg ;
reg [ADDRESS_WIDTH - 2 - 1 : 0] read_addr_to_l2_data_reg ;
reg [DATA_WIDTH - 1 : 0] data_from_l2_data_reg ;
reg data_from_l2_ready_data_reg ;
initial
begin
data_cache_ready_reg = HIGH ;
write_to_l2_valid_data_reg = LOW ;
write_addr_to_l2_data_reg = 30'b0 ;
data_to_l2_data_reg = 32'b0 ;
write_control_to_l2_data_reg = LOW ;
read_addr_to_l2_valid_data_reg = LOW ;
read_addr_to_l2_data_reg = 30'b0 ;
data_from_l2_data_reg = 32'b0 ;
data_from_l2_ready_data_reg = HIGH ;
end
always@(posedge CLK)
begin
if(DATA_CACHE_STORE == DATA_CACHE_STORE_W)
begin
write_to_l2_valid_data_reg <= HIGH ;
write_addr_to_l2_data_reg <= DATA_CACHE_WRITE_ADDRESS[ADDRESS_WIDTH - 1 : 2] ;
data_to_l2_data_reg <= DATA_CACHE_WRITE_DATA ;
end
else
begin
write_to_l2_valid_data_reg <= LOW ;
write_addr_to_l2_data_reg <= 30'b0 ;
data_to_l2_data_reg <= 32'b0 ;
end
if(DATA_CACHE_LOAD == DATA_CACHE_LOAD_W)
begin
read_addr_to_l2_valid_data_reg <= HIGH ;
read_addr_to_l2_data_reg <= DATA_CACHE_READ_ADDRESS[ADDRESS_WIDTH - 1 : 2] ;
end
else
begin
read_addr_to_l2_valid_data_reg <= LOW ;
read_addr_to_l2_data_reg <= 30'b0 ;
end
if(DATA_FROM_L2_VALID_DATA == HIGH)
begin
data_from_l2_data_reg <= DATA_FROM_L2_DATA ;
end
else
begin
data_from_l2_data_reg <= 32'b0 ;
end
end
//////////////////------ TEST CODE ------//////////////////
assign DATA_CACHE_READY = data_cache_ready_reg ;
assign WRITE_TO_L2_VALID_DATA = write_to_l2_valid_data_reg ;
assign WRITE_ADDR_TO_L2_DATA = write_addr_to_l2_data_reg ;
assign DATA_TO_L2_DATA = data_to_l2_data_reg ;
assign WRITE_CONTROL_TO_L2_DATA = write_control_to_l2_data_reg ;
assign READ_ADDR_TO_L2_VALID_DATA = read_addr_to_l2_valid_data_reg ;
assign READ_ADDR_TO_L2_DATA = read_addr_to_l2_data_reg ;
assign DATA_CACHE_READ_DATA = data_from_l2_data_reg ;
assign DATA_FROM_L2_READY_DATA = data_from_l2_ready_data_reg ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_4_V
`define SKY130_FD_SC_HDLL__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_4_V
|
// ledtest_ARM_MCU_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module ledtest_ARM_MCU_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3 // .hps_io_emac1_inst_RXD3
);
ledtest_ARM_MCU_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3) // .hps_io_emac1_inst_RXD3
);
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_stall_free_sink
#(
parameter integer DATA_WIDTH = 32,
parameter integer PIPELINE_DEPTH = 32,
parameter integer SHARINGII = 1,
parameter integer SCHEDULEII = 1,
parameter integer ALWAYS_THROTTLE = 0
)
(
input logic clock,
input logic resetn,
input logic [DATA_WIDTH-1:0] data_in,
output logic [DATA_WIDTH-1:0] data_out,
input logic input_accepted,
input logic valid_in,
output logic valid_out,
input logic stall_in,
output logic stall_entry,
output logic [SHARINGII-1:0] IIphases,
input logic inc_pipelined_thread,
input logic dec_pipelined_thread
);
reg shift_reg;
reg [DATA_WIDTH-1:0] reg_data_in;
localparam FIFO_DEPTH_LOG2 = CLogB2(PIPELINE_DEPTH);
localparam FIFO_DEPTH = 1 << FIFO_DEPTH_LOG2;
reg [FIFO_DEPTH_LOG2:0] counter;
reg [SHARINGII-1:0] IIshreg;
wire output_accepted;
wire staging_reg_stall;
wire fifo_valid;
wire [DATA_WIDTH-1:0] fifo_data;
wire throttle_pipelined_iterations;
assign stall_entry = counter[FIFO_DEPTH_LOG2] | (!IIshreg[0]) | throttle_pipelined_iterations;
assign output_accepted = fifo_valid & ~staging_reg_stall;
assign IIphases = IIshreg;
generate
if (SHARINGII == 1) begin
assign IIshreg = 1;
end else begin
always @(posedge clock or negedge resetn)
begin
if (!resetn)
begin
IIshreg <= {{(SHARINGII - 1){1'b0}},1'b1};
end
else
begin
IIshreg <= {IIshreg,IIshreg[SHARINGII-1]};
end
end
end
endgenerate
reg[$clog2(SCHEDULEII):0] IIschedcount;
reg[$clog2(SCHEDULEII):0] threads_count;
always @(posedge clock or negedge resetn)
begin
if (!resetn) begin
IIschedcount <= 0;
threads_count <= 0;
end else begin
if (IIshreg[0]) begin
// do not increase the counter if a thread is exiting
// increasing threads_count is already decreasing the window
// increasing IIschedcount ends up accepting the next thread too early
IIschedcount <= ((ALWAYS_THROTTLE == 0 ) && input_accepted && dec_pipelined_thread ) ? IIschedcount : (IIschedcount == (SCHEDULEII - 1) ? 0 : (IIschedcount + 1));
end
if (input_accepted) begin
threads_count <= (ALWAYS_THROTTLE) ? ( inc_pipelined_thread ? 2'b01 : threads_count ) : ( threads_count + inc_pipelined_thread - dec_pipelined_thread );
end
end
end
// allow threads in a window of the II cycles
// this prevents the next iteration from entering too early
assign throttle_pipelined_iterations = (IIschedcount >= (threads_count > 0 ? threads_count : 1));
always @(posedge clock or negedge resetn)
begin
if (!resetn)
begin
shift_reg <= 1'b0;
counter <= {(FIFO_DEPTH_LOG2+1){1'b0}};
reg_data_in <= 'x;
end
else
begin
shift_reg <= valid_in;
counter <= counter + input_accepted - output_accepted;
reg_data_in <= data_in;
end
end
acl_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(FIFO_DEPTH)
)
fifo (
.clock(clock),
.resetn(resetn),
.data_in(reg_data_in),
.data_out(fifo_data),
.valid_in(shift_reg),
.valid_out(fifo_valid),
.stall_in(staging_reg_stall)
);
acl_staging_reg #(
.WIDTH(DATA_WIDTH)
) staging_reg (
.clk(clock),
.reset(~resetn),
.i_data(fifo_data),
.i_valid(fifo_valid),
.o_stall(staging_reg_stall),
.o_data(data_out),
.o_valid(valid_out),
.i_stall(stall_in)
);
//ceil of the log base 2
function integer CLogB2;
input [31:0] Depth;
integer i;
begin
i = Depth;
for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction
endmodule
|
//Defines the top level CPU module
//This CPu is pipelined and has the following pipeline stages:
// 0. Fetch -- Instruction is read from the RAM buffer unless the CPU is executing a multi-cycle instruction.
// In that case, the next op will be 0.
// 1. Data dependency resolve -- All data is copied the appropriate shifter.
// 2. Execute
// 3. Writeback
// 4. (empty stage, used for various memory operations)
//
// As a bit of cover for the quality of this CPU core:
// "Software people design hardware as hardware people write software"
// Take that as you will.
module cpu(
CLK,
MEMD,
MEMRDY,
addr,
memDat,
memWrite,
hlt
);
input CLK;
input [15:0] MEMD;
input MEMRDY;
output [31:0] addr;
output [15:0] memDat;
output memWrite;
output hlt;
reg halt;
assign hlt=halt;
wire clk;
assign clk=CLK&&~halt;
reg [15:0] memOut;
assign memDat=memOut;
reg memW;
assign memWrite=memW;
//This is the operation shifter that will allow the CPU to complete its tasks:
reg [15:0] opShifter[4:0]; //Five stages should be enough for anybody.
wire [6:0] op1;
wire [6:0] op2;
wire [6:0] op3;
wire [6:0] op4;
wire [6:0] op5;
wire [2:0] aSel2;
wire [2:0] aSel3;
wire [2:0] aSel4;
wire [2:0] bSel2;
wire [2:0] bSel3;
wire [2:0] bSel4;
wire [2:0] cSel2;
wire [2:0] cSel3;
wire [2:0] cSel4;
wire [14:0] literalValue;
pipeBreakU pbru(opShifter[0], opShifter[1], opShifter[2], opShifter[3], opShifter[4], op1, op2, op3, op4, op5, aSel2, aSel3, aSel4, bSel2, bSel3, bSel4, cSel2, cSel3, cSel4, literalValue);
reg [14:0] literalValueIntermediary;
wire [4:0] aluOp;
aluOpU aou(op1, op2, op3, op4, op5, aluOp);
reg [7:0] procFlags; //This generates the set of flags used by the processor.
//Declare the CPU's register file:
reg [15:0] registers[7:0]; //Registers are addressed with 3-bit literals.
//Define some wires so that we can keep track of each register:
wire [15:0] r0;
assign r0=registers[0];
wire [15:0] r1;
assign r1=registers[1];
wire [15:0] r2;
assign r2=registers[2];
wire [15:0] r3;
assign r3=registers[3];
wire [15:0] r4;
assign r4=registers[4];
wire [15:0] r5;
assign r5=registers[5];
wire [15:0] r6;
assign r6=registers[6];
wire [15:0] r7;
assign r7=registers[7];
reg [15:0] aShifter[0:3]; //Make it one shorter than the overall op register.
reg [15:0] bShifter[0:3];
//Again, some debugging values:
wire [15:0] as3;
assign as3=aShifter[3];
wire [15:0] as2;
assign as2=aShifter[2];
wire [15:0] as1;
assign as1=aShifter[1];
wire [15:0] as0;
assign as0=aShifter[0];
wire [15:0] bs3;
assign bs3=bShifter[3];
wire [15:0] bs2;
assign bs2=bShifter[2];
wire [15:0] bs1;
assign bs1=bShifter[1];
wire [15:0] bs0;
assign bs0=bShifter[0];
reg [31:0] abCombined;
//Ensure that the computer can actually compute:
wire [7:0] flagsOut; //This is mostly unused.
reg [7:0] flags;
wire [15:0] aluOut;
wire aluShouldWriteBack;
ALU alu(op3[3:0], procFlags, aShifter[0], bShifter[0], flagsOut, aluOut, aluShouldWriteBack);
reg [15:0] intermediateResult;
//Make some wires to break the contents of the flags register out:
wire z, c, o, n;
assign z=flags[0];
assign c=flags[1];
assign o=flags[2];
assign n=flags[3];
//Declare a comparator for the cmp instruction, since manipulating the ALU would be a spot difficult.
wire greater, less, same;
reg g, l, s;
comparator cmp(aShifter[0], bShifter[0], greater, less, same);
//Declare the CPU's program counter:
reg [31:0] pCtr;
//Declare the CPU's stack pointer:
reg [31:0] stackPointer;
//wire [15:0] memOutMux [1:0];
reg [1:0] addrMuxSelector;
wire [31:0] addrMux[2:0];
assign addrMux[0]=pCtr;
assign addrMux[1]=stackPointer;
assign addrMux[2]=abCombined;
assign addr=addrMux[addrMuxSelector];
//This wire blocks the pipeline from attempting to issue more instructions.
wire pipeBlocked;
pipeBlockedU pbu(opShifter[0], opShifter[1], opShifter[2], opShifter[3], opShifter[4], pipeBlocked);
reg [31:0] shadowPc; //Used during calls and rets to keep the registers coherent.
//Set aside a direct path internally so that data stays up to date:
wire [15:0] aDataMux[4:0];
assign aDataMux[0]=registers[aSel2];
assign aDataMux[1]=aluOut;
assign aDataMux[2]=literalValueIntermediary;
assign aDataMux[3]=stackPointer[15:0];
assign aDataMux[4][7:0]=flags;
assign aDataMux[4][15:8]=0;
reg [31:0] instructionsFetched; //This is a performance/debugging variable only.
always@(posedge clk) begin
if(op1==44) begin
//$display("Call instruction at %d", $time);
end
if(op2!=0) begin
instructionsFetched<=instructionsFetched+1;
end
//Shift all of the ops down the pipe:
if(pipeBlocked) begin
opShifter[0]<=0; //Issue a NOP if the pipe's blocked.
end
else begin
opShifter[0]<=MEMD; //Else try to use the current bit of memory information.
pCtr<=pCtr+1;
end
//Ensure that the rest of the pipeline is up to date:
opShifter[1]<=opShifter[0];
opShifter[2]<=opShifter[1];
opShifter[3]<=opShifter[2];
opShifter[4]<=opShifter[3];
if(op3>63&&aSel2==7) begin //Data bypass for LDL; ||op4>63)
aShifter[0]<=aDataMux[2];
end
else if(op3==40&&cSel3==aSel2) begin
aShifter[0]<=aDataMux[3];
end
else if(op3==63&&cSel3==aSel2) begin
aShifter[0]<=aDataMux[4];
end
else if(cSel3==aSel2&&(op3>0&&op3<11)) begin //For int ops.
aShifter[0]<=aDataMux[1];
end
else if(cSel4==aSel2&&(op4>0&&op4<11)) begin //For int ops.
aShifter[0]<=intermediateResult;
end
else if((op4>63) && (aSel2==7)) begin
aShifter[0]<=aDataMux[2];
end
else begin
aShifter[0]<=registers[aSel2];//aDataMux[0];
end
aShifter[1]<=aShifter[0];
aShifter[2]<=aShifter[1];
aShifter[3]<=aShifter[2];
if((op3>63)&&bSel2==7) begin //Data bypass for LDL
bShifter[0]<=aDataMux[2];
end
else if(op3==40&&cSel3==bSel2) begin
bShifter[0]<=aDataMux[3];
end
else if(op3==63&&cSel3==bSel2) begin
bShifter[0]<=aDataMux[4];
end
//TODO: Ensure coherence for LDFLGS instruction.
else if(cSel3==bSel2&&(op3>0&&op3<11)) begin //For int ops.
bShifter[0]<=aDataMux[1];
end
else if(cSel4==bSel2&&(op4>0&&op4<11)) begin //For int ops, since the registers are not yet coherent.
bShifter[0]<=intermediateResult;
end
else if((op4>63) && (bSel2==7)) begin
bShifter[0]<=aDataMux[2];
end
else begin
bShifter[0]<=registers[bSel2];
end
bShifter[1]<=bShifter[0];
bShifter[2]<=bShifter[1];
bShifter[3]<=bShifter[2];
//Handle the writeback stage for normal ops.
//Everything else is handled for me along the normal integer pipeline.
if(op4<11 && op4>0) begin
registers[cSel4]<=intermediateResult;//aluOut;
flags<=flagsOut;
end
if(op3<11 && op3>0) begin
intermediateResult<=aluOut;
//registers[cSel4]<=aluOut;
//flags<=flagsOut;
end
//Handle non-normal operations:
//BEGIN 2ND PIPELINE STAGE LOGIC
if(op2>63) begin //Get the LDL instruction out of the way:
literalValueIntermediary<=literalValue;
end
else if(op2==40) begin //Store stack register
end
else if(op2==41) begin //Load stack register. Loads the stack register from A and B.
//abCombined[31:16]<=aShifter[0];//registers[aSel2];
//abCombined[15:0]<=bShifter[0];//[bSel2];
end
else if(op2==42) begin //Push.
addrMuxSelector<=1;
stackPointer<=stackPointer-1;
//memOut<=aShifter[1];//registers[aSel2];
end
else if(op2==43) begin //Pop
addrMuxSelector<=1;
//stackPointer<=stackPointer+1;
end
else if(op2==44) begin //Call
addrMuxSelector<=1;
//stackPointer<=stackPointer-1;
//pCtr<=pCtr+1; // So that ret doesn't recurse! NOTE: This is unncecessary due to the instruction's timing.
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
end
else if(op2==45) begin //Ret. AAAAUGH!
addrMuxSelector<=1;
//stackPointer<=stackPointer+1;
end
else if(op2==50) begin //CMP.
end
else if(op2>=51&&op2<=54) begin //Jmp instrs.
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
end
else if(op2==60) begin //Load
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
addrMuxSelector<=2;
end
else if(op2==61) begin //Store
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
addrMuxSelector<=2;
memOut<=registers[cSel2];//registers[cSel2];
end
else if(op2==62) begin //Loads flags from the lower 8 bits of register A.
end
else if(op2==63) begin //Stores flags to the lower 8 bits of register A.
end
//BEGIN 3RD PIPELINE STAGE LOGIC
if(op3>63) begin //Execute stage of the LDL instruction. Do nothing! Woo!
//registers[7][14:0]<=literalValueIntermediary;
//registers[7][15]<=0;
end
else if(op3==40) begin //Store stack register
end
else if(op3==41) begin //Load stack register. Loads the stack register from A and B.
end
else if(op3==42) begin //Push.
memW<=1;
memOut<=aShifter[0];
end
else if(op3==43) begin //pop
registers[cSel3]<=MEMD;
end
else if(op3==44) begin //Call
memOut<=pCtr[31:16];
memW<=1;
stackPointer<=stackPointer-1;
end
else if(op3==45) begin //Ret. AAAAUGH!
pCtr[15:0]<=MEMD;
stackPointer<=stackPointer+1;
end
else if(op3==50) begin //CMP.
g<=greater;
l<=less;
s<=same;
end
else if(op3>=51&&op3<=54) begin //Jmp instrs.
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
end
//else if(op3==52) begin //Jump on equal.
//
//end
else if(op3==60) begin //Load
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
addrMuxSelector<=2;
end
else if(op3==61) begin //Store
abCombined[31:16]<=aShifter[0];//registers[aSel2];
abCombined[15:0]<=bShifter[0];//registers[bSel2];
addrMuxSelector<=2;
if(op4>63&&cSel3==7) begin
memOut[14:0]<=literalValueIntermediary;
memOut[15]<=0;
end
else if(cSel4==cSel3) begin //Then it is most likely the product of an ALU action.
if(op4>0&&op4<11) begin
memOut<=intermediateResult;
end
else if(op4==41) begin
memOut<=stackPointer[15:0];
end
else begin //Hope for the best:
memOut<=registers[cSel3];
end
end
else begin
memOut<=registers[cSel3];
end
memW<=1;
end
else if(op3==62) begin //Load flags.
end
else if(op3==63) begin //Stores flags to the lower 8 bits of register A.
end
// BEGIN 4TH PIPELINE STAGE LOGIC
if(op4>63) begin //Writeback stage of the LDL instruction. Lovely!
registers[7][14:0]<=literalValueIntermediary;
registers[7][15]<=1'b0;
end
else if(op4==40) begin //Store stack register
registers[cSel4]<=stackPointer[15:0];
end
else if(op4==41) begin //Load stack register. Loads the stack register from A and B.
stackPointer[31:16]<=aShifter[1];
stackPointer[15:0]<=bShifter[1];
//stackPointer<=abCombined;
end
else if(op4==42) begin //Push
memW<=0;
//stackPointer<=stackPointer-1;
addrMuxSelector<=0;
end
else if(op4==43) begin //Pop
//registers[cSel4]<=MEMD;
stackPointer<=stackPointer+1;
addrMuxSelector<=0;
end
else if(op4==44) begin //Call
memOut<=pCtr[15:0];
stackPointer<=stackPointer-1;
shadowPc[31:16]<=registers[aSel4];
shadowPc[15:0]<=registers[bSel4];
end
else if(op4==45) begin //Ret. AAAAUGH!
pCtr[31:16]<=MEMD;
stackPointer<=stackPointer+1;
end
else if(op4==50) begin //CMP.
flags[7]<=g; //This sort of writeback allows for better debugging.
flags[6]<=l;
flags[5]<=s;
end
else if(op4==59) begin //Halt. Should I even bother?
halt<=1;
end
else if(op4==60) begin //Load
registers[cSel4]<=MEMD;
addrMuxSelector<=0;
end
else if(op4==51) begin //Jmp
//pCtr[31:16]<=//aShifter[2];
//pCtr[15:0]<=//bShifter[2];
pCtr<=abCombined;
end
else if(op4==52) begin //JE
if(s) begin
//pCtr[31:16]<=aShifter[2];//registers[aSel4];//aShifter[1];
//pCtr[15:0]<=bShifter[2];//registers[bSel4];//bShifter[1];
pCtr<=abCombined;
end
end
else if(op4==53) begin //Jump on positive (greater)
if(g) begin
pCtr[31:16]<=aShifter[2];//registers[aSel4];//aShifter[1];
pCtr[15:0]<=bShifter[2];//registers[bSel4];//bShifter[1];
end
end
else if(op4==54) begin //Jump on negative (less)
if(n) begin
pCtr[31:16]<=registers[aSel4];//aShifter[1];
pCtr[15:0]<=registers[bSel4];//bShifter[1];
end
end
else if(op4==61) begin //Store
memW<=0;
addrMuxSelector<=0;
end
else if(op4==62) begin //Load flags.
flags<=aShifter[2][7:0];
end
else if(op4==63) begin //Store flags.
registers[cSel4][7:0]<=flags;
end
// BEGIN 5TH PIPELINE STAGE LOGIC
if(op5==44) begin //Call
//pCtr[31:16]<=registers[cSel4];//Complete the jump
//pCtr[15:0]<=bShifter[2];
pCtr<=shadowPc;
memW<=0; //Stop writing to memory.
addrMuxSelector<=0; //Use the program counter for addressing.
//stackPointer<=stackPointer-1; //3 shifts prevents push from destroying the address.
end
else if(op5==45) begin //Ret. AAAAUGH!
addrMuxSelector<=0;
end
//Jmp placeholder.
end
initial begin
addrMuxSelector<=0;
abCombined<=0;
halt<=0;
pCtr<=0;
stackPointer<=0;
//Assign registers to 0:
registers[0]<=0;
registers[1]<=0;
registers[2]<=0;
registers[3]<=0;
registers[4]<=0;
registers[5]<=0;
registers[6]<=0;
registers[7]<=0;
memW<=0;
opShifter[0]<=0;
opShifter[1]<=0;
opShifter[2]<=0;
opShifter[3]<=0;
opShifter[4]<=0;
instructionsFetched<=0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_FUNCTIONAL_V |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
`include "timescale.v"
module fftTop (clk,reset,wb_clk,wb_stb_i,wb_dat_o,wb_dat_i,wb_ack_o,
wb_adr_i,wb_we_i,wb_cyc_i,wb_sel_i,wb_err_o, wb_rty_o
);
input clk;
input reset;
input wb_clk;
input wb_stb_i;
wire [31:0] rectify_wb_dat_o;
output [31:0] wb_dat_o;
input [31:0] wb_dat_i;
output reg wb_ack_o;
input [31:0] wb_adr_i;
input wb_we_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output wb_err_o;
output wb_rty_o;
reg wb_we_i_reg;
reg wb_cyc_i_reg;
reg wb_stb_i_reg;
reg [31:0] wb_dat_i_reg;
reg [31:0] wb_adr_i_reg, wb_adr_i_reg0;
reg fft_read;
wire fft_done;
reg [31:0] control_reg;
reg wb_rty_o;
reg wb_ack_o_reg;
reg [3:0] wb_sel_i_reg;
always @(posedge wb_clk)
begin
wb_cyc_i_reg <= wb_cyc_i;
wb_stb_i_reg <= wb_stb_i;
wb_we_i_reg <= wb_we_i;
wb_dat_i_reg <= wb_dat_i;
wb_sel_i_reg <= wb_sel_i;
wb_adr_i_reg0 <= wb_adr_i;
wb_adr_i_reg <= {wb_adr_i_reg0[31:4],wb_adr_i_reg0[3] ^ wb_sel_i_reg[3], wb_adr_i_reg0[2] ^ wb_sel_i_reg[2], wb_adr_i_reg0[1] ^ wb_sel_i_reg[1], wb_adr_i_reg0[0] ^ wb_sel_i_reg[0]};
wb_rty_o <= control_reg[1] ^ control_reg[3] ^ control_reg[4] ^ control_reg[6] ^ control_reg[17] ^ control_reg[19] ^ control_reg[23] ^ control_reg[29] ^ control_reg[31];
fft_read <= !wb_stb_i_reg;
end
always @(posedge wb_clk or posedge reset)
begin
if(reset==1)
begin
wb_ack_o_reg <= 0;
control_reg <= 32'h0;
end
else
begin
if(fft_done)
begin
control_reg[1] <= 1'b1;
end
if(wb_stb_i_reg && wb_cyc_i_reg && wb_we_i_reg && ~wb_ack_o_reg)
begin
wb_ack_o_reg <= 1;
case(wb_adr_i_reg[31:0])
32'h0:
begin
//Writing control register lower
control_reg[31:0] <= wb_dat_i_reg;
end
endcase
end
else if(wb_stb_i_reg && wb_cyc_i_reg && ~wb_we_i_reg && ~wb_ack_o_reg)
begin
wb_ack_o_reg <= 1;
case(wb_adr_i_reg[31:0])
32'h0:
begin
control_reg[1] <= 1'b0;
end
endcase
end
else
begin
wb_ack_o_reg <= 0;
control_reg[0] <= 1'b0;
end
end
end
bft fftInst (
.wbClk(clk),
.bftClk(clk),
.reset(reset),
.wbDataForInput(fft_read),
.wbInputData(wb_dat_i_reg),
.wbWriteOut(!wb_we_i_reg),
.wbDataForOutput(fft_done),
.wbOutputData(rectify_wb_dat_o),
.error(wb_err_o)
);
always @(posedge wb_clk)
wb_ack_o <= wb_ack_o_reg;
assign wb_dat_o = rectify_wb_dat_o;
endmodule
|
`timescale 1ns/1ns
module mii_seq
(input c,
input start,
output mdc,
inout mdio);
wire [4:0] mii_phyad;
wire [4:0] mii_addr;
wire [15:0] mii_wdata;
wire [15:0] mii_rdata;
wire mii_req, mii_we, mii_ack;
mii_mgmt #(.CLK_MHZ(125), .MDC_KHZ(500)) mii
(.clk(c), .phyad(mii_phyad), .addr(mii_addr),
.wdata(mii_wdata), .rdata(mii_rdata),
.req(mii_req), .we(mii_we), .ack(mii_ack),
.mdc(mdc), .mdio(mdio));
// ROM for the MII sequence
wire [3:0] seq_addr;
reg [31:0] seq_q;
always @(posedge c) begin
case (seq_addr)
4'h0: seq_q = 32'h8009_1c00; // disable 1g speed
4'h1: seq_q = 32'h8109_1c00; // disable 1g speed
4'h2: seq_q = 32'h8000_0340; // force 100M speed
4'h3: seq_q = 32'h8100_0340; // force 100M speed
//4'h4: seq_q = 32'h8000_8140; // software reset
//4'h5: seq_q = 32'h8100_8140; // software reset
default: seq_q = 32'h0;
endcase
end
localparam ST_IDLE = 3'h0;
localparam ST_TXRX = 3'h1;
localparam ST_CHILL = 3'h2;
localparam SW=3, CW=4;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire [15:0] chill_cnt;
always @* begin
case (state)
ST_IDLE:
if (start) ctrl = { ST_TXRX , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
ST_TXRX:
if (mii_ack) ctrl = { ST_CHILL, 4'b0000 };
else ctrl = { ST_TXRX , 4'b0000 };
ST_CHILL:
if (chill_cnt == 16'h1000)
if (seq_addr == 4'h3) ctrl = { ST_IDLE , 4'b0000 };
else ctrl = { ST_TXRX , 4'b0001 };
else ctrl = { ST_CHILL, 4'b0000 };
default: ctrl = { ST_IDLE, 4'b0000 };
endcase
end
r #(16) chill_cnt_r
(.c(c), .rst(state == ST_TXRX), .d(chill_cnt + 1'b1), .en(1'b1), .q(chill_cnt));
r #(4) seq_addr_r
(.c(c), .rst(state == ST_IDLE), .en(ctrl[0]),
.d(seq_addr + 1'b1), .q(seq_addr));
assign mii_req = state == ST_TXRX;
assign mii_we = seq_q[31];
assign mii_phyad = seq_q[28:24];
assign mii_wdata = seq_q[15:0];
assign mii_addr = seq_q[20:16];
endmodule
`ifdef test_mii_seq
module mii_seq_tb();
wire c;
sim_clk #(125) clk_125(c);
reg start;
wire mdc, mdio;
mii_seq dut(.*);
fake_mii mii_inst(.*);
initial begin
$dumpfile("mii_seq.lxt");
$dumpvars();
start = 0;
#100;
wait(~c);
wait(c);
start <= 1;
wait(~c);
wait(c);
start <= 0;
#1000000;
$finish();
end
endmodule
`endif
|
//==================================================================================================
// Filename : CORDIC_FSM_v3.v
// Created On : 2016-10-03 15:59:21
// Last Modified : 2016-10-04 11:23:26
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : CORDIC's FSM Unit
//
//
//==================================================================================================
`timescale 1ns / 1ps
module CORDIC_FSM_v3
(
//Input Signals
input wire clk, // Reloj del sitema.
input wire reset, // Reset del sitema.
input wire beg_FSM_CORDIC, // Señal de inicio de la maquina de estados.
input wire ACK_FSM_CORDIC, // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
input wire exception,
input wire max_tick_iter, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
input wire max_tick_var, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
input wire enab_dff_z,
//Output Signals
output reg reset_reg_cordic,
output reg ready_CORDIC, // Señal que indica que el calculo CORDIC se ha terminado.
output reg beg_add_subt, // Señal que indica al modulo de suma/resta que inicie su operacion.
output reg enab_cont_iter, // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
output reg enab_cont_var, // Señales de habilitacion y carga, respectivamente, en el contador de variables.
output reg enab_RB1, enab_RB2, enab_RB3,
output reg enab_d_ff5_data_out
);
//symbolic state declaration
localparam [3:0] est0 = 0,
est1 = 1,
est2 = 2,
est3 = 3,
est4 = 4,
est5 = 5,
est6 = 6,
est7 = 7;
//signal declaration
reg [3:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge reset)
begin
if(reset) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
reset_reg_cordic = 0;
enab_RB1 = 0;
enab_RB2 = 0;
enab_RB3 = 0;
enab_cont_var = 0;
enab_cont_iter = 0;
enab_d_ff5_data_out = 0;
ready_CORDIC = 0;
beg_add_subt = 0;
case(state_reg)
est0:
begin
reset_reg_cordic = 1'b1;
if(beg_FSM_CORDIC) begin
state_next = est1;
end else begin
state_next = est0;
end
end
est1:
begin
enab_RB1 = 1'b1;
state_next = est2;
end
est2:
begin
enab_RB2 = 1'b1;
if(exception) begin
state_next = est0;
end else begin
state_next = est3;
end
end
est3:
begin
enab_RB3 = 1'b1;
state_next = est4;
end
est4:
begin
enab_cont_var = 1'b1; //cont_var++
beg_add_subt = 1'b1;
if (max_tick_var) begin
state_next = est5;
end else begin
state_next = est4;
end
end
est5:
begin
beg_add_subt = 1'b1;
if (enab_dff_z) begin
state_next = est6;
end else begin
state_next = est5;
end
end
est6:
begin
enab_cont_iter = 1'b1; //cont_iter++
enab_cont_var = 1'b1; //Reset cont
if (max_tick_iter) begin
state_next = est7; //Es la ultima iteracion, por lo tanto, seguimos a la siguiente etapa
enab_d_ff5_data_out = 1;
end else begin
state_next = est2; //Seguir las iteraciones
//
end
end
est7:
begin
ready_CORDIC = 1'b1;
enab_d_ff5_data_out = 1'b1;
if(ACK_FSM_CORDIC) begin
state_next = est0;
end else begin
state_next = est7;
end
end
default :
begin
state_next = est0;
end
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:00:24 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210,
n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221,
n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232,
n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254,
n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276,
n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287,
n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298,
n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309,
n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320,
n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331,
n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342,
n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353,
n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364,
n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378;
XNOR2X1TS U35 ( .A(n242), .B(n241), .Y(res[23]) );
XNOR2X1TS U36 ( .A(n248), .B(n247), .Y(res[22]) );
NAND2X1TS U37 ( .A(n146), .B(n201), .Y(n202) );
NAND2X1TS U38 ( .A(n150), .B(n207), .Y(n208) );
NAND2X1TS U39 ( .A(n240), .B(n239), .Y(n241) );
NAND2X1TS U40 ( .A(n266), .B(n265), .Y(n267) );
NAND2X1TS U41 ( .A(n251), .B(n250), .Y(n252) );
NAND2X1TS U42 ( .A(n246), .B(n245), .Y(n247) );
NAND2X1TS U43 ( .A(n193), .B(n192), .Y(n194) );
NAND2X1TS U44 ( .A(n185), .B(n188), .Y(n187) );
NAND2XLTS U45 ( .A(n234), .B(n233), .Y(n235) );
NAND2XLTS U46 ( .A(n224), .B(n223), .Y(n225) );
BUFX6TS U47 ( .A(n215), .Y(n216) );
NAND2X2TS U48 ( .A(n177), .B(in1[31]), .Y(n182) );
OAI21X1TS U49 ( .A0(n239), .A1(n232), .B0(n233), .Y(n218) );
NAND2X4TS U50 ( .A(n215), .B(n122), .Y(n137) );
OR2X6TS U51 ( .A(n161), .B(in1[27]), .Y(n7) );
INVX6TS U52 ( .A(n160), .Y(n163) );
INVX2TS U53 ( .A(n212), .Y(n162) );
NAND2X4TS U54 ( .A(n141), .B(in1[26]), .Y(n160) );
NAND2X1TS U55 ( .A(n342), .B(in1[5]), .Y(n370) );
NOR2X6TS U56 ( .A(n8), .B(n126), .Y(n127) );
OAI21X2TS U57 ( .A0(n222), .A1(n233), .B0(n223), .Y(n132) );
NAND2X2TS U58 ( .A(n165), .B(in1[29]), .Y(n201) );
NAND2X2TS U59 ( .A(n164), .B(in1[28]), .Y(n207) );
NOR2X4TS U60 ( .A(n222), .B(n232), .Y(n133) );
MX2X2TS U61 ( .A(in2[28]), .B(n149), .S0(n175), .Y(n164) );
NAND2BX2TS U62 ( .AN(in2[29]), .B(n158), .Y(n173) );
NAND2X2TS U63 ( .A(n130), .B(in1[24]), .Y(n233) );
NAND2X1TS U64 ( .A(in1[0]), .B(in2[0]), .Y(n377) );
NOR2X6TS U65 ( .A(n125), .B(in1[21]), .Y(n249) );
NAND2X1TS U66 ( .A(n327), .B(in1[4]), .Y(n330) );
NAND2X1TS U67 ( .A(n154), .B(in2[27]), .Y(n155) );
NOR2X4TS U68 ( .A(n130), .B(in1[24]), .Y(n232) );
MX2X1TS U69 ( .A(in2[15]), .B(n81), .S0(n175), .Y(n83) );
MX2X2TS U70 ( .A(in2[18]), .B(n5), .S0(n339), .Y(n96) );
NAND2X2TS U71 ( .A(n138), .B(n144), .Y(n139) );
NOR3X4TS U72 ( .A(n152), .B(in2[28]), .C(n147), .Y(n158) );
NOR2X4TS U73 ( .A(n152), .B(n151), .Y(n153) );
MXI2X4TS U74 ( .A(n116), .B(n115), .S0(n339), .Y(n124) );
INVX2TS U75 ( .A(in2[21]), .Y(n3) );
NAND2X1TS U76 ( .A(n72), .B(in1[14]), .Y(n292) );
NAND2X2TS U77 ( .A(n54), .B(in1[10]), .Y(n311) );
CLKXOR2X2TS U78 ( .A(n321), .B(in2[3]), .Y(n322) );
XNOR2X2TS U79 ( .A(n105), .B(in2[23]), .Y(n106) );
XNOR2X2TS U80 ( .A(n86), .B(in2[19]), .Y(n87) );
NAND2X1TS U81 ( .A(n144), .B(n143), .Y(n151) );
NOR2X2TS U82 ( .A(n45), .B(n361), .Y(n48) );
NOR2X2TS U83 ( .A(n118), .B(n117), .Y(n119) );
NOR2X4TS U84 ( .A(n152), .B(in2[24]), .Y(n110) );
MXI2X2TS U85 ( .A(n67), .B(n62), .S0(n317), .Y(n64) );
INVX2TS U86 ( .A(n109), .Y(n89) );
NOR2X1TS U87 ( .A(n350), .B(in1[7]), .Y(n43) );
NOR2X2TS U88 ( .A(in2[25]), .B(in2[24]), .Y(n144) );
BUFX4TS U89 ( .A(add_sub), .Y(n175) );
NOR4BX2TS U90 ( .AN(n56), .B(n51), .C(n50), .D(n49), .Y(n52) );
OR2X2TS U91 ( .A(in2[21]), .B(in2[20]), .Y(n117) );
NOR2X2TS U92 ( .A(in2[13]), .B(in2[12]), .Y(n78) );
INVX4TS U93 ( .A(in2[8]), .Y(n21) );
NOR2X1TS U94 ( .A(in2[19]), .B(in2[18]), .Y(n102) );
NAND2X1TS U95 ( .A(n103), .B(n102), .Y(n107) );
INVX2TS U96 ( .A(n175), .Y(n154) );
CLKMX2X2TS U97 ( .A(in2[11]), .B(n59), .S0(n175), .Y(n63) );
BUFX8TS U98 ( .A(add_sub), .Y(n317) );
OR2X1TS U99 ( .A(n350), .B(in1[7]), .Y(n354) );
NAND2X2TS U100 ( .A(n63), .B(in1[11]), .Y(n306) );
NAND2X2TS U101 ( .A(n94), .B(in1[16]), .Y(n283) );
NAND2X1TS U102 ( .A(n196), .B(n150), .Y(n200) );
OR2X1TS U103 ( .A(in1[0]), .B(in2[0]), .Y(n374) );
OAI21XLTS U104 ( .A0(n309), .A1(n305), .B0(n306), .Y(n304) );
INVX2TS U105 ( .A(n183), .Y(n178) );
INVX4TS U106 ( .A(n245), .Y(n128) );
INVX2TS U107 ( .A(n264), .Y(n266) );
INVX2TS U108 ( .A(n232), .Y(n234) );
CLKAND2X2TS U109 ( .A(n374), .B(n377), .Y(res[0]) );
NAND2X2TS U110 ( .A(n178), .B(n182), .Y(n179) );
XNOR2X2TS U111 ( .A(n110), .B(in2[25]), .Y(n111) );
OAI21X2TS U112 ( .A0(n25), .A1(n24), .B0(n23), .Y(n44) );
INVX12TS U113 ( .A(in2[4]), .Y(n336) );
BUFX12TS U114 ( .A(add_sub), .Y(n339) );
NOR2X4TS U115 ( .A(n183), .B(n181), .Y(n185) );
INVX4TS U116 ( .A(n238), .Y(n227) );
INVX2TS U117 ( .A(n243), .Y(n244) );
NAND2X4TS U118 ( .A(n146), .B(n150), .Y(n168) );
INVX4TS U119 ( .A(n207), .Y(n197) );
INVX2TS U120 ( .A(n222), .Y(n224) );
OR2X6TS U121 ( .A(n164), .B(in1[28]), .Y(n150) );
NAND2X4TS U122 ( .A(n129), .B(in1[23]), .Y(n239) );
OR2X6TS U123 ( .A(n165), .B(in1[29]), .Y(n146) );
NOR2X4TS U124 ( .A(n131), .B(in1[25]), .Y(n222) );
MX2X2TS U125 ( .A(in2[25]), .B(n111), .S0(n175), .Y(n131) );
XOR2X1TS U126 ( .A(n349), .B(n346), .Y(res[6]) );
NOR2X2TS U127 ( .A(n173), .B(in2[30]), .Y(n174) );
NAND2X2TS U128 ( .A(n296), .B(n6), .Y(n76) );
XOR2X2TS U129 ( .A(n119), .B(in2[22]), .Y(n120) );
NOR2X4TS U130 ( .A(n89), .B(in2[16]), .Y(n90) );
OR2X2TS U131 ( .A(n83), .B(in1[15]), .Y(n82) );
MX2X2TS U132 ( .A(in2[13]), .B(n69), .S0(add_sub), .Y(n71) );
NOR2X4TS U133 ( .A(n44), .B(in1[8]), .Y(n361) );
NAND2X2TS U134 ( .A(n188), .B(n193), .Y(n172) );
INVX12TS U135 ( .A(n216), .Y(n258) );
NOR2X4TS U136 ( .A(n168), .B(n204), .Y(n188) );
NAND2X6TS U137 ( .A(n243), .B(n246), .Y(n238) );
NAND2X4TS U138 ( .A(n99), .B(n260), .Y(n101) );
INVX2TS U139 ( .A(n192), .Y(n170) );
INVX4TS U140 ( .A(n126), .Y(n246) );
XOR2X1TS U141 ( .A(n365), .B(n364), .Y(res[8]) );
MX2X2TS U142 ( .A(in2[30]), .B(n159), .S0(n175), .Y(n169) );
XOR2X1TS U143 ( .A(n298), .B(n297), .Y(res[13]) );
MX2X2TS U144 ( .A(in2[17]), .B(n91), .S0(add_sub), .Y(n95) );
XOR2X1TS U145 ( .A(n309), .B(n308), .Y(res[11]) );
XNOR2X2TS U146 ( .A(n90), .B(in2[17]), .Y(n91) );
XOR2X1TS U147 ( .A(n329), .B(n328), .Y(res[4]) );
XOR2X1TS U148 ( .A(n369), .B(n368), .Y(res[3]) );
NAND2X2TS U149 ( .A(n64), .B(in1[12]), .Y(n301) );
OR2X2TS U150 ( .A(n342), .B(in1[5]), .Y(n371) );
OR2X2TS U151 ( .A(n151), .B(in2[27]), .Y(n147) );
AND2X2TS U152 ( .A(n49), .B(n317), .Y(n34) );
NOR2X2TS U153 ( .A(in2[17]), .B(in2[16]), .Y(n103) );
INVX4TS U154 ( .A(in2[6]), .Y(n20) );
NOR2X4TS U155 ( .A(n54), .B(in1[10]), .Y(n310) );
NOR4X2TS U156 ( .A(n19), .B(n36), .C(in2[2]), .D(in2[0]), .Y(n25) );
NAND4X1TS U157 ( .A(n39), .B(n38), .C(in2[6]), .D(n336), .Y(n40) );
NAND2X2TS U158 ( .A(n83), .B(in1[15]), .Y(n288) );
MXI2X8TS U159 ( .A(n4), .B(n3), .S0(n154), .Y(n125) );
XOR2X4TS U160 ( .A(n114), .B(in2[21]), .Y(n4) );
XNOR2X1TS U161 ( .A(n236), .B(n235), .Y(res[24]) );
AOI21X4TS U162 ( .A0(n229), .A1(n240), .B0(n228), .Y(n230) );
OAI21X2TS U163 ( .A0(n365), .A1(n361), .B0(n362), .Y(n360) );
OAI21X2TS U164 ( .A0(n45), .A1(n362), .B0(n357), .Y(n46) );
NAND2X4TS U165 ( .A(n44), .B(in1[8]), .Y(n362) );
NOR2X4TS U166 ( .A(n277), .B(n282), .Y(n260) );
OAI21X4TS U167 ( .A0(n277), .A1(n283), .B0(n278), .Y(n261) );
INVX4TS U168 ( .A(n217), .Y(n240) );
NOR2X4TS U169 ( .A(in2[6]), .B(in2[4]), .Y(n27) );
XNOR2X1TS U170 ( .A(n281), .B(n280), .Y(res[17]) );
NAND2X4TS U171 ( .A(n336), .B(n21), .Y(n12) );
OAI21X1TS U172 ( .A0(n291), .A1(n298), .B0(n295), .Y(n294) );
XNOR2X1TS U173 ( .A(n275), .B(n274), .Y(res[18]) );
NOR2X4TS U174 ( .A(n64), .B(in1[12]), .Y(n300) );
BUFX3TS U175 ( .A(n259), .Y(n276) );
OAI21X2TS U176 ( .A0(n43), .A1(n347), .B0(n352), .Y(n47) );
NAND2X8TS U177 ( .A(n109), .B(n108), .Y(n152) );
OAI21X4TS U178 ( .A0(n258), .A1(n231), .B0(n230), .Y(n236) );
OAI21X4TS U179 ( .A0(n211), .A1(n172), .B0(n171), .Y(n180) );
XOR2X2TS U180 ( .A(n109), .B(in2[16]), .Y(n92) );
XOR2X2TS U181 ( .A(n88), .B(in2[18]), .Y(n5) );
XOR2X2TS U182 ( .A(n173), .B(in2[30]), .Y(n159) );
AOI21X4TS U183 ( .A0(n189), .A1(n193), .B0(n170), .Y(n171) );
INVX2TS U184 ( .A(n188), .Y(n191) );
MXI2X4TS U185 ( .A(n113), .B(n112), .S0(n339), .Y(n130) );
OAI21X2TS U186 ( .A0(n183), .A1(n192), .B0(n182), .Y(n184) );
NOR2X6TS U187 ( .A(n177), .B(in1[31]), .Y(n183) );
MX2X4TS U188 ( .A(in2[31]), .B(n176), .S0(n175), .Y(n177) );
NAND2X4TS U189 ( .A(n124), .B(in1[20]), .Y(n255) );
NOR2X4TS U190 ( .A(n118), .B(in2[20]), .Y(n114) );
XNOR2X4TS U191 ( .A(n118), .B(in2[20]), .Y(n115) );
OAI31X4TS U192 ( .A0(n37), .A1(n36), .A2(in2[0]), .B0(n35), .Y(n41) );
OAI21X4TS U193 ( .A0(n258), .A1(n238), .B0(n237), .Y(n242) );
NOR2X2TS U194 ( .A(n88), .B(in2[18]), .Y(n86) );
OAI21X4TS U195 ( .A0(n264), .A1(n272), .B0(n265), .Y(n98) );
NAND2X4TS U196 ( .A(n97), .B(in1[19]), .Y(n265) );
NOR2X8TS U197 ( .A(n97), .B(in1[19]), .Y(n264) );
MX2X4TS U198 ( .A(in2[19]), .B(n87), .S0(add_sub), .Y(n97) );
XNOR2X4TS U199 ( .A(n139), .B(in2[26]), .Y(n140) );
MXI2X8TS U200 ( .A(n143), .B(n140), .S0(n339), .Y(n141) );
MXI2X4TS U201 ( .A(n121), .B(n120), .S0(n339), .Y(n123) );
NAND2X8TS U202 ( .A(n79), .B(n78), .Y(n85) );
XOR2X1TS U203 ( .A(n258), .B(n257), .Y(res[20]) );
INVX2TS U204 ( .A(n288), .Y(n84) );
NAND3XLTS U205 ( .A(n320), .B(n317), .C(n29), .Y(n30) );
MXI2X2TS U206 ( .A(n93), .B(n92), .S0(n339), .Y(n94) );
NOR2X4TS U207 ( .A(n129), .B(in1[23]), .Y(n217) );
INVX2TS U208 ( .A(n152), .Y(n138) );
NAND2X4TS U209 ( .A(n344), .B(in1[6]), .Y(n347) );
NOR2X1TS U210 ( .A(n344), .B(in1[6]), .Y(n348) );
NOR2BX1TS U211 ( .AN(n15), .B(n14), .Y(n16) );
NAND2X2TS U212 ( .A(in1[9]), .B(n356), .Y(n357) );
NOR2X4TS U213 ( .A(n95), .B(in1[17]), .Y(n277) );
NOR2X2TS U214 ( .A(n94), .B(in1[16]), .Y(n282) );
NAND2X2TS U215 ( .A(n95), .B(in1[17]), .Y(n278) );
NOR2X4TS U216 ( .A(n96), .B(in1[18]), .Y(n271) );
INVX2TS U217 ( .A(n261), .Y(n269) );
INVX2TS U218 ( .A(n260), .Y(n270) );
NAND2X2TS U219 ( .A(n96), .B(in1[18]), .Y(n272) );
INVX4TS U220 ( .A(n276), .Y(n286) );
INVX2TS U221 ( .A(n210), .Y(n157) );
NOR2X4TS U222 ( .A(n141), .B(in1[26]), .Y(n210) );
NOR2X4TS U223 ( .A(n135), .B(n238), .Y(n122) );
NOR2X4TS U224 ( .A(in2[6]), .B(in2[5]), .Y(n11) );
NAND2X1TS U225 ( .A(n319), .B(n20), .Y(n36) );
NAND3XLTS U226 ( .A(n323), .B(n29), .C(n21), .Y(n19) );
NOR2X4TS U227 ( .A(in2[8]), .B(in2[9]), .Y(n56) );
INVX2TS U228 ( .A(in2[10]), .Y(n55) );
NAND3X1TS U229 ( .A(n12), .B(add_sub), .C(n10), .Y(n15) );
NOR2X4TS U230 ( .A(n356), .B(in1[9]), .Y(n45) );
INVX2TS U231 ( .A(n295), .Y(n74) );
NAND3XLTS U232 ( .A(n79), .B(n78), .C(n77), .Y(n80) );
NOR2X4TS U233 ( .A(n123), .B(in1[22]), .Y(n126) );
INVX2TS U234 ( .A(n239), .Y(n228) );
INVX2TS U235 ( .A(n237), .Y(n229) );
NAND2X4TS U236 ( .A(n240), .B(n133), .Y(n135) );
NOR2X4TS U237 ( .A(n63), .B(in1[11]), .Y(n305) );
INVX2TS U238 ( .A(n299), .Y(n309) );
INVX2TS U239 ( .A(n291), .Y(n296) );
NOR2X2TS U240 ( .A(n71), .B(in1[13]), .Y(n291) );
NAND2X2TS U241 ( .A(n71), .B(in1[13]), .Y(n295) );
CLKBUFX2TS U242 ( .A(n290), .Y(n298) );
OAI21X1TS U243 ( .A0(n269), .A1(n271), .B0(n272), .Y(n262) );
NOR2X1TS U244 ( .A(n270), .B(n271), .Y(n263) );
NOR2X2TS U245 ( .A(n124), .B(in1[20]), .Y(n254) );
NAND2X2TS U246 ( .A(n123), .B(in1[22]), .Y(n245) );
NAND2X1TS U247 ( .A(n227), .B(n240), .Y(n231) );
NAND2X1TS U248 ( .A(n219), .B(n227), .Y(n221) );
NAND2X2TS U249 ( .A(n131), .B(in1[25]), .Y(n223) );
NAND2X2TS U250 ( .A(n169), .B(in1[30]), .Y(n192) );
INVX2TS U251 ( .A(n181), .Y(n193) );
NOR2X4TS U252 ( .A(n169), .B(in1[30]), .Y(n181) );
INVX2TS U253 ( .A(n201), .Y(n166) );
NAND2X1TS U254 ( .A(n354), .B(n352), .Y(n351) );
NAND2X1TS U255 ( .A(n358), .B(n357), .Y(n359) );
OR2X1TS U256 ( .A(n356), .B(in1[9]), .Y(n358) );
XOR2XLTS U257 ( .A(n314), .B(n313), .Y(res[10]) );
INVX2TS U258 ( .A(n310), .Y(n312) );
NAND2X1TS U259 ( .A(n307), .B(n306), .Y(n308) );
INVX2TS U260 ( .A(n305), .Y(n307) );
XNOR2X1TS U261 ( .A(n304), .B(n303), .Y(res[12]) );
NAND2X1TS U262 ( .A(n302), .B(n301), .Y(n303) );
INVX2TS U263 ( .A(n300), .Y(n302) );
NAND2X1TS U264 ( .A(n296), .B(n295), .Y(n297) );
XNOR2X1TS U265 ( .A(n294), .B(n293), .Y(res[14]) );
NAND2X1TS U266 ( .A(n292), .B(n6), .Y(n293) );
XNOR2X1TS U267 ( .A(n287), .B(n289), .Y(res[15]) );
NAND2X1TS U268 ( .A(n82), .B(n288), .Y(n289) );
NAND2X1TS U269 ( .A(n284), .B(n283), .Y(n285) );
INVX2TS U270 ( .A(n282), .Y(n284) );
NAND2X1TS U271 ( .A(n279), .B(n278), .Y(n280) );
OAI21X1TS U272 ( .A0(n282), .A1(n276), .B0(n283), .Y(n281) );
OAI21X1TS U273 ( .A0(n270), .A1(n276), .B0(n269), .Y(n275) );
INVX2TS U274 ( .A(n271), .Y(n273) );
NAND2X1TS U275 ( .A(n256), .B(n255), .Y(n257) );
INVX2TS U276 ( .A(n254), .Y(n256) );
NAND2X1TS U277 ( .A(n157), .B(n160), .Y(n142) );
NAND2X1TS U278 ( .A(n7), .B(n212), .Y(n213) );
XNOR2X2TS U279 ( .A(n209), .B(n208), .Y(res[28]) );
AOI21X4TS U280 ( .A0(n48), .A1(n47), .B0(n46), .Y(n313) );
OR2X2TS U281 ( .A(n72), .B(in1[14]), .Y(n6) );
NOR2X2TS U282 ( .A(n305), .B(n300), .Y(n66) );
XOR2X2TS U283 ( .A(n268), .B(n267), .Y(res[19]) );
NOR2X4TS U284 ( .A(n249), .B(n254), .Y(n243) );
NAND2X4TS U285 ( .A(n161), .B(in1[27]), .Y(n212) );
AOI21X2TS U286 ( .A0(n189), .A1(n185), .B0(n184), .Y(n186) );
INVX2TS U287 ( .A(n189), .Y(n190) );
NAND2X4TS U288 ( .A(n125), .B(in1[21]), .Y(n250) );
NOR4X1TS U289 ( .A(n13), .B(n37), .C(n28), .D(n12), .Y(n14) );
INVX4TS U290 ( .A(n205), .Y(n198) );
XNOR2X1TS U291 ( .A(n337), .B(n336), .Y(n326) );
NAND2X4TS U292 ( .A(n109), .B(n104), .Y(n118) );
NAND2X2TS U293 ( .A(n109), .B(n103), .Y(n88) );
MXI2X4TS U294 ( .A(n323), .B(n322), .S0(n339), .Y(n324) );
NAND2X2TS U295 ( .A(n7), .B(n157), .Y(n204) );
INVX2TS U296 ( .A(n204), .Y(n196) );
OA21X4TS U297 ( .A0(n249), .A1(n255), .B0(n250), .Y(n8) );
NAND3X1TS U298 ( .A(n11), .B(in2[9]), .C(n29), .Y(n13) );
NOR3X4TS U299 ( .A(n118), .B(in2[22]), .C(n117), .Y(n105) );
CLKINVX6TS U300 ( .A(in2[5]), .Y(n341) );
INVX2TS U301 ( .A(n292), .Y(n73) );
NOR2X2TS U302 ( .A(n232), .B(n217), .Y(n219) );
NAND2X2TS U303 ( .A(n350), .B(in1[7]), .Y(n352) );
INVX2TS U304 ( .A(n277), .Y(n279) );
INVX2TS U305 ( .A(n249), .Y(n251) );
AOI21X1TS U306 ( .A0(n198), .A1(n150), .B0(n197), .Y(n199) );
NAND2X1TS U307 ( .A(n312), .B(n311), .Y(n314) );
NAND2X1TS U308 ( .A(n273), .B(n272), .Y(n274) );
OR2X8TS U309 ( .A(in2[3]), .B(in2[2]), .Y(n37) );
OR2X8TS U310 ( .A(in2[1]), .B(in2[0]), .Y(n28) );
NOR2X8TS U311 ( .A(n37), .B(n28), .Y(n337) );
INVX2TS U312 ( .A(n337), .Y(n51) );
INVX2TS U313 ( .A(n11), .Y(n9) );
NOR4X2TS U314 ( .A(n51), .B(in2[9]), .C(in2[7]), .D(n9), .Y(n18) );
XNOR2X1TS U315 ( .A(n317), .B(in2[9]), .Y(n17) );
INVX2TS U316 ( .A(in2[9]), .Y(n10) );
CLKINVX6TS U317 ( .A(in2[7]), .Y(n29) );
OAI21X4TS U318 ( .A0(n18), .A1(n17), .B0(n16), .Y(n356) );
INVX2TS U319 ( .A(in2[3]), .Y(n323) );
INVX2TS U320 ( .A(in2[1]), .Y(n319) );
XOR2X1TS U321 ( .A(n21), .B(n317), .Y(n24) );
NAND2X4TS U322 ( .A(n341), .B(n336), .Y(n49) );
NAND2X4TS U323 ( .A(n29), .B(n20), .Y(n50) );
NOR2X8TS U324 ( .A(n49), .B(n50), .Y(n57) );
NOR3X1TS U325 ( .A(n37), .B(n28), .C(n21), .Y(n22) );
AOI22X1TS U326 ( .A0(n57), .A1(n22), .B0(n34), .B1(n21), .Y(n23) );
INVX2TS U327 ( .A(n27), .Y(n26) );
NOR4X1TS U328 ( .A(in2[7]), .B(n26), .C(in2[5]), .D(n37), .Y(n33) );
XOR2X1TS U329 ( .A(n29), .B(n317), .Y(n32) );
NAND4X1TS U330 ( .A(n341), .B(in2[7]), .C(n27), .D(n337), .Y(n31) );
BUFX3TS U331 ( .A(n28), .Y(n320) );
OAI211X4TS U332 ( .A0(n33), .A1(n32), .B0(n31), .C0(n30), .Y(n350) );
INVX2TS U333 ( .A(n34), .Y(n42) );
XOR2X1TS U334 ( .A(n317), .B(in2[6]), .Y(n35) );
INVX2TS U335 ( .A(n320), .Y(n39) );
NOR2X1TS U336 ( .A(n37), .B(in2[5]), .Y(n38) );
OAI211X4TS U337 ( .A0(in2[6]), .A1(n42), .B0(n41), .C0(n40), .Y(n344) );
XOR2X1TS U338 ( .A(n52), .B(in2[10]), .Y(n53) );
MXI2X4TS U339 ( .A(n55), .B(n53), .S0(n317), .Y(n54) );
OAI21X4TS U340 ( .A0(n313), .A1(n310), .B0(n311), .Y(n299) );
NAND2X2TS U341 ( .A(n56), .B(n55), .Y(n60) );
NAND2X8TS U342 ( .A(n337), .B(n57), .Y(n61) );
NOR2X1TS U343 ( .A(n60), .B(n61), .Y(n58) );
XNOR2X1TS U344 ( .A(n58), .B(in2[11]), .Y(n59) );
INVX2TS U345 ( .A(in2[12]), .Y(n67) );
NOR3X8TS U346 ( .A(n61), .B(in2[11]), .C(n60), .Y(n79) );
XOR2X1TS U347 ( .A(n79), .B(in2[12]), .Y(n62) );
OAI21X4TS U348 ( .A0(n300), .A1(n306), .B0(n301), .Y(n65) );
AOI21X4TS U349 ( .A0(n299), .A1(n66), .B0(n65), .Y(n290) );
NAND2X1TS U350 ( .A(n79), .B(n67), .Y(n68) );
XOR2X1TS U351 ( .A(n68), .B(in2[13]), .Y(n69) );
INVX2TS U352 ( .A(in2[14]), .Y(n77) );
XNOR2X1TS U353 ( .A(in2[14]), .B(n85), .Y(n70) );
MXI2X4TS U354 ( .A(n77), .B(n70), .S0(n317), .Y(n72) );
AOI21X4TS U355 ( .A0(n6), .A1(n74), .B0(n73), .Y(n75) );
OAI21X4TS U356 ( .A0(n290), .A1(n76), .B0(n75), .Y(n287) );
XOR2X1TS U357 ( .A(n80), .B(in2[15]), .Y(n81) );
AOI21X4TS U358 ( .A0(n287), .A1(n82), .B0(n84), .Y(n259) );
NOR3X8TS U359 ( .A(n85), .B(in2[15]), .C(in2[14]), .Y(n109) );
NOR2X8TS U360 ( .A(n264), .B(n271), .Y(n99) );
INVX2TS U361 ( .A(in2[16]), .Y(n93) );
AOI21X4TS U362 ( .A0(n261), .A1(n99), .B0(n98), .Y(n100) );
OAI21X4TS U363 ( .A0(n259), .A1(n101), .B0(n100), .Y(n215) );
INVX2TS U364 ( .A(n107), .Y(n104) );
MX2X4TS U365 ( .A(in2[23]), .B(n106), .S0(n175), .Y(n129) );
NOR4X2TS U366 ( .A(n107), .B(n117), .C(in2[23]), .D(in2[22]), .Y(n108) );
INVX2TS U367 ( .A(in2[24]), .Y(n113) );
XNOR2X1TS U368 ( .A(n152), .B(in2[24]), .Y(n112) );
INVX2TS U369 ( .A(in2[20]), .Y(n116) );
INVX2TS U370 ( .A(in2[22]), .Y(n121) );
NOR2X8TS U371 ( .A(n128), .B(n127), .Y(n237) );
AOI21X4TS U372 ( .A0(n133), .A1(n228), .B0(n132), .Y(n134) );
OA21X4TS U373 ( .A0(n237), .A1(n135), .B0(n134), .Y(n136) );
NAND2X8TS U374 ( .A(n137), .B(n136), .Y(n206) );
INVX16TS U375 ( .A(n206), .Y(n211) );
INVX2TS U376 ( .A(in2[26]), .Y(n143) );
XOR2X1TS U377 ( .A(n211), .B(n142), .Y(res[26]) );
XNOR2X1TS U378 ( .A(n158), .B(in2[29]), .Y(n145) );
MX2X4TS U379 ( .A(in2[29]), .B(n145), .S0(n175), .Y(n165) );
NOR2X2TS U380 ( .A(n152), .B(n147), .Y(n148) );
XNOR2X1TS U381 ( .A(n148), .B(in2[28]), .Y(n149) );
XNOR2X1TS U382 ( .A(n153), .B(in2[27]), .Y(n156) );
OAI2BB1X4TS U383 ( .A0N(n175), .A1N(n156), .B0(n155), .Y(n161) );
AOI21X4TS U384 ( .A0(n163), .A1(n7), .B0(n162), .Y(n205) );
AOI21X4TS U385 ( .A0(n146), .A1(n197), .B0(n166), .Y(n167) );
OAI21X4TS U386 ( .A0(n205), .A1(n168), .B0(n167), .Y(n189) );
XNOR2X1TS U387 ( .A(n174), .B(in2[31]), .Y(n176) );
XNOR2X2TS U388 ( .A(n180), .B(n179), .Y(res[31]) );
OAI21X1TS U389 ( .A0(n187), .A1(n211), .B0(n186), .Y(res[32]) );
OAI21X4TS U390 ( .A0(n211), .A1(n191), .B0(n190), .Y(n195) );
XNOR2X2TS U391 ( .A(n195), .B(n194), .Y(res[30]) );
OAI21X4TS U392 ( .A0(n211), .A1(n200), .B0(n199), .Y(n203) );
XNOR2X4TS U393 ( .A(n203), .B(n202), .Y(res[29]) );
OAI2BB1X4TS U394 ( .A0N(n206), .A1N(n196), .B0(n205), .Y(n209) );
OAI21X4TS U395 ( .A0(n211), .A1(n210), .B0(n160), .Y(n214) );
XNOR2X2TS U396 ( .A(n214), .B(n213), .Y(res[27]) );
AOI21X4TS U397 ( .A0(n229), .A1(n219), .B0(n218), .Y(n220) );
OAI21X4TS U398 ( .A0(n258), .A1(n221), .B0(n220), .Y(n226) );
XNOR2X1TS U399 ( .A(n226), .B(n225), .Y(res[25]) );
OAI21X4TS U400 ( .A0(n258), .A1(n244), .B0(n8), .Y(n248) );
OAI21X4TS U401 ( .A0(n258), .A1(n254), .B0(n255), .Y(n253) );
XNOR2X2TS U402 ( .A(n253), .B(n252), .Y(res[21]) );
AOI21X4TS U403 ( .A0(n286), .A1(n263), .B0(n262), .Y(n268) );
XNOR2X1TS U404 ( .A(n286), .B(n285), .Y(res[16]) );
INVX2TS U405 ( .A(in2[2]), .Y(n316) );
XNOR2X1TS U406 ( .A(n320), .B(in2[2]), .Y(n315) );
MXI2X1TS U407 ( .A(n316), .B(n315), .S0(n339), .Y(n376) );
XOR2X1TS U408 ( .A(n319), .B(in2[0]), .Y(n318) );
MXI2X1TS U409 ( .A(n319), .B(n318), .S0(n317), .Y(n378) );
INVX2TS U410 ( .A(n369), .Y(n325) );
NOR2X1TS U411 ( .A(n320), .B(in2[2]), .Y(n321) );
OR2X2TS U412 ( .A(n324), .B(in1[3]), .Y(n367) );
NAND2X2TS U413 ( .A(n324), .B(in1[3]), .Y(n366) );
INVX2TS U414 ( .A(n366), .Y(n332) );
AOI21X1TS U415 ( .A0(n325), .A1(n367), .B0(n332), .Y(n329) );
MXI2X2TS U416 ( .A(n336), .B(n326), .S0(n339), .Y(n327) );
OR2X2TS U417 ( .A(n327), .B(in1[4]), .Y(n333) );
NAND2X1TS U418 ( .A(n333), .B(n330), .Y(n328) );
NAND2X1TS U419 ( .A(n333), .B(n367), .Y(n335) );
INVX2TS U420 ( .A(n330), .Y(n331) );
AOI21X1TS U421 ( .A0(n333), .A1(n332), .B0(n331), .Y(n334) );
OAI21X4TS U422 ( .A0(n369), .A1(n335), .B0(n334), .Y(n373) );
NAND2X1TS U423 ( .A(n337), .B(n336), .Y(n338) );
XNOR2X1TS U424 ( .A(n338), .B(in2[5]), .Y(n340) );
MXI2X2TS U425 ( .A(n341), .B(n340), .S0(n339), .Y(n342) );
INVX2TS U426 ( .A(n370), .Y(n343) );
AOI21X4TS U427 ( .A0(n373), .A1(n371), .B0(n343), .Y(n349) );
INVX2TS U428 ( .A(n348), .Y(n345) );
NAND2X1TS U429 ( .A(n345), .B(n347), .Y(n346) );
OAI21X2TS U430 ( .A0(n349), .A1(n348), .B0(n347), .Y(n355) );
XNOR2X1TS U431 ( .A(n355), .B(n351), .Y(res[7]) );
INVX2TS U432 ( .A(n352), .Y(n353) );
AOI21X2TS U433 ( .A0(n355), .A1(n354), .B0(n353), .Y(n365) );
XNOR2X1TS U434 ( .A(n360), .B(n359), .Y(res[9]) );
INVX2TS U435 ( .A(n361), .Y(n363) );
NAND2X1TS U436 ( .A(n363), .B(n362), .Y(n364) );
NAND2X1TS U437 ( .A(n367), .B(n366), .Y(n368) );
NAND2X1TS U438 ( .A(n371), .B(n370), .Y(n372) );
XNOR2X1TS U439 ( .A(n373), .B(n372), .Y(res[5]) );
AFHCONX2TS U440 ( .A(in1[2]), .B(n376), .CI(n375), .CON(n369), .S(res[2]) );
AFHCINX2TS U441 ( .CIN(n377), .B(n378), .A(in1[1]), .S(res[1]), .CO(n375) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_GeArN16R6P4_syn.sdf");
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Butterworth low pass IIR filter
// input: 8bit ADC signal, 1MS/s
// output: 8bit value, Fc=20khz
//
// coef: (using http://www-users.cs.york.ac.uk/~fisher/mkfilter/trad.html)
// Recurrence relation:
// y[n] = ( 1 * x[n- 2])
// + ( 2 * x[n- 1])
// + ( 1 * x[n- 0])
// + ( -0.8371816513 * y[n- 2])
// + ( 1.8226949252 * y[n- 1])
//
// therefore:
// a = [1,2,1]
// b = [-0.8371816513, 1.8226949252]
// b is approximated to b = [-0xd6/0x100, 0x1d3 / 0x100] (for optimization)
// gain = 2.761139367e2
//
// See details about its design see
// https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html
module lp20khz_1MSa_iir_filter(input clk, input [7:0] adc_d, output rdy, output [7:0] out);
// clk is 24MHz, the IIR filter is designed for 1MS/s
// hence we need to divide it by 24
// using a shift register takes less area than a counter
reg [23:0] cnt = 1;
assign rdy = cnt[0];
always @(posedge clk)
cnt <= {cnt[22:0], cnt[23]};
reg [7:0] x0 = 0;
reg [7:0] x1 = 0;
reg [16:0] y0 = 0;
reg [16:0] y1 = 0;
always @(posedge clk)
begin
if (rdy)
begin
x0 <= x1;
x1 <= adc_d;
y0 <= y1;
y1 <=
// center the signal:
// input range is [0; 255]
// We want "128" to be at the center of the 17bit register
// (128+z)*gain = 17bit center
// z = (1<<16)/gain - 128 = 109
// We could use 9bit x registers for that, but that would be
// a waste, let's just add the constant during the computation
// (x0+109) + 2*(x1+109) + (x2+109) = x0 + 2*x1 + x2 + 436
x0 + {x1, 1'b0} + adc_d + 436
// we want "- y0 * 0xd6 / 0x100" using only shift and add
// 0xd6 == 0b11010110
// so *0xd6/0x100 is equivalent to
// ((x << 1) + (x << 2) + (x << 4) + (x << 6) + (x << 7)) >> 8
// which is also equivalent to
// (x >> 7) + (x >> 6) + (x >> 4) + (x >> 2) + (x >> 1)
- ((y0 >> 7) + (y0 >> 6) + (y0 >> 4) + (y0 >> 2) + (y0 >> 1)) // - y0 * 0xd6 / 0x100
// we want "+ y1 * 0x1d3 / 0x100"
// 0x1d3 == 0b111010011
// so this is equivalent to
// ((x << 0) + (x << 1) + (x << 4) + (x << 6) + (x << 7) + (x << 8)) >> 8
// which is also equivalent to
// (x >> 8) + (x >> 7) + (x >> 4) + (x >> 2) + (x >> 1) + (x >> 0)
+ ((y1 >> 8) + (y1 >> 7) + (y1 >> 4) + (y1 >> 2) + (y1 >> 1) + y1);
end
end
// output: reduce to 8bit
assign out = y1[16:9];
endmodule
|
// DESCRIPTION: Verilator: SystemVerilog interface test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// counters
int cnt;
int cnt_src;
int cnt_drn;
// add all counters
assign cnt = cnt_src + cnt_drn + inf.cnt;
// finish report
always @ (posedge clk)
if (cnt == 3*16) begin
$write("*-* All Finished *-*\n");
$finish;
end
// interface instance
handshake inf (
.clk (clk),
.rst (rst)
);
// source instance
source #(
.RW (8),
.RP (8'b11100001)
) source (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_src)
);
// drain instance
drain #(
.RW (8),
.RP (8'b11010100)
) drain (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_drn)
);
endmodule : t
// interface definition
interface handshake #(
parameter int unsigned WC = 32
)(
input logic clk,
input logic rst
);
// modport signals
logic req; // request
logic grt; // grant
logic inc; // increment
// local signals
integer cnt; // counter
// source
modport src (
output req,
input grt
);
// drain
modport drn (
input req,
output grt
);
// incremet condition
assign inc = req & grt;
// local logic (counter)
always @ (posedge clk, posedge rst)
if (rst) cnt <= '0;
else cnt <= cnt + inc;
endinterface : handshake
// source module
module source #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.src inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + (inf.req & inf.grt);
// request signal
assign inf.req = rnd[0];
endmodule : source
// drain module
module drain #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.drn inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + (inf.req & inf.grt);
// grant signal
assign inf.grt = rnd[0];
endmodule : drain
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_spc_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sys.h"
`include "iop.h"
`include "ifu.h"
module cpx_spc_buf (/*AUTOARG*/
// Outputs
cpx_spc_data_cx2_buf, cpx_spc_data_rdy_cx2_buf,
// Inputs
cpx_spc_data_cx2, cpx_spc_data_rdy_cx2
);
input [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
input cpx_spc_data_rdy_cx2;
output [`CPX_WIDTH-1:0] cpx_spc_data_cx2_buf;
output cpx_spc_data_rdy_cx2_buf;
assign cpx_spc_data_rdy_cx2_buf = cpx_spc_data_rdy_cx2 ;
assign cpx_spc_data_cx2_buf = cpx_spc_data_cx2 ;
endmodule
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import Eqdep JMeq List.
Require Import CpdtTactics.
Set Implicit Arguments.
(* end hide *)
(** %\chapter{Reasoning About Equality Proofs}% *)
(** In traditional mathematics, the concept of equality is usually taken as a given. On the other hand, in type theory, equality is a very contentious subject. There are at least three different notions of equality that are important in Coq, and researchers are actively investigating new definitions of what it means for two terms to be equal. Even once we fix a notion of equality, there are inevitably tricky issues that arise in proving properties of programs that manipulate equality proofs explicitly. In this chapter, I will focus on design patterns for circumventing these tricky issues, and I will introduce the different notions of equality as they are germane. *)
(** * The Definitional Equality *)
(** We have seen many examples so far where proof goals follow "by computation." That is, we apply computational reduction rules to reduce the goal to a normal form, at which point it follows trivially. Exactly when this works and when it does not depends on the details of Coq's%\index{definitional equality}% _definitional equality_. This is an untyped binary relation appearing in the formal metatheory of CIC. CIC contains a typing rule allowing the conclusion [E : T] from the premise [E : T'] and a proof that [T] and [T'] are definitionally equal.
The %\index{tactics!cbv}%[cbv] tactic will help us illustrate the rules of Coq's definitional equality. We redefine the natural number predecessor function in a somewhat convoluted way and construct a manual proof that it returns [0] when applied to [1]. *)
Definition pred' (x : nat) :=
match x with
| O => O
| S n' => let y := n' in y
end.
Theorem reduce_me : pred' 1 = 0.
(* begin thide *)
(** CIC follows the traditions of lambda calculus in associating reduction rules with Greek letters. Coq can certainly be said to support the familiar alpha reduction rule, which allows capture-avoiding renaming of bound variables, but we never need to apply alpha explicitly, since Coq uses a de Bruijn representation%~\cite{DeBruijn}% that encodes terms canonically.
The %\index{delta reduction}%delta rule is for unfolding global definitions. We can use it here to unfold the definition of [pred']. We do this with the [cbv] tactic, which takes a list of reduction rules and makes as many call-by-value reduction steps as possible, using only those rules. There is an analogous tactic %\index{tactics!lazy}%[lazy] for call-by-need reduction. *)
cbv delta.
(** %\vspace{-.15in}%[[
============================
(fun x : nat => match x with
| 0 => 0
| S n' => let y := n' in y
end) 1 = 0
]]
At this point, we want to apply the famous %\index{beta reduction}%beta reduction of lambda calculus, to simplify the application of a known function abstraction. *)
cbv beta.
(** %\vspace{-.15in}%[[
============================
match 1 with
| 0 => 0
| S n' => let y := n' in y
end = 0
]]
Next on the list is the %\index{iota reduction}%iota reduction, which simplifies a single [match] term by determining which pattern matches. *)
cbv iota.
(** %\vspace{-.15in}%[[
============================
(fun n' : nat => let y := n' in y) 0 = 0
]]
Now we need another beta reduction. *)
cbv beta.
(** %\vspace{-.15in}%[[
============================
(let y := 0 in y) = 0
]]
The final reduction rule is %\index{zeta reduction}%zeta, which replaces a [let] expression by its body with the appropriate term substituted. *)
cbv zeta.
(** %\vspace{-.15in}%[[
============================
0 = 0
]]
*)
reflexivity.
Qed.
(* end thide *)
(** The [beta] reduction rule applies to recursive functions as well, and its behavior may be surprising in some instances. For instance, we can run some simple tests using the reduction strategy [compute], which applies all applicable rules of the definitional equality. *)
Definition id (n : nat) := n.
Eval compute in fun x => id x.
(** %\vspace{-.15in}%[[
= fun x : nat => x
]]
*)
Fixpoint id' (n : nat) := n.
Eval compute in fun x => id' x.
(** %\vspace{-.15in}%[[
= fun x : nat => (fix id' (n : nat) : nat := n) x
]]
By running [compute], we ask Coq to run reduction steps until no more apply, so why do we see an application of a known function, where clearly no beta reduction has been performed? The answer has to do with ensuring termination of all Gallina programs. One candidate rule would say that we apply recursive definitions wherever possible. However, this would clearly lead to nonterminating reduction sequences, since the function may appear fully applied within its own definition, and we would %\%naive%{}%ly "simplify" such applications immediately. Instead, Coq only applies the beta rule for a recursive function when _the top-level structure of the recursive argument is known_. For [id'] above, we have only one argument [n], so clearly it is the recursive argument, and the top-level structure of [n] is known when the function is applied to [O] or to some [S e] term. The variable [x] is neither, so reduction is blocked.
What are recursive arguments in general? Every recursive function is compiled by Coq to a %\index{Gallina terms!fix}%[fix] expression, for anonymous definition of recursive functions. Further, every [fix] with multiple arguments has one designated as the recursive argument via a [struct] annotation. The recursive argument is the one that must decrease across recursive calls, to appease Coq's termination checker. Coq will generally infer which argument is recursive, though we may also specify it manually, if we want to tweak reduction behavior. For instance, consider this definition of a function to add two lists of [nat]s elementwise: *)
Fixpoint addLists (ls1 ls2 : list nat) : list nat :=
match ls1, ls2 with
| n1 :: ls1' , n2 :: ls2' => n1 + n2 :: addLists ls1' ls2'
| _, _ => nil
end.
(** By default, Coq chooses [ls1] as the recursive argument. We can see that [ls2] would have been another valid choice. The choice has a critical effect on reduction behavior, as these two examples illustrate: *)
Eval compute in fun ls => addLists nil ls.
(** %\vspace{-.15in}%[[
= fun _ : list nat => nil
]]
*)
Eval compute in fun ls => addLists ls nil.
(** %\vspace{-.15in}%[[
= fun ls : list nat =>
(fix addLists (ls1 ls2 : list nat) : list nat :=
match ls1 with
| nil => nil
| n1 :: ls1' =>
match ls2 with
| nil => nil
| n2 :: ls2' =>
(fix plus (n m : nat) : nat :=
match n with
| 0 => m
| S p => S (plus p m)
end) n1 n2 :: addLists ls1' ls2'
end
end) ls nil
]]
The outer application of the [fix] expression for [addLists] was only simplified in the first case, because in the second case the recursive argument is [ls], whose top-level structure is not known.
The opposite behavior pertains to a version of [addLists] with [ls2] marked as recursive. *)
Fixpoint addLists' (ls1 ls2 : list nat) {struct ls2} : list nat :=
match ls1, ls2 with
| n1 :: ls1' , n2 :: ls2' => n1 + n2 :: addLists' ls1' ls2'
| _, _ => nil
end.
(* begin hide *)
(* begin thide *)
Definition foo := (@eq, plus).
(* end thide *)
(* end hide *)
Eval compute in fun ls => addLists' ls nil.
(** %\vspace{-.15in}%[[
= fun ls : list nat => match ls with
| nil => nil
| _ :: _ => nil
end
]]
We see that all use of recursive functions has been eliminated, though the term has not quite simplified to [nil]. We could get it to do so by switching the order of the [match] discriminees in the definition of [addLists'].
Recall that co-recursive definitions have a dual rule: a co-recursive call only simplifies when it is the discriminee of a [match]. This condition is built into the beta rule for %\index{Gallina terms!cofix}%[cofix], the anonymous form of [CoFixpoint].
%\medskip%
The standard [eq] relation is critically dependent on the definitional equality. The relation [eq] is often called a%\index{propositional equality}% _propositional equality_, because it reifies definitional equality as a proposition that may or may not hold. Standard axiomatizations of an equality predicate in first-order logic define equality in terms of properties it has, like reflexivity, symmetry, and transitivity. In contrast, for [eq] in Coq, those properties are implicit in the properties of the definitional equality, which are built into CIC's metatheory and the implementation of Gallina. We could add new rules to the definitional equality, and [eq] would keep its definition and methods of use.
This all may make it sound like the choice of [eq]'s definition is unimportant. To the contrary, in this chapter, we will see examples where alternate definitions may simplify proofs. Before that point, I will introduce proof methods for goals that use proofs of the standard propositional equality "as data." *)
(** * Heterogeneous Lists Revisited *)
(** One of our example dependent data structures from the last chapter (code repeated below) was the heterogeneous list and its associated "cursor" type. The recursive version poses some special challenges related to equality proofs, since it uses such proofs in its definition of [fmember] types. *)
Section fhlist.
Variable A : Type.
Variable B : A -> Type.
Fixpoint fhlist (ls : list A) : Type :=
match ls with
| nil => unit
| x :: ls' => B x * fhlist ls'
end%type.
Variable elm : A.
Fixpoint fmember (ls : list A) : Type :=
match ls with
| nil => Empty_set
| x :: ls' => (x = elm) + fmember ls'
end%type.
Fixpoint fhget (ls : list A) : fhlist ls -> fmember ls -> B elm :=
match ls return fhlist ls -> fmember ls -> B elm with
| nil => fun _ idx => match idx with end
| _ :: ls' => fun mls idx =>
match idx with
| inl pf => match pf with
| eq_refl => fst mls
end
| inr idx' => fhget ls' (snd mls) idx'
end
end.
End fhlist.
Implicit Arguments fhget [A B elm ls].
(* begin hide *)
(* begin thide *)
Definition map := O.
(* end thide *)
(* end hide *)
(** We can define a [map]-like function for [fhlist]s. *)
Section fhlist_map.
Variables A : Type.
Variables B C : A -> Type.
Variable f : forall x, B x -> C x.
Fixpoint fhmap (ls : list A) : fhlist B ls -> fhlist C ls :=
match ls return fhlist B ls -> fhlist C ls with
| nil => fun _ => tt
| _ :: _ => fun hls => (f (fst hls), fhmap _ (snd hls))
end.
Implicit Arguments fhmap [ls].
(* begin hide *)
(* begin thide *)
Definition ilist := O.
Definition get := O.
Definition imap := O.
(* end thide *)
(* end hide *)
(** For the inductive versions of the [ilist] definitions, we proved a lemma about the interaction of [get] and [imap]. It was a strategic choice not to attempt such a proof for the definitions that we just gave, which sets us on a collision course with the problems that are the subject of this chapter. *)
Variable elm : A.
Theorem fhget_fhmap : forall ls (mem : fmember elm ls) (hls : fhlist B ls),
fhget (fhmap hls) mem = f (fhget hls mem).
(* begin hide *)
induction ls; crush; case a0; reflexivity.
(* end hide *)
(** %\vspace{-.2in}%[[
induction ls; crush.
]]
%\vspace{-.15in}%In Coq 8.2, one subgoal remains at this point. Coq 8.3 has added some tactic improvements that enable [crush] to complete all of both inductive cases. To introduce the basics of reasoning about equality, it will be useful to review what was necessary in Coq 8.2.
Part of our single remaining subgoal is:
[[
a0 : a = elm
============================
match a0 in (_ = a2) return (C a2) with
| eq_refl => f a1
end = f match a0 in (_ = a2) return (B a2) with
| eq_refl => a1
end
]]
This seems like a trivial enough obligation. The equality proof [a0] must be [eq_refl], the only constructor of [eq]. Therefore, both the [match]es reduce to the point where the conclusion follows by reflexivity.
[[
destruct a0.
]]
<<
User error: Cannot solve a second-order unification problem
>>
This is one of Coq's standard error messages for informing us of a failure in its heuristics for attempting an instance of an undecidable problem about dependent typing. We might try to nudge things in the right direction by stating the lemma that we believe makes the conclusion trivial.
[[
assert (a0 = eq_refl _).
]]
<<
The term "eq_refl ?98" has type "?98 = ?98"
while it is expected to have type "a = elm"
>>
In retrospect, the problem is not so hard to see. Reflexivity proofs only show [x = x] for particular values of [x], whereas here we are thinking in terms of a proof of [a = elm], where the two sides of the equality are not equal syntactically. Thus, the essential lemma we need does not even type-check!
Is it time to throw in the towel? Luckily, the answer is "no." In this chapter, we will see several useful patterns for proving obligations like this.
For this particular example, the solution is surprisingly straightforward. The [destruct] tactic has a simpler sibling [case] which should behave identically for any inductive type with one constructor of no arguments.
[[
case a0.
============================
f a1 = f a1
]]
It seems that [destruct] was trying to be too smart for its own good.
[[
reflexivity.
]]
%\vspace{-.2in}% *)
Qed.
(* end thide *)
(** It will be helpful to examine the proof terms generated by this sort of strategy. A simpler example illustrates what is going on. *)
Lemma lemma1 : forall x (pf : x = elm), O = match pf with eq_refl => O end.
(* begin thide *)
simple destruct pf; reflexivity.
Qed.
(* end thide *)
(** The tactic %\index{tactics!simple destruct}%[simple destruct pf] is a convenient form for applying [case]. It runs [intro] to bring into scope all quantified variables up to its argument. *)
Print lemma1.
(** %\vspace{-.15in}% [[
lemma1 =
fun (x : A) (pf : x = elm) =>
match pf as e in (_ = y) return (0 = match e with
| eq_refl => 0
end) with
| eq_refl => eq_refl 0
end
: forall (x : A) (pf : x = elm), 0 = match pf with
| eq_refl => 0
end
]]
Using what we know about shorthands for [match] annotations, we can write this proof in shorter form manually. *)
(* begin thide *)
Definition lemma1' (x : A) (pf : x = elm) :=
match pf return (0 = match pf with
| eq_refl => 0
end) with
| eq_refl => eq_refl 0
end.
(* end thide *)
(** Surprisingly, what seems at first like a _simpler_ lemma is harder to prove. *)
Lemma lemma2 : forall (x : A) (pf : x = x), O = match pf with eq_refl => O end.
(* begin thide *)
(** %\vspace{-.25in}%[[
simple destruct pf.
]]
<<
User error: Cannot solve a second-order unification problem
>>
*)
Abort.
(** Nonetheless, we can adapt the last manual proof to handle this theorem. *)
(* begin thide *)
Definition lemma2 :=
fun (x : A) (pf : x = x) =>
match pf return (0 = match pf with
| eq_refl => 0
end) with
| eq_refl => eq_refl 0
end.
(* end thide *)
(** We can try to prove a lemma that would simplify proofs of many facts like [lemma2]: *)
(* begin hide *)
(* begin thide *)
Definition lemma3' := O.
(* end thide *)
(* end hide *)
Lemma lemma3 : forall (x : A) (pf : x = x), pf = eq_refl x.
(* begin thide *)
(** %\vspace{-.25in}%[[
simple destruct pf.
]]
<<
User error: Cannot solve a second-order unification problem
>>
%\vspace{-.15in}%*)
Abort.
(** This time, even our manual attempt fails.
[[
Definition lemma3' :=
fun (x : A) (pf : x = x) =>
match pf as pf' in (_ = x') return (pf' = eq_refl x') with
| eq_refl => eq_refl _
end.
]]
<<
The term "eq_refl x'" has type "x' = x'" while it is expected to have type
"x = x'"
>>
The type error comes from our [return] annotation. In that annotation, the [as]-bound variable [pf'] has type [x = x'], referring to the [in]-bound variable [x']. To do a dependent [match], we _must_ choose a fresh name for the second argument of [eq]. We are just as constrained to use the "real" value [x] for the first argument. Thus, within the [return] clause, the proof we are matching on _must_ equate two non-matching terms, which makes it impossible to equate that proof with reflexivity.
Nonetheless, it turns out that, with one catch, we _can_ prove this lemma. *)
Lemma lemma3 : forall (x : A) (pf : x = x), pf = eq_refl x.
intros; apply UIP_refl.
Qed.
Check UIP_refl.
(** %\vspace{-.15in}% [[
UIP_refl
: forall (U : Type) (x : U) (p : x = x), p = eq_refl x
]]
The theorem %\index{Gallina terms!UIP\_refl}%[UIP_refl] comes from the [Eqdep] module of the standard library. (Its name uses the acronym "UIP" for "unicity of identity proofs.") Do the Coq authors know of some clever trick for building such proofs that we have not seen yet? If they do, they did not use it for this proof. Rather, the proof is based on an _axiom_, the term [eq_rect_eq] below. *)
(* begin hide *)
Import Eq_rect_eq.
(* end hide *)
Print eq_rect_eq.
(** %\vspace{-.15in}% [[
*** [ eq_rect_eq :
forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h ]
]]
The axiom %\index{Gallina terms!eq\_rect\_eq}%[eq_rect_eq] states a "fact" that seems like common sense, once the notation is deciphered. The term [eq_rect] is the automatically generated recursion principle for [eq]. Calling [eq_rect] is another way of [match]ing on an equality proof. The proof we match on is the argument [h], and [x] is the body of the [match]. The statement of [eq_rect_eq] just says that [match]es on proofs of [p = p], for any [p], are superfluous and may be removed. We can see this intuition better in code by asking Coq to simplify the theorem statement with the [compute] reduction strategy. *)
(* begin hide *)
(* begin thide *)
Definition False' := False.
(* end thide *)
(* end hide *)
Eval compute in (forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h).
(** %\vspace{-.15in}%[[
= forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = match h in (_ = y) return (Q y) with
| eq_refl => x
end
]]
Perhaps surprisingly, we cannot prove [eq_rect_eq] from within Coq. This proposition is introduced as an %\index{axioms}%axiom; that is, a proposition asserted as true without proof. We cannot assert just any statement without proof. Adding [False] as an axiom would allow us to prove any proposition, for instance, defeating the point of using a proof assistant. In general, we need to be sure that we never assert _inconsistent_ sets of axioms. A set of axioms is inconsistent if its conjunction implies [False]. For the case of [eq_rect_eq], consistency has been verified outside of Coq via "informal" metatheory%~\cite{AxiomK}%, in a study that also established unprovability of the axiom in CIC.
This axiom is equivalent to another that is more commonly known and mentioned in type theory circles. *)
(* begin hide *)
(* begin thide *)
Definition Streicher_K' := UIP_refl__Streicher_K.
(* end thide *)
(* end hide *)
Check Streicher_K.
(* end thide *)
(** %\vspace{-.15in}% [[
Streicher_K
: forall (U : Type) (x : U) (P : x = x -> Prop),
P eq_refl -> forall p : x = x, P p
]]
This is the opaquely named %\index{axiom K}%"Streicher's axiom K," which says that a predicate on properly typed equality proofs holds of all such proofs if it holds of reflexivity. *)
End fhlist_map.
(* begin hide *)
(* begin thide *)
Require Eqdep_dec.
(* end thide *)
(* end hide *)
(** It is worth remarking that it is possible to avoid axioms altogether for equalities on types with decidable equality. The [Eqdep_dec] module of the standard library contains a parametric proof of [UIP_refl] for such cases. To simplify presentation, we will stick with the axiom version in the rest of this chapter. *)
(** * Type-Casts in Theorem Statements *)
(** Sometimes we need to use tricks with equality just to state the theorems that we care about. To illustrate, we start by defining a concatenation function for [fhlist]s. *)
Section fhapp.
Variable A : Type.
Variable B : A -> Type.
Fixpoint fhapp (ls1 ls2 : list A)
: fhlist B ls1 -> fhlist B ls2 -> fhlist B (ls1 ++ ls2) :=
match ls1 with
| nil => fun _ hls2 => hls2
| _ :: _ => fun hls1 hls2 => (fst hls1, fhapp _ _ (snd hls1) hls2)
end.
Implicit Arguments fhapp [ls1 ls2].
(* EX: Prove that fhapp is associative. *)
(* begin thide *)
(** We might like to prove that [fhapp] is associative.
[[
Theorem fhapp_assoc : forall ls1 ls2 ls3
(hls1 : fhlist B ls1) (hls2 : fhlist B ls2) (hls3 : fhlist B ls3),
fhapp hls1 (fhapp hls2 hls3) = fhapp (fhapp hls1 hls2) hls3.
]]
<<
The term
"fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3) (fhapp (ls1:=ls1) (ls2:=ls2) hls1 hls2)
hls3" has type "fhlist B ((ls1 ++ ls2) ++ ls3)"
while it is expected to have type "fhlist B (ls1 ++ ls2 ++ ls3)"
>>
This first cut at the theorem statement does not even type-check. We know that the two [fhlist] types appearing in the error message are always equal, by associativity of normal list append, but this fact is not apparent to the type checker. This stems from the fact that Coq's equality is%\index{intensional type theory}% _intensional_, in the sense that type equality theorems can never be applied after the fact to get a term to type-check. Instead, we need to make use of equality explicitly in the theorem statement. *)
Theorem fhapp_assoc : forall ls1 ls2 ls3
(pf : (ls1 ++ ls2) ++ ls3 = ls1 ++ (ls2 ++ ls3))
(hls1 : fhlist B ls1) (hls2 : fhlist B ls2) (hls3 : fhlist B ls3),
fhapp hls1 (fhapp hls2 hls3)
= match pf in (_ = ls) return fhlist _ ls with
| eq_refl => fhapp (fhapp hls1 hls2) hls3
end.
induction ls1; crush.
(** The first remaining subgoal looks trivial enough:
[[
============================
fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3 =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl => fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3
end
]]
We can try what worked in previous examples.
[[
case pf.
]]
<<
User error: Cannot solve a second-order unification problem
>>
It seems we have reached another case where it is unclear how to use a dependent [match] to implement case analysis on our proof. The [UIP_refl] theorem can come to our rescue again. *)
rewrite (UIP_refl _ _ pf).
(** [[
============================
fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3 =
fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3
]]
*)
reflexivity.
(** Our second subgoal is trickier.
[[
pf : a :: (ls1 ++ ls2) ++ ls3 = a :: ls1 ++ ls2 ++ ls3
============================
(a0,
fhapp (ls1:=ls1) (ls2:=ls2 ++ ls3) b
(fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3)) =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl =>
(a0,
fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3)
(fhapp (ls1:=ls1) (ls2:=ls2) b hls2) hls3)
end
rewrite (UIP_refl _ _ pf).
]]
<<
The term "pf" has type "a :: (ls1 ++ ls2) ++ ls3 = a :: ls1 ++ ls2 ++ ls3"
while it is expected to have type "?556 = ?556"
>>
We can only apply [UIP_refl] on proofs of equality with syntactically equal operands, which is not the case of [pf] here. We will need to manipulate the form of this subgoal to get us to a point where we may use [UIP_refl]. A first step is obtaining a proof suitable to use in applying the induction hypothesis. Inversion on the structure of [pf] is sufficient for that. *)
injection pf; intro pf'.
(** [[
pf : a :: (ls1 ++ ls2) ++ ls3 = a :: ls1 ++ ls2 ++ ls3
pf' : (ls1 ++ ls2) ++ ls3 = ls1 ++ ls2 ++ ls3
============================
(a0,
fhapp (ls1:=ls1) (ls2:=ls2 ++ ls3) b
(fhapp (ls1:=ls2) (ls2:=ls3) hls2 hls3)) =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl =>
(a0,
fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3)
(fhapp (ls1:=ls1) (ls2:=ls2) b hls2) hls3)
end
]]
Now we can rewrite using the inductive hypothesis. *)
rewrite (IHls1 _ _ pf').
(** [[
============================
(a0,
match pf' in (_ = ls) return (fhlist B ls) with
| eq_refl =>
fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3)
(fhapp (ls1:=ls1) (ls2:=ls2) b hls2) hls3
end) =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl =>
(a0,
fhapp (ls1:=ls1 ++ ls2) (ls2:=ls3)
(fhapp (ls1:=ls1) (ls2:=ls2) b hls2) hls3)
end
]]
We have made an important bit of progress, as now only a single call to [fhapp] appears in the conclusion, repeated twice. Trying case analysis on our proofs still will not work, but there is a move we can make to enable it. Not only does just one call to [fhapp] matter to us now, but it also _does not matter what the result of the call is_. In other words, the subgoal should remain true if we replace this [fhapp] call with a fresh variable. The %\index{tactics!generalize}%[generalize] tactic helps us do exactly that. *)
generalize (fhapp (fhapp b hls2) hls3).
(** [[
forall f : fhlist B ((ls1 ++ ls2) ++ ls3),
(a0,
match pf' in (_ = ls) return (fhlist B ls) with
| eq_refl => f
end) =
match pf in (_ = ls) return (fhlist B ls) with
| eq_refl => (a0, f)
end
]]
The conclusion has gotten markedly simpler. It seems counterintuitive that we can have an easier time of proving a more general theorem, but such a phenomenon applies to the case here and to many other proofs that use dependent types heavily. Speaking informally, the reason why this kind of activity helps is that [match] annotations contain some positions where only variables are allowed. By reducing more elements of a goal to variables, built-in tactics can have more success building [match] terms under the hood.
In this case, it is helpful to generalize over our two proofs as well. *)
generalize pf pf'.
(** [[
forall (pf0 : a :: (ls1 ++ ls2) ++ ls3 = a :: ls1 ++ ls2 ++ ls3)
(pf'0 : (ls1 ++ ls2) ++ ls3 = ls1 ++ ls2 ++ ls3)
(f : fhlist B ((ls1 ++ ls2) ++ ls3)),
(a0,
match pf'0 in (_ = ls) return (fhlist B ls) with
| eq_refl => f
end) =
match pf0 in (_ = ls) return (fhlist B ls) with
| eq_refl => (a0, f)
end
]]
To an experienced dependent types hacker, the appearance of this goal term calls for a celebration. The formula has a critical property that indicates that our problems are over. To get our proofs into the right form to apply [UIP_refl], we need to use associativity of list append to rewrite their types. We could not do so before because other parts of the goal require the proofs to retain their original types. In particular, the call to [fhapp] that we generalized must have type [(ls1 ++ ls2) ++ ls3], for some values of the list variables. If we rewrite the type of the proof used to type-cast this value to something like [ls1 ++ ls2 ++ ls3 = ls1 ++ ls2 ++ ls3], then the lefthand side of the equality would no longer match the type of the term we are trying to cast.
However, now that we have generalized over the [fhapp] call, the type of the term being type-cast appears explicitly in the goal and _may be rewritten as well_. In particular, the final masterstroke is rewriting everywhere in our goal using associativity of list append. *)
rewrite app_assoc.
(** [[
============================
forall (pf0 : a :: ls1 ++ ls2 ++ ls3 = a :: ls1 ++ ls2 ++ ls3)
(pf'0 : ls1 ++ ls2 ++ ls3 = ls1 ++ ls2 ++ ls3)
(f : fhlist B (ls1 ++ ls2 ++ ls3)),
(a0,
match pf'0 in (_ = ls) return (fhlist B ls) with
| eq_refl => f
end) =
match pf0 in (_ = ls) return (fhlist B ls) with
| eq_refl => (a0, f)
end
]]
We can see that we have achieved the crucial property: the type of each generalized equality proof has syntactically equal operands. This makes it easy to finish the proof with [UIP_refl]. *)
intros.
rewrite (UIP_refl _ _ pf0).
rewrite (UIP_refl _ _ pf'0).
reflexivity.
Qed.
(* end thide *)
End fhapp.
Implicit Arguments fhapp [A B ls1 ls2].
(** This proof strategy was cumbersome and unorthodox, from the perspective of mainstream mathematics. The next section explores an alternative that leads to simpler developments in some cases. *)
(** * Heterogeneous Equality *)
(** There is another equality predicate, defined in the %\index{Gallina terms!JMeq}%[JMeq] module of the standard library, implementing%\index{heterogeneous equality}% _heterogeneous equality_. *)
Print JMeq.
(** %\vspace{-.15in}% [[
Inductive JMeq (A : Type) (x : A) : forall B : Type, B -> Prop :=
JMeq_refl : JMeq x x
]]
The identifier [JMeq] stands for %\index{John Major equality}%"John Major equality," a name coined by Conor McBride%~\cite{JMeq}% as an inside joke about British politics. The definition [JMeq] starts out looking a lot like the definition of [eq]. The crucial difference is that we may use [JMeq] _on arguments of different types_. For instance, a lemma that we failed to establish before is trivial with [JMeq]. It makes for prettier theorem statements to define some syntactic shorthand first. *)
Infix "==" := JMeq (at level 70, no associativity).
(* EX: Prove UIP_refl' : forall (A : Type) (x : A) (pf : x = x), pf == eq_refl x *)
(* begin thide *)
Definition UIP_refl' (A : Type) (x : A) (pf : x = x) : pf == eq_refl x :=
match pf return (pf == eq_refl _) with
| eq_refl => JMeq_refl _
end.
(* end thide *)
(** There is no quick way to write such a proof by tactics, but the underlying proof term that we want is trivial.
Suppose that we want to use [UIP_refl'] to establish another lemma of the kind we have run into several times so far. *)
Lemma lemma4 : forall (A : Type) (x : A) (pf : x = x),
O = match pf with eq_refl => O end.
(* begin thide *)
intros; rewrite (UIP_refl' pf); reflexivity.
Qed.
(* end thide *)
(** All in all, refreshingly straightforward, but there really is no such thing as a free lunch. The use of [rewrite] is implemented in terms of an axiom: *)
Check JMeq_eq.
(** %\vspace{-.15in}% [[
JMeq_eq
: forall (A : Type) (x y : A), x == y -> x = y
]]
It may be surprising that we cannot prove that heterogeneous equality implies normal equality. The difficulties are the same kind we have seen so far, based on limitations of [match] annotations. The [JMeq_eq] axiom has been proved on paper to be consistent, but asserting it may still be considered to complicate the logic we work in, so there is some motivation for avoiding it.
We can redo our [fhapp] associativity proof based around [JMeq]. *)
Section fhapp'.
Variable A : Type.
Variable B : A -> Type.
(** This time, the %\%naive%{}% theorem statement type-checks. *)
(* EX: Prove [fhapp] associativity using [JMeq]. *)
(* begin thide *)
Theorem fhapp_assoc' : forall ls1 ls2 ls3 (hls1 : fhlist B ls1) (hls2 : fhlist B ls2)
(hls3 : fhlist B ls3),
fhapp hls1 (fhapp hls2 hls3) == fhapp (fhapp hls1 hls2) hls3.
induction ls1; crush.
(** Even better, [crush] discharges the first subgoal automatically. The second subgoal is:
[[
============================
(a0, fhapp b (fhapp hls2 hls3)) == (a0, fhapp (fhapp b hls2) hls3)
]]
It looks like one rewrite with the inductive hypothesis should be enough to make the goal trivial. Here is what happens when we try that in Coq 8.2:
[[
rewrite IHls1.
]]
<<
Error: Impossible to unify "fhlist B ((ls1 ++ ?1572) ++ ?1573)" with
"fhlist B (ls1 ++ ?1572 ++ ?1573)"
>>
Coq 8.4 currently gives an error message about an uncaught exception. Perhaps that will be fixed soon. In any case, it is educational to consider a more explicit approach.
We see that [JMeq] is not a silver bullet. We can use it to simplify the statements of equality facts, but the Coq type-checker uses non-trivial heterogeneous equality facts no more readily than it uses standard equality facts. Here, the problem is that the form [(e1, e2)] is syntactic sugar for an explicit application of a constructor of an inductive type. That application mentions the type of each tuple element explicitly, and our [rewrite] tries to change one of those elements without updating the corresponding type argument.
We can get around this problem by another multiple use of [generalize]. We want to bring into the goal the proper instance of the inductive hypothesis, and we also want to generalize the two relevant uses of [fhapp]. *)
generalize (fhapp b (fhapp hls2 hls3))
(fhapp (fhapp b hls2) hls3)
(IHls1 _ _ b hls2 hls3).
(** %\vspace{-.15in}%[[
============================
forall (f : fhlist B (ls1 ++ ls2 ++ ls3))
(f0 : fhlist B ((ls1 ++ ls2) ++ ls3)), f == f0 -> (a0, f) == (a0, f0)
]]
Now we can rewrite with append associativity, as before. *)
rewrite app_assoc.
(** %\vspace{-.15in}%[[
============================
forall f f0 : fhlist B (ls1 ++ ls2 ++ ls3), f == f0 -> (a0, f) == (a0, f0)
]]
From this point, the goal is trivial. *)
intros f f0 H; rewrite H; reflexivity.
Qed.
(* end thide *)
End fhapp'.
(** This example illustrates a general pattern: heterogeneous equality often simplifies theorem statements, but we still need to do some work to line up some dependent pattern matches that tactics will generate for us.
The proof we have found relies on the [JMeq_eq] axiom, which we can verify with a command%\index{Vernacular commands!Print Assumptions}% that we will discuss more in two chapters. *)
Print Assumptions fhapp_assoc'.
(** %\vspace{-.15in}%[[
Axioms:
JMeq_eq : forall (A : Type) (x y : A), x == y -> x = y
]]
It was the [rewrite H] tactic that implicitly appealed to the axiom. By restructuring the proof, we can avoid axiom dependence. A general lemma about pairs provides the key element. (Our use of [generalize] above can be thought of as reducing the proof to another, more complex and specialized lemma.) *)
Lemma pair_cong : forall A1 A2 B1 B2 (x1 : A1) (x2 : A2) (y1 : B1) (y2 : B2),
x1 == x2
-> y1 == y2
-> (x1, y1) == (x2, y2).
intros until y2; intros Hx Hy; rewrite Hx; rewrite Hy; reflexivity.
Qed.
Hint Resolve pair_cong.
Section fhapp''.
Variable A : Type.
Variable B : A -> Type.
Theorem fhapp_assoc'' : forall ls1 ls2 ls3 (hls1 : fhlist B ls1) (hls2 : fhlist B ls2)
(hls3 : fhlist B ls3),
fhapp hls1 (fhapp hls2 hls3) == fhapp (fhapp hls1 hls2) hls3.
induction ls1; crush.
Qed.
End fhapp''.
Print Assumptions fhapp_assoc''.
(** <<
Closed under the global context
>>
One might wonder exactly which elements of a proof involving [JMeq] imply that [JMeq_eq] must be used. For instance, above we noticed that [rewrite] had brought [JMeq_eq] into the proof of [fhapp_assoc'], yet here we have also used [rewrite] with [JMeq] hypotheses while avoiding axioms! One illuminating exercise is comparing the types of the lemmas that [rewrite] uses under the hood to implement the rewrites. Here is the normal lemma for [eq] rewriting:%\index{Gallina terms!eq\_ind\_r}% *)
Check eq_ind_r.
(** %\vspace{-.15in}%[[
eq_ind_r
: forall (A : Type) (x : A) (P : A -> Prop),
P x -> forall y : A, y = x -> P y
]]
The corresponding lemma used for [JMeq] in the proof of [pair_cong] is %\index{Gallina terms!internal\_JMeq\_rew\_r}%[internal_JMeq_rew_r], which, confusingly, is defined by [rewrite] as needed, so it is not available for checking until after we apply it. *)
Check internal_JMeq_rew_r.
(** %\vspace{-.15in}%[[
internal_JMeq_rew_r
: forall (A : Type) (x : A) (B : Type) (b : B)
(P : forall B0 : Type, B0 -> Type), P B b -> x == b -> P A x
]]
The key difference is that, where the [eq] lemma is parameterized on a predicate of type [A -> Prop], the [JMeq] lemma is parameterized on a predicate of type more like [forall A : Type, A -> Prop]. To apply [eq_ind_r] with a proof of [x = y], it is only necessary to rearrange the goal into an application of a [fun] abstraction to [y]. In contrast, to apply [internal_JMeq_rew_r], it is necessary to rearrange the goal to an application of a [fun] abstraction to both [y] and _its type_. In other words, the predicate must be _polymorphic_ in [y]'s type; any type must make sense, from a type-checking standpoint. There may be cases where the former rearrangement is easy to do in a type-correct way, but the second rearrangement done %\%naive%{}%ly leads to a type error.
When [rewrite] cannot figure out how to apply [internal_JMeq_rew_r] for [x == y] where [x] and [y] have the same type, the tactic can instead use an alternate theorem, which is easy to prove as a composition of [eq_ind_r] and [JMeq_eq]. *)
Check JMeq_ind_r.
(** %\vspace{-.15in}%[[
JMeq_ind_r
: forall (A : Type) (x : A) (P : A -> Prop),
P x -> forall y : A, y == x -> P y
]]
Ironically, where in the proof of [fhapp_assoc'] we used [rewrite app_assoc] to make it clear that a use of [JMeq] was actually homogeneously typed, we created a situation where [rewrite] applied the axiom-based [JMeq_ind_r] instead of the axiom-free [internal_JMeq_rew_r]!
For another simple example, consider this theorem that applies a heterogeneous equality to prove a congruence fact. *)
Theorem out_of_luck : forall n m : nat,
n == m
-> S n == S m.
intros n m H.
(** Applying [JMeq_ind_r] is easy, as the %\index{tactics!pattern}%[pattern] tactic will transform the goal into an application of an appropriate [fun] to a term that we want to abstract. (In general, [pattern] abstracts over a term by introducing a new anonymous function taking that term as argument.) *)
pattern n.
(** %\vspace{-.15in}%[[
n : nat
m : nat
H : n == m
============================
(fun n0 : nat => S n0 == S m) n
]]
*)
apply JMeq_ind_r with (x := m); auto.
(** However, we run into trouble trying to get the goal into a form compatible with [internal_JMeq_rew_r.] *)
Undo 2.
(** %\vspace{-.15in}%[[
pattern nat, n.
]]
<<
Error: The abstracted term "fun (P : Set) (n0 : P) => S n0 == S m"
is not well typed.
Illegal application (Type Error):
The term "S" of type "nat -> nat"
cannot be applied to the term
"n0" : "P"
This term has type "P" which should be coercible to
"nat".
>>
In other words, the successor function [S] is insufficiently polymorphic. If we try to generalize over the type of [n], we find that [S] is no longer legal to apply to [n]. *)
Abort.
(** Why did we not run into this problem in our proof of [fhapp_assoc'']? The reason is that the pair constructor is polymorphic in the types of the pair components, while functions like [S] are not polymorphic at all. Use of such non-polymorphic functions with [JMeq] tends to push toward use of axioms. The example with [nat] here is a bit unrealistic; more likely cases would involve functions that have _some_ polymorphism, but not enough to allow abstractions of the sort we attempted above with [pattern]. For instance, we might have an equality between two lists, where the goal only type-checks when the terms involved really are lists, though everything is polymorphic in the types of list data elements. The {{http://www.mpi-sws.org/~gil/Heq/}Heq} library builds up a slightly different foundation to help avoid such problems. *)
(** * Equivalence of Equality Axioms *)
(* EX: Show that the approaches based on K and JMeq are equivalent logically. *)
(* begin thide *)
(** Assuming axioms (like axiom K and [JMeq_eq]) is a hazardous business. The due diligence associated with it is necessarily global in scope, since two axioms may be consistent alone but inconsistent together. It turns out that all of the major axioms proposed for reasoning about equality in Coq are logically equivalent, so that we only need to pick one to assert without proof. In this section, we demonstrate by showing how each of the previous two sections' approaches reduces to the other logically.
To show that [JMeq] and its axiom let us prove [UIP_refl], we start from the lemma [UIP_refl'] from the previous section. The rest of the proof is trivial. *)
Lemma UIP_refl'' : forall (A : Type) (x : A) (pf : x = x), pf = eq_refl x.
intros; rewrite (UIP_refl' pf); reflexivity.
Qed.
(** The other direction is perhaps more interesting. Assume that we only have the axiom of the [Eqdep] module available. We can define [JMeq] in a way that satisfies the same interface as the combination of the [JMeq] module's inductive definition and axiom. *)
Definition JMeq' (A : Type) (x : A) (B : Type) (y : B) : Prop :=
exists pf : B = A, x = match pf with eq_refl => y end.
Infix "===" := JMeq' (at level 70, no associativity).
(** remove printing exists *)
(** We say that, by definition, [x] and [y] are equal if and only if there exists a proof [pf] that their types are equal, such that [x] equals the result of casting [y] with [pf]. This statement can look strange from the standpoint of classical math, where we almost never mention proofs explicitly with quantifiers in formulas, but it is perfectly legal Coq code.
We can easily prove a theorem with the same type as that of the [JMeq_refl] constructor of [JMeq]. *)
Theorem JMeq_refl' : forall (A : Type) (x : A), x === x.
intros; unfold JMeq'; exists (eq_refl A); reflexivity.
Qed.
(** printing exists $\exists$ *)
(** The proof of an analogue to [JMeq_eq] is a little more interesting, but most of the action is in appealing to [UIP_refl]. *)
Theorem JMeq_eq' : forall (A : Type) (x y : A),
x === y -> x = y.
unfold JMeq'; intros.
(** [[
H : exists pf : A = A,
x = match pf in (_ = T) return T with
| eq_refl => y
end
============================
x = y
]]
*)
destruct H.
(** [[
x0 : A = A
H : x = match x0 in (_ = T) return T with
| eq_refl => y
end
============================
x = y
]]
*)
rewrite H.
(** [[
x0 : A = A
============================
match x0 in (_ = T) return T with
| eq_refl => y
end = y
]]
*)
rewrite (UIP_refl _ _ x0); reflexivity.
Qed.
(** We see that, in a very formal sense, we are free to switch back and forth between the two styles of proofs about equality proofs. One style may be more convenient than the other for some proofs, but we can always interconvert between our results. The style that does not use heterogeneous equality may be preferable in cases where many results do not require the tricks of this chapter, since then the use of axioms is avoided altogether for the simple cases, and a wider audience will be able to follow those "simple" proofs. On the other hand, heterogeneous equality often makes for shorter and more readable theorem statements. *)
(* end thide *)
(** * Equality of Functions *)
(** The following seems like a reasonable theorem to want to hold, and it does hold in set theory.
%\vspace{-.15in}%[[
Theorem two_funs : (fun n => n) = (fun n => n + 0).
]]
%\vspace{-.15in}%Unfortunately, this theorem is not provable in CIC without additional axioms. None of the definitional equality rules force function equality to be%\index{extensionality of function equality}% _extensional_. That is, the fact that two functions return equal results on equal inputs does not imply that the functions are equal. We _can_ assert function extensionality as an axiom, and indeed the standard library already contains that axiom. *)
Require Import FunctionalExtensionality.
About functional_extensionality.
(** %\vspace{-.15in}%[[
functional_extensionality :
forall (A B : Type) (f g : A -> B), (forall x : A, f x = g x) -> f = g
]]
*)
(** This axiom has been verified metatheoretically to be consistent with CIC and the two equality axioms we considered previously. With it, the proof of [two_funs] is trivial. *)
Theorem two_funs : (fun n => n) = (fun n => n + 0).
(* begin thide *)
apply functional_extensionality; crush.
Qed.
(* end thide *)
(** The same axiom can help us prove equality of types, where we need to "reason under quantifiers." *)
Theorem forall_eq : (forall x : nat, match x with
| O => True
| S _ => True
end)
= (forall _ : nat, True).
(** There are no immediate opportunities to apply [functional_extensionality], but we can use %\index{tactics!change}%[change] to fix that problem. *)
(* begin thide *)
change ((forall x : nat, (fun x => match x with
| 0 => True
| S _ => True
end) x) = (nat -> True)).
rewrite (functional_extensionality (fun x => match x with
| 0 => True
| S _ => True
end) (fun _ => True)).
(** [[
2 subgoals
============================
(nat -> True) = (nat -> True)
subgoal 2 is:
forall x : nat, match x with
| 0 => True
| S _ => True
end = True
]]
*)
reflexivity.
destruct x; constructor.
Qed.
(* end thide *)
(** Unlike in the case of [eq_rect_eq], we have no way of deriving this axiom of%\index{functional extensionality}% _functional extensionality_ for types with decidable equality. To allow equality reasoning without axioms, it may be worth rewriting a development to replace functions with alternate representations, such as finite map types for which extensionality is derivable in CIC. *)
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
Debug Logic State Analyzer
Addr
0x000 : Control/Status
0x004 : Live Input Data
0x008 :
(...) : [Sample data, one per 'lsa_clk' with all 32-bits of input data]
0xFFF :
Control -
[0] Arm Trigger
[1] Force Trigger (Arm must also be set)
[2] Sample Done
[7-3] RESERVED
[15-8] Mode (to debug target to select data/trigger settings)
*/
module rcn_debug_lsa
(
input rcn_clk,
input rcn_rst,
input [68:0] rcn_in,
output [68:0] rcn_out,
output reg [7:0] lsa_mode,
input lsa_clk,
input lsa_trigger,
input [31:0] lsa_data
);
parameter ADDR_BASE = 1; // 4kB window
parameter INIT_ARMED = 1;
parameter INIT_FORCED = 0;
parameter INIT_MODE = 8'd0;
wire rcn_cs;
wire rcn_wr;
wire [23:0] rcn_addr;
wire [31:0] rcn_wdata;
reg [31:0] rcn_rdata;
rcn_slave #(.ADDR_BASE(ADDR_BASE), .ADDR_MASK(24'hFFF000)) rcn_slave
(
.rst(rcn_rst),
.clk(rcn_clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(rcn_cs),
.wr(rcn_wr),
.mask(),
.addr(rcn_addr),
.wdata(rcn_wdata),
.rdata(rcn_rdata)
);
//
// Clock domain crossing
//
reg [1:0] sync_av;
reg [1:0] sync_lsa;
reg [1:0] sync_lsa_av;
reg ctrl_arm;
reg rcn_arm;
reg lsa_arm;
reg ctrl_force;
reg rcn_force;
reg lsa_force;
reg [7:0] ctrl_mode;
reg [7:0] rcn_mode;
// lsa_mode in port list
reg sample_done;
reg rcn_done;
reg lsa_done;
wire [31:0] sample_live = lsa_data;
reg [31:0] rcn_live;
reg [31:0] lsa_live;
always @ (posedge rcn_clk or posedge rcn_rst)
if (rcn_rst)
begin
sync_lsa_av <= 2'd0;
sync_av <= 2'd0;
end
else
begin
sync_lsa_av <= sync_lsa;
sync_av <= (sync_lsa_av == sync_av) ? sync_av + 2'd1 : sync_av;
end
always @ (posedge lsa_clk)
sync_lsa <= sync_av;
always @ (posedge rcn_clk)
if (sync_av == 2'b01)
{rcn_live, rcn_done, rcn_mode, rcn_force, rcn_arm} <=
{lsa_live, lsa_done, ctrl_mode, ctrl_force, ctrl_arm};
always @ (posedge lsa_clk)
if (sync_lsa == 2'b10)
{lsa_live, lsa_done, lsa_mode, lsa_force, lsa_arm} <=
{sample_live, sample_done, rcn_mode, rcn_force, rcn_arm};
//
// Sample state machine
//
reg [9:0] sample_waddr;
reg [31:0] sample_data[1023:0];
always @ (posedge lsa_clk)
sample_done <= lsa_arm && (sample_waddr == 10'd0);
always @ (posedge lsa_clk)
if (!lsa_arm)
sample_waddr <= 10'd1;
else if (sample_waddr == 10'd1)
sample_waddr <= (lsa_force || lsa_trigger) ? 10'd2 : 10'd1;
else if (sample_waddr != 10'd0)
sample_waddr <= sample_waddr + 10'd1;
always @ (posedge lsa_clk)
if (lsa_arm)
sample_data[sample_waddr] <= lsa_data;
//
// Control register
//
reg init_cycle;
always @ (posedge rcn_clk or posedge rcn_rst)
if (rcn_rst)
begin
ctrl_arm <= 1'b0;
ctrl_force <= 1'b0;
ctrl_mode <= 8'd0;
init_cycle <= 1'b0;
end
else if (!init_cycle)
begin
ctrl_arm <= (INIT_ARMED != 0);
ctrl_force <= (INIT_FORCED != 0);
ctrl_mode <= INIT_MODE;
init_cycle <= 1'b1;
end
else if (rcn_cs && rcn_wr && (rcn_addr[11:2] == 10'd0))
begin
ctrl_arm <= rcn_wdata[0];
ctrl_force <= rcn_wdata[1];
ctrl_mode <= rcn_wdata[15:8];
end
always @ (posedge rcn_clk)
if (rcn_addr[11:2] == 10'd0)
rcn_rdata <= {16'd0, ctrl_mode, 5'd0, rcn_done, ctrl_force, ctrl_arm};
else if (rcn_addr[11:2] == 10'd1)
rcn_rdata <= rcn_live;
else
rcn_rdata <= sample_data[rcn_addr[11:2]];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_V |
//IEEE Floating Point Divider (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
//
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
`timescale 1ns / 1ps
module ip_minimal #(
parameter MY_MAC = 48'h00_AA_BB_CC_DD_EE,
parameter MY_IP = {8'd10, 8'd5, 8'd5, 8'd5},
parameter DEST_MAC = 48'h30_85_A9_13_05_32, // TODO: Implement ARP request
parameter DEST_IP = {8'd10, 8'd5, 8'd5, 8'd1}
) (
// Ethernet MAC
input wire eth_tx_clk,
output reg [ 7: 0] eth_tx_data,
output reg eth_tx_data_en,
input wire eth_tx_ack,
input wire eth_rx_clk,
input wire [ 7: 0] eth_rx_data,
input wire eth_rx_data_valid,
input wire eth_rx_frame_good,
input wire eth_rx_frame_bad,
// UDP
output reg [ 7: 0] udp_rx,
output reg udp_rx_dv,
input wire [ 7: 0] udp_tx,
input wire [15: 0] udp_tx_pending_data,
output reg udp_tx_rden
);
initial begin
eth_tx_data <= 8'h00;
eth_tx_data_en <= 0;
udp_rx <= 8'h00;
udp_rx_dv <= 0;
udp_tx_rden <= 0;
end
reg [47:0] my_mac_addr = MY_MAC;
reg [31:0] my_ip_addr = MY_IP;
reg [47:0] dest_mac_addr;
reg [31:0] dest_ip_addr;
// ----------------- Rx
`define RX_ST_PKT_BEGIN 8'b00000001
`define RX_ST_PKT_DROP 8'b00000010
`define RX_ST_PKT_GOOD_OR_BAD 8'b00000100
`define RX_ST_PKT_MYADDR 8'b00001000
`define RX_ST_PKT_TYPE_ARP 8'b00010000
`define RX_ST_PKT_TYPE_IP 8'b00100000
`define RX_ST_PKT_IP_UDP 8'b01000000
`define RX_ST_PKT_IP_UDP_PAYLOAD 8'b10000000
reg [7:0] rx_state = `RX_ST_PKT_BEGIN;
reg [15:0] rx_pos = 0;
reg [47:0] rx_mac;
reg [7:0] eth_rx_data_r=0;
wire [15:0] eth_rx_data_word = {eth_rx_data_r, eth_rx_data};
always @(posedge eth_rx_clk) if (eth_rx_data_valid) begin
//rx_buf[rx_pos] <= eth_rx_data;
eth_rx_data_r <= eth_rx_data;
case (rx_pos)
0, 6 : rx_mac[47:40] <= eth_rx_data;
1, 7 : rx_mac[39:32] <= eth_rx_data;
2, 8 : rx_mac[31:24] <= eth_rx_data;
3, 9 : rx_mac[23:16] <= eth_rx_data;
4, 10 : rx_mac[15: 8] <= eth_rx_data;
5, 11 : rx_mac[ 7: 0] <= eth_rx_data;
endcase
rx_pos <= rx_pos+1;
end else rx_pos <= 0;
`define SEND_PKT_NONE 0
`define SEND_PKT_ARP_REPLY 1
`define SEND_PKT_UDP 2
reg [7:0] rx_send_event = 0;
reg reply_req=0;
reg reply_ack=0;
reg [15:0] rx_udp_len;
reg [47:0] arp_reply_mac;
reg [31:0] arp_reply_ip;
reg [4+15:0] rx_ip_crc;
always @(posedge eth_rx_clk/* or negedge eth_rx_data_valid*/)
/*if (eth_rx_data_valid == 0 && rx_state !=`RX_ST_PKT_GOOD_OR_BAD)
rx_state <= `RX_ST_PKT_BEGIN;
else */case (rx_state)
`RX_ST_PKT_BEGIN:
if (rx_pos == 6)
if (&rx_mac || rx_mac == my_mac_addr) rx_state <= `RX_ST_PKT_MYADDR;
else rx_state <= `RX_ST_PKT_DROP;
`RX_ST_PKT_DROP:
if (!eth_rx_data_valid) rx_state <= `RX_ST_PKT_BEGIN;
`RX_ST_PKT_MYADDR:
if (rx_pos == 13) case (eth_rx_data_word)
16'h0806: rx_state <= `RX_ST_PKT_TYPE_ARP;
16'h0800: begin
rx_state <= `RX_ST_PKT_TYPE_IP;
rx_ip_crc <= 0;
end
endcase
`RX_ST_PKT_TYPE_ARP:
case (rx_pos)
15: if (eth_rx_data_word != 16'h0001) rx_state <= `RX_ST_PKT_DROP; // ARP type Ethernet
17: if (eth_rx_data_word != 16'h0800) rx_state <= `RX_ST_PKT_DROP; // Protocol IP
19: if (eth_rx_data_word != 16'h0604) rx_state <= `RX_ST_PKT_DROP; // hw and ip lenght
21: if (eth_rx_data_word != 16'h0001) rx_state <= `RX_ST_PKT_DROP; // Opcode request
22: arp_reply_mac[47:40] <= eth_rx_data;
23: arp_reply_mac[39:32] <= eth_rx_data;
24: arp_reply_mac[31:24] <= eth_rx_data;
25: arp_reply_mac[23:16] <= eth_rx_data;
26: arp_reply_mac[15: 8] <= eth_rx_data;
27: arp_reply_mac[ 7: 0] <= eth_rx_data;
28: arp_reply_ip[31:24] <= eth_rx_data;
29: arp_reply_ip[23:16] <= eth_rx_data;
30: arp_reply_ip[15: 8] <= eth_rx_data;
31: arp_reply_ip[ 7: 0] <= eth_rx_data;
41: begin
rx_send_event <= `SEND_PKT_ARP_REPLY;
rx_state <= `RX_ST_PKT_GOOD_OR_BAD;
end
endcase
`RX_ST_PKT_TYPE_IP: begin
if (rx_pos & 1'b1) rx_ip_crc<=rx_ip_crc+eth_rx_data_word;
casex (rx_pos)
14: if (eth_rx_data != 8'h4_5) rx_state <= `RX_ST_PKT_DROP; // IPv4 header len 20 bytes
//16:if (eth_rx_data_word// != 8'h45) rx_state <= `RX_ST_PKT_DROP; // Total lenght
//18: eth_rx_data_word id
//19: 0x02 - dont fragment
//21: fragment offs
//22: ttl
23: if (eth_rx_data != 8'h11) rx_state <= `RX_ST_PKT_DROP; // UDP
//25: //checksum
//26..29 src ip
30: if (eth_rx_data != my_ip_addr[31:24]) rx_state <= `RX_ST_PKT_DROP;
31: if (eth_rx_data != my_ip_addr[23:16]) rx_state <= `RX_ST_PKT_DROP;
32: if (eth_rx_data != my_ip_addr[15: 8]) rx_state <= `RX_ST_PKT_DROP;
33: begin
if (((rx_ip_crc[15+4:16] + rx_ip_crc[15:0] + eth_rx_data_word) != 16'hFFFF) && (eth_rx_data != my_ip_addr[ 7: 0])) rx_state <= `RX_ST_PKT_DROP;
else rx_state <= `RX_ST_PKT_IP_UDP;
end
endcase
end
`RX_ST_PKT_IP_UDP: begin
case (rx_pos)
//34 35 src port
//36 37 dst port
39: rx_udp_len <= eth_rx_data_word - 8;
//40 41 crc
41: begin
// TODO: Check CRC
rx_state <= rx_udp_len ? `RX_ST_PKT_IP_UDP_PAYLOAD : `RX_ST_PKT_GOOD_OR_BAD;
end
endcase
rx_send_event <= `SEND_PKT_NONE;
end
`RX_ST_PKT_IP_UDP_PAYLOAD:
if (rx_udp_len != 1 && eth_rx_data_valid) begin
rx_udp_len <= rx_udp_len - 1;
end else
rx_state<= `RX_ST_PKT_GOOD_OR_BAD;
`RX_ST_PKT_GOOD_OR_BAD:
if (eth_rx_frame_good || eth_rx_frame_bad) begin
rx_state<= `RX_ST_PKT_BEGIN;
reply_req <= reply_req ^ (eth_rx_frame_good && |rx_send_event);
end
endcase
always @(posedge eth_rx_clk)
if (rx_state == `RX_ST_PKT_IP_UDP_PAYLOAD) begin
udp_rx_dv<=1;
udp_rx<=eth_rx_data;
end else udp_rx_dv<=0;
// ----------------- Tx
`define TX_ST_WAIT 8'b00000001
`define TX_ST_HEADER 8'b00000010
`define TX_ST_HEADER_TAIL 8'b00001000
`define TX_ST_END 8'b00010000
`define TX_ST_END_WAIT 8'b00100000
reg [10:0] eth_tx_state = `TX_ST_WAIT;
reg [15:0] tx_pos;
reg [15:0] tx_len = 0;
reg eth_tx_start=0;
reg [7:0] tx_send_event=0;
reg [7:0] eth_tx_data_payload;
reg [15:0] udp_payload_size;
`define HEADER_MAC 14
`define HEADER_IP 20
`define HEADER_UDP 8
wire [15:0] udp_payload_size_udp = udp_payload_size+`HEADER_UDP;
wire [15:0] udp_payload_size_ip = udp_payload_size_udp+`HEADER_IP;
reg [23:0] tx_ip_check; //FIXME
always @(posedge eth_tx_clk)
begin
case (eth_tx_state)
`TX_ST_WAIT: begin
if (reply_ack != reply_req) begin
reply_ack <= reply_req;
tx_send_event = rx_send_event;
end else
if (udp_tx_pending_data)
tx_send_event = `SEND_PKT_UDP;
if (tx_send_event) begin
case (tx_send_event)
`SEND_PKT_ARP_REPLY: begin dest_mac_addr <= arp_reply_mac; tx_len<=42; end
`SEND_PKT_UDP: begin dest_mac_addr <= DEST_MAC; dest_ip_addr <= DEST_IP; tx_len<=udp_tx_pending_data+`HEADER_MAC+`HEADER_IP+`HEADER_UDP; udp_payload_size<=udp_tx_pending_data; end
endcase
eth_tx_state <= `TX_ST_HEADER;
tx_pos<=1;
end
end
`TX_ST_HEADER: begin
eth_tx_data_en<=1;
if (eth_tx_ack) begin
eth_tx_state <= `TX_ST_HEADER_TAIL;
tx_pos<=tx_pos+1;
eth_tx_data<=dest_mac_addr[39:32];
end else eth_tx_data<=dest_mac_addr[47:40];
end
`TX_ST_HEADER_TAIL: begin
tx_pos<=tx_pos+1;
eth_tx_data<=eth_tx_data_payload;
case (tx_pos)
2:eth_tx_data <=dest_mac_addr[31:24];
3:eth_tx_data <=dest_mac_addr[23:16];
4:eth_tx_data <=dest_mac_addr[15: 8];
5:eth_tx_data <=dest_mac_addr[ 7: 0];
6: eth_tx_data<=my_mac_addr[47:40];
7: eth_tx_data<=my_mac_addr[39:32];
8: eth_tx_data<=my_mac_addr[31:24];
9: eth_tx_data<=my_mac_addr[23:16];
10: eth_tx_data<=my_mac_addr[15: 8];
11: eth_tx_data<=my_mac_addr[ 7: 0];
default: eth_tx_data<=eth_tx_data_payload;
endcase
if (tx_send_event == `SEND_PKT_UDP) begin
case (tx_pos)
20: tx_ip_check <= 16'h4500 + udp_payload_size_ip + 16'hBABA + 16'h0511;
21: tx_ip_check <= tx_ip_check + my_ip_addr[31:16]+my_ip_addr[15:0]+dest_ip_addr[31:16]+dest_ip_addr[15:0];
22: tx_ip_check <= tx_ip_check[15:0]+tx_ip_check[23:16];
23: tx_ip_check <= ~tx_ip_check[15:0];
40: udp_tx_rden<=1'b1;
default: if (tx_pos+1 >= tx_len-1) udp_tx_rden<=1'b0;
endcase
end
if (tx_pos+1 >= tx_len) eth_tx_state <= `TX_ST_END;
end
`TX_ST_END: begin
eth_tx_data_en<=0;
eth_tx_state <= `TX_ST_END_WAIT;
tx_send_event = `SEND_PKT_NONE;
end
`TX_ST_END_WAIT: eth_tx_state <= `TX_ST_WAIT;
endcase
end
always @(tx_pos)
if (tx_send_event == `SEND_PKT_ARP_REPLY) case (tx_pos)
12: eth_tx_data_payload=8'h08; // ARP
13: eth_tx_data_payload=8'h06;
14: eth_tx_data_payload=8'h00; // ARP type ethernet
15: eth_tx_data_payload=8'h01;
16: eth_tx_data_payload=8'h08; // Proto type: IP
17: eth_tx_data_payload=8'h00;
18: eth_tx_data_payload=8'h06; // hw size
19: eth_tx_data_payload=8'h04; // proto size
20: eth_tx_data_payload=8'h00; // opcode 02 - reply
21: eth_tx_data_payload=8'h02; //
22: eth_tx_data_payload=my_mac_addr[47:40]; //sender mac from
23: eth_tx_data_payload=my_mac_addr[39:32];
24: eth_tx_data_payload=my_mac_addr[31:24];
25: eth_tx_data_payload=my_mac_addr[23:16];
26: eth_tx_data_payload=my_mac_addr[15: 8];
27: eth_tx_data_payload=my_mac_addr[ 7: 0];
28: eth_tx_data_payload=my_ip_addr[31:24]; //sender ip from
29: eth_tx_data_payload=my_ip_addr[23:16];
30: eth_tx_data_payload=my_ip_addr[15: 8];
31: eth_tx_data_payload=my_ip_addr[ 7: 0];
32: eth_tx_data_payload=arp_reply_mac[47:40]; //target mac (send to)
33: eth_tx_data_payload=arp_reply_mac[39:32];
34: eth_tx_data_payload=arp_reply_mac[31:24];
35: eth_tx_data_payload=arp_reply_mac[23:16];
36: eth_tx_data_payload=arp_reply_mac[15: 8];
37: eth_tx_data_payload=arp_reply_mac[ 7: 0];
38: eth_tx_data_payload=arp_reply_ip[31:24]; //target ip (send to)
39: eth_tx_data_payload=arp_reply_ip[23:16];
40: eth_tx_data_payload=arp_reply_ip[15: 8];
41: eth_tx_data_payload=arp_reply_ip[ 7: 0];
endcase
else
if (tx_send_event == `SEND_PKT_UDP) case (tx_pos)
12: eth_tx_data_payload=8'h08; // IP
13: eth_tx_data_payload=8'h00;
14: eth_tx_data_payload=8'h45; // IPv4 header len 20 bytes
15: eth_tx_data_payload=8'h00; // Fields
16: eth_tx_data_payload=udp_payload_size_ip[15: 8]; // Lenght
17: eth_tx_data_payload=udp_payload_size_ip[ 7: 0];
18: eth_tx_data_payload=8'hBA; // ID
19: eth_tx_data_payload=8'hBA;
20: eth_tx_data_payload=8'h00; // Fragment offset
21: eth_tx_data_payload=8'h00;
22: eth_tx_data_payload=8'h05; // TTL
23: eth_tx_data_payload=8'h11; // Payload type; UDP
24: eth_tx_data_payload=tx_ip_check[15: 8]; // Check sum
25: eth_tx_data_payload=tx_ip_check[ 7: 0];
26: eth_tx_data_payload=my_ip_addr[31:24]; //Source IP
27: eth_tx_data_payload=my_ip_addr[23:16];
28: eth_tx_data_payload=my_ip_addr[15: 8];
29: eth_tx_data_payload=my_ip_addr[ 7: 0];
30: eth_tx_data_payload=dest_ip_addr[31:24]; //Destination IP
31: eth_tx_data_payload=dest_ip_addr[23:16];
32: eth_tx_data_payload=dest_ip_addr[15: 8];
33: eth_tx_data_payload=dest_ip_addr[ 7: 0];
//UDP
34: eth_tx_data_payload=8'h11; // Source port
35: eth_tx_data_payload=8'h22;
36: eth_tx_data_payload=8'h12; // Destination port
37: eth_tx_data_payload=8'h34;
38: eth_tx_data_payload=udp_payload_size_udp[15: 8]; // Lenght
39: eth_tx_data_payload=udp_payload_size_udp[ 7: 0];
40: eth_tx_data_payload=8'h00; //Check sum UDP
41: eth_tx_data_payload=8'h00;
default: eth_tx_data_payload=udp_tx;
endcase
else eth_tx_data_payload=8'hZZ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O32AI_BLACKBOX_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A32OI_BEHAVIORAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B1 nand0_out ;
wire B1 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
// File : core_example_0.v
// Creation date : 28.11.2017
// Creation time : 16:31:16
// Description : Test arrangement for the example CPU with data memory, instuction memory, clock source, and SPI slave.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1184 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:cpu.subsystem:core_example:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.subsystem/core_example/1.0/core_example.1.0.xml
//-----------------------------------------------------------------------------
module core_example_0 #(
parameter ADDR_WIDTH = 10, // Width of the addresses.
parameter DATA_WIDTH = 16, // Width for data in registers and instructions.
parameter INSTRUCTION_ADDRESS_WIDTH = 8, // Width of an instruction address.
parameter INSTRUCTION_WIDTH = 28, // Total width of an instruction
parameter OP_CODE_WIDTH = 4, // Bits reserved for operation identifiers.
parameter PERIPHERAL_BASE = 256, // The first address for peripherals.
parameter REGISTER_COUNT = 8, // How many registers are supported in the core.
parameter REGISTER_ID_WIDTH = 3, // Bits reserved for identification a single register.
parameter SUPPORTED_MEMORY = 1024 // How much the system supports memory in total.
) (
// Interface: instructions
input [27:0] instruction_feed,
output [7:0] iaddr_o,
// Interface: local_data
input [15:0] local_read_data,
output [9:0] local_address_o,
output [15:0] local_write_data,
output local_write_o,
// Interface: peripheral_access
input [15:0] mem_data_i,
input mem_slave_rdy,
output [9:0] mem_address_o,
output [15:0] mem_data_o,
output mem_master_rdy,
output mem_we_o,
// These ports are not in any interface
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// memory_controller_cpu_system_to_alu_cpu_system wires:
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemaddress;
wire memory_controller_cpu_system_to_alu_cpu_systemalu_active;
wire [2:0] memory_controller_cpu_system_to_alu_cpu_systemalu_operation;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemalu_result;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemalu_status;
wire [2:0] memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1;
wire [2:0] memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemload_value;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_active;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_rdy;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_we;
wire memory_controller_cpu_system_to_alu_cpu_systemregister_active;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_input;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_output_1;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_output_2;
// clock_cpu_clk_source_to_register_bank_cpu_clk_sink wires:
wire clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
wire clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
// memory_controller_peripheral_access_to_peripheral_access wires:
wire [9:0] memory_controller_peripheral_access_to_peripheral_accessaddress;
wire [15:0] memory_controller_peripheral_access_to_peripheral_accessdata_ms;
wire [15:0] memory_controller_peripheral_access_to_peripheral_accessdata_sm;
wire memory_controller_peripheral_access_to_peripheral_accessmaster_rdy;
wire memory_controller_peripheral_access_to_peripheral_accessslave_rdy;
wire memory_controller_peripheral_access_to_peripheral_accesswe;
// instruction_decoder_instruction_feed_to_instructions wires:
wire [7:0] instruction_decoder_instruction_feed_to_instructionsaddress;
wire [27:0] instruction_decoder_instruction_feed_to_instructionsread_data;
// memory_controller_local_data_to_local_data wires:
wire [9:0] memory_controller_local_data_to_local_dataaddress;
wire [15:0] memory_controller_local_data_to_local_dataread_data;
wire memory_controller_local_data_to_local_datawrite;
wire [15:0] memory_controller_local_data_to_local_datawrite_data;
// Ad-hoc wires:
wire clock_clk_i_to_clk_i;
wire clock_rst_i_to_rst_i;
// alu port wires:
wire [2:0] alu_alu_op_i;
wire [15:0] alu_alu_result_o;
wire [15:0] alu_alu_status_o;
wire [15:0] alu_register_value_i1;
wire [15:0] alu_register_value_i2;
// clock port wires:
wire clock_clk_i;
wire clock_clk_o;
wire clock_rst_i;
wire clock_rst_o;
// instruction_decoder port wires:
wire instruction_decoder_alu_active_o;
wire [2:0] instruction_decoder_alu_op_o;
wire [15:0] instruction_decoder_alu_status_i;
wire [2:0] instruction_decoder_choose_reg1_o;
wire [2:0] instruction_decoder_choose_reg2_o;
wire instruction_decoder_clk_i;
wire [7:0] instruction_decoder_iaddr_o;
wire [27:0] instruction_decoder_instruction_feed;
wire [15:0] instruction_decoder_load_value_i;
wire instruction_decoder_mem_active_o;
wire instruction_decoder_mem_rdy_i;
wire instruction_decoder_register_active_o;
wire [15:0] instruction_decoder_register_value_o;
wire instruction_decoder_rst_i;
wire instruction_decoder_we_o;
// memory_controller port wires:
wire memory_controller_clk_i;
wire [9:0] memory_controller_local_address_o;
wire [15:0] memory_controller_local_read_data;
wire [15:0] memory_controller_local_write_data;
wire memory_controller_local_write_o;
wire [9:0] memory_controller_periph_address_o;
wire [15:0] memory_controller_periph_data_i;
wire [15:0] memory_controller_periph_data_o;
wire memory_controller_periph_master_rdy;
wire memory_controller_periph_slave_rdy;
wire memory_controller_periph_we_o;
wire memory_controller_rst_i;
wire memory_controller_sys_active_i;
wire [9:0] memory_controller_sys_address_i;
wire [15:0] memory_controller_sys_data_i;
wire [15:0] memory_controller_sys_data_o;
wire memory_controller_sys_rdy_o;
wire memory_controller_sys_read_rdy_o;
wire memory_controller_sys_we_i;
// register_bank port wires:
wire register_bank_alu_active_i;
wire [15:0] register_bank_alu_result_i;
wire [2:0] register_bank_choose_register_i1;
wire [2:0] register_bank_choose_register_i2;
wire register_bank_clk_i;
wire [15:0] register_bank_load_value_i;
wire register_bank_mem_read_rdy_i;
wire register_bank_register_active_i;
wire [15:0] register_bank_register_input;
wire [15:0] register_bank_register_output1;
wire [15:0] register_bank_register_output2;
wire register_bank_rst_i;
// Assignments for the ports of the encompassing component:
assign clock_clk_i_to_clk_i = clk_i;
assign iaddr_o[7:0] = instruction_decoder_instruction_feed_to_instructionsaddress[7:0];
assign instruction_decoder_instruction_feed_to_instructionsread_data[27:0] = instruction_feed[27:0];
assign local_address_o[9:0] = memory_controller_local_data_to_local_dataaddress[9:0];
assign memory_controller_local_data_to_local_dataread_data[15:0] = local_read_data[15:0];
assign local_write_data[15:0] = memory_controller_local_data_to_local_datawrite_data[15:0];
assign local_write_o = memory_controller_local_data_to_local_datawrite;
assign mem_address_o[9:0] = memory_controller_peripheral_access_to_peripheral_accessaddress[9:0];
assign memory_controller_peripheral_access_to_peripheral_accessdata_sm[15:0] = mem_data_i[15:0];
assign mem_data_o[15:0] = memory_controller_peripheral_access_to_peripheral_accessdata_ms[15:0];
assign mem_master_rdy = memory_controller_peripheral_access_to_peripheral_accessmaster_rdy;
assign memory_controller_peripheral_access_to_peripheral_accessslave_rdy = mem_slave_rdy;
assign mem_we_o = memory_controller_peripheral_access_to_peripheral_accesswe;
assign clock_rst_i_to_rst_i = rst_i;
// alu assignments:
assign alu_alu_op_i[2:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_operation[2:0];
assign memory_controller_cpu_system_to_alu_cpu_systemalu_result[15:0] = alu_alu_result_o[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemalu_status[15:0] = alu_alu_status_o[15:0];
assign alu_register_value_i1[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0];
assign alu_register_value_i2[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_2[15:0];
// clock assignments:
assign clock_clk_i = clock_clk_i_to_clk_i;
assign clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk = clock_clk_o;
assign clock_rst_i = clock_rst_i_to_rst_i;
assign clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst = clock_rst_o;
// instruction_decoder assignments:
assign memory_controller_cpu_system_to_alu_cpu_systemalu_active = instruction_decoder_alu_active_o;
assign memory_controller_cpu_system_to_alu_cpu_systemalu_operation[2:0] = instruction_decoder_alu_op_o[2:0];
assign instruction_decoder_alu_status_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_status[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1[2:0] = instruction_decoder_choose_reg1_o[2:0];
assign memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2[2:0] = instruction_decoder_choose_reg2_o[2:0];
assign instruction_decoder_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign instruction_decoder_instruction_feed_to_instructionsaddress[7:0] = instruction_decoder_iaddr_o[7:0];
assign instruction_decoder_instruction_feed[27:0] = instruction_decoder_instruction_feed_to_instructionsread_data[27:0];
assign instruction_decoder_load_value_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemmem_active = instruction_decoder_mem_active_o;
assign instruction_decoder_mem_rdy_i = memory_controller_cpu_system_to_alu_cpu_systemmem_rdy;
assign memory_controller_cpu_system_to_alu_cpu_systemregister_active = instruction_decoder_register_active_o;
assign memory_controller_cpu_system_to_alu_cpu_systemregister_input[15:0] = instruction_decoder_register_value_o[15:0];
assign instruction_decoder_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_we = instruction_decoder_we_o;
// memory_controller assignments:
assign memory_controller_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign memory_controller_local_data_to_local_dataaddress[9:0] = memory_controller_local_address_o[9:0];
assign memory_controller_local_read_data[15:0] = memory_controller_local_data_to_local_dataread_data[15:0];
assign memory_controller_local_data_to_local_datawrite_data[15:0] = memory_controller_local_write_data[15:0];
assign memory_controller_local_data_to_local_datawrite = memory_controller_local_write_o;
assign memory_controller_peripheral_access_to_peripheral_accessaddress[9:0] = memory_controller_periph_address_o[9:0];
assign memory_controller_periph_data_i[15:0] = memory_controller_peripheral_access_to_peripheral_accessdata_sm[15:0];
assign memory_controller_peripheral_access_to_peripheral_accessdata_ms[15:0] = memory_controller_periph_data_o[15:0];
assign memory_controller_peripheral_access_to_peripheral_accessmaster_rdy = memory_controller_periph_master_rdy;
assign memory_controller_periph_slave_rdy = memory_controller_peripheral_access_to_peripheral_accessslave_rdy;
assign memory_controller_peripheral_access_to_peripheral_accesswe = memory_controller_periph_we_o;
assign memory_controller_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
assign memory_controller_sys_active_i = memory_controller_cpu_system_to_alu_cpu_systemmem_active;
assign memory_controller_sys_address_i[9:0] = memory_controller_cpu_system_to_alu_cpu_systemaddress[9:0];
assign memory_controller_sys_data_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0] = memory_controller_sys_data_o[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemmem_rdy = memory_controller_sys_rdy_o;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy = memory_controller_sys_read_rdy_o;
assign memory_controller_sys_we_i = memory_controller_cpu_system_to_alu_cpu_systemmem_we;
// register_bank assignments:
assign register_bank_alu_active_i = memory_controller_cpu_system_to_alu_cpu_systemalu_active;
assign register_bank_alu_result_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_result[15:0];
assign register_bank_choose_register_i1[2:0] = memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1[2:0];
assign register_bank_choose_register_i2[2:0] = memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2[2:0];
assign register_bank_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign register_bank_load_value_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0];
assign register_bank_mem_read_rdy_i = memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy;
assign register_bank_register_active_i = memory_controller_cpu_system_to_alu_cpu_systemregister_active;
assign register_bank_register_input[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_input[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0] = register_bank_register_output1[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemaddress[15:0] = register_bank_register_output2[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemregister_output_2[15:0] = register_bank_register_output2[15:0];
assign register_bank_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
// IP-XACT VLNV: tut.fi:cpu.logic:alu:1.0
alu #(
.DATA_WIDTH (16))
alu(
// Interface: cpu_system
.alu_op_i (alu_alu_op_i),
.register_value_i1 (alu_register_value_i1),
.register_value_i2 (alu_register_value_i2),
.alu_result_o (alu_alu_result_o),
.alu_status_o (alu_alu_status_o));
// IP-XACT VLNV: tut.fi:cpu.logic:clock:1.0
clock clock(
// Interface: cpu_clk_source
.clk_o (clock_clk_o),
.rst_o (clock_rst_o),
// These ports are not in any interface
.clk_i (clock_clk_i),
.rst_i (clock_rst_i));
// IP-XACT VLNV: tut.fi:cpu.logic:instruction_decoder:1.0
instruction_decoder #(
.REGISTER_ID_WIDTH (3),
.INSTRUCTION_WIDTH (28),
.DATA_WIDTH (16),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_decoder(
// Interface: cpu_clk_sink
.clk_i (instruction_decoder_clk_i),
.rst_i (instruction_decoder_rst_i),
// Interface: cpu_system
.alu_status_i (instruction_decoder_alu_status_i),
.load_value_i (instruction_decoder_load_value_i),
.mem_rdy_i (instruction_decoder_mem_rdy_i),
.alu_active_o (instruction_decoder_alu_active_o),
.alu_op_o (instruction_decoder_alu_op_o),
.choose_reg1_o (instruction_decoder_choose_reg1_o),
.choose_reg2_o (instruction_decoder_choose_reg2_o),
.mem_active_o (instruction_decoder_mem_active_o),
.register_active_o (instruction_decoder_register_active_o),
.register_value_o (instruction_decoder_register_value_o),
.we_o (instruction_decoder_we_o),
// Interface: instructions
.instruction_feed (instruction_decoder_instruction_feed),
.iaddr_o (instruction_decoder_iaddr_o));
// IP-XACT VLNV: tut.fi:cpu.logic:memory_controller:1.0
memory_controller #(
.DATA_WIDTH (16),
.ADDR_WIDTH (10),
.MEMORY_SIZE (1024),
.PERIPHERAL_BASE (256),
.REGISTER_COUNT (8))
memory_controller(
// Interface: cpu_clk_sink
.clk_i (memory_controller_clk_i),
.rst_i (memory_controller_rst_i),
// Interface: cpu_system
.sys_active_i (memory_controller_sys_active_i),
.sys_address_i (memory_controller_sys_address_i),
.sys_data_i (memory_controller_sys_data_i),
.sys_we_i (memory_controller_sys_we_i),
.sys_data_o (memory_controller_sys_data_o),
.sys_rdy_o (memory_controller_sys_rdy_o),
.sys_read_rdy_o (memory_controller_sys_read_rdy_o),
// Interface: local_data
.local_read_data (memory_controller_local_read_data),
.local_address_o (memory_controller_local_address_o),
.local_write_data (memory_controller_local_write_data),
.local_write_o (memory_controller_local_write_o),
// Interface: peripheral_access
.periph_data_i (memory_controller_periph_data_i),
.periph_slave_rdy (memory_controller_periph_slave_rdy),
.periph_address_o (memory_controller_periph_address_o),
.periph_data_o (memory_controller_periph_data_o),
.periph_master_rdy (memory_controller_periph_master_rdy),
.periph_we_o (memory_controller_periph_we_o));
// IP-XACT VLNV: tut.fi:cpu.logic:register_bank:1.0
register_bank #(
.DATA_WIDTH (16),
.REGISTER_ID_WIDTH (3),
.REGISTER_COUNT (8))
register_bank(
// Interface: cpu_clk_sink
.clk_i (register_bank_clk_i),
.rst_i (register_bank_rst_i),
// Interface: cpu_system
.alu_active_i (register_bank_alu_active_i),
.alu_result_i (register_bank_alu_result_i),
.choose_register_i1 (register_bank_choose_register_i1),
.choose_register_i2 (register_bank_choose_register_i2),
.load_value_i (register_bank_load_value_i),
.mem_read_rdy_i (register_bank_mem_read_rdy_i),
.register_active_i (register_bank_register_active_i),
.register_input (register_bank_register_input),
.register_output1 (register_bank_register_output1),
.register_output2 (register_bank_register_output2));
endmodule
|
//`include "../../elink/hdl/elink_constants.v"
module fifo_async
(/*AUTOARG*/
// Outputs
full, prog_full, dout, empty, valid,
// Inputs
wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104; //FIFO width
parameter DEPTH = 32; //FIFO depth
//##########
//# RESET/CLOCK
//##########
input wr_rst; //write reset
input rd_rst; //read reset
input wr_clk; //write clock
input rd_clk; //read clock
//##########
//# FIFO WRITE
//##########
input wr_en;
input [DW-1:0] din;
output full;
output prog_full;
//###########
//# FIFO READ
//###########
input rd_en;
output [DW-1:0] dout;
output empty;
output valid;
`ifdef TARGET_CLEAN
fifo_async_model fifo_model (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
`elsif TARGET_XILINX
generate
if((DW==104) & (DEPTH==32))
begin
fifo_async_104x32 fifo_async_104x32 (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
endgenerate
`endif // !`elsif TARGET_XILINX
endmodule // fifo_async
// Local Variables:
// verilog-library-directories:("." "../../xilibs/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: firtap.v
//
// Project: DSP Filtering Example Project
//
// Purpose: Implements a single tap within a FIR filter. This particular
// FIR tap design is specifically designed to make it easier
// for the parent module to add (or remove) taps. Hence, by stringing
// N of these components together, an N tap filter can be created.
//
// This fir tap is a component of genericfir.v, the high speed (1-sample
// per clock, adjustable tap) FIR filter.
//
// Be aware, implementing a FIR tap in this manner can be a very expensive
// use of FPGA resources, very quickly necessitating a large FPGA for
// even the smallest (128 tap) filters.
//
// Resource usage may be minimized by minizing the number of taps,
// minimizing the number of bits in each tap, and/or the number of bits
// in the input (and output) samples.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017-2018, Gisselquist Technology, LLC
//
// This file is part of the DSP filtering set of designs.
//
// The DSP filtering designs are free RTL designs: you can redistribute them
// and/or modify any of them under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation, either version 3 of
// the License, or (at your option) any later version.
//
// The DSP filtering designs are distributed in the hope that they will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
// General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with these designs. (It's in the $(ROOT)/doc directory. Run make
// with no target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: LGPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/lgpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module firtap(i_clk, i_reset, i_tap_wr, i_tap, o_tap,
i_ce, i_sample, o_sample,
i_partial_acc, o_acc);
parameter IW=16, TW=IW, OW=IW+TW+8;
parameter [0:0] FIXED_TAPS=0;
parameter [(TW-1):0] INITIAL_VALUE=0;
//
input wire i_clk, i_reset;
//
input wire i_tap_wr;
input wire [(TW-1):0] i_tap;
output wire signed [(TW-1):0] o_tap;
//
input wire i_ce;
input wire signed [(IW-1):0] i_sample;
output wire [(IW-1):0] o_sample;
//
input wire [(OW-1):0] i_partial_acc;
output wire [(OW-1):0] o_acc;
//
reg [(IW-1):0] delayed_sample;
reg signed [(TW+IW-1):0] product;
// Determine the tap we are using
generate
if (FIXED_TAPS != 0)
// If our taps are fixed, the tap is given by the i_tap
// external input. This allows the parent module to be
// able to use readmemh to set all of the taps in a filter
assign o_tap = i_tap;
else begin
// If the taps are adjustable, then use the i_tap_wr signal
// to know when to adjust the tap. In this case, taps are
// strung together through the filter structure--our output
// tap becomes the input tap of the next tap module, and
// i_tap_wr causes all of them to shift forward by one.
reg [(TW-1):0] tap;
initial tap = INITIAL_VALUE;
always @(posedge i_clk)
if (i_tap_wr)
tap <= i_tap;
assign o_tap = tap;
end endgenerate
// Forward the sample on down the line, to be the input sample for the
// next component
initial o_sample = 0;
initial delayed_sample = 0;
always @(posedge i_clk)
if (i_reset)
begin
delayed_sample <= 0;
o_sample <= 0;
end else if (i_ce)
begin
// Note the two sample delay in this forwarding
// structure. This aligns the inputs up so that the
// accumulator structure (below) works.
delayed_sample <= i_sample;
o_sample <= delayed_sample;
end
`ifndef FORMAL
// Multiply the filter tap by the incoming sample
always @(posedge i_clk)
if (i_reset)
product <= 0;
else if (i_ce)
product <= o_tap * i_sample;
`else
wire [(TW+IW-1):0] w_pre_product;
abs_mpy #(.AW(TW), .BW(IW), .OPT_SIGNED(1'b1))
abs_bypass(i_clk, i_reset, o_tap, i_sample, w_pre_product);
initial product = 0;
always @(posedge i_clk)
if (i_reset)
product <= 0;
else if (i_ce)
product <= w_pre_product;
`endif
// Continue summing together the output components of the FIR filter
initial o_acc = 0;
always @(posedge i_clk)
if (i_reset)
o_acc <= 0;
else if (i_ce)
o_acc <= i_partial_acc
+ { {(OW-(TW+IW)){product[(TW+IW-1)]}},
product };
// Make verilator happy
// verilate lint_on UNUSED
wire unused;
assign unused = i_tap_wr;
// verilate lint_off UNUSED
endmodule
////////////////////////////////////////////////////////////////////////////////
//
// Filename: genericfir.v
//
// Project: DSP Filtering Example Project
//
// Purpose: Implement a high speed (1-output per clock), adjustable tap FIR
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017-2018, Gisselquist Technology, LLC
//
// This file is part of the DSP filtering set of designs.
//
// The DSP filtering designs are free RTL designs: you can redistribute them
// and/or modify any of them under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation, either version 3 of
// the License, or (at your option) any later version.
//
// The DSP filtering designs are distributed in the hope that they will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
// General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with these designs. (It's in the $(ROOT)/doc directory. Run make
// with no target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: LGPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/lgpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module genericfir(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
parameter NTAPS=128, IW=12, TW=IW, OW=2*IW+7;
parameter [0:0] FIXED_TAPS=0;
input wire i_clk, i_reset;
//
input wire i_tap_wr; // Ignored if FIXED_TAPS
input wire [(TW-1):0] i_tap; // Ignored if FIXED_TAPS
//
input wire i_ce;
input wire [(IW-1):0] i_sample;
output wire [(OW-1):0] o_result;
wire [(TW-1):0] tap [NTAPS:0];
wire [(TW-1):0] tapout [NTAPS:0];
wire [(IW-1):0] sample [NTAPS:0];
wire [(OW-1):0] result [NTAPS:0];
wire tap_wr;
// The first sample in our sample chain is the sample we are given
assign sample[0] = i_sample;
// Initialize the partial summing accumulator with zero
assign result[0] = 0;
genvar k;
generate
if(FIXED_TAPS)
begin
initial $readmemh("taps.hex", tap);
assign tap_wr = 1'b0;
end else begin
assign tap_wr = i_tap_wr;
assign tap[0] = i_tap;
end
for(k=0; k<NTAPS; k=k+1)
begin: FILTER
firtap #(.FIXED_TAPS(FIXED_TAPS),
.IW(IW), .OW(OW), .TW(TW),
.INITIAL_VALUE(0))
tapk(i_clk, i_reset,
// Tap update circuitry
tap_wr, tap[NTAPS-1-k], tapout[k],
// Sample delay line
i_ce, sample[k], sample[k+1],
// The output accumulator
result[k], result[k+1]);
if (!FIXED_TAPS)
assign tap[NTAPS-1-k] = tapout[k+1];
// Make verilator happy
// verilator lint_off UNUSED
wire [(TW-1):0] unused_tap;
if (FIXED_TAPS)
assign unused_tap = tapout[k];
// verilator lint_on UNUSED
end endgenerate
assign o_result = result[NTAPS];
// Make verilator happy
// verilator lint_off UNUSED
wire [(TW):0] unused;
assign unused = { i_tap_wr, i_tap };
// verilator lint_on UNUSED
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_2_V
`define SKY130_FD_SC_LS__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDLCLKP_1_V
`define SKY130_FD_SC_LP__SDLCLKP_1_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDLCLKP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O2111AI_BEHAVIORAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_BEHAVIORAL_V |
/*
* Copyright (c) 2013 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
`include "defines.v"
module stage3_execute(
/* cpu global */
input clk_i,
input rst_i,
/* to stage 2 */
output stall_o,
/* from stage 4 */
input stall_i,
/* from stage 2 */
input [1:0] control_branch_i,
input control_load_i,
input control_store_i,
input [3:0] aluop_i,
input [31:0] alu_a_i,
input [31:0] alu_b_i,
input [31:0] branch_test_val_i,
input do_wb_i,
input [4:0] wb_reg_i,
/* to stage1 */
output reg take_branch_o,
output [29:0] branch_pc_o,
/* to stage 4 */
output [31:0] alu_o,
output reg control_load_o,
output reg control_store_o,
output reg do_wb_o,
output reg [4:0] wb_reg_o
);
assign stall_o = stall_i;
reg [3:0] aluop;
reg [31:0] alu_a;
reg [31:0] alu_b;
reg [31:0] branch_test_val;
reg [1:0] control_branch;
/*
initial begin
ir <= 0;
nextpc_o <= 0;
end
*/
always @(posedge clk_i)
begin
if (rst_i) begin
aluop <= 0;
alu_a <= 0;
alu_b <= 0;
branch_test_val <= 0;
control_branch <= `CONTROL_BRANCH_COND_NZ;
control_load_o <= 0;
control_store_o <= 0;
do_wb_o <= 0;
wb_reg_o <= 0;
end else if (!stall_i) begin
aluop <= aluop_i;
alu_a <= alu_a_i;
alu_b <= alu_b_i;
branch_test_val <= branch_test_val_i;
control_branch <= control_branch_i;
control_load_o <= control_load_i;
control_store_o <= control_load_i;
do_wb_o <= do_wb_i;
wb_reg_o <= wb_reg_i;
end
end
always @(control_branch or branch_test_val)
begin
case (control_branch)
default: begin
take_branch_o = 0;
end
`CONTROL_BRANCH_COND_NZ: begin
take_branch_o = (branch_test_val != 0);
end
`CONTROL_BRANCH_COND_Z: begin
take_branch_o = (branch_test_val == 0);
end
endcase
end
assign branch_pc_o = alu_o[29:0];
alu alu0(
.op(aluop),
.a(alu_a),
.b(alu_b),
.res(alu_o)
);
endmodule // stage3_execute
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Funnel Shifter
// File : ded_funshf.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_funshf
#(parameter BYTES = 4)
(
input mclock,
`ifdef BYTE16 input [6:0] rad, // fifo read address.
`elsif BYTE8 input [5:0] rad, // fifo read address.
`else input [4:0] rad, `endif // fifo read address.
input [(BYTES<<3)-1:0] bsd0, // data in from fifo_0
input [(BYTES<<3)-1:0] bsd1, // data in from fifo_1
input apat8_4, // Area 8x8 mode.
input apat32_4, // Area 32x32 mode.
output reg [(BYTES<<3)-1:0] bsout, // funnel shifter output.
output [BYTES-1:0] cx_sel // color expand data
);
`ifdef BYTE16 reg [6:0] rad_1, rad_d; // fifo read address.
`elsif BYTE8 reg [5:0] rad_1, rad_d; // fifo read address.
`else reg [4:0] rad_1, rad_d; `endif// fifo read address.
reg [(BYTES<<4)-1:0] bsin; // data in from fifo.
reg [31:0] bpck_dat;
reg [4:0] cx_rad;
wire [1:0] n_a32_rad;
wire [1:0] a32_rad;
wire [3:0] bso_sel;
wire [127:0] bs1;
wire [135:0] bs2;
wire [151:0] bs4;
wire [183:0] bs8;
wire [BYTES-1:0] cx1;
wire [BYTES:0] cx2;
wire [BYTES+2:0] cx4;
wire [BYTES+6:0] cx8;
wire [BYTES+14:0] cx16;
/************************************************************************/
// The RAD value needs to be delayed one clock. This is due to the new Rams
// which has everything delayed one cycle
always @(posedge mclock) begin
rad_1 <= rad;
rad_d <= rad_1;
bsin <= {bsd1,bsd0};
end
/************************************************************************/
/* BYTE ADDRESSING */
/************************************************************************/
assign n_a32_rad = {2{~apat32_4}} & rad_d[4:3];
`ifdef BYTE16
assign bso_sel = {rad_d[6:5],n_a32_rad};
always @*
bsout = bs1;
assign bs1 = bso_sel[0] ? bs2[135:8] : bs2[127:0];
assign bs2 = bso_sel[1] ? bs4[151:16] : bs4[135:0];
assign bs4 = bso_sel[2] ? bs8[183:32] : bs8[151:0];
assign bs8 = bso_sel[3] ? bsin[247:64] : bsin[183:0];
`endif
`ifdef BYTE8
always @*
case ({rad_d[5],n_a32_rad})
3'h0: bsout = bsin[63:0];
3'h1: bsout = bsin[71:8];
3'h2: bsout = bsin[79:16];
3'h3: bsout = bsin[87:24];
3'h4: bsout = bsin[95:32];
3'h5: bsout = bsin[103:40];
3'h6: bsout = bsin[111:48];
3'h7: bsout = bsin[119:56];
endcase
`endif
`ifdef BYTE4
always @*
case (n_a32_rad)
2'h0: bsout = bsin[31:0];
2'h1: bsout = bsin[39:8];
2'h2: bsout = bsin[47:16];
2'h3: bsout = bsin[55:24];
endcase
`endif
/************************************************************************/
/* Packed one bit per pixel mux */
/************************************************************************/
assign a32_rad = {2{apat32_4}} & rad_d[4:3];
// FB: added to increase MC clock speed
always @(posedge mclock) begin
bpck_dat <= (apat8_4) ? {4{bsout[7:0]}} : bsout[31:0];
cx_rad <= {a32_rad, rad_d[2:0]};
end
`ifdef BYTE16
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[16:1] : cx2[15:0];
assign cx2 = cx_rad[1] ? cx4[18:2] : cx4[16:0];
assign cx4 = cx_rad[2] ? cx8[22:4] : cx8[18:0];
assign cx8 = cx_rad[3] ? cx16[30:8] : cx16[22:0];
assign cx16 = cx_rad[4] ? {bpck_dat[14:0],bpck_dat[31:16]} : bpck_dat[30:0];
`endif
`ifdef BYTE8
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[8:1] : cx2[7:0];
assign cx2 = cx_rad[1] ? cx4[10:2] : cx4[8:0];
assign cx4 = cx_rad[2] ? cx8[14:4] : cx8[10:0];
assign cx8 = cx_rad[3] ? cx16[22:8] : cx16[14:0];
assign cx16 = cx_rad[4] ? {bpck_dat[6:0],bpck_dat[31:16]} : bpck_dat[22:0];
`endif
`ifdef BYTE4
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[4:1] : cx2[3:0];
assign cx2 = cx_rad[1] ? cx4[6:2] : cx4[4:0];
assign cx4 = cx_rad[2] ? cx8[10:4] : cx8[6:0];
assign cx8 = cx_rad[3] ? cx16[18:8] : cx16[10:0];
assign cx16 = cx_rad[4] ? {bpck_dat[3:0],bpck_dat[31:16]} : bpck_dat[18:0];
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFRTP_PP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CONB_1_V
`define SKY130_FD_SC_LS__CONB_1_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog wrapper for conb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__conb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__conb_1 (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__conb base (
.HI(HI),
.LO(LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__conb base (
.HI(HI),
.LO(LO)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CONB_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Dec 25 17:16:48 2016
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_small/ball_small_sim_netlist.v
// Design : ball_small
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ball_small,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module ball_small
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [9:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 1.43485 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "ball_small.mem" *)
(* C_INIT_FILE_NAME = "ball_small.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "900" *)
(* C_READ_DEPTH_B = "900" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "900" *)
(* C_WRITE_DEPTH_B = "900" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
ball_small_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module ball_small_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [9:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
ball_small_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module ball_small_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [9:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
ball_small_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module ball_small_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [9:0]addra;
input [11:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9 ;
wire [9:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000013301330133013301330133013301330),
.INIT_01(256'h1330133013301330133013301330133013301330133013300000000000000000),
.INIT_02(256'h3C003C003C003C003C003C003C003C003C000000000013301330133013301330),
.INIT_03(256'h133013301330133013301330133013301330133013301330000000001C001C00),
.INIT_04(256'h00001C0000003C003C003C003C003C003C003C003C003C003C00000013301330),
.INIT_05(256'h0000000013301330133013301330133013301330133013300000000026190000),
.INIT_06(256'h2619261900001C0000003C003C003C003C003C003C003C003C003C003C003C00),
.INIT_07(256'h3C003C003C00000000001330133013301330133013301330133000002E3B2619),
.INIT_08(256'h261926192E3B2E3B00001C001C0000003C003C003C003C003C003C003C003C00),
.INIT_09(256'h3C003C003C003C003C003C000000133013301330133013301330133000002619),
.INIT_0A(256'h261926192E3B261926192619261900001C0000003C003C003C003C003C003C00),
.INIT_0B(256'h3C003C003C003C003C003C003C003C003C000000000013301330133013300000),
.INIT_0C(256'h000026192E3B26192E3B261926192619261900001C001C0000003C003C003C00),
.INIT_0D(256'h3C003C003C003C003C003C003C003C003C003C003C0000000000133013301330),
.INIT_0E(256'h1330000000002E3B26192619261926192E3B26192E3B26191C001C0000003C00),
.INIT_0F(256'h00003C003C003C003C003C003C003C003C003C003C003C003C003C0000001330),
.INIT_10(256'h0000000013300000261926192E3B26192E3B26192619261926192E3B1C001C00),
.INIT_11(256'h00001C001C001C001C0000003C003C003C003C003C003C003C003C003C003C00),
.INIT_12(256'h3C003C003C000000133000002E3B26192E3B26192E3B26192619261926192E3B),
.INIT_13(256'h2E3B000000001C001C001C001C001C003C003C003C003C003C003C003C003C00),
.INIT_14(256'h3C003C003C003C003C0000000000261926192E3B26192619261926192E3B2619),
.INIT_15(256'h26192E3B26191C001C001C001C001C001C001C001C0000003C003C003C003C00),
.INIT_16(256'h3C003C003C003C003C003C003C00000000002E3B2619261926192E3B26192E3B),
.INIT_17(256'h26192E3B26192E3B00001C001C001C003F3F3F3F3F3F1C001C0000003C003C00),
.INIT_18(256'h00003C003C003C003C003C003C003C003C00000000002E3B2619261926192E3B),
.INIT_19(256'h2E3B26192E3B26192619261900001C001C003F3F3F3F00003F3F3F3F1C001C00),
.INIT_1A(256'h1C001C0000003C003C003C003C003C003C003C003C0000000000261926192619),
.INIT_1B(256'h2619261926192E3B26192E3B261900001C001C001C003F3F00003F3F00003F3F),
.INIT_1C(256'h3F3F3F3F1C001C0000003C003C003C003C003C003C003C003C00000000002E3B),
.INIT_1D(256'h00002E3B2619261926192E3B261926192E3B261900001C0000003F3F3F3F0000),
.INIT_1E(256'h3F3F3F3F3F3F1C001C001C0000003C003C003C003C003C003C003C003C000000),
.INIT_1F(256'h3C00000000002619261926192E3B26192E3B26192619261900001C001C001C00),
.INIT_20(256'h1C001C001C00000000001C001C0000003C003C003C003C003C003C003C003C00),
.INIT_21(256'h3C003C003C00000000002E3B2619261926192E3B26192E3B26192E3B26190000),
.INIT_22(256'h2E3B26191C001C001C001C001C001C00000000003C003C003C003C003C003C00),
.INIT_23(256'h3C003C003C003C003C000000000000002E3B26192E3B26192E3B261926192619),
.INIT_24(256'h2E3B261926192E3B261900001C0000001C001C003C003C003C003C003C003C00),
.INIT_25(256'h3C003C003C003C003C003C00000000000000000026192E3B2619261926192619),
.INIT_26(256'h2E3B2619261926192619261926192619000000001C001C003C003C003C003C00),
.INIT_27(256'h3C003C003C003C003C003C003C003C0000001330133000002E3B26192E3B2619),
.INIT_28(256'h2E3B26192E3B261926192619261926192E3B26192619261900001C0000003C00),
.INIT_29(256'h00003C003C003C003C003C003C003C003C000000133013301330000000002619),
.INIT_2A(256'h00002E3B26192619261926192E3B26192E3B2619261926192E3B2E3B00001C00),
.INIT_2B(256'h261900001C0000003C003C003C003C003C003C003C0000001330133013301330),
.INIT_2C(256'h13301330000026192E3B26192E3B261926192619261926192E3B261926192619),
.INIT_2D(256'h26192619261900001C0000003C003C003C003C003C003C000000133013301330),
.INIT_2E(256'h13301330133013301330000000002619261926192E3B26192E3B26192E3B2619),
.INIT_2F(256'h261926192E3B26192E3B26191C001C0000003C003C003C003C00000013301330),
.INIT_30(256'h133013301330133013301330133013300000000026192E3B26192E3B26192619),
.INIT_31(256'h2E3B26192E3B26192619261926192E3B1C001C0000003C003C003C0000001330),
.INIT_32(256'h133013301330133013301330133013301330133013300000000026192E3B2619),
.INIT_33(256'h000026192E3B26192E3B26192619261926192E3B00001C001C00000000000000),
.INIT_34(256'h0000133013301330133013301330133013301330133013301330133000000000),
.INIT_35(256'h133013300000000000002619261926192E3B26192E3B26190000000000000000),
.INIT_36(256'h0000133013301330133013301330133013301330133013301330133013301330),
.INIT_37(256'h1330133013301330133013300000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000001330133013301330),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_1 ,douta[11:6],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9 ,douta[5:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module ball_small_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [9:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
ball_small_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 1.43485 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "ball_small.mem" *)
(* C_INIT_FILE_NAME = "ball_small.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "900" *) (* C_READ_DEPTH_B = "900" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "900" *) (* C_WRITE_DEPTH_B = "900" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module ball_small_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
ball_small_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module ball_small_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [9:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
ball_small_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_1_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_1_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for isobufsrc with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_1 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_1 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFSTP_PP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfstp (
CLK ,
D ,
Q ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
input SET_B;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O21BA_PP_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_PP_BLACKBOX_V
|
// This is written by Zhiyang Ong
//and Andrew Mattheisen
//for EE577b Troy WideWord Processor Project
module regfileww(rd1data, rd2data, wrdata, rd1addr, rd2addr, wraddr,
rd1en, rd2en, wren, wbyteen, clk);
// OUTPUTS
output [0:127] rd1data, rd2data;
// INPUTS
input [0:127] wrdata;
input clk;
input wren;
input rd1en, rd2en;
input [0:4] wraddr, rd1addr, rd2addr;
input [0:15] wbyteen;
reg [0:127] rd1data, rd2data;
reg [0:127] reg_file [0:31];
reg [0:127] result, temp;
// ===============================================================
always @(posedge clk)
begin
if(wren)
begin
temp=reg_file[wraddr];
result[0:7]=(wbyteen[0]==1'b1)? wrdata[0:7]:temp[0:7];
result[8:15]=(wbyteen[1]==1'b1)? wrdata[8:15]:temp[8:15];
result[16:23]=(wbyteen[2]==1'b1)? wrdata[16:23]:temp[16:23];
result[24:31]=(wbyteen[3]==1'b1)? wrdata[24:31]:temp[24:31];
result[32:39]=(wbyteen[4]==1'b1)? wrdata[32:39]:temp[32:39];
result[40:47]=(wbyteen[5]==1'b1)? wrdata[40:47]:temp[40:47];
result[48:55]=(wbyteen[6]==1'b1)? wrdata[48:55]:temp[48:55];
result[56:63]=(wbyteen[7]==1'b1)? wrdata[56:63]:temp[56:63];
result[64:71]=(wbyteen[8]==1'b1)? wrdata[64:71]:temp[64:71];
result[72:79]=(wbyteen[9]==1'b1)? wrdata[72:79]:temp[72:79];
result[80:87]=(wbyteen[10]==1'b1)? wrdata[80:87]:temp[80:87];
result[88:95]=(wbyteen[11]==1'b1)? wrdata[88:95]:temp[88:95];
result[96:103]=(wbyteen[12]==1'b1)? wrdata[96:103]:temp[96:103];
result[104:111]=(wbyteen[13]==1'b1)? wrdata[104:111]:temp[104:111];
result[112:119]=(wbyteen[14]==1'b1)? wrdata[112:119]:temp[112:119];
result[120:127]=(wbyteen[15]==1'b1)? wrdata[120:127]:temp[120:127];
reg_file[wraddr] = result;
end
// before synthesis, change the zs to 0!!!
rd1data=rd1en?reg_file[rd1addr]:128'd0;
rd2data=rd2en?reg_file[rd2addr]:128'd0;
end
endmodule
|
module ArithAlu(
/* verilator lint_off UNUSED */
clk,
opMode,
srca,
srcb,
dst,
sri,
sro
);
input clk;
input[4:0] opMode;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
input[3:0] sri;
output[3:0] sro;
parameter[4:0] UOP_NONE = 5'h00;
parameter[4:0] UOP_ADD = 5'h01;
parameter[4:0] UOP_SUB = 5'h02;
parameter[4:0] UOP_MUL = 5'h03;
parameter[4:0] UOP_AND = 5'h04;
parameter[4:0] UOP_OR = 5'h05;
parameter[4:0] UOP_XOR = 5'h06;
parameter[4:0] UOP_SHL = 5'h07;
parameter[4:0] UOP_SHR = 5'h08;
parameter[4:0] UOP_SAR = 5'h09;
parameter[4:0] UOP_ADDC = 5'h14;
parameter[4:0] UOP_ADDV = 5'h15;
parameter[4:0] UOP_SUBC = 5'h16;
parameter[4:0] UOP_SUBV = 5'h17;
parameter[4:0] UOP_TEST = 5'h18;
parameter[4:0] UOP_CMPEQ = 5'h1B;
parameter[4:0] UOP_CMPGT = 5'h1C;
parameter[4:0] UOP_CMPGE = 5'h1D;
parameter[4:0] UOP_CMPHS = 5'h1E;
parameter[4:0] UOP_CMPHI = 5'h1F;
/* verilator lint_off UNOPTFLAT */
reg[31:0] tDst;
reg[5:0] tShl;
reg[3:0] tSr;
reg tCvo;
assign dst=tDst;
assign sro=tSr;
always @ (opMode) begin
tSr=sri;
case(opMode)
UOP_ADD: begin
tDst = srca+srcb;
end
UOP_SUB: begin
tDst = srca-srcb;
end
UOP_MUL: begin
tDst = srca*srcb;
end
UOP_AND: begin
tDst = srca&srcb;
end
UOP_OR: begin
tDst = srca|srcb;
end
UOP_XOR: begin
tDst = srca^srcb;
end
UOP_SHL: begin
tShl = srcb[5:0];
tDst = srca<<tShl;
end
UOP_SHR: begin
tShl = srcb[5:0];
tDst = srca>>tShl;
end
UOP_SAR: begin
tShl = srcb[5:0];
tDst = srca>>>tShl;
end
UOP_ADDC: begin
if(sri[0])
tDst = srca+srcb+1;
else
tDst = srca+srcb;
tSr[0]=tDst[31]^srca[31];
end
UOP_ADDV: begin
{tCvo, tDst} = {srca[31], srca} + {srcb[31], srcb};
tSr[0]=tDst[31]^tCvo;
end
UOP_SUBC: begin
if(sri[0])
tDst = srca-srcb-1;
else
tDst = srca-srcb;
tSr[0]=tDst[31]^srca[31];
end
UOP_SUBV: begin
{tCvo, tDst} = {srca[31], srca} - {srcb[31], srcb};
tSr[0]=tDst[31]^tCvo;
end
UOP_TEST: begin
tDst = srca&srcb;
tSr[3:2]=sri[3:2];
tSr[0]=(tDst==0);
end
UOP_CMPEQ: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]==srcb[31:0]);
end
UOP_CMPGT: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>srcb[31:0]);
end
UOP_CMPGE: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>=srcb[31:0]);
end
UOP_CMPHS: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>srcb[31:0]);
end
UOP_CMPHI: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>=srcb[31:0]);
end
default: begin
tDst = 32'h0000_0000;
tSr=sri;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__A22OI_PP_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_PP_BLACKBOX_V
|
/***********************************************************************
16 bits WISHBONE timer
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
Implements a 16 bits timer (clock counter) to generate periodic
interrupts. Used by Tone.cpp Arduino API.
Port Write Read
0 Low Divider 0
1 High Divider 0
To Do:
-
Author:
- Salvador E. Tropea, salvador en inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar>
Copyright (c) 2017 Instituto Nacional de Tecnología Industrial
Distributed under the GPL v2 or newer license
------------------------------------------------------------------------------
Design unit: TM16bits(RTL) (Entity and architecture)
File name: tm16b.v
Note: None
Limitations: None known
Errors: None known
Library: lattuino
Dependencies: IEEE.std_logic_1164
IEEE.numeric_std
Target FPGA: iCE40HX4K-TQ144
Language: Verilog
Wishbone: None
Synthesis tools: Lattice iCECube2 2016.02.27810
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
------------------------------------------------------------------------------
Wishbone Datasheet
1 Revision level B.3
2 Type of interface SLAVE
3 Defined signal names RST_I => wb_rst_i
CLK_I => wb_clk_i
ADR_I => wb_adr_i
DAT_I => wb_dat_i
DAT_O => wb_dat_o
WE_I => wb_we_i
ACK_O => wb_ack_o
STB_I => wb_stb_i
4 ERR_I Unsupported
5 RTY_I Unsupported
6 TAGs None
7 Port size 8-bit
8 Port granularity 8-bit
9 Maximum operand size 8-bit
10 Data transfer ordering N/A
11 Data transfer sequencing Undefined
12 Constraints on the CLK_I signal None
***********************************************************************/
module TM16bits
#(
parameter CNT_PRESC=24,
parameter ENA_TMR=1
)
(
// WISHBONE signals
input wb_clk_i, // Clock
input wb_rst_i, // Reset input
input [0:0] wb_adr_i, // Adress bus
output [7:0] wb_dat_o, // DataOut Bus
input [7:0] wb_dat_i, // DataIn Bus
input wb_we_i, // Write Enable
input wb_stb_i, // Strobe
output wb_ack_o, // Acknowledge
// Interface
output reg irq_req_o,
input irq_ack_i
);
localparam integer CNT_BITS=$clog2(CNT_PRESC);
// Timer counter
reg [15:0] cnt_r=0;
// Divider value
reg [15:0] div_r=0;
wire tc; // Terminal count
// Microseconds source
wire ena_cnt;
reg [CNT_BITS-1:0] pre_cnt_r;
// Microseconds time source
always @(posedge wb_clk_i)
begin : tmr_source
if (wb_rst_i)
pre_cnt_r <= 0;
else
begin
pre_cnt_r <= pre_cnt_r+1;
if (pre_cnt_r==CNT_PRESC-1)
pre_cnt_r <= 0;
end
end // tmr_source;
assign ena_cnt=pre_cnt_r==CNT_PRESC-1;
// 16 bits counter
always @(posedge wb_clk_i)
begin : do_count
if (wb_rst_i || tc || (wb_stb_i && wb_we_i))
cnt_r <= 0;
else
if (ena_cnt)
cnt_r <= cnt_r+1;
end // do_count
assign tc=cnt_r==div_r-1 && ena_cnt;
// Interrupt logic
always @(posedge wb_clk_i)
begin : do_flag
if (wb_rst_i)
irq_req_o <= 0;
else if (tc && ENA_TMR)
irq_req_o <= 1;
else if (irq_ack_i)
irq_req_o <= 0;
end // do_flag
////////////////////////////////////////////////////////////////////////////
// WISHBONE read
////////////////////////////////////////////////////////////////////////////
assign wb_dat_o=0;
assign wb_ack_o=wb_stb_i;
////////////////////////////////////////////////////////////////////////////
// WISHBONE write
////////////////////////////////////////////////////////////////////////////
always @(posedge wb_clk_i)
begin : do_write_div
if (wb_rst_i)
div_r <= 0;
else if (wb_stb_i && wb_we_i)
begin
if (wb_adr_i)
div_r[15:8] <= wb_dat_i;
else
div_r[7:0] <= wb_dat_i;
end
end // do_write_div
endmodule // TM16bits
|
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